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C500 Architecture and Instruction Set

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1. 3 4 4 Instruction Set EX RE RE X GE xx 4 1 4 1 Addressing Modes RE e Pac 4 1 4 2 Introduction to the Instruction Set 4 3 4 2 1 Data Transfer Instructions 4 3 4 2 2 Arithmetic Instructions CR Ie CA P aL 4 4 4 2 3 Logic Instructions T TL TIL 4 5 4 2 4 Control Transfer Instructions 4 6 4 3 Instruction Definitions 4 8 4 4 Instruction Set Summary Tables 4 82 4 4 1 Functional Groups of Instructions 4 82 4 4 2 Hexadecimal Ordered Instructions 4 86 User s Manual 1 2000 07 _ C nfineon C500 technologies Fundamental Structure 1 Fundamental Structure 1 1 Introduction The members of the C500 Infineon Technologies microcontroller family are basically fully compatible in architecture and software to the standard 8051 microcontroller family Especially they are functionally upward compatible to the SAB 80C52 80C32 microcontroller While maintaining all architectural and operational characteristics of the SAB 80 52 80 32 the C500 microcontrollers differ in number and complexity of their peripheral units which have been adapted to the specific application areas The goal of this Archi
2. R2 data 9 SUBB A R2 BA CJNE R2 data rel 7 R34data 9B 50 A R3 BB CJNE R3 data rel 7 9 SUBB A R4 BC CJNE R4 data rel Rd data 9 lt A R5 BDH CJNE R5 data rel 7E R 6 data 9E 50 6 BE CJNE R6 data rel 7Fy MOV RH7J4data 9Fy SUBB A R7 BF CJNE R7 data rel User s Manual 4 87 2000 07 e Infineon technologies Table 4 4 C500 Instruction List in Hexadecimal Order Instruction Set Op Mnemonic Op Mnemonic Op Mnemonic Code Code Code PUSH direct EO MOVX A DPTR AJMP E1H AJMP C2 CLR bit E24 A RO C3H CLR E3H A RI1 C4H SWAP E4H CLR A C5H XCH A direct 5 C6H A RO E6H A RO C7H A R1 E74 A QHR1 C8 XCH A RO E8H A RO C9H XCH A R1 E9H MOV A R1 CAH A R2 EA A R2 XCH A R3 EB MOV A R3 CCH XCH A R4 ECH A R4 CDy XCH A R5 ED A R5 A R6 EE A R6 CFy XCH A R7 EF A R7 DO POP direct DPTR A Diy addri1 F1H ACALL Da bit MOVX RO A D3H MOVX RI1 A D4 DA A
3. D5H DJNZ direct rel F5H direct A D64 A RO F6H RO A 07 XCHD A R1 F74 MOV R1 A D8 DJNZ RO rel F84 MOV RO A D9 DJNZ Ri rel F9H MOV R1 A DA DJNZ R2rel R2 A DB DJNZ R3rel FBH MOV R3 A DC DJNZ R 4 rel FC MOV R4 A DDH DJNZ R5 rel FDy R5 A DE DJNZ Re rel FE MOV R6 A DF DJNZ 0 R7 rel FF MOV R7 A User s Manual 4 88 2000 07 Infineon 9085 I0I Business Excellence Business excellence means intelligent approaches and clearly defined processes which are both constantly under review and ultimately lead to good operating results Better operating results and business excellence mean less idleness and wastefulness for all of us more professional success more accurate information a better overview and thereby less frustration and more satisfaction Dr Ulrich Schumacher http www infineon com Published by Infineon Technologies AG
4. lt PC 3 SP lt SP 1 SP PC7 0 SP lt SP 1 SP lt PC15 8 PC addr15 0 Encoding 00010010 addr15 addr8 addrO Bytes Cycles User s Manual 4 44 2000 07 o _ technologies LJMP Function Description Example Operation Encoding Bytes Cycles User s Manual Instruction Set addr16 Long jump LJMP causes an unconditional branch to the indicated address by loading the high order and low order bytes of the PC respectively with the second and third instruction bytes The destination may therefore be anywhere in the full 64K program memory address space No flags are affected The label is assigned to the instruction at program memory location 1234 The instruction LJMP JMPADR at location 0123 will load the program counter with 12344 LJMP PC lt addr15 0 000010010 addr15 addr8 addr7 3 2 4 45 2000 07 o _ nfineon technologies MOV Function Description Example MOV Operation Encoding Bytes Cycles MOV Operation Encoding Bytes Cycles C500 Instruction Set lt dest byte gt lt src byte gt Move byte variable The byte variable indicated by the second operand is copied into the location specified by the first operand The source byte is not affecte
5. 111 1 1rrr Rn direct MOV Rn direct 1010 1rrr 2 2 direct address 4 47 Instruction Set 2000 07 o _ nfineon technologies MOV Operation Encoding Bytes Cycles MOV Operation Encoding Bytes Cycles MOV Operation Encoding Bytes Cycles MOV Operation Encoding Bytes Cycles User s Manual C500 Rn data MOV Rn lt data 0111 1rrr 2 1 direct A MOV direct lt A immediate data 1111 0101 2 1 direct Rn MOV direct lt Rn direct address 1000 1rrr direct direct MOV direct lt direct direct address 1000 0101 Instruction Set 3 2 dir addr Src dir addr dest 4 48 2000 07 e nfineon technologies MOV Operation Encoding Bytes Cycles MOV Operation Encoding Bytes Cycles MOV Operation Encoding Bytes Cycles MOV Ooeration Encoding Bytes Cycles User s Manual C500 direct Ri MOV direct lt Ri 10000111 direct address direct data MOV direct lt data Instruction Set 011110101 direct address immediate data
6. Encoding 1000 0100 Bytes 1 Cycles 4 User s Manual 4 30 2000 07 o _ C nfineon C500 technologies DJNZ Function Description Example User s Manual Instruction Set lt byte gt lt rel addr gt Decrement and jump if not zero DJNZ decrements the location indicated by 1 and branches to the address indicated by the second operand if the resulting value is not zero An original value of 00 will underflow to OFFH No flags are affected The branch destination would be computed by adding the signed relative displacement value in the last instruction byte to the PC after incrementing the PC to the first byte of the following instruction The location decremented may be a register or directly addressed byte Note When this instruction is used to modify an output port the value used as the original port data will be read from the output data latch not the input pins Internal RAM locations 404 50 and 60H contain the values 01 4 70 and 15 4 respectively The instruction sequence DJNZ 40H LABEL_1 DJNZ 50H LABEL 2 DJNZ 60H LABEL 3 will cause a jump to the instruction at label LABEL_2 with the values 00H and 15H the three RAM locations The first jump was not taken because the result was zero This instruction provides a simple way of executing a program loop a given number of times or for adding a moderate time delay from 2 to 512 mach
7. lt PC 2 if 1 then PC lt PC rel 01000000 rel address 4 38 2000 07 o _ technologies JMP Function Description Example Operation Encoding Bytes Cycles User s Manual Instruction Set A DPTR Jump indirect Add the eight bit unsigned contents of the accumulator with the sixteen bit data pointer and load the resulting sum to the program counter This will be the address for subsequent instruction fetches Sixteen bit addition is performed modulo 216 carry out from the low order eight bits propagates through the higher order bits Neither the accumulator nor the data pointer is altered No flags are affected An even number from 0 to 6 is in the accumulator The following sequence of instructions will branch to one of four AJMP instructions in a jump table starting at JMP_TBL MOV DPTR JMP_TBL JMP A DPTR JMP_TBL AJMP LABELO AJMP LABELI AJMP LABEL2 AJMP LABEL3 If the accumulator equals 04 when starting this sequence execution will jump to label LABEL2 Remember that AJMP is a two byte instruction so the jump instructions start at every other address JMP PC A DPTR 01110011 4 39 2000 07 9 Infineon technologies JNB Function Description Example Operation Encoding Bytes Cycles User s Manual C500 bit rel Jump if bit
8. 0100 0010 2 1 direct address 4 60 Instruction Set 2000 07 C nfineon C500 technologies Instruction Set ORL direct data Operation ORL direct lt direct data Encoding 01000011 direct address immediate data Bytes 3 Cycles 2 User s Manual 4 61 2000 07 o _ nfineon technologies ORL Function Description Example ORL Operation Encoding Bytes Cycles ORL Operation Encoding Bytes Cycles User s Manual C500 Instruction Set C lt src bit gt Logical OR for bit variables Set the carry flag if the Boolean value is a logic 1 leave the carry in its current state otherwise slash preceding the operand in the assembly language indicates that the logical complement of the addressed bit is used as the source value but the source bit itself is not affected No other flags are affected Set the carry flag if and only if P1 0 1 ACC 7 1 or OV 0 MOV Load carry with input pin Pl ORL C ACC 7 OR carry with the accumulato ORL C OV OR carry with the inverse of ORL lt bit 0111 0010 bit address C bit ORL C C v bit 1010 0000 bit address r bit 7 OV 2000 07 o _ technologies Function Description Exa
9. A Rn ANL lt A 010111 4 16 2000 07 e nfineon technologies ANL Operation Encoding Bytes Cycles ANL Operation Encoding Bytes Cycles ANL Operation Encoding Bytes Cycles ANL Operation Encoding Bytes Cycles User s Manual C500 A direct ANL A lt A direct 0101 0101 2 1 A QRi ANL lt A Ri direct address 0101 011i data ANL A lt A data 0101 0100 2 1 direct ANL direct lt direct A immediate data 0101 0010 2 1 direct address Instruction Set 2000 07 C nfineon C500 technologies Instruction Set ANL direct data Operation direct lt direct data Encoding 01010011 direct address immediate data Bytes 3 Cycles 2 User s Manual 4 18 2000 07 o _ nfineon technologies ANL Function Description Example ANL Operation Encoding Bytes Cycles ANL Operation Encoding Bytes Cycles User s Manual C500 C lt src bit gt Logical AND for bit variables Instruction Set If the Boolean value of the source bit is a logic 0 then clear the carry flag otherwise leave the
10. o _ C nfineon C500 technologies CPU Architecture Special Function Register PSW Address D0H Reset Value 00 Bit No MSB LSB 7 6 5 4 3 2 1 0 DOW CY AC FO RS1 RSO OV F1 P PSW Bit Function CY Carry Flag Used by arithmetic and conditional branch instruction AC Auxiliary Carry Flag Used by instructions which execute BCD operations FO General Purpose Flag RS1 Register Bank select control bits RSO These bits are used to select one of the four register banks RS1 RSO Function Registerbank 0 at data address 00 074 selected Registerbank 1 at data address 08 OF selected Registerbank 2 at data address 10H 174 selected O Registerbank 3 at data address 18H 1 selected OV Overflow Flag Used by arithmetic instruction F1 General Purpose Flag P Parity Flag Always set cleared by hardware to indicate an odd even number of one bits in the accumulator 2 4 Stack Pointer The stack pointer SP register is 8 bits wide It is incremented before data is stored during PUSH and CALL executions and decremented after data is popped during a POP and RET RETI execution i e it always points to the last valid stack byte While the stack may reside anywhere in the on chip RAM the stack pointer is initialized to 074 after a reset This causes the stack to begin a location 08H above register bank zero The SP can be
11. JNC rel Jump if carry flag is not set JB bit rel Jump if direct bit is set JNB bit rel Jump if direct bit is not set JBC bit rel Jump if direct bit is set and clear bit CJNE A direct rel Compare direct byte to A and jump if not equal CJNE A data rel Compare immediate to A and jump if not equal CJNE Rn data rel Compare immed to reg and jump if not equal CJNE Ri Compare immed to ind and jump if not equal DJNZ Rn rel Decrement register and jump if not zero DJNZ direct rel Decrement direct byte and jump if not zero NOP No operation UI NIAI OJ OW OW DM IO WwW IO MLM MLM PM PO 1 is not a valid instruction User s Manual 4 85 2000 07 e Infineon technologies C500 Instruction Set 4 4 2 Hexadecimal Ordered Instructions Table 4 4 Instruction List in Hexadecimal Order Op Mnemonic Op Mnemonic Op Mnemonic Code Code Code 00 NOP 20 JB bit rel 40H 01 AJMP 11 21 AJMP addri1 41H AJMP addri1 02 22 42 ORL direct A 03 RR A 234 RL A 434 ORL direct data 04 INC A 24 ADD A data 44 ORL A data 05 IMC direct 25H ADD A direct 454 ORL A dir
12. and the program counter is not incremented In any case execution is completed at the end of S6P2 Figure 3 1 a and b show the timing of a 1 byte 1 cycle instruction and for a 2 byte 1 cycle instruction Most C500 instructions are executed in one cycle MUL multiply and DIV divide are the only instructions that take more than two cycles to complete they take four cycles Normally two code bytes are fetched from the program memory during every machine cycle The only exception to this is when MOVX instruction is executed MOVX is one byte 2 cycle instruction that accesses external data memory During a MOVX the two fetches in the second cycle are skipped while the external data memory is being addressed and strobed Figure 3 1 c and d show the timing for a normal 1 byte 2 cycle instruction and for a MOVX instruction User s Manual 3 1 2000 07 C500 technologies CPU Timing 2 2 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 2 P2 ALE Read Read next Opcode Opcode Discard Read next 000000 again 5 a 1 Byte 1 Cycle Instruction e g INC A Read Read 2nd 000000 Byte Read next 2 Byte 1 Cycle Instruction 0 0 ADD Data Read next 000000 again Read Opcode Read next Opcode Discard Y Tel 1 Byte
13. 1 Cycles 1 User s Manual 4 67 2000 07 o _ technologies RLC Function Description Example Operation Encoding Bytes Cycles User s Manual Instruction Set A Rotate accumulator left through carry flag The eight bits in the accumulator and the carry flag are together rotated one bit to the left Bit 7 moves into the carry flag the original state of the carry flag moves into the bit 0 position No other flags are affected The accumulator holds the value 0C5H 110001015 and the carry is zero The instruction RLC A leaves the accumulator holding the value 8AH 100010108 with the carry set RLC An 1 lt n 0 6 lt lt 7 00110011 4 68 2000 07 o _ technologies Instruction Set RR A Function Rotate accumulator right Description The eight bits in the accumulator are rotated one bit to the right Bit 0 is rotated into the bit 7 position No flags are affected Example The accumulator holds the value 0C5 110001015 The instruction RR A leaves the accumulator holding the value 2 11100010g with the carry unaffected Operation RR lt 1 0 6 7 lt 0 Encoding 00000011 Bytes 1 Cycles 1 User s Manual 4 69 2000 07 o _ technologies Instruction Set RRC A Function Rotate accumulator right through carry flag Description Th
14. Description Example Operation Encoding Bytes Cycles User s Manual Instruction Set DPTR data16 Load data pointer with a 16 bit constant The data pointer is loaded with the 16 bit constant indicated The 16 bit constant is loaded into the second and third bytes of the instruction The second byte is the high order byte while the third byte holds the low order byte No flags are affected This is the only instruction which moves 16 bits of data at once The instruction MOV DPTR 1234H will load the value 1234 into the data pointer DPH will hold 12H and DPL will hold 34 lt data15 0 DPH g lt data15 8 O data7 0 10010000 immed data 15 8 immed data 7 0 3 2 4 52 2000 07 o _ technologies Function Description Example MOVC Operation Encoding Bytes Cycles User s Manual Instruction Set A A lt base reg gt Move code byte The MOVC instructions load the accumulator with a code byte or constant from program memory The address of the byte fetched is the sum of the original unsigned eight bit accumulator contents and the contents of a sixteen bit base register which may be either the data pointer or the PC In the latter case the PC is incremented to the address of the following instruction before being added to the accumulator otherwise the base reg
15. Interrupt are polled Vector Address Routine is latched 01859 Figure 2 5 Interrupt Detection Entry Diagram Note that if an interrupt of a higher priority level goes active prior to 55 2 in the machine cycle labeled C3 in Figure 2 5 then in accordance with the above rules it will be vectored to during C5 and 6 without any instruction for the lower priority routine to be executed Thus the processor acknowledges an interrupt request by executing a hardware generated LCALL to the appropriate servicing routine In some cases it also clears the flag that generated the interrupt while in other cases it does not then this has to be done by the user s software User s Manual 2 11 2000 07 o _ C nfineon C500 technologies CPU Architecture The program execution proceeds from that location until the RETI instruction is encountered The RETI instruction informs the processor that the interrupt routine is no longer in progress then pops the two top bytes from the stack and reloads the program counter Execution of the interrupted program continues from the point where it was stopped Note that the instruction is very important because it informs the processor that the program left the current interrupt priority level A simple RET instruction would also have returned execution to the interrupted program but it would have left the interrupt control system thinking an interrupt was still in progress In this cas
16. The C500 uses five addressing modes register direct immediate register indirect base register plus index register indirect Table 4 1 summarizes the memory spaces which may be accessed by each of the addressing modes Register Addressing Register addressing accesses the eight working registers RO R7 of the selected register bank The least significant bit of the instruction opcode indicates which register is to be used ACC B DPTR and CY the Boolean processor accumulator can also be addressed as registers Direct Addressing Direct addressing is the only method of accessing the special function registers The lower 128 bytes of internal RAM are also directly addressable Immediate Addressing Immediate addressing allows constants to be part of the instruction in program memory User s Manual 4 1 2000 07 o _ C nfineon C500 technologies Instruction Set Table 4 1 Addressing Modes and Associated Memory Spaces Addressing Modes Associated Memory Spaces Register addressing RO through R7 of selected register bank ACC B CY Bit DPTR Direct addressing Lower 128 bytes of internal RAM special function registers Immediate addressing Program memory Register indirect Internal RAM R1 RO SP external data memory addressing R1 RO DPTR Base register plus index Program memory DPTR PC register addressing Register Indirect Addressing Reg
17. 2 Cycle Instruction 0 0 Read next 000000 again Read Read next 000000 000000 No Fetch No Fetch MOVX Discard No ALE gt _5 lt 5 d MOVX 1 Byte 2 ADDR DATA Access of External Memory MCD02771 Figure 3 1 Fetch Execute Sequence User s Manual 3 2 2000 07 o _ C nfineon C500 technologies CPU Timing 3 2 Accessing External Memory There are two types of external memory accesses accesses to external program memory and accesses to external data memory Accesses to external program memory use the signal PSEN program store enable as the read strobe Accesses to external data memory use the RD or WR alternate functions of P3 7 and P3 6 to access the memory Fetches from external program memory always use a 16 bit address Accesses to external data memory can use either a 16 bit address MOVX DPTR or an 8 bit address MOVX Ri Whenever a 16 bit address is used the high byte of the address comes out on port 2 where it is held for the duration of the read write or code fetch cycle If an 8 bit address is being used MOVX Ri the contents of the port 2 SFR remain at the port 2 pins throughout the whole external memory cycle In this case port 2 pins can be used to page the external data memory In either case the low byte of the address is time multiplexed with the data byte on port 0 The
18. 3 1 2 2 1 Internal Data Memory 1 3 1 2 2 2 Internal Data Memory XRAM 1 5 1 2 2 3 External Data Memory 1 6 1 2 3 Special Function Register Area 1 6 2 CPU Architecture 2 1 2 1 resti e he ea LET 2 2 2 2 ped d EAE race EEEE 2 2 2 3 Program Status Word awake x a x ka 2 2 2 4 Stack Pointer 3 eua dada _ _ 2 3 2 5 Data POIO MEE EO I ELSE Ut COT TOL TIT QUIT 2 4 2 5 1 The Importance of Additional Datapointers 2 5 2 5 2 How the eight Datapointers of the C500 Realized 2 5 2 5 3 Advantages of Multiple Datapointers 2 6 2 5 4 Application Example and Performance Analysis 2 6 2 6 Enhanced Hooks Emulation Concept 2 9 2 7 Basic Interrupt Handling 2 10 2 8 Interrupt Response Time 2 12 3 CPU TIMING 3 1 3 1 Basic IMINO he Gee age 3 1 3 2 Accessing External Memory 3 3 3 2 1 Accessing External Program Memory 3 3 3 2 2 Accessing External Data Memory
19. 3 2 Ri A MOV Ri lt 111100111 1 1 Ri direct MOV Ri lt direct 10100111 direct address 2 2 4 49 2000 07 C nfineon C500 technologies Instruction Set MOV Ri data Operation MOV Ri lt data Encoding 01110111 immediate data Bytes 2 Cycles 1 User s Manual 4 50 2000 07 e nfineon technologies MOV Function Description Example MOV Operation Encoding Bytes Cycles MOV Operation Encoding Bytes Cycles User s Manual C500 Instruction Set lt dest bit gt lt src bit gt Move bit data The Boolean variable indicated by the second operand is copied into the location specified by the first operand One of the operands must be the carry flag the other may be any directly addressable bit No other register or flag is affected The carry flag is originally set The data present at input port 3 is 11000101 data previously written to output port 1 is 354 001101018 MOV 223 MOV P1 2 C will leave the carry cleared and change port 1 to 394 001110016 C bit MOV C lt bit 10100010 bit address 2 1 bit C MOV bit lt 10010010 bit address 4 51 2000 07 o _ technologies Function
20. 344 Location 34H of the external RAM holds the value 564 The instruction sequence MOVX 0L1 MOVX RO A copies the value 56 into both the accumulator and external RAM location 12 4 55 2000 07 o _ nfineon technologies MOVX Operation Encoding Bytes Cycles MOVX Operation Encoding Bytes Cycles MOVX Operation Encoding Bytes Cycles MOVX Operation Encoding Bytes Cycles User s Manual C500 A QRi MOVX lt Ri 11100011 1 2 A DPTR MOVX lt 11100000 Ri A MOVX Ri lt 11110011 1 2 CDPTR A MOVX DPTR 11110000 4 56 Instruction Set 2000 07 C nfineon C500 technologies Instruction Set MUL AB Function Multiply Description MUL AB multiplies the unsigned eight bit integers in the accumulator and register B The low order byte of the sixteen bit product is left in the accumulator and the high order byte in B If the product is greater than 255 OFF the overflow flag is set otherwise it is cleared The carry flag is always cleared Example Originally the accumulator holds the value 80 50H Register 8 holds the value 160 OA0 The instruction MUL AB will give the product 12 800 3200 so is changed to 324 001100106 and the accumulator is cleared The overflow flag is set carry
21. ADDRESS DATA signal drives both FETS in the port 0 output buffers Thus in external bus mode the port 0 pins are not open drain outputs and do not require external pullups The ALE address latch enable signal should be used to latch the address byte into an external latch The address byte is valid at the negative transition of ALE Then in a write cycle the data byte to be written appears on port 0 just before WR is activated and remains there until WR is deactivated In a read cycle the incoming byte is accepted at port 0 just before the read strobe RD is deactivated During any access to external memory the CPU writes FFH to the port 0 latch the special function register thus obliterating the information in the port 0 SFR Also aMOV PO instruction must not take place during external memory accesses If the user writes to port 0 during an external memory fetch the incoming code byte may be corrupted Therefore do not write to port 0 if external memory is used 3 2 1 Accessing External Program Memory External program memory is accessed under two conditions 1 Whenever signal EA is active low or 2 Whenever signal EA is inactive high and the program counter PC contains an address greater than the internal ROM size e g 1FFFF for 8K internal ROM or 3FFF for an 16K internal ROM This requires that the ROMless versions have always EA wired to V to enable the lower 8K 16K or 32K program bytes to be fetched from e
22. C500 technologies CPU Timing 4 55 S6 51 52 53 54 55 P1 2 1 2 1 P2 P1 P2 P1 P2 1 P2 P1 P2 ALE RD PCL out if Data program memory Sampled is external DPL or Ri or or 2 SER DPH or P2 SFR Out P2 SFR MCD02773 States Figure 3 3 External Data Memory Read Cycle States 9 po 2 P2 P2 P2 Pt P2 P1 P2 ALE PCL out if program memory is external DPL or Ri RD PCL Out PCH or PCH or P2 2 SFR DPH or P2 SFR Out P2 SFR MCD02774 Figure 3 4 External Data Memory Write Cycle Users Manual 3 5 2000 07 o _ C nfineon C500 technologies Instruction Set 4 Instruction Set The C500 8 bit microcontroller family instruction set includes 111 instructions 49 of which are single byte 45 two byte and 17 three byte instructions The instruction opcode format consists of a function mnemonic followed by a destination source operand field This field specifies the data type and addressing method s to be used Like all other members of the 8051 family the C500 microcontrollers can be programmed with the same instruction set common to the basic member the SAB 8051 Thus the C500 family microcontrollers are 100 software compatible to the SAB 8051 and may be programmed with 8051 assembler or high level languages 4 1 Addressing Modes
23. DPTR will change and to 134 and 01H INC DPTR lt 1 10100011 4 35 2000 07 o _ C nfineon C500 technologies JB Function Description Example Operation Encoding Bytes Cycles User s Manual Instruction Set bit rel Jump if bit is set If the indicated bit is a one jump to the address indicated otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the third instruction byte to the PC after incrementing the PC to the first byte of the next instruction The bit tested is not modified No flags are affected The data present at input port 1 is 11001010 The accumulator holds 56 010101105 The instruction sequence JB P1 2 LABEL1 JB ACC 2 LABEL2 will cause program execution to branch to the instruction at label LABEL2 JB lt if bit 1 then lt PC rel 0010 0000 bit address rel address 4 36 2000 07 o _ nfineon technologies JBC Function Description Example Operation Encoding Bytes Cycles User s Manual C500 bit rel Jump if bit is set and clear bit Instruction Set If the indicated bit is one branch to the address indicated otherwise proceed with the next instruction n either case clear the designated bit The branch destination is computed
24. The stack pointer is left decremented by two No other registers are affected the PSW is not automatically restored to its pre interrupt status Program execution continues at the resulting address which is generally the instruction immediately after the point at which the interrupt request was detected If a lower or same level interrupt is pending when the instruction is executed that one instruction will be executed before the pending interrupt is processed The stack pointer originally contains the value OBy An interrupt was detected during the instruction ending at location 01224 Internal RAM locations and contain the values 23H and 01H respectively The instruction will leave the stack pointer equal to 09 and return program execution to location 0123 15 8 lt SP SP lt SP 1 PC7 0 SP SP lt SP 1 00110010 4 66 2000 07 o _ technologies Instruction Set RL A Function Rotate accumulator left Description The eight bits in the accumulator are rotated one bit to the left Bit 7 is rotated into the bit 0 position No flags are affected Example The accumulator holds the value 0C5 110001015 The instruction RL A leaves the accumulator holding the value 8BH 1000101 1g with the carry unaffected Operation 1 lt n 0 6 0 7 Encoding 00100011 Bytes
25. by adding the signed relative displacement in the third instruction byte to the PC after incrementing the PC to the first byte of the next instruction No flags are affected Note When this instruction is used to test an output pin the value used as the original data will be read from the output data latch not the input pin The accumulator holds 56H 010101105 The instruction sequence JBC JBC ACC 3 L ACC 2 OL will cause program execution to continue at the instruction identified by the label LABEL2 with the accumulator modified to 524 010100108 JBC lt PC 3 if bit 1 then bit 0 lt PC rel 0001 0000 bit address rel address 2000 07 o _ C nfineon C500 technologies JC Function Description Example Operation Encoding Bytes Cycles User s Manual Instruction Set rel Jump if carry is set If the carry flag is set branch to the address indicated otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC after incrementing the PC twice No flags are affected The carry flag is cleared The instruction sequence JC LABELI CPL C JC LABEL2 will set the carry and cause program execution to continue at the instruction identified by the label LABEL2 JC
26. datapointers can make external bus accesses two times as fast as with a standard 8051 or 8051 derivative Here four data variables in the internal RAM and two additional stack bytes were spared too This means for some applications where all eight datapointers are employed that an C500 program has up to 24 byte 16 variables and 8 stack bytes of the internal RAM free for other use User s Manual 2 8 2000 07 o _ C nfineon C500 technologies CPU Architecture 2 6 Enhanced Hooks Emulation Concept The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new innovative way to control the execution of C500 MCUs and to gain extensive information on the internal operation of the controllers Emulation of on chip ROM based programs is possible too Each production chip has built in logic for the support of the Enhanced Hooks Emulation Concept Therefore no costly bond out chips are necessary for emulation This also ensure that emulation and production chips are identical The Enhanced Hooks Technology which requires embedded logic in the C500 allows the C500 together with an EH IC to function similar to a bond out chip This simplifies the design and reduces costs of an ICE system ICE systems using an EH IC and a compatible C500 are able to emulate all operating modes of the different versions of the C500 This includes emulation of ROM ROM with code rollover and ROMless modes of operation It is also able
27. devices or systems are intended to be implanted in the human body or to support and or maintain and sustain and or protect human life If they fail it is reasonable to assume that the health of the user or other persons may be endangered C500 Architecture and Instruction Set Infineon technologies thinking C500 Architecture and Instruction Set Users Manual Revision History 2000 07 Previous Version 1998 04 Page Subjects major changes since last revision Section on Package Information removed Enhanced Hooks Technology is a trademark and patent of Metalink Corporation licensed to Infineon Technologies We Listen to Your Comments Any information within this document that you feel is wrong unclear or missing at all Your feedback will help us to continuously improve the quality of this document Please send your proposal including a reference to this document to A 50 mcdocu comments infineon com a o _ C nfineon C500 technologies Table of Contents Page 1 Fundamental Structure 1 1 1 1 Te 1 1 1 2 Memory Organization 1 2 1 2 1 Program Memory 1 2 1 2 2 Data Memory a saaie 1
28. groups In Table 4 4 the instructions are ordered in the hexadecimal order of their opcode 4 4 1 Functional Groups of Instructions Table 4 3 Instruction Set Summary Mnemonic Description Byte Cycle Arithmetic Operations ADD A Rn Add register to accumulator 1 1 ADD A direct Add direct byte to accumulator 2 1 ADD Add indirect RAM to accumulator 1 1 ADD A data Add immediate data to accumulator 2 1 ADDC A Rn Add register to accumulator with carry flag 1 1 ADDC A direct Add direct byte to A with carry flag 2 1 ADDC A Ri Add indirect RAM to A with carry flag 1 1 ADDC A data Add immediate data to A with carry flag 2 1 SUBB A Rn Subtract register from A with borrow 1 1 SUBB A direct Subtract direct byte from A with borrow 2 1 SUBB A Ri Subtract indirect RAM from A with borrow 1 1 SUBB A data Subtract immediate data from A with borrow 2 1 INC A Increment accumulator 1 1 INC Rn Increment register 1 1 INC direct Increment direct byte 2 1 INC Ri Increment indirect RAM 1 1 DEC A Decrement accumulator 1 1 DEC Rn Decrement register 1 1 DEC direct Decrement direct byte 2 1 DEC Ri Decrement indirect RAM 1 1 INC DPTR Increment data pointer 1 2 MUL AB Multiply A and 8 1 4 DIV AB Divide A by B 1 4 DA A Decimal adjust accumulator 1 1 User s Manual 4 82 2000 07 e Infineon technologies Table 4 3 C500 Instruc
29. is cleared Operation MUL Encoding 10100100 Bytes 1 Cycles 4 User s Manual 4 57 2000 07 o _ nfineon technologies NOP Function Description Example Operation Encoding Bytes Cycles User s Manual C500 Instruction Set No operation Execution continues at the following instruction Other than the PC no registers or flags are affected It is desired to produce a low going output pulse on bit 7 of port 2 lasting exactly 5 cycles A simple SETB CLR sequence would generate a one cycle pulse so four additional cycles must be inserted This may be done assuming no interrupts are enabled with the instruction sequence CLR NOP NOP NOP NOP SETB NOP P2 7 2 7 0000 0000 4 58 2000 07 o _ technologies ORL Function Description Example ORL Operation Encoding Bytes Cycles User s Manual Instruction Set lt dest byte gt lt src byte gt Logical OR for byte variables ORL performs the bitwise logical OR operation between the indicated variables storing the results in the destination byte No flags are affected except P if lt dest byte gt A The two operands allow six addressing mode combinations When the destination is the accumulator the source can use register direct register indirect or immediate addressing when the destination is a direct address the source can be the acc
30. is not set Instruction Set If the indicated bit is a zero branch to the indicated address otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the third instruction byte to the PC after incrementing the PC to the first byte of the next instruction The bit tested is not modified No flags are affected The data present at input port 1 is 11001010 The accumulator holds 564 010101105 The instruction sequence JNB JNB LABEL2 JNB P1 3 LABEL1 ACC 3 LABEL2 will cause program execution to continue at the instruction at label PC lt PC if bit 0 then PC lt PC rel 0011 0000 bit address rel address 4 40 2000 07 o _ nfineon technologies JNC Function Description Example Operation Encoding Bytes Cycles User s Manual C500 rel Jump if carry is not set Instruction Set If the carry flag is a zero branch to the address indicated otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC after incrementing the PC twice to point to the next instruction The carry flag is not modified The carry flag is set The instruction sequence JNC CPL JNC LABEL l C LABEL2 will clear the carry and cause program execu
31. 1 MOV A direct Move direct byte to accumulator 2 1 MOV A Ri Move indirect RAM to accumulator 1 User s Manual 4 83 2000 07 e Infineon technologies C500 Instruction Set Table 4 3 Instruction Set Summary Mnemonic Description Byte Cycle MOV A data Move immediate data to accumulator 2 1 MOV Rn A Move accumulator to register 1 1 MOV Rn direct Move direct byte to register 2 2 MOV Rn data Move immediate data to register 2 1 MOV direct A Move accumulator to direct byte 2 1 MOV direct Rn Move register to direct byte 2 2 MOV direct direct Move direct byte to direct byte 3 2 MOV direct Ri Move indirect RAM to direct byte 2 2 MOV direct data Move immediate data to direct byte 3 2 MOV Ri A Move accumulator to indirect RAM 1 1 MOV Ri direct Move direct byte to indirect RAM 2 2 MOV Ri data Move immediate data to indirect RAM 2 1 MOV DPTR data16 Load data pointer with a 16 bit constant 3 2 MOVC A A DPTR Move code byte relative to DPTR to accumulator 1 2 MOVC Move code byte relative to PC to accumulator 1 2 MOVX A Ri Move external RAM 8 bit addr to A 1 2 MOVX A DPTR Move external RAM 16 bit addr to A 1 2 MOVX Ri A Move A to external RAM 8 bit addr 1 2 MOVX DPTR A Move A to external RAM 16 bit addr 1 2 PUSH direct Push direct byte onto stack 2 2 POP direct Pop direct byte from sta
32. 2 1 Program Memory The program memory of the C500 family microcontrollers can be composed of either completely external program memory of only internal program memory on chip ROM EEPROM or of a mixture of internal and external program memory If the EA pin EA External Access is held at low level the C500 microcontrollers execute the program code always out of the external program memory Romless C500 derivatives can use this type of program memory only C500 derivatives with on chip program memory typically use their internal program memory only If the internal program memory is used the EA pin must be put to high level With EA high the microcontroller executes instructions internally unless the address exceeds the upper limit of the internal program memory If the program counter is set to an address e g by a jump instruction which is higher than the internal program memory instructions are executed out of an external program memory When the instruction address again is below the internal program memory size limit internal program memory is accessed again Figure 1 1 shows the typical C500 family microcontroller program memory configuration for the two cases EA 0 and EA 1 The ROM boundary shown in Figure 1 1 applies to the C501 which has 8 Kbyte of internal ROM Other C500 family microcontrollers with different ROM size have different ROM boundaries User s Manual 1 2 2000 07 o _ C nfineon C500 technologies Fundament
33. 3 The instruction in progress is RETI or any write access to interrupt enable or priority registers Any of these three conditions will block the generation of the LCALL to the interrupt service routine Condition 2 ensures that the instruction in progress is completed before vectoring to any service routine Condition 3 ensures that if the instruction in progress is or any write access to interrupt enable or interrupt priority registers then at least one more instruction will be executed before any interrupt is vectored too this delay guarantees that changes of the interrupt status can be observed by the interrupt controller The polling cycle is repeated with each machine cycle and the values polled are the values that were present at the previous machine cycle Note that if any interrupt flag is active but not being responded to for one of the conditions already mentioned or if the flag is no longer active when the blocking condition is removed the denied interrupt will not be serviced In other words the fact that the interrupt flag was once active but not serviced is not remembered Every polling cycle interrogates only the pending interrupt requests The polling sequence is illustrated in Figure 2 5 C1 4 C2 gt lt C3 gt lt C4 gt lt G5 S5P2 5 e ee Interrupts Long Call to Interrupt Interrupt
34. 500 family microcontrollers don t provide this internal RAM area MCD02767 Figure 1 2 Internal Data Memory Organization User s Manual 1 4 2000 07 o _ C nfineon C500 technologies Fundamental Structure While the SFR area and the upper internal RAM area share the same address locations 80 F814 they must be accessed through different addressing modes The upper internal RAM can only be accessed through indirect addressing while the special function registers SFRs are accessible only by direct addressing instructions The SFRs which are located at addresses with address bit 0 2 equal 0 addresses 80H 88 F8p are bitaddressable SFRs 1 2 2 2 Internal Data Memory XRAM Some members of the C500 family microcontrollers provide an additional internal data memory area called the XRAM This data memory area is logically located at the upper end of the external data memory space except C502 but it is integrated on the chip Because the XRAM is used in the same way as external data memory the same instruction types must be used for accessing the XRAM Figure 1 3 shows a typical 256 byte XRAM address mapping of the C500 microcontrollers FFFFH Internal XRAM FF00 H FFFF iy FEFFH External Data Memory 0000 XRAM is located at the upper end of the external data memory area MCD02768 Figure 1 3 XRAM Memory Mapping 256 Byte Depending on the C500 derivat
35. Thus a single interrupt system the response time is always more than 3 cycles and less than 9 cycles User s Manual 2 12 2000 07 nfineon C500 technologies CPU Timing 3 CPU Timing 3 1 Basic Timing A machine cycle consists of 6 states Each state is divided into a phase 1 half during which the phase 1 clock is active and a phase 2 half during which the phase 2 clock is active Thus a machine cycle consists of the states S1P1 state 1 phase 1 through S6P2 state 6 phase 2 Depending on the C500 type of microcontroller each state lasts either one or two periods of the oscillator clock Typically arithmetic and logical operations take place during phase 1 and internal register to register transfers take place during phase 2 The diagrams in Figure 3 1 show the fetch execute timing related to the internal states and phases Since these internal clock signals are not user accessible the ALE address latch enable signal is shown for external reference ALE is normally activated twice during each machine cycle once during 51 2 and S2P1 and again during S4P2 and S5P1 The execution of a one cycle instruction begins at S1P2 when the opcode is latched into the instruction register If it is a two byte instruction the second reading takes place during S4 of the same machine cycle If it is a one byte instruction there is still a fetch at S4 but the byte read which would be the next op code is ignored discarded fetch
36. USH DPL PUSH DPH will leave the stack pointer set to and store 23H and 01 in internal RAM locations and OB respectively PUSH SP lt SP 1 SP direct 1100 0000 direct address 4 64 2000 07 o _ technologies Instruction Set RET Function Return from subroutine Description RET pops the high and low order bytes of the PC successively from the stack decrementing the stack pointer by two Program execution continues at the resulting address generally the instruction immediately following an ACALL or LCALL No flags are affected Example The stack pointer originally contains the value Internal RAM locations and contain the values 23H and 01 respectively The instruction RET will leave the stack pointer equal to the value 09H Program execution will continue at location 0123 Operation RET 15 8 SP SP SP 1 PC7 0 SP SP SP 1 Encoding 0010 0010 Bytes 1 Cycles 2 User s Manual 4 65 2000 07 o _ technologies RETI Function Description Example Operation Encoding Bytes Cycles User s Manual Instruction Set Return from interrupt RETI pops the high and low order bytes of the PC successively from the stack and restores the interrupt logic to accept additional interrupts at the same priority level as the one just processed
37. User s Manual July 2000 C500 Architecture and Instruction Set Microcontrollers Never stop thinking Edition 2000 07 Published by Infineon Technologies C St Martin Strasse 53 D 81541 Munchen Germany Infineon Technologies AG 2000 All Rights Reserved Attention please The information herein is given to describe certain components and shall not be considered as warranted characteristics Terms of delivery and rights to technical change reserved We hereby disclaim any and all warranties including but not limited to warranties of non infringement regarding circuits descriptions and charts stated herein Infineon Technologies is an approved CECC manufacturer Information For further information on technology delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide see address list Warnings Due to technical requirements components may contain dangerous substances For information on the types in question please contact your nearest Infineon Technologies Office Infineon Technologies Components may only be used in life support devices or systems with the express written approval of Infineon Technologies if a failure of such components can reasonably be expected to cause the failure of that life support device or system or to affect the safety or effectiveness of that device or system Life support
38. a Boolean processor performing the bit operations as set clear complement jump if not set jump if set and clear and move to from carry Between any addressable bit or its complement and the carry flag it can perform the bit operations of logical AND or logical OR with the result returned to the carry flag The program control section of the core controls the sequence in which the instructions stored in program memory are executed The 16 bit program counter PC holds the address of the next instruction to be executed The conditional branch logic enables internal and external events to the processor to cause a change in the program execution sequence 2 1 Accumulator ACC is the symbol for the accumulator register The mnemonics for accumulator specific instructions however refer to the accumulator simply as A 2 2 B Register The B register is used during multiply and divide and serves as both source and destination For other instructions it can be treated as another scratch pad register 2 3 Program Status Word The Program Status Word PSW contains several status bits that reflect the current state of the CPU The bits of the PSW are used for different functions which are two register bank selection bits two carry flags and an overflow flag for arithmetic instructions a parity bit for the content of the ACC and two general purpose flags The bit definitions of the PSW are shown on the next page User s Manual 2 2 2000 07
39. al Structure FFFF External Program External Memory Program Memory 2000 1FFF H Internal Boundary Program Memory 0000 0000 The location of the ROM boundary depends on the specific C500 devices MCD02766 Figure 1 1 Program Memory Configuration Example of the C501 1 2 2 Data Memory The data memory area of the C500 family microcontrollers consists of internal and external data memory portions The internal data memory area is addressed using 8 bit addresses The external data memory and the internal XRAM data memory are addressed by 8 bit or16 bit addresses The content of the internal data memory also XRAM is not affected by a reset operation After power up the content is undefined while it remains unchanged during and after a reset as long as the power supply is not turned off The XRAM content is also maintained when the C500 microcontrollers are in power saving modes 1 2 2 4 Internal Data Memory The internal data memory address space is divided into three basic physically separate and distinct blocks the lower 128 byte of internal data RAM the upper 128 byte of internal data RAM and the 128 byte special function register SFR area The lower internal data RAM and the SFR area further include 128 bit locations each These bits can be handled by specific bit manipulation instructions User s Manual 1 3 2000 07 C500 technologies Fundamental Structu
40. alue 764 011101105 and 354 001101018 in the accumulator XCHD A3 0 s Ri 3 0 11010111 4 78 2000 07 C nfineon C500 technologies XRL Function Description Example XRL Operation Encoding Bytes Cycles User s Manual Instruction Set lt dest byte gt lt src byte gt Logical Exclusive OR for byte variables XRL performs the bitwise logical Exclusive OR operation between the indicated variables storing the results in the destination No flags are affected except P if lt dest byte gt A The two operands allow six addressing mode combinations When the destination is the accumulator the source can use register direct register indirect or immediate addressing when the destination is a direct address the source can be accumulator or immediate data Note When this instruction is used to modify an output port the value used as the original port data will be read from the output data latch not the input pins If the accumulator holds 1100001 1g and register 0 holds OAA 101010108 then the instruction XRL A RO will leave the accumulator holding the value 69H 011010016 When the destination is a directly addressed byte this instruction can complement combinations of bits in any RAM location or hardware register The pattern of bits to be complemented is then determined by a mask byte either a constant contained in the instruction or a var
41. ared and both the carry flag and OV set to 1 A Rn ADDC lt A Rn 001111 A direct ADDC lt direct 001110101 direct address 2 1 4 13 2000 07 o _ nfineon technologies ADDC Operation Encoding Bytes Cycles ADDC Operation Encoding Bytes Cycles User s Manual C500 A QRi ADDC lt A Ri 00110111 1 1 data ADDC A data 00110100 2 1 immediate data 4 14 Instruction Set 2000 07 o _ C nfineon C500 technologies Instruction Set AJMP addr11 Function Absolute jump Description AJMP transfers program execution to the indicated address which is formed at run time by concatenating the high order five bits of the PC after incrementing the PC twice op code bits 7 5 and the second byte of the instruction The destination must therefore be within the same 2K block of program memory as the first byte of the instruction following AJMP Example The label UMPADR is at program memory location 0123 The instruction AJMP JMPADR is at location 0345 and will load the PC with 0123 Operation lt PC 2 10 0 lt address Encoding 10 a9 0 0001 a7 a5 4 3 a2 a1 a0 Bytes Cycles Us
42. ator contents to the indicated variable The source destination operand can use register direct or register indirect addressing RO contains the address 204 The accumulator holds the value 001111118 Internal RAM location 204 holds the value 754 011101015 The instruction XCH RO will leave RAM location 204 holding the value 3FH 001111118 and 75 011101015 in the accumulator A Rn XCH A s Rn 1100 1 rrr A direct XCH A s direct 110010101 direct address 2 1 4 76 2000 07 o _ C nfineon C500 technologies Instruction Set XCH A Ri Operation s Ri Encoding 11000111 Bytes 1 Cycles 1 User s Manual 4 77 2000 07 o _ technologies XCHD Function Description Example Operation Encoding Bytes Cycles User s Manual Instruction Set A Ri Exchange digit XCHD exchanges the low order nibble of the accumulator bits 3 0 generally representing a hexadecimal or BCD digit with that of the internal RAM location indirectly addressed by the specified register The high order nibbles bits 7 4 of each register are not affected No flags are affected RO contains the address 204 The accumulator holds the value 364 001101105 Internal RAM location 204 holds the value 75 011101015 The instruction XCHD A RO will leave RAM location 204 holding the v
43. carry flag in its current state A slash preceding the operand in the assembly language indicates that the logical complement of the addressed bit is used as the source value but the source bit itself is not affected No other flags are affected Only direct bit addressing is allowed for the source operand Set the carry flag if and only if P1 0 1 ACC 7 1 and OV 0 MOV ANL ANL C bit ANL 1 0 C ACC 7 C CV C bit 1000 0010 C bit ANL lt C A bit 1011 0000 Load carry with input pin state AND carry with accumulator bit 7 AND with inverse of overflow flag bit address bit address 4 19 2000 07 o _ C nfineon C500 technologies Function Description Example Users Manual Instruction Set lt dest byte gt lt Src byte gt ICI Compare and jump if not equal CJNE compares the magnitudes of the tirst two operands and branches if their values not equal The branch destination is computed by adding the signed relative displacement in the last instruction byte to the PC after incrementing the PC to the start of the next instruction The carry flag is set if the unsigned integer value of lt dest byte gt is less than the unsigned integer value of lt src byte gt otherwise the carry is cleared Neither operand is affected The first two o
44. ck 2 2 XCH A Rn Exchange register with accumulator 1 1 XCH A direct Exchange direct byte with accumulator 2 1 XCH A Ri Exchange indirect RAM with accumulator 1 1 XCHD A Ri Exchange low order nibble indir RAM with A 1 1 Boolean Variable Manipulation CLR C Clear carry flag 1 1 CLR bit Clear direct bit 2 1 SETB C Set carry flag 1 1 SETB bit Set direct bit 2 1 CPL C Complement carry flag 1 1 CPL bit Complement direct bit 2 1 Users Manual 4 84 2000 07 e Infineon technologies C500 Table 4 3 Instruction Set Summary Instruction Set Mnemonic Description Byte Cycle ANL bit AND direct bit to carry flag 2 2 ANL C bit AND complement of direct bit to carry 2 2 ORL C bit OR direct bit to carry flag 2 2 ORL C bit OR complement of direct bit to carry 2 2 C bit Move direct bit to carry flag 2 1 MOV bit C Move carry flag to direct bit 2 2 Program and Machine Control Absolute subroutine call LCALL addri6 Long subroutine call RET Return from subroutine RETI Return from interrupt AJMP addr11 Absolute jump LJMP addr16 Long iump SJMP rel Short jump relative addr JMP A DPTR Jump indirect relative to the DPTR JZ rel Jump if accumulator is zero JNZ rel Jump if accumulator is not zero JC rel Jump if carry flag is set
45. ction of the on chip memory resources The IRAM provides the internal RAM which includes the general purpose registers The interrupt requests from the peripheral units are handled by an interrupt controller unit C500 device specific is the configuration of the on chip peripheral units Serial interfaces timers capture compare units A D converters watchdog units or a multiply divide unit are typical examples for on chip peripheral units The external signals of these peripheral units are available at multifunctional parallel I O ports or at dedicated pins User s Manual 2 1 2000 07 o _ C nfineon C500 technologies CPU Architecture The arithmetic section of the core performs extensive data manipulation and is comprised of the arithmetic logic unit ALU an A register B register and PSW register Further it has extensive facilities for binary and BCD arithmetic and excels in its bit handling capabilities Efficient use of program memory results from an instruction set consisting of 44 one byte 41 two byte and 15 three byte instructions The ALU accepts 8 bit data words from one or two sources and generates an 8 bit result under the control of the instruction decoder The ALU performs the arithmetic operations add substract multiply divide increment decrement BDC decimal add adjust and compare and the logic operations AND OR Exclusive OR complement and rotate right left or swap nibble left four Also included is
46. d No other register or flag is affected This is by far the most flexible operation Fifteen combinations of source and destination addressing modes are allowed Internal RAM location 304 holds 40H The value RAM location 40 is 10H The data present at input port 1 is 11001010 OCA MOV RO 30H RO lt 30H MOV GRO lt 40H MOV R1 A 861 lt 40H MOV B 1 lt 10H MCV GR1 P1 RAM 40H lt OCAH MCV P2 PW P2 lt 0 leaves the value 30H in register 0 40H in both the accumulator and register 1 104 in register and OCA 11001010B both RAM location 40 and output on port 2 A Rn MOV lt 1110I1rrr 1 1 A direct MOV lt direct 11100101 direct address 2 1 1 MOV is not avalid instruction The content of the accumulator after the execution of this instruction is undefined User s Manual 4 46 2000 07 o _ nfineon technologies MOV Operation Encoding Bytes Cycles MOV Operation Encoding Bytes Cycles MOV Operation Encoding Bytes Cycles MOV Operation Encoding Bytes Cycles User s Manual C500 lt Ri 1110 0111 data MOV lt data 0111 0100 Rn A MOV Rn lt immediate data
47. data rel lt if A lt gt data then PC PC relative offset if lt data then 1 else C 0 10110100 immediate data rel address RN data rel lt PC if Rn lt gt data then PC PC relative offset if Rn lt data then C 1 else C 0 10111 immediate data rel address 3 2 2000 07 e nfineon technologies CJNE Operation Encoding Bytes Cycles CLR Function Description Example Operation Encoding Bytes Cycles User s Manual C500 Instruction Set Ri data rel lt PC if Ri lt gt data then PC PC relative offset if Ri lt data then 1 else 0 NN om 10110111 immediate data rel address A Clear accumulator The accumulator is cleared all bits set to zero No flags are affected The accumulator contains 5CH 010111005 The instruction CLR A will leave the accumulator set to 00H 00000000 CLR 0 11100100 2000 07 1 technologies CLR Function Description Example CLR Operation Encoding Bytes Cycles CLR Operation Encoding Bytes Cycles User s Manual Instructio
48. e eight bits in the accumulator and the carry flag are together rotated one bit to the right Bit 0 moves into the carry flag the original value of the carry flag moves into the bit 7 position No other flags are affected Example The accumulator holds the value 0C5 110001015 the carry is zero The instruction RRC A leaves the accumulator holding the value 624 0110001 0g with the carry set Operation RRC An An 1 n 0 6 A7 lt 0 Encoding 00010011 Bytes 1 Cycles 1 User s Manual 4 70 2000 07 e nfineon technologies SETB Function Description Example SETB Operation Encoding Bytes Cycles SETB Operation Encoding Bytes Cycles User s Manual C500 lt bit gt Set bit Instruction Set SETB sets the indicated bit to one SETB can operate on the carry flag or any directiy addressable bit No other flags are affected The carry flag is cleared Output port 1 has been written with the value 34 001101005 The instructions SETB SETB gt P1 0 will leave the carry flag set to 1 and change the data output on port 1 to 35 001101015 C SETB C 1 1101 0011 1 1 bit SETB bit lt 1 1101 0010 2 1 bit address 2000 07 o _ C nfineon C500 technologies Instruction Set SJMP rel Function Short jump D
49. e no interrupt of the same or lower priority level would be acknowledged 2 8 Interrupt Response Time If an external interrupt is recognized its corresponding request flag is set at S5P2 in every machine cycle The value is not polled by the circuitry until the next machine cycle If the request is active and conditions are right for it to be acknowledged a hardware subroutine call to the requested service routine will be next instruction to be executed The call itself takes two cycles Thus a minimum of three complete machine cycles will elapse between activation and external interrupt request and the beginning of execution of the first instruction of the service routine A longer response time would be obtained if the request was blocked by one of the three previously listed conditions If an interrupt of equal or higher priority is already in progress the additional wait time obviously depends on the nature of the other interrupt s service routine If the instruction in progress is not in its final cycle the additional wait time cannot be more than 3 cycles since the longest instructions MUL and DIV are only 4 cycles long and if the instruction in progress is RETI or a write access to interrupt enable or interrupt priority registers the additional wait time cannot be more than 5 cycles a maximum of one more cycle to complete the instruction in progress plus 4 cycles to complete the next instruction if the instruction is MUL or DIV
50. e operands byte operands and returns the result to the location of the first operand User s Manual 4 5 2000 07 o _ C nfineon C500 technologies Instruction Set 4 2 4 Control Transfer Instructions There are three classes of control transfer operations unconditional calls returns jumps conditional jumps and interrupts All control transfer operations some upon a specific condition cause the program execution to continue a non sequential location in program memory Unconditional Calls Returns and Jumps Unconditional calls returns and jumps transfer control from the current value of the program counter to the target address Both direct and indirect transfers are supported ACALL and LCALL push the address of the next instruction onto the stack and then transfer control to the target address ACALL is a 2 byte instruction used when the target address is in the current 2K page LCALL is a 3 byte instruction that addresses the full 64K program space In ACALL immediate data i e an 11 bit address field is concatenated to the five most significant bits of the PC which is pointing to the next instruction If ACALL is in the last 2 bytes of a 2K page then the call will be made to the next page since the PC will have been incremented to the next instruction prior to execution RET transfers control to the return address saved on the stack by a previous call operation and decrements the SP register by two 2 to ad
51. e read from the output data latch not the input pins Register 0 contains 7 011111108 Internal RAM locations 7 and 7Fy contain OFFy and 40y respectively The instruction sequence INC RO INC RO INC RO will leave register 0 set to 7 and internal RAM locations 7 7Fy holding respectively 00H and 414 A INC lt A 1 00000100 IMC lt 1 0000I1rrr 4 33 2000 07 o _ nfineon technologies INC Operation Encoding Bytes Cycles INC Operation Encoding Bytes Cycles User s Manual C500 direct INC direct lt direct 1 0000 0101 2 1 Ri INC Ri lt Ri 1 direct address 0000 0111 4 34 Instruction Set 2000 07 o _ C nfineon C500 technologies INC Function Description Example Operation Encoding Bytes Cycles User s Manual Instruction Set DPTR Increment data pointer Increment the 16 bit data pointer by 1 A 16 bit increment modulo 216 is performed an overflow of the low order byte of the data pointer DPL from OFF to 00 will increment the high order byte No flags are affected This is the only 16 bit register which can be incremented Registers and contain 124 and OFE respectively The instruction sequence INC DPTR INC DPTR INC
52. ect 06 INC 26 ADD A RO 46 ORL A RO 074 INC R1 27 ADD A R1 47 ORL A R1 08 INC RO 284 ADD A RO 48 ORL A RO 094 INC R1 29H ADD A R1 49 ORL A R1 OA INC R2 2A ADD A R2 4A ORL A R2 R3 2B ADD A R3 4BH ORL A R3 OC INC R4 2CH ADD A R4 4 ORL A R4 OD INC R5 2D ADD A R5 4DH ORL A R5 OE INC R6 2E A R6 4E ORL A R6 0FH INC R7 2Fy ADD A R7 4FH ORL A R7 104 JBC bit rel 30H JNB bit rel 50 JNC rel 114 ACALL 11 314 ACALL 51H ACALL 12H LCALL addr16 324 RETI 52H ANL direct A 134 RRC A 33H RLC A 534 ANL direct data 144 DEC A 344 ADDC A data 54 ANL A data 15 DEC direct 35H ADDC 55H ANL A direct 164 DEC 36 ADDC 564 ANL A RO 174 DEC 1 37 ADDC A QR1 574 ANL A R1 184 DEC RO 384 ADDC 584 ANL A RO 194 DEC R1 394 ADDC A R1 594 ANL A R1 1AH R2 3A ADDC A R2 5A ANL A R2 1B R3 3B ADDC 5By ANL A R3 1CH DEC R4 3CH ADDC A R4 5Cy ANL A R4 1DH DEC R5 3D ADDC 5 5DH ANL A R5 1E R6 3E A R6 ANL A R6 1FH DEC R7 3FH ADDC A R7 5Fy ANL A R7 User s Manual 4 86 2000 07 Infineon C500 technologies Instruction Set Table 4 4 Instruction List in Hexadecimal Order cont d Op Mnemonic Op Mnemonic Op Mnemon
53. ected User s Manual 2 4 2000 07 o _ C nfineon C500 technologies CPU Architecture 2 5 1 The Importance of Additional Datapointers The standard 8051 architecture provides just one 16 bit pointer for indirect addressing of external devices memories peripherals latches etc Except for a 16 bit move immediate to this datapointer and an increment instruction any other pointer handling is to be done byte by byte For complex applications with peripherals located in the external data memory space e g CAN controller or extended data storage capacity this turned out to be a bottle neck for the 8051 s communication to the external world Especially programming in high level languages PLM51 C51 PASCAL51 requires extended RAM capacity and at the same time a fast access to this additional RAM because of the reduced code efficiency of these languages 2 5 2 How the eight Datapointers of the C500 are Realized Simply adding more datapointers is not suitable because of the need to keep up 100 compatibility to the 8051 instruction set This instruction set however allows the handling of only one single 16 bit datapointer DPTR consisting of the two 8 bit SFRs DPH and DPL To meet both of the above requirements speed up external accesses 100 compatibility to 8051 architecture the C500 contains a set of eight 16 bit registers from which the actual datapointer can be selected This means that the user s program
54. egister DPTR or PC The byte operand accessed Is transferred to the accumulator User s Manual 4 3 2000 07 o _ C nfineon C500 technologies Instruction Set Address Object Transfer MOV DPTR data loads 16 bits of immediate data into a pair of destination registers DPH and DPL 4 2 2 Arithmetic Instructions The C500 family microcontrollers have four basic mathematical operations Only 8 bit operations using unsigned arithmetic are supported directly The overflow flag however permits the addition and subtraction operation to serve for both unsigned and signed binary integers Arithmetic can also be performed directly on packed BCD representations Addition NC increment adds one to the source operand and puts the result in the operand flags in PSW are not affected ADD adds A to the source operand and returns the result to A ADDC add with carry adds A and the source operand then adds one 1 if CY is set and puts the result in A DA decimal add adjust for BCD addition corrects the sum which results from the binary addition of two digit decimal operands The packed decimal sum formed by DA is returned to A CY is set if the BCD result is greater than 99 otherwise it is cleared Subtraction SUBB subtract with borrow subtracts the second source operand from the first operand the accumulator subtracts one 1 if CY is set and returns the result to A DEC decrement subtract
55. er incrementing the PC twice The accumulator is not modified No flags are affected The accumulator originally contains 01 4 The instruction sequence JZ LABELI DEC A JZ LABEL2 will change the accumulator to 00 and cause program execution to continue at the instruction identified by the label LABEL2 JZ PC 2 if A 0 then PC PC rel 01100000 rel address 4 43 2000 07 C nfineon C500 technologies Instruction Set LCALL addr16 Function Long call Description LCALL calls a subroutine located at the indicated address The instruction adds three to the program counter to generate the address of the next instruction and then pushes the 16 bit result onto the stack low byte first incrementing the stack pointer by two The high order and low order bytes of the PC are then loaded respectively with the second and third bytes of the LCALL instruction Program execution continues with the instruction at this address The subroutine may therefore begin anywhere in the full 64 Kbyte program memory address space No flags are affected Example Initially the stack pointer equals 074 The label SUBRTN is assigned to program memory location 12344 After executing the instruction LCALL SUBRTN at location 0123 the stack pointer will contain 09H internal RAM locations 08H and 09 will contain 26H and 014 and the PC will contain 1234 Operation
56. er s Manual 4 15 2000 07 C nfineon C500 technologies ANL Function Description Example ANL Operation Encoding Bytes Cycles User s Manual Instruction Set lt dest byte gt lt src byte gt Logical AND for byte variables ANL performs the bitwise logical AND operation between the variables indicated and stores the results in the destination variable No flags are affected except P if lt dest byte gt A The two operands allow six addressing mode combinations When the destination is a accumulator the source can use register direct register indirect or immediate addressing when the destination is a direct address the source can be the accumulator or immediate data Note When this instruction is used to modify an output port the value used as the original port data will be read from the output data latch not the input pins If the accumulator holds 1100001 15 and register 0 holds 10101010 then the instruction ANL A RO will leave 814 10000001 the accumulator When the destination is a directly addressed byte this instruction will clear combinations of bits in any RAM location or hardware register The mask byte determining the pattern of bits to be cleared would either be a constant contained in the instruction or a value computed in the accumulator at run time The instruction ANL P1 01110011B will clear bits 7 3 and 2 of output port 1
57. erally interrupt vector addresses are located in the code memory area starting at address 00034 The minimum distance between two consecutive vector addresses is always 8 bytes Therefore interrupt vectors can be assigned to the following addresses 00034 000 0013y 001By 0023 002 0033 OOFBy FFFF Program Memory Timer 2 0028 Interrupt Serial Port 00234 Interrupt Timer 1 0018 Interrupt External 00134 Interrupt 1 Timer 0 8 Bytes 0008 Interrupt External 0003H Interrupt 0 Reset 00004 MCD02770 Figure 2 4 Interrupt Vector Addresses Example of the C501 An interrupt source indicates to the interrupt controller an interrupt condition by setting an interrupt request flag The interrupt request flags are sampled in each machine cycle The sampled flags are polled during the following machine cycle If one of the flags was in a set condition in the preceeding cycle the polling cycle will find it and the interrupt controller will cause the CPU to branch to the vector address of the appropriate service routine by generating an internal LCALL This hardware generated LCALL is blocked by any of the following conditions User s Manual 2 10 2000 07 o _ C nfineon C500 technologies CPU Architecture 1 An interrupt of equal or higher priority is already in progress 2 The current polling cycle is not in the final cycle of the instruction in progress
58. escription Program control branches unconditionally to the address indicated The branch destination is computed by adding the signed displacement in the second instruction byte to the PC after incrementing the PC twice Therefore the range of destinations allowed is from 128 bytes preceding this instruction to 127 bytes following it Example The label RELADR is assigned to an instruction at program memory location 01234 The instruction SJMP RELADR will assemble into location 0100H After the instruction is executed the PC will contain the value 0123 Note Under the above conditions the instruction following SUMP will be at 102 Therefore the displacement byte of the instruction will be the relative offset 01234 010214 214 In other words an SUMP with displacement of OFEH would be a one instruction infinite loop Operation SUMP lt PC 2 lt PC rel Encoding 10000000 ICI address Bytes Cycles User s Manual 4 72 2000 07 o _ technologies SUBB Function Description Example SUBB Operation Encoding Bytes Cycles User s Manual Instruction Set A lt src byte gt Subtract with borrow SUBB subtracts the indicated variable and the carry flag together from the accumulator leaving the result in the accumulator SUBB sets the carry borrow flag if a borrow is needed for bit 7 and clears C otherwise If C
59. fineon technologies ADD Function Description Example ADD Operation Encoding Bytes Cycles ADD Operation Encoding Bytes Cycles User s Manual C500 Instruction Set A lt src byte gt Add ADD adds the byte variable indicated to the accumulator leaving the result in the accumulator The carry and auxiliary carry flags are set respectively if there is a carry out of bit 7 or bit 3 and cleared otherwise When adding unsigned integers the carry flag indicates an overflow occurred OV is set if there is a carry out of bit 6 but not out of bit 7 or a carry out of bit 7 but not out of bit 6 otherwise OV is cleared When adding signed integers OV indicates a negative number produced as the sum of two positive operands or a positive sum from two negative operands Four source operand addressing modes are allowed register direct register indirect or immediate The accumulator holds 1100001 15 and register 0 holds OAA 101010105 The instruction ADD A RO will leave 6DH 011011018 in the accumulator with the flag cleared and both the carry flag and OV set to 1 A Rn ADD lt A 0010 1rrr A direct ADD lt A direct 00100101 direct address 2 1 4 11 2000 07 e nfineon technologies ADD Operation Encoding Bytes Cycles ADD Operation E
60. g if there was a carry out of the high order bits but wouldn t clear the carry The carry flag thus indicates if the sum of the original two BCD variables is greater than 100 allowing multiple precision decimal addition OV is not affected All of this occurs during the one instruction cycle Essentially this instruction performs the decimal conversion by adding 00H 06H 60 or 664 to the accumulator depending on initial accumulator and PSW conditions Note DA A cannot simply convert a hexadecimal number in the accumulator to BCD notation nor does DA A apply to decimal subtraction The accumulator holds the value 56H 01010110p representing the packed BCD digits of the decimal number 56 Register 3 contains the value 67 011001115 representing the packed BCD digits of the decimal number 67 The carry flag is set The instruction sequence ADDC A R3 DA A will first perform a standard two s complement binary addition resulting in the value OBE 101111108 the accumulator The carry and auxiliary carry flags will be cleared The decimal adjust instruction will then alter the accumulator to the value 24 00100100 indicating the packed BCD digits of the decimal number 24 the low order two digits of the decimal sum of 56 67 and the carry in The carry flag will be set by the decimal adjust instruction indicating that a decimal overflow occurred The true sum 56 67 and 1 is 124 4 26 2000 07 o _ technologie
61. he PSW flags The number of bytes and machine cycles required the binary machine language encoding and a symbolic description or restatement of the function is also provided Note Only the carry auxiliary carry and overflow flags are discussed The parity bit is always computed from the actual content of the accumulator Similarly instructions which alter directly addressed registers could affect the other status flags if the instruction is applied to the PSW Status flags can also be modified by bit manipulation User s Manual 4 8 2000 07 o _ technologies Instruction Set Notes on Data Addressing Modes Rn direct Ri data data 16 bit A Working register RO R7 128 internal RAM locations any IC port control or status register Indirect internal or external RAM location addressed by register RO or R1 8 bit constant included in instruction 16 bit constant included as bytes 2 and 3 of instruction 128 software flags any bit addressable I O pin control or status bit Accumulator Notes on Program Addressing Modes addri6 addr11 rel Destination address for LCALL and LJMP may be anywhere within the 64 Kbyte program memory address space Destination address for ACALL and AJMP will be within the same 2 Kbyte page of program memory as the first byte of the following instruction SJMP and all conditional jumps include an 8 bit offset byte Range is 127 128 bytes relative t
62. iable computed in the accumulator at run time The instruction XRL P1 00110001B will complement bits 5 4 and O of output port 1 A Rn XRL2 lt v Rn 01101rrr 4 79 2000 07 o _ nfineon technologies XRL Operation Encoding Bytes Cycles XRL Operation Encoding Bytes Cycles XRL Operation Encoding Bytes Cycles XRL Operation Encoding Bytes Cycles User s Manual C500 A direct XRL A lt A direct 0110 0101 2 1 Ri XRL lt Ri direct address 0110 0111 data XRL lt A v data 0110 0100 2 1 direct A XRL direct lt direct v A immediate data 0110 0010 2 1 direct address 4 80 Instruction Set 2000 07 C nfineon C500 technologies Instruction Set XRL direct data Operation direct lt direct v data Encoding 01100011 direct address immediate data Bytes 3 Cycles 2 User s Manual 4 81 2000 07 e Infineon C500 technologies Instruction Set 4 4 Instruction Set Summary Tables The following two tables give a survey about the instruction set of the C500 family microcontrollers In Table 4 3 the instructions are ordered in functional
63. ic Code Code Code 60 JZ rel 804 SJMP rel A0 ORL C bit AJMP 11 81 AJMP addr11 Aly AJMP L11 62 XRL direct 824 ANL C bit A2 63 XRL direct data 834 MOVC A A PC INC DPTR 64 XRL A data 844 DIV AB A44 MUL AB 65 XRL A direct 85 MOV direct direct Ady l 66H XRL A RO 86H MOV direct ORO A6 MOV RO direct 67 XRL A R1 87 MOV direct R1 A74 MOV 684 XRL A RO 88 MOV direct RO A8H MOV 694 XRL A R1 894 MOV direct R1 A94 MOV R1 direct A R2 8AH MOV direct R2 MOV R2 direct 6BH A R3 88 MOV direct R3 ABH MOV R3 direct 6Cy A R4 8CH MOV direct R4 AC MOV R4 direct 6Dy A R5 8DH 5 ADH MOV R5 direct 6EH A R6 8EH MOV direct R6 AEH R6 direct 6FH A R7 8FH MOV direct R7 AF MOV R7 direct 704 JNZ rel 904 MOV DPTR data16 BO ANL 714 ACALL 11 914 ACALL addr11 72 ORL C direct 924 B2H bit 73H JMP A DPTR 93H MOVC A A DPTR CPL C 744 MOV A data 944 SUBB A data B44 CJNE A data rel 75H direct data 95 SUBB Agirect 5 CJNE Agirect el 764 MOV RO0 data 964 SUBB 86 CJNE RO data rel 774 MOV R1 data 97 SUBB A RI1 B7 CJNE Rt data rel 784 MOV RO data 984 SUBB B84 CJNE RO data rel 794 MOV R i data 994 SUBB A R1 B94 R1 data rel
64. ine cycles with a single instruction The instruction sequence MOV R2 8 TOGGLE CPL Pl DJNZ R2 TOGGLE will toggle P1 7 eight times causing four output pulses to appear at bit 7 of output port 1 Each pulse will last three machine cycles two for DJNZ and one to alter the pin 4 31 2000 07 o _ nfineon technologies DJNZ Operation Encoding Bytes Cycles DJNZ Operation Encoding Bytes Cycles User s Manual C500 Rn rel DJNZ lt PC 2 Rn lt Rn 1 if Rn 0 or Rn lt 0 then PC lt rel 1101 1rrr rel address direct rel DJNZ lt PC 2 direct lt direct 1 if direct gt 0 or direct lt 0 then PC PC rel Instruction Set 1101 0101 direct address rel address 3 2 2000 07 o _ nfineon technologies INC Function Description Example INC Operation Encoding Bytes Cycles INC Operation Encoding Bytes Cycles User s Manual C500 Instruction Set lt byte gt Increment INC increments the indicated variable by 1 An original value of OFFy will overflow to 001 No flags are affected Three addressing modes allowed register direct or register indirect Note When this instruction is used to modify an output port the value used as the original port data will b
65. ister 0 set to 7 and internal RAM locations 7 and 7Fy set to OFFy and 3FH A DEC lt A 1 00010100 lt Rn 1 0001 1rrr 4 28 2000 07 o _ nfineon technologies DEC Operation Encoding Bytes Cycles DEC Operation Encoding Bytes Cycles User s Manual C500 direct DEC direct lt direct 1 00010101 2 1 Ri DEC Ri lt Ri 1 00010111 direct address 4 29 Instruction Set 2000 07 o _ C nfineon C500 technologies Instruction Set DIV AB Function Divide Description DIV AB divides the unsigned eight bit integer in the accumulator by the unsigned eight bit integer in register B The accumulator receives the integer part of the quotient register B receives the integer remainder The carry and OV flags will be cleared Exception II B had originally contained 00H the values returned in the accumulator and B register will be undefined and the overflow flag will be set The carry flag is cleared in any case Example The accumulator contains 251 OFBH or 111110118 and B contains 18 124 or 000100105 The instruction DIV AB will leave 13 in the accumulator OD or 000011018 and the value 17 114 or 000100016 in B since 251 13 x 18 17 Carry and OV will both be cleared Operation DIV A15 8 B7 0
66. ister indirect addressing uses the contents of either RO or R1 in the selected register bank as a pointer to locations in a 256 byte block the 256 bytes of internal RAM or the lower 256 bytes of external data memory Note that the special function registers are not accessible by this method The upper half of the internal RAM can be accessed by indirect addressing only Access to the full 64 Kbytes of external data memory address space is accomplished by using the 16 bit data pointer Execution of PUSH and POP instructions also uses register indirect addressing The stack may reside anywhere in the internal RAM Base Register plus Index Register Addressing Base register plus index register addressing allows a byte to be accessed from program memory via an indirect move from the location whose address is the sum of a base register DPTR or PC and index register ACC This mode facilitates look up table accesses Boolean Processor The Boolean processor is a bit processor integrated into the 500 family microcontrollers It has its own instruction set accumulator the carry flag bit addressable RAM and I O The bit manipulation instructions allow set bit clear bit complement bit jump if bit is set jump if bit is not set jump if bit is set and clear bit move bit from to carry User s Manual 4 2 2000 07 o _ C nfineon C500 technologies Instruction Set Addressable bits or their compleme
67. ister is not altered Sixteen bit addition is performed so a carry out from the low order eight bits may propagate through higher order bits No flags are affected A value between 0 and 3 is in the accumulator The following instructions will translate the value in the accumulator to one of four values defined by the DB define byte directive INC A PC RET DB 66H DB 77H DB 88H DB 99H If the subroutine is called with the accumulator equal to 01 it will return with 774 in the accumulator The INC A before the instruction is needed to get around the RET instruction above the table If several bytes of code separated the MOVC from the table the corresponding number would be added to the accumulator instead A OA DPTR MOVC lt DPTR 10010011 4 53 2000 07 o _ C nfineon C500 technologies Instruction Set A A PC Operation MOVC PC PC 1 lt A PC Encoding 1000 0 01 1 Bytes 1 Cycles 2 User s Manual 4 54 2000 07 o _ C nfineon C500 technologies MOVX Function Description Example User s Manual Instruction Set lt dest byte gt lt src byte gt Move external The MOVX instructions transfer data between the accumulator and a byte of external data memory hence the X appended to MOV There are two types of instructions differing in whether they pro
68. ive the size of the XRAM area differs from 128 upto 3K byte Further the XRAM can be enabled or disabled If an internal XRAM area is disabled external data memory can be accessed in the address range of the internal XRAM User s Manual 1 5 2000 07 o _ C nfineon C500 technologies Fundamental Structure 1 2 2 3 External Data Memory The 64 Kbyte external data memory can be addressed by instructions that use 8 bit or 16 bit indirect addressing A 16 bit external memory addressing mode is supported by the instructions using the 16 bit datapointer DPTR for addressing For 8 bit addressing MOVX instructions with the general purpose registers RO R1 are used 1 2 3 Special Function Register Area The registers of a C500 microcontroller except the program counter and the four general purpose register banks reside in the special function register SFR area The special function register area typically provides 128 bytes of direct addressable SFRs The SFRs which are located at addresses with address bit 0 2 equal 0 addresses 804 884 8 are bitaddressable SFRs see also Figure 1 1 For example the SFR with byte address 80 provides the bit locations with bit addresses 80H to 87 The bit addresses of the SFR bits reach from 80 to F8H Due to the limited number of 128 standard SFRs some derivatives of the C500 microcontroller family provide an additional 128 byte SFR area called the mapped SFR a
69. just the SP for the popped address AJMP LUMP SJMP transfer control to the target operand The operation of AJMP and LUMP are analogous to ACALL and LCALL The SJMP short jump instruction provides for transfers within a 256 byte range centered about the starting address of the next instruction 128 to 127 JMP A DPTR performs a jump relative to the DPTR register The operand in A is used as the offset 0 255 to the address in the DPTR register Thus the effective destination for a jump can be anywhere in the program memory space User s Manual 4 6 2000 07 o _ C nfineon C500 technologies Instruction Set Conditional Jumps Conditional jumps perform a jump contingent upon a specific condition The destination will be within a 256 byte range centered about the starting address of the next instruction 128 to 127 JZ performs a jump if the accumulator is zero JNZ performs a jump if the accumulator is not zero JC performs a jump if the carry flag is set JNC performs a jump if the carry flag is not set JB performs a jump if the directly addressed bit is set JNB performs a jump if the directly addressed bit is not set JBC performs a jump if the directly addressed bit is set and then clears the directly addressed bit CJNE compares the first operand to the second operand and performs a jump if they are not equal CY is set if the first operand is less tha
70. may keep up to eight 16 bit addresses resident in these registers but only one register at a time is selected to be the datapointer Thus the datapointer in turn is accessed or selected via indirect addressing This indirect addressing is done through a special function register called DPSEL data pointer select register All instructions of the C500 which handle the datapointer therefore affect only one of the eight pointers which is addressed by DPSEL at that very moment Figure 5 1 illustrates the addressing mechanism a 3 bit field in register DPSEL points to the currently used DPTRx Any standard 8051 instruction e g MOVX DPTR A transfer a byte from accumulator to an external location addressed by DPTR now uses this activated DPTRx User s Manual 2 5 2000 07 o _ C nfineon C500 technologies CPU Architecture 1 21411 0 DPSEL 92H DPTB7 DPSEL Selected Data 2 0 pointer 0 DPTRO DPTRO 0 0 1 1 0 1 0 DPTR2 DPH 83H DPL 821 0 1 1 DPTR3 1 0 0 DPTR4 1 0 1 DPTRS External Data Memory 1 1 0 DPTR6 MCD00779 1 1 1 DPTR 7 Figure 2 2 Accessing of External Data Memory via Multiple Datapointers 2 5 3 Advantages of Multiple Datapointers Using the above addressing mechanism for external data memory results in less code and faster execution of external accesses Whenever the conten
71. mple Operation Encoding Bytes Cycles User s Manual Instruction Set direct Pop from stack The contents of the internal RAM location addressed by the stack pointer is read and the stack pointer is decremented by one The value read is the transfer to the directly addressed byte indicated No flags are affected The stack pointer originally contains the value 32H and internal RAM locations 30 through 32H contain the values 20H 23 and 014 respectively The instruction sequence POP DPH POP DPL will leave the stack pointer equal to the value 30H and the data pointer set to 0123H At this point the instruction POP SP will leave the stack pointer set to 20H Note that in this special case the stack pointer was decremented to 2FH before being loaded with the value popped 20 POP direct lt SP SP lt SP 1 11010000 direct address 4 63 2000 07 o _ C nfineon C500 technologies PUSH Function Description Example Operation Encoding Bytes Cycles User s Manual Instruction Set direct Push onto stack The stack pointer is incremented by one The contents of the indicated variable is then copied into the internal RAM location addressed by the stack pointer Otherwise no flags are affected On entering an interrupt routine the stack pointer contains 09 4 The data pointer holds the value 01234 The instruction sequence P
72. n Set bit Clear bit The indicated bit is cleared reset to zero No other flags are affected CLR can operate on the carry flag or any directly addressable bit Port 1 has previously been written with 5DH 010111016 The instruction CLR P1 2 will leave the port set to 594 010110018 C CLR C 0 11000011 bit CLR bit lt 0 11000010 bit address 4 23 2000 07 o _ C nfineon C500 technologies Instruction Set CPL A Function Complement accumulator Description Each bit of the accumulator is logically complemented one s complement Bits which previously contained a one are changed to zero and vice versa No flags are affected Example The accumulator contains 5CH 010111005 The instruction CPL A will leave the accumulator set to 101000116 Operation CPL lt Encoding 11110100 Bytes 1 Cycles 1 User s Manual 4 24 2000 07 o _ nfineon technologies CPL Function Description Example CPL Operation Encoding Bytes Cycles CPL Operation Encoding Bytes Cycles User s Manual C500 bit Complement bit Instruction Set The bit variable specified is complemented A bit which had been a one is changed to zero and vice versa No other flags are affected CPL can operate on the carry or any directly addressable bit Note When this instructio
73. n is used to modify an output pin the value used as the original data will be read from the output data latch not the input pin Port 1 has previously been written with 5DH 010111018 The instruction sequence CPL CPL will leave the port set to 5BH 010110115 C CPL BI l bit lt C 1011 0011 bit CPL lt bit 1011 0010 bit address 4 25 2000 07 o _ C nfineon C500 technologies DA Function Description Example User s Manual Instruction Set A Decimal adjust accumulator for addition DA A adjusts the eight bit value in the accumulator resulting from the earlier addition of two variables each in packed BCD format producing two four bit digits Any ADD or ADDC instruction may have been used to perform the addition If accumulator bits 3 0 are greater than nine xxxx1010 xxxx1111 or if the AC flag is one six is added to the accumulator producing the proper BCD digit in the low order nibble This internal addition would set the carry flag if a carry out of the low order four bit field propagated through all high order bits but it would not clear the carry flag otherwise If the carry flag is now set or if the four high order bits now exceed nine 1010xxxx 1111xxxx these high order bits are incremented by six producing the proper BCD digit in the high order nibble Again this would set the carry fla
74. n the second operand otherwise it is cleared Comparisons can be made between A and directly addressable bytes in internal data memory or an immediate value and either A a register in the selected register bank or a register indirectly addressable byte of the internal RAM DJNZ decrements the source operand and returns the result to the operand A jump is performed if the result is not zero The source operand of the DJNZ instruction may be any directly addressable byte in the internal data memory Either direct or register addressing may be used to address the source operand Interrupt Returns transfers control as RET does but additionally enables interrupts of the current priority level User s Manual 4 7 2000 07 C nfineon C500 technologies Instruction Set 4 3 Instruction Definitions All 111 instructions of the C500 family microcontrollers can essentially be condensed to 53 basic operations in the following alphabetically ordered according to the operation mnemonic section Table 4 2 PSW Flag Modification CY OV AC Instruction Flag Instruction Flag CY CY CV ADD X X X SETB 1 ADDC X X X CLR 0 SUBB X X X CPL C X MUL 0 X ANL C bit X DIV 0 X ANL C bit X DA X ORL C bit X RRC X ORL C bit X RLC X MOV C bit X CJNE X A brief example of how the instruction might be used is given as well as its effect on t
75. nal memory e g RO User s Manual 1 7 2000 07 o _ C nfineon C500 technologies CPU Architecture 2 CPU Architecture The typical architecture of a C500 family microcontroller is shown in Figure 2 1 This block diagram includes all main functional blocks of the C500 microcontrollers The shaded blocks are basic functional units which are mandatory for each C500 microcontroller The other functional blocks such as XRAM peripheral units and ROM RAM sizes are specific to each C500 microcontroller derivative XRAM Serial Port Address Bus Timers Peripheral Bus Data Bus WDU Basic functional blocks MCB02769 Figure 2 1 C500 Microcontroller Architecture Block Diagram The core block represents the CPU Central Processing Unit of the C500 family microcontrollers The CPU consists of the instruction decoder the arithmetic section the CPU registers and the program control section The housekeeper unit generates internal signals for controlling the functions of the individual internal units within the microcontroller Port O and port 2 are required for accessing external code and data memory and for emulation purposes The external control signals and the clock generation are handled in the external control block The access control unit is responsible for the sele
76. ncoding Bytes Cycles User s Manual C500 A QRi ADD lt A Ri 0010 011i A data ADD A A data 0010 0100 2 1 immediate data Instruction Set 2000 07 o _ nfineon technologies ADDC Function Description Example ADDC Operation Encoding Bytes Cycles ADDC Operation Encoding Bytes Cycles User s Manual C500 Instruction Set A lt src byte gt Add with carry ADDC simultaneously adds the byte variable indicated the carry flag and the accumulator contents leaving the result in the accumulator The carry and auxiliary carry flags are set respectively if there is a carry out of bit 7 or bit 3 and cleared otherwise When adding unsigned integers the carry flag indicates an overflow occurred OV is set if there is a carry out of bit 6 but not out of bit 7 or a carry out of bit 7 but not out of bit 6 otherwise OV is cleared When adding signed integers OV indicates a negative number produced as the sum of two positive operands or a positive sum from two negative operands Four source operand addressing modes are allowed register direct register indirect or immediate The accumulator holds 1100001 1g and register 0 holds 10101010 with the carry flag set The instruction ADDC A RO will leave 6 011011108 in the accumulator with AC cle
77. nts may be logically AND ed or OR ed with the contents of the carry flag The result is returned to the carry register 4 2 Introduction to the Instruction Set The instruction set is divided into four functional groups data transfer arithmetic logic control transfer 4 2 1 Data Transfer Instructions Data transfer operations are divided into three classes general purpose accumulator specific address object None of these operations affects the PSW flag settings except a POP or MOV directly to the PSW General Purpose Transfers MOV performs a bit or byte transfer from the source operand to the destination operand PUSH increments the SP register and then transfers a byte from the source operand to the stack location currently addressed by SP POP transfers a byte operand from the stack location addressed by the SP to the destination operand and then decrements SP Accumulator Specific Transfers exchanges the byte source operand with register A accumulator XCHD exchanges the low order nibble of the source operand byte with the low order nibble of A MOVX performs a byte move between the external data memory and the accumulator The external address can be specified by the DPTR register 16 bit or the R1 or RO register 8 bit MOVC moves a byte from program memory to the accumulator The operand in A is used as an index into a 256 byte table pointed to by the base r
78. o the first byte of the following instruction All mnemonics copyrighted O Intel Corporation 1980 User s Manual 4 9 2000 07 o _ C nfineon C500 technologies ACALL Function Description Example Operation Encoding Bytes Cycles User s Manual Instruction Set addr11 Absolute call ACALL unconditionally calls a subroutine located at the indicated address The instruction increments the PC twice to obtain the address of the following instruction then pushes the 16 bit result onto the stack low order byte first and increments the stack pointer twice The destination address is obtained by successively concatenating the five high order bits of the incremented PC op code bits 7 5 and the second byte of the instruction The subroutine called must therefore start within the same 2K block of program memory as the first byte of the instruction following ACALL No flags are affected Initially SP equals 074 The label SUBRTN is at program memory location 0345 After executing the instruction ACALL SUBRTN at location 0123 SP will contain 09H internal RAM location 08 09 will contain 25 and 01 respectively and the PC will contain 0345 ACALL PC PC 2 SP SP 1 PC7 0 SP SP 1 SP lt PC15 8 PC10 0 page address 10 a9 38 1 0 0 O 1 a7 a5 a4 a2 a1 ad 4 10 2000 07 o _ n
79. perands allow four addressing mode combinations the accumulator may be compared with any directly addressed byte or immediate data and any indirect RAM location or working register can be compared with an immediate constant The accumulator contains 34H Register 7 contains 56H The first instruction in the sequence 7 60H s o4 4 ow R7 60 NOT EQ JC REO LOW If R7 lt 60g 7 gt 60H sets the carry and branches to the instruction at label By testing the carry flag this instruction determines whether R7 is greater or less than 60H If the data being presented to port 1 is also 34H then the instruction WAIT CJNE A P1 WAIT clears the carry flag and continues with the next instruction in sequence since the accumulator does equal the data read from If some other value was input on P1 the program will loop at this point until the P1 data changes to 344 4 20 2000 07 o _ nfineon technologies CJNE Operation Encoding Bytes Cycles CJNE Operation Encoding Bytes Cycles CJNE Operation Encoding Bytes Cycles User s Manual C500 Instruction Set A direct rel lt if A lt gt direct then PC PC relative offset if A lt direct then lt 1 else 0 10110101 direct address rel address A
80. r Load Source Pointer 2 2 2 2 Number of cycles Increment and check for end of table execution time not relevant for this consideration Fetch source data byte from ROM table Save source_pointer and sload destination pointer 5 Increment destination pointer time not relevant Transfer byte to destination address Save destination pointer Restore old datapointer Total execution time machine cycles 28 2 7 2 2 2 2 2 2000 07 e nfineon technologies C500 CPU Architecture Example 2 Using Two Datapointers Code for C509 Initialization Routine MOV MOV MOV MOV DPSEL 06H DPTR 1FFFH DPSEL 07H DPTR 2FAOH Initialize DPTR6 with source pointer Initialize DPTR7 with destination pointer Table Look up Routine under Real Time Conditions PUSH MOV MOVC MOV MOVX POP 5 DPSEL DPSEL 06H DPTR A DPTR DPSEL 07H DPTR A DPSEL Number of cycles Save old source pointer 2 Load source pointer 2 Increment and check for end of table execution time not relevant for this consideration Fetch source data byte from ROM table 2 Save source pointer and sload destination pointer 2 Transfer byte to destination address 2 Save destination pointer and restore old datapointer 2 Total execution time machine cycles 12 The above example shows that utilization of the C500 s multiple
81. re Figure 1 2 shows the configuration of the three basic internal RAM areas The lower data RAM is located in the address range 00 7 and can be addressed directly e g MOV A direct or indirectly e g MOV A RO with address in RO A bit addressable area of 128 free programmable direct addressable bits is located at byte addresses 20H 2FH of the lower data RAM Bit 0 of the internal data byte at 20H has the bit address while bit 7 of the internal data byte at 2FH has the bit address 7 The lower 32 locations of the internal lower data RAM are assigned to four banks with eight general purpose registers GPRs each Only one of these banks can be enabled at a time to be used as general purpose registers FFH Upper RAM Area Internal Data RAM 70 7 3 1 indirect addressable 128 Byte gt o gt gt gt cn C1IC72 C1IC2 Internal Data RAM 16 Bytes with 128 bitaddressable Bits gt gt indirect amp direct addressable 128 Byte C7 CI Ol alo 0 0B 04 03 III 3 Registerbank 3 Registerbank 2 Registerbank 1 Registerbank 0 Internal SFR Area direct addressable 128 Byte 1 This internal RAM area is optional Some low end C
82. rea The mapped SFR area provides the same addressing capabilities direct addresses bit addressing as the standard SFR area Special Function Register SYSCON Address B1H Bit No MSB LSB 7 6 5 4 3 2 1 0 SYSCON The functions of the shaded bits are not described in this section Bit Function RMAP Special function register map bit 0 The access to the non mapped standard special function register area is enabled default after reset RMAP 1 The access to the mapped special function register area is enabled As long as bit RMAP is set mapped special function registers can be accessed This bit is not cleared by hardware automatically Thus when non mapped mapped registers are to be accessed the bit RMAP must be cleared set by software respectively each Some registers e g ACC are accessed independently of bit RMAP User s Manual 1 6 2000 07 o _ C nfineon C500 technologies Fundamental Structure Two bits in the program status word RS0 PSW 3 and RS1 PSW 4 select the active register bank This allows fast context switching which is useful when entering subroutines or interrupt service routines The 8 general purpose registers of the selected register bank may be accessed by register addressing For indirect addressing modes the registers RO and R1 are used as pointer or index register to address internal or exter
83. read or written under software control User s Manual 2 3 2000 07 o _ nfineon technologies 2 5 C500 Data Pointer CPU Architecture 8 bit accesses to the internal XRAM data memory or the external data memory are executed using the data pointer DPTR as 16 bit address register Normally the C500 family microcontrollers have one data pointer But some members of the C500 family provide eight data pointers The availability of eight data pointers especially supports the programming in high level languages which have a demand to store data in large external data memory portions Special Function Register DPL Address 82H Special Function Register Address 83 Special Function Register DPSEL Address Reset Value 00 Reset Value 00H Reset Value 00H MSB LSB Bit No 7 6 5 4 3 2 1 0 82H 7 6 5 A 3 2 1 L58 DPL 83H MSB 6 5 4 3 2 1 0 DPH 924 2 1 0 DPSEL Bit Function Reserved bits for future DPSEL 2 0 Data pointer select bits DPSEL 2 0 defines the number of the actual active data pointer DPTRO 7 DPSEL2 DPSEL1 DPSELO Function 0 0 0 Data pointer 0 selected 0 0 1 Data pointer 1 selected 0 1 0 Data pointer 2 selected 0 1 1 Data pointer 3 selected 1 0 0 Data pointer 4 selected 1 0 1 Data pointer 5 selected 1 1 0 Data pointer 6 selected 1 1 1 Data pointer 7 sel
84. s SUBB Operation Encoding Bytes Cycles User s Manual C500 Instruction Set A direct SUBB lt A direct 10010101 direct address 2 1 Ri SUBB lt A Ri 10010111 1 1 data 5088 lt A C data 10010100 immediate data 2 1 4 74 2000 07 C nfineon C500 technologies Instruction Set SWAP A Function Swap nibbles within the accumulator Description SWAP A interchanges the low and high order nibbles four bit fields of the accumulator bits 3 0 and bits 7 4 The operation can also be thought of as a four bit rotate instruction No flags are affected Example The accumulator holds the value 0C5H 110001015 The instruction SWAP A leaves the accumulator holding the value 5CH 010111008 Operation SWAP A3 0 s A7 4 A7 4 A3 0 Encoding 1100 0100 Bytes 1 Cycles 1 User s Manual 4 75 2000 07 o _ nfineon technologies Function Description Example XCH Operation Encoding Bytes Cycles XCH Operation Encoding Bytes Cycles User s Manual C500 Instruction Set A lt byte gt Exchange accumulator with byte variable XCH loads the accumulator with the contents of the indicated variable at the same time writing the original accumul
85. s one 1 from the source operand and returns the result to the operand flags in PSW are not affected Multiplication MUL performs an unsigned multiplication of the A register by the B register returning a double byte result A receives the low order byte B receives the high order byte OV is cleared if the top half of the result is zero and is set if it is not zero CY is cleared AC is unaffected Division DIV performs an unsigned division of the A register by the B register it returns the integer quotient to the A register and returns the fractional remainder to the B register Division by zero leaves indeterminate data in registers A and B and sets OV otherwise OV is cleared CY is cleared AC remains unaffected User s Manual 4 4 2000 07 o _ C nfineon C500 technologies Instruction Set Flags Unless otherwise stated in the previous descriptions the flags of PSW are affected as follows CY is set if the operation causes a carry to or a borrow from the resulting high order bit otherwise CY is cleared AC is set if the operation results in a carry from the low order four bits of the result during addition or a borrow from the high order bits to the low order bits during subtraction otherwise AC is cleared OV is set if the operation results in carry to the high order bit of the result but not a carry from the bit or vice versa otherwise OV is cleared OV is used in two s complemen
86. s y Instruction Set BCD variables can be incremented or decremented by adding 01 or 994 If the accumulator initially holds 304 representing the digits of 30 decimal then the instruction sequence ADD A 99H DA A will leave the carry set and 294 in the accumulator since 30 99 129 The low order byte of the sum can be interpreted to mean 30 1 29 Operation contents of accumulator are BCD if A3 0 gt 9 1 then 0 0 6 if 7 4 gt 9 111 then 7 4 7 4 6 Encoding 11010100 Bytes 1 Cycles 1 User s Manual 4 27 2000 07 o _ nfineon technologies DEC Function Description Example DEC Operation Encoding Bytes Cycles DEC Operation Encoding Bytes Cycles User s Manual C500 Instruction Set byte Decrement The variable indicated is decremented by 1 An original value of 00H will underflow to OFFH No flags are affected Four operand addressing modes are allowed accumulator register direct or register indirect Note When this instruction is used to modify an output port the value used as the original port data will be read from the output data latch the input pins Register 0 contains 7 011111118 Internal RAM locations 7 and 7Fy contain 00H and 40y respectively The instruction sequence DEC RO DEC RO DEC RO will leave reg
87. t arithmetic because it is set when the signal result cannot be represented in 8 bits P is set if the modulo 2 sum of the eight bits in the accumulator is 1 odd parity otherwise P is cleared even parity When a value is written to the PSW register the P bit remains unchanged as it always reflects the parity of A 4 2 3 Logic Instructions The C500 family microcontrollers perform basic logic operations on both bit and byte operands Single Operand Operations CLR sets A or any directly addressable bit to zero 0 SETB sets any directly bit addressable bit to one 1 CPL is used to complement the contents of the A register without affecting any flag or any directly addressable bit location RL RLC RR RRC SWAP are the five operations that can be performed on A RL rotate left RR rotate right RLC rotate left through carry RRC rotate right through carry and SWAP rotate left four For RLC and RRC the CY flag becomes equal to the last bit rotated out SWAP rotates A left four places to exchange bits 3 through 0 with bits 7 through 4 Two Operand Operations ANL performs bitwise logical AND of two operands for both bit and byte operands and returns the result to the location of the first operand ORL performs bitwise logical OR of two source operands for both bit and byte operands and returns the result to the location of the first operand XRL performs logical Exclusive OR of two sourc
88. tecture and Instruction Set Manual is to summarize the basic architecture and functional characteristics of all members of the C500 microcontroller family This includes the description of the architecture and the description of the complete instruction set Detailed information about the different versions of the C500 microcontrollers are given in the specific User Manuals User s Manual 1 1 2000 07 o _ C nfineon C500 technologies Fundamental Structure 1 2 Memory Organization The memory resources of the C500 family microcontrollers are organized in different types of memories data and program memory which further can be located internally on the microcontroller chip or outside of the microcontroller The memory partitioning of the C500 microcontrollers is typical for a Harvard architecture where data and program areas are held in separate memory areas The on chip peripheral units are accessed using an internal special function register memory area The available memory areas have different sizes and are located in the following five address spaces Table 1 1 C500 Address Spaces Type of Memory Location Size Program Memory External max 64 KByte Internal ROM Depending on C500 version EEPROM 2K up to 64 KByte Data Memory External max 64 KByte Internal XRAM Depending on C500 version 256 Byte up to 3 KByte Internal 128 or 256 Byte Special Function Register Internal 128 256 Bytes 1
89. tion Set Summary Instruction Set Mnemonic Description Byte Cycle Logic Operations ANL A Rn AND register to accumulator 1 1 ANL A direct AND direct byte to accumulator 2 1 ANL A Ri AND indirect RAM to accumulator 1 1 ANL A data AND immediate data to accumulator 2 1 ANL direct A AND accumulator to direct byte 2 1 ANL direct data AND immediate data to direct byte 3 2 ORL A Rn OR register to accumulator 1 1 ORL A direct OR direct byte to accumulator 2 1 ORL A Ri OR indirect RAM to accumulator 1 1 ORL A data OR immediate data to accumulator 2 1 ORL direct A OR accumulator to direct byte 2 1 ORL direct data OR immediate data to direct byte 3 2 XRL A Rn Exclusive OR register to accumulator 1 1 XRL A direct Exclusive OR direct byte to accumulator 2 1 XRL A Ri Exclusive OR indirect RAM to accumulator 1 1 XRL A data Exclusive OR immediate data to accumulator 2 1 XRL direct A Exclusive OR accumulator to direct byte 2 1 XRL direct data Exclusive OR immediate data to direct byte 3 2 CLR A Clear accumulator 1 1 CPL A Complement accumulator 1 1 RL A Rotate accumulator left 1 1 RLC A Rotate accumulator left through carry 1 1 RR A Rotate accumulator right 1 1 RRC A Rotate accumulator right through carry 1 1 SWAP A Swap nibbles within the accumulator 1 1 Data Transfer MOV A Rn Move register to accumulator 1
90. tion to continue at the instruction identified by the label LABEL2 JNC PC PC 2 if C 0 then PC lt PC rel 0101 0000 2 2 ICI address 4 41 2000 07 o _ C nfineon C500 technologies Instruction Set JNZ rel Function Jump if accumulator is not zero Description If any bit of the accumulator is a one branch to the indicated address otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC after incrementing the PC twice The accumulator is not modified No flags are affected Example The accumulator originally holds 00H The instruction sequence JNZ LABEL1 INC A JNZ LABEL2 will set the accumulator to 01 and continue at label LABEL2 Operation M7 PC PC 2 if A 0 then PC lt PC rel Encoding 01110000 ICI address Bytes Cycles User s Manual 4 42 2000 07 o _ technologies JZ Function Description Example Operation Encoding Bytes Cycles User s Manual Instruction Set rel Jump if accumulator is zero If all bits of the accumulator are zero branch to the address indicated otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC aft
91. to operate in single step mode and to read the SFRs after a break ICE System Interface to Emulation Hardware SYSCON RSYSCON EH IC C500 Enhanced Hooks MCU Interface Circuit Optional mu Ports Port3 Port 1 RPort2 RPortO TALE TPSEN Target System Interface MCS02647 Figure 2 3 Basic C500 MCU Enhanced Hooks Concept Configuration Port 0 port 2 and some of the control lines of the C500 based MCU are used by Enhanced Hooks Emulation Concept to control the operation of the device during emulation and to transfer informations about the program execution and data transfer between the external emulation hardware ICE system and the C500 MCU User s Manual 2 9 2000 07 o _ C nfineon C500 technologies CPU Architecture 2 7 Basic Interrupt Handling Each member of the C500 microcontroller family provides several interrupt sources These interrupts are generated typically by external events or by the internal peripheral units If an interrupt is accepted by the CPU the microcontroller interrupts a running program and proceeds the program execution at an interrupt source specific vector address where the interrupt service routine is located After the execution of a return from interrupt instruction the program is continued at the point where it has been interrupted Figure 2 4 shows an example for the interrupt vector addresses of a C500 microcontroller C501 Gen
92. ts of the datapointer must be altered between two or more 16 bit addresses one single instruction which selects a new datapointer does this job If the program uses just one datapointer then it has to save the old value with two 8 bit instructions and load the new address byte by byte This not only takes more time it also requires additional space in the internal RAM 2 5 4 Application Example and Performance Analysis The following example shall demonstrate the involvement of multiple data pointers in a table transfer from the code memory to external data memory Start address of ROM source table 1FFF Start address of table in external RAM 2FA0OH User s Manual 2 6 2000 07 e nfineon technologies Example 1 Using only One Datapointer Code for a C501 C500 Initialization Routine LOW SRC_PTR 0FFH Initialize shadow variables with source pointer MOV MOV MOV MOV HIGH SRC_PTR 1FH CPU Architecture LOW DES_PTR 0A0H Initialize shadow variables with destination pointer HIGH DES PTR 2FH Table Look up Routine under Real Time Conditions PUSH PUSH MOV MOV MOVC MOV MOV MOV MOV INC MOVX MOV MOV POP POP DPL DPH DPL LOW SRC_PTR DPH HIGH SRC_PTR DPTR LOW SRC_PTR DPL HIGH SRC_PTR DPH DPL LOW DES_PTR DPH HIGH DES_PTR DPTR DPTR A LOW DES_PTR DPL HIGH DES_PTR DPH DPH DPL User s Manual Save old datapointe
93. umulator or immediate data Note When this instruction is used to modify an output port the value used as the original port data will be read from the output data latch the input pins If the accumulator holds 1100001 15 and RO holds 55 010101018 then the instruction ORL A RO will leave the accumulator holding the value 007 110101118 When the destination is a directly addressed byte the instruction can set combinations of bits in any RAM location or hardware register The pattern of bits to be set is determined by a mask byte which may be either a constant data value in the instruction or a variable computed in the accumulator at run time The instruction ORL P1 00110010B will set bits 5 4 and 1 of output port 1 A Rn ORL lt Rn 0100 1rrr 4 59 2000 07 e nfineon technologies ORL Operation Encoding Bytes Cycles ORL Operation Encoding Bytes Cycles ORL Operation Encoding Bytes Cycles ORL Operation Encoding Bytes Cycles User s Manual C500 A direct ORL A lt A v direct 0100 0101 2 1 A Ri ORL A lt v Ri direct address 0100 011i A data ORL lt data 0100 0100 2 1 direct A ORL direct lt direct V immediate data
94. vide an eight bit or sixteen bit indirect address to the external data RAM In the first type the contents of RO or R1 in the current register bank provide an eight bit address multiplexed with data on PO Eight bits are sufficient for external MO expansion decoding or a relatively small RAM array For somewhat larger arrays any output port pins can be used to output higher order address bits These pins would be controlled by an output instruction preceding the MOVX In the second type of MOVX instructions the data pointer generates a sixteen bit address P2 outputs the high order eight address bits the contents of DPH while PO multiplexes the low order eight bits DPL with data The P2 special function register retains its previous contents while the P2 output buffers are emining the contents of DPH This form is faster and more efficient when accessing very large data arrays up to 64 Kbyte since no additional instructions are needed to set up the output ports Itis possible in some situations to mix the two MOVX types A large RAM array with its high order address lines driven by P2 can be addressed via the data pointer or with code to output high order address bits to P2 followed by a MOVX instruction using RO or R1 An external 256 byte RAM using multiplexed address data lines is connected to the C500 port 0 Port 3 provides control lines for the external RAM Ports 1 and 2 are used for normal I O Registers 0 and 1 contain 124 and
95. was set before executing a SUBB instruction this indicates that a borrow was needed for the previous step in a multiple precision subtraction so the carry is subtracted from the accumulator along with the source operand AC is set if a borrow is needed for bit 3 and cleared otherwise OV is set if a borrow is needed into bit 6 but not into bit 7 or into bit 7 but not bit 6 When subtracting signed integers OV indicates a negative number produced when a negative value is subtracted from a positive value or a positive result when a positive number is subtracted from a negative number The source operand allows four addressing modes register direct register indirect or immediate The accumulator holds 0C9 11001001 p register 2 holds 544 010101005 and the carry flag is set The instruction SUBB A R2 will leave the value 744 011101008 in the accumulator with the carry flag and AC cleared but OV set Notice that 0C9 minus 54 is 754 The difference between this and the above result is due to the borrow flag being set before the operation If the state of the carry is not known before starting a single or multiple precision subtraction it should be explicitly cleared by a CLR C instruction A Rn SUBB lt 10011 4 73 2000 07 o _ nfineon technologies SUBB Operation Encoding Bytes Cycles SUBB Operation Encoding Bytes Cycle
96. xternal memory When the CPU is executing out from external program memory see timing diagram in Figure 3 2 all 8 bits of port 2 are dedicated to an output function and may not be used for general purpose During external program fetches they output the high byte of the PC with the port 2 drivers using the strong pullups to emit bits that are 1 s User s Manual 3 3 2000 07 o _ C nfineon C500 technologies CPU Timing 1 52 53 54 55 56 51 52 P1 P2 P2 P1 P2 P1 P2 P1 1 P2 P1 P2 P1 P2 ALE Data Data Data Sampled Sampled Sampled PCL PCL PCL Out Out Out P2 PCH Out PCH Out PCH Out MCD02772 States Figure 3 2 External Program Memory Fetches 3 2 2 Accessing External Data Memory The port 2 drivers use the strong pullups during the entire time that they are emitting address bits that 15 This occurs when the MOVX instruction is executed and when external program fetches are executed During this time the port 2 latch the special function register does not have to contain 1 s and the contents of the port 2 SFR are not modified If the external memory cycle is not immediately followed by another external memory cycle the undisturbed contents of the port 2 SFR will reappear in the next cycle Figure 3 3 and Figure 3 4 show in detail the timings of the external data memory read and write cycles User s Manual 3 4 2000 07

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