V1724 Registers Description
Contents
1. 241 INTERRUPT STATUS ID OXEF14 enne 2 42 INTERRUPT EVENT NUMBER OXEF1 8 R W 2 43 BLT EVENT NUMBER R W 2 44 SCRATCH OXEF20 dAT cusses E EE E R E EEEE 2 45 SOFTWARE RESET OXEF24 cab reto th 2 46 SOFTWARE CLEAR XBE28 W a Rer etes ae e ages nn Neb Badan ad 2 47 FLASH ENABLE 2 R W n 2 48 FLASH DATA OXEF30 R W nennen REE nennen nennen 2 49 CONFIGURATION RELOAD 0 4 LIST OF TABLES TABLE 2 1 ADDRESS MAP FOR THE MODEL V1724 TABLE 2 2 ROM ADDRESS MAP FOR THE MODEL V1724 eene eee neret nennen nennen TABLE 2 3 OUTPUT BUFFER MEMORY BLOCK DIVISION nennen entente n n ente teen entente enne Filename Number of pages Page V1724_REGISTERS_REV1 DOC 23 4 CA2. Front Panel I O Control 0x811C r w Bit Function 0 I O Normal operations TRG OUT signals outside trigger 15 presence trigger are generated according to Front Panel Trigger Out Enable Mask setting see S 2 24 1 I O Test Mode TRG OUT is a logic level set via bit 14 12 TRG OUT Test Mode set to 1 0 TRG OUT Test Mode set to 0 PATTERN LATCH MODE 0 PATTERN field into event headers is the status of 16 LVDS 9 Front Panel Inputs latched with board internal trigger if a post trigger value is set the internal trigger is delayed respect to external one 1 PATTERN field into event headers is the status of 16 LVDS Front Panel Inputs latched with external trigger rising edge 00 General Purpose I O 01 Programmed I O 10 Pattern mode LVDS signals are input and their value is written into header PATTERN field 5 0 LVDS I O 15 12 are inputs 1 LVDS I O 15 12 are outputs 4 0 LVDS I O 11 8 are inputs 1 LVDS I O 11 8 are outputs 3 0 LVDS I O 7 4 are inputs 1 LVDS I O 7 4 are outputs 2 0 LVDS 1 O 3 0 are inputs 1 LVDS I O 3 0 are outputs 0 panel output signals TRG OUT CLKOUT enabled 1 1 panel output signals TRG OUT CLKOUT enabled in high impedance 0 0 TRG CLK are NIM I O Levels 1 TRG CLK are TTL I O Levels Bits 5 2 are meaningful for General Purpose I O use only 14 7 6 Filename Number of pages Page V1724_REGISTERS_REV1
3. 6 0 Trigger Output on Input Over Threshold 1 Trigger Output on Input Under Threshold allows to generate local trigger either on channel over or under threshold see 2 3 and 2 6 5 reserved 4 0 Memory Random Access 1 Memory Sequential Access 3 0 Test Pattern Generation Disabled 1 Test Pattern Generation Enabled 2 reserved 1 0 Trigger Overlapping Not Enabled 1 Trigger Overlapping Enabled Allows to handle trigger overlap 0 0 Window Gate 1 Single Shot Gate Allows to handle samples validation This register allows to perform settings which apply to all channels It is possible to perform selective set clear of the Channel Configuration register bits writing to 1 the corresponding set and clear bit at address 0x8004 set or 0x8008 clear see the following 8 2 13 and 2 14 Default value is 0x10 Channel Configuration Bit Set 0x8004 w Bit Function 7 0 Bits set to 1 means that the corresponding bits in the Channel i Configuration register are set to 1 Channel Configuration Bit Clear 0x8008 w Bit Function 7 0 Bits set to 1 means that the corresponding bits the Channel Configuration register are set to 0 Filename Number of pages V1724_REGISTERS_REV1 DOC 23 Page 12 CAEN Tools for Discovery Document type User s Manual MUT 2 15 2 16 2 17 2 1
4. Channel 0 trigger disabled 1 Channel 0 trigger enabled This register bits 0 7 enable the channels to generate a local trigger as the digitised signal exceeds the Vth threshold enables to generate the trigger bit enables Ch1 to generate the trigger and so on Bits 26 24 allows to set minimum number of channels that must be over threshold beyond the triggering channel in order to actually generate the local trigger signal for example if bit 7 0 FF all channels enabled and Local trigger coincidence level 1 whenever one channel exceeds the threshold the trigger will be generated only if at least another channel is over threshold at that moment Local trigger coincidence level must be smaller than the number of channels enabled via bit 7 0 mask EXTERNAL TRIGGER ENABLE bit30 enables the board to sense TRG IN signals SW TRIGGER ENABLE bit 31 enables the board to sense software trigger see 2 21 Filename Number of pages Page V1724_REGISTERS_REV1 DOC 23 16 CAEN Tools for Discovery Document type Title Revision date User s Manual MUT V1724 Registers Description 11 03 2015 2 23 Trigger Source Enable Mask 0x810C r w Bit Function 31 0 Software Trigger Disabled 1 Software Trigger Enabled 30 0 External Trigger Disabled 1 External Trigger Enabled 7 0 Channel 7 trigger disabled 1 Channel 7 trigger enabled 6 0 Channel 6 trigger disabled 1 Channel 6 trigger enabled
5. V1724_REGISTERS_REV1 DOC 23 22 CAEN Tools for Discovery Document type Title Revision date User s Manual MUT V1724 Registers Description 11 03 2015 2 48 Flash Data OxEF30 r w Bit Function 7 0 Data to be serialized towards the SPI On board Flash This register is handled by the Firmware upgrade tool 2 49 Configuration Reload OxEF34 w Bit Function 31 0 A write access to this register causes a software reset a reload of Configuration ROM parameters PLL reconfiguration Filename Number of pages V1724_REGISTERS_REV1 DOC 23 Page 23
6. 5 Clock source 0 Internal 1 External 4 EVENT FULL itis setto 1 as the maximum nr of events to be read is reached 3 EVENT READY it is set to 1 as at least one event is available to readout 2 0 RUN off 1 RUN 1 reserved 0 reserved 2 21 Software Trigger 0x8108 w Bit Function 81 0 A write access to this location generates a trigger via software Filename Number of pages V1724 REGISTERS REVI DOC 23 Page 15 CAEN Tools for Discovery Document type Title Revision date User s Manual MUT V1724 Registers Description 11 03 2015 2 22 Trigger Source Enable Mask 0x810C r w Bit Function 31 0 Software Trigger Disabled 1 Software Trigger Enabled 30 0 External Trigger Disabled 1 External Trigger Enabled 29 27 reserved 26 24 Local trigger coincidence level default 0 23 8 reserved 7 0 Channel 7 trigger disabled 1 Channel 7 trigger enabled 6 0 Channel 6 trigger disabled 1 Channel 6 trigger enabled 5 0 Channel 5 trigger disabled 1 Channel 5 trigger enabled 4 0 Channel 4 trigger disabled 1 Channel 4 trigger enabled 3 0 Channel 3 trigger disabled 1 Channel 3 trigger enabled 2 0 Channel 2 trigger disabled 1 Channel 2 trigger enabled 1 0 Channel 1 trigger disabled 1 Channel 1 trigger enabled 0 0
7. 5 0 Channel 5 trigger disabled 1 Channel 5 trigger enabled 141 0 Channel 4 trigger disabled 1 Channel 4 trigger enabled 3 0 Channel 3 trigger disabled 1 Channel 3 trigger enabled 2 0 Channel 2 trigger disabled 1 Channel 2 trigger enabled 1 0 Channel 1 trigger disabled 1 Channel 1 trigger enabled 0 0 Channel 0 trigger disabled 1 Channel 0 trigger enabled This register bits 0 7 enable the channels to generate a local trigger as the digitised signal exceeds the Vth threshold enables to generate the trigger biti enables Ch1 to generate the trigger and so on EXTERNAL TRIGGER ENABLE bit30 enables the board to sense TRG IN signals SW TRIGGER ENABLE bit 31 enables the board to sense software trigger see S 2 21 2 24 Front Panel Trigger Out Enable Mask 0x8110 r w Bit Function 31 0 Software Trigger Disabled 1 Software Trigger Enabled 30 0 External Trigger Disabled 1 External Trigger Enabled 7 0 Channel 7 trigger disabled 1 Channel 7 trigger enabled 6 0 Channel 6 trigger disabled 1 Channel 6 trigger enabled 5 0 Channel 5 trigger disabled 1 Channel 5 trigger enabled 141 0 Channel 4 trigger disabled 1 Channel 4 trigger enabled 3 0 Channel 3 trigger disabled 1 Channel 3 trigger enabled 2 0 Channel 2 trigger disabled 1 Channel 2 trigger enabled 1 0 Channel 1 trigger disabled 1 Channel 1
8. 8118 R W FRONT PANEL I O CONTROL 0X811C R W CHANNEL ENABLE MASK 0X8 120 R W ROC FPGA FIRMWARE REVISION 0X8124 R EVENT STORED 0X812C R SET MONITOR DAC 0x8 138 R W BOARD INFO 0X8140 R Filename V1724 REGISTERS REVI DOC 6 Revision date 11 03 2015 Number of pages Page 23 3 CAEN Tools for Discovery Document type Title Revision date User s Manual MUT V1724 Registers Description 11 03 2015 2 33 MONITOR MODE 0X8144 R W 2 34 EVENT SIZE UD 4 05 10 1 TE 2 35 ANALOG MONITOR 0X8150 R W 2 36 VME CONTROL R W c cecesssscecsscecesssnsecsecescesssssecsessnsucesnossesssnsecesssnsessensnsesseseeseessnseess 2 37 VMESTATUS XEEQO4 R ri nenn ai ala anna 2 38 BOARD ID OXEF08 R W LLL A RANADE TE Aane EAE 2 39 MCST BASE ADDRESS AND CONTROL OXEFOC R W Y 2 40 RELOCATION ADDRESS OXEF10 R W
9. DOC 23 18 CAEN Tools for Discovery Document type Title Revision date User s Manual MUT V1724 Registers Description 11 03 2015 2 28 Channel Enable Mask 0x8120 r w 2 29 2 30 2 31 2 32 Bit Function 7 0 Channel 7 disabled 12 Channel 7 enabled 0 Channel 6 disabled 6 Channel 6 enabled 5 0 Channel 5 disabled 12 Channel 5 enabled 4 0 Channel 4 disabled 1 Channel 4 enabled 3 0 Channel 3 disabled 1 Channel 3 enabled 2 0 Channel 2 disabled 1 Channel 2 enabled 1 0 1 disabled 1 Channel 1 enabled 0 0 Channel 0 disabled 1 Channel 0 enabled Enabled channels provide the samples which are stored into the events and not erased The mask cannot be changed while acquisition is running ROC FPGA Firmware Revision 0x8124 r Bit Function 31 16 Revision date in Y M DD format 15 8 Firmware Revision X 7 0 Firmware Revision Y Bits 31 16 contain the Revision date in Y M DD format Bits 15 0 contain the firmware revision number coded on 16 bit X Y format Event Stored 0x812C r Bit Function 31 0 This register contains the number of events currently stored in the Output Buffer This register value cannot exceed the maximum number of available buffers according to setting of buffer size register Set Monitor DAC 0x8138 r w Bit Functi
10. X x X Channel n 25 THRES 0 1 24 A24 A32 D32 X X Channel n Z8 NSAMP 0x1n28 A24 A32 D32 X X Channel n THRESHOLD 0x1n80 A24 A32 D32 X X Channel n TIME OVER UNDER THRESHOLD 0x1n84 A24 A32 D32 X X Channel n STATUS 0x1n88 A24 A32 D32 R X X Channel n AMC FPGA FIRMWARE REVISION Ox1n8C A24 A32 D32 R Channel n BUFFER OCCUPANCY 0x1n94 A24 A32 D32 R X X X Channel n DAC 0x1n98 A24 A32 D32 X X Channel n ADC CONFIGURATION Ox1n9C A24 A32 D32 X X CHANNEL CONFIGURATION 0x8000 A24 A32 D32 X X CHANNEL CONFIGURATION BIT SET 0x8004 A24 A32 D32 W X X CHANNEL CONFIGURATION BIT CLEAR 0x8008 A24 A32 D32 W X X BUFFER ORGANIZATION 0x800C A24 A32 D32 X X BUFFER FREE 0x8010 A24 A32 D32 X x CUSTOM SIZE 0x8020 A24 A32 D32 X X ANALOG MONITOR POLARITY AND SHIFT 0x802A A24 A32 D32 X X ACQUISITION CONTROL 0x8100 A24 A32 D32 X X ACQUISITION STATUS 0x8104 A24 A32 D32 R SW TRIGGER 0x8108 A24 A32 D32 W TRIGGER SOURCE ENABLE MASK 0x810C A24 A32 D32 X x FRONT PANEL TRIGGER OUT ENABLE MASK 0 8110 A24 A32 D32 X X POST TRIGGER SETTING 0x8114 A24 A32 D32 X x FRONT PANEL I O DATA 0x8118 A24 A32 D32 X X FRONT PANEL I O CONTROL 0x811C A24 A32 D32 X X CHANNEL ENABLE MASK 0x8120 A24 A32 D32 X X ROC FPGA FIRMWARE REVISION 0x8124 A24 A32 D32 R EVENT STORED 0x812C A24 A32 D32 R X X X SET MONITOR DAC 0x8138 A24 A32 D32 X X BOARD INFO 0x8140 A24 A32 D32 R Filename Nu
11. purchased version Board ID Board identifier Revision hardware revision identifier Serial MSB serial number MSB Serial LSB serial number LSB Table 2 2 ROM Address Map for the Model V1724 Description Address Content checksum OxF000 0 4 checksum_length2 004 0x00 checksum_lengthi 0 008 0x00 checksum_lengthO OxFOOC 0x20 constant2 OxF010 0x83 constant1 OxF014 0x84 constantO OxF018 0x01 c_code OxFO1C 0x43 r_code OxF020 0x52 oui2 OxF024 0x00 oui OxF028 0x40 ouiO OxFO2C OxE6 V1724LC 0x10 V1724 VX1724 0x11 V1724B VX1724B 0x40 V1724C VX1724C 0x12 Vers OxFO30 y 724D VX1724D 0x41 V1724E VX1724E 0x42 V1724F VX1724F 0x43 V1724G 0x44 V1724 0x00 board2 OxF034 VX1724 0x01 board1 OxF038 0x06 boardO OxFO3C OxBC revis3 OxF040 0x00 revis2 OxF044 0x00 revis1 OxF048 0x00 revisO OxFO4C 0x01 sernum1 OxF080 0x00 sernumO OxF084 0x16 These data are written into one Flash page at Power ON the Flash content is loaded into the Configuration RAM where it is available for readout Filename Number of pages Page V1724_REGISTERS_REV1 DOC 23 9 CAEN Tools for Discovery Document type User s Manual MUT 2 3 2 4 2 5 2 6 Title Revision date V1724 Registers Description 11 03 2015 Channel n ZS_THRES 0x1n24 r w Bit Func
12. trigger enabled 0 0 Channel 0 trigger disabled 1 Channel 0 trigger enabled This register bits 0 7 enable the channels to generate a TRG_OUT front panel signal as the digitised signal exceeds the Vth threshold BitO enables to generate the TRG_OUT biti enables Ch1 to generate the TRG_OUT and so on EXTERNAL TRIGGER ENABLE bit30 enables the board to generate the TRG_OUT SW TRIGGER ENABLE bit 31 enables the board to generate TRG_OUT see 2 21 Filename Number of pages Page V1724_REGISTERS_REV1 DOC 23 17 CAEN Tools for Discovery Document type Title Revision date User s Manual MUT V1724 Registers Description 11 03 2015 2 25 Post Trigger Setting 0x8114 r w 2 26 2 27 Bit Function 31 0 Post trigger value The register value sets the number of post trigger samples The number of post trigger samples is Npost PostTriggerValue 2 ConstantLatency where Npost number of post trigger samples PostTriggerValue Content of this register ConstantLatency constant number of samples added due to the latency associated to the trigger processing logic in the ROC FPGA This value is constant but the exact value may change between different firmware revisions Front Panel I O Data 0x8118 r w Bit Function 15 0 Front Panel I O Data Allows to Readout the logic level of LVDS I Os and set the logic level of LVDS Outputs
13. 8 Title V1724 Registers Description Revision date 11 03 2015 Buffer Organization 0x800C r w Bit Function 3 0 BUFFER CODE The BUFFER CODE allows to divide the available Output Buffer Memory into a certain number of blocks according to the following table Table 2 3 Output Buffer Memory block division CODE Nr of blocks Mem Locations max Block size Samples block max 0000 1 262144 1024K 512K 0001 2 131072 512K 256K 0010 4 65536 256K 128K 0011 8 32768 128K 64K 0100 16 16384 64K 32K 0101 32 8192 32K 16K 0110 64 4096 16K 8K 0111 128 2048 8K 4K 1000 256 1024 4K 2K 1001 512 512 2K 1K 1010 1024 256 1K 512 A write access to this register causes a Software Clear This register must not be written while acquisition is running The number of Memory Locations depends on Custom size register setting see 2 17 Buffer Free 0x8010 r w Bit Function 11 0 N Frees the first N Output Buffer Memory Blocks Custom Size 0x8020 r w Bit Function 0 Custom Size disabled 31 0 Nioc 0 Number of memory locations per event 1 location 2 samples This register must not be written while acquisition is running Analog Monitor Polarity and Shift 0x802A r w Bit Function 3 1 This field allows to shift the signal in order to obtain the 8 bit of the Chx DATA field o
14. EN Tools for Discovery Document type Title Revision date User s Manual MUT V1724 Registers Description 11 03 2015 1 Important Notices The content of this document has been extracted from V1724 amp VX1724 User Manual Revision N 28 Date 06 February 2012 FOR RELEASES OF THE ROC FPGA FIRMWARE HIGHER THAN 3 8 THE CONTENT OF THIS DOCUMENT MAY RESULT NOT FULLY COMPLIANT IT IS INTENDED TO BE REPLACED BY A NEW DOCUMENT UNIFYING THE REGISTERS DESCRIPTIONS OF CAEN DIGITIZERS CURRENTLY IN PROGRESS Filename Number of pages Page V1724 REGISTERS REVI DOC 23 5 CAEN Tools for Discovery Document type Title Revision date User s Manual MUT V1724 Registers Description 11 03 2015 2 VME Interface The following sections will describe in detail the board s VME accessible registers content AN N B bit fields that are not described in the register bit map are reserved and must not be over written by the User Filename Number of pages Page V1724 REGISTERS REVI DOC 23 6 CAEN Tools for Discovery Document type Title Revision date User s Manual MUT V1724 Registers Description 11 03 2015 2 1 Registers address map Table 2 1 Address Map for the Model V1724 REGISTER NAME ADDRESS ASIZE DSIZE MODE RES S RES CLR EVENT READOUT BUFFER 0x0000 0xOFFC A24 A32 A64 D82
15. V1724 Registers Description 11 March 2015 MOD V1724 8 CHANNEL 14 BIT 100 MS S DIGITIZER CAEN will repair or replace any product within the guarantee period if the Guarantor declares that the product is defective due to workmanship or materials and has not been caused by mishandling negligence on behalf of the User accident or any abnormal conditions or operations CAEN declines all responsibility for damages or injuries caused by an improper use of the Modules due to negligence on behalf of the User It is strongly recommended to read thoroughly the CAEN User s Manual before any kind of operation CAEN reserves the right to change partially or entirely the contents of this Manual at any time and without giving any notice Disposal of the Product The product must never be dumped in the Municipal Waste Please check your local regulations for disposal of electronics products MADE IN ITALY We stress the fact that all the boards are made in Italy because in this globalized world where getting the lowest possible price for products sometimes translates into poor pay and working conditions for the people who make them at least you know that who made your board was reasonably paid and worked in a safe environment this obviously applies only to the boards marked MADE IN ITALY we can not attest to the manufacturing process of third party boards CAEN Tools for Discovery Document type Title User s Man
16. annel 1 disabled 12 Channel 1 enabled 0 0 Channel 0 disabled 12 Channel 0 enabled 2 36 VME Control r w Bit Function 7 0 Release On Register Access RORA Interrupt mode default 1 Release On AcKnowledge ROAK Interrupt mode 6 0 RELOC Disabled BA is selected via Rotary Switch 1 RELOC Enabled BA is selected via RELOC register see 2 40 5 0 ALIGN64 Disabled 1 ALIGN64 Enabled 4 0 BERR Not Enabled the module sends a DTACK signal until the Filename Number of pages Page V1724_REGISTERS_REV1 DOC 23 20 CAEN Tools for Discovery Document type Title Revision date User s Manual MUT V1724 Registers Description 11 03 2015 2 37 2 38 2 39 CPU inquires the module 1 BERR Enabled the module is enabled either to generate a Bus error to finish a block transfer or during the empty buffer read out in D32 3 Optical Link interrupt disabled 1 Optical Link interrupt enabled 2 0 Interrupt level 02 interrupt disabled Bit 7 this setting is valid only for interrupts broadcasted on VMEbus interrupts broadcasted on optical link feature RORA mode only n RORA mode interrupt status can be removed by accessing VME Control register see 2 36 and disabling the active interrupt level n ROAK mode interrupt status is automatically removed via an interrupt acknowledge cycle Interrupt generation is restored by setti
17. elocation Address OxEF10 r w Bit Function These bits contains the A31 A16 bits of the address of the module 15 0 it can be set via VME for a relocation of the Base Address of the module 2 41 Interrupt Status ID OxEF14 r w Bit Function 81 0 This register contains the STATUS ID that the module places on the VME data bus during the Interrupt Acknowledge cycle 2 42 Interrupt Event Number OxEF18 Bit Function 9 0 INTERRUPT EVENT NUMBER If interrupts are enabled the module generates a request whenever it has stored in memory a Number of events gt INTERRUPT EVENT NUMBER 2 43 BLT Event Number OxEF1C r w Bit Function 7 0 This register contains the number of complete events which has to be transferred via BLT CBLT 2 44 Scratch OxEF20 r w Bit Function 31 0 Scratch to be used to write read words for VME test purposes 2 45 Software Reset OxEF24 w Bit Function 31 0 A write access to this location allows to perform a software reset 2 46 Software Clear OxEF28 w Bit Function 31 0 A write access to this location clears all the memories 2 47 Flash Enable OxEF2C r w Bit Function 0 0 Flash write ENABLED 1 Flash write DISABLED This register is handled by the Firmware upgrade tool Filename Number of pages Page
18. evision date in Y M DD format 15 8 Firmware Revision X 7 0 Firmware Revision Y Bits 31 16 contain the Revision date in Y M DD format Bits 15 0 contain the firmware revision number coded on 16 bit X Y format Example revision 1 3 of 12 June 2007 is 0x760C0103 2 9 Channel n Buffer Occupancy 0 1 94 Bit Function 10 0 Occupied buffers 0 1024 2 10 Channel n DAC 0x1n98 r w Bit Function 15 0 DAC Data Bits 15 0 allow to define a DC offset to be added the input signal in the 1 125V 1 125V range low range or in the 1V 8V range high range When Channel n Status bit 2 is set to 0 DC offset is updated see 2 7 2 11 Channel n ADC Configuration 0x1n9C r w Bit Function 31 0 Reserved Filename Number of pages Page V1724 REGISTERS REVI DOC 23 11 CAEN Tools for Discovery Document type User s Manual MUT 2 12 2 13 2 14 Title Revision date V1724 Registers Description 11 03 2015 Channel Configuration 0x8000 r w Bit Function 19 16 Allows to select Zero Suppression algorithm 0000 no zero suppression default 0001 full suppression based on the integral ZS INT 0010 zero length encoding ZLE 0011 full suppression based on the amplitude ZS AMP 15 8 reserved 7 0 Analog monitor disabled 1 Analog monitor enabled
19. f Run take place on SW command that is by setting resetting bit 2 01 S IN CONTROLLED MODE If the acquisition is armed i e bit 2 1 then Run starts when S IN is asserted and stops when S IN returns inactive If bit 2 0 the acquisition is always off 10 FIRST TRIGGER CONTROLLED MODE If the acquisition is armed i e bit 2 1 then Run starts on the first trigger pulse rising edge on TRG IN this pulse is not used as trigger actual triggers start from the second pulse The stop of Run must be SW controlled i e bit 2 0 11 2 GPIO CONTROLLED MODE Like 01 but using GPIO RUN instead of S IN 5 Filename Number of pages Page V1724 REGISTERS REVI DOC 23 14 CAEN Tools for Discovery Document type Title Revision date User s Manual MUT V1724 Registers Description 11 03 2015 2 20 Acquisition Status 0x8104 r Bit Function 8 Board ready for acquisition PLL and ADCs are synchronised correctly 0 not ready 1 ready This bit should be checked after software reset to ensure that the board will enter immediatly run mode after RUN mode setting otherwise a latency between RUN mode setting and Acquisition start might occur 7 PLL Status Flag 0 PLL loss of lock 1 2 no PLL loss of lock NOTE flag can be restored to 1 via read access to Status Register see 2 37 6 PLL Bypass mode 0 No bypass mode 1 Bypass mode
20. hreshold Channel n Threshold 0x1n80 r w Bit Function 13 0 Threshold Value for Trigger Generation Each channel can generate a local trigger as the digitised signal exceeds the Vth threshold and remains under or over threshold for Nth couples of samples at least local trigger is delayed of Nth quartets of samples with respect to input signal This register allows to set Vth LSB input range 14bit Channel n Over Under Threshold 0x1n84 r w Bit Function 11 0 Number of Data under over Threshold Each channel can generate a local trigger as the digitised signal exceeds the Vth threshold and remains under or over threshold for Nth quartets of samples at least local trigger is delayed of Nth quartets with respect to input signal This register allows to set Number of samples under or over threshold Nth 4 Filename Number of pages V1724 REGISTERS REVI DOC 23 Page 10 CAEN Tools for Discovery Document type Title Revision date User s Manual MUT V1724 Registers Description 11 03 2015 2 7 Channel Status 0x1n88 Bit Function 5 Buffer free error 1 trying to free a number of buffers too large 4 3 reserved Channel n DAC see 2 10 Busy 2 1 Busy 0 DC offset updated 1 Memory empty 0 Memory full 2 8 Channel n AMC FPGA Firmware 0x1n8C r Bit Function 31 16 R
21. mber of pages Page V1724_REGISTERS_REV1 DOC 23 7 CAEN Tools for Discovery Document type Title Revision date User s Manual MUT V1724 Registers Description 11 03 2015 REGISTER NAME ADDRESS ASIZE DSIZE MODE RES S RES CLR MONITOR MODE 0x8144 A24 A32 D32 X EVENT SIZE 0x814C A24 A32 D32 R X X ANALOG MONITOR 0x8150 A24 A32 D32 X VME CONTROL OxEFOO A24 A32 D32 X VME STATUS OxEF04 A24 A32 D32 R BOARD ID OxEFO08 A24 A32 D32 X MULTICAST BASE ADDRESS amp CONTROL OxEFOC A24 A32 D32 X RELOCATION ADDRESS OxEF10 A24 A32 D32 X INTERRUPT STATUS ID OxEF14 A24 A32 D32 X INTERRUPT EVENT NUMBER OxEF18 A24 A32 D32 X BLT EVENT NUMBER OxEF1C A24 A32 D32 X SCRATCH OxEF20 A24 A32 D32 X SW RESET OxEF24 A24 A32 D32 W SW CLEAR OxEF28 A24 A32 D32 W FLASH ENABLE OxEF2C A24 A32 D32 X FLASH DATA OxEF30 A24 A32 D32 X CONFIGURATION RELOAD OxEF34 A24 A32 D32 W CONFIGURATION ROM 0xF000 0xF3FC A24 A32 D32 R Filename V1724_REGISTERS_REV1 DOC Number of pages 23 Page 8 CAEN Tools for Discovery Document type Title Revision date User s Manual MUT V1724 Registers Description 11 03 2015 2 2 Configuration ROM 0xF000 0xF084 r The following registers contain some module s information D32 accessible read only OUI manufacturer identifier IEEE OUI Version
22. ng an Interrupt level gt 0 via VME Control register VME Status Bit Function 0 BERR FLAG no Bus Error has occurred 2 1 BERR FLAG a Bus Error has occurred this bit is re set after a status register read out 1 Reserved 0 0 No Data Ready 1 Event Ready Board ID OxEF08 r w Bit Function 4 0 GEO VME64X versions this register can be accessed in read mode only and contains the GEO address of the module picked from the backplane connectors when CBLT is performed the GEO address will be contained in the EVENT HEADER Board ID field Other versions this register can be accessed both in read and write mode it allows to write the correct GEO address default setting 0 of the module before CBLT operation GEO address will be contained in the EVENT HEADER Board ID field MCST Base Address and Control OXEFOC r w Bit Function Allows to set up the board for daisy chaining 00 disabled board 9 8 01 last board 10 first board 11 intermediate These bits contain the most significant bits of the MCST CBLT 7 0 address of the module set via VME i e the address used in MCST CBLT operations Filename Number of pages Page V1724_REGISTERS_REV1 DOC 23 21 CAEN Tools for Discovery Document type Title Revision date User s Manual MUT V1724 Registers Description 11 03 2015 2 40 R
23. on 11 0 This register allows to set the DAC value 12bit This register allows to set the DAC value in Voltage level mode LSB 0 244 mV terminated on 50 Ohm Board Info 0x8140 r Bit Function 15 8 Memory size Mbyte channel Board Type 7 0 0 V1724 Filename Number of pages Page V1724_REGISTERS_REV1 DOC 23 19 CAEN Tools for Discovery Document type Title Revision date User s Manual MUT V1724 Registers Description 11 03 2015 2 33 Monitor Mode 0x8144 r w Bit Function This register allows to encode the Analog Monitor operation 000 Trigger Majority Mode 001 Test Mode 010 Analog Monitor Inspection Mode 011 Buffer Occupancy Mode 100 Voltage Level Mode 2 0 2 34 Event Size 0x814C r Bit Function 31 0 Nr of 32 bit words in the next event 2 35 Analog Monitor 0x8150 r w Bit Function Analog Inspection inverter 31 0 1 1X Magnify factor 00 1x 21 20 01 2x 10 4x 11 8x 19 Offset sign O positive 1 negative 18 8 Offset Value 7 0 Channel 7 disabled 1 Channel 7 enabled 0 Channel 6 disabled 6 4 Channel 6 enabled 5 0 Channel 5 disabled 12 Channel 5 enabled 4 0 Channel 4 disabled 1 Channel 4 enabled 5 0 Channel 3 disabled 12 Channel 3 enabled 2 0 Channel 2 disabled 12 Channel 2 enabled 1 0 Ch
24. tion 31 0 Positive Logic 1 Negative Logic 30 Threshold Weight used in Full Suppression based on the integral only 0 Fine threshold step Threshold Z8 THRES 29 0 1 Coarse threshold step Threshold Z8 THRES 29 0 64 29 0 With Full Suppression based on the integral the 30 LSB value represents the value depending on bit 30 to be compared with sum of the samples which compose the event and see if it is over under threshold depending on the used logic With Full Suppression based on the amplitude the 14 LSB represent the value to be compared with each sample of the event and see if it is over unedr threshold depending on the used logic With Zero Length Encoding the 14 LSB represent the value to be compared with each sample of the event and see if it is good or skip type Channel n 25 NSAMP 0x1n28 r w Bit Function 81 0 With Full Suppression based on the amplitude ZS AMP bits 20 0 allow to set the number Ns of subsequent samples which must be found over under threshold depending on the used logic necessary to validate the event if this field is set to 0 it is considered 1 With Zero length encoding ZLE bit 31 16 allows to set read the number of data to be stored before the signal crosses the threshold bit 15 0 allows to set read N rwo the number of data to be stored after the signal crosses the t
25. ual MUT V1724 Registers Description TABLE OF CONTENTS 1 IMPORTANT NOTICES 2 VMEINTERFACE 2 1 2 2 2 3 24 2 5 2 6 2 7 2 8 219 2 10 2 11 2 12 2 13 2 14 2 15 2 16 2 17 2 18 2 19 2 20 2 21 2 22 2 23 2 24 2 25 2 26 2 27 2 28 2 29 2 30 2 31 2 32 REGISTERS ADDRESS MAP eee CONFIGURATION ROM 0XF000 0XF084 R CHANNEL N ZS THRES 0X1N24 R W CHANNEL N ZS NSAMP 0X1N28 R W CHANNEL N THRESHOLD 0X1N80 R W CHANNEL N OVER UNDER THRESHOLD 0X1N84 R W CHANNEL N STATUS OX1N88 R CHANNEL N AMC FPGA FIRMWARE 0X1N8C CHANNEL N BUFFER OCCUPANCY 0 194 R CHANNEL N DAC 0X1N98 R AW CHANNEL N ADC CONFIGURATION 0X1N9C R W CHANNEL CONFIGURATION 0X8000 R W CHANNEL CONFIGURATION BIT SET 0 8004 CHANNEL CONFIGURATION BIT CLEAR 0 8008 W BUFFER ORGANIZATION 0X800C R W BUFFER FREE 0X8010 R W CUSTOM SIZE 0X8020 R W ANALOG MONITOR POLARITY AND SHIFT 0 802 R W ACQUISITION CONTROL 0X8100 R W ACQUISITION STATUS OX8104 R SOFTWARE TRIGGER 0X8108 W TRIGGER SOURCE ENABLE MASK 0X8 10C R w TRIGGER SOURCE ENABLE MASK 0X810C R w FRONT PANEL TRIGGER OUT ENABLE MASK 0X8110 R w POST TRIGGER SETTING 0X8114 R W FRONT PANEL I O DATA
26. ut of the 14 bit converted sample Default value is 6 in this case Chx DATA represents the 8 MSB of the 14 bit converted sample If this field is 0 Chx DATA represents the 8 LSB of the 14 bit converted sample If the 8 selected bits are all 0 the transferred Chx DATA is 0 0 signal not inverted default value 1 signal inverted Filename V1724_REGISTERS_REV1 DOC 23 Number of pages CAEN Tools for Discovery Document type Title Revision date User s Manual MUT V1724 Registers Description 11 03 2015 2 19 Acquisition Control 0x8100 r w Bit Function 0 Normal Mode default board becomes full whenever all buffers are full 1 Always keep one buffer free board becomes full whenever N 1buffers are full N of blocks 4 reserved 0 COUNT ACCEPTED TRIGGERS 3 1 COUNT ALL TRIGGERS allows to reject overlapping triggers 0 Acquisition STOP 2 1 Acquisition RUN allows to RUN STOP Acquisition Start Stop Mode 00 REGISTER CONTROLLED 1 0 01 S IN CONTROLLED 10 FIRST TRIGGER CONTROLLED 11 GPIO CONTROLLED Bit 2 allows to Run and Stop data acquisition when such bit is set to 1 the board enters Run mode and a Memory Reset is automatically performed When bit 2 is reset to 0 the stored data are kept available for readout In Stop Mode all triggers are neglected Bits 1 0 descritpion 00 REGISTER CONTROLLED MODE default Sart and Stop o
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