SMT351 User Manual
Contents
1. For more information about 3L Diamond please refer the 3L website Synthesis and Implementation tool The design is implemented using Xilinx ISE 8 2 SP2 Synthesiser used is XST FPGA resource usage Follow is the device utilization summary after Place and Route Resource XC2VP7 Number of 70 278 396 External lOBs Number of 40 18 44 RAMB16s Number of 82 4081 4928 SLICEs Number of 50 8 16 BUFGMUXs Number of 50 2 4 DCMs Power PC 0 1 1 Registers definition The SMT351 is configured via a set of 16 bits registers described in this section Control register 0x4 15 3 2 1 0 RST_INPUT RDBKEN START R W 0 R W 0 R W 0 Description flags are active when 1 START Writing 1 and then 0 to this bit will start the storage of the data RDBKEN Read back enable When this bit is set read back of memory is enabled and SMT351 starts outputting data RST_INPUT f When this bit is set to 1 the data are cleared from the input buffer Address register Low order 16 bits 0x5 Write in this register the low 16 bits of address at which you want to start the cycle 15 0 Low order 16 bits of the address R W 0 Address register High order 16 bits 0x6 Write in this register the high 16 bits of address at which you want to start the cycle 15 0 High order 16 bits of the address R W 0 Count register Low order 16 b2. available in output SMT351 modules can be cascaded to extend storage capability The module is based on DDR SDRAM memory components running at up to 133 MHz DDR Double Data Rate SDRAM activates the data outputs on both the rising and falling edges of the system clock rather than on just the rising edge potentially doubling the output A Xilinx Virtex ll Pro FPGA or XC2VP20 or XC2VP30 controls input and output data flows on two Sundance High speed Bus SHB connectors This bus is compatible with a wide range of Sundance processor converter and I O modules Features 2 x Sundance High speed Bus SHB connectors 6 x comport connectors Xilinx Virtexll Pro FPGA XC2VP7 or XC2VP20 or XC2VP30 1GB Double Data Rate DDR SDRAM 133 MHz Additional resources SUNDANCE SHB specification TI TIM specification amp user s guide Samtec QSH Catalogue page Micron DDR SDRAM webpage Certificate Number FM 55022 Version 1 6 Page 8 of 25 SMT351 User Manual Architecture description SMT351 block diagram Figure 1 shows a block diagram of the SMT351 board Refer to the following section for additional information on the major blocks J1 Top Primary TIM Ri Connector 4 2x ComPorts SDLs LEDs External 5 Volt Power Supply FPGA configured converted to LED 2 5 Volts by
3. capability e SMT351 G provides 1GB storage capability CPLD A Xilinx CPLD is used to manage configuring the FPGA It connects to the six comports available on the module Sundance High Speed Bus Two SHB connectors are available on the SMT351 Unidirectional 32 bit SHB interfaces are implemented on SHB connectors They run at 100 MHz giving a 400MB s data rate thru the SMT351 SHB A implements a receiver only interface while SHB B implements a transmitter only interface Please refer to the SUNDANCE SHB specification for more details Comports The SMT351 provides up to 6 comports which are used to receive the configuration bitstream and commands to the FPGA Once configured the SMT351 is controlled via comport 3 The number of comports provided depends on the type of FPGA fitted on the board e XC2VP7 provides 3 comports 0 1 and 3 e XC2VP20 or XC2VP30s provides 6 comports Version 1 6 Page 10 of 25 SMT351 User Manual TTL I Os Four TTL I Os supporting LVTTL signals are connected directly to the FPGA JP2 These I Os are not used by Sundance firmware and are available for customer use You must ensure that any lines you connect to these pins are LVTTL compatible in order to protect the FPGA pads as lines are not clamped See JP2 pinout section for more details LEDs Five LEDs are available on the board They are all driven by the FPGA Table 1 LED description LED Descripti
4. 26 in configuration CPLD ELLE too or Or tor tor e Se Pe DE 00200303 1270 35 to ro too to LL ee ee o RSL Virtexll PRO Figure 6 SMT351 connector locations O Indicates pin 1 of connector LEDs dc Bee o SEN AFHIL skille le ojo Li ON Li es kd d sie N e gt gt Li e o Bee WM e Se Dale D3 e FONE ENE e ae EE e e EEN EES 0 mr aal Soe D Cos Y UKAS QUALITY MANAGEMENT Certificate Number FM 55022 Version 1 6 Page 23 of 25 SMT351 User Manual JP2 pinout The following diagram shows JP2 s pinout JP2 TTL I Os Figure 7 TTL I Os JP2 pinout A square is drawn around pin 1 on PCB to indicate its location Represented on figure 5 in connectors location section The following table shows JP2 mapping to the FPGA Signal name FPGA pin number TTLO AC10 TTL1 AD10 TTL2 AC11 TTL3 AD11 Version 1 6 Page 24 of 25 SMT351 User Manual JP1 pinout JTAG Header Figure 8 JTAG header JP1 pinout Signal name Connector pin number VCC TMS TCK TDI TDO OOP N GND A square is drawn around pin 1 on PCB to indicate its location Represented on figure 5 in connectors location section Versi
5. ANCE SHB specification for more details The SHB interfaces implemented in SMT351 are unidirectional full word 32 bits SHB A is a receiver only interface and SHB B is a transmitter only interface both are clocked at 100 MHz giving a maximum data rate of 400 MB s Registers Command words can be sent over comport 3 to control the SMT351 Words received will be written into registers in the FPGA See Registers definition section for more details Version 1 6 Page 17 of 25 SMT351 User Manual Clock structure This section describes the various clock domains in the FPGA The figure below shows the four clock domains of the SMT351 design and their interrelation Control Y Com Registers words Port 9 Memory compartment 0 Output SHB IK gt e MBytes Figure 5 FPGA s clock domains Table 4 FPGA s clock domains description Clock domain Colour Frequency Description ComPort EE 50 MHz Comport and registers clock Data input EQU lt 100 MHz SHB A clock Data output LS 100 MHz SHB B clock DDR SDRAM LS 100 MHz DDR SDRAM clock Version 1 6 Page 18 of 25 SMT351 User Manual FPGA implementation This section gives some technical details about the FPGA firmware Language The FPGA is fully designed in VHDL 3L Diamond The FPGA of the SMT351 is designed with 3L Diamond FPGA All examples provided are designed using Diamond
6. FIG Table 3 TIM CONFIG feature SW1 settings TIM CONFIG Switch number 4 Enabled ON Disabled OFF Once a DSP application has been loaded CONFIG can be driven the following way include SMI3xx h define CONFIG BIT 1 lt lt 6 int main CONFIG UINT32 CONFIG BIT timer_delay 100 CONFIG CONFIG_BIT timer_delay 100 Version 1 6 Page 14 of 25 SMT351 User Manual Functional description This section describes the functional architecture of the SMT351 programmed with the release 2 of the firmware This applies only to the boards shipped after the 01 08 06 The boards shipped before the 01 08 06 use the release 1 of the firmware and you should refer to version 1 3 of the user manual To upgrade from version 1 to version 2 please contact Sundance FPGA design overview The following diagram shows the data path implemented in the FPGA of the SMT351 Control N Com e words port Registers Memory compartment 0 d 400 ae 400 MBytes SHB Mux SE MByes Memory gt compartment 1 Figure 2 SMT351 FPGA data flow Data input on SHB A are stored into memory and then sent to SHB B Memory is organised in two independent compartments compartments O and compartments 1 Both compartments are accessed at the same time
7. SMT351 User Manual Certificate Number FM 55022 Version 1 6 Page 2 of 25 SMT351 User Manual Revision History Date Comments Engineer Version 28 07 04 First revision JPA 1 1 16 09 04 Added pin number for JP1 pinout section Updated connectors location section 30 09 04 Updated software library section 01 06 05 Added annexe 1 Removed Sundance logo 18 07 06 General update for release 2 of the firmware 08 09 06 Minor changes added for the release of the JPA 1 firmware for the SMT351 G Version 1 6 Page 3 of 25 SMT351 User Manual Table of Contents ReVision A Ee ee ee ee ee ed ee ee aE 2 Table of COMERS EE 3 ott ee eie 1 Ar N TA 7 BIS ee lei RO N i a A E EE oe 7 REM RE OE OE RR RE RE EE 7 Addiional tESQUICES ENDER DE EE RD SR Ee eek ED ee Eg ed 7 Architecture descripta da 8 MTS Bee dao Mi da 8 Geet 9 EPA AR EE EA EE EG 9 ue ss ie AR RD SR So 9 EE A a 9 Sundance High Speed BUS dicas 9 E elt ee 9 EE 10 RE 10 JIAO eege eege 10 EE 10 Using the SMT351 ee 11 PEGA Rer le UE e 12 EE 13 Functional DOSCUDION ceci rotos 14 FPGA design Oovenlew EEN 14 Memory compatmentS EE 15 Sundance High Speed Bus SHB ccc ce vsgec ce EER ESEG KEER EE ess EE GEE GEE ters KS EE oe 16 Registers ER ARE ated os 16 Glorek E EE 17 FPGA impl mentation EE 18 e UE Te 18 SUSHI E 18 Synthesis and Implementation oo 18 Version 1 6 Page 4 of 25 SMT351 User Manual PRGA resource Usage EE 18 Registers de
8. a DC DC converter On board Oscillator 50 MHz N D D 4 LEDs 4 TTL IOs i y 40 UO pins D 128 256 Mbytes DDR Clock Feedbac RAM MT46V16M16 2 x Sundance High speed 1 e y Bus Connectors Xilinx FPGA 40 UO pins D 128 256 Mbytes DDR Virtexll Pro FF896 Clock Feedbac RAM MT46V16M16 XC2VP7 20 30 40 VO pins D 128 256 Mbytes DDR 2x RSL Connectors 1 5V Core Clock Feedbac RAM MT46V16M16 8 RSL Interfaces 2 5 3 3V VO A 4017 0 pins D 128 256 Mbytes DDR FPGA Clock Feedbac RAM MT46V16M16 configuration via i lt one of six comports 6 pin JTAG header J2 Bottom Secondary TIM Connector 4x ComPorts SDLs Figure 1 SMT351 board block diagram Version 1 6 Page 9 of 25 SMT351 User Manual Block description This section describes the major blocks of the SMT351 board FPGA The SMT351 board uses a Xilinx Virtex Il Pro XC2VP7 XC2VP20 or XC2VP30 to control the data flow between the SMT351 board and external devices The FPGA is also used to implement the SHB comport and DDR SDRAM interfaces The FPGA is configured via a 6 pin JTAG header or from a user selectable Comport Memory The SMT351 board contains sixteen 133 MHz DDR SDRAM components from Micron or Samsung that provide up to 1 GB of storage capacity The DDR SDRAM is a high speed CMOS dynamic random access memory Two versions of the SMT351 exist e SMT351 M provides 512MB storage
9. am down the comport selected by SW1 The Sundance library for the SMT351 includes a function to configure the FPGA in this way The table below gives the possible settings for SW1 Table 2 configuration comport selection Comport Switch Switch Switch Switch number number 1 number 2 number 3 number 4 0 ON ON ON X 1 ON ON OFF X 2 ON OFF ON X 3 OFF OFF OFF X 4 OFF ON ON X 5 OFF ON OFF X X irrelevant The factory setting selects comport 3 to configure the FPGA At power up the FPGA is not configured LED D1 will be lit upon FPGA configuration Certificate Number FM 55022 Version 1 6 Page 13 of 25 SMT351 User Manual Reset The SMT351 is reset by the TIM global reset There is also a TIM CONFIG signal provided on the TIM connector J4 pin 74 This provides a means of reprogramming the FPGA without having to drive the TIM Global Reset signal CONFIG falling will reset the SMT351 in the same way that a TIM global Reset pulse will Other modules in the system that are sensitive to the TIM global Reset signal will not be affected by CONFIG CONFIG is driven from another TIM site on the carrier board for instance from a DSP module running an application See General Firmware Description for information on the DSP TIM CONFIG signal After a Global Reset pulse a DSP module drives CONFIG low and keeps it low by default Setting SW1 switch number 2 will enable or disable TIM CON
10. finition EE 19 Control register 0X4 EE 19 Address register Low order 16 bits 0X5 ee ee 19 Address register High order 16 bits OX6 ee 19 Count register Low order 16 bitS Ox h ee Re ee ee 19 Count register High order 16 bits xp 20 Repeat register OXD ranas 20 Application examples is EE ii ESE io o 21 Connector e EDE AAA E EE a 22 adel ea RE EE dd 23 EA lee ei EE EE EE N EE EE Ge DE ete 24 Physical iere 25 Version 1 6 Page 5 of 25 SMT351 User Manual Table of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 SMT351 board block diagram ooooooococccccncccconononananccnnnnncnonnnnnnnnnnnnnnnnnnnnnnnnnns 8 SMT351 FPGA data HOW eed ee ee ee ee Ge ee Re de 14 e RES state machine EE EE a Eg 15 DDR SDRAM components compartments organization ee 16 FPGA s clock domains EES DR GR Ee EE RE Ee 17 SMT351 Reegele ee 22 TTEVPOS TE ee EE 23 JTAG header UPA e ne EE 24 Tables of Tables Table 1 LED description BEEN 10 Table 2 configuration comport selection RR ee ee ee 12 Table 3 TIM CONFIG feature SW1 settings ese ee ee RR ee Re ee ee 13 Table 4 FPGA s clock domains description sees Re ee ee ee 17 Certificate Number FM 55022 Introduction Description The SMT351 card is a TIM format memory module that is able to store up to 1GB of data at 400MB s The module works in a similar way than a FIFO memory The first data stored into module will be
11. its 0x7 Write in this register the low 16 bits of total number of 32 bits words you want to store Certificate Number FM 55022 Version 1 6 Page 20 of 25 SMT351 User Manual 15 0 High order 16 bits of the word count R W 0 Count register High order 16 bits 0x8 Write in this register the high 16 bits of total number of 32 bits words you want to store 15 0 High order 16 bits of the word count R W 0 Memory register O and memory register 1 are used to configure the SMT351 to store different amount of data Repeat register 0x9 This value stored in this register represent the number of store read cycles the SMT351 will execute This is typically used when two or more SMT351 are cascaded 15 0 Repeat value R W 0 Application example SMT351 comes with an example that illustrates the basic functions of the board This example is developed under 3L Diamond DSP and 3L Diamond FPGA A version of the example using only Diamond DSP is also provided The example shows how you can configure the board to store various amounts of data Certificate Number FM 55022 Connector Locations Power module SHB RSL JTAG TTL lOs SMT351 c12003 Multiprocessor Technology Limited KI O Sundance E E A tors ree rorr o 0 D ani pe f 2R 9 Banu 11 69 x 8
12. on D1 FPGA Done pin The LED is on when FPAG is NOT configured D2 Unused D3 Image of DDR SDRAM clock board heart beat D4 Unused D5 Unused JTAG The SMT351 includes a 6 pin JTAG header 2mm DIL header which allows re programming the FPGA using a cable such as Xilinx Parallel Ill or Parallel IV cables See connector location section for its location on board Refer to the following section for the pinout of this connector Switch SMT351 provides two switches SW1 and SW2 SW1 is connected to CPLD and SW2 is connected to FPGA SW2 is unused by the default firmware Version 1 6 Page 11 of 25 SMT351 User Manual Using the SMT351 We refer in the rest on this document to the SMT351 G For the SMT351 M please read 512MB instead of 1GB The SMT351 can store up to 1 GB of data in memory User selects the amount of memory to store and read back by writing in the registers of the board Following are described the main features that user should keep in mind when using SMT351 The SMT351 can store from 32 bytes to 1GBytes or 512 Mbytes depending on the type of SMT351 used The total amount of data stored must be a multiple of 32 bytes SMT351 will start outputting data after half of the total amount of data to store will have been provided to it FPGA Configuration There are two ways to configure the FPGA 1 Use the on board JTAG header and Xilinx JTAG programming tools 2 Send the configuration bitstre
13. on 1 6 Page 25 of 25 Physical Properties SMT351 User Manual Dimensions Weight Supply Voltages Supply Current 12V 5V 3 3V 5V 12V MTBF
14. so that data can be stored in one compartments while data are being read back from the other This mechanism allows a continuous data rate of 400MB s This mechanism continues repeat times where repeat is set by the user in the Repeat register Version 1 6 Page 15 of 25 SMT351 User Manual Start command Repeat 0 comp 0 End of read in bankA and end of write in bankB End of write Write comp 0 comp 1 Figure 3 SMT351 state machine Memory compartments This section describes the details of the memory compartments The following diagram shows how the DDR SDRAM components are organized within a memory compartment Version 1 6 Page 16 of 25 n Fo S jo EI 9 N be gt Si Ko a w w ke ho 9 9 z S O O Er Ss S N ei ei ESS KS DDR SDRAM DDR SDRAM 32 Meg x 16 bits 32 Meg x 16 bits Chip Enable 2 Chip Enable 0 Chip Enable 3 Chip Enable 1 A Figure 4 DDR SDRAM components compartments organization One compartments is made from eight 32M x 16 bits DDR SDRAM components each of them having a 16 bit data bus Memory components are accessed in pairs Sundance High Speed Bus SHB SMT351 User Manual Data are input and output from SMT351 using the SHB protocol See SUND
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