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User`s Manual - Emulation Technology Inc.

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2. o 9 e X1 wn 8 HH h FB2 z 1 11111111 5 11111111 es Wii 22 az mm FBS e o um o mm z E o o um e P 6 9 ul 76 25 336 2 06 Figure 3 3 ET5000k10S Dimensions the PCI Specification The pull up is 1M which should not adversely impact PCI functionality in any way The PCI JTAG signals TDI TMS TRST are not used TDI and are connected together per the PCI Specification to maintain JTAG chain integrity on the motherboard The signals TMS and TRST are left unconnected The FPGA is volatile meaning it loses its brains when power is off The Sm
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5. LM R107 82 72 R 110 R2 79 2 20 052 1 32 REF REF PROCESSING CAP 375 9 52 OUTSIDE PROFILE SHOWN ONLY NOTE 5 FRAME CONTACTS 04 1 0 25 8 261 270 6 86 SEE NOTE 3 222 025 0 64 0 64 SOLDER TAILS NOTE 4 C 050 1 27 VIEW A code tolerances unless otherwise E CUM CUSTOMER fenno Jote xx 01 COPY ELECTRONICS C 30245 TH 03 11 93 linear 005 projection title MICROPAX 025M SMT 16 41 0969 MRC 06 11 95 0020 i xp p und t 01 70 94 fonge o sz uet ponia cnn Tay WIGROPAK X 50646 06 23 95 MHAHN 3 4 93 size VIEW OPTIONAL ENDS FOR V51287 10 20 95 chr M HAHN 3 4 93 9 1 29 4 0964 003 2455 08 PCB HOLE 2 57095 sw 07722 97 Jens ns 374703 3 sheet revision POE index sheet 11121351 j 1 1 form 7530 001 103 3 22526 EMULATION TECHNOLOGY INC Figure A 3 Berg 91294 003 Datasheet Page 1 of 3 A 4 BERG CONNECTOR DATASHEETS Droits de reproduction BERG ELECTRONICS INC Tous droits strictement reserves Reproduction ou communication a des tiers interdite sous quelque forme que ce soit sans autorisation ecrit
6. 7 5 LVDS PPP 7 5 7 6 Unbuffered I O 7 6 Connectors P2 PA 7 6 Connector 7 7 6 Buffered 7 6 suu 7 6 7 6 Test Interface 7 7 Connector yard E eq 7 7 Daughter Card I O Connections 7 7 Chapter 8 Reset Schemes LEDs Bus Bars and 200 Pin Connectors Reset Schemes 8 1 LEDS D 8 3 Bus 8 4 ET5000K10S USER S MANUAL The 200 Pin Connectors P8 and P9 8 4 The 8 5 Chapter 9 Utilities PCI Debug General Pontificating 9 1 5 5 9 1 AETEST Utility Installation Instructions 9 2 Installation Instructions for DOS 9 2 Installation Instructions for Windows NT 9 2 Installation Instructions for Windows 2000 9 2 Installation Instructions for LINUX 9 3 Installation Instructions for Solaris 9 3 Installation Instructions for Windows 98 ME 9 3 AETEST Options Description and Definitions 9 4 9 4 AET
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12. z 5 x niii S _ i cu z z 8 cs E a lt jan T Figure 2 11 P2 Serial Port Locations A female to female RS232 cable is provided with the ET5000k10S This cable will attach directly to the RS232 port of a PC We get our cables from Jameco http www jameco com The part number is 132345 Male to female extension cables are part number 25700 The RS232 port is configured with the following parameters Bits per second 9600 Data bits 8 Parity None Stop Bits 1 FLow control None Terminal Emulation VT100 We use the Windows based program HyperTerminal Hypertrm exe The configuration file 5000 105 is supplied on the CD ROM or can be downloaded from our web page Users have the option of connecting the serial port if they wish to see any messages during the configuration process 2 18 EMULATION TECHNOLOGY INC ET5000K10S FEATURES OVERVIEW AND GENERAL DESCRIPTION NOTE It is NOT mandatory to have the serial port connection in order to configure the FPGA in Select MAP mode However if an error occurs during the configuration then without a serial port connection the user will not be able to see any error messages In addition without a serial port connection a user c
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35. PWB with a single Altera Stratix FPGA FBGA1508 Device availability EP1S80 EP1S60 and EP1S40 gt 450 000 ASIC gates with EP1S80 LSI standard Embedded Memory Device Flip Flops 18 x 18 Multipliers M512 RAM RAM Fast Easy FPGA configuration via standard SmartMedia FLASH card Microprocessor controlled ATmega128L RS232 port for configuration operation status and control Fastest possible configuration speed via Passive Parallel method e 10 on board linear regulator for 3 3V and 1 5V Standalone operation via separate power connector 3 3 not needed on backplane e 6 low skew clocks distributed to the FPGA and test connectors 2 7 993 4 Roboclockll PLLs 2 socketed oscillators PCI Clock 1 clock CPLD Robust observation debug with 242 connections for logic analyzer observability or for pattern generator stimulus Status LEDs User designed daughter PWB for custom circuitry and interfaces 5000 105 USER S MANUAL 2 1 T5000K10S FEATURES OVERVIEW AND GENERAL DESCRIPTION SignalTap and Identify from Synplicity fully supported via JTAG interface Figure 2 1 shows a block diagram of the 5000 105 ET5000k10S Description The ET5000k10S is a complete logic emulation system that enables ASIC IP designers a vehicle to prototype logic and memory designs for a fraction of the cost of exi
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39. AETEST Main Screen is shown in Figure 9 3 Screen Emulator PCI Controller Driver v42 Read FPGA revision PCI Menu Memory Menu Clock Menu Dedicated Multiplier Test Daughter Board Menu Perform Sanity Check on bit file Quit PCI BASE ADDRESS 21315111 12112 044444 E HARRAH E 5 Please select option Figure 9 3 AETEST Main Screen Options Read FPGA Revision Display the revision ID of the FPGA We will update the revision ID of the FPGA every time we change the reference design PCI Menu Display the PCI utilities menu Memory Menu Display the Memory Menu Flash Menu Display the Flash Utilities Menu ET2000k10 series only Clock Menu Display the Clock Utilities Menu Dedicated Multiplier Test Execute the multiplier test Q Quit and return to the DOS prompt The selections are sometimes case sensitive so be aware of the status of the CAPS LOCK on your keyboard The base addresses for each of the configured BARs is displayed on all screens You will need these addresses if you want to manually read and write to address locations within the PCI reference design In this example Figure 9 3 above BARO is configured to OxFD800000 and 1 is configured to 0xE0000000 BAR 5 2 are not configured so they show up as 0x0 9 6 EMULATION TECHNOLOGY INC UTILITIES PCI Menu AETEST PCI menu is shown in Figure 9 4 ASIC Emulator PCI Controller Driver v42
40. EMULATION TECHNOLOGY INC CLOCKS AND CLOCK DISTRIBUTION DCLK 7 R signal 7 is routed from of the Roboclock outputs to one of the Roboclockll inputs Jumper JP5 lies along this connection route JP5 must be installed in order to utilize 7 R DCLK 7 and GCLKOUT are complementary input on Roboclock 2 and are both single ended TTL inputs When either of them is being used the other one must be left open Thus GCLKOUT must be undriven FPGA for DCLK 7 R to operate DCLK 7 provides two useful results First any clock signal or some derivation sent to Roboclock 1 can be driven onto Roboclockll for full distribution Second running a clock through Roboclock to Roboclockll gives the user more divide and multiply options for the clock frequencies Here is an example If you have a 40MHz input clock the user cannot output a 30MHz clock with a single Roboclockll s multiply and divide options However the user can input a 40MHz to Roboclockll 1 and divide it by 4 By installing the JP5 jumper 10MHz clock will be driven onto Roboclockll 2 Setting Roboclockll 2 s feedback outputs to divide by 3 the operating frequency will become 30MHz Thus a 30MHz could be driven onto the Roboclockll 2 output signals NOTE The signal GCLKOUT must be left open in order to utilize DCLK 7 R ET5000K10S USER S MANUAL 4 1 CLOCKS AND CLOCK DISTRIBUTION 4 16 EMULAT
41. T5000K10S FEATURES OVERVIEW AND GENERAL DESCRIPTION D Fi 1 1 Film Figure 2 12 Delkin 32 MB 3 3 V Smart Media Card WARNING Do NOT format a SmartMedia card using the default Windows format program All Smart Media cards come preformatted from the factory files be deleted from the when they are no longer needed If for some reason you absolutely need to format a SmartMedia card you must use the format program that is included in the FlashPath SmartMedia floppy adapter software Synthesis and Emulation Issues The QuartuslI software from Altera is able to synthesize directly from Verilog or VHDL code However third party synthesis tools provide an advantage to create a memory block or multiplier all you need to do is describe them functionally and the tool will infer the appropriate DSP and RAM megafunctions for Quartus to place and route On the other hand if you are using Quartus to synthesize and you try to infer an M RAM block using a functional description Quartus will attempt to route 200 000 LEs as a memory array So if you don t have any other synthesis tool you will need to become familiar with Quartus megafunctions We have tried the following tools for synthesis Synplicity Synplify http www synplicity com Synopsys FPGA Express http www synopsys com Synopsys FPGA Compiler II Exemplar LeonardoSpe
42. lt 512k x 36 Powen 8 FlowThrough i ECLK data 36 Pipelined lt 34 SSRAM 54 512 36 36 FlowThrough ACLK data Pipelined lt EP1 S40 60 80 control 14 SSRAM 512k x 36 100 SDRAM lt ECLK 1 po pin PM DIMM Module p to 2GB x 72 125 DDR E CLOCKS JUS 32 64 Bit PCI PCI X Figure 2 1 ET5000k10S Block Diagram BGA 1508 Clock Roboclock Selection PEL Jumpers 1 or External Roboclock ECLK Cable pa 2 2 EMULATION TECHNOLOGY INC ET5000K10S FEATURES OVERVIEW AND GENERAL DESCRIPTION Easy The configuration bit files for the FPGA are copied onto a 32 megabyte Configuration SmartMedia FLASH card provided and an on board microprocessor controls the FPGA configuration process Visibility into the configuration process is enhanced with an RS232 port FPGA configuration runs quickly SmartMedia 48 MHz Eight LEDs provide instant status and operational feedback Four of these LEDs are connected to the CPLD and can be user configured FPGA Stratix U11 F The 5000 105 contains one Stratix FPGA The package is a flip chip fine pitch BGA with 1508 pins F1508 The pitch on the pins is 1 mm This isn t important but this pin density makes the PWB a bitch to layout Keep that in mind if you try to make one of these at home Most of the 1203
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44. 08 09 0 01 Im 9 la o 33IQ ON ON OI 08 09 08 09 0 1 1 0 etbd 2 12 lt gt 6 2190Q Ol VLSOG O H m diS ev 9exd 34IQ OI 92 1 JJIQ ON ON OI 1 151 21223 ZLEOG O 100Q 0l Hre gz 08 ON ONIOI 1S0Q Ol lt gt lod 3210101 7 1 08 09 2N OI 08 09 07 01 11800701 08 09 0 1 ZSlzv 6zXL 441001 z2x 33IQ ON ON OI 1 HLEOQ OI 108 0 01 08 09 2N OI 1SSOQ OI lt gt uvgo3M lod 16 E Lex 3310 01 HIG ONIONIO reg 08 09 ON OI 08 09 0 1 1 szy 0180 01 08 09 esy 4410 01 JJIQ ON ON OI 774 5 sry ZLODG O 08 09 09 1 ser 331Q OI uc X4 33IQ ON ON OI 08 09 0 08 09 07 O 5 08 09 0 L1SOQ OI OC CIV J4IQ OI JJIG ON ON OI ENYN 151 8 11000001 as 09 ON ON OI 8 9 SOM 4410 01 ut XL J4IQ ON ON OI Ipod EVES 08 09 2N OI 08 09 ON OI 1 09 2N ON OI 01800001 eyg od en 4410 01 J3IQ ON ON OI 08 09 00 01090101 bg Fe 08 09 09 1 08 09 33IQ OI 33IQ ONIO
45. EMULATION TECHNOLOGY INC lup pa 44 T 4 World Leader in ps est Accessories EMULATION TECHNOLOGY INC World Leader in Adapters Clips and Test Accessories ET5000k10S User s Manual Version 0 93 October 1 2003 EMULATION TECHNOLOGY INC 5000 105 USER S MANUAL EMULATION TECHNOLOGY INC World Leader in Adapters Clips and Test Accessories The information contained within this manual and the accompanying software program are protected by copyright all rights are reserved by Emulation Technology inc Therewith Emulation Technology Inc reserves a the right to make periodic modifications to this project without obligation to notify any person or entity of such revision Copying dupli cating selling or otherwise distributing any part of this product without the prior written consent of an authorized representative of Emulation Technology Inc is prohibited 2344 Walsh Avenue Bldg Santa Clara CA 95051 www emulation com et emulation com 408 982 0660 FAX 408 982 0664 Copyright 2003 Emulation Technology Inc All Rights Reserved EMULATION TECHNOLOGY INC 5000 105 USER S MANUAL Table of Contents Chapter 1 Getting Started Emulation Technology Inc Technical Support 1 1 Relevant Information 1 1 0 65 1 2 Chapter 2 5000 105
46. FPGA P9 Signal Pin 911 Daughter Test FPGA J1 Signal Board Header P8 Signal Pin Header Header 8 11 9 1 mur ICONE mus mm mm 3 3 V P9 106 P9 107 P9 108 P9 109 TST HDRA 79 mnc 112 PANAI 15 17 LIE TST HDRA 80 LIN mn AF10 AE10 10 TST HDRB 79 TST HDRB 90 TST HDRB 81 TST_HDRB 82 TST_HDRB 83 TST HDRB 84 TST_HDRB 85 TST_HDRA 81 P8 114 TST HDRA 82 rns SL mne mm m TST HDRA 86 TST HDRA 87 one mm Um m SL HA Leu mum 9 117 9 118 TST_HDRB 86 TST_HDRB 87 TST HDRB 98 TST_HDRB 89 TST HDRB 90 TST HDRB 91 TST HDRB 92 TST HDRB 93 TST HDRB 94 TST HDRB 95 AMT P9 127 P9 128 5000 105 USER S MANUAL 7 1 DAUGHTER CONNECTIONS ET3K10SD OBSERVATION DAUGHTER CARD FOR 200 PIN CONNECTORS Table 7 2 Daughter Board Header FPGA Pin Map Daughter Test FPGA Test J1 Signal Header P8 Signal Pin Header P9 Signal Pin Header P8
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51. Differential SSTL 2 The differential SSTL 2 standard is a 2 5 V standard used for applica tions such as high speed DDR SDRAM clock interfaces This standard supports differential signals in systems using the SSTL 2 standard and supplements the SSTL 2 standard for differential clocks The differential SSTL 2 standard does not require an input reference voltage differential Bitstream stratix devices have no special bitstream encryption function Emulation Encryptions Technology Inc may be able to assist with scrambling bitfiles to protect IP on the SmartMedia card which would then be descrambled in the programming CPLD Users should be aware however that the bitstream would be unprotected between the CPLD and FPGA so they could still be examined and reverse engineered Our ET3000k10 products use Xilinx FPGAs which can be used to decrypt the bitstream inside the FPGA 2 8 EMULATION TECHNOLOGY INC ET5000K10S FEATURES OVERVIEW AND GENERAL DESCRIPTION providing complete design protection If you are interested in this feature please be aware that there are some issues with the Xilinx encryp tion feature described in the ET3000k10 FAQ on our website BP and FPGA Configuration The ET5000k10S has an ATmega128L microprocessor that is used to control the configuration process U4 The amount of internal SRAM 4 Kbytes was not large enough to hold the FAT needed for SmartMedia so an external 32 k x 8 SRAM was added Th
52. Observation Daughter Card for 200 pin Connectors The traditional approach to experiment with new devices involving wiring together some ICs on a breadboard is fast becoming impractical and inef fective Instead designers using new high density devices need custom PC boards representing a substantial investment of time and money Prototype boards from manufacturers can meet this demand for experi mentation while eliminating the expense and time involved with custom PC boards Additionally such prototype boards facilitate the under standing and advantages of new device features Purpose The ET3k10SD daughter card allows external connection to the signals present on the 5000 105 series ASIC prototyping boards The ET5000k10S allows logic emulation with Stratix devices prior to commit ting to using them for specific applications It allows designers to try Stratix features such as BlockRAM DLLs and Selectl O resource with an off the shelf resource Features The ET3k10SD Daughter Card has the following features Buffered I O Passive and Active Bus Drivers e Unbuffered I O e Differential LVDS pairs Note Not available on 5000 105 ASIC prototyping board Headers for Test Points The daughter card contains headers that may be useful with certain types of oscilloscope probes or when wiring pins to prototype areas Figure 7 1 is a block diagram of the ET3k10SD Daughter Card The ET3k10SD Daughter Card is
53. PLLSEL2 high Roboclock1 Roboclock2 with PLLSEL2 low 427 installed and FCKLOUT unused WITH 10 PIN RIBBON CABLE Option _ Connected to 421 922 3 PLL1B PLL2B BUFINA are driven from cable BUFINB can be clocks jumpered to CLKOUT or CLOCKB or left undriven 4 BUFINB JP6 4 PLL1BN JP6 2 Buffer A is undriven 2 external PLL2B and BUFINA are driven from cable with PLL1A jumpered to clocks CLKOUT or CLOCKA Same options as above for BUFINB PECL The board can be set up for PECL inputs in PLL1B and PLL1BN and in clocks PLL2B and PLL2BN PECL ready boards cannot function without the cable except as in options 3 and 4 above Figure 4 4 External Ribbon Cable Connections Both differential pairs provide some flexibility The user can provide a single 3 3 V TTL input It can be attached to either input However the other input must be left open The user can provide a differential clock input to the pair The differential clock inputs must obey the electrical specifications listed in Table 4 8 on page 11 While attaching a ribbon cable the user can jumper oscillator signal CLOCKB to BUFINPB 3807 2 on P54 This results in full use of all of the timing devices the ET5000k108 See Figure 4 4 Roboclock PLL Clock Buffers Figure 4 5 is a functional diagram of Roboclock 1 and Roboclock 2 Jumper Descriptions Headers J8 JP10 JP9 and JP11 are used to control the PLLs Each head
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58. LogiCORE PCI X Interface ADDR VLD Menu selections or button presses FILE OPEN e Italic font denotes the following items Variables in statements which require user supplied values ngdbuild design_name References to other manuals See the Libraries Guide for more information Emphasis in text It is not a bug it is a feature e Dark shading indicates items that are not supported or reserved in out Snoop Done signal Not Supported e Square brackets indicate an optional entry or a bus index ngdbuild option_name design_name ET5000K10S USER S MANUAL 1 3 GETTING STARTED DATA 3 1 0 A vertical or horizontal ellipsis indicates repetitive material that has been omitted XYZ The use of fn SIG1 SIGn in HDL pseudocode frag ment should be interpreted as combinational function of signals SIG1 through SIGn SUM fn A B Cin The prefix 0x or the suffix n indicate hexadecimal notation A read of address 0x00110373 returned 45524943h A f an n an n or a means the signal is active low INT4 15 active low fpga inta nis active low SRAMCS is active low FPGA GRSTn is active low EMULATION TECHNOLOGY INC ET5000K10S FEATURES OVERVIEW AND GENERAL DESCRIPTION Chapter 2 ET5000k10S Features Overview and General Description ET5000k10S Features The ET5000k10S features include 32 64 bit 3 3V
59. Se i 44 4 4 4 44 44 54 54 m o momo e sap s m m 24 PUR I D a Lire 1005 INK 341 eM Y 1 m gt i 05 1 7 hs 8 Ud DAUGHTER CONNECTIONS ET3K10SD OBSERVATION DAUGHTER CARD FOR 200 PIN CONNECTORS MADE IN USA DAUGHTER BOARD L Daughter Card Power Supply 7 4 Ano mm nt D JS E F 5 1111 UI co C16 C19 C21 2282862 512 94 C E ELIT 211114 TIC Figure 7 3 ET3k10SD Daughter Card Assembly Drawing IDT74LVC16245A chips are used as bus transceivers in the active mode The ET3k10SD has separate enable direction signals for each driver NOTE Availability of these I O signals depends on the location of the daughter card with respect to the development board The LEDs act as visual indicators representing the active power sources 01 LED indicating 43 3 V present e D2 LED indicating 45 0 V present e LED indicating 12 V present Under normal operating conditions all LEDs should be on A linear power supply U4 is present to provide level shift translation functions when the board is populated with bus switches EMULATION TECHNOLOGY INC DAUGHTER CONNECTIONS ET3K10SD OB
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61. gt 34 gt Divide and FS2 3050 gt Phase select 30814329 Matrix INV3 H i zl Dividend 2050 Phase select 5051 gt Matrix 1 6 1 PN Divide and 1556 B Phase select i FDS1 1051 1 Figure 4 5 Functional Diagram Roboclock 1 Roboclock 2 4 6 EMULATION TECHNOLOGY INC CLOCKS AND CLOCK DISTRIBUTION JP8 GND 22 JP11 GND 22 Figure 4 6 Header Layout The Header Classifications are shown in Table 4 2 Table 4 2 Header Classification Controls Header Group General Control Group 2 PLL1 Divider Control Group 3 PLL2 Divider Control Group 4 Feedback and Control The input pins are either LVTTL or 3 level input pins The LVTTL pins need to be jumpered HIGH or LOW which is achieved by connecting the input pin to the neighboring 3 3 V or GND pin using a jumper The 3 level input pins can be in a HIGH MID or LOW state The HIGH and LOW states are achieved in the same way as the LVTTL pins The MID state is reached by leaving the input pin unjumpered The Roboclockll s have internal circuitry 5000 105 USER S MANUAL 4 CLOCKS AND CLOCK DISTRIBUTION to bring the pin to 1 5 V when left open The Jumper Definitions are shown in Table 4 3 Table 4 3 Jumper Definitions Name PLLSEL2 1 Type Default Description LVTTL LOW Input Clock Select If LOW U15 DCLK 7 or FCLKOUT
62. uonduoseq Aa envas 2184 vivus 2164 ZZ 8 2184 LAVHS 2184 2164 30 2184 LIAVSS T 2184 PAYS ER E Dix TENTI ENYYS uosav 2164 udsav rM 7 2096 Wvuas 1154 _ 2184 _ 1080 116d 2164 Wvss Tan LWVHS 2164 170180 5 9dOG rWvHS 2164 2164 LlWvHS 2164 09 Wvuas 1164 4400 2104 5 _ 2109 EXIST ST 2184 OSAV Tso gt 1184 WVeds L olawod Wvsas 1164 m 4 gt 2184 27 LIAVHS ewvss 2164 C gt 5 1 0POQ LAVHS C L7olaod 2164 2704004 LWVYS lt gt 2184 1 0leOG LWVYS 470 216 L olpod vWvus 2184 6 2164
63. 2 24 Synthesis 5 2 25 ET5000K10S USER S MANUAL iii Chapter 3 3 1 PCI Mechanical Specifications 3 1 Some Notes on the ET5000k10S and 3 1 JP2 Present Signals for 3 4 M66EN 66MHz Enable 3 5 TP13 PME Power Management Enable 3 5 PCI PCI X 3 6 SPS PCIXCAP Re 3 6 Chapter 4 Clocks and Clock Distribution Functional Overview 4 1 CIOCK OO 3 E CRUS 4 2 Orientation and Description 4 2 Jumper Control for the Most Common Applications 4 3 Ribbon Cable Providing an Off Board Clock to the 15000 105 cae OS AR 4 4 Roboclock PLL Clock Buffers 4 5 Jumper 5 4 5 General 4 8 Feedback and Clock Multiplication 4 9 Clock Division 4 9 Clock 4 10 Differential 4 11 Useful Notes and 4 12 Customizing the
64. 98L33HA S8vH3HA S82J3HA S8LJ3HA vassayA v8CH3HA Y8LJJHA 8SJ3HA 8 J3HA 8cH3HA 8LJ3HA C8vH3HA 28 J3HA 8LJ3HA 8 8 8 80IDDA 80IDDA 80IDDA ZOIOO9A LOIDOA LOIODA LOIDOA LOIODA 9OIDDA QOIDDA 90I99A SOIOOA SOIDDA SOIDDA SOIDDA YOIOOA YOIOOA OI9OA LOIODA LOIDDA LOIODA LOIDDA LOIODA 8091 94 08 09 075 43 8081 V983 08SLd3 1 810n0 9TId 9Tld 81n0 99A 999 999 OLMd 999 6Tld 999 999 LTld 999 9114 999 909 909 Tld 999 909 999 VODA 01114 YDA 6114 8114 LTld 9Tld STld VOOA ANIOOA ANIOOA ANIOOA ANIOOA LNIDOA LNIODA ANIOOA INIOOA ANIOOA ANIOOA ANIOOA ANIOOA INIOOA ANIOOA ANIOOA ANIOOA ANIOOA ANIOOA ANIOOA ANIOOA ANIOOA INIOOA ANIOOA INIOOA ANIOOA ANIOOA ANIOOA INIOOA ANIOOA ANIOOA
65. DSP EEPROM EIA ESD FAQ FAT FPGA FT HDL I O IP LAB LE LSI LUT LVCMOS microprocessor Base Address Register ball grid array Basic Input Output Services complementary metal oxide semiconductor Complex Programmable Logic Device Configuration Settings File digital signal processing Electrically Erasable PROM Electronic Industries Association Electro Static Discharge frequently asked questions file allocation table field programmable gate array flowthrough Hardware Description Language input output intellectual property Logic Array Blocks logic element large scale integration look up table low voltage complementary metal oxide semiconductor ET5000K10S USER S MANUAL LVDS LVTTL MDR PCI PCI X PL PLL PNP PWB RAM RBF REGE RISC SDRAM SRAM SSRAM TTL VCO VHDL VREF ZBT Low Voltage Differential Signaling low voltage transistor transistor logic Mini D Ribbon peripheral component interconnect peripheral component interconnect extended pipelined phase lock loop plug and play printed wire board random access memory Raw Binary File register enable reduced instruction set computer synchronous dynamic random access memory shadow random access memory synchronous static random access memory transistor transistor logic voltage controlled oscillator VHSIC Hardware Description Language reference voltage zero bus turnaround
66. G 1 EMULATION TECHNOLOGY INC Index Symbols C F DS 4 8 to 4 9 See microprocessor Numerics 3 3Vaux 3 4 66MHZ ENABLE 3 5 A ACLK 4 2 4 14 7 7 ADSC 5 6 5 9 ADSP 5 6 5 9 ADV 5 9 AETEST 9 1 to 9 13 Altera 2 1 2 3 2 5 2 7 2 13 to 2 14 2 19 2 24 4 13 5 12 ASIC 2 1 to 2 2 2 25 4 1 4 13 5 1 7 1 7 5 7 7 ATmega128L 2 1 2 9 to 2 10 2 12 2 16 B22 4 13 BA 5 9 BCLK 4 2 4 14 7 7 BCPUCLK 2 16 Berg A 1 to A 6 Berg Connectors A 1 to A 6 BIOS 9 1 9 9 BlockRAM 7 1 9 13 board termination voltage 2 8 Bridges2Silicon 2 16 BUFINA 4 3 to 4 4 BUFINB 4 2 to 4 5 BUP_CLK 2 14 bus bars 8 4 BWE 5 9 BWx 5 9 C380 4 4 5000 105 USER S MANUAL C381 4 4 C382 4 4 C383 4 4 carry chains 2 3 CAS 5 9 CCLK 4 8 4 11 to 4 12 4 14 7 7 5 9 CE2 5 9 CK 5 9 5 12 5 12 CLK 2 14 CLKOUT 4 2 to 4 4 clock 2 5 2 16 4 1 to 4 2 4 4 4 13 to 4 15 5 1 5 6 5 12 arrays 2 25 buffer 2 14 4 1 to 4 2 4 5 4 11 6 2 buffer input 2 14 configuration 4 1 CPLD input 2 14 DDR clock select jumper 5 15 DDR PLL 5 15 DDR SDRAM 5 12 DDR select jumper 5 12 differential 4 11 distribution 4 1 4 3 divider function 2 1 2 16 division 2 16 4 9 enable 2 4 feedback 4 9 FPGA 2 14 frequency 3 1 4 2 4 12 4 15 7 5 frequency multipliers 4 9 grid 2 14 4 2 to 4 4 4 11 header clocks 4 14 to 4 15 input 4 3 4 5 4 8 to 4 9 4 11 4 15 interfaces 2 8 intputs 4 12
67. P58 2 23 P7 2 11 to 2 12 7 6 P8 4 14 7 7 P9 4 14 7 7 pattern generator 2 1 to 2 2 PCI 3 1 3 4 to 3 7 AETEST PCI menu 9 7 board 6 5 bus 3 1 9 1 9 13 capability 3 6 clock 2 1 configuration 9 9 connector 4 13 6 1 6 5 controller 3 1 debug 9 1 device function 9 7 to 9 8 device number 9 7 edge connector 3 1 3 3 fingers 6 2 6 5 function number 9 7 JTAG signals 3 4 mechanical specifications 3 1 memory 9 9 to 9 11 power 3 1 6 5 power management 1 2 present header 3 5 present signals 3 4 reference design 9 6 signals 3 1 to 3 2 slot 2 2 3 1 6 1 6 3 Special Interest Group 1 1 specification 1 1 to 1 2 2 8 3 1 3 4 target design 2 2 PCI Menu 9 7 PCI CLK 4 13 to 4 14 PCI X 2 8 3 4 3 6 capability 3 6 capability header 3 6 controller 3 1 edge connector 3 1 3 3 frequency 3 7 power 3 1 present header 3 5 present signals 3 4 slot 2 2 3 1 5000 105 USER S MANUAL specification 2 8 PCIXCAP 3 6 PCPLD CLKOUT 2 14 PECL 4 4 4 11 pipeline 2 5 5 1 5 6 to 5 8 PL See pipeline PLL 2 1 4 1 to 4 2 4 5 4 8 to 4 9 4 13 to 4 14 5 12 5 15 PLL1A 4 2 to 4 3 4 8 PLL1B 4 11 PLL1B PRE 4 3 PLL1BN 4 8 4 11 PLL1BN 4 3 to 4 4 PLL2B 4 11 to 4 12 PLL2B PRE 4 3 PLL2BN 4 8 4 11 to 4 12 PLL2BN PRE 4 3 PLL5 4 13 to 4 14 PLLSEL2 4 8 PME 3 5 polarity 4 13 power 2 12 2 21 to 2 22 3 1 3 4 to 3 5 6 1 6 3 1 5 V 6 3 2 5 V 6 2 3 3 6 2 connector 2 1 6 3 distribution 3 1 6 1 limit 6 5 rail 6 2
68. P8 069 TST HDRA 52 T28 TST HDRA 50 5000 105 USER S MANUAL 7 DAUGHTER CONNECTIONS ET3K10SD OBSERVATION DAUGHTER CARD FOR 200 PIN CONNECTORS Table 7 2 Daughter Board Header FPGA Pin Map Daughter Test FPGA Test J1 Signal Header P8 Signal Pin Header P9 Signal Pin Header 8 11 9 11 T6 PAN 28 076 TST HDRA S9 C7 AE28 78 PANDG US44 MAS P8 078 TST HDRA 60 87 AF28 79 PANI US46MAS P8 079 TST HDRA 61 A7 628 Cw jua rows HN 8 PNIS P8 081 TST HDRA 63 M27 82 MN P8 082 TST HDRA 64 K27 o P8 084 TST HDRA 66 B8 H27 85 0 P8 085 TST HDRA 67 AF P9 085 627 127 P8 086 TST HDRA 68 9 F27 P8 087 TST HDRA 69 89 PN OO P8 089 HDRA 70 V9 Cm Ir rm num Cm m rors HN 8 093 1 5 AE20 AE20 94 P8 094 TST HDRA 74 Crue row Cm mus ron Inm nes mem Dm mv mum ewe mom joo mas num mum asv Deme nm a mm m 12 V 1 5 V AE20 7 10 EMULATION TECHNOLOGY INC DAUGHTER CONNECTIONS ET3K10SD OBSERVATION DAUGHTER CARD FOR 200 PIN CONNECTORS Table 7 2 Daughter Board Header FPGA Pin Map
69. ence voltage or a termination voltage PCI X Peripheral Component Interface The PCI standard specifies support for 33 MHz 66 MHz and 133 MHz PCI bus applications It uses a LVTTL input buffer and a Push Pull output buffer This standard does not require the use of a reference voltage or a board termination voltage Vry however it does require 3 3 V input output source voltage Vcco SSTL 3 class and Il SSTL 3 uses a series termination resistor on output signals and a parallel termination resistor on input signals Stratix devices use a VREF of 1 5 to enable the appropriate resistors internally Because SSTL 3 requires parallel termination it is only available on banks 3 4 7 and 8 and on clock output signals CTT CTT uses a parallel termination resistor on input signals with no termina tion resistors on output signals Stratix devices use a VREF of 1 5 to enable the appropriate resistors internally Because CTT requires parallel termination it is only available on banks 3 4 7 and 8 and on clock output signals SSTL 2 Class amp The SSTL 2 I O standard is 2 5 V memory bus standard used for applica tions such as high speed DDR SDRAM interfaces This standard defines the input and output specifications for devices that operate in the SSTL 2 logic switching range of 0 0 to 2 5 V This standard improves operation in condi tions where a bus must be isolated from large stubs
70. gt PLLI1A and CLOCKB lt gt BUFINB 5000 105 USER S MANUAL 4 3 CLOCKS AND CLOCK DISTRIBUTION PLL2B_PRE Cis PLL2BN PRE 393 PLL1B_PRE C396 PLL1BN PRE ctoo In this configuration a 3807 2 receives an oscillator input Roboclockll 1 receives an oscillator input while Roboclockll 2 receives the CPLD output clock signal 3807 1 is unused Finally the grid may be configured as Configuration 3 CLKOUT lt gt CLOCKA lt gt CLOCKB lt gt PLL1BN The 3807 1 receives an oscillator input and the 3807 2 receives a CPLD input Meanwhile Roboclockll 1 receives the other oscillator input The user can wire wrap a clock to the unused driver s as needed This enables full use of the timing devices the 5000 105 Also the destination of the output clocks might dictate some other config uration This manual and other documentation should provide more than enough information to satisfy the user s needs See Figure 4 3 3 3 3 3V 3 3 3 3 197 amp R201 R182 amp R190 82 82 82 82 PLL2B 0 1uF PLL2BN NM p PLLIBN 2 0 1uF R183 amp R191 R198 amp R200 130 amp 130 130 amp 130 Figure 4 3 PECL Clock Input and Termination Ribbon Cable Providing an Off Board Clock to the ET5000k10S NOTE C380 C381 C382 and C383 are stuffed with 0 ohm resistors Note that the
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74. 34IQ ON OI y 900 8 Vu u9g LoXH 3dIQ ON O d90L 08Xl JJIQ ON OI utZL 96 0 XL 34IQ OI 34IQ ON OI uOWz ZXL J4IQ OI JJIQ ON OI Hosny 998 09 1 4 10 1 gt 901 08 1 JJIQ ON OI 4 621 16 84 4410 01 44IG ON OI L dol z cXL dIQ OI D Hoey a Fs 998 09 29 1 441 01 d 01 64 09X4 33 404 4621 16 8 34IG OI 90 eray 151 JJIQ ON O 55 doe zzisVxer 3314 01 17 LIAVSI Vu 4 8 29 4 JJIQ ON O R u 01 64 09X JJIQ OI dszL 46 L XL 34IQ OI gt 44IQ ON ON OI 4 3dIQ 2N O gt 3JIQ ON O 2704 u g z0Xd 3dIQ ON O d 0V LgXL JdIQ ON OI uszi 46 L XL 314 01 3dIQ ON ON OI NVus ULL E EXL JdIQ OI 46 88 1 dIQ ON OI 978 19 8 1 3410 01 U 0U L8XL JdIQ ONI OI 995 86 6 4IQ OI Hery AV dLL E XL 410101 gt ULE EZ OLXY_ 341 0 acr 2 1 8 19 8 1 5310 01 4801 08 19 510 01 u9zL 86 6 X4 44IQ OI cy 33IQ ON ONIOI grav 5 4410 01 die ez oixel 3314 01 ney 998 59 6 J4IQ OI 4801 08 19 JIQ OI doz 8G z XL 34IQ OI u9pLXL 34IQ ON ON OI 410 01 uze SzX1 J3IQ ONI OI eer
75. 4 PCI ADI61 4 PCI 62 4 PCI 0 63 lt lt 5 lt 6 4 PCI Pin P2 A58 B58 A57 B56 A55 B55 A54 B53 B52 A49 48 47 47 46 B45 A44 A32 B32 A31 B30 A29 B29 A28 B27 A25 B24 A23 B23 A22 B21 A20 B20 A52 B44 B33 B26 A34 B35 B16 A36 B37 A38 A26 B18 A60 B60 A67 A6 B40 B42 A15 B39 A43 A17 A91 B90 A89 B89 A88 B87 A86 B86 A85 B84 A83 B83 A82 B81 A80 B80 79 78 A77 B77 A76 B75 A74 B74 A73 B72 A71 B71 A70 B69 A68 B68 B66 A65 B65 A64 Figure 3 1 FPGA Pin Connections for PCI Signals EMULATION TECHNOLOGY INC Pg7 PCI REQn PCI CBEn3 PCI CBEn2 PCLIRDYn lt gt C L FDYn PCI DEVSELn lt gt PCI LOCKn lt gt Pg6 PCI PERRn Qo PCI SERRn lt gt PCI CBEn1 PCI Me6EN lt M66EN 64 lt lt gt PCI 64 PCI 6 4 12 5V PCI TDIO PCLINTAn PCI INTAn PRSNT1 VIO 1 PRSNT2 B14 3 3VAUX ra EL VIO gt n RSTn 1 PCI GNTn voz 1
76. 5 4 12 ET5000k10S PCI Operation 4 13 PCI 5 4 13 4 14 Header Clocks 4 14 254858 4 15 Chapter 5 Memories SSRAIVISS 5 1 SSRAM lt 5 1 Pipeline Flowthrough ZBT 5 6 SDRAM 239211223 3 9 3 32 29223 22 2 2 3 5 9 SDRAM On Board Options 5 11 DDRSDRAM 5 12 17 EMULATION TECHNOLOGY INC DDR SDRAM On Board 5 12 Chapter 6 Power Supplies and Power Distribution 133 POWE 6 2 22 52 V 6 2 1 5 V 6 3 Stand Alone Operation 6 3 Chapter 7 Daughter Connections to ET3k10SD Observation Daughter Card for 200 pin Connectors PUFDOSO ACE RUE RAE X 7 1 Features 7 1 Daughter Card 05 7 4 Power 7 4 26 8 dX d 7 5 Power acide nmn e oo de Rd aa 7 5 Connector 8
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78. Mime 7 8 EMULATION TECHNOLOGY INC DAUGHTER CONNECTIONS ET3K10SD OBSERVATION DAUGHTER CARD FOR 200 PIN CONNECTORS Table 7 2 Daughter Board Header FPGA Pin Map Daughter Test Test J1 Signal Header P8 Signal Pin Header P9 Signal Pin Header 8 11 9 11 Ril 99 WR NM 53 am 1208 Mas 56 8 02443411 8 056 TST HDRA 40 57 251 U2 46J4 13 28 057 TST_HDRAT41 AN6 29 057 TST_ TST HDRA 32 TST HDRA 33 TST HDRA 34 TST HDRA 35 TST HDRA 36 TST HDRA 37 TST HDRA 38 TST HDRA 39 P9 057 TST HDRBI41 58 U2 47 14 15 P8 058 HDRA 42 AM6 P9 058 TST HDRB 42 TST HDRA 43 6 29 059 TST HDRB 43 TST HDRA 44 6 P9 060 TST HDRB 44 TST HDRA 45 P9 061 TST HDRB 45 TST HDRA 46 P9 062 TST HDRB 46 TST 47 P9 063 TST HDRB 47 TST HDRA 48 P9 064 TST HDRB 48 TST HDRA 49 29 065 TST HDRB 49 P9 067 TST HDRB 50 E 2 ome nus nn ___ 6 nos 69 33641
79. PCI Device Function Hum 1 5 Set PCI Device Number F gt Set PCI Function Number D Display all Configured PCI Devices 1 Display Vendor and Device ID for PCI device function 1 2 Loop on POI device fun 1 and Display Vendor and Device ID 3 Loop on PCI device fun 1 and Don t Display Vendor and Device ID 4 Loop on all PCI device numbers and Display Device Vendor G Display all PCI information for PCI device function 1 6 Write config dword 7 Read config dword 8 Display Config Registers HxH for device function 1 Configure BAR s from File U Configuration to File M Main Menu Q gt Quit PCI BASE ADDRESS BHHHBHBBH i HHHBHHBBH 2 HHHBHBBBH 4 5 Please select option _ Figure 9 4 AETEST PCI Menu Set PCI Device Number Sets a PCI device number of your choice as the active device hex input This option lists the available Device Numbers to help you match up your Device ID and Vendor ID with the device number Set PCI Function Number Sets a PCI function number of your choice as the active function of a multi function device hex input This option lists the Device ID and Vendor ID of each function within the active device number to help you to choose the desired function Display all Configured PCI Devices Displays the PCI Device Numbers and corres
80. Reads and displays all of the configuration space for the active device and function number Use options S and F to change between the active device number and function number and then use this option to view the entire configuration space Write config uration DWORD Allows write to configuration space The following text will appear to remind you what is in configuration space for a PCI device CS VENDOR 00 00 PCL Lo PCI CS 0 04 PCI CS 5 050 06 PCI CS REVISION 100 08 PCI CS CLASS 9 PCI CS CACHE LINE SIZEOxOc PCI CS MASTER LATENCYOxOd PCI CS HEADER TYPEOxOe PCI CS BISTOxOf PCI CS BASE ADDRESS 00x10 PCI CS BASE ADDRESS 10x14 PCI CS BASE ADDRESS 20x18 PCI CS BASE ADDRESS 30 1 PCI CS BASE ADDRESS 40x20 PCI CS BASE ADDRESS 50x24 PCI EXPANSION ROMOx30 PCI CS INTERRUPT LINEOx3c PCI CS INTERRUPT PINOx3d PCI 5 MIN GNTOx3e PCI CS MAX LATOx3f Input config offset hex 0 00 0 word to write in hex Loop indefinitely y or n If looping was selected any keypress will stop the loop Read config uration DWORD Allows read from configuration space Has options for single read loop read with display and loop read without display EMULATION TECHNOLOGY INC UTILITIES Configure BARs from File Reloads the PCI configuration of the active device from file It writes to the command register and writes the 6 bars with
81. SRAMA 0094 lt lt 4 0095 lt 5 4 0096 lt 5 0097 lt 5 lt gt SRAMA 5 lt Figure 5 4 SSRAM 4 U13 Bus Signals 5000 105 USER S MANUAL SSRAM 4 U13 SAO SA1 SA2 5 4 5 5 5 6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 expansion Suid 55 ADV ADSP ADSC BWA BWB BWC BWD BWE GW MODE CE OE ZZ SUId 04402 DQaO DQa1 DQa2 DQa3 DQa4 DQa5 DQa6 DQa7 DQbO DQb1 DQb2 DQb3 DQb4 DQb5 DQb6 DQb7 DQcO DQc1 DQc2 DQc3 DQc4 DQc5 DQc6 DQc7 DQdO DQd1 0042 DQd3 4 0045 DQd6 DQd7 DQPa DQPb DQPc Pipeline Flowthrough ZBT Pin 14 of each SSRAM may be pulled high pulled low or left unconnected Table 5 1describes which 0 ohm resistors must be used for each type of SSRAM to function correctly Table 5 1 Requirements for Non Standard 55 5 ZBT Pipeline Install Install Install Install R129 R130 R128 R215 R2 R3 R1 R70 ZBT Install Install Install Install Flowthrough R129 R130 R128 R215 R140 R142 R138 R216 Syncburst Flowthrough No Extra Resistors or Pipeline Syncburst FT Flowthrough Figure 5 5 is the most straightforward type of SSRAM available for the 5000 1065 Write data may be acc
82. and give you arrays of LEs instead 3 Much to our surprise the synthesis programs recognized RTL multi plier code and used the embedded multipliers without any trouble So like the memories RTL description of your multipliers is all that is necessary unless you are synthesizing with Quartus Make sure to check the report files multipliers that are implemented using logic blocks as opposed to the embedded memory blocks take huge amounts of FPGA resources 4 Clocks are the biggest problem when converting ASIC code to FPGA code FPGAs only have a limited number of clock arrays This is far too complicated to describe here so get the Stratix Data Sheet and read about the clocks 5000 105 USER S MANUAL 2 2 T5000K10S FEATURES OVERVIEW AND GENERAL DESCRIPTION 2 26 EMULATION TECHNOLOGY INC Chapter PCI Overview The 5000 105 can be hosted in a 32 bit or 64 bit PCI slot is also supported Stand alone operation is described in Stand Alone Opera tion on page 3 An EP1580 7 with care should be able to support a 64 bit 66 MHz PCI or PCI X controller We have not tested the PWB at PCI X speeds of 100 MHz and 133 MHz We suspect but won t guarantee that the ET5000k10S can support these high frequencies provided the speed grade of the FPGA is adequate Figure 3 1 shows the FPGA pin connections for the PCI signals This data is provided on the CD ROM in a csf file titled pins F csf for your convenie
83. input of the DDR SDRAM EEPROM Stuffing a 10 K Ohm resistor R59 will keep the wP signal low inactive The default configuration is R59 stuffed The EEPROM holds data describing size configuration and timing charac teristics of the DDR SDRAM The data is write protected when the wP signal is high There should be little or no reason to want to overwrite the EEPROM data Some manufacturers simply connect the WP pin of the EEPROM chip to the power supply in which case the WP resistor has no effect whatsoever Header JP4 allows the user to select which clock the DDR SDRAM runs off of Figure 5 14 shows the DDR Clock Select Jumper JP4 The signal DDR PLL6 which is connected to pin 2 of JP4 connects to the input of the FPGA s Enhance PLL6 A PLL must be instantiated in the FPGA HDL code to setup the DDR clock signal This PLL will need to have three 3 output positive differ ential clocks one board level clock output used for feedback one clock input and one feedback input see Figure 5 14 for a diagram of the DDR PLL circuit 5 12 EMULATION TECHNOLOGY INC 011 DDR SDRAM J2 AT19 6 008 01 10 21 lt 008 CKI NC 21 lt pDR CLK 2 NC 4 cLK o n 021 4 cK1s NC awai lt lt R NC _ DD
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85. rails 6 1 to 6 2 6 4 to 6 5 8 1 rating 7 5 reference 6 3 requirements 3 4 source 6 5 sources 7 4 specification 6 3 supplies 6 1 to 6 5 8 1 supply 2 23 5 11 to 5 12 6 1 to 6 3 6 5 7 4 to 7 5 switch 9 9 power distribution to 6 5 Power Management Enable See PME power supplies 6 1 to 6 5 8 1 power supply 2 23 5 11 to 5 12 6 1 to 6 3 6 5 7 4 to 7 5 power up 9 1 prototyping board 7 1 7 5 7 7 PWB 1 1 2 1 to 2 3 2 16 2 23 3 1 PWR RSTn 2 14 Index Continued Q Quartus 2 17 2 19 to 2 20 2 24 to 2 25 R R1 5 6 R128 5 6 129 5 6 R130 R3 5 6 R138 5 6 R140 5 6 142 5 6 198 4 4 R2 5 6 7 8 R206 4 4 R207 4 4 R209 4 4 R210 4 4 R211 4 4 R212 4 4 R214 4 4 R215 5 6 R216 5 6 R217 5 11 R218 5 11 R59 5 12 R70 5 6 RAS 5 9 RB C F F 4 8 reference design 2 17 2 21 9 6 REGE 5 12 regulator 2 1 3 1 6 2 reset 2 4 2 13 8 1 button 2 22 functionality 8 1 schemes 2 14 8 1 to 8 2 ROBO LOCK1 2 14 ROBO LOCK2 2 14 Roboclock 2 1 4 1 to 4 7 4 10 to 4 15 5 9 6 2 5 9 Roboclocks 6 2 RS232 2 1 2 3 2 17 to 2 18 RST 3 4 9 1 S S1 2 13 2 22 to 2 23 4 9 SDRAM 2 3 4 13 5 9 5 11 to 5 12 6 2 6 5 bus signals 5 10 to 5 11 DIMM 5 1 5 9 EEPROM 5 11 test 9 2 9 13 Selectl O 7 1 serial port 2 12 to 2 13 2 17 to 2 19 2 21 location 2 18 Signals 2 14 2 14 UP ALE 2 14 UP RDn 2 14 UP WRn 2 14 UPAD 2 14 UPPADDR 2 14 3 3Vaux 3 4
86. 08 09 08 09 0v OI a 08 09 07 01 65 uaa 9 1 8 09 O8VOQ 08 09 0v O er y 8 08 0904 01 08 09 essy arre geq uda 426 s 28904 08 09 00 01 9 08 09 0v O esa v 08 09 2N OI m 08 ON ON OI sea 5 08 ON ON OI 08 09 gt 4 y 81500 08 09 0 01 S 5870 08 09 v 99500 08 09 0 101 08 09 09 1 v 8 9 08 09 Hrne esa 08 09 0 9 Wy T y 8LOQ 0g 09 0 O 5 amp vSOQ OS O9 0v OI y Tu g 9 01 08 09 09 1 08 09 ON OI y v 08 09 09 1 8700 08 09 0 rsq y V V V V 220 y 7890 08 09 07 01 gt L860Q 08 09 0v OI y Sd v v8LOQ 08 09 0 OI 08 ON ONIOI y 08 ON ON OI 08 09 v 08 09 2N OI vHYOQ 08 09 0v OI v 89 28600108 09 09 1 5 LOQ 08 09 0v O 08 09 09 1 v 08 09 0 01 08 09 dV v 08 09 0 1 08 09 0 9 1 989040 08 09 0 01 86500 08 09 07 01 y v 98 00 08 09 07 0 98VOQ 08 09 0v OI V 9 08 09 09 1 08 09 ONIOI 05 v 08 09 2N OI 08 09 ON OI ved 8900108 09 09 1 86
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88. 1 neq lt gt uawvH4 lod 5204 ZAVAS apr 4410 01 gt 2 1 08 09 ONIOI 08 09 ON OI 71600 01 08 09 09 1 opp 109 JJIQ ONIOI JJIG ON OI be AY WIVSOH 151 91vOQ OI 9LLOG O rry 104 08 09 0v OI O8 09 ONIOI jezy Ld 8 LSL gn 33IG ON OI mi drolesxd 1 SGT 08 09 0 1 ey spy 51600 11900101 x SCT 9 6 J3IQ OI ugg Sg zvX 314 01 ees 295 128 08 09 0701 81100101 08 09 2N OI 08 09 0 01 1500 3310 01 2 331001 Er evs FEF 00080001 gt d EN UT Tz 8170 0 2 08 09 0V Ol r ITE q 21600 01 41900001 kg T ST ucp 0 Xd 34IQ OI Y uggjos eyxl 441001 be 699104 1304 01 LLOQ OI lt 7 24 09 09 00 08 ON ONIOI AVES 4 0 6 4 3310 01 deo os evxL 33IQ OI 08 09 0 01 m 08 09 0v OI 7 m Y190Q 0 ozy 97 96 1 4107 09 j4IG ON ON OI H 21 01 X 1LSOQ O 08 09 ON OI 2 1900 01 154 995 961 34IQ ON OI 34IQ ON ON OI 5 199 T O8 09 ONIOI rr 22
89. 14 EMULATION TECHNOLOGY INC Appendix A Berg Connector Datasheets Figure A 1 and Figure A 2 contain the schematics for the Berg 91403 003 Connector Figure A 3 through Figure A 5 contain the schematics for the Berg 91294 003 connector 5000 105 USER S MANUAL A 1 BERG CONNECTOR DATASHEETS All rights strictly reserved Reproduction or issue to third parties in any form whatever is not permitted without written authority from the proprietor Property of C BERG ELECTRONICS Copyright BERG ELECTRONICS INC UD o 3 Cn mo 25 4 m gt 5 i o ze 56 mm gt U o o o e ze xm 2 2 15 A eb 12945 90 520 EA bue P sabun om es 6 5 2 2 2 8 ES 5 o 7 5 ete gt 2 Bass n N CA OW CA N Hg em R 5 g a 5 3 a 8 O 20 11 12 838 gt lt m yonpoud A E im 14 n na IR ED on gt 5 2113 EE 2 rnm sz 5125 NEN ELECTRONICS
90. 2900 922 4410 01 g 98 1 3JIQ ON ON OI Ug6 4 65XL 3IG OI gt vas dL L 68 0X4_441C 01 9 801 28 14 10 01 ere dzXL jdIQ ON ON OI 3414 01 Hoery 151 qj u8 XL 4410 466 1 2 29 4 43IQ OI zoq ULL L 68 0LXH 33IQ OI d L 60L E8XL 34IQ OI ese uz zXH 34IQ ON OI 922 3310 0 gr 46 4 J3IG ON ON OI u66 L Z8X4 34IQ OI esvivd Wvuds d LL egXL JdIQ ON OI JJIQ OI Hasy 4 4 33IQ ON OI ugz S LS 1XL 341 01 ne AV J4IQ ON ON OI 466 09 174 10 01 ULLL 88XL 44IG ON O 1 901 8X4 3310 01 pare JdIQ ON ON OI dez S VS 4410 01 AV Vu 46 1 J4IG ON ON OI u66 4 09X1 JIQ OI Q H 34IQ OI Ug 1 90 1 8Xel JJIQ OI J4IG ON ON OI 4 10 01 Horny u6 XL 400 2 4410 01 UgLL O6 L ZX 4410 01 dec L 0LL gX L 4310 01 v JHIQ ON ON OI 462 8 8 3414 01 gr 908 4IQ OI 0905 dgLL 06 69X1 34IG OI LOL 4410 01 Heny 6 J4IG ON ON OI uvz 99VXL J4IQ OI eren 44IQ ON ON OI do0L t4 L9XL 4410 1 uam gt U8L1 06 69XL 34IQ OI 466 201 88 4 10 1 FNY Up 0ZXL 3dIQ ON OI dyz 9L 9XL 4410 151
91. 2X 0 045 91 14 ooo 008 2 DIM B DIM PROPOSED TERMINATION 050 1 27 2903 0000 REQUIREMENTS 004 10 POS 253 122222 nd 160 4 06 REF 480 12 19 0 010 0 001 0 25 0 03 00870 20 SJ x 0 053 1 33 REF 2X BOTTOM VIEW TI matl code tolerances unless ecn dr date 01 005 projection title LE do ____ XXXX 0020 gh fonges 037 Jae 378 85 INCH MM HAHN 3 8 93 er mham 3 8 93 1 Ll 9 Haw 3 8 93 sheet index sheet 1 form no 7530 001 103 1 2 3 NOTES MATERIALS DIELECTRIC LCP CONTACTS BeCu FRAME ZINC ALLOY 3 2 PLATING SOLDER TAILS 150u 3 81um Sn Pb FRAME 150u 3 81um BRIGHT TIN CONTACTS 30u 76um OVER 50u 1 27um Ni OR 60u 1 52um OVER 75u 1 90um Ni 3 WHEN THE CONNECTOR IS MATED WITH THE OPPOSITE HALF THE PARALLEL BD TO 80 IS 47 01 APPLYS TO VERT THRU amp SURFACE MT STYLES 4 THE SOLDER TAILS ON THIS PRODUCT ARE DESIGNED TO BE COMPLIANT IN ORDER TO ACCOMMODATE PRINTED CIRCUIT BOARD DIMENSIONAL VARIATIONS THEREFORE HOLDDOWN HARDWARE IS REQUIRED TO SECURE THE CONNECTOR TO THE PRINTED CIRCUIT BOARD FOR MOST TYPES OF SOLDER REFLOW OPERATIONS FOR FURTHER APPLICATION DATA INCLUDING HOLE SIZES FOR VARIOUS TYPES OF HARDW
92. 32 bit kernel Note that all the text files including the scripts are DOS text format with an extra carriage return character after every new line so you need to convert them 1 install the driver to the driver directory make sure the driver file is the sparc sub directory and run sh dndey uninsrtall sh 2 uninstall the driver run sh dndev uninstall sn 3 the test utility run aetest_solaris as root after the driver is loaded The driver is compiled with the gcc compiler aetest solaris Is compiled with gmake You can download it from the GNU website The make from the Solaris installation does not work with our makefile format You may need to make aetest solaris executable run chmod u x aetest solaris Installation Instructions for Windows 98 ME There are two ways to run AETEST You can run the DOS version aetestdj exe directly or you can run AETEST with a device driver 5000 105 USER S MANUAL 9 3 UTILITIES DEUICE ID 15H1 AETEST Options Description Definitions To run AETEST with a device driver follow the steps below 1 Choose a default PCI driver for the device When Windows first starts with the device plugged in it should ask for a device driver Select Specify the location of the driver Select Display a list of the drivers in a specific location Select Other devices Under Manufacturers tab select u
93. 5000 105 Stratix FPGA V INT 011 We also run 1 5 Va little hot At worst case for all components the 1 5 V power supply should never fall below 1 50 V Table 6 3 Specification for 1 5 V Power Minimum Typical Maximum Voltage 1 55 1 56 1 58 If you use the 5000 105 a lab environment the Stratix FPGA will never see worst case power and temperature so you can use typical commer cial timing NOTE In a lab environment the FPGA never sees the worst case temperature power You use typical commercial timing Stand Alone Operation The ET5000k10S can be used stand alone meaning it doesn t have to be plugged into a PCI slot Connector P1 is used to provide power to the ET5000k10S in this configuration 1 is a Molex drive power connector and will connect to any standard ATX power supply see Figure 6 2 The power supply that we used is shown in Figure 6 3 but any ATX or AT style power supply will work We use a 250 watt supply Since the 5000 105 does not draw enough current to meet the minimums required by the supply we plug an old disk drive into another one of the Molex connec tors The current drawn by the disk drive sinks enough current to make the switchers in the power supply happy 5000 105 USER S MANUAL 6 3 POWER SUPPLIES AND POWER DISTRIBUTION E P Figure 6 3 Example Power Supply The P1 connector is
94. 515151 111510 Hind 4 4 44 Hin Figure 9 10 AETEST Memory Display 18 Hindi 051241 245544 24 44 511 4 2 1515 2 2 4 2 Hind Hin HARARE HARARE HAAR 4 1 f forward pages the screen forward in memory b back pages the screen backwards in memory jump jump to a specific location in hex 0 goto jump back to the original address location specified at the beginning d delay and display loop display wait for a second and dis play again Loop until a key is struck 1 HHA Hid HAHAHAH 1 1 HAHAHAH 101 01 1 Him Him 1 1 You will be prompted for the memory location hex The physical address is needed All 4 gigabytes of PCI memory can be read Three options are available 1 Read once and display 2 Read indefinitely and display 3 Read indefinitely and don t display Write Read Memory Byte write and read a single DWORD from a specific memory location After entering a memory address hex 32 bits you specify how many DWORDS you want written and read back and 9 12 EMULATION TECHNOLOGY INC UTILITIES the data Then you choose from the 3 options as above The menu option does not perform any data checking Figure 9 11 Numbers of long words to write in decimal 2 byte to write in hex 88888888 byte to write in hex
95. 66MHZ ENABLE 3 5 ACLK 4 2 4 14 7 7 ADSC 5 6 5 9 ADSP 5 6 5 9 ADV 5 9 BA 5 9 BCLK 4 2 4 14 7 7 BCPUCLK 2 16 BUFINA 4 3 to 4 4 BUFINB 4 2 to 4 5 BUP CLK 2 14 BWE 5 9 BWx 5 9 CAS 5 9 CCLK 4 8 4 11 to 4 12 4 14 7 7 5 9 CE24 5 9 CK 5 9 5 12 5 12 CLK 2 14 CLKOUT 4 2 to 4 4 Clock Signals ACLK 4 2 4 14 7 7 BCLK 4 2 4 14 7 7 BCPUCLK 2 16 BUFINA 4 3 to 4 4 BUFINB 4 2 to 4 5 CCLK 4 8 4 11 to 4 12 4 14 7 7 EMULATION TECHNOLOGY IN 2 14 CLKOUT 4 2 to 4 4 CLOCKA 4 2 to 4 4 CLOCKB 4 2 to 4 5 CPLD CLK 2 14 CPUCLK 2 16 DCLK 2 16 4 3 4 8 4 11 4 14 to 4 15 7 11 DCLK 7 R 4 14 to 4 15 ECLK 4 8 4 11 to 4 14 5 1 5 9 7 7 7 11 FCLKOUT 4 8 4 14 GCLKOUT 4 13 to 4 15 HDR CLKOUT 4 8 INV1 4 12 INV2 4 8 4 12 PCI CLK 4 13 to 4 14 PCPLD CLKOUT 2 14 PLL1A 4 2 to 4 3 4 8 PLL1B 4 11 PLL1B 4 3 PLLIBN 4 8 4 11 PLL1BN_PRE 4 3 to 4 4 PLL2B 4 11 to 4 12 PLL2B PRE 4 3 PLL2BN 4 8 4 11 to 4 12 PLL2BN PRE 4 3 PLLSEL2 4 8 RB C F F 4 8 CLOCKA 4 2 to 4 4 CLOCKB 4 2 to 4 5 CONF DONE TDO 2 14 2 16 CPLD CLK 2 14 CPLD LED 2 14 CPLD TCK 2 14 to 2 15 CPLD TDI 2 14 to 2 15 CPLD TDO 2 14 to 2 15 CPLD TMS 2 14 to 2 15 CPLD TRST 2 14 CPUCLK 2 16 DATAO TDI 2 14 2 16 DCLK 2 16 4 3 4 8 4 11 4 14 to 4 15 7 11 DCLK TCK 2 14 2 16 DCLK 7 R 4 14 to 4 15 DDR SDRAM 5 12 DDR CLK 5 12 DDR CLKn 5 12 DDR CLK 5 12 DDR CLKn 5 12 DIP1 0 2 14 ECLK 4 8 4 11 to 4 14 5 1 5 9 7 7 7
96. AD47 PCI AD45 PCI AD35 277 AD51 2 8 78 Bes d _B79 AZ9 AT A81 GND PCI AD44 A83 PCI 042 VIO 6 i 250 PCI AD40 Ba AD LAM PCI AD38 ape PCI AD36 PCI 63 631 AD 0 63 Note The B of the connector must be on the components side o f the Figure 3 2 PCI PCI X Edge Connector 5000 105 USER S MANUAL zu zu zu fallal allal lal la e 9 0 0 0 0 0 0 O O0 O O O O O O O O O O 0 0 6 5 0o09090000000000000000009 9 n mn 5 HH JP1 MI gil 4 7 elel B p 13 eos Rs 21 2729 Rs EB d EB d 4 Rd mium 679 999999999999999 89959999999999999999 dd 51 1
97. ELKI FBp GCLKOUT 7 7 Enhanced m GCLKOUT PCI CLK PLL5 DDRS RoboClock II OSC PLL2B 944 0 12 RER ECLK9 Enhanced PLL 11 ACLKO Fast 5 Ribbon cable for PLL 1 SDR external clocks connect h SDRAM 48MHz BCLKO Fast J1 33 PLL2 0 3 BUFINA Clock Buff FPGA CPLD CLKO EP1S80F1508C7 CPLD CPLD CLKOUT PI49FCT3805 CPLD CLK1 EPM3256A BUFINB BCLK 0 3 UP CLK CCLKO Fast PLL 3 PLD KO PLD K Fast PLL 4 CLKOp n OSC CLOCKB PLL1B CCLK O 3 ACI 5 aa DDR_PLL6 CLK1p n DDR ners S me RoboClock 7 6 CLK2p n 184 Pin CYB944V REPAR PLL_FB6p E DCLK7 UP uP ATmega 128L ECLK6 SSRAM ECLK4 SSRAM 1M x 36 1M x 36 Test Header A Test Header B ECLK7 SSRAM ECLK5 SSRAM 1M x 36 1M x 36 Figure 4 1 Clock Distribution Block Diagram 5000 105 USER S MANUAL 4 1 CLOCKS AND CLOCK DISTRIBUTION Clock Grid Orientation and Description The Clock Grid JP6 a 5X3 0 1 in header distributes clock signals to two FCT3807 clock buffers and two lt PLL clock buffers CY7B993 or CY7B994 The clock outputs from the buffers are dispersed throughout the board Two 3 3 V half can oscillator sockets X2 and and the signal CLKOUT from the CPLD provide on board input clock solutions The 5000 105 is shipped with both a 14 318 MHz X2 and a 33 MHz X3 oscillator Neither X
98. Features Overview General Description ET5000k10S Features 2 1 ET5000k10S Description 2 2 Easy Configuration via SmartMedia 2 3 FPGA Stratix U11 2 3 Flip Flops and 5 2 3 Embedded 2 4 Multipliers ene ceeds ERROR 2 5 159065 08505656046 Rr ee 2 7 Bitstream 5 2 8 and FPGA Configuration 2 9 The pP Some 5 2 9 Unused pP Connections 2 10 ATmega128L JTAG Interface 2 11 Programming the ATmega128L 08 2 12 Detailed 5 2 12 CPLD EPM3256A 2 14 Some Miscellaneous Notes on the CPLD 2 16 Notes on Header 2 16 Fast Passive Parallel Configuration Instructions 2 17 Creating Files for Fast Passive Parallel 2 17 Setting up the Serial Port P2 RS232 Port 2 17 Creating Main Configuration File main txt 2 19 Starting Fast Passive Parallel Configuration 2 21 Description of Main Menu Options 2 22 6 2 23 Synthesis and Emulation Issues
99. HARDWARE SEE 932 DO NOT REMOVE PROCESSING CAP UNTIL SOLDERING 15 COMPLETED BY ADDING LETTER H TO TABULATED P N THE OPTIONAL HOLD DOWNS WILL BE SUPPLIED INTEGRAL W CONNECTOR EXAMPLE HOLD DOWN code tolerances unless otherwise specified 13 E RG tr ar 499 ELECTRONICS near 2005 projection ETT ee casu __ PLUG DOUBLE MODULE 345 Ten eng 374783 size dwg ppc B 1 1 shel pL s index Eq gc form no 7530 001 103 iJ 2 3 euge 22526 4 EMULATION TECHNOLOGY INC Figure A 5 Berg 91294 003 Datasheet Page 3 of 3 A 6 ET5000k10S Schematic The ET5000k10S Schematic is presented on the following pages 5000 105 USER S MANUAL B 1 _ LLL LL 002 vp pesojosip Aue pue 0 Sjubu ejes pue asn uononpoudei jeno uejeudoud dnoJc SL JO 00 0000 7010 0S ayepdn oq INIG 24 Auedoud y 51 pue jeeus JequinN
100. LAVHS 331 01 ute 9z LzXL 34IQ OI US u06 v9 LGX 34IQ OI doLL Z8XL JdIQ ON OI JdIQ ON OI 9 J4IQ OI dre 9z LzXL 3410 01 y 204 envas 9 6 99 9 1 4 10 1 34IQ ON OI 462110 28 4 10 1 J3IQ ON OI ony 27 9 9 1 4514 01 92 61 4 1001 ODIO an 416 59 25 1 3 4410 01 Vu 4IQ OI J4IQ 09 0t OI S USLZJLXL 92 61 4410 01 926 99 6 4410 01 UuLLUES V9XH 4 10 1 dezVLOLIS XL 4410 01 4410 09 09 1 2 Eey 4410 01 JIQ ON OI 91 UZ6 99 ESXL J4IQ OI dLLLXL JdIQ ON ON OI 5 u6zWL0LSZXL 341 01 J4IQ ON ONIOI opg VIVO v U9L 8 8XL J4IQ OI 6 JdIQ ON OI on 426 9 5 1 J4IQ OI ULLLXL JHIG ON ONIOI J4IQ OI u0S XH JJIQ ON ON OI epy 991 8 8 1 J4IQ OI 466 22 02 3414 0 eese QVE qA 4410 01 921 1 58 9 4 10 01 He UOELIZOL ESXH_ J4IQ OI 34IQ ON ON OI 9 151 AYUS ULL6 6XL 4410 01 466 22 02 4410 01 Herp 976 99 34IQ OI UZ
101. LOCK has a pull up This is technically a violation of the PCI specification but we have seen systems from SUN that have the LOCK pin floating Remember that the function of this pin was deleted in the 2 2 version of 5000 105 USER S MANUAL 3 1 011 024 24 C24 A24 C25 B25 D25 B26 A26 D26 B28 C27 A28 A27 B29 C28 C31 B32 D31 A32 C32 B33 D32 A33 D33 A34 C34 B35 D34 A35 C35 B36 C26 A29 A31 B34 D30 D29 B22 D11 B32 C30 C33 A36 C23 A23 D18 C36 A30 B30 G26 C29 D28 D35 C9 A8 D10 B9 C10 A9 C11 B10 D12 A1 C12 B11 D13 A11 C13 B12 D14 A12 C14 B13 D15 B14 C15 A14 D16 B15 C16 B16 D17 A16 C17 B17 A17 C18 B23 D23 4 _ 4 2 lt PCI LADE3 4 AD 4 4 PCI AD 5 4 PCI AD 6 4 PCI jj PCL_ADJ 8 9 10 _________ gt AD 11 __________ AD 12 4 PCI AD 13 AD 14 4 PADIS ADI A P_ADII7 4 PCI AD 18 lt AD 19 lt 20 lt
102. TABLE TITLE PAGE 2 1 ET5000k10S Stuffing Option Comparison 2 3 2 2 Signals and Connections to P4 2 15 2 3 FPGA Serial JTAG Configuration Header 2 16 2 4 JP1 Configuration Jumper Settings 2 21 2 5 Stratix FPGA Approximate File Sizes 2 23 3 1 Present Signal Definitions 3 5 3 2 MGGEN Jumper Descriptions 3 5 3 3 PCIXCAP Jumpers 3 6 3 4 66 and PCIXCAP Encoding 3 7 4 1 Clock Grid Signal Descriptions 4 2 4 2 Header Classification 4 7 4 3 Jumper 5 4 8 4 4 Frequency Range Settings 4 9 4 5 Output Divider 5 4 9 4 6 Time Unit 4 10 4 7 Clock Skew Settings 4 11 4 8 LVPECL Input Specifications 4 11 4 9 Clock OE Pin Jumper Settings 4 13 5 1 Requirements for Non Standard SSRAMs 5 6 5 2 Syncburst and ZBT SSRAM Timing 5 9 6 1 Specification for 43 3 V Power 6 2 6 2 Specification for 42 5 V Power and 1 25 V Reference 6 3 6 3 Specification for 41 5 V Power 6 3 7 1 Connector J8 Pins External Power 7 5 7 2 Daughter Board Header FPGA Pin Map 7 7 ET5000K10S USER S MANUAL i E
103. U14 PLL1A or HDR_CLKOUT Is selected as the input clock If HIGH the U15 PLL2BN U14 PLL1BN pair is selected as the input clock Output Mode If HIGH clock outputs disable to high Z state If LOW clock outputs disable to HOLD OFF mode If MID clock outputs disable to factory test mode Invert Mode When HIGH clocks CCLK 3 0 ECLK 3 0 are inverted When MID these clock outputs are non inverting When LOW the INV2 1 3 Level pairs CCLK 1 0 and CCLK 3 2 ECLK 1 0 and ECLK 3 2 will be complementary FBDIS 2 1 IVTTL LOW Feedback Disable When HIGH feedback is disabled When LOW feedback is enabled RB C F F 1 0 3 Level Output Phase Function Each pair controls the CaP 10511201 phase function of the respective group of 3 Level outputs See Clock Skew on page 10 for more information FB 3 Level Output Divider Function Each pair controls the divider function of the respective group of outputs See Clock Division on page 9 for more information Frequency Select The input specifies the operating range of the nominal frequency See General Control on page 8 more information Feedback Output Phase Function The input controls the phase function of the feedback outputs See Feedback and Clock Multiplication on page 9 for more information 1 FBDS 1 0 2 1 3 Level Feedback Output Divider Function Each pair controls
104. V card Card sizes of 16 32 64 and 128 megabytes have been tested on the ET5000k10S We have not seen 256 MB or larger cards for sale yet but when we do there will probably be an update to the CPLD and processor on our website to support them Table 2 5 Stratix FPGA Approximate File Sizes Number of Configuration Bytes Stratix FPGA SOF for EP1S80 2 954 672 RBF for EP1S80 2 992 071 We get our SmartMedia cards from http www computers4sure com A Delkin Devices 16 megabyte card part number DDSMFLS2 16 sells for about 15 A 32 megabyte card part number DDSMFLS2 32 will set you back about 20 see Figure 2 12 New SmartMedia cards do not require formatting before use NOTE SmartMedia cards do need to formatted before they are used The Windows format command DOES NOT WORK it is necessary to use the FlashPath utility to format a SmartMedia card Do not press down on the top of the SmartMedia Connector J1 if a Smart Media card is not installed The metal case shorts to the 3 3 V power supply and the case gets hot enough to burn your finger We suggest that you leave a SmartMedia card in the connector to prevent this from occur ring A polyswitch fuse F1 has been added so that the PWB and the Smart Media connector are protected if you do accidently press on the top of the connector NOTE Do NOT press on the SmartMedia Connector P58 if a card is not installed ET5000K10S USER S MANUAL 2 23
105. aren t quite sure what the largest size SDRAM DIMM is that will work in the 5000 105 but here is the math as best we understand it 14 Address lines A 13 0 multiplexed between RAS CAS address 10 not used for CAS 27 2 bank address BA 1 0 2 4 chip selects 3 0 used in pairs1 So we think that there are 29 address bits 27 2 and 2 possible chips selects which add one more address bit This totals 30 address bits 1 of 72 bit long words which is 8 Gbytes Please tell us if this math is wrong SDRAM modules require 4 clocks 3 0 These clocks are driven by the Roboclockll 2 and the signal names The CD ROM has a datasheet of an acceptable 1 Gbyte SDRAM module from Micron The file name is SDF36C64 127x72G B pdf 5000 105 USER S MANUAL 5 9 011 5 7 W7 U5 R7 L6 N6 R8 AB8 V6 E5 V8 L3 V7 R6 U8 R5 97 6 T8 P5 T7 N5 M6 K5 8 Y7 P8 P7 V5 U6 L5 K6 M9 T9 94 43 AC8 8 7 5 AL4 AK4 AL8 AL7 AK8 7 AJ8 AJ7 AH8 7 AG8 7 AF8 AF7 AE8 AE7 AD8 AD7 MB8 SDRAM_CKE 0 SDRAM CKE 1 SDRAM CSN 0 SDRAM CSN 1 SDRAM 5 2 SDRAM CSN 3 SDRAM 0 SDRAM BA 1 SDRAM WEn SDRAM CASn SDRAM RASn SDRAM ADDJI0 SDRAM 1 SDRAM ADDI2 SDRAM ADDI3 SDRAM ADDJI4 SDRAM ADDI5 SDRAM ADDI6 SDRAM ADDI7 SDRAM ADDIS SDRAM 00191 SDRAM ADD 10 S
106. bit and the largest blocks M RAM can be configured anywhere from 4 x 144 bits to 64K x 9 bits The embedded memory is dual ported and can be used to construct almost any type of memory FIFOs dual port RAMs single port RAMS etc The two largest blocks M RAM and M4K RAM are fully dual ported memory with read and write functions available on two separately clocked ports M512 RAM is a simple dual port memory meaning that Register chain routing from previous LE LAB wide Register Bypass Synchronous Load Programmable LAB wide Packed 2 Synchronous Register Select Clear LUT chain routing to next LE Row column and direct link routing Synchronous Load and Clear Logic Hr D Row column and direct link routing Local Routing Register chain Hegister output Feedback Figure 2 2 General LE Diagram Carry OutO Carry Out1 LAB Carry Out EMULATION TECHNOLOGY INC ET5000K10S FEATURES OVERVIEW AND GENERAL DESCRIPTION one port is write only and the other is read only Any of the memory blocks can be configured as simple dual port or single port memory See Figure 2 3 for a diagram of the memory Multipliers Stratix devices feature a large number of multipliers grouped into what Altera calls DSP blocks see Figure 2 4 The EP1S80 contains 22 DSP blocks each of which can provide one 36x36 bit multiplier four 18x18 bit multi pliers or eight 9x9 bit multipliers Each block als
107. communication a des tiers interdite sous quelque forme que ce soit sons autorisation ecrite du propietaire Tous droits strictement reserves Propriete de C BERG ELECTRONICS All rights strictly reserved Reproduction or issue to third parties in any form whotever is not permitted without written authority from the proprietor Droits de reproduction BERG ELECTRONICS INC Copyright BERG ELECTRONICS INC Property of C BERG ELECTRONICS PRODUCT NO OF 91403 001 120 1 930 50 35 830 21 08 725 18 42 1 550 39 37 2 150 54 61 1 700 43 18 965 24 51 30 GXT 91403 002 160 2 430 61 72 1 080 27 43 975 24 76 2 050 52 07 2 650 67 31 2 200 55 88 1 215 30 86 30 GXT 91403 003 200 2 930 74 42 1 330 33 78 1 225 31 12 2 550 64 77 3 150 80 01 2 700 68 58 1 465 37 21 30 91403 402 160 2 430 61 72 1 080 27 43 975 24 76 2 050 52 07 2 650 67 51 2 200 55 88 1 215 30 86 60 GXT 200 2 930 74 42 1 330 33 78 1 225 51 12 2 550 64 77 3 150 80 01 2 700 68 58 1 465 37 21 60 GXT OTE 4 050 1 27 C zx 025 0 63 100 2 54 REF 0 015 0 38 00 05 RO 110 R2 79 REF 2X FULL R TYP 410 10 41 0 220 5 58 REF 2X 85 160 4 06 090 2 29 FRAME TO BOARD CONTACT AREA 0 07511 91 0 050 1 27 REF
108. is also connected to the FPGA intended as an input so that the design can check the status of REGE Do NOT drive this signal high when JP7 is jumpered On some SDRAMs the REGE input may be used to select Registered or Non Registered behavior If REGE is high the control signals will go through registers before being sent to the individual DRAMs delaying access by clock cycle but improving fanout if it is low the signals will be passed directly to the DRAMs DDR SDRAM The ET5000k10S has a socket for 184 pin DDR SDRAM DIMM Either a regis tered or unbuffered module fits in the socket J2 The same PC266 PC2100 modules that you put into your PC are used here Your 5000 105 will be stuffed and tested with a 512 MB PC2100 DDR SDRAM DIMM unless other wise specified DIMM pins are connected to the FPGA and the pins are shown in Figure 5 12 and Figure 5 13 The largest DDR SDRAM that the 5000 105 can be stuffed with is 1 GB x 72 8 GB DDR SDRAM modules require three 3 differential clocks CK 2 0 and CK 2 0 these clocks are driven by the FPGA s enhanced PLL6 outputs and the signal names are DDR CLK 2 0 and DDR CLKn 2 0 For further information on Stratix PLL operation see the Altera website at www altera com The Stratx Datasheet 45 stx pda which can be found on the ET5000k10S CD ROM also provides useful information on PLLs DDR SDRAM On Board Options R59 is connected to the wP Write Protect
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110. multiplication 4 9 OE pin jumper settings 4 13 output 2 14 4 8 to 4 9 output signals 2 8 outputs 4 2 4 9 4 13 to 4 14 5 12 5 15 PCI 2 1 PCI CLK 4 14 PLL 5 15 processor signal 2 16 PWB network 2 16 scheme 4 2 signal descriptions 4 2 to 4 3 signals 4 2 4 4 4 11 to 4 12 4 14 5 12 5 15 7 6 I 1 Index Continued skew 4 2 4 9 to 4 10 settings 4 11 speed 2 5 SSRAM 5 1 status reporting 2 14 syncburst 5 6 Clock Utilities Menu 9 6 CLOCKA 4 2 to 4 4 CLOCKB 4 2 to 4 5 CONF DONE TDO 2 14 2 16 configuration 2 1 2 7 2 14 2 19 2 22 9 7 9 9 2 9 bar 9 9 circuitry 4 2 clock 4 3 to 4 4 DDR SDRAM 5 12 debug 9 7 expansion 3 5 file 2 18 2 23 file names 2 20 FPGA 2 1 2 3 2 9 2 14 2 16 2 19 to 2 20 2 22 3 4 headers 2 16 JTAG 2 16 jumper settings 2 21 menu 2 22 PCI CLK 4 14 SDRAM 5 11 to 5 12 serial 2 16 slave serial 2 16 SmartMedia 2 16 2 21 2 23 stand alone 6 3 status 2 22 tab 2 17 via Fast Passive Parallel 2 1 2 16 2 19 via fast passive parallel 2 17 via SmartMedia 2 1 2 3 configuration space 9 2 9 4 9 8 CPLD 2 1 2 3 2 8 2 12 2 14 2 16 2 23 4 2 to 4 4 6 2 CPLD CLK 2 14 CPLD LED 2 14 CPLD TCK 2 14 to 2 15 CPLD TDI 2 14 to 2 15 CPLD 2 14 to 2 15 CPLD 2 14 to 2 15 CPLD TRST 2 14 CPUCLK 2 16 CSF 2 7 2 17 custom daughter cards 2 2 CY7B993V 4 2 4 9 to 4 10 4 12 D D1 7 4 D2 7 4 D3 7 4 DATAO TDI 2 14 2 16 daughter cards 2 2 6 5 7 1 to 7 14 DCLK 2 16 4 3 4
111. of long words to a specific PCI memory location Figure 9 6 Bar Number amp H 5 1 Address fhHBHHHBHH Humbers of long words to write amp in decimal 2 long word to write hex aaaaaaaa long word to write hex 55555555 Loop indefinitely y or n gt Hit a key to continue Figure 9 6 AETEST Write to Memory Test You will be prompted for the memory location in hex The physical address is needed All 4 gigabytes of PCI memory can be accessed A minimum of 1 to a maximum of 1024 long words can be written in sequential order to the same address A looping option is available if you want to use an oscilloscope If you are in a scope loop any keypress will terminate the loop and return you to the main menu Read Memory Test Read a single long word from a specific PCI memory location Figure 9 7 Bar Number amp H 5 Address fhHBBHHHH 1 Display result 2 Displau result and loop indefinitely 3 Don t display result and loop indefinitely Please select Figure 9 7 AETEST Read Memory Test You will be prompted for the memory location in hex The physical address is needed All 4 gigabytes of PCI memory can be read Three options are available 1 Read once and display 2 Read indefinitely and display 3 Read indefinitely and don t display 9 10 EMULATION TECHNOLOGY INC UTILITIES Write Read Test write long word to a specific memory lo
112. oq yous 9 AVI jddng 70L000SNG uonduose 5 siouaghs E 1 aypelg Dd amas nam 5 5 esa ssa 184 esr ooz 103 21 pesojosip Aue oj pue s y6u ejes pue asn 4 jeno uejeudoud se 1ese dnoJc 94 Auedoud s pue 1 Aq pesojosip uoneuuojul 991 gni Lovo 5172881 dnoJs 941 5 2 2591 AG e mm 9602 9602 mn gods dude TS AOL AOL i anyo 4000 F 40001 gt velo 090A 099 AG e butTdnoseq AG 90878 0475 92818 0913 92878 90878 0375 2313 gt 0315 0414 2878 28783 9602 9602 9602 9602 9602 9602 9602 9602 9602 9602 9602 9602 AOL AOL AOL AOL AOL AOL AOL AOL AOL AOL AOL AOL ANOOL 4000 4
113. pdf and ATmegal28_DS pdf But if you intend to use the pP for your own purposes you should check the Atmel web page to get a copy of the latest user s manual datasheet and erratas The Atmel web page is http www eu atmel com atmel The ATmega128L is under the section called Flash Microcontroller AVR 8 Bit RISC Most of the features are unused A variety of test headers allow for possible use of these features Each header and the various possible functions are described in the sections that follow Figure 2 6 is a block diagram of the ATmega128L and its various interfaces on the ET5000k10S 5000 105 USER S MANUAL 2 9 T5000K10S FEATURES OVERVIEW AND GENERAL DESCRIPTION 3 Noise Conditioner JP1 Config JMPR 2 0 Jumpers RS232 Level Translator RS232 Connector LLL ICL3221 2 4 Smart Card EIE Inserted Programming Header P5 Reset P4 Programming Header Rev 5 30 03 P O avcc j TAG Pose CSF A D Inputs or FWRTSM User FPGA 911 General 7 Atmel AVR ATmega128L uP 128kbytes FLASH 4kbytes SRAM 4kbytes EEPROM U4 5V 05 3 3 4154 Reset amp Power Threshold Detection S1 uP LED 3 0 Figure 2 6 ET5000k10SBlock Diagram ATmega128L and ET5000k10S Interfaces P1 Unused Connections 2 10 P1 contains connections to the ATmega128L that were not used else where These te
114. pictured in Figure 7 2 Figure 7 3 shows the assembly drawing of the ET3k10SD Daughter Card The ET3k10SD Daughter Card provides 16 differential pairs 48 buffered passive active I O and 66 unbuffered signals The IDT74FST163245 chips are used as bus switches in the passive mode and the 5000 105 USER S MANUAL 7 1 DAUGHTER CONNECTIONS ET3K10SD OBSERVATION DAUGHTER CARD FOR 200 PIN CONNECTORS DIFFERENTIAL BCLK1 CCLK1 ECLK1 95 MBCK6 J3 J4 J5 J6 J7 50 PIN IDC HEADER UNBUFFERED 00 17 92 DIFF PAIR 0 15 J6 UNBUFFERED I O 0 23 50 PIN MINI D RIBBON CABLE CONNECTOR Jf UNBUFFERED 0 23 LINEAR REGULATOR 12VDC TO 3 3V J1 POWER INDICATORS BUFFERED 0 15 U1 UNBUFFERED 0 15 3 9VDC 3 3 5 0 12 0 93 BUFFERED I O 0 7 POWER U2 UNBUFFERED 10 0 15 HEADER BUFFERED 007 0 7 3154 3 3 J4 5 0 412 0V J6 BUFFERED 0 0 15 U3 UNBUFFERED I O 0 15 12 0V GND 20 PIN IDC 74LVC16245APA 200 PIN MICROPAX HEADER 74FST163245PA U1 U2 U3 BUFFERS OR LEVEL TRANSLATORS BOTTOM OF PWB Figure 7 1 ET3k10SD Daughter Card Block Diagram 7 2 EMULATION TECHNOLOGY INC 14 pom 3 mur 19 Ie a E EDI ME a 5 os m n e
115. schematic shows capacitors in positions C380 C381 C382 and C383 The ET5000k10S has 0 ohm resistors in these capacitor positions The termination resistors 206 211 R207 R212 R209 R198 and R214 R210 are not stuffed The 5000 105 gives the user a simple means to bring off board clocks onto the board The user can attach 10 pin ribbon cable to rows B and C of the Clock Grid JP6 B consists of an input to 3807 1 and differential pair inputs to both Roboclockll s JP6 C consists of ground pins for signal integ rity These signals are described in Table 4 1 on page 2 BUFINA is a stan dard 3 3 V TTL input EMULATION TECHNOLOGY INC CLOCKS AND CLOCK DISTRIBUTION WITHOUT 10 PIN RIBBON CABLE JP6 B J P6C CLKOUT JP6 7 CLOCKA JP6 13 CLOCKB JP6 1 goes to goes to goes to Roboclock 2 may PLL1A JP6 10 BUFINA JP6 14 BUFINB JP6 4 be driven by Roboclock 1 Roboclock 2 may 2 BUFINB JP6 4 BUFINA JP6 14 PLL1BN JP6 2 be driven by Roboclock 1 BUFINA JP6 14 PLL1BN JP6 2 3 PLL2BN JP6 8 20 Buffer is undriven PLL1A JP6 10 BUFINB JP6 4 PLL2B JP6 11 requires wire wrap BUFINA Buffer A amp BUFFINB gt Buffer 9 PLL1A Roboclock1 DCLK PLLSEL1 low PLL1B 3 Roboclocki 9 CCLK DCLK PLLSEL1 high PLL2B 9 Roboclock2
116. the divider function of the feedback outputs See Feedback and Clock Multiplication on page 9 for more information General Frs 2 1 isa3 Level input which determines the allowable range for the Control operating frequency of the device Depending on the chip grade the PLL can operate between 12 100 MHz or 24 200 MHz The actual 4 8 EMULATION TECHNOLOGY INC CLOCKS AND CLOCK DISTRIBUTION frequency can be determined by setting all jumpers to their defaults Thus Will be seen on all of the divide by one clock outputs The user can set FS accordingly The Frequency Range Settings are shown in Table 4 4 Table 4 4 Frequency Range Settings CY7B993V CY7B994V 5 2 1 MHz MHz Feedback First of all 5 2 1 must be set LOW enabling feedback The feed Clock Pack output is looped back to the feedback input When a divided output 1 is applied to the feedback input the VCO voltage controlled oscillator of Multiplication the PLL aligns the feedback input with the original input clock Thus with 10 MHz input clock and the feedback outputs set to divide by 2 must be 20 MHz Consequently 10 MHz is seen on the feedback output clocks and can be aligned with the input clocks The feedback clock divider function actually serves as a clock multiplication mechanism for the oper ating frequency The divider function and the clock skew function are set in the sa
117. the values from the file This is useful for hot swap ping devices power switch still required on extender or reinitializing a device when its configuration has been altered WARNING Because the PCI BIOS is not assigning the BARs for this device you may induce a memory conflict by using this option This option is for advanced users only Save Bar Configuration to File Writes PCI Device ID Vendor ID and the BARS into a file from the active device This option is for advanced users only Memory memory menu Figure 9 5 allows you to perform a variety of tests of PCI memory along with some 5000 105 specific tasks ASIC Emulator PCI Controller Driver 42 1 Write Duord Same Address gt 25 Head Duord Same Address 35 Wreite Read Duord Same Address gt 4 gt Memory Fill 5 BAR Memory Write 8 Memory Display c memory test on 55 i d memory test 55 2 e memory test on 55 3 f memory test on g full memory test including blockram gt memory test on FPGA block memory p bar memory range test k har memory address data bitwise test SRAM memory test gt Main Menu Q Quit PGI BASE ADDRESS BHABHA 1 HHHBHHHBH 2 5 BEAR HAHAH 4 HHHHHHBH Please select option Figure 9 5 AETEST Memory Menu 5000 105 USER S MANUAL 9 9 UTILITIES Write to Memory Test write a selected number
118. there is a valid SmartMedia card inserted properly in the socket If there is not a valid SmartMedia card in the socket then UP_LED 3 0 will flash see Figure 8 2 on page 8 3 for LED descrip tions and the Main Menu will appear from the serial port A SmartMedia card is determined to be invalid if either the format of the card does not follow the SSFDC specifications or if it does not contain a file named main txt in the root directory If the configuration was successful a message stating so will appear and the Main Menu will come up Other wise an error message will appear The LEDs on DS1 and DS2 give feedback during and after the configura tion process see LEDs on page 3 for further details After the FPGA has been configured the following Main Menu will appear on the serial port 1 Configure 8 using main txt ET5000K10S USER S MANUAL 2 21 T5000K10S FEATURES OVERVIEW AND GENERAL DESCRIPTION Interactive FPGA configuration menu Check Configuration status Select file to use in place of main txt List files on SmartMedia SEE c 25 18 Select FPGA to program via JTAG Description of Main Menu Options 1 Configure FPGAS Using main txt as the Configuration File selecting this option the FPGA will configure in Fast Passive Parallel mode You can also press the reset button S1 to reconfigure the FPGA in Fast Passive Parallel mode 2 Interactive FPGA configuration menu This opti
119. 0 s cV gt zWvss 96d 59 PNW 0404 89 i cV 1701 y 9800 0 y 920d on zWvus 9 geng 27 VA ac eod gt 17040 znvus 2810 5 EY peng 99 2700004 go 2208 PAS 200 ge 208 2 C 2 z oleod zWvss 96d epg 401800 LEV VAY SOC _ OV OV oly INCONNU WVHSS 71 orn 71 yueg 0 1 9 XINL vVINVHSS 9 XINL CINVHSS 3 00 440 110096268 54 001440 1009 268 3 ZZ 6 5 5 L9 ssa L5 L9 UJO ENVAS Ol _ ___ _ 5 4 uo 9087 230 MOL 02 ssa A ssa L4 1 6 99 ssa 9 4 9 28 uMO tWVHS i 000 ___ _ SSA 9 2 1 2 5 s
120. 0 74 42 1 330 33 78 1 225 31 12 2 550 64 77 3 150 80 01 2 790 70 87 1 465 37 21 50 OPTIONAL 2 430 61 72 1 080 27 43 975 24 76 2 050 52 07 2 650 67 31 2 290 58 16 1 215 30 86 30 SEE CAPS INSTALLED NOTE 6 ON CONNECTOR 2 430 61 72 1 080 27 43 975 24 76 2 050 52 07 2 650 67 31 2 290 58 16 1 215 30 86 60 GXT 200 2 930 74 42 1 330 33 78 1 225 31 12 2 550 64 77 3 150 80 01 2 790 70 87 1 465 37 21 60 GXT 011 CAPS SUPPLIED LOOSE PIECE 2 430 61 72 1 080 27 43 975 24 76 2 050 52 07 2 650 67 31 2 290 58 16 1 215 30 86 30 CXT gt 23 gt 2 23 ci 91294 4135 NOTES 1 MATERIALS DIELECTRIC LCP CONTACTS PHOS BRONZE FRAME ZINC ALLOY 3 2 PLATING SOLDER TAILS 150 u 3 81um Sn Pb FRAME 150u 3 81um BRIGHT TIN CONTACTS 30u 76um OVER 50u 1 27um Ni OR 60u 1 52um OVER 75u 1 90um 3 WHEN CONNECTOR IS MATED WITH HALF THE PARALLEL BD TO BD HGT IS 47 01 APPLYS TO VERT THRU amp SURFACE MT STYLES 4 THE SOLDER TAILS ON THIS PRODUCT DESIGNED TO BE COMPLIANT IN ORDER TO ACCOMMODATE PRINTED CIRCUIT BOARD DIMENSIONAL VARIATIONS THEREFORE HOLDDOWN HARDWARE 1 REQUIRED TO SECURE THE CONNECTOR TO THE PRINTED CIRCUIT BOARD FOR MOST TYPES OF SOLDER REFLOW OPERATIONS FOR FURTHER APPLICATION OATA INCLUDING HOLE SIZES FOR VARIOUS TYPES OF
121. 000 F 4000 Az 100 gt 4000 FE 4000 F 40001 4100 4000 4000 41001 6519 OvLO 612 2430 189 210 eco AG e AC et oma 0813 ona 0818 awo L amro 02 9602 9602 9602 AOL AOL AOL AOL ANOOL ANOOL 40001 40001 OOOA 0012 922 89 029A I 499 7219 AG e INVI INVI 9602 9602 Anos 27 anos 2510 16 AG 3900 L 389 91 56086141 Jn 0 0 INVL INVI INVI INVI E 9601 9601 9601 9601 AOL AOL AOL AOL gt 4000 SS 4000 SF 4 00 282 4010 ISLO 910 99 9719 AS VOL 5 SvcH _ 980111 rav lino NIA AG JOSUUOD 9JoN V AS L ddng 18 Mog Jeauly 3nduj 2 gt 5 5 S 55 Glossary and Acronyms BIOS CMOS CPLD CSF
122. 000K10S FEATURES OVERVIEW AND GENERAL DESCRIPTION Optional Serial Shift Register Inputs from Previous DSP Block N Multiplier Stage Optional Stage Configurable D Q as Accumulator or Dynamic Adder Subtractor ENA CLRN x Q 2 CLRN Q Output Selection Multiplexer Adder Subtractor Accumulator 1 D Q 2 CLRN Q c Optional Output Summation Stage Register 51406 for Adding Four Multipliers Together Adder Subtractor Accumulator 2 Optional Serial Shift Register Outputs to Next DSP Block in the Column Y Optional Input Register Stage with Parallel Input or Shift Register Configuration Optional Pipeline Register Stage to MultiTrack Interconnect Figure 2 4 DSP Block Diagram 2 6 EMULATION TECHNOLOGY INC ET5000K10S FEATURES OVERVIEW AND GENERAL DESCRIPTION Figure 2 5 also shows more detail about the optional shift register path which makes FIR or IIR filters easy to implement Most synthesis tools will accept Verilog or VHDL descriptions of multpliers and infer a DSP block with the appropriate configuration For those that don t Altera provides a megafunction generator to help with direct instantiation of the hardware resources See Synthesis and Emulation Issues on page 24 for more detail Issues Terminator technology is supported on all pins The resistors used for RDN and RUP should be 250 ohms for series termination or impedan
123. 029 029 029A 029 osal 04 502 0502 042 esid 158 05606 1545 2 AY 04 013 Sy md M Odv 51084 199 05084 0484 10100 54 4454 Vd3H 353 84 42920904 6 164 lt 6 E zoot osos 6 E LMOOT 15577585 eroon D V U OE 6 D 0brToG 628d C Dem 0105 6 6d le obnoa em obriog 6 6d c obriov Dem 27 0804 6 154 ona Had 0c 11 9c o o7 8154 07 22 ov 09 59 59 00 lt 51 57 __ 72 22510 57 q 5 0504 13384 03484 9v AN 151 22510 7 2201 q J 05 gH I 03384 25 dg Eoo gg SO osag N n 7 TOY Jeduunf 412995 42015 21 129 5253 SNH 22 6SNY 17007
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125. 0804 29 28 2024 S 9004 84 0 000 ejes pue asn uononpoudei jeno aus uejeudoud juejed dnoJc GL jo Z 00 0000 7010 209 ayepdn Ajjenuew oq INIG dnog y si pue AG jeus pajejeuac pesojosip 52019 yoLoosna d045 INIG 1 or VV 594 ezsid M 17 1155354 NOL QNO Ol 294 QNO Ol QNO Ol 290 QNO OL sjeduunf 7 20 50qoy 66 0 092A 092A brio S08 10J6vld NOW 829 1019 i SEE SU 7044 99 _ 20088 YEE 6044 LOJN 194 o 9dL zvo Vu SIE 0024 SSH OMIOVH ein qq 0500 0 S0cH NODA NODA NODA NOOSA NODA NODA NODA pa 34 4 zi o 280 830 8
126. 0Q 08 09 0v O eras 8LOQ 08 09 0 OI 18 01 08 09 0 1 08 09 2N OI 8 9 rr 980 08 09 0 1 y teg 08 09 0 1 79600 08 09 0 9 1 08 09 ON OI 8 08 09 remy usvo waa gt 08 09 0101 08 09 9 1 08 ON ONIOI S860Q 08 09 0v OI USVO 08 09 ON OI 08 ON ON OI d 08 ON ON OI 08 09 0 1 08 09 09 1 08 09 09 rex w 08 09 0v OI 986001 08 09 09 eny 08 09 09 1 08 09 09 9999 08 0008 09 0 1 08 09 09 08 2 0809001 etr ug 08 09 0v Ol 186001 08 09 09 1 sgy 08 09 0v OI 08 09 ON OI y 8 0 9 08 09 y 0900 08 09 08 ONIONIO rey O8 ON ONIOI 08 09 ON OI 9 1 08 09 0101 08 09 re 28200 08 09 07 01 08 08 ns 8200 08 09 07 0 08 09 09 1 er 09 09 0t OI 08 09 0v OI 08 09 2N OI 08 09 05 1 i 8 500 08 09 07 01 08 09 09 1 gen 2820 0 08 09 07 08 09 Harpy 08 09 0 1 08 09 09 etsy 08 09 8 eddy 7 8 0Q 08 09 0v OI 08 09 09 y 82800 08 09 07 01 08 09 2N OI g 08 ON ON OI
127. 1 LI LI LI LI LI LI LI LI LI LI LI LI LI LI GND GND GND GND GND GND GND 0 0 A 0 40 0 60 LJ LJ LJ 54 LJ LJ LJ LJ 0 0 A 0 On 8 DO 00 0 204 C 5 1 11 LO 11 11 ED t m m m m m m en en en en en en en en en 11 44 EBEBEB T L LL LL LL LL LL LL LL LL LL LJ 11 1 1 LL LL LL LL TEILE LL LL LL LL LL LL LL LL LL L LL LJ L LL LL LL LJ LL LL LL LL LJ ab E 117211 1111 ol LEELEE E lol 2111 EL 11111111 4 2 4 2 2 2 o z z 2 2 O Ki m Lupo Om 9 alob
128. 1 inclk O DDR CLKIO DDR DDR SDRAM DDR CLKI2 DIMM DDR CLKnIO DDR DDR CLKnI2 Figure 5 14 DDR PLL Circuit Block Diagram To make the three positive differential output clocks differential the IO STANDARD for all three clock signals needs to be set to DIFFERENTIAL SSTL 2 The Board level PLL clock output is used for the feedback and needs to have STANDARD set to SSTL 2 CLASS The input clock to the must have its STANDARD setto SSTL 2 CLASS For infor mation on how to set the TO STANDARD property please see the Quantus help files If the 10 STANDARD properties are set up correctly then the three negative differential clock signals 008 CLKn 2 0 will automati cally be output from the FPGA You do not need to include these negative clock signals in your FPGA HDL code or pin assignment file To change which clock goes to the DDR the user just needs to change the position of the jumper on JP4 Please note there should only be one jumper 4 The DDR Clock Select Jumper is illustrated in Figure 5 15 JP4 ACLK1 DDR PLL LK lx DCER NR DDR CLK ETER Figure 5 15 DDR Clock Select Jumper JP4 Pg7 DDR_CLK gt ET5000K10S USER S MANUAL 5 1 5 16 EMULATION TECHNOLOGY INC POWER SUPPLIES AND POWER DISTRIBUTION Chapter 6 Power Supplies and Power Distribution The 5000 105 can be hosted in a 3 3 V PCI slot or it can be used st
129. 11 FBDIS 4 8 to 4 9 FBDS 4 8 to 4 9 FBFO 4 8 4 11 5000 105 USER S MANUAL FCLKOUT 4 8 4 14 FPGA 2 14 CPLD TMS 2 14 DIP1 0 2 14 FPGA CDONEF 2 14 FPGA CEnF 2 14 FPGA CSnF 2 14 FPGA D 2 14 FPGA DCLK 2 14 FPGA IODONEF 2 14 FPGA MSEL 2 14 FPGA nCONFF 2 14 FPGA RDYnBUSYF 2 14 FPGA CDONEF 2 14 FPGA CEnF 2 14 FPGA CSnF 2 14 FPGA D 2 14 FPGA DOF 2 14 FPGA DCLK 2 14 FPGA_GRSTn 2 14 FPGA IODONEF 2 14 FPGA MSEL 2 14 FPGA nCONFF 2 14 FPGA RDYnBUSYF 2 14 FS 4 8 to 4 10 4 12 GCLKOUT 4 13 to 4 15 GND 2 15 2 17 4 3 4 11 7 5 7 7 to 7 14 GW 5 9 HDR CLKOUT 4 8 INTB 3 4 INTC 3 4 INTD 3 4 INV1 4 12 INV2 4 8 4 12 JTAG CONF_DONE TDO 2 14 2 16 CPLD 2 14 to 2 15 CPLD_TDI 2 14 to 2 15 CPLD TDO 2 14 to 2 15 CPLD TMS 2 14 to 2 15 CPLD TRST 2 14 DATAO TDI 2 14 2 16 DCLK TCK 2 14 2 16 nCONFIG TMS 2 14 2 16 nSTATUS 2 14 2 16 TCK 2 14 to 2 16 3 4 TDI 2 14 to 2 16 3 4 TDO 2 14 to 2 16 3 4 TMS 2 14 to 2 16 3 4 TRST 3 4 LD 5 9 LOCK 3 1 MODE 4 8 nCONFIG TMS 2 14 2 16 nSTATUS 2 14 2 16 7 6 PCI 3 3Vaux 3 4 INTB 3 4 INTC 3 4 INTD 3 4 LOCK 3 1 PCI Signals CE 5 9 CE2 5 9 PCI CLK 4 13 to 4 14 PCPLD CLKOUT 2 14 PLL1A 4 2 to 4 3 4 8 PLL1B 4 11 PLL1B PRE 4 3 PLL1BN 4 8 4 11 PLL1BN PRE 4 3 to 4 4 PLL2B 4 11 to 4 12 PLL2B PRE 4 3 PLL2BN 4 8 4 11 to 4 12 PLL2BN PRE 4 3 PLLSEL2 4 8 PWR RSTn 2 14 RAS 5 9 RB C F F 4 8 REGE 5 12 Reset FPGA GRSTn 2 14 PWR
130. 2 1 2 3 2 25 EP1S80 2 1 to 2 5 2 13 2 23 2 25 256 2 14 ESD 1 1 extender card 3 1 external memories 2 2 5 1 Fast Passive Parallel 2 16 to 2 17 2 19 2 21 to 2 22 FBDIS 4 8 to 4 9 FBDS 4 8 to 4 9 FBFO 4 8 4 11 FCLKOUT 4 8 4 14 feedback disable 4 8 5000 105 USER S MANUAL feedback output divider function 4 8 feedback output phase function 4 8 FLASH 2 1 2 3 2 9 2 11 2 13 9 6 FlashPath 2 21 2 23 to 2 24 flowthrough 5 1 5 6 to 5 8 FPGA 1 2 2 1 2 3 2 8 to 2 9 2 13 to 2 14 2 16 to 2 17 2 19 to 2 23 2 25 3 1 3 4 to 3 5 4 13 4 15 5 9 5 12 5 15 6 2 to 6 3 7 7 9 1 9 6 9 13 pin connections 3 2 pin map 7 7 FPGA D 2 13 FPGA F 2 20 to 2 21 FPGA CDONEF 2 14 FPGA CEnF 2 14 FPGA CSnF 2 14 FPGA D 2 14 FPGA DOF 2 14 FPGA DCLK 2 14 FPGA GRSTn 2 14 FPGA IODONEF 2 14 FPGA MSEL 2 14 FPGA nCONFF 2 14 FPGA RDYnBUSYF 2 14 frequency select 4 8 FS 4 8 to 4 10 4 12 FT See flowthrough G GCLKOUT 4 13 to 4 15 2 15 2 17 4 3 4 11 7 5 7 7 to 7 14 GW 5 9 H HDR CLKOUT 4 8 header clocks 4 15 HyperTerminal 2 13 2 18 impedance 2 7 input clock select 4 8 INTB 3 4 INTC 3 4 I 3 Index Continued INTD 3 4 Interconnect 7 7 9 2 interconnect 9 2 Interconnects 7 7 INV1 4 12 INV2 4 8 4 12 J J1 2 23 7 7 J10 7 7 J16 7 7 J19 5 10 to 5 11 42 5 12 6 2 J3 5 9 6 2 J8 4 2 4 5 7 5 J9 7 7 JP1 2 21 JP10 4 2 4 5 4 7 JP11 4 2 4 5 4 7 J
131. 2 nor X3 are used by the configuration circuitry so the user is free to stuff any standard 3 3 V half can oscillator in the X2 and X3 positions more detail later in Customizing the Oscillators on page 12 The Clock Grid can also accept a 5X2 ribbon cable This cable can provide input clocks to both of the Roboclockll s and one of the 3807 buffers The FCT3807 clock buffer provides a high speed 1 to 10 buffer with low skew 0 35 ns allowing clocks A ACLK 9 0 and BCLK 9 0 to be distributed point to point The two Roboclockll PLL clock buffers U14 and U15 offer functional control of clock frequency and skew among other things They are configured via header arrays J8 JP10 JP9 and JP11 The ET5000k10S comes from the factory stuffed with CY7B994V which can operate at frequencies from 24 MHz to 200 MHz They can also be stuffed with CY7B993V which operate from 12 MHz to 100 MHz Note Output frequency can be as low as 1 MHz depending on the operating frequency see below for details Each chip has 16 output clocks along with 2 feedback output clocks Two sets of eight output clocks are jumper selectable for each chip The feedback clocks are controlled separately The PLL clock buffers can accept either 3 3 V LVTTL or LV Differential LVPECL reference inputs The devices can operate at up to 12x the input frequency while the output clocks can be divided up to 12x the operating frequency Phase adjustments can be made in 625 ps o
132. 310 01 9694 d3IQ ON ONIOI re 08 09 09 1 Ez 08 09 08 09 0N OI 1 6 66 92 1 3310 01 gt 46999 3JIG ON OI H 08 09 ON OI dod gt 9180001 08 09 0 6 66 92 1 3310 01 J4IQ ON OI bg 19 9150 01 m 08 09 9 08 09 09 s 5 ora 4IQ 09 0v O AV O8 ON ON OI 8 9 51800 01 08 ON ONIOI 1 3 6vIVvVEXM 3310 01 Ko 0 3HIQ O9 0v OI H q S1 0q 0I gt 11000101 Lar 08090980 O 08 09 2NIO rey 0 09 22 1 3410 01 JIQ ONIOI n 08 09 07 01 08 09 09 1 0 lt gt 800 01 11800 01 be 08 05 20 1 441001 04 8X 441Q ON OI 1 9LOOG O Pag 08 09 2N OI 5 08 09 0v O 4410 01 uL XL 34IQ ON ON OI 09 ON ON OI 8 9 bee d 64 udOlS 104 lt C gt 1809 01 91600 01 be 908 29 4410 01 34IQ ON ON OI zry 51600 100 01 Hoy 08 09 0 8 9 821 4410 01 JdIQ ON ON OI 151 08 09 2N OI 08 09 0 lt gt seq 48850001 81800101 zu 3alg ol d 2x4 34IQ ON ON OI 1 SOQ OI 100001 fg
133. 4 TP13 3 5 TRST 3 4 U U1 2 9 7 6 U10 5 3 6 2 U11 2 3 4 13 6 2 to 6 3 7 7 U12 6 2 U13 5 1 5 5 6 2 U14 4 2 4 8 4 13 6 2 U15 4 2 4 8 6 2 U16 6 2 U17 6 2 U18 6 2 U2 2 17 7 6 U3 7 6 04 2 9 6 2 7 4 to 7 5 U6 5 1 6 2 U7 6 2 08 2 12 5 1 5 4 6 2 U9 5 1 to 5 2 6 2 UP ALE 2 14 UP RDn Signals UP RDn 2 14 UP WRn 2 14 UPAD 2 14 UPPADDR 2 14 V VCC 2 17 Vendor ID 9 7 to 9 9 verbose level 2 19 to 2 22 Verilog 1 2 2 2 2 7 2 14 2 17 2 24 VHDL 1 2 2 2 2 7 2 24 Virtex 2 13 voltage 2 8 2 10 4 11 6 2 7 5 board termination 2 8 differential 2 8 4 11 reference 2 8 6 2 to 6 3 5000 105 USER S MANUAL sources 5 supply 6 2 to 6 3 termination 2 8 translation 2 17 voltage controlled oscillator 4 9 W WP 5 11 to 5 12 X X1 2 16 4 1 to 4 2 6 2 X2 4 1 to 4 2 4 12 to 4 13 6 2 X3 4 1 to 4 2 4 12 to 4 13 6 2 Xilinx 2 9 Z ZBT 5 6 5 8 to 5 9 1 9 1 10 EMULATION TECHNOLOGY INC
134. 4410 01 y d9 XL 33IG ON ON OI 96 0 25 1 34IQ OI 9911 28 89 4 10 1 UgeL SOL 98XY_44IG O 4IQ ON ON OI 3310 01 Lees S 89241 ddIQ ON ON OI 4 6 69 08 4 10 01 48 99Xel JJIQ OI 90 6 1 34IQ O e JJIG ON ONI OI doz zLSXs 319 01 9 2 JIG ON ON OI 6 69 09 5510 01 poy 98 19 1 4510 01 3414 01 Hegy zoq 44IQ ON ON OI 77 4 3JIQ ON ON OI 426 2 89 1 3414 01 911 98 9 1 33IQ OI 9 1 901 08 1 34IQ OI Heese 22 AVuS 3dIQ ON ON OI J4Iq ol LSL 7 4 JJIQ 2N ON OI 6 1 88 1 33IQ OI 34IQ OI L 901 09XL 33IQ OI sey 34IQ ON ON OI 4 10 01 gem 91151 JdIQ ON ON OI 986 0 9 4410 01 2500 U911 98 69X4 4IQ OI dse 40V L9XL 34IQ O gare 8 JJIQ ON ON OI 34IQ OI E 982 4 JdIQ ON ON OI 86 0 9 3310 01 9911 28 89 1 J4IQ OI 466 201 18 4410 01 JdIQ ON ON OI 4410 01 pray gr 34IQ ON ON OI 486 2 66 17 J4IQ OI gt dM 914 28 89 1 3310 01 JIQ OI
135. 5 2 0093 DQd3 lt 9 2 0094 0094 lt 5 2 0095 0095 lt 5 2 0096 0996 lt 2 0097 0097 lt SRAM2 DGPa DQPa SRAM2_DQPhb lt 5 2 DGPc DQPc lt lt 5 2 DQPd Figure 5 2 SSRAM 2 010 Bus Signals ET5000K10S USER S MANUAL SSRAM 3 08 SRAMS3 lt _ 1 SA1 lt 5 2 5 2 lt 5 lt 5 A4 5 4 5 5 5 SA6 5 7 SA7 lt SRAM3_A8 SA8 A 9 SA9 lt 10 SA10 lt lt 5 11 SA11 12 12 A SRAMS 13 SA13 SRAM3_A14 14 lt 15 5 15 16 SA16 17 17 lt 5 18 5 18 lt 19 SA19 expansion lt 5 ADVn ADV lt _ 5 ADSP lt SRAM3_ADSCr ADSC lt BWAn BWA lt SRAM3 BWBn BWB lt SRAM3 BWCn BWC lt SRAM3 BWDn
136. 5 lt 0080146 lt 0080471 lt 0080148 lt DDR 0149 lt DDR D 50 lt DDR 0 51 lt DDR D 52 lt DDR D 53 lt DDR D 54 lt lt DDR D 55 lt DDR D 56 lt DDR D 57 lt 0080158 lt _ DDR D 59 lt DDR D 60 lt DDR D 61 lt DDR D 62 lt lt DDR D 63 Continued 14 DDR DATA 0 gt RN14 RN16 RN16 RN14 RN14 RN16 RN18 RN18 RN20 RN20 RN18 RN18 RN20 RN20 RN22 RN22 RN24 RN24 RN22 RN22 RN24 RN24 RN26 RN26 RN28 RN28 RN26 RN26 RN28 RN28 RN35 RN35 RN37 RN37 RN35 RN35 RN37 RN37 RN39 RN39 RN41 RN41 RN39 RN39 RN41 RN41 RN43 RN43 RN45 RN45 RN43 RN43 RN45 RN45 RN47 RN47 RN49 RN49 RN47 RN47 RN49 RN49 DDR_DATA 1 gt DDR_DATA 2 gt DDR_DATA 3 gt DDR_DATA 4 DDR_DATA 5 gt 6 44 DDR DATA 6 DDR DATA 7 gt DDR DATA 8S gt DDR DATA gt DDR DATA 10 DDR DATA 11 gt DDR DATA 12 gt DDR DATA 13 gt DDR DATA 14 gt DDR DATA 15 gt DDR DATA 16 gt DDR DATA 17 gt DDR DATA 18 gt DDR DATA 19 DDR DATA 20 DDR DATA 21 DDR DATA 22 gt DDR DATA 23 gt DDR DATA 24 gt DDR DATA 25 DDR DATA 26 DDR DA
137. 5 see Figure 2 8 Programming A cable used to reprogram the ATmega128L is shipped with the the 5000 105 You will need to reprogram the ATmega128L if we update the code or you intend to use the processor for your own application P5 ATmega1 28L is used for this purpose 08 Figure 2 9 illustrates P5 3 3V ISP R117 0 P5 BRXD PWRRSTn 6 STXL 10 J Figure 2 9 P5 Schematic Detailed Instructions 1 Download the latest update for the processor and CPLD at www emulation com file uP_CPLD zip 2 You will first need to reprogram the CPLD Please see CPLD EPM3256A on page 14 for instructions use the file jed that can be found in the downloaded zip file 3 Next you will program the processor ATmetga128L Connect the cable that was shipped with the 5000 105 to header P5 with the red purple wire on the cable connected to pin 1 and connect the other end to the serial port of your PC 4 n order to program the processor you will need to install AVR Studio that is included on the CD that was shipped with the 5000 105 This software can also be downloaded at www atmel com 5 From the Windows START menu choose 5 gt AVR Stu dio x xx where x xx is the version number 6 Once AVR Studio is open select TOOLS gt STK500 AVRISP JTAG ICE and a new window should appear with the title STK500 At the bottom of the STK500 window if you see Detecting FAILED t
138. 8 4 11 4 14 to 4 15 7 11 DCLK TCK 2 14 2 16 DCLK 7 R 4 14 to 4 15 DDR clock select jumper 5 12 5 15 DDR SDRAM 2 3 2 8 4 13 5 12 DIMM 5 1 5 12 6 2 DDR CLK 5 12 DDR CLKn 5 12 debug 2 1 9 1 to 9 13 analyzer based 9 1 to 9 13 Device ID 2 19 9 4 9 7 to 9 9 differential LVDS pairs 7 1 DIMM 5 1 5 9 5 12 6 2 DIP1 0 2 14 DIR 7 6 divider function 4 8 to 4 9 settings 4 9 DLL 7 1 DN3000k10 Fequently Asked Questions 1 1 Technical Support 1 1 DN3000k10SD 2 2 7 1 to 7 14 DN5000k10S 1 1 3 1 4 2 1 5 Power 6 3 2 5 Power 6 2 3 3 Power 6 2 2 9 ATmega128L 2 12 to 2 13 block diagram 2 2 clock scheme 4 1 DDR SDRAM 5 12 description 2 2 dimensions 3 4 Fast Passive Parallel configuration 2 21 features 2 1 FPGA 2 3 2 17 2 20 FPGA configuration 2 9 Issues 2 7 JTAG interface 2 12 EMULATION TECHNOLOGY IN Index Continued LEDs 8 3 memories 5 1 oscillators 4 2 4 12 PCI 3 1 PCI X 3 1 pipeline SSRAM 5 6 power supplies 6 1 reset 8 1 ribbon cable 4 4 SDRAM 5 9 Serial Port 2 17 to 2 18 SmartMedia 2 23 SSRAM 5 1 stand alone operation 6 3 to 6 5 stuffing options 2 3 synthesis 2 25 timing devices 4 4 to 4 5 DNPCIEXT S3 3 1 DOS 9 1 to 9 3 9 6 DOS extender 9 2 drive power connector 6 3 DS1 2 21 4 9 DS2 2 21 DSP 2 3 2 5 2 7 dual port 2 4 to 2 5 E ECLK 4 8 4 11 to 4 14 5 1 5 9 7 7 7 11 EEPROM 2 11 5 11 to 5 12 embedded memory 2 1 2 4 2 25 EP1S40 2 1 2 3 EP1S60
139. 99999999 l Display result 2 Display result and loop indefinitely 3 Don t display result and loop indefinitely Please select Figure 9 11 AETEST Write Read Memory Byte Memory test on 55 Tests one of the SSRAM chips on the ET5000k10S Memory test on SSRAMA Tests one of the SSRAM chips on the ET5000k10S Memory test on SSRAMS Tests one of the SSRAM chips on the ET5000k10S Memory test on SDRAM Tests the SDRAM chip on the ET5000k10S Full Memory Test Including BlockRAM Tests all of the memories This includes the SSRAM chips the SDRAM and the BlockRAM internal to the FPGA Memory test on FPGA block memory Tests the BlockRAM inside the FPGA On the ET2000k10 the BlockRAM is only in FPGA F BAR memory range test Generic memory test that prompts the user for BAR number starting address offset DWORD count and number of iter ations The user is also prompted if the program should stop if error occurs or if the program should display any errors that occur This allows for maximum flexibility when debugging a design with an oscilloscope or debugging any memories or memory locations on your PCI bus The memory test is very complete performing a write then a read to every location a read from every location and then a read write read test to every location All other memory test options listed in the memory menu are based on this generic memory test function ET5000K10S USER S MANUAL 9 13 UTILITIES 9
140. AA37 AB39 AB37 AB37 AC38 AJ34 AB36 AM39 AN38 AP39 AB34 AB35 AC34 AC35 AD33 AC33 AJ35 AD34 AP38 AG37 AD39 AD38 AD37 AE38 AE37 AF39 AF38 AG38 AH39 AH38 AH37 AJ39 AJ38 AJ37 AK39 AK38 AH35 AH36 AL37 AJ33 AH32 AG32 AK33 AE33 AH34 AG36 AG35 AG34 AF35 AF34 AE36 AE35 AC37 AK37 AL36 AE34 lt 1_ lt Ad lt 2 lt 5 lt SRAM 4 lt SRAMI 5 lt 5 1 lt 7 lt SRAM 8 lt 5 1 9 SRAM A10 SRAM 11 lt lt 5 1 A12 lt lt 1 A13 lt 5 1 14 lt lt 5 1 A15 lt 5 1 A16 lt 5 1 A17 lt 5 1 A18 lt 5 1 A19 lt 5 1 ADVn lt _ 5 lt 5 1 ADSCn lt BWAn BWBn lt 5 BWCn lt 5 BWDn lt BWEN lt SRAMI lt SRAMI_LBOn lt lt OEn lt lt S
141. AM DATA 55 DQ55 V4 lt SDRAM 56 DQ56 04 4 5 DATA 57 DQ57 lt SDRAM 58 DQ58 R4 SDRAM DATA 59 DQ59 lt _ SDRAM DATA 60 DQ60 M4 6 61 0061 14 6 62 0962 lt SDRAM 63 DQ63 AC4 lt SDRAM_REGE see REGE below Figure 5 11 SDRAM J19 Bus Signals Page 2 of 2 SDRAM On Board Options R218 and R217 are connected to the wP Write Protect input of the SDRAM EEPROM Stuffing a 0 resistor in R217 will keep the wP signal high whereas stuffing it in R218 drives the signal low The default configuration is R217 stuffed NEVER stuff both resistors at the same time The EEPROM holds data describing the size configuration and timing char acteristics of the SDRAM The data is write protected when the wP signal is high There should be little or no reason to want to overwrite the EEPROM data Some SDRAM manufacturers simply connect the WP pin of the EEPROM chip to the power supply of the SDRAM in which case the WP resistors have no effect whatsoever ET5000K10S USER S MANUAL 5 11 Header JP7 is connected to the REGE Register Enable input of the SDRAM and to ground A pull up resistor keeps the REGE signal high when the header is unconnected adding a jumper between the two pins drives the signal low The default configuration is no jumper REGE
142. ANIOOA ANIOOA ANIOOA ALLN d lt AS 9114 SOA 8114 AGL AGL AG e lt gt 5 gt o Lo X o o W LLL 002 vp pesojosip Aue pue NSQ F0LOO0SNQY00A3HASOLLVIASHOSYSMSNQW3SI VX OMY 4 Sjubu ejes pue esn uononpoudei jeno uejeudoud se 1ese dnoJc SL 10 6 00 0000 7010 0S ayepdn oq INIG dnoJ9 24 Auedoud y 51 pue J pajeJeuec 2 pesojosip uoneuuojut eu BIN 3821 ANOS NIC 941 QNO 2 gt 5 5 S QNO QNO Se 96 161 9 S6 0ldHQOH LSL 181 93 LvL ON HOH 151 21 2 8 V Japeay 1891 Japeay 1891 2 lt 5 I 2 x S 2002 9 Menuer Aepsunu NSQ Y0LOO0SNQY00AGHISOLLVINSHOSYISMSNQW 3I VXHOM Y 4 ayepdn
143. ARE SEE 932 5 DO NOT REMOVE PROCESSING CAP UNTIL SOLDERING 15 COMPLETED CAP WILL PREVENT POTENTIAL NOSE PIECE BOW DURING HIGH TEMP SOLDERING PROCESS ELECTRONICS MICROPAX 025M SMT RECEPT SINGLE MODULE MICROPAX product family code wr 91408 pap cs cage code 4 22526 Figure A 2 Berg 91403 003 Datasheet Page 2 of 2 5000 105 USER S MANUAL Droits de reproduction BERG ELECTRONICS INC Tous droits strictement reserves Reproduction ou communication a des tiers interdite sous quelque forme que ce soit sans autorisation ecrite du propietaire Propriete de c BERG ELECTRONICS Alt rights strictly reserved Reproduction or issue to third parties ony form BERG Copyright BERG ELECTRONICS INC whatever is not permitted without written authority from the proprietor Property of C BERG ELECTRONICS ERG CONNECTOR DATASHEETS 2121 1111 fF 1 3 PRODUCT NO SEE TABLE TABLE 0 044 1 12 0 040 X 0 047 DIA REF OVAL 0 062 1 57 DRAIN AREA 5 S 0 015 0 38 N STAND OFF S I 0 008 0 20 THICKNESS DIM E POS f 0 116 2 95 SECTION REF 2X ROTATED COUNTERCLOCKWISE 90 SCALE 10 1 LLL 010 EF 2x L 4 07 0 220 5 59 0 104 2 64 REF 2X ee
144. BWD lt 5 BWEn BWE lt 5 GW lt SRAM3_LBOn MODE lt SRAM3 CEn lt 5 OEn OE lt SRAWG ZZ 72 lt 5 00 0 DQa0 lt 5 0 DQa1 lt 5 00 2 DQa2 00 3 DQa3 lt 5 00 4 DQa4 lt SRAM3 00 5 DQa5 lt SRAM3 00 6 DQa6 lt SRAM3_DQa7 DQa7 SRAM3 0060 DQbO SRAM3 00 1 DQb1 lt 5 0062 DQb2 lt SRAM3 DQb3 DQb3 lt SRAM3 0004 DQb4 lt SRAM3_DQD5 DQb5 X 0056 DQb6 lt SRAM 0007 0057 lt SRAM3 00 0 lt lt 00 lt _ 2 DQc2 lt 5 _ DQc3 lt lt 00 4 lt 5 _ 5 DQc5 lt 5 00 6 DQc6 lt 5 DQc7 lt SRAM3 0080 lt 0001 lt 0092 lt SRAM3 0093 DQd3 lt 5 3 0004 0094 lt 0095 0095 lt
145. DRAM ADD 11 SDRAM ADD 12 SDRAM ADD 13 SDRAM 0 SDRAM 1 SDRAM 2 SDRAM 3 SDRAM 41 SDRAM 5 SDRAM 6 SDRAM 7 SDRAM SCL SDRAM SDA SDRAM 5 0 SDRAM 1 SDRAM 5 2 SDRAM 0 SDRAM CB 1 SDRAM 2 SDRAM CB 3 SDRAM 4 SDRAM CB 5 SDRAM 6 SDRAM 7 SDRAM 0 SDRAM 1 SDRAM 2 SDRAM 3 SDRAM 41 SDRAM 5 SDRAM 6 SDRAM DATA 7 SDRAM 8 SDRAM 9 SDRAM DATA 10 SDRAM DATA 11 SDRAM DATA 12 SDRAM 13 SDRAM DATA 14 SDRAM DATA 15 SDRAM 16 SDRAM J3 CKEO CKE1 508 1 2 S3 BAO BA1 WE CAS RAS SUld uu A1 A2 A3 4 5 6 7 8 9 10 11 12 13 suld UJ DQBM1 DQBM2 DQBM3 DQBM4 DQBM5 DQBM6 DQBM7 SCL SDA SA1 SA2 EN CB2 4 5 CB6 CB7 000 001 002 003 004 005 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 0014 0015 0016 suld ejeq Figure 5 10 SDRAM J19 Bus Signals Page 1 of 2 EMULATION TECHNOLOGY INC 011 SDRAM 93 MB7 lt SDRAM DATA 17 DQ17 18 SDRAM 8 DQ18 L7 lt 5 9 DQ19 SDRAM 20 DQ20 J8 lt DATAI 1 0021 J7 lt SDRAM
146. ECTRONICS 005 linear 0025 10020 1 005 projection title MICROPAX 025M SMT EL PLUG DOUBLE MODULE LLL a Teng eem 372 93 size i no der ue 3 4793 scat 91294 374 93 10 2 0 sheel revision TEE 11111 3 1 2 3 coge code 4 form no 7530 001 103 22526 Figure 4 Berg 91294 003 Datasheet Page 2 of 3 5000 105 USER S MANUAL Droits de reproduction BERG ELECTRONICS Reproduction ou communication a des tiers interdite sous quelque forme que ce soit sans autorisation ecrite du propietaire Propriete de C BERG ELECTRONICS Tous droits strictement reserves to third parties any form ELECTRONICS whatever is not permitted without written authority from the proprietor Copyright BERG ELECTRONICS INC ion issue hts strictly reserved Reproducti ng Property of BERG ELECTRONICS AI ERG CONNECTOR DATASHEETS CONTACT NO OF IM DIM E DIM F DIM G PROCESSING 91294 001 120 1 930 50 95 830 21 08 725 18 42 1 550 39 37 2 150 54 61 1 790 45 47 965 24 51 30 CAPS INSTALLED ON CONNECTOR NOT SHIPPED ON CONNECTOR ps _ gl PRODUCT 200 2 930 74 42 1 330 33 78 1 225 31 12 2 550 64 77 3 150 80 01 2 790 70 87 1 465 37 21 30 200 2 93
147. EDs 5000 105 has eight LEDs that are used to visually communicate the status of circuitry Figure 8 2 Figure 8 2 ET5000k10S LEDs From left to right the LEDs are labeled CPLD LEDO CPLD LED1 CPLD LED2 CPLD LED3 UP LEDO UP LED1 UP LED2 UP LED3 see Figure 8 3 DS2 DS1 CPLD LED1 CPLD LED3 UP LED1 UP LED3 CPLD LEDO CPLD LED UP LEDO UP LED Figure 8 3 ET5000k10S LED Diagram The LEDs have the following functions UP LED3 Lights when the configuration process from the SmartMedia was successful UP LED 2 O These three LEDs have multiple meanings When all 3 LEDs are blinking then the pP has been repro grammed and is waiting for the user to enter FPGA stuffing 5000 105 USER S MANUAL 8 3 RESET SCHEMES LEDS BUS BARS AND 200 PIN CONNECTORS Bus Bars information via serial port or there is not a valid SmartMe dia card present and the FPGA has been configured During configuration the combination of LEDs lit tells the user which FPGA is currently being configured UP LED2 UP LED1 UP LEDO off off on FPGA off on off on on off on FPGA D CPLD LED3 lights when the FPGA is NOT configured CPLD LED2 lights when reset is asserted PWRRST CPLD_LED1 lights when the in Roboclock is LOCKED CPLD LEDO lights when the PLL in Roboclock Il is LOCKED You are free to reprogr
148. EST Main Screen 9 6 Gier P 9 6 Men PP 9 7 Memory 9 9 Appendix ABerg Connector Datasheets Appendix ET5000k10S Schematic 7 1 EMULATION TECHNOLOGY INC LIST FIGURES List of Figures FIGURE TITLE PAGE 2 1 ET5000k10S Block Diagram 2 2 2 2 General LE Diagram 2 4 2 3 Dual Port Data Flows 2 5 2 4 DSP Block Diagram 2 6 2 5 Multiplier Sub Component Block Diagram 2 7 2 6 ET5000k10SBlock Diagram of ATmega128L and ET5000k10S Interfaces 2 10 2 7 P1 Unused pP Connections 2 11 2 8 P7 Interface 2 11 2 9 P5 BER ELA EUR OR MER NEA Ec 2 12 2 10 Location of 5000 105 2 15 2 11 P2Serial Port Locations 2 18 2 12 Delkin 32 MB 3 3 V Smart Media 2 24 3 1 FPGA Pin Connections for PCI Signals 3 2 3 2 Edge 3 3 3 3 ET5000k10S 5 3 4 3 4 JP2 Present Header 3 5 3 5 66 Capability Header 3 6 4 1 Clock Distribution Block Diagram 4 1 4 2 Cl k Grid 4 3 4 3 PECL Clock I
149. I 34IQ ON OI PO 4 J4IQ OI dee ceXL 34IQ ON OI om 97 89 57 4410 01 UPOL GZXL 33IQ ON OI Gove 9 14 4621 86 9 4410 151 dg 0 OXL UJ LNAY U8Z OZ E Xl J4IQ OI AWA Wvuas gt 48 89 91 4410 01 gt 4601 1 89 3310 01 Age 052 0924 9NGu uezL 86 9 XW 44100100 JJIQ OI L ug Xw 4JIQ ON O Lanur dez oz e xr 4 10 1 6944 9 9 44IQ N O ug01 14 98X 5310 01 082 dezWveXL 34IQ ON OI 4410 01 5 AV gt J3IQ ON OI Herny 4424 qr 498 69 jdlQ N O 950 8 1 JJIQ ON OI U ZIVOXL JJIQ ON OI gt JdIQ ON OI JdIQ OI a 468 12 1 4 40 gLvudH sr dsg 6s ovXL 4 bu UG0L 9 XL JdIQ ON OI 4 10 01 34IQ ON OI 4410 01 J4IQ OI Leere 7r US8 6S 9PXL 4 d901 8 68Xs 4410 1 2400 vive uz 96 2 X4 34IQ OI C 66 1 JJIQ ON OI 9 g 62 J4IQ OI 98 19 4 34IQ ON OI 901 8 69 33IQ OI 2 96 0 1 4410 01 UbL G6XL JdIQ ON OI y 4 amp 33IQ ON OI
150. I O pins are utilized on the F1508 package The standard speed grade we stuff is 7 We can use 6 speed grade but don t fall out of your chair when you get the price Note that Altera seems to have cancelled plans for the EP1S120 Although this part appears in some Altera literature we haven t seen any scheduled release date or other documentation for it Don t expect to see anything larger than the EP1S80 until at least the 2004 time frame Table 2 1 shows the stuffing options for the 5000 105 Table 2 1 ET5000k10S Stuffing Option Comparison DDR Total Header SDRAM Connections Stuffed FPGA SSRAMs SDRAM The following is a very brief overview of the Stratix family More informa tion can be gleaned from the Stratix Datasheet ds_stx paf This file is on the CD ROM supplied with the 5000 105 but you are better off getting the latest version from the Altera Web page http www altera com Make sure to get the latest errata sheet also Flip Flops and Figure 2 2 shows what Altera calls a Logic Element or LE Each LE contains LUTs flip flop and a 4x1 look up table LUT LEs are arranged in groups of 10 called Logic Array Blocks LAB 1580 is an array of LABs with 91 rows and 101 columns but there are 9 RAM blocks which appear in place of 13 row by 11 column sections of the grid leaving a total of 7904 LABs and 19040 LEs Other blocks such as DSP multiplier blocks and smaller RAM are arranged in ent
151. ION TECHNOLOGY INC Chapter 5 Memories The ET5000k10S has six external memories four 36 bit SSRAMs one 72 bit SDRAM DIMM and one 72 bit DDR SDRAM DIMM The four SSRAMS are referred to as SSRAM 1 U9 SSRAM 2 U6 SSRAM 3 U8 and SSRAM 4 U13 SSRAMs The SSRAMs can be stuffed with ZBT non ZBT pipeline or flowthrough parts We believe we have anticipated the additional address lines for the 1M x 36 and 2 M x 36 parts when they are available The 5000 105 is stuffed at the factory with 512 K x 36 bit Synchronous Pipeline Burst SRAM Samsung K7A163600M QC1400 are probably the parts you will have stuffed into your ET5000k10S The datasheet is on the CD ROM in the file DS K7A1636 18 00M pdf The SSRAMs are tested at 133 MHz SSRAM Notes 4AIIssRAMs use for their clock The signal connections for SSRAM 1 are shown in Figure 5 1 The signal connections for SSRAM 2 are shown in Figure 5 2 The signal connections for SSRAM 3 are shown in Figure 5 3 The signal connections for SSRAM 4 are shown in Figure 5 4 Flowthrough 55 5 are functionally the closest to ASIC style memories Pipeline SSRAMs can be clocked at faster frequencies ZBT SSRAMs are typi cally one generation behind in density The subtle differences between the styles of memories are described in the next section 5000 105 USER S MANUAL 5 1 011 AA36 4 AJ36 AF33 6 5 AD36 AD35 AM38 AN39 AC39 AA39 AA38
152. LL PS SOXH J4IQ OI do L z0L 9 XL 34IQ OI uOSLXL JJIQ ON ON OI v d4L6 6XL 34IQ OI uge zIzZXL J4IQ Ol Hegy V LAS ut6 99 LX J3IQ OI JdIQ ON ON OI 1 Ssvlvd Wvuas V ZOL 9 XL 4410 01 JJIQ ON ON OI v g USL OL OLXL 4410 01 dog z zeXL 33IQ Ol VS ga 6 89 55 1 4 10 1 UZLLXL JHIQ ON ONIOI 9 JIQ OI JJIQ ON ONIOI 9 d8L 0L 01X L 4410 01 96 82 12 4IQ OI Horey 7 1 6 89 55 1 deL1 Gg 99XM J4IQ OI 4 881 34IQ 2N ON OI WS 4410 1 496 82 34IQ Ol 9 557 196 9 8 4410 01 4410 01 vogi 9 dLEL EOLILIXL 4410 01 ULSLXL JJIQ ON ON OI a 9 d8L 0L EXH 34IG OI 3JIQ ON ON OI ely LAVAS 74 96 9 8 34IQ OI deLL Gg 99XL J4IQ OI Jd 9 6 60 21 1 4410 01 151 NWS 4HIQ ON ON OI 72 996 69 99 1 3IQ OI UELL S8 99X1 5410 01 TET GEM Tas LL AAAS ev lt 3510 01 08 9 4410 01 3210101 9 TU Vu Sm XS gov 3310 01 1 lezizzXs 34IQ OI 99 1214 YWYYS WYYAS M WVSUS lt gt 5 gt o L
153. MULATION TECHNOLOGY INC Chapter 1 Getting Started The 5000 105 is sensitive to static electricity so treat the PWB accord ingly The target market for this product is engineers that are familiar with FPGAs and circuit boards so a lecture in ESD really isn t appropriate and wouldn t be read anyway However we have sold some of these units to people who are not as familiar with this issue The following web page has an excellent tutorial on the Fundamentals of ESD for those of you who are new to ESD sensitive products http www esda org basics part1 cfm Emulation Technology Inc Technical Support The following means of technical support are available 1 The ET5000k10S User s Manual This is the main source of technical information We strive to produce excellent documentation and this manual should contain most of the answers to your questions The Emulation Technology Web Page The web page will contain the latest manual application notes faq articles and any device errata and manual addenda Please visit and bookmark http www emulation com E Mail to support emulation com You may direct questions feedback to Emulation Technology using this e mail address Phone Support We are happy to help Call us at 1 800 ADAPTER during the hours of 8 00 A M to 5 00 P M Pacific Time Some of us get in early and stay late so you might try us outside of these hours also Frequently Asked Questions In the
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156. P2 3 4 JP3 3 5 to 3 6 JP4 4 14 5 12 5 15 JP5 4 14 to 4 15 JP6 4 2 4 4 4 11 JP7 5 12 JP8 4 7 JP9 4 2 4 5 4 7 4 13 JTAG 2 9 2 11 to 2 13 2 16 to 2 17 2 22 to 2 23 3 4 cable 2 16 chain 3 4 configuration 2 16 interface 2 2 2 11 programming 2 16 to 2 17 2 22 to 2 23 signals 2 14 to 2 15 3 4 L LD 5 9 LE 2 3 to 2 4 LED 2 1 2 3 2 21 7 4 8 3 linear power supply 7 4 linear regulator 2 1 6 2 LOCK 3 1 logic 2 1 logic analyzer 2 1 to 2 2 2 16 low voltage differential signaling See LVDS low voltage TTL See LVTTL LTC1326 8 1 LUT 2 3 LVCMOS33 2 8 LVDS 7 1 7 5 LVPECL 4 2 4 11 M66EN 3 5 to 3 6 main configuration file See main txt main txt 2 17 2 19 to 2 23 MDR 7 6 memories 2 2 2 25 4 13 5 1 9 13 microprocessor 2 1 2 3 2 9 to 2 11 2 14 2 16 6 2 9 1 MODE 4 8 multiplexing 5 9 multiplication 2 5 4 9 Multiplier 2 5 2 7 multiplier 2 1 2 3 2 5 2 24 to 2 25 4 9 9 2 9 6 multiplier blocks 2 3 multiplier logic 2 5 N nCONFIG TMS 2 14 2 16 nSTATUS 2 14 2 16 O OE 7 6 oscillator 2 1 2 16 4 1 to 4 5 4 9 4 12 to 4 13 6 2 oscilloscope 7 1 9 7 9 10 9 13 output divider function 4 8 to 4 9 output mode 4 8 output phase function 4 8 output enable 7 6 P P1 2 10 to 2 11 6 1 6 3 to 6 5 7 6 EMULATION TECHNOLOGY IN Index Continued P2 2 17 to 2 18 7 6 P3 2 16 7 6 P4 2 14 to 2 15 7 6 P5 2 12 2 16 7 6 P54 4 5
157. PLL5 The resulting PLL output be sent to Roboclockll 914 the signal GCLKOUT All of the memories the ET5000k10S run off one of the clock outputs from Roboclockll PCI CLK PCI_CLK 15 connected to the Stratix Enhanced PLL5 input pin B22 To run Details all memories off of PCI_CLK a PLL must be instantiated in the FPGA code The PLL will require a minimum of three connections input clk output clk and external feedback input For further information on Stratix PLL oper ation see the Altera website at http www altera com The Stratix Datasheet ds_stx pdf which be found on the ET5000k10S CD ROM also provides useful information on PLLs 5000 105 USER S MANUAL 4 13 CLOCKS AND CLOCK DISTRIBUTION GCLKOUT Header Clocks The GCLKOUT signal is connected to one of the four input pins on Roboclockll GCLKOUT s complementary input is DCLK 7 FCLKOUT and DCLK 7 R are both single ended TTL inputs When either of them is being used the other one must be left open For complete PCI CLK operation jumper JP5 must not be stuffed leaving DCLK 7 R open If set to the default configuration Roboclockll will drive a one to one PCI CLK derived clock on its outputs See Roboclock PLL Clock Buffers on page 5 for more information Roboclockll has 12 clock outputs 12 0 The FPGA ECLK 9 ECLK 12 SSRAMs ECLK 7 41 DDR SDRAM ECLK 3 0 and DDR SDRAM PLL outputs
158. PMEn PCI AD31 Bao PCI_AD30 TP13 822 028 2 PCI_AD26 V Bos 025 pb PCI AD24 A26 inset 5 PCI_IDSEL P f 5020 PCI AD20 PCI AD19 pgao A30 7 5 430 PCI AD18 5 AD18 PCI 017 Aa 3339 PCI FRAMEn 4 PCLTRDYn bci 80 eT ec stom 3av 538 PCIXCAP STOP iai 3 3 lt PCI STOPn ov E B R158 5 1K 2 1 Haa t L Am L B46 PCI AD12 TR PCI AD Bag ie PCI AD9 480 PCI AD8 B52 m A52 0 HE REHAB LIBRO 931 m Las PCI AD6 542 rae _ PCI 4 PCI REQ64n Bet 64 PCI CBEn7 6 A65 PCI CBEn5 B66 AGG VIO 4 67 A67 PCI PAR64 PCI AD63 Bes ics 5 ADG lt _ gt PCI_PAR64 Pg6 4 70 PCI 060 PCI AD59 H AD60 71 5 11758 10 LA 573 AD57 PCI AD56 ERE m n AD 374 Dos PLEASE ion 15 L B76 GND aze SC ADEO 5 PCI
159. R gt gt DDR CKEN 1 CKE1 3 10 DDR CSn 0 gt 50 9 APO 4 DDR CSn 1 51 y DDRCSn2 y 828 5 7 14 CSn 3 53 NC o AP16 008 BA Q BAO AR16 DDR BA i y AR34 4 DDR BA 2 BA2 NC AP13 DDR WEn _ AP11 4 DDR CASn AP14 4 RASn 5 5 7 5 Av36 4 NC AR18 4 ADD AR22 DDR ADD 1 gt AP22 lt DDR ADD 2 gt 23 DDR ADD 3 gt 24 DDR ADD A4 4 814 DDR ADD 5 4 a 6 lt ADD 6 DDR ADD 7 v AP29 DDR ADD 8 AP31 gt DDR ADD g 5 9 6 008 ADD 10 AP32 DDR ADD i1
160. RAMI ZZ lt 5 00 0 lt 1 lt 5 DGa2 lt 5 DGa3 5 DQa4 lt 5 00 5 lt 5 lt DQa7 lt 0060 lt 0061 lt 0052 lt 0063 lt lt 1 0064 lt 0065 lt 0066 lt 5 1 0067 lt 5 00 0 lt 00 1 lt 5 1 00 2 lt lt 1 DQc3 lt 5 DQc4 lt 5 0055 lt 5 00 6 lt 5 DQc7 lt 5 0090 lt SRAM 1 0091 lt 0092 lt 0003 lt 0094 lt 5 DQd5 lt 0096 1 0007 lt 1 DGPa lt lt DGPc lt SSRAM 1 99 SAO SA1 SA2 5 4 5 5 5 6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 expansion a SseJppy AD
161. RSTn 2 14 ROBO LOCK1 2 14 ROBO LOCK2 2 14 RST 3 4 9 1 SDRAM BA 5 9 CAS 5 9 CK 5 9 5 12 RAS 5 9 REGE 5 12 WP 5 11 to 5 12 SM ALE 2 14 SM CEn 2 14 SM CLE 2 14 SM D 2 14 SM RDYBUSYn 2 14 SM REn 2 14 SM WEn 2 14 SmartMedia SM ALE 2 14 SM CEn 2 14 SM CLE 2 14 SM D 2 14 SM RDYBUSYn 2 14 SM REn 2 14 SM WEn 2 14 SM WPn 2 14 SP WPn 2 14 SRAM CSn 2 14 TCK 2 14 to 2 16 3 4 TDI 2 14 to 2 16 3 4 TDO 2 14 to 2 16 3 4 TMS 2 14 to 2 16 3 4 TRST 3 4 UP ALE 2 14 UP WRn 2 14 UPAD 2 14 UPPADDR 2 14 VCC 2 17 WP 5 11 to 5 12 SM ALE 2 14 SM CEn 2 14 SM CLE 2 14 SM D 2 14 SM RDYBUSYn 2 14 SM REn 2 14 SM WEn 2 14 SM WPn 2 14 SmartMedia 2 1 2 3 2 8 to 2 9 2 13 to 2 14 2 16 2 21 to 2 24 3 4 9 1 speed 3 6 5 6 clock 2 5 clock buffer 4 2 configuration 2 1 grade 2 3 2 25 3 1 interface 2 14 LVDS 7 5 PWB 3 1 SRAM 2 9 2 14 5 1 6 2 CSn 2 14 SSRAM 2 3 4 13 to 4 14 5 1 5 6 6 2 bus signals 5 2 to 5 5 test 9 2 9 13 timing 5 8 to 5 9 startup 9 4 to 9 5 static electricity 1 1 Stratix 1 2 2 1 2 3 to 2 5 2 8 to 2 9 2 13 to 2 14 2 16 2 23 2 25 3 1 4 13 to 4 14 5 12 6 2 to 6 3 7 1 switching regulator 3 1 6 2 Syncburst 5 6 to 5 9 Synopsys 2 24 to 2 25 Synplicity 2 2 2 16 2 24 synthesis 2 24 to 2 25 tools 2 7 2 24 to 2 25 EMULATION TECHNOLOGY INC T target design 2 2 TCK 2 14 to 2 16 3 4 TDI 2 14 to 2 16 3 4 TDO 2 14 to 2 16 3 4 terminator technology 2 7 TMS 2 14 to 2 16 3
162. SERVATION DAUGHTER CARD FOR 200 PIN CONNECTORS Options Resistors R10 and R11 can be used to select different voltage sources 5 V 43 3 V respectively When used U4 must be removed in order prevent contention NOTE Never populate R10 R11 simultaneously this will result in a shorted power supply Power Rating 5 power supply is rated for 1 A 3 3 V power supply is rated for 1 5 V power supply is rated for 1 A 12 V power supply is rated for 0 5 A 12 V power supply is rated for 0 5 A Connector J8 Table 7 1 shows the connections of J8 Table 7 1 Connector J8 Pins External Power Function i Function LVDS Low voltage differential signaling LVDS is a signaling method used for high speed transmission of binary data over copper It is well recognized that the benefits of balanced data transmission begin to outweigh the costs over single ended techniques when the signal transmission times approach 10 ns This represents signaling rates of about 30 Mbps or clock rates of 60 MHz in single edge clocking systems and above LVDS is defined in the TIA EIA 644 standards NOTE Not available the 5000 105 ASIC prototyping board ET5000K10S USER S MANUAL 7 DAUGHTER CONNECTIONS ET3K10SD OBSERVATION DAUGHTER CARD FOR 200 PIN CONNECTORS Connector is a Mini D Ribbon connector 50 pin manufactured by used specifically for high speed LVDS signaling The co
163. SNT2 or both JP3 66 66 Enable The 66 7 ENABLE pin M66EN indicates to the host whether the device can operate at 66 MHz or 33 MHz Section 7 5 1 in the Specification 2 2 provides the gory details For 33 MHz only FPGA designs install a jumper between pins 9 and 10 of JP3 For 66 MHz capable designs install a jumper between pins 7and 8 instead Table 3 2 shows the jumper descriptions for 66 Table 3 2 M66EN Jumper Descriptions Jumper JP3 Description TP13 PME Power Management Enable This board does not have built in support for PME power management enable Connecting PME to an FPGA that is not powered is a bad idea the system powers up as the board is installed PME is connected to TP13 This test pin allows the user to connect external circuitry to PME if this functionality is desired 5000 105 USER S MANUAL 3 JP3 PCI PCI X Capability Figure 3 5 shows the PCI X M66EN Capabilities Header Add in PCI X boards tell the system what speed they are capable of running by the correct setting of this header c P3 PCIXCAP 4 6 10 66 136 206 9 10K 0 01uF C218 I Figure 3 5 PCI X MGGEN Capability Header K Add in cards indicate at which frequency they support PCI X using a pin called PCIXCAP If the card s maximum frequency is 133 MHz this pin is left unconnected except for a decoupling capacitor C206 If the card s m
164. T3k10SD Daughter Card Block Diagram 7 2 7 2 ET3k10SD Daughter Card 7 3 7 3 ET3k10SD Daughter Card Assembly Drawing 7 4 8 1 Reset Functionality 8 2 8 2 5000 105 LEDS Eres 8 3 8 3 ET5000k10S LED 8 3 8 4 91294 003 Pin Numbering 8 5 8 5 200 Pin Connectors Signal Connections 8 7 9 1 ET5000k10SAETEST Startup Screen ET5000k10S RECOGNIZEGs Ex Rus SE S RENE ME IR E EE 9 4 9 2 AETEST Startup Screen No PCI Peripheral Recognized 9 5 9 3 AETEST Main Screen 9 6 9 4 AETEST PCI 9 7 9 5 AETEST Memory Menu 9 9 9 6 AETEST Write to Memory Test 9 10 9 7 AETEST Read Memory Test 9 10 9 8 AETEST Write Read Test 9 11 9 9 AETEST Memory 9 11 9 10 AETEST Memory Display 9 12 9 11 AETEST Write Read Memory Byte 9 13 A 1 Berg 91403 003 Datasheet Page 1012 A 2 A 2 Berg 91403 003 Datasheet Page 2 of 2 A 3 A 3 Berg 91294 003 Datasheet Page 1 of 3 A 4 A 4 Berg 91294 003 Datasheet Page 2 of 3 A 5 5 Berg 91294 003 Datasheet Page 3 of 3 A 6 vill EMULATION TECHNOLOGY INC IST TABLES List of Tables
165. TA 27 gt DDR DATA 28 DDR DATA 29 gt DDR DATA 30 gt DDR DATA 81 gt DDR 32 4 DDR DATA 33 gt DDR DATA 34 DDR DATA 35 DDR DATA 36 gt DDR DATA 37 gt DDR DATA 38 gt DDR DATA 39 DDR DATA 40 gt DDR DATA 41 gt DDR DATA 42 gt DDR DATA 43 DDR DATA 44 DDR DATA 45 DDR DATA 46 DDR DATA 47 gt DDR DATA 48 DDR DATA 49 DDR 50 DDR DATA b1 DDR DATA b2 gt DDR 53 gt DDR 54 gt DDR 55 DDR 56 gt DDR DATA 57 DDR DATA 58 DDR 59 DDR DATA 60 DDR DATA 61 DDR DATA 62 DDR DATA 63 gt DDR SDRAM J2 DQO DQ1 002 003 004 005 DQ6 DQ7 008 009 0010 0011 0012 0013 0014 0015 0016 0017 0018 0019 0020 0021 0022 0023 0024 0025 0026 0027 0028 0029 0030 0031 0032 0033 0034 0035 0036 0037 0038 0039 0040 0041 0042 0043 0044 0045 0046 0047 0048 0049 0050 0051 0052 0053 0054 0055 0056 0057 0058 0059 0060 0061 0062 0063 Figure 5 13 DDR SDRAM 22 Bus Signals Page 2 of 2 EMULATION TECHNOLOGY INC FPGA 01
166. U11 P9 U11 mo suem mum LM 2 AC ur w E LN GND _ 158 TST E LE LN 8 INN LELCL CIL NE LN NEL LN wo mm y e 147 NM 28 160 045 7 12 EMULATION TECHNOLOGY INC DAUGHTER CONNECTIONS ET3K10SD OBSERVATION DAUGHTER CARD FOR 200 PIN CONNECTORS Table 7 2 Daughter Board Header FPGA Pin Map Daughter Test Test J1 Signal Header P8 Signal Pin Header P9 Signal Pin Header 8 11 9 11 ear _ xs stoma _ ras run um mu suum _ _ um _ ns mm uum mun m LN m LN m m m 1 zi DW raum s Dm rana zs Mum Om zn Mum _ suna mm m Ow ran
167. UAL Figure 5 12 DDR SDRAM 22 Bus Signals Page 1 of 2 5 13 011 AU34 AU33 AW33 AW32 AV34 AW34 AU32 AV32 AU31 AV32 AV29 AW29 31 030 AW30 AU29 AV28 28 27 28 AU28 AU27 AR28 AR27 AU26 26 26 25 26 AV25 AR26 AT25 AV17 AU17 AR17 AT16 AW17 AT17 AW16 AV16 AT15 AW14 AV14 AU14 AV15 AR15 AT14 AR14 AV13 AU13 AT12 AR12 AT13 AR13 AW12 AV12 11 10 9 9 AW11 AU11 AU10 9 4 0080101 lt lt DDR D 1 lt 0080121 lt DDR D 3 lt lt 0080141 4 0080151 4 0080161 lt lt DDR lt DDR 018 lt M 0080191 lt DDR D 10 DDR D 11 lt lt DDR 0112 lt lt DDR D 13 lt lt DDR D 14 4 DDR 0115 lt DDR D 16 lt _ DDR D 17 lt lt DDR 0118 lt lt DDR D 19 lt lt DDR D 20 lt 0080211 lt 0080122 lt 0080123 lt DDR D 24 lt DDR D 25 lt DDR D 26 lt DDR 0127 lt DDR D 28 lt lt DDR D 29 lt DDR D 30 lt DDR D 31 lt DDR D 32 lt DDR 0133 lt DDR D 34 lt DDR D 35 lt DDR D 36 lt DDR D 37 DDR D 38 lt DDR D 39 lt DDR D 40 lt DDR 0141 lt DDR D 42 4 DDR 0143 lt DDR D 44 lt lt DDR D 4
168. V ADSP ADSC BWA BWB BWC BWD BWE GW MODE CE OE 22 DQaO DQa1 DQa2 4 5 7 DQbO DQb1 DQb2 DQb3 DQb4 DQb5 DQb6 DQb7 DQcO DQc1 DQc2 DQc3 DQc4 DQc5 DQc6 DQc7 DQdO DQd2 DQd3 DQd4 DQd5 DQd6 DQd7 DQPa DQPb DQPc DQPd Figure 5 1 SSRAM 1 U9 Bus Signals EMULATION TECHNOLOGY INC SSRAM 2 010 lt 2 lt 2 1 SA1 lt lt 2 A2 SA2 lt 5 2 lt SRAM2 4 SA4 lt 5 2 5 SA5 lt 2 SA6 gt lt 2 A7 SA7 lt 5 2 8 lt 5 2 9 SA9 lt 5 2 A10 5 10 D lt 5 2 11 11 5 lt SRAM2 A12 SA12 v lt gt 2 A13 SA13 2 A14 14 lt 5 2 A15 SA15 lt 2 A16 SA16 lt 5 2 17 17 lt 5 2 A18 18 SRAMA2 19 SA19 expansion lt 2 ADVn ADV lt 5 2 ADSPn ADSP lt 5 2 ADSCn ADSC SRAM2_BWAn BWA lt 5 2 BWBn BWB 9 lt 5 2 BWC BWC lt
169. am the CPLD and or microprocessor to use any or all of the LEDs for your own purposes The two bus bars B1 and B2 are installed to prevent flexing of the PWB and serve no other purpose They are connected quite solidly into the ground plane of the DN5000k10S at every hole and you can use the metal bars to ground test equipment such as oscilloscopes and pattern genera tors Be careful not to short any power rails or signals to these metal bars they can carry a lot of current The PCI bracket BRK1 is also connected to the ground plane at each of the screw mounts The 200 Pin Connectors P8 and P9 The DN5000k10S contains two 200 pin connectors and P9 Daughter cards of any sort may be plugged into these connectors The relative pin location of the powers grounds and signals is identical for each of the connectors A hole that can be used to attach a standoff is located at the same relative position from each connector seeFigure 8 4 This hole is grounded on the DN5000k10S so connect this mounting hole to digital ground on your daughter card The mechanical position of the 200 pin connectors on the DN5000k10S is shown in Figure 8 4 The 200 pin connector used on the DN5000k10S is a Berg Electronics 91294 003 in the Micropax family This link will take you to the Berg website http www berg com This Berg connector was chosen because of its high pin density performance and availability The part number for the mating connec
170. and alone Figure 6 1 shows the various supplies used on the ET5000k10S and the connections of these supplies on the circuit board The supply 5 V from the PCI connector or P1 supplies the basic power to the 5000 105 The 3 3 V power from the PCI connector is not used nor is it connected to any circuitry on the 5000 105 P10 P8 5 3 3 V 31 5 12 V 12V Linear Supply 200 pin Micropax P9 Connectors 5 V VCCINT 43 3 V VCCO 1 5 V VCCAUX FPGA 12V U11 12 12 vrer 1 25 V PCI X 12 DDR SDRAM SSRAMED Figure 6 1 ET5000k10S Power Distribution The ET5000k10S when plugged into PCI slot has the following different power rails 45V 43 3 5000 105 USER S MANUAL 6 1 POWER SUPPLIES AND POWER DISTRIBUTION 3 3 V Power 12 5 V Power 42 5 V 41 25 V tracks to 2 5 V 41 5 V 12 12 The power rails 3 3 V 2 5 and 1 25 1 5 are created using switching regulators with 5 V as the input while 1 5 is created with linear regulator 3 3 V from the PCI fingers is not used U17 is for 43 3 V 016 is for 42 5 and 1 25 V U18 is for 1 5 V Heat is not an issue with this style of switching regulator Each regulator should be able to supply the minimum 10 A of current without strain The most demanding application of the 5000 105 should fit within the 10 A budget on these two power rai
171. annot select any Main Menu options after the config uration process is complete Creating Main Configuration File main txt To control which bit file on the Smart Media card is used to configure the FPGA in Select MAP mode a file named main txt must be created and copied to the root directory of the Smart Media card The configuration process cannot be performed without this file Below is a description of the options that can be set in the file a description of the format this file needs to follow and an example of a main txt file Options Verbose Level During the configuration process there are three different verbose levels that can be selected for the serial port messages Level 0 Fatal error messages Sanity Check errors e g file was created for the wrong part RBF file was created with wrong version of Altera tools or Quartus options are set incorrectly Initializing message will appear before configuration A single message will appear once FPGA is configured level f All messages that Level 0 displays Displays configuration type should be Fast Passive Parallel Displays current FPGA being configured if the configuration type is set to Fast Passive Parallel Displays a message at the completion of configuration for each FPGA configured evel 2 All messages that Level 1 displays Options that are found in nain txt file names for each FPGA as entered in
172. artMedia method takes about 1 second to configure an EP1580 after power is stable It is likely that FPGA F will finish the configuration process before RST is deasserted If your system has an unusually fast RST it is possible that the FPGA will not be configured when RST deasserts RS T4 that deasserts before the FPGA has finished cannot properly configure the PCI PCI X mode latch The signal 3 3vaux is not connected The signals INTB INTC and INTD are not connected JP2 Present Signals for PCI PCI X The present signals indicate to the system board whether an add in card is physically present in the slot and if one is present the total power requirements of the add in card The JP2 PCI X Present Header is shown in Figure 3 4 EMULATION TECHNOLOGY INC Figure 3 4 2 Present Header Table 3 1 shows the Present Signal Definitions for Table 3 1 Present Signal Definitions PRSNT1 9 PRSNT21 Expansion Configuration Open Open No expansion board present Ground Open Expansion board present 25W maximum Open Ground Expansion board present 15W maximum Ground Ground Expansion board present 7 5W maximum We have never seen the present signals used anywhere but we have heard of systems that will not PNP Plug and Play configure a PCI board if both the present pins are left open We recommend installing a jumper in loca tion 1 2 for PRSNT1 or 3 4 for PR
173. as eg olv Lya Wvsas LLL33HS 9dOQ u3M8 4400 vus m ad L olpod vvvvvv 2 gt 5 S AVHS AV 6 is dM 2706 WIN 02701 WVHS 2 vas ZZ vivus TS 22 ZI TEE qos U3O uaa u3O Uo UMO 2 5 AV 2 PWVYS UMO PAVES UMO vAVHS UAGV ZNYNS uan vAVus 9 vWVHS ZNVYS dOd zWVvus UAQV 2 5 Nyy 2 vIAVHS _ AV r
174. aximum frequency is 66 MHz it connects PCIXCAP to ground through a resistor R93 and decoupling capacitor C206 Conventional PCI cards connect this pin to ground JP3 PCIXCAP For PCI only not PCI X capable jumper between pins 5 and 6 For PCI X 133 MHz capable jumper between pins 3 and 4 For PCI X 66 MHz capable jumper between pins 1 and 2 and pins 3 and 4 The PCIXCAP jumpers are detailed in Table 3 3 Table 3 3 PCIXCAP Jumpers Jumper s Installed The M66EN and PCIXCAP Encodings are shown in Table 3 4 3 6 EMULATION TECHNOLOGY INC Table 3 4 M66EN PCIXCAP Encoding Conventional PCI X Device M66EN PCIXCAP Device Frequency Frequency Capability Capability Not Not Capable Connected Not PCI X 66 MHz Connected Not PCI X 133 MHz Connected Not Not PCI X 133 MHz Connected Connected ET5000K10S USER S MANUAL 3 EMULATION TECHNOLOGY INC Chapter 4 Clocks and Clock Distribution Functional Overview 5000 105 ASIC emulation board has a flexible and configurable clock scheme Figure 4 1 is a block diagram showing the clocking resources and connections The clocking structures for the 5000 105 include the following features e 2user selectable socketed oscillators X2 X3 e 148 MHz oscillator X1 2 CY7B993 CY7B994 Multi Phase PLL Clock Buffers 2 3807 Low Skew Clock Buffers DCLK DCLK7R
175. c Analyzer See Application Note 175 at www altera com literature lit qts html or other solu tions such as the Bridges2Silicon system which was recently acquired by Synplicity see www bridges2silicon com The JTAG method of configuration should be used if the SmartMedia method isn t work ing Remember that programming a Stratix part through JTAG uses a file nota rbf file Table 2 3 has the pinouts Table 2 3 FPGA Serial JTAG Configuration Header on Cable Header Schematic Serial Mode JTAG Mode Pin P3 CONF DONE TDO CONF DONE TDO nCONFIG TMS nCONFIG TMS BEEN 2 16 EMULATION TECHNOLOGY INC ET5000K10S FEATURES OVERVIEW AND GENERAL DESCRIPTION Table 2 3 FPGA Serial JTAG Configuration Header Cable Schematic Serial Mode Mode Pin P3 Fast Passive The FPGA on the ET5000k10S can be configured in Fast Passive Parallel Parallel mode using a Smart Media card Fast Passive Parallel configuration is the easiest and quickest way to configure the FPGA The ET5000k10S is shipped Configuration with two 32 MB Smart Media cards One of these Smart Media cards Instructions contains reference design bit files produced for Fast Passive Parallel configuration and files main txt that sets options for the configuration process for description of options see Creating Main Configuration File main txt on page 19 This Smart Media card has been labe
176. carry the following text is lifted directly from the specification for the family of connectors 6 1 Current Rating Current rating shall be evaluated in still air at 25 ambient temperature Under the following conditions the temperature rise shall be no greater than 30 C All contacts powered at 0 5 amp One contact powered at 3 0 amps Most of the signals are TTL or some low current variation such as LVDS so you can reasonably expect to get up to 3 amps per power pin through this connector Remember that the 3 3V and 1 5V power supplies are limited to 5 amps total the memories the FPGA and the clock circuitry on the DN5000k10S consume 3 3V The FPGA only consumes 1 5V If you use the DN5000k10S stand alone meaning that it is not plugged into a PCI slot the auxiliary power connector has 5V and 12V but does have 12V So unless you provide 12 to the DN5000k10S via another connection 12 will not be available for use by a daughter card The 200 pin connectors are shown in Figure 8 5 NOTE 12V is not required by the DN5000k10S The DN5000k10S will operate normally without a 12V power supply EMULATION TECHNOLOGY INC RESET 5 5 LEDS BUS BARS AND 200 PIN CONNECTORS Test Header Test Header P9 P8 E e LO LO LO LO LO LO LL LO LO LO a Ld 8 1 1
177. cation and immediately read what was written Repeat for a selected number of long words Figure 9 8 Bar Number 0 55 Address fhHBHHBH Humbers of long words to write Cin decimal 2 long word to write in hex long word to write hex aaa 1 Display result 2 Display result and loop indefinitely 3 Don t display result and loop indefinitely Please select Figure 9 8 AETEST Write Read Test You will be prompted for the memory location in hex The physical address is needed All 4 gigabytes of PCI memory can be read The program will prompt for the number of long words you with to write 1 to 1024 Three options are available 1 Read once and display 2 Read indefinitely and display 3 Read indefinitely and don t display Option 3 is a very useful scope loop Memory Fill Fill memory with a selected pattern Figure 9 9 Input bar number 49 52 Input starting address and 32 bit aligned Input number of bytes Chex and divisible 4d 1088 Fill with address data 55555555 _ BHxffffffff data address n E Figure 9 9 AETEST Memory Fill You will be prompted for the memory location in hex The physical address is needed 4 gigabytes of PCI memory can be written The program will prompt for the number of bytes in hex you wish to fill 4 to Oox ffffc T
178. ce matching standards Parallel termination requires 1000 ohm resistors for RDN and RUP Terminator technology is a very nice feature and we recommend you use it on all I O signals The default IO STANDARD attribute for the csf file is LVTLL VCCO pins are connected to either 43 3 V or 2 5 V VREF pins connected to 1 5 V or 2 5 V so the ET5000k10S does not support standards that require other values of VREF So the I O standards supported are LVTTL Low Voltage TTL The low voltage TTL or LVTTL standard is a general purpose EIA JESDSA sign a 1 sign b 1 acir 3 0 clock 3 0 ena 3 0 shiftin B A Data A Result to Adder blocks Optional Multiply Accumulate and Multiply Add Pipeline Data B shiftout shiftout A Figure 2 5 Multiplier Sub Component Block Diagram ET5000K10S USER S MANUAL 2 T5000K10S FEATURES OVERVIEW AND GENERAL DESCRIPTION standard for 3 3 V applications that use the LVTTL input buffer and a Push Pull output buffer The standard requires a 3 3 V input and output source voltage but does not require the use of a reference voltage a termination voltage LVCMOS33 3 3 Volt Low Voltage CMOS This standard is an extension of the LVCMOS standard JESD8 5 It is used in general purpose 3 3 V applications The standard requires a 3 3 V input output source voltage but does not require the use of a refer
179. ctrum http www exemplar com products leonardospectrum html Of the four listed here we find that Synplicity offers the best perfor mance followed by Exemplar The Synopsys products are not the easiest 2 24 EMULATION TECHNOLOGY INC ET5000K10S FEATURES OVERVIEW AND GENERAL DESCRIPTION products to use and probably should be avoided until Synopsys decides that they want to be in this market It is generally not worth your time to preserve your Synopsys ASIC compiler directives and scripts by using the FPGA synthesis products from Synopsys The time you save using Snopsys products is offset by other hassles Synthesis The FPGA used on your 5000 105 is an EP1S80s F1508 package Notes EP1S60s available on request Unless you paid for a faster speed grade the 6 is what you will be getting 2 Assuming you have a synthesis tool other than Quartusll memories are best implemented by describing them behaviorally in your RTL four synthesis products are sophisticated enough to map your behav ioral descriptions into the memory blocks It is NOT necessary to instantiate memories manually unless you are synthesizing with Quartus Make sure however to check the report files to make sure that your memories were implemented in memory blocks if this is possible If input and output registers in your RTL don t match the behavior of the embedded memory blocks the synthesis program may not recognize what you intended
180. dant Each of the steps must start and execute flaw lessly before the next step occurs When you get a PCI card for the first time it is necessary to debug each step before attempting to go to the next We provide utilities to help with each step Steps 1 and 2 are best done without an operating system in place Windows NT based systems take minutes to reboot after a crash the BLUE screen of death and an NT driver won t work unless the hardware is debugged Since crashing is a regular occurrence in a PCI hardware debug environment we find it easiest to do our debug and manufacturing test in the old DOS environment Virtually all PCI peripherals get configured with addresses beyond the IM boundary On a PC C programs cannot access memory locations beyond IM unless special programs called DOS extenders are used Several freeware DOS extenders are available We use a free DOS extender called DJGPP More information can be found at http www delorie com DJGPP PC Based AETEST EXE A utility program called AETEST is provided with the ET5000k10S AETEST can be run under DOS Windows 98 ME Windows NT 2000 or LINUX When used under DOS you must boot your PC with a DOS disk We ship one with the ET5000k10S in case you don t know how to make one on your own features work in the native mode of AETEST which is DOS 5000 105 USER S MANUAL 9 1 UTILITIES AETEST Utility Installation Instructions source code for AETEST is p
181. date the CPLD The connections are on header P4 The relevant signals and the connections to P4 are listed in Table 2 2 Figure 2 10 shows the location of P4 2 14 EMULATION TECHNOLOGY INC ET5000K10S FEATURES OVERVIEW AND GENERAL DESCRIPTION Table 2 2 Signals and Connections to P4 Cable P4 Signal m omemume 3 _ om omemum 3 e 3 25 zz css Em m J3 mm mm e e 22 255 254 29 ces cs HBHHEHEHEBE BE PA BERG 4 fe Redi Es tan TO a 7 R 11111111 8 mm z eo m 20 m ui n t 2 JP3 11111111 Rs 806 Figure 2 10 Location P4 the ET5000k10S 5000 105 USER S MANUAL 2 1 T5000K10S FEATURES OVERVIEW AND GENERAL DESCRIPTION Some Miscellaneous Notes the CPLD X1 is a 48 MHz oscillator This part i
182. dia card can contain other files 2 20 EMULATION TECHNOLOGY INC ET5000K10S FEATURES OVERVIEW AND GENERAL DESCRIPTION Example of main txt J start or file Verbose level 2 Sanity check y FPGA fpgabP rbr the line above configures FPGA F a file fpgaF rbf end of main txt Given the above example file e Verbose level is set to 2 e Asanity check on the bit files will be performed FPGA F will be configured with file fogaF rbf Starting Fast Passive Parallel Configuration If using the reference design SmartMedia card that came with the 5000 105 then no files need to be copied to the card Otherwise copy your RBF file and main txt to the root directory of the SmartMedia card using the FlashPath floppy adapter Make sure the jumpers on JP1 are set for Fast Passive Parallel as shown in Table 2 4 Table 2 4 JP1 Configuration Jumper Settings Pins 9 10 Pins 7 8 Pins 5 6 MSEL 2 MSEL 1 5 Configuration Mode et om ot Set up the serial port connection as described above in Setting up the Serial Port P2 RS232 Port on page 17 Next place the SmartMedia card in the SmartMedia socket on the ET5000k10S and turn on the power NOTE the card can only go in one way The SmartMedia card is hot swappable and can be taken out or put into the socket even when the power is on Once the power has been turned on the configuration process will begin as long as
183. downloads section of our web page you can find a document called ET5000k10 S Frequently Asked Questions FAQ We will update this document occasionally with information that may not be in the User s Manual Relevant Information Information about PCI can be obtained from the following sources The PCI Special Interest Group has a web page that has lots of good stuff Copies of the latest PCI specification may be ordered here ET5000K10S USER S MANUAL http www pcisig com PCI Special Interest Group 2575 NE Kathryn St 17 Hillsboro OR 97124 FAX 503 693 8344 GETTING STARTED Conventions As of June 2003 the most current versions of the PCI Specifications are PCI Local Bus Specification Revision 3 0 PCI Hot Plug Specification Revision 2 0 PCI Power Management Interface Specification Revision 1 1 PCI X Addendum to the PCI Local Bus Specification Revision 1 0a Other recommended specifications include PCIMG 2 0 Compact PCI Specification Revision 2 1 or greater PCI Industrial Computer Manufacturers Group PICMG 401 Edgewater Place Suite 500 Wakefield MA 01880 USA TEL 781 224 1100 FAX 781 224 1239 http www picmg org The best book to get if you need an introduction to PCI is PCI System Architecture Fourth Edition MindShare Inc Tom Shanley and Don Anderson Ignore some of the ignorant statements made in the Customer Review section at http www amazon com This is an excellent book for PCI and we
184. ds for yes n for no If the line is missing or the character after the is not y or n then the sanity check will be enabled For each FPGA that the user wants to configure there should be exactly one entry in the main txt file with the following format FPGA F example rbf In the above format the following FPGA is to signal that this entry is for FPGA F and FPGA F would then be configured with the bit file example rbf The 5000 105 has one to five FPGAs which are FPGA A B D E and F The example has only one FPGA which is FPGA F There can be any number of spaces between the the configuration file name but they need to be on the same line Comments are allowed with the following rules 1 All comments must start at the beginning of the line 2 All comments must begin with 3 If a comment spans multiple lines then each line must start with Commented lines will be ignored during configuration and are only for the user s purpose Thefile nain txt 15 NOT case sensitive IMPORTANT configuration file names have a maximum length of eight 8 characters with an additional three 3 for the extension Do not name your configuration files with long file names In addition all file names should be located in the root directory of the Smart Media card no subdi rectories or folders are allowed Since the main txt file controls which file is used to configure the FPGA the Smart Me
185. e address latching function is done via LVT373 1 The microprocessor has the following responsibilities Reading the SmartMedia Configuring the Stratix FPGA e Executing ET5000k108 self tests Other than FPGA configuration the pP has no responsibilities Less than 2596 of the 128 Kbytes of FLASH is used for FPGA configuration and utili ties so you are welcome to use the rest of the resources of the uP for your own purposes Instructions for customizing the pP are contained in the file Custom ATmegal28L pdf This file is the cd rom it can down loaded from the Emulation Technology Inc web page REMEMBER You can use the microprocessor for your own purposes We ship a programming cable for the ATmega128L with the ET5000k10S Updates to the code will be posted on our web site If you wish to do your own development you will need the compiler which we do not ship with the product The compiler is available from IAR http www iar com The part number is EWA90PCUBLV 150 Note that if you are willing to program the FPGA with the JTAG or serial cable the CLPD and the pP have no function In this case you can use all of the resources of the uP for your own purposes The Some 1281 is gross overkill for the FPGA configuration function The Details datasheet and user s manual are the CD ROM that was shipped with the ET5000k10S The file names 128 UM
186. e du propietaire Propriete de C BERG ELECTRONICS ELECTAONICS All rights strictly reserved Reproduction or issue to third parties in any form whatever is not permitted without written authority from the proprietor Property of BERG ELECTRONICS Copyright BERG ELECTRONICS INC PRODUCT SEE TABLE DIM PUS 1 003 0 08 000 0 0 0 050 61 27 DIM 2 004 10 0 045 91 14 005 0 08 E 000 0 0 RO 110 R2 79 100 2 54 REF 2 160 4 06 090 2 29 0000000000000000000000000000000000000000 200000000000000000000000000000000000000 ee 0 220 5 58 ee REF 2X FULL R TYP 410 10 41 00000000000000000000000000 025 0 64 050 1 27 FRAME TO BOARD 4 002 05 CONTACT AREA 0 075 1 91 WP 0 015 0 38 004 103 0 050 1 27 REF 2X 005 13 GIA 8 ex DIM 0 PROPOSED TERMINATION REQUIREMENTS Wl TM 0 160 4 06 REF 0 480 12 010 25 OY i 0 052 1 33 010 25 G x 2X REF 0 010 001 25 03 L X DIM B REF KEY SIDE BOTTOM VIEW 1 code tolerances unless otherwise specified RG tr no dr 301 EL
187. e test 1 VENDOR ID 71f3 DEVICE ID 2454 AntiFuse test 2 VENDOR ID 507 DEVICE ID 2367 AntiFuse test 3 VENDOR ID bc92 DEVICE ID 2e6c AntiFuse test 4 VENDOR ID e125 DEVICE ID c38c AntiFuse test 5 VENDOR ID e62c DEVICE ID ca76 AntiFuse test 6 VENDOR ID 448b DEVICE ID e6a Emulated with 8051 VENDOR ID 1243 DEVICE ID 4321 PCI Device VENDOR ID 5143 DEVICE ID PCI Device sensor board VENDOR ID dead DEVICE ID beer LYNX 9610 VENDOR ID 10b5 DEVICE ID 9610 Didn t find known device in the following list vendor id 5045 vendor vendor id abcd vendor id abcd vendor id abcd vendor id abcd vendor id 1234 vendor id 1234 vendor id 11e3 vendor id 1010 vendor id 71f3 device device 1951234 device 141 1225 device 19 1236 device 141224 device 1951240 device 19 5678 device 1d 5679 device 6 device id 5064 device id 2454 vendor 101 207 device 1092307 vendor id bc92 vendor 128 vendor id e62c vendor id 448b vendor id 1243 vendor id 5143 vendor id dead vendor 1d 10b5 device id 2e6c device id c38c device id ca76 device 1 device id 4321 devige device device 1d 9610 Hit a key to continue Figure 9 2 AETEST Startup Screen No PCI Peripheral Recognized AETEST will still run but many product specific options will not be avail able 5000 105 USER S MANUAL 9 UTILITIES AETEST Main
188. epted on the same clock cycle as the activation signal and address and read data is returned one clock cycle after it is requested Syncburst is designed to allow two controllers to access the same SSRAM using two activation signals ADSC ADSP an activation with ADSP requires data and byte enables one clock cycle after the address and activation Syncburst PL Pipelined Figure 5 6 is identical except for registered outputs which delay read data an additional clock cycle but may be necessary for high speed designs Zero Bus Turnaround ZBT SSRAMs are designed to eliminate wait states between reads and writes by synchronizing data Thus ZBT SSRAMs Figure 5 7 accept and return data one clock cycle after the address phase and ZBT PL SSRAMs Figure 5 8 accept and return data two clock cycles after the address phase This allows the user to begin a write burst imme diately after the last word of a read burst because read data will be returned before the first write data is required The timing is illustrated in Figure 5 9 and Table 5 2 EMULATION TECHNOLOGY INC Write Control Logic 18 2 Burst E Control 1 0 Address Register Output Buffers Read Control Logic Figure 5 5 Syncburst FT Write Control Logic 18 2 EN Burst B Control 5 9 Memory Address Register Control Logic Figure 5 6 Syncburst PL 5000 105 USER S MANUAL 5 In
189. er consists of GND pins in row A various inputs in row 43 3 V pins in row C The layout of the headers is shown in Figure 4 6 5000 105 USER S MANUAL 4 CLOCKS AND CLOCK DISTRIBUTION Clock A E L ROBOCLOCK1 Phase Control Logic Frequency VCO Divide and Phase i1 Clock Selection d REFB OUTPUT MODE 22 PLLSEL1 FS gt and ase select Matrix gt and Ss Phase select 7 01 D Divide Ss Phase select lt Matrix gt D Ss Divide and Phase select E Matrix i DCLK 7 2 Divide and Phase select E Matrix 5 gt lt Gm Gm Gm gt lt gt Gm gt lt gt lt gt lt gt Gm gt 3 PLLSEL2 Clock B FBFO MODE1 Duplicate of Clock A FBDSO See details above FBDS1 Divide and Phase select Matrix FBDIS JP9 B 2 gt B 4 INK gt Divide an 4080 Phase select gt 405143 Matrix FBDSO1 I FBDS11
190. exibility 5000 105 USER S MANUAL 4 11 CLOCKS AND CLOCK DISTRIBUTION Useful Notes and Hints The CY7B993V 4V can output LVTTL complementary differential signals too Setting INV1 INV2 LOW will result in clocks CCLK 1 0 and CCLK 3 2 ECLK 1 0 and ECLK 3 2 becoming complementary pairs Anetwork of series and parallel resistors could be used to reduce the nominal swing of the clock signals The CYB993V consistently outputs 32 5 MHz signals in cases of improper settings or unacceptable clock inputs This was observed when CY7B993V part was operating at a nominal frequency of 36 4 MHz with FS set LOW e Identical clocks were sent to PLL2B and PLL2BN For the CY7B994V part the operating frequency can reach up to 200 MHz However the maximum output frequency is 185 MHz This means when 185 MHz lt 200 MHz the output divider must be set to at least 2 Otherwise the Roboclockll s will output garbage Customizing the Oscillators The user can customize the frequency of the clock networks by stuffing oscillators in X2 and X3 The ET5000k108 is shipped with a 14 318 MHz oscillator in location X2 and 100 MHz oscillator in X2 The Roboclockll s are not 5 V tolerant so 3 3 V oscillators are necessary NOTE If you stuff your own oscillators 3 3 V CMOS outputs are necessary since the Roboclockll s are not 5 V signalling tolerant We get our oscillators from Digi Key http www d
191. f this initial display is debug information The program is looking for a Vendor and Device ID that it recognizes and finds vendor 0x17DF device 0x1505 which is a ET5000k10S The lines after Configura tion space show what is in the configuration space and how the BARs are configured EMULATION TECHNOLOGY INC UTILITIES Searching Searching searching Searching Searching Searching Searching Searching Searching Searching Searching Searching Searching Searching Searching Searching Searching Searching Searching Searching for for for for for for for for for for for for for for for for for for for for If AETEST does not see a PCI peripheral it recognizes you will see the following Figure 9 2 Quad Sharc VENDOR ID 5045 DEVICE DN2000K10 Asic Emulator VENDOR ID abcd DEVICE ID 1234 DN2000K10 Asic Emulator 12000 VENDOR ID abcd DEVICE 1235 DNZO00UKIO Asic Emulator l000E VENDOR ID abcd DEVICE ID 1236 DN2000K10 Asic Emulator 1600E VENDOR ID abcd DEVICE ID 1237 DN3000K108 Asic Emulator 6000 VENDOR ID abcd DEVICE ID 1240 q15064 q15064 q15064 q15064 q15064 q15064 q15064 q15064 415064 415064 415064 Greg s Cohu s interface test VENDOR ID 1234 DEVICE ID 5678 64 dram LFSR VENDOR ID 1234 DEVICE ID 5679 PowerPC bridge VENDOR ID 11e3 DEVICE ID PowerPC bridge old VID DID VENDOR ID 1010 DEVICE ID 5064 AntiFus
192. for each Roboclockll derived clock is given in Table 4 7 Based on the following information the user will be able to adjust the skew for any of the Roboclockll outputs ty Table 4 6 Time Unit N factor CY7B993V CY7B994V MHz MHz at which at which ty 1 ns ty 1 ns 4 10 EMULATION TECHNOLOGY INC CLOCKS AND CLOCK DISTRIBUTION Table 4 7 Clock Skew Settings Input Signals Output Skew Function RB C F FO DCLK 3 0 DCLK 7 4 CCLK 3 0 CCLK 7 4 Feedback RB C F F1 and or or or ECLK 3 0 or ECLK 7 4 Output FBFO 2 1 11 8 ECLK 15 12 1 LOW clock skew is equivalent to the skew on DCLK 3 0 or ECLK 11 8 The clock skew is equivalent to the skew DCLK 7 4 orECLK 15 12 Differential in addition to LVTTL clock signals the Roboclockll clock buffers can handle Clocks LV Differential LVPECL clocks The user can cable in an acceptable differ ential signal to PLL1B and PLLIBN or PLL2B and PLL2BN through the clock grid JP6 The signals must obey the specifications given in Table 4 8 Onboard circuitry is available to center the signals about the proper voltage if needed Table 4 8 LVPECL Input Specifications Description Differential Voltage The clock input of the Roboclockll can accept a superset of PECL PECL involves a 1 V swing about 2 Roboclockll clock input can accept a swing of up to 3 3 V about 2 which gives the user another dimension of fl
193. from Altera for this function The datasheet is on the CD ROM and is titled epm3256a pdf Approximately 90 of the resources of this device are utilized so 1096 are available for your own purposes The Verilog source for the CPLD is provided on the CD ROM The file name is CPLD V The CPLD performs the following functions nterface to ATmega128L and SRAM Clock Output to uP Data Lower Address 7 0 Upper Address UPPADDR 15 8 Control Signals ALE RDn WRn SRAM Select SRAM CSn Data Retrieval from SmartMedia Card Data Bus SM 7 0 Control SM_CLE SM SM WEn SM WPn SM CEn SM REn SM RDYBUSYn Configuration and Clock Status Reporting CPLD LED 3 0 ROBO LOCK1 ROBO LOCK2 Control of FPGA Parallel Configuration Clock FPGA DCLK Chip Select CSnF FPGA CEnF Control FPGA nCONFF CDONEF FPGA IODONEF FPGA RDYnBUSYF Data Bus FPGA D 7 1 FPGA Mode Selector Switches MSEL 2 0 0 Pass Through of Serial JTAG Cable Signals Cable DCLK TCK CONF DONE TDO nCONFIG TMS MSTATUS DATAO TDI FPGA Chain CPLD TMS CPLD CPLD TDI CPLD TCK CPLD TRST Support for Clocking Schemes CPLD Clock Input 48 Inputs from Clock Buffers CLK 1 0 Output to Clock Grid PCPLD CLKOUT e Interface to Reset Schemes FPGA GRSTn PWR_RSTn We may periodically up
194. g Mas LLL 9 184 mm s mmm 000 W ET5000K10S USER S MANUAL 7 1 DAUGHTER CONNECTIONS ET3K10SD OBSERVATION DAUGHTER CARD FOR 200 PIN CONNECTORS Table 7 2 Daughter Board Header FPGA Pin Map Daughter Test J1 Signal P8 m menn _ mmus zs _ _ men za _ mw mem 7 14 P8 Signal FPGA Pin Test Header P9 Signal P9 253 EMULATION TECHNOLOGY INC RESET SCHEMES LEDS BUS BARS AND 200 PIN CONNECTORS Chapter 8 Reset Schemes LEDs Bus Bars and 200 Pin Connectors Reset Schemes A LTC1326 chip from Linear Technology controls reset functionality for the ET5000k10S Figure 8 1 shows the distribution of the reset signal PWRRST In addition to controlling the reset the power supplies rails 5 V 3 3 V 2 5 41 5 V are threshold detected by the LTC1326 Undervoltage conditions will case the assertion of the reset signal The LTC1326 has a push button Momentarily depressing this button causes 200 ms reset pulse on the signal PWRRST If the push button is depressed 2 seconds and held PwRRST is asserted continuously LED5 when lit means that reset is asserted so if you press and hold S1 you should see LED5 illuminate after a few seconds If LED5 illuminates for any reason during no
195. hat means either there is no power on the 5000 105 there is another program open that is using the serial port or the serial cable connecting the AVR tool is not connected properly If this happens 2 12 EMULATION TECHNOLOGY INC ET5000K10S FEATURES OVERVIEW AND GENERAL DESCRIPTION you should close down the window titled STK500 correct the situa tion and then select TOOLS STK500 AVRISP JTAG ICE again You will not be able to continue unless you see something very similar to the following at the bottom of the STK500 window Detecting AVRISP found on COMI Getting revisions HW 0x01 SW Major 0x01 SW Minori 0x07 0K 7 the PROGRAM tab select the ATmega128 under the DEVICE drop down menu and in the FLASH section where it says INPUT HEX FILE browse and select the file ET5000k10S_128 a90 that can be found in the downloaded zip file uP_CPLD zip from the Emulation Technology Inc website To program the device all you need to do is hit the PROGRAM button in the FLASH section When the program ming is complete it takes about 45 seconds you should see a mes sage at the bottom of the window that looks something like this Detecting AVRISP found on COMI Getting revisions HW 0 01 SW Major 0 01 SW Minors Reading FLASH input file OK Setting device parameters serial programming mode OK Entering programming mode OK Erasing device OK Programming FLASH using block mode 100 Leavi
196. he default option and click on Next 4 Waituntil it finishes new hardware device searching choose Add a new device and click on Next 5 Choose No I want to select the hardware from a list and press Next 7 6 Choose Other Devices from Hardware Types list and press 7 Click on Have Disk EMULATION TECHNOLOGY INC UTILITIES 8 In Copy Manufacturer s Files From window find the directory where gldriver sys Is located then press 9 You should see dn2000k10 driver under Models click on Next 10 Press and then Finish 11 Run aetestnt exe Installation Instructions for LINUX This has been tested on Red Hat Linux 7 2 kernel version 2 4 x Note that all the text files including the scripts are DOS text format with an extra carriage return character after every new line so you need to convert them 1 You must be root to start the driver and the program load and dndev unload are scripts that load and unload the driver dndev o is the driver file Load the driver type sn load Unload the driver type sh dndev unload After driver is loaded run the utility linux p dem M Note You might need to run chmod on aetest 1inux to make it executable type chmod u x aetest linux Installation Instructions for Solaris The utility and driver are tested on Solaris 7 0 Sparc with the
197. he following fill options are available 1 fill with 0 fill all the locations with 0x00000000 clear the memory 2 address data fill each long word with its address 3 alternating 0x55555555 OxAAAAAAAA 5000 105 USER S MANUAL 9 11 UTILITIES 31515 841 HAHA Hmmm B Hmmm HB HaHa Hinc B Hime H 98128 48 315158 HBH1cH Hm 28 4H tCh ack Oxffffffff set all of memory 5 data address fill each long word with the address each bit inverted Memory Display Display 160 long words of memory You are prompted for the starting address in hex Input starting address hex and 32 bit aligned The following screen is displayed Figure 9 10 4 HAHAHAH 44244 HAHAHAH HAHAHAH HAHAHAH HAHAHAH HAHAHAH 1 15151515111512 HAHAHAH 24 HAHAHAH HAHAHAH HAHAHAH Cj ump gotocB 4 114 24044144 244124 2404 124 24 14 1515 215151515 51510 40 4 224044144 24044124 24044114 214 4 16 19 Hindi paganan 24 24 Hmmm Hindi Hindi Hindi Hind 244 244 HAHAHAH 14 2 15151515151512 444 44 Hin 2
198. his cable comes pack aged with a bracket attached Remove the bracket to eliminate the possi bility of it falling on the 5000 105 which could short signals and damage the board After you have removed the bracket plug the cable into P2 P2 is not keyed so make sure you get the orientation correct Pin 1 is identified with the number 1 and a dot Figure 2 11 is a cutout from the assembly drawing and shows the location of P2 and Pin 1 5000 105 USER S MANUAL 2 1 T5000K10S FEATURES OVERVIEW AND GENERAL DESCRIPTION e e e e o 0 0 0 O O O O O O O O O e Cs Eg i33 20 zs cs E ES B a fast E p sd al d Fl Es BAAR Fd Fd d 19 ol d 3 ldk 1 Ssmi Sisal 8 a ls Be EE 2 alla E 1 2 823 9 RN2 RN31 RN34 RN3GRN3G RNA J 4 34 4 ws SIE EE Se RN36 154 1544 42 4 2 ee 2 Ruta 54 eod ede e RNA unn 5 s 5 unii 2 E
199. igikey com Of note is an Epson line of oscillators called the SG 8002 Programmable Oscillators Any frequency between 1 00 2 106 25 MHz can be procured in the normal Digi Key shipping time of 24 hours A half can 3 3 V CMOS version is needed with a tolerance of 50 ppm The part number for an acceptable oscillator from this family would be SG 8002DC PCB ND package SG 531 output enable 3 3V CMOS 50 ppm If the order is placed via the web page the requested frequency two decimal places is placed in the Web Order Notes The datasheet is on the CD ROM for this oscillator The file name is SG8002DC pdf EMULATION TECHNOLOGY INC CLOCKS AND CLOCK DISTRIBUTION Any polarity of output enable for each oscillator on pin 1 is acceptable Make sure that you have the proper jumper settings at positions 9 and10 of JP9A JP9B and JP9C See Figure 4 7 and Table 4 9 for a description 3 3V JP9C D FS1 FBFO1 FBDSO1 FBDS11 FS2 FBFO2 FBDSO2 FBDS12 OSCA 26 OSCB 29 HEADER 10x3 HEADER 10x3 HEADER 10x3 Figure 4 7 Clock OE Pin Jumper Settings Table 4 9 Clock OE Pin Jumper Settings Clock Jumper Settings ET5000k10S PCI_CLK Operation ET5000k10S ASIC emulation board has the ability to run the FPGA all SSRAMs SDRAM and DDR SDRAM off of PCI_CLK is a single desti nation clock which is routed to FPGA F U11 from the PCI connector The user can input PCI_CLK to the Stratix Enhanced
200. ire columns squeezed between two LAB columns Each LUT can implement any Boolean function of four inputs An LUT can also be configured as a two input adder subtractor with a carry chain coming from the adjacent LE and going to the next LE In order to reduce delays caused by long carry chains each set of 5 LEs computes two adder 5000 105 USER S MANUAL 2 3 T5000K10S FEATURES OVERVIEW AND GENERAL DESCRIPTION Embedded Memory LAB Carry In sadnih Carry In1 Carry InO data1 data2 data3 data4 Chip Wide Reset Clock amp Clock Enable Select labclk1 labclk2 labclkena1 labclkena2 2 4 results simultaneously then uses the carry result from the previous set of 5 to select which result is correct The flip flop in each LE includes a clock enable input an asynchronous preset and reset synchronous set and reset logic and an asynchronous load function Data input can come from the LUT in the same LE to register addition or boolean outputs or the LUT and flip flop can be used indepen dently of each other For more information check www altera com for the Stratix datasheet Stratix has boatloads of embedded memory The EP1S80 contains 767 blocks of 576 bits 364 blocks of 4 5 Kbits and 9 blocks of 576 Kbits The smallest memory blocks called M512 RAM can be configured for data widths ranging from 32 x 18 bits to 512 x 1 bit medium sized blocks MAK RAM can be configured ranging from 128 x 36 bits to 4K x 1
201. led with a sticker marked reference design The other Smart Media card is empty and is for use with your own designs To configure the FPGA with the refer ence design please skip to Starting Fast Passive Parallel Configuration on page 21 Creating RBF Files for Fast Passive Parallel To create an RBF file with Quartusll software Go to Assignments menu and drag down to Settings Click on Device under Compiler Settings on the left then click the Device amp Pin Options button on the right Go to the Configuration tab select Configuration Scheme Fast Passive Parallel and disable the option to Use Configuration Device Go to the Programming Files tab turn on Raw Binary File 7 1 and turn off all other options Note the sof file for programming will also be created The easy way to assign pins is to create your project then open the csf file created in a text editor If your pinlist is formatted correctly you can copy it and paste it into the csf file in the section labeled CHIP design name Sample files on the software CD provided found in the folder labeled Verilog show how to format the information and provide the correct pinlist for the signal names used on the board Setting up the Serial Port P2 RS232 Port P2 is for an RS232 connection to a terminal An ICL3221 U2 provides voltage translation to RS232 levels A cable that converts the 10 pin header to 9 is shipped with the 5000 105 T
202. ll worth the money The best book to get if you need an introduction to PCI X is PCI X System Architecture MindShare Inc Tom Shanely and Karen Gettman You are going to need to know Verilog or VHDL to use the Stratix FPGA If you need a reference we recommend the following book for Verilog Verilog HDL A Guide to Digital Design and Synthesis Samir Palnitkar ISBN 0 13 451675 3 If you are one of those people that actually like VHDL we feel sorry for you The following books may be helpful Essential VHDL RTL Synthesis Done Right Sundar Rajan The IQ Booster Improve Your IQ Performance Dramatically Edwin Breecher This manual uses the following conventions An example illustrates each convention The term PCI X will be used generically unless there is a specific instance where PCI applies This design guide generically refers to PCI X protocol EMULATION TECHNOLOGY INC GETTING STARTED Courier font denotes the following items Signals on PCI Bus side of the PCI X Interface FRAME IO PCI X Interface signal name PCI X Bus signal name Signals within the user application BACK UP 5 Command line input and output setenv XIL LOC CLOSED HDL pseudocode assign question to be to be assign cannot have cake amp eat it Design file names peim Lop v peim Ltop vLhd Courier bold denotes the following items Signals on the user side of
203. ls A heat sink is used to keep the linear regulator within its specification The specification for the 3 3 V power is shown in Table 6 1 The 43 3 V supply is used by the following components on the 5000 105 Stratix FPGA I O 011 banks 1 6 Roboclocks U14 U15 Clock buffer U12 CPLD U6 Microprocessor 04 Microprocessor SRAM U7 4 SSRAMs 8 U9 U10 U13 DDR SDRAM DIMM J3 3 Oscillators X1 X2 X3 We do run 43 3 a little hot At worst case for all components the 43 3 V power supply should never fall below 3 30 V Table 6 1 Specification for 3 3 V Power Minimum Typical Maximum Voltage 3 35 3 39 3 44 The specification for 2 5 V power is shown Table 6 2 The 2 5 supply is used by the following components on the 5000 105 e Stratix FPGA I O 011 banks 7 8 DDR SDRAM DIMM J2 In addition the 42 5 V supply outputs a 1 25 V power rail used by the Stratix FPGA as a reference voltage The reference voltage tracks to the supply voltage within 1 EMULATION TECHNOLOGY INC POWER SUPPLIES AND POWER DISTRIBUTION 1 5 V Power Table 6 2 Specification for 2 5 V Power and 1 25 V Reference Min Typical Supply Current N A N A Reference Voltage 49 596 of 5096 of 50 596 of Supply Supply Supply Reference Current N A N A The specification for the 1 5 V power is shown in Table 6 3 The 1 5 V supply is used by the following component on the
204. main txt Maker ID Device ID and size of Smart Media files found on Smart Media card If sanity check is chosen the RBF file attributes will be dis played part package date and time of the RBF file During configuration a will be printed out after each block 16 KB has successfully been transferred from the Smart Media to the current FPGA Sanity Check The Sanity Check if enabled verifies that the RBF file was created for the right part the right version of Altera was used and the Quartus options were set correctly If any of the settings found in the RBF file are not compatible with the FPGA a message will appear from the serial port and the user will be asked whether or not they want to continue with the RBF file Please see the section Creating RBF Files for 5000 105 USER S MANUAL 2 19 T5000K10S FEATURES OVERVIEW AND GENERAL DESCRIPTION Fast Passive Parallel on page 17 for details on which Quartus options need to be changed from the default settings Format The format of the main txt file is as follows The first nonempty uncommented line main txt should be Verbose level X where X can be 0 1 or 2 If this line is missing or X is an invalid level then the default verbose level will be 2 The second nonempty uncommented line in main txt tells whether or not to perform a sanity check on the bit files before configuring an FPGA Sanity check y where y stan
205. me manner for the feedback and the normal clock outputs See Clock Division on page 9 and Clock Skew on page 10 respectively Clock Division Thethree pairs of DS inputs per chip are used to control the two groups of clock outputs and the feedback outputs of each PLL The user can simply follow the Divider Function Table to acquire the desired output frequency There two things to remember First FS 2 1 must set properly according to fNOM Second the FBDS feedback inputs act as operating clock frequency multipliers The Output Divider Settings are shown in Table 4 5 Table 4 5 Output Divider Settings Input Signals Output Divider Function C fF DS1 and C F DSO and FBDS1 2 1 FBDSO 2 1 Feedback Output Output Signals Signals Ow mw o a ow NN 5000 105 USER S MANUAL 4 9 CLOCKS AND CLOCK DISTRIBUTION Table 4 5 Output Divider Settings Input Signals Output Divider Function C fF DS1 and C F DSO and FBDS1 2 1 FBDSO 2 1 Feedback Output Output Signals Signals Clock Skew Clock skew is controlled by the inputs The clock skew may be any integer value from 0 to 8 times the Roboclockll time unit ty The time unit value is derived from the operating frequency and the FS 2 1 setting The following equation yields the time unit ty 2 1 f vou The possible values for N are given in Table 4 6 The available skew
206. must have jumper connecting pins 9 amp 10 to send ECLK 8 to DDR SDRAM receive ECLK signals To complete this setup a feedback signal must be connected to the PLL in FPGA Roboclockll sends 12 to the feedback input of the FPGA ECLK 12 needs to be connected to the fbin input signal of the PLL Using ECLK 12 as feedback allows the PLL to properly synchronize the ET5000k10S CLK network which completes the setup see Figure 4 8 for a diagram of the circuit FPGAF ECLK 12 Figure 4 8 PCI CLK PLL Circuit The 5000 105 can be run off any single ended TTL clock signal which is sent to the Roboclocks The distribution provides the 5000 105 this flexibility has special implications for the ET5000k10 PCI opera tion GCLKOUT Is assigned to a dedicated clock output pin in the Stratix architec ture and can be used to drive Roboclock 2 see the section ET5000k10S PCI CLK Operation on page 13 for details The ET5000k108 differs from previous emulator boards because the Stratix architecture assigns each PLL to specific clock pins In the case of GCLKOUT the only possible source is from PLL5 which has only one possible input So the sole purpose of GCLKOUT is to provide the means to run the whole board with PCI CLK Each of the two 200 pin header P8 and P9 receives a clock signal from each of the five clock groups ACLK BCLK CCLK DCLK and
207. n connections can be used for external TTL connections to the externally generated interrupts or any other function that the ATmega128L supports on these pins Remember that the ATmega128L is not 5 V tolerant so if you attach external TTL signals to these pins the voltage level of these signals must not exceed 3 3 V The P1 schematic is shown in Figure 2 7 EMULATION TECHNOLOGY INC ET5000K10S FEATURES OVERVIEW AND GENERAL DESCRIPTION uP GPIO P1 P D2 03 2 04 gt 05 07 SM CDn WF n 57193 04 7 3 E 5 06 07 Figure 2 7 P1 Unused Connections uP JTAG 3 3 3V PWRRSTn Figure 2 8 P7 JTAG Interface PDO INTO PD1 PD2 INT2 PD4 IC1 PD5 PD6 T1 PD7 T2 z h PFO ADCO PF1 ADC1 PF2 ADC2 PF3 ADC3 PF4 ADC4 PF5 ADC5 PF6 ADC6 PF7 ADC7 ATmega128L 1281 processor has JTAG interface that can be used for on JTAG Interface debugging real time emulation and programming Of FLASH EEPROM fuses and Lock Bits In order to take advantage of the JTAG inter face you must have the Atmel AVR JTAG ICE kit part number ATAVR JTAGICE and AVR studio software that Atmel provides free at 5000 105 USER S MANUAL 2 11 T5000K10S FEATURES OVERVIEW AND GENERAL DESCRIPTION www atmel com The JTAG interface for the ATmega128L can be accessed through header P7 of the 5000 10
208. nce The PCI PCI X edge connector is shown in Figure 3 2 Stratix parts cannot tolerate 5 V ttl signaling so the ET5000k10S must be plugged into a 3 3 V PCI slot PCI X by definition is 3 3 V signaling The PWB is keyed so that it is not possible to mistakenly plug the board into a 5 V pci slot NOT grind out the key in the PCI host slot and Do NOT modify the ET5000k10S to get to fit into the slot If you need a 3 3 V PCI slot the ETPCIEXT S3 Extender card can do this function This extender also has the capability to slow the clock frequency of the PCI bus by a factor of two a function that is very useful when prototyping ASICS NOTE 5 V Signaling on Stratix parts causes them to smoke This is quite BAD Do NOT Modify the 5000 105 board to fit into your pci slot PCI Mechanical 5000 105 is not a standard sized PCI card it is too tall and slightly Specifications too long This is sometimes an issue in servers that have a bracket installed over the top of the PCI cards If you need to close the case on a ET5000k108 some tower configurations may work Figure 3 3 shows the exact dimen sions the ET5000k10S Some Notes on 23 3V power is not needed on the host PCI connector 43 3 V power is the derived from 5 V using an on board 10 A switching regulator Power ET5000k10S distribution for the 5000 105 is described in Power Supplies and Power Distribution on page 1 and PCI PCI X
209. ng programming mode OK 8 After programming the processor close all AVR Studio windows and setup the serial port according to the section titled Setting up the Serial Port P2 RS232 Port on page 17 Please note that in this sit uation connecting the serial port is mandatory and the FPGA cannot be configured via the SmartMedia card until you have completed all the instructions in this section 9 Reset the 5000 105 by pressing S1 After about 5 seconds you should see the following in the HyperTerminal window Please select the FPGA on the board Enter one of the FPGA locations on your board that contains an FPGA and you should see the following menu 1 Virtex II 1000 456 2 Virtex II 6000 FF1152 3 Virtex II 4000 FF1152 4 Virtex 3000 676 5 Virtex II 8000 FF1152 6 Altera Apex II 2A40 7 Altera Apex II 2A70 8 Altera Stratix 1580 1508 7 Please enter selection 1 6 for FPGA D 5000 105 USER S MANUAL 2 13 T5000K10S FEATURES OVERVIEW AND GENERAL DESCRIPTION Enter option 8 for Stratix FPGAs 10 The processor and the CPLD are now ready to configure the FPGA S Please see the section titled Starting Fast Passive Parallel Configura tion on page 21 for further instructions CPLD Some non volatile logic is needed to handle the counters and state EPIM3256A _ machines associated with the high speed interface to the SmartMedia card We used an 3256 CPLD
210. nknown device Under Models select unsupported device DU d 29 18 The driver file aetest98 exe must be in the same directory Run aetest98 exe NOTE re compile the driver file pcicfg vxd you need the VtoolsD compiler from www numega com Startup When AETEST is first started it tries to find a device that it recognizes We have arbitrarily defined the 5000 105 with a DEVICE of 0x1505 and a VENDOR ID of 0x17DF You should see the following screen if AETEST recognizes 5000 105 Figure 9 1 searching for DM5HHHKi1H Stratix Asic Emulator 64 bit test UEHDOR ID 1 ud f DEVICE ID 15H6 searching for DH5HHBi1BH4d Stratix FPGA board ID i17df DEUIGCE ID 15H 5 found device 11701 41505 hus 2 d amp f 3H 5 4 Stratix FPGA board Configuration space 84 AHAHHH Hc HARRAH 14 fe4thhhhh HRA 24 HHAHHHHH 2c UBHahb56 78 34 HRA HHBBBBBH 122 000008 zize BHxHBHBdHHHHH zize HxHHB4HHHHH zize HxHHHHHHHH zize HxHHWBHHHHHH 1 gt HARRAH 1H 15H51 7d0f 7 HHHHHHHH 2 11 1 xf xf e 4660048 xf e HBHBBH xHHHHHBHBH xHHHBHBHBH Compiled on Jun 13 2883 at 13 38 22 press any key Figure 9 1 ET5000k10SAETEST Startup Screen ET5000k10S Recognized Most o
211. nnector mates with a standard off the shelf 3M cable assembly P N 14150 EZBB XXX OLC where 15 050 0 5 m 1502 1 5m 300 3 0 500 5 0 Please contact for further details http www1 3m comY Unbuffered The ET3k10SD Daughter Card provides 66 unbuffered I O signals including 5 single ended clock signals The function of these signals is position dependent NOTE Signals P4NX7 P4NX6 are also used for direction select output enable U2 U3 respectively Connectors P2 2 P4 Buffered Interface header IDC headers 50 providing 48 buffered signals See Table 7 2 on page 7 Connector P7 1 Unbuffered Interface Header P1 P3 IDC headers 50 pin providing 66 buffered signals See Table 7 2 on page 7 Buffered The ET3k10SD Daughter Card provides 48 buffered signals The func tion of these signals is position dependent U1 U2 and U3 allow for different populating options and devices can be active or passive Active The LCV162245A is used for asynchronous communication between data buses It allows data transmission from the A to the B or from the B to the A bus depending on the logic level at the direction control DIR input The output enable input can be used to disable the device so that the busses are effectively isolated Passive The FST163245 bus switches are used to connect or isolate two ports with
212. nput and Termination 4 4 4 4 External Ribbon Cable Connections 4 5 4 5 Functional Diagram of Roboclock 1 and Roboclock 2 4 6 4 6 Header 4 7 4 7 Clock OE Pin Jumper Settings 4 13 4 8 PCI CLK PLL Circuit 548 558 4 14 5 1 SSRAM 1 09 Bus Signals 5 2 5 2 SSRAM 2 010 Bus Signals 5 3 5 3 SSRAM 08 Bus Signals 5 4 5 4 SSRAM 4 013 Bus Signals 5 5 5 5 SyncDUrst FT iiic mE xum ER 5 7 5 6 SyncDurst PL 2i 8583 Seow Cue 5 7 5 7 Syncburst 2 2 2 22 2 2 22 22 5 8 5 8 Syncburst 2 5 8 5 9 Syncburst ZBT SSRAM Timing 5 8 5 10 SDRAM 019 Bus Signals Page 1 of 2 5 10 5 11 SDRAM J19 Bus Signals 2 of 2 5 11 ET5000K10S USER S MANUAL vii IST OF FIGURES List of Figures Continued FIGURE TITLE PAGE 5 12 DDR SDRAM 22 Bus Signals Page 1 2 5 13 5 13 DDR SDRAM 72 Bus Signals 2 of 2 5 14 5 14 DDR PLL Circuit Block Diagram 5 15 5 15 DDR Clock Select Jumper 5 15 6 1 ET5000k10S Power Distribution 6 1 6 2 Molex Connector P1 Auxiliary Power 6 4 6 3 Example Power Supply 6 4 7 1 E
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214. o contains adder subtractor accumulator registers which can be configured to provide many common DSP functions such as FIR or IIR filters FFT or DCT without the use of LAB resources The Stratix datasheet available at www altera com has more detailed information on how the multipliers and adders are configured for some common functions Figure 2 4 shows a DSP block configured for four 18x18 bit multipliers A DSP block can be configured as two parallel systems of 9x9 bit multipliers each of which is also described by Figure 2 4 The adder blocks can be used to add or subtract two or four multipliers such as in complex multiplica tion or to add a new result each clock cycle to an accumulated sum They are also used to configure the DSP block as a 36x36 bit multiplier with or without an accumulator registers in Figure 2 4 are optional as shown by Figure 2 5 which is a detailed view of a single 18x18 bit or 9x9 bit multiplier Any or all of the registers may be used to pipeline the multiplier logic and improve the clock speed or the alternate path may be used to bypass the register ALTQPRAM rdaddress a rden a outclock a outclocken a data wraddress a wren a inclock a inclocken a rdaddress b rden b outclock b outclocken b data b wraddress bf wren b inclock b inclocken b inaclr a outaclr a outaclr b inst Figure 2 3 Dual Port Data Flows 5000 105 USER S MANUAL 2 T5
215. on takes you to a menu titled Interactive Configuration Menu and allows the FPGA to be configured through a set of menu options instead of using the main txt file The menu options are described below Description of Interactive Configuration Menu options 1 Select a bit file to configure FPGA s This menu option allows the user to select a file from a list of files found on the SmartMedia card to use to configure the FPGA 2 Set verbose level current level 2 This menu option allows the user to change the verbose level from the current setting Please note if the user goes back to the main menu and configures the FPGA s using main txt the verbose level will be set to whatever setting is specified in main txt 3 Disable Enable sanity check for bit files This menu option either allows the user to disable or enable the sanity check depending on what the current setting is Please note if the user goes back to the main menu and configures the FPGA s using main txt the sanity check will be set to whatever setting is specified in main txt M Main menu This menu option takes the user back to the Main Menu described above 3 Check Configuration status This option checks the status of the DONE pin and prints out whether or not the FPGA s have been config ured along with the file name that was used for configuration 4 Select file to use in place main txt By default the processor uses the main t
216. out providing any current sink or source capabilities Thus they generate little or no noise of their own while providing a low resistance 7 6 EMULATION TECHNOLOGY INC DAUGHTER CONNECTIONS ET3K10SD OBSERVATION DAUGHTER CARD FOR 200 PIN CONNECTORS path for an external driver The output enable OE input can be used to disable the device so that the busses are effectively isolated Test Interface The ET3k10SD Daughter Card provides a 200 pin connector to interface to one of three test connectors the 5000 105 ASIC prototyping board J9 J10 and J16 Connector J1 J1 Test Interface Connector Micropax connector 200 pin used as a standard interface to all the Emula tion Technology Inc development boards This connector has a specified current rating of 0 5 amps per contact See Table 7 2 on page 7 Daughter Card I O Connections Table 7 2 shows the ET3k10SD Daughter Card Interconnects to connec tors P55 P56 and P58 Table 7 2 Daughter Board Header FPGA Pin Map Daughter Test FPGA Test Board Header P8 Signal Pin Header P9 Signal Header P8 U11 P9 mm LN mee 28 005 005 Baka P9005 LEAL ______ _ aw _____ me o rmo Wai _ mm am m man ow mans peon CW mw zi sou ar ma LH CW mm
217. ponding Device ID and Vendor ID of all devices seen on the bus This does not display device numbers with a Device ID and Vendor ID of all ones OxFFFF Display Vendor and Device ID for PCI device function Displays the Vendor ID and Device ID of the active device and function number In the example above this would display the Vendor ID and Device ID of the PCI device at device number 0x7r function number 0x00 Loop on PCI device fun 71 0 and Display Vendor and Device ID Reads and displays the Vendor ID and Device ID of the active device number and function number Repeats this action until the user hits a key to stop it Loop on PCI device fun 7f 0 and Don t Display Vendor and Device ID Same as previous menu option except doesn t display results This menu option is useful when using an oscilloscope to debug configu ration reads 5000 105 USER S MANUAL 9 UTILITIES Loop on all PCI device numbers and Display Device Vendor ID s Loops on each device number reading the Vendor ID and Device ID for each It moves onto the next device number when you press any key That is it continually reads the Vendor ID and Device ID from device number 0 until you hit a key at which point it continually reads the Vendor ID and Device ID from device number 1 It moves all the way through device number 0 to device number 0x7F in case there are any bridges on your PCI bus Display all PCI information for PCI device function 71 0
218. put 18 2 Reg E Address gt Register Burst Control 16 Read Control Logic 18 2 E Burst ntrol 1 0 K Write K Write M Addr Addr 1 2 Address Register V Read Control Logic Figure 5 8 Syncburst ZBT PL Setup i Hold Address 4 Phase Syncburst mse 585 ZBT FT 1 Flowthrough Pipelined Figure 5 9 Syncburst and ZBT SSRAM Timing Read Phase 5 8 EMULATION TECHNOLOGY INC Table 5 2 Syncburst and ZBT SSRAM Timing Syncburst Address Phase CE2 CE CE CE2 CE ADSC ADSP R w LD 4 BWx address address or or 2 BWx 4 Write Phase BWE BWx data Read Phase Valid Data Valid Data continue a burst ADV LD is low to load new address high to continue bust For write access only Writes to all four bytes SDRAM The 5000 105 has a socket for a 3 3 V 168 pin SDRAM DIMM Either registered or unbuffered modules fit in the socket J3 The same PC100 PC133 SDRAM modules that you put into your PC are used here Your 5000 105 will be stuffed and tested with 1 Gbyte PC133 SDRAM DIMM unless otherwise requested DIMM pins are connected to the FPGA and the pins are shown in Figure 5 10 and Figure 5 11 We
219. r 1300 ps steps up to 10 4 ns All adjustments are jumper selectable The clock grid JP6 gives the user the ability to customize the clock scheme the ET5000k10S A brief description of each pin is given in Table 4 1 The physical orientation of the pins is diagrammed in Figure 4 2 Table 4 1 Clock Grid Signal Descriptions Signal Description CLKOUT Clock signal from CPLD Typically 12 MHz PLLIA Input to Roboclockll 1 CLOCKA Clock signal of oscillator 1 X1 BUF INB Clock input to 3807 2 CLOCKB Clock signal of oscillator 2 X2 EMULATION TECHNOLOGY INC CLOCKS AND CLOCK DISTRIBUTION JP6 A JP6 B JP6 C Figure 4 2 Clock Grid Table 4 1 Clock Grid Signal Descriptions Signal Description PLL2B PRE Secondary clock input to Roboclockll 2 Differential pair with PLL2BN_PRE PLL2BN PRE BUFINA PLLIBSN PLLIB PRE Jumper Three main configurations are the most common Control for the first the grid may be jumpered as follows Most Common Configuration 1 CLKOUT lt gt PLL1A CLOCKA and Applications CLOCKB lt gt BUFINB Both 3807s receive their inputs from the oscillators Roboclockll 1 receives a clock input from the CPLD Also Roboclockll 2 can use DCLK 7 from Roboclockll 1 as an input This is explained in Roboclock PLL Clock Buffers on page 5 Second the input clock distribution can be configured as Configuration 2 CLKOUT lt gt PLL2BN_PRE CLOCKA lt
220. rated to 13 A far more current than the 5000 105 use The ET5000k10S when used stand alone has the following different power rails 45V P10 12 Figure 6 2 Molex Connector P1 Auxiliary Power EMULATION TECHNOLOGY INC POWER SUPPLIES AND POWER DISTRIBUTION NOTE If you use the ET5000k10S stand alone with an ATX power supply the ET5000k10S may not draw enough current to meet the minimum current required by the switchers in the 3 3 V 2 5 V 1 25 V tracks to 2 5 V 41 5 V 12 supply Connecting a disk drive to another connector will solve this problem By specification board may consume a maximum of 25 watts from the fingers of the connector This power limit is below that the ET5000k10S is capable of consuming even if daughter cards and or large SDRAM banks are installed The P1 connector can be used to augment the power obtained from the PCI fingers P1 can be used provided that the 5 and 12 power rails the connector are supplied the same power source as the PCI fingers NOTE P1 and PCI may provide power at the same time but ONLY if the same power source used to supply P1 is also supplying power to PCI 5000 105 USER S MANUAL 6 POWER SUPPLIES AND POWER DISTRIBUTION 6 6 EMULATION TECHNOLOGY INC DAUGHTER CONNECTIONS ET3K10SD OBSERVATION DAUGHTER CARD FOR 200 PIN CONNECTORS Chapter 7 Daughter Connections to ET3k10SD
221. rmal operation this indicates that PWRRST 15 active and that something is wrong Note that if you press S1 and release it quickly you probably won t see LED5 since the 200 ms reset pulse is not long enough for the eye to observe Depressing the push button S1 causes the following sequence of events 1 Reset of the CPLD and uP 2 FPGA configuration is cleared 3 Ifthe switches on S2 are set for Fast Passive Parallel and there is a valid SmartMedia card inserted into the socket then the FPGA will be configured A SmartMedia card is valid if it complies with the SSFDC specification and contains a file named main txt in the root directory If the card is invalid or there is no card present then the FPGA will not be configured 4 The Main Menu will appear The identical sequence of events occurs at power up 5000 105 USER S MANUAL 8 1 RESET SCHEMES LEDS BUS BARS AND 200 PIN CONNECTORS 3 3 5 0 1 5 3 3 2 5 Push Button 1 PCI PCI X Interface ISP Interface Header Reset Circuit LTC1326 Reset Circuit LTC1326 PCI RSTn 3 EP1S80F1508 PWRRSTn uP ATmega128L FPGA_GRSTn CPLD EPM3256A PWRRST Note RS232 Tranceiver must be disabled during RS232 uP programming phase in 3221 order to avoid contention on the BTXD signal pin Figure 8 1 Reset Functionality EMULATION TECHNOLOGY INC RESET 5 5 LEDS BUS BARS AND 200 PIN CONNECTORS L
222. rovided so you are welcome to customize the program to your own applications AETEST is not a stable program We add and subtract features when we need to for debug and verification purposes so don t be concerned if the screens that you see aren t exactly replicated here In a nutshell AETEST lets you do the following Determine if PCI recognizes the ET5000k10S Read write loop any memory location Read write loop configuration space Display all configured PCI devices Display memory setting from any locations Fill memory with various patterns Run various tests on the ET5000k10S SSRAM Test Multiplier Test SDRAM Test Interconnect Test Daughter Card Test Installation Instructions for DOS 1 files aetestdj exe and cwsdpmi exe the DOS extender need to be in the same directory 2 aetestdj exe Installation Instructions for Windows NT 1 Install the device driver install exe and gldriver sys must in the same directory 2 Type install 3 After the driver is installed start the driver by selecting Control Panel gt Devices gt find QLDriver gt click Start 4 Run aetestnt exe Installation Instructions for Windows 2000 1 Install the device driver gldriver2000 inf and the driver file qldriver sys should be the same directory 2 Open Control Panel click on Add Remove Hardware and then go to Next 3 Choose Add Troubleshoot a device t
223. s soldered down to the PWB and is not intended to be user configurable The 48 MHz is divided down to 8 MHz in the CPLD to provide the clock for the ATmega128L pP The processor clock signal is labeled CPUCLK BCPUCLK on the schematic Serial and JTAG configuration of the Stratix FPGA are back off positions only that is why those signals are connected to the CPLD Fast Passive Parallel is the quickest configuration method but we wanted to provide the user as many options as possible If you want to use 100 of the CPLD and pP for your own purposes you can configure the FPGA using the JTAG cable The 48 MHz clock can be divided down in the CPLD and used to drive the PWB clock network See Chapter 4 for a more detailed description of this option Notes on Header P3 Fast Passive Parallel using the SmartMedia card is the best way to configure the FPGA Two other options exists if for some reason the SmartMedia card method is not applicable 1 Serial Programming Using the Cable Header P3 has the 5 serial con nections that are used to configure the FPGA using the serial method Table 2 3 has the pinouts Note that this is a back off position to SmartMedia and JTAG and should only be used in dire circumstances Note also that the switches on P5 will need to change to reflect slave serial configuration 2 JTAG Programming The JTAG connection can be used to configure the FPGA and can also be used to connect the SignalTap Logi
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226. sting solutions The 5000 105 can be hosted in 32 64 bit PCI PCI X slot or can be used as a stand alone device A single 5000 105 stuffed with a single EP1S80 can emulate up to 450 000 gates of logic as measured by LSI A high O count 1508 pin flip chip BGA package is employed The F1508 package has 1203 1 5 which allows for abundant connections to daughter connectors and external memories A total of 242 test pins are provided on the top of the PWB via high density connectors for logic analyzer based debugging or for pattern generator stimulus Custom daughter cards such as the ET3k10SD can be mounted to these connectors as a means of interfacing the 5000 105 to application specific circuits A reference 32 bit PCI target design and test bench is provided in Verilog and VHDL at no additional cost 1 412V 2 5V 1 5 9 test connectors Reset Control CONFIGURATION _ 214 JTAG 242 Connector Aux Power 1 Smart Media 1692191 guration 32kx8 32kx8 SRAM tion 031 Flash based uP FPGA Configuration Controller 21 3 3 address FlowThrough 1 5V data 3 Pipelined lt ECLK control 14 SSRAM m 512k x 36 43 3V address T FlowThrough Regulator Al S Pipelined we 226 Altera Stratix 7 7 gt 8
227. tor is 91403 003 We stock the mating connector at our offices in La Jolla CA so if you are designing a daughter card and are having trouble getting this part call us We would be happy to send you a few at our cost Appendix A contains a mechanical datasheet for both the Berg 91403 003 and 91294 003 connectors This style of connector has four mounting holes two screw holes at each end and two alignment holes between pins 50 51 and after pin 100 see Figure 8 4 These mounting holes are part of the metal shell of the connector and make an important connection to the mating connector EMULATION TECHNOLOGY INC RESET 5 5 LEDS BUS BARS AND 200 PIN CONNECTORS REF ZW a zz 5 Mounting Holes Figure 8 4 91294 003 Pin Numbering four of these mounting holes are connected to digital ground on the DN5000k10S therefore the shell of the connector is grounded We used the pin numbering shown in Figure 8 4 for the 200 pin 91294 003 connectors The Signals Each of the two 200 pin connectors has the following P8 has 147 signals connected to the FPGA P9 has 96 signals connected to the FPGA 5clocks The following power rails 12V 1 pin 12V 1 pin 5V 2 pins 5000 105 USER S MANUAL 8 RESET SCHEMES LEDS BUS BARS AND 200 PIN CONNECTORS 3 3 2 pins 41 5V 2 pins GND 23 pins case Regarding the amount of current that the power pins can
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229. xt to get the names of the files to be used for configuration as well as options for the configuration process How ever a user can put several files that follow the format main txt on the SmartMedia card that contain different options for the config uration process By selecting the main menu option 4 the user can select a t xt file from a list of files that should be used in place of main txt After selecting a new file to use in place of main txt the user should select Main Menu option 1 to configure the FPGA s according to this new file If the power is turned off or the reset but 2 22 EMULATION TECHNOLOGY INC ET5000K10S FEATURES OVERVIEW AND GENERAL DESCRIPTION SmartMedia ton S1 is pressed the configuration file is changed back to the default main txt 5 List files on SmartMedia This option prints out a list of all the files found on the SmartMedia card 6 Select FPGA to Program with JTAG This option must be set to enable an FPGA before it can be programmed through JTAG The configuration file for the FPGA is copied to a SmartMedia card using the SmartDisk FlashPath Floppy Disk Adapter The approximate file size for each possible Stratix FPGA is shown below in Table 2 5 Note that several files can be put on a 32 megabyte card We supply two 32 megabyte SmartMedia cards with the 5000 105 SmartMedia is a standard so you can get more SmartMedia cards if you want The 5000 105 requires 3 3

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