ST16C554/554D/68C554
Contents
1. normal default condi tion Logic 1 Set DMA mode 1 Transmit operation in mode 0 When the 554D is in the ST16C450 mode FIFOs disabled FCR bit 0 logic 0 or in the FIFO mode FIFOs enabled FCR bit 0 logic 1 FCR bit 3 logic 0 and when there are no characters in the transmit FIFO or transmit holding register the TXRDY pin will be a logic 0 Once active the TXRDY pin will go to a logic 1 after the first character is loaded into the transmit holding register Receive operation in mode 0 When the 554D is in mode 0 FCR bit 0 logic 0 or in the FIFO mode FCR bit 0 logic 1 FCR bit 3 logic 0 and there is at least one character in the receive FIFO the RXRDY pin will be a logic 0 Once active the RXRDY pin will go to a logic 1 when there are no more characters in the receiver AE NB NB SS PLZ 5 47 ST16C554 554D 68C554 Z EXAR A NB NB NB NB b e fa Transmit operation in mode 1 When the 554D is in FIFO mode FCR bit 0 logic 1 FCR bit 3 logic 1 the TXRDY pin will be a logic 1 when the transmit FIFO is completely full It will be a logic 0 if one or more FIFO locations are empty Receive operation in mode 1 When the 554D is in FIFO mode FCR bit 0 logic 1 FCR bit 3 logic 1 and the trigger level has been reached or a Receive Time Out has occurred the RXRDY pin will go to a logic 0 Once activated it will goto a logic 1 after there are no more char2. 10 different interrupt level options using 16 bit PC 104 bus extension WO lines are short circuit protected Dual 20 pin I O headers 2 ports per header 5V only operation Extended temperature 40 to 85 C operation 2003 Diamond Systems Corp Emerald MM User Manual V4 13 Page 3 3 MECHANICAL DRAWING EE O O ooo o o C 2000 DIAMOND SYSTEMS CORP EMERALD MM V4 Description of Key Elements J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J16 PC 104 8 bit bus connector PC 104 16 bit bus connector User I O header for serial ports 1 and 2 User VO header for serial ports 3 and 4 Configuration for serial port 1 Configuration for serial port 2 VO address configuration Interrupt level configuration for port 1 Interrupt level configuration for port 2 Interrupt level configuration for port 3 Interrupt level configuration for port 4 Factory use only Configuration for serial port 3 Configuration for serial port 4 1 Wire interface Model EMM 1W XT only 2003 Diamond Systems Corp Emerald MM User Manual V4 13 Page 4 4 SERIAL PORT VO HEADER PINOUT AND PIN DESCRIPTION Emerald MM provides two identical 20 pin headers labeled J3 and J4 for the 4 serial ports Two ports are contained on each header Pin 1 and numbers are marked on the board for connector polarity identification For 1 Wire interface see page 10 RS 232 Configuration DCD 1 DCD 3 RXD 1 RXD 3 TXD 1 TXD 3 DTR 1 DTR 3 GND
3. 4 respectively Termination is only needed and should only be used at the cable endpoints Installing termination resistors at additional points in the network may cause overloading and failure of the line drivers due to the lower impedance caused by multiple resistors in parallel 5 5 Interrupt Levels J8 Port 1 interrupt configuration J9 Port 2 interrupt configuration J10 Port 3 interrupt configuration J11 Port 4 interrupt configuration Each serial port requires an interrupt level as well as a base I O address Four jumper blocks J8 through J11 are provided to select the interrupt level for each port from among levels 2 3 4 5 6 7 10 11 12 and 15 Install a jumper in the position corresponding to the desired interrupt level for each port Note Interrupt levels 2 7 are available on the standard 8 bit PC 104 bus header J1 If you are using an 8 bit bus these are the only levels available to you Interrupt levels 10 11 12 and 15 are available on the 16 bit PC 104 bus extension header J2 If you are using a 16 bit bus then all 10 levels are available to you Also on a system with a 16 bit bus interrupt level 2 is rerouted to level 9 5 6 Interrupt Sharing On the PC 104 bus interrupt levels may be shared by multiple devices For this reason the interrupt is driven to a logic high level by the device requesting service and when the device is serviced it tri states the line rather tha
4. The 554D divides the basic crystal or external clock by 16 Further division of this 16X clock provides two table rates to support low and high data rate applications using the same system design Customized Baud Rates can be achieved by selecting the proper divisor values for the MSB and LSB sections of baud rate generator Programming the Baud Rate Generator Registers DLM MSB and DLL LSB provides a user capability for selecting the desired final baud rate The example in Table 5 below shows the two selectable baud rate IT ihi 1 8432 MHz tables available when using a 7 3728 MHz crystal Table 5 BAUD RATE GENERATOR PROGRAMMING TABLE Output Output User User DLM DLL Baud Rate Baud Rate 16 x Clock 16x Clock Program Program 1 8432 MHz 7 3728 MHz Divisor Divisor Value Value Clock Clock Decimal MET ND NG NG AD ADA EE 5 42 Z EXAR ST16C554 554D 68C554 ANN NB NB NB NB NG ce e DMA Operation The 554D FIFO trigger level provides additional flexibility to the user for block mode operation LSR bits 5 6 provide an indication when the transmitter is empty or has an empty location s The user can optionally operate the transmit and receive FIFOs in the DMA mode FCR bit 3 When the transmit and receive FIFOs are enabled and the DMA mode is deactivated DMA Mode O the 554D activates the interrupt output pin for each data transmit or receive operation When DMA mode is activated DMA Mo
5. 68 mode which allows easy integration with Motorola and other popu lar microprocessors The ST16C554C 064 64 pin offers three state interrupt control while the ST 16C554DCQ64 provides constant active interrupt outputs The 64 pin devices do not offer TXRDY RXRDY outputs The 554D combines the package interface modes of the 16C554 and 68C554 series on a single integrated chip FEATURES Compatibility with the Industry Standard ST16C454 ST68C454 ST68C554 TL16C554 1 5 Mbps transmit receive operation 24MHz 16 byte transmit FIFO 16 byte receive FIFO with error flags Independent transmit and receive control Software selectable Baud Rate Generator Four selectable Receive FIFO interrupt trigger levels Standard modem interface ORDERING INFORMATION Partnumber Pins Package Operating temperature ST16C554DCJ68 68 PLCC 0 C to 70 C ST16C554DCQ64 64 TQFP 0 C to 70 C ST16C554CQ64 64 TOFP 0 C to 70 C ST16C554DIJ68 68 PLCC 40 C to 85 C ST16C554DIQ64 64 TQFP 40 C to 85 C INTB RTSB DTRB CTSB DSRB PLCC Package 9 CDA 8 RIA 7 RXA 5 INTSEL ST 16C554DCJ68 16 MODE ol le lol ld al le a a la lo foo lo lo lo lo lo lo a DN e o QUAD UART WITH 16 BYTE FIFO S DSRD CTSD DTRD GND RTSD INTD CSD TXD TXC CSC INTC RTSC DTRC CTSC DSRC ST 16C554 554D 68C554 La EXAR PIZZA Figure 1 Package
6. Descriptions 64 Pin TQFP Package 68 Pin PLCC Package lt Q 5 sz 3 T goe S sz 2 388988 E B amp BS RARARA BAY HE o 0OrX 658838858 z z53S 50 al fel fe 2118 18 Is Ie 188 15 IS SS ISIS ISIS IS e SI fo eo el el al 18 5 IS 8 2 8 S 5 DSRA 1 O 48 DSRD DSRA 10 O 60 DSRD CTSA 2 47 CTSD CTSA 11 59 CTSD DTRA 3 46 DTRD DTRA 12 58 DTRD vee 13 57 GND vee 4 45 GND RTSA 14 56 RTSD RTSA 5 44 RTSD IRQ 15 55 NC INTA 6 43 INTD cs 16 54 N C csa 7 42 CSD TXA 17 53 TXD Oe ST16C554CQ64 5 no ST16C554DCJ68 A w 18 52 N C ow 9 40 IOR MODE ST16C554DCQ64 ve S 68 MO 51 no 1x8 10 39 TXC A3 20 50 A4 csB 1 38 csc NC 21 49 NC INTB 12 37 INTC RTSB 22 48 RTSC RTSB 13 36 RTSC GND 23 47 vee GND 14 35 vec DTRB 24 46 DTRC DTRB 15 34 DTRC CTSB 25 45 CTSC cTSB 16 33 CTSC DSRB 26 44 DSRC nlle ollel xl lel s el elln lel lel ell y ej olala a NAN KANANE ANE ANANA NE nelle le lela el sls lens le el Sl le el je Sea 81 sl 8 8 3 8 8 5 8 8 e fu 9 2 00 000 Y Z So AN EO 9 9 oO 9 m a o oa q x Q X O lt lt lt 3 Ad u Z xX A m 8 8 Sy Sta g i E a goes EERS TT OR BE TT REHBRBBEREFSA d xx oe S kk UK AAN NB NB NB AD a 9 30 Z EXAR A TT Figure 2 Block Diagram 16 Mode Transmit Transmit S FIFO Shift D0 D7 a X Regi
7. GND DCD 2 DCD 4 RXD 2 RXD 4 TXD 2 TXD 4 DTR 2 DTR 4 GND GND RS 422 Configuration NC NC NC TXD 1 TXD 3 TXD 3 GND GND RXD 3 RXD 1 RXD 3 NC GND GND NC NC NC NC TXD 2 TXD 4 TXD 4 GND GND RXD 4 RXD 2 RXD 4 NC GND GND NC RS 485 Configuration NC NC NC NC TXD RXD 1 TXD RXD 1 TXD RXD 3 TXD RXD 3 GND NC GND NC NC NC NC NC GND NC NC NC NC NC NC NC TXD RXD 2 TXD RXD 2 TXD RXD 4 TXD RXD 4 GND NC GND NC NC NC NC NC GND NC NC NC 2003 Diamond Systems Corp Emerald MM User Manual V4 13 Page 5 Signal Definitions Signal Name Definition Direction RS 232 DCD Data Carrier Detect Input DSR Data Set Ready Input RXD Receive Data Input RTS Request To Send Output TXD Transmit Data Output CTS Clear To Send Input DTR Data Terminal Ready Output RI Ring Indicator Input RS 422 TXD TXD Differential Transmit Data Output RXD RXD Differential Receive Data Input RS 485 TXD RXD Differential Transmit Receive Bi directional TXD RXD Differential Transmit Receive Bi directional Common to all protocols GND NC O 2003 Diamond Systems Corp Ground Not Connected Emerald MM User Manual V4 13 Page 6 5 BOARD CONFIGURATION 5 1 Port and Interrupt Register Address Selection Each peripheral board in the computer system must have a unique l O address or block of addresses Emerald MM actually uses five VO address blocks one for each of the four serial ports and one for the interrupt st
8. Manual V4 13 Page 10 8 INSTALLING EMERALD MM IN WINDOWS NT 1 Run REGEDT32 EXE and go to the following dialog box Key Local Machine System CurrentControlSet Service Serial Parameters 2 Add a new key for each serial port by selecting Edit Add Key The following parameters need to be specified for each serial port SerialN N serial port number 1 2 3 4 etc Parameter Type Value Comments DosDevices REG SZ Name of port e g COM5 COM6 ForceFifoEnable REG DWORD 0x1 for yes Interrupt REG DWORD IRQ level in Hex format e g 0x5 for 5 or Oxa for 10 InterruptStatus REG DWORD Address of interrupt status register in Hex e g 0x224 PortAddress REG DWORD Address or port in Hex e g 0x120 for Hex 120 Portlndex REG DWORD Bit position in status register 0x1 for LSB through 0x4 Sharedlnterrupts REG DWORD 0x1 for yes 0x0 for no 3 Exit REGEDT32 EXE and restart NT See the example on the following page 2003 Diamond Systems Corp Emerald MM User Manual V4 13 Page 11 Windows NT Example The following example is for an EMM XT board installed on a CPU that already contains 2 serial ports called COM1 and COM2 The address setting combination is A out B in C out and all ports are sharing interrupt level 12 Note that all ports share the same interrupt status register but the bit position changes Port 1 Port 2 Port 3 Port 4 Interrupt Status Register Address 0x120 0x128 0x130 0x138 0x244 Interrupt Level
9. associated with the 16 mode only and for individual chan nels A through D When in 16 Mode these pins enable data transfers between the user CPU and the ST16C554D for the channel s addressed Individual UART sections A B C D are addressed by providing a logic 0 on the respective CS A D pin When the 68 mode is selected the functions of these pins are reassigned 68 mode functions are described under the their respective name pin head ings Data Bus Bi directional These pins are the eight bit three state data bus for transferring information to or from the controlling CPU DO is the least significant bit and the first data bit in a transmit or receive serial data stream Signal and power ground Interrupt A B C D active high This function is associated with the 16 mode only These pins provide individual channel interrupts INT A D INT A D are enabled when MCR bit 3 is set to a logic 1 interrupts are enabled in the interrupt enable register IER and when an interrupt con dition exists Interrupt conditions include receiver errors available receiver buffer data transmit buffer empty or when a modem status flag is detected When the 68 mode is selected the functions of these pins are reassigned 68 mode functions are described under the their respective name pin headings Interrupt Select active high with internal pull down This function is associated with the 16 mode only When the 16 mode
10. bus O 2003 Diamond Systems Corp 4 RS 232 RS 422 RS 485 Jumper selected or fixed depending on the version 115kbps standard version 460 8kbps available HS option 5 6 7 or 8 data bits Even odd or no parity All outputs protected against continuous short circuit 3KQ min 30V max 5V min 7V typical 0 2V min 0 2V max 12KQ min 1 0mA max Vin 12V 0 8mA max Vin 7V 2 0V min RL 500 0 2V max 2 20 position 2x10 025 sguare pin header on 1 centers Headers mate with standard ribbon cable IDC connectors 3 55 x 3 775 PC 104 standard 5VDC 10 80mA typical all outputs unloaded 40 to 85 C standard 5 to 95 noncondensing 8 bit and 16 bit bus headers are installed and used 16 bit header is used for interrupt levels only Emerald MM User Manual V4 13 Page 13 La EXAR ST16C554 554D ST68C554 ANNE A NB NB A he A A DESCRIPTION The ST16C554D is a universal asynchronous receiver and transmitter UART with a dual foot print interface The 554D is an enhanced UART with 16 byte FIFOs receive trigger levels and data rates up to 1 5Mbps Onboard status registers provide the user with error indications and operational status modem interface control System interrupts may be tailored to meet user reguirements An internal loopback capability allows onboard diagnostics The 554D is available in 64 pin TOFP and 68 pin PLCC packages The 68 pin PLCC package offer an additional
11. indi vidual serial transmit channel data from the 554D The TX signal will be a logic 1 during reset idle no data or when the transmitter is disabled During the local loopback mode the TX input pin is disabled and TX data is internally connected to the UART RX Input V Rev 3 00 NB NB NB NB NG O 5 38 La EXAR ST16C554 554D 68C554 Aa NB NB NB NB NG N a GENERAL DESCRIPTION The 554D provides serial asynchronous receive data synchronization parallel to serial and serial to paral lel data conversions for both the transmitter and receiver sections These functions are necessary for converting the serial data stream into parallel data that is reguired with digital data systems Synchronization for the serial data stream is accomplished by adding start and stops bits to the transmit data to form a data character character orientated protocol Data integ rity is insured by attaching a parity bit to the data character The parity bit is checked by the receiver for any transmission bit errors The electronic circuitry to provide all these functions is fairly complex especially when manufactured on a single integrated silicon chip The ST16C554D represents such an integration with greatly enhanced features The 554D is fabri cated with an advanced CMOS processto achieve low drain power and high speed requirements The 554D is an upward solution that provides 16 bytes of transmit and receive FIFO memory instead of 1 bytes pr
12. or Write strobes A logic 1 to 0 transition transfers the contents of the CPU data bus DO D7 to the register selected by CS and A0 A4 Similarly a logic O to 1 transition places the contents of a 554D register selected by CS and A0 A4 on the data bus DO D7 for transfer to an external CPU Receive Ready active low This function is associated with 68 pin packages only RXRDY contains the wire OR ed status of all four receive channel FIFOs RXRDY A D A logic 0 indicates receive data ready status i e the RHR is full or the FIFO has one or more RX characters available for unloading This pin goes to a logic 1 when the FIFO RHR is full or when there are no more characters available in either the FIFO or RHR For 64 68 pin packages individual channel RX status is read by examining individual internal registers via CS and A0 A4 pin functions Transmit Ready active low This function is associated with 68 pin package only TXRDY contains the wire OR ed status of all four transmit channel FIFOs TXRDY A D A logic 0 indicates a buffer ready status i e at least one location is empty and available in one of the TX channels A D This pin goes to a logic 1 when all four channels have no more empty locations in the TX FIFO or THR Power supply inputs MET NB NB NB NB AD A EE 5 36 La PAR ST 16C554 554D 68C554 A A AF SYMBOL DESCRIPTION Symbol Signal Pin Description 64 type Crystal or External Clock In
13. programmed word length 1 1 LCR BIT 3 Parity or no parity can be selected via this bit Logic O No parity normal default condition Logic 1 A parity bit is generated during the transmis sion receiver checks the data and parity for transmis sion errors LCR BIT 4 If the parity bit is enabled with LCR bit 3 set to a logic 1 LCR BIT 4 selects the even or odd parity format Logic O ODD Parity is generated by forcing an odd number of logic 1s in the transmitted data The receiver must be programmed to check the same format normal default condition Logic 1 EVEN Parity is generated by forcing an even the number of logic 1 s in the transmitted The receiver must be programmed to check the same format LCR BIT 5 If the parity bit is enabled LCR BIT 5 selects the forced parity format LCR BIT 5 logic 0 parity is not forced normal default condition LCR BIT 5 logic 1 and LCR BIT 4 logic 0 parity bit is forced to a logical 1 for the transmit and receive data LCR BIT 5 logic 1 and LCR BIT 4 logic 1 parity bit is forced to a logical 0 for the transmit and receive data D Rev 300 i NB NB 7 7777 ST16C554 554D 68C554 Z EAR E LCR LCR LCR Parity selection Bit 5 Bit 4 Bit 3 X X 0 No parity Odd parity Even parity Force parity 1 Forced parity 0 LCR BIT 6 When enabled the Break control bit causes a break condition to be transmitted the TX output is f
14. 12 12 12 12 Serial3 DosDevices REG SZ COM3 ForceFifoEnable REG DWORD 0x1 Interrupt REG DWORD Oxc InterruptStatus REG_DWORD 0x244 PortAddress REG_DWORD 0x120 Portlndex REG DWORD 0x1 Sharedlnterrupts REG DWORD 0x1 Seriald DosDevices REG SZ COM4 ForceFifoEnable REG DWORD 0x1 Interrupt REG_DWORD Oxc InterruptStatus REG_DWORD 0x244 PortAddress REG_DWORD 0x128 Portlndex REG DWORD 0x2 Sharedlnterrupts REG DWORD 0x1 Serial DosDevices REG SZ COM5 ForceFifoEnable REG_DWORD 0x1 Interrupt REG_DWORD Oxc InterruptStatus REG_DWORD 0x244 PortAddress REG_DWORD 0x130 Portlndex REG DWORD 0x3 Sharedlnterrupts REG DWORD 0x1 Serial6 DosDevices REG SZ COM6 ForceFifoEnable REG_DWORD 0x1 Interrupt REG_DWORD Oxc InterruptStatus REG_DWORD 0x244 PortAddress REG_DWORD 0x138 Portlndex REG DWORD 0x4 Sharedlnterrupts REG DWORD 0x1 O 2003 Diamond Systems Corp Emerald MM User Manual V4 13 Page 12 9 SPECIFICATIONS Serial Port Specifications No of serial ports Protocol Maximum baud rate Communications parameters Short circuit protection RS 232 mode Input impedance Input voltage swing Output voltage swing RS 422 RS 485 modes Differential input threshold Input impedance Input current Differential output voltage High low states differential output voltage symmetry General Specifications VO header Dimensions Power supply Current consumption Operating temperature Operating humidity PC 104
15. 4 DIAMOND SYSTEMS CORPORATION EMERALD MM 4 Channel Multi Protocol Serial Port PC 104 Module User Manual V4 13 263 300 aj lo a 5 4 09 Jes Edele e 13 m te E sa m m s NTZ INTI 9270 30 FIGHSSO9LLS v ek 20717233205 ug Copyright 2003 DIAMOND SYSTEMS CORPORATION 8430 D Central Ave Newark CA 94560 Tel 510 456 7800 Fax 510 456 7878 techinfo diamondsystems com www diamondsystems com TABLE OF CONTENTS 1 IC CH RA NEE 3 ao du EES EE EE EE EE EE EE EE ER 3 3 EMERALD MM BOARD DRAWING 6000000000000000000 sees sees sees se esse 0000000000000000 See naa Bee nasa Se ee ee ee 4 4 SERIAL PORT VO HEADER PINOUT AND PIN DESCRIPTION 6000000000000000000 sees se esse esse ese ees 5 5 BOARD CONFIGURATION ee esse esse ese see see See See nn sasa ee es 7 6 RS 485 TRANSMITTER CONTROL sees sees sees se esse esse ese ee ee Ee Ge osnovna Bee Bee Be Ee Ee ee Ee Ee SE Ge See 10 UR DUNN TEL DE 10 8 INSTALLING EMERALD MM IN WINDOWS NI seesse esse ese esse esse esse esse ese es se es ee See osnovan ovna See ie 11 9 SPECIFICATIONS esesssessee osnovno bees see se ee Ee Ee Ee Ee Ge osnovna ovna ananasa Be ee Ee Ee Ee Ee Ge ERG SEA See Be ee 13 2003 Diamond Systems Corp Emerald MM User Manual V4 13 Page 2 E M E RAL D M M 4 Channel Multi Protocol Serial Port PC 104 Module 1 DESCRIPTION Emerald MM is a PC 104 format VO module with 4 serial ports The board is available in m
16. E point to point Out In Out Out In Out RS 422 point to point In Out In Out Out Out RS 422 multi drop In Out In Out Out In RS 485 multi drop In Out Out In Out In 2003 Diamond Systems Corp Emerald MM User Manual V4 13 Page 7 5 3 Configuration for RS 422 and RS 485 Modes When RS 422 or RS 485 modes are selected not all signals are used by the line drivers and receivers Depending on your software configuration you may need to force some inputs true so that your software will operate correctly Jumper blocks J5 J6 J13 and J14 provide a means to force the input signals true connect them to ground or logic 0 for ports 1 4 respectively The signals that can be controlled in this fashion are CTS DCD DSR and RI To force an input signal true on a port install a jumper next to that signal s name on the corresponding header for that port Jumpers should not be installed in these locations for RS 232 operation NOTE The positions TX and RX are not used for this purpose Installing jumpers in these locations has an entirely different meaning See Cable Endpoint Termination below 5 4 RS 422 RS 485 Cable Endpoint Termination In RS 422 or RS 485 networks termination resistors are normally installed at the endpoints of the cables to minimize reflections on the lines Emerald MM provides 12002 resistors for this purpose To enable resistor termination install jumpers in the locations TX and RX of J5 J6 J13 or J14 for ports 1
17. HR empty flag in the LSR register will be set to a logic 1 when the transmitter is empty or when data is transferred to the TSR Note thata write operation can be performed when the transmit holding register empty flag is set logic 0 FIFO full logic 1 at least one FIFO location available The serial receive section also contains an 8 bit Receive Holding Register RHR Receive data is removed from the 554D and receive FIFO by reading the RHR register The receive section provides a mechanism to prevent false starts On the falling edge of a start or false start bit an internal receiver counter starts counting clocks at 16x clock rate After 7 1 2 clocks the start bit time should be shifted to the center of the start bit At this time the start bit is sampled and if it is still a logic 0 it is validated Evaluating the start bit in this manner prevents the receiver from assem bling a false character Receiver status codes will be posted in the LSR Interrupt Enable Register IER The Interrupt Enable Register IER masks the inter rupts from receiver ready transmitter empty line status and modem status registers These interrupts would normally be seen on the INT A D output pins in the 16 mode or on WIRE OR IRQ output pin in the 68 mode IER Vs Receive FIFO Interrupt Mode Operation When the receive FIFO FCR BIT 0 a logic 1 and receive interrupts IER BIT 0 logic 1 are enabled the receive interrupts and register status
18. Receive Ready RXRDY will go to a logic 0 when ever the Receive Holding Register RHR is loaded with a character Mode 1 Set and enable the interrupt in a block mode operation The transmit interrupt is set when the transmit FIFO is below the programmed trigger level TXRDY remains a logic 0 as long as one empty FIFO location is available The receive interrupt is set when the receive FIFO fills to the programmed trigger level However the FIFO continues to fill regardless of the programmed level until the FIFO is full RXRDY remains a logic 0 as long as the FIFO fill level is above the programmed trigger level FCR BIT 0 Logic 0 Disable the transmit and receive FIFO normal default condition Logic 1 Enable the transmit and receive FIFO This bit must be a 1 when other FCR bits are written to or they will not be programmed FCR BIT 1 Logic 0 No FIFO receive reset normal default condition Logic 1 Clears the contents of the receive FIFO and resets the FIFO counter logic the receive shift regis ter is not cleared or altered This bit will return to a logic 0 after clearing the FIFO FCR BIT 2 Logic 0 No FIFO transmit reset normal default condition Logic 1 Clears the contents of the transmit FIFO and resets the FIFO counter logic the transmit shift regis ter is not cleared or altered This bit will return to a logic 0 after clearing the FIFO FCR BIT 3 Logic 0 Set DMA mode 0
19. T CHANNEL SELECTION GUIDE 68 MODE INTERFACE CS UART CHANNEL N A N A None 0 1 0 1 0 0 1 1 Internal Registers The 554D provides 13 internal registers for monitoring and control These resisters are shown in Table 4 below Twelve registers are similar to those already available in the standard 16C454 These registers function as data holding registers THR RHR inter rupt status and control registers IER ISR line status and control registers LCR LSR modem status and control registers MCR MSR programmable data rate clock control registers DLL DLM and a user assessable scratchpad register SPR Register func tions are more fully described in the following para graphs Table 4 INTERNAL REGISTER DECODE A2 Al AO READ MODE WRITE MODE General Register Set THR RHR IER ISR MCR MSR LCR LSR SPR Line Status Register zk OO O O Scratchpad Register Baud Rate Register Set DLL DLM Note 2 LSB of Divisor Latch MSB of Divisor Latch Receive Holding Register Interrupt Status Register Modem Status Register Transmit Holding Register Interrupt Enable Register FIFO Control Register Line Control Register Modem Control Register Scratchpad Register LSB of Divisor Latch MSB of Divisor Latch Note 2 These registers are accessible only when LCR bit 7 is set to a logic 1 MET ND LA ff N N N AD Z EXAR ST16C554 554D 68C554 ANN NB NB NB NB NG ce e FIFO O
20. acters in the FIFO FCR BIT 4 5 Not used Initialized to a logic 0 FCR BIT 6 7 logic 0 or cleared is the default condi tion Rx trigger level 1 These bits are used to set the trigger level for the receive FIFO interrupt An interruptis generated when the number of charac ters in the FIFO equals the programmed trigger level However the FIFO will continue to be loaded until it is full Table 7 INTERRUPT SOURCE TABLE Priority Level ISR BITS Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BIT 7 BIT 6 RX FIFO trigger level 0 1 1 4 0 8 1 14 Interrupt Status Register ISR The 554D provides four levels of prioritized interrupts to minimize external software interaction The Inter rupt Status Register ISR provides the user with six interrupt status bits Performing a read cycle on the ISR will provide the user with the highest pending interrupt level to be serviced No other interrupts are acknowledged until the pending interrupt is serviced Whenever the interrupt status register is read the interrupt status is cleared However it should be noted that only the current pending interruptis cleared by the read A lower level interrupt may be seen after reread ing the interrupt status bits The Interrupt Source Table 7 below shows the data values bit 0 5 for the four prioritized interrupt levels and the interrupt sources associated with each of these interrupt levels Source of the interrupt LSR Receiver Li
21. atus register Each port s address block consists of 8 consecutive addresses while the interrupt status register occupies a single address The VO addresses are set with jumper block J7 located at the right edge of the board Eight different VO address combinations are selectable The address shown below for each port is the base address of that port i e the lowest address of the port s VO address block Interrupt A B C Port 1 Port 2 Port 3 Port 4 Status In In In 3F8 2F8 3E8 2E8 220 Out In In 3E8 2E8 3A8 2A8 220 In Out In 380 388 288 230 224 Out Out In 240 248 260 268 224 In In Out 100 108 110 118 240 Out In Out 120 128 130 138 244 In Out Out 140 148 150 158 248 Out Out Out 160 168 170 178 24C 5 2 Serial Protocol Selection JS Port 1 protocol configuration J6 Port 2 protocol configuration J13 Port 3 protocol configuration J14 Port 4 protocol configuration Depending on the model you have different protocol configurations are possible For configurable versions protocol selection is made by installing jumpers in the positions indicated below in the configuration headers J5 J6 J13 and J14 For fixed protocol versions the configuration is preset with wire jumpers in these same positions RS 422 is full duplex while RS 485 is half duplex In multi drop mode the transmitter is controlled by the RTS line This feature requires software control and is not automatic Protocol 1 2 3 4 5 6 RS 232 DT
22. d to RESET IOR is not used and INT A D s are connected in a WIRE OR configuration The WIRE OR outputs are connected internally to the open source IRQ signal output This pin is not available on 64 pin packages which operate in the 16 mode only Address 0 Select Bit Internal registers address selection in 16 and 68 modes Address 1 Select Bit Internal registers address selection in 16 and 68 modes Address 2 Select Bit Internal registers address selection in 16 and 68 modes Address 3 4 Select Bits When the 68 mode is selected these pins are used to address or select individual UART s providing CS is a logic 0 In the 16 mode these pins are reassigned as chip selects see CSB and CSC These pins are not available on 64 pin packages which operate in the 16 mode only Chip Select active low In the 68 mode this pin functions as a multiple channel chip enable In this case all four UARTs A D are enabled when the CS pin is a logic 0 An individual UART channel is selected by the data contents of address bits A3 A4 When the 16 mode is selected 68 pin device this pin functions as CSA see definition under CS A B This pin is not available on 64 pin packages which operate in the 16 mode only D Rev 300 NB NB SS NG N N A 5 33 ST 16C554 554D 68C554 La EXAR PIZZA SYMBOL DESCRIPTION Symbol Pin Signal Pin Description 68 64 type INTSEL Chip Select A B C D active low This function is
23. de 1 the user takes the advantage of block mode operation by loading or unloading the FIFO in a block sequence determined by the preset trigger level In this mode the 554D sets the interrupt output pin when characters in the transmit FIFOs are below the trans mit trigger level or the characters in the receive FIFOs are above the receive trigger level Loopback Mode The internal loopback capability allows onboard diag nostics In the loopback mode the normal modem interface pins are disconnected and reconfigured for loopback internally MCR register bits 0 3 are used for controlling loopback diagnostic testing In the loopback mode OP1 and OP2 in the MCR register bits 3 2 control the modem RI and CD inputs respectively MCR signals DTR and RTS bits 0 1 are used to control the modem CTS and DSR inputs respectively The transmitter output TX and the receiver input RX are disconnected from their asso ciated interface pins and instead are connected to gether internally See Figure 12 The CTS DSR CD and RI are disconnected from their normal modem control inputs pins and instead are connected internally to DTR RTS OP1 and OP2 Loopback test data is entered into the transmit holding register via the user data bus interface DO D7 The transmit UART serializes the data and passes the serial data to the receive UART via the internal loopback connec tion The receive UART converts the serial data back into
24. e RI input In the loopback mode this bit is equivalent to the OP1 bit in the MCR register D Rev 300 NB NB SS NG N N ZZ 5 51 ST16C554 554D 68C554 AN ZA A a N N NS MSR BIT 7 CD active high logical 1 Normally this bit is the compliment of the CD input In the loopback mode this bit is equivalent to the OP2 bitin the MCR register Scratchpad Register SPR The ST16C554D provides a temporary data register to store 8 bits of user information ST16C554D EXTERNAL RESET CONDITIONS REGISTERS RESET STATE IER BITS 0 7 0 ISR BIT 0 1 ISR BITS 1 7 0 LCR BITS 0 7 0 MCR BITS 0 7 0 LSR BITS 0 4 0 LSR BITS 5 6 1 LSR BIT 7 0 MSR BITS 0 3 0 MSR BITS 4 7 input signals FCR BITS 0 7 0 SIGNALS RESET STATE MET PP 7 7 A777 yy 5 52 Z EXAR
25. gister Writing a logic 1 to MCR bit 0 will set the DTR output to logic 0 enabling the modem This pin will be a logic 1 after writing a logic 0 to MCR bit 0 This pin has no effect on the UART S transmit or receive operation D Rev 300 NB NB SS N N N A 5 37 ST 16C554 554D 68C554 La EXAR PIZZA SYMBOL DESCRIPTION Symbol Pin Signal Pin Description 68 64 type Ring Indicator active low These inputs are associated with individual UART channels A through D A logic 0 on this pin indicates the modem has received a ringing signal from the telephone line A logic 1 transition on this input pin will generate an interrupt Requestto Send active low These outputs are associated with individual UART channels A through D A logic 0 on the RTS pin indicates the transmitter has data ready and waiting to send Writing a logic 1 in the modem control register MCR bit 1 will set this pin to a logic 0 indicating data is available After a reset this pin will be set to a logic 1 This pin has no effect on the UART s transmit or receive operation Receive Data Input RX A D These inputs are associated with individual serial channel data to the ST16C554D The RX signal will be a logic 1 during reset idle no data or when the transmitter is disabled During the local loopback mode the RX input pin is disabled and TX data is internally connected to the UART RX Input internally Transmit Data These outputs are associated with
26. he trigger level in the FIFO mode of operation Logic 0 Disable the receiver ready interrupt normal AE NG AD AD AD a 9 46 Z EXAR ST16C554 554D 68C554 E default condition Logic 1 Enable the receiver ready interrupt IER BIT 1 This interrupt will be issued whenever the THR is empty and is associated with bit 1 in the LSR register Logic O Disable the transmitter empty interrupt normal default condition Logic 1 Enable the transmitter empty interrupt IER BIT 2 This interrupt will be issued whenever a fully as sembled receive character is transferred from the RSR to the RHR FIFO i e data ready LSR bit 0 Logic 0 Disable the receiver line status interrupt normal default condition Logic 1 Enable the receiver line status interrupt IER BIT 3 Logic O Disable the modem status register interrupt normal default condition Logic 1 Enable the modem status register interrupt IER BIT 4 7 Not used Initialized to a logic 0 FIFO Control Register FCR This register is used to enable the FIFOs clear the FIFOs set the transmit receive FIFO trigger levels and select the DMA mode The DMA and FIFO modes are defined as follows DMA MODE Mode 0 Set and enable the interrupt for each single transmit or receive operation and is similar to the ST16C454 mode Transmit Ready TXRDY will go to a logic 0 when ever an empty transmit space is available in the Transmit Holding Register THR
27. is selected this pin can be used in conjunction with MCR bit 3 to enable or disable the three state interrupts INT A D or override MCR bit 3 and force continuous interrupts Interrupt outputs are enabled continuously by making this A NB NB NB NB a 5 34 La PAR ST 16C554 554D 68C554 A A AF SYMBOL DESCRIPTION Symbol Pin Signal Pin Description 68 64 type pin a logic 1 Making this pin a logic 0 allows MCR bit 3 to control the three state interrupt output In this mode MCR bit 3 is set to a logic 1 to enable the three state outputs This pin is disabled in the 68 mode Due to pin limitations on 64 pin packages this pin is not available To cover this limitation two 64 pin QFP package versions are offered The ST16C554DCQ64 operates in the continuos interrupt enable mode by bonded this pin to VCC internally The ST16C554CQ64 operates with MCR bit 3 control by bond ing this pin to GND 52 40 Read strobe active low Strobe This function is associ ated with the 16 mode only A logic 0 transition on this pin will load the contents of an Internal register defined by address bits A0 A2 onto the ST16C554D data bus DO D7 for access by an external CPU This pin is disabled in the 68 mode 18 9 Write strobe active low strobe This function is associ ated with the 16 mode only A logic 0 transition on this pin will transfer the contents of the data bus DO D7 from the external CPU to an internal register that is defined b
28. n driving it low This technique avoids contention by two devices trying to drive the line with opposing logic levels O 2003 Diamond Systems Corp Emerald MM User Manual V4 13 Page 8 5 7 Interrupt Pulldown Resistor 5 8 5 9 In order to guarantee valid logic levels on the line when the device is not requesting service each active interrupt level requires a 1KQ pulldown resistor Only one such resistor should be used on each active interrupt line Each interrupt configuration header on Emerald MM has a position marked R for enabling the pulldown resistor Install a jumper in this position to connect the resistor and remove the jumper to disconnect the resistor If two or more ports are sharing the same interrupt level install the jumper in the R position for any one of the ports and leave it off the others Interrupt Status Register The interrupt status register indicates the status of each por s interrupt request line It operates regardless of whether interrupt sharing is enabled see below If two or more ports are sharing the same interrupt level the status register will still indicate the correct status of each port s interrupt request line ee OO wa Definitions X Bit not used generally reads back as a 1 INT4 1 Status of interrupt reguest for each port 0 no interrupt request active for this port 1 interrupt request active for this port Default Settings The default settings for Emerald MM are as foll
29. n the FIFO mode only one break character is loaded into the FIFO LSR BIT 5 This bit is the Transmit Holding Register Empty indi cator This bit indicates that the UART is ready to accept a new character for transmission In addition this bit causes the UART to issue an interruptto CPU when the THR interrupt enable is set The THR bit is setto a logic 1 when a character is transferred from the transmit holding register into the transmitter shift register The bitis resetto logic O concurrently with the loading of the transmitter holding register by the CPU Inthe FIFO mode this bitis setwhen the transmit FIFO is empty it is cleared when at least 1 byte is written to the transmit FIFO LSR BIT 6 This bit is the Transmit Empty indicator This bit is set toalogic 1 whenever the transmit holding register and the transmit shift register are both empty It is reset to logic O whenever either the THR or TSR contains a data character In the FIFO mode this bit is set to one whenever the transmit FIFO andtransmit shift register are both empty LSR BIT 7 Logic O No Error normal default condition Logic 1 At least one parity error framing error or break indication is in the current FIFO data This bit is cleared when LSR register is read Modem Status Register MSR This register provides the current state of the control interface signals from the modem or other peripheral device that the 554D is connected to Four bits of thi
30. ne Status Register S Received Data Ready RXRDY Receive Data time out TXRDY Transmitter Holding Register Empty MSR Modem Status Register AT PP PPP 5 48 La EXAR ST16C554 554D 68C554 Aa NB NB NB NB NG N a BIT 2 Word length Stop bit length Bit time s 0 1 ISR BIT 0 Logic O An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt service routine Logic 1 No interrupt pending normal default condi tion ISR BIT 1 3 logic 0 or cleared is the default condition These bits indicate the source for a pending interrupt at interrupt priority levels 1 2 and 3 See Interrupt Source Table ISR BIT 4 5 Not used Initialized to a logic 0 ISR BIT 6 7 logic 0 or cleared is the default condition These bits are set to a logic 0 when the FIFO is not being used They are set to a logic 1 when the FIFOs are enabled Line Control Register LCR The Line Control Register is used to specify the asynchronous data communication format The word length the number of stop bits and the parity are selected by writing the appropriate bits in this register LCR BIT 0 1 logic 0 or cleared is the default condi tion These two bits specify the word length to be transmit ted or received BIT 1 BIT 0 Word length 0 1 0 1 LCR BIT 2 logic 0 or cleared is the default condition The length of stop bit is specified by this bit in conjunction with the
31. orced to a logic 0 state This condition exists until disabled by setting LCR bit 6 to a logic 0 Logic O No TX break condition normal default condition Logic 1 Forces the transmitter output TX to a logic 0 for alerting the remote receiver to a line break condition LCR BIT 7 Not used Initialized to a logic 0 Modem Control Register MCR This register controls the interface with the modem or a peripheral device MCR BIT 0 Logic 0 Force DTR output to a logic 1 normal default condition Logic 1 Force DTR output to a logic 0 MCR BIT 1 Logic O Force RTS output to a logic 1 normal default condition Logic 1 Force RTS output to a logic 0 MCR BIT 2 This bit is used in the Loopback mode only In the loopback mode this bit is use to write the state of the modem RI interface signal via OP1 MCR BIT 3 Used to control the modem CD signal in the loopback mode Logic O Forces INT A D outputs to the three state mode during the 16 mode normal default condition In the Loopback mode sets OP2 CD internally to a logic 1 Logic 1 Forces the INT A D outputs to the active mode during the 16 mode Inthe Loopback mode sets OP2 CD internally to a logic 0 MCR BIT 4 Logic O Disable loopback mode normal default condition Logic 1 Enable local loopback mode diagnostics MCR BIT 5 7 Not used Initialized to a logic 0 Line Status Register LSR This register p
32. ovided in the 16 68C454 The 554D is de signed to work with high speed modems and shared network environments that require fast data process ing time Increased performance is realized in the 554D by the larger transmit and receive FIFOs This allows the external processor to handle more network ing tasks within a given time This increases the service interval giving the external CPU additional time for other applications and reducing the overall UART interrupt servicing time The 554D combines the package interface modes of the 16C554D and 68C554 series on a single inte grated chip The 16 mode interface is designed to operate with the Intel type of microprocessor bus while the 68 mode is intended to operate with Motorola and other popular microprocessors Following a reset the 554D is down ward compatible with the ST16C454 ST68C454 dependent on the state of the interface mode selection pin 16 68 The 554D is capable of operation to 1 5Mbps with a 24 MHz crystal or external clock input With a crystal of 14 7464 MHz the user can select data rates up to 921 6Kbps The rich feature set of the 554D is available through internal registers Selectable receive FIFO trigger levels selectable TX and RX baud rates modem interface controls In the 16 mode INTSEL and MCR bit 3 can be configured to provide a software con trolled or continuous interrupt capability Due of pin limitations for the 64 pin 554D this feature is offered by t
33. ows Protocol settings All ports set for RS 232 Address Interrupt settings J7 AB C In In Out Feature Address Interrupt level Port 1 100 3 Port 2 108 3 Port 3 100 3 Port 4 108 3 Interrupt Status 240 O 2003 Diamond Systems Corp Emerald MM User Manual V4 13 Page 9 6 RS 485 TRANSMITTER CONTROL In an RS 485 network the same pair of wires is used for both transmit and receive signals Although any number of nodes can be listening simultaneously only one can be transmitting or have its transmitter turned on in order for valid data to be transmitted across the network On Emerald MM an RS 485 port s transmitter enable signal is controlled by that port s RTS signal The RTS signal must be asserted driven low to enable the transmitter and deasserted driven high to turn off the transmitter 7 1 WIRE INTERFACE In model EMM 1W XT a 1 Wire interface module HA7S from Point Six Inc is mounted on the board near the top edge This port converts the RS 232 signals from port 1 into 1 Wire signals The user connections for port 1 are made through a separate 4 pin header J16 on the right side of the board The port 1 signals on pins 1 10 of J3 may not be used because of conflicts with the RX line being driven by the 1 Wire interface module On model EMM 1W XT Ports 2 3 and 4 are fixed in RS 232 mode J16 1 Wire Pinout 5 Gnd 1 Wire Gnd R O IN j gt 2003 Diamond Systems Corp Emerald MM User
34. parallel data that is then made available at the user data interface DO D7 The user optionally com pares the received data to the initial transmitted data for verifying error free operation of the UART TX RX circuits In this mode the receiver and transmitter interrupts are fully operational The Modem Control Interrupts are also operational However the interrupts can only be read using lower four bits of the Modem Control Register MCR bits 0 3 instead of the four Modem Status Register bits 4 7 The interrupts are still con trolled by the IER AE NB NB SS PLZ 5 43 ST16C554 554D 68C554 Z DAR A NB NB NB NB b N Figure 12 INTERNAL LOOPBACK MODE DIAGRAM Transmit Transmit o gt i FIFO Shift A D0 D7 Registers Register Na IOR IOW Data bus Control Logic RESET Receive Receive FIFO Shift Registers Register ta v ra S A0 A2 338 Aa CS A D VAI u S x Be es a H ei S E S o o de A S ke INTA D S Ss RXRDY 3 3 TXRDY gt S E S O gt E CN u SS XTALI M3 4 S XTAL2 la 3 BO AAN NG AD AD AD Ia 5 44 MCR Bit 4 1 TX A D RX A D RTS A D CDA D DTR A D RI A D OPI A D DSR A D OP2 A D CTS A D La PAR ST 16C554 554D 68C554 ooo REGISTER FUNCTIONAL DESCRIPTIONS The following table delineates the assigned bit functions for the fifteen 554D internal registers The assigned bit functions are mo
35. peration The 16 byte transmit and receive data FIFO s are enabled by the FIFO Control Register FCR bit 0 With 16C554 devices the user can only set the receive trigger level The receiver FIFO section in cludes a time out function to ensure data is delivered to the external CPU An interrupt is generated when ever the Receive Holding Register RHR has not been read following the loading of a character or the receive trigger level has not been reached Timeout Interrupts The interrupts are enabled by IER bits 0 3 Care must be taken when handling these interrupts Following a resetthe transmitter interrupt is enabled the 554D will issue an interrupt to indicate that transmit holding register is empty This interrupt must be serviced prior to continuing operations The LSR register provides the current singular highest priority interrupt only Servicing the interrupt without investigating further interrupt conditions can result in data errors When two interrupt conditions have the same priority it is important to service these interrupts correctly Receive Data Ready and Receive Time Out have the same interrupt priority when enabled by IER bit 0 The receiver issues an interrupt after the number of characters have reached the programmed trigger level In this case the 554D FIFO may hold more characters than the programmed trigger level Follow ing the removal of a data byte the user should recheck LSR bit 0 for additional charac
36. put Functions as a crystal input or as an external clock input A crystal can be connected between this pin and XTAL2 to form an internal oscillator circuit see figure 8 Alternatively an external clock can be connected to this pin to provide custom data rates see Baud Rate Generator Programming Output of the Crystal Oscillator or Buffered Clock See also XTAL1 Crystal oscillator output or buffered clock output Carrier Detect active low These inputs are associated with individual UART channels A through D A logic 0 on this pin indicates that a carrier has been detected by the modem for that channel Clear to Send active low These inputs are associated with individual UART channels A through D A logic 0 on the CTS pin indicates the modem or data set is ready to accept transmit data from the 554D Status can be tested by reading MSR bit 4 Data Set Ready active low These inputs are associated with individual UART channels A through D A logic 0 on this pin indicates the modem or data set is powered on and is ready for data exchange with the UART This pin has no effect on the UART s transmit or receive operation This pin has no effect on the UART s transmit or receive operation Data Terminal Ready active low These inputs are associated with individual UART channels A through D A logic 0 on this pin indicates that the 554D is powered on and ready This pin can be controlled via the modem control re
37. re fully defined in the following paragraphs 0 FCR e o 4 A2 A1 AO Register BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Note 5 General Register Set IER 00 modem receive transmit receive interrupt status register register interrupt ISR 01 FIFO s FIFO s INT INT INT INT enabled enabled priority priority priority status bit 2 bit 1 bit 0 LCR 00 divisor set set even parity stop latch break parity parity enable bits enable LSR 60 break framing parity overrun receive holding interrupt error error error data empty ready MSR XO0 CD DSR CTS delta delta delta delta CD RI DSR CTS Special Register set Note 2 Note 2 The Special register set is accessible only when LCR bit 7 is set to 1 Rev 3 00 PPP AD AD AD AD Table 6 ST16C554D INTERNAL REGISTERS ai status line holding holding RCVR RCVR DMA FIFO trigger trigger mode enable MSB LSB select MCRI00 loop OP2 OP 1 RTS back INTx enable 5 45 ST16C554 554D 68C554 Z EAR E Note s The value between the square brackets represents the register s initialized HEX value Transmit THR and Receive RHR Holding Reg isters The serial transmitter section consists of an 8 bit Transmit Hold Register THR and Transmit Shift Register TSR The status of the THR is provided in the Line Status Register LSR Writing to the THR transfers the contents of the data bus D7 DO to the THR providing that the THR or TSR is empty The T
38. rovides the status of data transfers between the 554D and the CPU LSR BIT 0 Logic O No data in receive holding register or FIFO normal default condition Logic 1 Data has been received and is saved in the receive holding register or FIFO LSR BIT 1 Logic 0 No overrun error normal default condition Logic 1 Overrun error A data overrun error occurred in the receive shift register This happens when addi tional data arrives while the FIFO is full In this case the previous data in the shift register is overwritten Note that under this condition the data byte in the receive shift register is not transfered into the FIFO therefore the data in the FIFO is not corrupted by the error LSR BIT 2 Logic 0 No parity error normal default condition Logic 1 Parity error The receive character does not have correct parity information and is suspect In the FIFO mode this error is associated with the character at the top of the FIFO LSR BIT 3 Logic 0 No framing error normal default condition Logic 1 Framing error The receive character did not AE NG AD A ADA a 9 50 Z EXAR ST16C554 554D 68C554 ANN NB NB NB NB NG ce e have a valid stop bit s In the FIFO mode this error is associated with the character at the top of the FIFO LSR BIT 4 Logic 0 No break condition normal default condi tion Logic 1 The receiver received a break signal RX was a logic O for one character frame time I
39. rrupt outputs INT A D When INTSEL is a logic 1 MCR bit 3 has no effect on the INT A D outputs and the package operates with interrupt outputs enabled continuously Programmable Baud Rate Generator The 554D supports high speed modem technologies that have increased input data rates by employing data compression schemes For example a 33 6Kbps modem that employs data compression may require a 115 2Kbps input data rate A 128 0Kbps ISDN modem that supports data compression may need an input data rate of 460 8Kbps The 554D can support a standard data rate of 921 6Kbps A dual baud rate generator is provided for the transmitter and receiver allowing independent TX RX channel control The programmable Baud Rate Generator is capable of accepting an input clock up to 24 MHz as required for supporting a 1 5Mbps data rate The 554D can be configured for internal or external clock operation For internal clock oscillator operation an industry standard micropro cessor crystal parallel resonant 22 33 pF load is connected externally between the XTAL1 and XTAL2 pins see figure 8 Alternatively an external clock can be connected to the XTAL1 pin to clock the internal baud rate generator for standard or custom rates see Baud Rate Generator Program ming AMEN NB NB SS NG N N A ZZ 5 41 ST 16C554 554D 68C554 La PAR ooo The generator divides the input 16X clock by any Figure 8 Crystal oscillator connection divisor from 1 to 2 1
40. s register are used to indicate the changed information These bits are setto a logic 1 whenever a control input from the modem changes state These bits are set to a logic O whenever the CPU reads this register MSR BIT 0 Logic 0 No CTS Change normal default condition Logic 1 The CTS input to the 554D has changed state since the last time it was read A modem Status Interrupt will be generated MSR BIT 1 Logic 0 No DSR Change normal default condition Logic 1 The DSR input to the 554D has changed state since the last time it was read A modem Status Interrupt will be generated MSR BIT 2 Logic 0 No RI Change normal default condition Logic 1 The RI input to the 554D has changed from a logic 0 to a logic 1 A modem Status Interrupt will be generated MSR BIT 3 Logic 0 No CD Change normal default condition Logic 1 Indicates that the CD input to the has changed state since the last time it was read A modem Status Interrupt will be generated MSR BIT 4 CTS active high logical 1 Normally MSR bit 4 bit is the compliment of the CTS input However in the loopback mode this bit is equivalent to the RTS bit in the MCR register MSR BIT 5 DSR active high logical 1 Normally this bit is the compliment of the DSR input In the loopback mode this bit is equivalent to the DTR bit in the MCR register MSR BIT 6 RI active high logical 1 Normally this bit is the compliment of th
41. sters Register 3 IOR Sy jan IOW EE RESET S O A Receive Receive A0 A2 3 Y S 40 sas S FIFO Shift CS A A I g i i YE 2 oS Registers Register S A Sa a che S JE L INT A D ad a gt S RXRDY S ES TXRDY SES SON kanng INTSEL XTALI SS Ss S amp S 283 e O ES XTAL2 RB Rev 3 00 1L LLLLLL L 5 31 ST16C554 554D 68C554 TX A D RX A D ST 16C554 554D 68C554 La EXAR PIZZA Figure 3 Block Diagram 68 Mode Transmit Transmit FIFO Shift TY A D D0 D7 Registers Register R W RESET Data bus amp Control Logic Receive Receive FIFO Shift RX A D Registers Register A0 A4 CS Register Select Inter Connect Bus Lines amp Control signals IRQ Ss RXRDY EE TXRDY S SN DTR A D RTS A D Modem ON Y E Control XTALI HP S 3 pa de RIA D S S S S CD A D XTAL2 g s DSR A D MIE aaa AAN 5 32 La PAR ST 16C554 554D 68C554 ose SYMBOL DESCRIPTION Symbol Signal Pin Description 64 type 16 68 Interface Type Select input with internal pull up This input provides the 16 Intel or 68 Motorola ae interface type select The functions of IOR IOW INT A D and CS A D are re assigned with the logical state of this pin When this pin is a logic 1 the 16 mode interface 16C554D is selected When this pin is a logic 0 the 68 mode interface 68C554 is selected When this pin is a logic 0 IOW is re assigned to R W RESET is re assigne
42. ters A Receive Time Out will not occur if the receive FIFO is empty The time out counter is reset at the center of each stop bit received or each time the receive holding register RHR is read The actual time out value is T Time out length in bits 4 X P Programmed word length 12 To convert the time out value to a character value the user has to consider the complete word length includ ing data information length start bit parity bit and the size of stop bit i e 1X 1 5X or 2X bit times Example A If the user programs a word length of 7 with no parity and one stop bit the time out will be T 4X7 programmed word length 12 40 bit times The character time will be equal to 40 9 4 4 characters or as shown in the fully worked out ex ample T programmed word length 7 stop bit 1 start bit 1 9 40 bit times divided by 9 4 4 characters Example B If the user programs the word length 7 with parity and one stop bit the time out will be T 4X 7 programmed word length 12 40 bit times Character time 40 10 programmed word length 7 parity 1 stop bit 1 start bit 1 4 characters In the 16 mode for 68 pin packages the system board designer can optionally provide software controlled three state interrupt operation This is accomplished by INTSEL and MCR bit 3 When INTSEL interface pin is left open or made a logic 0 MCR bit 3 controls the three state inte
43. ultiple versions with different combinations of protocols EMM XT 2 ports configurable for RS 232 RS 422 or RS 485 2 ports fixed RS 232 standard configuration EMM 4M XT 4 ports configurable for RS 232 RS 422 or RS 485 EMM 4232 XT 4 ports fixed in RS 232 EMM 4485 XT 4 ports configurable for RS 422 or RS 485 special order EMM 1W XT 4 ports fixed RS 232 port 1 has 1 Wire interface special order Eight different I O address combinations can be selected and 10 different interrupt levels can be assigned to configure each port allowing operation as COM1 through COM4 as well as many other settings Two I O headers are provided with two serial ports on each header The board operates on 5V only eliminating the need for a 12V supply that is often required for serial port operation Emerald MM is based on the 16C554 quad serial port IC This device contains 4 identical sets of registers one for each port and is compatible with the standard PC serial port Each port contains a 16 byte FIFO Complete descriptions of these registers may be found in the Appendix Most users will not need this programming information as it is normally handled by the operating system s communications software 2 FEATURES 416C550 compatible serial ports with 16 byte FIFOs e RS 232 RS 422 RS 485 and 1 Wire interface capability depending on the model Upto 115 2kbps in standard configuration 460 8kbps available 8different I O address options
44. will reflect the following A The receive data available interrupts are issued to the external CPU when the FIFO has reached the programmed trigger level It will be cleared when the FIFO drops below the programmed trigger level B FIFO status will also be reflected in the user accessible ISR register when the FIFO trigger level is reached Both the ISR register status bit and the interrupt will be cleared when the FIFO drops below the trigger level C The data ready bit LSR BIT 0 is set as soon as a character is transferred from the shift register to the receive FIFO It is reset when the FIFO is empty IER Vs Receive Transmit FIFO Polled Mode Op eration When FCR BIT 0 equals a logic 1 resetting IER bits 0 3 enables the 554D in the FIFO polled mode of operation Since the receiver and transmitter have separate bits in the LSR either or both can be used in the polled mode by selecting respective transmit or receive control bit s A LSR BIT 0 will be a logic 1 as long as there is one byte in the receive FIFO B LSR BIT 1 4 will provide the type of errors encoun tered if any C LSR BIT 5 will indicate when the transmit FIFO is empty D LSR BIT 6 will indicate when both the transmit FIFO and transmit shift register are empty E LSR BIT 7 will indicate any FIFO data errors IER BIT 0 This interrupt will be issued when the FIFO has reached the programmed trigger level or is cleared when the FIFO drops below t
45. wo different QFP packages The ST16C554DCQ64 operates in the continuos interrupt enable mode by bonded INTSEL to VCC internally The ST16C554CQ64 operates in conjunction with MCR bit 3 by bonding INTSEL to GND internally FUNCTIONAL DESCRIPTIONS Interface Options Two user interface modes are selectable for the 554D package These interface modes are designated as the 16 mode and the 68 mode This nomenclature corresponds to the early 16C554D and 680554 pack age interfaces respectively The 16 Mode Interface The 16 mode configures the package interface pins for connection as a standard 16 series Intel device and operates similar to the standard CPU interface avail able on the 16C554D In the 16 mode pin 16 68 logic 1 each UART is selected with individual chip select CSx pins as shown in Table 2 below Table 2 SERIAL PORT CHANNEL SELECTION GUIDE 16 MODE INTERFACE CSC UART CHANNEL D Rev 300 i NB AD 7 7777 5 39 ST16C554 554D 68C554 Z EAR A NB NB NB NB b N a The 68 Mode Interface The 68 mode configures the package interface pins for connection with Motorola and other popular micro processor bus types The interface operates similar to the 68C454 554 In this mode the 554D decodes two additional addresses A3 A4 to select one of the four UART ports The A3 A4 address decode function is used only when in the 68 mode 16 68 logic 0 and is shown in Table 3 below Table 3 SERIAL POR
46. y address bits AO A2 When the 16 mode is selected this pin functions as R W see definition under R W 15 Interrupt Request or Interrupt A This function is associ ated with the 68 mode only In the 68 mode interrupts from UART channels A D are WIRE OR ed internally to function as a single IRQ interrupt This pin transitions to a logic 0 if enabled by the interrupt enable register wnenever a UART channel s requires service Individual channel interrupt status can be determined by addressing each channel through its associated internal register using CS and A3 A4 In the 68 mode an external pull up resistor must be connected between this pin and VCC The function of this pin changes to INTA when operating in the 16 mode see definition under INTA D Rev 300 Af ff f f N N A 5 35 ST 16C554 554D 68C554 La PAR PIZZA SYMBOL DESCRIPTION Symbol Pin Signal Pin Description 68 64 type 13 47 64 4 21 35 52 Reset In the 16 mode a logic 1 on this pin will reset the internal registers and all the outputs The UART transmitter output and the receiver input will be disabled during reset time See ST16C554D External Reset Conditions for ini tialization details When 16 68 is a logic 0 68 mode this pin functions similarly but as an inverted reset interface signal RESET Read Write Strobe active low This function is associated with the 68 mode only This pin provides the combined functions for Read
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