EVBUM2076 - Crystal Clock Oscillator Module Evaluation Board
Contents
1. Generic Marking Diagram Soldering Footprint PACKAGE DIMENSIONS 6 PIN CLCC 7x5 2 54P CASE 848AB 01 ISSUE C NOTES B 1 DIMENSIONING AND TOLERANCING PER ASME Y14 5M 1994 4X C3 0 15 2 CONTROLLING DIMENSION MILLIMETERS MILLIMETERS DIM MIN NOM MAX E A 170 1 80 1 90 A1 0 70 REF INDICATOR A2 0 36 REF A3 008 0 10 0 12 x JA b 1 30 1 40 1 50 S D 7 00 BSC Di 617 620 623 D2 666 681 6 96 TOP VIEW D3 5 08 BSC E 5 00 BSC A3 A2 E1 4 37 4 40 4 43 Z 0 10 C E2 465 480 4 95 E3 3 49 BSC Y EJ A A e 2 54 BSC H 1 80 REF L 11 127 137 Ki SIDE VIEW R 0 70 REF SEATING PLANE Oo GENERIC D3 MARKING DIAGRAM 0 10 C AJB XXXXX Specific Device Code 0 05 C ex b E e m A exL A Assembly Location WL Wafer Lot BOTTOM VIEW YY aar WW Work Week G Pb Free Package SOLDERING FOOTPRINT This information is generic Please refer H EN to device data sheet for actual part mark ing e Pb Free indicator G or microdot 1 50 may or may not be present aai 2 54 j LL PITCH DIMENSION MILLIMETERS 5 06 6x For additional information on our Pb Free strategy and soldering details please2. download the ON Semiconductor Soldering and Mounting Techniques Reference Manual SOLDERRM D www BD fI com ON XOCLCC6EVB ON Semiconductor and D are registered trademarks of Semiconductor Components Industries LLC SCILLC SCILLC reserves the right to make changes without further notice to any products herein SCILLC makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does SCILLC assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation special consequential or incidental damages Typical parameters which may be provided in SCILLC data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts SCILLC does not convey any license under its patent rights nor the rights of others SCILLC products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur Should Buyer purchase or use SCILLC products for any such unintended or unauthorized appli
3. D fI com ON XOCLCC6EVB Evaluation Board Fabrication Notes 1 2 3 QN tA N Material FR 4 Finished copper to be loz 0 0014 external layers Minimum copper plating 0 0007 thick for plated thru holes annular ring to be 0 0002 minimum LPI soldermask green Soldermask registration 0 002 N A All exposed copper areas to be gold plated 0 000030 gold over 0 000100 nickel If specified silkscreen is to be white epoxy ink Hole diameter tolerance is 0 002 maximum layer to layer misregistration shall be 0 004 measurement method must comply with MIL P 55110D Figure 1 Finished conductor width shall not vary more than 0 001 from artwork master 50 Q traces are 0 024 wide 10 11 12 13 14 15 16 17 18 Warp and twist of single sided boards shall not exceed 0 002 per inch warp and twist of multi layer boards shall not exceed 0 010 per inch All dimensions are in inches unless otherwise specified tolerances XX 0 010 XXX 0 004 Acceptability requirements per IPC A 600E Drawing is viewed from component or primary side This is a 4 layer board All holes are plated thru unless otherwise specified Drill size units are thousandths of an inch Trim all silkscreen which flows over via holes or SMD pads Break all sharp edges PCB edges should be smooth and even www BD ff com ON XOCLCC6EVB Appendix Mechanical Case Outline
4. XOCLCCGEVB Crystal Clock Oscillator Module Evaluation Board User s Manual for NBX Family in 6 Pin CLCC 5 mm x 7 mm Package Generic Evaluation Board XOCLCC6EVB Devices NBXxxxx Description This Evaluation Board user s manual is a guide for using the XOCLCC6EVB Evaluation Board to provide a convenient platform for quickly evaluating characterizing and verify performance and operation of a device in the NBXxxxx family of Clock Oscillator Modules packaged in the 6 pin CLCC 5mm by 7 mm CASE 848AB see Appendix This family of devices offer an internal crystal and PLL IC This Evaluation Board Manual and Evaluation Board should be used in conjunction with a specific device data sheet which contains full technical details on specifications and operation An NBXxxxx Clock Oscillator Module device may be directly solder mounted onto the available evaluation board footprint or multiple units may be inserted and tested by solder mounting a separate insertion socket P N AM0393 320R from SER Electronics onto the available footprint Evaluation Board Features 6 pin CLCC solder footprint for solder mounting a device or test socket Incorporates jumper headers to conveniently and manually control the levels for the Output Enable Pin 1 and Frequency Select Pin 2 pins Enable single or split power supply operation LVPECL differential outputs are accessed via SMA connectors offering different output load con
5. cation Buyer shall indemnify and hold SCILLC and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part SCILLC is an Equal Opportunity Affirmative Action Employer This literature is subject to all applicable copyright laws and is not for resale in any manner PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT N American Technical Support 800 282 9855 Toll Free ON Semiconductor Website www onsemi com Literature Distribution Center for ON Semiconductor USA Canada P O Box 5163 Denver Colorado 80217 USA Europe Middle East and Africa Technical Support Order Literature http www onsemi com orderlit Phone 303 675 2175 or 800 344 3860 Toll Free USA Canada Phone 421 33 790 2910 a Fax 303 675 2176 or 800 344 3867 Toll Free USA Canada Japan Customer Focus Center For additional information please contact your local Email orderlit onsemi com Phone 81 3 5817 1050 Sales Representative www BDTIC com ON a
6. cilloscope Or Frequency Counter Power Supply VEE 3 3V 3 3V Note For CML outputs 50 Q to Vpp is needed for proper termination See application note AND8173 D Figure 5 Typical Lab Setup for CML Outputs DO NOT JUMPER DUTGND and SMAGND Power Supply Digital Oscilloscope High Impedance Differential Jumper Figure 6 Typical Lab Setup for LVDS Outputs SUMPER DUTGND and SMAGND www BD Tt tom ON XOCLCC6EVB Table 5 XOCLCC6EVB EVALUATION BOARD BILL OF MATERIALS Components Manufacturer Description Part Number Qty Jumper Header Berg 100 mil In House 5 Test Point Keystone Anvil SMD 5016 3 Shunt Connector Johanson SMA Edge Mount 142 0711 821 2 Capacitor Kemet 22 uF 10 T491D22K016AS Case C or D 2 Capacitor Kemet 0 1 uF 10 C0603C104K4RAC 2 Socket Not Supplied SER Electronics Socket 6 Lead 5mm x 7mm AM0393 320R 1 VDD VDD 1 r Jumper Header Test Point eot Point L m f I VDD 1 6 ke L 4 rqa CLK 1 DUTGND FSEL r Test 1 5 SMA Point c L 4 L i Jumper Header GND DUTGND f 1 r CLK t 15 J2 Test SMA m DUTGND E Jumper Header DUTGND LJ suAGND 22uF u 1uF Y O 1uF SMAGND SMAGND Figure 7 XOCLCC6EVB Evaluation Board Schematic 4 LAYER STRUCTURE iU SIDE dq 4 NIL 062 004 z E M ERA SCALE NONE BOTTON SIDE Figure 8 XOCLCC6EVB Evaluation Board Layer Lamination Stackup www B
7. figurations ON Semiconductor hitp onsemi com EVAL BOARD USER S MANUAL Evaluation Board Manual Document Features Information on the XOCLCC6EVB Evaluation Board Appropriate Lab Setup and Procedures Board build Bill of Materials Table 5 Evaluation Board schematic Figure 7 Evaluation Board Lamination Stackup Figure 8 Evaluation Board Fabrication Notes Appendix Mechanical Case Outline Generic Marking Diagram Soldering Footprint What measurements can you expect to make With this evaluation board the following measurements could be performed in single ended or differential modes of operation DC Characteristics Frequency Performance Output Rise and Fall Time Phase Noise e Jitter Front Back Figure 1 Evaluation Board Images Front and Back Semiconductor como ATATA B D ik CO m ON Order Number February 2012 Rev 2 e e EVBUM2076 D XOCLCC6EVB EVALUATION BOARD MAP Figure 2 Evaluation Board Layout Table 1 EVALUATION BOARD MAP DESCRIPTION Number Description 1 DUT PIN6 Positive supply connection anvil and test point 2 Decoupling capacitors See BOM board schematic for details 3 DUT PIN 4 OE jumper header to force logic HIGH Active or LOW Outputs Disabled to High Impedance Leave open or use jumper to force HIGH OE Pin defaults HIGH when left floating see Figure 3 below 4 OE connection anvil and test
8. ors are installed from Vpp to SMAGND and DUTGND to SMAGND near the test points see BOM Devices may be tested in one of three supply modes see Table 3 A Single Positive 3 3 V Setup No offset to supplies or output levels B Split 3 3 V Setup Offsets the Vpp DUTGND and output voltage levels by 1 3 V and avoids an additional separate Vrr supply and allows a direct connection to test equipment such as an oscilloscope or counter with 50 2 impedance to GND inputs SMAGND Vrr Vpp 2 0 V 0 0 V C Single Negative 3 3 V Setup Offsets the Vpp DUTGND and output voltage levels by 3 3V Table 3 XOCLCC6EVB POWER SUPPLY CONNECTION VOLTAGES A Single C Single Positive B Split 3 3 V Negative 3 3 V Setup Setup 3 3 V Setup V V V TT TT Vpp 20V Vpp 2 0 V SMAGND 2 0 V SMAGND 0V Vpp 0V DUTGND DUTGND DUTGND 3 3 V SMAGND 1 3V 0V NOTE SMAGND is the SMA cable shield reference for the inputs and outputs only not to be confused with the device ground pin DUTGND TT Vpp 2 0 V 1 3V Step 2 Connect Output Signals Table 4 gives a list of specific LOGIC Levels and their appropriate Power Supply and Typical Lab Setup conditions LVPECL The LVPECL outputs have standard open emitter outputs and must be externally DC loaded and AC terminated A split power supply technique takes advantage of terminating the LVPECL outputs into 50 Q of an oscilloscope or a frequency c
9. ounter Since Vrr Vpp 2 V offsetting Vpp to 2 0 V yields Vrr 0 V or Ground SMAGND The Vrr terminal connects to the isolated SMAGND connector ground plane and is not to be confused with the device ground pin DUTGND See Application Note ANS8020 D for details on ECL termination CML For CML lab setup and test operation with negative supply voltage is recommended to enable the 50 Q internal impedance in the oscilloscope to be used as a termination of the CML signals Vpp 0 0 V SMAGND 0 0 V and DUTGND 3 3 V See Application Note AN8173 D for details on CML termination www BD ff com ON XOCLCC6EVB LVDS Driver termination is a 100 Q resistor across the Step 3 Configure FSEL and OE differential lines located at the receiver input The FSEL and OE control pins can be controlled from an external source via the appropriate test point or via the Table 4 TYPICAL LAB SETUP jumper headers located on the evaluation board as indicated in Figures 2 and 7 Refer to the specific device datasheet for Typical Lab details on the proper settings for these pins LOGIC Levels Power Supply Setup LVPECL Split 3 3 V CML Single 3 3 V See Figure 5 LVDS Single 3 3 V See Figure 6 2 0V Digital Oscilloscope Or Frequency Counter VDD 2 0V Power Supply Figure 4 Split Power Supply Lab Setup for LVPECL Outputs DO NOT JUMPER DUTGND and SMAGND www BD fI com ON XOCLCC6EVB ov VDD SMAGND 0V Digital Os
10. point 5 DUT PIN 2 FSEL jumper header to force logic HIGH or LOW FSEL Pin defaults HIGH when left floating see Figure 3 below 6 FSEL connection anvil and test point 7 Device ground DUTGND connection anvil and test point 8 DUT PIN 3 GND SMAGND jumper header to force DUTGND connection to SMAGND see Figure 3 below 9 SMAGND connection anvil and test point 10 SMA outputs CLK CLK 11 6 pin CLCC 5mmX7mm DUT Device under test www BD fI com ON XOCLCC6EVB ogr H L H L H Da AG D o 0 SELECT HIGH SELECT LOW Evaluation Board Jumper Headers on OE Pin 4 FSEL Pin 5 SELECT OPEN i H SELECT OPEN DUTGND connected to SMAGND Evaluation Board Jumper Header on DUTGND Pin 3 Figure 3 Select Positions for Evaluation Board Jumper Headers on OE Pin 4 FSEL Pin 5 and DUTGND Pin 3 TIME DOMAIN MEASUREMENTS Equipment Table 2 indicates the recommended equipment for making characterization and performance measurements Table 2 BASIC EQUIPMENT Power Supply with 4 HP6624A or similar 1 outputs Real Time Oscilloscope DPO70804 or similar Matched High Speed Cables with SMA Storm Semflex or 2 similar Connectors Setup The following steps should be followed for proper equipment setup Step 1 Connect Power split power supply mode Three power levels must be provided to the board Vpp DUTGND and SMAGND via the test point anvils at the edges of the board Bypass capacit
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