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An Introduction to the MC68HC16Z1

1. 000000 em gemet AS 7 _ aos n veeR EXCEPTION l 0000 0 RESET INITIAL ZK SK AND PK 010000 Bank 1 at HE ee ee 020000 Fank 000A 5 BERR BUS ERROR 000C 6 SWI SOFTWARE INTERRUPT ee 030000 Ceues 0012 001 SE UNASSIGNED RESERVED 512 KBYTE 0026 10 UNASSIGNED RESERVED C 040000 Tee 0024 12 LEVEL INTERAUPT AUTOVECTOR 0026 13 LEVEL3 INTERRUPT AUTOVECTOR 002 14 LEVEL 4 INTERRUPT AUTOVECTOR 050000 Cous DOOR 15 LEVELS INTERRUPT AUTOVECTOR 002C 16 LEVEL 6 INTERRUPT AUTOVECTOR 002E 17 LEVEL 7 INTERRUPT AUTOVECTOR 060000 Ce 0030 18 SPURIOUS INTERRUPT 0032 006E 19 37 UNASSIGNED RESERVED 0070 01FE 38 FF USER DEFINED INTERRUPTS 070000 gank7 PROGRAM 07FFFF DATA SPACE 080000 uerwen INACCESSIBLE FFF700 y F7FFFF ADC F80000 BANKS FFF73F aes ene CONTROL SE FFF83F FA0000 MBaNK10 FFF900 FFF93F FB0000 Ca 512 KBYTE FFFA00 FC0000 I BanK12 aM FFFA7F FD0000 Cous SRAM FFFB00 CONTROL FFFB07 FE0000 Vous 1 FFFC00 FF0000 BANK15 y QSM INTERNAL REGISTERS FFFDFF FFFFFF Figure 17 Pseudolinear Addressing with Combined Program and Data Spaces 4 1 1 2 The Extension Fields The CPU16 generates the lower 20 bits of a 24 bit address by concatenating a 4 bit value in an exten sion field with a 16 bit address There are five extension fields EK XK
2. 6 1 2 Reference Manuals M683HC16 Family CPU16Central Processor Unit Reference Manual CPU16RM AD Modular Microcontroller Family Analog to Digital Converter Reference Manual ADCRM AD Modular Microcontroller Family Queued Serial Module Reference Manual QSMRM AD Modular Microcontroller General Purpose Timer Reference Manual GPTRM AD Modular Microcontroller Family System Integration Module Reference Manual SIMRM AD 6 1 3 Application Notes AN437 D Using the MC68332 Periodic Interrupt Timer AN461 D An Introduction to the HC16 for HC11 Users AN1050 D Designing for Electromagnetic Compatibility with HCMOS Microcontrollers AN1051 D Transmission Line Effects in PCB Applications AN1058 D Reducing A D Errors in MCU Applications AN1062 D Using the QSPI for Analog Data Acquisition AN1213 D 16 Bit DSP Servo Control with the HC16Z1 AN1230 D A BDM Driver Package for Modular Microcontrollers AN1233 D Using the M68HC16 DSP to Build an Audio Frequency Analyzer AN1249 D Brushed DC Motor Control Using the MC68HC16Z1 AN1254 D M68HC16 Audio Tone Generation AN1310 D Using the MC68HC16Z1 Microcontroller for AC Induction Motor Control M68HC16PN01 D Transporting M68HC11 code to M68HC 16 devices 6 1 4 Development Tools and Software Freesca e Microcontroller Development Tools Directory MCUDEVTLDIR D 6 1 5 Books Programming Microcontrollers in C TB328 6 2 Freeware Data Systems The Freescal e Freeware BBS can be accessed by modem a
3. 4 1 3 2 Initializing Exception Vectors Other Than Heset 34 4 1 4 CPU Condition Code Heoister A 34 4 2 Configuring the System Integration Module 35 4 2 1 System Integration Module Configuration Register SIMCR sesseesseesseseesesresrresnsss 35 4 2 2 Clock Synthesizer Control Register GONCH 35 4 2 3 System Protection Control Register GYPCH 35 4 2 4 Periodic Interrupt Timer Register PITR eececceeeeeeneeeeeeeneeeeeeeaeeeeeeeaaaeeeeeseaeeeeeseeaaes 36 4 2 5 Periodic Interrupt Control Register DICH 36 4 2 6 Chip Select Pin Assignment Registers CSPARO and CGPAPI 36 4 2 7 Chip Select Base Address Registers CSBARBT CGBAPfO 70 36 4 2 8 Chip Select Option Registers CSORBT and CGOpI0 710 36 4 2 9 General Purpose I O Ports AE 37 4 2 10 Example of SIM Initialization 0 0 2 cece ceeeeeceeeeeeeeeeeeaeeeeeeeeeseaeeeeeeeeesaeesseeeeesnaeeeseaaeeee 37 4 3 Configuring Internal RAM fccctetecgexasnecsteteectin raet aaien rara annara eaa aa a eean aaaea eaaa aa tent 39 4 4 Configuring the Queued Serial Module 39 4 4 4 Configuring the WEE 39 4 4 2 Configuring the OP 40 4 4 2 1 QSPI Initialization Example ecccc cc ceeeeeeeeeeeeeeeeeeeeeeeaeeeeeeeeeseaeeeeeaeeeeeeeeeeeaeeesaes 41 4 4 3 Initializing QSM Interrupts eee ee cece cence eeeeeeeeeeeeeeeaaeeseeeeeesaaaeseeeeeeseaaeeseeeeeseaeeseaeeeee 42 4 5 Configuring the General Purpose Timer 42 E E El 43 45 2 GPT Initialization Example sac ci
4. OCH channels OC1 does not have the ability to toggle on a match LDD TCNT add offset to TCNT for delay before ADDD 200 first compare STD TOC1 store TCNT Offset into TOC1 STD TOC4 store TCNT Offset into TOC4 STD TI405 store TCNT Offset into TOC5 All of the OC channels are initialized with the same value so that the 5 square waves will be phase locked Different offsets could be used for each channel This would simply skew the square waves with respect to each other they would still be frequency locked LDD 5000 STD CTL1 JOC 4 and 5 will toggle on compare NU RES LDD OC1_INT Store interrupt routine addresses STD 108 Z jin the vector table Note this could LDD OC4_INT be done in the file init_int asm STD S10E Z LDD OC5_INT STD 110 2 LDD 0085 STD GPTMCR set SUPV 1 IARB 5 LDD 0680 GPT priority 6 base vector 80 STD ICR LDD c800 TCNT is Sys CLlk Div 4 reset value STD TMSK1 each count 238 nsec for 16 78 MHz Sys Clk enable interrupts for OC channels WAI_FOR_INT BRA WAI_FOR_INT normally this would go on to the next program task Each time that a match occurs between OC4 or OC5 and the Timer Counter TCNT the respective OC channel will toggle If the software driver for the OC channel does not service an OC flag for some reason a match will occur each 65 535 DONT counts OC1 is a special case When it matches with TCNT it will drive pins OC1 3 to the level written to the respec
5. This example initializes chip selects 0 1 and 2 to select two 8 bit external RAMs The RAMs are mapped at address 30000 It also initializes the periodic interrupt timer to time out every one second INCLUDE equates asm include register equates For More Information On This Product Go to www freescale com Freescale Semiconductor Inc INCLUDE init_res asm initialize reset vector INCLUDE init_int asm initialize exception table ORG 200 begin program at 200 immediately after the exception table INITSYS LDAB S0F BE point to internal registers LDAB 503 TBXK point XK to bank 3 for external RAM access LDX 50000 now X points to 30000 LDAA 7F STAA SYNCR set system clock to 16 78 MHz CLRA STAA SYPCR disable software watchdog LDD MCR ANDD FFFO set interrupt arbitration field to a ORD 0005 unique value SID MCR INITCS This section initializes two 32K x 8 RAM chips using the Chip Selects The memory will start at address 30000 and will be both byte and word readable and writable This program assumes that the RAM chips have access times of 85 ns and require no wait states The DSACK field of the CSOR Registers may need to be adjusted for chips that have faster or slower access times The hardware configuration should be similar to Figure 13b shown earlier in this tutorial in the section Connecting Memory and Peripherals However if loadi
6. YK ZK SK and PK The EK field contains ADDR 19 16 of the address used by the extended addressing mode The XK YK and ZK fields contain ADDR 19 16 of the indexed registers IX IY and IZ respectively Likewise the SK field extends the stack pointer and the PK field extends the program counter Immediately after the re lease of reset the ZK SK and PK fields are determined by the values stored in the reset vector at lo cation 000000 All other extension fields must be written by the program code after reset This is done For More Information On This Product Go to www freescale com Freescale Semiconductor Inc with the transfer B to extension field instructions TBEK TBXK TBYK TBZK and TBSK An example of how to modify an extension register is shown below INIT LDAB S01 BEK EK is now set to 1 ACCESS LDD 0000 Load accumulator D with the value at address 10000 4 1 1 3 Switching Between Banks One way to access a particular bank when doing extended addressing is to write that bank number into the EK register Then every time the program reads or writes a memory location bits 16 through 19 of the extended address will be the value in the EK register Many programmers use the EK register to access bank 15 since that is where the internal registers are located To access other banks use one or more of the index registers as page pointers The IZ register is the most convenient register to use because bo
7. these pins to digital data These inputs should have low AC impedance at the pins This can be ac complished by placing a capacitor with good high frequency characteristics at the input pin A series resistor can also be used to implement a simple RC filter However when using a series resistor the user must consider the source impedance of the circuit supply the analog signal and any leak age that may occur It is imperative that for greatest accuracy in conversions the analog power supply and reference volt ages must be isolated from the digital power bus There must be low impedance paths between all an alog ground points in the circuit Use large width PC board traces for routing power to decrease impedance between analog reference points increase the effectiveness of decoupling filtering and de crease the chance of high frequency cross coupling For best results carve an analog ground plane out of the digital ground plane Chapter 6 of the ADC Reference Manual ADCRM AD has more information on pin connection considerations MC68HC16Z1TUT D For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 4 6 1 ADC Initialization Example This program initializes the ADC and samples the ADO pin It uses the single channel four conversion sequence The most recent conversion will be in the E register and its format will be right justified un signed Be sure to connect Vopa Vssa Vrh and Vo as described
8. BDM 3 1 2 2 How BDM Works The debugger causes the MCU to enter debugging mode by driving the BKPT pin low at the release of the RESET signal Reset causes the MCU to fetch the reset exception vectors load the program counter and stack pointer then fetch the first instruction pointed to Since the SRAM module is disabled out of reset reset vector fetches are made from external memory enabled by the CSBOOT signal If the CSBOOT chip select circuit is configured to enable a 16 bit port DATAO 1 at release of RESET the first word of the instruction is fetched however if the CSBOOT chip select circuit is configured to enable an 8 bit port DATAO held low at the release of RESET the MCU fetches the first byte of the instruction The MCU then enters BDM At this point the debugger causes the MCU to fetch several instructions which are displayed in the de bugger window on the computer screen If valid stack pointer and program counter values are present and a valid program is resident at the address pointed to by the initial PC value the debugger will dis play the code beginning at the program counter address If the initial stack pointer and program counter values are not valid however or if the external memory is either not connected or uninitialized when the fetches are made it is very likely that the initial SP and PC values will be FFFF and that both the initial SK and PK values will be FF CSBOOT is the only chip select circui
9. E E 1 2 Designing the Hardware ccccceseccceesseeeeeeeeeseeeseeeeeneeeseeeeseeeeseeesneeseeenseeeeeeeeaseaeseeensneeeeeeenseceeeenanes 4 2 1 Using Data Bus Pins to Configure the MCL 4 2 2 ChoOOSiNg MEMOry WI rriren eestadecnnecgeceasteceneteeestecareeetes reseacaneitaaeeaeetacecenepet teas 5 2 3 Pins that Need Pull Up ReSiStOrs AA 6 2A USING SOCKEIS Ais A tet Saas Ate ee ian tee ca hie tl sa lea ae 7 2 ClOCK CIRCUIT TEE 8 2 5 1 Using the Internal Frequency Synthesizer Circuit ccecccecceeeeeeneeeeeneeeeeeeeseteeeestaeeesaes 8 2 5 2 Using a Crystal Oscillator Circuit 0 cccceecccceeeeeeeeeeeeeeeeeeeeeeeeeceaeeeeeaeeeeaeeeseaaeeseeeeennaeeeeaes 8 2 5 2 1 Oscillator Components AA 8 Ee RE 10 2 5 2 3 Layout and Strange Behavior tsignp ninenin agiia aane aa ia eana aeaa ASEET 11 2 5 2 4 XFC and VDDSYN E O E E O E E T 11 2 5 2 5 Evaluating Oscillator Pertormance 12 2 5 2 6 Using a Canned Oscillator 0 eccececeeeeceeeeeeeeaeeeeeeeeeeeaeeeseaeeeseaeeeseaeeeseieeeeteaeeseaes 12 2 5 3 Using an External Clock Ferir fev tere ies eeg ke eeeeE eke coed aa eeri ea aaa a anaana d piinia 13 2 6 Getting Out of Reset 2 0 eeecceec ce ceseeeeeeeeeeeaeeeeeeeeeeaeeeaeeeecaaeeeeaeeecaaeeseeaaeessaeeeseaaeeeseeeeseaeeesenees 13 27 e Tee 14 2 7 1 Low Voltage Inhibit Devices 20 ee cectee eee enne eee ee eeaae eee eeeaaaeeeeeeeaaeeeeeeeaaaeeeeeeenaeeeeeeenaaes 14 2 7 1 1 Using LVI Devices with External Oscillators
10. Inc 2 5 2 3 Layout and Strange Behavior Oscillator layout is just as important as a good quality crystal and cleanliness in manufacturing the print ed circuit board The best possible solution is to use a multi layer board with a separate ground plane The rules for oscillator layout are quite simple First locate the crystal and all associated external com ponents as close to the oscillator pins as possible Second do not under any circumstance run a high frequency trace under either the feedback or series resistor or the crystal Third if there is no separate ground plane make sure that the ground for the bypass capacitors is connected to a solid ground trace Figure 5 shows typical one layer oscillator layout EXTAL GND XTAL GROUND PLANE Chypass 332TUT XTAL PCB LAYOUT Figure 5 Typical One Layer Oscillator Layout Do not run high frequency conductors near and particularly underneath the crystal the feedback re sistor or the series resistor In Figure 5 only a ground trace runs underneath these components Also note that in Figure 5 the ground trace is tied to the ground pin nearest to the oscillator pins This helps prevent large loop currents in the vicinity of the crystal It is also very important to tie the ground pin to the most solid ground in the system The trace that connects the oscillator and the ground plane should not connect to any other circuit element as the inje
11. OO KEE NAAA z e OOOO oo lt M CO ei Cl e SE Gef TUE e e ze HH EE EE E EE OC ANRNANNKLARNASRFSRANGAOAMYS anaagaaaaaKe EOOSCOSSSSELOSSSSSVGSSSzeeoegogageggs Coop Oo Ss OO OO op D oO st st st st st OO TXD PQS7 BRICSO ADDR1 FC2 CS5 PC2 ADDR2 FC1 CS4 PC1 VDDE VDDE VSSE VSSE ADDR3 FCO CS3 PCO ADDR4 CSBOOT ADDR5 DATAO ADDR6 DATA ADDR7 DATA2 ADDR8 DATA vssl vssl ADDR9 DATA4 ADDR10 DATA5 ADDR11 DATA6 ADDR12 M68HC16Z1 DATA7 ADDR13 DATA8 ADDR14 DATA9 ADDR15 VDDE ADDR16 VSSE ADDR17 DATA10 ADDR18 DATA11 VDDE DATA12 VSSE DATA13 VDDA DATA14 VSSA DATA15 ANO PADAO ADDRO AN1 PADA1 DSACKO PEO AN2 PADA2 DSACKT PE1 ANS PADAS AVEC PE2 AN4 PADA4 DS PE4 ANS PADA5 ASIPES VRH VDDE opt ams w wu ee x kk t s GO sx Oo Now T2eHetSePOPEo5SOSGSSSHEECLRFPELPERHS KFOOFEDESSKaMOSEOaATMSumeacaaadceradcn EEGEN e e SEO E e HI E E t ZASS e e aa gt DI An Q w IS O O O O O O A HI HI H H Q ul KS Oe or gt ONIEROase Oye EG NN Zz Doga S Q nw LL w H x D D Z1 132 PIN QFP Figure 10 Pinout of MC68HC16Z1 132 Pin Package To control power supply ground noise use dedicated ground and supply planes When designing a two layer board make the power and ground traces on the PCB as large as practical and connect a bypass capacitor to each power supply pin The Vrpndy zer and Vbpe sse supply pins should all have dedicat ed filter capacitors and ideally all supply pins should be connec
12. allow interrupts on levels 6 and 7 only mask out levels 5 and below ANDP FF1F ORP 00a0 During interrupt processing a copy of the current CCR is saved onto the stack and the priority level of the interrupt being serviced is written to the IPL field of the CCR This means that during execution of an interrupt routine only higher priority interrupts can be recognized However the CPU16 guarantees that at least the first instruction of an interrupt routine will be executed before another interrupt can pre empt it This allows the interrupt routine to inhibit other interrupts except for level 7 during the routine by re writing the IPL field in the CCR For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 2 10 2 Interrupt Arbitration Field Most modules in the MCU can request interrupt service The CPU treats external interrupts as interrupt service requests from the system integration module SIM The interrupt arbitration IARB field in the configuration register of each module determines which module s interrupt requests take precedence when the CPU receives more than one request at the same priority level In order for interrupt requests to be acknowledged each module must be assigned a unique ARB number between 1 lowest pre cedence and F highest precedence Out of reset the SIM IARB field has an initial value of F while other modules have initial IARB values of 0 2 10 3 Interru
13. an 8 bit vector number onto the data bus Chip select logic then terminates the ACK cycle with DSACK a a ee ae ee MC68HC16Z1TUT D For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MC68HC16Z1 PERIPHERAL D7 D14 lt _ _ _ _ _ gt D6 D13 lt _ _____ gt D5 E ja OOOC CO 2 b G E ER gt CH xX 332TUT PERI CONN Figure 15 Chip Select Line Used for Interrupt Acknowledge 2 10 4 2 Autovectors When an external device cannot supply a vector number in response to an IACK cycle an autovector can be used instead The autovector number is determined by the priority of the interrupt request For example autovector number 2 corresponds to IRQ2 In order for an autovector to be automatically used the IACK cycle must be terminated by an AVEC signal There are two ways to do this either assert the AVEC signal externally or use the internal chip select circuitry to provide the AVEC signal Once the bus cycle has been terminated the CPU saves the current context loads the 16 bit vector into the PC and begins to execute the service routine at that address As a side note internal modules cannot ter minate an IACK cycle with AVEC which would cause the CPU to automatically provide the autovector An internal module must request a particular vector number by writing the appropriate value to its inter rupt configuration register Th
14. and F All interrupting modules must have a unique non zero value in the IARB field Is the IPL field in the condition code register set to a value lower than the desired interrupt lev el The CPU will not recognize an interrupt that is at the same level or lower than the value in the IPL field Level 7 is the only exception to this rule it is always recognized Is the IACK cycle terminated with AVEC or DSACK The IACK cycle must be terminated by assertion of the AVEC or DSACK signals or a chip select circuit must be configured to assert AVEC or DSACK internally e Does the interrupt request signal negate inside the exception handler It is a good idea to control negation of the interrupt in software The interrupt should be negated before the RTI instruction E ee ey eee ee ee ee MC68HC16Z1TUT D For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 3 Establishing Communication 3 1 Communicating with the Target Board After a target board has been built it is generally necessary to communicate with it for debugging pur poses Although a designer can write a ROM monitor to communicate with the MCU via the serial port itis simpler and often more effective to use an emulator or the CPU16 background debug mode BDM for communication 3 1 1 Using an Emulator An emulator is a direct replacement for the chip that is used to evaluate both software and signals on the target boa
15. as much as possible 2 8 3 Other Sources of Information Freescale publishes two application notes on related subjects Designing for Electromagnetic Compatibility with HCMOS Microcontrollers AN1050 Transmission Line Effects in PCB Applications AN1051 EDN Magazine offers a reprint of the Designer s Guide to Electromagnetic Compatibility Refer to 6 Sources of Information for ordering information EMC consultants are probably the best source of information on this topic since they specialize in EMC and RFI problems Consultants can help troubleshoot real problems conduct seminars and provide tu torials books and software on the subject 2 9 Connecting Memory and Peripherals The MCU offers many different ways to configure memory and peripherals The user can decode the external bus interface externally or use chip selects Since it is usually more efficient to use the chip selects this tutorial does not cover signal decoding However the SIM Reference Manual SIMRM AD gives detailed explanations and examples of how to decode signals for both 8 and 16 bit memory de vices on pages 5 31 through 5 34 These examples also show how to use function code pins to deter mine which address space is being accessed The MC68HC16Z1 can generate 12 chip select signals These signals can be used to expand the sys tem A chip select signal selects and enables a particular peripheral device or memory chip for data transfer The chip sele
16. crystal oscillator It is shown in Figure 3 Its components consist of a series resistor a feedback resistor a crystal an in verter and two capacitors Rs Series resistor Rs must be large enough to appropriately limit current to the crystal and yet small enough to provide enough current to start oscillation quickly The smaller Rs the faster the oscillator will start However if Rs is too small the crystal will start up in unpredictable modes or dissipate too much power This can cause heating problems In extreme cases the crystal may even be damaged and not work properly again If Rs is too large the oscillator will start very slowly or not at all The best way to minimize start up time is to minimize the size of Rs within the guidelines of the maximum power dissipation The crystal manufacturer generally recommends a range of values to use To ensure that Rs is large enough to prevent the crystal from being overdriven observe the output frequency as a function of Vpp on the CLKOUT pin If the crystal is overdriven at start up i e the first 500 ms or so after the power is turned on the frequency will be very unstable Rf Feedback resistor Rf is used to bias the inverter between EXTAL and XTAL inside the MCU Rf affects the loop gain lower values reduce gain while higher values increase gain C1 and C2 The series combination of C1 and C2 provides the parallel load for the crystal Their val ues may be varied to trim freq
17. crystal with a temperature range of 40 to 85 degrees Celsius is ECX205 This crystal also comes in other packages Fox 813 693 0099 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc The part number for a surface mount 32 768 kHz crystal with a temperature range of 40 to 85 degrees Celsius is FSM327 This crystal also comes in other packages KDS Daishinku 913 491 6825 The part number for a surface mount 32 768 kHz crystal with a temperature range of 40 to 85 degrees Celsius is DMX 38 This crystal comes in other packages Statek 714 639 7810 The part number for a surface mount 32 768 kHz crystal that can be used at 25 degrees Celsius is CX 1VS SMI 32 768kHz For a temperature range of 40 to 85 degrees Celsius the part number is CX 1VS SMI 32 768kHz A 2 5 2 2 Grit and Grime Oscillators are quite sensitive to dirt solder flux grease and other conducting materials on the circuit board These materials can allow a very high resistance leakage path from one of the amplifier pins to either ground or the positive terminal of the power supply When the oscillator has power applied but has not started the crystal and bypass capacitors appear as DC open circuits An oscillator in a DC condition would appear as shown in Figure 4 The resistor Rd represents a high resistance leakage path somewhere in the range of 5 to 20 MQ The feedback resistor Rf is al
18. example is in the file init_res asm in the archive 16Z1_ init on the Freeware Data System org 0008 put the following code in memory after the reset vector DW 0000 The address of label INT is stored at location 0008 DW INT which is the breakpoint vector DW INT Bus Error DW INT Software Interrupt DW INT Illegal Instruction DW INT Division by Zero etc In the actual program code the following routine must be included INT code to handle the exception goes here RTI return to the code that was previously being executed 4 wech A CPU Condition Code Register The CPU condition code register contains some very important information The CCR is discussed on page 3 4 of the CPU16 Reference Manual CPU16RM AD The field that the user code must initialize is the interrupt priority level field which consists of bits 7 5 The interrupt priority level determines which interrupts are recognized and which are masked Level 7 interrupts are always recognized To allow other interrupts this field must contain a value that is lower than the interrupt priority level desired For example to allow level 6 interrupts the value must be 101 or less Out of reset the field has a value of 111 which disables all interrupts except for level 7 interrupts REES MC68HC16Z1TUT D For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 4 2 Configuring the System Integ
19. interrupt routine for PIT MC68HC16Z1TUT D For More Information On This Product Go to www freescale com Freescale Semiconductor Inc INCW 0000 X increments the first word in the RAM at RTI address 30000 INT RTI unused interrupts point here 4 3 Configuring Internal RAM The internal RAM can be mapped to any 2 Kbyte boundary in the address map but it must not overlap the module control registers or be mapped to addresses 80000 to 7FFFFF which are inaccessible to the CPU16 The RAM is in low power stop mode out of reset To initialize the RAM write the desired base address to the RAM base address and status register a write once only register and clear the STOP bit to enable the RAM If battery backup for the RAM is not used connect the Vstpy pin to ground When using the ICD16 de bugger make sure not to display any potentially uninitialized memory in the F3 and F6 windows be cause the debugger tries to read this memory and will display error messages if it is uninitialized 4 4 Configuring the Queued Serial Module The queued serial module QSM is divided into two submodules the serial communications interface SCI and the queued serial peripheral interface QSPI The following sections give basic examples of QSM configuration See the QSM Reference Manual QSMRM AD for more detailed information 4 4 1 Configuring the SCI The following example program can be assembled with IASM16 This example is in the sci
20. more detailed description of the fields in chip select option registers 2 10 5 Level Sensitive versus Edge Sensitive Interrupt Pins Interrupt pins IRQ 6 1 are level sensitive Assertion of an active low signal connected to one of these For More Information On This Product Go to www freescale com Freescale Semiconductor Inc pins is recognized as a valid interrupt request if the interrupt priority level of the pin is greater than the value of the IPL field in the condition code register CCR Once an interrupt service request is recog nized the CCR is copied onto the stack then the IPL value is changed to match the priority level of the interrupt being serviced This prevents interrupts of the same or lower priority while the service routine executes For instance if the IPL value is 3 and a level five service request is recognized the CCR is stacked then the IPL value is changed to 5 An RTI instruction at the end of the service routine nor mally terminates interrupt service RTI pops the stacked CCR and thus restores the original IPL value The IPL field can also be changed by writing to the CCR If an interrupt service routine writes a lower value to the IPL field while the request signal is still asserted the CPU recognizes a second service request IRQ7 is both edge and level sensitive Level seven interrupts cannot be masked by the IPL field When a level seven interrupt service request is recognized the current value
21. of the condition code register is pushed onto the stack and the IPL value is changed to 7 It is very important to make certain that the IRQ7 signal be negated before the level seven interrupt ser vice routine ends A new level seven interrupt will be recognized in the following cases If the IRQ7 signal negates and is then re asserted while the interrupt service routine is executing If the IRQ7 signal remains asserted through the execution of the RTI instruction that ends the ser vice routine If the IRQ7 signal is asserted and the IPL field is written during execution of the interrupt service routine This is true even when the mask is re written to 7 Provide for negation of the signal within the service routine and avoid writing to the CCR during execu tion of the level seven interrupt service routine 2 10 6 Checklist for External Interrupt Acknowledge Is the desired pin configured as an interrupt pin instead of an I O pin The interrupt pins are dual function pins Their initial configuration is determined by the state of data bus pin 9 at the release of reset After reset their configuration is determined by the port F pin assign ment register e Was the starting address of the interrupt routine written to the vector offset address The CPU must be told where the interrupt service routine begins See 4 1 2 Exceptions for a more de tailed explanation ele the IARB field in the SIMCR a unique non zero value between 1
22. or intermittent signals by means of an external circuit and clear the latch in the interrupt service routine 5 2 7 Problem The Processor Asserts HALT and Halts A double bus fault has occurred and the halt monitor previously called the double bus fault monitor is not enabled A double bus fault can occur under the following conditions 1 When bus error exception processing begins and a second bus error is detected before the first instruction of the first exception handler is executed 2 When one or more bus errors occur before the first instruction after a reset is executed 3 When a bus error occurs while the CPU is loading information from a bus error stack frame during execution of a return from exception RTE instruction MC68HC16Z1TUT D For More Information On This Product Go to www freescale com Freescale Semiconductor Inc After the double bus fault occurs the MCU drives the HALT line low and can only be restarted by a re set When the HALT line is driven low internally the double bus fault monitor will immediately cause a reset if it is enabled If the double bus fault monitor has been disabled by clearing the HME bit in the system protection control register SYPCR the MCU will remain halted indefinitely and must be reset externally 5 2 8 Problem A Chip Select Generates the Wrong Number of Wait States 1 Either DSACK1 or DSACKO has floated low These signals should be tied high via a pull up re sis
23. the registers check the block sizes and thus the number of address lines com pared Since the MCU does not look at all 24 address lines when it compares for a match two chip select circuits can respond to the same base address even though the base address reg isters contain different values Table 8 Sample Chip Select Values CS CSBARx CSORx BLKSZ CSBOOT 0003 68B0 64K CS0 0504 58FE 128K CST F800 5830 16K CS10 0400 4F3E 2K Table 9 Block Size Encodings for Chip Selects BLKSZ 2 0 Block Size Address Lines Compared 000 2 Kbyte ADDR 23 11 001 8 Kbyte ADDR 23 13 010 16 Kbyte ADDR 23 14 011 64 Kbyte ADDR 23 16 100 128 Kbyte ADDR 23 17 101 256 Kbyte ADDR 23 18 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 9 Block Size Encodings for Chip Selects BLKSZ 2 0 Block Size Address Lines Compared 110 512 Kbyte ADDR 23 19 111 1 Mbyte ADDR 23 20 In Table 8 the addresses for CSO and CS10 conflict Both will respond to the address 40000 CS0 is programmed to start at 50000 however it is programmed incorrectly It does not lie on an even bound ary of 128 Kbytes remember that 1 Kbyte 1024 bytes As shown in Table 9 only address lines 23 through 17 are compared for a block size of 128 Kbytes The address decoding process works as fol lows CSBARO 0504 base address of 5
24. 0 ccccecesseeeeeeeeeeeeeeeeeteeessaaeeneaes 15 2 7 1 2 Using LVI Devices with Multiple Power Supplies cccceeeeeeeeeseeteeeeeeeseeeseees 15 2 8 Designing for Electromagnetic Compaibiltv nesen essennennsennnernnsrnnnsrnnnnrnessrnnsenn 15 2 8 1 Reducing Power Supply Noise 15 2 8 2 Suggestions for Reducing EMISSIONS ssssseseeeseesseeeesnetnettietsinsttinssirnssrnnstnnsstnnsen nnne 18 2 8 3 Other Sources Of Information ccceeeeecceeeeeeseeeeeeeeeeeeeaeeeeeeeeeeaaeeeeeeeeesaeeeseaeeeseeeeseeeeee 19 2 9 Connecting Memory and Peripherals 19 2 9 1 Using Chip Selects to Generate DGSACK nent 19 2 9 1 1 The Relationship Between Wait States and Memory Speed sneeenseeeeneeeeen 19 2 9 2 Using Chip Select Signals to Enable Boot Memory cccceceeeeeeeeeeeeeeeeeteteeeeeneeeees 20 2 9 3 Using Chip Select Signals to Enable External Memory ssssseessseesseseressrsssrrssrresrnnss 21 2 9 3 1 How to Construct Word Memory from Two Byte Memories 21 210 Usma External Interrupts cictet eve scctecceeteua ede sve geus lev Ve S REE S EEEN cage ice d e AERA EE KENTEEN 23 2 10 1 Interrupt Priority Levels A 23 2 10 2 Interrupt Arbitration Feli eenei e R E EREE TE E E eE E ea RERNE 24 2103 MEUPE VECOS e a E E E aud AEEA E S SEA 24 2 10 4 The Interrupt Acknowledge Cycle 24 Kalb ANE 24 ZTA AULOVECIOIS zects stints heceeedl ireebeias eeeei as E E Oa ieee teem eee ts 25 2 10 5 Level Sensitive versus Edge Sensitive In
25. 00 N Alma School Road Chandler Arizona 85224 1 800 521 6274 or 1 480 768 2130 support freescale com Europe Middle East and Africa Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen Germany 44 1296 380 456 English 46 8 52200080 English 49 89 92103 559 German 33 1 69 35 48 48 French support freescale com Japan Freescale Semiconductor Japan Ltd Headquarters ARCO Tower 15F 1 8 1 Shimo Meguro Meguro ku Tokyo 153 0064 Japan 0120 191014 or 81 3 5437 9125 support japan freescale com Asia Pacific Freescale Semiconductor Hong Kong Ltd Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 800 2666 8080 support asia freescale com For Literature Requests Only Freescale Semiconductor Literature Distribution Center P O Box 5405 Denver Colorado 80217 1 800 441 2447 or 303 675 2140 Fax 303 675 2150 LDCForFreescaleSemiconductor hibbertgroup com Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty repr
26. 0000 and block size of 128K 23 20 19 16 15 12 118 7 4 3 0 5000 0000 0101 0000 0000 0000 0000 For a 128 Kbyte block size address lines 16 0 are decoded as zero As a result bits 19 16 are read as a four instead of a five and CSO responds to the address space starting at location 40000 How ever CS10 is also programmed to respond to the address space starting at location 40000 It is ac ceptable for two chip select circuits to respond to the same address space however in this case the option registers are programmed for a different number of wait states As a result the first termination signal seen will be from CSO after three wait states on any read or write access possibly before the external device is ready to respond especially if it was meant to have CS10 terminate the cycle after 12 wait states To correct the problem the values in CSBARO and or CSBAR10 must be changed If the value in CSBARO is changed to 0404 and the value in CSBAR10 is changed to a base address that does not overlap such as 0300 then 40000 is an acceptable base address for CSO since it is an exact mul tiple of 128 Kbytes That is 1K 400 128K 20000 40000 20000 2 an integer Therefore 40000 is on a 128 Kbyte boundary 5 2 9 Problem A Chip Select Does Not Assert Ensure that a valid base address is written to the chip select base address register Because the CPU16 does not recognize addresses 80000 to F7FFFF base addres
27. 1 Using Data Bus Pins to Configure the MCU and 2 3 Pins that Need Pull Up Resistors 2 A capacitor on RESET can also prevent the device from coming out of reset Do not put any ca pacitors on RESET See Sections 2 1 and 2 3 3 MODCLK is pulled high at the release of RESET and the VCO is not locking Check the compo nents in the crystal circuit to ensure that they are correct Check the layout to ensure that the board is clean and that there are no noisy signals nearby to affect operation of the oscillator and make sure that power is applied to Vppsyn Also make sure that the crystal frequency is within specifications If all else fails change crystals See 2 5 Clock Circuitry 4 MODCLK is pulled low at the release of RESET and there is no external clock signal Make sure that there is a signal going into EXTAL See 2 5 Clock Circuitry 5 2 2 Problem Device Resets Every 16 ms 1 The software watchdog is enabled but is not being serviced by the program When the watchdog is enabled the program must write a sequence to the software service register to prevent the watchdog from timing out and resetting the MCU The software watchdog is enabled out of reset and the program must disable it by clearing the SWE bit in the SYPCR register Note that this is a write once only register 2 If the code does disable the watchdog but the device is still resetting every 16 ms then the code is probably not being executed Either the memory is no
28. ACK signal or the chip select logic must generate the DSACK signal internally If an au tovector is used an external device can assert the AVEC signal or an AVEC signal can be generated by the chip select logic Since normal bus cycles occur in user or supervisor space but an IACK cycle occurs in CPU space the same chip select circuit cannot be used to terminate both an IACK cycle and anormal bus cycle 2 10 4 1 User Vectors Once an interrupting device has placed a user vector number on the external data bus in response to an IACK signal from the MCU either the device must terminate the IACK cycle with DSACK or the chip select logic must generate DSACK internally When the bus cycle has been terminated the vector num ber is left shifted once multiplied by 2 to form the 16 bit vector address The CPU then saves the cur rent context loads the 16 bit vector into the PC and begins to execute the service routine at that address An example is shown in Figure 15 Chip select 1 is configured for interrupt acknowledge and automatic generation of the DSACK signal It is connected to the ACK pin of the peripheral Because the proces sor drives F FFFFx onto the address bus and drives the function code pins to indicate CPU space dur ing an IACK cycle the chip select base address register must be programmed to FFFX When the CPU recognizes an interrupt and initiates an IACK cycle CS1 is asserted In response the peripheral drives
29. DR DATA ADDR ROM 32K X 16 CE 332TUT EXT MEM CONN 3 Figure 14 Configuring 16 Bit Memory with 8 Bit RAMs Separate Read and Write Enables 2 10 Using External Interrupts The MCU has seven external interrupt lines IRQ 7 1 These are active low signals that cause the pro cessor to jump to a special routine and then return to the main code The following paragraphs cover the basic elements of servicing external interrupt service requests Refer to 4 1 2 Exceptions for more detail Chapter 6 of the SIM Reference Manual SIMRM AD has an in depth explanation of how to use external interrupts 2 10 1 Interrupt Priority Levels An interrupt can be recognized on one of seven priority levels These levels correspond to the numeric values of the external interrupt request lines Level one IRQ1 has the lowest priority level seven IRQ7 has the highest priority level Levels one through six can be masked by the interrupt priority level IPL field contained in bits 7 through 5 of the condition code register CCR The level specified in the IPL field and all levels below it are masked and are not recognized by the CPU Level 7 is the only ex ception to this rule it cannot be masked Out of reset the IPL field is set to level 7 Thus levels 1 through 6 will not be recognized unless the IPL field is re written to a lower value The priority mask value can be changed by writing a new value into the appropriate bits of the CCR EXAMPLE To
30. E INHIBIT INHIBIT DEVICE A S DEVICE B 332TUT DUAL RESET CONN Figure 9 Using LVI Devices with Multiple Power Supplies 2 8 Designing for Electromagnetic Compatibility Because of the fast clock speed and relatively short rise and fall times of MCU signals the designer must consider electromagnetic compatibility EMC issues All high speed digital devices radiate noise and if FCC compliance is required the designer must do everything possible to limit emissions from the MCU Use of a four layer board is probably the best single option the designer has Although a two layer board will work a multilayer PCB is much more effective at both protecting the MCU from emissions and reducing emissions from the MCU EMC compatibility is a complex topic and this tutorial can present only a brief overview of EMC design techniques 2 8 1 Reducing Power Supply Noise The MCU is very susceptible to noise created by large or rapid fluctuations in current through a partic ular power supply pin The power supply pins are divided up into Vppe Vsse and Vpp Vsg The Vppe Vsse pins power the external drivers and pins while the Vpp Vss pins power the internal peripherals and core of the MCU It is very important to keep the Vppi VYss pins free of noise as the CPU is generally For More Information On This Product Go to www freescale com Freescale Semiconductor Inc more sensitive to power supply noise than the port drivers
31. Figure 1 Circuitry to Drive Data Bus Pins During RESET Assertion There are several alternative methods of driving data bus pins low during reset The easiest methods are to connect a resistor in series with a diode from the data bus pin to the RESET line or to connect a transistor as shown in Figure 2 When using a bipolar transistor a base current limiting resistor is re quired When using field effect transistor a base limiting resistor is not needed However the best meth od is to use the configuration shown in Figure 1 DATA PIN mv DATA PIN e 1N4148 RESET RESET 332TUT DAT RESET HOLD Figure 2 Alternate Methods of Conditioning Data Bus Pins 2 2 Choosing Memory Width One decision that must be made early in the design is the width of memory to be used Systems with 8 bit wide memory 16 bit wide memory or a combination of the two can be implemented using only the For More Information On This Product Go to www freescale com Freescale Semiconductor Inc onboard chip select lines Using 8 bit memory simplifies the design and reduces cost but with a significant performance penalty This penalty is not fixed but depends on the amount of time that the processor spends accessing the 8 bit memory as opposed to accessing other external memory or performing internal accesses or oper ations Moving from 16 bit to 8 bit program memory may reduce CPU performance by 40 when exe cuting simple CPU instructions that o
32. Freescale Semiconductor Inc LDE 0005 counter that will count to end of message The next three commands check to see if the transmit data register is empty by looking at the TDRE bit in the SCI status register SCSR If the TDRE bit is zero then there is data in register TDR that has not yet been sent to the transmit serial shifter If the TDRE bit is one then the transfer has occurred and a new character may be written to register TDR Thus this sequence of code loops until the TDRE bit is one LOOP LDAB 0 X jist char in accumulator B CHAR LDAA SCSR see if TDRE bit in SCI Status Register is ANDA 01 set BEQ CHAR wait until it is LDAA SCSR ANDA SFE STAA SCSR clear TDRE bit CLRA STD SCDR store char to be printed in data register AIX 1 point to next char SUBE 01 BNE OOP loop to print next char FINISH BRA FINISH stay here when done INT RTI unused exceptions point here MESSAGE FCB 12345 712345 will be printed 4 4 2 Configuring the QSPI The QSPI uses a synchronous serial bus to communicate with external peripherals and other MCUs The QSPI serial protocol is compatible with the serial peripheral interface SPI on the M68HC11 and M68HC05 families of MCUs The module also has a queue programmable queue pointers that allow up to 16 automatic transfers and a wrap around mode that allows continuous transfers to and from the queue wit
33. Freescale Semiconductor Order this document by MC68HC16Z1TUT D An Introduction to the MC68HC1621 By Sharon Darley and Charles Melear 1 Introduction Use of microcontrollers MCUs presents new challenges as clock speeds increase and bus structures become more complex In particular designing a system with Freescale s 16 bit MC68HC16Z1 can be challenging for those used to the 8 bit world The MC68HC16Z1 is a member of the Freescale modular microcontroller family a series of 16 bit and 32 bit devices constructed from standard on chip peripheral modules that communicate by means of a standard intermodule bus The MC68HC16Z1 is a sophisticated single chip control system that incor porates a 16 bit CPU module CPU16 a system integration module SIM a general purpose timer GPT a queued serial module QSM an 8 channel analog to digital converter ADC and a 1 Kbyte standby RAM SRAM The MCU thus provides a designer with many options ranging from reset con figuration to interrupt generation that must be considered during the design phase This tutorial is intended to assist development and reduce debug time for first time designers of MC68HC16Z1 systems It covers four major topics designing the hardware establishing communica tion initializing the MCU and troubleshooting Each topic is discussed in a separate section that in cludes practical examples Along with two other Freescale documentsAn Introduction to the HC16 for HC11
34. ILR register determine the priority levels of QSPI and SCI interrupts respectively If the fields are set to the same level the QSPI takes priority 2 INTV 7 0 in the QIVR register determines the interrupt vector number For the QSPI the least significant bit is read as a one and for the SCI the least significant bit is read as a zero 3 IARB in the QMCR register determines precedence if the QSM and another module simulta neously make an interrupt service request of the same priority This field must be initialized to a unique non zero value if interrupts are enabled 4 IPL in the CPU condition code register determines the priority level at which interrupts are rec ognized In order for QSM interrupts to be recognized this field must be given a value that is lower than the interrupt priority level specified in the QILR register 5 The interrupt vector tells the processor where to find the interrupt service routine Store the start ing address of the service routine in the interrupt vector table at the appropriate vector offset ad dress The vector offset address is equal to interrupt vector number X 2 4 5 Configuring the General Purpose Timer The general purpose timer GPT is a software interrupt driven timer that is very similar to the timer MC68HC16Z1TUT D For More Information On This Product Go to www freescale com Freescale Semiconductor Inc used extensively on the M68HC11 series of microcontrollers Because the G
35. PT uses design rules for the M68300 family the GPT runs four times faster on the M68300 M68HC16 families than it does on the M68HC11 family While the GPT does reside on the intermodule bus it does not have a self con tained arithmetic logic unit or RISC like microengine like the time processor unit on other modular MCUs with specialized instruction sets The GPT functions are briefly described below For a more de tailed explanation refer to the GPT Reference Manual GPTRM AD Input Capture Pins IC 1 3 Each of these pins is associated with a single input capture function and has a dedicated 16 bit capture register to hold the captured counter value These pins can also be con figured for general purpose I O Output Compare Pins OC 1 4 Each of these pins has a dedicated 16 bit compare register and a 16 bit comparator Pins OC2 OC3 and OC4 are associated with a specific output compare function whereas the OC function can affect the output of any combination of output compare pins Automatic preprogrammed pin actions occur on a successful match The OC1 pin can alternately be used to output the clock selected for the timer counter register TCNT Also any of the pins can be used for general purpose I O Pulse Accumulator Input Pin PAI The pulse accumulator counter PACNT is an 8 bit read write up counter register that can operate in an external event counting or gated time accumulation mode The user software can write the numb
36. SET low for 512 clock cycles This cycle repeats until RESET is finally perceived to be at a logic 1 Figure 8 shows the waveform that is produced on the RESET line when the pull up resistor is too large and pull up current is inadequate For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 5 VOLTS INDETERMINATE LOGIC LEVEL 10 OR 14 SYSTEM CLOCKS 512 SYSTEM CLOCKS 0 VOLTS 332TUT RESET LEVEL TIM Figure 8 RESET Waveform Caused by Weak Pull Up If the PLL circuit is not used and an external clock at the desired frequency of the system clock is ap plied to EXTAL prior to start up the start up sequence is the same except that the MCU recognizes the clock immediately instead of waiting for the PLL to lock 2 7 Power Supply Always connect all power and ground pins to power sources Internal power buses only serve about 8 10 pins each The power and ground pins are usually not connected together within the device If any power pin is left floating the pins served by the floating power pin can receive power from internal cir cuitry such as internal protection diodes However the current path will usually have several diode drops resulting in a low output high voltage about 3 volts on associated output pins 2 7 1 Low Voltage Inhibit Devices A low voltage inhibit LVI device also referred to as a reset supervisor circuit protects the MCU by keepi
37. U16RM AD for detailed discussion of exception processing and a complete list of exception vectors The first four words in the exception vector table are used for the initial ZK SK and PK values the initial stack pointer and program counter values and the initial IZ register value These are referred to collec tively as the reset vector because the CPU16 loads them during reset exception processing Unlike oth er vectors the reset vector is mapped to program space to facilitate fetching the values The reset vector is always located at address 000000 All the other exception vectors occupy one word in the table and are located in data space These vec tors point to the beginning of software routines that handle particular exceptions All the vectors in the exception vector table must be initialized The reset vector is generally fetched from external ROM Cor rect initial values for the reset vector must be written to addresses 000000 through 000006 in order for the system to begin program execution Following is an example of how the exception vector table works An external device asserts IRQ7 and the CPU acknowledges the interrupt service request The external device must either provide a user vector number on the data bus and then terminate the bus cycle by asserting DSACK or it must assert AVEC and allow the processor to automatically supply the level 7 autovector number which is 17 As suming the external device asserts AVEC v
38. Users AN461 and Transporting M68HC 11 Code to M68HC 16 Devices M68HC16PN01 D this tutorial provides a hands on supplement to the MC68HC 1621 User s Manual which presents a comprehensive overview of the MCU For more information on device operation electrical characteristics registers and control bit def inition refer to the appropriate sections of the manual For more detailed information refer to the refer ence manual for each of the on chip peripheral modules See 6 Sources of Information for a complete list of MC68HC16Z1 technical literature The software examples included in the tutorial and a sample system schematic are available through Freeware Data Systems The files are in the mcu16 directory in an archived file called 16Z1init arc The PKXARC utility is used to de archive these files PKXARC itself is contained in a self expanding file entitled PKX35A35 exe located in the Freeware IBM directory Also in the mcu16 directory are quikst20 arc and 5band_sa exe The first file is an archive of several example initialization files and the second is an archive of files to make a five band frequency analyzer See 6 2 Freeware Data Sys tems for a phone number for modem access and addresses for internet access Freescale Semiconductor Inc 2004 All rights reserved ie O O Z freescale semiconductor Freescale Semicanductor Inc Section Page L INTRODUCTION E dee EENS Deeg fev enced E A E
39. When designing a multilayer board simply route the power and ground pins directly to the power and ground planes when designing a two layer board however it is best to isolate the power bus that serves the core of the chip from the power bus that serves the port drivers Figure 10 shows groups of pins that are powered by the same supply pins Although only the 132 pin plastic surface mount package is shown the groups for the 144 pin package are the same In each group the Vppe and Vege pins that power a particular group are shown in bold face type The Vpp and Vss pins are labeled as such EXTAL and XTAL are powered only by Vppsyn When control of noise on the power buses is important it is possible to isolate sections of the chip that are particularly noisy The data and address buses are particularly noisy because they continually change state and the same can be true of serial ports and timer pins The amount of noise generated by a particular pin is dependent upon the load being driven and the switching frequency A designer who knows which power and ground connections serve particular pins can shield other signal conduc tors from these noisy lines ei MC68HC16Z1TUT D For More Information On This Product Go to www freescale com Freescale Semiconductor Inc ne Na ar Q CO oO st ei 3 wo Ri Oli Si B a ES SSS ke CH oO Zo ER co LO oS Q CO IN GO N N N HNE NDD Sne EE EE SB BBB O O OD BOO Laags Bow aazoat aqaaaqamMmGaag
40. _init asm file in the archive 16Z1_ init on the Freeware Data System The program prints a five character mes sage to the screen Do the following before running this program 1 Connect an RS 232 cable from the PC serial port to the target board 2 When using ICD16 set the serial communications protocol for the COM port being used 9600 baud no parity eight data bits and one stop bit For example when using COM 2 type in the command serial 2 9600 n 8 1 When using ICD16 enable the serial communications by typing serialon 3 4 Load and run the program SCI INITIALIZATION This program initializes the SCI and prints the message 12345 to a dumb terminal INCLUDE EQUATES ASM EQUates for common register addresses INCLUDE INIT_RES ASM initialize reset vector INCLUDE INIT_INT ASM initialize interrupt vectors ORG 200 begin program at 200 immediately after the exception table INIT_SIM LDAB 0F point to bank SF for internal register addressing BEK CLRB TBXK LDAA S7F STAA SYNCR increase clock speed CLR SYPCR disable software watchdog INIT_SCI LDD 0037 STD SCCRO set the SCI baud rate to 9600 LDD S000C STD SCCR1 enable the receiver and transmitter PRINT LDX MESSAGE load the address of the message to be printed into address register X For More Information On This Product Go to www freescale com
41. above in 4 6 Configuring the An alog to Digital Converter Connect an input signal to the ADO pin Make sure that the input is within the range of Vay and Vo This example is in the file adc_init asm in the archive 16Z1_init on the Freeware Data System INCLUDE EQUATES ASM register equates INCLUDE INIT_RES ASM initialize reset vector INCLUDE INIT_INT ASM initialize interrupt vectors ORG 200 CLRE INIT_SIM LDAB SOF set K fields to SF to point to internal regs TBEK LDAA 7F STAA SYNCR increase clock speed CLR SYPCR disable software watchdog INIT_ADC LDD 0000 STD ADCMCR enable ADC LDD 0043 STS field 8 A D clocks STD ADCTLO 8 bit sample period SYS CLOCK 8 START_ADC LDD 0000 STD ADCTL1 Single 4 conversion single channel ADO writing to the ADCTL1 reg starts conversion LDAA 80 SEE_IF_DONE BITA ADSTAT check for the Sequence Complete Flag BEQ SEE_IF_DONE wait until conversion is complete LDE RJURRO read result in lower byte of register BRA START_ADC 7go get another sample INT RTI unused interrupts point here 5 Troubleshooting Because of the complexity of the MCU there are a considerable number of potential fatal flaws that can cause a prototype application to either not operate from power up or to fail soon after This section covers common problems causes and fixes This is not an
42. agnose by conventional means such as probing the input and output with an oscilloscope The capacitance of a scope probe can be large compared to the effective capacitance of the particular node of the oscillator that is probed This added capacitance can cause an errant oscillator to move to a more stable region where it appears to work correctly or on the other hand a working oscillator could be moved into a region of no oscillation at all Therefore it is important to measure oscillator performance indirectly This can be done through the CLKOUT pin which is a buffered form of the internal system clock Monitoring the CLKOUT pin with an oscilloscope does not affect the oscillator and provides an accurate representation of oscillator prob lems If the MCU is running off the internal PLL and a 32 768 kHz crystal the CLKOUT frequency should be 8 389 MHz at the release of reset The CLKOUT signal is likely to do one of three things when power is turned on It will either remain at a constant DC level jump quickly to the proper frequency or first jump to the desired frequency then enter a very high frequency metastable state and then jump back to the fundamental frequency With a small amount of practice these metastable states which last for approximately 100 to 500 ms can be easily detected on an oscilloscope In the third case the MCU generally takes almost a second to reach steady state which provides plenty of time for it to attempt operatio
43. al purpose I O port F Pull up lines that are to be used for interrupt service to 5 V via 10 KQ resistors hold DATAQ low during reset reassign the pins to be used for interrupt requests by writing to the port F pin assignment register then change the IPL mask val ue to enable maskable interrupts yan SSS SSS ee ee MC68HC16Z1TUT D For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 2 Hold DATAQ high during reset as described in 2 1 Using Data Bus Pins to Configure the MCU to assign all these pins for use as interrupt request inputs Pull up all lines that are to be used for interrupt service including IRQ7 to 5 V via 10 KQ resistors hold DATAQ high during reset re assign the pins that are not used for interrupt requests by writing to the port F pin assignment register then change the IPL mask value to enable maskable interrupts Remember that the level 7 interrupt is non maskable when configured as an interrupt line IRQ7 is always enabled The only way to disable external IRQ7 interrupts is to assign the IRQ7 pin to I O func tion via the port F pin assignment register DSACK 0 1 During bus transfers external devices can drive these signals to indicate port width These signals are active even if the bus transfer is to or from a peripheral that is using one of the chip selects to terminate the bus cycle Putting 10 KQ pull ups on these two pins prevents accidental asser tio
44. atform board PFB a plug in daughtercard called the personality board MPB and the M68ICD16 debugger The PFB has memory sockets logic analyzer connections and jumpers which allow the user to select the state of critical boot up signals such as the data bus pins and MOD CLK The MPB contains the MCU and crystal The system is very versatile because there are MPBs for a number of different devices and several MPBs can be used with the same PFB 3 2 3 The MMDS1632 The MMDS1632 is an emulator that provides high speed real time hardware and software emulation for the target system It replaces the MCU completely It is designed to work with a package specific personality board PPB and the MPB Both of these boards must be purchased separately The MPB is not necessary if the user has a target board already built In this case a connection from the MMDS1632 can be soldered or socketed to the connections intended for the MCU Contact a local Freescale sales office for more information on the MMDS1632 4 System Initialization 4 1 Configuring the Central Processing Unit For a detailed overview of the CPU16 refer to An Introduction to the HC16 for HC11 Users Transport ing M68HC11 Code to M68HC16 Devices CPU16 Reference Manual and Using M68HC 16 Digital Sig nal Processing to Build an Audio Frequency Analyzer These documents contain in depth discussion of For More Information On This Product Go to www freescale com Freescale Semiconduc
45. before system initialization See 2 1 Using Data Bus Pins to Configure the MCU 3 An interrupt is received and the interrupt vectors have not been initialized Make sure that the interrupt vectors are initialized See 4 1 3 2 Initializing Exception Vectors Other Than Reset 4 The BR or BGACK pin has floated low and the CPU has relinquished control of the bus Configure these pins for chip select operation out of reset by pulling DATA1 high during reset or put pull up resistors on these pins 5 Some of the pins are being powered up before Vpp If the MCU is connected to another system with a separate power supply use an LVI device to prevent the system with the faster power sup ply from driving logic one levels before the system with the slower power supply has become op erational If this happens the driven pins on the device with the slow supply will momentarily have a higher voltage than the Vpp pin This condition can cause the input protection diodes to become momentarily forward biased and cause significant current injection into the device sub strate which will probably improperly charge or discharge some of the internal nodes of the MCU This action is completely random and it is impossible to predict what will happen when significant injection occurs Usually the MCU will not function at all and will display undefined states For example the RESET HALT BERR BR and FREEZE signals may be asserted but the device may fail to fet
46. bits 7 4 in the GPT interrupt configuration register ICR For example choosing a base vector number of 81 would assign interrupt vector 80 to input capture 1 interrupt vector 82 to input capture 2 interrupt vector 83 to input capture 3 and so on through assignment of interrupt vector 8B to pulse accumulator input flag For example if output compare 1 is being set up to request interrupt service the interrupt vector is 84 The vector address is 2 84 108 Thus the starting address of the interrupt routine must be stored in location 108 2 Store an interrupt priority level for the GPT in bits 10 8 of the ICR This value determines the priority of GPT interrupt service requests The value must be a number between 1 and 7 level 7 has the highest priority and level 1 has the lowest The value stored in the IPL field in the CPU condition code register determines whether an interrupt request is rec ognized The value in the IPL field must be lower than the GPT interrupt priority level in order for the GPT to interrupt the CPU unless the interrupt level is seven in which case it cannot be masked 3 If desired specify which interrupt source within the GPT has the highest priority by writing to bits 15 12 of the ICR This value determines which interrupt source within the GPT has the highest priority As Table 7 1 on page 7 3 in the GPT Reference Manual GPTRM AD shows each interrupt source within the GPT is pre as
47. cceisctesvscebeactedecetd reve ceed beans te aeaaaee hasaan aaea ara aaa eed 44 4 6 Configuring the Analog to Digital Converter 46 4 6 1 ADC Initialization Exa mpl esinti sneinen ea aaea aaa aa aana aaa Eea ae h feaa 47 5 TROUDICSNOOUING scaron a AA T E A 47 5A Critical Signals to CHECK EE 47 5 2 Common Problems and Solutions ccccccececcceeceeeeeeeeeeeeeeeeaeeeseeeeecaeeseeneeescaeeeseeeeseeeseeaeeees 48 5 2 1 Problem Device Stays in Heset 48 5 2 2 Problem Device Resets Every 16pme ececceceeeeeneeeeeeeeneeeeeeeeaeeeeeeeaaeeeeeeeaeeeeeseaaes 48 5 2 3 Problem CLKOUT Frequency is Incorrect cc ccceceeeeeeeeeceeeeeeeeaeeseeeeeeeaaeseeeeeeeseaeeneaes 48 5 2 4 Problem System Crashes after Fetching Reset Vector sssseeseeesseeesseeesreerrresrreesrresens 49 5 2 5 Problem Debug System Cannot Enter DUDM 50 5 2 6 Problem The Processor Takes a Spurious Interrupt Exception 50 5 2 7 Problem The Processor Asserts HALT and Hate 50 5 2 8 Problem A Chip Select Generates the Wrong Number of Wait Giates 51 5 2 9 Problem A Chip Select Does Not Asset 52 5 3 Problem ADC Results are Inaccurate eeeeeceeeeeeeeneeeeeeeeeeeaaeeeeeeeesaaaeeeeneeesaaeeteaeeeseaeeeeaaeeee 52 6 Sources Of INFOFMAUON ce ic eee edd EE 53 Gil Technical Literature sai acai caccesapugideg SES E T EEA EA ERT E EERSTEN EEN 53 6 1 lUsers Mamer ege 53 6 1 2 Reference Manuals 2002 ccccccecesecceeeeeeeeeeeeeeeeeneeeeeessaeeeeeeesaneeeseeesaneee
48. ch opcodes See 2 7 Power Supply For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 5 2 5 Problem Debug System Cannot Enter BDM 1 BKPT is not held low at the release of RESET Holding BKPT low at the release of RESET en ables BDM and driving it low after reset causes the processor to enter BDM The debugger should take care of this 2 The memory is uninitialized and the processor is trying to access bad addresses In this case most debuggers should drive BERR to terminate the bus cycle If the debugger does not do this either write valid addresses to the reset vectors or if this is not possible manually pulse BERR low to terminate a hung bus cycle 5 2 6 Problem The Processor Takes a Spurious Interrupt Exception 1 The interrupt arbitration IARB field for the module requesting interrupt service is not a unique non zero value Each internal module has its own IARB field External interrupts use the IARB field in the SIMCR interrupts 2 There are noise spikes on an IRQ line Use pull up resistors on the IRQ lines 3 A square wave is used to generate external interrupts and the source of the interrupt is going away before the interrupt is acknowledged 4 The program code is disabling an internal module or is arbitrarily clearing interrupt enable bits for an internal module before the interrupt is acknowledged Instead of arbitrarily clearing the enable bits first mask out t
49. configuration is shown in Figure 12 To use a 16 bit memory connect the memory data lines to MCU data bus DATA 15 0 Connect address line ADDR1 from the MCU to AO of the memory MCU ADDR 16 0 ADDR 13 0 l ce Sannin CCG ADDIE DATA 15 0 DATA ADDR DATA ADDR ROM 32K X 16 CE ROM ENABLE 332TUT EXT MEM CONN 1 Figure 12 Using Chip Select Signals to Enable 8 Bit RAM 2 9 3 1 How to Construct Word Memory from Two Byte Memories For chip select signals other than CSBOOT forming word memory that is byte accessible from two For More Information On This Product Go to www freescale com Freescale Semiconductor Inc byte wide devices is simple Use a separate chip select pin for each device and configure chip select logic to decode the upper and lower bytes respectively Each of the chip select circuits must be config ured as a 16 bit port even though only eight bits of memory are being accessed This allows both byte and word writes if both memories were connected to the same chip select line byte writes would corrupt the adjacent byte This function can also be implemented in external logic by gating a single chip select line with the MCU ADDRO line to select upper and lower bytes For ROM memory a single chip select can be used to enable both byte wide ROMs as the MCU uses only the required byte on the data bus during a byte read and ignores the remaining byte Figure 13 illustrates how to connect two 8 bit memori
50. ct circuits can also be programmed to generate data transfer and size acknowl edge DSACK interrupt acknowledge IACK and autovector AVEC signals 2 9 1 Using Chip Selects to Generate DSACK Chip select circuits can be configured to wait for external data and size acknowledge signals on the DSACK1 and DSACKO lines or to generate internal DSACK signals A circuit can generate an internal DSACK signal even if the pin is configured for discrete output or alternate function The chip select logic can wait for a certain number of clock states before generating DSACK These states are called wait states Wait states are inserted after state 3 of a read or write bus cycle A normal bus cycle lasts three clock cycles plus the number of wait clock cycles The chip select logic can insert a maximum of 13 wait states 2 9 1 1 The Relationship Between Wait States and Memory Speed Memory speed and the number of wait states necessary are related by the following equations Address access time 2 5 WS A tcyc min tCHAV max S DICL min Chip select access time MCU read cycle 2 WS X tcyC min teLsa max DICL min Chip select access time MCU write cycle 2 WS X teycimin tcLsa max tcLSN min In the equations WS is the number of wait states programmed in the DSACK field For fast termination mode WS 1 for zero wait states WS 0 for one wait state WS 1 etc Also it is assumed that chip select asser
51. ction Pin Left High Alternate Function Pin Pulled Low DATAO CSBOOT is 16 Bit Port CSBOOT is 8 Bit Port CSO BR DATA1 S1 BG 2 BGACK CS3 FCO DATA2 S4 FC1 S5 FC2 DATA3 S6 ADDR19 DATA4 CS 7 6 ADDR 20 19 DATA5 CS 8 6 ADDR 21 19 DATA6 CS 9 6 ADDR 22 19 DATA7 CS 10 6 ADDR 23 19 DATA8 DSACKO DSACK1 AVEC DS AS SIZE PORTE 1 0 pins DATA9 IRQ 7 1 MODCLK PORTF 1 0 pins DATA11 Slave Mode Disabled Slave Mode Enabled MODCLK VCO System Clock EXTAL System Clock BKPT Background Mode Disabled Background Mode Enabled Notes 1 Slave mode is not a supported mode it is used for factory testing The slave mode must not be used in a cus tomer application As an example Table 1 shows that the state of data bus pin 0 DATAO during reset determines whether CSBOOT operates as a 16 bit chip select or as an 8 bit chip select Likewise data bus pin 1 DATA1 determines whether the CSO BR CS1 BG and CS2 BGACK pins function as chip select lines or as bus control signals After reset software can make other selections for these pins by writing to the appro priate pin assignment register A simple method of pulling a data bus pin high is to connect a 10 KQ resistor between it and the 5 volt supply Although putting a resistor on a data bus pin degrades performance at higher frequencies many designers use resistive pull ups without significant side effects The preferred method of driving data bus pins during reset is by means of an acti
52. ction of current into this trace tends to make the os cillator unstable 2 5 2 4 XFC and Vppsyn Noise on the XFC Vppsyn and Vss pins causes frequency shifts in CLKOUT The XFC filter capacitor and the Vppsyn bypass capacitors should be kept as close to the XFC and Vppsyn pins as possible with no digital logic coupling to either XFC or Vppsyn The ground for the Vppsyn bypass capacitors should be tied directly to the Vss ground plane If possible route Vppsyn and Vgg as separate supply runs or planes Vppsyn May require an inductive or resistive filter to control supply noise A Vopsyn resistive filter would consist of a 100 to 500 Q resistor from Vpp to Vppsyn and a 0 1 uF by pass capacitor from Vppsyn to Vase The proper values for the resistor and capacitor can be determined by examining the frequency of the Vppsyn noise The RC time constant needs to be large enough to filter the supply noise An inductive filter would replace the resistor with an inductor The low pass filter requires an external low leakage capacitor typically 0 1 uF with an insulation resis tance specification as high as practical The main criterion is that the capacitor be low leakage because leakage affects frequency stability and accuracy Do not use a tantalum capacitor Although the S M Reference Manual SIMRM AD recommends an insulation resistance of 30 000 MQ this value may not be necessary in all applications For most consumer room temperature applicatio
53. cussed in detail in 4 1 3 1 Initializing the Reset Vector 3 2 Communicating with Freescale Boards Third party vendors sell many types of development tools to help establish communication with the MCU These tools are described in the Freescale Microcontroller Development Tools Directory Howev er this tutorial focuses only on Freescale evaluation boards 3 2 1 The M68HC16Z1EVB The M68HC16Z1EVB is an evaluation board that consists of a platform board with the processor held in place by a socket The board has logic analyzer connectors and sockets for external memory It also has a built in background debug mode BDM connector for use with a debugger The necessary logic is already on the board so the user can use a standard 25 pin connector cable and does not need an ICD16 cable with the 10 pin connector To run the board as a stand alone system and not use BDM simply remove the PAL U5 that is sock eted onto the EVB Then change jumpers J1 and J4 from the pseudo ROM position to the EPROM po sition On some older boards the PAL may be soldered to the EVB In this case configure the PAL so that its inputs appear as if they are connected to the PC Connect the following pins to ground and 5 volts as shown ground DB25 pins 6 8 21 PAL pins 6 10 11 5 volts DB25 pins 4 7 13 PAL pins 4 9 20 3 2 2 The M68MEVB1632 The M68MEVB1632 is a newer and more sophisticated development board than the M68HC16Z1EVB It consists of a pl
54. d be separated and isolated from Vpp with a low pass filter Any supply noise present on Vopsyn will translate into shifts in the system clock generated from the PLL Always supply power to Vppsyn even when using an external oscillator and bypassing the internal PLL 2 8 2 Suggestions for Reducing Emissions In general follow standard design practices for EMC A list of techniques that are often used in board design follows These techniques are guidelines for good design not strict rules and are not specific to designs that incorporate the MC68HC16Z1 e Minimize the number of devices on the board Capacitive coupling tends to occur around the holes that connect a particular layer of the board to the power and ground planes e Use a canned oscillator instead of a crystal to reduce emissions from the oscillator If a crystal circuit must be used locate it as centrally as possible e Use a four layer PCB As a general rule a multilayer board is at least 10 times better than a two layer board for both emissions and immunity To reduce emissions even further enclose the signal traces between the power and ground planes because the added capacitance between the signal trace and ground results in a lower characteristic impedance e Plot thick layout lines with the layout program then cut the actual traces on the board thin Ifa trace that conducts a high frequency signal must be routed on the surface of the PCB route ground traces parallel to
55. d terminates the bus cycle or it specifies that the external device must provide the DSACK signal by driving the external DSACK pins Assertion of the external DSACK pins will terminate a bus cycle even if the DSACK field is programmed for a certain number of wait states If a chip select circuit is used to provide an autovector fast termination is automatically selected and the DSACK field is not used For more information on how to determine the number of wait states needed see 2 9 1 Using Chip Selects to Generate DSACK F SPACE This field indicates the address space of the access To access memory select supervisor or supervisor user space For IACK cycles select CPU space G IPL If the chip select circuit is used to provide an IACK signal or AVEC the IPL field indi cates the interrupt priority level selected H AVEC This field determines whether a chip select circuit generates an autovector in re sponse to an IACK initiated by the assertion of an IRQ pin For normal bus cycles this field is not used If a chip select circuit is to be used to generate an IACK signal program this field to zero to disable autovector generation If a chip select is to be used to generate an autovector program this field to one 4 2 9 General Purpose I O Ports Certain SIM pins can be configured as general purpose UO ports when not used for other purposes Port E pins share function with bus control signals port F pins share
56. e internal module will then automatically terminate the IACK cycle with DSACK and provide the CPU with the vector number as specified by its interrupt configuration register One way to use autovectors is to tie the AVEC pin to ground This effectively generates an external AVEC signal only in response to all IACK cycles caused by external interrupt service requests If it is not desirable for all external interrupts to autovector specific external devices can assert AVEC in re sponse to an IACK cycle However in this case it is usually easier to set up a chip select circuit to pro vide the AVEC signal internally Perform the following steps to set up a chip select circuit to generate the AVEC signal 1 Configure the chip select pin for any of its available functions in the pin assignment register 2 Program the appropriate base address register to FFF8 or higher 3 Select the following fields in the appropriate option register A MODE Bit select asynchronous mode 0 B BYTE Field select assertion for both bytes 11 C R W Field select assertion for both reads and writes 11 D STRB Bit select synchronization with AS 0 E DSACK Field select number of wait states user specified F SPACE Field select CPU space assertion 00 G IPL Field select interrupt priority level user specified H AVEC Bit enable AVEC generation 1 See 4 2 Configuring the System Integration Module for a
57. ector number 17 is automatically supplied to the CPU16 The CPU16 multiplies the vector number by two to calculate the vector address which in this case is 2E The CPU reads address 2E and uses the 16 bit number it contains as the starting address of the interrupt service routine It does not use the PK register when jumping to exception routines except in the case of the reset vector All other exception handlers must be located within bank 0 or vectors must point to a jump table Table 6 Exception Vector Table Vector Number Vector Offset Assignment Hexadecimal Hexadecimal 0 0 Reset Initial ZK SK and PK 1 2 Reset Initial Program Counter 2 4 Reset Initial Stack Pointer 3 6 Reset Initial IZ Direct Page 8 8 10 Various Errors and Exceptions 9 E 12 1C Unassigned Reserved F 1E Uninitialized Interrupt 10 20 Unassigned Reserved 11 22 Level 1 Interrupt Autovector 12 24 Level 2 Interrupt Autovector 13 26 Level 3 Interrupt Autovector 14 28 Level 4 Interrupt Autovector 15 2A Level 5 Interrupt Autovector 16 2C Level 6 Interrupt Autovector 17 2E Level 7 Interrupt Autovector 18 30 Spurious Interrupt 19 37 32 6E Unassigned Reserved 38 FF 70 1FE User Defined Interrupts For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 4 1 3 1 Initializing the Reset Vector Immediately after the release of RESET an i
58. eeenseeeseeeseneeeeeenennees 53 6 1 3 Application er 53 6 1 4 Development Tools and Software cccccccceeeeeeeeeeceeeeeeeeeeeceaeeeeeaeeeeeaeeeseaaeeseeeeeesnaeeteaes 53 Ga le 53 6 2 Freeware Data Gvstems nasaren 53 6 2 1 eil et te RENE e 54 NEE 54 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 2 Designing the Hardware 2 1 Using Data Bus Pins to Configure the MCU The logic level of the data bus pins during reset determines many important operating characteristics of the MCU Ensuring that the data bus is in a known condition during reset is vital to proper operation because the state of each data bus pin is sampled on the rising edge of the RESET signal The data bus pins have weak internal pull up circuitry that should cause them to default to a logic one if left float ing the pull up current is 15 to 120 uA However since it is possible for external bus loading to over come these internal pull ups it is a good idea to drive data bus pins that are critical to successful operation of the application to a known condition during reset and for at least 5 ns afterwards there is a 5 ns hold time requirement after the release of RESET for a data bus pin to be recognized at a par ticular logic level Table 1 shows how each data bus pin affects the system configuration Table 1 Reset Mode Selection Mode Select Pin Default Fun
59. elf The manufacturer specifies this value and also specifies a circuit usually one like that of Figure 3 along with the circuit values The crystal manufacturer makes a tacit assumption that the amplifier has enough drive capability to handle the required load so that the output voltage levels of the amplifier are not af fected Parameters related to suppression of harmonics and overtones are generally not specified by the crys tal manufacturer Harmonics are integer multiples of the fundamental frequency The first overtone is approximately 1 7 times the fundamental frequency Since a typical oscillator circuit forms a low pass filter the 3 db roll off point should be set at about 1 5 times the fundamental frequency of the crystal This should cause no attenuation at the fundamental but should cause significant attenuation at the first overtone and even greater attenuation at the first harmonic When figuring the reactance of the entire circuit it is most important to use the typical parameters of the crystal the input and output capacitance of the amplifier and the remainder of the external components in the calculation Many companies make crystals Most re sell their products through electronics distributors that are list edin the EITD Electronic Industry Telephone Directory Refer to 6 Sources of Information for ordering information Four crystal manufacturers are ECS 800 237 1041 The part number for a surface mount 32 768 kHz
60. en 0 and F in the queue To disable wrap around mode so that the QSPI only goes through the queue once clear th WREN bit SPCR2 14 to a zero LDD 4F00 STD SPCR2 NEWQP 0 ENDQP SF WREN is enabled STAB SPCR3 Disable loop mode HALTA and MODF interrupts and HALT LDX DATA Point X to the data to be transmitted LDY TRO Point Y to the transmit data RAM LDZ CRO Point Z to the command RAM LDE 10 Set a counter to count down from 16 10 since there are 16 queu ntries to fill LOOP LDD 0 X STD 0 Y Begin a loop to fill the transmit RAM AIX 02 Store the data right justified AIY 02 The next commands fill the command RAM in a right justified manner There is one byte of control information for each QSPI command to be executed in the queue Here all four chip selects will drive low during each serial transfer CLRB STAB 0 2 INCZ fill command RAM chip selects active low SUBE S01 Subtract one from the counter BNE LOOP Fill next queue entry if not done LDD 8000 STD SPCR1 Begin operation by setting the SPE bit FINISH BRA FINISH Normally this would begin the next task INT RTI unused interrupts will jump here DATA DB 16 Set aside memory space for the data to be transmitted This program does not initialize the data 4 4 3 Initializing QSM Interrupts To enable interrupts on the QSM initialize the following five fields 1 ILPQSPI and ILSCI in the Q
61. equency of TCNT is the system clock di vided by four Therefore for a 16 778 MHz system clock each TCNT tick is 238 ns long Thus the pe riod of OC 1 3 is approximately 122 us and the periods of OC4 and OC5 are approximately 244 us and 488 us respectively This example is in the file gpt_init asm in the archive 16Z1_init on the Freeware Data System INCLUDE EQUATES ASM register addresses INCLUDE INIT_RES ASM j initialize reset vector INCLUDE INIT_INT ASM initialize interrupt vectors ORG 200 yan SSS SSS ee ee MC68HC16Z1TUT D For More Information On This Product Go to www freescale com Freescale Semiconductor Inc INIT_SIM LDAB SOF set EK to SF to point to internal regs TBEK LDAA STF increase clock speed to 16 778 MHz STAA SYNCR assuming a 32 kHz crystal and using the VCO CLR SYPCR disable software watchdog ANDP SFFI1F ORP 0040 allow interrupts on levels 6 and 7 INIT_GPT LDD SFFOO STD PDDR make all GPT pins outputs LDD 0000 set 14 05 pins to output compare STD PACTL this is the default value LDD 3800 set up value for OC1M OC1D OC1 controls STD OCT OC1 3 data 0 at match TOC1 works differently than the other four OC channels because it can control all five OC channels Here it is configured to affect only the OC1
62. er of edges to be counted to the PACNT register As the edges are counted the counter will approach FF roll over to 00 and generate an interrupt The pulse accumu lator overflow flag will indicate that the count has rolled over Pulse Width Modulation PWMA PWMB These are the outputs to the two PWM functions They can be programmed to generate a periodic waveform with a variable frequency and duty cycle Alternately these pins can be used for general purpose I O PWMA can also be used to output the clock selected as the input to the PWM counter PWMCNT Auxiliary Timer Clock Input PCLK This is an external clock input dedicated to the GPT that can be used as the clock source for the capture compare unit or the PWM unit in place of one of the prescaler outputs If this pin is not used as a clock input it can be used as a general purpose input pin General Purpose I O Many of the GPT pins can be used as general purpose O All that is needed to configure a pin to general purpose O is to select the data direction in the data direction register called PDDR in older manuals and DDRGP in newer manuals and the actual data in the data register called PDR in older manuals and PORTGP in newer manuals Take special care when writing data to the data register since a read of this register returns the actual pin state and not the data just written to it Beware of the following scenario The current value of PORTGP is FF The user software w
63. es as one 16 bit port It also shows the connec tions necessary for a 16 bit memory In this example configuration CSO is connected to the chip enable pin CE of the first RAM chip and CS1 is connected to the chip enable pin of the second RAM chip This effectively makes CS0 the upper byte enable and CS1 the lower byte enable The RAW line of the MCU is connected to the R W lines of both RAM chips CSBOOT is connected to the ROM enable AD DR 13 1 of the MCU are connected to address lines 12 0 of each RAM chip and ADDR 16 1 of the MCU are connected to address lines 15 0 of the ROM MCU ADDR 16 0 ADDR 13 1 ADDR 13 1 DATA 15 0 mea ADDR 16 1 DATA DATA 15 0 DATA ADDR DATA ADDR DATA ADDR ROM 32K X 16 CE 332TUT EXT MEM CONN 2 Figure 13 Configuring 16 Bit Memory with 8 Bit RAMs Common R W Input Another common configuration is shown in Figure 14 Here the chip enables CE are always asserted the write enable WE for upper byte access is connected to CS0 the write enable for lower byte access is connected to CS1 and the read enable OE for both upper and lower byte accesses are connected to CS2 See 4 2 10 Example of SIM Initialization for software to initialize this example system ae ae ee MC68HC16Z1TUT D For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MCU ADDR 16 0 ADDR 13 1 ADDR 13 1 aed N Ieren DATAI7 0 DATA 15 0 DATA ADDR DATA AD
64. es resistor is correct check for the presence of metastable states during power up If there is extremely high frequency oscillation on the CLKOUT pin during the first few hundred milliseconds of operation and increasing the size of Rs does not fix the problem the only real solution is to find a different brand and or style of crystal There is no practical way to compensate for a crystal that exhibits poor self suppression of the first overtone and first har monic Once again if a particular crystal type and brand is prone to starting at overtones or har monics just don t use it No amount of circuit design will ever compensate for a bad or poor quality crystal Usually it is impossible to observe oscillator operation with an oscilloscope connected to one of the os cillator pins The oscilloscope adds 3 30 pF and 1 10 MQ of loading to Vss which will usually affect oscillator operation When the oscilloscope is connected to the EXTAL input the 10 MQ to Vss oscil loscope input forms a resistive divider with Rf and often disables the oscillator by biasing the circuit out of the linear region of the EXTAL input This problem can sometimes be overcome by capacitively cou pling the oscilloscope with a very small capacitor 1 5 pF between the oscilloscope probe and the os cillator pin It is better to observe the CLKOUT signal since this does not alter the operation of the oscillator It may be possible to observe XTAL since it is isolated fr
65. esentation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters which may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or
66. eset When a pin is configured for I O during reset and will never be reconfigured for the alternate func tion a pull up resistor may not be needed Table 1 shows which signals are affected by data bus pin state during reset BR CSO Use a 10 KQ pull up to prevent an unexpected bus request This pin is configured as a chip select pin when DATA1 is held high at the release of reset Conditioning DATA1 as described in 2 1 Using Data Bus Pins to Configure the MCU precludes use of a pull up BERR This is an input signal that is asserted in the absence of DSACK to indicate a bus error con dition Using a 10 KQ pull up resistor prevents the unexpected assertion of bus error HALT This is an active low bidirectional signal that can be used to halt the external bus among other things Using a 10 KQ pull up resistor will prevent an erroneous bus halt Since HALT is a bidirectional signal do not connect it directly to BERR RESET or 5 Volts IRQ 7 1 Although the interrupt lines have internal pull up circuitry the circuitry is weak and can be overcome by noise and capacitive coupling Make certain that pins configured for use as interrupt re quest inputs rather than for use as general purpose I O are pulled up to 5 Volts There are two ways to lessen the chances for erroneous interrupt service requests 1 Hold DATAQ low during reset as described in 2 1 Using Data Bus Pins to Configure the MCU to assign all these pins to gener
67. exhaustive discussion but it is intended to be used as a check list of the main problem areas that can cause an application to fail 5 1 Critical Signals to Check e RESET should stay low for at least 512 clocks during a power on reset If using the internal PLL RE SET will remain low for a little longer because the VCO must lock first RESET should then go high and remain high e CLKOUT should be at the system clock frequency If MODLCK is held high at the release of reset CLKOUT should be 512 times the frequency going into EXTAL 8 389 MHz for a 32 768 kHz crystal Make sure that the frequency is exact as a measurable error may indicate limp mode and oscillator faults If MODCLK is held low at the release of reset the frequency on CLKOUT should be the fre quency going into EXTAL e Immediately after reset CSBOOT should pulse low five times for a 16 bit port and nine times for an 8 bit port e FREEZE should be low and HALT should be high Otherwise the MCU is halted or is in BDM For More Information On This Product Go to www freescale com Freescale Semiconductor Inc e BR and BGACK should be high Otherwise the external bus is granted away e Make sure that the data bus pins are configured correctly during reset e Make sure that IRQ7 is high during reset 5 2 Common Problems and Solutions 5 2 1 Problem Device Stays in Reset 1 There is no pull up resistor on RESET RESET needs an 820 Q resistor to 5 volts See 2
68. function with interrupt request sig nals and port C output only pins share functions with chip select signals The ports are controlled by pin assignment registers CSPAR PEPAR and PFPAR and data direction registers DDRE and DDRF Pin assignment registers determine whether a pin is used for general purpose I O or for another function Data direction registers determine whether an I O pin is an input or an output Data is written to and read from the port data registers PORTC PORTE and PORTF 1 Assign port pins by writing to pin assignment registers 2 Program the data direction registers to assign input or output function to port pins 3 Use the Port data registers to read write data 4 2 10 Example of SIM Initialization This example assumes that three other files equates asm init_res asm and init_int asm exist The file equates asm defines labels for the internal registers The file init_res asm initializes the reset vector It contains the code shown in 4 1 3 1 Initializing the Reset Vector The file init_int asm initializes the interrupt vectors It contains the code shown in 4 1 3 2 Initializing Exception Vectors Other Than Re set This file is not necessary for debugging but should be included in final application code This ex ample can be assembled with the IASM16 assembler available from P amp E Microcomputer Systems This example is in the file init_res asm in the archive sim_init on the Freeware Data System
69. h no CPU intervention The queue is useful in applications such as control of an A D converter Remember the following points when using the QSPI e Setting the SPE bit to enable the QSPI should be the last step in initialization e Data direction register DDRQS and port data register PORTQS must be initialized even for pins that are assigned to the QSPI in pin assignment register PQSPAR e Peripheral chip select signals are asserted when a command in command RAM is executed but the assertion state active high or active low of the peripheral chip select signal is determined by the val ue of the appropriate bit in PORTQS e Take special care when writing PORTQS since a read of this register returns the actual pin state and not the data just written to it Beware of the following scenario The QSPI is inactive and the current value of PORTQS is FF The user software wishes to clear bit 0 and then OR this bit with a value in another register which also happens to be zero Thus the end result should be FE To accomplish this the software does a BCLR instruction immediately followed by an OR instruction However there is a good probability that after the BCLR instruction the pin state will not have changed by the time the CPU reads PORTQS for the OR instruction Thus the CPU could read the value FF from PORTQS instead of FE and end up with the wrong result To avoid this scenario put a NOP or a different instruction between two read modify w
70. he interrupt level by writing to the IPL field in the CPU status register For example if a level 3 interrupt is to be masked set the IPL field to three or higher Then disable the enable bit for the specific interrupt 5 An internal module is initialized improperly in such a way that the module cannot respond with an internal DSACK even when that module is the one asserting the interrupt 6 The IACK cycle is terminated by BERR instead of DSACK or AVEC The assertion of BERR causes the spurious interrupt vector vector number 24 to be taken A spurious interrupt will be taken in the following three situations A The CPU recognizes the occurrence of a valid interrupt request and begins the IACK cycle If none of the modules enter arbitration by asserting an IARB field value the spurious interrupt monitor asserts BERR internally B After arbitration the interrupt source that wins arbitration does not terminate the IACK cycle with DSACK or AVEC In this case the bus monitor asserts the internal BERR signal C An external device terminates the IACK cycle by asserting BERR An interrupt request signal must remain asserted from the time it first occurs until the end of the IACK cycle The most common cause of spurious interrupts is a periodic signal such as a Square wave con nected to an external interrupt request line Other signals such as the output of a shaft decoder will also cause spurious interrupts Latch periodic
71. in SPSR The next command defines the initial states of the chip select signals in PORTQS formerly called QPDR The chip selects may be active high or active low The initial state set in the PORTQS is the inactive state The active state is selected in the command RAM In this example the initial state of the chip select lines is high and the initial state of SCK is low This defines the chip selects to be active low and SCK to be active high The SCI TXD signal bit is not affected LDAB 7B STAB PORTQS define initial states of chip selects SCK STAB PQSPAR Assign all pins to the QSPI Pins can be jassigned to the QSPI or for general purpose I O on a pin by pin basis LDAB S7E STAB DDRQS Select the direction of the signal lines jas outputs except for MISO LDD 8002 STD SPCRO Configure the QSPI as master select 8 data bits per transfer set the inactive state of SCK as low capture data on the leading edge of SCK baud rate is 4 19 MHz For More Information On This Product Go to www freescale com Freescale Semiconductor Inc The next commands set the control parameters Interrupts are not enabled To enable interrupts upon assertion of the SPIF bit set SPCR2 15 To clear an interrupt read and then clear the SPIF bit Wrap around mode is enabled NEWOP is set to zero and ENDOP is set to F Thus the QSPI will continuously transmit the data betwe
72. indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part e 2 lt freescale semiconductor
73. ishes to clear bit 0 and then OR this bit with a value in another register which also happens to be zero Thus the end result should be FE To ac complish this the software does a BCLR instruction immediately followed by an OR instruction How ever there is a good probability that after the BCLR instruction the pin state will not have changed by the time the CPU reads PORTGP again for the OR instruction Thus the CPU could read the value FF from PORTGP instead of FE and end up with the wrong result To avoid this scenario put a NOP or a different instruction between two read modify write instructions involving the PORTGP register 4 5 1 GPT Interrupts Several steps must be followed in order for a GPT channel to request interrupt service 1 Store the starting address of the interrupt service routine in the CPU interrupt vector table The location in the vector table where the service routine starting address is stored is called the vector address The vector address is calculated from the interrupt vector number the address is two times the vector number The interrupt vector number is formed by concatenating a base vector number with the vector For More Information On This Product Go to www freescale com Freescale Semiconductor Inc number given in Table 7 1 on page 7 3 in the GPT Reference Manual GPTRM AD As shown in Table 7 1 each timer channel has a separate vector number Choose a base vector number and write it to
74. it to reduce radiation and crosstalk Connect the ground traces to ground planes at varied intervals not to exceed the wavelength 4 at the highest frequency or harmonic expected e Round off PCB trace corners as much as possible to reduce the amount of excess capacitance that is introduced to the trace at corners e Make spacing between adjacent active traces greater than the trace width to minimize crosstalk e Put a chassis ground ring on the periphery of each layer of the PCB to intercept the field coming off the board Interconnect these rings with small ceramic capacitors e Use ferrite chokes when troubleshooting Placing a choke around a signal line and the return conduc tor carrying a differential signal causes fields developed in the ferrite core by the opposing currents to cancel Ferrite chokes can also be used on input output lines Because board mounted chokes in me ise el MC68HC16Z1TUT D For More Information On This Product Go to www freescale com Freescale Semiconductor Inc crease the number of holes connecting to the supply planes they should be used only as a last resort e Localize any high frequency circuits such as the clock and address or data buses Decouple locally using high frequency filters such as ferrite chokes or damping resistors Be sure to separate the high speed and low speed circuits e Turn off any output signals such as ECLK that are not used e Shield the board externally e Reduce power supply noise
75. its of the address and the upper 4 bits are transparent Therefore the CPU can view the memory space as sixteen continuous 64 Kbyte banks without worrying about the gap between banks 7 and 8 when accessing memory 4 1 2 Exceptions An exception is a special condition such as a reset an interrupt or an address error that pre empts normal processing When the processor recognizes an exception it jumps to a special address and ex ecutes code starting at that address until it reaches a return from interrupt RTI instruction Then it resumes execution of the normal program code The vectors in the exception vector table tell the pro cessor the starting address of each exception routine 4 1 3 Exception Vector Table The CPU16 recognizes 256 exception vector numbers Each vector number corresponds to a space in the exception vector table that is one word long Thus the table extends 512 bytes upward in memory from the base address Each of the spaces in the table contains a 16 bit value that is used as an ad dress pointer or vector The actual address of each of the vectors in the table referred to as the vector address is two times the vector number and is located in memory bank 0 a ey eee eee ee ee MC68HC16Z1TUT D For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 6 is an overview of the exception vector table Refer to SECTION 9 EXCEPTION PROCESSING in the CPU16 Reference Manual CP
76. lers have become more complex bidirectional reset pins have become standard Bidirectional reset lines allow an external device to reset the MCU and also allow the MCU to assert reset for associated pe ripherals Bidirectional pins must be driven with open collector devices A typical circuit for driving the MCU RESET pin is shown in Figure 7 The RESET pin is driven by an open collector device and it is pulled to a logic 1 by an 820 Q resistor 5V 5V A MC68HC16Z1 10KQ S 820 _ OC oe S Ee RESET 10 100uF 5V H e L LOW VOLTAGE INHIBIT DEVICE 332TUT LVI RESET CONN Figure 7 Typical MC68HC16Z1 Reset Circuit When the internal PLL is used to generate the internal system clock the RESET pin works as follows At power up the MCU drives RESET low When the PLL locks the MCU releases RESET for two sys tem clock cycles If the external pull up resistor can pull RESET to a logic 1 during the two cycles the MCU assumes that the reset is a power on reset rather than an external reset However if RESET does not rise to a logic 1 during the two cycles the MCU assumes that the reset is an external reset and drives RESET to a logic 0 for 512 clock cycles After 512 cycles have elapsed the MCU releases RE SET for 10 clock cycles If RESET is a logic 1 at the end of the 10 cycles the MCU begins program execution If RESET is a logic 0 at the end of the 10 cycles the MCU once again actively drives RE
77. lso be low Thus there is a large gap in the middle of the memory map that the CPU cannot access This gap begins at 080000 and ends at F7FFFF Table 5 illustrates examples of accessible and inaccessible memory Table 5 Examples of Accessible and Inaccessible Addresses Hex Address A 23 20 A 19 16 A 15 12 A 11 8 A 7 4 A 3 0 Accessible 04000 0000 0100 0000 0000 0000 0000 yes 08000 0000 1000 0000 0000 0000 0000 no F8000 1111 1000 0000 0000 0000 0000 yes The address line comparators used for matches between the address bus and the chip select base ad dress registers CSBAR in the system integration module SIM still do a comparison on all 24 address lines As address lines A 23 19 always have the same value i e all high or all low the address com parators will never find a match between a CSBAR and the physical address bus if a value between 08000 and F7FFFF is in the CSBARx register The memory map for combined program and data space is shown in Figure 17 As shown in Figure 17 the memory map is divided into 16 banks of memory and each bank is 64 Kbytes long The most significant nibble of the addresses in banks 0 through 7 is 0 and the most significant nibble of the ad dresses in banks 8 through 15 is F ae ae ee MC68HC16Z1TUT D For More Information On This Product Go to www freescale com Freescale Semiconductor Inc
78. n of DSACK 0 1 which can occur if the pins are left floating AVEC If this signal is asserted during an interrupt acknowledge cycle an autovector will be used for the external interrupt being serviced If the AVEC pin is connected permanently to ground all external interrupts will autovector Using a 10 KQ pull up resistor will prevent unexpected assertion of the AVEC pin TSTME TSC The inactive state of this pin is 5 Volts Pulling it low enables special test mode but the MCU cannot enter test mode unless the state of a bit in one of the test mode registers is changed by the software Although this should happen only if the software is corrupted to prevent entering special test mode put a 10 KQ pull up resistor on this pin Special test mode is generally used only for factory testing Driving this pin to approximately 1 6 times Vpp causes the MCU to place all output drivers ina high impedance state isolating the MCU from the rest of the system BKPT DSCLK Background debug mode BDM operation is enabled when BKPT is asserted at the rising edge of the RESET signal BDM remains enabled until the next system reset If BKPT is at a logic level one on the trailing edge of RESET BDM is disabled BKPT is re latched on each rising transition of RESET A 4 7 KQ pull up resistor will ensure that BDM is not unexpectedly enabled upon reset R W Putting a 10 KQ pull up resistor on this pin will prevent accidental writes
79. n while the clock is in a metastable state 2 5 2 6 Using a Canned Oscillator A second option when using the internal frequency synthesizer circuit is to hold MODCLK high during reset and connect an external clock reference or canned oscillator a single package that includes the oscillator and required external components to the EXTAL pin Leave the XTAL pin floating but con nect the filter circuit shown in Figure 6 to Vppsyn and XFC The allowable frequency range is 20 50 kHz One manufacturer of canned oscillators is MC68HC16Z1TUT D For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Oak Frequency Control Group 717 486 3411 2 5 3 Using an External Clock To use an external clock connect a clock signal to the EXTAL pin and hold MODCLK low during reset Leave the XTAL and XFC pins floating but connect Vppsyn to power The frequency control bits in the SYNCR register have no effect the signal applied to the EXTAL pin should appear unchanged on the CLKOUT line The external clock must comply with the following expression Minimum external clock high low time 50 percentage variation of external clock input duty cycle Minimum external clock high low time is a specification given in the device electrical characteristics Minimum external clock period 2 6 Getting Out of Reset Asserting and releasing the RESET line was once a relatively simple task However as microcontrol
80. ng it in reset until full voltage is applied and by forcing an external reset as soon as power starts to fall This prevents the MCU from going into an indeterminate state due to a power supply failure or slow power supply ramp up time It is a good idea to use an LVI device since the MCU is not guaranteed to stay in reset when power is below Vpp In fact the actual voltage level that causes the MCU to go into reset is not a specified parameter and the MCU may continue to try to operate even when power dips below Vpp A number of manufacturers make LVI devices that can be used with the MCU Analog Devices 617 461 3392 LVI part numbers are ADM698 and ADM699 These devices require pull up resistors Dallas Semiconductor 214 450 0448 Various reset supervisor circuits Part numbers DS1233A D and M do not require pull up resistors Linear Technologies 408 432 1900 LVI part numbers are LTC692 and LTC693 These devices require a pull up resistor Maxim 800 998 8800 or 408 737 7600 Various reset supervisor circuits MAX 690 and MAX 700 series devices require pull up resistors but MAX 809 devices do not Freescale Semiconductor Inc 408 432 1900 One reset supervisor circuit part number is MC34064 It requires an external pull up resistor lt SSS SS Ni MC68HC16Z1TUT D For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 2 7 1 1 Using LVI Devices with External Oscillat
81. ng this program into memory using a debugger connect CSBOOT to RAM instead of ROM KKK KKK KK KKK KK KKK KK KKK KK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KK KK KK KK LDD 50003 STD CSBARBT base address of 00000 block size of 64K LDD 57870 STD CSORBT both bytes R W one wait state if you jare programming this code into ROM set this field to 6B30 Set up chip selects with a base address of 30000 block size of 64K LDD 0303 STD CSBARO set CSO base addr to 30000 64K blk LDD 0303 STD CSBAR1 set CS1 RAM base addr to 30000 64K blk STD CSBAR2 set Chip Select 2 at base addr 30000 LDD 5030 STD CSORO set Chip Select 0 upper byte write only LDD 3030 STD CSOR1 set Chip Select 1 lower byte write only LDD 6830 STD CSOR2 set Chip Select 2 both bytes read only LDD S3FFF STD CSPARO set Chip Selects 0 1 2 to 16 bit ports CLRW 0000 X write 0 to 30000 INIT PIT This section of code initializes the periodic interrupt timer to interrupt every second assuming a 32 kHz input to EXTAL LDD CLKINT STD 0080 2Z store starting addr of interrupt routine jat location 80 40 X 2 Z was initialized to 0 in init_res asm LDD 0640 STD PICR interrupt level 6 vector 40 LDD 0110 STD PITR time out period of 1 second ANDP SFF1F mask interrupts below level 6 ORP SOOA0 ITSELF BRA ITSELF stay here while waiting for interrupts CLKINT
82. nly take a few clock cycles to execute The impact is less in systems that make intensive use of CPU registers and complex instructions As a general guide e Use fast word memory for the CPU stack especially when programming in high level languages e Use fast word memory for frequently accessed variables e Use fast word memory for time critical routines perhaps by copying them from slow main ROM into fast external or internal RAM e Use slow byte memory for rarely executed non critical routines such as initialization routines 2 3 Pins that Need Pull Up Resistors Many of the input pins need pull up resistors to prevent unexpected conditions The pins discussed be low must be conditioned in all applications An incorrect voltage on one or more of them can cause gen eral system failure Other input pins such as TPU inputs can be left floating without adverse effect in certain applications The designer must determine which pins can cause system failure in a particular application and deal with them appropriately In general it is best to condition all input pins so that they are in a known state whether they are used or not Never connect a pin directly to 5 volts if it is possible to configure the pin as an output Attempting to drive an output low when it is connected to voltage source can damage the output drivers Many of the pins have dual functions and can be configured as I O pins by holding specific data bus lines low during r
83. ns polystyrene ca pacitors are recommended See Figure 6 for a recommended circuit For More Information On This Product Go to www freescale com Freescale Semiconductor Inc C3 C1 0 1uF 0 1uF gt XFC t gt VDDSYN C4 E 0 01uF Vss MAINTAIN LOW LEAKAGE ON THE XFC NODE 332TUT XFC CONN Figure 6 Conditioning the XFC and Vppsyn Pins 2 5 2 5 Evaluating Oscillator Performance Once an entire oscillator circuit is built it is very important to evaluate circuit characteristics Of partic ular interest is how the oscillator starts If the oscillator starts in a metastable state that persists for sev eral hundred milliseconds it is quite possible that this state will persist until the MCU releases reset and tries to start fetching instructions When this happens the PLL may well be operating at a frequency far greater than the maximum specified for the MCU Any variation in the input frequency of the PLL is mul tiplied by the feedback ratio of the PLL If the MCU starts operating i e reset is released and the inter nal clocks are gated to the internal buses while the oscillator is operating at an overtone or first harmonic the MCU will probably enter an inoperative state in which it cannot be restarted by a hardware reset In this case the only option is to turn the system power off and then attempt a power on reset Because oscillators are very sensitive circuits malfunctions are difficult to di
84. nsfer and active low peripheral chip select pins Modifying the code to disable the wrap around mode is very simple The modification is explained in the comments This example is in the file qspiinit asm in the archive 16Z1_init on the Freeware Data System INCLUDE EQUATES ASM file of register equates INCLUDE INIT_RES ASM j initialize reset vector INCLUDE INIT_INT ASM initialize interrupt vectors ORG 200 begin program at 200 after the exception table INIT_SIM LDAB SOF initialize K registers YK ZK to bank SF XK to bank 0 BEK TBYK TBZK CLRB TBXK LDAA S7F STAA SYNCR increase clock speed CLR SYPCR disable software watchdog INIT OSPI LDD SPCR1 ANDD 7F STD SPCR1 Clear the SPE bit to disable the QSPI Enabling the QSPI is the last step in the initialization sequence The next commands read and clear the flags in SPSR These flags are the QSPI finished flag SPIF the mode fault flag MODF and the halt acknowledge flag HALTA The SPIF bit is usually the flag of interest It is set by the QSPI upon completion of a serial transfer when the address of the command being executed matches the ENDOP If wrap around mode is enabled th SPIF bit is set each time the QSPI cycles through the queue If interrupts ar nabled assertion of the SPIF bit causes an interrupt LDAB SPSR ANDB 500 STAB SPSR read and clear flags
85. nternal state machine fetches the word values at address es 000000 through 000006 These values generally referred to collectively as the reset vector are shown in Table 7 The values in the reset vector must be initialized in order for program execution to begin Table 7 Reset Vector for CPU16 Address Reset Vector 0000 Initial ZK SK and PK 0002 Initial Program Counter Lower Word 0004 Initial Stack Pointer Lower Word 0006 Initial IZ Register Lower Word Sample code to initialize the reset vector follows Make sure that the stack does not overlap the program code the stack grows downward in memory If the assembler does not recognize DW check the manual to determine the format for defining a constant word Another common format is DC W This example is in the file init_res asm in the archive 16Z1_ init on the Freeware Data System org 0000 begin at address 000000 of memory map DW 0000 initial ZK SK and PK 0 DW 0200 initial PC 200 DW 3000 initial SP 3000 DW 0000 jinitial IZ 0000 4 1 3 2 Initializing Exception Vectors Other Than Reset Each exception vector should point to a handler routine in case the exception is accidentally taken In an actual program the vectors would point to different labels but in the example below all of the vectors point to the same label INT This label must be included later on in the code in case an exception is taken This
86. oard that are spaced so that a female Berg connector can plug into them Figure 16 shows the pinouts for the recommended 10 pin BDM connector Table 4 describes the BDM signals DS 1 O 2 BERR GND 3 O O 4 BKPT DSCLK GND 5 O O 6 FREEZE RESET 7 O 8 IPIPE1 DSI VDD 9 10 IPIPEO DSO 332TUT BERG10 Figure 16 10 Pin BDM Connector For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 4 BDM Connections 10 Pin Connector Signal Use 1 DS Data strobe 2 BERR Output from ICD to BERR input 3 GND Ground reference Output from ICD to BKPT input assertion causes MCU to 4 BKPT DSCLK first enable and then enter background mode Once in BDM this pin becomes the serial clock 5 GND Ground reference 6 FREEZE nee ni indicating whether it is operating normal 7 RESET Device reset 8 IPIPE1 DS Serial input data to the MCU in BDM 9 Von Device operating voltage 10 IPIPEO DSO__ Serial output data from the MCU in BDM Only ten pins on the board a special cable and software are needed to debug The M68ICD16 cable has a 10 pin female connector on one end and a PAL with a 25 pin connector on the other end The 10 pin connector will plug directly into a male header or connector with the layout shown in Figure 16 The PAL end of the cable plugs into the parallel port of a PC The PC runs the debugger software that controls the MCU in
87. om the rest of the oscillator by Rs Observe Ipp without the oscilloscope connected and again with it connected If Ipp is unchanged it is usually safe to assume the oscillator was unaffected For additional information see 2 5 Clock Circuitry 5 2 4 Problem System Crashes after Fetching Reset Vector 1 Incorrect reset configuration of boot memory width is causing the address bus to increment by the wrong amount during fetches of the reset vectors Check DATAO to make sure that it is being driven to the correct state during reset If CSBOOT is a 16 bit port drive DATAO high during re set if it is an 8 bit port drive DATAO low See 2 1 Using Data Bus Pins to Configure the MCU 2 An IRQ7 interrupt is received during or immediately after reset The MCU will recognize the in terrupt after fetching the reset information and first instruction In a typical system that is booting out of ROM stack RAM will not be enabled at this point and the first bus cycle to write the stack frame will hang the MCU Make sure that the IRQ 7 1 lines are either pulled up through resistors to 5 volts or configure the pins as PORTF I O lines by pulling DATAS9 low during reset Also start up software should enable the stack RAM by configuring the appropriate chip select circuits be fore enabling the interrupt lines by writing to the PFPAR register This problem is likely to be intermittent as it would only occur if an IRQ7 interrupt is received in the short time
88. ors An LVI device provides an extra degree of protection when an external oscillator that has an indepen dent power supply is used to generate the system clock In this case the LVI device ensures that the oscillator does not power up before the MCU 2 7 1 2 Using LVI Devices with Multiple Power Supplies Take special precautions when system components that are connected to each other have separate power supplies Generally one power supply will reach operating voltage more quickly than another A device connected to this fast supply can begin to operate before devices connected to a slower supply have reached operating voltage If a device connected to a fast supply drives logic one levels to a device connected to a slow supply the input protection diodes of the slow starting device can be momentarily forward biased and significant current can be injected into the device substrate In the case of an MCU the injected current can cause internal nodes to be improperly charged or discharged Since this action is random it is impossible to predict what will happen when injection occurs Usually the processor will fail to fetch opcodes Figure 9 shows how to use LVI devices to prevent this problem Each power sup ply is monitored by a separate LVI device Signals from other boards are inhibited until correct operating voltage is applied POWER SUPPLY POWER SUPPLY Al tow LW o VOLTAGE VOLTAG
89. pt Vectors Vectors are 16 bit addresses that point to the interrupt service routines and other exception handlers They are stored in a data structure called the exception vector table There are 256 vector addresses in the exception vector table of these 199 can be used for interrupts The base address of the excep tion vector table is determined by the value stored in the vector base register A vector number is used to calculate the vector address i e a displacement into the exception vector table 2 10 4 The Interrupt Acknowledge Cycle After the CPU recognizes a valid interrupt request the CPU begins the interrupt acknowledge IACK cycle The CPU changes the IPL mask value to the level of the acknowledged interrupt to preclude low er or equal priority interrupt requests then initiates a read cycle in CPU space Since there is no dedi cated IACK pin on the MCU an external IACK signal is usually provided by a chip select pin Vector numbers can be supplied by the device requesting interrupt service or they can be generated automatically Vector numbers supplied by the device cause the CPU to access one of 192 user vectors in the exception vector table automatically generated vectors cause the CPU to access one of the 7 autovectors in the table Each method of vector number acquisition requires a different form of IACK cycle termination H a vector number is supplied either the requesting device must terminate the ACK cycle with a DS
90. ptions for CSBOOT if desired Reducing the number of wait states from the re set value of 13 increases execution speed 2 Program the option registers for each chip select circuit used A MODE Select asynchronous mode 0 unless using the ECLK output to provide synchro nous bus timing for 6800 peripherals In synchronous mode 1 the STRB and DSACK fields have no effect Ke MC68HC16Z1TUT D For More Information On This Product Go to www freescale com Freescale Semiconductor Inc B BYTE This field determines whether to assert the chip select signal for an upper byte ac cess lower byte access both or neither When two 8 bit memories are used to make up one 16 bit port the associated chip select circuits are programmed identically except for BYTE field values select upper byte for one and lower byte for the other C R W This field specifies whether to assert the chip select signal during a read cycle a write cycle or both When the chip select circuit is used to generate an IACK signal or to provide an autovector this field must be set to read or read write D STRB This field specifies whether chip select assertion is synchronous with AS or DS If a chip select circuit is used to generate an IACK signal or to provide an autovector this field should be set to AS E DSACK This field either specifies the number of wait states to insert before the chip select circuit asserts DSACK an
91. ration Module Since the SIM determines important operating characteristics of the entire MCU it should be the first module after the CPU to be initialized The following paragraphs discuss registers important to initial configuration 4 2 1 System Integration Module Configuration Register SIMCR The SIMCR controls module mapping for the MCU internal use of the FREEZE signal and the prece dence of simultaneous interrupt requests of the same priority Configure the SIMCR as follows Leave the state of the module mapping MM bit at its reset state of one MM determines where the in ternal control registers are located in the system memory map When MM 0 register addresses range from 7FF000 to 7FFFFF when MM 1 register addresses range from FFF000 to FFFFFF How ever since the CPU16 cannot access addresses 080000 to 7FFFFF do not change the MM bit to zero 1 If using the software watchdog periodic interrupt timer or the bus monitor select action taken when FREEZE is asserted The freeze software enable FRZSW bit determines whether the software watchdog and periodic interrupt timer counters continue to run when FREEZE is assert ed and the freeze bus monitor enable FRZBM bit determines whether the bus monitor contin ues to operate when FREEZE is asserted 2 Select the interrupt arbitration level for the SIM with the interrupt arbitration IARB field The de fault state out of reset is F the highest precedence To a
92. rd Emulators can be very sophisticated and costly but are very useful in tracking down design problems because they allow the designer to see exactly what the MCU is doing at every step of operation When both the board and code are fully debugged the emulator is removed and the MCU is placed on the board 3 1 2 Using Background Debug Mode Background debug mode is a special CPU operating mode that allows an external host to take control of the MCU BDM is a very useful tool for debugging During BDM operation normal instruction execu tion is suspended and microcode executes built in debugging instructions under external control Since BDM suspends processor execution an external host can examine and change memory and registers BDM instructions and the protocol required to use them are described in detail in the CPU16 Reference Manual CPU16RM AD AN1230 D A BDM Driver Package for Modular Microcontrollers shows how to implement a BDM communication interface using C language drivers While a BDM interface is relatively easy to implement ready made BDM interfaces are inexpensive and reliable Freescale sells the M68ICD16 BDM debugger made by P amp E Microcomputer Systems The M68ICD16 consists of the necessary cable and software to implement BDM debugging on an IBM com patible PC All the discussions in this section assume that M68ICD16 is being used 3 1 2 1 BDM Signals To use BDM simply connect ten MCU lines to pins on the development b
93. rite instructions involving the PORTQS register e Take special care when writing PORTQS while using the QSPI because control of the PORTQS pins is shared by the QSPI and the CPU During transfers the QSPI controls the pins assigned to it in the PQSPAR but when transfers are complete control reverts to what the CPU has written in PORTQS Beware of the following scenario The CPU writes the initial value of PORTQS to FF so that the inactive state of each QSPI chip select pin is high The CPU configures the active state of each chip select to be low in the command RAM Later the user software decides to make PCS1 bit 4 in PORTQS drive low all of the time To do this it arbitrarily does an AND of PORTQS with EF to clear bit 4 without affecting any other bits in the Ke MC68HC16Z1TUT D For More Information On This Product Go to www freescale com Freescale Semiconductor Inc register However if this is done arbitrarily there is a possibility that the QSPI will be active and will be driving all of the chip selects low Thus the CPU could read bits 3 6 as zero instead of one and end up writing back an erroneous value to PQSPAR In this situation all of the chip selects would drive low all of the time To avoid this scenario only modify PORTQS when the QSPI is disabled the SPE bit is zero 4 4 2 1 QSPI Initialization Example This example illustrates how to initialize the QSPI in the wrap around mode with eight data bits per tra
94. s register values 0800 to F7FF are invalid 5 3 Problem ADC Results are Inaccurate 1 Ensure that Vppa and Vgsa are as noise free as possible and are as isolated from the digital power supply as possible 2 Ensure that Vay and Vp are within the voltage limits specified by Vppa and Vssa and that they are as noise free and clean as possible 3 Ensure that the analog inputs to AD 0 7 are within the voltage limits specified by Vay and Vay and that they are as noise free and clean as possible Also ensure that the inputs are low leak age low impedance Ensure that the input current does not exceed the disruptive input current specification for the device ya SSS SSS I a e MC68HC16Z1TUT D For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Refer to 4 6 Configuring the Analog to Digital Converter earlier in this tutorial and Chapter 6 in the ADC Reference Manual ADCRM AD 6 Sources of Information 6 1 Technical Literature All Freescale literature can be ordered by mail from Freescale Literature Distribution Centers shown on the back page of this publication or through local sales offices For U S and European literature orders call 800 441 2447 Freescale publication BR1116 D4dvanced Microcontroller Technical Literature in cludes a complete listing of literature sales offices distributors and an order form 6 1 1 User s Manual MC68HC 1621 User s Manual MC68HC16Z1UM AD
95. signed a priority However the user can pick one of those sources to have the highest priority For example if a 4 is written to bits 15 12 of the ICR then OC1 will have the highest priority When OC1 generates an interrupt the low nibble of the vector will be 0 instead of 4 The remaining channels maintain their original relative priority and vector addresses 4 Store an interrupt arbitration value in the IARB field of the GPT module configuration register The IARB field value determines precedence when the CPU receives more than one interrupt request of the same interrupt priority level Each interrupting module must be assigned a unique IARB number between 01 lowest precedence and 0F highest precedence 5 Set the interrupt enable bit for the channel in the timer interrupt mask register TMSK1 TMSK2 This simply involves writing the channel s bit number to a one To clear an interrupt negate the appropriate interrupt status flag in the timer interrupt flag regis ters TFLG1 TFLG2 Read the flag in the asserted state and then write a zero to the bit As long as the interrupt status flag is set the channel will continue to request interrupts 4 5 2 GPT Initialization Example The following example uses all five output compare channels In this example OC1 controls the OC1 OC2 and OC3 pins OC4 and OC5 operate independently The period of OC 1 3 is 200 TCNTs The period of OC4 is 400 and the period of OC5 is 800 The fr
96. so in this range Assuming that Rd and Rf are both 10 MQ the voltage at point A is half the voltage difference between points B and C Thus if the XTAL pin is at a logic 1 4 5 volts and point C is at ground the voltage at point A EXTAL pin will be 2 25 volts If point B is ata logic 0 0 5 volts and point C is at ground the voltage at point A is 0 25 volts Thus the voltage at point A may be interpreted as a logic 0 regardless of whether the XTAL pin is a logic 1 or a logic 0 This de pends on the threshold of the inverter whose input is connected to point A Likewise if point C is con nected to 5 volts point A may be interpreted as a logic 1 regardless of the state of the XTAL pin A circuit with this problem will not oscillate The only way to diagnose this problem is to remove the external circuit components as well as the MCU from the board and use an Ohm meter to check the resistance from points A and B to ground Anything other than a completely open circuit is a sign of trouble The obvious solution is to clean the printed cir cuit board If the dirt or grime that form the high resistance path is on an inner layer of the printed circuit board the board is unusable INTERNAL AMPLIFIER y XTAL EXTAL Kg f cn 10 MQ TO 5 OR GND d 10 MQ 332TUT XTAL RF RD CONN Figure 4 DC Model of Oscillator Circuit MC68HC16Z1TUT D For More Information On This Product Go to www freescale com Freescale Semiconductor
97. t op eration or alternate function 2 If a chip select circuit is used to generate an interrupt acknowledge signal it must be configured for chip select operation However if a chip select circuit is used to generate an autovector the pin can also be used for discrete output or its alternate function 4 2 7 Chip Select Base Address Registers CSBARBT CSBAR 0 10 Chip select signals are asserted when the CPU accesses certain ranges of addresses The base ad dress registers specify the address ranges for each chip select circuit 1 Reprogram the base address and or blocksize of CSBOOT if desired The default value out of reset is a base address of 000000 with a blocksize of 1 Mbyte 2 Program the base address and block size for each chip select circuit that is used The base ad dress must be on a word boundary of the block size For example for an 8 Kbyte block size the base address can be 2000 4000 6000 8000 etc If a chip select circuit is used to generate an interrupt acknowledge signal or an autovector the base address register must be set to FFF8 or higher because interrupt acknowledge cycles occur in CPU space Remember that the CPU16 cannot access memory locations 080000 to F7FFFF so do not program these ad dresses in the base address register 4 2 8 Chip Select Option Registers CSORBT and CSOR 0 10 The option registers control the conditions under which a chip select signal is asserted 1 Reprogram the o
98. t phone number 512 891 3733 Freeware can be accessed via internet at freeware aus sps mot com For World Wide Web access use hittp For More Information On This Product Go to www freescale com Freescale Semiconductor Inc freeware aus sps mot com The Freeware system contains a wealth of information concerning Freescale MCUs and downloadable software 6 2 1 Application Snapshots Application snapshots provide brief discussions of commonly encountered problems and technical is sues concerning MCUs Snapshots are available on the Freeware system access the Tech_Notes area to see a list of topics and download snapshots The system provides instructions concerning nav igation and downloading files 6 3 Other Sources EDN Magazine s Designer s Guide to Electromagnetic Compatibility Call 800 523 9654 for a reprint of the article EITD Electronic Industry Telephone Directory Lists phone numbers addresses and fax numbers of about 30 000 sources for electronics products and services Call 800 888 5900 or 216 425 9000 MC68HC16Z1TUT D For More Information On This Product Go to www freescale com Freescale Semiconductor Inc For More Information On This Product Go to www freescale com Freescale Semiconductor Inc How to Reach Us Home Page www freescale com E mail support freescale com USA Europe or Locations Not Listed Freescale Semiconductor Technical Information Center CH370 13
99. t programmed properly or something is preventing the MCU from executing code Check all pull up resistors for good connections and correct values Also check the frequency of CLKOUT 5 2 3 Problem CLKOUT Frequency is Incorrect 1 MODCLK is not driven correctly during reset To use a crystal and the internal PLL MODCLK must be driven high during reset To use an external clock and bypass the internal PLL MOD CLK must be driven low during reset 2 The crystal is settling into overtones due to a poor quality crystal or incorrect components in the crystal circuit 3 If the frequency is unstable it is possible that the crystal is being overdriven Increase Rs to re duce crystal drive 4 There is residue on the PCB Since low frequency crystal circuits tend to be very high impedance the PCB must be clean dry and free of conductive material such as solder rosin and excessive moisture from high humidity 5 In the absence of other circuit problems the series resistor is the most probable culprit when an oscillator will not start The resistor limits the power that starts the crystal oscillating If the resis tance is too low the crystal will start oscillating in unpredictable modes and could even become damaged If the resistance is too high the oscillator will start very slowly or not at all MC68HC16Z1TUT D For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 6 If the value of the seri
100. t that is active out of reset and it enables only the first one Mbyte of memory When the first instruction fetches are made at FFFFFF there will be nothing to generate DSACK and termi nate the bus cycle and the debugger software will force a bus error Should this occur the debugger generally displays a series of Memory implementation error debugger supplied DSACK messages on the computer screen After the debugger software has finished making the scheduled number of pro gram fetches the error messages will stop and the MCU will be in BDM waiting for the next debugger command However additional errors will occur if the next command is an external memory access be cause the program counter and stack pointer values are invalid When using a software background mode debugger to boot an MCU from external RAM or uninitialized ROM it is imperative that the following actions be taken immediately after starting the debugger 1 Load a value into the stack pointer It must point to a modifiable memory address ey eee ee ee ee MC68HC16Z1TUT D For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 2 Load the address of the first instruction to be executed into the program counter The debugger should now work reliably That is programs can be downloaded into the RAM and exe cuted Alternatively write the reset vector to memory location 000000 and then reset the MCU The reset vector is dis
101. tain contact If the MCU is likely to be removed and replaced consider using a zero insertion force socket Three socket manufacturers are For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 3M 800 328 0411 AMP 800 522 6752 and Yamaichi 408 452 0797 2 5 Clock Circuitry The designer must decide whether to use the internal frequency synthesizer circuit or an external clock to produce the system clock signal Both options are discussed in the following paragraphs 2 5 1 Using the Internal Frequency Synthesizer Circuit The MCU uses a voltage controlled oscillator VCO and a phase locked loop PLL to generate an in ternal high speed clock This arrangement permits low power operation using only the low frequency oscillator Low frequency in CMOS technology translates into low power because power consumption is proportional to frequency The internal frequency synthesizer circuit is enabled when the MODCLK pin is pulled high during reset The synthesizer requires a reference frequency in order to operate There are two reference frequency options a crystal oscillator circuit or an external clock reference such as a canned oscillator circuit a single package which contains the crystal and buffer circuit as the input 2 5 2 Using a Crystal Oscillator Circuit 2 5 2 1 Oscillator Components The crystal oscillator used is a Pierce oscillator also known as a parallel resonant
102. ted to the supply at a single location A recommended layout technique is shown in Figure 11 Essentially the bypass capacitor should be positioned so that it serves the power pin itself rather than the surrounding metal trace This is accom plished by running a specific conductor to the power pin and then locating the bypass capacitor as close to the power pin as possible For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Another way to control power supply noise created by the MCU is to put a small inductor in series with the power supply lines for the port drivers This method can help control noise on the power traces of the PCB However it should be used only as a last resort because it can introduce other noise prob lems Also a series inductor in the power supply line will probably have little effect on radiated noise which is generally a result of the port driver switching speed Limiting instantaneous current change by putting an inductor in series with the power supply pin for the port will not appreciably affect the current through a particular driver because the integrated circuit generally has enough internal capacitance to support an instantaneous current surge while the driver switches POWER PLANE VDD PIN N BYPASS CAP 1 uF TYPICAL GND PLANE 332TUT VDD LAYOUT Figure 11 Proper Placement of a Bypass Capacitor The Vppsyn and Vstpy supply pins shoul
103. terrupt Pins 25 2 10 6 Checklist for External Interrupt Acknowledge ssssessssssssessssessisssrrssrnrssrnssrnsstnneennnnt 26 3 Establishing COMMUNICATION cccceeeeeeeeeeeeeneeeeeeeeeeseeeeeeeeeesaaeeeneeeeessaessaseeeeseaeeseseeeeesseeseseeeeneees 27 3 1 Communicating with the Target Board 27 Sel Ty USing ance UI TEE 27 3 1 2 Using Background Debug Mode 27 EE BIO ae ets s EE 27 S22 HOw RTR 28 3 2 Communicating with Freescale BoardS ssesssseessseesreesistsiestiretitnssinssrnsstnnntnnntnnnnnnnntnnnnnnnnt 29 9 2 1 The MEBHCIGZIEVBysstccscats cis cevetertevcshes eege ooh sand Menu ttsitel eeetiviiei ieee NERT Nee ERD 29 3 2 2 The M68MEVB1632 cceeceeeeceeceeeeeeeeeee cease a aa E A A A E AER aaa 29 RER TREK ea a a a a eileen aa AER a NEE ES 29 d System Initialization aine Seege 29 4 1 Configuring the Central Processing Un 29 4 1 1 The CPU16 Memory Map and Bank Switching 0 cccecceceeeeeeeeeeeeeeeeeeeeeeeeeeseeeeeeeeeees 30 EES MC68HC16Z1TUT D For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 4 1 1 1 The Memory Maeres ieres reen E EEE RAE T EEE RATE 30 ATi he Extension Palda cece aE SEEE seek EAE E RER 31 4 1 1 3 Switching Between Banks 32 A12 ee 32 4 1 3 Exception Vector Table eisers os eena ET EEEE FERAE EEOAE EAR R 32 4 1 3 1 Initializing the Reset VeCtor ececcccceeeeccccceeeeeeceeeeeeseeceeeeeeeeeceeeseseeceeeeeneeceeenennees 34
104. th a write cycle time of 130 ns requires one wait state since 130 ns is between 89 2 ns and 148 8 ns Table 3 Memory Access Times in Nanoseconds Wait 16 78 MHz 20 97 MHz States Chip Select Read Access Address Chip Select Read Access Address Memory Write Access Access Memory Write Access Access F T 29 6 55 4 19 7 43 55 0 89 2 115 0 67 4 91 25 1 148 8 174 6 115 1 138 95 2 208 4 234 2 162 8 186 65 3 268 0 293 8 210 5 234 35 4 327 6 353 4 258 2 282 05 5 387 2 413 305 9 329 75 6 446 8 472 6 353 6 377 45 7 506 4 532 2 401 3 425 15 8 566 0 591 8 449 0 472 85 9 625 6 651 4 496 7 520 55 10 685 2 711 544 4 568 25 11 744 8 770 6 592 1 615 95 12 804 4 830 2 639 8 663 65 13 864 0 889 8 687 5 711 35 2 9 2 Using Chip Select Signals to Enable Boot Memory The MCU CSBOOT chip select circuit is always enabled from reset Because the internal SRAM mod MC68HC16Z1TUT D For More Information On This Product Go to www freescale com Freescale Semiconductor Inc ule is disabled out of reset the CSBOOT signal is generally used to select an external boot ROM The CSBOOT chip select circuit features hardware controlled selection of 8 bit or 16 bit bus width Bus width is controlled by the state of the DATAO line at the release of the RESET signal The default bus width out of reset is 16 bits because the DATAO line is pulled up to logic level 1 internally however the internal p
105. th it and the ZK field can be stored in the reset vector so that it is initialized automatically out of reset Shown below is a short sample code snippet that uses index registers as page pointers In this example the IY register points to bank 10 and the EK field points to bank 15 This code snippet initializes CS BOOT to point to bank 10 Note that the addresses written to the chip select base address registers include bits 23 20 This is because the address comparators that determine whether a chip select line should assert compare bits 23 20 of the actual address bus to bits 23 20 of the address in the chip select base address register The chip select registers are discussed in further detail in 4 2 6 Chip Se lect Pin Assignment Registers CSPARO and CSPAR 1 INITSYS LDAB SOF BEK set EK to SOF to access control registers LDAB SOA TBYK IY will address bank 10 CSINIT LDD SFA03 CSBOOT block size 64 KBytes assume 16 bit port STD CSBARBT base addr FA0000 bank A MAIN LDD 1234 jLoad D with the immediate value of 1234 STD 7300 Y Store 1234 at SFA7300 bank 10 In summary the memory map for CPU16 based processors consists of two 512 Kbyte blocks separated by a gap from address 80000 to address F7FFFF This is because when CPU driven address lines 20 23 follow the same logic state as address line 19 Because these lines are driven automatically the CPU only sees the lower 20 b
106. tion On This Product Go to www freescale com Freescale Semiconductor Inc 4 2 4 Periodic Interrupt Timer Register PITR PITR and PICR control the periodic interrupt timer PIT The PIT begins to run when a timing modulus is written to the PITM field in PITR However interrupt requests from the PIT are recognized only after an interrupt priority level is written into the PIRQL field in the PICR Clearing PITM stops the timer clear ing PIRQL disables interrupts but the timer continues to run Because the CPU treats external inter rupts as SIM interrupt requests PIT interrupts take precedence over external interrupts of the same priority To use the timer proceed as follows 1 Make certain that there is a vector to the interrupt service routine in the exception vector table and that there is a service routine at the address pointed to 2 Select whether or not to prescale the timer clock signal PTP bit in PITR 3 Select the timing modulus or interrupt rate PITM field in PITR 4 2 5 Periodic Interrupt Control Register PICR 1 Determine the appropriate PIT vector number and interrupt priority 2 Write vector number and interrupt priority to PIV and PIRQL fields in PICR 4 2 6 Chip Select Pin Assignment Registers CSPARO and CSPAR1 The chip select pins can be used in a number of ways CSPAR determine the functions of the pins 1 Set up the chip select pins for discrete output 8 bit chip select operation 16 bit chip selec
107. tion is based on address strobe If it is based on data strobe add 2 tcyc to tesa for For More Information On This Product Go to www freescale com Freescale Semiconductor Inc the write cycle chip select access time The other known parameters are shown in Table 2 Table 2 Parameters Needed for Calculating Memory Access Times Parameter Symbol 16 78 MHz 20 97 MHz Min Max Min Max Clock Period tcyc 59 6 ns 47 7 ns Clock Low to AS DS CS Asserted teLSA 2 ns 25 ns 0 23 ns Data In Valid to Clock Low Data Setup toicL 5 ns 5ns Clock High to Address FC SIZE RMC Valid tCHAV 0 29 ns 0 23 ns Clock Low to AS DS CS Negated toLsn 2ns 29 ns 2ns 23 ns MCU read cycle access time is used to determine the number of wait states needed for a given memory speed because it is longer than write cycle access time and is thus the limiting factor As an example the equations below are solved for zero wait states assuming 16 78 MHz timing Address access time 2 5 X 59 6 ns 29 ns 5 ns 115 ns Chip select access time MCU read cycle 2 X 59 6 ns 25 ns 5 ns 89 2 ns Chip select access time MCU write cycle 2 X 59 6 ns 25 ns 2 ns 96 2 ns The equations can also be solved for the number of wait states needed given the memory speed Use Table 3 to find the number of wait states required for a particular memory speed For example with a 16 78 MHz clock a memory wi
108. tive bits in the OC1D register Following are the interrupt routines In each one a new future value is written into the appropriate TOC register OCS INT interrupt routine for OC5 LDD TI405 ADDD 400 STD TI405 ad 400 to value in OC5 register BCLRW TFLG1 8000 clear 1405 flag RTI OC4_INT interrupt routine for OC4 LDD TOC4 ADDD 200 STD TOC4 add 200 to value in OC4 register For More Information On This Product Go to www freescale com Freescale Semiconductor Inc BCLRW TFLG1 4000 clear TOC4 flag RTI OC INT interrupt routine for OC LDAB OCTD BNE DRIVE_PINS_LO branch if pins are high BSETW OC1M 0038 set OC1 3 to go high at next match BRA GET_TOC1 DRIVE_PINS_LO BCLRW OC1M 0038 set OC1 3 to go low at next match GET_TOC1 LDD TOC1 ADDD 100 STD TOC1 add 100 to value in OC1 register BCLRW TFLG1 0800 clear TOC1 flag RTI INT RTI unused interrupts point here 4 6 Configuring the Analog to Digital Converter The analog to digital converter ADC takes an analog voltage as an input and provides a digital read ing It has eight channels and selectable 8 or 10 bit resolution Each result is available in three formats right justified unsigned left justified signed and left justified unsigned depending on the address from which it is read The ADC can also be used for digital I O Port ADA is an input only port and port ADB is an output only port Data in these t
109. to memory while the device is being powered up Normally R W is always defined However when power is first applied to the device R W can be undefined for a few cycles This may cause a problem for EEPROM or battery backed up RAM RESET An 820 Q pull up resistor is required for this pin Do not put capacitors on the RESET pin The reason for such a strong pull up and no extra capacitance is that the RESET line must rise to a logic 1 within approximately10 system clocks after the MCU has driven RESET low for 512 clocks or else the MCU re asserts the RESET line for an additional 512 clock cycles MODCLK If using the internal PLL to generate the system clock this pin must be pulled up with a 10 KQ resistor or driven high during reset If using an external clock source and bypassing the PLL con nect this pin to ground or drive it low during reset 2 4 Using Sockets Because of the high pin count the MCU package has a very narrow lead pitch which makes it nearly impossible to hand solder onto a board This is not a problem for design activities that can manufacture PC boards but designers who are assembling a limited number of prototypes or who cannot manufac ture PC boards will probably need to use a socket to hold the chip The wider spacing of socket pins makes it possible to connect the socket to a board Sockets are not a place to economize Use a good quality socket that firmly holds the MCU in place so that all pins main
110. tor Inc the CPU including topics such as the CPU16 s DSP instructions and how they can be applied in a real system the architectural differences between the M68HC11 s CPU and the CPU16 the CPU16 instruc tion set and the different addressing modes the difference between program and data space and the CPU16 s internal registers Initial stack pointer program counter IZ register and extension register values are fetched from boot ROM Other CPU resources that must be initialized include the exception vector table and the condition code register Also the memory map must be allocated 4 1 1 The CPU16 Memory Map and Bank Switching The CPU16 memory map is divided into 16 pages These pages are called banks Each bank is 64 Kbytes long for a total of 1 Mbyte of available memory If the memory is further divided into program and data space 2 Mbytes are available 1 Mbyte for program space and 1 Mbyte for data space However to accomplish this the function code pins must be externally decoded 4 1 1 1 The Memory Map Assuming combined program and data space the CPU16 can address 1 Mbyte of memory Because the MCU has 24 address lines the memory map begins at address 000000 and ends at FFFFFF However when the CPU is driving the address bus ADDR 23 20 follow the logic state of ADDR19 This means that if the CPU drives ADDR19 high then ADDR 23 20 will also be high Likewise if the CPU drives ADDR19 low then ADDR 23 20 will a
111. tor or be configured as I O pins The DSACK pins along with other bus control signals are configured as I O pins by driving DATA8 low during reset or by programming the appropriate CS PAR bits 2 Multiple chip selects with different wait states are responding to the same address it does not matter whether the chip select pins are connected to anything Whether or not multiple chip se lects respond to the same address is determined by both the base address and the block size in the associated chip select base address register CSBAR 3 The MCU sees only base addresses that lie on a word boundary of the block size It will interpret each base address as an address that is on a word boundary This will cause an incorrectly pro grammed chip select circuit to match on an unexpected address An example of how to deter mine if chip select circuits are programmed correctly is shown below A On a sheet of paper make a table with four columns as shown in Table 8 Initialize the base address and option registers then look at all of the base address and option registers Fill in the appropriate cell in the table with the value in the corresponding option register and base address register In addition fill in the BLKSZ cell with the block size indicated by the last three bits of the base address register Table 9 shows block size values B Compare the base address register values to see if any overlap In addition to checking the actual values in
112. uency In high frequency applications C1 and C2 are usually equal How ever in low frequency applications C1 can be smaller than C2 about 5 pF to provide a higher voltage at the EXTAL input A wider voltage swing at this input will result in lower power supply current Usually the actual capacitances will be smaller than the intended capacitances since circuit and layout capaci tances add to the values of C1 and C2 Inverter The inverter is inside the MCU It provides the 180 degree phase shift necessary for oscil lation Crystal The crystal is made of piezoelectric quartz It must be a good quality crystal that is capable of suppressing harmonics and overtones and quickly locking onto the fundamental frequency If a par ticular crystal type or brand is prone to starting with overtones or harmonics don t use it No amount of circuit design can compensate for a bad or poor quality crystal The MCU is designed to use a 32 768 kHz AT cut crystal to produce an 8 389 MHz CLKOUT signal The frequency of the internal clock can be increased or decreased by writing to the SYNCR register a ee a e l MC68HC16Z1TUT D For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Figure 3 shows clock circuitry for a Daishinku DMX 38 32 768 kHz crystal but the circuit will work for most other 32 768 kHz crystals also To use other crystal values the allowable range is 20 kHz 50 kHz consult the crystal
113. ull up circuit is weak so it is best to follow the recommendations in 2 1 Using Data Bus Pins to Configure the MCU For example to design a system that uses 16 bit boot memory built from two 27C512 byte EPROMs connect the chip select and output enable lines of the EPROMs to the CSBOOT line Also connect MCU address lines ADDR 1 16 to address lines 0 15 of the memories Do not use ADDRO of the MCU This system will be word accessible only In general the MCU cannot make byte writes to word memory selected by CSBOOT This lack of byte write capability is not much of a practical limitation since the CSBOOT signal is generally used for read only access and all CPU32 instructions must be word aligned However if byte write capability is re quired the SIZ and CSBOOT signals can be used to generate high byte and low byte chip select signals The only other way to modify individual bytes is to use word moves being careful to write the original data back to the unchanged byte 2 9 3 Using Chip Select Signals to Enable External Memory Chip select signals can be configured for 8 bit or 16 bit ports To use an 8 bit memory connect the memory element s data lines to the upper half of the MCU data bus DATA 15 8 The MCU reads and writes an 8 bit port on the upper half of the data bus During write cycles data is echoed on the lower half of the data bus as well Connect address line ADDRO of the MCU to AO of the memory An example
114. ve driver A circuit to perform this function is shown in Figure 1 This circuit uses a 3 state buffer such as a 74HC244 non inverting octal driver and meets the 5 ns hold time requirement While this method does require external circuitry it is recommended when high levels of noise may be encountered or when high reliability of operation is an overriding concern Tie 74HC244 inputs high or low respectively so that the desired logical values will be driven to the in dividual data bus pins when the output enable OE pin is driven low The OE will be driven low when the following three conditions are met RESET is low data strobe DS is high and read write R W is MC68HC16Z1TUT D For More Information On This Product Go to www freescale com Freescale Semiconductor Inc high Conditioning RESET with R W and DS ensures that writes to external memory will be completed before the 74HC244s are enabled Otherwise if an external RESET signal was applied during a write to external memory and was not conditioned with R W and DS the 74HC244s would turn on during the write and cause data bus contention gt Ni om D iS TIE INPUTS 3 HI OR LO e AS NEEDED EE S gt INS OF OUT8 gt D8 MC68HC16Z1 gt NI oun gt D7 e e 74HC244 R AS NEEDED e gt INS OE OUT8 _ D RESET DS DA BCE 5V 5V 8202 10KQ 10KQ 332TUT DAT PIN RESET
115. vendor for analysis of the crystal components needed C RS ae 330KQ XTAL D 10MQ EXTAL c2 22 PF Vss RESISTANCE AND CAPACITANCE BASED ON A TEST CIRCUIT CONSTRUCTED WITH A DAISHINKU DMX 38 32 768 KHZ CRYSTAL SPECIFIC COMPONENTS MUST BE BASED ON CRYSTAL TYPE CONTACT CRYSTAL VENDOR FOR EXACT CIRCUIT 332TUT XTAL CONN 1 Figure 3 System Clock with a 32 768 kHz Reference Crystal For the most accurate oscillator frequency use the Pierce version of the crystal rather than the series resonant version with C1 and C2 values to match the specified load capacitance of the crystal As a side note start up time is inversely proportional to frequency A 32 kHz crystal may take several hun dred milliseconds to start up Be aware all crystals are not created equal nor are they close In fact there are several different types of tuning elements that can be used for low frequency oscillators in the range of 32 768 kHz While there are many characteristics of the various tuning elements that can be precisely measured there are other characteristics that are extremely difficult to measure and express in a useful way Maximum power dissipation of a crystal is generally specified by the manufacturer of the device Crystal power dissipation is a function of the reactance of the combined input and output capacitance of the internal amplifier of the microcontroller and of the external circuit components including the crystal its
116. void spurious interrupts each module requesting interrupts must have a unique non zero value in the IARB field The CPU treats ex ternal interrupt requests as SIM interrupts 4 2 2 Clock Synthesizer Control Register SYNCR SYNCR controls clock frequency clock signal usage during low power stop and frequency of the 6800 bus clock output ECLK Configure SYNCR as follows Set frequency control bits W X Y to specify frequency 1 Select action to be taken during loss of crystal RSTEN bit activate a system reset or operate in limp mode 2 Select system clock during LPSTOP STSIM and STEXT bits 3 If using the ECLK select the ECLK frequency EDIV bit 4 2 3 System Protection Control Register SYPCR SYPCR controls the software watchdog which is enabled out of reset This means that unless the SWE bit is cleared a program must write the appropriate service sequence to the software service register SWSR in a defined period or the MCU will reset each time the watchdog times out Disable the software watchdog if desired by clearing the SWE bit 1 If the watchdog is enabled perform the following actions A Choose whether to prescale the software watchdog clock SWP bit B Select the time out period SWT bits 2 Enable the double bus fault monitor if desired DATAFE bit or HME bit 3 Enable the external bus monitor BME bit if desired 4 Select the time out period for bus monitor BMT bits For More Informa
117. wo ports resides in the port data register called PDR in older man uals and PORTADA in newer manuals In order to use the ADC as an analog to digital converter the user must be sure to properly connect the following pins Vou and Vo These are the analog reference voltages that are connected to the analog reference pins The ADC uses them as a reference to determine the range of voltage it can expect on the analog input pins Because they are separated from the analog power supply pins Vppa and Vssa they can and should be connected to regulated and filtered supplies to allow the ADC to achieve its highest degree of accuracy Any noise on these two pins will translate into errors in the conver sion results The use of bypass capacitors or low pass filtering is recommended In addition Vay must be less than or equal to Vppa and Vp must be greater than or equal to Vssa Vppa and Vssa These pins supply power to the analog circuitry associated with the sample am plifier and RC DAC array Other circuitry in the ADC is powered from the digital power bus pins Von and Vase Dedicated power for the RC DAC array is necessary to isolate sensitive analog cir cuitry from noise on the digital power bus The power to Vppa and Vsga should be as quiet as pos sible Analog input pins AN 0 7 These are the actual input pins to the converter The input to these pins must be within the range specified by Vay and Vo The ADC converts the analog input on

An Introduction to the MC68HC16Z1

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