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User manual IBS SUPI 3 UM - Digi-Key

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3. Table 1 4 Mechanical dimensions of the QFP 100 housing Millimeters Inches Millimeters Inches DIM Min Max Min Max DIM Min Max Min Max A 19 90 20 10 0 783 0 791 P 0 325 BSC 0 013 BSC B 13 90 14 10 0 547 0 555 Q 0 7 0 7 2 80 3 40 0 110 0 134 R 0 25 0 35 0 010 0 014 D 0 22 0 38 0 009 0 015 5 22 95 23 45 0 904 0 923 2 55 3 05 0 100 0 120 T 0 13 0 005 F 0 22 0 33 0 009 0 013 U 0 0 0 65 BSC 0 026 BSC V 16 95 17 45 0 667 0 687 H 0 25 0 010 0 40 0 016 J 0 11 0 23 0 004 0 009 x 1 60 REF 0 063 REF K 0 73 1 03 0 028 0 040 Y 0 58 REF 0 023 REF L 12 35 REF 0 486 REF Z 0 83 REF 0 033 REF M 5 16 5 16 AA 18 85 REF 0 742 REF N 0 11 0 17 0 004 0 007 1 12 CONTACT 6025_en_03 Structure and basic wiring 1 3 3 Signal description Table 1 5 Signal description Designation Meaning Type OSC1 Oscillator input OSC OSC2 Oscillator output OSC C3 Clp C2 Configuration inputs Cl C1 for the MFP interface CI CO CI KM1 Configuration inputs CI KMO for the INTERBUS interface RGNDA ID12 IDO Identification code setting data length entry CI MFP15 MFPO Multi function pins BDp SLxx Control line ID data cycle SLO1 MAUWH Select line IN forward path MAU warning forward path ST SLO2 Select line OUT forward path B12 SLI1 Sel
4. MFP n Assignment 0 x 1 x 2 DI Incoming data line 3 x 4 x 5 x 6 DO Outgoing data line 7 x 8 ALARM Alarm output 9 X 10 X 11 X 12 X 13 X 14 X 15 X X Not to be used The INTERBUS master can set the alarm output via a corresponding service 6025 en 03 PHOENIX CONTACT 3 3 IBS SUPI 3 16 bit output 3 3 input output mode In the 16 bit output mode the INTERBUS OUT data of the first two internal OUT registers is available in parallel at the multifunction pins and can be connected directly to the application Data is updated synchronously with the INTERBUS cycle The outputs are 4 mA CMOS drivers If no additional I O points to be used the ToExR2 and FromExR pins are to be connected Should additional IN data be used external shift registers are to be connected between pins ToExR1 and FromExR OUT data can be expanded by the connection of external shift registers to the 2 pin see also Section Register expansion on page 3 25 Table 3 4 Configuration 16 bit output C3 C2 C1 co MFP mode 1 0 0 1 16 bit output Table 3 5 Assignment of the MFP interface for the 16 bit output mode MFP n Assignment Significance 0 Byte0A 0 28 1 0 1 29 2 0 2 210 3 Byte0A 3 2 4 0 4 212 5 ByteOA 5 213 6 0 6 214
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6. 3 14 CIKEXH Eee isn an 3 25 GIOCK dit aided ine Pao dece Be 1 16 Command register 2 3 15 ame 3 34 Control signals siseasi nee 3 7 D tec real 3 7 Data CY ClO a 3 14 Data length 1 19 1 20 A 7 Data register with IBS SRE 1 3 26 Data Width 1 20 A 7 Disable clear eiii lee 3 17 D SUB 15 er 2 1 D SUB od uie eR RE ERREUR RR ERR 2 8 E Electrical isolation 2 2 2 8 Encoding of the data length 3 18 Encoding of the data 3 18 External shift registers 3 25 F Failure of the I O voltage 3 20 Field of application esee 1 8 H Housing type uere nen 1 3 Ho sing TYPOS uec oeil 1 3 VO aCCOSS i iei ata ee ad 3 16 Identification cycle 2 3 14 Identification 0 422 111 1 19 IN data 2 3 4 INTERBUS 3 16 INTERBUS 1 18 INTERBUS reset 3 14 INTERBUS watchdog 2 2 3 16 Interrupt logic est 3 11 Invalid data cycle 3 14 L Bayer 3 14 3 17 Eocal DUS e
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10. 1 9 Table 1 4 Mechanical dimensions of the QFP 100 housing 1 12 Table 1 5 Signal description deb qe let see 1 13 Table 1 6 Clock tiMINg eee eo 1 17 Table 1 7 Configuration of the INTERBUS 1 18 Table 1 8 Configuration of the MFP 2 1 19 Table 1 9 ID code data 1 19 Section 2 Table 2 1 8 wire local bus configuration een 2 1 Table 2 2 Pin assignment of the 15 pos D SUB INTERBUS local bus GOFIDGCIOF eite ote pipe Pee nne HERE 2 2 Table 2 3 2 wire local bus configuration 2 2 Table 2 4 Remote bus 2 3 Table 2 5 Pin assignment of the 9 pos D SUB INTERBUS remote bus CONMMOCION M PE 2 3 Section 3 Table 3 1 Operating modes of the MFP 3 1 Table 3 2 Configuration BK module with local bus 3 2 Table 3 3 Configuration BK module with 2 wire 3 3 Table 3 4 Configuration 16 bit 3 4 Table 3 5 Assignment of the MFP interface for the 16 bit output mode esssee eme 3 4 Table 3 6 Configuration 16 bit input essen 3 5 Tabl
11. Weitergabe sowie Vervielfaeltigung dieser Unterlage teilung oder Gebrauchsmuster Eintragung vorbehalten tung und Mitteilung ihres Inhalts nicht gestattet nicht ausd ten zu Schadenersatz Phoenix Contact application remotebus terminal module a Interface 5 45V GND 5 vey s deii 3 3 gt L 8 5 5v a OUT 3 8 2 2 1 GNDI 5 GND H 1 GND 5 5VI E g 8 5 en 2 se 8 es HCHL2601 2 Y i p ae osc1 5 2 8 DID gt H Voutj K 1 DI2 3 az TE CKI2 lt g GND E pure os SLI2 lt 44 male e 1 5 CRIL CRI2 2 outgoing Interface 8 vec branch HEPL260i 7 gt pol 525 gt E ge
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13. Identification cycle Valid data cycle Invalid data cycle Check sequence Layer2_To Command register 0 reserved 5191 013 Figure 3 7 Assignment of the interrupt event register 6025_en_03 PHOENIX CONTACT 3 13 Explanation of the interrupt sources INTERBUS inactive PCP send PCP receive INTERBUS reset INTERBUS cycle counter Identification cycle Valid data cycle Invalid data cycle Check sequence Layer2_To A watchdog which monitors INTERBUS activity and which can be parameterized via the SET I register elapsed This means that user data was not updated during this time This event also resets the Bus Active BA diagnostic signal INTERBUS data registers are not reset see Section 3 4 2 Interrupt source for PCP communication If this interrupt is present the CPU can write a new communication word to the SUPI 3 chip The SEND interrupt identifies the end of a data or ID cycle Interrupt source for PCP communication If this interrupt is present the CPU can read a new communication word from the SUPI 3 chip Interrupt receive identifies the end of a valid data cycle with IDLE bit 1 This INTERBUS device has been setto the reset state due to a fatal error or by the master using the INTERBUS reset Alarm Stop Request command at the master This event should always be evaluated The INTERBUS data registers are reset An 8 bit counter loaded via the register wi
14. 3 19 Flow chart for the initialization with created Not Ready ID COD Crs erp 3 22 Assignment of the IB state register 22221121 3 23 No register expansion 3 25 Register expansion with SRE 1 esee 3 26 Expansion of the internal SUPI 3 registers by means of register teinte ue tle tudo sod en 3 26 16 bit I O device with 2x8 bit IN register expansion 3 27 16 bit I O device with 2x8 bit OUT register expansion 3 27 48 bit I O device with 4x8 bit IN register expansion 3 28 48 bit I O device with 2x8 bit IN and 2x8 bit OUT register eXpansion 3 28 32 bit device with 4x8 bit IN register expansion 3 29 6025 en 03 PHOENIX CONTACT C 1 IBS SUPI 3 Figure 3 20 32 bit device with 2x8 bit IN and 2x8 bit OUT register EXPANSION een cn 3 29 Figure 3 21 Timing diagram for register expansion 3 30 Figure 3 22 Timing diagram in 1 em 3 30 C 2 PHOENIX CONTACT 6025_en_03 C2 List of tables Section 1 Table 1 1 Different e ettet pe 1 3 Table 1 2 General 1 8 Table 1 3 QFP 100 pin table eet C
15. 14 Byte0E 6 26 15 Byte0E 7 27 MSB ByteOA Output byte ByteOE Input byte Please refer to the Appendix for application examples 3 6 PHOENIX CONTACT 6025 en 03 Application interface 3 4 uP microprocessor access mode Inthe uP access mode it is possible to address the SUPI 3 chip from a microprocessor like an I O component 0 RAM For this purpose the SUPI 3 has an 3 bit bidirectional data bus D7 to DO a 4 bit address bus A3 to AO the active low control signals Chip Select CS ENCR ENDRR ENDRW Read RD and Write WR and an active low interrupt request line IRQ Table 3 10 Assignment of the MFP interface for the uP access mode MFP n Assignment 0 AO 1 Al 2 A2 3 A3 4 RD 5 6 CS 7 IRQ 8 DO 9 D1 10 D2 11 D3 12 D4 13 D5 14 D6 15 D7 Please refer to the Appendix for application examples MFP interface timing The interface timing is suitable for both Intel and Motorola based bus access The signal CS and WR or CS and RD are connected internally such that even an inactive signal is sufficient to stop the access 6025 en 03 PHOENIX CONTACT 3 7 IBS SUPI 3 Write access ICS 0 9 d T 00 07 Valid data 51914007 Figure 3 1 MFP interface timing write access Table 3 11 MFP interface timing write
16. 6025_en_03 PHOENIX CONTACT 1 9 IBS SUPI 3 Table 1 3 QFP 100 pin table continued Pin No Pin Name Pin No Pin Name Pin No Pin Name 31 14 66 Vss 100 ToExR1 32 MFP13 67 ID3 33 n c 68 ID2 34 MFP12 69 101 35 11 a 55 lt 2 52 A Gok m mc 97 nO900050500 20000 2020 Error 80 75 70 65 60 fe 011 2 LBRes ModAck 85 RBDA 45 MFP5 Vss MFP6 CKI1 Vss Vdd MFP7 vs Vad 55 Hx INTERBUS LaOuC MFP8 LalnDa m ee MFP9 LaOuD 6 10 CLKEXR MFP11 CRO2 MFP12 ResReg ToExXR2 MFP13 ToExR1 71 1 5 10 15 20 14 T 25 22 lt lt m gt 5191A004 OZ zc 2 0 0 C ado x X Nye 882805 2848506850008 2822658 Figure 1 3 Pin layout the QFP 100 housing 1 10 PHOENIX CONTACT 6025 en 03 Structure and basic wiring 1 3 2 QFP 100 Quad Flat Pack nn SUPI3 INTERBUS Detail 5191A003 I 0 10 0 004 Detail C I Detail C Detail B Figure 1 4 Mechanical dimensions of the QFP 100 housing original dimension millimeters 6025_en_03 PHOENIX CONTACT 1 11 IBS SUPI 3
17. Allrights reserved in the event of the grant of a patent or the registration of a utility model or design Postfach ges den Fall der Patenter Alle Rechte fuer teilung oder Gebrauchsmuster Eintragung vorbehalten Phoenix Contact GmbH amp Co 32819 Blomberg 1341 OSZ_16MHz ResU application ResReg LaOuD C1kExR 2 LaInD SUPT 23 InterBus FromExR HY register expansion for digital DATA DATA DATA DATA IN 12 DATA DATA IN 10 DATA IN 9 DATA IN 8 DATA IN 7 DATA IN DATA IN 5 DATA IN 4 DATA IN 3 DATA IN 2 DATA IN 1 DATA IN 0 61 5 C2 LOAD DATA_OUT_9 DATA_OUT_8 DATA_OUT_ DATA_OUT_6 DATA_OUT_4 DATA_OUT_3 DATA_OUT_1 DATA OUT 0 DATA OUT 15 MSB DATA OUT 14 DATA OUT 12 DATA OUT 11 DATA OUT 10 LSB Attention Note that the expansion register are to be located in the immediate vicinity of IBS SUPI If the 1 and ToExR2 signals are not buffered it is only possible to use 4 expansion ICs due to the capcitive load Masstab j igh Anzahl Blatt gepr register expansion for digit Blaetter Nr version 1 1 01 08 96 Lutz PHCENIX Z Nr Anzahl Kopie CONTACT Nr Datum Name Rev Aenderung Datum Name Pruefdatum
18. register Relative write address 6 MSB LSB 07 bs pe 01 vo Switch ID length 0 External 1 Internal Switch MFP CONF 0 External 1 Internal MFP mode Processor watchdog 0 Inactive 1 Active with filter time 13 Switch ID code 0 External 1 Internal Reserved 5191018 Figure 3 9 Assignment of the SET II register 1 For the internal ID code setting bits DO and D1 must be set to internal Switch ID length This bit allows to separate the hardware connections of pins 1012 to ID8 and to reroute them to bits D7 to of the register The bit must always be considered together with Switch ID code bit 6 see below Switch MFP CONF MFP allows to separate the hardware connections of pins C3 to CO and to map them to the table with bits D4 to D2 of the SET II register 6025_en_03 PHOENIX CONTACT 3 19 IBS SUPI 3 MFP CONF mode Processor watchdog Switch ID code Example In the uP modes of operation the internal SUPI 3 register length can be set using this table The StatErr pin can be used for example to indicate a breakdown of the I O voltage in the slave or the release of an external processor watchdog The microprocessor can select whether this pin is active as I O error with a filter time of tf 270 ms or as input for a uP watchdog with a filter time of tfs 2 5 us by bit 5 in the SET II register Setting the bit res
19. 3 2 Bus terminal module mode A bus terminal BK module always starts a new level in the INTERBUS system A new level can be a remote bus or a local bus A maximum of 16 levels FW 4 0 or later is permitted BK modules are always remote bus devices A BK module connects the INTERBUS local bus devices in the field with the INTERBUS remote bus The BK module makes voltage supply 9 V 1 A available for the INTERBUS logic of the local bus devices The BK module can also connect or disconnect the connected remote bus or local bus branch to or from the rest of the network when requested by the INTERBUS master 6025_en_03 PHOENIX CONTACT 3 1 IBS SUPI 3 A distinction is made between a standard BK module and a BK module Bk with I O points BK I O The standard BK module fulfills the functions described above However it has no I O points so that a data length of 0 must be set Since no external I O points are implemented the FromExR input pin is to be connected to the TOExR1 output In addition to the BK functions described above the BK modules with I O points can loop external in I O points between pins 1 and FromExR see also Section 3 5 The LBST message input is used in these operating modes to recognize a connected local bus or remote bus branch cable BK module with 8 wire local bus branch Table 3 2 Configuration BK module with local bus branch C3 c2 C1 1 0 0 0 BK module 8 wire
20. AO The address area assignment is backward compatible with the SUPI 2 chip Table 3 14 Address area assignment of the SUPI 3 Rel address Write register Read register 0 IB IN byte 0 MSB byte 0 MSB 1 IB IN byte 1 IB OUT byte 1 2 IB IN byte 2 IB OUT byte 2 3 IB IN byte 3 IB OUT byte 3 4 Interrupt enable Interrupt event 5 Set Interrupt event 6 Set Il Reserved 7 ID code low byte IB state 8 Cycle write Cycle read 9 Processor message register Processor command register 10 IB IN byte 4 IB OUT byte 4 11 IB IN byte 5 IB OUT byte 5 12 IB IN byte 6 IB OUT byte 6 13 IB IN byte 7 LSB IB OUT byte 7 LSB 14 Interrupt enable Il Reserved 15 Test mode Test state All registers of the SUPI 3 chip have the default value 0 The INTERBUS IN OUT data registers are set to their initial value 0 by ResU and INTERBUS reset All other registers are set to 0 only during power up reset ResU The contents of the cycle read register is mapped to the reserved read registers relative addresses 6 and 14 To maintain compatibility with future protocol chips these two registers should not be used NOTE The test mode and test state registers relative address 15 are used fora production test of the chip and should not be used for applications By writing 40 to the test mode register it is possible to mirror the WRITE registers to the READ registers so the
21. Byte1E 3 23 12 Byte1E 4 24 13 Byte1E 5 25 14 Byte1E 6 26 15 Byte1E 7 27 il Please note that the lower byte of the data word is on the MFP pins 8 to 15 and the higher byte is on the MFP pins 0 to 7 6025_en_03 PHOENIX CONTACT 3 5 IBS SUPI 3 8 bit input and 8 bit output Unlike the two modes described above this mode does not represent a 16 bit but an 8 bit device The MFP interface is configured in such a way that both 8 bit input as well as 8 bit output is possible simultaneously without register expansion The outputs are 4 mA CMOS drivers Please observe see also Section Identification code that the INTERBUS controller boards support the data length of 1 byte 8 bits only as of firmware version 4 0 If no external expansion is necessary the TOExR2 and FROMEXR pins are to be connected see Section Register expansion on page 3 25 Table 3 8 Configuration 8 bit input and 8 bit output C3 C2 C1 CO MFP mode 1 1 0 1 8 bit input and 8 bit output Table 3 9 Assignment of the MFP interface for the 8 bit input and 8 bit output mode MFP n Assignment Significance 0 ByteOA 0 2 LSB 1 0 1 2 2 0 2 22 3 Byte0A 3 23 OUTPUT 4 0 4 24 Byte 5 Byte0A 5 25 6 Byte0A 6 26 7 Byte0A 7 27 MSB 8 Byte0E 0 2 LSB 9 Byte0E 1 21 10 Byte0E 2 2 11 ByteOE 3 23 INPUT 12 ByteOE 4 2 Byte 13 ByteOE 5 25
22. ENCR D i as 27 1 157 27 ujo 2 IDRR EN ENDRR 25 25 ENDRW ENDRW ENDRW REL 37 1802 max 6 1 37 11806 ResReg 33 ResReg 33 ResReg ToExR2 gt i spr spo 25 21 spr spo 33 22 snr spo 2 ClkExR gt 20 2 20 36 20 36 X raoun 2 raoun 2 raoun 42 42 42 ResReg gt 4 gt ResU LaOuD gt Lalnp gt s FromExR lt Attention Note that the expansion register are to be located in the immediate vicinity of IBS SUPI Masstab Anzahl Blatt gepr register expansion with IBS SRE 1 Bigetterts Nn gezeil version 1 1 Lutz PHOENIX Z Nr Anzahl Kopi CONTACT 3 3 Et Kopien Datum Name Rev Aenderung Datum Name Pruefdatum gepr tung und Mitteilung ih nichtausdruecklich zugestanden ten zu Schadenersatz Phoenix Contact teilung ode VW are forbidden without and giving it to others and the use 32819 Blomberg contents thereof served in the event of the grant of a patent All rights registration of a utility model or design 1341 or the Postfach communication of the express authority Offenders are liable to the payment of dama Copying of this document or ges soweit handlungen verpflich den Fall der Patenter fue Zuwide Eintragung vorbehalten
23. IBS SUPI 3 to be set using CO C3 and possibly used external register must match the logic data length to be set using 108 1012 even if the chip was reconfigured with software afterwards see Section SET I register on page 3 16 and Section SET II register on page 3 19 A 8 PHOENIX CONTACT 6025_en_03 B Wiring examples The following applies for all wiring examples All resistors have a tolerance of 1 maximum All capacitors have a tolerance of 20 maximum Electrical isolation has to be at least 500 VAC Only components from the component reference list of the INTERBUS Club will be used The circuit diagrams were prepared with the greatest possible care Phoenix Contact does not guarantee the correctness of the circuit diagrams 6025_en_03 PHOENIX CONTACT 1 are forbidden without express authority Offenders are liable to the payment of dama 32819 Blomberg and giving it to others and the use served in the event of the grant of a patent be rights 1341 no connector must All or the registration of a utility model or design communication of the contents thereof Postfach Copying of this document or ges 906 ans6as remote IN connected conductively wizh PE The soweit handlungen verpflich den Fall der Patenter Zuwide Alle Rechte fue GmbH amp Co uecklich zugestanden Weitergabe sowie Vervielfaeltigung dieser Unterlage teilung
24. Not Ready ID codes subsequent initialization of the SUPI chip is easily possible for a uP application It is irrelevant when the SUPI is initialized The bus master can operate the bus in any case and expects the new configuration of devices not yet initialized This function is supported by firmware version 4 0 x or later For microprocessor applications two Not Ready ID codes are defined not Ready ID code Remote bus device ID 38hex Local bus device ID 78hex If one of the two codes is applied to pins ID7 IDO new functions are internally active 1 Thecreated ID code is valid after power up 2 The data length is set to zero inside the chip 3 The data length zero is entered in the ID register independently of the code at pins ID12 ID8 4 After the microprocessor has written the Set Il register address 6 further access to all initialization registers write address 5 6 and 7 is disabled 6025 en 03 PHOENIX CONTACT 3 21 IBS SUPI 3 Example RESET 4 UNLOCKED Write to Registers 5 6 and 7 Write to can be written registar register 7 Write to register 6 LOCKED Registers 5 6 and 7 can no longer be written 5191A017 Figure 3 10 Flow chart for the initialization with created uP_Not_Ready ID code The SET II register can only be written once after RESET UNLOCKED state The registers with write addresses 5 and 7 must therefore be written before In this way initializa
25. T ResReg gt t 8 2 LN a a 7705 E RESin RES x E sensern RES gt ResU y 7 Please observe layout 2 Gn notes of the manufacturer ToExR2 gt Other connector types may be used depending on the device type FromExR 6 Please observe layout notes of the manufacturer and the chapter clock generation of the IBS SUPI3 manual pales GND GND Masstab Anzah Remotebus with optical isolation typ 1 E gezeil version 2 0 Lutz PHCENIX Anzahl Kopie CONTACT 1 1 Z Nr Kopien Nr Datum Name Rev Aenderung Datum Name Pruefdatum gepr S 5 D 3 O 3 8 i 8 8 15 a als 5 5 i o 5 R als EX 4 55 g 8 q Bye of 7 a a 8 5 gt _ x 5 515 Alg ak gt E A gt 0 Yo af
26. Timing for register 3 30 TOEXR 3 25 2 uir REL REP EORR 3 25 TR diagnostic 2121 3 33 V Valid data 2 4 1 3 14 W Watchdog C 6 PHOENIX CONTACT 6025 en 03
27. Unit indicate a critical but still functioning transmission path MAU warnings can only be used in dedicated 2 wire operation as MAU warning input filtered with 3 520 us See also Diagnostic inputs and outputs on page 3 32 s These inputs require a hardware connection and the levels applied must not be modified during bus operation See Section Overview on page 2 1 and Section Overview on page 3 1 The filtering causes the signals to have the same state for at least tti before a modified signal state becomes effective internally Explanation of cell types BDp Bidirectional with Schmitt trigger inputs with internal pull up resistor 50 kQ typical and 4 mA driver outputs Cl CMOS input Clp CMOS input with internal pull up resistor 50 kQ typical ST Schmitt trigger input STp Schmitt trigger input with internal pull up resistor 50 kQ typical B2 2 mA output B12 12 mA driver output OSC Oscillator cell 6025_en_03 PHOENIX CONTACT 1 15 IBS SUPI 3 Clock supply 1 4 Basic wiring 1 4 1 Clock initialization The SUPI 3 has an on chip oscillator Therefore for applications in which the 15 MHz clock required by the SUPI is of no further use it is sufficient to use a 16 MHz quartz The quartz is connected to the OSC1 and OSC2 pins With the two capacitors that are connected from OSC1 and OSC2 to ground the quartz forms a three point oscillator To set the working point of the on chip oscillator 1
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29. diagram in detail 3 30 PHOENIX CONTACT 6025 en 03 Application interface Table 3 20 Timing for register expansion Symbol Explanation Time ns Minimum Maximum 11 LaOuD length 18000 12 LalnD length 8000 t3 OUT data valid after rising LaOuD edge 66 t4 IN data valid before rising LalnD edge 19 t5 CLKExR length 2000 t6 1 valid after rising CIKExR edge 1000 t7 ToExR2 valid after rising edge 62 5 8 Serial data valid before rising edge 1125 All outputs loaded with 30 pF The data at the FromExR input is always taken over with the falling edge of CIkExR The ResReg signal has no time reference to the other signals of the register expansion For register expansion it must be ensured that the CIkExR signal is not deformed by loading with external capacitances and thus shifted excessively behind is buffered ToExR2 must also be buffered because of the signal shift In this case the runtimes to 2 are less critical than in the cycle line itself The times specified for the components in the shift registers used must also be considered Please refer to the Appendix for application examples 6025 en 03 PHOENIX CONTACT 3 31 IBS SUPI 3 cc BA 3 6 Diagnostic inputs and outputs The SUPI 3 protocol chip has different diagnostic inputs and outputs which simplify the location of error sources within the INTERB
30. diverted to the return path by circuitries inside the chip 2 2 PHOENIX CONTACT 6025 en 03 INTERBUS interfaces 2 3 Remote bus connection Table 2 4 Remote bus configuration KMO KM1 CKO1 RGNDA INTERBUS interface mode 1 1 0 0 2 wire remote bus 500 kbits Fiber optic transmitters and receivers or RS 485 drivers are pre connected to the INTERBUS interface The two INTERBUS interfaces consist only of data lines DO1 DI1 DO2 and DI2 All other input signals of the two interfaces are to be connected to alow potential The incoming bus interface is equipped with optocouplers for electrical isolation The RBST pin is connected to pin 9 of the remote bus output connector Pin RBST recognizes the physical position of the device in the ring A low potential is connected externally to this pin via a resistor Pin 9 is jumpered to Vpp in the remote bus cable connector The RBST input is thus connected to high and SUPI 3 recognizes that it is not the last device in the ring Therefore it forwards its data to the following device in the ring Without output connector RBST 0 the outgoing interface is switched off and diverted to the return path by circuitries inside the chip By default 9 pos D SUB connectors are used for the remote bus When using other connectors make sure that RBST is high when the connector is connected and low when the connector is disconnected The following table lists the assignment
31. es Inhalts nicht gestattet Alle Rechte Gebrauchsmuste GmbH amp Co application microcontroller interface GAL20V8 350 10 1 80 32 2 3 19 18 1 cel XTALl PSEN 052 ALE EA P30 D RXD 9 ResU RST VPD P31 TXD CL IRQ SUPI P32 INTO P33 INTL P34 TO P35 RAM32KX8 100NS OSZ 16MHz ResU SUPE 5 InterBus 117 1111 444 Masstab Anzahl Blatt gepr uP Interface Blaetter gezeil version 1 1 01 08 96 Lutz EEEN Z Nr Anzahl CONTACT 4 4 GNI Kopien Datum Name Rev Aenderung Datum Name Pruefdatum gepr Weitergabe sowie Vervielfaeltigung dieser Unterlage tung und Mitteilung ih nicht ausdruecklich zugestanden ten zu Schadenersatz Phoenix Contact teilung ode are forbidden without express authority Offenders are liable to the payment of dama 32819 Blomberg and giving it to others and the use served in the event of the grant of a patent rights 1341 not be All or the registration of a utility model or design t communication of the contents thereof Postfach Copying of this document or ges onnector mus IN The remo Verwer Soweit handlungen verpflich den Fall der Patenter Zuwide Alle Rechte fue uecklich zugestanden GmbH amp Co
32. for the oscillator with new external circuitry The pad dimensions of the QFP 100 housing were modified so that chip requires less space 6025 en 03 PHOENIX CONTACT 1 5 IBS SUPI 3 Improvements compared to SUPI 2 Filtering of the quasi static inputs RBST LBST 270 ms CONF 35 ms StatErr 270 ms standard 2 5 us uP watchdog ResIN 520 us These signals also had Schmitt trigger input circuits Additional functions Increase of driver capability of the outputs ResReg CIkExR BA LD TR Error from 2 mA to 12 mA Watchdog for bus active is now reset for every valid ID or data cycle Start bit recognition A spike pulse lt 100 ns in the critical range is recognized as a start bit error Manufacturer mask identification Hardware version can be detected by the master Information is mapped to the INFO register of the ID send buffer Layer 2 timeout monitoring If LaOuD is not sent within a preset time process OUT data is reset and ResReg activated provided that the master has enabled the function uP ID code register Now the entire ID code IDO ID12 can be set by a microprocessor not Ready ID code If IDO to 107 38hex remote bus device or IDO to 107 78hex local bus device is set new functions are active internally StatErr can additionally be used to indicate activation of an external processor watchdog Processor command and alarm registers on address 9
33. gepr e forbidden without a and giving it to othersand the use 32819 Blomberg contents thereof ity Offenders are liable to the payment of dama gistration of a utility model or design 1341 Allrights reserved in the event of the grant of a patent communication of the Copying of this document express autho ges or the Postfach Verw soweit handlungen verpflich fuer den Fall der Patenter Zuwide Eintragung vorbehalten Rechte es Inhalts nicht gestattet Alle amp Co Gmb sowie Vervielfaeltigung dieser Unterlage Gebrauchsmuste Weitergab application register expansion with IBS SRE 1 ResU e OSZ 16MHz DATA ADDR C Bus GND GND GND 14 A0 31 0 14 A0 31 A0 14 A0 Lk 05 1 51 xi 32 115 i xi 32 1514 2 18 a 33 a2 18 x2 33 a2 18 19 A3 19 19 A3 A3 A3 SRE 1 SRE 1 SRE 1 10 34 00 4 loo ose 34 Do le ose 34 2 2 n Resu 2 2 1 1 Resu 2 a pi 39 InterBus D2 D2 D2 D3 4 D3 JRD 13 RD D3 4 13 RD D3 4 D3 RD 13 RD D4 C yan Da 8 EAR D4 8 4 02 R DS 9 55 05 9 D5 D5 9 5 06 10 26 06 10 26 D6 10 26 D6 ENCR D6 ENCR D6
34. input causes a message Peripheral error indication OBB1 qe for G4 The ModAck output can be used to acknowledge a set module error In the bus master the error is acknowledged with the following command Quit Peripheral Error This output will then be active once for 4 bit times 8 us The active high CONF message input is used to request a reconfiguration for the INTERBUS network If this input is not used it has to be statically connected to Vas The input is filtered The filter value is 35 ms Setting this input causes a message Reconfiguration request 1 for G4 Only for bus terminal module applications indicates the red LED an error in the connected branch The INTERBUS controller board activates this output with a corresponding command 07 14he for G4 The active high MAU inputs MAUWH incoming INTERBUS interface MAUWR outgoing INTERBUS interface MAUWS branch interface only for BK modules indicates the impairment of the transmission quality for e g optical or HF paths to a critical value however still performing a proper function The MAU of the corresponding interface incoming outgoing or branch must be able to evaluate the receive quality and to provide this as a digital signal to the corresponding input Setting this input causes a corresponding message 5340 for G4 This function is supported as of firmware version 4 0 x by the bus master The inputs are filtered in the MAU warning fu
35. liability and exemptions from liability do not apply in so far as liability must be assumed e g according to product liability law in cases of premeditation gross negligence on account of loss of life physical injury or damage to health or on account of the violation of important contractual obligations Claims for damages for the violation of important contractual obligations are however limited to contract typical predictable damages provided there is no premeditation or gross negligence or that liability is assumed on account of loss of life physical injury or damage to health This ruling does not imply a change in the burden of proof to the detriment of the user 6025_en_03 PHOENIX CONTACT IBS SUPI 3 Internet Subsidiaries Published by Statement of legal authority This manual including all illustrations contained herein is copyright protected Use of this manual by any third party is forbidden Reproduction translation and public disclosure as well as electronic and photographic archiving or alteration requires the express written consent of Phoenix Contact Violators are liable for damages Phoenix Contact reserves all rights in the case of patent award or listing of a registered design Third party products are always named without reference to patent rights The existence of such rights shall not be excluded How to contact us Up to date information on Phoenix Contact products and our Terms and Con
36. the protocol chip by intelligent modules even after the bus master has initialized the INTERBUS system This means when the INTERBUS master has detected a device with the uP not Ready ID code in the INTERBUS system it waits for the final configuration Therefore the same hardware can be used for very different applications Two message registers which realize a management channel to the INTERBUS master are another new feature The user has no direct access to the channel It is an option for future applications A new function has been implemented in the SET II register By setting bit 5 a uP watchdog input is activated Register 14 which was previously not available is used to enable additional interrupts In this way an interrupt can be generated when the master writes a processor alarm register or when the layer 2 watchdog has elapsed The new register 15 stores test functions for an engineering test during the development of the chip These functions are not important for the user Summary of the new IBS SUPI 3 chip features With its diagnostic features the diagnostic and report manager is the heart of the SUPI extensions It stores error localization information for the bus master new functions are supported by controller boards as of Generation 4 only firmware 4 0 or later The SUPI 3 is manufactured in a 0 5 uim technology This requires a more careful design and offers the use of additional quartz types
37. to 2 5 us See also Section SET II register on page 3 19 ModAck Acknowledge output for a recognized module error B2 This output is not used in standard applications CONF Reconfiguration request alarm input The inputis filtered STp with tf4 35 ms This input is connected to GND in standard applications RBDA Outgoing interface is disabled alarm output B12 LBDA TR Local bus disabled alarm output for BK PCP active B12 with uP with PCP protocol software BA INTERBUS active alarm output B12 Error Error in the connected local bus alarm output for BK B12 modules Signals for external register expansion CIkExR Clock for external shift registers B12 ToExR1 Data output for external shift registers without using the B2 SUPI 3 internal registers ToExR2 Data output for external shift registers after use of the B2 SUPI 3 internal registers FromExR Data input for external shift registers ST LaOuD Latch signal of output data shift registers gt latch registers B2 LaOuC Latch signal of control data shift registers gt latch B2 registers LalnD Latch signal of input data peripherals gt shift registers B2 ResReg Reset signal for external latch registers Can also be used B12 as the INTERBUS reset inactive alarm output ResU Initialization reset ST 5 V supply voltage Vss Ground 1 14 PHOENIX CONTACT 6025_en_03 Structure and basic wiring MAU warning bits Medium Attachment
38. 0 0 0 1 0 2 words 0 0 0 1 1 3 words 0 0 1 0 0 4 words 0 0 1 0 1 5 words 0 0 1 1 0 8 words 6025_en_03 PHOENIX CONTACT 1 19 IBS SUPI 3 Table 1 9 ID code data length continued 1012 1011 1010 109 108 Data length Firmware version 0 0 1 1 1 9 words 0 1 0 0 0 1 nibble 4 0 0 1 0 0 1 1 byte 4 0 0 1 0 1 1 3 bytes 4 0 0 1 1 0 0 Reserved 0 1 1 0 1 2 bits 4 0 0 1 1 1 0 6 words 3 2 0 1 1 1 1 7 words 3 2 1 0 0 0 0 Reserved 1 0 0 0 1 26 words 3 7 1 0 0 1 0 16 words 3 2 1 0 0 1 1 24 words 3 2 1 0 1 0 0 32 words 3 2 1 0 1 0 1 10 words 3 2 1 0 1 1 0 12 words 3 2 1 0 1 1 1 14 words 3 2 1 1 X X X Reserved The datalength is supported by the controller board bus master with the specified firmware version or later The datalengths 1 byte and 3 bytes are supported by the PC AT T board version 3 1 or later The data lengths supported by firmware version 3 2 or later are recognized by the PC AT T board by driver version 2 0 or later The length entry determines the data register length of the entire INTERBUS device that 1 means the total of registers configurable in the SUPI chip and additional external registers if any By default this length entry is wired via SUPI 3 pins ID12 ID8 by hardware The physical data length of the IBS SUPI to be set by CO C3 and possibly used external register must match the logic data length to be set by ID8 ID12 even if the chip was reconfigured w
39. 1 Its register length can be configured from one to six word s CLKExR ResReg LalnD LaOuD SUPI 3 ToExR1 FromExR ToExR2 6025A040 Figure 3 13 Register expansion with SRE 1 Expansion of the SUPI 3 internal INTERBUS data registers In this case the external shift registers are to be connected to the ToExR2 output and to be fed back to the FromExR input IN and OUT registers are possible CLKEXR ResReg LaOuD SUPI 3 ToExR1 FromExR ToExR2 E p External shift registers in steps of 16 bits Inputs and or outputs 6025A022 Figure 3 14 Expansion of the internal SUPI 3 registers by means of register expansion 3 26 PHOENIX CONTACT 6025 en 03 Application interface Implementing a 16 bit device with 16 inputs and 16 outputs Using the SUPI 3 as a 16 In this case a 16 bit shift register asynchronous and parallel loading is to be connected bit output between pins TOExR1 and FromExR CLKEXR MFP LalnD SUPI 3 ToExR1 2x8 IN shift FromExR ToExR2 registers 80254023 Figure 3 15 16 bit I O device with 2x8 bit IN register expansion Using the SUPI 3 as a 16 In this case a 16 bit shift register is to be connected to pin 1 bit input CLKExR ResReg MFP LalnD LaOuD SUPI 3 ToExR1 2x8 OUT shift FromExR ToExR2 registers 6025A024 Figure 3 16 16 bit I O device with 2x8 bit OUT register expansion Imple
40. 11 6F Analog INTERBUS Loop input and output modules Loop 115 73 Analog INTERBUS Loop input and Loop output modules with alarm AIO Loop 99 63 inputs and configuration outputs Profile compliant analog output modules PROFILE AO 121 79 Profile compliant analog input modules PROFILE Al 122 7A Profile compliant analog input output modules PROFILE AIO 123 7B ENCOM with input data ENCOM 102 66 ENCOM with input and output data ENCOM 103 67 Local bus devices with parameter channel Modules with parameter channel 2 PCP words PA channel 220 DC Modules with parameter channel 4 PCP words PA channel 221 DD Modules with parameter channel 1 PCP word PA channel 223 DF DRIVECOM 2 PCP words DRIVECOM 192 DRIVECOM 4 PCP words DRIVECOM 193 C1 DRIVECOM 1 PCP word DRIVECOM 195 C3 ENCOM 2 PCP words ENCOM 212 D4 ENCOM 4 PCP words ENCOM 213 D5 ENCOM 1 PCP word ENCOM 215 D7 Profile compliant modules 2 PCP words Profile PA channel 216 D8 Profile compliant modules 4 PCP words Profile PA channel 217 D9 Profile compliant module 1 PCP word Profile PA channel 219 DB Not with register latching local bus Special 120 78 Not for re initialization local bus Special 108 6 uP_Not_Ready for re initialization Loop Special 104 68 This ID code is only supported by INTERBUS masters of Generation 4 or later This ID code is only supported by INTERBUS mast
41. 25_en_03 Structure and basic wiring The permissible deviation applies to both short time as well as long time stability mw LIN 5191A006 Figure 1 6 Clock ratio for the clock of INTERBUS protocol chips Table 1 6 Clock timing Designation Name Symbol Min Typical Max Unit a Clock period tc 62 5 62 5 62 5 ns 6 25 6 25 ps b Pulse width tpH 25 31 25 37 5 ns high Pulse width low 25 31 25 37 5 ns 6025_en_03 PHOENIX CONTACT 1 17 IBS SUPI 3 Initialization Reset conditions D INTERBUS interfaces To put the SUPI 3 to a defined state after power up the initialization input ResU should be set to low during power up During operation ResU should be set to high The reset time must be at least 2 clock cycles 125 ns when the oscillator has settled and the voltage has been applied During the reset phase all outputs have a low level If in microprocessor applications the not Ready ID code is not used see Section ID code register on page 3 20 the SUPI 3 must be initialized before the INTERBUS master is started up The following conditions must be met for the INTERBUS reset at protocol chips of the 3rd generation SUPI 3 kernel voltage must be monitored in the specified range 5 V 10 Theresettime must be at least 2 clock cycles 125 ns when the oscillator has settled and the voltage is reached Thereset must not be inf
42. 7 Byte0A 7 215 MSB 8 Byte1A 0 20 LSB 9 Byte1A 1 21 10 Byte1A 2 2 11 Byte1A 3 23 12 Byte1A 4 24 13 Byte1A 5 25 14 Byte1A 6 26 15 Byte1A 7 27 Please note that the lower byte of the data word is on the MFP pins 8 to 15 and the higher byte is on the MFP pins 0 to 7 3 4 PHOENIX CONTACT 6025_en_03 Application interface 16 bit input In the 16 bit input mode the application can connect 16 parallel signals directly to the multi function pins The inputs are designed as CMOS Schmitt triggers Data is taken over synchronously to the INTERBUS cycle and transmitted to the INTERBUS master The data length can be expanded by external shift registers which are connected between ToExR2 and FromExR Should additional OUT data be used these external shift registers are to be connected to pin TOExR1 If no external extension is necessary pins ToExR2 and FROMEXR are to be connected see Section Register expansion page 3 25 Table 3 6 Configuration 16 bit input C2 C1 1 0 1 0 16 bit input Table 3 7 Assignment of the MFP interface for the 16 bit input mode MFP n Assignment Significance 0 ByteOE 0 28 1 ByteOE 1 29 2 Byte0E 2 210 3 Byte0E 3 211 4 Byte0E 4 212 5 Byte0E 5 213 6 Byte0E 6 214 7 Byte0E 7 215 MSB 8 Byte1E 0 20 LSB 9 Byte1E 1 21 10 Byte1E 2 22 11
43. AUTOMATION N User manual IBS SUPI3 UME Order No INTERBUS protocol chip IBS SUPI 3 OGD OO GD GD OGD OO OD 0 GDC INSPIRING INNOVATIONS AUTOMATION User manual INTERBUS protocol chip IBS SUPI 3 2010 12 09 Designation IBS SUPI3 UME Revision 03 Order No This user manual is valid for Designation IBS SUPI 3 QFP IBS CHIP Muster Order No 2746087 2746951 6025 en 03 PHOENIX CONTACT IBS SUPI 3 Please observe the following notes In order to ensure the safe use of the product described you have to read and understand this manual The following notes provide information on how to use this manual User group of this manual The use of products described in this manual is oriented exclusively to qualified electricians or persons instructed by them who are familiar with applicable standards and other regulations regarding electrical engineering and in particular the relevant safety concepts Phoenix Contact accepts no liability for erroneous handling or damage to products from Phoenix Contact or third party products resulting from disregard of information contained in this manual Explanation of symbols used and signal words hazards Obey all safety messages that follow this symbol to avoid possible This is the safety alert symbol It is used to alert you to potential personal injury AN injury or death DANGER This indicates a hazar
44. ExR CLKExR ResReg LalnD LaOuD SUPI 3 ToExR1 4x8bit external shift registers FromExR ToExR2 with inputs 6025A027 Figure 3 19 32 bit I O device with 4x8 bit IN register expansion 32 bit device with 16 OUT The internal SUPI 3 registers have been used as inputs and expanded by 2x8 bit IN and 32 IN addresses registers Parallel to this 2x8 bit shift registers with outputs are connected with TOExR1 CLKExR ResReg LalnD LaOuD SUPI 3 ToExR1 2x8bit OUT shift registers FromExR ToExR2 IN shift registers 6025A028 Figure 3 20 32 bit device with 2x8 bit IN and 2x8 bit OUT register expansion 6025_en_03 PHOENIX CONTACT 3 29 IBS SUPI 3 3 5 2 Register expansion interface timing Valid data cycle Invalid data cycle Valid data cycle ik tf lt gt gt gt T LaOuD 1 1 F LalnD Detail 1 Out 121 In CIKExR ToExR2 ToExR1 FromExR Detail 2 d 81914018 Figure 3 21 Timing diagram for register expansion ti 9 Detail 1 4 gt gt LaOuD LAInD Out New data t3 t4 MFP In A Valid data t 0 15 Detail 2 hi CkExR n nk ToExR2 N NH N 2 7 ToExR1 N NH X t6 FromExR M M 1 x 8 gt 6025 001 Figure 3 22 Timing
45. In a hybrid cable it carries additional 24 V for the power supply of the I O This limits expansion of the installation remote bus to a maximum of 50 m A local bus device is used where the physical distance to the next device is limited to less than 10 m e g switch cabinet level The synchronous 8 wire protocol with CMOS levels or the 2 wire protocol with CMOS levels is used for the local bus The entire logic required for the INTERBUS interface of a local bus device is supplied by the pre connected bus terminal module through a supply line in the bus cable This allows to operate the INTERBUS interface even if the voltage of the application breaks down When a local bus branch device fails the bus terminal module can disconnect the defective local bus branch from the network The rest of the network can continue operation 2 2 Local bus interface 8 wire protocol Table 2 1 8 wire local bus configuration KMO KM1 CKO1 RGNDA INTERBUS interface mode 0 0 1 8 wire local bus The RGNDA pin is to be set to high and the and 1 pins to low for local bus applications The bus signal pins of the SUPI 3 fulfill the INTERBUS specification of the local bus The 9 V supply of the local bus can be lowered to 5 V and monitored The active low output signal of a monitoring module is connected to the ResU initialization pin The RBST pin is connected to pin 4 of the local bus output connector The output connector of the IN
46. TERBUS cable contains a jumper Without an output connector and thus without a jumper RBST 0 the outgoing interface is switched off and diverted to the return path by circuitries inside the chip 15 pos D SUB connectors are used for the local bus The following table lists the assignments of the input and output interfaces 6025 en 03 PHOENIX CONTACT 2 1 IBS SUPI 3 Table 2 2 Pin assignment of the 15 pos D SUB INTERBUS local bus connector Pin Signal name of the incoming Signal name of the outgoing interface male connector interface female connector 1 9 9V 2 9V 9 3 Not used 5V 4 Not used RBST 5 SLI1 SLI2 6 CKI2 7 2 8 012 9 GND GND 10 GND GND 11 LBRes 12 SLO1 SLO2 13 CKO1 CKO2 14 CRO1 CRO2 15 DO1 DO2 Please refer to the Appendix for application examples Local bus interface 2 wire protocol Table 2 3 2 wire local bus configuration KMO KM1 CKO1 RGNDA INTERBUS interface mode 1 1 0 1 2 wire local bus The two INTERBUS interfaces only consist of the data lines DO1 DO2 012 and RBST All other input signals of the two interfaces are to be connected to a low potential The incoming bus interface can be equipped with optocouplers for electrical isolation The RBST signal is jumpered in the output connector to Without output connector RBST 1 the outgoing interface is thus switched off and
47. Table 1 8 Configuration of the MFP interface C2 C1 1 0 0 0 BK 8 wire local bus 0 0 1 1 BK I O module with 8 wire local bus 0 0 0 0 BK module 2 wire branch line 0 1 0 0 BK I O module with 2 wire branch line 1 0 0 1 16 bit output 1 0 1 0 16 bit input 1 1 0 1 8 bit input and 8 bit output 0 0 0 1 uP interface 1 byte 1 0 1 1 uP interface 2 bytes 1 1 1 1 uP interface 4 bytes 1 1 0 0 uP interface 6 bytes 0 0 1 0 uP interface 8 bytes Identification code Each INTERBUS device has an identification code ID code which can be read by the INTERBUS master controller in an identification cycle ID cycle The INTERBUS master obtains information from the identification code about the type of the device and its data register length in a data cycle The identification code consists of three groups An8 bitcodeis applied to pins 100 107 The INTERBUS Club has determined this code in the ID code specification depending on the functionality of the device An extract of these codes can be obtained from the Appendix Signals 1013 1015 are not available as pins They are reserved for the system management e g diagnostics and cannot be changed directly by the user PinsID8 ID12 specify the physical data length of the entire bus device It is to be set for each device according to the following table Table 1 9 ID code data length ID12 ID11 ID10 ID9 ID8 Data length Firmware version 0 0 0 0 0 0 words 0 0 0 0 1 1 word
48. US network The diagnostic inputs and outputs to be used depend on the physical location of the device within the INTERBUS network and its functions Certification of a module by the club requires that the status of diagnostic pins and power supply is indicated with LEDs Remote bus device Table 3 21 Diagnostic inputs outputs of a remote bus device Operating cc RD TR StatErr ModAck LD Conf Error mode ResReg RBDA LBDA Bus terminal M M M _ M M module Input output M M M PCP device M M M M Mandatory Local bus device Table 3 22 Diagnostic inputs outputs of a local bus device Operating mode TR cc BA StatErr ModAck ResReg Input output PCP device M Mandatory Explanation of diagnostic inputs and outputs The green CC Cable Check diagnostic LED is connected to the CMOS output ResReg of the SUPI 3 CC monitors the bus activity on Layer 1 of the incoming bus CC is active when the cable connection is good and the INTERBUS controller board is notin a reset state The CC LED becomes inactive after an INTERBUS reset or power up reset The green BA Bus Active LED atthe SUPI 3 output is a Layer 2 activity display The output has an off delay of the duration of the preset INTERBUS watchdog default 630 ms See Sectio
49. access Symbol Explanation Time ns minimum Valid data before positive edge of WR 15 t2 Valid data after positive edge of WR 10 t3 WR pulse width 30 3 8 PHOENIX CONTACT 6025 en 03 Application interface Read access ICS gt 0 RD 7 u 5 00 07 X Valid data X 5191A008 Figure 3 2 MFP interface timing read access Table 3 12 MFP interface timing read access Symbol Explanation Time ns Min Max 14 Valid data after negative edge of RD 25 t5 Data bus high resistance after positive edge of RD 25 t6 RD pulse width 80 modes of operation Table 3 13 uP modes of operation SUPI pin MFP interface mode C3 C2 C1 co 0 0 0 1 interface 1 byte 1 0 1 1 interface 2 bytes 1 1 1 1 uP interface 4 bytes 1 1 0 0 uP interface 6 bytes 0 0 1 0 interface 8 bytes Inthe uP modes of operation the data width may be varied between one and eight bytes with the configuration pins CO to C3 The five uP modes of operation therefore differ only with respect to the active data length This data length can also be changed with the software see Section SET II register on page 3 19 6025 en 03 PHOENIX CONTACT 3 9 IBS SUPI 3 Address area assignment The following register descriptions are independent of the selected uP mode of operation The SUPI 3 chip provides four address lines A3 to
50. ally and the IRQ line becomes inactive After an interrupt request IRQ low the CPU in and ideal system has the following time periods available for reading the interrupt event ll register and the INTERBUS OUT data registers as well as for writing the INTERBUS IN data registers 13 5 tai Length of an INTERBUS bit 2 us typical n Number of bytes in the entire network Permissible access time of the CPU The minimum time occurs when the INTERBUS NETWORK comprises one device only Implemented device 2 words 32 bits The input and output direction is to be used The worst case time amounts to gt T 234 us After an interrupt request the CPU has a maximum of 234 us to read the interrupt event ll register and the INTERBUS OUT data registers 0 to 3 and to write the IN data registers 0 to 3 6025_en_03 PHOENIX CONTACT 3 15 IBS SUPI 3 Using a polling bit If it is not possible in the application to achieve synchronization with interrupts the I O access bit can be polled For this purpose the IB state register with relative address 7 must be read If the I O access polling bit has the value 1 INTERBUS data registers must no longer be accessed If the I O access bit is 0 access to the data registers may take place during the next 34 bit times This time is independent of the device data length and the INTERBUS configuration Therefore synchronization via the polling bit places
51. alue after every INTERBUS reset Interrupt mode Since the connected microprocessor reads and writes the data registers asynchronously to the INTERBUS cycle inconsistent data may occur when the reading and writing coincides with the latch update phase of an INTERBUS cycle In this phase secured OUT data is stored in the IB OUT data registers and data is transmitted from the IB IN data registers to red to INTERBUS To synchronize access to the data registers the SUPI 3 chip as an interrupt logic which makes available several INTERBUS cycle synchronous events as interrupts It is also possible to use certain events as polling bits The different interrupt sources are enabled via two common interrupt enable registers by setting the corresponding bit to 1 After an interrupt event IRQ becomes 0 occurs the source can either be read in the Interrupt Event register and or in the Interrupt Event II register The bit which corresponds to the event is to 1 by the chip The read access causes an automatic reset of the registers and the IRQ request line after an interrupt IRQ 14 1 Event 2 4 X rel addr 5 02 00 1 Read address 5 min 62 5 ns gt max 125 ns 5191A009 Figure 3 3 Timing of the interrupt signals using the example of the DATA cycle interrupt The latch phase completes the check sequence of every INTERBUS cycle 6025_en_03 PHOENIX CONTACT 3 11 IBS SUPI 3 Int
52. alve manifolds ISO valve manifolds 5 05 Remote bus device analog Analog output modules AO 49 31 Analog input modules Al 50 32 Analog input output modules AlO 51 33 Profile compliant analog output modules PROFILE AO 53 35 Profile compliant analog input modules PROFILE Al 58 3A Profile compliant analog input output modules PROFILE AlO 59 3B ENCOM with input data ENCOM 54 36 ENCOM with input and output data ENCOM 55 37 Remote bus devices with parameter channel Modules with parameter channel 2 PCP words PA channel 240 FO Modules with parameter channel 4 PCP words PA channel 241 1 Modules with parameter channel 1 PCP word PA channel 243 F3 DRIVECOM 2 PCP words DRIVECOM 224 EO DRIVECOM 4 PCP words DRIVECOM 225 1 4 6025 03 ID code specification extract Table A 5 Extract from the ID code specification continued Description of module function ID code ID code dec hex DRIVECOM 1 PCP word DRIVECOM 227 E3 ENCOM 2 PCP words ENCOM 244 F4 ENCOM 4 PCP words ENCOM 245 F5 ENCOM 1 PCP word ENCOM 247 F7 Profile compliant modules 2 PCP words Profile PA channel 228 E4 Profile compliant modules 4 PCP words Profile PA channel 229 E5 Profile compliant module 1 PCP word Profile PA channel 231 E7 uP_Not_Ready with register latching remote bus Sp
53. c does not constitute any further duty on the part of Phoenix Contact to furnish information on alterations to products and or technical documentation Any other agreement shall only apply if expressly confirmed in writing by Phoenix Contact Please note that the supplied documentation is product specific documentation only and that you are responsible for checking the suitability and intended use of the products in your specific application in particular with regard to observing the applicable standards and regulations Although Phoenix Contact makes every effort to ensure that the information content is accurate up to date and state of the art technical inaccuracies and or printing errors in the information cannot be ruled out Phoenix Contact does not offer any guarantees as to the reliability accuracy or completeness of the information All information made available in the technical data is supplied without any accompanying guarantee whether expressly mentioned implied or tacitly assumed This information does not include any guarantees regarding quality does not describe any fair marketable quality and does not make any claims as to quality guarantees or guarantees regarding the suitability for a special purpose Phoenix Contact accepts no liability or responsibility for errors or omissions in the content of the technical documentation in particular data sheets installation instructions manuals etc The aforementioned limitations of
54. ditions can be found on the Internet at www phoenixcontact com Make sure you always use the latest documentation It can be downloaded at www phoenixcontact n tal If there are any problems that cannot be solved using the documentation please contact your Phoenix Contact subsidiary Subsidiary contact information is available at www phoenixcontact com PHOENIX CONTACT GmbH amp Co KG PHOENIX CONTACT FlachsmarktstraBe 8 P O Box 4100 32825 Blomberg Harrisburg PA 17111 0100 Germany USA Phone 49 0 52 35 3 00 Phone 1 717 944 1300 Fax 49 0 52 35 3 4 12 00 Should you have any suggestions or recommendations for improvement of the contents and layout of our manuals please send your comments to tecdoc phoenixcontact com PHOENIX CONTACT 6025_en_03 Table of contents 1 Structure and basic ad eee eee 1 1 1 1 laugoo ree 1 2 1 2 B si6 Structure oen donum d 1 3 1 2 1 New features of the IBS SUPI chip 1 5 1 2 2 Field Of application oot tutte scirent sed 1 8 1 3 HOUSING type iU ee eel i ee i 1 8 1 3 1 QFP 100 pint ble u nennen ea 1 9 1 3 2 QFP 100 Quad Flat 1 11 1 3 3 Signal description u ee eine urn 1 13 1 4 eti Dir RO nr Ren 1 16 1 4 1 Clock initiallZatiOl coire ce nern 1 16 1 4 2 Configuratio
55. dous situation which if not avoided will result in death or serious injury WARNING This indicates a hazardous situation which if not avoided could result in death or serious injury CAUTION This indicates a hazardous situation which if not avoided could result in minor or moderate injury The following types of messages provide information about possible property damage and general information concerning proper operation and ease of use NOTE This symbol and the accompanying text alerts the reader to a situation which may cause damage or malfunction to the device either hardware or software or surrounding property This symbol and the accompanying text provides additional information to the reader It is also used as a reference to other sources of information manuals data sheets literature on the subject matter product etc PHOENIX CONTACT 6025 en 03 IBS SUPI 3 General terms and conditions of use for technical documentation Phoenix Contact reserves the right to alter correct and or improve the technical documentation and the products described in the technical documentation at its own discretion and without giving prior notice insofar as this is reasonable for the user The same applies to any technical changes that serve the purpose of technical progress The receipt of technical documentation in particular data sheets installation instructions manuals et
56. e 3 7 Assignment of the MFP interface for the 16 bit input 3 5 Table 3 8 Configuration 8 bit input and 8 bit 3 6 Table 3 9 Assignment of the MFP interface for the 8 bit input and 8 bit outp tmode 4 hi pete beet oen De dio tuoi 3 6 Table 3 10 Assignment of the MFP interface for the uP access mode 3 7 Table 3 11 MFP interface timing write access ne rerrrn rnent 3 8 Table 3 12 interface timing read 3 9 6025 en 03 PHOENIX CONTACT IBS SUPI 3 Table 3 13 puPimodes of Operation iet e e e T e eed eel 3 9 Table 3 14 Address area assignment of the 3 10 Table 3 15 INTERBUS watchdog in the SUPI 3 3 16 Table 3 16 neige Mc aed eee iv 3 17 Table 3 17 Mapping of the SET I register to the length entry in the ID code 3 17 Table 3 18 Encoding of the data length in the SET I 3 18 Table 3 19 Mapping of the ID code register to the ID 3 20 Table 3 20 Timing for register expansion eee 3 31 Table 3 21 Diagnostic inputs outputs of a remote bus device 3 32 Table 3 22 Diagnostic inputs outputs of a l
57. ecial 56 38 uP_Not_Ready for re initialization remote bus Special 60 3C Local bus device digital Digital output modules DO 189 BD Digital input modules DI 190 BE Digital input output modules DIO 191 BF Digital INTERBUS Loop output modules IBS Loop DO 177 B1 Digital INTERBUS Loop input modules IBS Loop DI 178 B2 Digital INTERBUS Loop input output modules IBS Loop DIO 179 B3 Profile compliant digital output modules PROFILE DO 181 B5 Profile compliant digital input modules PROFILE DI 182 B6 Profile compliant digital input output modules PROFILE DIO 183 B7 Wrenching controllers Wrench contr 187 BB Local bus device analog Analog output modules AO 125 7D Analog output modules with alarm inputs AIO 91 5B Analog input modules Al 126 7E Analog input modules with configuration outputs 95 Analog input output modules AlO 127 7F Analog input and output modules with alarm inputs and configuration 83 53 outputs Analog INTERBUS Loop output modules AO Loop 113 71 Analog INTERBUS Loop output modules with alarm inputs AIO Loop 107 6B Analog INTERBUS Loop input modules Al Loop 114 72 6025_en_03 PHOENIX CONTACT 5 IBS SUPI 3 Table A 5 Extract from the ID code specification continued Description of module function ID code ID code dec hex Analog INTERBUS Loop input modules with configuration outputs Loop 1
58. ect line OUT return path B12 SLI2 Select line IN return path ST Dxx Data line of the INTERBUS ring DO1 Data line IN forward path ST DO2 Data line OUT forward path B12 Data line OUT return path 12 DI2 Data line IN return path ST CKxx Clock line for the INTERBUS devices CKO1 Clock line IN forward path ST CKO2 Clock line OUT forward path B12 Clock line OUT return path B12 CKI2 Clock line IN return path ST CRxx Control line check sequence CRO1 MAUWR Control line IN forward path MAU warning return path ST CRO2 Control line OUT forward path B12 Control line OUT return path B12 CRI2 Control line IN return path ST ResIn MAUWS INTERBUS reset input MAU warning branch Input STp filtered with 12 520 us directly passed on to pin LBRes LBRes INTERBUS reset output B2 RBST Alarm input whether outgoing INTERBUS interface is ST used Input filtered with 270 ms 6025_en_03 PHOENIX CONTACT 1 13 IBS SUPI 3 Table 1 5 Signal description continued Designation Meaning Type LBST Alarm input whether local bus interface is used in BK ST module applications In all other modes of operation this pin is to be connected to Vas Input filtered with 270 ms Diagnostic signals StatErr Module error alarm input uP watchdog input filtered STp with t 270 ms When using the pin as a uP watchdog pin the scan time is set
59. errupt enable register The interrupt enable registers enable the interrupt sources of the interrupt event register separately An interrupt is enabled when the corresponding bit is set to 1 The RESET value of the interrupt enable register is 0 Interrupt enable register Relative write address 4 MSB LSB D7 06 05 DA 03 D2 D1 DO E INTERBUS inactive PCP send PCP receive Check sequence INTERBUS reset ID cycle DATA cycle INTERBUS cycle counter 51914010 Figure 3 4 Assignment of the interrupt enable register Interrupt enable register Relative write address 14 MSB LSB 07 06 05 04 03 02 01 DO Layer2_To Command register Reserved ze Figure 3 5 Assignment of the interrupt enable II register 3 12 PHOENIX CONTACT 6025 en 03 Application interface Interrupt event register The interrupt event registers store events which have caused an interrupt Access to this register is only permitted after an interrupt request Polling these registers is not permitted Interrupt event register Relative read address 4 MSB LSB 07 06 05 04 03 02 DO L INTERBUS inactive PCP send PCP receive 0 reserved INTERBUS reset INTERBUS cycle counter 0 reserved so91a012 Figure 3 6 Assignment of the interrupt event register Interrupt event II register Relative read address 5 MSB LSB or os 58 e 51 oo
60. ers with firmware 4 50 or later 6 PHOENIX CONTACT 6025_en_03 Length code specification Length code specification Table A 6 ID code data length 1012 1011 1010 109 108 Data length Firmware version 0 0 0 0 0 0 words 0 0 0 0 1 1 word 0 0 0 1 0 2 words 0 0 0 1 1 3 words 0 0 1 0 0 4 words 0 0 1 0 1 5 words 0 0 1 1 0 8 words 0 0 1 1 1 9 words 0 1 0 0 0 1 nibble 4 0 0 1 0 0 1 1 byte 4 0 0 1 0 1 1 3 bytes 4 0 0 1 1 0 0 Reserved 0 1 1 0 1 2 bits 4 0 0 1 1 1 0 6 words 3 2 0 1 1 1 1 7 words 3 2 1 0 0 0 0 Reserved 1 0 0 0 1 26 words 3 7 1 0 0 1 0 16 words 3 2 1 0 0 1 1 24 words 3 2 1 0 1 0 0 32 words 3 2 1 0 1 0 1 10 words 3 2 1 0 1 1 0 12 words 3 2 1 0 1 1 1 14 words 3 2 1 1 X X x Reserved The data length is supported by the controller board bus master with the specified firmware version or later data lengths 1 byte and bytes are supported by the PC board version 3 1 or later The data lengths supported by firmware version 3 2 or later are recognized by the PC AT T board by driver version 2 0 or later 6025 en 03 PHOENIX CONTACT A 7 IBS SUPI 3 The length entry determines the data register length of the entire INTERBUS device that means the total of register configurable in the SUPI chip and additional external registers if any By default this length entry is wired via SUPI 3 pins ID12 ID8 by hardware The physical data length of the
61. evices are automatically cleared after they have been taken over by INTERBUS The clearing mechanism is enabled by default To use IN bytes 0 and 1 for dedicated I O applications the clearing mechanism can be disabled with the Disable Clear bit After this bit has been set the data item written in IN bytes 0 and 1 is transmitted in each data cycle Thus IN bytes 0 and 1 act in the same way as IN bytes 2 to 3 and 10 to 13 Table 3 16 PCP bit Disable Clear bit PCP device 0 device 1 Length entry of the identification code The length entry determines the data register length of the entire INTERBUS device i e all external registers are included By default this length entry is wired via the SUPI 3 pins 1012 108 by hardware The SUPI 3 chip offers the possibility of setting the length entry of the identification code the SET I register by means of software This allows to adapt the data length to the application without changing the hardware Set the ID Length bit in the SET II register to 1 so that the length entry can take effect The external setting is always the default setting Table 3 17 Mapping of the SET I register to the length entry in the ID code SET I register D7 D6 D5 D4 D3 ID code 012 1011 ID10 9 ID8 A flexible setting of the data register length is also possible with the hardware setting of the uP_Not_Ready ID codes see Sect
62. form a management channel to the master currently still reserved On chip diagnostics The master activates on chip diagnostics on the devices during the bus system detection All devices capable of diagnostics exchange their operation ID registers and diagnostic ID registers The master thus recognizes all devices able for diagnostics If errors should occur they are stored in the diagnostic register The following diagnostic elements are implemented in the line decoder forward return branch Power up reset detection MAU fail wire interrupt wire short circuit CRC Cyclic Redundancy Check Stop bit error detection Validity check of the check sequence RBST LBST change detection MAU warnings impairment of the transmission quality Eightalternative ID registers are addressed by a control word of the controller board and transmitted in the next ID cycle 1 6 PHOENIX CONTACT 6025 en 03 Structure and basic wiring following registers can be selected 0 Standard register First diagnostic bit register Second diagnostic Register Alarm bit register Processor alarm register Reserved Reserved OO Manufacturer mask identification The standard ID register is the default setting 6025_en_03 PHOENIX CONTACT 1 7 IBS SUPI 3 1 2 2 Field of application The SUPI 3 has been designed for industrial applications Table 1 2 General data Qua
63. higher time demands on the CPU see Section IB state register on page 3 23 3 4 2 SET I register Relative write address 5 The SET I register allows to parameterize the INTERBUS watchdog and the length entry of the identification word can be preset MSB LSB Lor os me mel pa oo INTERBUS watchdog Disable clear Length entry ID code 51914015 Figure 3 8 Assignment of the SET I register Description of the INTERBUS watchdog The INTERBUS watchdog monitors Layer 2 transmission on INTERBUS The watchdog is reset with every valid cycle It has no effect on the data registers of the SUPI 3 chip The watchdog has two outputs output Bus Active This output which is available as physical pin on the SUPI 3 chip is used as the diagnostic output BA The off delay of BA is as long as the INTERBUS watchdog Interrupt source INTERBUS inactive This interrupt is generated if the SUPI 3 chip has not detected any valid data cycle until after the watchdog time elapsed The following table shows the parameterization options Table 3 15 INTERBUS watchdog in the SUPI 3 chip 01 DO Watchdog time ms 0 0 630 635 default 0 1 315 320 1 0 143 148 1 1 73 78 3 16 CONTACT 6025_en_03 Application interface Disable clear In order to support PCP communication INTERBUS IN bytes 0 and 1 which form the communication channel for PCP d
64. in two years of delivery Proper storage of the components in an unopened package is required for good processing If the ASICs are packaged in dry packs and the moisture content is OK according to HIC the ASICs do not have to be dried before use If this is not the case the ASICs can be treated according to IPC JEDEC J STD 20A 1 3 Soldering For information on soldering the surface mounted components described in this manual IBS SUPI 3 QFP and IBS CHIP Muster please refer to the IPC JEDEC J STD 020 JOINT INDUSTRY STANDARD document This document is available upon request Please contact Phoenix Contact 6025_en_03 PHOENIX CONTACT A 3 IBS SUPI 3 A2 ID code specification extract Table A 5 Extract from the ID code specification Description of module function ID code ID code dec hex Bus terminal modules BK BK with 8 wire local bus branch BK 8L LB 52 34 BK with 2 wire local bus branch BK 2L LB 8 08 BK with INTERBUS Loop branch BK SL 4 04 BK with 2 wire remote bus branch BK 2L RB 12 oc Remote bus device digital Digital output modules DO 1 01 Digital input modules DI 2 02 Digital input output modules DIO 3 03 Profile compliant digital output modules PROFILE DO 13 oD Profile compliant digital input modules PROFILE DI 14 Profile compliant digital input output modules PROFILE DIO 47 2F ISO v
65. ion ID code register on page 3 20 6025_en_03 PHOENIX CONTACT 3 17 IBS SUPI 3 The meaning of the ID lengths bits ID12 ID8 can be obtained from the following table Table 3 18 Encoding of the data length in the SET I register 1012 1011 1010 109 108 Data length Firmware version 0 0 0 0 0 0 words 0 0 0 0 1 1 word 0 0 0 1 0 2 words 0 0 0 1 1 3 words 0 0 1 0 0 4 words 0 0 1 0 1 5 words 0 0 1 1 0 8 words 0 0 1 1 1 9 words 0 1 0 0 0 1 nibble 4 0 0 1 0 0 1 1 byte 4 0 0 1 0 1 1 3 bytes 4 0 0 1 1 0 0 Reserved 0 1 1 0 1 2 bits 4 0 0 1 1 1 0 6 words 3 2 0 1 1 1 1 7 words 3 2 1 0 0 0 0 Reserved 1 0 0 0 1 26 words 3 7 1 0 0 1 0 16 words 3 2 1 0 0 1 1 24 words 3 2 1 0 1 0 0 32 words 3 2 1 0 1 0 1 10 words 3 2 1 0 1 1 0 12 words 3 2 1 0 1 1 1 14 words 1 1 x x x Reserved 3 2 The data length is supported by the controller board bus master with the specified firmware version or later The data lengths 1 byte and 3 bytes are supported by the PC AT T board version 3 1 or later The data lengths supported by firmware version 3 2 or later are recognized by the PC AT T board by driver version 2 0 or later 3 18 PHOENIX CONTACT 6025 en 03 Application interface The length entry determines the data register length of the entire INTERBUS device that means the total of registers configurable in the SUPI chip and additional external registers if any 3 4 3
66. ith software afterwards see Section SET I register on page 3 16 and Section SET II register on page 3 19 1 20 PHOENIX CONTACT 6025 en 03 Structure and basic wiring Example SUPI 3 chip with register expansion SRE 1 Data length SUPI 3 4 words C3 to CO 0010 Data length SRE 1 3 words Length entry at the ID pins 7 words ID12 to 8 01111 Total of SUPI 3 and register expansion 6025 en 03 PHOENIX CONTACT 1 21 IBS SUPI 3 1 22 PHOENIX CONTACT 6025_en_03 INTERBUS interfaces 2 INTERBUS interfaces 2 1 Overview When the chip is interfaced to INTERBUS it can be connected to the remote bus installation remote bus or local bus Remote bus connection is always chosen when long distances up to 800 m via fiber optic HCS fiber or up to 400 m via wires have to be covered An asynchronous 2 wire protocol and a fiber optic or differential voltage interface according to RS 485 are used in the remote bus Therefore the bus cable requires two fibers or five signal lines Five signal lines for electrical transmission are necessary since there is always one wire pair for the forward and return path as well as a ground cable A remote bus device always has its own voltage supply In the event of a remote bus failure the entire network can only be operated up to the last functioning remote bus device Post connected devices can no longer be addressed The installation remote bus is a special type of remote bus
67. local bus 0 0 1 1 BK I O module with 8 wire local bus Both operating modes provide as local bus an 8 wire interface which is available at the MFP interface according to the following table MFP n Assignment 0 Clock line input 1 SLI Control line data ID cycle input 2 DI Data line input 3 CRI Control line check sequence input 4 CKO Clock line output 5 SLO Control line data ID cycle output 6 DO Data line output 7 CRO Control line check sequence output 8 ALARM Alarm output 9 x 10 X 11 X 12 X 13 X 14 X 15 X TheINTERBUS master can set the alarm output via a corresponding service X Not to be used In this case the LBRes signal belongs to the complete 8 wire local bus interface 3 2 PHOENIX CONTACT 6025 en 03 Application interface BK module with 2 wire branch A second group within the bus terminal module class are BKs with 2 wire branch as additional INTERBUS interface The 2 wire branch can be used for example for setting up an installation remote bus segment or a 2 wire local bus segment In this group a distinction is also made between BK and a I O Table 3 3 Configuration BK module with 2 wire branch C3 c2 C1 0 0 0 0 BK module 2 wire branch line 0 1 0 0 BK I O module with 2 wire branch line In this group the MFP interface has the following assignment
68. luenced by software LCAs or similar In particular the reset must not be controlled by a microprocessor NOTE For indirect and direct connection of the reset input the components used in the entire voltage range of the voltage monitor must be operated in accordance with regulations Standard logic gates are not suitable for this purpose 1 4 2 Configuration options The SUPI 3 has two separate INTERBUS interfaces and one interface to the application The SUPI 3 chip can be interfaced to the INTERBUS remote bus or local bus The RGNDA pin of the SUPI determines whether the chip will be used for a remote or local bus device In addition pins KMO 1 and have to be configured according to the following table Table 1 7 Configuration of the INTERBUS interface KMO KM1 CKO1 RGNDA INTERBUS interface mode 0 0 1 8 wire local bus 1 1 0 1 2 wire local bus 1 1 0 0 2 wire remote bus 500 kbit 0 1 0 0 2 wire remote bus 2 Mbit For copper interfaces only Pin CKO1 is the incoming INTERBUS clock line for 8 wire applications For 2 wire applications the pin must have a low level 1 18 PHOENIX CONTACT 6025 en 03 Structure and basic wiring Multifunction interface The 16 bit multifunction pin interface MFP is the interface to the application Configuration pins C3 C2 C1 CO allow the following interface connections to the INTERBUS network
69. m gt CRO1_ _MAUWR CRO 5 vente gt SLOl MAUWH SLO2 GND 4 GND 5 gt ResIn MAUWS LBRes gt L EHE 5 GND GNDI TNI GNDI GND KMO N 5 3 RBST lt 1 lt m gt InterBus 8 75179 zl 5 T gt 1 MFP2 DI3 Ved 4 15 8 ET gt c2 c3 MFP6 DO3 gt gt a LBST lt StatErr gt StatErr 45V 5 other open ene iL gt 4 MFP8 Alarm gt 6 1 7705 3 Q7 GND A 2 Vref cc 8 gt 2 6 5 comer re ik BA gt uet SFH610 3 4 sensein res gt ResU ResReg gt sr Alarm output 8 4 v Gnd 3 3 21 3 for option x a a 5 A 5 A 1 gt E FromExR 6 Please observe layout notes of the manufacturer Other connector types may be 2 GND used depending on the device type Masstab Please observe layout notes of the 1 Anzah gepr manufacturer and the chapter clock remotebus terminal module E generation of the IBS SUPI3 manual version 0 0 01 02 97 Lutz PHOENIX cu Anzahl Kopie CONTACT 1 5 Z Nr Kopien Nr Datum Name Rev Aenderung Datum Name Pruefdatum gepr C Appendix Section 1 Section 3 C1 List of figures Figure 1 1 Figure 1 2 Figure 1 3 Figure 1 4 Fig
70. menting an I O device with 32 bit input and 16 bit output There are different ways of assigning an address The internal registers of the SUPI 3 can be used as inputs outputs or not at all In addition it is also possible to assign different data lengths to such a device The following figures show the different ways 6025_en_03 PHOENIX CONTACT 3 27 IBS SUPI 3 48 bit device with 16 OUT The internal SUPI 3 registers have been used as outputs and expanded by 4x8 bit shift and 32 IN addresses registers with inputs CLKExR ResReg LalnD LaOuD SUPI 3 ToExR1 FromExR ToExR2 4x8bit external shift registers with inputs 6025A025 Figure 3 17 48 bit I O device with 4x8 bit IN register expansion 48 bit device with 16 OUT The internal SUPI 3 registers have been used as inputs and expanded by 4x8 bit shift and 32 IN addresses registers with inputs and outputs CLKExR ResReg LalnD LaOuD SUPI 3 ToExR1 FromExR ToExR2 2x8bit external shift registers with inputs 2x8bit external shift registers with outputs 6025A026 Figure 3 18 48 bit I O device with 2x8 bit IN and 2x8 bit OUT register expansion 3 28 PHOENIX CONTACT 6025_en_03 Application interface 32 bit device with 16 OUT The internal SUPI 3 registers have been used as outputs Parallel to this 4x8 bit shift and 32 IN addresses registers with inputs have been looped in between pins ToExR1 and From
71. n ID cycle the master can write to the contents of the command register register A connected microprocessor receives an interrupt with every new command if it was switched on see also Section Processor alarm register and processor command register on page 3 24 The check sequence completes an INTERBUS cycle and ensures the validity of the data transmitted 3 4 1 Synchronization options To ensure data consistency CPU access to the SUPI 3 chip must be synchronized with the INTERBUS cycle In principle there are two options for synchronizing the CPU access with the INTERBUS cycle Using interrupts Using a polling bit Using interrupts When interrupt controlled synchronization is used the Data Cycle interrupt is suitable The interrupt is enabled by writing 40 to the interrupt enable l register with the relative address 4 only once during initialization After each interrupt request IRQ becomes low the interrupt event ll register with the relative address 5 has to be read If the contents of this register is 0255 current data can now be read out of the OUT data registers If the contents of the register is 04544 OUT data originates from the last valid data cycle Independent of the contents of the interrupt event Il register the CPU can write to and read from the INTERBUS IN OUT data registers after the interrupt request After reading the interrupt event ll register the contents are cleared automatic
72. n SET I register on page 3 16 3 32 PHOENIX CONTACT 6025 en 03 Application interface TR RD LD The green TR Transmit Receive diagnostic LED becomes active when PCP communication is being carried out via INTERBUS It is connected to the active high SUPI 3 LBDA TR pin in the uP modes An external off delay is provided for this output to guarantee a visible indication on the LED The output pulse has a minimum length of 8 us The yellow RD LED at the RBDA output indicates statically that the outgoing remote bus Remote Bus Disabled is switched off This diagnostic feature is only relevant for remote bus devices and is active in the INTERBUS RESET state Only for bus terminal modules shows the active high LBDA TR pin with a yellow LED that the branch has been disconnected Local Bus Disabled This output is active in the INTERBUS RESET state 6025_en_03 PHOENIX CONTACT 3 33 IBS SUPI 3 Input StatErr Acknowledge output ModAck Reconfiguration request CONF E Error MAU warning Input output module error The active low input StatErr is used for example to report a module error e g I O voltage not applied to the INTERBUS controller board Applying a low level to this input causes a module error If StatErr is not used it has to be statically connected to Vpp The input is filtered see Section Signal description on page 1 13 The default filter value is 270 ms Setting this
73. n 03 Application interface If the application requires a data length of 32 bits as an output module the following write commands have to be executed Writing 1455 in the SET I register write address 5 Writing ID code 0154 in the ID code register write address 7 and then Writing in the SET II register write address 6 3 4 5 IB state register Relative read address 7 MSB LSB Reserved INTERBUS reset I O access KM1 KMO Reserved 0 Figure 3 11 Assignment of the IB state register Different internal operating states are mapped in the IB state register The physical assignment of configuration pins 1 and can be read in bits D4 and D3 immediately after the operating voltage U has been applied The active bit D2 maps the check sequence phase The check sequence completes an INTERBUS cycle and ensures validity of the data transmitted The I O access bit is therefore suitable for synchronization of uP access by polling see Section Synchronization options on page 3 15 Like the INTERBUS reset interrupt an active bit D1 indicates INTERBUS reseti e this INTERBUS device was set to the reset state due to a fatal error or by the master using an INTERBUS reset Alarm Stop Request command at the master This event should always be evaluated The INTERBUS data registers are reset Bits marked reserved have no meaning and must be masked out for evaluati
74. n Options eerie Ae 1 18 2 CINTERBUS IDIGITAOBS 2 1 2 1 cR M A mL cce ede 2 1 2 2 Local bus interface 8 wire emen 2 1 2 8 Remote bus 2 3 3 Application Interfaee Ec E Pep aad 3 1 3 1 CC 3 1 3 2 Bus terminal module 3 1 3 3 Input o tput eroe ae 3 4 3 4 HP microprocessor access mode sssssseeeeeen nene 3 7 3 4 1 Synchronization options 3 15 3 4 2 ten tet ederent aae AS 3 16 3 4 3 DUPP IEEE 3 19 3 4 4 ID code register 3 20 3 4 5 IB State register inermem ree Rte as 3 23 3 4 6 Cycle read and cycle write registers 3 24 3 4 7 Processor alarm register and processor command register 3 24 3 5 Register expansion code erede aa asia 3 25 3 5 1 Examples s 2 ex ase s pae habet aedes pug cedo ins 3 25 3 5 2 Register expansion interface timing 3 30 3 6 Diagnostic inputs and 3 32 Technical uo d etia Da tc aca A 1 A1 General notes about proces
75. nction The filter value is 520 us 3 34 PHOENIX CONTACT 6025 en 03 Technical data Table A 1 Absolute limit values Symbol Parameters Value Unit Vpp DC supply voltage 0 5 to 47 0 V Vin DC input voltage 1 5 to Vpp 1 5 V Vout DC output voltage 0 5 to Vpp 0 5 V DC current per pin inputs and outputs 50 mA DC current per pin Vpp and Vss pins 75 mA Table A 2 Recommended operating conditions Symbol Parameters Min Max Unit Vpp DC supply voltage 4 5 5 5 V Vin Vout DC input output voltage 0 0 Vpp V TA Industrial temperature range 40 85 Table 3 DC data Symbol Parameters Condition 40 C to 85 C Min Max Vin Input voltage high CMOS inputs Vout 0 1 V 0 7 or Vit Input voltage low CMOS inputs Vpp 0 1 V 0 3 20 Schmitt trigger inputs Positive switching threshold 0 7 Negative switching threshold 0 25 Hysteresis to 0 12 Output voltage high Outputs B2 lou 2 2 mA 3 7V Vpp Vou Outputs BDp lou 4 mA 3 7V Vpp Outputs B12 lou 12 mA 3 7V Vpp 6025 en 03 PHOENIX CONTACT A 1 IBS SUPI 3 Table A 3 DC data continued Symbol Parameters Condition 40 C to 85 C Min Max Output voltage low Outp
76. neration of INTERBUS slave protocol chips It is pin and function compatible with the previous SUPI 1 and 2 chip versions Its most important new feature is its central diagnostics and report manager being part of the new INTERBUS diagnostic concept The INTERBUS SUPI 3 protocol chip resulted from a VHDL model and has a complexity of about 15000 gate equivalents The following block diagram shows the structure of the circuit MFP 15 0 16 MHz ID send Data send receive bulfer receive buffer Address ID Address ToExR MAU L warning 4 FromExR Error detectors 51914039 Transmission medium Figure 1 2 Block diagram of the chip 6025_en_03 PHOENIX CONTACT 1 3 IBS SUPI 3 The protocol stack in the middle comprises layer 1 and layer 2 of the ISO OSI reference model Data is provided to the MDS Medium Dependent Sublayer from an external MAU Medium Attachment Unit e g RS 485 or fiber optic access In this layer scanning line decoding and encoding are carried out and time conditions are defined The SUPI 3 chip has three channels in the MDS for one incoming and two outgoing interfaces The MIS Medium Independent Sublayer forms the upper edge of layer 1 i e the physical layer It is intended for routing the three MDS channels and for connecting layer 2 Its lower edge represents the medium access control MAC This layer performs the ring access as well as the data
77. ntity Value Min Type Max Unit Supply voltage 4 5 5 0 5 5 V Temperature 40 25 85 1 3 Housing type The following list explains general symbols and text that will be used in the drawing of the housing Position Maximum material condition MMC Feature control frame Basic or exact dimension Basic untoleranced dimension locating true position A dimension which is obtained from other dimensions and their tolerances 5191B029 1 8 PHOENIX CONTACT 6025_en_03 Structure and basic wiring 1 3 1 100 pin table Table 1 3 QFP 100 pin table Pin No Pin Name Pin No Pin Name Pin No Pin Name 1 RBST 36 MFP10 70 IDO 2 KMO 37 MFP9 71 SLI 3 38 8 72 RGNDA 4 KM1 39 73 StatErr 5 n c 40 Vpp 74 n c 6 CKO2 41 Vss 75 CRI 7 n c 42 MFP7 76 n c 8 FromExR 43 Vss 77 CONF 9 DO2 44 MFP6 78 n c 10 LBST 45 MFP5 79 BA 11 CO 46 MFP4 80 LBDA TR 12 C1 47 MFP3 81 Error 13 C2 48 MFP2 82 DH 14 CKO1 49 MFP1 83 C3 15 DO1 50 84 LBRes 16 MAUWR 51 85 ModAck 17 SLO1 MAUWH 52 MAUWS 86 18 Vss 53 ID12 87 Vss 19 Vpp 54 n c 88 20 OSC1 55 ID11 89 Vpp 21 OSC2 56 90 22 ResU 57 1010 91 Vss 23 012 58 129 92 SLO2 24 n c 59 ID8 93 LaOuC 25 CRI2 60 ID7 94 LalnD 26 n c 61 95 LaOuD 27 SLI2 62 ID6 96 CIkExR 28 CKI2 63 ID5 97 CRO2 29 MFP15 64 98 ResReg 30 65 ID4 99 ToExR2
78. ocal bus device 3 32 Appendix A Table A 1 nnn 1 Table 2 Recommended operating A 1 Table A 3 DO data iiie 1 Table A 4 ds ato A 3 Table A 5 Extract from the ID code specification A 4 Table A 6 ID code data A 7 C 4 PHOENIX CONTACT 6025 en 03 C3 Index Numerics 16 Inputs sta ae 3 27 16 OUT and 32 IN 3 28 3 29 T6 outp ls te es 3 27 16 ea 3 5 3 27 16 Dit Hesse ea 3 4 3 27 32 bit input iere tee edere 3 27 32 bit input and 16 bit 3 27 8 bit InpUt iie dU elus 3 6 G Dit oUtput iin eom PR UE sane 3 6 A Address area 3 10 Address DUS emet oon n eec 3 7 output onion utt 3 2 3 3 ee 1 2 B BA is 3 16 BA diagnostic 3 32 Bus terminal module eee 3 1 C CC diagnostic LED eene 3 32 Certificato Ne ce be eet 3 32 Check
79. oder Gebrauchsmuster Eintragung vorbehalten tung und Mitteilung ihres Inhalts nicht gestattet nicht ausd ten zu Schadenersatz Phoenix Contact application remote bus with optical isolation type 1 5VI 5V IN 5V 5V OUT ia fe 9 GNDI 8 8 8 8 8 E 15nF GNDI GND m tu amp a GND GND S 5VI 5V er GND 1 8 st PE 15 DIZ HCHL2601 Y ii 121 5 osci osc2 75179 z E x BIT 4 gt Vouti K lt DIL 2 lt du um 5 CKI2 lt Hpb v SMI 112 gt lt CRI2 L a Doi 2 gt 390 gt CROl MAUWR box y SLO1_ _MAUWH 502 gt CRO2 gt ResIn MAUWS LBRes gt gt 0 gt 1 InterBus rp gt CONF 4 iBsST RBST po staterr gt StatErr RBDA gt BA gt
80. on 6025_en_03 PHOENIX CONTACT 3 23 IBS SUPI 3 3 4 6 Cycle read and cycle write registers The cycle read and cycle write registers can be used for cycle synchronous processing together with the enabled INTERBUS cycle counter interupt e g to check the number of INTERBUS cycles from the slave application and the react on a certain n th cycle Any desired 8 bit value can be written in the cycle write register The cycle read register is incremented with every valid data cycle If the value of the cycle write register is reached an interrupt is activated bit 5 in the interrupt event l register is set and the value in the cycle read register is reset to zero Then the described procedure is repeated 3 4 7 Processor alarm register and processor command register The SUPI 3 offers a management channel to the bus master This function must be enabled by the bus master and is supported by firmware 4 0 or later Management messages from the master to the slave are received in the processor command register and can trigger an interrupt Management messages from the master to the slave are written to the processor message register The management channel is reserved for future applications 3 24 PHOENIX CONTACT 6025_en_03 Application interface 3 5 Register expansion If the data length of the SUPI 3 is to be extended this can be done independently of the selected mode of operation using external shift registers or the se
81. ossible by setting the uP_Not_Ready ID code see uP not Ready ID code on page 3 21 Application example The following example is to show how to proceed when you are using the ID length and MFP mode bits Depending on the degree of extension an application requires data lengths of 16 to 32 bits as input output or module The changeover is to be done without changing the hardware i e by the CPU with software Solution The SUPI is set to the uP Interface 2 byte mode using hardware pins C3 C0 101 1b and to a data length of one word using pins ID12 ID8 00001b ID code is set to ID pins 100 107 If the application requires data length of 32 bits as an output module the following write commands have to be executed Writing 1455 in the SET I register write address 5 3 20 PHOENIX CONTACT 6025 en 03 Application interface Writing 01 the ID code register write address 7 Writing the SET II register write address 6 Please note that these changeover commands can only be executed during the initialization phase of the SUPI 3 chip that means before the master started the first ID cycle and not during operation Alternatively the SUPI 3 chip offers the possibility of using the uP Not Ready ID code operation with microprocessor This variant should be preferred to the direct changeover explained above JP not Ready ID code With the uP
82. resistor is inserted from OSC1 to OSC2 in parallel to the quartz The capacitor values given in Figure Clock lines of the SUPI 3 on page 1 16 are only a typical case Please observe that due to the board layout the interfering capacitances have a considerable effect on the response time of the quartz oscillating circuit Therefore it is required to check as for any other design the correct behavior in the specified range and to modify the proposed values if necessary Tests of typical layouts with the quartz elements recommended in the component reference list of the INTERBUS Club have shown a safe response with the circuit and case capacitances of 22 pF each described in the SUPI 2 manual The circuit of Figure 1 5 should be used for new designs or redesigns With this clock no other components must be operated additionally when a quartz crystal is used The oscillator can also be operated by an external 16 MHz clock with a CMOS level In this case the oscillator operates as a buffer The external clock signal is to be connected to the OSC1 oscillator input Internal oscillato External clock 5K6 T T 0502 OSC2 NT Quartz e 16 MHz 1M il Quartz oscillator 10 16 MHz OSC1 OUT OSC1 51914005 Figure 1 5 Clock lines of the SUPI 3 For the clock applies f 16 MHz 100 ppm Clock ratio 50 10 duty cycle 1 16 PHOENIX CONTACT 60
83. rial register expansion chip IBS SRE 1 Order No 2752851 The SUPI 3 chip has two data outputs which offer a simple serial interface The 1 output lies before and the ToExR2 output after the SUPI 3 internal buffers The FromExR input can be used to return the shift register data The CIKEXR signal is to be used as a clock for the external registers The active low LalnD signal is used as a transfer signal from the application to the shift registers The active high LaOutD signal is used as latch signal from the shift registers to the memory registers The active low ResReg reset signal is available for resetting the memory registers after an INTERBUS reset il The possibility of expanding internal registers with external registers or the SRE 1 should be used as such For EMC reasons itis not useful to implement an internal serial interface with remote shift registers using these signals Extension ICs should be located as close as possible to the IBS SUPI 3 5 1 Examples There are various combination options for expanding the registers No register expansion Pins ToExR2 and FromExR are to be connected with each other The internal SUPI 3 registers are used only CLKExR ResReg LalnD LaOuD SUPI 3 ToExR1 FromExR ToExR2 6025A021 Figure 3 12 No register expansion 6025 en 03 PHOENIX CONTACT 3 25 IBS SUPI 3 Expansion of the SUPI 3 internal data registers with the IBS SRE
84. rk on the Internet at www interbusclub com Current hardware and software information for the device manufacturer as well as further product documents from Phoenix Contact can be found on the Internet at www phoenixcontact net catalog 6025_en_03 PHOENIX CONTACT 1 1 IBS SUPI 3 Local Bus 8 Stations max 10m Remote Bus Installation Remote Bus Remote Bus Spur max 50 m SUPI MFP pP SUPE 400m Application areas of the INTERBUS slave protocol chip 50438102 Figure 1 1 Fields of application of the INTERBUS SUPI 3 slave protocol chip 1 1 Introduction The IBS SUPI 3 chip is an ASIC in 0 5 um CMOS technology It represents the third generation of INTERBUS slave protocol chips and is pin and function compatible to the previous SUPI 2 chip Every INTERBUS master operates together with the SUPI 3 chip The IBS PC AT T PC interface board supports the SUPI 3 chip by driver version 3 1 or later 1 2 PHOENIX CONTACT 6025_en_03 Structure and basic wiring Currently the SUPI 3 is available in one housing type QFP 100 Table 1 1 Different versions Housing Order designation Order No QFP 100 IBS SUPI 3 QFP 2746087 QFP 100 IBS CHIP Muster 2746951 1 2 Basic structure The SUPI is the third ge
85. s of the input and output interfaces Table 2 5 Pin assignment of the 9 pos D SUB INTERBUS remote bus connector Pin Signal name of the incoming Signal name of the outgoing interface male connector interface female connector 1 DO1 DO2 2 012 3 GNDI GND 4 Reserved Reserved 5 Reserved 5V 6 DO1 DO2 7 DI1 DI2 8 Reserved Reserved 9 Reserved RBST Please refer to the Appendix for application examples 6025_en_03 PHOENIX CONTACT 2 3 IBS SUPI 3 2 4 PHOENIX CONTACT 6025_en_03 Application interface 3 Application interface 3 1 Overview The configuration of the MFP interface determines how the application accesses the INTERBUS network via the SUPI 3 chip Three classes are distinguished Bus terminal module Direct input output Access using a microprocessor uP interface The following table lists the three classes and the configuration via pins C2 C1 and Table 3 1 Operating modes of the MFP interface C2 C1 1 0 0 0 BK module 8 wire local bus 0 0 1 1 BK I O module with 8 wire local bus 0 0 0 0 BK module 2 wire branch line 0 1 0 0 BK I O module with 2 wire branch line 1 0 0 1 16 bit output 1 0 1 0 16 bit input 1 1 0 1 8 bit input and 8 bit output 0 0 0 1 uP interface 1 byte 1 0 1 1 uP interface 2 bytes 1 1 1 1 uP interface 4 bytes 1 1 0 0 uP interface 6 bytes 0 0 1 0 uP interface 8 bytes
86. s offer a better evaluation This reduces hardware expense considerably The power up reset circuitry of the SUPI 3 chip has also been optimized For a better detection of errors caused by the transmission medium e g loose contacts or failure of a differential signal line of the RS 485 interface this state must be mapped to a high level at the data input This means for the RS 485 interface to force a logic 1 on the receive data line in the event of an error The line decoders in the MDS sublayer interpret this as an idle message Since idle messages defined in the protocol have a logic encoding a distinction is possible using MAU fail timers If the MAU fail timer recognizes this 1 state for a set time this is indicated as a MAU error to the diagnostics manager The MAU warning function can detect for example the impairment of optical components caused by aging or an increasing pollution of lenses in the data light barriers before it comes to a complete failure For this the output of a trigger must be led to the new MAU warning inputs of the SUPI 3 chip For a better support of software flexibility on the slaves the module identification code ID code can now be loaded to the SUPI 3 chip Like the length code in the SET I register this code is protected from accidental writing by an automatic latching mechanism This mechanism and applying the uP not Ready ID code to the physical pins of the SUPI 3 allows reconfiguration of
87. security The MAC sublayer serves the 8 byte transmit and receive buffers for INTERBUS data as well as the 16 byte transmit and receive buffers for the identification transmission cycle The application and higher protocol layers have access to these buffers via the 16 bit Multi Functions Pin interface MFP interface The MFP interface can be set according to the interface implementation requirements via four configuration pins as an I O port or as a microprocessor interface of a CPU environment The interface contains an interrupt controller with the necessary write and read registers as well as parameterization and state registers for CPU applications These registers allow to configure the chip and to visualize certain protocol events Data of the transmit and receive buffers is taken from the MAC sublayer encoded correspondingly and sent to the suitable MDS channel via the MDS sublayer After the line encoding data is sent to the medium via the external MAU Compared to previous chips the central diagnostics and report manager as well as the error detectors which are able to read certain error patterns at all MDS channels and the MAC sublayer are important new features of the SUPI 3 chip This block distinguishes between events with high or low priority Events of low priority also called report events are for example the MAU warnings in the block diagram These warnings are provided by the MAU and indicate an impairment of the transmis
88. sing A 3 A 1 1 Sloragecusss iss statim cie HUE DERE E E A 3 A 1 2 Processing time sn near A 3 AVES Sold ring 2 ID code specification A 4 A3 Length code A 7 6025 en 03 PHOENIX CONTACT i IBS SUPI 3 Wiring examples C Appendix MM M E M B 1 C 1 List Of figures nite En RID E e tene deal aed C 1 HE BO tables x i C 3 ann er 5 6025 03 Structure and basic wiring 1 Structure and basic wiring The IBS SUPI 3 Serial Universal Protocol Interface chip represents a new generation of INTERBUS slave protocol chips and an easy interface to INTERBUS The integrated diagnostic and error management is a novelty in the chip it allows an exact determination of error location and cause in a system and also reduces external circuitry On the basis of this description you may implement your own INTERBUS devices within a very short time With the end user in mind subject the devices to the INTERBUS conformance test In addition to this document you will find the INTERBUS Club guideline Conformity Test and Certification as a reference wo
89. sion quality This means that not only faults but also creeping impairment in quality is detected and signaled at a very early stage Diagnostic events with high priority are error sources which cause interference in the transmission cycle The diagnostics and report manager ensures both generation and non time critical transmission of error patterns The error patterns are stored in the ID send buffer and transmitted from the MAC sublayer to the bus master If an error exceeds the permissible data update time of the bus system but is too short for a central check of all devices by the master the on chip diagnostics shows its performance The diagnostics manager stores all detected errors on the transmission medium as well as breakdowns of the voltage supply as error patterns in the chip until it has been read and acknowledged by the bus master This procedure allows a unique assignment of sporadic errors which in general are difficult to identify to the error location 1 4 PHOENIX CONTACT 6025_en_03 Structure and basic wiring 1 2 1 New features of the IBS SUPI 3 chip Although the diagnostics described above is an important feature it is less important to developers of INTERBUS devices when designing the circuit The efforts are reduced because functions are implemented in the SUPI 2 chip by additional hardware For example the voltage monitoring of all electrically isolated areas is no longer necessary because the MDS sublayer
90. ss uses 2 1 Local bus branch 3 ne uae 3 1 M MAU warning Baer ala 3 34 tfe ute enis 1 19 1 18 Moduleerf r 2 3402er 3 34 Multi function pins essen 3 4 N No register expansion 3 25 6025 en 03 PHOENIX CONTACT C 5 IBS SUPI 3 O OsScillatOr 1 ctio ee 1 16 3 4 P communication esee 3 17 nr en 3 14 3 14 Pin description 2 1 4 1 13 Polling 3 16 Processor 3 20 Q 1 16 R RD diagnostic 3 33 Remote bus i ph ehe 2 1 Remote bus 3 1 Remote bus connection 2 1 Remote or local bus branch 3 1 Resheg iue aae e eter 3 25 85 485 0 nannten 2 1 S 1 ch ee 3 22 Soldering conditions A 3 Stal EM cr Assassin 3 34 Switch code 5 ence 3 20 Switch 2 3 19 Switch MFP 3 19 Synchronization ioci orco caderet 3 16 Synchronizing the CPU access 3 15 T
91. th the relative address 8 and value n counted n valid data cycles Before the interrupt occurs the current counter value can be read via relative address 8 see Section Cycle read and cycle write registers on page 3 24 This interrupt indicates the end of an identification cycle This interrupt indicates the end of a data cycle Current OUT data is present This interrupt can also be used to synchronize CPU access to the SUPI 3 chip Data can be read and or written again After his IR event data of the OUT bytes originates from the last valid data cycle since the just finished data cycle has been detected invalid Although the CPU may write to IN bytes and read the OUT bytes The check sequence has been initiated by the INTERBUS master IN and OUT bytes can only be written or read for 60 us A time basis on the chip which is independent of the bus monitors cyclic operation Layer 2 monitoring can only be set by the INTERBUS master FW 4 0 or later If no valid INTERBUS cycle is detected within the time preset by the master 50 ms 200 ms 1000 ms off process data is reset The ResReg signal is activated for connected external registers if any A single pulse of 375 ns is generated The event is communicated to the microprocessor of the device with an interrupt G4 error message OC6B 3 14 PHOENIX CONTACT 6025 en 03 Application interface How to proceed Time requirements Example I
92. tion data is changed only once during operation In addition the bus master recognizes microprocessor devices that have not been initialized the uP_Not_Ready ID code and expects a re initialization with the correct values However bus operation is still possible since there a devices with the data length zero on the bus that have not yet been initialized After writing to register 6 the locked state is achieved Application example The following example shows you how to proceed when using the uP_Not_Ready ID code Depending on the degree of extension an application requires data lengths of 16 to 32 bits as input output or module The changeover is to be done without changing the hardware i e by the CPU The module is connected to the remote bus Solution The SUPI 3 is set to the uP interface 2 byte mode using hardware pins 1011b to a data length of one word via pins ID12 ID8 0 00016 and to the uP_Not_Ready ID code 0011 10006 via pins 107 100 When pins 107 100 are set in this way SUPI 3 has a length of zero in the INTERBUS system If the application requires a data length of 16 bits as an I O module the following write commands have to be executed Writing in the SET I register relative address 5 Writing ID code in the ID code register write address 7 and then Writing 41 the SET II register write address 6 3 22 PHOENIX CONTACT 6025 e
93. ults in selecting the uP watchdog function Bit D5 of the SET II register is mapped to the message bit register The master recognizes which of the functions is active and corresponding messages are generated If Switch ID code is set together with Switch ID length the lower byte of the ID code is set according to the contents of the register with the relative write address 7 Hardware settings at ID pins IDO to ID7 are then ignored The Switch ID code bit can only be activated when the Switch ID length bit is set 3 4 4 10 code register The ID code is defined in the INTERBUS Club ID Code Specification depending on the functions of the device An extract from this code can be found in Appendix By default this ID code is specified by the hardware of SUPI 3 pins IDO to ID7 The SUPI 3 offers the option of setting the ID code in the ID code register relative address 7 with software This makes it possible to adapt the ID code to the application type without modifying the hardware In order to make the ID code in the ID code register relative address 7 valid the Switch ID code bit in the SET II register must be set to 1 The external setting is always the default setting Table 3 19 Mapping of the ID code register to the ID code ID code register 07 06 05 D4 03 02 01 00 ID code 107 106 105 104 ID3 102 ID1 IDO A flexible setting of the ID code is also p
94. ure 1 5 Figure 1 6 Figure 3 1 Figure 3 2 Figure 3 3 Figure 3 4 Figure 3 5 Figure 3 6 Figure 3 7 Figure 3 8 Figure 3 9 Figure 3 10 Figure 3 11 Figure 3 12 Figure 3 13 Figure 3 14 Figure 3 15 Figure 3 16 Figure 3 17 Figure 3 18 Figure 3 19 Fields of application of the INTERBUS SUPI slave protocol chip 1 2 Block diagram of the 1 3 Pin layout of the QFP 100 housing 44440 1 10 Mechanical dimensions of the QFP 100 housing original dimension millimeters 2 1 11 Clock lines of the 1 16 Clock ratio for the clock of INTERBUS protocol chips 1 17 interface timing write access 3 8 interface timing read access 3 9 Timing of the interrupt signals using the example of the DATA cycle interupt 5 nitent pp ERR EE 3 11 Assignment of the interrupt enable register 3 12 Assignment of the interrupt enable Il register 3 12 Assignment of the interrupt event register 3 13 Assignment of the interrupt event Il register 3 13 Assignment of the SET I register sse 3 16 Assignment of the SET II register
95. uts B2 2 mA Vss 0 4V VoL Outputs BDp 4 mA Vss 0 4V Outputs B12 12 mA Vss 0 4V Output current high Outputs B2 3 7 V 2 mA lou Outputs BDp 4mA Outputs B12 12 Output current low Outputs B2 Vor 0 4 V 2 lot Outputs BDp 4 Outputs B12 12 lin Input leakage current no internal pull up resistor Vin Vas 5 5 Input leakage current with Vin Vss 30 pA 165 internal pull up resistor 50 kohms typical PUL Vin Vss 15 120 loz Output leakage current High resistance 10 pA 10 pA 55 Current consumption Approx 20mA All input static all outputs unused oscillator operates with 16 MHz A 2 PHOENIX CONTACT 6025_en_03 General notes about processing 1 General notes about processing These guidelines do not necessarily specify extreme conditions which must be observed for safety reasons for the named surface mounted components IBS SUPI 3 QFP and IBS CHIP Muster In many cases the housings withstand much higher temperatures than standard PCBs These guidelines are intended to create soldering conditions permitting high quality design and minimum improvement work A 1 1 Storage Table A 4 Storage Symbol Parameters Value Unit Storage temperature 5 to 30 Relative humidity for storage 30 to 60 A 1 2 Processing time We recommend using the ASICs with
96. y can be read back The READ registers are then no longer available This can be used for instance to check whether writing to the registers worked correctly Writing restores the original function 3 10 CONTACT 6025_en_03 Application interface INTERBUS registers The INTERBUS data registers with the relative addresses 0 to 3 and 10 to 13 are provided for the I O exchange between application and INTERBUS master The data registers designated INTERBUS IN byte are to be written by the application while the INTERBUS OUT byte data registers are to be read by the application Please note that the IN bytes 0 and 1 are cleared automatically after data is transmitted over INTERBUS default setting If this data register is not cyclically written to the written data item will be transmitted only once Afterwards the value 0 is transmitted in those bytes For applications in which no PCP communication is used the value 04 disable clear is to be written once to the SET I register with the relative address 5 after initialization has been completed In doing so automatic clearing of the INTERBUS IN bytes 0 and 1 is deactivated see Section SET I register on page 3 16 The value of the data registers falls as the address rises i e fora device with a data width of 8 bytes the byte with address 0 is the high byte and the byte with address 13 is the low byte The data registers are set to their initial v

User manual IBS SUPI 3 UM - Digi-Key

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