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MPC8360 MDS Processor Board

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1. hee 5 10 100 1000 MPC8360 8 E Ethernet JTAG to JrAG 9 12C 20 5 ME M S S B lt gt Enct4 SIR 2 2 dm Z 12 2 z USB 1 1 1 1 EEPROM 9 256Kb EEPROM 9 BRD 2 DDR 1 zi SPD H gt gt He gt 4 Dual RS232 DBE ze 6 PCI UPC2 QE amp Other SPD wt m P Power 125 DDR ane E Core Supply 3 Bus Switch for Voltage Clamp RTC lt 5 o Figure 1 2 MPC8360 MDS Processor Board Block Diagram MPC8360 MDS Processor Board Rev A 1 Freescale Semiconductor 14 Definitions Acronyms and Abbreviations ADS Application Development System BCSR Board Control and Status Register BRD Board Revision Detect 2 EEPROM BSP Board Support Package CCR COP Control Register FPGA COP Common On chip Processor JTAG Debug Port CS Chip Select CW Code Warrior IDE for PowerPC DAC Digital to Analog Converter DDR Double Data Rate DIP Dual In Line Package DMA Direct Memory Access DUART Dual UART EEPROM Electrical Erasable Programmable Mem
2. HRESET output eee SES CINDY a o PCIMODE D FRR I ICY i ES H Load CFG Device is ready 1 SRESET output 1 1 1 TRST ZZ Input Device is ready Reset Input Signals Reset Configuration Word 277 1 tart Load Reset Configuration Figure 5 2 Reset Timing Diagram 5 1 2 Reset Circuit The Reset Circuit of the MPC8360 MDS Processor Board has the following features e Reset controller MIC2774N 23BM5 MICREL drives the PORESET signal Low power detect device drives PORESET as follows if the detected input power is less than 4 5V PORESET is driven at 5V if the detected input power is less than 3V PORESET is driven at 3 3V if the detected input power is less than 2V PORESET is driven at 2 2V if the detected input power is less than 1 6V PORESET is driven at 1 8V e JTAG COP can drive HRESET or SRESET depending on the command given from the JTAG device Push button for PORESET HRESET and SRESET FLASH memory is protected during PORESET and after that until the system is enabled e PCI RST signal is connected to PORESET signal The BCSR resets the GETH PHYs 5 1 3 MPC8360 MDS Processor Board Reset Principles Upon power on The device MIC2774N 23BMS drives PORESET low for 300msec to the 8360 BCSR FLASH and PIB if connected 8360 MDS Processor Board Rev A Freescale Semicon
3. E 5 15 5 4 12 BCSRI Status Registet Sos me ea rug e a o Sob 5 16 5 4 13 BCSR12 Status Register o patet a was 5 16 5 4 14 BCSR13 Status Register qe vs ROMS 5 17 5 4 15 BCSR14 Board Status Register 14 UE TA 5 18 5 4 16 CUR COP Control Registe ren hed See ee 5 18 5 5 External esi Pesce odes COU PUR OE dA 5 19 5 5 1 Pl MimiAB USB Connector s UR P Se 5 19 5 5 2 525 ee Ha SOR PAN 5 20 5 5 3 P3 32 bit PEIL Edge ote PRENNE 5 20 5 5 4 P4 P5 P6 Logic Analyzer Connectors 5 20 5 5 5 etate d te bg dau 5 21 5 5 6 Debug COP Connector ud ue RR yee AEE 5 21 5 5 7 P9 FPGA s In System Programming 8 5 22 5 5 8 PTO Power dca e o A hay qq bs 5 22 5 5 9 JJZ GETH Port Connector a wee kd ee SE 5 23 20 CPR uk enS 5 23 5 6 1 GO CONN e 5 23 5 6 2 PCI
4. v dades 5 44 6 Working with the PIB 6 1 Platform I O Board Concept x ais sesenta d eet TA 6 1 62 MPC8360E MDS Processor Board as 6 2 6 3 MPC8360E MDS Processor Board as 6 3 6 4 8360 MDS Processor Board PIB Signals 6 3 Chapter 7 Replacing Devices 7 1 Replacing Flash Memory 2 4 0 244 8 date acy E EX 7 1 7 14 Cleaning Flash ake ak Oe cu cd M 7 2 T20 SODIMM UniS ois Bist hee eee en 7 3 7 3 Replacing MPC8360E Processor deed VR 7 5 MPC8360 MDS Processor Board Rev A 1 Freescale Semiconductor 3 MPC8360 MDS Processor Board Rev 1 Freescale Semiconductor Chapter 1 General Information 1 1 Introduction This document describes the MPC8360 MDS Processor Board in its stand alone operating mode in its operating mode via a PCI slot in a PC and in its operating mode on the PowerQUICC MDS Platform I O Board PIB The MPC8360 MDS Processor Board is an ADS that provides a complete debugging environment for engineers developing applications for the MPC8360 series of Freescale processors The MPC8360E is a cost
5. 2 51 32 bit HYMD232M646D6 10000000 7FFFFFFF Empty Space 80000000 9FFFFFFF Inbound Outbound window 32 0000000 DFFFFFFF Empty Space MPC8360 MDS Processor Board Rev A 1 Freescale Semiconductor 3 1 Table 3 1 MPC8360 MDS Processor Board Memory Map continued Volume port Address Range Device Name in Bytes 0000000 Internal Memory Register 2MB 32 Space 0200000 EFFFFFFF Empty Space 256MB Local Bus SDRAM 64MB 32 8 F0000000 F3FFFFFF optional MT48LC16M16A2TG 6A 1 parity or on CS2 with MT48LC32M16A2TG 7E for parity or or 128MB 0000000 F7FFFFFF MT48LC16M16A2TG 6A x 2 9 F4000000 F7FFFFFF Empty Space in case SDRAM is only 64MB 64MB F8000000 F8007FFF BCSR on CS1 Xilinx FPGA 32KB F8008000 F800FFFF PIB CS4 see PIB documentation 32KB F8010000 F8017FFF PIB CS5 see PIB documentation 32KB F8018000 F801FFFF PIB CS3 see PIB documentation 32KB 14 F8020000 FDFFFFFF Empty Space 100MB 15 FE000000 FLASH on CSO MT28F128 16 16 FE800000 Empty Space 24MB 3 2 Configuration Registers Mapping The table below shows how to initialize the registers in the MPC860 It shows the register name its address and what value must be written to that register for proper initialization There are sev
6. 1 23 12 18 22 GPIO50 UPC1 TxDATA 10 2 22 12 19 PB23 GPIO51 1 22 P12 F21 PB24 52 PMCO J1 21 P12 F22 PB25 GPIO53 PMCO J2 20 P12 F24 PB26 GPIO54 2 48 12 25 27 GPIO55 MPC8360 MDS Processor Board Rev A 1 Freescale Semiconductor Table 6 1 TDM UPC Ethernet Signals continued PMC XMC pin MPC8360 PIB Signal Function 1 MPC8360 Clock Number Pin Number Name Name Number amp USB 1 13 12 5 12 GPIO68 CLK13 PMCO J3 42 P12 G3 14 GPIO70 CLK15 2 45 P12 F30 PDO GPIO82 1 52 P12 G7 PD1 GPIO83 2 43 P12 G8 PD2 4 PMCO J2 32 P12 G10 PD3 GPIO85 PMCO J1 26 P12 G11 PD4 GPIO86 PMCO J1 43 P12 G13 PD5 GPIO87 1 33 P12 G14 PD6 GPIO88 2 35 P12 G16 PD7 GPIO89 PMCO J1 36 P12 G17 PD8 GPIO90 2 38 P12 G19 PD9 GPIO91 PMCO J1 37 P12 G20 PD10 GPIO92 PMCO J2 25 P12 G22 PD11 GPIO93 4 5 2 42 P12 G23 PD12 GPIO94 2 39 P12 G25 PD13 GPIO95 2 54 P12 G26 PD14 GPIO96 RMII6 TXDO PMCO J1 61 P12 G28 PD15 GPIO97 RMII6 TXD1 1 53 P12 H10 PD18 GPIO100 RMII6 TXEN 1 46 P12 H12 PD19 GPIO10
7. Riser PMC XMC Connector MPC8360 PIB Signal Function 1 8360 Clock Number i Name Name Number amp USB Pin Number PMCO J3 48 P12 A17 GPIO6 3 52 12 19 10 GPIO7 PMC1 J3 54 P12 A20 11 GPIO8 3 58 12 22 12 9 3 60 12 14 15 GPIO12 SEnet1 RX DV RX E GEnet1 RX_DV _RX_ER 1 40 P12 C30 9 GPO65 3t1 GTXC 3Enet1 GTXCLK CLI CLK10 PMC1 J3 52 12 28 GPIO64 st1 Input 125M 1 1 125 CLK9 PMCO J1 48 P12 A16 GPIO5 TDMA RXD 0 UPC1 RxCLAV 1 2 46 12 23 PA13 TDMA TXD O0 UPC1 TxCLAV 1 2 57 12 25 14 GPIO11 TDMA RSYNC UPC1 RxEN 1 PMCO J2 19 P12 B15 PA16 GPIO13 TDMA TSYNC UPC1 TxEN 1 PMCO J3 25 P12 A5 PC7 GPIO63 TDMA RXCLK CLK3 GPIO58 PMCO J3 29 P12 A28 PC3 GPIO59 TDMA TXCLK CLK4 PMCO J3 31 P12 C13 PA26 GPIO23 TDME RSYNC PMCO J3 35 P12 B17 PA17 GPIO14 TDME TSYNC PMCO J3 37 P12 D7 PA29 GPIO26 TDME RXD 0 3 41 P12 D8 PA30 GPIO27 TDME TXD O0 PMCO J2 58 P12 K26 PC16 GPI72 TDME TXCLK UPC1 TxCLAV 3 CLK17 PMCO J3 7 P13 A3 PC23 GPI79 TDME RXCLK UPC1 RMOD CLK24 PMCO J3 49 P12 B18 PA18 GPIO15 TDMD TSYNC PMCO J3 53 P12 B20 PA19 GPIO16 TDMD TXD O0 PMCO J3 55 12 10 PA24 GPIO21 TDMD RSYNC 3 59 12 12 PA25 GPIO22 TDMD RXD 0 PMCO J2 34 P12 G1 PC13 GPIO69 TDMD RXCLK UPC1 TxEN 3 CLK14 3 61 12
8. re A W I2Cl Signals 122 12 2 Signals A MODE 4 EEPROM I2C 0b101 0000 i EN ui POR Device Config Dip Switch Array To IO Expander on IO Board 7 EEE 66Mhz CLK CLKIN EEEE Figure 5 1 Reset Circuit Block Diagram Once the PORESET signal is negated the MPC8360 starts to load the reset configuration word RCW bits These bits are latched from the DIP switches into appropriate FPGA registers the BCSR s Excluding the hard coded options there are three ways to drive the RCW Via BCSR RESET SOURCE 0 2 000 amp FCFG 0 SW9 3 Via FLASH RESET SOURCE 0 2 000 amp FCFG 1 SW9 3 e Vial2C 1 bus RESET SOURCE 0 2 is 001 010 depending on the value desired for PCI CLK The setting for FCFG has no effect in this case All the RCW bits can be changed from their initial settings using either the FPGA BCSR through the local bus or using the LLD low level debugger The BCSR must then drive HRESET PORESET to load a new configuration word to the device It is possible to read the value of the RCW from the BCSRs Figure 5 2 below shows the timing for the reset sequence 8360 MDS Processor Board Rev A 5 2 Freescale Semiconductor Stable 32 4 PLLs are locked
9. Hardware Preparation and Installation This chapter provides unpacking instructions hardware preparation and installation instructions for the MPC8360 MDS Processor Board including all three configurations Stand Alone PIB Combined Mode and Agent Mode either on the PIB or inserted in a PC For more details on hardware preparation see the Hardware Getting Started document for the MPC8360 MDS Processor Board 2 1 Unpacking Instructions NOTE If the shipping carton is damaged upon receipt request carrier s agent to be present during unpacking and inspection of equipment CAUTION AVOID TOUCHING AREAS OF INTEGRATED CIRCUITRY STATIC DISCHARGE CAN DAMAGE CIRCUITS 1 Unpack equipment from shipping carton 2 Refer to packing list and verify that all items are present 3 Save packing material for storing and reshipping of equipment 2 2 Installation Instructions Do the following in the order indicated to install the MPC8360 MDS Processor Board properly 1 Verify that Jumpers and Switches are in default positions For default positions see the Hard ware Getting Started Guide document for the 8360 MDS Processor Board 2 Determine in which working configuration you will operate the MPC8360 MDS Processor Board Stand Alone continue from Section 2 2 1 PIB Combined Mode with the PIB Board continue from Section 2 2 2 Agent Mode continue from Section 2 2 3 MPC8360 MDS Processor Board Rev A
10. receives its defaults upon Power on or PORESET signals BCSR11 fields are described below in Table 5 12 Table 5 12 BCSR11 Register Description ed _ mm Amm QUISCE QUISCE Siatus Allow the processor power down mode to be Processor determined low by reading via JTAG I F If this bit is high the processor power down mode cannot be determined by reading from the JTAG I F 1 BUFFEN Expansion Buffer Enable A value of low enables access to the PIB for the Combined Mode A value of high sets the expansion defined at buffer for working in the stand alone mode May be rewritten any Power On time via LBIU SHMOOEN SHMOO Test Enable Enables programming the Internal Core Power Supply and applying an external clock from the PIB Board low When the bit is high the board operates in regular mode May be rewritten any time via LBIU BRDWP BRD Write Protect When high the BRD EEPROMs on the Processor Board cannot be written to When low the BRD s can be written to May be rewritten any time via LBIU PORESET Power On Reset Toggling low high within the proper time window will generate a PORESET negative pulse on the board May be rewritten any time via LBIU 5 7 SWOP Software Option Three bits code the value read from the Rotary SW Rotary switch Coded 5 413 BCSR12 Status Register On the board BCSR12 acts as a control register BCSR12 which may be read or written at any time receives its defaults upon Power on signa
11. 1 GPIO57 TDMD TXCLK o CLK2 PMCO J3 4 P12 B21 PA20 GPIO17 TDMB TSYNC 3 6 12 1 10 GPO66 TDMB TXCLK i RE CLK11 PMCO J2 23 P12 B24 PA22 GPIO19 TDMB TXD 0 UPC1 RxCLAV 2 PMCO J3 10 P12 A30 4 60 TDMB RXCLK CLK5 PMCO J1 47 P12 C15 PA27 GPIO24 TDMB RXD 0 UPC1 TxCLAV 2 3 12 12 16 28 GPIO25 TDMB RSYNC UPC2 RxADDRI5 PMCO J2 52 P12 K28 PC17 GPI73 TDMF RXCLK UPC1 RxCLAV 3 CLK18 PMCO J3 16 P12 B23 PA21 GPIO18 TDMF TSYNC PMCO J3 18 P12 B26 PA23 GPIO20 TDMF RSYNC PMCO J3 17 P12 J18 PE9 GPIO119 TDMF RXD O0 UPC1 STPA PMCO J3 11 P12 J19 PE10 GPIO120 TDMF TXDI 0 UPC1 RVAL PMCO J3 22 P12 A7 PC18 GPI74 TDMF TXCLK REM CLK19 PMCO J1 P13 A11 PC29 PC29 GPIO No GPIO ber Number PMCO J1 P13 A10 PC28 NoGPIO PC28 Number GPIO Num ber PMC1 J3 1 P12 D10 PBO 28 3 2 Enet3 TXD 0 PMC1 J3 5 P12 D11 PB1 GPIO29 Enet3 TXD 1 TXD 3 Enet3 TXD 1 MPC8360 MDS Processor Board Rev A 1 6 4 Freescale Semiconductor Table 6 1 TDM UPC Ethernet Signals continued i Riser Connector MPC8360 PIN PIB Signal Function 1 Function 2 MPC8360 Clock Number Number amp USB Pin Number PMC1 J3 7 P12 D16 PB4 2 PMC1 J3 11 P12 E9 PB6 GPIO34 PMC1 J3 13 P12 E11 PB7 GPIO35 PMC1 J3 17 P12 E18 PB12 GPIO40 PMC1 J3 19 P12 E20 PB13 GPIO41 PMC1 J3 55 P12 D13 PB2 GPIO30 USB_OE
12. PMC1 J3 25 P12 D14 PB3 1 USB_TP PMC1 J3 29 P12 E8 5 GPIO33 PMC1 J3 31 P12 E12 PB8 GPIO36 USB_TN PMC1 J3 35 12 14 PB9 GPIO37 USB RP PMC1 J3 37 P12 E15 PB10 GPIO38 USB RXD PMC1 J3 41 P12 E17 PB11 GPIO39 USB RN PMCO J3 34 P12 H26 PEO GPIO110 Enet7 TXDO PMCO J1 41 P12 J10 4 GPIO114 Enet7 TXEN 3 30 P12 J13 PEG GPIO116 Enet7 RXDO 1 54 12 22 12 GPIO122 Enet7 RXDVCRS 1 20 P13 C1 21 GPIO77 CLK22 3 1 13 1 22 GPIO78 CLK23 2 1 16 P12 J21 PE11 GPIO121 2 55 P12 J14 GPIO117 Enet7 RXDO PMCO J2 51 P12 J24 PE13 GPIO123 UPC1 TxADDRI4 PMCO J1 10 P12 H27 PE1 GPIO111 UPC1 TxADDR 3 Enet7 TXD1 3 43 12 PC11 GPI67 CLK12 3 47 12 1 PCO GPIO56 CLK1 1 4 12 29 2 GPIO112 UPC1 RxADDR O0 1 58 P12 H30 PE3 GPIO113 TDMG TSYNC UPC1 TxADDR O 2 13 12 11 5 GPIO115 1 55 12 16 GPIO118 2 61 13 5 19 GPIO75 CLK20 PMCO J1 17 P13 C3 PC20 GPIO76 CLK 1 PMCO J1 32 P12 E21 PB14 GPIO42 2 29 12 15 4 1 29 12 9 16 GPIO44 UPC1 TxCLAV O 2 28 12 10 17 GPIO45 1 28 P12 F12 PB18 46 PMCO J1 27 P12 F13 PB19 GPIO47 PMCO J2 26 P12 F15 PB20 GPIO48 1 49 12 16 21 GPIO49
13. Twisted Pair Receive Data positive BI DB n input Green Twisted Pair Receive Data negative BI DB input 5 6 1 General The MPC8360 PCI interface allows the MPC8360 MDS Processor Board to function as either a PCI host or as a PCI peripheral device referred to as agent mode The PCI port is muxed with the ATM port In order to enable PCI signals and disable ATM signals the value of PCI MODE must be set to 0 This can be set via DIP Switches SW9 1 or BCSR10 4 this pin is driven constantly There are four MPC8360 MDS Processor Board operation configurations each of which uses the PCI in host or agent mode indicated Stand alone Host mode but PCI interface not used Mounted on PIB through Riser Connectors Host mode Mounted on PIB through PMC Connectors Agent mode Installed on PC Agent mode 8360 MDS Processor Board Rev A Freescale Semiconductor 5 23 The PCI controller mode of operation is determined at reset by values of the reset configuration word high RCWH These be seen in BCSR4 bits PCIHOST PCIARB and PCICKDRV as shown in the following two sections 5 6 2 PCI Setting when MPC8360 MDS Processor Board is Host If the 8360 MDS Processor Board is in a stand alone configuration or on the riser connectors of the PIB that is not inserted in a PC nor inserted on the PIB as an agent the FPGA configures the RCW to PCI Host by setting BCSRA 0 to 1 The PCI port
14. high oras 1 RW a Device low USB Voltage Source When this bit is low the 1 RW MPC8360 supplies power to USB When high the USB gets power from the MINI USB connector 8360 MDS Processor Board Rev A Freescale Semiconductor 5 17 5 4 15 BCSR14 Board Status Register 14 On the board BCSR14 acts as a control register BCSR14 which may be read or written at any time receives its defaults upon Power on signals BCSR14 fields are described below in Table 5 15 Table 5 15 BCSR14 Register Description Enable When this bit is high is enabled When this bit is low is disabled Note in early versions may not be supported but is used to select the unused signals in RGMII RTBI to be routed to the PIB 1 MII2 Enable When this bit is high 2 is enabled When this bit is low 2 is disabled Note in early versions is not supported but it used to select the unused signals in RGMII RTBI to be routed to the PIB 5 416 Control Register CCR COP Control Register is a service register accessed from the Local Bus It is a part of PCIDJTAG converter for the Agent Mode The CCR fields are described below in Table 5 16 Table 5 16 CCR COP Register Description Default BIT MNEMONIC upon PORESET TAP Data Input Drives serial data into COP port Disabled TAP Data Output Reads serial data from COP port Disabled TAP Clock When
15. 1 Freescale Semiconductor 2 1 2 2 1 For Stand Alone Mode For Stand Alone Mode only Connect the four plastic spacers See Figure 2 1 1 2 Connect external cables in accordance with your development needs 3 Connect PSU to P10 and turn the power on off switch to ON 4 Verify that LD1 and LD2 turn on and turn off see Figure 2 2 for location They should on for only a few moments This indicates that the board has successfully completed the boot up sequence i Plastic Screw Plastic Spacer n 7 Figure 2 1 Connecting Plastic Spacers MPC8360 MDS Processor Board Rev A 1 2 2 Freescale Semiconductor Power Supply Port JTAG COP Connector Reset LEDs LD1 green LD2 red Figure 2 2 Boot Up sequence LD1 and LD2 turn on then off MPC8360 MDS Processor Board Rev A 1 Freescale Semiconductor 2 3 2 2 2 For PIB Combined Mode 1 Remove protective covers from the 300 pin connectors on the bottom side of the processor board See Figure 2 3 2 Remove protective covers from the 300 pin connectors on the PIB board see Figure 2 4 Underside of processor Remove protective Covers by hand Figure 2 3 Remove Protective Covers from 300 connectors underside of MPC8360 MDS Processor Board shown Protective Covers Figure 2 4 Remove Protective Covers from 300 pin connectors MPC8360 MDS Processor Board Rev A 1 2 4 Freescale Semi
16. 15 USB 1 1 Block Charge BCSR USBVCC gt to CPU ini AB ini 5 Connector B m Vbus 836x m ID D USB OE SPEED D TXN VMO Ds D VPO 15K GND TXP sed RXN L1 lt 27 15K 1 5 48Mhz CNT Table 5 30 below also reproduced in Table 6 4 describes the USB signals with their other functions options The table shows The pin selection from the MPC8360 e The location pin on the Riser connectors that connect PIB to the MPC8360 MDS Processor Board The pin name used on the PIB The pin on the PMC on PIB The pin function for the GMII TBI the MPC8360 MDS Processor Board UCC1 amp UCC2 or TDMG e The pin function when the PIB uses UCC4 UPC1_TXEN2 And finally the pin name used by the Universal Serial Bus USB Table 5 30 USB Signals and their mix with other functions MPC8360 Pin Name Riser Conn Signals PMC on Function2 Function1 name PIB RGMII RMII PB2 P12 D13 GPIO30 PMC1 J3 55 Enet2 TXD 4 Enet4 RXD 1 RXD 3 P12 D14 GPIO31 PMC1 J3 25 Enet2 TXD 5 Enet4 RX DV RX CR 5 PB8 P12 E12 GPIO36 PMC1 J3 31 Enet2 TXD 7 Enet4 RXD O RXD 2 8360 MDS Processor Board Rev A Function3 USB OE USB TP USB TN Freescale Semiconductor 5 37 Table 5 30 USB Signals and their mix with other functions continued PB9 12 14 G
17. PIB itself The table below shows how to configure the host Processor Board for using the PIB ethernet connections as opposed to its own ethernet connections Table 6 6 Selecting GMII RGMII TBI RTBI BCSR8 0 1 Select Geth1 BCSR9 0 BCSR14 0 7 Enable Dis Enable Disa Function Mode able Geth PHY1 ble MII1 Selected 00 RGMII 00 RGMII 00 RGMII 00 RGMII 01 RTBI 01 RTBI 01 RTBI 01 RTBI 0 Enable 0 Enable 1 Disable 1 Disable 0 Enable 0 Enable 1 Disable 1 Disable 0 Disable 1 Enable 0 Disable 1 Enable 0 Disable 1 Enable 0 Disable 1 Enable RGMII MII Relevant signals connected to PIB MII RTBI MII Relevant signals connected to PIB MII MPC8360 MDS Processor Board Rev A 1 Freescale Semiconductor 6 13 MPC8360 MDS Processor Board Rev 1 6 14 Freescale Semiconductor Chapter 7 Replacing Devices This chapter provides instructions on replacing various devices on the MPC8360 MDS Processor Board 7 1 Replacing Flash Memory To remove the flash memory follow the instructions below in Figure 7 1 to Figure 7 4 below in that order Note that the flash memory can be changed no more than 50 times To replace the flash memory follow the instructions in reverse order Figure 7 4 to Figure 7 1 then secure the casing as shown in Figure 7 5 14 Figure 7 1 Flash Memory push t
18. Rev 1 Freescale Semiconductor Chapter 4 Controls and Indicators This chapter describes controls and indicators of the MPC8360 MDS Processor Board which includes switches jumpers LEDs and push buttons 4 1 Switches Figure 4 1 below shows the locations of the DIP Switches Note that when the value of the switch is Zero Close up of SW11 from underside of board swt T PCB13094V0 Figure 4 1 MPC8360 MDS Processor Board Switches Locations Descriptions of settings for the DIP switches are described below For more detailed descriptions of the bits and fields see the MPC8360 User Manual MPC8360 MDS Processor Board Rev A 1 Freescale Semiconductor 4 1 SW3 CFG_RSO CFG_RS1 CFG_RS2 CLKDIV SPMFO SPMF1 SPMF2 SPMF3 f9 ost The On DIP Switch position ON corresponds to a signal value of zero SW3 1 SW3 3 CFG_RS sets the Reset Configuration Words Source Default setting 000 RCW is retrieved from the local bus see also Section 5 1 1 SW3 4 CLKDIV selects the relationship between CLKIN and PCI SYNC OUT If MPC8360 is configured as a PCI Agent factory setting then CLK DIV is low If MPC8360 is host CLK DIV should be high Default setting Low SW3 5 SW3 8 SPMF selects the System PLL Multiplication Factor Default setting 0100 clock ratio csb_clk CLKIN 4 266MHz or csb_clk PCI_CLK
19. Selecting GPIO function for PIB PB2 P12 D13 PMC1 J3 55 Enet2 TXD 4 should PB3 12 014 GPO31 PMC1 J3 25 Enet2 TXDI5 be 1 amp 5 8 2 5 should be 00 or 01 PB5 P12 E8 GPO33 PMC1 J3 29 Enet2 TXD 6 Sig G2WIDE 0 PB8 P12 E12 GPO36 PMC1 J3 31 Enet2 TXD 7 PB11 P12 E17 GPO39 PMC1 J3 41 Enet2 RXD 7 Table 6 3 PCI UTOPIA Bus Signals PIB PMC dabo 5 PCI Function Utopia Function on PMC1 Only MPC8360 MDS Processor Board Rev A 1 Freescale Semiconductor Table 6 3 PCI UTOPIA Bus Signals continued 5 PMC1 2 3 J1 32 13 23 PG17 PMC1 2 3 J2 29 P13 D20 PG18 PMC1 2 3 J1 29 P13 C22 PG19 PMC1 2 3 J2 28 P13 B23 PG20 PMC1 2 3 J1 28 P13 A19 PG21 PMC1 2 3 J1 27 P13 K16 PG22 PMC1 2 3 J2 26 P13 J19 PG23 PMC1 2 3 J2 23 P13 H24 PG24 PMC1 2 3 J1 23 P13 G23 PG25 PMC1 2 3 J2 22 P13 F24 PG26 PMC1 2 3 J1 22 P13 E21 PG27 PMC1 2 3 J1 21 P13 D19 PG28 PMC1 2 3 J2 20 P13 C18 PG29 PMC1 2 3 J2 19 P13 B21 PG30 PMC1 2 3 J1 20 P13 A17 PG31 PMC1 2 3 J1 52 P13 D23 PF7 PMC1 2 3 J2 43 P13 C26 PF8 PMC1 2 3 J2 32 P13 D25 PF9 PMC1 2 3 J1 26 P13 A23 PF10 PMC1 2 3 J1 43 P13 E26 PF11 PMC1 2 3 J1 33 P13 F28 PF12 PMC1 2 3 J2 35 P13 G26 PF13 PMC1 2 3 J1 36 P13 H29 PF14 PMC1 2 3 J2 38 P13 J24 PF
20. asserted low TAP clock is enabled and Disabled W driven into the COP port If negated high TAP clock is disabled TAP Mode Select When asserted low drives TMS signal into Disabled COP port TAP Reset When asserted low resets TAP controller of COP Disabled Hard Reset Low provides short negative HRST pulse on the Disabled W board Soft Reset Low provides short negative SRST pulse on the Disabled board Check Stop When asserted low causes Machine Check Stop Disabled of the processor MPC8360 MDS Processor Board Rev A 5 18 Freescale Semiconductor Table 5 16 CCR COP Register Description continued Default BIT MNEMONIC upon PORESET 7 COPEN CCR COP Enable Low permits access to processor JTAG port 1 via CCR register High disables the CCR register 5 5 External Connections External connections locations are shown in Figure 5 6 below Figure 5 6 External Connections for the MPC8360 MDS Processor Board 5 5 1 P1 MiniAB USB Connector MiniAB USB connector pinout is shown in Table 5 17 P1 MiniAB USB Connector below This connector is used for connectivity to external devices USB1 1 It is accessible from the front panel of the board see Figure 1 1 for location Table 5 17 P1 MiniAB USB Connector Signal Name Description Vbus 5V Power for USB Power is generated internally if working in PCI mode or is supplied from a cable in stand al
21. fce S A OD Ba A ade bats 5 38 5 11 1 Stand Alone PIB i resen sa EIN rb RR UR be RID dcus 5 38 5 112 Inserted VPC o SENE nantes Palace ees teu teas 5 38 2422 UART rc 5 40 12 DM E RO 5 41 5 13 1 I2C CO ee 5 41 5 13 2 12 2 ae feta Ya dU add dao Dose te Ts 5 42 514 External Interrupts oos scs tacto ioe sca 5 42 5 14 1 ABORT EP eee ee ante tht ae tie atta 5 43 5 14 2 PIB Intetrupito ez e V psu vost irs diua 5 43 5 14 3 RG Internet cete Bas ee eS de rete ss A 5 43 5 14 4 RUC Interr pb tee eed deae ved REN ba 5 43 5 14 5 FEASH IrniterRIDU 2 eate Qe 5 43 5 14 6 JTAG COP Interrupt ic ont zu ced rrr ER PIE eee Pudor bie Pas 5 43 5 147 GETH ar Ce ett Ese es d toe De 5 43 oU Power Supply Sgt eee qa tud 5 43 5 15 1 Primary or GNU PED IUE 5 44 5 15 2 MPC8360E MDS Processor Board Power Supply Structure 5 44 5 15 3 Power Supply Operation 222022 ae auct etis gece
22. level debugger although it can operate properly without connecting it to the FPGA 5 1 7 Manual Hard Reset To allow a run time Hard Reset a manual Hard Reset is facilitated via SW6 Note that this cannot be done when the MPC8360E Processor Board is connected in a PC Agent Mode but instead SW1 PORESET can be used In addition a manual Hreset for the MPC8360 can be done by toggling bit 4 in the CCR Address F800000F register in the FPGA 5 1 8 Manual Soft Reset To allow a run time Soft Reset manual Soft Reset is facilitated via SW8 Note that this cannot be done when the MPC8360E Processor Board is connected in a PC Agent Mode In addition a manual Sreset for the MPC8360 can be done by toggling bit 5 in the CCR Address F800000F register MPC8360 MDS Processor Board Rev A Freescale Semiconductor 5 5 5 2 Default Settings The default settings for the MPC8360 MDS Processor Board are as follows e Clock in primary clock 66Mhz Core freq 533Mhz e CCB 266Mhz DDR 266Mhz QE 400Mhz QE Clock Primary clock x CEPMF set by SW9 4 8 Local Bus 66Mhz LBIU LCRR 0x4 e Primary DDR DDRI CFG RS 0 2 BootSeq RomLoc Read configuration word from Local Bus BCSR PCI MODE Enable PCI Clock drive 5 3 Clocking A block diagram showing internal details for the clocks of the MPC8360 MDS Processor Board is shown below in Figure 5 5 As can be seen from the diagram all i
23. or 10 For Selecting GPIO function for PIB BCSR9 0 should be 1 amp BCSR8 0 1 should be 00 or 01 Sig nMIIIEN 0 Freescale Semiconductor Table 6 2 GMII1 RGMII1 TBI1 RTBI1 amp GMII2 RGMII2 TBI2 RTBI2 continued action for MPC8360 Pin Riser Conn PIB GPIO Pin MPC XMC MII GMII 1 MII GMII 2 GETH PIB PA13 P12 A23 GPIO10 2 46 GEnet1 RXD4 CO For GMII TBI func tion BCSR9 0 should be 0 amp PBO P12 D10 GPO28 PMC1 J3 1 Enet1 RXD 6 BCSR8 0 1 should be 11 or 10 1 P12 D11 GPO29 PMC1 J3 5 Enet1 RXD 5 For Selecting GPIO function for PIB BCSR9 0 should 4 P12 D16 GPO32 PMC1 J3 7 Enet1 RXD 7 PB6 P12 E9 GPO34 PMC1 J3 11 Enet1 TXD 4 BE c a M Sig GIWIDE 0 PB7 12 11 GPO35 1 13 13 Enet1 TXD 5 3 PB9 P12 E14 GPO37 PMC1 J3 35 Enet1 TXD 6 PB10 12 15 8 PMC1 J3 37 Enet1 TXD 7 PC3 P12 A28 GPIO59 PMCO J3 29 always used for GETH PA26 P12 C13 GPIO23 PMCO J3 31 GEnet2 RXD 3 For RGMII RTBI function BCSR9 1 PA17 12 17 GPIO14 PMCO J3 35 GEnet2 TXD 0 should be 0 For Selecting GPIO PA29 P12 D7 GPIO26 3 37 GEnet2 RX_DV function for PIB BCSR9 1 should PA18 P12 B18 GPIO15 PMCO J3 49 GEnet2 TXD 1 be 1 Sig GONARROW 0 PA19 P12 B20 GPI
24. the G ETH2 controller For details on possible values and their meanings See Table 5 9 May be rewritten any time via LBIU Note If mounted on PIB should be only Reduced mode 4 TSEC1MST Master Mode If high GETH1 transceiver configures in Master Mode otherwise when low GETH1 transceiver operates as Slave May be rewritten any time via LBIU 5 TSEC2MST GETH2 Master Mode If high 2 transceiver configures in Master Mode otherwise when low 2 transceiver operates as Slave May be rewritten any time via LBIU 8360 MDS Processor Board Rev A 5 12 Freescale Semiconductor Table 5 8 BCSR8 Register Description continued DEF on 7 FLEN FLASH Enable Low enables Flash accesses When high R W Flash operation is not available PSRAM part may be enabled instead May be rewritten any time via Table 5 9 G ETH Port Mode Setting Value TSEC1 2M 00 The G ETH controller operates the RGMII protocol using only four transmit data signals and four receive data signals 01 The G ETH controller operates in the RTBI protocol using only four transmit data signals and four receive data signals 10 The G ETH controller operates in the GMII protocol using eight transmit data signals and eight receive data signals 11 The G ETH controller operates in the TBI protocol using ten transmit data signals and eight receive data signals 5 4 10 BCSR
25. the MPC8360E User s Manual The PIB signal name is the name of the signal on the PIB that uses the indicated pin This is not necessarily the name of the signal on the MPC8360 device or on the specific module connected to the slot on the PIB e Function 1 and Function 2 indicate that the specific pin can have two different functions depending on the configuration of the MPC8360 device see first row in Table 6 1 below Table 6 1 TDM UPC Ethernet Signals Riser Connector MPC8360 PIN PIB Signal Function 1 Function 2 MPC8360 Clock Number Number amp USB Pin Number UTOPIA UTOPIA PCI 2xRGMII 4 Devices GETH 8TDM 4xRMII UTOPIA POS 4 UTOPIA PCI PMCO J3 40 P11 G7 PA1 MDIO MDIO PMC1 J3 34 2 4 63 PMC3 J2 52 PMCO J3 24 P11 G5 PA2 MDC MDC PMC1 J3 30 PMC2 J4 58 PMC3 J2 54 P13 F18 PAO PAO No GPIO Num ber 3 64 P12 A8 PA3 GPIOO 3 54 12 10 4 GPIO1 PMC1 J3 58 P12 A11 5 GPIO2 PMC1 J3 60 12 13 6 GPIO3 46 12 14 GPIO4 MPC8360 MDS Processor Board Rev A 1 Freescale Semiconductor 6 3 Table 6 1 TDM UPC Ethernet Signals continued
26. 000000 SS EN 1 ADJST 2 50 BNDS 0xE0002000 0x00000007 first 128MB CS0 CONFIG 0 0002080 0 80000102 13 row bits 10 columns bits TIMING_CFG_1 0 0002108 0x37343321 TIMING_CFG_2 OxE000210C 0x00000800 MPC8360 MDS Processor Board Rev A 1 Freescale Semiconductor Table 3 4 Init DDR values for 2 x 32 bit continued DDR_SDRAM_CFG OxE0002110 0x42008000 32 BE 0 64 bit bus is used 2T EN 1 DDR SDRAM MODE 0 0002118 0 20000163 DDR_SDRAM_INTERVA 0002124 0x045B0100 L delay before enable DDR_SDRAM_CFG 0 0000130 0xC2008000 Second DDR Controller Registers CAUTION CAUTION SDDRIOE SECONDARY DDR IO ENABLE MUST BE SET TO 1 USE A CONFIGURATION WORD WHICH INCLUDES SDDRIOE 1 OR SET SDDRIOE 1 THROUGH BCSR7 3 AND CNFLOCK BCSR13 3 AND PORE SET BCSRI 1 4 CLK CNTL 0 0000130 0 82000000 CSO_BNDS 0 0000000 0x0008000B first 64 CONFIG 0 0000080 0 80000101 13 row bits 9 columns bits CS1_BNDS 0 0000008 last 64 CS1_CONFIG 0 0000084 0 80000101 13 row bits 9 columns bits TIMING_CFG_1 0 0000108 0 37343321 CFG 2 0 000010 0 00000800 DDR_SDRAM_CFG 0 0000110 0x420C8000 DDR SDRAM MODE 0 0000118 020000163 DDR_SDRAM_INTERV 0 0000124 0 045 0100 AL delay before enable DDR_SDRAM_CFG 0 000110 0xC20C8000 8360 MDS Processor Board
27. 1 2 49 12 14 PD20 GPIO102 RMII6 RXDO 2 9 12 15 PD21 GPIO103 RMII6 RXD1 PMCO J2 31 P12 H17 PD22 GPIO104 PMCO J1 60 P12 H18 PD23 GPIO105 PMCO J1 59 P12 H20 PD24 GPIO106 PMCO J2 49 P12 H21 PD25 GPIO107 2 8 12 23 PD26 GPIO108 RMII6 TXDVCRS 2 10 P12 H24 PD27 GPIO109 PMCO J3 5 P12 F27 PC24 GPIO80 PMCO J2 23 12 28 25 GPIO81 PMCO J3 19 P12 G29 PD16 GPIO98 3 13 12 9 PD17 GPIO99 RMII CLK UCC 3 5 7 PMC1 J3 47 P12 G5 15 GPO71 It can be used for UCC CLK16 3 4 5 6 7 8 PMC1 J3 43 P12 C3 PC6 GPO62 RMII CLK UCC 4 6 8 CLK7 PMC1 J3 61 P12 K11 PE16 GPO126 PMC1 J3 4 P12 K12 PE17 GPO127 PMC1 J3 49 P12 K16 PE19 GPO129 PMC1 J3 59 P12 K20 PE22 GPO132 PMC1 J3 6 P12 K22 PE23 GPO133 PMC1 J3 53 P12 K23 PE24 GPO134 PMC1 J3 55 P12 K25 PE25 GPO135 PMC1 J3 10 P12 J26 PE26 GPO136 MPC8360 MDS Processor Board Rev A 1 6 6 Freescale Semiconductor Table 6 1 TDM UPC Ethernet Signals continued MPC8360 MDS Processor Board Rev A 1 Riser Connector MPC8360 PIN PIB Signal Function 1 Function 2 MPC8360 Clock Number Number amp USB Pin Number PMC1 J3 12 P12 E28 PE27 GPO137 PMC1 J3 16 P12 J25 PE14 GPO124 PM
28. 1 RTBI 01 RTBI 01 RTBI Enable 0 Enable 1 Disable 1 Disable o Enable 0 Enable 1 Disable 0 Disable 1 Enable 0 Disable 1 Enable 0 Disable 1 Enable 0 Disable RGMII MII Signals not used for MII bus connected to PIB Relevant signals connected to PIB MII not supported yet RTBI MII not supported yet Relevant signals connected to PIB 8360 MDS Processor Board Rev A Freescale Semiconductor 5 35 Table 5 29 Selecting GMII RGMII TBI RTBI or PIB continued sm Enable Disable Enable Disable GETH Mode Geth PHY1 Function Selected 01 RTBI 1 Disable 1 Enable MII not supported yet Signals not used for MII bus connected to PIB 10 GMII Enable Disable GMII 10 GMII Enable Enable GMII 10 GMII Disable Disable All signals connected to PIB 10 Disable Enable not supported yet Signals not used for bus connected to PIB Enable Disable TBI Enable Enable not supported yet Signals not used for bus connected to PIB Disable Disable All signals connected to PIB Disable 1 Enable not supported yet Signals not used for bus connected to PIB 5 10 USB The USB module is a standard Universal Serial Bus for implementing a USB interface in compliance with the USB 1 1 specification It is able to act as
29. 1 RXD 3 PMC1 J3 1 P12 D10 PBO GPIO28 PMC1 J3 5 12 011 1 29 1 13 7 P12 D16 PB4 2 PMC1 J3 11 P12 E9 PB6 GPIO34 Enet3 RXD O RXD 2 PMC1 J3 13 P12 E11 PB7 GPIO35 Enet3 RXD 1 RXD 3 PMC1 J3 17 P12 E18 PB12 GPIO40 PMC1 J3 19 P12 E20 PB13 GPIO41 PMC1 J3 55 P12 D13 PB2 GPIO30 PMC1 J3 25 P12 D14 PB3 GPIO31 PMC1 J3 29 P12 E8 PB5 GPIO33 PMC1 J3 31 P12 E12 PB8 GPIO36 PMC1 J3 35 P12 E14 PB9 GPIO37 PMC1 J3 37 P12 E15 PB10 GPIO38 PMC1 J3 41 P12 E17 PB11 GPIO39 3 34 P12 H26 PEO GPIO110 1 41 12 10 4 GPIO114 3 30 P12 J13 PEG GPIO116 2 55 P12 J14 PE7 GPIO117 PMCO J1 10 P12 H27 PE1 GPIO111 1 54 12 22 12 GPIO122 2 54 P12 G26 PD14 GPIO96 1 61 P12 G28 PD15 GPIO97 1 53 12 10 PD18 GPIO100 PMCO J2 49 P12 H14 PD20 GPIO102 PMCO J2 9 P12 H15 PD21 GPIO103 2 8 12 23 PD26 GPIO108 Enet8 RX ER Enet8 TXD OJ TXD 2 Enet8 TXD 1J TXD 3 Enet8 TX EN Enet8 RXD O J RXD 2 Enet8 RXD 1 RXD 3 Enet3 TXD 0 Enet3 TXD 1 Enet3 TX_EN Enet3 RXD 0 Enet3 RXD 1 Enet3 RX_DV Enet3 RX_ER USB_OE Enet4 does not ume Rev Proto1 USB_TN USB_RP USB_RXD USB_RN weno 7 MPC8360 MDS Processor Board Rev A 1 6 12 Freescale Semiconductor There are ethernet connections on the
30. 15 PMC1 2 3 J1 37 P13 K23 PF16 PMC1 2 3 J4 5 P13 J18 PF17 PMC1 2 3 J2 42 P13 C25 PF18 PMC1 2 3 J2 39 13 0 PF19 PMC1 2 3 J1 17 P13 G28 PF20 PMC1 2 3 J1 41 P13 F30 PF21 PMC1 2 3 J1 10 P13 E27 PF22 PMC1 2 3 J1 16 P13 J25 PF23 PMC1 2 3 J2 55 P13 A25 PF24 MPC8360 MDS Processor Board Rev A 1 PCI Function Utopia Function on PMC1 Only PCI_GNT_B 1 UPC2_RxADDRI 4 6 10 Freescale Semiconductor Table 6 3 PCI UTOPIA Bus Signals continued PIB PMC icm n Utopia Function PMC1 Only PMC1 2 3 J2 57 P13 K25 PF25 PCI_GNT_B 2 UPC2_RxEN_B 1 PMC2 J1 13 P11 A28 PF26 PCI CLK 0 Not Used UPC2 RxEN 3 3 36 13 13 27 PCI CLK 1 Master PCI CLK for Host PMC1 J1 13 P13 A28 PF28 PCI CLK 2 UPC2 CLKO TXCLK PMC1 J2 47 P12 B12 PF4 M66EN UPC2 RxDATA 6 PMC1 J2 54 P13 C29 PF3 UART2_SIN UPC2 RxDATA 9 PMC1 J2 9 P13 E29 PFO UART2_SOUT UPC2 RxDATA 5 PMC1 J2 8 P13 K20 PF1 UART2 CTS UPC2 RxDATA 1 PMC1 J2 10 P13 K22 PF2 UART2_RTS UPC2 RxDATA 0 PMCO J3 36 P13 J13 Clock B XPCI CLK1 uff PMC2 J1 13 P13 A28 Clock B XPCI CLKO uff Table 6 4 USB Signals 8360 Pin Riser Conn Signals PMC on PIB Function2 Function1 Function3 Name name PIB RGMII RMII PB2 P12 D13 GPIO30 PMC1 J3 55 Enet2 TXD 4 Enet4 RXD 1 RXD 3 USB OE PB3 P12 D14 GPIO31 PMC1 J3 25 Enet2 TXD
31. 4 SW4 SW4 1 SW4 2 Configuration Boot Sequencer Boot sequencer loads configuration data from the serial ROM a Default setting 00 disables access to 2 ROM SW4 3 SW4 5 Boot ROM location Tr r BOOISEQO 271 Default setting 110 provides Flash boot on local bus Pc 2 SW4 6 DDR Clock Mode Ba SOMO ED Default setting 0 DDR_Controller_Clock csb_clk ratio is 1 1 ae 25 SWA 7 Local Bus Clock Mode 2 ene 52 Default setting 0 the local bus and Secondary DDR memory controller i s will operate with a frequency equal to csb_clk i SW4 8 CEPDF 8c GERDE B Default setting 0 QE_clk primary clock input X CEPMF SW9 SW9 1 PCI MODE Default setting this switch should be only in 0 state see BCSR10 4 SW9 2 PCICKDRV 1 lt 0 Default setting 1 PCI clock output buffers are enabled 1 PCIMODE 1 ON SW9 3 FCFG sets RCW source on local bus 2 PCICKDRV 2 0 BCSR source settings from DIP switches SW3 1 SW3 3 3 3 1 Flash source 4 4 Default setting 1 Flash boot 5 CEPMF1 5 SW9 4 SW9 8 CEPMF 6 CEPMF2 6 QE PLL multiplication factor 7 CEPMF3 7 Default setting 6 00110 8 CDPMF4 8 If CLKDIV 0 then for 400Mhz CEPMF should be 6 MPC8360 MDS Processor Board Rev A 1 Freescale Semiconductor SW10 W10 1 SW10 7 core PLL setting sets the ratio between the e300 core clock and the inter
32. 5 Enet4 RX DV RX USB TP PB8 P12 E12 GPIO36 PMC1 J3 31 Enet2 TXD 7 Enet4 RXD O RXD 2 USB TN PB9 P12 E14 GPIO37 PMC1 J3 35 Enet1 TXD 6 Enet4 TXD O TXD 2 USB RP PB10 P12 E15 GPIO38 PMC1 J3 37 Enet1 TXD 7 Enet4 TXD 1 TXD 3 USB RXD PB11 P12 E17 GPIO39 PMC1 J3 41 Enet2 RXD 7 Enet4 TX_EN USB_RN PC20 P12 C3 GPIO76 1 17 TDMG_TXCLK XUPC1_TXEN2 USB CLK CLK21 BRG9 Table 6 5 GETH Signals if traverses the PIB 3 PIB Text P Riser Conn MPC8360 Pin Name Pin Function1 Pin Function2 Pin Function3 CLK UCC 3 5 7 PMC1 J3 47 P12 G5 PC15 GPO71 It can be used for UCC CLK16 3 4 5 6 7 8 PMC1 J3 43 P12 C3 PC6 GPO62 CLK UCC 4 6 8 CLK7 PMC1 J3 61 P12 K11 PE16 GPO126 PMC1 J3 4 P12 K12 PE17 GPO127 PMC1 J3 49 P12 K16 PE19 GPO129 PMC1 J3 59 P12 K20 PE22 GPO132 8360 MDS Processor Board Rev A 1 Freescale Semiconductor 6 11 Table 6 5 GETH Signals if traverses the PIB continued PMC1 J3 6 P12 K22 PE23 GPO133 PMC1 J3 53 P12 K23 PE24 GPO134 PMC1 J3 55 P12 K25 PE25 GPO135 PMC1 J3 10 P12 J26 PE26 GPO136 PMC1 J3 12 P12 E28 PE27 GPO137 PMC1 J3 16 P12 J25 PE14 GPO124 PMC1 J3 18 P12 K10 PE15 GPO125 PMC1 J3 22 P12 K14 PE18 GPO128 PMC1 J3 24 P12 K17 PE20 GPO130 Enet8 RXD O RXD 2 PMC1 J3 28 P12 K19 PE21 GPO131 Enet8 RXD
33. 60 MDS Processor Board Rev A 5 26 Freescale Semiconductor 5 8 Local Bus This section describes devices that are connected to the local bus of the MPC8360 MDS Processor Board ADD LATCH LAD 31 16 gt LLA 31 0 ADD BUFFER LAD 15 0 p LLA 31 16 gt E LLA 29 15 LLA 29 15 LLA 29 15 LLA 26 6 SDRAM SDRAM SDRAM 32 MB 32 MB Parity LAD 31 16 LAD 15 10 LDP 3 0 XDIT 0 MPC836X 31 0 0 Riser Conn XD 15 0 RIGHT LDP 3 0 LA 31 27 LGPL 5 0 gt XCTRL LWE LBCTL Ready PORESET PORESET Figure 5 9 Local Bus Scheme 5 8 1 Address Latch Data Transceiver The address latch buffer used is Texas Instruments SN74ALVTH32373GKE The address latch buffer latches the addresses and drives them to the fast bus which includes SDRAM components It also drives the address to an extra 16 bit buffer T s SN74ALVCH32244KR for the slow bus which connects to Flash and BCSR in addition to PIB components via riser connectors The data transceiver is On Semi s MC74LCX245DT One side of the buffer is connected to the MPC863X LAD 0 31 Only Flash BCSR and PIB Riser connectors are connected to the other side of the data transceiver 8360 MDS Processor Board Rev A Freescale Semiconductor 5 27 5 8 2 SDRAM The SDRAM memory is implemented using thre
34. 9 Status Register The BCSRO serves as an 8 bit control register BCSR9 may be read or written at any time BCSR9 defaults are attributed at the time of Power On Reset or HRESET BCSR9 fields are described below in Table 5 10 Table 5 10 BCSR9 Register Description DEF BIT MNEMONIC on ATT HRST RW GETH1EN 2 GETHRST RS232EN GETH Transceiver 1 Enable When low enables the Geth PHY 1 When negated high GETH PHY 1 enters standby mode May be rewritten via LBIU GETH Transceiver 2 Enable When low enables Get PHY 2 When negated high GETH PHY 2 enters standby mode May be rewritten via LBIU GETH Transceiver Reset The GETH devices are reset when the GETHRST is asserted low The Board Hard Reset signal of the MPC836x will reset GETH phy devices This bit may be rewritten via LBIU When this bit is negated high that is toggled from 0 to 1 the PHY configuration is taken from the current values in BCSRS 0 5 After the PHY configuration is completed this bit is cleared high UART Ports Transceivers Enable Upon activation low the Dual RS232 Transceiver using the UART ports of the MPC8360 is enabled When negated high the RS232 Transceiver enters standby mode May be rewritten via LBIU 8360 MDS Processor Board Rev A Freescale Semiconductor Table 5 10 BCSR9 Register Description continued MNEMONIC on HRST BOOTWP SIGNALO SIGNAL1 CEUARTEN BOOT 2 EEPRO
35. C1 J3 18 P12 K10 PE15 GPO125 PMC1 J3 22 P12 K14 PE18 GPO128 PMC1 J3 24 P12 K17 PE20 GPO130 PMC1 J3 28 P12 K19 PE21 GPO131 6 13 P13 F15 GPIO PA31 no Number GPIO Num ber Table 6 2 GMII1 RGMII TBI1 RTBI1 amp GMII2 RGMII2 TBI2 RTBI2 z 5 action for MPC8360 Pin Riser Conn PIB GPIO Pin MII GMII 1 MII GMII 2 PAO P13 F18 PAO No GPIO XMCO J06 E1 GEnet1 RXCLK always used for Num 5 GETH PA3 12 8 GPIOO 3 64 GEnet1 TXD 0 For RGMII RTBI function BCSR9 0 PA4 P12 A10 GPIO1 3 54 GEnet1 TXD 1 should be 0 For Selecting GPIO PA5 P12 A11 GPIO2 PMC1 J3 58 GEnet1 TXD 2 function for PIB 5 9 0 should PA6 P12 A13 GPIO3 PMC1 J3 60 GEnet1 TXD 3 be 1 Sig GINARROW 0 12 14 GPIO4 3 46 GEnet1 TX_EN PAQ P12 A17 GPIO6 3 48 GEnet1 RXD 0 PA10 P12 A19 GPIO7 3 52 GEnet1 RXD 1 PA11 P12 A20 GPIO8 PMC1 J3 54 GEnet1 RXD 2 PA12 P12 A22 GPIO9 3 58 GEnet1 RXD 3 PA15 P12 B14 GPIO12 3 60 GEnet1 RX_DV PC9 P12 C30 GPIO65 1 40 GEnet1 GTX_CLK always used for GETH 12 28 64 PMC1 J3 52 always used for GETH PC10 P12 E1 GPO66 3 6 Enet1 TXCLK MII ________ 8 12 16 GPIO5 1 48 GEnet1 TX_ER For GMII TBI func tion BCSR9 0 14 12 25 GPIO11 2 57 GEnet1 CRS should be 0 amp BCSR8 0 1 should PA16 P12 B15 GPIO13 PMCO J2 19 GEnet1 RX ER be 11
36. CK This line is qualified with same manner as TDI and changes the state of the JTAG machines This line is pulled up internally by the MPC8360 11 nSRSTc When asserted by an external H W generates Soft Reset sequence for the MPC8360 Pulled Up on the ADS using a 4 7KQ resistor When driven by an external tool MUST be driven with an Open Drain gate Failure to do so might result in permanent damage to the processor and or to ADS logic 13 nHRSTc When asserted by an external H W generates Hard Reset sequence for the MPC8360 Pulled Up on the ADS using a 4 7KQ resistor When driven by an external tool MUST be driven with an Open Drain gate Failure to do so might result in permanent damage to the processor and or to ADS logic 8360 MDS Processor Board Rev A Freescale Semiconductor 5 21 Table 5 19 Connector continued Signal Name Description 14 KEY No pin in connector Serves for correct plug insertion See Figure 5 7 for location 15 Check Stop Output Machine Check Stop Output X X X X X X X X X X X X 16 14 2 Figure 5 7 P8 COP connector front view 5 5 7 P9 FPGA s In System Programming ISP This is a 16 pin generic 0 100 pitch header connector providing In System Programming capability for on board programmable logic devices by Xilinx FPGA Spartan 2E The pinout of P9
37. CSRO may be read or written at any time BCSRO defaults are attributed immediately after a Power On Reset or HRESET BCSRO fields are described below in Table 5 2 Table 5 2 BCSRO Register Description Local Bus Secondary DDR Controller Selects local bus SW4 7 Sampledat and secondary DDR memory controllers clock ratio The bitis HRESET set by default by appropriate DIP switch May be rewritten via LBIU 1 1 DDR SDRAM Clock Mode If this bit set high the DDR SWA 6 SDRAM memory controller will operate with frequency equal Sampled at to twice the frequency of the csb clk If this bit is low the HRESET DDR SDRAM memory controller will operate at the csb_clk frequency A DIP switch may change DDRCM bit setting May be rewritten any time via LBIU set low by default May be rewritten via LBIU HRESET 4 7 4 7 System PLL Multiplication Factor The four bits reflect SW3 5 8 SPMFT 0 3 signals logic level during Hard Reset Sampled at Configuration sequence The bits are set by default by PORESET neg 2 8 2 3 SVCOD 0 1 VCO Division The two bits reflect SVCOD 2 3 signals logic SW11 1 2 level during Hard Reset Configuration sequence The bits are Sampled at appropriate DIP switch May be rewritten via LBIU 5 4 2 BCSR1 Status Register On the board BCSR1 acts as a control register BCSR1 which may be read or written at any time receives its defaults immediately after Power On or PORESET BCSRI fields are described be
38. Geth PHY1 Function Selected 00 RGMII 0 Enable 0 Disable RGMII 00 RGMII Enable 1 Enable MII 01 RTBI Enable Disable RTBI 01 RTBI Enable 1 Enable MII 01 RTBI Disable MII 5 9 6 RMII via the PIB The PIB contains the RTL8208 PHY device which supports an 8 port integrated physical layer and transceiver for 10Base T and 100Base TX When used with the MPC8360 MDS Processor Board 6 of these 8 ports can be utilized and are connected to UCC 3 8 MPC8360 MDS Processor Board Rev A Freescale Semiconductor 5 33 The input clock to the RTL8208 device is 50 arriving from the clock oscillator This input clock is split to 2x50MHXx lines one to the MPC8360 Clock 16 and the other to Clock 7 Clock 16 is the only clock that can supply the UCC RMII or the ODD UCC Clock 7 can be used for the Even numbered UCCs Figure 5 14 below is a block diagram showing the connection scheme of the RMII PHY on the PIB to the MPC8360 MDS Processor Board Note that ENET6 amp ENET7 share the same pins with TDM amp Therefore bus switch must be placed on the sharing signals in order to buffer the signals for a short trace In order to do this the following should be written to I2C address 0x26 to Reg 6 write Ox7ffc and then to Reg 2 0x7ffe That is 0x26 0x06 Ox7ffc 0x26 0x02 0 7 DC amp MDIO Base Address 01XXX 8xRMII PHY Enet4 is not functional in MPC8360PB RevPr
39. M Protect When asserted low BOOT EEPROM functions normally when negated high write operations are disabled May be rewritten via LBIU Signal LED 0 A dedicated Green LED is illuminated when SIGNALO is active low The LED is unlit when in it s inactive default state high During the Reset Configuration sequence the illuminated LED indicates the SRESET assertion The user may utilize the LED for s w Slave signalling purposes May be rewritten via LBIU Signal LED Slave 1 dedicated Red LED is illuminated when SIGNAL1 is active low The LED is unlit when in its inactive default state high During the Reset Configuration sequence the illuminated LED indicates the HRESET assertion May be rewritten via LBIU For CE UART on the Processor Board this bit should be active low When this bit is negated high the UPC2 ATM is used 8360 MDS Processor Board Rev A pp Freescale Semiconductor 5 4 11 BCSR10 Status Register On the board BCSR10 acts as a control register BCSR10 which may be read or written at any time receives its defaults upon Power On or PORESET BCSR10 fields are described below in Table 5 11 CFG_CLKIN_DIV CFG RS 0 2 PCI MODE FLASHPRT JTAG2SEL Table 5 11 BCSR10 Description DEF on MNEMONIC Function PORESET CLKIN Division The reflects CFG_CLKIN_DIV signal logic level during the Power On Reset Configuration sequence If low agent mode CLKIN is not c
40. MPC8360 MDS Processor Board User Manual Rev A 1 05 2006 vA freescale semiconductor MPC8360 MDS Processor Board Rev 1 Freescale Semiconductor Contents Chapter 1 General Information 1 1 TEGO DUCTION gly awit 1 1 12 Working Configurations ie ud ances tacks ER RE de ees 1 1 1 2 1 Stand Alone Mode 1 1 12 2 PIB Combined Mode as 1 2 1 2 3 Agent Mode Im PC or PIB cave eae c RIA ee dg s 1 2 1 3 MPC8360E MDS Processor 1 2 1 3 1 ORNS o vsu ety ae hate ve ad re 1 2 1 3 2 Ext rnal Connections REPRE RR NOIRE UR ERR E 1 3 1 3 3 Block Diagram on esce ago e QU e eL s atc edd ds 1 5 1 4 Definitions Acronyms and Abbreviations 1 6 1 5 Related 1 7 Specifications quet eee et Grd ah te to hase tu umet fut 1 7 Chapter 2 Hardware Preparation and Installation 2 1 Unpacking Insteictlons a ALN ea 2 1 2 2 mstallattan id
41. O16 3 53 GEnet2 TXD 2 PA24 P12 C10 GPIO21 3 55 GEnet2 RXD 1 PA25 P12 C12 GPIO22 3 59 GEnet2 RXD 2 PA20 P12 B21 GPIO17 PMCO J3 4 GEnet2 TXD 3 PA21 P12 B23 GPIO18 3 16 2 PA23 P12 B26 GPIO20 3 18 GEnet2 RXD 0 PC28 No GPIO P13 A10 PC28 No GPIO 1 GEnet2 TBIRXCLK always used for Number Number 1 GETH 1 13 15 1 GPIO 06 1 GEnet2 RXCLK always used for Number 3 GETH PC2 12 13 GPIO58 06 5 GEnet2 GTXCLK always used for GETH PC16 P12 K26 GPI72 2 58 Enet2 TXCLK MII PA22 P12 B24 GPIO19 PMCO J2 23 Enet2 TX ER For GMII TBI func tion BCSR9 0 PA30 P12 D8 GPIO27 3 41 GEnet2 RX_ER should be 0 amp BCSR8 2 3 should PA28 P12 C16 GPIO25 PMCO0 J3 12 Enet2 CRS be 11 or 10 For Selecting GPIO function for PIB BCSR9 1 should be 1 amp BCSR8 2 3 should be 00 or 01 Sig nMIDEN 0 8360 MDS Processor Board Rev 1 Freescale Semiconductor Table 6 2 GMII1 RGMII1 TBI1 RTBI1 amp GMII2 RGMII2 TBI2 RTBI2 continued action for MPC8360 Pin Riser Conn PIB GPIO Pin MPC XMC MII GMII 1 MII GMII 2 GETH PIB PA27 P12 C15 GPIO24 1 47 Enet2 RXD4 COL For GMII TBI func tion BCSR9 0 PB12 12 18 GPO40 PMC1 J3 17 Enet2 RXD 5 should be 0 amp BCSR8 2 3 should PB13 P12 E20 GPO41 PMC1 J3 19 Enet2 RXD 6 be 11 or 10 For
42. PIO37 PMC1 J3 35 Enett TXD 6 Enet4 TXD O TXD 2 USB RP PB10 12 15 8 1 13 37 Enett TXD 7 Enet4 TXD 1JTXD 8 USB PB11 12 17 GPIO39 PMC1 J3 41 Enet2 RXD 7 Enet4 TX EN USB USB CLK PC20 P12 C3 GPIO76 1 17 TDMG TXCL XUPC1 TXEN2 K CLK21 BRG9 5 11 Debugging Applications 5111 Stand Alone and on PIB Chip debugging is provided via the JTAG port While the MPC8360 MDS Processor Board functions as a host on PIB riser connectors or as a Stand Alone the standard 16 pin JTAG COP connector P8 see also Section 5 5 6 is used to connect a USB Tap to which a PC with CodeWarrior is connected 5 11 2 Inserted in PC When the MPC8360 MDS Processor Board functions as an agent plugged into a PC s PCI slot the access to JTAG COP interface is available via the PCI bus and a special register implemented in the FPGA called the CCR described below In this case the PC acts as a host and debugging is carried out using CodeWarrior or a similar IDE installed on the PC For debugging purposes the PC host may download program code to an inbound memory window in the address space of the MPC8360 MDS Processor Board e g DDR SDRAM on its local bus The access to the JTAG COP debug port can be reached by using the COP control register CCR The CCR is mapped on the local bus memory space which allows it to be seen from the PCI host Manipula
43. RX DV RXD 3 0 RXD 3 0 Figure 5 12 RGMII Signal Mapping 5 9 4 Reduced Ten Bit Interface RTBI The RTBI interface pin mapping is shown in Table 5 26 The RTBI supports only 1000Base T This interface reduces the number of pins between the PHY and the MPC836x device to 12 pins The RTBI to copper interface is selected by software through the MDC and MDIO pins or by BCSR8 0 5 and BCSR9 0 2 Table 5 26 RTBI Signals RTBI Signal Name PHY Signal Name GTX CLK GTX CLK TD4 TD9 TX EN TD 0 3 TXD 3 0 RCX RXCLK RD4 RD9 RX DV RD 3 0 RXD 3 0 Figure 5 13 shows the signal mapping between the MPC8360 device and PHY in RTBI mode 8360 MDS Processor Board Rev A Freescale Semiconductor 8360 RTBI mode PHY M gt TD4_TD9 gt TX EN TDI3 0 gt TXD 3 0 as RX_CLK RD4_RD9 RX DV lt Beis RXDJ 3 0 Figure 5 13 RTBI Signal Mapping 5 9 5 RGMII or RTBI via the PIB In order to use the maximum number of pins for functions between the processor board and the PIB configure UCC1 2 to use the RGMII or RTBI protocols which use fewer pins than or TBI The table below shows how to do this Note that in this case GETH PHY1 connection and must be disabled Table 5 27 Selecting GMII RGMII TBI RTBI or PIB sum Select Geth1 Enable Disable Enable Disable Mode
44. Setting when MPC8360E MDS Processor Board is 5 24 5 6 3 PCI Setting when MPC8360E MDS Processor Board is 5 24 Bf SOD Read wine e 5 25 De BUS ites ath em att 5 27 5 8 1 Address Latch Data 5 27 5 8 2 SDRAM os a Ad ai atl Saal ORAS 5 28 5 8 3 Flash Memory de aad eee as ee diu RT V b ded 5 29 S GETH Rees se ere NO eee ee a cedit seien 5 29 MPC8360 MDS Processor Board Rev A 1 2 Freescale Semiconductor 5 9 1 DNAS Ee bk DRE hs 5 30 5 9 2 Ten Bit Interiace TBI Foot atu ae ab Os 5 30 5 9 3 Reduced Pin Count GMII RGMII iiu era A RUD aden AUR a lon 5 31 5 9 4 Reduced Ten Bit Interface RIBI d vedete a Su et tes 5 32 5 9 5 via the gov SR La E d dese Sane 5 33 5 9 6 RMIlvi the PIB obe e fp S 5 33 5 9 7 SUMMA ys iq 5 35 USB ted 5 36 2 11 Debuseino Applications soot cim oo bec
45. a device or host controller and provides interfaces to negotiate the host or peripheral role on the bus A dedicated USB transceiver made by Fairchild USBI1T11AMxX is provided A MiniAB connector see Section 5 5 1 on page 5 19 provides functioning in both device and host modes To correctly support the two different speed modes Full Speed 12Mbit s and Low Speed 1 5Mbit s when being used either as a device or as a host a detachable pull up resistor is provided over the D line of the USB controlled by the USB_SPEED bit of BCSR13 When functioning as a host and when USB_SPEED 15 in low speed level low D is pulled up while D remains floating When the USB_SPEED bit is in high speed level D is pulled up and D floats When functioning as a device D and D are both connected directly to the line MPC8360 MDS Processor Board Rev A 5 36 Freescale Semiconductor Vbus Voltage is monitored by Charge pumps that provide 5V power Vbus and monitor the power fault on the MiniAB connector A Vbus detection failure on the USB 1 1 Serial Mode is reported to the MPC836x by an IRQ signal A 48Mhz clock is input to the MPC8360 pin PC20 clock 21 and BRG15 The 48Mz is used for full speed and can be divided internally To use this clock for Low speed use BRG9 Figure 5
46. a s ata SEN he RECS 2 1 2 2 1 For Stand Alone Modes roh 2 2 2 22 For PIB Combined 2 4 2 2 3 OG oo ue O aa EAA 2 11 Chapter 3 Memory Map 3 1 MPC8360E MDS Processor Board 3 1 32 Configuration Registers 1 3 2 Chapter 4 Controls and Indicators 4 1 WIC ES Gene LEM SS OLE EN Iu 4 1 AD des 4 4 UD Seis FM 4 5 4 4 Other Controls and 4 6 4 41 254 ek Vb met vod a ua s 4 6 5 Functional Description 5 1 Reset amp Reset Configuration 2 isaac eR UR UE A e 5 1 5 1 1 Reset Clocking and Configuration Initialization 5 1 22152 Reset Circuit ou ata inte tod te pede s AU sn RE a 5 3 MPC8360 MDS Processor Board Rev A 1 Freescale Semiconductor 1 5 1 3 MPC8360E MDS Processor Board Reset 5 3 5 1 4 POWELL o ceo abarca F
47. agent on the PIB Insert PCI adaptor or adaptors into the PIB as shown in Figure 2 11 and Figure 2 12 then insert the Processor Board into an adaptor using its PCI edge connector as shown in Figure 2 13 Operate Code Warrior to verify that the processor board has been installed properly 3 Connect external cables in accordance with your development needs 4 Verify that LD1 and LD2 turn on and then turn off see Figure 2 2 for location They should be on for only a few moments This indicates that the board has successfully undergone the boot up sequence as Agent QOC3 Module Figure 2 14 PIB with one Processor Board as Host another as Agent and a QOC3 module MPC8360 MDS Processor Board Rev 1 Freescale Semiconductor 2 11 MPC8360 MDS Processor Board Rev 1 Freescale Semiconductor 3 3 1 MPC8360 MDS Processor Board Mapping The MPC8360 Memory Controller governs all access to the processor memory slaves Consequently the memory map may be reprogrammed according to user needs The memory map defined in Table 3 1 is only a recommendation The user can choose to work with alternative memory mapping It should be noted that the described mode is supported by Metrowerks Code Warrior debug tool After performing Hard Reset the debug host may initialize the memory controller via the
48. ata eli odd NR Ride 5 4 5 1 5 H rd Reset err 5 5 5 1 6 COP JTAG Port Hard Reset stand alone 5 5 5 1 7 Manual Hard Reset 255 cox ud eds RI II ER eR Cah dci PERROS 5 5 5 1 8 Manual Soft Resets ND eu e 5 5 2 Settings ee fpc urn unb ox dde 5 6 5 3 CIOCKING ERE 5 6 54 FPGA Board Control amp Status Registers 5 8 5 4 1 BGSRO Status Register 2o caw eae ae beeen ee 5 9 5 4 2 BCSR1 Stat s Register M d S s 5 9 543 BCSR2 sche E Et 5 10 5 4 4 BCSR3 Stat s Register E crn 5 10 5 4 5 BCSR4 Status R sister o2 a variant Ra Se kak 5 10 5 4 6 BGSRS Status Register uu oes y coxa Id uen d p meto E Cue 5 11 5 4 7 BCSR6 Status Revistet sc sese ue ctr ue RU e Rene tacens ds 5 11 5 4 8 BUCSR7 Status REGIE Rasy atu d ecg cea bp E he ea tia al EE d 5 12 5 4 9 Status Register Ves alma wis ee E 5 12 5 4 10 BESR9 Status Register cias oit Ede eate S e CAT 5 13 5 4 11 BGSR10 Status Registers
49. cheme 5 13 1 2 1 12 1 has six devices connected to it The first is the Boot EEPROM ST EEPROM M24256 B 256Kbit which provides configuration settings Its address is 0 50 when RESET SOURCE 0 2 001 or 010 The Serial Presence Detect SPD function utilized on a dedicated EEPROM in the SODIMM allows retrieval of the configuration data of the integrated DIMM to a program DDR controller e second device is the SPD EEPROM for SODIMM 1 DDR It is located at address 0x51 8360 MDS Processor Board Rev A Freescale Semiconductor 5 41 The third device is SPD EEPROM for SODIMM 2 DDR It is located at address 0x52 The fourth device is the Real Time Clock RTC implemented by Maxim DS1374 It is located at address 0x68 The DS1374 uses an external 32 768kHz crystal The DS1374 includes a 32 bit binary counter to continuously count time in seconds Separate output pins are provided for an interrupt and a square wave at one of four selectable frequencies 32 768kHz 8 192kHz 4 096kHz and 1Hz This output provides a tick signal for RTC input to the MPC8360 The RTC device is fully programmed via serial bus The fifth device is the BCSR which can be used as the I2C Master or Slave When the BCSR is a Master the COP interface controlled via the BCSR in addition to all I2C 1 bus devices When the BCSR is a Slave the COP interface or the MPC8360 can write
50. conductor 3 Connect processor board to PIB board as shown in Figure 2 5 Ensure a tight fit by pressing down on the processor board by hand only until the pins engage see Figure 2 5 5 Manually fasten the four screws as shown in Figure 2 6 Figure 2 5 Connect Processor board to PIB and press down with fingers 1 n E Figure 2 6 Fasten the four tightening screws 1 Although an MPC8349 Processor Board is shown this step is the same for the MPC8360E MPC8360 MDS Processor Board Rev A 1 Freescale Semiconductor 2 5 6 If you will be working with back plane and wish GETH signals to traverse either the back plane connection or the front plane optical connection connect the two GETH sockets on the MPC8360 MDS Processor Board with sockets on the PIB board as shown in Figure 2 7 and Figure 2 8 Note that if you do not do this you can still connect GETH cables directly to the Processor board s sockets if they are accessible in your laboratory configuration GETH Inter connecting Cables GETH Inter connecting Cable connected Figure 2 8 Connect GETH interconnecting cables to sockets on PIB 7 Connect the power supply to the voltage input as shown in Figure 2 9 MPC8360 MDS Processor Board Rev A 1 2 6 Freescale Semiconductor Figure 2 9 Connecting Power input to the PIB MPC8360 MDS Processor Board Rev A 1 Freescale Semiconductor 2 7 8 If you wish to work with a m
51. connector so this allows additional access to bus addressable peripherals The DDR64 2xDDR32 SDRAM and FLASH memory respond to all types of memory access program data and Direct Memory Access DMA The following table Table 3 1 presents the Memory Map of the MPC8360 MDS Processor Board It includes an address range for each target that utilizes memory the target itself on the board the specific device that is used to implement the target s function the amount of memory allotted to the target volume in bytes and its port size in bits Note the information on the DDR SDRAM There are two main options using one 64 bit device or one or two 32 bit devices The one 64 bit device can be used to implement a memory capacity of 256MB or 1GB Alternatively a memory capacity of 256MB 128 128 can be implemented using two 32 bit devices Table 3 1 MPC8360 MDS Processor Board Memory Map Port No Address Range Target Device Name Volume Size in in Bytes DDR SDRAM 0 00000000 OFFFFFFF Main SODIMM HYMD232M646D6 w o ECC 256MB 64 8 for 256MB volume MEMC1CSO0 MEMC1CS1 for 256MB space ECC 64 bit 00000000 3FFFFFFF MT9VDDT3272PHG with 1GB for 1GB volume ECC for 1GB space 1 00000000 O7FFFFFF Main SODIMM SDN01632A1B71MT L 60 128MB 32 8 for 128MB volume 1 50 MEMC1CS1 w o ECC ECC 32 bit 08000000 OFFFFFFF for additional 128MB volume Second SODIMM 2 50
52. crews removed Figure 7 14 Remove heat sink MPC8360 MDS Processor Board Rev A 1 Freescale Semiconductor 7 5 Figure 7 17 Chip alignment Incorrect 74 mF grt 1 Alignment Indicator 4 aligned correctly x Figure 7 16 Chip alignment Correct MPC8360 MDS Processor Board Rev A 1 Freescale Semiconductor MPC8360 MDS Processor Board Rev 1 Freescale Semiconductor How to Reach Us Home Page www freescale com E mail support freescale com USA Europe or Locations Not Listed Freescale Semiconductor Technical Information Center CH370 1300 N Alma School Road Chandler Arizona 85224 1 800 521 6274 or 1 480 768 2130 support freescale com Europe Middle East and Africa Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen Germany 44 1296 380 456 English 46 8 52200080 English 49 89 92103 559 German 33 1 69 35 48 48 French support freescale com Japan Freescale Semiconductor Japan Ltd Headquarters ARCO Tower 15F 1 8 1 Shimo Meguro Meguro ku Tokyo 153 0064 Japan 0120 191014 or 81 3 5437 9125 support japan freescale com Asia Pacific Freescale Semiconductor Hong Kong Ltd Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 800 2666 8080 support asia freescale com For Literature Requests Only Freescale Semiconductor Literature Distributi
53. ded for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners Freescale Semiconductor Inc 2005 All rights reserved
54. ductor 5 3 BCSR performs initialization procedures drives the BCSR Done signal to logical 1 in order to keep PORESET low After finishing initialization the BCSR Done signal is logical 0 The BCSR drives a RESET signal to the GETH PHYs When the MPC8360PB is in Agent Mode PORESET can be driven by PCI RST signal The PCI edge connector PIN RST is connected to the PORESET in order to reset the MPC8360PB There are several reset sources on the MPC8360E Processor Board In Agent mode Power On Reset Manual Hard Reset e Manual Soft Reset e MPC8360 device HRESET amp SRESET can be driven through JTAG COP connector by BCSR by RTC when it reaches its count value or by push buttons Reset Controller gt Power Good FLASH aes W Write Protect i SEES Low Power Detect lt 4 5V PIB Riser Con Reset to BCSR A 8360 PORESET JTAG COP CONN 5 PCI Reset e gt SRESET SRESET 28 Option BCSR Done BCSR Hreset p Sreset RTC 1 2 Figure 5 3 Reset Block Scheme 5 1 4 Power On Reset The power on reset to the MPC8360E Processor Board initializes the processor s state after power up A dedicated logic unit asserts PORESET input for a period long enough to c
55. e 5 1 below shows a schematic diagram of the reset circuit including the various signals and their sources Table 5 1 Reset Configuration Words Source Value Reset Configuration Signal Name Binary Meaning SW3 1 3 RESET 0 2 000 Reset configuration word is loaded from a local bus EEPROM or the BCSR and DIP switches depending on the value of SW9 3 001 Reset configuration word is loaded from an 2 EEPROM PCI_CLK PCI_SYNC_IN is in the range of 25 44 Mhz 010 Reset configuration word is loaded from an 2 EEPROM PCI_CLK PCI_SYNC_IN is in the range of 44 66 666 Mhz 011 Hard coded option 0 Reset configuration word is not loaded 100 Hard coded option 1 Reset configuration word is not loaded 101 Hard coded option 2 Reset configuration word is not loaded 110 Hard coded option 3 Reset configuration word is not loaded 111 Hard coded option 4 Reset configuration word is not loaded MPC8360 MDS Processor Board Rev A Freescale Semiconductor 5 1 S EN FLASH MPC8360 5 CS 0 FCFG Flas BCSR 12A lt 5 Flash BCSR Local Bus LD 0 7 JTAG COP D l CFG RESET SOURCE amp CLKIN DIV CFG Signals BCSR COP p COP Signals 2 MEN PORESET NN W PORESET CFG_CLKIN DI HRESET CFG PCI gt
56. e 5 11 below the TBI uses the same signals as the GMII interface MPC8360 G ETH CRS TBI Mode PHY TBI_TXCLK gt GTX TX_CLK TADE gt TX_EN TXD 7 0 gt TXD 7 0 aoa RX_CLK BRADS RX_ER RADE RX_DV RXD 7 0 RXD 7 0 2 Figure 5 11 TBI Signal Diagram 5 9 3 Reduced Pin Count RGMII This option should be used if 10 or 100Base T speed is desired This interface reduces the number of pins between the PHY and the MPC836x device to 12 pins The RGMII to copper interface is selected by software through the MDC and MDIO pins or by BCSR8 0 5 See Section 5 4 9 on page 5 12 for more details In this mode of operation the data is transmitted and received on both clock edges The signals used in this mode are shown in Table 5 25 Table 5 25 RGMII Signals RGMII Signal Name PHY Signal Name GTX_CLK GTX_CLK TX_EN TX_EN MPC8360 MDS Processor Board Rev A Freescale Semiconductor 5 31 Table 5 25 RGMII Signals continued RGMII Signal Name PHY Signal Name TXD 3 0 TXD 3 0 RX CLK RX CLK RX CTL RX DV RXD 3 0 RXD 3 0 Figure 5 12 below shows the signal mapping between the MPC8360 device and PHY in RGMII mode MPC836x RGMII mode PHY a a gt GTX_CLK DEGIL gt TXD 3 0 gt TXD 3 0 RX_CLK RX_CTL
57. e back plane if used Optical signals via 2x SFP connectors for GETH on the front plane side of the PIB are also provided The MPC8360 MDS Processor Board can be connected to a PC in this configuration via a parallel port connector without needing an external command converter 1 2 3 Agent Mode in PC or PIB Using its PCI edge connector the MPC8360 MDS Processor Board can be inserted into a PC or onto the PIB Power and debugging are supplied from the PC no command converter necessary Other external connections are the same as in the Stand Alone Mode In this mode the MPC8360 MDS Processor Board acts as an Agent 1 3 MPC8360 MDS Processor Board 1 3 1 Features e Supports MPC8360E running up to 533MHz at 1 2V Core voltage e DDR 64 bit on SODIMM at a rate up to 333MHz or 2 x DDR 32bit units on two SODIMM each at a rate up to 333MHz PCI edge connector interfaces with 32bit PCI bus used when inserted in a PC or as an agent on the PIB Two 10 100 1000Mb sec Ethernet Phys on GETH ports USB 1 1 Transceiver Dual RS232 transceiver on one DUART port Local Bus interface 133MHz SDRAM memory implemented using three units 64Mbyte size with parity One 16Mbyte expandable Flash with 16bit port size in socket Address Latch and Buffers to support slow devices on the PIB Board Mictor Logic Analyzer Connectors on mux bus for evaluation only Three Hi speed Riser Connectors to enable connection
58. e of Micron s MT48LC16M16A2TG 6A units They organized as 4 Banks x 4M x 16bits where all input and output levels are compatible with LVTTL One is configured as a 64Mbyte bank The other two devices are 32Mbyte and are used in order to achieve a capacity of 64Mbyte plus 1 device for four bits parity There is a total of 3 MT48LC16M16A2TG 6 devices The device has 13 Rows 9 Column and 2 bits for bank select Table 5 23 below describes the local bus address interface to the SDRAM The first row in the table LB ADD shows the local bus address from A29 to A6 the logical address This row also shows that the columns start at A21 and continue to A29 The bank select uses logical address A19 and A20 and the row address uses local bus A6 to A18 The next row in the table ROW FOLD shows how the row address folds over the column address for example we can see that the bank select internal A19 and A20 will go out on A15 and A16 The next row in the table SDRAM ADD shows the address pins from the SDRAM point of view We can see that A10 operates with the command and comes with the rows so that command A10 comes from A8 LSDA10 is connected to SDRAM A10 The bank selects signals are the MSB address bits in the SDRAM and are latched with the row addresses that is they will placed after the rows signals on A15 and A16 The signals connected to the SDRAM is LAD 15 29 while SDRAM A10 is connected to LSDA10 During the first phase of memo
59. ector The External 5V Power Supply is a standard power supply Its parameters are Vin 100V 240V AC Nin freq 50Hz 60Hz lin 2A e OUTPUT 5V DC out 5 5 15 2 MPC8360 MDS Processor Board Power Supply Structure The MPC8360 MDS Processor Board supplies power via the following e Power Module DC DC converter DNS04S3R3RO6PC made by Delta to produce MPC836X 1 2V voltage Core 6A e Power Module DC DC converter DNS04S3R3RO6PC made by Delta to produce 3 3V 6A LDO regulators LT1764EQ 2 5V FAN1655 Fairchild Co Produce DDR VDD DDR bus required termination and reference voltages 1 25V 2 Vggp 1 25V e Set linear regulator and LDO regulator MIC49150 LT1764 2 5 from Linear Tech Provides all necessary TSEC PHY s VDDO VDDOH AVDD and DVDDL core voltage 2 5V DC 1V DC 1 5A Provides necessary visual indication and power sequence functions 5 15 3 Power Supply Operation When a 5V Power source is connected to the board the MPC8360E 1 2V core voltage is generated first The MPC8360E OVDD should not reach 1 V before MPC8360E VDD reaches 1 V All the above voltages are derived from the 3 3V power supply using LDO regulators and Linear regulators After 3 3V and 1 2V have been produced the green LED Power Good LD10 indication is illuminated When the 5V PIB Power source is selected a 3V PIB Indication is inserted into the FPGA The MPC8360E LVDD voltage group is used fo
60. ectors J1 J2 RJ45 8 pin Gigabit Ethernet Connectors MPC8360 MDS Processor Board Rev A 1 Freescale Semiconductor 1 3 9 16 header for FPGA programming E 1 P10 Voltage Input ape P8 JTAG COP P7 SMB RF Connector P5 P6 MICTOR x3 Logic Analyzer P11 P12 P13 300 pin FCI Expansion Connectors on underside P3 PCI 32Bit Edge Connector J1 J2 RJ45 Gigabit Ethernet Front Panel E mm m up P2 RJ45 DUART signals P1 MiniAB USB Figure 1 1 MPC8360 MDS Processor Board External Connections MPC8360 MDS Processor Board Rev A 1 1 4 Freescale Semiconductor 1 3 3 Block Diagram The block diagram of the MPC8360 MDS Processor Board is shown below in Figure 1 2 SODIMM DDR 32bit SODIMM DDR 64 32bit SPI 128MByte 333Mhz 256 128MByte 333Mhz FLASH SDRAM FLASH eo j 8 Bo OEP de 32bit 64MB SMbyte 9 d 2 gt as 1 5 xa Clocks A A AA gt E 5 9 5 06 a es a 9 gt lt lt le 10 100 1000 CLKIN y gt 9 z Ethernet i SYNC IN SYNC OUT 5 U 5 7 m GMII RGMII RGMII Y Es 2 5 8 a e Pa ROMI m gt Local Bus 2 PCI Mapped Parallel Agent only o GMII RGMII GMII 5 y
61. ed into the P10 Power Connector on the board s front side for the Stand Alone Mode The MPC8360 MDS Processor Board is powered by the 5V external power supply when the SW5 Power Switch is turned to the ON up position When the MPC8360 MDS Processor Board is plugged into an PC via the PCI edge connector it is powered from the edge connector s 5V power rail Agent Mode In the PIB Combined Mode 5V power is supplied from the PIB s power supply via risers connectors Note that if working in either of these two modes the position of SW1 is ignored MPC8360 MDS Processor Board Rev A 1 Freescale Semiconductor 4 5 4 4 Other Controls and Indicators 4 4 1 Push Buttons Table 4 2 below describes the functionality of the board s push buttons See Figure 4 3 for the locations of these push buttons Table 4 2 The MPC8360 MDS Processor Board Push Buttons Pressing button SW1 results in Power On Reset for all components on the MPC8360 MDS SW1 Processor Board Power on Reset Use this reset button when the MPC8360 MDS PRESET Processor Board is installed in a PC Rotary Switch SW2 allows the user to change SW2 the program flow according to eight available Software Option cases SW OPT Not available when installed in a PC Pressing button SW6 results in a Hard Reset for SW6 the MPC8360 Hard Reset HRESET Not available when installed in a PC Pressing button SW7 results in a Soft Reset for SW7 the MPC8360 Des
62. een ATM function of USB function ATM USB For USB connect 1 2 For ATM connect 3 2 JP3 TDMATXCLK M2GTX125 For GMII2 connect 1 2 M2GTX125 for GTETH2 For TDMA when using PIB connect 3 2 JP5 LVDD2 3 3V 2 5V 8360 LVDD2 Power For LVDD2 3 3V connect 2 3 For LVDD2 2 5V connect 1 2 JP6 Clock source PIB onboard External JP6 Clock Connected 1 2 to configure for an external clock JP7 JP7 reset not connected Reset JP8 JP9 JP8 JP9 not in use MPC8360 MDS Processor Board Rev A 1 Freescale Semiconductor 43 LEDs The MPC8360 MDS Processor Board has the following LEDs locations shown in Figure 4 2 above LD1 LD2 Signaling LEDs LED s LD1 green and LD2 red are program controlled They are used for extra visibility on the running utility They are lit up by setting bits BCSRO 5 6 respectively LD3 USB Power When lit green the USB Vbus is powered LD4 LD5 GETH Enable The green LED LD4 5 indicates enable for GETH Transceivers U6 U5 respectively LD6 DUART Enable A green LED LD6 indicates enable for the RS232 Dual Transceiver LD7 Power GOOD A green LED LD7 indicates that the MPC8360 MDS Processor Board power is operating normally 108 Not in Use LD9 BOOT Indicator The LD9 indicates MPC8360 boot processing LD10 5V Power Indicator The green LED LD10 indicates a 5V power level on the MPC8360 MDS Processor Board A 5V power supply is plugg
63. effective highly integrated communications processor that addresses the needs of the networking wireless infrastructure and telecommunications markets Target applications include next generation DSLAMs network interface cards for 3G base stations Node Bs routers media gateways and high end IADs The 8360E extends current PowerQUICC II offerings adding higher CPU performance additional functionality faster interfaces and interworking between ATM and Ethernet based protocols while addressing the requirements related to time to market price power and package size The MPC8360E can be used for the control plane along with data plane functionality The MPC8360 MDS Processor Board includes various peripherals such as data input output devices GETH USB DUART memories DDR SDRAM optional Serial EEPROM FLASH and BCSR registers and control switches and LED indicators Using its on board resources and debugging devices a developer is able to upload code run the code set breakpoints display memory amp registers and connect his own proprietary hardware to be incorporated into a target system that uses the MPC8360E as a processor The software application developed for the MPC8360E can be run ina bare bones operation with only the MPC8360E processor or with various input or output data streams such as from the GETH connection PCI or the USB connections Results can be analyzed using the Code Warrior debugger in addition to usi
64. eral instances that require repeat actions such as writing FF to LSDMR several times These must be carried out as described Table 3 2 MPC8360 MDS Processor Board Configuration Registers Register Name 1 joda Description IMMRBAR Oxff400000 0 0000000 Local Access Window FLASH LBLAWBARO 0 0000020 0 000000 0 0000024 0 80000017 16 Local Access Window BCSR LBLAWBAR1 0xE0000028 0 8000000 LBLAWBAR1 0xE000002C Ox8000000E 32K MPC8360 MDS Processor Board Rev A 1 3 2 Freescale Semiconductor Table 3 2 MPC8360 MDS Processor Board Configuration Registers continued Register Name Posen pesa Description Local Access Window SDRA LBLAWBAR2 0xE0000030 OxF0000000 LBLAWBAR2 0 0000034 0x80000019 64M LBLAWBAR2 0 0000034 0x8000001A 128M Local Access Window PIB LBLAWBARS 0xE0000038 OxF8008000 LBLAWBARS 0 000003 0x8000000F 64K PIB CS4 OR4 0 0005024 OxFFFFE9F7 32K BR4 0xE0005020 oxF8008801 Port size 8bit MSEL GPCM PIB CS5 ORS OxE000502C OxFFFFE9F7 32K BRS OxE0005028 OxF8010801 Port size 8bit MSEL GPCM Local Access Window PCI PCILAWBARO 0 0000060 0x80000000 PCILAWBARO 0 0000064 0x8000001C 512M QE Secondary Bus Access Windows LBMCSAR 0xE0001800 0x000F0000 LBMCEAR 0 0001840 LBMCAR 0 0001880 0 00000001 LBIU
65. erved 8360 MDS Processor Board Rev A Freescale Semiconductor 5 11 5 4 8 BCSR7 Status Register On the board BCSR7 acts as a control register BCSR7 which may be read or written at any time receives its defaults immediately after PORESET signals BCSR7 fields are described below in Table 5 7 Table 5 7 BCSR7 Register Description DEF on SDDRIOE Lo DRM DDR IO Enable This bit reflects SDDRIOE signals RW logic level during Reset Configuration sequence The bit is set by default to low which means the secondary DDR is disabled May be rewritten via LBIU RW 28 4 TLE True Little Endian If high true little endian is used If low big endian is used 29 5 LALE LATE Timing If high the LALE is negated 1 2 Ibiu controller clk RW earlier than normal If low normal LALE timing is used 5 4 9 BCSR8 Status Register On the board BCSRS acts as a control register BCSR8 which may be read or written at any time receives its defaults immediately after PORESET BCSRS fields are described below in Table 5 8 Table 5 8 5 8 Register Description DEF on TSEC1M G ETH port 1 Config Mode These two bits select the communication protocol used by the G ETH1 controller For details on possible values and their meanings See Table 5 9 May be rewritten any time via LBIU Note If mounted on PIB should be only Reduced mode 3 TSEC2M G ETH port 2 Config Mode These two bits select the communication protocol used by
66. gister SW9 4 8 Sampled at HRESET On the board BCSR4 acts as a control register BCSR4 which may be read or written at any time receives its defaults immediately after PORESET signal BCSR4 fields are described below in Table 5 5 Table 5 5 BCSR4 Register Description PCIHOST PCI Host Mode If low the PCI processor is set to agent mode This occurs when the Processor Board is not connected to the PIB riser connectors stand alone inserted in PC or inserted in PMC slot in PIB When the Processor Board is combined with the PIB connected to riser connections this bit is high the PCI processor is in host mode If P3 Edge Connector connected to PC or PIB 0 If P3 not connected 1 2 2 PCIARB PCI Internal Arbiter Mode PCI Arbiter Set low for PCI add in card configuration in PC or on PMC slot in PIB to provide external arbiter When the Processor Board is combined with the PIB the bit is high to configure the PCI port with an internal arbiter 3 3 PCICKDRV PCI Clock Output Drive The bit reflects the PCICKDRV signal logic level during Reset Configuration sequence The bit is set by appropriate DIP switches May be rewritten via LBIU 8360 MDS Processor Board Rev A If P3 Edge Connector connected to PC or PIB 0 If P3 not connected 1 SW9 2 5 10 Freescale Semiconductor Table 5 5 BCSR4 Register Description continued 4 4 COREDIS Core Disable Mode When high the e300 core is prevented f
67. he PIB and allocates resources for them A list of signals between the PIB and the Processor Board is supplied in Section 6 4 below It is important to note that an external debugger must be connected to the JTAG COP connector on the board on which the processor to be debugged is found MPC8360 MDS Processor Board Rev A 1 6 2 Freescale Semiconductor 6 3 8360 MDS Processor Board as Agent If the MPC8360 MDS Processor Board is inserted in an adaptor on the PIB the edge connector P3 disconnects the clock generated on the agent Processor Board Its clock is therefore supplied from the host Processor Board via the adaptor connector on the PIB A list of signals between the PIB and the Processor Board is supplied in Section 6 4 below It is important to note that an external debugger must be connected to the JTAG COP connector on the board on which the processor to be debugged is found 6 4 MPC8360 MDS Processor Board PIB Signals The tables below show the correspondence between signals on the MPC8360 and those on the PIB They are divided by subject TDM signals UPC Ethernet USB etc and there may be some repeat entries The PMC XMC pin number is the number of the pin on the PMC slot of the PIB The Riser Connector Pin is the number of the pin on the MPC8360 MDS Processor Board that connects to the PIB The MPC8360 Pin name is the name of the pin on the MPC8360 device For a complete list of these pins see
68. ications The MPC8360 MDS Processor Board specifications are given in Table 1 1 Table 1 1 MPC8360 MDS Processor Board specifications CHARACTERISTICS SPECIFICATIONS Power requirements Stand Alone Mode 5V 3A external DC power supply PIB Combined Mode Power supplied by PIB Working in PC Power supplied by PC MPC8360 MDS Processor Board Rev A 1 Freescale Semiconductor Table 1 1 MPC8360 MDS Processor Board specifications CHARACTERISTICS SPECIFICATIONS MPC8360E processor Internal clock runs at 533MHz 1 2V note that the board supports any working frequency that the MPC860 supports To change the working frequency see Section 5 3 Memory Two DDR busses 2 x 128MB space 32bit wide in two SODIMM 200 s Data rate 333MHz Local Bus SDRAM Optional Buffered Memory Flash on socket BCSR on FPGA 64MB space 32bit wide 4bit parity implemented in three SDRAM parts 133MHz clock 16MB space 16bits wide 16 registers 8bits wide Expansion Four banks with 16bit Address bus 16bit Data bus connected to riser connectors Operating temperature 0 C 70 C Storage temperature 25 C to 85 C Relative humidity 5 to 90 non condensing Dimensions according to PCI 64 bit Add in card form factor Length Width Height 285 mm 106 mm 16 mm MPC8360 MDS Processor Board Rev A 1 Freescale Semiconductor Chapter 2
69. ich is enabled only when jumper JP6 2 3 is closed Optional 5 5 6 P8 Debug COP Connector P8 is Freescale standard JTAG COP connector for the PowerPC It is a 16 pin 90 two row header connector with key During debug all processors connected by the JTAG chain may be accessed through connector P8 The pinout of P8 is shown in Table 5 19 P8 JTAG COP Connector below Table 5 19 P8 JTAG COP Connector Pin No Signal Name Description TDOc Transmit Data Output This is the MPC8360 JTAG serial data output driven by Falling edge of TCK 2 10 12 16 GND Main GND plane TDIc Transmit Data In This is the JTAG serial data input of the MSC8101 sampled on the rising edge of TCK nTRSTc Test port Reset When this signal is active Low it resets the JTAG logic This line is provides a pull down on the ADS with a 4 7KQ resistor which provides a continuous reset of the JTAG logic when connector is unplugged N C Not Connected SENSE Connect to 3 3V power supply bus via protection resistor May be used for Command Convertor power Test port Clock This clock shifts out data to from the JTAG logic Data is driven on the falling edge of TCK and is sampled both internally and externally on its rising edge Check Stop Input Machine Check Stop Input TMSc Test Mode Select This input selects test mode and is sampled on the rising edge of T
70. is shown in Table 5 20 P9 FPGA Programming ISP Connector below Table 5 20 P9 FPGA Programming ISP Connector Pin No Signal Name Attr Description 1 ISP TDO Transmit Data Output 2 10 12 GND Main GND plane 16 3 ISP_TDI Transmit Data In 4 5 8 11 1 N C Not Connected 3 14 15 6 SENSE P Connect to 3 3V power supply bus via protection resistor Use for programmer powering 7 ISP_TCK Test port Clock 9 ISP_TMS Test Mode Select 5 5 8 P10 Power Connector P10 15 2mm Power Jack RAPC722 which provides a connection to an external power supply 5DC 2 5A MPC8360 MDS Processor Board Rev A 5 22 Freescale Semiconductor 5 5 9 J1 J2 GETH Port Connector The GETH connectors on the MPC8360 J1 J2 are both Twisted Pair 1000 Base T compatible connectors They are implemented with a 90 8 pin RJ45 Combo connector with internal magnetics and two LEDs indicating communication speed signals of which are described in Table 5 21 1 J2 GETH Port Interconnect Signals below These connections are on the front panel For location see Figure 1 1 Green LED indicates 1000Mbit Data rate Yellow LED is lit when 100Mbit Data rate mode Table 5 21 J1 J2 GETH Port Interconnect Signals Wire Color 10Base T 100Base T Signal 1000 Base T Signal Twisted Pair Transmit Data positive BI DA output White Orange Twisted Pair Transmit Data negative BI DA output
71. l arbitration BCSR4 2 0 and the PCI Clock Output Drive should be set to low BCSR4 3 0 8360 MDS Processor Board Rev A 5 24 Freescale Semiconductor Also note that in Agent Mode the CLKIN is neutralized and the SYNCIN pin receives a clock from an external to the board clock oscillator via the P3 edge connector The MPC8360 MDS Processor Board is compatible with PCI specification Revision 2 2 The PCI Interface is 3 3V 5V 32 bit It uses a 32 bit multiplexed address data bus that can run from 25MHz up to 66MHz 5 7 DDR The DDR SDRAM Interface supports a 256MByte 333MHz bus in both 64 bit or 2x 32 bit widths e 64 bit The MPC8360 MDS Processor Board supports a 64 bit data width by using a DDR SODIMM e 2x 32 bit Implementation of 2 X 32 bit DDR I F is shown in Figure 5 8 To implement one 64 bit bus or 2 x 32 bit buses two SODIMM sockets are mounted on the board M1 M2 one of which M1 has 64 bit capability that can be configured to work at either 32 bits LOW 1 or at 64 bits For 32 bit LOW the SDN01632A1B71MT L 60 from SWISSBIT is used in mounted on U34 see Figure 7 6 Note that it is the only SODIMM for which 32 bit LOW only is populated For the 2 x 32 bit mode SDN01632A1B71MT L 60 from Swissbit is used in mounted on U34 see Figure 7 6 and a standard 64 bit SODIMM module is configured for 32 bit HIGH and used in M2 mounted on U69 see Figure 7 7 Fo
72. lected by setting the 88 1111 HWCFG MODE 3 0 to 0b1111 It can also be controlled by BCSRS8 0 3 amp BCSR9 0 2 If using 1000Base T speed 125MHz input to the MPC8360 is taken from the PHY Each one ofthe PHYs is driving its own 125MHz clock to the appropriate UCC The MPC8360 GMII interface transmits a 125MHz clock to the PHY GTX CLK pin Note The COL signal is not used in this board although it appears in the schematics pa 125Mhz Clock 88E1141 GTX CLK erect TX_CLK MER gd nce Oro TX_EN ESTA gt TXD 7 0 lt RX_CLK RX_ER RX ER RX RX DV Em RXD 7 0 lt CRS Figure 5 10 GMII Interconnections 5 9 2 Ten Bit Interface TBI The TBI interface pin mapping is shown in Table 5 24 The TBI interface supports 1000Base T mode of operation only The TBI to copper interface is selected by software through the MDC and MDIO pins or by BCSR8 0 5 For more details see Section 5 4 9 on page 5 12 Table 5 24 TBI Signals TBI Signal Names TBI Signal Name PHY Signal Name TBI TXCLK GTX CLK RXCLK1 TX CLK TXD9 TX ER TXD8 TX EN 8360 MDS Processor Board Rev A 5 30 Freescale Semiconductor Table 5 24 TBI Signals continued TBI Signal Names TBI Signal Name PHY Signal Name TXD 7 0 TXD 7 0 RX_CLKO RX_CLK RXD9 RX_ER RXD8 RX DV RXD 7 0 RXD 7 0 external PU CRS As shown in Figur
73. low in Table 5 3 Table 5 3 BCSR1 Register Description DEF on Reserved Reserved 9 15 1 7 COREPLL 2222 2 24 4 PLL Multiplication Factor The seven bits reflect COREPLL 0 6 signals logic level during Hard Reset Configuration sequence The bits Sampled at are set by appropriate DIP switch default May be rewritten via LBIU HRESET MPC8360 MDS Processor Board Rev A Freescale Semiconductor 5 9 5 4 3 BCSR2 Status Register This register is reserved 5 4 4 BCSR3 Status Register On the board BCSR3 acts as a control register BCSR3 which may be read or written at any time receives its defaults immediately after the PORESET signal BCSR3 fields are described below in Table 5 4 Table 5 4 BCSR3 Register Description DEF on CE PLL VCO The two bits reflect CEVCOD 0 1 signals logic SW11 3 4 24 25 CEVCODYJI O0 1 level during Hard Reset Configuration sequence The bits Sampled at set low by default May be rewritten via LBIU HRESET CEPDF CE PLL Division Factor This bits reflect CEPDF signal logic SWA 8 level during Reset Configuration sequence The bits are set by Sampled at appropriate DIP switch May be rewritten via LBIU HRESET 27 31 3 7 PLL Multiplication Factor The five bits reflect signals logic level during Reset Configuration sequence The bits are set by appropriate DIP switch May be rewritten via LBIU 5 4 5 BCSRA Status Re
74. ls BCSR12 fields are described below in Table 5 13 Table 5 13 BCSR12 Register Description DEF on 0 3 REV BCSR Revision Four bits revision coding Programmed value SUBREV BCSR SUB Revision Four bits revision coding value MPC8360 MDS Processor Board Rev A 5 16 Freescale Semiconductor 5 414 BCSR13 Status Register On the board BCSR13 acts as a control register BCSR13 which may be read or written at any time receives its defaults upon Power on signals BCSR13 fields are described below in Table 5 14 Table 5 14 BCSR13 Register Description DEF on g PIBDRIVEPC10 PIBDRIVEPC16 ES USBEN USBSPEED p USBMODE in USBVCC PIB Drive PC10 If high this bit instructs the PIB to drive the signal PC10 If low this signal is not PIB Drive PC16 If high this bit instructs the PIB to drive the signal PC16 If low this signal is not driven FLASH Configuration When high and 1 configuration source set as Local Bus CFG_RST_SOURCE the RCW is loaded from FLASH if low from BCSR Config Bit Lock When low BCSR contents don t 1 update during PORESET When high BCSR contents do update during PORESET Low provides the normal mode Use for debug purpose USB1 1 Enable When low the USB is enabled When high the USB is disabled USB1 1 SPEED When this bit is high USB full 1 RW Speed is selected When this bit is low USB low speed is selected USB Mode Sets the USB as a host
75. lso possible to configure to other PHY configuration modes via the PHY internal registers Note also the following Some of the PHY configuration parameters require a Soft Reset to activate the new configuration value See PHY documentation from Marvel for a list of such parameters The PHY reset input is driven by either an assertion of HRST Hard Reset or by writing zero to BCSR9 2 The registers BCSR9 0 1 are the enable bits for each of the PHYs Note that whenever BCSR9 2 is changed from low to high the value of BCSR8 0 5 is driven to the PHY to configure the hardware setting The PHYs reset any time an HRST Hard Reset sequence is taken The PHY may execute a Soft Reset by asserting bit 15 MSB of the 88E1111 control register 0 via the MDC amp MDIO signals When the PIB is used only the reduced modes RGMII and RTBI are recommended Section 5 9 1 to Section 5 9 6 describe in more detail each PHY mode MPC8360 MDS Processor Board Rev A Freescale Semiconductor 5 29 5 9 1 GMII Interface This interface is the default interface upon Power On This interface is recommended on this board for 1000Base T speed Note for 100Base T and 10Base T modes RGMII interface should be selected see Section 5 9 3 on page 5 31 Figure 5 10 below indicates the signal mapping of the 88E1111 device to GMII interface The interface supports GMII to copper or GMII to fiber connections in 1000Base T speed The GMII interface is se
76. nal csb_clk ERN Default setting 00001000 for fcore 533MHz 4S CABOBEBUDGT 4 en Set 00000110 for fcore 500MHz 2 COREPLL1 2 3 2 3 4 4 COREPLL4 5 6 COREPLL5 6 7 COREPLL6 7 8 NC 8 SW11 SW11 1 SW11 2 SVCODE sets SVCODE to 0 Default setting 00 1 0 SW11 3 SW11 4 CEVCODE 1 SVCODEO 1 ON Set CECVOD to 0 2 SVCODE1 2 Default setting 00 8 CECVODO 3 SW11 5 COREDIS 4 CECVODI 4 1 e300 core is prevented from fetching the boot code until 5 COREDIS 5 configuration by an external master is complete 6 6 0 e300 core runs normally 7 7 Default setting 0 8 8 SW5 Power Switch SW5 power switch ON power from an external 5V power supply via the P10 power jack combined mode powered from 5V on PIB power supply through riser connectors regardless of SW5 position board plugged as a PCI add in card PC internal power supply will provide 5V via PCI edge connector PCB MPC8360 MDS Processor Board Rev A 1 Freescale Semiconductor 4 2 Figure 4 2 below shows the locations of the jumpers and LEDs Jumpers LD7 8 9 JP6 JP1 1 JP9 JP1 Figure 4 2 MPC8360 MDS Processor Board Jumpers and LEDs Locations Table 4 1 Jumper Settings 8360 MDS Processor Board jumpers settings are described in Table 4 1 below JP1 GETH Voltage 3 3V 2 5V For 2 5V connect 1 2 For 3V JP1 connect 3 2 JP1 1 JP1 1 Select betw
77. ng other methods for directly analyzing the input or output data stream The BSP is built using the Linux OS This board can also be used as a demonstration tool for the developer For instance the developer s application software may be programmed into its Flash memory and run in exhibitions 1 2 Working Configurations 1 2 1 Stand Alone Mode Host The MPC8360 MDS Processor Board can be run in a stand alone mode like other application development systems with direct connections to debuggers via a JTAG COP connector and JTAG Parallel Port command converter power supply and the GETH MiniAB USB and Dual RS 232 DUART connections In this mode the MPC8360 MDS Processor Board acts as a Host MPC8360 MDS Processor Board Rev A 1 Freescale Semiconductor 1 1 1 2 2 PIB Combined Mode as Host The MPC8360 MDS Processor Board can be connected to the PIB the Platform I O Board which allows it to be used in a back plane and provides room and connections for additional modules There are many modules some of which are TDM or ATM modules There can also be additional Processor Boards from the MPC83xx family acting as Agents This capability allows the MPC8360E processor on the MPC8360 MDS Processor Board to act as a Host for Agent processors in the MPC83xx family Power for the MPC8360 MDS Processor Board in this case is provided via the PIB The PIB also provides an additional 2x4 twisted pair for GETH signals to be connected via th
78. nput signals those that are on the left of the block except CLKIN DIV and CLKIN are from the configuration word and should be set according to information in the 8360 User s Manual A diagram showing certain electrical aspects of the clocking connections is shown below in Figure 5 4 There are two modes of clock operations e Agent Host In Agent mode the MPC8360 MDS Processor Board is inserted in a PC or in an adaptor on the PIB Its edge connector P3 which is inserted in the PC s or PIB s PCI slot causes an open circuit between PCI SYNC OUT and PCI SYNC IN The PC or the host processor on the PIB therefore supplies the input clock signal via the PCI SYNC IN pin In this case the CLKIN pin is connected to GND In Host mode the edge connector P3 is not connected As a result CLKIN is not connected to ground and supplies a clock signal to PCI SYNC OUT via a 5 loop trace which covers the PCI clock routing on the PIB which in turn is connected to PCI SYNC IN thus supplying a clock to the MPC8360E device 8360 MDS Processor Board Rev A 5 6 Freescale Semiconductor MPC8360 SyncIN DDR CLK d PCI Agent CLK from edge connector PLL 35 DDRSyncIN 5 loop al DDRSyncOUT 4 SyncOUT DODGERS RR Lee E _ Yo 66Mhz CLK CLK Figure 5 4 Clocks Showing External Connection Scheme and 5 Loop Figure 5 5 Clocks I
79. nternal Block Diagram MPC8360 MDS Processor Board Rev A Freescale Semiconductor 5 7 Working with ATM signals It is important to note that if working with ATM UPC2 signals the MPC8360E must receive a 66MHz signal on the PCI SYNC IN pin Since this is the frequency of the CLKIN signal this is not a problem in Host mode However in Agent mode when the clock signal comes from an outside source and the CLKIN is connected to GND the user must ensure that the ATM nevertheless uses this 66MHz signal Do this as follows First write to the following before you set the PCIMODE bit BCSR10 4 bit to 1 OX EFE35010 to offset XX00148C and then OX FFE3A030 to offset 0x XX00148C 54 FPGA Board Control amp Status Registers The FPGA contains the BCSR which is an 8 bit wide read write register file that controls or monitors most of the MPC8360 MDS Processor Board hardware options The BCSR s register may be accessed from the Local Bus The BCSR includes up to 16 registers some of which are optional BCSR registers are duplicated numerous times within a CS1 region This is due to the CS region s 32KB minimum block size and the fact that only address lines A 27 31 are decoded for register selection by the BCSR BCSR is implemented on a Xilinx FPGA device that provides register and logic functions over some MPC8360 MDS Processor Board signals The BCSR controls or monitors the following function
80. nts as an input output signal OD Open Drain driver Hi Z Three state 8360 MDS Processor Board Rev A Freescale Semiconductor 5 39 BCSR External Command Converter 836X Local Bus Mapped Agent only PCI JTAG Local LA 27 31 COP JTAG Bus LAD 0 7 1402 TIRGI PCI JTAG MUX CCR Control nCOP_EN bit Figure 5 17 JTAG Block diagram 5 12 UART Ports To assist with development of user s applications and to provide convenient communication channels with both a terminal and a host computer two RS 232 transceivers are provided on the MPC8360 MDS Processor Board These transceivers are connected to the MPC8360 device via dedicated UART ports and UART2 The implementation is done by the HIN211CA part from Intersil which internally generates the required RS 232 levels from a single 3 3V supply The transceivers are enabled by BCSR9 3 As for the ports the UARTI port is always enabled while BCSR9 7 enables disables the use of the UART2 port If the UART2 port is not used these pins be used by UPC2 for other functions on the PIB The UART also features hardware flow control The RS 232 signals are presented on a single 10 pin RJ45 connector due to the small amount of room available on the PCI panel used when the MPC8360 MDS Processor Board is inserted in a A special cable included wi
81. o dislodge casing MPC8360 MDS Processor Board Rev A 1 Freescale Semiconductor 7 1 Figure 7 2 Flash Memory open casing Figure 7 3 Flash Memory remove memory unit Figure 7 4 Flash Memory unit removed Figure 7 5 Flash Memory replacing unit push in until click is heard 7 1 1 Cleaning Flash Memory If there is some decrease in performance from the flash memory unit the socket may need to be cleaned Do this by dipping a tooth pick dipped in isopropyl alcohol and gently removing any residual debris from the flash memory socket MPC8360 MDS Processor Board Rev A 1 7 2 Freescale Semiconductor 7 2 Replacing SODIMM units To remove or replace the SODIMM units follow the instructions in Figure 7 6 through Figure 7 10 in that order Figure 7 7 SODIMM Memory for 64 bit or 32 bit High Socket U69 on top side of board MPC8360 MDS Processor Board Rev A 1 Freescale Semiconductor 7 3 pops up das B 7 3 Replacing MPC860 Processor To remove the MPC860 processor follow the instructions in Figure 7 11 to Figure 7 16 below then remove the chip MPC8360 MDS Processor Board Rev A 1 7 4 Freescale Semiconductor To replace the MPC860 processor align the chip properly as shown in Figure 7 16 then follow the instructions in Figure 7 15 to Figure 7 11 below in that order Note that the Allen wrench is provided in the tool kit Figure 7 13 Allen s
82. odule connected to a PCI adaptor follow the illustrations in Figure 2 10 Figure 2 11 and Figure 2 12 to connect these items to the PIB Note that the card can only be inserted in the and PMCO shown The PCI adaptors can be inserted in any section for up to 4 PCI adaptors if space allows Connect using module s latches as shown Tighten by hand LADA Connect using PCI latches as shown Tighten by hand i M 1 2 qus 7 inf E ja Ea i Figure 2 11 Connecting adaptor to PIB MPC8360 MDS Processor Board Rev A 1 2 8 Freescale Semiconductor 9 10 11 12 Figure 2 12 Inserting spacers between PCI card and PIB The fully assembled PIB Processor board is shown in Figure 2 13 which also shows the PIB external connections relevant when the MPC8360 is used All external connections of the Processor board are active when the Processor board is installed on the PIB except the voltage input receives power from the PIB power input or the back plane only and the JTAG COP connection P8 which is replaced by the parallel port connection to a Figure 2 13 three PCI adaptors and one additional module shown installed on the PIB PCI cards are ready to receive any PCI compatible board including an 83xx Processor board installed in this case in the same manner as they are in a PC Using this system these boards
83. of the above interrupts 5 14 3 PCI Interrupt Each PCI slot on the PIB can generate up to four interrupts for a total of sixteen 4 slots x 4 interrupts each Each PCI expansion board can generate an interrupt at any given time When the MPC8360 MDS Processor Board is in Agent Mode only the INTA is used 5 14 4 RTC Interrupt RTC real time clock device used is DS1374 from Maxim It is connected to IRQ5 and can be programmed via the I2C 1 bus 5 14 5 FLASH Interrupt The FLASH memory is connected to IRQ6 Invoking this interrupt indicates that the programming of the flash was done 5 146 JTAG COP Interrupt The Connector uses two interrupts IRQ6 amp IRQ7 for Check Stop In Out It is used when working with an external debugger 5 147 GETH Interrupt has IRQ as an interrupt and GETH2 has 2 as an interrupt Invoking any one of these interrupts indicates that data has been transferred via the specific GETH port 5 15 Power Supply The MPC8360 MDS Processor Board power supply provides all necessary voltages for correct operation of the MPC8360 device the DDR TSEC Xilinx FPGA and all on board peripheral devices MPC8360 MDS Processor Board Rev A Freescale Semiconductor 5 43 5 151 Primary Power Supply There are 3 possible sources of power e External 5V Power Supply with On Off Power switch e 5V Power Supplied via PCI Edge Connector e 5V Power Supplied via PIB Riser Conn
84. on Center P O Box 5405 Denver Colorado 80217 1 800 521 6274 or 303 675 2140 Fax 303 675 2150 LDCForFreescaleSemiconductor hibbertgroup com Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters that may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized for use as components in systems inten
85. one mode while the USB controller configures the device Note also BCSR13 7 2 Differential Negative Data Differential Positive Data MPC8360 MDS Processor Board Rev A Freescale Semiconductor 5 19 Table 5 17 P1 MiniAB USB Connector continued Identification Signal for Host Device Mode Setting PCI mode vs stand alone mode 5 5 2 P2 DUART Port The DUART port connector P2 is implemented with a 90 10 pin RJ45 connector signals of which are described in Table 5 18 Table 5 18 DUART Port Description UART Signal Name Port Description CTS1 Clear To Send RTS1 EN Ready To Send ojo o s e 211 eee c meom _ om Rome wem For connection to regular D Type 9 RS232 cable use special cable from MPC8360 MDS Processor Board set 5 5 3 P3 32 bit PCI Edge Connector P3 is a PCI 32 bit edge connector used when the MPC8360 MDS Processor Board functions as an agent in either a PC or inserted in an adaptor on the PIB see Figure 2 14 5 5 4 P5 P6 Logic Analyzer Connectors P4 P5 and P6 are 38 pin SMT high density matched impedance connectors made by Tyco and used for Logic Analyzer measurements They contain local bus MPC8360 signals 8360 MDS Processor Board Rev A 5 20 Freescale Semiconductor 5 5 5 P7 SMB Connector RF Subminiature Coaxial Connector P7 is used to connect an external clock to the MPC8360 wh
86. onnected to PCI SYNC OUT which in turn is connected to PCI SYNC IN If high PCI SYNC receives its signal from SYNC OUT which in turn is connected to CLKIN host mode The bit is set by default by appropriate DIP switch SW3 4 May be rewritten via LBIU Reset Configuration Words Source These bits reflect CFG RS 0 2 signals logic level during PORESET Configuration sequence The bits are set by default by appropriate DIP switch SW3 3 May be rewritten LBIU PCI MODE Select if the PCI or ATM is used If low PCI is used If high ATM is used but see note below This switch is driven constantly and should be driven always to H L after reset sequence The PCIMODE switch on SW9 1 should not be set to 1 for ATM In order to place the device in ATM mode write to Ox XX001484 OX EFE35010 Flash Protected If this bit is low the flash memory is protected and cannot be written to or changed If this bit is high the flash memory can be written to LEDs Enable Extinguish all LED when high When low the LEDs are controlled normally May be rewritten any time via LBIU JTAG Chain Select When high this bit selects JTAG chain for external devices on PMC cards Low provides JTAG normal configuration 8360 MDS Processor Board Rev A Freescale Semiconductor 5 412 BCSR11 Status Register On the board 11 acts as a control register BCSR11 which may be read or written at any time
87. ory FCFG Flash Configuration Select of Riser Connector FLASH Non volatile reprogrammable memory FPGA Field Programmable Gate Array GbE Gigabit Ethernet GETH Gigabit Ethernet GPCM General Purpose Chip select Machine GPL General Purpose Line 2 Philips Semi Serial Bus LBIU Local Bus Interface Unit LED Light Emitting Diode Isb least significant bit MII Media Independent Interface GMII General Media Independent Interface JTAG Joint Test Access Group OTG On the Go PC IBM compatible Personal Computer PCI Peripheral Components Interconnect MPC8360 MDS Processor Board Rev A 1 Freescale Semiconductor Physical Layer PIB Platform I O Board expands the ADS functionality PSRAM Pseudo Static Random Access Memory PSU Power Supply Unit RCW L H Reset Configuration Word Low High RGMII Reduced General Media Independent Interface RTC Real Time Clock SDRAM Synchronous Dynamic Random Access Memory SMB Type of Mini RF connector SODIMM Mini DIMM Form Factor SPD Serial Present Detect TSEC Triple Speed Ethernet Controller ULPI UTMI Low Pin Interface UPM User Programmable Machine USB Universal Serial Bus 20 Zero Delay clock buffer with internal PLL for skew elimination 1 5 Related Documentation e MPC8360E HW Specification e MPC8360E User s Manual PowerQUICC MDS Platform I O Board User s Manual e MPCS8360E Hardware Getting Started 1 6 Specif
88. otol ENIM 1 2 3 8 8360 I2C Add DC Data mE DC Reg Add UPC1 amp TDM Signals 0x26 0x06 0x7ffc 0x26 0x02 0x7ffe IO Expander Figure 5 14 RMII as it traverses the PIB Table 6 5 describes each one of the UCC 3 8 pins used for RMII in the PIB It describes a complete trace of all signals from the MPC8360 device pins to the riser connectors on the MPC8360 MDS Processor Board to the PMC connections on the PIB and finally to the RMI functions named on the PIB MPC8360 MDS Processor Board Rev A 5 34 Freescale Semiconductor 5 9 7 Table 5 28 shows the MPC836x device G ETH pins used for each of the above mentioned interface modes Table 5 28 G ETH Pin Use GMII RGMII TBI RTBI GT CLK GT CLK TXC TBI TXCLK TXC TX CLK RCLK1 TX ER TX ER TXD9 TX_EN TX_EN TX_CTL TXD8 TD4_TD9 TXD 7 0 TXD 7 0 TD 8 0 TXD 7 0 TD 3 0 RX_CLK RX_CLK RXC RXCLKO RXC RX_ER RX_ER RXD9 RX DV RX DV RX CTL RXD8 RXD 7 0 RXD 7 0 RXD 3 0 RXD 7 0 RD 3 0 CRS CRS COL Table 5 29 below summarizes what values to write to which registers in order to set the G ETH mode Table 5 29 Selecting GMII RGMII TBI RTBI or PIB BCSRS8 0 1 GETH Mode BCSR9 0 Enable Disable Geth PHY1 MII1 Enable Disable Function Selected 00 RGMII 00 RGMII OO RGMII 00 RGMII 0
89. over the MPC8360 core voltage MPC8360 MDS Processor Board Rev A Freescale Semiconductor stabilization A Power On Reset may be generated manually as well by an on board dedicated push button SW1 In addition a power on reset for the MPC8360 be done by toggling bit 4 in BCSRI1 5 1 5 Hard Reset Hard Reset may be generated on the MPC8360E Processor Board by any one of the following sources e COP JTAG Port in Stand Alone Mode only Manual Hard Reset e Board Internal sources Hard Reset when generated causes the MPC8360 to reset all its internal hardware except for PLL logic and re acquires the Hard Reset configuration from its current source Since Hard Reset also resets the refresh logic for dynamic RAMs their content is lost as well CAUTION HRESET is an open drain signal and must be driven with an open drain gate by whatever external source is driving it Otherwise contention will occur over that line and that might cause permanent damage to either board logic and or to the MPC8360 5 1 6 COP JTAG Port Hard Reset stand alone only To provide convenient Hard Reset capability for a COP JTAG controller an HRESET line has been connected to the COP JTAG port connector The COP JTAG controller may directly generate a Hard Reset by asserting low this line The HRST signal from the COP JTAG is then driven to the FPGA and from the FPGA to the MPC8360 This technique is used in order to cooperate with the low
90. pite the reset clock and D chip select data as well as SDRAM if installed Reset contents are retained SRESET Not available when installed in a PC Pressing button SW8 results in aborting SW8 C program execution by issuing a level 0 interrupt NMI Abort to the MPC8360 The ABORT switch signal is NMI de bounced 8360 MDS Processor Board Rev 1 4 6 Freescale Semiconductor SW6 7 8 Resets and NMI SW2 Rotary Switch Swi AUS POR Figure 4 3 MPC8360 MDS Processor Board Push Buttons and Auxiliary POR MPC8360 MDS Processor Board Rev A 1 Freescale Semiconductor 4 7 MPC8360 MDS Processor Board Rev 1 Freescale Semiconductor Chapter 5 Functional Description In this chapter the design details of various modules of the MPC8360 MDS Processor Board are described This includes memory map details and software initialization of the board 5 1 Reset amp Reset Configuration 5 1 1 Reset Clocking and Configuration Initialization The MPC8360 samples four configuration pins at Power on Reset negation Three of these pins RESET 0 2 allow setting up to eight variant reset configuration sources such as I2C EEPROM parallel EPROM Flash or various hard coded options see the MPC8360E User Manual for more details See Table 5 1 for a list of the options The fourth pin CLKIN DIV determines whether or not CLKIN is divided by 2 Figur
91. r TSEC I F It is required to provide 3 3V or 2 5V to this voltage group in order to test it in both voltages Therefore a jumper JP5 is mounted on board Each of the regulators used in the on board power supply have embedded over current voltage and temperature protection The ability to measure the amount of current consumed by the 1 2V is provided by measuring the voltage drop on the fixed series resistors 10mQ in the corresponding circuits 8360 MDS Processor Board Rev A 5 44 Freescale Semiconductor 3 3V 6A A 1 2V 10A A 1V 1 5A Regulator TSEC DDR gt 7 VDD 2 5V 3A Regulator 1 25V 2 1A Regulator TERM VTT gt 2 5V 3A rms Regulator MPC836X GVDD DDR LVDD1 2 GETH LVDDO PCI OVDD IO VDD CORE AVDD1 2 3 4 5 6 3V PIB Insertion Indication BCSR FPGA_PRST 1 8V 1 5 Regulato r VCCINT 3 3V PIB 5V 5V enon SEQ DC D Convenor 5V Input Sources m mui mt unum Figure 5 20 Power Distribution on the MPC8360 MDS Processor Board Reset Controller 5V PIB 5V External 8360 MDS Processor Board Rev A Freescale Semicond
92. r the 64 bit mode only one SODIMM module should be used in M1 mounted on U69 see Figure 7 7 Note For using 32 bit SODIMM with an ECC choose a module that has a clock for ECC from module CK2 amp CK2 8360 MDS Processor Board Rev A Freescale Semiconductor 5 25 MPC8360 M1DQ 0 31 M2DQ 0 31 M1DQ 32 63 M1 M2DOS 0 3 M1DQS 4 M1ECC 0 7 M1DQS8 M1MDM 0 3 M2MDM 0 3 M1MDM 4 7 1 510 1 M1CAS M1RAS M1WE M1MA 14 0 M1CKO M1CKO M1CK1 1CK M1CKENO 2 5 M2RAS M2WE M2MA 14 0 2 7 M2MDQS8 1 5 M2MDM8 1 4 M2CKO M1CK2 M2CKO M1CK2 M2CK1 2 1 M2CKEN1 M1CK4 M2CKENO M1CK5 SODIMM32L 64 bit SODIMM64 bit Use only for M2 bus32 bit DQ 0 31 631 S 0 3 Q S 4 7 ECC 0 7 DQS8 MDM8 9 II D IM 0 3 m M 4 7 CS 0 1 CAS RAS WE CKO CKO CK1 069 CK2 NC CK2 NC CKENO CKEN1 DQ 0 31 NC i D Q 32 63 DQS 1 3 NC 5 4 7 DQ 0 7 ECC 0 7 DQSO DQS8 MDMO MDM8 MDM 1 3 NC MDN 4 7 CS 0 1 CAS RAS WE A 14 0 U34 CK2 CK2 CK1 CK1 CKO CKENO CKEN1 Figure 5 8 DDR Connections Block Diagram MPC83
93. read to from the BCSR registers The sixth device is the PIB 5 13 2 l2C 2 2 has three devices connected to it The first device is the EEPROM Board This is serial Atmel EEPROM AT24C01A 128KByte at address 0x50 This device contains all Board history The second device is the BCSR as Master Slave the same as on 12 1 The third device is the PIB 12 Address 0x50 0 51 0 52 0 68 BCSR Boot SPD SPD EEPROM soDIMI sopim2 RTC MASTER PIB MPC8360 Hs X 12 1 0 50 BCSR EEPROM Digital resistance ae ASTER 12 2 Figure 5 19 Dual I2C Block Scheme 5 14 External Interrupts There are several external interrupts applied to the MPC8360 via its interrupt controller ABORT NMI PIB PCI interrupt Host or Agent RTC FLASH COP CKSTPIn CKSTPO 8360 MDS Processor Board Rev A 5 42 Freescale Semiconductor e amp GETH2 5 141 ABORT Interrupt The ABORT is generated by a push button see Section 4 4 1 for location When this button is depressed the IRQO input to the MPC8360 15 asserted The purpose of this type of interrupt is to support the use of resident debugger if any is made available to the board 5 14 2 Interrupt The PIB has 4 interrupts IRQ4 IRQ5 IRQ6 IRQ7 In PCI Host mode they are called IROW IRQX IRQY amp IRQZ appropriately Each PMC module can use all four
94. registers LCRR 0 0005004 0 00000004 Flash CSO BRO 0xE0005000 OxFE001001 Port size 16bit MSEL GPCM ORO 0 0005004 7 16 BCSR CS1 0005008 0 8000801 Port size 8bit MSEL GPCM OR1 000500 OxFFFFE9F7 32K SDRAM CS2 OR2 0xE0005014 0 006901 64M MPC8360 MDS Processor Board Rev A 1 Freescale Semiconductor 3 3 Table 3 2 8360 MDS Processor Board Configuration Registers continued Register Name jtd ed Description BR2 0 0005010 OxF0001861 Port size 32 bit MSEL SDRAM LSRT 0 00050 4 0x3F000000 LSRT SDRAM refresh timer period MRTPR 0 0005084 0 20000000 LSDMR 0 0005094 0x0063B723 SDRAM LSDMR 0 0005094 0x2863B723 OxF0000000 0x000000FF LSDMR 0 0005094 0x0863B723 0 0000000 0x000000FF 0 0000000 0x000000FF OxF0000000 0x000000FF 0 0000000 0x000000FF 0 0000000 0x000000FF 0 0000000 0x000000FF 0 0000000 0x000000FF OxF0000000 0x000000FF LSDMR 0005094 0 1863 723 OxF00000ce 0x000000FF LSDMR 0 0005094 0 4063 723 LSRT OxE00050A4 0x20000000 LSRT SDRAM refresh timer period MRTPR 0 0005084 0x20000000 MRTPR Refresh timers prescaler lt Period of the refresh timers input clk gt lt sys_clk gt lt 0 20 gt Table 3 3 Init DDR values for DDR 64 bit Register Name 5 Description DDRLAWBARO OxEO0000A0 0
95. rom SW11 5 fetching the boot code until configuration by an external master is complete If low the core runs normally May be rewritten via LBIU 5 5 BMS Boot Memory Space Sets lower 8MByte boot memory space location when the DDR is used as the PCI boot source Otherwise for LBIU boot source this bit is high for upper boot memory space location User may change boot source location by request May be rewritten any time via LBIU 6 7 6 7 BOOTSEQ 0 1 Boot Sequencer Configuration These two bits reflect SW4 1 2 5 11 signals logic level during Reset Configuration sequence The bits are set by appropriate DIP switch May be rewritten via LBIU 5 4 6 5 5 Status Register On the board BCSRS acts as a control register BCSR5 which may be read or written at any time receives its defaults immediately after the PORESET signal 5 5 fields are described below in Table 5 6 Table 5 6 BCSR5 Register Description DEF on SWEN Soft Ware Watchdog Enable This bit reflects the SWEN signals logic level during Reset Configuration sequence The bit is set by default to low to Software Watchdog Disable May be rewritten via LBIU 9 11 1 3 ROMLOC 0 2 Boot ROM Interface Location These bits reflect ROMLOC 0 2 SWA 3 5 signals logic level during Reset Configuration sequence The bits are set by default by appropriate DIP switch May be rewritten via LBIU 5 4 7 BCSR6 Status Register This register is res
96. ry access the LALE will latch Local Bus Address 6 18 plus bank select A19 A20 on A15 A16 The local bus will then drive LRAS and the SDRAM device will latch the row and bank select During the second phase of memory access the LALE will latch the column on A21 A29 then the local bus will drive LCAS and finally the SDRAM will latch the column The parity device is the same device as for D 0 31 as it has the same parameters The Local Bus Data Parity LDP 0 3 is connected to the SDRAM data D 3 0 and the local bus LPBS signal is connected to the SDRAM DQM The address pins of the parity device are connected to the same pins as the data devices Table 5 23 SDRAM Connection to Local BUS 5 Row Connection 13 lines Column Connection 9 lines Select LB 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 ADD LSB ROW 8 18 FOLD SDRAM AO ADD Second Column num of COLS 9 lines ALE to LATCH First Bank Sel ROW num of ROWS 13 lines ALE to BSMA LB LATCH 19 20 Address Multiplexed A 6 18 over A 21 29 MPC8360 MDS Processor Board Rev A 5 28 Freescale Semiconductor 5 8 3 The Flash memory used see also Section 7 1 on page 7 1 is the MT28F128J3RG 12 from Micron The standard unit has 128Mbit but can be upgraded to 256Mbit by simply inserting the larger
97. s e Power on Reset amp Hardware configuration setting for the processor Hardware Reset Configuration bits are stored in BCSR registers available from the Local Bus e Hard Soft Reset and NMI IRQ push buttons debounce function Hardware Configuration for both GETH transceivers e Enable Disable to Two GETH 1 2 Transceivers Dual RS232 Transceiver LED off e Provides hardware write protection for FLASH and BRD I2C EEPROM e Two LEDs one green one red which provide software signaling e Special CCR COP register for JTAG port connectivity Status registers include PCI Host Mode indicates if the Board is working in a Host Mode Stand Alone or PIB Combined or the Agent Mode BCSR4 0 Processor Low Power Mode QUISCE BCSR11 0 BCSR Revision code BCSR12 0 3 REV BCSR12 4 7 SUBREV MPC8360 MDS Processor Board Rev A 5 8 Freescale Semiconductor Sections of the BCSR slice control registers generally have low active notations This means that a bit function is realized while the bit is zero When a bit is set to high a related function is disabled The default setting is assumed to be non functional The most significant bit is bit 0 The BCSR No s 0 7 registers reflect the values in the RCW High and Low registers of the MPC8360 chip The correspondence is indicated in the CWL or CWH column 5 4 1 BCSRO Status Register BCSRO serves as 8 bit control register on the board B
98. should be set to internal arbitration BCSR4 2 1 and the PCI Clock Output Drive should be set to high BCSR4 3 1 Also note that in Host Mode the CLKIN pin receives a 66Mhz clock from an external to the chip clock oscillator This is located on the Processor Board The following table Table 5 22 shows PCI settings that determine the communication settings between the Processor Board and the PMC slots when the MPC8360 MDS Processor Board is mounted on the PIB as a Host The configuration setting is done using the I2C 2 bus and the device addresses relate to 2 2 addresses The I2C device controls its setting using the PCA9555P W an I O expander For more details on this see the PIB User s Manual Table 5 22 PCI Settings for PIB device address register address All modes 0 All modes 0x0034 All modes 0 All modes OxFFFF All modes OxFFEF PCI Expansion Board OxF8FF 32 bit PCI PMC1 32 bit OxFFFF PCI PMC1 amp PMC2 32 bit OxF7FF 2 2 3 zy o o gt 5 lt 3 2 PMC3 32 bit OxFDFF 2 PMC2 amp PMC3 32 bit OxF9FF 5 6 3 PCI Setting when MPC8360 MDS Processor Board is Agent If the MPC8360 MDS Processor Board is inserted in a PC or inserted on a PMC slot on the PIB the FPGA configures the RCW to PCI Agent by setting BCSRA 0 to 0 The PCI port should be set to externa
99. sly operating the PCI bus on amp on PMCO Supports the operation of ATM on PMCO for UPCI and PMCI for UPC2 e Provides 6 ports for UCC3 UCC8 Allows a view of all the QE signals through PMCI In the block diagram in Figure 6 1 below note carefully the specific communication lines that are connected with each PMCx slot For example connects to the PMCI slot and the PMC2 slot and PCI2 connects to the PMC2 and PMC3 slot The specific connections dictate which modules can be connected to which PMC slot 8360 MDS Processor Board Rev 1 Freescale Semiconductor 6 1 8 gor In Header JB22 JB23 MDC amp MDIO MPC83xx Processor Board BxRMII PH 48V Input From Backplane RS422 ENET1 2 3 8 Parallel Port to JTAG nput Fro Power Su m pply 2x OPTIC CE Signals PCI2 PCHH MDC MDIO SPI Local Bus SPARE UTOPIA JTAG PMC PMCO 2xGETH OPTIC Figure 6 1 PIB Block Diagram with Processor Board 6 2 MPC8360 MDS Processor Board as Host If the edge connector P3 is not connected the MPC8360 MDS Processor Board configures itself as a Host which means that its clock is supplied via a clock device on the Processor Board In addition the Host Processor Board configures the PCI communication bus on the PIB identifies the various agents and modules connected to t
100. th the MPC8360 MDS Processor Board kit was prepared to connect between the 10 RJ45 to two Opin D Type female connectors The connector may be directly connected via standard serial cable to any IBM PC compatible RS 232 port 8360 MDS Processor Board Rev A 5 40 Freescale Semiconductor MPC8360 RS232 Buffer 10Pin RJ45 0 UART2 SOUT PF3 UART2 SIN PF2 UART2 RTS UART2 CTS External Dual Flat Cable to 9pin Dtype nCEUARTEN BCSR9 7 RS232EN BCSR9Q 3 Connected to Riser Connector to PIB for UPC2 signals Figure 5 18 RS232 Block Diagram The table below show the signals used by UART2 and their alternate UPC2 function The table below describes the complete use of the signals from the MPC8360 to the PIB Riser Connectors and from the Riser connectors to the PMC slots located on the PIB Table 5 32 UART2 and UPC2 shared signals MPC8360 Riser Conn PMC Conn Pin on PIB on PIB 5 13 12 Dual Port The MPC8360E has a dual I2C interfaces 2 1 amp I2C 2 with multi master support Each I2C uses two wire interface that contains an SCL Serial Clock signal and an SDA Serial Data signal for data transfer All devices that are connected to these two signals must have open drain or open collector outputs A logical AND function is performed on both signals with external pull up resistors located on the MPC8360 MDS Processor Board See Figure 5 19 for an illustration of the I2C connection s
101. ting bits in the CCR allows the PCI host to manage a serial access to the Processor Debug Port in the same manner as an on board command converter Figure 5 16 below illustrates this access concept Table 5 31 shows a list of CCR bits and their possible values and attributes Figure 5 17 below illustrates the access path to the COP from the host via the PCI bus 8360 MDS Processor Board Rev A 5 38 Freescale Semiconductor Host Memory MPC836x Memory View View SN Local Bus CCR TDI TCK TMS TRST HRST SRST EN COP like Header Figure 5 16 CCR PCI Local Bus Concept The CCR bit fields are described below Table 5 31 CCR Description Bit Mnemonic Function Default POR Value Attr 0 TDI Test Data In Hi Z W O MSB TDO Test Data Out 1 Test Clock Hi Z W O 2 TMS Test Mode Hi Z W O 3 TRST Test Reset Hi Z W O 4 HRESET Hard Reset Hi Z W O OD 5 SRESET Soft Reset Hi Z W O OD 6 Reserved 7 nCOP EN High Enables the CCR COP signals on Hi R W LSB the debug port Low Allows a different COP debug source Hreset or Sreset bits assertion causes a reset to the processor s register They receive the default value that causes a reset in the Local Bus Controller To access CCR again the prior Local Bus Controller values should be configured Note or W Read or Write option or O Prese
102. to the PIB Board Debug port access via dedicated 16 pin connector COP via PCI port or from parallel port interface on the PIB e One I2C port for EEPROM 256Kbyte Real Time Clock RTC and SODIMM SPD EEPROM A second 2 port is used to connect to the Board Revision Detect 256Kbyte EEPROM MPC8360 MDS Processor Board Rev A 1 1 2 Freescale Semiconductor 1 3 2 Can function in one of three configurations Stand alone Asa PCI add in card for a standard PC computer or as an agent on the PIB PIB combined mode development platform with Processor Board as a Host and PIB connected together Board Control and Status Register BCSR implemented in Xilinx FPGA Three power options Main 5V power 15 fed from external power supply for stand alone mode Power from PC supply when acting as a PCI add in card Power from the PIB when PIB and Processor Boards are combined PCI add in card form factor dimensions 285mm x 106mm External Connections The MPC8360 MDS Processor Board interconnects with external devices via the following set of connectors P1 USB connector P2 RJ45 10 pin for DUART signals P3 32bit PCI Edge Connector P4 P5 P6 Three Logic Analyzer MICTOR Connectors P7 SMB RF Connector for external pulse generator P8 16 pin COP JTAG Connector P9 16 pin header for FPGA In System Programming P10 Voltage Input P11 P12 P13 300 pin FCI Expansion Conn
103. uctor 5 45 MPC8360 MDS Processor Board Rev 5 46 Freescale Semiconductor Chapter 6 Working with the PIB 6 1 Platform I O Board Concept The MPC8360 MDS Processor Board together with the MPC8Xxx MDS Processor Board form the MPC8Xxx Modular Development System MDS The MDS enables software programmers to develop software for the 8Xxx architecture A block diagram of the PIB with a Processor Board is shown in Figure 6 1 on page 6 2 The PIB provides more capabilities for developing 8Xxx software than the MPC8Xxx Processor Board alone by allowing an MPC8Xxx Processor Board to be configured as a Host with up to four PCI compatible boards as Agents connected to PCI slots via PMC PCI adaptors or via the Expansion adaptor on the PIB motherboard The PIB also allows an MPC8Xxx Processor Board to be used in a back plane configuration and provides room and connections for additional modules such as an ATM Quad OC3 or other modules Power is provided by the PIB which also provides additional signal connections via the back plane if used and optical GETH connectors on the front plane side of the PIB The MPC8360 MDS Processor Board can be connected to a PC in this configuration via a parallel port connector without the need for an external command converter In summary the PIB provides the following Support for the MPC8360 as a PCI Host Support for MPC83xx Agent boards connected to the PCI bus e Supports simultaneou
104. up to three function as agents while the Processor board already installed functions as a host This allows you to take advantage of the parallel processing capabilities of the 83xx line of products Operate Code Warrior to verify that the processor board has been installed properly Connect power cable to the PIB and external cables in accordance with your development needs Verify that LD1 and LD2 turn on and then turn off see Figure 2 2 for location They should be on for only a few moments This indicates that the board has successfully undergone the boot up sequence MPC8360 MDS Processor Board Rev A 1 Freescale Semiconductor 2 9 Power input for table top configuration Front plane connection Power input for ors installed optical GETH working with a back plane PCI adapt is gt i Back plane connection 2 incl GETH and voltage T z ee Additional module installed Parallel port to PC Double RS 232 p connected to RJ45 DUART GETH twisted pair Not relevant for MPC8360 Figure 2 13 Fully Assembled Combined system PIB Processor Board additional module and PCI cards MPC8360 MDS Processor Board Rev A 1 2 10 Freescale Semiconductor 2 2 3 For Agent Mode 1 Installed in a PC Insert the MPC8360 MDS Processor Board into a PC using its PCI edge con nector As an
105. volume device in the socket The Flash is connected to the slow bus The slow bus is organized in such a way that the data is obtained from the data transceiver and the address is obtained from the address latch buffer The Chip Select signal is connected to the CSO line for booting from the Flash A special buffer for control signals is used in order to minimize the load on the local bus control signals which are already used on the SDRAM Local bus LOE control Flash OE and LBS 0 1 control Flash WE signals The Local Bus A7 is routed to the flash for optional expansion The flash output STS signal indicates that either a programming or erase function is being done this signal is connected to MPC836X interrupt line In order to boot from FLASH SW9 3 should be set to 1 5 9 GETH GETH ports features are as follows e Support for TBI and RTBI The GETH ports are compatible with for 10 100 BaseT or GMI TBI and RTBI for 1000Base T Default mode When working in PIB Combined Mode attached to riser connections PIB TBI and RTBI are supported on both the MPC8360 MDS Processor Board and on the PIB Two IEEE 802 3 compliant GETH ports with 10 100 1000 Base TX I F e Two PHYs from Marvel 88 1111 connected to ENETI amp ENET2 Pins e The two PHYs are controlled and configured via the Processor Board s BCSR8 0 5 in all modes It is a
106. x00000000 DDRLAWARO 4 0x8000001B 256 First DDR Controller Registers SODIMM initializations CLK_CNTL 0 0002130 0 82000000 SS EN 1 CLK_ADJST 2 CSO_BNDS 0 0002000 0 00000007 first 128MB MPC8360 MDS Processor Board Rev A 1 3 4 Freescale Semiconductor Table 3 3 Init DDR values for DDR 64 bit continued CS0_CONFIG 0 0002080 0 80000101 CS1_BNDS 0xE0002008 0x0008000f last 128MB CS1_CONFIG 0 0002084 0 80000101 TIMING_CFG_1 0 0002108 0 37343321 CFG 2 0 000210 0 00000800 DDR_SDRAM_CFG 0 0002110 0 42008000 32 0 gt 64 bit bus is used 2T_EN 1 DDR_SDRAM_MODE 0 0002118 0 20000162 DDR_SDRAM_INTERV 0 0002124 0x045B0100 AL delay before enable DDR_SDRAM_CFG 0 0002110 0xC2008000 Table 3 4 Init DDR values for 2 x 32 bit Register Name scenes Description Local Access Window DDR SDRAM DDRLAWBARO 0xE00000A0 0x00000000 DDRLAWARO OxEO0000A4 0x8000001A first 128M Local Access Window Secondary DDR SDRAM SDDRLAWBARO 0xE00000E0 0x08000000 SDDRLAWARO 4 0x8000001A first 128M QE Secondary Bus Access Windows SDMCSAR 0 0001804 0 00008000 SDMCEAR 0 0001844 SDMCAR 0 0001884 0x00000001 First DDR Controller Registers SWISSBIT Half SODIMM SODIMM initializations CLK CNTL 0xE0002130 0x82

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