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1. http netpro evtek Fi pdc pdc centre x Fig 1 An example of laboratory report displayed in the main browser of Deeds 11 The Deeds simulation tools The simulation tools are three a Digital Circuit Simulator d DcS a Finite State Machine Simulator d FsM and a Micro Computer Board Emulator d McE All the simulation tools are characterized by a learn by doing approach They are integrated together design and simulation of complex networks integrating standard logic with state machines are possible In Fig 2 a few screen shots of the Deeds tools are shown a 1 Pee Flop Q o BN I of a Esp 4 of JEO FET Dec Ber cE FEET aF iruclieneus equi pa ri Fi of 1 ami rn iw F1 EI Anana Ir El hi KL perge 5 H clock sr of archer ur cing 3 af cegmentizl xr Bie state marliines pa 159 Aer Prieka mehea rrr sr fuat Siete IE P B ies x Aer Mort a LT dE Een ila pas sal to i rie Dya ewe mra dur
2. Gur mh ENET je i h ii ir lam Fam HR E s EE E F HE HE FP FF FF HE PT FF FF FJ HP FF FF FF HE FF FF FF FP FI HHGO FF FF T7 HF FF PP TW BEF FT PF TW FF HF FT pr PF HE FF BP FF HB FF PE PF HW FF EF FW FF BE FF EF PS FF BE FF P FF FI FF EF TE FF FF FF FF FF FF TW FF SN FTP FT EF FF HF FF EF TW FF HE FF FF TT PF PT BL IIENNH Br UIESM Fig 2 The Deeds environment the main and assistant browsers on top left and the three Simulation Tools the Digital Circuit Simulator on top right the Finite State Machine Simulator on bottom left and the Micro Computer Emulator on bottom right Deeds The Main Browser The simulators are integrated around two HTML browsers enabling active Internet navigation to sites where students find pages with lessons exercises and laboratory assignments The main web browser of Deeds when activated shows a HTML page that allows to connect to the Deeds web site and to the on line learning materials developed at DIBE University of Genoa The main browser Fig 3 has been developed around the standard Microsoft WebBrowser component the same used by the Microsoft Internet Explorer amp exte
3. 7 ADD instruction AND s A lt A AND s P 00 The underlined bits replace the A lt AORS 0 P 0 O 110 underlined bits in the ADD set lt uem ICD d a w en ER LN HL 1 KES S V 0 ka s 1 deas 1 00 110 100 d gt DEC m M lt m 1 101 m is any of r HL IX d IY d as shown for the INC instruction DEC same format and states as INC Replace 100 with 101 in opcode CPL e 1 1 00 101111 2F 1 1 4 One s Du 11 101 101 ED 2 2 Two s A lt A 1 01 000 100 44 complement The V symbol in the P V flag column indicates that the P V flag contains the overflow of the operation Similarly the P symbol indicates parity r means any of the registers A B C D E H L ADD A IY d lt d Tr WO 3 rs FD 3 5 19 10000 110 CY means the carry flip flop Flag Notation flag is not affected 0 flag is reset 1 flag is set t flag is set according to the result of the operation 103 Arithmetic Instructions 16 bits operation 8 Z H PVN 762020 Hex ayes commens Mnemonic Operation S Z H 76543210 Bytes Cycles Cycles Comments kasa VAR uu kas ADC HL ss HL HL ss T vg 11 101 101 ED 2 4 15 TY 01 ss1 010 SBC HL ss HL HL ss 1 dq
4. Gesting us me cre robat k zm 1 liming analysis of Internet Libera Irnrraginicireolo Explorer 3 Deeds flip flop 0 6 E the of the ene ME Ps 8 Fle Run Tons 0 m sequential network using the timing ile sio i A b da mb 3 um You can open it m the d DeS with a 1 3 gt mon x click on the figure JE PET Fhp flop i Home Open Back Forward Stop Refresh Assistant d Dc5 Analysis of a 1to 2 2i T Analysis of a simplified shared line communication channel Telnet Application of Boolean Algebra Analysis of a multi level logic network Design of a programmable logic gate Synthesis of a boolean function Functional analysis of a two level combinational network Analysis and design of multiplexer based combinational networks Alora risor Simulate the JK PET Arithmetic circuits Pay attention to put m evidence m the timing diagram the meanmgful combinations of input values include Preset and Clear activation Design of a sign converter and of a two bit adder eds Storig Delays and Hazands Remember that the Pr
5. Fig 26a The d DcS File menu Command to create a new circuit file Command to open a circuit file The file can be also downloaded directly from a Web site Save Command to save current circuit file Save as Print Command to print the circuit Command to save current circuit file with a different name or in a different position 35 Paper Setup Command to define current paper format and orientation It displays the Paper Setup dialog window Fig 26b Paper Setup Paper Format Bib Vertical rr zl C Horizontal Fig 26b The Paper Setup dialog window Recent Files List Commands to re open the most recent files Up to 8 recent files can be reopened with this list The symbol that is displayed on the left of the file name means that The file has been stored The file has been stored by the user on the local disk or network the user on the local disk or network has been downloaded from site but it has been saved yet on the local disk or network The file has been loaded from a local courseware where it is read only and it has not been saved yet on the local disk or network Standard command to close the application 36 Undo Redo Copy Select All Copy Image Delete zi CErl C b L LI Paste select All Copy Image
6. L II v mcr per ered MIC HL HL 9 1 v D Do 110 100 INC IX dl F of Be 11011101 DD 3 B 23 X 1 00 110 100 WI INC IY dl d D Lf seg intin 11 111 101 FD 3 E 23 Fig 77 An example of the on line instruction set documentation the Arithmetic and Logic instructions zu 81 DMCB Short Guide DMCS Processor Architecture Load 8 Lead lEbits Avithmetic Logic 8 bits Arithmetic 16 bits CPU Control Jump Subprogram Call and Return i i Input Output Alfabetical Order Mumerical Order ASCII cade Shift and Rotate Instructions Mnemonic Symbolic Flags 00 Opcode Bytes es Clock Comments S Z C 76543210 001 111 br m pd D F a 8 00 000140 PLC IX d 007509 1 FE P n 11 011 101 Sed 11 001 011 J r L RLE IY d erue t Ir P sp ET E m 0 t ju E E 010 m of r CHL m ed v xd as shown for the fem a Pee b T RLCinstruction m m f E 0 011 Instruction format and States are the Replace 000 with E Fig 78 Another of the on line instruction set documentation the Shift and Rotate instructions When the user wishes to verify the correctness of the written cod
7. flag is not affected 0 flag is reset 1 flag is set X flag is don t care flag is set according to the result of the operation 104 Jump Instructions Symbolic Flags Opcode M Clock Mnemonic Operation S Z H PNN C 76543210 Hex Bytes Cycles Cycles Comments 3 1 10 10 JP nn PC nn 11000 011 C 3 lt n gt n gt 3 3 Condition NZ non zero Z zero NC non carry C carry PO parity odd PE parity even P sign positive 111 Msign negative 11 101 001 E9 11011 101 D 2 11 101 001 E9 11 111 101 FD 2 2 11 101 001 E9 4 JP HL PC HL JP IX PC lt IX JP IY PC IY Notes Flag Notation flag is not affected 3 D JP cc nn if cc is true 11 cc 010 PC lt nn n gt n gt Call and Return Instructions Symbolic Flags Opcode M Mnemonic Operation S Z H C 76543210 Hex Bytes Cycles Comments 1 CALL nn SP SP 1 11 001 101 CD 5 SP PCy n gt SP lt SP 1 n SP PC PC nn 3 if cc is false 5 if cc is true CALL cc nn if cc is true 11 ccc 100 3 SP lt SP 1 lt n gt 3 SP lt lt n gt SP SP 1 SP PC PC lt nn RET PC SP 11 001 001 C9 1 SP SP 1 PCy lt SP SP lt SP 1 1 if cc is false m RET cc if cc is true PC SP SP lt SP 1 PCy lt SP SP lt SP 1 RST p SP lt SP 1 SP PCy SP lt SP 1 SP PC PC lt p Notes F
8. E Cerca s Preferiti Indirizzo http esng dibe unige 22 vai Collegamenti e Commenti finali Mostra p v AT Deliverable n 4 ESD2 EO 2003 2004 Laboratory Session 4 Asynchronous serial communication Group nn Name and Surname 12 Name and surname 2 Assignment 4 1 Asynchronous serial communication and Paste from the d NIcE editor add comments i needed i E Area sconosciuta Fig 88 The simple template provided on the web page that the student can download In the next figure an example of complete report is displayed Fig 89 g hiipainetpio ertek ipda fuse fest ntn frd HE File Modifica Visualizza Inserisci Formato Strumenti Tabell gt b gt gt ic Indietro x B L Cerca s Preferiti Indirizzo http j netpro evtek Fipdc pc Vai Collegamenti gt p 62 gt r ru 1 ti Commenti finali Mostra v z adl 5 P SERIN 33h SEROUT 35h oo00h 0100h 0100h LD SP 0000h CALL INIT CALL RECEPTION CALL ENCRIFTION CALL TRANSMISSION JP LOOF LD 00h LD HL 00h LD DE 00h LD BC 00h OUT SERDUT EITTIHE Delay equal to a bit time RET TIHE165 Delay equal to i bit time 16 BET RECEPTION IN SEBIN CALL 16 AND 00000001 JP Z RECEPTION LD B 8 CTRLSTART IN
9. 1 ani Group 1 1 Dn 1 za al ect F Syste ectronic Systems and Networking User Manual Feb 2004 Edited by Giuliano Donzellini and Domenico Ponta Exegi monumentum aere perennius regalique situ pyramidum altius quod non imber edax non Aquilo impotens possit diruere aut innumerabilis annorum series et fuga temporum Quinto Orazio Flacco Deeds Digital Electronics Education and Design Suite User Manual Index Preface P 8 Introduction P 9 Deeds as a learning environment for digital electronics P 10 How to use Deeds to teach theory P 10 How to use Deeds to solve exercises P 10 How to use Deeds to learn to design electronic systems 11 The Deeds simulation tools P 12 Deeds The Main Browser P 13 Deeds Main browser Menu P 16 Deeds The Assistant Browser d AsT P 22 Deeds The Assistant Browser Menu P 23 Deeds The Digital Circuit Simulator d DcS P 25 Introduction P 26 A simple example P 27 A simple example of interaction between Deeds browsers and d DcS P 30 d DcS Menu Commands P 35 Deeds Finite State Machine Simulator d FsM Introduction Finite State Machines FSM description languages ASM charts State Block Decision Block Conditional Output Block ASM Charts amp State Diagrams FSM description languages state transition table FSM description languages hardware description language Learning FSM methods and problems Reusing FSM component they can be
10. d CB27 SLA A CB20 SLA B CB21 SLAC CB22 SLA D CB23 SLAE CB24 SLAH CB25 SLA L CB2E SRA HL DDCB d 2E SRA IX d FDCB 2E SRA d CB2F SRA CB28 SRA B CB29 SRAC CB2A SRA D CB2B SRAE CB2C SRAH CB2D SRA L CB3E SRL HL DDCB d 3E SRL IX d FDCB d SRL lY d CB3F SRL A CB38 SRL B CB39 SRLC SRL D SRL E SRLH SRL L SUB HL SUB IX d SUB IY d SUB A SUB B SUB C SUB D SUB E SUB H SUBL SUB n XOR HL IX d XOR IY d XOR A XOR B XOR C XOR D XOR E XOR H XOR L XOR n 111 DMC8 Instructions in numerical order 11nn 16n NOP LD BC nn LD BC A INC BC INC B DEC B LDB n RLCA ADD HL BC LD A BC DEC BC INC C DECC LD C n RRCA LD DE nn LD DE A INC DE INC D DEC D LDD n RLA ADD HL DE LD A DE DEC DE INC E DEC E LDE n RRA LD HL nn LD nn HL INC HL INC H DEC H LDH n ADD HL HL LD HL nn DEC HL INC L DEC L LDL n CPL LD SP nn LD nn A INC SP INC HL DEC HL LD HL n SCF ADD HL SP LD A nn DEC SP INC A DEC LDA n CCF LD B B LD B C LD B D LD B E LD LD B L LD B HL LD B A LD C B LD C C LD C D LD C E LD LD C L LD C HL LD C A LD D B LD D C LD D D LD D E LD D H LD D L LD D HL LD D A LD E B LD E C LD E D LD E E LD E H LD E L LD E HL LD E A LD H B LD H C LD H D LD H E LD H H
11. 110 W ss 11 001 011 it a katu Lm 11 001 011 CB 11 b 110 isisa s IX d T 11011 101 11 001 011 SETb IY d IY d lt 1 11 111 101 11 001 011 Notes The notation m indicates bit b 0 to 7 of location m BIT instructions are performed by an bitwise AND Flag Notation e flag is not affected 0 flag is reset 1 flag is set X flag is don t care t flag is set according to the result of the operation NOOR G N Oly To form new opcode replace 11 of SET 5 with 10 Flags and states are the same IN A n IN r t 0 P 0 2 000 OUT r er n 161 001 Notes The V symbol in the P V flag column ndicales al the P V flag contains the overflow of the operation Similarly the P symbol indicates parity r means any of the registers A B C D E H L Flag Notation flag is not affected 0 flag is reset 1 flag is set t flag is set according to the result of the operation 107 DMC8 Instructions in alfabetical order The instructions are 659 considering all the possible variations 8E ADC A HL FDCB d46 BIT 0 IY d CB6F BIT 5 A DDBEd IX d CB47 BIT 0 A CB68 BIT 5 B FD8Ed d 40 BIT 0 B CB69 BIT 5 C 8F ADCA A CB41 BIT 0 C CB6A BIT 5 D 88 ADC A B 42 BIT 0 D CB6B BIT 5 E 89 ADC A C CB43 BIT 0 E CB6C BIT 5 8A ADC A D CB44 BIT 0 H CB6D 5 L 8B ADC A E CB
12. 118 24 02 2003 d AsT e A little bug was fixed it occurred during page loading in the Assistant Browser 20 02 2003 All e The Deeds and Assistant browsers are now enabled and specialized to run the Deeds learning material as well ordinary HTML pages During operation these browsers decode the so called Deeds Commands that the author of a lesson or laboratory session include in the HTML page to enable interactivity between the HTML page and each Deeds tool included in the suite e Nowitis possible to open a file downloading it from internet This command is intended to be driven by the Deeds browser when the user clicks on an active link to open a file Deeds Now when a Tool is launched the Splash Form is displayed only the firth time e The problem of double launch of Deeds when you start it from the Application Bar has been solved e For debug reasons a hard close command has been added If could be necessary you may close the Deeds main application without closing also the other tools activating the ordinary File Close command while pressing the Shift and Control keys d DcS e Now the title of the Timing Diagram window shows the current timing simulation mode the modes enabled are by now the Incremental Interactive Simulation mode IIS and the Timing Interval Simulation mode TIS e Nowitis possible to open a file downloading it from internet This command is intended to be
13. 37 SCF CBC6 SET 0 HL DDCB d C6 SET 0 IX d FDCB d C6 SET 0 IY d CBC7 SET 0 A CBCO SET 0 B CBC1 SET 0 C CBC2 SET 0 D CBC3 SET 0 E CBC4 SET 0 H CBC5 SET 0 L CBCE SET 1 HL DDCB d CE SET 1 IX d FDCB d CE SET 1 IY d CBCF SET 1 CBC8 SET 1 B CBC9 SET 1 C CBCA SET 1 D CBCB SET 1 E CBCC SET 1 CBCD SET 1 L CBD6 SET 2 HL DDCB d D6 SET 2 IX d FDCB d D6 SET 2 IY d CBD7 SET 2 A CBDO SET 2 B CBD1 SET2 C CBD2 SET 2 D CBD3 SET2 E CBD4 SET 2 H CBD5 SET 2 L CBDE SET 3 HL DDCB d DE SET 3 IX d FDCB d DE SET 3 IY d CBDF SET 3 A CBD8 SET 3 B CBD9 SET 3 C CBDA SET 3 D CBDB SET 3 E CBDC SET 3 H CBDD SET 3 L CBE6 SET 4 HL DDCB d E6 SET 4 IX d FDCB d E6 SET 4 IY d CBE7 SET 4 A CBE0 SET 4 B CBE1 SET 4 C CBE2 SET 4 D CBE3 SET 4 E CBE4 SET 4 H CBE5 SET 4 L CBEE SET 5 HL DDCB d EE SET 5 IX d FDCB d EE SET 5 IY d CBEF SET 5 A CBE8 SET 5 B CBE9 SET 5 C CBEA SET 5 D CBEB SET 5 E CBEC SET 5 H CBED SET 5 L CBF6 SET 6 HL DDCB d F6 SET 6 IX d FDCB d F6 SET 6 IY d CBF7 SET 6 A CBF0 SET 6 B CBF1 SET 6 C CBF2 SET 6 D CBF3 SET 6 E CBF4 SET 6 H CBF5 SET 6 L CBFE SET 7 HL DDCB d FE SET 7 IX d FDCB d FE SET 7 IY d CBFF SET 7 A CBF8 SET 7 B CBF9 SET 7 C CBFA SET 7 D CBFB SET 7 E CBFC SET 7 H CBFD SET 7 L CB26 SLA HL DDCB d 26 SLA IX d FDCB 26 SLA
14. CALL TIMEl6 AND 00000001 aje gt E Area sconosciuta Fig 89 A partial view of a final student report 90 d McE Menu Commands The menu of the Micro Computer Emulator allows the user to access all the function of the application The ToolBars replicate most of the commands already in the menu to speed up user operations Micro Computer Emulator Oud WIE Edit Project Emulation Deeds Open cave Save 5 Close Close All p Print Ctrl F Code mc 2 Code mcd E 3 ESAME 06 02 2004 mc8 E 4 ESAME 06 02 2004 mc8 9S 502 EO 2004 04 05 es3 mc8 01030 1 tem mc8 AlE ExiE Fig 90 The File menu Command to create a new void source file If one or more files not void are already in the editor a new editor page is created Command to open a source file If one or more files are already in the editor a new editor page is created and the file will be opened in it The file can be downloaded directly from a web site Save Command to save current source file Save as Command to save current source file with a different name or in a different position Print Command to print the source file 91 Recent Files List Commands to re open the most recent files Up to 8 recent files can be reopene
15. DDCB d B6 FDCB d B6 CBB7 CBB0 CBB1 CBB2 CBB3 CBB4 CBB5 CBBE RES 5 A RES 5 B RES 5 C RES 5 D RES 5 E RES 5 H RES 5 L RES 6 HL RES 6 IX d RES 6 IY d RES 6 A RES 6 B RES 6 C RES 6 D RES 6 E RES 6 H RES 6 L RES 7 HL DDCB d BE RES 7 IX d FDCB d BE RES 7 IY d CBBF CBB8 CBB9 CBBA CBBB CBBC RES 7 A RES 7 B RES 7 C RES 7 D RES 7 E RES 7 RES7 L RET RET C RET M RET NC RET NZ CB16 DDCB d 16 FDCB d 16 CB17 CB10 CB11 CB12 CB13 CB14 CB15 17 06 DDCB d 06 FDCB d 06 CB07 CB00 CB01 CB02 CB03 CB04 CB05 7 ED6F CB1E DDCB d 1E FDCB d 1E CB1F CB18 CB19 CB1A CB1B CB1C CB1D 1F CB0E DDCB d 0E FDCB d 0E CB0F CB08 CB09 CB0A CB0B CB0C CB0D RET P RET PE RET PO Z RL HL RL IX d RL IY d RLA RLB RLC RLD RLE RLH RLL RLA RLC HL RLC IX d RLC IY d RLC A RLC B RLCC RLCD RLC E RLCH RLCL RLCA RLD RR HL RR IX d RR d RR A RR RRC RRD RRE RRH RRL RRA RRC HL RRC IX d RRC IY d RRC A RRC B RRC C RRC D RRC E RRC H RRCL RRCA RRD RST 00h RST 08h RST 10h RST 18h RST 20h RST 28h RST 30h RST 38h SBC A HL SBC A IX d FD9E d SBC A IY d 9F SBCA A 98 SBCA B 99 SBCA C 9A SBCA D 9B SBCA E 9C SBC A H 9D SBCA L DEn SBCA n ED42 SBC HL BC ED52 SBC HL DE ED62 SBC HL HL ED72 SBC HL SP
16. Delete Del Fig 27 The d DcS Edit menu Command to undo the previous operation Command to redo the operation previously cancelled by the Undo command command temporary inhibited Command to cut the selected part of the circuit and copy it on the clipboard command temporary inhibited Command to copy the selected part of the circuit on the clipboard command temporary inhibited Command to paste the clipboard content in the circuit command temporary inhibited Command to select all the object of the drawing Command to copy the selection as a bitmap image and put it on the Clipboard Command to delete all the selected components 3 View Menu Aei SE Fie Edit View Tools Circuit 5 n Es Zoom In RT s Zoom m zoomi Zoom 2 zZoom3 L Zoom4 _ FoomS Ctre5 Page Layout Fig 28 The d DcS View menu Zoom In Command to zoom in the drawing Zoom Out Command to zoom out the drawing Zoom 1 2 3 4 5 Command to zoom the view to different levels The standard level is the 3 Normal Command to set the normal view of drawing space i e as uniform continuous background only with the indication of drawing margins Page Layout Command to set the view of the drawing space as a paper foil i e with visible foil borders and shadows together with drawing
17. Fig 66 The d FsM View menu Zoom In Out Command to zoom in or zoom out the drawing Property ToolBox Command to activate the Property Window that enables the user to set and modify the properties of the selected State Block Conditional Block or Conditional Output Block It shows four different property pages depending on the context Fig 67 Properties State Black Name b Active Outputs OUT Code FF State at Reset activation Properties Conditional Output Black Active Outputs Property to Edit Fig 67 The four pages of Property Window used to define properties of state conditional and conditional output blocks Command to set the normal view of drawing space i e as uniform continuous background only with the indication of drawing margins Page Layout Command to set the view of the drawing space as a paper foil i e with visible foil borders and shadows together with drawing margins 72 juste nus Window Dee Start Simulation Stop Simulation Fig 68 The d FsM Simulation menu Start Simulation Command to start the functional simulation of the finite state machine represented by the currently ASM diagram During simulation the editor commands are inhibited and the Timing Diagram window is displayed Fig 59 Stop Simulation Command to stop simulation and return to the edit mode of the ASM diagram Fo
18. LD SP IX 109 F5 C5 D5 E5 DDE5 FDE5 CB86 DDCB d 86 FDCB d 86 CB87 CB80 CB81 CB82 CB83 CB84 CB85 CB8E DDCB d 8E FDCB d 8E CB8F CB88 CB89 CB8A CB8B CB8C CB8D CB96 DDCB d 96 FDCB d 96 CB97 CB90 LD SP IY LD SP nn NEG NOP OR HL OR IX d OR IY d OR A ORB ORC ORD ORE OR ORL ORn OUT C A OUT C B OUT C C OUT C D OUT C E OUT C H OUT C L OUT n A POP AF POP BC POP DE POP HL POP IX POP IY PUSH AF PUSH BC PUSH DE PUSH HL PUSH IX PUSH IY RES 0 HL RES 0 IX d RES 0 IY d RES 0 RES 0 B RES 0 C RES 0 D RES 0 E RES 0 H RES 0 L RES 1 HL RES 1 IX d RES 1 IY d RES1 A RES 1 B RES 1 C RES 1 D RES 1 RES 1 RES 1 L RES 2 HL RES 2 IX d RES 2 IY d RES2 A RES2 B CB91 CB92 CB93 CB94 CB95 CB9E DDCB d 9E FDCB d 9E CB9F CB98 CB99 CB9A CB9B CB9C CB9D DDCB d FDCB d A6 CBA7 CBA0 CBA1 CBA2 CBA3 CBA4 CBA5 CBAE RES 2 C RES 2 D RES 2 E RES 2 H RES 2 L RES 3 HL RES 3 IX d RES 3 IY d RES 3 A RES 3 B RES 3 C RES 3 D RES 3 E RES 3 H RES 3 L RES 4 HL RES 4 IX d RES 4 IY d RES 4 A RES 4 B RES 4 C RES 4 D RES 4 E RES 4 H RES 4 L RES 5 HL DDCB d AE RES 5 IX d FDCB d AE RES 5 IY d CBAF CBA8 CBA9 CBAA CBAB CBAC CBAD CBB6
19. RES 2 HL RES 2 RES 3 RES 3 C RES 3 D RES 3 E RES 3 H RES 3 L RES 3 HL RES 3 A RES 4 B 113 CBA1 CBA2 CBA3 CBA4 CBA5 CBA6 CBA7 CBA8 CBA9 CBAA CBAB CBAC CBAD CBAE CBAF CBB0 CBB1 CBB2 CBB3 CBB4 CBB5 CBB6 CBB7 CBB8 CBB9 CBBA CBBB CBBC CBBD CBBE CBBF CBC0 CBC1 CBC2 CBC3 CBC4 CBC5 CBC6 CBC7 CBC8 CBC9 CBCA CBCB CBCC CBCD CBCE CBCF CBDO CBD1 CBD2 CBD3 CBD4 CBD5 CBD6 CBD7 CBD8 CBD9 CBDA CBDB CBDC RES 4 C RES 4 D RES 4 E RES 4 H RES 4 L RES 4 HL RES 4 A RES 5 B RES 5 C RES 5 D RES 5 E RES 5 H RES 5 L RES 5 HL RES 5 A RES 6 B RES 6 C RES 6 D RES 6 E RES 6 H RES 6 L RES 6 HL RES 6 A RES 7 B RES 7 C RES 7 D RES 7 E RES 7 H RES 7 L RES 7 HL RES 7 A SET 0 B SET 0 C SET 0 D SET 0 E SET 0 H SET 0 L SET 0 HL SET 0 A SET 1 B SET 1 C SET 1 D SET 1 SET 1 H SET 1 L SET 1 HL SET 1 A SET 2 B SET2 C SET 2 D SET2 E SET 2 H SET2 L SET 2 HL SET 2 A SET 3 B SET 3 C SET 3 D SET 3 E SET 3 H CBDD CBDE CBDF CBEO CBE1 CBE2 CBE3 CBEA CBE5 CBE6 CBE7 CBE8 CBE9 CBEA CBEB CBEC CBED CBEE CBEF CBFO CBF1 CBF2 CBF3 CBF4 CBF5 CBF6 CBF7 CBF8 CBF9 CBFA CBFB CBFC CBFD CBFE CBFF CCnn CDnn CEn CF DO D1 D2nn D3 n D4nn D5 D6 n D7 D8 DAnn DBn DCnn DDO9 DD19 DD21 nn DD22 nn DD23 DD29 DD2A nn DD2B DD34 d SET 3 L SET
20. nux h Mort eck al a Des xvneluranaus zequennial nae ark 6030 The cincodi ti aimed ID 2 3 0 1 2 3 und pte Cii pg ras kr oun pi ha d fur comter scheme CQ aud QU ais Pre coureurs Fel utaq Hee rimis pp the count ur corre zy Tari eileen the of thee clark di tem high eem copa und ranret prz mada Ear coract input tz Sw ad the T aed epus kaya eo ro Dar kaya fee un ler risa hog clt para gra EER sui EO Gans C Tem De Mee Bee Exim Cae 11 E Germs a j ma mah ft imer Get sa TM dla W 2 re hama EL 12 Fi Be Pe m F 1 A UD DDD LE gt Coss E L H m P P B EL IT E B E BE E E E H F B 1412
21. setting their properties Fig 44b The student inserts conditional blocks setting their properties Fig 44c The student inserts logical path the green lines no property needs to be set Note that the line arrows are automatically added Fig 45 The simulation results for the edge detector described above Fig 46a b The ASM transition table describing the component on the left and the generated symbol on the right Fig 47 Two instances of the component are connected in a circuit composed of standard gates in the d DcS Fig 48 Timing simulation of the previous network obtained with the d DcS Fig 49 A list of laboratory assignments with use of d FsM opened in the Deeds main browser Fig 50a The specific laboratory assignment opened in the Assistant browser first page Fig 50b The specific laboratory assignment opened in the Assistant browser second page Fig 51 The downloaded ASM diagram template of the solution Fig 52a b c The three pages of the Input Output dialog window used to define inputs outputs and state variables Fig 53 The property window displaying the properties of the a state Fig 54 The property window displaying the properties of a condition block Fig 55 The finished ASM diagram and its timing simulation in the d FsM Fig 56 The finished d DcS schematic and the timing simulation of the component in the d DcS Fig 57 Also in this case the student will download the r
22. 0 0 0 0 0 0 0 0 Please check the specified port address it doesn t match with the board setup SP 60000000 oc iE Farts IN amp ddr Jo Code Label Comment Addr Code 21 pE Comment onl 0106 CD2401 LOOP CALL RECEPTION B 0109 1 CALL B amp e egpesss o waow foo ee CALL TEANSHISSIQ BUT 0108 0601 JP LOOP 001 o o o o o 00 r021OC m 0 0 o o o deme THLE nr 098 1 25 0114 10000 LD HL OOH on OB 9 8 9 00 031 OD 9 0 9 foo 0117 110000 LD DE DDH M L4 011A 010000 LD 00 O11D D335 OUT 3 di ES Fig 84 The program under test in the interactive debugger of the d McE a Warning has be sent to the user In Fig 84 the program is Animated by the student i e it is automatically executed step by step at a human readable speed The speed is controlled by the cursor visible on the tool bar Animation Speed In this example a typical warning message is generated by the debugger In a real case if a port hardware address is not correctly instanced in the program code unpredictable events could result By the learner point of view it could be very difficult realize what really happens in the system
23. 3 HL SET SET 4 SET 4 4 SET 4 SET 4 SET 4 L SET 4 HL SET 4 SET 5 B SET 5 C SET 5 D SET5 E SET 5 H SET 5 L SET 5 HL SET5 A SET 6 B SET 6 C SET 6 D SET 6 6 SET 6 L SET 6 HL SET 6 SET 7 B SET 7 C SET 7 D SET 7 SET 7 SET 7 L SET 7 HL SET7 CALL Z nn CALL nn ADC RST 8h RET NC POP DE JP NC nn OUT n A CALL NC nn PUSH DE SUB n RST 10h RET C JP C nn IN A n CALL C nn ADD IX BC ADD IX DE LD IX nn LD nn IX INC IX ADD IX IX LD IX nn DEC IX INC IX d DD35 d DD36 dn DD39 DD46 d DD4E d DD56 d DD5E d DD66 d DD6E d DD70 d DD71 d DD72 d DD73 d DD74 d DD75 d DD77 d DD7E d DD86 d DD8E d DD96 d DD9E d DDA6 d DDAE d DDB6 d DDBE d DDCB d 06 DDCB d 0E DDCB d 16 DDCB d 1E DDCB d 26 DDCB d 2E DDCB d 3E DDCB d 46 DDCB d 4E DDCB d 56 DDCB d 5E DDCB d 66 DDCB d 6E DDCB d 76 DDCB d 7E DDCB d 86 DDCB d 8E DDCB d 96 DDCB d 9E DDCB d A6 DEC IX d LD IX d n ADD IX SP LD B IX d LD C IX d LD D IX d LD E IX d LD H IX d LD L IX d LD IX d B LD IX d C LD IX d D LD IX d E LD IX d H LD IX d L LD IX d A LD A IX d ADD A IX d ADC A IX d SUB IX d SBC A IX d AND IX d XOR IX d OR IX d CP IX d RLC IX d RRC IX d RL IX d RR IX d SL
24. 7 IY d FDE1 POP IY FDE5 PUSH IY FDE9 JP IY FDF9 LD SP IY FEn CPn FF RST 38h 115 Appendix Deeds historical version notes Notes are reported in time reverse order 20 01 2004 d McE It has been solved a bug of the Save As command now if you press the Cancel button of the Save As standard dialog the Close operations if running are aborted as expected The execution of the RRCA instruction has been fixed The I O Port Address dialog on computers with the video card configured in low resolution mode did not appear The problem has been fixed the dialog now will show always centred on the main window 11 11 2003 Deeds d AsT Now when a new version of the Deeds is installed the browser home pages are reset to the defaults to avoid confusion between the different Deeds versions However the address of the previous user home page is not lost it will be found in the history list of the opened pages in the open window d DcS An error in simulation of finite state machine components has been fixed the behaviour of the network when the FSM Reset input is activated at time 0 Now when you start the interactive simulation the input switches are initialised according to the assigned names as in the timing simulation mode the initial value will be set to one if the name represents an active low signal i e the name is negated As a consequence for
25. FF FF 0050 FF FF n70 FF FF m FF FF CF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF YYYYYYYY YYYYYYYY IN OBJECT CODE aan cogo COE EU nn 50 0 mm DEI ppuan INTERRUPT cs DS OUT 0 9 goo 00 00 moo m0 00 ES SA0080 JP 0100H PUSH HL PUSH AF SAVE ALL USED REGISTER ONT PUSH BC PUSH DE LD TIME CONTROL IF SECOND FI DEC A puOBeseseessse o re10Dsesesss o A 320080 LD TIME A C26400 NZ FINE INT IF IT NOT IT DOESN T U DEEL UPDATE IN VELBEF 47 BoA 1 00 LD E 00H E IS USED STATE REGIS DEOS LD C 8 RE IS COUNTER EI Address 0067h CAPS INS NUM Fig 73 The assembler level debugger of the Micro Computer Emulator computer ile Edit Bra ect Emulation Deeds Options DMC8 AP FLASH Fig 74 The emulated board as represented in the
26. Fe EEE Finite State Machine Flip Flop R 5 latch Commands to insert Flip Flop components Registers 5 1 5 0 Register 2 bits 1 5 1 5 0 Register 4 bits 2 5 1 5 0 Register 8 bits 3 5 LP O Register 2 bits 4 5 IP O Register 4 bits 5 SLP Register 8 bits 6 P L 5 0 Register 2 bits 7 P I 5 O Register 4 bits 8 P I 5 O Register 8 bits 9 Universal Register 2 bits 4 Universal Register 4 bits B Registers h Universal Register 8 bits Counters E Counters Finite State Machine Commands to insert Counter components Finite State Machine BH Finite State Machine li TRO New Finite State Machine Load Finite State Machine Commands to insert Finite State Machine components The New command activate the Finite State Machine Simulator d FsM allowing the user to create a new component from scratch The Load command allows the user to load a previously designed component 43 Simulation Menu Interactive Animation Timing Diagram Simulation Start Animation Stop Animation zn Deeds Mode 2 L Interactive Animation Ctrl F8 MN ZH Timing Diagram Simulation Fo gt Skart Animation r I 5 Stop Animation z uid Options Help E Fig 31 The d DcS Simulation menu Command group to set the simulation mode the file in the
27. Fig 44a The student inserts state blocks setting their properties 7 Finite State Machine Simulator edeedetector_b fsm aid File Edit view Simulation Window Help m x 5 e IJ Ex amp lt J w P El TE ua p I A4 55 30 Fig 44b The student inserts conditional blocks setting their properties 56 r3 D Lj Li D A Fitz atit ite 2g22d srsergp e psy fio EU n fi File Edit view Simulation Window Help p d ES Property to Edit A4 15 Fig 44c The student inserts logical path the green lines no property needs to be set Note that the line arrows are automatically added The diagram describes an edge detector Each time the input IN presents a transition O to 1 or T to 0 an output pulse of the duration of one clock cycle is generated To verify its behaviour it is possible simulate it with the d FsM The timing simulation of the d FsM is only functional it don t take in count component delays for instance because it simulates directly the algorithm without synthesize the network in term of gates and flip flops Fig 45
28. The d McE debugger instead has been designed to track many common mistakes reporting them to the student before then unwanted results could complicate the understanding of the wrong behaviour of the program In the present case Fig 84 the processor should execute the OUT instruction at address 011Dh But the address instanced by the instruction is 35h while no port has been set to respond to this address So the student has two possibilities to return to the editor and change the source code adapting it to the board setup or to change the board setup 88 To change the board setup for instance it is possible to activate with a right click on the port pane the I O Ports Address Decoding dialog window Fig 85 VO Address Decoding Input Port Address Addresses In ram IB n je jos Hex Dec 7 Output Port Address oaj 22 OoB ocje E ope OF Cancel Fig 85 Port addresses can be modified in the I O Ports Address Decoding dialog window Another possibility that resembles the real case is to switch the current d McE page and visualize the physical board as seen in Fig 74 Now it is possible to toggle with a mouse click the address dip switches that define the hardware address decoding Fig 86 IA IB IC and ID are the addresses of the four parallel input ports available on board OA OB OC and OD are those of the four output port
29. Version Notes Command to display the Deeds Version Notes file Command to display the d FsM splash window dialog 76 Deeds The Micro Computer Emulator d McE gt V A IN VIPS SF fee Ag This image from the ancient and mysterious Piri Reis 1513 77 Introduction With the Micro Computer Emulator the user can practice programming at assembly language level Fig 72 It functionally emulates a board including CPU ROM and RAM memory parallel I O ports reset circuitry and a simple interrupt logic The custom 8 bit CPU named DMC8 has been designed to suite our educational needs and it is based on a simplified version of the well known Z80 CPU processor Micro Goode File Edit Project Emulation Deeds Options View Help Board Editor Debugger Da g Pam ig E Code PDA EQU DeedsProject EQU DElh Deeds EQU OEZh HTML EQU 8000h EQU 800 me ORG 0000h MCE Files mcf JP 0100h Interrupt handler routine ORG O038h INTERRUPT PUSH AF save all used register onto the stack PUSH BC PUSH DE PUSH HL ESAME 06 02 2004 tr LD TIME rcontrol if a second has finished DEC LD TIME NZ FINE INT it L3 hot ib dosesH t update the 1 IN VELREF LD B LD E 00h C B SOC a counter LD HL VE
30. a particular state only if a certain condition on inputs is satisfied such output signals are known as conditional outputs or Mealy outputs In that case you need to use the CLIT conditional output block Just put the ellipse on a transition arrow coming out of a decision diamond and write inside the ellipse the name of the output signal you want to activate when the expression inside the diamond is true Please notice that the conditional Fig 38c Conditional Output block does not represent a state instead it activates an output that it is active Block in the state it descends from ASM Charts amp State Diagrams It is easy to convert a State Diagram in an ASM Chart and vice versa In Fig 39a we report a basic example of State Diagram oR SR 00 Input conditians 00 01 10 state number output Fig 39a The State Diagram representation of a SR flip flop 51 The following ASM Chart Fig 39b can be used to model exactly the same behaviour state name output Gl EM is activated P input conditions Fig 39b The ASM Chart representation of a SR flip flop The first thing you can see is that in both models you have an object to represent the states of the machine The states are numbered 1 2 in the State Diagram and labelled with letters a b in the ASM Chart but the 1 1 relationship between them is obvious e state 1 state a flip flop output 0 e state 2 state b flip flop output 1 A
31. margins 38 Digital Circuit Simulator Lab _06_es_02_full pbs File Edit View 7 52 Circuit Simulation Deeds Options F H a to d elect by Area DD D p e Select and Move Select and Delete so irl EE Abe Label 4 Fig 29 The d DcS Tools menu Select One Command to selects one object by point and click Select by Area Command to select a group of objects in a rectangular area Select and Move Command to select and move a single object by point and click Select and Delete Command to select and delete a single object by point and click Label Command to insert or edit the label of a selected object it is possible to associate labels only to Input Output blocks and to Finite State Machine components Rotate Group of commands to rotate an object during its insertion Right Down Left Up Four commands to rotate an object during its insertion to the specified direction Toggle Command to toggle the direction of an object during its insertion 39 Digital Circuit Simulator 06 es 07 full phs Fie Edit View Tools 22 1 Simulation Deeds Options Help amp Clock Generator fbe 551 Input Sree i gt i a gt EF GE Gt I High Level vec SL Low Level Gnd T0 s su u te sine gt Wire Output Display C
32. not affected continue 101 Load Instructions 16 bits second section Symbolic Flags Opcode Mnemonic Operation 5 2 H PVN C 76 543 210 SP lt SP 1 SP SP lt SP 1 SP qq PUSH IX SP lt SP 1 SP lt SP IX PUSH IY SP lt SP 1 SP IY SP lt SP 1 SP IYL POP qq SP qq SP lt SP 1 SP lt SP lt SP 1 POP IX SP IX SP lt IX SP lt SP 1 POP IY SP IY SP lt IY SP lt SP 1 SP lt SP 1 SP SP lt SP 1 SP lt qq Notes 11 qqO 101 11 011 101 11 100 101 11 111 101 11 100 101 11 440 001 11 011 101 11 100 001 11 111 101 11 100 001 11 qqO 101 dd is any of the register pair BC DE HL SP qq is any of the register pair BC DE HL AF Flag Notation flag is not affected M Clock Hex Bytes Cycles Cycles OO 1 1 Comments 102 Arithmetic and Logic Instructions 8 bits Symbolic Flags Opcode Clock Mnemonic Operation 5 2 H PVN 76 543 210 ie Cycles Comments 10000 r r Reg ADD A n lt t V 0 1 11000110 000 B mee pee Dre v eise rp ei ADD A HL A HL t V 0 10000 110 010 011 ADD 4 lt 1 0 7 11011101 5 1 100 H 10 000 110 101 L 111 A lnc V 0 lt s is of r n HL s eee perp 9 IY d m
33. only and it has not been saved yet on the local disk or network Standard command to close the application 70 File Sele View Simulation inda Undo CErl X Copy Image Faste Select All Le Define Inj Out Ctrl I Fig 64 The d FsM Edit menu Undo Command to undo the previous operation command temporary inhibited Cut Command to cut the selected part of the ASM diagram and copy it on the clipboard command temporary inhibited Copy Image Command to copy the selection as a bitmap image and put it on the Clipboard Command to paste the clipboard content in the circuit command temporary inhibited Select All Command to select all the object of the drawing Define In Out Command to define or modify Inputs Outputs and State Variables It activates a modal dialog window see Fig 65 where the user can add rename and delete the Input and Output lines up to 8 lines as well as the State Variables up to 6 The dialog is divided in the specialized pages Input Output and State Vars New ADD QC QB State Register DK Cancel Fig 65 The three pages of the Input Output dialog window used to define inputs outputs and state variables 71 View Menu state Machine Simulator VS Simulation Window Deer Zoom In coom P Property ToolBox Ctrl F Drawing Grid Norrnal Page Layout
34. schematic editor if it is not file in the schematic editor if it is not Command to start simulation when currently mode is Animation Command to stop simulation when currently mode is Animation Command to set the Interactive Animation Mode for simulation When activated simulation don t start immediately If the Timing Diagram window is opened it will be closed The editing commands are disabled and the user is prompted to save Command to set the Timing Diagram Mode for simulation When activated simulation doesn t start immediately but the Timing Diagram window is opened instead The editing commands are disabled and the user is prompted to save the 44 Options Help Switch to Deeds Crrl F7 Swikch to Last F7 Switch to Wexk Fig 32 d DcS Deeds menu Switch to Deeds Command to switch focus to the Deeds main browser Switch to Last Command to switch to the tool that was last on top before switching to the currently opened instance of the d DcS Switch to Next Command to switch focus among all active Deeds applications in order of activation 45 Options Menu Options C gt E Standard ToolBar v Component ToolBar Toolbars Show and Dock All Toolbars Dockable ToolBar Status Bar Fig 33 The d DcS Options menu Configuration Command to change the application configuration disabled in this version ToolBars Comman
35. template doc a Visualizza Inserisci Formato Strumenti Tabella Finestra 7 V O E 1009 6 Cl Lettura E Titolo Casella paste the timing diagram here Assignment 2 2 Analysis ofa de multiplexer 1 2 1 Schematic paste here your schematic 2 Truth Table fill the truth table paste the timung diagram here Assignment 2 3 Analysis of a simplified shared line communication channel 1 Schematic paste here your schematic 2 Timing Diagram paste the timing diagram here Hote that the timing diagram could be quite large maybe it will be necessary to copy and paste the timing results in afew separate images Fig 25 The report template for this laboratory assignment 34 d DcS Menu Commands The menu of the Digital Circuit Simulator allows the user to access all the function of the application The ToolBars replicate most of the commands already in the menu to speed up user operations eireuit Simulator View Tools Circuit Si E Open Save Save Print Paper Setup Lab es z Full pbs 2 Lab es 02 Full pbs 3 Lab 02 es 03 Full pbs 4 Lab 02 es 02 Full pbs 5 0040 1 phs SetReset pbs 7 Complex pbs 8 ex00220_1 pbs Exit
36. the FSM block and therefore simulate digital systems characterised by a functional division between architecture and controller the last one being implemented by a finite state machine If a student wishes to compare the results with the ones obtained by traditional synthesis he can proceed manually using the table of transitions or the ASM chart in order to obtain a traditional structure with a state register made by flip flops and a combinational network based on logic gates 55 A simple example In following screen shots of the d FsM Fig 44a b c you can see the drawing of an ASM diagram followed by a preliminary verification in the internal timing simulator d the student picks up state blocks from the bin on the Tool Bar Fig 44a then e adds conditional blocks Fig 44b and by last f connect logically them using lines Fig 44c At every step when needed the student sets properties of each introduced block gt Finite State Machine Simulator edgedetector a fsm A5 mx 8 Edit View Simulation Window Help Z8 X me eo p om om n Ed Ie E 9 State Block a Outputs LI OUT Lode S 4 59 50 0 State at Reset activation
37. time 625 When the goes ligh the receiver continues to sample SERIN at the same rate If the line 15 sampled lich for 8 times continuously the receiver declares recogmsed the start bit and assumes to be at the middle of the bit time On the contrary the recerrer re starts operations okmg again tor the next valid start bit TF the receiver recognises the start bit it will continue sampling the line but only once every bit time 10 mS starting from the middle of the recognised start bit acquiring the following 8 data bits 07 0 and the stop bit Ifthe stop bit is wrong the data bits are ignored and the system re starts waiting again for a new start bit Ifthe stop bit is correct the cryptographic operation takes place and the resulting byte will serially transmitted according to the defined standard onto the SEROUT Ime The program should start on activation of the system hardware RESET Click here to load a trace lot a possible solution Suggestions For the sake of simplicity suppose that itis not possible to receive data when transmitting As suggested in the solution trace divide the assembly code m reusable subprograms and suppose available two delay subroutines named 10 ms TIMIELI6 625 Fig 82b The specific laboratory assignment opened in the Assistant browser second p
38. to Finite State Machines Download Re thinking a synchronous counter as Finite State Machine FS OU Reverse engineering a synchronous sequential circuit 00250 Design of a synchronous mod 5 up down counter Oe TUS Design of a simple serial line Design of finite state machines Download ign of a timing sequence generator 00290 00260 l Design of a serial data processor 00300 Run a new instance of the Assistant Browser Deeds Exercises by topic Fig 6 the learning material page available the Deeds web site opened the main browser 19 Deeds Main browser Menu The main browser menu allows to navigate web site to run simulators and tools to switch between the opened tools and to customize the user options File Menu Open Page Deeds Deeds Learning Materials Run Tools Options Help Home Page 2 Page Chri c Back 4A Back gt Forward Ctrl F stop ctes Foy Refresh Bp LA Print Preview a E Print Page Exit Fig 7 The main browser File menu Deeds Open a Courseware Page or Document Dass Register as Home Page Command to navigate to the main browser home page it can be user defined Open the Open Page dialog Fig 8 In this dialog window the user can type dir
39. where Learning Material are available In Fig 4 you see the screen shots web page of the site DES P File Run Tools Options Help NS22 S lt S Home Open Back Forward Stop Refresh Assistant d DcS ho D S University of Genoa 958 Jibe Essas Bagot E Electronic Systems and Networking Group lectronics E ducation amp D esign shows a page with an example of guide to the simulators usage Also here all objects can be made active The links that the page shows permit for instance to launch the Digital Circuit Simulator load a file in it Print the schematic simply by a click in the HTML Please open the Digital Circuit page Simulator Digital Circuit Simulator o The tipical usage of the Deeds Assistant Then load the file Counterpbs inthe js to be tiled to a Simulation Tool guiding the Simulator student in the work expecially for beginners Operazione completata Deeds Home Page Fig 4 The main browser connected to the Sreen Shots page of the Deeds web site The user can also download the last version of the Deeds suite as soon as it become available Fig 5 5 Deeds Deeds File Run Tools Options Help a Open Back Forward Stop Refresh Assistant d This preliminary beta version of Deeds includes only the following tools eThe Deeds Main Browser The d AsT Assistant Br
40. 1 DD 00 110 110 36 d o lt n gt LD IY n IY d lt n 11 111 101 FD 00 110 110 36 gt BAG Rew pM LD A DE A lt LESS EE 011 010 E DLL Ime I LD DE A lt IRR Te 010 010 B E T r r means any of the registers D E H T Notation flag is not affected 100 Load Instructions 16 bits first section Symbolic Flags Opcode Clock Mnemonic Operation 5 2 PVN C 76 543 210 Bytes m Cycles Comments Nd m p E LD nn 11011101 00 110 001 lt n LD IY nn IY lt nn 11 111 101 00 110 001 lt n LD HL nn L lt nn m lt 1 LD dd dd lt nn T 107 i01 lt 1 01 dd1 011 LD IX nn 11 011 101 IX lt 1 00 101 010 LD IY nn IY lt nn 11 111 101 lt nn 1 00 101 010 LD L 22 3 5 16 nn 1 H lt n gt LD nn d nn dd 11 101 101 nn 1 lt 01 ddO 011 LD IX nn IX 11 011 101 nn 1 lt IXH 00 100 010 lt LD nn IY nn IY 11 111 101 nn 1 lt IY 00 100 010 lt LD SP SP IX 11 011 101 DD 11 111 001 F9 LD SP IY SP lt IY 11 111 101 FD 11 111 001 F9 Notes dd is any of the register pair BC DE HL SP qq is any of the register pair BC DE HL AF Flag Notation flag is
41. 1 to 2 00040 Verify the behavior of the 1 gt 2 demultiplerer represented m the figure below using the Deeds Digital Circuit Simulator 4 5 Click on the figure to open in the d Dc5 a trace of the network s schematic and then complete itte obtain the schematic below lo complete the drawing you should also name the Input and Output components click here Lt fad or on the same button on the 6 5 tooolbar then click on each M component to be named Qu 1 Once completed the schematic you ll be ready to start the functional simulation ofthe network and then the tmine simulation In this the mput waveforms should be defined order to distinguish easily the selected output from the non selected one Fig 21 The specific laboratory assignment opened in the Assistant browser The assignment asks the user to verify the behavior of the 1 22 demultiplexer represented in the figure using the Deeds Digital Circuit Simulator The text suggests to click on the figure to open in the d DcS a trace of the network s schematic and then to complete it In this example you see that it is necessary only a simple click on the figure to activate the simulator and to download from the web site a template of the solution This approach aims to simplify user operation avoiding to spend time in no useful and distracting tasks 31 The user will see the Digital Circuit Simulator an
42. 43 LL ENTITY deriv Llock Reset IN atd_logic Reset IM std logic gt Inputs gt Outputes OUT std logic ARCHITECTURE behave OF deriv I5 Behavioral Description TYPE states is state a state b state c state d SIGMAL State Next State states BEGIN Next State Combinational Logic Copy Fig 62 The VHDL code window If you wish to save the generated code in a file click on the Save button you will prompted to chose a name file before to save it If you want include the VHDL code in another text file click on the Copy button to pass all the VDHL code onto the clipboard ready to be pasted in a code editor of your choice Command to print the Finite State Machine ASM diagram Command to define current paper format and orientation It displays the Paper Setup dialog window Fig 63 Papen Setup Paper Format a4 21 29 7 Vertical Horizontal Fig 63 The Paper Setup dialog window 69 Recent Files List Commands to re open the most recent files Up to 8 recent files can be reopened with this list The symbol that is displayed on the left of the file name means that The file has been stored by the user on the local disk or network Q The file has been downloaded from a web site but it has not been saved yet on the local disk or network fo The file has been loaded from a local courseware where it is read
43. 45 BIT 0 L CB76 BIT 6 HL 8C ADC A H CB4E BIT 1 HL DDCB d 76 BIT 6 IX d 8D ADC A L DDCB d 4E BIT 1 IX d FDCB d 76 6 IY d CEn ADCA n FDCB d 4E 1 IY d CB77 BIT 6 A ED4A ADC HL BC CB4F 1 A CB70 BIT 6 B ED5A ADC HL DE CB48 BIT 1 B CB71 BIT 6 C ED6A ADC HL HL CB49 1 CB72 BIT 6 D ED7A ADC HL SP CB4A BIT 1 D CB73 BIT 6 E 86 ADD A HL CB4B BIT 1 E CB74 BIT 6 H DD86d IX d CB4C BIT 1 H CB75 BIT 6 L FD86d d CB4D BIT 1 L CB7E BIT 7 HL 87 ADD A A CB56 BIT 2 HL DDCB d 7E BIT 7 IX d 80 ADD A B DDCB d 56 BIT 2 IX d FDCB d 7E BIT 7 IY d 81 ADD A C FDCB d56 BIT 2 IY d CB7F BIT 7 A 82 ADD A D CB57 BIT 2 A CB78 BIT 7 B 83 ADD A E CB50 BIT 2 B CB79 BIT 7 C 84 ADD CB51 BIT 2 C CB7A BIT 7 D 85 ADD A L CB52 BIT 2 D CB7B BIT 7 E ADD CB53 BIT 2 E CB7C BIT 7 H 9 ADD HL BC CB54 BIT 2 H CB7D BIT 7 L 19 ADD HL DE CB55 BIT 2 L DC CALL C nn 29 ADD HL HL CB5E BIT 3 HL FCnn CALL M nn 39 ADD HL SP DDCB d 5E BIT 3 IX d D4nn CALL NC nn DD09 ADD IX BC FDCB d 5E BIT 3 IY d CDnn CALL nn DD19 ADD IX DE CB5F BIT 3 A C4nn CALL NZ nn DD29 ADD IX IX CB58 BIT 3 B Fann CALL P nn DD39 ADD IX SP CB59 3 CALL PE nn FD09 ADD IY BC CB5A BIT 3 D E4nn CALL PO nn FD19 ADD IY DE CB5B BIT3 E CCnn CALL Z nn FD29 ADD IY CB5C BIT 3 H 3F CCF FD39 ADD IY S
44. A IX d SRA IX d SRL IX d BIT 0 IX d BIT 1 IX d BIT 2 IX d BIT 3 IX d BIT 4 IX d BIT 5 IX d BIT 6 IX d BIT 7 IX d RES 0 IX d RES 1 IX d RES 2 IX d RES 3 IX d RES 4 IX d DDCB d AE RES 5 IX d DDCB d B6 RES 6 IX d DDCB d BE RES 7 IX d DDCB d C6 SET 0 IX d DDCB d CE SET 1 IX d DDCB d D6 SET 2 IX d DDCB d DE SET 3 IX d DDCB d E6 SET 4 IX d DDCB d EE SET 5 IX d DDCB d F6 DDCB d FE DDE1 DDE5 DDE9 DDF9 SET 6 IX d SET 7 IX d POP IX PUSH IX JP IX LD SP IX 114 ED62 ED63 nn ED67 ED68 ED69 ED6A ED6F ED72 73 ED78 ED79 ED7A ED7B EF SBCA n RST 18h RET PO POP HL JP PO nn CALL PO nn PUSH HL AND n RST 20h RET PE JP HL JP PE nn CALL PE nn IN B C OUT C B SBC HL BC LD nn BC NEG IN C C OUT C C ADC HL BC LD BC nn IN D C OUT C D SBC HL DE LD nn DE IN E C OUT C E ADC HL DE LD DE nn IN H C OUT C H SBC HL HL LD nn HL RRD IN L C OUT C L ADC HL HL RLD SBC HL SP LD nn SP IN A C OUT C A ADC HL SP LD SP nn XOR n RST 28h RET P POP AF JP P nn DI CALL P nn PUSH AF ORn RST 30h RET M LD SP HL JP M nn EI CALL M nn FDO9 FD19 FD21 nn FD22 nn FD23 FD29 FD2A nn FD2B FD34 d FD35 d FD36dn FD39 FD46
45. D1INF 2003 2004 Laboratory Session 8 Design of Simple Finite State Machines Group nn Name and Surname 1 gt Mame and Surname 2 gt Assignment 8 1 Design of a synchronous mod 5 up down counter I d FsM ASM Diagram paste here the ASM Diagram 2 d FsM Timing diagram paste here the timing diagram 314 Schematic paste schematic 4 DeS Timing diagram paste here the timing diagram 0 j I T m m r F Ek Disegna 4 4 4 8 z lt gt D T a nt a REG REV EST 55C Inglese a Fig 58 The report template for this laboratory assignment assignment 66 The timing diagram window In this window Fig 59 the timing diagram of all the signals is constructed during the simulation in a interactive mode The timing diagram displays the Input and Output signals and at bottom the current State by symbolic name and by code Fig 59 The Timing Diagram window of the d FsM CLOCK In the default mode the user clicks on the Clock button to advance the simulation by step clock cycle If the tool bar button o is checked the simulation step is automated the execution speed is controlled by the tool bar cursor To toggle Input signal values the user clicks on the Input signal buttons under the Clock button In the IN example of Fig 59 the butt
46. F FF FF FF FF B 0 0 o o0 020 0 6 0 w FF FF FF FF FF FF FF FF FF E 39209 00 joo FF FF FF FF FF FF FF FF H 92552005950 L 00 vc Eit 15 IK 0 0 0 ooo gt a 0 0 1070 D 0 vos FF FF FF IY sossossssoseoses o FF FF FF SP 0898889 8808889 099 rs m 003A 003A 120 Ports N geeseess o sssvss o INTERRUPT PUSH AF SAVE ALL USED PUSH BC II struct i on sec 00 te p rsi EE ra I 4 OUT MMMM PUSH HL 00 ms sse o 1021 eo 9 9 919 aw 00 LD TIME CONTROL IF SECUND H DEC OBeosssssss o os oDsopepese E E Fig 80 The Debugger module shows the program under test the memory the CPU registers the I O ports The first pane in the window shows the CPU internal registers For instance at this moment of the program execution the Program Counter register contains the value 003Ah as you can see also in the last pane where the current instruction to be executed in actually at this address The second pane displays the memory contents The used memory locations are highlighted they correspond to the object code under execution The user can change manually each memory location The third pane represents the Input Output port contents The user can interact w
47. Fig 50a The specific laboratory assignment opened in the Assistant browser first page The assignment asks the user to design a synchronous mod 5 up down counter using the Finite State Machine Simulator In the laboratory assignment Fig 50a is explained that the counter should generate a numerical sequence on the outputs QC QB and QA depending from the line input EN and DIR The counter is synchronous with the clock CK and it is initialized by an asynchronous Reset input In particular the input DIR defines the count direction up or down and the input EN enables the count operation that will take place on every clock positive edge 61 In Fig 50b the assignment continues with a suggestion to download an ASM diagram template to be guided toward the solution If the student use this option he or she could concentrate better on the argument instead of build from scratch the solution bothering with the simulator details and spending time in less useful and distracting tasks The option is not mandatory however and the student can freely activate the simulator without using the template Assistant DEEDS Laboratory Session Back Forward Menu You can use the ASM diagram template provided where you ll find the state variables X Y and Z already detined as well as the outputs QC OB and QA and the mputs DIR and EN In the template the codes of five states have been also detined At the reset the counter should
48. Interrupt Request Debugger command to simulate the effect of a Interrupt Request Partial Timer Reset Debugger command to reset the partial clock cycle 95 or Code mcB Options View Help Switch to Deeds Ctrli F7 Switch to Last FF Switch to Next ShiFt F7 Fig 96 The d McE Deeds menu Switch to Deeds Command to switch focus to the Deeds main browser Switch to Last Command to switch to the tool that was last on top before switching to the currently opened instance of the Switch to Next Command to switch focus among all active Deeds applications in order of activation 96 Options Menu View Help e Configuration Fig 97 The d McE Options menu Configuration Command to change the application configuration disabled in this version 97 View Menu Assembler Oukput Ctri A v Directory browser Ctrl B Simbol Table Registers Object Code Fig 98 The View menu Assembler Output Command to hide show the Assembler Output message list at bottom Directory browser Commands to hide show the Directory Browser to the left of main window Symbol Table Command to hide or show the assembler Symbol Table window Fig 99 Simbol Table Label WHEELS VELREF EVAL TIME VEL 0 INTERRUPT UPDATE LOOF OUTPUT RE INIT Fig 99 The Symbol
49. L 0 LOOF LD HL liL Assembling file INS Fig 72 The assembler code editor of the Micro Computer Emulator d McE The integrated source code editor enables user to enter assembly programs and a simple command permits to assemble link and load them in the emulated system memory 78 The execution of the programs can be run step by step in the interactive debugger Fig 73 In the debugger as in professional tools the user can evaluate the contents of all the structures involved in the hardware software system by stepping the execution of the programs Miro Computer sed File Edt Project Emulation Deeds Options View Help Board Editor Debugger mm mu F i gt il ti Clock Cieles _ U Last B m Animate Pauze Step Step Animation Speed HL F artial i Reset Int REGISTERS T Bit 15 IX 0 0 0 0 0 0 079 090609506 ono 9909 9 9 9 9 9 0 8 9 8 Ho ooo 93 9030 00100 x X oon 5010010000000 foo de 232252 5020 8 0 0 0 0 jl PC _ Gu VF MEMORY 0 00 00 0 9 0 00 onis Ep mmm amm foo f 0020
50. LA D SLAE SLAH SLA L SLA HL SLA A SRA B SRA C SRA D SRA E SRA H SRA L SRA HL SRA A SRL B SRL C SRL D SRL E SRL H SRL L SRL HL SRL A BIT 0 B BIT 0 C BIT 0 D BIT 0 E BIT 0 H BIT 0 L BIT 0 HL BIT 0 A BIT 1 B BIT 1 C BIT 1 D 1 1 H BIT 1 L BIT 1 HL BIT 1 A BIT 2 B BIT 2 C BIT 2 D BIT 2 E BIT 2 H BIT 2 L BIT 2 HL BIT 2 A BIT 3 B BIT 3 C BIT 3 D BIT 3 E BIT 3 H BIT 3 L BIT 3 HL BIT 3 A BIT 4 B BIT 4 C BIT 4 D BIT 4 E BIT 4 H CB65 CB66 CB67 CB68 CB69 CB6A CB6B CB6C CB6D CB6E CB6F CB70 CB71 CB72 CB73 CB74 CB75 CB76 CB77 CB78 CB79 CB7A CB7B CB7C CB7D CB7E CB7F CB80 CB81 CB82 CB83 CB84 CB85 CB86 CB87 CB88 CB89 CB8A CB8B CB8C CB8D CB8E CB8F CB90 CB91 CB92 CB93 CB94 CB95 CB96 CB97 CB98 CB99 CB9A CB9B CB9C CB9D CB9E CB9F CBA0 BIT 4 L BIT 4 HL 4 5 5 5 D 5 5 5 L 5 HL 5 6 6 6 D BIT 6 E BIT 6 H 6 L BIT 6 HL BIT 6 A BIT 7 B BIT 7 C BIT 7 D BIT 7 E BIT 7 H BIT 7 L BIT 7 HL BIT 7 A RES 0 B RES 0 C RES 0 D RESO E RES 0 H RESO L RES 0 HL RES 0 A RES 1 B RES 1 C RES 1 D RES 1 RES 1 RES 1 L RES 1 HL RES 1 RES 2 RES 2 RES 2 D RES 2 RES 2 H RES 2 L
51. LD H L LD H HL LDH A LD L B LD L C LD L D LD L E LD L H LD L L LD L HL LDL A LD HL B LD HL C LD HL D LD HL E LD HL H LD HL L HALT LD HL A LD A B LDA C LD A D LDA E LD LD A L LD A HL LDA A ADD A B ADD A C ADD A D ADD A E ADD A H ADD A L ADD A HL ADDA A ADC A B ADC A C ADC A D ADC A E ADC A H ADC A L ADC A HL ADC A A SUB B SUB C SUB D SUB E SUB SUB L SUB HL SUB A SBC A B SBCA C SBC A D SBC A E SBC A H SBC A L SBC A HL SBCA A AND B AND C AND D AND E AND H AND L AND HL AND A XOR B XOR C XOR D XOR E XOR H XOR L XOR HL XOR A 112 OR B OR C OR D OR E OR H ORL OR HL ORA CP B CPC CPD CPE CP L CP HL CP A RET NZ POP BC JP NZ nn JP nn CALL NZ nn PUSH BC ADDA n RST Oh RET Z RET JP Z nn RLC B RLC C RLC D RLC E RLC H RLCL RLC HL RLCA RRC B RRC C RRC D RRC E RRC H RRCL RRC HL RRC A RLB RLC RLD RLE RLH RLL RL HL RLA RR RRC RRD RRE RRH RRL RR HL RR A SLA B CB21 CB22 CB23 CB24 CB25 CB26 CB27 CB28 CB29 CB2A CB2B CB2C CB2D CB2E CB2F CB38 CB39 CB3A CB3B CB3C CB3D CB3F CB40 CB41 CB42 CB43 CB44 CB45 CB46 CB47 CB48 CB49 CB4A CB4B CB4C CB4D CB4E CB4F CB50 CB51 CB52 CB53 CB54 CB55 CB56 CB57 CB58 CB59 CB5A CB5B CB5C CB5D CB5E CB5F CB60 CB61 CB62 CB63 CB64 SLAC S
52. Micro Computer Emulator 79 A simple example In the following screen shot Fig 75 you can see an assembly program edited in the d McE code editor The code editor supports syntax highlighting The code of the DMC8 microprocessor assembly is mainly the same of the well known Z80 CPU processor but reduced of some instructions to simplify and linearize the instruction set Micro Computer Emulator Pee File Edit Project Emulation 2 22 Options View Help Board Editor Debugger Dae o t Code mes gt D Interrupt handler routine DeedsProject ORG 0038h Deeds INTERRUFT PUSH rsave all used register onto the PUSH BC PUSH DE PUSH HL Files mca LD TIME control if a second has finished DEC LD TIME JP Nz FINE INT rif it is not it doesn t update VELREF LD B ESAME 06 02 2004 tr Assembling file First pass Second pass Code assembled with success ce o ee 7 Fig 75 The editing phase of an assembly program in the d McE The microprocessor architecture is documented in the help system This presents topics to the user as a multi page window Fig 76 The instruction set is documented on line to help the user in writing the assembly programs examples in Fig 77 and 78 80 55 DMCB Short Guide Subprogram Call and Return Shift and Rotate Bit Input Output Alfabetical O
53. P CB5D 3 L HL A6 AND HL CB66 BIT 4 HL DDBEd CP IX d DDA6d IX d DDCB d 66 BIT 4 IX d FDBEd FDA6d d FDCB d 66 4 d 7 CB67 BIT 4 A B8 CPB AO AND B CB60 BIT 4 B B9 CPC A1 AND C CB61 BIT 4 BA CP D A2 AND D CB62 BIT 4 D BB CP E A3 AND E CB63 BIT 4 E BC CP H A4 AND H CB64 BIT 4 H BD CP L A5 AND L CB65 BIT 4 L FE n E6 n AND n CB6E BIT 5 HL 2F CPL CB46 BIT 0 HL DDCB d 6E BIT 5 IX d 35 DEC HL DDCB d 46 BIT 0 IX d FDCB d 6E BIT 5 IY d DD35d DEC d 108 DDE9 FDE9 DA FAnn D2nn C3nn C2nn F2nn EAnn E2nn CAnn 12 77 70 71 72 73 DEC IY d DEC A DEC B DEC BC DEC C DEC D DEC DE DEC E DEC H DEC HL DEC IX DEC DECL DEC SP INC HL INC IX d INC IY d INC A INC B INC BC INC C INC D INC DE INC E INC H INC HL INC IX INC IY INCL INC SP JP HL JP IX JP IY JP C nn JP M nn JP NC nn JP nn JP NZ nn JP P nn JP PE nn JP PO nn JP Z nn LD BC A LD DE A LD HL A LD HL B LD HL C LD HL D LD HL E 74 75 36 n DD77 d DD70 d DD71 d DD72 d DD73 d DD74 d DD75 d DD36dn FD77 d FD70 d FD71 d FD72 d FD73 d FD74 d FD75d FD36 dn 32nn ED43 nn ED53 nn 22nn ED63nn DD22nn FD22nn ED73nn 0A 1A DD7E d FD7E d 3Ann 78 79 7B 7C 7D 3E n 46 DD46
54. PU registers the I O ports Fig 81 A list of laboratory assignments opened in the Deeds main browser Fig 82a The specific laboratory assignment opened in the Assistant browser first part Fig 82b The specific laboratory assignment opened in the Assistant browser second part Fig 83 The Micro Computer Emulator opened by a click on the web page The editor shows the trace of the solution automatically downloaded from the courseware site Fig 84 The program under test in the interactive debugger of the d McE a Warning has be sent to the user Fig 85 Port addresses can be modified in the I O Ports Address Decoding dialog window Fig 86 Port addresses can be modified by a mouse click on the simulated on board dip 55 56 57 57 58 switches Fig 87 The student can download the report template to speed up its compilation and delivering Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig The simple template provided the web page that the student can download A partial view of a final student report The d McE File menu The d McE Edit menu The d McE Project menu The Source Info dialog window The I O Ports Address Decoding dialog window The d McE Emulation menu The d McE Deeds menu The d McE Options menu The d McE View menu The Symbol Table window Compact View or Extended View 100 The d M
55. Sreen Shots page of the Deeds web site Fig 5 The download page in the Deeds web site Fig 6 the learning material page available in the Deeds web site opened in the main browser Fig 7 The main browser File menu Fig 8 The Open Page dialog window Fig 9 The main browser Run menu Fig 10 The main browser Tools menu Fig 11 The main browser Options menu Fig 12 The main browser Help menu Fig 13 The Assistant opened aside of the main browser showing a page with a problem assignment Fig 14 The Assistant main menu appended to the toolbar Fig 16 The circuit editor of the Digital Circuit Simulator d DcS Fig 17a The drawing phase of the digital circuit editor the insertion of components Fig 17b The next phase of the work the connection of components using wires Fig 17c The animation at work the user switches the Inputs and the circuit shows changes on the Outputs Fig 18 The Timing Diagram simulation window Fig 19 The timing simulation results displayed in the Timing Diagram window Fig 20 A list of laboratory assignments opened in the Deeds main browser Fig 21 The specific laboratory assignment opened in the Assistant browser Fig 22 The Digital Circuit Simulator opened by a click on the web page The circuit template has been automatically downloaded from the courseware site Fig 23 The timing simulation of the circuit once completed by the student Fig 24 Th
56. Table window Registers Hex View Object Code Dec View Command to change the user numerical format of the registers Hexadecimal or Decimal Object Code Registers Object Code 2 Compact View u Extended View Command to change the display mode of the Object Code pane of the Debugger Compact View or Extended View 98 Help Menu Index HSH DMC8 Short Guide Ctrl F1 License Agreement version Motes About Fig 100 The Help menu Index Command to open the d McE Help System disabled in this version DMC8 Short Guide Command to open the DMC8 short programming guide License Agreement Command to display the Licence Agreement Version Notes Command to display the Deeds Version Notes file Command to display the d McE splash window dialog 99 8 Instruction Set In this chapter all the instructions implemented in the D C8 microprocessor are listed Load Instructions 8 bits operon s z H PNN 72020 commens _ Mnemonic Operation S Z H PVN C 76 543 210 Bytes Cycles Cycles Comments ers LD r i r i DUC B me ew pP ss 011 E LD IX d r IX d os 100 H r 110 101 L o 111 A 01 r 110 o we me u 110 r d gt Mass i 01110 r ee L kus IX d n 11 011 10
57. art The theme continue with the guidelines for a possible solution as the student at the moment of this laboratory session faces this kind of problems for the first time Fig 82b The Deeds let to get a trace of the solution with a simple click on the specific link It will be automatically downloaded and opened in the source code editor of the d McE Fig 83 As usual this approach let the user simplify the operations necessary to start with the true work 86 Micro Computer Emulator este usum temmet File Edit Project Emulation Deeds Options view Help Board Editor Debuager Dela Be o G m E d D 01060 1 Authors znamel znamez SERIN EQU cp input parallel port SEROUT BO routput parallel port Files ORG 0000k collegamento al RESET hardware JP 0100h Code 9 ORG oooh JESAME_06_02_2004 rr lt iniz STACK P INTER CALL INIT CALL zreceiver subprogram CALL lt encription subprogram CALL ztransmitter subprogram JP LOOP initialization clear variables and output port Fig 83 The Micro Computer Emulator opened by a click on the web page The editor shows the trace of the solution automatically downloaded from the courseware site Note the icon visible on top of the editor page In this case the symbol indicates that the file has been downloaded from the web When the user will save it on the local disk this little
58. assemble operation It shows the Source Info dialog window Fig 93 Source Into Assembled lines structions Labels Fig 93 The Source Info dialog window I O Ports Address Decoding Command to display the I O Ports Address Decoding dialog window that lets the user set the hardware addresses of the Input Output ports Fig 94 VO Ports Address Decoding Input Port Address Addresses In lt IB jor joz ID os jos EL Hex Dec Output Port Address ok Fig 94 The I O Ports Address Decoding dialog window 94 Emulation Menu sm Deeds Options view Animate B step F8 Step Over Ctrl F8 Reset Board 2 Interrupt Request ae Partial Timer Reset Fig 95 The d McE Emulation menu Debugger command to Animate the execution of the program Debugger command to pause the Animation Debugger command to execute one instruction the one pointed by the Program Counter Step Over This debugger command has the same effect of the previous Step command except for a particular case the execution of the CALL When the Program Counter points to a CALL instruction the Step Over command forces the execution of the program until the corresponding RET return instruction is found Reset Board Debugger command to simulate the effect of a Hardware Reset
59. at Command to insert a NOT component And 2 inputs gt NANDs 4 Y J gt And 3 inputs i NORs J And 4 inputs 3 gt k Commands to insert AND components x 1 Mand 2 inputs it j gt ORs T NORs inputs gt ExoRs kid gt 4 inputs Commands to insert NAND components gt NORs EXORs k Decoders gt Cr 2 inputs z Gr 3 inputs Or 4 inputs Commands to insert OR components 41 P Nor 2 inputs Mor 3 inputs Jj Mor 14 inputs Decoders Encoders d Decoders Encoders d Multiplexers h Decoders Decoders Decoder 2 gt 4 with enable Encoders Multiplexers Decoder 3 gt 8 with enable Demultiplexers Decoder 3 gt 81138 like Encoders B Encoders ht Multiplexers Multiplexers Multiplexers Demultiplexers Fr Flip Flop Registers Commands to insert Multiplexer components Demultiplexers Demultiplexers KF Demultiplexer 1 gt 2 FI Flip Flop Registers h Counters h K Demultiplexer 1 gt 4 K Demultiplexer 1 8 Commands to insert Demultiplexer components 42 Flip Flop Flip Flop Flip Flop D Registers d Seater Flip Flop JK p e E
60. ata processor 10 Design of serial_programmable pulse generator 2004 05 10 Assignments File AMD D eedsPrajecrwebsiteYWerProeDeedsY 0040 Re Thinking 5Svnc Car Electronic System Design 1 INF Labe 2 Fig 49 A list of laboratory assignments with use of d FsM opened in the Deeds main browser The student executes the assignment 8 1 Design of a synchronous mod 5 up down counter As in the example related to the d DcS with a click of the user on the link the specific assignment will be opened in the Assistant Fig 50a and 50b 60 Assistant DEEDS Laboratory Session gt B Back Forward Menu Design of a synchronous mod S up down counter Design a synchronous mod 5 up down counter using the Finite state IMachme Simulator 4 5 The counter should generate cyclically the sequence from to 1007 when counting up or from 100 to O00 when Conning CK EH As you see m the figure The counter has a clock and generates three outputs QC MSE QE and OA LSB The count operation is synchronous with the clock CE _ The input EN i equal to L enables the count on every clock positive edge when itis the counter does not respond the clock and the output remaims unchanged The input DIR defines the count direction 0 down 1 up The Reset when activated resets asprchronausiy all the count outputs
61. cE Help menu Preface Deeds is the acronym of Digital Electronics Education and Design Suite but as deeds mean I m not sure if they will be good or bad just like The Deeds of Gallant Knights that the splash form recalls The Deeds of Gallant Knights from a picture of G David XVI Century Paris Musee de l Armee Introduction Deeds is conceived as a suite of simulators tools and learning material for Digital Electronics Deeds helps student acquiring theoretical foundations analysis capabilities ability to solve problems all over the subject topics practical synthesis and design skills Its approach is characterised by the learning by doing concept Deeds Digital Electronics Education and Design Suite It covers the following areas of digital electronics Combinational logic networks from simple gates to decoders encoders multiplexers and demultiplexers Sequential logic networks from simple flip flops to registers and counters Finite state machine design Micro computer programming at assembly level and interfacing Major tools that Deeds includes are An HTML main browser to navigate in Internet where students will find lessons exercises and laboratory assignments An HTML assistant browser that assists students in their work A schematic digital circuit editor with component data sheet support An interactive circuit animator to experiment with components and simple ne
62. d 11 101 101 ED 2 4 15 CY 01 ssO 010 00 1 001 oca E qt oot t 7 jemon 20 7 j 00 100 011 23 ques mm 2 FT 00 100 011 23 El YS quet qt 7 0 77 Jen 2 o o 00 101 011 2B em Nem muon 2 o 00 101 011 2B I The V symbol in the P V flag column indicates that the P V flag contains the overflow of the operation Ss means any of the registers BC DE HL SP Pp means any of the registers BC DE IX SP Rr means any of the registers BC DE IY SP 16 bit additions are performed by first adding the two low order eight bits and then the two high order eight bits ndicates the flag is affected by the 16 bit result of the operation ndicates the flag is affected by the 8 bit addition of the high order eight bits CY means the carry flip flop Flag Notation flag is not affected 0 flag is reset 1 flag is set flag is set according to the result of the operation CPU Control Instructions Symbolic Flags Opcode Clock Mnemonic Operation 2 A 76 543 210 Bytes Odes cas Comments CCF X 00 111 111 1 Complement CY CY carry flag IW amr The V symbol in the P V flag column indicates that the P V flag contains the overflow of the operation Similarly the P symbol indicates parity Nointerrupts are issued directly after a DI or El CY means the carry flip flop Flag Notation
63. d FD46 d LD HL H LD HL L LD HL n LD IX d A LD IX d B LD IX d C LD IX d D LD IX d E LD IX d H LD IX d L LD IX d n LD IY d A LD IY d B LD IY d C LD IY d D LD IY d E LD IY d H LD IY d L LD IY d n LD nn A LD nn BC LD nn DE LD nn HL LD nn HL LD nn IX LD nn IY LD nn SP LD A BC LD A DE LD A HL LD A IX d LD A IY d LD A nn LD A A LD A B LD A C LD A D LDA E LD A H LD A L LDA n LD B HL LD B IX d LD B IY 4 d LDB A LD B B LDB C LD B D LDB E LD B H LDB L LD B n LD BC nn LD BC nn LD C HL LD C IX d LD C IY d LDC A LD C B LD C C 67 60 61 62 63 64 65 26n 2Ann 21nn DD2A nn DD21 nn FD2A FD21 DD6E d FD6E d LD C D LDC E LD C H LDC L LD C n LD D HL LD D IX d LD D IY 4 d LDD A LDD B LDD C LDD D LDD E LD D H LDD L LDD n LD DE nn LD DE nn LD E HL LD E IX d LD E IY d LD E A LD E B LD E C LD E D LD E E LD E H LD E L LD E LD H HL LD H IX d LD H IY d LDH A LDH B LDH C LDH D LDH E LD H H LDH L LDH n LD HL nn LD HL nn LD IX nn LD IX nn LD IY nn LD IY nn LD L HL LD L IX d LD L IY d LDL A LD L B LDL C LD L D LDL E LD L H LDL L LDL n LD SP nn LD SP HL
64. d FDAE d FD56 d FD5E d FD66 d FD6E d FD70 d FD71 d FD72 d FD73 d FD74 d FD75 d FD77 d FD7E d FD86 d FD8E d FD96 d FD9E d FDA6 d FDAE d FDB6 d FDBE d FDCB d 06 FDCB d OE FDCB d 16 FDCB d 1E FDCB d 26 FDCB d 2E FDCB d 3E FDCB d 46 FDCB d 4E FDCB d 56 FDCB d 5E FDCB d 66 FDCB d 6E FDCB d 76 FDCB d 7E FDCB d 86 FDCB d 8E FDCB d 96 FDCB d 9E FDCB d A6 FDCB d AE FDCB d B6 FDCB d BE FDCB d C6 FDCB d CE FDCB d D6 ADD IY BC ADD IY DE LD IY nn LD nn IY INC IY ADD IY IY LD IY nn DEC IY INC IY d DEC IY d LD IY d n ADD IY SP LD B IY d LD C IY d LD D IY d LD E IY d LD H IY d LD L IY d LD IY B LD IY d C LD IY d D LD IY E LD IY d H LD IY d L LD IY d A LD A IY d ADD IY d ADC A IY d SUB IY d SBC A IY d AND IY d XOR IY d OR IY d CP IY d RLC IY d RRC IY d RL IY d RR IY d SLA IY d SRA IY d SRL IY d BIT 0 IY d 1 IY d BIT 2 IY d BIT 3 IY d BIT 4 IY d BIT 5 IY d BIT 6 IY d BIT 7 IY d RES 0 IY d RES 1 IY d RES 2 IY d RES 3 IY d RES 4 IY d RES 5 IY d RES 6 IY d RES 7 IY d SET 0 IY d SET 1 IY d SET 2 IY d FDCB d DE SET 3 IY d FDCB d E6 SET 4 IY d FDCB d EE SET 5 IY d FDCB d F6 SET 6 IY FDCB d FE SET
65. d with this list The symbol that is displayed on the left of the file name means that The file has been stored by the user on the local disk or network Q The file has been downloaded from a web site but it has not been saved yet on the local disk or network fo The file has been loaded from a local courseware where it is read only and it has not been saved yet on the local disk or network Standard command to close the application 92 Undo Cut Copy Delete Select All Find Ctrl V Ctrl Del Select All Fig 91 The Edit menu Command to undo the previous operation command temporary inhibited Command to cut the selected piece of text and put it onto the clipboard Command to copy the selected piece of text onto the clipboard Command to paste the text from the clipboard Command to delete the selected piece of text Command to select all the text in the editor Standard command to search strings in the text file opened in the editor 93 Project Menu Em ulator Codeine ms Emulation Deeds Options Assemble Ctr F3 i Informations Ports Address Decoding Fig 92 The d McE Project menu Command to compile assemble the assembly source file opened in the editor Informations Command to show statistical information about the previous compile
66. d the file downloaded in it as in Fig 22 BI Digital Circuit Simulator 040_1 BAHA Fie Edit View Tools Circuit Simulation Deeds Options Help a C Se po P m bD D D Pe FO B Ble v 22 73 7 Fig 22 The Digital Circuit Simulator opened by a click on the web page The circuit template has been automatically downloaded from the courseware site The assignment suggests now to complete the drawing and also to activate a few useful simulator commands directly from the web page with a simple click Once completed the schematic also the simulation can be started directly from the Deeds web page In Fig 23 you can see the results expected from the student work File Edit View Tools Circuit Simulation Deeds Options Help Dp m m amp me 4 D D 2 De 3 g Eh D HAE F mu uds Diagram Miming Interval Simulabon mode Je Tm PN 9 80 30 40 20 160 0 an 30 100 110 120 130 140 150 160 militia heen ae ru dard Parada e Para Ta Por red E In Duti SS 44 4 lt lt m gt F hh d 4 pixelsins Fig 23 The timing simulation of the circuit once completed by the student 32 Now is the time for the student to compile and deliver a good report In the Deeds assignm
67. driven by the Deeds browser when the user clicks on an active link to open a file e he warning messages of the simulator when needed are displayed in a list at the bottom of the main window if in animation mode or at the bottom of the timing diagram window if in timing mode In this way the messages results more kind to the user than before when each message was displayed by a dialog box e Now the last status bar message can be displayed moving the mouse over the bar itself In the Timing Diagram the highlighting of the transitions of a specific signal has been enhanced By clicking the button corresponding to a specific signal you can toggle among four highlight modes a vertical lines on 0 1 transitions only b vertical lines on 1 0 transitions only c vertical line on all transition d no highlight d FsM e Drag and Drop of FSM files from the file manager has been enabled 10 05 2002 d DcS e Finite State Machine components when not completed cann t be loaded in the d DcS This is OK but under some circumstances the user message explaining that the file wasn t completed didn t appear This problem has been fixed 119 d FsM The Print command has been fixed now it is possible to print on paper ASM diagrams Some file save file open bugs has been fixed The Save file commands have been completed with automatic file backup generation for instance before saving file name fsm if a pr
68. ds to control ToolBars appearance Standard ToolBar Command to hide or show the Standard ToolBar the upper one Component ToolBar Command to hide or show the Component ToolBar the lower one Show and Dock All ToolBars Command to show and dock in all the ToolBars Dockable ToolBars Command to enable or disable the docking modality of the ToolBars Status Bar Command to hide or show the Status Bar 46 Help Menu Index he Data Sheets License Agreement Version Motes Abouk Fig 34 The d DcS Help menu Index Command to open the d DcS Help System disabled in this version Data sheets Command to open the Data Sheets help system disabled in this version License Agreement Command to display the Licence Agreement Version Notes Command to display the Deeds Version Notes file Command to display the d Dcs splash window dialog 47 Deeds Finite State Machine Simulator d FsM TT This image from the Tapestry Bayeux Bayeux Cathedral France 48 Introduction The Finite State Machine Simulator d FS M allows graphical editing and simulation of Finite State Machines components using the ASM Algorithmic State Machine paradigm fig 35 The tool allows the local functional simulation of the finite state machines designed by the user with runtime display of the relations between state and timing evolution fig 36 Finite State Mac
69. e the state code 000 here and the active outputs none in the example The check box on the left imposes this one as Reset State The user is asked to complete the ASM diagram and using the timing simulation integrated in the d FsM to verify the correct sequence of output values and state codes The user will start drawing adding path lines and diamonds as required by the requested functionality 63 In Fig 54 you see the Property Window as it appears when the user select a condition block The user can change the orientation of the diamond connections and the condition chosen among the input variables DIR in this example E File Edit View simulation Window Deeds Help o 28 bense j amp amp cooilw HEH E 4 128 37 Modified Fig 54 property window displaying the properties of a condition block Once the student have finished the design the next step required is to verify the behaviour of the counter with the timing simulator of the d FsM itself Fig 55 ga Finite State Machine Simulator Lab_08_es_01_full fsm File Edit View Simulation Window Deeds Help 4 114 4 Fig 55 The finished ASM diagram its timing simulation in the d FsM 64 When the user clicks on the Clock button the internal simulator evaluates next state and outputs according to the current input values and displays the resul
70. e or when the coding is finished he or she can launch the Assembler module using the tool bar button C In Fig 9 an example of assembling report in case of error is shown a unknown label was found and the offending line is pointed by a little symbol Computer Emulator Code File Edit Project Emulation Deeds Options wiew Help Board Editor Debugger Da ki m m o e ml PUSH save all used register onto the PUSH BC EC PUSH DE PUSH HL DeedsProject gt Deeds HTML 25 Circuits LD TIME control if a second has finished uus DEC MCB Files mc8 AD u s JP NZ FINE INT Code mca IN VELREF ESAME 06 2 2004 rr LD B 4t Ls iot FE morsi t updlabe Assembling file cCode mca First pass Second pass Row 20 gt 22 Unknow Label or Incorrect Hex value Line 20 Col 1 Modified CAPS IN 5 NJ Fig 79 The Assembler module reports an error the source code 82 When the code has been cleaned and no syntax error is reported the program can be tested in the debugger Fig 80 s Micro Computer Emulator aed File Edt Project Emulation Deeds Options View Board Editor Debugger II Ll i 339 Last A i Animate Fause Step Step Over Tu Partial 333 11 Reset Int REGISTERS 2 MEMORY T 09599999 F 990x909 9 F FF FF FF FF F
71. e state machine module and the microcomputer board emulator can work simultaneously in the simulation of a system where standard digital components can be controlled by a state machines as it is the case in contemporary digital design Obviously the modules can be used independently to test separately the system s parts The student can complete its work programming at assembly level a microcomputer board Students use Deeds to download the assignment from a web page The assignment consists of a functional description and a set of specification of the system that students must design The approach is meant to replicate the features of a professional environment within the guidelines suggested by the educational purposes Project development phases are guided by help and instructions supplied through the Assistant Browser Such instructions can be given step by step or by simple guidelines the use of the simulation tools can be more or less guided by the text of the assignment to left creativity and fantasy to the user initiative In Fig 1 an example of laboratory student report displayed in the main browser gt Deeds http netpro evtek fifpdc pde centreB05 group3128 topic2910 version19053 a SEE File Run Tools Options Help MG 2 o m gt Stop Refresh d MsF d McE Home Open Back Forward d SrB Commenti Finali Mostra 42 7 va I EX 3 Schematic T
72. e student can download the report template to speed up its compilation and delivering Fig 25 The report template for this laboratory assignment Fig 26a The d DcS File menu Fig 26b The Paper Setup dialog window Fig 27 The d DcS Edit menu Fig 28 The d DcS View menu Fig 29 The d DcS Tools menu Fig 30 The d DcS Circuit menu Fig 31 The d DcS Simulation menu Fig 32 The d DcS Deeds menu Fig 33 The d DcS Options menu Fig 34 The d DcS Help menu Fig 35 The ASM editor of the Finite State Machine Simulator d FsM Fig 36 The ASM editor of the Finite State Machine Simulator d FsM Fig 37 A simple Algorithmic State Machine ASM diagram Fig 38a State Block Fig 38b Decision Block Fig 38c Conditional Output Block Fig 39a The State Diagram representation of a SR flip flop Fig 39b The ASM Chart representation of a SR flip flop Fig 40a ASM chart and State diagram representing the same algorithm the FSM waits in the state a until the x input goes to one Fig 40b Another example of ASM chart and State diagram representing the same algorithm Fig 41 The state transition table of the example above as generated by the d FsM Fig 42 The VHDL equivalent of the ASM diagram in Fig 37 as generated by the d FsM Page 11 12 Fig 43 In this example a component designed with the d FsM has been imported in the d DcS Fig 44a The student inserts state blocks
73. ectly a URL address or browse the local network or disk The chosen web page can be set as Home Page A short history of previously opened pages is maintained Page M Add Delete Browse Cancel Help Fig 8 The Open Page dialog window 16 Back Forward Refresh Print Preview Print Page Exit Standard browsing command to return to the previous opened page Standard browsing command to return to the next opened page after using the Back command Standard browsing command to stop the download of the current page Standard browsing command to reload the currently opened page Standard command to preview the current page before printing Standard command to print the current page Standard command to close the Assistant 17 2 2 Deeds Deeds Learning Materials Fie 14 Tools Options Help GP Assistant Browser Micro Computer Board Emulator Es Student Report Builder Fig 9 The main browser menu Assistant Browser Command to open manually an instance of the Assistant Browser Digital Circuit Simulator Command to open manually an instance of the Digital Circuit Simulator d DcS Finite State Machine Designer Command to open manually an instance of the Finite State Machine Designer Simulator d FsM Micro Computer Board Emulator Command to open manually an instance of the Micro Computer Board Emulator d MCE 18 Tools Menu Deed
74. els This class of design is called a Finite State Machine or just a state machine Modern digital circuit design is essentially based on Finite State Machines Design synthesis and documentation of a state machine require a formal approach Currently several design methods are employed based either on graphic tabular or textual representations of the algorithm underlying the state machine FSM description languages ASM charts The most common graphical methods currently in use to describe a FSM are Moore and Mealy State Diagrams In our simulator we use the ASM Algorithmic State Machine method instead A typical ASM chart or diagram resembles flowchart notation Fig 37 even if they are not the same thing It describes state flow the output functions and the next state functions of a state machine ASM charts have the same function as Moore and Mealy State Diagrams they describe the behaviour of finite state machines so that it is clearly understandable for the designer and at the same time ASM charts support a direct translation into a hardware realization of the control algorithm Fig 37 A simple Algorithmic State Machine ASM diagram 50 An ASM chart is composed of three basic elements the State rectangular box the Decision Block diamond and the Conditional Output Box A set composed of one state box decision blocks and conditional output blocks is named ASM Block An ASM Block has one entry point but ma
75. en lines have been fixed The algorithm that automatically assigns the code to a newly created state has been modified Now it assigns to the state the first not used code checking it from the lowest code available If no state is deleted this mode of operation is equivalent to assign codes in up order If a state is deleted its code will be re used If a code value is no more available the user when trying to insert a new state block is prompted to add another variable to the state register During insertion moving or editing of ASM blocks and lines if the user presses the escape key the current operation is automatically aborted The delete key now acts on the key down instead of the key up conforming its behaviour to all the Windows application In the IN OUT dialog pressing the Return key generates no more a tedious beep also in the same dialog it is now possible to edit as expected the eighth Input or Output entry Now it is possible to design a FSM having no input signal for instance a simple binary counter d DcS In the previous version a click on the Cancel button of the message dialog that appears when you want to create a new Finite State Machine hanged the d DcS The problem has been fixed 13 05 2003 d FsM Cascade connection of more than two conditional blocks do not hang the program anymore the bug has been fixed Now the program seems also to process correctly conditi
76. ent page a link is prepared to download and edit a report template file Fig 24 2 Deeds Electronic System Design 1 INF Laboratory Sessions File Run Tools Options Help a 9 o S de Home Open Back Forvard stop Refesh Assistant d MsF d McE Analysis or simple logic gates 2 5inulation of combinational networks 2004 03 08 esigmments 2 1 Analysis of a multiplexer 2 to 1 22 Analysis of a demultiplexer 1 to 2 23 Analysis of a simplified shared lme communication channel 3 Analysis synthesis and simulation of combinational networks a Assignments Eeport Download 2004 03 15 3 1 Analysis of a multi level logic network 0060 5 2 Design of a programmable logic gate OOO FO 3 3 Synthesis of a boolean function OUR 4 Analysis synthesis and simulation of combinational networks D Electranic System Design 1 INF Laborat gt Fig 24 The student can download the report template to speed up its compilation and delivering This has been previewed to uniform the report styles making easier the teacher task especially when the number of student is valuable But the availability of a report template is very useful also to the student because it saves a lot of time speeding up the student work and leaving more time to concentrate on the arguments to learn 33 This is the report template for this laboratory assignment Fig 25 Microsoft Word Gy 02
77. eport template to speed up its compilation and delivering Fig 58 The report template for this laboratory assignment assignment Fig 59 The Timing Diagram window of the d FsM Fig 60 The ASM Table window Fig 61 The d FsM File menu Fig 62 The VHDL code window Fig 63 The Paper Setup dialog window Fig 64 The d FsM Edit menu Fig 65 The three pages of the Input Output dialog window used to define inputs outputs and state variables Fig 66 The d FsM View menu Fig 67 The four pages of Property Window used to define properties of state conditional and conditional output blocks Fig 68 The d FsM Simulation menu Fig 69 The d FsM Window menu Fig 70 The d FsM Deeds menu Fig 71 The d FsM Fig 72 The assembler code editor of the Micro Computer Emulator d McE Fig 73 The assembler level debugger of the Micro Computer Emulator Fig 4 The emulated board as represented in the Micro Computer Emulator Fig 75 The editing phase of an assembly program in the d McE Fig 76 The DMC8 architecture as shown by the help system Fig 7 An example of the on line instruction set documentation the Arithmetic and Logic instructions Fig 78 Another example of the on line instruction set documentation the Shift and Rotate instructions Fig 79 The Assembler module reports an error in the source code Fig 80 The Debugger module shows the program under test the memory the C
78. errupt handling Download 5004 01 20 Assignment Eeport 5 1 Introduction to parallel interfacing and interrupt handling ama di i E Electronic System Design 2 EC Lak 2 Fig 81 A list of laboratory assignments opened in the Deeds main browser With a click on the link the assignment will open in the Assistant see Fig 82a and 82b 84 Assistant DEEDS l aboratony Sesmioni microprocessor based system receives ASCH chars trom an asynchronous serial line crvptographs and re transmits them into another asynchronous serial Only parallel ports are available in the system hardware so it will be necessary to write a program that implements de senahsation and re senrialisation of the serial signals The standard format used here for asynchronous serial communication is specified as follows 1 One start bit high 2 data bits b7 b0 b7 ahead 5 One stop bit low 4 Bitrate of LOO bits per second Line Stet b7 be b5 b3 b2 b1 po Let s suppose to connect the mput serial SERIN to the bit of the parallel input port INPORT address 33h and the output serial line to the bit O of the parallel output port OL TPORT address 35h cryptographic operation is done simply by encoding the byte to be transmitted with the folowing formula Byte to be transmitied ASCH Char received EXOR Byte transmitted bef
79. eset and Clearinputs are normally used to imtialise the component at the beginning but they can be used also to Set or Reset the device asynchronously during the normal operations of the network SE 8 Aa a and elimmation of static hazards eds Sourc 1 1 Flip Hops irete Deeds Exercise n Fig 13 The Assistant opened aside of the main browser showing a page with a problem assignment All objects that a web page visualises can be made active For instance by clicking on the figure showing the schematics the Digital Circuit Simulator could be started and the circuit loaded ready to be tested this important feature will be described in detail later 22 Deeds Assistant browser Menu The Assistant menu has been reduced to the essential Fig 14 to simplify user operation Its graphical shape has been chosen to minimize the window size allowing the positioning of the Assistant aside of the simulation tool without occupy to much area of the screen Assistant DEEDS Laboratory Session BE Back Forward Menu HomePage Ans Open Page Deeds AE a Back Ctrl B Load the follo
80. est comparing simulation results with reasoning and theory concepts 29 A simple example of interaction between Deeds browsers and d DcS In Fig 20 a list of assignments is opened in the Deeds main browser Suppose that the student has to attend the assignment 2 1 Analysis of a demultiplexer 1 to 2 2 Dee ds Electronic System Design 1 INF Laboratory Sessions File Run Tools Options Help h Home Open Back Forward Stop Refresh Assistant d DcS d MsF Analysis or simple logic gates 2 Simulation of combinational networks Download 5004 03 09 Assignments Report 2 1 Analysis of a multiplexer 2 to 1 00020 2 1 Analysis of a demultiplexer 1 to 2 0048 2 3 Analysis of a simplified shared line communication channel 00050 3 Analysis synthesis and simulation of combinational networks Download a 2004 03 15 Assignments Report 3 1 Analysis of a multi level logic network 00060 3 1 Design of a programmable logic gate OOO 70 3 3 Synthesis of a boolean function 0050 4 Analysis synthesis and simulation of combinational networks Electronic System Design 1 INF Laborat 2 Fig 20 A list of laboratory assignments opened in the Deeds main browser Than he or she clicks on the link and the assignment will open in the Assistant see Fig 21 30 Assistant Pato ar 18221011 BAA ww 8 2 For ue Menu Deeds Analysis of a demultiplexer
81. evious version of the file exists this is renamed in name fsm The File Close command has been fixed it no more operational if no file is opened A known problem has not been fixed yet under some circumstances big ASM diagrams can show a sensible slowing of window repainting 22 03 2002 d DcS Now in the schematic editor labeling of the component is allowed only for Input Output components Attempt to label another kind of component results in a warning message on the status bar of the window You can set a negation bar over Input Output component labels placing a l on front of the label string The editor accepts also a leading or V but the 7 has to be preferred Moreover the negation bar is now displayed also on the signal name in the timing diagram window Drawing of Finite State Machine components has been partially fixed for those components placed with down and up orientation Before this fix displayed name of inputs and outputs were not the right ones Anyway we suggest to not use down and up orientation for Finite State Machines as name strings could easily overlap In the Timing Diagram now signal names are buttons evidenced by proper glyphs and colors and negated signal are displayed up lined You can highlight the transitions of a specific signal with a click on its name button in this way you can relate its transitions with the behaviour of the network under simulation If you c
82. f END case end process Slate Register 9 949924 Se REG process Ck Reset begin if Reset 0 then State state a elsif rising edge Ck then State Next State end if end process Outputs Combinational Logic OUTPUTS process State IIN begin Set output defaults OOUT lt 0 Set output as function of current state and input CASE State IS when state a gt if IIN 1 then OOUT 1 end if when state b if 0 then OOUT 1 end if END case end process END behave Fig 42 The VHDL equivalent of the ASM diagram in Fig 37 as generated by the d FsM 54 Learning FSM methods and problems The choice of a FSM description language is very important under the pedagogical point of view When first introducing the state machine we believe it is essential that the learner masters its fundamental concepts and develop an intuitive understanding of its behaviour At this level therefore we believe it is convenient to represent the machine algorithms with graphical methods in our case ASM charts When the student has gained familiarity with the design method and is ready to develop non standard digital structures described by a set of specifications switching to an hardware description language will develop his abstraction skills and introduce him to professional design The VHDL export feature has been developed to
83. he d FsM tool can export the finite state machine in VHDL format The command is available under the File menu item The user can view the VHDL code copy it on the clipboard or save it on a text file vhd The State at Reset is highlighted with a little diamond placed on the top left of the state block A starting state block is now accepted i e a state without a connection over it normally used as State at Reset or to drive the FSM through the unused states to a safe state The graphic editor has been radically modified Now blocks and lines can t be inserted or moved over other blocks and lines this is highlighted in the editor by displaying a red denied signal when appropriate The selection rectangle is now re sizable grip points are available to move the four vertexes with the mouse Now it is possible to show hide the drawing grid the command is under the View menu item In the editor the user can use the new Zoom commands they permit an easier editing of the ASM diagrams the commands are under the View menu item and on the toolbar 117 A new feature of the editor permits the controls of insertion moving and editing of lines This feature automatically breaks or links together the lines as they are inserted moved or edited The criteria are to connect line segments only on their vertexes In this way all the previous bugs related a lateral shaped connection betwe
84. hine Simulator mostro_01 fsm ASM State Chart File Edit View Simulation Window Help B amp B P kal Ad 13 64 Fig 35 The ASM editor of the Finite State Machine Simulator d FsM The components that the d FsM produces can be directly used in the d DcS and inserted into any digital circuit Also it can be exported in VHDL language A general purpose Finite State Machine software simulator helps the student to enhance his design skills and facilitates also the transition from the pedagogical to the professional field by introducing CAD methodologies 49 a amg Magram a m W J m R Fig 36 The ASM editor of the Finite State Machine Simulator d FsM Finite State Machines Finite State Machines FSM represent a model to design a class of digital sequential circuits A sequential system is a block whose outputs are a function not only of the current inputs but also of the previous ones In other words the logic has a sort of memory which records previous input history so it can be responded to in the present Given this definition sequential circuits would seem to require enormous amounts of memory to record all previous inputs However for any real logic design task the fact that previous input combinations result in only a finite number of distinct output classes reduces this memory requirement to manageable lev
85. icon will change in Once completed the assembly coding of the program the student will compile it If no syntax error has been found the verification of the program functionality can start Fig 84 87 I BE File Edit Pri Emulation Deeds Options view Help Editor Debugger pe T 5 a Animate Pause Step Step Over Animation Speed Partial 85 n il m r REGISTERS 4 RE Eik T T IFF sgsssssss gt Fv s sss B EET RES EST EG T m FF FF FF FF FF FF FF FF FF B 10 02 02 0 00 0 000 00 39 80 00 9 6 90 60 0 oo 0010 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF D oao o 00 E 9uoxououu DD2 FF FF FF FF FF FF FF FF FF FF FF FF FF FF I a WF FF FF FF ss ooo 070 00 Warning Es ler ler lee it FF FF FF IX 5920292 ys Unknown Address 35h 53d 5 3 F FF FF Instruction execution aborted and execution paused IY 0
86. imported in d DcS A simple example A simple example of interaction between Deeds browsers and d FsM The timing diagram window d FsM Menu Commands UU UU UY U U UY UU Deeds The Micro Computer Emulator d McE P 77 Introduction P 78 A simple example P 80 A simple example of interaction between Deeds browsers and d McE P 84 d McE Menu Commands P 91 DMC8 Instruction Set Load Instructions 8 bits Load Instructions 16 bits first section Load Instructions 16 bits second section Arithmetic and Logic Instructions 8 bits Arithmetic Instructions 16 bits CPU Control Instructions Jump Instructions Call and Return Instructions Rotate and Shift Instructions Bit Handling Instructions Input and Output Instructions DMC8 Instructions in alfabetical order DMC8 Instructions in numerical order Appendix Deeds historical version notes JU U U U U U UD UU UD 112 116 Index of Figures Fig 1 An example of laboratory report displayed in the main browser of Deeds Fig 2 The Deeds environment the main and assistant browsers on top left and the three Simulation Tools the Digital Circuit Simulator on top right the Finite State Machine Simulator on bottom left and the Micro Computer Emulator on bottom right Fig 3 The main browser of Deeds showing the HTML page that allows to connect to the Deeds web site and to the on line learning materials Fig 4 The main browser connected to the
87. ined with the d DcS Ed 0 5__ Timing Diagram Timing Interval Simulation mode edgedetec iz Reset In B Ind Dut rn Set the Timing Interval Simulation TIS mode 4 ra pixel Fig 48 Timing simulation of the previous network obtained with the d DcS This image from the Tapestry of Bayeux Bayeux Cathedral France 59 A simple example of interaction between Deeds browsers and d FsM As in the example applied to the Deeds with the d DcS in Fig 49 a list of laboratory assignments is opened in the Deeds main browser A Deeds Electronic System Design 1 INF Laboratory Sessions File Run Tools Options Help a a x c gy 4005 Home Open Back Forward Stop Assistant 3 2 clock H equencyv or a Svricnronous seguenta networ 6 4 Analysis of asynchronous up and down counters Analysis of sequential networks as finite state machines 2004 04 19 Assignments Report 7 1 Re thinking a synchronous counter as Finite State Machine FSM 00240 7 2 Revwerse engineering a synchronous sequential circuit OCA 3 Design of simple finite state machines Download 5004 04 26 Assignments Report 8 1 Design of a synchronous mod 5 up down counter OO FO 8 1 Design of a simple serial receiver 0 Design of finite state machines Download 2004 05 02 Assiguimenis Report 9 1 Design of a timing sequence generator 0290 9 2 Design of a serial d
88. inputs DIR and EN The necessary five state blocks are already drawn 62 In Fig 52a b c are displayed the pre defined properties as they appear in the Input Output dialog windows that the user activates with the tool bar command SS State Register OK Cancel Fig 52a b c The three pages of the Input Output dialog window used to define inputs outputs and state variables Note that the specification requires that the a state will be the Reset state i e the starting state of the component at the activation of the asynchronous Reset Also this characteristic has been pre defined in the template as the a state appears in the drawing with a ittle diamond placed on it Actually all the states properties have been pre defined in the template The user can modify this properties opening the Property Window This can be left aside to the editor during the operations to open it press the tool bar button Phy In Fig 53 you see the Property Window as it appears when the user select the a state block with a mouse click on it JHE 5 File Edit View Simulation Window Deeds Help nega mu _ B EI 4 182 50 State at Reset activation Fig 53 The property window displaying the properties of the a state For a state block the user can set or change the symbolic name a in the present cas
89. instance all the components that require a low activated reset now will start un initialised showing unknown outputs until the user will reset them expressly When you exit the interactive simulation all inputs an outputs reset to their default status Now during the timing simulation the circuit in the editor shows input and output value coherently with simulation results You can observe the input output status of the circuit in the editor before and after each simulation step Now when you print the circuit or copy it as image on the clipboard the resulting picture is coherent with the input output values currently displayed in the editor The maximum time for simulation has been fixed now it is no more limited to 32678 nS d FsM Now when timing simulation window is iconized and the simulation closed the bar buttons are correctly enabled and updated Now when editor and timing windows are in iconized or maximized state and the user closes them their normal position instead of the currently one is saved In this way when the user will re open the windows these will be placed in their normal position The correction has been done to reduce flickering and flashing of the windows on the screen 04 11 2003 d DcS 116 An error in simulation of decoder components has been fixed d McE In the debugger OBJECT CODE frame the memory extended view command has been fixed now in this mode all the
90. instructions on how to explore or test the circuit itself Such procedure is equally useful to convey concepts on simple components or quite complex networks In the first case simulators allows to animate circuits i e to explore them interactively In the second one their capabilities of tracing signals in the time and data domain allows a thorough test of the network How to use Deeds to solve exercises The target of traditional exercises is to help understanding theory applying it to simple cases and providing a feedback to the teacher through the delivery of the solutions In our system exercises are presented as HTML pages containing text and figures of the assignments The role of Deeds is to allow students to check the correctness of the solutions obtained manually and to provide graphical tools for editing the web page containing their reports until they are satisfied with their work and use Deeds to deliver the reports through the network The use of Deeds implies also a different approach to the structure of the exercises In fact with the simulator students may be tempted to skip manual analysis Exercises therefore must be targeted more to the real understanding of the issues than to the execution of repetitive tasks 10 How to use Deeds to learn to design electronic systems The development of a digital design project is the field where Deeds can fully be exploited In fact the interactive logic simulator the finit
91. ith these ports changing the Input values by clicking on the little round buttons corresponding to the port bits or writing the value in the field aside in decimal or hexadecimal coding The last pane presents to the user the object code in execution as loaded in memory in numerical format on the left and in assembly source format on the right The student can execute the program step by step or by animation a modality that resembles the real execution but at human readable speed A cursor permits to regulate the animation speed to the needs of the test 83 A simple example of interaction between Deeds browsers and d McE In Fig 81 a list of laboratory assignments is opened in the Deeds main browser The student has to attend the assignment 4 1 of the course on Microcomputer Asynchronous serial communication 2 Deeds Electronic System Design 2 E0 Laboratory Sessions File Run Tools Options Help bh A 9 99 gt B d Home Open Back Forward Stop Assistant d DOcS d Mz d McE d 2 5tring handling in assembly Download 2003 12 16 ssgement Report 2 1 handling m assembly 01040 3 Simulation of digital networks Download 2004 12 23 Asstgnment Report 3 1 Micro computer simulation of a Register ounter OTOSD s 4 Serial communication Download 2004 01 13 Report 4 1 Asynchronous serial communication 01060 Parallel interfacing and int
92. lag Notation flag is not affected 11 ccc 000 11 t 111 I 105 Rotate and Shift Instructions Symbolic Flags Opcode Clock Mnemonic Z A T 76 543 210 Pyles Odes ees Comments m RLCr 1 10 PO 11 001 011 00000 r RLC HL 7 0 Te 7 0 PO 11 001 011 00 000 110 RLC IX d cro 11 011 101 11 001 011 lt d gt 00 000 110 RLC IY d 11 111 101 11 001 011 CB gt 000 110 0 PO 1 m is of r HL IX d IY d as sod C OL P O t 101 and States are the same as RLC SRL m 0 0 P 0 111 Replace 000 with shown code RLD t 10 0 11 101 101 ED 2 5 18 Ll ald t 0 P O 11 101 101 ED 2 Notes ae e P symbol in the P V flag column indicates that the P V flag contains the parity of the result r means any of the registers A B C D E H L CY means the carry flip flop Flag Notation flag is not affected 0 flag is reset 1 flag is set t flag is set according to the result of the operation je mp D je gt 106 Bit Handling Instructions NE s z 12 s sa Soe St comes Mnemonic Operation S H PVN C 76 543 210 Hex Bytes Cycles Cycles Comments pe ee fo ee Z lt 01 b BIT b HL X O0 11 001 011 Z lt HL 01 b 110 BIT b IX d 11 011 101 DD d gt 01 b 110 b IY d 11 111 101 FD 4 5 20 01
93. lick with the mouse right button on a signal name button you activate a context menu Context Menus allow to move up or down the signal traces and to set signal properties For instance you can change clock period and initial value for clock inputs and initial value of the ordinary input signals can be set In the Timing Diagram activating simulation and or signal editing without to release the Time Stop cursor is now inhibited avoiding the bug of losing the cursor Now the F8 short cut not only sets the Timing Diagram Simulation mode but also put the Timing Diagram window on the Top if already present Instead if the Timing Diagram window is on Top the F short cut gets the main window Top again The problem of redrawing of the vertical lines used as cursors in the timing diagram has been fixed before when hint messages of buttons were displayed and the mouse moved away through the diagram some pieces of lines remained on the screen When timing simulation is active editing of circuit is now actually inhibited the out of bound error has been eliminated Now before to simulate the application asks the user for saving the file of the circuit if the file has been modified The internal simulation loop has been enhanced making timing simulation faster Now it is possible to break simulation when tired to wait for long times by clicking on the Stop button You ll be requested to confirm breaking During long sim
94. ls and operations on them The last description the functional one is the more powerful because it allows to see the hardware circuit as a software program with input and output variables The FSM is therefore described as a process activated in our case by the clock or reset signals Each state is coded as an internal variable An instruction case within each state defines the outputs to activate and the next state 53 DEEDS Digital Electronics Education and Design Suite VHDL Code generated by Finite State Machine Simulator d FsM Copyright 2001 2004 DIBE University of Genoa Italy Web Site http esng dibe unige it netpro Deeds LIBRARY ieee USE ieee std logic 1164 ALL ENTITY Deriv UC IS PORT p gt Clock amp Reset Ck IN std_logic Reset IN std_logic x 555 55 S gt Inputs IIN IN std_logic s gt Outputs OOUT OUT std logic END Deriv UC ARCHITECTURE behave OF Deriv UC IS Behavioral Description TYPE states is state a state b SIGNAL State Next State states BEGIN Next State Combinational Logic FSM process State IIN begin CASE State IS when state a if IIN 1 then Next State state b else Next State state a end if when state b if IIN 1 then Next State state b else Next State state a end i
95. make easier the transition from ASM description method to the HDL based world Reusing FSM component they can be imported in d DcS As said before the component the d FsM produces can be directly used in the d DcS and inserted into any digital circuit In Fig 43 you see a screen shot where the simple component seen before is imported in the d DcS and the network is simulated r o3 lt m Ju Iis ri t p Bes Timing Diagram Timing Interval Simulation mode EEE deriv fsm IN fout M4 lt 9 gt k n 4 nS pixel Fig 43 In this example a component designed with the d FsM has been imported in the d DcS In the d DcS the FSM interpreter works together the simulator kernel to produce functional results FSM to a maximum number of 64 states can be designed and simulated and a practical limitation to 8 inputs and 8 outputs has been introduced mostly for graphical reasons Such limitations are largely compatible with the learning aims of the simulator The FSM interpreter is able to simulate synchronous FSM with conditioned outputs In the d DcS the student can drive the inputs and observe the outputs of the FSM block as well as the internal state of the FSM in Fig 43 the row named with the name of the component deriv fsm The user can connect standard digital components to
96. micro processor memory space is shown The ASCII table page in the On Line Help has been corrected 15 10 2003 d McE A new simulation tool has been added to the Deeds the Micro Computer Emulator d The functionally emulated board include a CPU ROM and RAM memory parallel I O ports reset circuitry and a simple interrupt logic The custom 8 bit CPU named DMC8 has been designed to suite our educational needs and it is based on a simplified version of the well known Z80 processor The d McE integrates a Code Editor an Assembler and a machine level interactive Debugger The integrated source code editor enables user to enter assembly programs and a simple command permits to assemble link and load them in the emulated system memory The execution of the programs can be run step by step in the interactive debugger where the user can observe all the structures involved in the hardware software system By now the integration of this tool with the Deeds is not complete the board can not be inserted in the d DcS yet d DcS The simulation kernel code has been completely revised and its code linked with the executable The current version doesn t need the installation of the ActiveX that the previous versions do and some mistake in the simulation of complex components has been fixed The Delete by Selection command has been fixed Some other minor bugs have been corrected 11 07 2003 d FsM Now t
97. nded to support all the required functions by the Deeds environment It is mainly used to connect to the sites containing the learning materials The browser supports all the features that the user can expect to find including JAVA Virtual Machine amp JavaScript VBScript amp XML support Deeds Deeds Demo Page Fie Run Tools Options Help e B HiH pen Back Forward Stop Refresh Assistant 5 d 5rB The Deeds anew learning environment for digital electronics It 15 conceived as a suite of simulators tools and learnmg material to help students ac qurmg theoretical foundations analysis capabilites ability to solve problems all over the subject topics practical synthesis and design skills In this version we release the new RAM Micro Computer Emulator Visit the official Deeds Web Site Learning Materials is available on line Download the last version of Deeds Deeds Demo Fig 3 The main browser of Deeds showing the HTML page that allows to connect to the Deeds web site and to the on line learning materials When the user launches the Deeds environment the main browser shows up All the other tools can be activated by the menu and or toolbar command The main browser acts as main window of the application suite 13 With Deeds the user can directly navigate to the own web site
98. nother noticeable thing is that the two models are morphologically very similar In both models you can observe that every state has two outgoing transitions one being a loop on the state itself and the other going to the other state This similarity is always true if you make a conversion between ASM Charts and State Diagrams just remember that in ASM Charts conditional transitions come out of decision diamonds which are not states but they belong to the state they descend from The method used to represent conditional transitions on ASM Charts is more algorithm oriented as it uses flow chart syntax which is less redundant than State Diagram syntax In this case for example it helps the reader understand that the transition that follows state a depends only on the value of the S input Similar considerations can be done about the transition that follows state b only the value of the R input is relevant in that case The following pictures are examples of ASM Chart lt gt State Diagram conversion Fig 40a and 40b Fig 40a ASM chart and State diagram representing the same algorithm the FSM waits in the state a until the x input goes to one 52 DONE Fig 40b Another example of ASM chart and State diagram representing the same algorithm FSM description languages state transition table The state transition table Fig 41 is the most compact description of a FSM and lends itself very well to be used as interface
99. ode nearest to the professional simulators 26 A simple example In following screen shots Fig 17a b c you can see the circuit during the drawing and then simulated by animation a the student picks up components from the bin on the Component Tool Bar then b connects them using Wires When finished c the student activates the animation E s Digital Unnamed File Edit view Tools Circuit Simulation Deeds Options Help 5 s t C Se Io gt m rr E REIR ODDO PIDE DS PL J gt Nand 2 inputs inputs d Mand 4 inputs gt Logic gate NAND 3 inputs Bg ejen File Edit View Tools Circuit Simulation Deeds Options Help amp gt SB p m Ot Pl ain Gi u EE 4 20 mm 7 Fig 17b The next phase of the work the connection of components using wires 27 m Bari eje gir Suabia File Edit View Tools Circuit Simulation Deeds Options Help ID ah Slo e s s P C S p e we 4 D Ds PER K FE EE PE 4 21 50 2 Fig 17 animation at work the user switches the Inputs the circuit shows changes the Outputs To enter the animation mode the user clicks on the triangular play button gt on the toolbar During the animation the editing command are disabled and the ci
100. omponents a Error Check List Decoders Encoders Multiplexers Demultiplexers TFI Flip Flop Registers Counters EEF Finite State Machine m Fig 30 The d DcS Circuit menu Clock Generator Command to insert in the circuit a Clock Generator component Input Command to insert in the circuit a Input Switch component High Level Command to insert in the circuit a High Level Input component logic 1 Low Level Command to insert in the circuit a Low Level Input component logic 0 Wire Command to insert in the circuit a wire segment The wiring system supports automatic insertion of wire nodes when a wire is connected to another one 40 Command to insert in the circuit a binary Output Display component it displays 0 1 or unknown symbols Display Components Command to insert in the circuit an Hexadecimal Output Display component it displays hex digits from 0 to F or a unknown symbol Input Command to insert in the circuit a Input Switch component Error Check List Command to error check the wiring of the circuit It shows or hides at the bottom of the window an error check list of wire connections Command to insert in the circuit a component selected by the user in the sub menu A description of all the sub menu s is reported in the following T M
101. on is 2 The button restarts simulation from time 0 The button activates the ASM Table window Fig 60 In this table Inputs Outputs and current and next States are expressed in a compact tabular form Fig 60 The ASM Table window 67 d FsM Menu Commands The menu of the Finite State Machine Simulator allows the user to access all the function of the application The ToolBars replicate most of the commands already in the menu to speed up user operations Finite State Machine Simulate Save Close Export Print File A Paper Setup deriv Fsm Lab es 01 Full Fsm ex 2z70 1 kem Fsm edgedetector Fsm edgedetector_c Fsm edgedetector_b Fsm edgedeteckor a Fsm LIC fsm Exit Fig 61 The d FsM File menu Command to create a new Finite State Machine file Command to open a Finite State Machine file The file can be also downloaded directly from a web site Save Command to save current Finite State Machine file Save as Command to save current Finite State Machine file with a different name or in a different position 68 Command to close the current Finite State Machine Export VHDL Command to export the Finite State Machine ASM diagram in VHDL language It shows a window with the equivalent VHDL code generated from the internal data Paper Setup base Fig 62 VAD Code LIBRARY ieee USE ieee std logic ll6
102. onal blocks connected a nonsense mode Some algorithmic optimization has been done so the program now is faster that before during redrawing when the diagram is big The Properties window now shows correctly for all the screen resolution Now the user controls its visibility and the visibility is remembered between work sessions The In Out dialog now remembers between work sessions which page was last opened The timing window doesn t ask the user anymore if no simulation has been started instead now the program prompts the user on a clear diagram request if data could be lost Drawing of output names in the state and conditional output blocks has been enhanced They are displayed from left to right on two lines If some output name can not be displayed for lack of space a sign appears after the last one on the second line to notify the user that more output have been assigned to the block but that they can not be displayed Anyway the complete output list is visible on the bottom status bar when the user points the mouse over the block of interest The algorithm that shows the arrows on the lines has been enhanced and the arrow shape modified Drawing of the input name in the decisional blocks has been horizontally centered d DcS Drawing of input and output pin names in the FSM components has been enhanced To avoid overlapping of long names names too long are shorted at display level
103. ore At beginning use the value of 000000001 as the one transmitted before Fig 82a The specific laboratory assignment opened in the Assistant browser first part In this assignment Fig 82a we require to the student to write a program to receive and retransmit serial asynchronous information using the parallel ports available in the d McE The program should take in charge the operation of de serializing and serializing data Also a simple cryptographic method is applied to data before retransmitting it In the assignment is described the format of the serial data packet standard 8 bit asynchronous serial communication without parity control That protocol previews one start bit at 1 eight data bits b7 b0 b7 ahead one stop bit at 0 It is defined a low bit rate 100 bits per second with the aim to let the user concentrate on the basic tasks without bothering too attention to timing problems The text continues suggesting to connect the input and output serial lines to specific bits of the available input and output ports INPORT and OUTPORT The simple cryptographic operation requires that the program remember the previous transmitted byte and combine it in a byte wise EXOR operation with the currently received one 85 lt Assistant DEDS laboratory 2322101 a 5 m ard Menu Solution guidelines To capture the start bit the receiver samples SERIN with a period of 1 16 of the bit
104. owser The d DC 5 Digital Circuit Simulator 9 The d Fs M Finite State Machine Simulator 9 The d IMCE Micro Computer Emulator B Internet download Deeds Version Floppy download 2 ra o Bonm Disk 1 Disk 2 Disk 3 Disk 4 Deeds as Fig 5 The download page in the Deeds web site 14 Deeds has been developed as common simulation tool to be shared among different institutions running courses on Digital Design as a support of the activities of the NetPro project in the field of Electronic Engineering NetPro a European project of the Leonardo DaVinci program develops project based learning through Internet It has created models tools and services to facilitate communication and collaboration between distant students and to manage access and control of project deliverables We test NetPro methodologies and tools by running pilot projects An important characteristic of the pilot courses is that project groups can be distributed over different academic institutions and countries A pilot course may have teams from more than one institution and more than one nation while teams themselves could be inter institutional and international The immediate goal of the collaboration between pilot sites is to provide learning tasks that are meaningful for all students independently of their local arrangements Joint working is possible if teams use the same language all the components of our pilot
105. rcuit can t be changed when the user clicks on the Input Switches B see Fig 17c the Outputs change according to the simulation results showing O 0 or unknown values To exit the animation mode it is necessary to click on the square stop button E Instead if the timing simulation is to be performed the user should click on the Timing Simulation button This will show the Timing Diagram simulation window Fig 18 very similar to the ones that we find in professional tools for digital electronics E Tinie Magram himine Ital simulanon mode Bz Set Bu 44 4 lt a B bh d TE t 756 n5 Editable Input please click bo add new edge or move left 4 nS pixel a Fig 18 The Timing Diagram simulation window 28 In this window first of all the user defines the timing of the input signals drawing them on the diagram with the mouse A vertical line cursor permits to define the end time of the simulation When the user clicks on the triangular play button gt on the toolbar the simulation is executed and its results are displayed in the same window Fig 19 teil d DeS Timing Diagram Timing Interval Simulation mode i Set z Reset 4 5 44 4 lt 4 nS pixel Fig 19 The timing simulation results displayed in the Timing Diagram window The student can verify the correct behaviour of the network under t
106. rder Numerical Order ASCH code DMCS Processor Architecture Load bits Load 16 bits Arithmetic Logic 8 bits Arithmetic 16 bits CPU Control Jump DMCS Processor Architecture Internal Address Bus 55 DMCB Short Guide Subprogram Call and Return Shift and Rotate Bit Input Output Alfabetical Order Numerical Order ASCH cade DMCS Processor Architecture Load 8 bits Load 16 hits Hn 9 bits Arithmetic 15 bits CPU Contral Jump Arithmetic Logic Instructions bits Mnemonic Symbolic Flags Opcode Hex Bytes Clock Comments Operation S BAN 78543210 Cycles ADD A r v O Dp 10000 r r 2 000 Beat 1 f 11 900 110 E m n 010 ADD A HL A cA HL v 0 10000110 E p ADD A IX d owe DL fF 011 101 101 luris ADD A IY d A cA EUN d Is of we og 11 111 101 10 000 110 4 ea ADCAS 00 KES DE f amp is any af om A s MI PII a 010 CI ed as shown for the SBCAS 0 A AeA sc e4 s CY t 011 ADD instruction anos 00 5 4 AND ET 0 x x x The underlined bits ORs Asas A B bD Pe D D replace the VERUS underlined bits in the ER o
107. s Fig 86 Port addresses can be modified by a mouse click on the simulated on board dip switches When finished the student had to compile and deliver a report A template file for the report is available in the assignment page see Fig 87 lt Deeds Electronic System Design 2 E0 Laboratory Sessions File Run Tools Options Help a gt x o GE Home Oper Back Forward Stop Refresh Assistant d Dic5 L aac RON UNA Se eae 2 String handling in assembly 2003 12 16 Assignment 21 String handling in assembl 3 Simulation of digital networks Download 2004 12 23 Assignment Report 3 1 Micro computer simulation of a Eegister C ounter LOA 4 Serial communication Download 5004 0113 Report 4 l Asynchronous serial communication 5 Parallel interfacing and interrupt handling Download 5004 01 20 Assignment Report 5 1 Introduction to parallel interfacing and interrupt handling a ES System Design 2 Lat Z Fig 87 The student can download the report template to speed up its compilation and delivering 89 In this case the template presents only a header that permit to uniform all the report styles making easier the teacher task Fig 88 el p fwww esng dibe unige it netpro deeds lear SEE File Modifica Visualizza Inserisci Formato Strumenti gt ae p Indietro gt
108. s Deeds Learning Materials 224 Options Help Assistant Deeds Demo Page E Refresh v Digital Circuit Simulator SetReset_INand pbs Finite State Machine Simulator quatkro Fsm Finite State Machine Simulator deri Switch to Deeds Application Shift F7 Switch to Tool Gn Top F7 Close All Tools J xD 3 Fig 10 The main browser Tools menu d wj w First items group Commands to switch focus to the chosen tool All the opened tools are indexed here together with the name of the corresponding opened file if any When the user click on an item the tool will go on top Switch to Next Deeds Application Command to switch to the next Deeds open tool or browser Switch to Tool on Top Command to switch to the tool that was on top before switching to the main browser Close Tool Command to close all the opened tool If a file opened in a tool is not saved the user will be prompted and the close operation stopped 19 Options Menu SR Deeds Deeds Learning Materials File Run Tools Help Status Bar Find this page Ctrl F f Dockable Toolbars Fig 11 The main browser Options menu Configuration Command to change the application configuration disabled in this version ToolBars Commands to con
109. s including student deliverables and communication are in English and if the classes involved study the same topic at the same time of year All documents produced are available as web sites for on line fruition or as downloadable files In fig 6 you see opened in the main browser the learning material index page available in the Deeds web site 5 Deede Vasds Exercices by topici Run Tools Options Help 2 o n m Home Open Back Forward Stop Refresh Assistant d Dic5 6 Flip Flops and Registers Download Analysis of a Set Reset Flip Flop 00140 Tuning analysis of a SE Latch Fhp Bop Timing analysis of a D PET flip Hop 00160 Timing analysis of a JE PET flip flop DOT Analysis of a 3 bit shitt register D PET 00180 1 1 Counters and other sequential networks Download Analysis of a module 4 Johnson counter Analysis of a synchronous sequence generator uosti Maamur clock frequency of a synchronous sequential network 00220 Analysis of asynchronous up and down counters 00230 Analysis of a counter from the d DcS component library D02205 Analysis of the possible states of a synchronous sequential circuit 00190 Introduction
110. shows the results of the simulation As expected the output line OUT goes high for one clock cycle each time the input line IN presents a level transition Fig 45 The simulation results for the edge detector described above 5 In Fig 46 is reported the ASM transition table describing the designed FSM as well as the preview of the automatically generated symbol of the new component Nm ASM Table mex our 0 00 Cancel Fig 46 The ASM transition table describing the component on the left and the generated symbol on the right Now the component is ready to be imported in the d DcS We insert the component in a very simple way loading it from file An example of use of this component in the d DcS is shown in the Fig 47 where two instances of it are connected in a circuit composed also of standard gates pm LIT i Metal Oyen Sinha s ass Sre phs File Edit wiew Tools Circuit Simulation Deeds Options Help X Rt mE P m 8 D 8 gg Fig 47 Two instances of the component connected in circuit composed of standard gates in the d DcS 58 Then the student could verify the correct behaviour of the network under test comparing d DcS simulation results with those expected in particular with the functional simulation produced by the d Fsm In Fig 48 you see a screen shot of the timing simulation obta
111. stant 24 Deeds The Digital Circuit Simulator d DcS LLA Age This image from the Tapestry of Bayeux Bayeux Cathedral France 25 Introduction The Digital Circuit Simulator d DcS appears to the user as a graphical schematic editor with a library of simplified logic components specialised toward pedagogical needs and not describing specific commercial products Fig 16 As described before the schematic editor allows to build simple digital networks composed of gates flip flops pre defined combinational and sequential circuits and custom defined components defined as Finite state machine i nj eireuisanulator Coups nus File Edit wiew Tools Circuit Simulation Deeds Options Help gt m m a e w 2 6 c s p z P 5 D gt gt so p E LOAD L IH Univ b CL Fig 16 The circuit editor of the Digital Circuit Simulator d DcS Simulation can be interactive or in timing mode In the first mode the student can animate the digital system in the editor controlling its inputs and observing the results This is the simplest mode to examine a digital network and this way of operation can be useful for the beginners In the timing mode the behaviour of the circuit can be analysed by a timing diagram window in which the user can define graphically an input signal sequence and observe the simulation results This is the m
112. start from zero For this reason the a state is the Reset state the starting state of the at the activation of the asynchronous Reset In the template as it is convenient m the present case the state codes have been assigned equal to the outputs values X QC Y GB and Z QA using the timme simulation the correct sequence of the output values and the state codes Once you have finished the FIM design you it in the d as a component You can use the d DcS schematic template provided and complete r with the component Repeat the simulation of the counter with the d DcS timing simulator Fig 506 specific laboratory assignment opened in the Assistant browser second page To download the template it is necessary only a simple click on the link in the text The d FsM will be activated and the file downloaded from the web site automatically In Fig 51 you see the suggested template as downloaded in the simulator Finite State Machine Simulator ex00270 1 tem fsm ASM State Chart E File Edit View Simulation Window Deeds Help De IJ Bw amp D EI Ad 111 22 Fig 51 The downloaded ASM diagram template of the solution In the template as the text of the assignment explains the student will find some important definition already set the state variables X Y Z the outputs QC QB QA and the
113. the timing simulation of the component in the d DcS As in the example related to the d DcS at this point the student will compile and deliver report about its work As already seen in the assignments page a link is set to download a report template file Fig 57 65 5 Deeds Electronic System Design 1 INF Laboratory Sessions Fie Run Tools Options Help 2004 04 19 8 2004 04 26 9 2004 05 03 Open Back Forward Stop o Analysis of sequential networks as finite state machines Assigninenis Assistant d Dc5 d hs d McE d 5rB Refresh x Derwaiload Report 1 Re a synchronous counter as Finite State Machine 00240 00250 Design of simple finite state machines Download Assignments 8 1 Design of a synchronous mod 5 up down counter 8 2 Design of a simple serial line receiver Design of finite state machines Download Assignments Report 9 1 Design of a timing sequence generator 0230 9 1 Design of a serial data processor OO 300 Electronic System Design 1 INF La 2 Fig 57 Also in this case the student will download the report template to speed up its compilation and delivering In Fig 58 is displayed the report template prepared for this laboratory assignment downloaded and ready to be edited a Word Misualizza Inserisci Formato Strumenti Tabela Finestra Deliverable n 8 ES
114. trol ToolBars appearance Browser ToolBar Command to hide or show the Browser ToolBar Status Bar Command to hide or show the Status Bar Show and Dock All ToolBars Command to show and dock in all the ToolBars Dockable ToolBars Command to enable or disable the docking modality of the ToolBars 20 Deeds Deeds Learning Materials Run Tools Options AX 5 Index je Home License Agreement Help Menu version Motes Fig 12 The main browser menu Command to open the Deeds Help System License Agreement Command to display the Licence Agreement Version Notes Command to display the Version Notes file Command to display the Deeds splash window dialog 21 Deeds The Assistant Browser d AsT The Assistant HTML browser has characteristics similar to those of the main browser but it is specialized to assist students side by side in their work fig 13 This is the browser used to open lessons exercises and laboratory assignments As the main also the Assistant browser has been conceived around the standard Microsoft WebBrowser component In Fig 13 the Assistant browser is opened aside of the main one showing a page with a problem assignment from the ESD1 NetPro course To open an assignment the user will click on the desired topic listed in the main browser the Assistant will open automatically showing itself aside rl A
115. ts on the time diagram At the same time in the editor window the corresponding new state is highlighted with a coloured frame around it see Fig 55 This is an important feature because a major difficulty for a beginner is to understand the correspondence between states and events time sequence Finally when the behaviour of the component satisfies all the required specifications the component could be imported in the d DcS see the assignment Fig 50b Also in this case a simple d DcS schematic template is provided to speed up the operations it can be easy downloaded and opened in the d DcS with a click on the hyperlink in the text Once completed the schematic the simulation of the counter could be repeated in the d DcS timing simulator Fig 56 E m Wm 1 i File Edit View Tools Circuit Simulation Deeds Options Help ma dri vx p fs eb amp LU i i IL i rir fi i feel gol 4 ete Iz T fak a amp amp P m Hw a Clock EJ Lab n8 e DIR Reset EN ac GB 44 a y b 4 Fig 56 The finished d DcS schematic and
116. tworks directly on the schematics An interactive logic simulator with a timing diagram tracer to analyse events in the logic networks and to interact step by step with the circuit A finite state machine editor simulator the algorithm is described using an Algorithmic State Machine graphical editor A microcomputer board emulator the board include an 8 bit CPU ROM RAM I O ports An assembler level interactive debugger module Deeds tools can interact with each other The HTML main and assistant browsers allows to launch all the other tools and interact with them The browser can control editors and simulators to realise a true interaction between text and experiments The schematic editor allows to connect traditional logic circuits with subsystems defined by the user with the help of the finite state machine editors and the micro computer emulator It is possible to experiment with digital systems controlled by state machines The architecture of Deeds allows a scalable approach to the lessons exercises and laboratory sessions All the tools included allow either a simplified scenario to beginners and a more exhaustive and complete environment for skilled students Deeds as a learning environment for digital electronics Deeds is conceived as a learning environment for digital electronics With such term we mean a collection of tools and text material that help students acquiring theoretical foundations of the s
117. ubject analysis capabilities ability to solve problems all over the subject topics practical synthesis and design skills Deeds is conceived as a common resource for all introductive courses in digital electronics As such it may contain different technical subjects different pedagogical formats lectures exercises lab assignments etc delivered at different student levels Deeds is therefore born as a set of tools listed before that teachers can complete and personalise to suit their pedagogical needs by contributing to the lecture space with their own materials There is no need for a specific authoring tool because the lecture space can be composed with any HTML editor completed by a helper application that facilitates the linking of the editors and simulators commands to the lecture text How to use Deeds to teach theory A lecture based on Deeds appears as HTML pages with text and figures The page aspect and layout are totally up to the author At this level students see a normal on line book or document But many of the figures and visual objects are active because they are connected to the editing and simulation tools of Deeds For example let s suppose that theory presents a certain digital circuit visualising its schematics in a picture When the user clicks on the picture Deeds launches the corresponding simulator and opens that schematic together with another windows the Helper that contains step by step
118. ulations a percentage of the work is displayed on the status bar at bottom Finite State Machine simulation has been fixed and enhanced now at simulation start their state is considered undefined until the Reset signal is activated as expected However due to limitation of the model used by now the outputs are considered always unknown until state stay undefined without taking in count conditions from the inputs d FsM 120 e Now it is possible to restore correctly the application windows after having closed them in the maximized state e Now some commands no more generate errors when activated in absence of opened windows e Some error message revised some others translated in English e The Print command has been disabled waiting a major fix of the printing module A few minor bugs have been fixed Deeds e The main browser is not yet fully operational but a link to the Deeds Web Site has been added in the demo page 01 03 2002 d DcS e Added the ability to copy on the Clipboard the Timing Diagram current view e Now the Timing Diagram you can highlight the transitions of a specific signal with a click on its button in this way you can relate its transitions with the behaviour of the network under simulation e Afew bugs have been fixed 22 02 2002 and before Released for internal beta test only 121
119. ur commands to rotate an object during its insertion to the specified direction 3 Mice ei Deeds Help Tile Vertical Tile Horizontal Cascade Arrange Icons w 1 ASM State Chart Fig 69 The d FsM Window menu Tile Vertical Command to tile vertically the opened windows the graphical editor the timing diagram the ASM table Tile Horizontal Command to tile horizontally the opened windows as above Cascade Command to cascade diagonally the opened windows as above Arrange Icons Command to reorder the icons of the iconized windows at the bottom of the main window Opened windows list Command to switch focus among the opened windows within the main window 74 Switch to Deeds 7 Switch to Last F Switch Ea Wexk sShiFtE F7 Fig 70 The d FsM Deeds menu Switch to Deeds Command to switch focus to the Deeds main browser Switch to Last Command to switch to the tool that was last on top before switching to the currently opened instance of the d DcS Switch to Next Command to switch focus among all active Deeds applications in order of activation 75 Help Menu Help Index License Agreement Version Motes About Fig 71 The d FsM Help menu Index Command to open the d FsM Help System disabled in this version License Agreement Command to display the Licence Agreement
120. wing circ Forward Ctrl F combimahonalcrcutis composed by a half ac full adder the five gate Refresh represent two levels Stop Print Preview E Print Page i Help Deeds Options ED N Exit E Fig 14 The Assistant main menu appended to the toolbar Home Page Command to navigate to the Assistant local home page Open Page Open the Open Page dialog Fig 15 In this dialog window the user can type directly a URL address or browse the local network or disk The chosen web page can be set as Home Page A short history of previously opened pages is maintained Open a page Add 4 51 Browse Cancel j Fig 15 The Open Page dialog window Register it as current topic Home Page Standard browsing command to return to the previous opened page Standard browsing command to return to the next opened page after using the Back command 23 Refresh Print Preview Print Page Deeds Exit Standard browsing command to stop the download of the current page Standard browsing command to reload the currently opened page Standard command to preview the current page before printing Standard command to print the current page Command group to navigate between the opened Deeds tools Command group to change the Assistant configuration and options Standard command to close the Assi
121. with computer software and as a basis for the logical synthesis of the hardware Of course the table is not a valid FSM design tool because it does not provide any help in conceiving the FSM algorithm Its main usefulness rests therefore in its use as a synthetic representation that may be common to both the languages described above Fig 41 The state transition table of the example above as generated by the d FsM FSM description languages hardware description language The use of circuit description languages HDL VHDL Verilog to represent finite state machine has gained a strong diffusion and probably in many cases has replaced the graphical languages The description of the state machine takes in this case the format of a high level software program The Finite State Machine Simulator exports the FSM components in VHDL format Very High speed integrated circuits Hardware Description Language In Fig 42 you can see the VHDL equivalent of the ASM diagram in Fig 37 as generated by the Finite State Machine Simulator The list starts with the Entity i e the definition of the FSM as a block with inputs and outputs Then an object Architecture of the entity is instantiated An entity may be described in three different ways structural data flow functional The structural description decomposes the entity in terms of basic digital components and their connections The data flow description represents the FSM in terms of signa
122. y have any number of exit paths each of them connecting to another state box The FSM moves from state to state at each clock cycle each state may have a state output conditional blocks allow choosing a direction as a function of the value of the inputs conditional outputs depend not only on states but also on input values State Block On an ASM chart a state is represented by a state box which is a rectangle 001 with the name of the state encircled and placed at the side of the rectangle OUT Fig 38a You can specify that an output signal is unconditionally active in a LE particular state by writing output signal s name inside the corresponding state box Output signals written inside state boxes are known as state outputs or Moore outputs Fig 38a State Block Decision Block While unconditional transitions can be represented with a straight not labelled arrow traced between two state boxes conditional transitions deserve a more specific symbol This is called decision diamond Depending on the value of the expression written inside the diamond the machine will follow one of the two labelled transition arrows going out of the diamond A diamond has always two 0 1 outgoing arrows one labelled 1 or TRUE and the other labelled 0 or FALSE that corresponds to the values of the boolean expression inside Fig 38b Decision Block Conditional Output Block Sometimes you may need to activate an output signal in

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