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Élan™SC520 Microcontroller Register Set Manual

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1. 6 1 Table 6 2 PCI Bus Host Bridge Direct Mapped Registers 6 2 Table 6 3 PCI Bus Host Bridge Indexed 5 5 6 2 Table 7 1 SDRAM Controller MMCR Registers 7 1 Table 7 2 Example ECC Check Codes and Associated 1 7 13 Table 8 1 Write Buffer and Read Buffer MMCR 8 1 Table 9 1 ROM Controller MMCR 5 lt 9 1 Table 10 1 GP Bus MMCR Registers lille 10 1 Table 10 2 GP Bus Echo Mode Minimum 10 2 Table 11 1 GP DMA MMCR 11 1 Table 11 2 GP DMA Direct Mapped 11 2 Table 12 1 Programmable Interrupt Controller MMCR 5 12 1 Table 12 2 Programmable Interrupt Controller Direct Mapped 12 2 Table 12 3 Master PIC I O Port 0020h Access 12 27 Table 12 4 Master PIC I O Port 0020h Access Summary Same as Table 12 3 12 29 Table 12 5 Master PIC I O Port 0020h Access Summary Same as Table 12 3 12 31 Table 12 6 Slave 2 PIC I O Port 0024h Access
2. 12 40 Table 12 7 Slave 2 PIC I O Port 0024h Access Summary Same as Table 12 6 12 42 Table 12 8 Slave 2 PIC I O Port 0024h Access Summary Same as Table 12 6 12 44 Table 12 9 Slave 1 PIC I O Port 00A0h Access 5 12 52 Table 12 10Slave 1 PIC I O Port 00A0h Access Summary Same as Table 12 9 12 54 Table 12 11Slave 1 PIC 1 0 Port 00A0h Access Summary Same as Table 12 9 12 56 Table 13 1 Programmable Interval Timer Direct Mapped 5 13 1 Table 13 2 PIT Counter Mode 13 9 Table 14 1 General Purpose Timer MMCR Registers 14 1 Table 15 1 Software Timer MMCR 5 15 1 Table 16 1 Watchdog Timer MMCR 5 16 1 Table 16 2 Watchdog Timer Exponent Selections 16 3 Table 17 1 Real Time Clock Direct Mapped 17 1 Table 17 2 Real Time Clock Indexed 17 1 Table 18 1 UART MMCR Registers 18 1 Table 18 2 UART Direct Mapped 18 1 Table 18 3 Baud Rates Divisor
3. 15 14 13 12 11 10 9 8 Bit MCA 15 8 Reset 0 0 0 0 0 0 0 0 R W R W 7 6 5 4 3 2 1 0 Bit MCA 7 0 Reset 0 0 0 0 0 0 0 0 R W R W Register Description This register contains one of the compare values for the GPTMR1ONT register see page 14 12 Bit Definitions Bit Name Function 15 0 15 0 GP Timer 1 Maxcount Compare Register A This register contains one of the maximum values that GP Timer 1 can count to before resetting its count register to O Programming Notes GP Timer 0 and GP Timer 1 each have two maxcount compare registers GPTMRxMAXCMPA and GPTMRxMAXCMPB If the maxcount compare register that is in use contains the value 0000h and the timer is enabled the timer counts to FFFFh at which point the appropriate action occurs based on the timer configuration options that are set For details see the GPTMRICTL register bits INT MAX CNT RIU MAX_CNT ALT_CMP and CONT CMP starting on page 14 10 If the maxcount compare register that is in use contains a value other than 0000h and the timer is enabled the timer counts to the programmed maxcount value lan SC520 Microcontroller Register Set Manual 14 13 AMDA General Purpose Timer Registers GP Timer 1 Maxcount Compare B GPTMR1MAXCMPB Memory Mapped MMCR Offset C80h 15 14 13 12 11 10 9 8 Bit MCB 15 8 Reset 0 0 0 0 0 0 0 0 R W R W 7 6 5
4. 7 6 5 4 3 2 1 Bit Reserved DMA2ADR 27 24 Reset 0 0 0 0 0 0 0 R W RSV R W Register Description This register provides the extended page address for Channel 2 Bit Definitions Bit Name Function 7 4 Reserved Reserved This bit field should be written to 0 for normal system operation 3 0 DMA2ADR DMA Channel 2 Extended Page Address 27 24 This bit field specifies the highest four memory address bits A27 A24 for Channel 2 Programming Notes The extended page address is used in conjunction with the memory address and the page address registers for the associated channel to make up a 28 bit address A27 A0 The Channel 2 extended page address bit field DMA2ADR 27 24 does not increment or decrement during DMA because this channel does not support enhanced mode 11 12 Elan SC520 Microcontroller Register Set Manual GP DMA Controller Registers AMDA GP DMA Channel 3 Extended Page GPDMAEXTPG3 Memory Mapped MMCR Offset D89h 7 6 5 4 3 2 1 0 Bit Reserved DMASADR 27 24 Reset 0 0 0 0 0 0 0 0 R W RSV R W Register Description This register provides the extended page address for Channel 3 Bit Definitions Bit Name Function 7 4 Reserved Reserved This bit field should be written to 0 for normal system operation 3 0 DMASADR DMA Channel 3 Extended Page Address 27 24 This bit field specifies the highest four memory address bits A27
5. 7 15 CHAPTER8 WRITE BUFFER AND READ BUFFER REGISTER 8 1 Bl OVerviow a sed eibi ib Dae 8 1 8 2 Hegister see E eee e eder aedes 8 1 SDRAM Buffer Control DBCTL 8 2 CHAPTER9 ROM FLASH CONTROLLER REGISTERS 9 1 OVervIOW kee ae tale URP END Ea eee ena 9 1 9 2 Registers io ou aes Sea ea ie SS oe hub bxc EE Lei 9 1 BOOTCS Control BOOTCSCTL 9 2 ROMCS 1 Control ROMCSICTL 9 4 ROMCS2 Control ROMCS2CTL 9 6 vi Elan SC520 Microcontroller Register Set Manual Table of Contents CHAPTER 10 GENERAL PURPOSE BUS CONTROLLER REGISTERS 10 1 TOAOQVERVICW ree fide de A 10 1 10 2 Hegisters ive Ae eee eee GU EGRE 10 1 GP Echo Mode GPECHO 10 2 GP Chip Select Data Width 0 10 3 GP Chip Select Qualification 5 10 5 GP Chip Select Recovery Time 5 10 7 GP Chip Select Pulse Width 10 8 GP Chip Select Offset 10 9 GP Read Pulse Width 10 10 GP Read Offset 10 11 GP Write Pulse Width
6. This register is used to control the functionality and modes of operation of GP Timer 0 Bit Definitions Bit 15 14 Name ENB P_ENB_WR Elan SC520 Microcontroller Register Set Manual Function GP Timer 0 Enable 0 GP Timer 0 is inhibited from counting 1 GP Timer 0 counting is enabled If GP Timer 0 was previously enabled via setting the ENB bit and is operating and then software clears the ENB bit by writing a 0 then GP Timer 0 is inhibited from counting but is not reset The various timer status bits and the TMROUTO output pin also remain stable In this scenario setting this ENB bit again causes the timer to continue from the state that it was in just prior to being disabled This bit can only be modified set or cleared via software if the P ENB WR bit of this register is set i e written as 1 during the same write cycle access to this register The ENB bit is automatically cleared by hardware under certain circumstances if noncontinuous mode is selected See the CONT bit description on page 14 5 GP Timer 0 Permit Enable Bit Write 0 Software cannot modify the ENB bit in this write cycle 1 Software can modify the ENB bit in this write cycle This bit allows selective software modifications of the ENB bit When the P WR bit is set during a write cycle access to this register the ENB bit can be modified in that same write cycle When the P ENB Wh bit is written as
7. 2 5 Programmable Address Region 2 2 2 5 Programmable Address Region 2 5 Programmable Address Region 4 2 5 Programmable Address Region 5 5 2 5 Programmable Address Region 6 6 2 5 Programmable Address Region 7 7 2 5 Programmable Address Region 8 8 2 5 Programmable Address Region 9 PARQ 2 5 Programmable Address Region 10 1 2 5 Programmable Address Region 11 11 2 5 Programmable Address Region 12 2 2 5 Programmable Address Region 13 1 2 5 Programmable Address Region 14 14 2 5 Programmable Address Region 15 15 2 5 Configuration Base Address 2 9 RESET GENERATION REGISTERS 3 1 LOVERVICWE cetacean eh tater Meal obe gu a MERE DRE uus t EE 3 1 3 2 Registers obest haee tne oce Eus e i ede ERES eds 3 1 System Board Information 3 2 Reset Configuration 3 3 Reset Status 5 55 3 5 SCP Data
8. 10 12 GP Write Offset 10 13 GPALE Pulse Width 10 14 GPALE Offset 10 15 CHAPTER 11 GP DMA CONTROLLER REGISTERS 11 1 11 1 Overview 2 4 00 bee eta ex ev bee bev ve ee eres 11 1 14 2 Flegisters 5 320142 Beye tk Bs SB Ae 11 1 GP DMA Control 1 11 4 GP DMA Memory Mapped I O 11 5 GP DMA Resource Channel Map A GPDMAEXTCHMAPA 11 6 GP DMA Resource Channel B GPDMAEXTCHMAPB 11 8 GP DMA Channel 0 Extended Page GPDMAEXTPGO 11 10 GP DMA Channel 1 Extended Page GPDMAEXTPG1 11 11 GP DMA Channel 2 Extended Page GPDMAEXTPG2 11 12 GP DMA Channel Extended Page GPDMAEXTPG3 11 13 GP DMA Channel 5 Extended Page GPDMAEXTPG5 11 14 GP DMA Channel 6 Extended Page GPDMAEXTPG6 11 15 GP DMA Channel 7 Extended Page GPDMAEXTPG7 11 16 GP DMA Channel Extended Transfer Count 11 17 GP DMA Channel 5 Extended Transfer Count GPDMAEXTTC5 11 18 GP DMA Channel 6 Extended Transfer Count GPDMAEXTTC6 11 19 GP DMA Channel 7 Extended Transfer Count GPDMAEXTTC7 11 20 Buffer Chaining Control
9. 7 6 5 4 3 2 1 0 Bit DMA7MAR 23 16 Reset 0 0 0 0 0 0 0 0 R W R W Register Description This register provides bits 23 16 of the memory address for Channel 7 Bit Definitions Bit Name Function 7 1 DMA7MAR DMA Channel 7 Memory Address Bits 23 17 23 16 For 8 bit transfers enhanced mode only the value in this bit field is used with the values in the GPDMA7MAR register see page 11 84 and the GRPDMAEXTPG7 register see page 11 16 to generate DMA address bits 27 0 For 16 bit transfers bits 7 1 of this bit field hold address bits 23 17 and address bit 16 is located in the GPDMA7MAR register see page 11 84 Bit 0 of this bit field is not used in 16 bit DMA operation The bit 0 value read back is always the last value written but the bit is not applied to the system address unless 8 bit operation is selected Programming Notes In enhanced mode this channel can be programmed for 8 bit DMA transfers see the descriptions for GPDMACTL register bits CH7 ALT SIZE and ENH MODE ENB on page 11 4 In enhanced mode this register is updated during DMA cycles if the DMA addresses cross the 64 Kbyte boundary for 8 bit transfers or cross the 128 Kbyte boundary for 16 bit transfers 11 72 Elan SC520 Microcontroller Register Set Manual GP DMA Controller Registers AMDA Master DMA Channel 5 Page GPDMA5PG Direct Mapped Address 008Bh 7 6 5 4 3 2 1 0
10. 7 6 5 4 3 2 1 0 Bit CH2_CNT 15 0 Reset 0 0 0 0 0 0 0 0 R W R W Register Description This register stores the current count values for PIT Channel 2 Bit Definitions Bit Name Function 7 0 CH2_CNT 15 0 16 bit Counter for Programmable Interval Timer Channel 2 This bit field provides read or write access to either the counter high byte only low byte only or low byte followed by high byte as defined by the CTR_RW_LATCH bit field of the PITMODECTL register see page 13 7 Either a latched or unlatched free running count value can be read from this bit field CH2_CNT A latched count can be read immediately after a counter latch command is issued via the PITCNTLAT register see page 13 10 After the one or two bytes of latched count data are read subsequent reads return the unlatched count A latched count can also be read immediately following a read back command issued via the PITRDBACK register in which the LCNT bit is 0 and the CNT2 bit is 1 see page 13 11 In this case also after the one or two bytes of latched count are read subsequent reads return the unlatched count Programming Notes If a read back command is issued by writing the PITRDBACK register with the LSTAT bit clear and the CNT2 bit set see page 13 11 the subsequent read to this address Port 0042h returns the PIT2STA register status byte see page 13 5 If a read back command is issued in which PITRDBACK register bits LSTA
11. 12 21 GPIRQ1 Interrupt Mapping 1 12 21 GPIRQ2 Interrupt Mapping 2 12 21 GPIRQ3 Interrupt Mapping 12 21 GPIRQ4 Interrupt Mapping 12 21 GPIRQ5 Interrupt Mapping 5 12 21 GPIRQ6 Interrupt Mapping 6 12 21 GPIRQ7 Interrupt Mapping 7 12 21 GPIRQ8 Interrupt Mapping 8 12 21 GPIRQQ Interrupt Mapping 9 12 21 GPIRQ10 Interrupt Mapping 12 21 Master PIC Interrupt Request 12 24 Master PIC In Service 12 25 Master PIC Initialization Control Word 1 MPICICW1 12 26 Master PIC Operation Control Word 2 MPICOCW2 12 28 Master PIC Operation Control Word 3 MPICOCWS 12 30 Master PIC Initialization Control Word 2 2 12 32 Master PIC Initialization Control Word 12 33 Master PIC Initialization Control Word 4 MPICICW4 12 35 Master PIC Interrupt Mask 1 5 12 36 Slave 2 PIC Interrupt Request S2PICIR
12. 1 11 66 General 2 2 11 67 General 3 11 68 Slave DMA Channel 0 Page 11 69 General 4 4 11 70 Master DMA Channel 6 Page 6 11 71 Master DMA Channel 7 Page 7 11 72 Master DMA Channel 5 Page 5 11 73 General 5 5 11 74 General 6 11 75 General 7 7 11 76 General 8 8 11 77 Master DMA Channel 4 Memory Address GPDMA4MAR 11 78 Master DMA Channel 4 Transfer Count GPDMA4TC 11 79 Master DMA Channel 5 Memory Address GPDMA5MAR 11 80 Master DMA Channel 5 Transfer Count GPDMABTO 11 81 Master DMA Channel 6 Memory Address GPDMA6MAR 11 82 Master DMA Channel 6 Transfer Count GPDMAGTO 11 83 Master DMA Channel 7 Memory Address GPDMA7MAR 11 84 Master DMA Channel 7 Transfer Count GPDMA7TC 11 85 Master DMA Channel 4 7 Status 11 86 Master DMA Channel 4 7 Control
13. 7 6 5 4 3 2 1 0 Bit MASTR CBP 7 0 Reset x x x x x x x x R W W Register Description This register channel provides a mechanism to adjust the byte pointer to the low byte of the memory address and transfer count registers for Channels 4 7 Bit Definitions Bit Name Function 7 0 MASTR_CBP Master DMA Clear Byte Pointer 7 0 The DMA controller s 16 bit memory address and terminal count registers are accessed by writing or reading consecutive 8 bit values to the same direct mapped I O address A single byte pointer is used across the master DMA controller to determine which byte is accessed if any of these 16 bit registers is read or written Any access to one of these registers toggles the byte pointer between the low and high bytes A write of any data to this bit field MASTR CBP clears the byte pointer so that the next memory address or transfer count register access is to the low byte Programming Notes lan SC520 Microcontroller Register Set Manual 11 93 AMD GP DMA Controller Registers Master DMA Controller Reset MSTDMARST Direct Mapped I O Address OODAh 7 6 5 4 3 2 1 0 Bit MASTR RST 7 0 Reset 0 0 0 0 0 0 0 0 R W W Register Description This register provides a reset mechanism for Channels 4 7 Bit Definitions Bit Name Function 7 0 MASTR RST Master DMA Controller Reset 7 0 A write of any data to this address resets the DMA controller to t
14. This register provides a mask or unmask capability for the DMA request signal to each of Channels 0 3 Bit Definitions Bit 7 3 1 0 Name Reserved CHMASK MSKSEL 1 0 Programming Notes The same DMA channel masks can be controlled via DMA registers SLDMAMSK SLDMAMSKRST see page 11 60 and SLDMAGENMSK see page 11 61 Before masking an active DMA channel software must ensure that the DMA request is deasserted Masking an active channel while it is being granted might cause the system to hang 11 54 Function Reserved This bit field should be written to 0 for normal system operation DMA Channel Mask 0 Clear the mask bit for the channel selected by the MSKSEL bit field 1 2 Set the mask bit for the channel selected by the MSKSEL bit field If the AINIT bit is 0 in the SLDMAMODE register see page 11 55 the mask bit is set internally when the corresponding channel reaches the end of its transfer count If the AINIT bit is 1 the mask bit remains clear when the transfer ends DMA Channel Mask Select This bit field selects the DMA channel that is to latch the CHMASK bit internally to mask or unmask the DMA request signal into the specified DMA channel 00 Mask or unmask DMA Channel 0 per the CHMASK bit 01 Mask or unmask DMA Channel 1 per the CHMASK bit 10 Mask or unmask DMA Channel 2 per the CHMASK bit 11 Mask or unmask DMA Channel 3 per the CHMASK bit Elan SC520 Microcontrol
15. Register Description This register is used to control the functionality and modes of operation of GP Timer 2 Bit Definitions Bit 15 14 Name ENB P_ENB_WR Elan SC520 Microcontroller Register Set Manual Function GP Timer 2 Enable 0 GP Timer 2 is inhibited from counting 1 GP Timer 2 counting is enabled If GP Timer 2 was previously enabled via setting the ENB bit and is operating and then software clears the ENB bit by writing a 0 then GP Timer 2 is inhibited from counting but is not reset The various timer status bits also remain stable In this scenario setting this ENB bit again causes the timer to continue from the state that it was in just prior to being disabled This bit can only be modified set or cleared via software if the bit of this register is set i e written as 1 during the same write cycle access to this register The ENB bit is automatically cleared by hardware under certain circumstances if noncontinuous mode is selected See the CONT_CMP bit description on page 14 16 GP Timer 2 Permit Enable Bit Write 0 Software cannot modify the ENB bit in this write cycle 1 Software can modify the ENB bit in this write cycle This bit allows selective software modifications of the ENB bit When the P WR bit is set during a write cycle access to this register the ENB bit can be modified in that same write cycle When the P ENB Wh bit is written as a 0 during a w
16. 7 6 5 4 3 2 1 0 Bit GP_WR_WIDTH 7 0 Reset 0 0 0 0 0 0 0 0 R W R W Register Description This register is used to program the pulse width for the write strobes GPIOWR and GPMEMWR Bit Definitions Bit Name Function 7 0 GP_WR_ Signal Width for GPIOWR and GPMEMWR WIDTH 7 0 This field adjusts the signal pulse width time of the GP bus write strobes The resolution of this parameter is one internal 33 MHz clock period The width used is GP WR WIDTH 1 internal clock periods i e if GP WR WIDTH is 0 the pulse is one clock period wide Programming Notes Figure 10 1 on page 10 7 shows the relationships between the various adjustable GP bus timing parameters 10 12 Elan SC520 Microcontroller Register Set Manual General Purpose Bus Controller Registers GP Write Offset GPWROFF AMD Memory Mapped MMCR Offset COEh 7 6 5 4 3 2 1 0 Bit GP WR OFF 7 0 Reset 0 0 0 0 0 0 0 0 R W R W Register Description This register is used to program the offset from beginning of a GP bus cycle for GPIOWR and GPMEMWR Bit Definitions Bit Name 7 0 GP_WR_OFF 7 0 Programming Notes Function Offset Time for GPIOWR and GPMEMWR This field adjusts the offset time of the GP bus write strobes The resolution of this parameter is one internal 33 MHz clock period The offset time used is GP_WR_OFF 1 internal clock periods i e if GP_WR_OFF is 0
17. Register Description This register provides address bits A15 A0 of the next memory address for Channel 5 in buffer chaining mode Bit Definitions Bit Name Function 15 0 DMA5_NXT_ DMA Channel 5 Next Address Low ADR 15 0 This bit field provides address bits A15 A0 of the next memory buffer to be used by Channel 5 in the buffer chaining mode Programming Notes The value of this register is ignored if buffer chaining mode is not enabled for this channel in the GPDMABCCTL register see page 11 21 Bit 0 of this register GPDMANXTADDLS5 is ignored for 16 bit mode transfers so the buffer address used is always even in 16 bit mode Software should ensure that 16 bit mode buffers always begin on an even word boundary 11 28 Elan SC520 Microcontroller Register Set Manual GP DMA Controller Registers AMDA GP DMA Channel 5 Next Address High GPDMANXTADDH5 Memory Mapped MMCR Offset DAGh 15 14 13 12 11 10 9 8 Bit Reserved DMAS_NXT_ADR 27 24 Reset 0 0 0 0 0 0 0 0 R W RSV R W 7 6 5 4 3 2 1 0 Bit DMAS_NXT_ADR 23 16 Reset 0 0 0 0 0 0 0 0 R W R W Register Description This register provides address bits A27 A16 of the next memory address for Channel 5 in buffer chaining mode Bit Definitions Bit Name Function 15 12 Reserved Reserved This bit field should be written to 0 for normal system operation 11 0 DMA5 _ DMA Channel 5 Next
18. Trailing edge ring indicator TERI Delta data set ready DDSR Delta clear to send DCTS Receiver line status UARTxLSR Break indicator BI page 18 21 Framing error FE Parity error PE Overrun error OE Transmitter holding register Transmit holding register 16450 empty compatible mode or transmitter FIFO 16550 compatible mode empty Received data available Data ready 16450 compatible mode FIFO trigger level reached 16550 compatible mode FIFO time out FIFO time out 16550 compatible mode Notes 1 Before any UART interrupt is enabled the corresponding UARTxMAP register see page 12 21 must be configured to route the interrupt to the appropriate interrupt request level and priority 2 The OUT2 bit in the UARTxMCR register page 18 19 is used as a master control for UART interrupts The OUT2 bit must be set for UART interrupts to be generated Status bits can be read even when interrupts are disabled 3 If two of the interrupts enabled in the UARTXINTENB register are pending simultaneously the highest priority interrupt is iden tified in the INT ID bit field of the UARTXINTID register see page 18 13 4 There are no polled status bits for the FIFO trigger level and FIFO time out events These events are indicated by the INT ID bit field only see page 18 13 2 The Fa 2 en interrupt is enabled with the received data available interrupt by the ERDAI b
19. 7 6 5 4 3 2 1 0 Bit Reserved SRC RXTC ENB TXTC Reset 0 0 0 0 0 0 0 0 R W RSV R W R W R W Register Description This register is used to enable or disable the transmit and receive transfer count TC interrupt and also select from two internal baud rate clock sources Bit Definitions Bit Name Function 7 3 Reserved Reserved This bit field should be written to 0 for normal system operation UART x Clock Source Enable 0 218 432 MHz 1 1 8432 MHz UART x Receive TC Interrupt Enable 0 Receive TC interrupt disable 1 Receive TC interrupt enable UART x Transmit TC Interrupt Enable 0 Transmit TC interrupt disable 1 Transmit TC interrupt enable 2 CLK SRC 1 RXTC 0 TXTC ENB Programming Notes Each UART can generate an interrupt when the transfer count GPTC signal associated with DMA transfers is asserted Table 18 5 on page 18 14 provides a summary of UART interrupt sources Elan SC520 Microcontroller Register Set Manual 18 3 UART Serial Port Registers Memory Mapped UART 1 General Status UART1STA MMCR Offset CC1h UART 2 General Status UART2STA MMCR Offset CC5h 7 6 5 4 3 2 1 0 Bit Reserved RXTC_DET TXTC_DET Reset 0 0 0 0 0 0 0 0 R W RSV R W R W Register Description This register shows the status of transfer count TC interrupt detected for the UART These bits are cleared by writing a 1 to them
20. Register Description This is a general purpose register Bit Definitions Bit Name Function 7 0 PORT8C 7 0 General Purpose R W Register Writes to this bit field are stored internally and propagated to the GP bus Reads from this bit field return the internal register value but are not propagated to the GP bus Programming Notes 11 74 Elan SC520 Microcontroller Register Set Manual GP DMA Controller Registers AMDA General 6 GPDMAGR6 Direct Mapped I O Address 008Dh 7 6 5 4 3 2 1 0 Bit PORT8D 7 0 Reset 0 0 0 0 0 0 0 0 R W R W Register Description This is a general purpose register Bit Definitions Bit Name Function 7 0 PORT8D 7 0 General Purpose R W Register Writes to this bit field are stored internally and propagated to the GP bus Reads from this bit field return the internal register value but are not propagated to the GP bus Programming Notes lan SC520 Microcontroller Register Set Manual 11 75 AMD General 7 GPDMAGR7 GP DMA Controller Registers Direct Mapped Address OO8Eh 7 6 5 4 3 1 0 Bit PORT8E 7 0 Reset 0 0 0 0 0 0 0 R W R W Register Description This is a general purpose register Bit Definitions Bit Name Function 7 0 PORT8E 7 0 General Purpose R W Register Writes to this bit field are stored internally and propagated to the GP bus Reads from this bit field retu
21. 0 Do not enter AMDebug technology mode on a CPU hard or soft reset 1 Enable the microprocessor to enter AMDebug technology mode on a CPU hard or soft reset Programmable Reset Enable 0 Programmable reset is disabled 1 Programmable reset is enabled Setting this bit enables programmable resets during which SDRAM configuration and SDRAM contents are preserved After this bit is set programmable resets can be generated by one of four sources m PRGRESET pin m Watchdog timer time out generated reset W Software write to the SYS RST bit with the PRG bit set in the same write m AMDebug technology system reset If this bit PRG RST is cleared the PRGRESET pin has no function The other programmable reset sources if generated initiate non SDRAM preserving system resets This bit is cleared by default so a toggle on the PRGRESET pin does not affect the ElanSC520 microcontroller Software GP Bus Reset Software can write to this bit to control the GPRESET pin and read back the pin s state The internal registers are not affected 0 Deassert GP bus reset 1 Assert GP bus reset Elan SC520 Microcontroller Register Set Manual 3 3 AMD Reset Generation Registers Bit Name Function 0 SYS_RST Software System Reset Software can write to this bit to trigger a one shot system reset The last value written is what is read 0 Do not cause a one shot system reset event to be generated 1 Caus
22. GP Chip Select Offset GPCSOFF page 10 9 GP Read Pulse Width GPRDW page 10 10 GP Read Offset GPRDOFF page 10 11 GP Write Pulse Width GPWRW page 10 12 GP Write Offset GPWROFF page 10 13 GPALE Pulse Width GPALEW page 10 14 GPALE Offset GPALEOFF Elan SC520 Microcontroller Register Set Manual page 10 15 10 1 General Purpose Bus Controller Registers GP Echo Mode GPECHO Memory Mapped MMCR Offset COOh 7 6 5 4 3 2 1 0 z GP_ECHO_ Bit Reserved ENB Reset 0 0 0 0 0 0 0 0 R W RSV R W Register Description This register is used to enable the GP bus echo mode Bit Definitions Bit Name Function 7 1 Reserved Reserved This field should be written to 0 for normal system operation 0 GP ECHO GP Bus Echo Mode Enable ENB This bit is used to enable the echo mode of GP bus 0 Echo mode is disabled 1 Echo mode is enabled Accesses to the microcontroller s integrated peripherals are echoed to the external GP bus Programming Notes While echo mode is enabled the access timing to internal peripherals is modified to adhere to the external timings programmed by the user This ensures that external peripherals connected to the GP bus still work as programmed by the user Thus it is possible that access to internal peripherals are slower in echo mode than in normal mode While echo mode is enabled the syst
23. Register Description This register provides bit fields that identify the AMD microcontroller and its version These values are hard wired in the device Different revisions of a product can be distinguished by the MAJORSTEP and MINORSTEFP bit fields Bit Definitions Bit Name 15 8 PRODUCT ID 7 0 7 4 5 3 0 3 0 3 0 Programming Notes Function Product Type of Elan SC520 Microcontroller 00000000 Identifies the product as the ElanSC520 microcontroller Major Stepping Level This bit field represents the microcontroller s major revision level A different MAJORSTEP bit field value is assigned to each major revision of the microcontroller Minor Stepping Level This bit field represents the microcontroller s minor revision level A larger MINORSTEP bit field value indicates a later revision within a particular MAJORSTEP bit field level The value that is read back depends on the current major and minor revision level of the specific lanSC520 microcontroller Contact your AMD representative for information about available revision levels 4 2 Elan SC520 Microcontroller Register Set Manual Am5 86 CPU Control CPUCTL AMD 5 86 CPU Registers Memory Mapped MMCR Offset 02h 7 6 5 4 3 2 1 0 CACHE Bit Reserved WR_MODE Reserved CPU SPD 1 0 Reset 0 0 0 0 1 R W RSV R W RSV R W Register Descriptio
24. Register Description This register is the first initialization register of the Slave 1 controller Bit Definitions Bit Name Function 7 5 Reserved Reserved This bit field should be written to 0 for normal system operation This I O address changes functions when read See the programming notes for this register S1PICICW1 on page 12 52 4 SLCT_ICW1 Initialization Control Word 1 Select Software must set this bit to 1 when writing this address Port 00AOh to access this register S1PICICW1 0 The write does not access this register S1PICICW1 Instead either the S1PICOCW2 register see page 12 53 or the S1PICOCWS register see page 12 55 is written depending on the state of bit 3 1 The write accesses this register S1PICICW1 Subsequent writes to Port 00A1h access additional initialization control words See the programming notes for this register S1PICICW1 page 12 52 3 LTIM Level Triggered Interrupt Mode This bit is the global interrupt mode selection for the Slave 1 PIC 0 Edge sensitive interrupt request detection 1 Level sensitive interrupt request detection If the S1_GINT_MODE bit in the PICICR register is set see page 12 5 the LTIM bit determines the interrupt mode for the Slave 1 PIC channels If the 1 GINT MODE bit is cleared the Slave 1 LTIM bit has no meaning and the Slave 1 PIC channel modes can be programmed individually via the SL1PICMODE register see page 12 8 2 ADI Address Interval 0 Interrup
25. 0 Input 1 Output PIO17 Input or Output Select This bit programs PIO17 as an input or output 0 Input 1 Output PIO16 Input or Output Select This bit programs PIO16 as an input or output 0 Input 1 Output AMD The PIOx_DIR bit for each PIO pin chooses if the pin is an input or output After reset all of the PIO signals are inputs with pullup or pulldown termination Before any PIO can be used as an output this register PIODIR31 16 must be programmed to change the PIO from an input to an output The PIOx DIR bit for a pin has no effect if the corresponding PIOx FNC bit is set in the PIOPFS31_ 16 register see page 20 5 If the PIOx FNC bit is set the corresponding pin is assigned its interface function not its PIO function Although software can perform a 32 bit access of MMCR offset C2Ah to set the direction for all 32 PIO pins with a single instruction the 32 bit access is split into two separate 16 bit accesses with the PIODIR15 0 register being accessed prior to the PIODIR31 16 register The two accesses are not simultaneous Elan SC520 Microcontroller Register Set Manual 20 15 AMD Programmable Input Output Registers PIO15 PIOO Data PIODATA15 0 Memory Mapped MMCR Offset C30h 15 14 13 12 11 10 9 8 gy PIO14 PIO13 PIO12_ PIO11 PIO10_ PIO9_ PIO8_ DATA DATA DATA DATA DATA DATA DATA DATA Reset 2 R W RW R W R W R W R W R W R W R W 7 6 5 4
26. 010 0 0110 1 0 S1PICOCW3 S1PICIR page 12 49 0 0 0 0 1 0 1 1 S1PICOCW3 S1PICISR page 12 50 0 0 0j 1 x X S1PICICW1 page 12 51 12 56 Elan SC520 Microcontroller Register Set Manual Programmable Interrupt Coniroller Registers AMD Slave 1 PIC Initialization Control Word 2 S1PICICW2 Direct Mapped I O Address 00A1h 7 6 5 4 3 2 1 0 Bit T7 T3 A10 A8 Reset x x x x x x x R W W W Register Description This register is the second initialization register of the Slave 1 controller Bit Definitions Bit Name Function 7 3 T7 T3 Bits 7 3 of Base Interrupt Vector Number for this PIC The PIC concatenates the T7 T3 bit field value to the 3 bit PIC interrupt request level in the bit 2 0 position to form the interrupt vector For example a PC AT compatible system bits T7 T3 for the Master PIC are programmed to 00001b so the Master PIC IRO channel generates an interrupt 08h vector PC AT IRQO and bits T7 T3 for the Slave 1 PIC are programmed to 01110b so the Slave 1 PIC IRO channel generates an interrupt 70h PC AT IRQ8 2 0 A10 A8 A10 A68 of Interrupt Vector This bit field should always be written to 0 for normal operation It is always 0 in a PC AT compatible system Programming Notes If the S2 bit in the MPICICWS3 register is cleared see page 12 34 then the Slave 1 controller is bypassed and programming this registe
27. 1 Set the PIO26 signal High PIO25 Set 0 No effect 1 Set the PIO25 signal High PIO24 Set 0 No effect 1 Set the PIO24 signal High Elan SC520 Microcontroller Register Set Manual Bit Name 7 PIO23 SET 6 PIO22 SET 5 PlO21 SET 4 PIO20 SET 3 19 SET 2 PIO18 SET 1 PIO17 SET 0 PlO16 SET Programming Notes Programmable Input Output Registers Function PIO23 Set 0 No effect 1 Set the PIO23 signal High PIO22 Set 0 No effect 1 Set the PIO22 signal High PIO21 Set 0 No effect 1 Set the PIO21 signal High PIO20 Set 0 No effect 1 Set the PIO20 signal High PIO19 Set 0 No effect 1 Set the PIO19 signal High PIO18 Set 0 No effect 1 Set the PIO18 signal High PIO17 Set 0 No effect 1 Set the PIO17 signal High PIO16 Set 0 No effect 1 2 Set the PIO16 signal High AMD Each PIOx SET bit is used to drive the corresponding PIO output High Writing a 1 to any bit of this register causes the corresponding PIO pin to be driven High if it is programmed to be an output via the corresponding PIOx DIR bit in the PIODIR31_16 register see page 20 14 Writing 1 to a pin s PIOx SET bit overrides any previous write to the pin s PIOx DATA or PIOx CLR bit see page 20 18 and page 20 26 Writing O to any bit in this register has no effect If a PIO pin is programmed to be an input or if the pin is programmed for its interface function
28. 7 6 5 4 3 2 1 0 Bit Reserved SFNM BUF_M S 1 0 Reset X X X X 0 0 0 1 R W RSV Register Description This register is the fourth initialization register of the Slave 1 controller Bit Definitions Bit Name Function 7 5 Reserved Reserved This bit field should be written to 0 for normal system operation This bit field is write only 4 SFNM Special Fully Nested Mode Enable 0 Normal nested mode 1 Special fully nested mode For PC AT compatibility this bit should be programmed as 0 3 2 BUF_M S 1 0 Buffered Mode and Master Slave Select 00 Non buffered mode 01 Non buffered mode 10 Buffered mode Slave 11 Buffered mode Master In the ElanSC520 microcontroller these PC AT compatible bits are internally fixed to OOb 1 Automatic EOI Mode 0 Normal EOI the interrupt handler must send an End of Interrupt command to the PIC s 1 Auto EOI the EOI is automatically performed after the second interrupt acknowledge signal from the CPU In the ElanSC520 microcontroller this bit is internally fixed to 0 The Slave 1 PIC and Slave 2 PIC do not support automatic EOI mode 0 PM Microprocessor Mode 0 2 8080 8085 mode 1 2 8086 mode In the lanSC520 microcontroller design this PC AT compatible bit is internally fixed to 1 Programming Notes The PIC s initialization control word 81PICICWX registers 1 4 must be programmed in sequence Writing to Port 00AO0h with b
29. BCD However the maximum value in either mode can be achieved by clearing this register PITOCNT to 0 All three PIT counters run at the same rate If the CLK PIN DIR bit is 0 in the CLKSEL register see page 20 9 the CLKTIMER input signal drives the PIT counters Otherwise the PIT counters run at 1 1892 MHz 13 2 Elan SC520 Microcontroller Register Set Manual Programmable Interval Timer Registers AMDA PIT Channel 1 Count PIT1CNT Direct Mapped I O Address 0041h 7 6 5 4 3 2 1 0 Bit CH1_CNT 15 0 Reset 0 0 0 0 0 0 0 0 R W R W Register Description This register stores the current count values for PIT Channel 1 Bit Definitions Bit Name Function 7 0 CH1_CNT 15 0 16 bit Counter for Programmable Interval Timer Channel 1 This bit field provides read or write access to either the counter high byte only low byte only or low byte followed by high byte as defined by the CTR_RW_LATCH bit field of the PITMODECTL register see page 13 7 Either a latched or unlatched free running count value can be read from this bit field CH1_CNT A latched count can be read immediately after a counter latch command is issued via the PITCNTLAT register see page 13 10 After the one or two bytes of latched count data are read subsequent reads return the unlatched count A latched count can also be read immediately following a read back command issued via the PITRDBACK register in which
30. Register Description This register is used to initialize and read back the RTC alarm second Bit Definitions Bit 7 0 ALM SECOND 7 0 Programming Notes Function RTC Alarm Second Software initializes the alarm seconds value for the RTC by writing data to this bit field in either binary or binary coded decimal BCD format The alarm seconds component of the RTC time can be read from this bit field Writing any value from COh to FFh to this bit field makes the seconds component of the alarm a wild card For example setting the hours minutes and seconds alarm registers to COh causes an RTC alarm event to be generated once per second The wild card based once per second alarm does not occur unless the hours and minutes alarm settings are also wild cards The RTC logic checks once per second to see if an alarm has occurred Valid values for this bit field range from 0 to 59d and all wild card values Software can suspend updating of the RTC via the SET bit in the RTCCTLB register see page 17 16 Software selects binary or BCD format via the DATE MODE bit in the RTCCTLB register Software can enable the RTC alarm as an interrupt via the ALM INT ENB bit in the RTCCTLB register The ALM INT bit in the RTCSTAC register indicates whether an alarm event has occurred see page 17 18 Elan SC520 Microcontroller Register Set Manual 17 5 Real Time Clock Registers RTC Current Minute RTCCURMIN I
31. 0 The IRO input to the Slave 2 PIC is not asserted 1 2 The IRO input is asserted This register S2PICIR is accessed by first writing a value of OAh to Port 0024h followed by a read back from Port 0024h If the S5 bit in the MPICICWS register is cleared see page 12 33 then the Slave 2 controller is bypassed and any interrupt requests latched in this register S2PICIR are not propagated to the CPU Elan SC520 Microcontroller Register Set Manual 12 37 AMD Slave 2 PIC In Service S2PICISR Programmable Interrupt Controller Registers Direct Mapped Address 0024h 7 6 5 4 3 2 1 0 Bit IS7 156 155 154 153 152 151 ISO Reset x x x x x x x x R W R Register Description This register indicates the Slave 2 interrupt priority levels that are being serviced Bit Definitions Bit Name Function 7 IS7 Interrupt Request 7 In Service 0 Interrupt request 7 is not being serviced 1 Interrupt request 7 is being serviced 6 IS6 Interrupt Request 6 In Service 0 Interrupt request 6 is not being serviced 1 Interrupt request 6 is being serviced 5 IS5 Interrupt Request 5 In Service 0 Interrupt request 5 is not being serviced 1 Interrupt request 5 is being serviced 4 IS4 Interrupt Request 4 In Service 0 Interrupt request 4 is not being serviced 1 Interrupt request 4 is being serviced 3 IS3 Interrupt Request 3 In Service 0 Interrupt request 3 is not being serviced
32. 00 No qualification Qualify the chip select with write strobes GPIOWR or GPMEMWR 10 Qualify the chip select with read strobes GPIORD or GPMEMRD 11 Qualify the Wi P select with both strobes GPIORD and GPIOWR or GPMEMRD and GPMEMW 5 4 GPCS2 RW GPCS2 Qualifier Selection 1 0 This field is used to qualify the GP bus chip select 2 with GPIORD GPIOWR GPMEMRD or GPMEMWR 00 No qualification Qualify the chip select with write strobes GPIOWR or GPMEMWR 10 Qualify the chip select with read strobes GPIORD or GPMEMRD 11 Qualify the an select with both strobes GPIORD and GPIOWR or GPMEMRD and GPMEMW 3 2 GPCS1_RW GPCS1 Qualifier Selection 1 0 This field is used to qualify the GP bus chip select 1 with GPIORD GPIOWR GPMEMRD or GPMEMWR 00 No qualification Qualify the chip select with write strobes GPIOWR or GPMEMWR 10 Qualify the chip select with read strobes GPIORD or GPMEMRD 11 Qualify t the Wi P select with both strobes GPIORD and GPIOWR or GPMEMRD and GPM 1 0 GPCSO RW GPCSO Qualifier Selection 1 0 This field is used to qualify the GP bus chip select 0 with GPIORD GPIOWR GPMEMRD GPMEMWR 00 No qualification Qualify the chip select with write strobes GPIOWR or GPMEMWR 10 Qualify the chip select with read strobes GPIORD or GPMEMRD 11 Qualify t ine nip select with both strobes GPIORD and GPIOWR or GPMEMRD and GPMEMWR
33. 1 11 21 Buffer Chaining Status 5 11 22 Buffer Chaining Interrupt Enable GPDMABSINTENB 11 24 Buffer Chaining Valid GPDMABCVAL 11 25 GP DMA Channel 3 Next Address Low GPDMANXTADDL3 11 26 GP DMA Channel 3 Next Address High GPDMANXTADDH3 11 27 GP DMA Channel 5 Next Address Low GPDMANXTADDLS5 11 28 GP DMA Channel 5 Next Address High GPDMANXTADDH5 11 29 GP DMA Channel 6 Next Address Low GPDMANXTADDLO 11 30 GP DMA Channel 6 Next Address High GPDMANXTADDH6O 11 31 GP DMA Channel 7 Next Address Low GPDMANXTADDL7 11 32 GP DMA Channel 7 Next Address High GPDMANXTADDH7 11 33 GP DMA Channel 3 Next Transfer Count Low GPDMANXTTCL3 11 34 GP DMA Channel Next Transfer Count High 11 35 GP DMA Channel 5 Next Transfer Count Low GPDMANXTTCL5 11 36 GP DMA Channel 5 Next Transfer Count High GPDMANXTTCH5 11 37 GP DMA Channel 6 Next Transfer Count Low GPDMANXTTCL6 11 38 GP DMA Channel 6 Next Transfer Count High GPDMANXTTCH6 11 39 GP DMA Channel 7 Next Transfer Count Low GPDMANXTTCL7 11 40 GP DMA Channel 7 Next Transfer Count High GPDMANXTTCH 7 11 41 Slave DMA Channel 0 Memory Address GPDMAOMAR 11 42 Slave DMA Channel 0 Transfer Count GPDMAOTC 11 43 Slave DMA Channel 1 Memory Add
34. 6 9 Host Bridge Master Interrupt Status HBMSTIRQSTA 6 12 Host Bridge Master Interrupt Address MSTINTADD 6 14 PCI Configuration Address PCICFGADR 6 15 PCI Configuration Data 6 17 Device Vendor ID 1 1 6 18 Status Command 6 19 Class Code Revision ID PCICCREVID 6 22 Header PCIHEADTYPE 6 23 Master Retry Time Out 6 24 CHAPTER 7 SDRAM CONTROLLER REGISTERS 7 1 FA OVOIVIOW i x petes ted uet daa Boni acne eius mir E tere as 7 1 2 RegisterS Cos ot a douce REI M bea w hp eG oes YI 7 1 SDRAM Control DRCCTL 0 0000 cee eee 7 2 SDRAM Timing Control 7 4 SDRAM Bank Configuration DRCCFG 7 5 SDRAM Bank 0 3 Ending Address DRCBENDADR 7 7 ECC Control ECCCTL 0 0 00 cee 7 9 ECC Status 5 7 10 ECC Check Bit Position 7 11 ECC Check Code Test ECCCKTEST 7 12 ECC Single Bit Error Address 5 7 14 ECC Multi Bit Error Address
35. Although software can perform a 32 bit access of MMCR offset C20h to select all 32 PIO pin functions with a single instruction the 32 bit access is split into two separate 16 bit accesses with the PIOPFS15 0 register being accessed prior to the PIOPFS31_16 register The two accesses are not simultaneous 20 6 Elan SC520 Microcontroller Register Set Manual Chip Select Pin Function Select CSPFS Bit Reset R W AMD Programmable Input Output Registers Memory Mapped MMCR Offset C24h 7 6 5 4 3 2 1 0 GPCS7_ GPCS6_ GPCS5_ GPCS4_ GPCS3_ GPCS2_ GPCS1_ Reserved SEL SEL SEL SEL SEL SEL SEL 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W RSV Register Description This register selects the pin functionality for pins that have general purpose chip selects GPCSx as their alternate function Bit Definitions Bit Name GPCS7_SEL GPCS6_SEL GPCS5_SEL GPCS4_SEL GPCS3_SEL GPCS2_SEL Function TMROUTO or GPCS7 Function Select This bit is used to make either the TMROUTO signal or the GPCS7 signal available on the pin The default on reset is TMROUTO 0 The pin is IMROUTO 1 2 The pin is GPCS7 TMROUT1 or GPCS6 Function Select This bit is used to make either the TMROUT1 signal or the GPCS6 signal available on the pin The default on reset is TMROUT1 0 The pin is TMROUT1 1 2 The pin is GPCS6 TMRINO or GPCS5 Function Select This bit is used to make either the TMR
36. Although software can perform a 32 bit access of MMCR offset C34h to set bits across all 32 PIO pins with a single instruction the 32 bit access is split into two separate 16 bit accesses with the PIOSET15 0 register being accessed prior to the PIOSETS31 16 register The two writes are not simultaneous Elan SC520 Microcontroller Register Set Manual 20 21 AMD Programmable Input Output Registers PIO31 PIO16 Set PIOSET31 16 Memory Mapped MMCR Offset C36h 15 14 13 11 10 9 8 Bit PIO31_ PIO30_ PIO29 __ PIO28 _ PIO27 PlO26 _ 25 _ PlO24 SET SET SET SET SET SET SET Reset X X x x x x x R W W W W W W W W 7 6 5 3 2 1 0 Bit PIO23 PIO22_ PlO21 PIO20 __ PIO19 PIO18 _ PIO17_ PIO16_ SET SET SET SET SET SET SET Reset x x x x x x x R W W W W W W W W Register Description This register is used to make the output level High selectively for pins PlO31 PIO16 Bit Definitions Bit Name 15 PIO31 SET 14 SET 13 PIO29 SET 12 PIO28 SET 11 PIO27 SET 10 26 SET 9 PIO25 SET 8 24 SET 20 22 Function PIO31 Set 0 No effect 1 Set the PIO31 signal High PIO30 Set 0 No effect 1 Set the PIO30 signal High PIO29 Set 0 No effect 1 Set the PIO29 signal High PIO28 Set 0 No effect 1 2 Set the PIO28 signal High PIO27 Set 0 No effect 1 Set the PIO27 signal High PIO26 Set 0 No effect
37. GP DMA Channel 3 Next Transfer Count High GPDMANXTTCHS page 11 35 GP DMA Channel 5 Next Transfer Count Low GPDMANXTTCL5 page 11 36 GP DMA Channel 5 Next Transfer Count High GPDMANXTTCH5 page 11 37 GP DMA Channel 6 Next Transfer Count Low GPDMANXTTCL6 page 11 38 GP DMA Channel 6 Next Transfer Count High GPDMANXTTCH6 page 11 39 GP DMA Channel 7 Next Transfer Count Low GPDMANXTTCL7 page 11 40 GP DMA Channel 7 Next Transfer Count High GPDMANXTTCH7 1 2 DIRECT MAPPED I O REGISTERS The direct mapped I O registers include the Configuration Base Address CBAR register and PC AT compatible peripheral registers such as the programmable interval timer PIT programmable interrupt controller PIC direct memory access DMA controller the real time clock RTC index and data registers the PCI configuration address and data registers two universal asynchronous receive transmit UART devices and miscellaneous control registers defined for compatibility The microcontroller s third PIC and the CBAR register are not found in PC AT compatible systems page 11 41 Table 1 2 lists all of the direct mapped I O registers in the lanSC520 microcontroller Table 1 2 Direct Mapped I O Registers Register Name Mnemonic I O Address Page Number Slave DMA 0000 000Fh Slave DMA Channel 0 Memory Address GPDMAOMAR 0000h page
38. Master Controller Write Posting Enable This bit enables Am5 86 CPU to PCI bus memory write cycles to be posted writes 0 Disables Am5 86 CPU to PCI bus write posting 1 Enables Am5 86 CPU to PCI bus write posting Note that this bit should not be set while the microcontroller is configured for non concurrent arbitration mode i e while the CNCR MODE ENB bit is clear in the SYSARBCTL register see page page 5 2 Reserved This bit field should be written to 0 for normal system operation This register is reset by a system reset The bits in this register are not affected by a PCI bus reset A PCI bus reset is initiated by setting the PCI RST bit Elan SC520 Microcontroller Register Set Manual Host Bridge Target Interrupt Control HBTGTIRQCTL Register Description PCI Bus Host Bridge Registers AMD Memory Mapped MMCR Offset 62h 15 14 13 12 11 10 9 8 Bs Rin T DLYTO T APER T DPER IRQ_SEL IRQ_SEL IRQ_SEL Reset 0 0 0 0 0 0 0 0 R W RSV R W R W R W 7 6 5 4 3 2 1 0 T DLYTO T APER T DPER MUR IRQ IRQ_ENB IRQ Reset 0 0 0 0 0 0 0 0 R W RSV R W R W R W This register contains bit fields for configuring and enabling host bridge target interrupts Bit Definitions Bit 15 11 10 7 3 Name Reserved T_DLYTO_ IRQ_SEL T APER IRQ SEL T_DPER_ IRQ_SEL Reserved T_DLYTO_ IRQ_ENB T_AP
39. Master PIC Operation Control Word 2 MPICOCW2 0020h page 12 28 Master PIC Operation Control Word 3 MPICOCWS 0020h page 12 30 Master PIC Initialization Control Word 2 MPICICW2 0021h page 12 32 Master PIC Initialization Control Word 3 MPICICWS 0021h page 12 33 Master PIC Initialization Control Word 4 MPICICWA 0021h page 12 35 Master PIC Interrupt Mask Slave 2 PIC MPICINTMSK 0021h 0024h 0025h page 12 36 Slave 2 PIC Interrupt Request S2PICIR 0024h page 12 37 Slave 2 PIC In Service S2PICISR 0024h page 12 38 Slave 2 PIC Initialization Control Word 1 S2PICICW1 0024h page 12 39 Slave 2 PIC Operation Control Word 2 S2PICOCW2 0024h page 12 41 Slave 2 PIC Operation Control Word 3 S2PICOCWS 0024h page 12 43 Slave 2 PIC Initialization Control Word 2 S2PICICW2 0025h page 12 45 Slave 2 PIC Initialization Control Word 3 S2PICICW3 0025h page 12 46 Slave 2 PIC Initialization Control Word 4 S2PICICW4 0025h page 12 47 Slave 2 PIC Interrupt Mask Programmable Interval Timer S2PICINTMSK 0025h 0040 0043h page 12 48 PIT Channel 0 Count PITOCNT 0040h page 13 2 PIT Channel 1 Count PIT1CNT 0041h page 13 3 PIT Channel 2 Count PIT2CNT 0042h page 13 4 PIT 0 Status PITOSTA 0040h page 13 5 PIT 1 Status PITISTA 00
40. Page Number lanSC520 Microcontroller Revision ID REVID Am5 86 CPU Control SDRAM Controller CPUCTL SDRAM Control DRCCTL page 7 4 SDRAM Timing Control DRCTMCTL page 7 4 SDRAM Bank Configuration DRCCFG page 7 5 SDRAM Bank 0 3 Ending Address DRCBENDADR page 7 7 ECC Control ECCCTL page 7 9 ECC Status ECCSTA page 7 10 ECC Check Bit Position ECCCKBPOS page 7 11 ECC Check Code Test ECCCKTEST page 7 12 ECC Single Bit Error Address ECCSBADD page 7 14 ECC Multi Bit Error Address SDRAM Buffer ECCMBADD page 7 15 SDRAM Buffer Control ROM Flash Controller BOOTCS Control BOOTCSCTL ROMCS 1 Control ROMCS1CTL ROMCS2 Control PCI Bus Host Bridge ROMCS2CTL Host Bridge Control HBCTL page 6 3 Host Bridge Target Interrupt Control HBTGTIRQCTL page 6 5 Host Bridge Target Interrupt Status HBTGTIRQSTA page 6 7 Host Bridge Master Interrupt Control HBMSTIRQCTL page 6 9 Host Bridge Master Interrupt Status HBMSTIRQSTA page 6 12 Host Bridge Master Interrupt Address System Arbitration MSTINTADD page 6 14 System Arbiter Control SYSARBCTL PCI Bus Arbiter Status PCIARBSTA System Arbiter Master Enable SYSARBMENB Arbiter Priority Control 1 2 ARBPRICTL Elan SC520 Microcontroller Register Set Manual Table 1
41. Programmable Interrupt Coniroller Registers Programming Notes If the S5 bit in the MPICICWS register is cleared see page 12 33 then the Slave 2 controller is bypassed and programming this register does not affect other registers Port 0024h provides access to different Slave 2 PIC registers based on the data that is written Table 12 7 provides a summary of bit patterns to write for access to each register Table 12 7 Slave 2 PIC I O Port 0024h Access Summary Same as Table 12 6 Bits Port 0024h Register Written Next Port 0024h Read Returns 6 5 4 3 2 1 0 0 x S2PICOCW2 12 41 1 x 0 S2PICOCWS page 12 43 0 0 0 0 1 0 1 0 S2PICOCWS3 S2PICIR page 12 37 0 0 0 0 1 0 1 1 S2PICOCWS3 S2PICISR page 12 38 0 0 01 x X S2PICICW1 page 12 39 12 42 Elan SC520 Microcontroller Register Set Manual Programmable Interrupt Coniroller Registers AMD Slave 2 PIC Operation Control Word S2PICOCW3 Direct Mapped Address 0024h 7 6 5 4 3 2 1 0 z SLCT_ Bit Reserved ESMM_SMM 1 0 ICW1 IS OCWS3 P RR RIS 1 0 Reset x 1 x x x R W RSV Register Description This register controls the PIC s mask and poll modes It also controls read access for the S2PICIR and S2PICISR registers see page 12 37 and page 12 38 and write acces
42. Programming Notes To ensure that the lower byte of this register GPDMA5TC is always accessed first software should precede any access to this register with a write to the MSTDMACBP register see page 11 93 to clear the master DMA byte pointer By default this channel is set up for PC AT compatibility 16 bit DMA transfers on the master DMA controller For 16 bit transfers each transfer is two bytes so a transfer count of FFFFh results in a transfer of 128 Kbytes The value in this register GPDMABTO can be used with the value in the GPDMAEXTTCS5 register see page 11 18 to allow counts of up to 16 M 16 777 216 transfers In PCI bus 2 2 compliant designs software must limit the length of GP bus DMA demand or block mode transfers Very large transfers could cause the PCI Host Bridge target controller to violate the 10 us memory write maximum completion time limit set in the PC Local Bus Specification Revision 2 2 lan SC520 Microcontroller Register Set Manual 11 81 AMD GP DMA Controller Registers Master DMA Channel 6 Memory Address GPDMAGMAR Direct Mapped Address 00C8h 7 6 5 4 3 2 1 0 Bit DMA6MAR 16 1 Reset X X X X X X X X R W R W Register Description This register contains bits 16 1 of the memory address for Channel 6 during DMA operation Bit Definitions Bit Name Function 7 0 DMA6MAR Lower 16 Bits of DMA Channel 6 Memory Address 16 1 This 8 bit field is
43. Software should set the SET bit to 1 before changing the DS ENB bit and then clear the SET bit afterward lan SC520 Microcontroller Register Set Manual 17 17 AMD RTC Status C RTCSTAC Real Time Clock Registers Address 70h 71h RTC Index OCh 7 6 5 4 _ ALM UPD_ Bit INT FLG NT FLG INT FLG INT FLG RgSeINed Reset 0 X X x R W R RSV Register Description The RTC Status C provides RTC interrupt status Bit Definitions Bit 7 6 5 17 18 Name INT_FLG PER_INT_FLG ALM_INT_FLG Function Interrupt Request Flag 0 The RTC interrupt request to the programmable interrupt controller PIC is driven inactive 1 2 When this bit transitions from 0 to 1 the RTC interrupt request to the PIC is driven active which generates a CPU interrupt if the RTC interrupt source is enabled at the PIC The INT FLG bit is set to 1 when any one or more of the PER INT FLG ALM INT or UPD INT bits transition from 0 to 1 while the corresponding enable bit is asserted in the RTCCTLB register see page 17 16 The INT FLG bit is also set to 1 if an RTC interrupt source enable bit is written to 1 when the associated flag bit is already asserted The INT FLG bit is cleared after read and is also cleared by an RTC only reset If the internal RTC is disabled via the DIS bit in the ADDDECCTL register see page 2 3 the internal signal associated wit
44. The same DMA channel masks can be controlled via DMA registers MSTDMAMSK see page 11 90 MSTDMAMSKRST see page 11 96 and MSTDMAGENMSK Before masking an active DMA channel software must ensure that the DMA request is deasserted Masking an active channel while it is being granted might cause the system to hang Elan SC520 Microcontroller Register Set Manual 11 97 AMDA GP DMA Controller Registers 11 98 Elan SC520 Microcontroller Register Set Manual 1 12 1 12 2 Table 12 1 CHAPTER re Ta AMD 1 PROGRAMMABLE INTERRUPT CONTROLLER REGISTERS OVERVIEW This chapter describes the programmable interrupt controller PIC registers of the ElanSC520 microcontroller The ElanSC520 microcontroller s programmable interrupt controller PIC consists of three industry standard controllers integrated with a highly programmable interrupt router The PIC register set includes two groups of registers 39 memory mapped configuration region MMCR registers are used to configure and control PIC functions specific to the ElanSC520 microcontroller i 28 direct mapped I O registers are used for industry standard PIC configuration control and status functions See the Elan SC520 Microcontroller User s Manual order 22004 for details about the interrupt controller Table 12 1 and Table 12 2 on page 12 2 list each type of PIC register in offset order with the corresponding description s page number REGISTERS Progr
45. Transmit Holding Register 16450 Compatible Mode or Transmitter FIFO 16550 Compatible Mode Empty 0 The transmitter still has data to place in the transmit shift register 1 In 16450 compatible mode the transmit holding register is ready to accept a new character In 16550 compatible mode the transmit FIFO is completely empty In 16450 compatible mode this bit is automatically reset by a write to the UARTXxTHR register see page 18 7 In 16550 compatible mode this interrupt is cleared when the transmit FIFO is written to This bit can be used to generate an interrupt if programmed to do so via the Interrupt Enable register Break Indicator 0 There is no break indication associated with the current character 1 In 16450 compatible mode this bit is set when the UART has detected that the sending UART has transmitted a break condition for a period longer than the time it takes to receive start data parity and stop bits In 16550 compatible mode this bit is set when an entire word start data parity stop that was received into the FIFO with break indication present is now at the top of the FIFO Only one break indication is loaded into the FIFO regardless of the duration of the break condition A new character is not loaded into the FIFO until the next valid start bit is detected This latched status bit is automatically cleared by a read from this register UARTxLSR Elan SC520 Microcontroller Register Set Manual
46. the offset time is one clock period Figure 10 1 on page 10 7 shows the relationships between the various adjustable GP bus timing parameters Elan SC520 Microcontroller Register Set Manual 10 13 General Purpose Bus Controller Registers GPALE Pulse Width GPALEW Memory Mapped MMCR Offset COFh 7 6 5 4 3 2 1 0 Bit GP_ALE_WIDTH 7 0 Reset 0 0 0 0 0 0 0 0 R W R W Register Description This register is used to program the signal width for GPALE Bit Definitions Bit Name Function 7 0 GP_ALE_ Signal Width for GPALE WIDTH 7 0 This field adjusts the signal pulse width time of the GPALE signal The resolution of this parameter is one internal 33 MHz clock period The width used is GP ALE WIDTH 1 internal clock periods i e if GP ALE WIDTH is 0 the pulse is one clock period wide Programming Notes Figure 10 1 on page 10 7 shows the relationships between the various adjustable GP bus timing parameters 10 14 Elan SC520 Microcontroller Register Set Manual General Purpose Bus Controller Registers GPALE Offset GPALEOFF AMD Memory Mapped MMCR Offset C10h 7 6 5 4 3 1 0 Bit GP ALE OFF 7 0 Reset 0 0 0 0 0 0 0 R W R W Register Description This register is used to program the offset from the beginning of a GP bus cycle for GPALE Bit Definitions Bit 7 0 GP ALE OFF 7 0 Programming Notes
47. 1 Interrupt request 3 is being serviced 2 IS2 Interrupt Request 2 In Service 0 Interrupt request 2 is not being serviced 1 Interrupt request 2 is being serviced 1 151 Interrupt Request 1 In Service 0 Interrupt request 1 is not being serviced 1 Interrupt request 1 is being serviced 0 ISO Interrupt Request 0 In Service Programming Notes 0 Interrupt request 0 is not being serviced 1 2 Interrupt request 0 is being serviced This register S2PICISR is accessed by first writing a value of OBh to Port 0024h followed by a read back from Port 0024h If the S5 bit in the MPICICWS3 register is cleared see page 12 33 then the Slave 2 controller is bypassed and interrupt requests latched are not serviced 12 38 Elan SC520 Microcontroller Register Set Manual AMD Programmable Interrupt Controller Registers Slave 2 PIC Initialization Control Word 1 S2PICICW1 Direct Mapped Address 0024h 7 6 5 4 3 2 1 0 z SLCT_ Bit Reserved ICW1 LTIM ADI SNGL IC4 Reset x x x x 1 0 R W RSV Register Description This register is the first initialization register of the Slave 2 controller Bit Definitions Bit Name Function 7 5 Reserved Reserved This bit field should be written to 0 for normal system operation This I O address changes functions when read See the programming notes for this register S2PICICW1 on page 12 40 4 SLCT_ICW1 Initialization
48. 1 Interrupt request 6 is being serviced 5 IS5 Interrupt Request 5 In Service 0 Interrupt request 5 is not being serviced 1 Interrupt request 5 is being serviced 4 IS4 Interrupt Request 4 In Service 0 Interrupt request 4 is not being serviced 1 Interrupt request 4 is being serviced 3 IS3 Interrupt Request 3 In Service 0 Interrupt request 3 is not being serviced 1 Interrupt request 3 is being serviced 2 IS2 Interrupt Request 2 In Service 0 Interrupt request 2 is not being serviced 1 Interrupt request 2 is being serviced 1 151 Interrupt Request 1 In Service 0 Interrupt request 1 is not being serviced 1 Interrupt request 1 is being serviced 0 ISO Interrupt Request 0 In Service Programming Notes 0 Interrupt request 0 is not being serviced 1 Interrupt request 0 is being serviced This register S1PICISR is accessed by writing a value of OBh to Port 00AOh followed by a read back from Port 00 If the S2 bit in the MPICICWS3 register is cleared see page 12 34 then the Slave 1 controller is bypassed and interrupt requests latched are not serviced 12 50 Elan SC520 Microcontroller Register Set Manual AMD Programmable Interrupt Controller Registers Slave 1 PIC Initialization Control Word 1 S1PICICW1 Direct Mapped Address 00AOh 7 6 5 4 3 2 1 0 z SLCT_ Bit Reserved ICW1 LTIM ADI SNGL IC4 Reset x x x x 1 0 R W RSV
49. 1 wait state 10 2 wait states 11 wait states Elan SC520 Microcontroller Register Set Manual ROM Flash Controller Registers AMDA Bit Name Function 3 Reserved Reserved This bit field should be written to 0 for normal system operation 2 0 FIRST_DLY BOOTCS Device Delay for First Access 2 0 This bit field is used to configure the number of wait states for the first access to the ROM and for subsequent accesses if the MODE bit is 0 000 0 wait states 001 1 wait state 010 2 wait states 011 3 wait states 100 4 wait states 101 5 wait states 110 6 wait states 111 7 wait states Programming Notes The device attached to the BOOTCS chip select signal is used as the boot device Therefore upon reset this device s DGP and WIDTH bit field values must be delivered to the ROM controller via the CFG2 CFGO pinstraps For all other ROM devices this configuration information is programmed by the initialization software Elan SC520 Microcontroller Register Set Manual 9 3 AMD ROM Flash Controller Registers ROMCS1 Control ROMCS1CTL Memory Mapped MMCR Offset 54h 15 14 13 12 11 10 9 8 Bit Reserved DGP WIDTH 1 0 MODE Reserved Reset 0 0 0 0 0 0 0 0 R W RSV R W R W R W RSV 7 6 5 4 3 2 1 0 Bit Reserved SUB DLY 1 0 Reserved FIRST DLY 2 0 Reset 0 0 1 1 0 1 1 1 R W RSV R W RSV R W Register Description This register conta
50. 10 No significance 11 2 16550 compatible mode is enabled The FIFO mode is selected by the FIFO_ENB bit in the UARTxFCR register see page 18 16 5 4 Reserved Reserved These bits always read back 00b 18 12 Elan SC520 Microcontroller Register Set Manual Bit Name Function 3 1 INT_ID 2 0 UART Serial Port Registers Interrupt Identification Bit Field AMD The INT D bit field indicates only the highest priority interrupt as defined in Table 18 4 when two interrupt sources are pending simultaneously When the interrupt source is cleared a subsequent read from the INT ID bit field returns the next highest priority interrupt source The INT D bit field has no meaning if the INT NOT bit is 1 Table 18 4 INT ID Bit Field UART Interrupt Identification and Priority Description Modem status Identification Priority Fourth Lowest Transmit holding register empty 16540 compatible mode Transmit Third FIFO empty 16550 compatible mode Second Received data available 16540 compatible mode Receiver FIFO trigger 16550 compatible mode Receive line status First Highest Not used Not used FIFO time out Not used Second In 16450 compatible mode the INT_ID 2 bit always reads back 0 A receiver FIFO trigger occurs when the data in the receive FIFO fills to the level set in the RFRT bit field of the UARTxFCR register see page 18 15 A FIFO ti
51. 2 Reserved Programming Notes Function Reserved This bit field should be written to 0 for normal system operation ECC Multi Bit Error Address This register contains the physical address bits 27 2 of the location where a multi bit error occurred The address is captured upon the detection of a multi bit error and the bit field is inhibited from capturing subsequent error addresses until the MBIT ERR bit in the ECCSTA register is cleared by writing a 1 see page 7 10 Note This register does not include byte enables BE from the requesting master therefore only doubleword resolution is provided in the indication Reserved This bit field should be written to 0 for normal system operation Elan SC520 Microcontroller Register Set Manual 7 15 SDRAM Controller Registers 7 16 Elan SC520 Microcontroller Register Set Manual CHAPTER ee Ta AMD WRITE BUFFER AND READ BUFFER REGISTER 8 1 OVERVIEW This chapter describes the write buffer and read buffer register of the lanSC520 microcontroller The write buffer and read buffer are two buffering techniques integrated in the lanSC520 microcontroller to increase SDRAM system performance Although both of these features are tightly integrated with the SDRAM controller the write buffer and the read buffer s read ahead feature can be independently enabled via the SDRAM Buffer Control DBCTL register The write buffer and read buffer register set consists
52. Bits 15 8 of the channel s transfer count can be read from or written to this bit field immediately after transfer count bits 7 0 are read from or written to this bit field The actual number of transfers is one more than the programmed transfer count value Programming Notes To ensure that the lower byte of this register GPDMA1TC is always accessed first software should precede any access to this register with a write to the SLDMACBP register see page 11 57 to clear the slave DMA byte pointer In PCI bus 2 2 compliant designs software must limit the length of GP bus DMA demand or block mode transfers Very large transfers could cause the PCI Host Bridge target controller to violate the 10 us memory write maximum completion time limit set in the PC Local Bus Specification Revision 2 2 lan SC520 Microcontroller Register Set Manual 11 45 GP DMA Controller Registers Slave DMA Channel 2 Memory Address GPDMA2MAR Direct Mapped I O Address 0004h 7 6 5 4 3 2 1 0 Bit DMA2MAR 15 0 Reset X X X X X X X X R W R W Register Description This register contains bits 15 0 of the memory address for Channel 2 during DMA operation Bit Definitions Bit Name Function 7 0 DMA2MAR Lower 16 Bits of DMA Channel 2 Memory Address 15 0 This 8 bit field is used in two successive I O accesses to read or write the channel s memory address bits 15 0 Bits 7 0 of the channel s memor
53. DSRx signal in UARTxMCR register 18 19 18 20 in UARTxMSR register 18 23 18 24 DTR bit field 18 20 DTRx signal 18 19 18 20 E ECC check bit and data bit positions figure 7 11 ECC Check Bit Position register 7 11 ECC Check Code Test register 7 12 ECC check codes and associated data table 7 13 ECC Control register 7 9 ECC Data Bit Position bit field 7 11 ECC Enable for All Four Banks bit field 7 9 ECC Interrupt Mapping register 12 19 ECC Multi Bit Error Address bit field 7 15 ECC Multi Bit Error Address register 7 15 ECC NMI Enable bit field 12 19 ECC Single bit Error Address bit field 7 14 ECC Single Bit Error Address register 7 14 ECC Status register 7 10 CHK POS bit field 7 11 ECC bit field 7 9 ECC IRQ MAP bit field 12 20 ECC NMI ENB bit field 12 19 ECCCKBPOS register 7 11 ECCCKTEST register 7 12 ECCCTL register 7 9 ECCMAP register 12 19 ECCMBADD register 7 15 ECCSBADD register 7 14 ECCSTA register 7 10 Elan SC520 Microcontroller Revision ID register 4 2 EMSI bit field 18 11 Enable Bad ECC Check Bits bit field 7 12 ENABLE bit field in CBAR register 2 9 in PCICFGADR register 6 15 Index 6 Index Enable bit field in CBAR register 2 9 in PCICFGADR register 6 15 Enable Modem Status Interrupt bit field 18 11 Enable Multi Bit Interrupt bit field 7 9 Enable Received Data Available Interrupt bit field 18 1 1 Enable Receiver Line Status Inte
54. GP DMA Controller Registers Direct Mapped Address 00D4h 7 6 5 4 3 2 1 0 Bit Reserved CHMASK MSKSEL 1 0 Reset 0 0 0 0 0 X X X R W RSV W W This register provides a mask or unmask capability for the DMA request signal to each of Channels 4 7 Bit Definitions Bit 7 3 1 0 Name Reserved CHMASK MSKSEL 1 0 Programming Notes The same DMA channel masks can be controlled via DMA registers MSTDMAMSK MSTDMAMSKRST see page 11 96 and MSTDMAGENMSK see page 11 97 Before masking an active DMA channel software must ensure that the DMA request is deasserted Masking an active channel while it is being granted might cause the system to hang 11 90 Function Reserved This bit field should be written to 0 for normal system operation DMA Channel Mask 0 Clear the mask bit for the channel selected by the MSKSEL bit field 1 Set the mask bit for the channel selected by the MSKSEL bit field If the AINIT bit is 0 in the MSTDMAMODE register see page 11 91 the mask bit is set internally when the corresponding channel reaches the end of its transfer count If the AINIT bit is 1 the mask bit remains clear when the transfer ends DMA Channel Mask Select This bit field selects the DMA channel that is to latch the CHMASK bit internally to mask or unmask the DMA request signal into the specified DMA channel 00 Mask or unmask DMA Channel 4 per the CHMASK bit 01
55. Programming Notes When this register GPCSQUAL is used to qualify a GP bus chip select signal the external timing relationship between the qualifier and the chip select is not guaranteed For example deassertion of the chip select signal could precede the qualifiers deassertion on the external GP bus If a single qualifier type only read or only write is used to qualify a GP bus chip select signal the corresponding chip select is not asserted for accesses of the other type For example if the GPCSO_RW bit field is set to 01b to qualify GP Chip Select 0 with write strobes only GP Chip Select 0 is not asserted for read accesses Before using of the GPCS7 GPCS 1 signals software must set the corresponding GPCSx SEL bit in the CSPFS register see page 20 7 Before using the GPCSO signal software must set the PIO27 SEL bit in the PIOPFSS31 16 register see page 20 5 10 6 Elan SC520 Microcontroller Register Set Manual General Purpose Bus Controller Registers AMDA GP Chip Select Recovery Time GPCSRT Memory Mapped MMCR Offset CO8h 7 6 5 4 3 2 1 0 Bit GPCS RECOVR 7 0 Reset 0 0 0 0 0 0 0 0 R W R W Register Description This register is used to program the chip select recovery time for all GP bus cycles Bit Definitions Bit Name Function 7 0 Chip Select Recovery Time GPCS_ RECOVR 7 0 This field adjusts the recovery time for all the GP bus chip selects The resolut
56. Real Time Clock Registers Address 70h 71h RTC Index O5h 7 6 5 4 3 2 1 0 ALM_ Bit ALM HOUR 6 0 Reset X X X X X X X X R W RW R W This register used to initialize and read back the RTC alarm hour Bit Definitions Bit Name ALM_ AM PM ALM HOUR 6 0 Programming Notes Software selects 12 hour or 24 hour mode via the HOUR MODE SEL bit inthe RTCCTLB register see page 17 17 Software can suspend updating of the RTC via the SET bit in the RTCCTLB register Software selects binary or BCD format via the DATE_MODE bit in the RTCCTLB register Software can enable the RTC alarm as an interrupt via the ALM_INT_ENB bit in the RTCCTLB register The ALM_INT_FLG bit in the RTCSTAC register indicates whether an alarm event has occurred see page 17 18 Function RTC Alarm AM PM Indicator If the HOUR_MODE_SEL bit is 0 in the RTCCTLB register see page 17 17 the ALM AM PM bit is used to indicate whether the alarm hour is AM or PM 0 The alarm hour is AM 12 hour mode only In 24 hour mode always clear this bit to 0 unless programming a wild card see the ALM HOUR bit description 1 The alarm hour is PM 12 hour mode only The RTC logic checks this bit field once per second RTC Alarm Hour Software initializes the alarm hour value for the RTC by writing data to this bit field in either binary or binary coded decimal BCD format The alarm hours compone
57. Register Description This register is the second initialization register of the Master controller Bit Definitions Bit Name Function 7 3 T7 T3 Bits 7 3 of Base Interrupt Vector Number for this PIC The PIC concatenates the T7 T3 bit field value to the 3 bit PIC interrupt request level in the bit 2 0 position to form the interrupt vector For example a PC AT compatible system bits T7 T3 for the Master PIC are programmed to 00001b so the Master PIC IRO channel generates an interrupt 08h vector PC AT IRQO and bits T7 T3 for the Slave 1 PIC are programmed to 01110b so the Slave 1 PIC IRO channel generates an interrupt 70h PC AT IRQ8 2 0 A10 A8 A10 A68 of Interrupt Vector This bit field should be written to 0 for normal operation It is always 0 ina PC AT compatible system Programming Notes The PIC s initialization control word MPICICWx registers 1 4 must be programmed in sequence Writing to Port 0020h with bit 4 1 causes the MPICICW1 register to be written and also resets the PIC s internal state machine and the internal MPICICWXx register pointer Then MPICICWX registers 2 4 can be programmed by sequential writes to Port 0021h Each time Port 0021h is written to following the write to MPICICW1 the internal register pointer points to the next MPICICWx register MPICICW1 and MPICICW2 must always be programmed The MPICICW3 register is skipped if the SNGL bit in MPICICW1 is 1 The MPICICW4 register is ski
58. Reset x 1 x x x R W RSV Register Description This register controls the PIC s mask and poll modes It also controls read access for the S1PICIR and S1PICISR registers see page 12 49 and page 12 50 and write access for this register S1PICOCWS3 and forthe S1PICOCW2 and S1PICICW1 registers see page 12 53 and page 12 51 Bit Definitions Bit Name 7 Reserved 6 5 ESMM_SMM 1 0 4 SLCT_ICW1 3 IS OCWS 1 0 RIS 1 0 Function Reserved This bit field should be written to 0 for normal system operation This I O address changes functions when read See the programming notes for this register S1PICICW1 on page 12 56 Special Mask Mode 00 No operation 01 No operation 10 Reset special mask 11 Set special mask Initialization Control Word 1 Select Software must clear this bit to 0 when writing this address Port OOAOh to access either this register S1PICOCWS or the S1PICOCW2 register 0 The write accesses either this register S1PICOCWS3 or the S1PICOCW2 register see page 12 53 depending on the state of bit 3 1 The write accesses the S1PICICW1 register see page 12 51 Access is OCW3 Software must set this bit S OCW3 and clear SLCT_ICW1 when writing this address Port OOAOh to access this register S1PICOCW3 0 The write accesses the S1PICOCW2 register see page 12 53 if the SLCT_ICW1 bit is cleared 1 The wri
59. SC520 Microcontroller Register Set Manual GP DMA Controller Registers AMDA GP DMA Channel 6 Next Address High GPDMANXTADDH6 Memory Mapped MMCR Offset DAAh 15 14 13 12 11 10 9 8 Bit Reserved DMA6_NXT_ADR 27 24 Reset 0 0 0 0 0 0 0 0 R W RSV R W 7 6 5 4 3 2 1 0 Bit DMA6_NXT_ADR 23 16 Reset 0 0 0 0 0 0 0 0 R W R W Register Description This register provides address bits A27 A16 of the next memory address for Channel 6 in buffer chaining mode Bit Definitions Bit Name Function 15 12 Reserved Reserved This bit field should be written to O for normal system operation 11 0 DMA6 _ DMA Channel 6 Next Address High ADR 27 16 This bit field provides address bits A27 A16 of the next memory buffer to be used by Channel 6 in the buffer chaining mode Programming Notes The value of this register is ignored if buffer chaining mode is not enabled for this channel in the GPDMABCCTL register see page 11 21 lan SC520 Microcontroller Register Set Manual 11 31 AMDA GP DMA Controller Registers GP DMA Channel 7 Next Address Low GPDMANXTADDL7 Memory Mapped MMCR Offset DACh 15 14 13 12 11 10 9 8 Bit DMA7 NXT ADR 15 8 Reset 0 0 0 0 0 0 0 0 R W R W 7 6 5 4 3 2 1 0 Bit DMA7 NXT ADR 7 0 Reset 0 0 0 0 0 0 0 0 R W R W Register Description This register provides
60. SWTMRMICRO C62h page 15 3 Software Timer Configuration General Purpose Timers SWTMRCFG C64h C70 C8Eh page 15 4 GP Timers Status GPTMRSTA C70h page 14 2 GP Timer 0 Mode Control GPTMROCTL C72h page 14 3 GP Timer 0 Count GPTMROCNT C74h page 14 6 GP Timer 0 Maxcount Compare A GPTMROMAXCMPA C76h page 14 7 GP Timer 0 Maxcount Compare B GPTMROMAXCMPB C78h page 14 8 GP Timer 1 Mode Control GPTMR1CTL C7Ah page 14 9 GP Timer 1 Count GPTMR1CNT C7Ch page 14 12 GP Timer 1 Maxcount Compare A GPTMR1MAXCMPA C7Eh page 14 13 GP Timer 1 Maxcount Compare B GPTMR1MAXCMPB C80h page 14 14 GP Timer 2 Mode Control GPTMR2CTL C82h page 14 15 GP Timer 2 Count GPTMR2CNT C84h page 14 17 GP Timer 2 Maxcount Compare A Watchdog Timer GPTMR2MAXCMPA C8Eh CBO CB6h page 14 18 Watchdog Timer Control WDTMRCTL CBOh page 16 2 Watchdog Timer Count Low WDTMRCNTL CB2h page 16 4 Watchdog Timer Count High WDTMRCNTH CB4h page 16 5 Reserved CB6h 1 4 Elan SC520 Microcontroller Register Set Manual Configuration Register Overview Table 1 1 Register Name UART Serial Ports Mnemonic MMCR Offset CCO CC6h AMD Memory Mapped Configuration Region MMCR Registers By Offset Continued Page Number UART 1 General Control UAR
61. 0 OPMODE_SEL SDRAM Operation Mode Select 2 0 These commands are used in the SDRAM initialization and detection algorithm 000 Normal SDRAM mode 001 NOP command enabled 010 CPU to SDRAM cycles are converted to All Banks Precharge commands 011 CPU to SDRAM cycles are converted to a Load Mode Register command The data to be loaded is driven on MA12 MAO 100 Auto refresh enabled 101 111 Reserved When specifying NOP All Banks Precharge Load Mode Register or Auto Refresh commands the command is not actually applied to the SDRAM devices until a CPU access to SDRAM occurs either a read or write cycle The specified command is issued to the SDRAM devices during the CPU access rather than the typical SDRAM read or write access Before using a write cycle to apply any of these SDRAM commands make sure the WB_ENB bit is clear in the DBCTL register see page 8 3 Because the command is not issued to the SDRAM until the CPU accesses SDRAM code executing out of ROM must specifically access SDRAM after selecting a command in the OPMODE_SEL bit field to properly configure the SDRAM device The Load Mode Register command must be issued to the SDRAM for the setting of the CAS LAT bit of the DRCTMCTL register to take effect see page 7 4 In addition to setting the CAS latency as programmed in the CAS_LAT bit the following fixed parameters are also written to the SDRAM device s mode register when a Load Mode Register command
62. 2 3 RTC Interrupt Mapping register 12 21 RTC Status C register 17 18 RTC Status D register 17 20 RTC CMOS Data Port bit field 17 3 RTC CMOS RAM Data Port register 17 3 RTC CMOS RAM Index bit field 17 2 RTC CMOS RAM Index register 17 2 RTC_CMOS_REG_X bit field 17 21 RTC_DIS bit field 2 3 RTC_VRT bit field 17 20 RTCALMHR register 17 9 RTCALMMIN register 17 7 RTCALMSEC register 17 5 RTCCMOS register 17 21 RTCCTLA register 17 14 RTCCTLB register 17 16 RTCCURDOM register 17 11 RTCCURDOW register 17 10 RTCCURHR register 17 8 RTCCURMIN register 17 6 RTCCURMON register 17 12 RTCCURSEC register 17 4 RTCCURYR register 17 13 RTCDATA register 17 3 RTCIDX register 17 2 RTCMAP register 12 21 RTCSTAC register 17 18 RTCSTAD register 17 20 RTG bit field in GPTMROCTL register 14 4 in GPTMR1CTL register 14 10 RTS bit field 18 20 RTSx signal 18 19 18 20 RW bit field 13 5 Index rxdackx internal signal 11 8 11 9 RXDRQx Channel Mapping bit field 11 8 11 9 rxdrqx internal signal 11 8 11 9 18 5 18 15 RXDRQx_CHSEL bit field 11 8 11 9 RXTC_DET bit field 18 4 RXTC_ENB bit field 18 3 S S DVSL TIM bit field 6 20 S ABT bit field 6 20 S1PICICW1 register 12 51 S1PICICW2 register 12 57 S1PICICWS register 12 58 S1PICICWA register 12 59 S1PICINTMSK register 12 60 S1PICIR register 12 49 S1PICISR register 12 50 S1PICOCW register 12 53 S1PICOCWS register 12 55 S2PICICW
63. 3 CH3_INT_ Slave 1 PIC Channel 3 Interrupt Mode MODE 0 Edge sensitive interrupt request detection 1 Level sensitive interrupt request detection 2 CH2_INT_ Slave 1 PIC Channel 2 Interrupt Mode MODE 0 Edge sensitive interrupt request detection 1 Level sensitive interrupt request detection 1 CH1_INT_ Slave 1 PIC Channel 1 Interrupt Mode MODE 0 Edge sensitive interrupt request detection 1 Level sensitive interrupt request detection 0 CHO_INT_ Slave 1 PIC Channel 0 Interrupt Mode MODE 0 Edge sensitive interrupt request detection 1 Level sensitive interrupt request detection Programming Notes There is a global overriding bit S1_GINT_MODE in the PICICR register see page 12 5 When set the S1 GINT MODE bit causes this register SL1PICMODE to have no effect on the interrupt mode programmed for each channel If the S1 GINT MODE bitis set the overriding global interrupt mode for the Slave 1 PIC channels is determined by the LTIM bit in the S1PICICW1 register see page 12 51 If the 1 GINT MODE bit is cleared the LTIM bit has no meaning and the SL1PICMODE register bits take effect for determining each Slave 1 PIC channel s interrupt mode 12 8 Elan SC520 Microcontroller Register Set Manual Programmable Interrupt Coniroller Registers Slave 2 PIC Interrupt Mode SL2PICMODE Bit Reset R W AMD Memory Mapped MMCR Offset DO4h 7 6 5 4 3 2 1 0 CH7 INT CH6 INT CH5 INT INT CH3 INT
64. A24 for Channel 3 Programming Notes The extended page address is used in conjunction with the memory address and the page address registers for the associated channel to make up a 28 bit address A27 A0 In enhanced mode the Channel extended page address bit field DMAS3ADR 27 24 increments or decrements if the memory address crosses the 16 Mbyte boundary In normal mode these bits remain constant during the DMA transfer Enhanced mode is enabled by setting the ENH MODE ENB bit in the GPDMACTL register see page 11 4 lan SC520 Microcontroller Register Set Manual 11 13 AMDA GP DMA Controller Registers GP DMA Channel 5 Extended Page GPDMAEXTPG5 Memory Mapped MMCR Offset D8Ah 7 6 5 4 3 2 1 0 Bit Reserved DMASADR 27 24 Reset 0 0 0 0 0 0 0 0 R W RSV R W Register Description This register provides the extended page address for Channel 5 Bit Definitions Bit Name Function 7 4 Reserved Reserved This bit field should be written to 0 for normal system operation 3 0 DMA5ADR DMA Channel 5 Extended Page Address 27 24 This bit field specifies the highest four memory address bits 27 24 for Channel 5 Programming Notes The extended page address is used in conjunction with the memory address and the page address registers for the associated channel to make up a 28 bit address A27 A0 In enhanced mode the Channel 5 extended page address bit field DMA5A
65. Bit DMASMAR 23 16 Reset 0 0 0 0 0 0 0 0 R W R W Register Description This register provides bits 23 16 of the memory address for Channel 5 Bit Definitions Bit Name Function 7 1 DMA5MAR DMA Channel 5 Memory Address Bits 23 16 23 16 For 8 bit transfers enhanced mode only the value in this bit field is used with the values in the GPDMA5MAR register see page 11 80 and the GPDMAEXTPG5 register see page 11 14 to generate DMA address bits 27 0 For 16 bit transfers bits 7 1 of this bit field hold address bits 23 17 and address bit 16 is located in the GPDMA5MAR register see page 11 80 Bit 0 of this bit field is not used in 16 bit DMA operation The bit 0 value read back is always the last value written but the bit is not applied to the system address unless 8 bit operation is selected Programming Notes In enhanced mode this channel can be programmed for 8 bit DMA transfers see the descriptions for GPDMACTL register bits CH5 ALT SIZE and ENH MODE ENB on page 11 4 In enhanced mode this register is updated during DMA cycles if the DMA addresses cross the 64 Kbyte boundary for 8 bit transfers or cross the 128 Kbyte boundary for 16 bit transfers lan SC520 Microcontroller Register Set Manual 11 73 AMD General 5 GPDMAGR5 GP DMA Controller Registers Direct Mapped Address 008Ch 7 6 5 4 3 1 0 Bit PORT8C 7 0 Reset 0 0 0 0 0 0 0 R W R W
66. Bit Definitions Bit 7 AM PM 6 0 HOUR 6 0 Programming Notes Function RTC AM PM Indicator If the HOUR MODE SEL bit is 0 in the RTCCTLB register see page 17 17 the AM PM bit is used to indicate whether the current hour is AM or PM 0 The current hour is AM 12 hour mode only In 24 hour mode always clear this bit to 0 1 The current hour is PM 12 hour mode only The RTC logic updates this bit field once per second RTC Current Hour Software initializes the hours value for the RTC by writing data to this bit field in either binary or binary coded decimal BCD format The hours component of the RTC time can be read from this bit field The RTC logic updates this bit field once per second In 24 hour mode valid values for this bit field range from 0 to 23d In 12 hour mode valid values for this bit field range from 1 to 12d If a value outside of the valid range is programmed the register value including the AM PM bit increments up to FFh wraps around to 0 and only then does the value remain within the valid range Software selects 12 hour or 24 hour mode via the HOUR MODE SEL bit inthe RTCCTLB register see page 17 17 Software can suspend updating of the RTC via the SET bit in the RTCCTLB register Software selects binary or BCD format via the DATE MODE bit in the RTCCTLB register 17 8 Elan SC520 Microcontroller Register Set Manual RTC Alarm Hour RTCALMHR Register Description AMD
67. Bit Definitions Bit Name Function 7 6 CTR_SEL 1 0 PIT Counter Select Read back Command When this address Port 0043h is written with bits 7 6 11b the PITRDBACK register is addressed and this CTR_SEL bit field invokes the read back command 00 10 The PITMODECTL or PITCNTLAT register is addressed see page 13 7 and page 13 10 11 Read back command the values selected by bits 5 1 of this register are made available to be read back from the PITxCNT registers see the descriptions starting on page 13 2 immediately following completion of the I O write that invokes this read back command Latched counts are read back from the PITxCNT registers see the descriptions starting on page 13 2 based on the current read write mode selected for each counter via the CTR RW LATCH bit field of the PITMODECTL register see page 13 7 The latched status bytes are returned in the PITxSTA register format see page 13 5 If both LSTAT and LCNT Ob the status byte is made available at the respective PITxONT register first When this byte has been read the latched count bytes are made available bits 7 0 first and then bits 15 8 if the channel is set up to read back all 16 bits of count via the CTR RW LATCH bit field of the PITMODECTL When this address Port 0043h is written with bits 7 6 4 11b and bits 5 4 4 OOb this address is redefined for the duration of the current I O write as the PITMODECTL register see page 13 7 Whe
68. Bit Definitions Bit Name Function 7 2 Reserved Reserved This bit field should be written to 0 for normal system operation 1 RXTC_DET UART x Receive TC Detected When reading 0 TC not detected 1 TC detected This bit is cleared by writing a 1 0 TXTC DET UART x Transmit TC Detected When reading 0 TC not detected 1 TC detected This bit is cleared by writing a 1 Programming Notes Each UART can generate an interrupt when the transfer count GPTC signal associated with DMA transfers is asserted Table 18 5 on page 18 14 provides a summary of UART interrupt sources 18 4 Elan SC520 Microcontroller Register Set Manual UART 1 FIFO Control Shadow UART1FCRSHAD UART 2 FIFO Control Shadow UART2FCRSHAD Bit Reset R W AMD UART Serial Port Registers Memory Mapped MMCR Offset CC2h MMCR Offset CC6h 6 5 4 3 2 1 0 RFRT 1 0 Reserved DMA TF CLR RF CLR FIFO MODE 0 0 0 0 0 0 0 R RSV R R R Register Description This register is provided for reading the information written to the UART x FIFO Control UARTxFCR register see page 18 15 because the UARTXxFCR register is write only Writing to this shadow register has no effect Bit Definitions Bit 7 6 5 4 Name RFRT 1 0 Reserved DMA MODE TF CLR RF CLR Function Receiver FIFO Register Trigger Bits In 16550 compatible mode this bit field specifies the trigger level
69. CHAPTER O AMDA AMD 1 1 CONFIGURATION REGISTER OVERVIEW The lan SC520 microcontroller has four different types of configuration registers B Memory Mapped Configuration Region MMCR Registers These are memory mapped peripherals and configuration registers that are specific to the ElanSC520 microcontroller s control and status functions such as the SDRAM and GP bus controllers These registers are 8 bits 16 bits or 32 bits wide and reside in memory space B Direct Mapped Registers These include the Configuration Base Address CBAR register the PCI Configuration Address and Data PCICFGADR and PCICFGDATA registers and PC AT compatible peripherals All direct mapped I O registers reside in fixed I O space The CBAR PCICFGADR and PCICFGDATA registers are 32 bits wide All other direct mapped peripheral configuration registers are 8 bits wide B PCI Host Bridge Indexed Configuration Registers These registers are located in the PCI bus configuration space which is defined in the PC Local Bus Specification Revision 2 2 to be accessed through two 32 bit I O locations at OCF8h index and OCFCh data B RTC Indexed Registers These registers are located in the PC AT compatible real time clock RTC configuration space which is accessed using I O ports 0070h index and 007 1h data Register descriptions are organized within this manual by function e g GP bus SDRAM or UART Each function s chapter descri
70. CLK TST SEL bit field 20 9 CLKSEL register 20 9 CLKTEST signal Output Clock Select bit field 20 9 Pin Direction bit field 20 9 Pin Enable bit field 20 9 CLKTIMER signal in PITOCNT register 13 2 in PIT1ONT register 13 3 in PIT2CNT register 13 4 Pin Direction bit field 20 9 Pin Enable bit field 20 9 Clock Mode bit field 11 4 Clock Select register 20 9 CMD SEL bit field 19 5 CMOS RAM Location bit field 17 21 CMOSDATA bit field 17 3 CMOSIDX bit field 17 2 CNCR MODE ENB bit field 5 2 Index AMD CNT bit field in GPTMROCNT register 14 6 in GPTMRICNT register 14 12 in GPTMR2CNT register 14 17 CNTx bit field 13 11 Codekit software iii Compressed Timing bit field in MSTDMACTL register 11 87 in SLDMACTL register 11 51 COMPTIM bit field in MSTDMACTL register 11 87 in SLDMACTL register 11 51 Configuration Base Address register 2 9 Configuration Data bit field 6 17 CONT CMP bit field in GPTMROCTL register 14 5 in GPTMR1CTL register 14 11 in GPTMR2CTL register 14 16 Counter Latch Command bit field in PITCNTLAT register 13 10 in PITXSTA register 13 5 Counter Mode bit field 13 8 Counter Mode Status bit field 13 6 Counter Read Write Operation Control bit field in PITMODECTL register 13 7 in PITXSTA register 13 5 COUNTH bit field 16 5 COUNTL bit field 16 4 CPU Clock Speed bit field 4 3 CPU Reset Control bit field 3 7 CPU Shutdown Reset Detect bit field 3 6 CPU CLK SPD bit field 4 3 C
71. Causes the UART to enter 16450 compatible mode Disables accesses to receive and transmit FIFOs and all FIFO control bits except this bit 1 Causes the UART to enter 16550 compatible mode Enables receive and transmit FIFO buffers and enables accesses to other FIFO control bits Programming Notes The contents of this write only register can be read back via the UART x FIFO Control Shadow UARTxFCRSHAD register see page 18 5 18 16 Elan SC520 Microcontroller Register Set Manual UART 2 Line Control UART2LCR UART 1 Line Control UART1LCR Register Description AMD UART Serial Port Registers Direct Mapped I O Address 02FBh Address O3FBh 7 6 5 4 3 2 1 0 Bit DLAB SB SP EPS PENB STP WLS 1 0 Reset 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W This register is used to configure the format of the UART frame for data transfer including character length stop bits and parity The DLAB bit is used to gain access to the baud rate divisor latches or the UARTxTHR and UARTXRBR registers Bit Definitions Bit Name DLAB SB SP EPS PENB Function Divisor Latch Access 0 Software can access the transmit holding receive buffer and interrupt enable registers UARTXTHR page 18 7 UARTxRBR page 18 8 and UARTxINTENB page 18 11 1 Software can access the baud rate divisor latch registers UARTxBCDL page 18 9 and UARTXBCDH page 18 10 Set Break Ena
72. DDCD TERI Function Data Carrier Detect In normal operation loopback mode disabled this bit is the complement of the DCDx signal 0 DCDx input signal is High deasserted 1 DCDx input signal is Low asserted If in loopback mode this bit tracks the OUT2 bit in the UARTxMCR register see page 18 19 Ring Indicator In normal operation loopback mode disabled this bit is the complement of the RINx signal 0 RINx input signal is High deasserted 1 RINx input signal is Low asserted If in loopback mode this bit tracks bit OUT1 bit in the UARTxMCR register see page 18 19 Data Set Ready In normal operation loopback mode disabled this bit is the complement of the DSRx signal 0 DSRx input signal is High deasserted 1 DSRx input signal is Low asserted If in loopback mode this bit tracks bit DTR bit in the UARTxMCR register see page 18 20 Clear To Send In normal operation loopback mode disabled this bit is the complement of the CTSx signal 0 CTSx input signal is High deasserted 1 CTSx input signal is Low asserted If in loopback mode this bit tracks bit RTS bit in the UARTxMCR register see page 18 20 Delta Data Carrier Detect 0 Indicates that the DCDx signal has not changed since this register UARTxMSR was last read 1 Indicates that the DCDx signal changed since the UARTxMSR register was last read Trailing Edge Ring Indicator 0 Indicates that t
73. Direct Mapped I O Address 0020h 7 6 5 4 3 2 1 0 SLCT_ Bit R SL EOI 2 0 IW IS OCW3 LS 2 0 Reset X X X X X X X X R W W W Register Description This register provides control for various interrupt priority end of interrupt EOI modes It also controls write access for this register MPICOCW2 and for the MPICOCWS MPICICW1 registers see page 12 30 and page 12 26 Bit Definitions Bit Name Function 7 5 R SL EOI 2 0 Interrupt Request EOI and Priority Rotation Controls 000 Rotate in auto EOI mode clear 001 Nonspecific EOI 010 No operation 011 Specific EOI 100 Rotate in auto EOI mode set 101 Rotate on nonspecific EOI command 110 Set priority command 111 Rotate on specific EOI command 4 SLCT_ICW1 Select ICW1 Software must clear this bit to 0 when writing this address Port 0020h to access either this register MPICOCW2 or the MPICOCWS register 0 The write accesses either this register MPICOCW2 or the MPICOCWS register see page 12 30 depending on the state of bit 3 1 The write accesses the MPICICW1 register see page 12 26 3 IS OCWS Access is OCW3 Software must clear this bit IS_OCW3 and clear SLCT_ICW1 when writing this address Port 0020h to access this register MPICOCW2 0 The write accesses this register MPICOCW2 if the SLCT_ICW1 bit is cleared 1 The write accesses the MPICOCWS register see 12 30 if th
74. GPCSOFF register 10 9 GPCSPW register 10 8 GPCSQUAL register 10 5 GPCSRT register 10 7 Index GPCSx signal Function Select bit field 20 5 20 7 20 8 in GPCSDW register 10 3 10 4 in GPCSOFF register 10 9 in GPCSPW register 10 8 in GPCSQUAL register 10 5 10 6 in GPCSRT register 10 7 in PARx register 2 7 Qualifier Selection bit field 10 5 10 6 GPCSx DW bit field 10 3 GPCSx RW bit field 10 5 10 6 GPCSx SEL bit field 20 7 20 8 GPDACKx Function Select bit field 20 3 GPDACKx signal 11 6 11 7 GPDBUFOE Function Select bit field 20 6 GP DMA See also DMA Master DMA Slave DMA GP DMA Channel 0 Extended Page register 11 10 GP DMA Channel 1 Extended Page register 11 11 GP DMA Channel 2 Extended Page register 11 12 GP DMA Channel 3 Extended Page register 11 13 Extended Transfer Count register 11 17 Next Address High register 11 27 Next Address Low register 11 26 Next Transfer Count High register 11 35 Next Transfer Count Low register 11 34 GP DMA Channel 5 Extended Page register 11 14 Extended Transfer Count register 11 18 Next Address High register 11 29 Next Address Low register 11 28 Next Transfer Count High register 11 37 Next Transfer Count Low register 11 36 GP DMA Channel 6 Extended Page register 11 15 Extended Transfer Count register 11 19 Next Address High register 11 31 Next Address Low register 11 30 Next Transfer Count High register 11 39 Next Transfer Co
75. GPDMAGR6 page 11 75 General 7 GPDMAGR7 page 11 76 General 8 System Control Port A Slave 1 PIC GPDMAGR8 SYSCTLA 00A0 00A1h page 11 77 Slave 1 PIC Interrupt Request S1PICIR 00A0h page 12 49 Slave 1 PIC In Service S1PICISR 00A0h page 12 50 Slave 1 PIC Initialization Control Word 1 S1PICICW1 00A0h page 12 51 Slave 1 PIC Operation Control Word 2 S1PICOCW2 00A0h page 12 53 Slave 1 PIC Operation Control Word 3 S1PICOCWS 00A0h page 12 55 Slave 1 PIC Initialization Control Word 2 S1PICICW2 00A1h page 12 57 Slave 1 PIC Initialization Control Word 3 S1PICICWS 00A1h page 12 58 Slave 1 PIC Initialization Control Word 4 S1PICICWA 00A1h page 12 59 Slave 1 PIC Interrupt Mask Master DMA S1PICINTMSK 00A1h 00C0 00DEh page 12 60 Master DMA Channel 4 Memory Address GPDMA4MAR 00COh page 11 78 Master DMA Channel 4 Transfer Count GPDMA4TC 00C2h page 11 79 Master DMA Channel 5 Memory Address GPDMAS5MAR 00C4h page 11 80 Master DMA Channel 5 Transfer Count GPDMASTC 00C6h page 11 81 Master DMA Channel 6 Memory Address GPDMA6MAR 00C8h page 11 82 Master DMA Channel 6 Transfer Count GPDMA6TC 00CAh page 11 83 Master DMA Channel 7 Memory Address GPDMA7MAR 00CCh page 11 84 Master DMA Channel 7 Transfer Count GPDMA7TC OOCEh
76. If buffer chaining is enabled and software has not set the channel s CHx CBUF VAL bit before the end of the buffer is reached then the GPTC signal is asserted Note that software can only set the CHx CBUF VAL bit to indicate to the hardware that the Next Address and Transfer Count registers contain valid information The CHx CBUF VAL bit can be cleared only by hardware Elan SC520 Microcontroller Register Set Manual 11 25 AMDA GP DMA Controller Registers GP DMA Channel 3 Next Address Low GPDMANXTADDL3 Memory Mapped MMCR Offset DAOh 15 14 13 12 11 10 9 8 Bit NXT ADR 15 8 Reset 0 0 0 0 0 0 0 0 R W R W 7 6 5 4 3 2 1 0 Bit DMA3_NXT_ADR 7 0 Reset 0 0 0 0 0 0 0 0 R W R W Register Description This register provides address bits A15 A0 of the next memory address for Channel 3 in buffer chaining mode Bit Definitions Bit Name Function 15 0 DMA3_NXT_ DMA Channel 3 Next Address Low ADR 15 0 This bit field provides address bits A15 A0 of the next memory buffer to be used by Channel 3 in the buffer chaining mode Programming Notes The value of this register is ignored if buffer chaining mode is not enabled for this channel in the GPDMABCCTL register see page 11 21 Bit 0 of this register GPDMANXTADDLS is ignored for 16 bit mode transfers so the buffer address used is always even in 16 bit mode Software should ensure that 16 bit mode
77. Mask or unmask DMA Channel 5 per the CHMASK bit 10 Mask or unmask DMA Channel 6 per the CHMASK bit 11 Mask or unmask DMA Channel 7 per the CHMASK bit Elan SC520 Microcontroller Register Set Manual GP DMA Controller Registers AMDA Master DMA Channel 4 7 Mode MSTDMAMODE Direct Mapped Register Description Address 00D6h 7 6 5 4 3 2 1 0 Bit TRNMOD 1 0 ADDDEC AINIT OPSEL 1 0 MODSEL 1 0 Reset X X X X X X X X R W W w This register indicates the transfer mode for Channels 4 7 Bit Definitions Bit 7 6 3 2 Name TRNMOD 1 0 ADDDEC AINIT OPSEL 1 0 Function Transfer Mode This bit field selects the transfer mode for the channel selected by the MODSEL bit field 00 Demand transfer mode 01 10 Block transfer mode 11 Single transfer mode Cascade mode Only Channel 4 should be programmed for cascade mode All other channels should be programmed for one of the other modes Address Decrement This bit field selects increment or decrement counting for the channel selected by the MODSEL bit field 0 Increment the DMA memory address after each transfer 1 Decrement the DMA memory address after each transfer Automatic Initialization Control This bit field enables automatic initialization for the channel selected by the MODSEL bit field 0 Automatic initialization is disabled 1 Automatic initialization is enabled
78. Programming Notes latched microsecond count of the software timer Function Reserved This bit field should be written to 0 for normal system operation SWT Microsecond Count This read only bit field holds the latched microsecond count value from a free running microsecond counter Each read of this bit field returns the currently latched microsecond count value On each read of the SWTMRMILLI register see page 15 2 the value in the internal microsecond counter is latched into this bit field US This US bit field is reset to 0 at system reset The internal microsecond counter increments at a rate of 1 MHz and counts from 0 to 999 It rolls over from 999 back to 0 Every time the microsecond counter rolls over the MS ONT bit field in the SWTMRMILLI register is incremented see page 15 2 Note that the XTAL FREQ bit in the SWTMRCFG register see page 15 4 must be set appropriately in order for the increment rate to be correct Elan SC520 Microcontroller Register Set Manual 15 3 AMDA Software Timer Registers Software Timer Configuration SWTMRCFG Memory Mapped MMCR Offset C64h 7 6 5 4 3 2 1 0 i XTAL_ Bit Reserved FREQ Reset 0 0 0 0 0 0 0 0 R W RSV R W Register Description This register is used to calibrate the software timer to the crystal frequency being used Bit Definitions Bit Name Function 7 1 Reserved Reserved This bit field should be written to 0 fo
79. Programming Notes Enhanced mode is enabled by setting the ENH MODE ENB bit in the GPDMACTL register see page 11 4 In PCI bus 2 2 compliant designs software must limit the length of GP bus DMA demand or block mode transfers Very large transfers could cause the PCI Host Bridge target controller to violate the 10 us memory write maximum completion time limit set in the PC Local Bus Specification Revision 2 2 lan SC520 Microcontroller Register Set Manual 11 19 AMDA GP DMA Controller Registers GP DMA Channel 7 Extended Transfer Count GPDMAEXTTC7 Memory Mapped MMCR Offset D93h 7 6 5 4 3 2 1 0 Bit DMA7TC 23 16 Reset 0 0 0 0 0 0 0 0 R W R W Register Description This register provides the extended transfer count bits for Channel 7 Bit Definitions Bit Name Function 7 0 DMA7TC DMA Channel 7 Transfer Count Extension 23 16 This bit field provides the higher 8 bits of the transfer count for DMA Channel 7 In enhanced mode this bit field is used with the DMA7TC 15 0 bit field in the GPDMA7TC register see page 11 85 to allow counts up to 16 M 16 777 216 transfers In normal mode the value of this bit field DMA7TC 23 16 is ignored Programming Notes Enhanced mode is enabled by setting the ENH MODE ENB bit in the GPDMACTL register see page 11 4 In PCI bus 2 2 compliant designs software must limit the length of GP bus DMA demand or block mode transfers Very large transfers
80. Real Time Clock Registers AMDA General Purpose CMOS RAM 114 bytes RTCCMOS Address 70h 71h RTC Indexes OE 7Fh 7 6 5 4 3 2 1 0 Bit RTC_CMOS_REG_X 7 0 Reset x x x x R W R W Register Description These registers are the general purpose CMOS RAM registers Bit Definitions Bit 7 0 CMOS REG X 7 0 Programming Notes Function CMOS RAM Location These are 114 bytes of general purpose battery backed nonvolatile CMOS RAM available for use by system software applications etc In a PC AT compatible system many of these bytes can be used by the system BIOS The number of bytes used and the meaning of data stored in a given CMOS RAM byte location can vary between different BIOS vendors or even between different versions of a single BIOS Accesses to CMOS RAM locations can be performed without any regard for RTC operations For example DATE MODE bit has no effect on CMOS RAM data If the RTC is disabled via the DIS bit in the ADDDECCTL register see page 2 3 the CMOS RAM is unavailable but not lost unless both main and backup power to the internal RTC is removed Re enabling the RTC allows access to the CMOS RAM with its contents intact lan SC520 Microcontroller Register Set Manual 17 21 Real Time Clock Registers 17 22 Elan SC520 Microcontroller Register Set Manual CHAPTER ee AMD 1 18 UART SERIAL PORT REGISTERS 18 1
81. Reset 0 0 0 0 0 0 0 0 R W R W Register Description This register provides bits 15 0 of the next transfer count for Channel 5 in buffer chaining mode Bit Definitions Bit Name Function 15 0 DMA5_NXT_ DMA Channel 5 Next Transfer Count Low TC 15 0 This bit field provides bits 15 0 of the next transfer count to be used by Channel 5 in the buffer chaining mode Programming Notes The value of this register is ignored if buffer chaining mode is not enabled for this channel in the GPDMABCCTL register see page 11 21 In PCI bus 2 2 compliant designs software must limit the length of GP bus DMA demand or block mode transfers Very large transfers could cause the PCI Host Bridge target controller to violate the 10 us memory write maximum completion time limit set in the PCI Local Bus Specification Revision 2 2 11 36 Elan SC520 Microcontroller Register Set Manual GP DMA Controller Registers AMDA GP DMA Channel 5 Next Transfer Count High GPDMANXTTCH5 Memory Mapped MMCR Offset DBGh 7 6 5 4 3 2 1 0 Bit DMA5_NXT_TC 23 16 Reset 0 0 0 0 0 0 0 0 R W R W Register Description This register provides bits 23 16 of the next transfer count for Channel 5 in buffer chaining mode Bit Definitions Bit Name Function 7 0 DMA5_NXT_ DMA Channel 5 Next Transfer Count High TC 23 16 This bit field provides bits 23 16 of the next transfer count to be used by Channel 5 in the
82. SSI Command Select Three commands are available to initiate an SSI transaction 00 Reserved 01 Transmit command initiate a transaction in which the contents of the SSIXMIT register are shifted out see page 19 4 10 Receive command initiate a transaction in which data is shifted in to the SSIRCV register see page 19 7 11 Simultaneous Transmit Receive command initiate a transaction in which both transmit and receive happen simultaneously When read this bit field returns the last command written to it This register should not be written while the BSY bit is set in the SSISTA register see page 19 6 The CMD SEL bit field is decoded and the command executed after the command is written Software should load the SSIXMIT register if necessary before writing the command The SSIRCV register can be read after the transaction is complete There is at least one 33 MHz clock period idle time between transactions A slave device should be enabled if necessary before a transmit or receive transaction is initiated and the device should be disabled if necessary after the transaction is complete Software can use programmable I O PIO pins to implement device enable signals See Chapter 20 Programmable Input Output Registers for details about configuring PIO pins Elan SC520 Microcontroller Register Set Manual 19 5 Synchronous Serial Interface Registers SSI Status SSISTA Memory Mapped MMCR Offset
83. The host bridge allows the Am5 86 CPU to generate PCI bus master cycles and allows PCI bus masters to access the ElanSC520 microcontrollers SDRAM The host bridge register set includes three groups of registers B Six memory mapped configuration region MMCR registers are used to configure and control most functions specific to the ElanSC520 microcontroller host bridge Two direct mapped I O addresses are used to access the PCI bus configuration space for both the host bridge and for any other devices present on the PCI bus Five host bridge specific PCI bus indexed registers in the PCI bus configuration space provide the mandatory header registers that are required for any PCI bus device plus the Master Retry Time Out register In addition to the host bridge the PCI bus can contain several other devices each with its own PCI configuration space that is also accessed via the two PCI direct mapped registers Access from other PCI bus masters to the host bridge registers is not supported The host bridge implements only those configuration registers that are related to the host bridge functions See the Elan SC520 Microcontroller User s Manual order 22004 for details about the host bridge controller Table 6 1 Table 6 2 on page 6 2 and Table 6 3 on page 6 2 list each type of host bridge controller register in offset order with the corresponding descriptions page number REGISTERS PCI Bus Host Bridge MMCR Registers Reg
84. This register stores the control word used to define the operation of the channels including mode Bit Definitions Bit Name Function 7 6 CTR_SEL 1 0 PIT Counter Select When this address Port 0043h is written with bits 7 6 4 11b and bits 5 4 4 00b the PITMODECTL register is addressed and this CTR SEL bit field specifies which of the three PIT channels is affected by the settings written to bits 5 0 00 Select PIT counter 0 01 Select PIT counter 1 10 Select PIT counter 2 11 The PITRDBACK register is addressed see page 13 11 When this address Port 0043h is written with bits 7 6 11b this address is redefined for the duration of the current I O write as the PITRDBACK register see page 13 11 When this address Port 0043h is written with bits 7 6 11b and bits 5 4 00b this address is redefined for the duration of the current I O write as the PITCNTLAT register see page 13 10 5 4 CTR RW LATCH Counter Read Write Operation Control 1 0 When this address Port 0043h is written with bits 7 6 z 11b and bits 5 4 z 00 the PITMODECTL register is addressed and these CTR_RW_LATCH bits define what can be written to the register where x is selected by bits 7 6 of this PITMODECTL register 00 The PITCNTLAT register is addressed see page 13 10 01 Read write counter bits 7 0 only 10 Read write counter bits 15 8 only 11 Read write counter bits 7 0 follow
85. default memory map for the lower 1 Gbyte address range 00000000h 3FFFFFFFh is either SDRAM if enabled or PCI Accesses to any external GP bus devices or devices connected to ROMCS1 or ROMCS2 require a PARx window to be enabled and configured to access them 000 The window is disabled All other bits in the PARx register are ignored 001 The window targets a GP bus I O region This is the only I O space access possible through a PARx window All other settings refer to the memory address space For GP bus windows the ATTR bit field selects a GP bus chip select See the programming notes for this register on page 2 8 for GP bus I O address restrictions 010 The window targets a GP bus memory region For GP bus windows the ATTR bit field selects a GP bus chip select 011 The window targets a PCI bus memory region Only and PAR1 support a PCI bus memory region as a target Define a PCI bus window only when attempting to forward cycles to the PCI bus in the lower 256 Mbyte address range 00000000h to OFFFFFFFh 100 The window targets a BOOTCS region boot ROM or Flash memory device The ElanSC520 microcontroller forces the BOOTCS signal active at system reset but the boot code must initialize a PARx register to decode the required space for the ROM Refer to theElan SC520 Microcontroller User s Manual order 22004 for details on configuring the boot ROM during system initialization 101 The window targets
86. in HBMSTIRQCTL register 6 9 6 10 in PCISTACMD register 6 13 6 19 6 20 SERR ENB bit field 6 20 SET bit field 17 16 Set Break Enable bit field 18 17 SFNM bit field in MPICICWA register 12 35 in S1PICICWA register 12 59 in S2PICICWA register 12 47 SGL INT ENB bit field 7 9 SIG SERR bit field 6 19 Signal Width for GPIOWR and GPMEMWR bit field 10 12 for GPALE bit field 10 14 for GPIORD and GPMEMRD bit field 10 10 for the GP Bus Chip Selects bit field 10 8 Signaled System Error bit field 6 19 Signaled Target Abort bit field 6 20 Single PIC bit field in MPICICW1 register 12 26 in S1PICICW 1 register 12 52 in S2PICICW1 register 12 40 Single bit ECC Error bit field 7 10 SL bit in R SL EOI bit field 12 28 12 41 12 53 SL1PICMODE register 12 8 SL2PICMODE register 12 9 Index Slave 1 PIC I O Port 00A0h access summary table 12 52 Initialization Control Word 1 register 12 51 Initialization Control Word 2 register 12 57 Initialization Control Word 3 register 12 58 Initialization Control Word 4 register 12 59 In Service register 12 50 Interrupt Mask register 12 60 Interrupt Mode register 12 8 Interrupt Request register 12 49 Operation Control Word 2 register 12 53 Operation Control Word 3 register 12 55 Slave 2 PIC I O Port 0024h access summary table 12 40 Initialization Control Word 1 register 12 39 Initialization Control Word 2 register 12 45 Initialization Control Word 3 register 12 4
87. lan SC520 Microcontroller Register Set Manual Order 22005B AMD 2001 Advanced Micro Devices Inc All rights reserved The contents of this document are provided in connection with Advanced Micro Devices Inc AMD products AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to speci fications and product descriptions at any time without notice No license whether express implied arising by estoppel or otherwise to any in tellectual property rights is granted by this publication Except as set forth in AMD s Standard Terms and Conditions of Sale AMD assumes no liability whatsoever and disclaims any express or implied warranty relating to its products including but not limited to the implied warranty of merchantability fitness for a particular purpose or infringement of any intellectual property right AMD s products are not designed intended authorized or warranted for use as components in systems intended for surgical implant into the body or in other applications intended to support or sustain life or in any other application in which the failure of AMD s product could create a situation where personal injury death or severe property or environmental damage may occur AMD reserves the right to discontinue or make changes to its products at any time without notice Trademarks AMD the AMD logo and c
88. number Table 20 2 on page 20 2 provides an overview of how bits in the PIO pin configuration registers are used to control individual PIO pins REGISTERS Programmable I O MMCR Registers Register Name PIO15 PIOO Pin Function Select Mnemonic PIOPFS15 0 MMCR Offset Page Number page 20 3 PIO31 PIO16 Pin Function Select PIOPFSS1 16 page 20 5 Chip Select Pin Function Select CSPFS page 20 7 Clock Select CLKSEL page 20 9 Drive Strength Control DSCTL page 20 10 PIO15 PIOO Direction PIODIR15 0 page 20 12 PIOS31 PIO16 Direction PIODIR31 16 page 20 14 PIO15 PIOO Data PIODATA15 0 page 20 16 PIO31 PIO16 Data PIODATA31 16 page 20 18 PIO15 PIOO Set PIOSET15 0 page 20 20 PIO31 PIO16 Set PIOSETS31 16 page 20 22 PIO15 PIOO Clear PIOCLR15 0 page 20 24 PIO31 PIO16 Clear PIOCLR31_16 Elan SC520 Microcontroller Register Set Manual page 20 26 20 1 AM Programmable Input Output Registers Table 20 2 PIO Register Programming Summary Function Data Data Select Direction Register Set Clear Register Register Register Bit Register Register Bit 1 Bit Bit Writes Bit Bit Reads Resulting Programmable I O Pin Function The pin is not a PIO it uses its interface function The value of the pin can be read at the Data bit but writes to the Direction Data Set and Clear bits have no e
89. see page 18 17 this bit field holds the east significant byte of a 16 bit baud rate clock divisor that is used to generate the 16x baud clock Programming Notes Setting the DIV 15 0 bit field to 0000h is not supported When the DLAB bit is 0 in the UARTxLCR register see page 18 17 reads from this address access the UART x Receive Buffer UARTxRBR register see page 18 8 and writes to this address access the UART x Transmit Holding UARTxTHR register see page 18 7 When the DLAB bit is 1 in the UARTXxLCR register reads from and writes to this address access the UART x Baud Clock Divisor Latch LSB UARTxBCDL register The clock source frequency is selected by the CLK_SRC bit in the UARTxCTL register see page 18 3 Table 18 3lists the divisor value in decimal and hexadecimal to use with each clock frequency to achieve common baud rates Table 18 3 Baud Rates Divisors and Clock Source DIV 15 0 Decimal DIV 15 0 Hexadecimal Baud Rate 1 8432 MHz 18 432 MHz 1 8432 MHz 18 432 MHz 300 baud 600 baud 2400 baud 4800 baud 7200 baud 9600 baud 14 4 kbaud 19 2 kbaud 57 6 kbaud 115 2 kbaud 144 kbaud 192 kbaud 288 kbaud 576 kbaud 1 152 Mbaud Elan SC520 Microcontroller Register Set Manual 18 9 UART Serial Port Registers Direct Mapped UART 2 Baud Clock Divisor Latch MSB UART2BCDH Address 02F9h UART 1 Baud Cloc
90. see page 18 23 Elan SC520 Microcontroller Register Set Manual UART 2 Line Status UART2LSR UART 1 Line Status UART1LSR Bit Reset R W AMD UART Serial Port Registers Direct Mapped I O Address 02FDh I O Address O3FDh 7 6 5 4 3 2 1 0 ERR_IN_ FIEO TEMT THRE BI FE PE OE DR 0 1 1 0 0 0 0 0 R R R R R R R R Register Description This read only register shows the status of the data transfer with indicators for transmitter or transmit holding register empty break detected framing error parity error overrun error and received data ready Bit Definitions Bit Name ERR_IN_FIFO TEMT THRE Function 16550 Compatible Mode Error 0 In 16550 compatible mode there is no parity error framing error or break condition in the receive FIFO In 16450 compatible mode this bit always reads back 0 1 At least one parity error framing error or break condition is present in the receive FIFO 16550 compatible mode only This bit is cleared by a read from this register UARTxLSR or by a read from the receiver FIFO when there are no more error conditions present in the FIFO Transmitter Empty Indicator 0 The transmit shift register still has data to transmit 1 In 16450 compatible mode both the transmit holding register and the transmit shift register are empty In 16550 compatible mode both the transmit FIFO and the transmit shift register are empty
91. that is written to the ECC SDRAM devices During a read cycle the requested data is read from SDRAM along with the stored ECC check code A new check code is then generated from the read data and compared to the read ECC check code 7 12 Elan SC520 Microcontroller Register Set Manual SDRAM Controller Registers AMDA If there is an ECC mismatch either a single bit or multiple bit error has been detected Single bit errors are corrected as data is returned to the requesting master and an interrupt is generated if enabled Multi bit errors are not corrected but an NMI is generated if enabled This register ECCCKTEST provides a way for the user to alter the ECC check code that is written to the ECC SDRAM If the ECC check code is altered so that it reflects a single bit or multiple bit error it is detected by the lanSC520 microcontroller when that location is read if ECC is enabled This feature can be used for test purposes and also for ECC error handler development Because the write buffer decouples master write requests from the actual SDRAM access it is advisable to disable the write buffer when using the feature provided by this register Otherwise the ECC check code specified in this register might be applied to a write buffer write access to SDRAM and not the particular access intended In addition care should be taken to ensure that the Am5 86 CPU cache allows the write cycle to propagate to the SDRAM So that test software n
92. 0 0 R W R W RSV R W 23 22 21 20 19 18 17 16 Bit ADR 23 16 Reset 0 0 0 0 0 0 0 0 R W R W 15 14 13 12 11 10 9 8 Bit ADR 15 12 Reserved Reset 0 0 0 0 0 0 0 0 R W R W RSV 7 6 5 4 3 2 1 0 Bit MATCH 7 0 Reset 0 0 0 0 0 0 0 0 R W W This register can be used to alias the memory mapped configuration region MMCR that is used to access many of the lanSC520 microcontroller s integrated peripheral functions The MMCR is always accessible at FFFEF000 FFFEFFFFh in the region directly below the boot ROM space but it can also be aliased to any 4 Kbyte boundary within the first 1 Gbyte of memory space Bit Definitions Bit 31 30 29 12 Name ENABLE Reserved ADR 29 12 Function Enable This bit must be set to enable write access to the CBAR register Upon reading the ENABLE bit returns the state of the MMCR alias 0 MMCR alias is disabled 1 2 MMCR alias is enabled Writes to this bit are ignored if the value CBh is not written to the MATCH bit field in the same write cycle Reserved This bit field should be written to O for normal system operation Start Address This bit field defines the starting address of the memory mapped configuration region on a 4 Kbyte boundary The address programmed in this bit field is compared to internal Am5 86 CPU bus signals a29 a12 Writes to this bit field are ignored unless the ENABLE bit set and the value CBh is written to the MATCH bit field in the same writ
93. 1 Signaled Target Abort This bit is set by the host bridge target controller when it terminates a transaction with a target abort The host bridge responds with a target abort when an address parity error is detected 0 Target controller did not end a transaction with a target abort 1 Target controller ended a transaction with a target abort This bit is cleared by writing a 1 Device Select DEVSEL Timing These read only bits define the slowest DEVSEL timing for the host bridge target controller 01 The host bridge target controller always uses medium DEVSEL timing This bit field is internally fixed to 01b Data Parity Reported This bit is set by the host bridge master controller when during a host bridge master controller PCI bus cycle PERR is asserted by the host bridge or a PCI bus target and the Parity Error Response bit PERR RES in the PCISTACMD register see page 6 21 is also set 0 The master controller did not detect parity error 1 The master controller detect parity error This bit is cleared by writing a 1 Fast Back to Back Capable This read only bit indicates the host bridge target controller is capable of fast back to back transactions 1 The host bridge target controller is capable of fast back to back transactions UDF Supported This read only bit indicates the host bridge does not support user definable features 0 The host bridge does not support user definable features 66 MHz Capabl
94. 1 Two ROM chip select signals ROMCSx Any of the two ROM chip select signals Numbers b Binary number d Decimal number Decimal is the default radix h Hexadecimal number x in register address Any of several legal values e g using OxF8h for the UART Transmit Holding register is either O2F8h or OSF8h depending on the UART X Y The bit field that consists of bits X through Y Example The SB ADDR 23 16 bit field 33 MHz Refers to the system clock frequency being used This can be either 33 000 MHz or 33 333 MHz See the Elan SC520 Microcontroller User s Manual order 22004 for more information about clock generation General field Bit field in a register one or more consecutive and related bits can It is possible to perform an action if properly configured will A certain action is going to occur Set the ENB bit Write the ENB bit to 1 Note The bit referred to is either in the register being described or the register is referred to explicitly in the surrounding text Clear the ENB bit Change the ENB bit to 0 Usually a bit is cleared by writing a 0 to it however some bits are cleared by writing a 1 Reset the ENB bit Context sensitive Can refer either to resetting the bit to its default value or to clearing the bit Elan SC520 Microcontroller Register Set Manual xix AM De Introduction XX Elan SC520 Microcontroller Register Set Manual
95. 1 The pin is GPDACK1 PIO10 or GPDACK2 Function Select This bit is used to select the functionality of the PIO10 pin 0 The pin is PIO10 1 The pin is GPDACK2 PIO9 or GPDACK3 Function Select This bit is used to select the functionality of the PIOO9 pin 0 The pin is PIO9 1 The pin is GPDACK3 Elan SC520 Microcontroller Register Set Manual 20 3 AM DA Programmable Input Output Registers Bit Name Function 8 PIO8 PIO8 or GPDRQO Function Select This bit is used to select the functionality of the 8 pin 0 The pin is PIO8 1 The pin is GPDRQO 7 PIO7 FNC PIO7 or GPDRQ1 Function Select This bit is used to select the functionality of the PIO7 pin 0 The pin is PIO7 1 The pin is GPDRQ1 6 PlO6 PIO6 or GPDRQ2 Function Select This bit is used to select the functionality of the PIO6 pin 0 The pin is PIO6 1 The pin is GPDRQ2 5 PIO5 PIO5 or GPDRQ3 Function Select This bit is used to select the functionality of the PIO5 pin 0 The pin is PIO5 1 The pin is GPDRQ3 4 PlO4 PIO4 or GPTC Function Select This bit is used to select the functionality of the PIO4 pin 0 The pin is PIO4 1 The pin is GPTC 3 PIO3 FNC PIO3 or GPAEN Function Select This bit is used to select the functionality of the PIOS pin 0 The pin is PIO3 1 The pin is GPAEN 2 PIO2 FNC PIO2 or GPRDY Function Select This bit is used to select the functionality of the PIO2 pin 0 The pin is PIO2
96. 1 2 The pin is GPRDY 1 PIO1 FNC PIO1 or GPBHE Function Select This bit is used to select the functionality of the PIO1 pin 0 The pin is PIO1 1 pin is GPBHE 0 PIOO_FNC PIOO or GPALE Function Select This bit is used to select the functionality of the PIOO pin 0 The pin is PIOO 1 The pin is GPALE Programming Notes This register PIOPFS15 0 should be written early in the microcontroller s initialization routine The bit values to write depend on which pins are to be used for PIO functions as opposed to interface functions This depends on how the microcontroller is used in each particular system design On reset each PIO pin is an input with a pullup or pulldown resistance for termination See the pin list summary table in the Elan SC520 Microcontroller Data Sheet order 22003 Software writes a 1 to the corresponding bit in this register to change a pin to its interface function For example PIO2 shares a pin with the GP bus GPRDY signal so before GPRDY can be used a 1 must be written to the PIO2 FNC bit To summarize W Abit must be cleared to use the corresponding pin as a programmable I O pin W Abit must be set to 1 to use the corresponding pin for its interface function Although software can perform a 32 bit access of MMCR offset C20h to select all 32 PIO pin functions with a single instruction the 32 bit access is split into two separate 16 bit accesses with the PIOPFS15 0 register being accessed prior to
97. 11 34 Elan SC520 Microcontroller Register Set Manual GP DMA Controller Registers AMDA GP DMA Channel 3 Next Transfer Count High GPDMANXTTCH3 Memory Mapped MMCR Offset DB2h 7 6 5 4 3 2 1 0 Bit DMA3_NXT_TC 23 16 Reset 0 0 0 0 0 0 0 0 R W R W Register Description This register provides bits 23 16 of the next transfer count for Channel 3 in buffer chaining mode Bit Definitions Bit Name Function 7 0 DMA3_NXT_ DMA Channel 3 Next Transfer Count High TC 23 16 This bit field provides bits 23 16 of the next transfer count to be used by Channel 3 in the buffer chaining mode Programming Notes The value of this register is ignored if buffer chaining mode is not enabled for this channel in the GPDMABCCTL register see page 11 21 In PCI bus 2 2 compliant designs software must limit the length of GP bus DMA demand or block mode transfers Very large transfers could cause the PCI Host Bridge target controller to violate the 10 us memory write maximum completion time limit set in the PCI Local Bus Specification Revision 2 2 lan SC520 Microcontroller Register Set Manual 11 35 AMDA GP DMA Controller Registers GP DMA Channel 5 Next Transfer Count Low GPDMANXTTCL5 Memory Mapped MMCR Offset DB4h 15 14 13 12 11 10 9 8 Bit DMA5_NXT_TC 15 8 Reset 0 0 0 0 0 0 0 0 R W R W 7 6 5 4 3 2 1 0 Bit 5 NXT TC 7 0
98. 11 42 Slave DMA Channel 0 Transfer Count GPDMAOTC 0001h page 11 43 Slave DMA Channel 1 Memory Address GPDMA1MAR 0002h page 11 44 Slave DMA Channel 1 Transfer Count GPDMA1TC 0003h page 11 45 Slave DMA Channel 2 Memory Address GPDMA2MAR 0004h page 11 46 Slave DMA Channel 2 Transfer Count GPDMA2TC 0005h page 11 47 Slave DMA Channel 3 Memory Address GPDMA3MAR 0006h page 11 48 Slave DMA Channel 3 Transfer Count GPDMAS3TC 0007h page 11 49 Slave DMA Channel 0 3 Status SLDMASTA 0008h page 11 50 Slave DMA Channel 0 3 Control SLDMACTL 0008h page 11 51 Slave Software DRQ n Request SLDMASWREQ 0009h page 11 53 Slave DMA Channel 0 3 Mask SLDMAMSK 000Ah page 11 54 Slave DMA Channel 0 3 Mode SLDMAMODE 000Bh page 11 55 Slave DMA Clear Byte Pointer SLDMACBP 000Ch page 11 57 Slave DMA Controller Reset SLDMARST 000Dh page 11 58 Slave DMA Controller Temporary SLDMATMP 000Dh page 11 59 Slave DMA Mask Reset SLDMAMSKRST 000Eh page 11 60 Slave DMA General Mask SLDMAGENMSK 000Fh page 11 61 Elan SC520 Microcontroller Register Set Manual 1 7 AMD Table 1 2 Register Name Master Programmable Interrupt Controller Configuration Register Overview Direct Mapped I O Registers Continued Mnemonic Address 0020 0021h Page Number Master PIC Interrupt Request MPICIR 0020h page 12 24 Master PIC In Service MPICISR 0020h page 12 25 Master PIC Initialization Control Word 1 MPICICW1 0020h page 12 26
99. 12 37 Slave 2 PIC In Service 62 1 15 12 38 Slave 2 PIC Initialization Control Word 1 S2PICICW1 12 39 Slave 2 PIC Operation Control Word 2 S2PICOCW2 12 41 Slave 2 PIC Operation Control Word 3 S2PICOCW3 12 43 Slave 2 PIC Initialization Control Word 2 S2PICICW2 12 45 Slave 2 PIC Initialization Control Word 3 S2PICICW3 12 46 Slave 2 PIC Initialization Control Word 4 S2PICICW4 12 47 Slave 2 PIC Interrupt Mask 52 1 5 12 48 Slave 1 PIC Interrupt Request S1PICIR 12 49 Slave 1 PIC In Service 1 12 50 Slave 1 PIC Initialization Control Word 1 S1PICICW1 12 51 Slave 1 PIC Operation Control Word 2 STPICOCW2 12 53 Slave 1 PIC Operation Control Word 3 STPICOCW3 12 55 Slave 1 PIC Initialization Control Word 2 S1PICICW2 12 57 Slave 1 PIC Initialization Control Word 3 S1PICICW3 12 58 Slave 1 PIC Initialization Control Word 4 S1PICICW4 12 59 Slave 1 PIC Interrupt Mask 51 1 5 12 60 Floating Point Error Interrupt Clear FPUERRCLR 12 61 Elan SC520 Microcontroller Register Set Manual ix AMD Table of Contents CHAPTER 13 PROGRAMMABLE INTERVAL TIMER REGISTERS 13 1 19 TOVervIeW s cese been t y eer
100. 16450 compatible mode the DMA operation is defined as if this bit were set to O 0 The internal rxdrq signal to the DMA controller goes High when there is at least one character in the receiver FIFO or the UARTx Receive Buffer register see page 18 8 The txdrq signal goes High when the transmitter FIFO 16550 compatible mode or the UARTx Transmit Holding register page 18 7 16450 compatible mode is not full 1 The internal rxdrq signal goes High when the trigger level or the time out has been reached and then it goes inactive when there are no more characters in the FIFO or holding register For transmit the txdrq signal goes High when the transmitter FIFO is not full and remains High until the transmitter FIFO is completely full Transmitter FIFO Clear 0 Writing a 0 to this bit has no effect This bit is self clearing and does not need to be reset by software 1 Writing a 1 to this bit position clears the transmit FIFO and resets the transmit FIFO counter logic It does not clear the transmitter shift register Receiver FIFO Clear 0 Writing a 0 to this bit has no effect This bit is self clearing and does not need to be reset by software 12 Writing a 1 to this bit position clears the receive FIFO and resets the receive FIFO counter logic It does not clear the receive shift register lan SC520 Microcontroller Register Set Manual 18 15 AMD UART Serial Port Registers Bit Name Function 0 FIFO_ENB FIFO Enable 0
101. 18 17 16 Bit Reserved Reset 0 0 0 0 0 0 0 0 R W RSV 15 14 13 12 11 10 9 8 Bit Reserved HI PRI 1 SEL 3 0 Reset 0 0 0 0 1 1 1 1 R W RSV R W R W R W R W 7 6 5 4 3 2 1 0 Bit Reserved HI PRI 0 SEL 3 0 Reset 0 0 0 0 1 1 1 1 R W RSV R W R W R W R W Register Description This register defines priorities for the PCI bus arbiter Bit Definitions Bit 31 30 29 12 5 6 Name CPU PRI 1 0 Reserved Function PCI Bus Arbiter CPU Priority This bit field defines the relative Am5 86 CPU PCI master priority 00 Reserved 01 The Am5 86 CPU is granted the PCI Bus after every one external PCI master cycle 10 The Am5 86 CPU is granted the PCI Bus after every two external PCI master cycles 11 2 The Am5 86 CPU is granted the PCI Bus after every three external PCI master cycles Reserved This bit field should be written to 0 for normal system operation Elan SC520 Microcontroller Register Set Manual Bit 11 8 HI PRI 1 SEL 3 0 7 4 Reserved 3 0 HI PRI 0 SEL 3 0 Programming Notes System Arbitration Registers AMD Function PCI Bus Arbiter High Priority 1 This bit defines which PCI master is in position 1 of the high priority queue 0000 PCI master connected to REQO and GNTO is in position 1 of the high priority queue 0001 PCI master connected and GNT1 is in position 1 of the high priority queue 0010 PCI master connected to REQ2 and GNT2 is in
102. 18 21 AMD Bit Name 3 FE 2 PE 1 OE 0 DR Programming Notes UART Serial Port Registers Function Framing Error 0 No framing error has been reported since line status was last read 1 In 16450 compatible mode this bit is set to indicate that a received character did not have a valid stop bit In 16550 compatible mode this bit is set when a character that was received into the FIFO with a framing error is at the top of the receive FIFO This latched status bit is automatically cleared by a read from this register UARTxLSR Parity Error 0 There is parity error associated with the current character 1 In 16450 compatible mode this bit is set upon receipt of data with incorrect parity In 16550 compatible mode this bit is set when a character that was received into the FIFO with bad parity is at the top of the receive FIFO This latched status bit is automatically cleared by a read from this register UARTxLSR Overrun Error 0 No overrun error has been reported since line status was last read 1 In 16450 compatible mode this bit is set if a new character is received into the receiver buffer before a previous character was read thus resulting in lost data In 16550 compatible mode this bit is set if a new character is completely received into the shift register when the FIFO is already 100 full Data in the FIFO is not overwritten by this overrun The data in the shift register is lost when the next ch
103. 2 SSI Transmit SSIXMIT seee hniena a 19 4 SSI Command 551 19 5 SSI Status SSISTA ea dS poeta vets PO PES Ete detta 19 6 SSI Receive 51 19 7 CHAPTER 20 PROGRAMMABLE INPUT OUTPUT REGISTERS 20 1 20 1 OVERVIEWS iiaia ken Eae denk pedet der bed e uxo 20 1 20 2 Hegistersc Su iy by RR EE BAA E 20 1 PIO15 PIOO Pin Function Select PIOPFS15 0 20 3 1 16 Pin Function Select PIOPFS31 16 20 5 Chip Select Pin Function Select 20 7 Clock Select CLKSEL 20 9 Drive Strength Control 5 1 20 10 PIO15 PIOO Direction 15 0 20 12 1 16 Direction PIODIR31_16 20 14 15 Data PIODATA15 0 20 16 1 16 Data PIODATA31 16 20 18 15 Set PIOSET15 0 20 20 PIO31 PIO16 Set PIOSET31 16 20 22 PIO15 PIOO Clear 15_0 20 24 PIOS31 PIO16 Clear _16 20 26 INDEX Index 1 xii Elan SC520 Microcontroller Register Set Manual Table of Content
104. 21 PIT 0 Interrupt Mapping PITOMAP D20h page 12 21 PIT 1 Interrupt Mapping PIT1MAP D21h page 12 21 PIT 2 Interrupt Mapping PIT2MAP D22h page 12 21 UART 1 Interrupt Mapping UART1MAP D28h page 12 21 UART 2 Interrupt Mapping UART2MAP D29h page 12 21 PCI Interrupt A Mapping PCIINTAMAP D30h page 12 21 PCI Interrupt B Mapping PCIINTBMAP D31h page 12 21 PCI Interrupt C Mapping PCIINTCMAP D32h page 12 21 PCI Interrupt D Mapping PCIINTDMAP D33h page 12 21 DMA Buffer Chaining Interrupt Mapping DMABCINTMAP D40h page 12 21 SSI Interrupt Mapping SSIMAP D41h page 12 21 Watchdog Timer Interrupt Mapping WDTMAP D42h page 12 21 RTC Interrupt Mapping RTCMAP D43h page 12 21 Write Protect Violation Interrupt Mapping WPVMAP D44h page 12 21 AMDebug Technology RX TX Interrupt Mapping ICEMAP D45h Elan SC520 Microcontroller Register Set Manual page 12 21 1 5 AMD Table 1 1 Configuration Register Overview Memory Mapped Configuration Region MMCR Registers By Offset Continued Register Name Mnemonic MMCR Offset Page Number Floating Point Error Interrupt Mapping FERRMAP page 12 21 GPIRQO Interrupt Mapping GPOIMAP page 12 21 GPIRQ1 Interrupt Mapping GP1IMAP page 12 21 GPIRQ2 Interrupt Mapping GP2IMA
105. 3 2 1 0 5 PIO6 PIO5_ PIO4_ PIO3_ PIO2 PIO1 PIOO DATA DATA DATA DATA DATA DATA DATA DATA Reset R W R W R W R W R W R W R W R W RW Register Description This register is used to read or write the value for pins PIO15 PIOO Bit Definitions Bit Name 15 PIO15 DATA 14 PlO14 DATA 13 PIO13 DATA 12 PIO12 DATA 11 11__ DATA 10 PIO10 DATA 9 PIO9 DATA 8 PIO8 DATA 20 16 Function Read or Write the PIO15 Pin 0 2 PIO15 is Low 1 PIO15 is High Read or Write the PIO14 Pin 0 2 PIO14 is Low 1 PIO14 is High Read or Write the PIO13 Pin 0 PIO13 is Low 1 PIO13 is High Read or Write the PIO12 Pin 0 PIO12 is Low 1 PIO12 is High Read or Write the PIO11 Pin 0 2 PIO11 is Low 1 2 PIO11 is High Read or Write the PIO10 Pin 0 PIO10 is Low 1 PIO10 is High Read or Write the PIO9 Pin 0 2 PIO9 is Low 1 PIO9 is High Read or Write the PIO8 Pin 0 PIO8 is Low 1 PIO8 is High Elan SC520 Microcontroller Register Set Manual Programmable Input Output Registers AMD Function 7 PIO7_DATA Read or Write the PIO7 Pin 0 PIO7 is Low 1 is High 6 PIO6 DATA Read or Write the PIO6 Pin 0 PIO6 is Low 1 PIO6 is High 5 PIO5 DATA Read or Write the PIO5 Pin 0 PIO5 is Low 1 5 is High 4 4 DATA Read or Write the PIO4 Pin 0 PIO4 is Low 1 PIO4 is High 3 PIO3 DATA Read or Write the PIO3 Pin 0
106. 4 3 2 1 0 Bit MCB 7 0 Reset 0 0 0 0 0 0 0 0 R W R W Register Description This register contains one of the compare values for the GPTMR1ONT register see page 14 12 Bit Definitions Bit Name Function 15 0 MCB 15 0 GP Timer 1 Maxcount Compare Register B This register contains one of the maximum values that GP Timer 1 can count to before resetting its count register to O Programming Notes GP Timer 0 and GP Timer 1 each have two maxcount compare registers GPTMRxMAXCMPA and GPTMRxMAXCMPB If the maxcount compare register that is in use contains the value 0000h and the timer is enabled the timer counts to FFFFh at which point the appropriate action occurs based on the timer configuration options that are set For details see the GPTMR1CTL register bits INT MAX CNT RIU MAX_CNT ALT_CMP and CONT CMP starting on page 14 10 If the maxcount compare register that is in use contains a value other than 0000h and the timer is enabled the timer counts to the programmed maxcount value 14 14 Elan SC520 Microcontroller Register Set Manual GP Timer 2 Mode Control GPTMR2CTL AMD General Purpose Timer Registers Memory Mapped MMCR Offset C82h 15 14 13 12 11 10 9 8 Bit ENB P ENB WR INT ENB Reserved Reset 0 0 0 0 0 0 0 0 R W R W R W RSV 7 6 5 4 3 2 1 0 CONT_ Bit Reserved MAX_CNT Reserved CMP Reset 0 0 0 0 0 0 0 0 R W RSV R W RSV R W
107. 45 A20 Gate Control bit field 3 9 A20 Gate Data bit field 3 7 A20_GATE bit field 3 7 A20G_CTL bit field 3 9 Access is OCWS bit field in MPICOCW2 register 12 28 in MPICOCWS register 12 30 in S1PICOCW2 register 12 53 in S1PICOCWS register 12 55 in S2PICOCW2 register 12 41 in S2PICOCWS register 12 43 ADDDEC bit field in MSTDMAMODE register 11 91 in SLDMAMODE register 11 55 ADDDECCTL register 2 2 Address Decode Control register 2 2 Address Decrement bit field in MSTDMAMODE register 11 91 in SLDMAMODE register 11 55 Address Interval bit field in MPICICW1 register 12 26 in S1PICICW1 register 12 51 in S2PICICW1 register 12 39 AMD 1 ADI bit field in MPICICW1 register 12 26 in S1PICICW1 register 12 51 in S2PICICW1 register 12 39 ADR bit field 2 9 signal 6 16 AEO bit field in MPICICW4 register 12 35 in S1PICICW4 register 12 59 in S2PICICW4 register 12 47 AINIT bit field in MSTDMAMODE register 11 91 in SLDMAMODE register 11 55 Alarm Interrupt Enable bit field 17 16 Alarm Interrupt Flag bit field 17 18 ALM_AM_PM bit field 17 9 ALM_HOUR bit field 17 9 ALM_INT_ENB bit field 17 16 ALM_INT_FLG bit field 17 18 ALM_MINUTE bit field 17 7 ALM_SECOND bit field 17 5 ALT_CMP bit field in GPTMROCTL register 14 5 in GPTMRICTL register 14 11 Alternate CPU Core Reset Control bit field 3 9 Alternate Size for Channel x bit field 11 4 AM_PM bit field 17 8 Am5 86 CPU Control
108. 5 2 Status bit field 5 3 High Priority O bit field 5 7 High Priority 1 bit field 5 7 Request x Enable bit field 5 4 5 5 Status register 5 3 PCI Bus Host Bridge direct mapped registers table 6 2 indexed registers table 6 2 MMCR registers table 6 1 PCI Bus Reset bit field 6 3 PCI Configuration Address register 6 15 Data register 6 17 PCI Host Bridge Interrupt Mapping bit field 12 18 Interrupt Mapping register 12 17 NMI Enable bit field 12 17 PCI indexed registers table 1 11 PCI Interrupt Request INTx Polarity bit field 12 15 PCI Interrupt x Mapping register 12 21 PCI IRQ MAP bit field 12 18 PCI NMI ENB bit field 12 17 PCI RST bit field 6 3 PCIARBSTA register 5 3 PCICCREVID register 6 22 Index PCICFGADR register 6 15 PCICFGDATA register 6 17 PCIDEVID register 6 18 PCIHEADTYPE register 6 23 PCIHOSTMAP register 12 17 PCIINTAMAP register 12 21 PCIINTBMAP register 12 21 PCIINTCMAP register 12 21 PCIINTDMAP register 12 21 PCIMRETRYTO register 6 24 PCISTACMD register 6 19 PE bit field 18 22 PENB bit field 18 17 PER INT ENB bit field 17 16 PER INT FLG bit field 17 18 Periodic Interrupt Enable bit field 17 16 Flag bit field 17 18 PERR bit field 13 13 PERR signal in HBMSTIRQCTL register 6 10 in PCISTACMD register 6 20 PERR signal in HBMSTIRQCTL register 6 10 PERR DET bit field 6 19 PERR RES bit field 6 21 PG SZ bit field 2 7 PHS INV ENB bit field 19 3 PIC Poll Command
109. 58 SLAVE TMP bit field 11 59 SLCT_ICW1 bit field in MPICICW1 register 12 26 in MPICOCW2 register 12 28 in MPICOCWS register 12 30 in S1PICICW1 register 12 51 in S1PICOCW2 register 12 53 in S1PICOCWS register 12 55 in S2PICICW1 register 12 39 in S2PICOCW2 register 12 41 in S2PICOCWS register 12 43 SLDMACBP register 11 57 SLDMACTL register 11 51 SLDMAGENMSK register 11 61 SLDMAMODE register 11 55 SLDMAMSK register 11 54 SLDMAMSKRST register 11 60 SLDMARST register 11 58 SLDMASTA register 11 50 SLDMASWREOQ register 11 53 SLDMATMP register 11 59 SMM bit field in MPICOCWS register 12 30 in S1PICOCWS register 12 55 in S2PICOCWS register 12 43 SNGL bit field in MPICICW1 register 12 26 in S1PICICW1 register 12 52 in S2PICICW1 register 12 40 Software DMA Request bit field in MSTDMASWREQ register 11 89 SLDMASWREQ register 11 53 Software GP Bus Reset bit field 3 3 Software Interrupt 16 1 Control register 12 10 22 17 NMI Control register 12 13 Software NMI Source bit field 12 13 Software System Reset bit field 3 4 Elan SC520 Microcontroller Register Set Manual Index AMD Software Timer Configuration register 15 4 Microsecond Count register 15 3 Millisecond Count register 15 2 MMCR registers table 15 1 SOUTx signal 18 17 18 19 SP bit field 18 17 special cycle recognition bit not implemented 6 21 Special Fully Nested Mode Enable bit field in MPICICWA register 12 35 in S1PICICW
110. 6 21 Memory Access Enable bit field 6 21 memory write and invalidate enable bit not implemented 6 21 memory mapped configuration region MMCR registers table 1 2 Memory Mapped Device for DMA Channel x bit field 11 5 microcontroller reset sources table 3 6 Microprocessor Mode bit field in MPICICWA register 12 35 in S1PICICWA register 12 59 in S2PICICWA register 12 47 Minor Stepping Level bit field 4 2 MINORSTEP bit field 4 2 MINUTE bit field 17 6 MODE bit field in BOOTCSCTL register 9 2 in ROMCS1CTL register 9 4 in ROMCS2CTL register 9 6 MODSEL bit field in MSTDMAMODE register 11 92 in SLDMAMODE register 11 56 MONTH bit field 17 12 MPICICW1 register 12 26 MPICICW2 register 12 32 MPICICWS register 12 33 MPICICWA register 12 35 MPICINTMSK register 12 36 MPICIR register 12 24 MPICISR register 12 25 Elan SC520 Microcontroller Register Set Manual Index AMD MPICMODE register 12 6 MPICOCW2 register 12 28 MPICOCWS register 12 30 MS ONT bit field 15 2 MSBF ENB bit field 19 3 MSKSEL bit field in MSTDMAMSK register 11 90 in SLDMAMSK register 11 54 MSTDMACBP register 11 93 MSTDMACTL register 11 87 MSTDMAGENMSK register 11 97 MSTDMAMODE register 11 91 MSTDMAMSK register 11 90 MSTDMAMSKRST register 11 96 MSTDMARST register 11 94 MSTDMASTA register 11 86 MSTDMASWREOQ register 11 89 MSTDMATMP register 11 95 MSTINTADD register 6 14 MULT INT ENB bit field 7 9 Multi Bit Er
111. 6 3 This register PCISTACMD is register number 1 in the host bridge specific PCI configuration space The PCI Local Bus Specification Revision 2 2 defines four bit fields in the Status Command register that are reserved in the ElanSC520 microcontroller These PCI bus functions do not apply to the host bridge controller Wait cycle control bit 7 the host bridge controller does not support address data stepping VGA palette snoop enable bit 5 the host bridge is not a graphics device Memory write and invalidate enable bit 4 the host bridge does not generate memory write and invalidate commands as a PCI bus master Special cycle recognition bit 3 the host bridge ignores PCI bus special cycles Elan SC520 Microcontroller Register Set Manual 6 21 PCI Bus Host Bridge Registers Class Code Revision ID PCICCREVID Address OCF8h OCFCh PCI Index 08h 81 30 29 28 27 26 25 24 Bit CL CD 7 0 Reset 0 0 0 0 0 1 1 0 R W R 23 22 21 20 19 18 17 16 SBCL_CD 7 0 Reset 0 0 0 0 0 0 0 0 R W R 15 14 13 12 11 10 9 8 PRG IF 7 0 Reset 0 0 0 0 0 0 0 0 R W R 7 6 5 4 3 2 1 0 REV_ID 7 0 Reset 0 0 0 0 0 0 0 0 R W R Register Description This register contains the PCI configuration header space class code program interface and revision identification Bit Defin
112. 9 Pulse Width register 10 8 Qualification register 10 5 Recovery Time register 10 7 GP Echo Mode register 10 2 GP Read Offset register 10 11 GP Read Pulse Width register 10 10 GP Timer 0 Count register 14 6 Interrupt Mapping register 12 21 Maxcount Compare A register 14 7 Maxcount Compare B register 14 8 Mode Control register 14 3 GP Timer 1 Count register 14 12 Interrupt Mapping register 12 21 Maxcount Compare A register 14 13 Maxcount Compare B register 14 14 Mode Control register 14 9 GP Timer 2 Count register 14 17 Interrupt Mapping register 12 21 Maxcount Compare A register 14 18 Mode Control register 14 15 GP Timer x Alternate Compare bit field in GPTMROCTL register 14 5 in GPTMR1CTL register 14 11 GP Timer x Continuous Mode bit field in GPTMROCTL register 14 5 in GPTMR1CTL register 14 11 in GPTMR2CTL register 14 16 GP Timer x Count Register bit field in GPTMROCNT register 14 6 in GPTMRICNT register 14 12 in GPTMR2CNT register 14 17 GP Timer x Enable bit field in GPTMROCTL register 14 3 in GPTMR1CTL register 14 9 in GPTMR2CTL register 14 15 GP Timer x External Clock bit field in GPTMROCTL register 14 5 in GPTMR1CTL register 14 11 GP Timer x Interrupt Enable bit field in GPTMROCTL register 14 4 in GPTMR1CTL register 14 10 in GPTMR2CTL register 14 16 GP Timer x Interrupt Status bit field 14 2 GP Timer x Maxcount Compare Register In Use bit field in GPTMROCTL register 14 4 in GPTMR1CT
113. 9 5 in ROMCS2CTL register 9 7 Floating Point Error Interrupt Clear register 12 61 Floating Point Error Interrupt Mapping register 12 21 Force Bad ECC Check Bits bit field 7 12 FPUERR RST bit field 12 61 FPUERRCLR register 12 61 Framing Error bit field 18 22 FRC BAD CHK bit field 7 12 Function Number bit field 6 16 FUNCTION NUM bit field 6 16 G General 0 register 11 62 General 1 register 11 66 General 2 register 11 67 General 3 register 11 68 General 4 register 11 70 General 5 register 11 74 General 6 register 11 75 General 7 register 11 76 General 8 register 11 77 General Purpose CMOS RAM 114 bytes 17 21 General Purpose Interrupt Request GPIRQx Polarity bit field 12 15 12 16 General Purpose R W Register bit field in GPDMAGRO register 11 62 in 1 register 11 66 in GPDMAGR2 register 11 67 in GPDMAGR3 register 11 68 in GPDMAGR4 register 11 70 in GPDMAGRS register 11 74 in GPDMAGRE register 11 75 in GPDMAGR7 register 11 76 in GPDMAGR8 register 11 77 general purpose timer MMCR registers table 14 1 GNT_TO_ID bit field 5 3 GNT TO INT ENB bit field 5 2 GNT TO STA bit field 5 3 GNTx signal 5 3 5 4 5 5 5 7 GP Bus Echo Mode Enable bit field 10 2 minimum timing table 10 2 GP bus MMCR registers table 10 1 GP bus signal timing adjustment figure 10 7 Elan SC520 Microcontroller Register Set Manual AMD GP Chip Select Data Width register 10 3 Offset register 10
114. A bit field in this register GPDMAMMIO is ignored if the corresponding channel is mapped to an internal UART via the GPDMAEXTCHMAPB register see page 11 8 Elan SC520 Microcontroller Register Set Manual 11 5 AMD GP DMA Controller Registers GP DMA Resource Channel Map A GPDMAEXTCHMAPA Memory Mapped MMCR Offset D82h 15 14 13 12 11 10 9 8 Bit GPDRQS3 CHSEL 3 0 GPDRQ2_CHSEL 3 0 Reset 1 1 1 1 1 1 1 1 R W R W R W 7 6 5 4 3 2 1 0 Bit GPDRQ1 CHSEL 3 0 GPDRQO CHSEL 3 0 Reset 1 1 1 1 1 1 1 1 R W R W R W Register Description This register indicates the channel mapping for the GPDRQ3 GPDRQO and GPDACKS GPDACKO pins Bit Definitions Bit Name 15 12 GPDRQ3_ CHSEL 3 0 11 8 GPDRQ2_ CHSEL 3 0 Function GPDRQ3 Channel Mappin Map the GPDRQ3 and GPDACK3 pins to a GP DMA channel 0000 Channel 0 0001 Channel 1 0010 Channel 2 0011 Channel 3 0101 Channel 5 0110 Channel 6 0111 Channel 7 All other values are treated as unconnected GPDRQ2 Channel Mapping Map the GPDRQ2 and GPDACK2 pins to a GP DMA channel 0000 Channel 0 0001 Channel 1 0010 Channel 2 0011 Channel 3 0101 Channel 5 0110 Channel 6 0111 Channel 7 All other values are treated as unconnected Elan SC520 Microcontroller Register Set Manual Bit Name 7 4 GPDRQ1_ CHSEL 3 0 3 0 GPDRQO CHSEL 3 0 Programming Notes GP DMA Controller Regi
115. AM Programmable Input Output Registers PIO15 PIOO Direction PIODIR15 0 Memory Mapped MMCR Offset C2Ah 15 14 13 12 11 10 9 8 Bi PIO15_ PIO14_ PIO13_ PIO12_ PIO11_ PIO10_ PIOS PIO8 _ DIR DIR DIR DIR DIR DIR DIR DIR Reset 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W 7 6 5 4 3 2 1 0 Bit PIO7_ PIO6_ PIO5_ PIO4_ PIO3_ PIO2_ PIO1_ PIOO_ DIR DIR DIR DIR DIR DIR DIR DIR Reset 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Register Description This register contains the direction bits for pins PIO15 PIOO Bit Definitions Bit Name Function 15 PIO15 DIR PIO15 Input or Output Select This bit programs PIO15 as an input or output 0 Input 1 Output 14 PlO14 DIR PIO14 Input or Output Select This bit programs PIO14 as an input or output 0 Input 1 Output 13 PIO13 DIR PIO13 Input or Output Select This bit programs PIO13 as an input or output 0 Input 1 Output 12 PIO12 DIR PIO12 Input or Output Select This bit programs PIO12 as an input or output 0 Input 1 Output 11 PIO11 DIR PIO11 Input or Output Select This bit programs PIO11 as an input or output 0 Input 1 Output 10 PIO10 DIR PIO10 Input or Output Select This bit programs PIO10 as an input or output 0 Input 1 Output 20 12 Elan SC520 Microcontroller Register Set Manual Bit Name 9 PIO9 DIR 8 PIO8 DIR 7 PIO7 DIR 6 PlO6 DIR 5 PIOS DIR 4 PIO4 DIR 3 DIR 2 PIO2 DIR 1
116. AT compatibility 16 bit DMA transfers on the master DMA controller For 16 bit transfers each transfer is two bytes so a transfer count of FFFFh results in a transfer of 128 Kbytes The value in this register GPDMAGTO can be used with the value in the GPDMAEXTTC6 register see page 11 19 to allow counts of up to 16 M 16 777 216 transfers In PCI bus 2 2 compliant designs software must limit the length of GP bus DMA demand or block mode transfers Very large transfers could cause the PCI Host Bridge target controller to violate the 10 us memory write maximum completion time limit set in the PC Local Bus Specification Revision 2 2 lan SC520 Microcontroller Register Set Manual 11 83 AMD GP DMA Controller Registers Master DMA Channel 7 Memory Address GPDMA7MAR Direct Mapped Address 00CCh 7 6 5 4 3 2 1 0 Bit DMA7MAR 16 1 Reset X X X X X X X X R W R W Register Description This register contains bits 16 1 of the memory address for Channel 7 during DMA operation Bit Definitions Bit Name Function 7 0 DMA7MAR Lower 16 Bits of DMA Channel 7 Memory Address 16 1 This 8 bit field is used in two successive I O accesses to read or write the channel s memory address bits 16 1 for 16 bit DMA transfers Bits 8 1 of the channel s memory address can be read from or written to this bit field immediately after a write to the MSTDMACBP register see page 11 93 Bits 16 9 o
117. Address High ADR 27 16 This bit field provides address bits A27 A16 of the next memory buffer to be used by Channel 5 in the buffer chaining mode Programming Notes The value of this register is ignored if buffer chaining mode is not enabled for this channel in the GPDMABCCTL register see page 11 21 lan SC520 Microcontroller Register Set Manual 11 29 AMDA GP DMA Controller Registers GP DMA Channel 6 Next Address Low GPDMANXTADDL6 Memory Mapped MMCR Offset DA8h 15 14 13 12 11 10 9 8 Bit DMA6 NXT ADR 15 8 Reset 0 0 0 0 0 0 0 0 R W R W 7 6 5 4 3 2 1 0 Bit DMA6 NXT ADR 7 0 Reset 0 0 0 0 0 0 0 0 R W R W Register Description This register provides address bits A15 A0 of the next memory address for Channel 6 in buffer chaining mode Bit Definitions Bit Name Function 15 0 DMA6_NXT_ DMA Channel 6 Next Address Low ADR 15 0 This bit field provides address bits A15 A0 of the next memory buffer to be used by Channel 6 in the buffer chaining mode Programming Notes The value of this register is ignored if buffer chaining mode is not enabled for this channel in the GPDMABCCTL register see page 11 21 Bit 0 of this register GPDMANXTADDLE6 is ignored for 16 bit mode transfers so the buffer address used is always even in 16 bit mode Software should ensure that 16 bit mode buffers always begin on an even word boundary 11 30 Elan
118. Architecture Mindshare Inc Reading MA Addison Wesley 1995 ISBN 0 201 40993 3 ISA System Architecture Mindshare Inc Reading MA Addison Wesley 1995 ISBN 0 201 40996 8 80486 System Architecture Mindshare Inc Reading MA Addison Wesley 1995 ISBN 0 201 40994 1 The Indispensable PC Hardware Book Hans Peter Messmer Wokingham England Addison Wesley 1995 ISBN 0 201 87697 3 lan SC520 Microcontroller Register Set Manual xvii AMD Table O 1 xviii Introduction DOCUMENTATION CONVENTIONS Table 0 1 lists the documentation conventions used throughout this manual Documentation Notation Notation Meaning Reset Default Values Default Value after a system reset 0 Low 1 Active or High X No value is guaranteed Determined by sources external to the lanSC520 microcontroller Read Write Attributes R The bit field is read only A write to the register at this bit field has no effect The contents may or may not be changed by hardware W The bit field is write only Reading this register at this bit field does not return a meaningful value and has no side effects R W The bit field is read write Reading the register at this bit field always returns the last value written Reads have no side effects R W The bit field is read write with conditions The indicates that there are side effects to using this bit For example reading a bit or regist
119. Bit Reserved REQ4 ENB REQ2 ENB REQ1 0 0 0 0 0 0 0 0 R W RSV R W R W R W R W R W Register Description This register selects the masters that are enabled for arbitration Bit Definitions Bit 15 5 Name Reserved REQ4 ENB REQ3_ENB REQ2_ENB REQ1 ENB Function Reserved This bit field should be written to 0 for normal system operation PCI Bus Arbiter Request 4 Enable This bit enables the PCI master request connected to the REQ4 pin If this request is disabled the PCI bus arbiter does not assert GNT4 to allow the PCI master connected to REQ4 and GNT4 to access the PCI bus 0 The PCI master request connected to the REQ4 pin is disabled 1 The PCI master request connected to the REQ4 pin is enabled PCI Bus Arbiter Request 3 Enable This bit enables the PCI master request connected to the REQ3 pin If this request is disabled the PCI bus arbiter does not assert to allow the PCI master connected to the REQ3 and GNT3 pins to access the PCI bus 0 The PCI master request connected to the REQ3 pin is disabled 1 The PCI master request connected to the REQ3 pin is enabled PCI Bus Arbiter Request 2 Enable This bit enables the PCI master request connected to the REQ2 pin If this request is disabled the PCI bus arbiter does not assert GNT2 to allow the PCI master connected to the REQ2 and GNT2 pins to access
120. CNT Reserved BNK1 COLWDTH 1 0 BNKO BNK CNT Reserved BNKO_ COLWDTH 1 0 Programming Notes SDRAM Controller Registers Function Bank 1 Internal SDRAM Bank Count This bit specifies the number of internal banks supported by the SDRAM devices 0 2 bank device 1 4 bank device Reserved This bit field should be written to 0 for normal system operation Bank 1 Column Address Width These two bits specify the column address width of the SDRAM devices populated in Bank 1 00 8 bit column address 01 9 bit column address 10 10 bit column address 11 11 bit column address Bank 0 Internal SDRAM Bank Count This bit specifies the number of internal banks supported by the SDRAM devices 0 2 bank device 1 4 bank device Reserved This bit field should be written to 0 for normal system operation Bank 0 Column Address Width These two bits specify the column address width of the SDRAM devices populated in Bank 0 00 8 bit column address 01 9 bit column address 10 10 bit column address 11 11 bit column address This register DRCCFG should be modified only when the write buffer and the read ahead feature of the read buffer are disabled in the DBCTL register see page 8 3 Before changing the BNKx_BNK_CNT BNKx COLWDTH bit fields software must issue an All Banks Precharge command to the SDRAM devices via the OPMODE SEL bit field in the DBCCTL register see page 7 3 This command returns the SDRAM
121. Function Reserved This bit field should be written to 0 for normal system operation I O Pad Drive Strength for SCS3 SCSO These bits select the drive strength of I O pads for the SCS3 SCSO signals 00 Reserved 01 2 18 mA pads 10 12 mA pads default 11 Reserved Note Default state of SCS3 SCSO drive strength is 12 mA I O Pad Drive Strength for SRASA SRASB SCASA SCASB and SWEA SWEB These bits select the drive strength of I O pads for the SRASA SRASB SCASA SCASB and SWEA SWEB signals 00 24 mA pads default 01 18 mA pads 10 12 mA pads 11 Reserved Pad Drive Strength for SDQM3 SDQMO These bits select the drive strength of I O pads for the SDQM3 SDQMO signals 00 24 mA pads default 01 18 mA pads 10 12 mA pads 11 Reserved Elan SC520 Microcontroller Register Set Manual Programmable Input Output Registers AMD 3 2 MA_DRIVE Pad Drive Strength for MA12 MAO and BA1 BAO 1 0 These bits select the drive strength of I O pads for the MA12 MAO and BA1 BAO signals 00 24 mA pads default 01 18 mA pads 10 12 mA pads 11 Reserved 1 0 DATA_DRIVE Pad Drive Strength for MD31 MD0 and MECC6 MECCO 1 0 These bits select the drive strength of I O pads for the MD31 MDO and 6 signals 00 24 mA pads default 01 18 mA pads 10 12 mA pads 11 Reserved Programming Notes Elan SC520 Microcontroller Register Set Manual 20 11
122. GP Timer 1 The count rate depends on the value of the PSC_SEL and EXT_CLK bits in the GPTMRICTL register see page 14 11 and page 14 11 Ifthe EXT CLK and PSC SEL bits are both 0 the count is incremented every fourth processor clock cycle Ifthe EXT CLK bit is 0 and the PSC_SEL bit is 1 the count is incremented each time the GP Timer 2 maxcount is reached Ifthe EXT CLK bitis 1 the count is incremented on every positive edge driven on the TMRIN1 input pin up to 1 4 of the CPU clock speed This register GPTMR1CNT can be read at any time to determine the remaining count duration until a maximum count value is reached at which time this register is reset by hardware This register can also be written at any time If this register is written while the counter is enabled the new value is latched into the GP Timer 1 counter and counting proceeds from this new value Programming Notes Each time this GPTMR1ONT register is incremented its value is compared with the value of register GPTMR1MAXCMPA or GPTMR1MAXCMPB see page 14 13 and page 14 14 and various actions are taken when a maximum count is reached For details see the GPTMR1CTL register bits INT ENB MAX CNT RIU MAX ONT ALT CMP and CONT starting on page 14 10 14 12 Elan SC520 Microcontroller Register Set Manual General Purpose Timer Registers AMDA GP Timer 1 Maxcount Compare A GPTMR1MAXCMPA Memory Mapped MMCR Offset C7Eh
123. GP8IMAP GPIRQO Interrupt Mapping GP9IMAP GPIRQ10 Interrupt Mapping GP10IMAP 7 6 5 4 3 2 AMD Memory Mapped MMCR Offset D1Ah MMCR Offset D1Bh MMCR Offset D1Ch MMCR Offset D20h MMCR Offset D21h MMCR Offset D22h MMCR Offset D28h MMCR Offset D29h MMCR Offset D30h MMCR Offset D31h MMCR Offset D32h MMCR Offset D33h MMCR Offset D40h MMCR Offset D41h MMCR Offset D42h MMCR Offset D43h MMCR Offset D44h MMCR Offset D45h MMCR Offset D46h MMCR Offset D50h MMCR Offset D51h MMCR Offset D52h MMCR Offset D53h MMCR Offset D54h MMCR Offset D55h MMCR Offset D56h MMCR Offset D57h MMCR Offset D58h MMCR Offset D59h MMCR Offset D5Ah Bit Reserved INT MAP 4 0 Reset 0 0 0 0 0 0 R W RSV R W Elan SC520 Microcontroller Register Set Manual 12 21 AMD Programmable Interrupt Coniroller Registers Register Description These registers map each of the interrupt sources except for ECC and PCI Host Bridge interrupts see page 12 19 and page 12 17 respectively to their desired interrupt channel or NMI Bit Definitions Bit Name Function 7 5 Reserved Reserved This bit field should be written to 0 for normal system operation 4 0 INT MAP 4 0 Interrupt Mapping The value in this 5 bit field maps the interrupt source for the register to one of the following interrupt priority channels on the microcontroller or as an NM 00000 Disables the interrupt source as an input 000
124. GPDMANXTTCL7 Memory Mapped MMCR Offset DBCh 15 14 13 12 11 10 9 8 Bit DMA7_NXT_TC 15 8 Reset 0 0 0 0 0 0 0 0 R W R W 7 6 5 4 3 2 1 0 Bit DMA7_NXT_TC 7 0 Reset 0 0 0 0 0 0 0 0 R W R W Register Description This register provides bits 15 0 of the next transfer count for Channel 7 in buffer chaining mode Bit Definitions Bit Name Function 15 0 DMA7 NXT DMA Channel 7 Next Transfer Count Low TC 15 0 This bit field provides bits 15 0 of the next transfer count to be used by Channel 7 in the buffer chaining mode Programming Notes The value of this register is ignored if buffer chaining mode is not enabled for this channel in the GPDMABCCTL register see page 11 21 In PCI bus 2 2 compliant designs software must limit the length of GP bus DMA demand or block mode transfers Very large transfers could cause the PCI Host Bridge target controller to violate the 10 us memory write maximum completion time limit set in the PCI Local Bus Specification Revision 2 2 11 40 Elan SC520 Microcontroller Register Set Manual GP DMA Controller Registers AMDA GP DMA Channel 7 Next Transfer Count High GPDMANXTTCH7 Memory Mapped MMCR Offset DBEh 7 6 5 4 3 2 1 0 Bit DMA7 NXT TC 23 16 Reset 0 0 0 0 0 0 0 0 R W R W Register Description This register provides bits 23 16 of the next transfer count for Channel
125. In this mode the GPTMR1MAXCMPPB register is not used In single compare mode the TMROUT1 pin is high while the counter is counting and being compared to the GPTMR1MAXCMPA register The TMROUT1 pin is pulsed Low for a single CPU clock cycle after the maximum value is reached 1 Alternate compare square wave mode if the timer is enabled the timer counts to the GPTMR1MAXCMPA register value and then resets the GPTMR1CNT register to 0 Then the timer counts to the GPTMR1MAXCMPPB register value page 14 14 and then resets the GPTMR1ONT register value to 0 In alternate compare mode the TMROUT1 pin is high while the counter is counting and being compared to the GPTMR1MAXCMPA register The TMROUT1 pin is Low while the counter is counting and being compared to the GPTMR1MAXCMPB register If the CONT bit is set alternate compare mode generates a square wave signal on the TMROUT 1 pin with a frequency and duty cycle determined by the two maximum count register values Note If external clocking is used and the clock is stopped during a count sequence the timer output remains in its previous state i e the state it was in prior to the clock stopping The remaining timer status also remains the same and normal operation commences upon the external clock being driven again See the Continuous mode bit description below for a more detailed description of how the comparison registers are used in continuous and noncontinuous modes GP
126. Loopback mode is disabled 1 Loopback mode is enabled The following internal connections are made by setting this diagnostic bit RTSx is internally connected to CTSx DTRx is internally connected to DSRx out is internally connected to RINx out2 is internally connected to DCDx Also the SOUTx pin is driven High the SIN input line is blocked and interrupt generation to the PIC is disabled The transmit shift register is directly connected to the receive shift register In addition the DTRx and RTSx signals and the internal out1 and out2 signals are forced inactive Modem status events UARTxMSR register see page 18 23 can be forced by setting the EMSI bit the UARTxINTENB register see page 18 11 and changing one of the bits OUT2 OUT1 RTS or DTR in this register UARTxMCR in loopback mode Enable UART x Interrupts This bit controls the internal out2 signal which is used internally as a master enable for UART x interrupts when loopback mode is disabled 0 No UART x interrupt requests are sensed at the Programmable Interrupt Controller PIC 1 UART x interrupt requests are enabled In loopback mode the internal out2 signal is internally connected to the DCDx signal which can be read via the DCD bit in the UARTxMSR register see page 18 23 0 In loopback mode the out2 signal forces DCDx High deasserted 1 In loopback mode the out2 signal forces DCDx Low asserted out1 Control This bit controls
127. O Address 70h 71h RTC Index 02h 7 6 5 4 3 1 0 Bit MINUTE 7 0 Reset X X X X X X x R W R W Register Description This register is used to initialize and read back the RTC current minute Bit Definitions Bit Name Function 7 0 MINUTE 7 0 RTC Current Minute Software initializes the minutes value for the RTC by writing data to this bit field in either binary or binary coded decimal BCD format The minutes component of the RTC time can be read from this bit field The RTC logic updates this bit field once per second Valid values for this bit field range from 0 to 59d If a value greater than 59d is programmed the bit field value increments up to FFh wraps around to 0 and only then does the value remain in the valid range Programming Notes Software can suspend updating of the RTC via the SET bit in the RTCCTLB register see page 17 16 Software selects binary or BCD format via the DATE_MODE bit in the RTCCTLB register 17 6 Elan SC520 Microcontroller Register Set Manual Real Time Clock Registers AMDA RTC Alarm Minute RTCALMMIN I O Address 70h 71h RTC Index 03h 7 6 5 4 3 2 1 0 Bit ALM MINUTE 7 0 Reset x x x x x x R W R W Register Description This register used to initialize and read back the RTC alarm minute Bit Definitions Bit 7 0 MINUTE 7 0 Programming Notes Function RTC Alarm Min
128. OVERVIEW This chapter describes the universal asynchronous receiver transmitter UART registers of the ElanSC520 microcontroller The lanSC520 microcontroller includes two industry standard 16550 compatible UARTs The UART register set includes two groups of registers B Six memory mapped configuration region MMCR registers are used to configure and control UART functions specific to the ElanSC520 microcontroller 24 direct mapped I O registers are used for industry standard UART configuration control and status functions See the Elan SC520 Microcontroller User s Manual order 22004 for details about the UARTs Table 18 1 and Table 18 2 list each type of UART register in offset order with the corresponding description s page number 18 2 REGISTERS Table 18 1 UART MMCR Registers Register Name Mnemonic MMCR Offset Page Number UART 1 General Control UART1CTL page 18 3 UART 1 General Status UART1STA page 18 4 UART 1 FIFO Control Shadow UART1FCRSHAD page 18 5 UART 2 General Control UART2CTL page 18 3 UART 2 General Status UART2STA page 18 4 UART 2 FIFO Control Shadow UART2FCRSHAD page 18 5 Table 18 2 UART Direct Mapped Registers Register Name Mnemonic l O Address Page Number UART 2 Transmit Holding UART2THR page 18 7 UART 2 Receive Buffer UART2RBR page 18 8 UART 2 Baud Clock Divisor Latch LSB UART2BCDL page 18 9 UART 2 Baud Clock Divisor Latch MSB UART2BCDH page 18 10 UART 2 Interrupt Ena
129. RIU bit to determine where the timer is in its current count sequence 0 Software must clear this bit by writing a O to it This bit is never automatically cleared by hardware 1 This bit is set by hardware any time the timer count value reaches a maximum count value maximum count value A or maximum count value B This bit cannot be set by software When GP Timer 1 is in alternate compare mode the ALT CMP bit 1 the MAX CNT bit is set whenever the GP Timer 1 count value equals the value of either register GPTMR1MAXCMPA see page 14 13 or GPTMR1MAXCMPB page 14 14 The MAX ONT bit is set for this condition regardless of the state of the INT bit The MAX ONT bit can be used to monitor timer status through software polling instead of making use of interrupt generation GP Timer 1 Retrigger This bit determines the control function provided by the GP Timer 1 input pin TMRIN1 when TMRIN 1 is not configured as the timer clock source i e when the EXT CLK bit is 0 0 A high level on the TMRIN1 input pin allows the timer to count and a Low level on this pin holds the timer count value constant 1 If the timer is enabled a 0 to 1 edge transition on the TMRIN1 pin resets the existing GP Timer 1 count value and then counting continues This bit is ignored when external clocking is selected i e when the EXT bitis 1 Elan SC520 Microcontroller Register Set Manual Bit Name 3 PSC_SEL 2 EXT_CLK 1
130. RP eee bep ER ER 13 1 13 2 Hegisters ER lags A Le 13 1 PIT Channel 0 Count 13 2 PIT Channel 1 Count 1 1 13 3 PIT Channel 2 Count 2 13 4 PIT O Status PITOSTA 2 nsere ht Clulpedoepbbi m d 13 5 PIT 1 Status PITISTA citiin sinuen na e a iE eee 13 5 PIT 2 Status PIT2STA i se i ae cee 13 5 PIT Mode Control 13 7 PIT Counter Latch Command PITCNTLAT 13 10 PIT Read Back Command 13 11 System Control Port B 18 13 CHAPTER 14 GENERAL PURPOSE TIMER REGISTERS 14 1 14 1 14 1 14 2 Flegisters ee cod bonded ee ba ee eked Mend 14 1 GP Timers Status 5 14 2 GP Timer 0 Mode Control 14 3 GP Timer 0 Count 14 6 GP Timer 0 Maxcount Compare A GPTMROMAXCMPA 14 7 GP Timer 0 Maxcount Compare B GPTMROMAXCMPB 14 8 GP Timer 1 Mode Control 1 1 14 9 GP Timer 1 Count 1 14
131. Register Set Manual UART Serial Port Registers AMDA Direct Mapped UART 2 Interrupt Enable UART2INTENB I O Address 02F9h UART 1 Interrupt Enable UART1INTENB I O Address O3F9h 7 6 5 4 3 2 1 0 Bit Reserved EMSI ERLSI ETHREI ERDAI Reset 0 0 0 0 0 0 0 0 R W RSV R W R W R W R W Register Description This register enables the following serial port interrupts modem status receiver line status transmitter holding register empty received data available and time out interrupt This register can be accessed only when the DLAB bit is in the UARTxLCR register see page 18 17 Each interrupt can individually activate the interrupt request signal Bit Definitions Bit Name Function 7 4 Reserved Reserved This bit field should be written to O for normal system operation 3 EMSI Enable Modem Status Interrupt 0 Disable modem status interrupt 1 Enable modem status interrupt 2 ERLSI Enable Receiver Line Status Interrupt 0 Disable receiver line status interrupt 1 Enable receiver line status interrupt 1 ETHREI Enable Transmitter Holding Register Empty Interrupt 0 Disable transmitter holding register empty interrupt 1 Enable transmitter holding register empty interrupt 0 ERDAI Enable Received Data Available Interrupt 0 Disable data available interrupt in 16450 compatible mode in 16550 compatible mode disable FIFO trigger level reached interrupt and time out interrupt 1
132. Registers Master Retry Time Out PCIMRETRYTO Address OCF8h OCFCh PCI Index 41h 7 6 5 4 3 2 1 0 Bit M_RETRY_TO 7 0 Reset 0 0 0 0 0 0 0 0 R W R Register Description This register contains the PCI master retry time out Bit Definitions Bit Name Function 7 0 M RETRY TO Master Retry Time Out 7 0 This bit field defines the number of times the master controller retries a transaction before aborting the cycle For read transactions that are aborted due to a time out a data value of FFFFFFFFh is returned to the Am5 86 CPU 00h2 Retry time out disabled The master controller continues to retry the transaction until the target responds This is the default value Other The master controller continues to retry the transaction for the number of times programmed into this bit field For example if this bit field is set to 80h the number of retries is 128 Therefore the total number of attempts including the initial attempt is the number of retries programmed in this bit field plus 1 Programming Notes This register is reset by a system reset or by a PCI bus reset A PCI bus reset is initiated by setting the PCI RST bit in the HBCTL register see page 6 3 This register PCIMRETRYTO is byte 1 of register number 16d in the host bridge specific PCI configuration space This register must not be changed except when there is no outstanding CPU to PCI bus transaction pending This is th
133. Reserved This bit field should be written to 0 for normal system operation Elan SC520 Microcontroller Register Set Manual ROM Flash Controller Registers AMDA Bit Name Function 2 0 FIRST_DLY Chip Select 1 Device Delay for First Access 2 0 This bit field is used to configure the number of wait states for the first access to the ROM and for subsequent accesses if the MODE bit is 0 000 0 wait states 001 1 wait state 010 2 wait states 011 3 wait states 100 4 wait states 101 5 wait states 110 6 wait states 111 7 wait states Programming Notes Elan SC520 Microcontroller Register Set Manual 9 5 AMD ROM Flash Controller Registers ROMCS2 Control ROMCS2CTL Memory Mapped MMCR Offset 56h 15 14 13 12 11 10 9 8 Bit Reserved DGP WIDTH 1 0 MODE Reserved Reset 0 0 0 0 0 0 0 0 R W RSV R W R W R W RSV 7 6 5 4 3 2 1 0 Bit Reserved SUB DLY 1 0 Reserved FIRST DLY 2 0 Reset 0 0 1 1 0 1 1 1 R W RSV R W RSV R W Register Description This register contains configuration information about the location i e SDRAM bus or GP bus width operation mode and timing of the ROM devices that are attached to the ElanSC520 microcontroller ROMCS2 signal Bit Definitions Bit Name 15 13 Reserved 12 DGP 11 10 WIDTH 1 0 9 MODE 8 6 Reserved 5 4 SUB DLY 1 0 3 Reserved 9 6 Function Reserved This bit field sh
134. Set Manual Table of Contents AMD GP Timer 0 Interrupt Mapping 12 21 GP Timer 1 Interrupt Mapping 1 12 21 GP Timer 2 Interrupt Mapping 2 12 21 PIT 0 Interrupt Mapping 12 21 PIT 1 Interrupt Mapping 1 12 21 PIT 2 Interrupt Mapping 2 12 21 UART 1 Interrupt Mapping 1 12 21 UART 2 Interrupt Mapping 2 12 21 PCI Interrupt A Mapping 12 21 PCI Interrupt B Mapping 12 21 PCI Interrupt C Mapping 12 21 PCI Interrupt D Mapping 12 21 DMA Buffer Chaining Interrupt Mapping DMABCINTMAP 12 21 SSI Interrupt Mapping 1 12 21 Watchdog Timer Interrupt Mapping WDTMAP 12 21 RTC Interrupt Mapping RTCMAP 12 21 Write Protect Violation Interrupt Mapping WPVMAP 12 21 AMDebug Technology RX TX Interrupt Mapping ICEMAP 12 21 Floating Point Error Interrupt Mapping FERRMAP 12 21 GPIRQO Interrupt Mapping
135. This bit field determines the Bank 0 boundary defined in 4 Mbyte increments This value is compared to physical address bits 28 22 during an SDRAM request to select a bank Bank 0 is selected if physical address bits 28 22 are less than the BNKO END bit field value Programming Notes This register DRCBENDADR should be modified only when the write buffer and the read ahead feature of the read buffer are disabled in the DBCTL register see page 8 3 The value specified in each BNKx END bit field determines the upper address boundary of the corresponding SDRAM bank in 4Mbyte increments Each bank s lower boundary is determined by the end of the next lower enabled bank so the addressable SDRAM space is the concatenation of the enabled banks The top of the highest configured bank is the top of memory If any particular bank is disabled via its BNKx ENB bit the associated BNKx END bit field value has no effect Banks do not have to be enabled contiguously Figure 7 1 gives a few examples of SDRAM bank configuration Figure 7 1 Examples of Bank Ending Address Configuration Example 1 Example 2 Example 3 1FFFFFFh 37FFFFFh BFFFFFFh BNK3 END BNK3 END BNK3 END Bank 3 8 Mbytes 08h 32 Mbytes 64 Mbytes 30h 1800000h 1800000n 4 8000000 BNK2 END Disabled NAA BNK2 END BNK2_ENB 0 E an ioo0000n 96 e 4000000h 20h FFFFFFh 17FFFFFh 3FFFFFF
136. This register is the first initialization register of the Master controller Bit Definitions Bit 7 5 12 26 Name Reserved SLCT_ICW1 LTIM ADI SNGL Function Reserved This bit field should be written to 0 for normal system operation This I O address changes functions when read See the programming notes for this register MPICICW1 on page 12 27 Select ICW1 Software must set this bit to 1 when writing this address Port 0020h to access this register MPICICW1 0 The write does not access this register MPICICW1 Instead either the MPICOCW2 register see page 12 28 or the MPICOCWS register see page 12 30 is written depending on the state of bit 3 1 The write accesses this register MPICICW1 Subsequent writes to Port 0021h access additional initialization control words See the programming notes for this register MPICICW1 on page 12 27 Level Triggered Interrupt Mode This bit is the global interrupt mode selection for the Master PIC 0 Edge sensitive interrupt request detection 1 Level sensitive interrupt request detection If the M GINT MODE bit in the PICICR register is set see page 12 5 the LTIM bit determines the interrupt mode for the Master PIC channels If the M GINT MODE bit is cleared the Master LTIM bit has no meaning and the Master PIC channel modes can be programmed individually via the MPICMODE register see page 12 6 Address Interval 0 Interrupt vectors are sep
137. Timer 1 Continuous Mode This bit is used to configure GP Timer 1 for continuous or noncontinuous mode 0 Noncontinuous mode the GPTMRICNT register see page 14 12 is cleared and the timer halts whenever the count reaches the maximum count value The ENB bit is also cleared by hardware after every counter sequence 1 Continuous mode The timer count is reset to O after it reaches the maximum count value A or B and the timer immediately begins counting again If the CONT CMP bit is cleared and the ALT CMP bit is set GP Timer 1 counts to the GPTMR1MAXCMPA register value see page 14 13 and then resets the count value After the timer count has been reset the timer continues operation by counting to the GPTMR1MAXCMPB register value page 14 14 When the timer count reaches the GPTMR1MAXCMPB register value the timer clears its count value clears the ENB bit and then halts lan SC520 Microcontroller Register Set Manual 14 11 AMDA General Purpose Timer Registers GP Timer 1 Count GPTMR1CNT Memory Mapped MMCR Offset C7Ch 15 14 13 12 11 10 9 8 Bit CNT 15 8 Reset 0 0 0 0 0 0 0 0 R W R W 7 6 5 4 3 2 1 0 Bit CNT 7 0 Reset 0 0 0 0 0 0 0 0 R W R W Register Description This register contain the current count of GP Timer 1 Bit Definitions Bit Name Function 15 0 CNT 15 0 GP Timer 1 Count Register This bit field contains the current count of
138. W RSV RW RW R W R W Register Description This register provides the status of channels 3 5 6 and 7 when buffer chaining is enabled Bit Definitions 2 1 11 22 Name Reserved CH7 _ STA CH6 _ STA CH5_EOB_ STA Function Reserved This bit field should be written to 0 for normal system operation End of Current Buffer in Channel 7 This bit is set by the GP bus DMA controller when the current buffer transfer is completed 0 The event has not occurred or software cleared this bit by writing a 1 12 The current buffer transfer is completed In addition an interrupt is generated if bit CH7 INT ENB is 1 in the GPDMABSINTENB register see page 11 24 Software should write a 1 to this bit CH7 EOB STA to acknowledge the transfer completion and clear the interrupt condition This acknowledgment is usually done in the interrupt handling routine if the interrupt is enabled Writing 0 to this bit has no effect If this bit is 0 writing a 1 to it has no effect This bit s value when read is meaningful only if buffer chaining is enabled End of Current Buffer in Channel 6 This bit is set by the GP bus DMA controller when the current buffer transfer is completed 0 The event has not occurred or software cleared this bit by writing a 1 12 The current buffer transfer is completed In addition an interrupt is generated if bit CH6 INT ENB is 1 in the GPDMABSINTENB register see
139. address bits A15 A0 of the next memory address for Channel 7 in buffer chaining mode Bit Definitions Bit Name Function 15 0 DMA7_NXT_ DMA Channel 7 Next Address Low ADR 15 0 This bit field provides address bits A15 A0 of the next memory buffer to be used by Channel 7 in the buffer chaining mode Programming Notes The value of this register is ignored if buffer chaining mode is not enabled for this channel in the GPDMABCCTL register see page 11 21 Bit 0 of this register GPDMANXTADDL 7 is ignored for 16 bit mode transfers so the buffer address used is always even in 16 bit mode Software should ensure that 16 bit mode buffers always begin on an even word boundary 11 32 Elan SC520 Microcontroller Register Set Manual GP DMA Controller Registers AMDA GP DMA Channel 7 Next Address High GPDMANXTADDH7 Memory Mapped MMCR Offset DAEh 15 14 13 12 11 10 9 8 Bit Reserved DMA7_NXT_ADR 27 24 Reset 0 0 0 0 0 0 0 0 R W RSV R W 7 6 5 4 3 2 1 0 Bit DMA7 NXT ADR 23 16 Reset 0 0 0 0 0 0 0 0 R W R W Register Description This register provides address bits A27 A16 of the next memory address for Channel 7 in buffer chaining mode Bit Definitions Bit Name Function 15 12 Reserved Reserved This bit field should be written to 0 for normal system operation 11 0 DMA7 NXT DMA Channel 7 Next Address High ADR 27 16 This bit field provides address bit
140. allow counts of up to 16 M 16 777 216 transfers In PCI bus 2 2 compliant designs software must limit the length of GP bus DMA demand or block mode transfers Very large transfers could cause the PCI Host Bridge target controller to violate the 10 us memory write maximum completion time limit set in the PC Local Bus Specification Revision 2 2 lan SC520 Microcontroller Register Set Manual 11 85 AMD Master DMA Channel 4 7 Status MSTDMASTA GP DMA Controller Registers Direct Mapped Address 00DOh 7 6 5 4 3 2 1 0 Bit DMAR7 DMAR6 DMAR5 DMAR4 TC7 TC6 TC5 TC4 Reset 0 0 0 0 R W R R R R R R R R Register Description This register indicates the request status and terminal count status for Channels 4 7 Bit Definitions Bit Name DMAR7 DMAR6 DMAR5 DMAR4 TC7 TC6 TC5 TC4 Programming Notes Bits 3 0 of this register are reset when read Any read from this register MSTDMASTA clears bits 3 0 11 86 Function Channel 7 DMA Request 0 Channel 7 DMA request not pending 1 Channel 7 DMA request pending Channel 6 DMA Request 0 Channel 6 DMA request not pending 1 Channel 6 DMA request pending Channel 5 DMA Request 0 Channel 5 DMA request not pending 1 Channel 5 DMA request pending Channel 4 DMA Request 0 Channel 4 DMA request not pending 1 Channel 4 DMA request pending Channel 7 Terminal Count 0 Channel 7 ter
141. allows the current count of the selected channel to be read Bit Definitions Bit Name Function 7 6 CTR_SEL 1 0 PIT Counter Select When this address Port 0043h is written with bits 7 6 4 11b and bits 5 4 00b the PITCNTLAT register is addressed and this CTR_SEL bit field specifies which of the three counter elements to latch for read back from the associated count register 00 Select PIT counter 0 01 Select PIT counter 1 10 Select PIT counter 2 11 The PITRDBACK register is addressed see page 13 11 When this address Port 0043h is written with bits 7 6 11b this address is redefined for the duration of the current I O write as the PITRDBACK register see page 13 11 When this address Port 0043h is written with bits 7 6 11b and bits 5 4 00b this address is redefined for the duration of the current I O write as the PITMODECTL register see page 13 7 5 4 CTR_CMD 1 0 Counter Latch Command When this address Port 0043h is written with bits 7 6 11b and bits 5 4 00b the PITCNTLAT register is addressed and this CTR_CMD bit field invokes the counter latch command 00 The Counter Latch command is invoked 01 11 The PITMODECTL or PITRDBACK register is addressed see page 13 7 and page 13 11 Latched counts are read back from the PITxONT registers see the descriptions starting on page 13 2 based on the current read write mode selected for each counter via the CTR RW LATCH bit field
142. always the last value written but the bit is not applied to the system address unless 8 bit operation is selected Programming Notes In enhanced mode this channel can be programmed for 16 bit DMA transfers see the descriptions for GRPDMACTL register bits CH8 ALT SIZE and ENH MODE ENB on page 11 4 In the enhanced mode this register is updated during DMA cycles if the DMA addresses cross the 64 Kbyte boundary for 8 bit transfers or cross the 128 Kbyte boundary for 16 bit transfers 11 64 Elan SC520 Microcontroller Register Set Manual GP DMA Controller Registers AMDA Slave DMA Channel 1 Page GPDMA1PG Direct Mapped Address 0083h 7 6 5 4 3 2 1 0 Bit DMA1MAR 23 16 Reset 0 0 0 0 0 0 0 0 R W R W Register Description This register provides bits 23 16 of the memory address for Channel 1 Bit Definitions Bit 7 0 DMA1MAR 23 16 Programming Notes Function DMA Channel 1 Memory Address Bits 23 16 This bit field is used with the values in the GPDMA1MAR register see page 11 44 and the GPDMAEXTPG 1 register see page 11 11 to generate DMA address bits 27 0 lan SC520 Microcontroller Register Set Manual 11 65 AMD GP DMA Controller Registers General 1 GPDMAGR1 Direct Mapped I O Address 0084h 7 6 5 4 3 2 1 0 Bit PORT84 7 0 Reset 0 0 0 0 0 0 0 0 R W R W Register Description This is a general purp
143. bit is set the overriding global interrupt mode for the Master PIC channels is determined by the LTIM bit in the MPICICW1 register see page 12 26 If the M GINT MODE bit is cleared the LTIM bit has no meaning and the MPICMODE register bits take effect for determining each Master PIC channel s interrupt mode Elan SC520 Microcontroller Register Set Manual 12 7 AMD Slave 1 PIC Interrupt Mode SL1PICMODE Programmable Interrupt Controller Registers Memory Mapped MMCR Offset DO3h 7 6 5 4 3 2 1 0 Bit CH7 INT CH6 INT CH5 INT CH4_INT_ CH3_INT_ CH2 INT CH1 INT CHO INT i MODE MODE MODE MODE MODE MODE MODE MODE Reset 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Register Description This register controls the individual Slave 1 PIC channel interrupt mode Bit Definitions Bit Name Function 7 CH7_INT_ Slave 1 PIC Channel 7 Interrupt Mode MODE 0 Edge sensitive interrupt request detection 1 Level sensitive interrupt request detection 6 CH6_INT_ Slave 1 PIC Channel 6 Interrupt Mode MODE 0 Edge sensitive interrupt request detection 1 Level sensitive interrupt request detection 5 CH5_INT_ Slave 1 PIC Channel 5 Interrupt Mode MODE 0 Edge sensitive interrupt request detection 1 Level sensitive interrupt request detection 4 CH4_INT_ Slave 1 PIC Channel 4 Interrupt Mode MODE 0 Edge sensitive interrupt request detection 1 Level sensitive interrupt request detection
144. buffer chaining mode Programming Notes The value of this register is ignored if buffer chaining mode is not enabled for this channel in the GPDMABCCTL register see page 11 21 In PCI bus 2 2 compliant designs software must limit the length of GP bus DMA demand or block mode transfers Very large transfers could cause the PCI Host Bridge target controller to violate the 10 us memory write maximum completion time limit set in the PCI Local Bus Specification Revision 2 2 lan SC520 Microcontroller Register Set Manual 11 37 AMDA GP DMA Controller Registers GP DMA Channel 6 Next Transfer Count Low GPDMANXTTCL6 Memory Mapped MMCR Offset DB8h 15 14 13 12 11 10 9 8 Bit NXT TC 15 8 Reset 0 0 0 0 0 0 0 0 R W R W 7 6 5 4 3 2 1 0 Bit DMA6_NXT_TC 7 0 Reset 0 0 0 0 0 0 0 0 R W R W Register Description This register provides bits 15 0 of the next transfer count for Channel 6 in buffer chaining mode Bit Definitions Bit Name Function 15 0 DMA6 NXT DMA Channel 6 Next Transfer Count Low TC 15 0 This bit field provides bits 15 0 of the next transfer count to be used by Channel 6 in the buffer chaining mode Programming Notes The value of this register is ignored if buffer chaining mode is not enabled for this channel in the GPDMABCCTL register see page 11 21 In PCI bus 2 2 compliant designs software must limit the length of G
145. buffers always begin on an even word boundary 11 26 Elan SC520 Microcontroller Register Set Manual GP DMA Controller Registers AMDA GP DMA Channel 3 Next Address High GPDMANXTADDH3 Memory Mapped MMCR Offset DA2h 15 14 13 12 11 10 9 8 Bit Reserved DMA3_NXT_ADR 27 24 Reset 0 0 0 0 0 0 0 0 R W RSV R W 7 6 5 4 3 2 1 0 Bit DMAS3 NXT ADR 23 16 Reset 0 0 0 0 0 0 0 0 R W R W Register Description This register provides address bits A27 A16 of the next memory address for Channel 3 in buffer chaining mode Bit Definitions Bit Name Function 15 12 Reserved Reserved This bit field should be written to 0 for normal system operation 11 0 DMA3_NXT_ DMA Channel 3 Next Address High ADR 27 16 This bit field provides address bits A27 A16 of the next memory buffer to be used by Channel 3 in the buffer chaining mode Programming Notes The value of this register is ignored if buffer chaining mode is not enabled for this channel in the GPDMABCCTL register see page 11 21 Elan SC520 Microcontroller Register Set Manual 11 27 AMDA GP DMA Controller Registers GP DMA Channel 5 Next Address Low GPDMANXTADDL5 Memory Mapped MMCR Offset DA4h 15 14 13 12 11 10 9 8 Bit DMAS5 NXT ADR 15 8 Reset 0 0 0 0 0 0 0 0 R W R W 7 6 5 4 3 2 1 0 Bit DMA5_NXT_ADR 7 0 Reset 0 0 0 0 0 0 0 0 R W R W
146. by issuing a counter latch or read back command viathe PITCNTLAT or PITRDBACK register see page 13 10 or page 13 11 A counter latch or read back command does not stop a counter from running but rather takes a snapshot of the current value Once the count has been latched further latch commands are ignored until all latched count data is read back from the associated count register A read back command is a higher priority command than the counter latch command The counter latch command is a subset of the read back command because only one channel can have its counter latched per counter latch command The programmable interval timer does not provide any way to read back the original count programmed into any of the three count registers 13 12 Elan SC520 Microcontroller Register Set Manual Programmable Interval Timer Registers System Control Port B SYSCTLB Direct AMD Mapped Address 0061h 7 6 5 4 1 0 z PITOUT2_ PIT _OUT2_ Bit PERR IOCHCK STA RFD Reserved ENB PIT_GATE2 Reset 0 0 1 x 0 0 0 R W R R R R RSV R W R W Register Description This register contains the PC AT compatible System Control Port B register bits that pertain to the programmable interval timer PIT Bit Definitions Function PC AT Parity Error Indicator This PC AT compatible bit is not supported always reads back 0 PC AT Channel Check Indicator This PC AT compatible bit is not supported always
147. can count to before resetting its count register to 0 Programming Notes GP Timer 2 has only one maxcount compare register If this register GPTMR2MAXCMPA is written with the value 0000h and the timer is enabled the timer counts to FFFFh at which point the appropriate action occurs based on the timer configuration options that are set For details see the GPTMR2CTL register bits INT_ENB MAX_CNT and CONT starting on page 14 16 If the maxcount compare register contains a value other than 0000h and the timer is enabled the timer counts to the programmed maxcount value 14 18 Elan SC520 Microcontroller Register Set Manual CHAPTER ee Ta AMD 1 1 5 SOFTWARE TIMER REGISTERS 15 1 15 2 Table 15 1 OVERVIEW This chapter describes the software timer registers of the ElanSC520 microcontroller The software timer is one of four lanSC520 microcontroller timer modules The other timer modules are described in the following chapters Chapter 14 General Purpose Timer Registers E Chapter 13 Programmable Interval Timer Registers E Chapter 16 Watchdog Timer Registers The software timer register set consists of three memory mapped configuration region MMCR registers used access and control the timer See the Elan SC520 Microcontroller User s Manual order 22004 for details about the software timer Table 15 1 lists the software timer registers in offset order with the corresponding description s
148. configuration space header registers plus a Host Bridge specific Master Retry Time Out PCIMRETRYTO register defined in the PCI configuration space Note that additional microcontroller specific PCI Host Bridge configuration registers are provided the MMCR space see Table 1 1 PCI indexed registers are accessed via two 32 bit direct mapped I O locations Port OCF8h and Port OCFCh The PCI configuration mechanism can be used to access either the Host Bridge specific PCI indexed registers or the device specific PCI indexed registers for any 1 10 Elan SC520 Microcontroller Register Set Manual Configuration Register Overview AMD other device that is connected to the PCI bus Refer to the PC Local Bus Specification Revision 2 2 for details on PCI configuration Table 1 3 lists all of the PCI indexed registers in the lanSC520 microcontroller Table 1 3 PCI Indexed Registers Register Name Mnemonic I O Address PCI Index Page Number Device Vendor ID PCIDEVID OCF8h 0CFCh 00h page 6 18 Status Command PCISTACMD OCF8h 0CFCh 04h page 6 19 Class Code Revision ID PCICCREVID OCF8h OCFCh 08h page 6 22 Header Type PCIHEADTYPE OCF8h 0CFCh OEh page 6 23 Master Retry Time Out PCIMRETRYTO OCF8h O0CFCh 41h page 6 24 1 4 RTC AND CMOS RAM INDEXED REGISTERS Real time clock and CMOS RAM indexed registers are accessed using I O ports 0070h index and 0071h data These registers provide PC AT compatible setup c
149. controller write transaction or during the address phase of a master controller read transaction 0 Master controller has not detected the parity error signal asserted 1 Master controller has detected the parity error signal asserted This bit is cleared by writing a 1 This bit operates regardless of the corresponding interrupt enable bit M_RPER_IRQ_ENB the HBMSTIRQCTL register see page 6 10 Master Detected Parity Error Interrupt Status This bit is set when the master controller detects a parity error during a master controller read transaction 0 Master controller has not detected a parity error 1 Master controller has detected a parity error This bit is cleared by writing a 1 This bit operates regardless of the corresponding interrupt enable bit M_DPER_IRQ_ENB in the HBMSTIRQCTL register see page 6 10 This register is reset by a system reset The bits in this register are not affected by a PCI bus reset A PCI bus reset is initiated by setting the PCI_RST bit in the HBCTL register see page 6 3 Elan SC520 Microcontroller Register Set Manual 6 13 AMD PCI Bus Host Bridge Registers Host Bridge Master Interrupt Address MSTINTADD Memory Mapped MMCR Offset 6Ch 81 30 29 28 27 26 25 24 Bit M_AD_IRQ_ID 31 24 Reset 0 0 0 0 0 0 0 0 R W R 23 22 21 20 19 18 17 16 Bit M AD I
150. could cause the PCI Host Bridge target controller to violate the 10 us memory write maximum completion time limit set in the PC Local Bus Specification Revision 2 2 11 20 Elan SC520 Microcontroller Register Set Manual Buffer Chaining Control GPDMABCCTL Register Description AMD GP DMA Controller Registers Memory Mapped MMCR Offset D98h 6 5 4 3 2 1 0 B CH7_ CH6_ CH5_ CH3_ eee BCHN_ENB BCHN_ENB BCHN_ENB BCHN_ENB Reset 0 0 0 0 0 0 0 0 R W RSV R W R W R W R W This register controls the buffer chaining feature in enhanced mode Bit Definitions Programming Notes Name Reserved CH7_BCHN_ ENB CH6_BCHN_ ENB CH5_BCHN_ ENB CH3_BCHN_ ENB Function Reserved This bit field should be written to 0 for normal system operation Buffer Chaining Enable for Channel 7 This bit enables buffer chaining via the Channel 7 Next Address and Channel 7 Next Transfer Count registers See the register descriptions beginning on page 11 32 and page 11 40 When this bit is set the CH7 VAL bit in the in the GRPDMABCVAL register becomes effective see page 11 25 0 Disable buffer chaining 1 Enable buffer chaining enhanced mode only Buffer Chaining Enable for Channel 6 This bit enables buffer chaining via the Channel 6 Next Address and Channel 6 Next Transfer Count registers See the register descriptions beginning on page 11 30 and page 11 38 When this bit
151. devices to an idle state and also clears the SDRAM controller s page table entries 7 6 Elan SC520 Microcontroller Register Set Manual SDRAM Controller Registers AMDA SDRAM Bank 0 3 Ending Address DRCBENDADR Memory Mapped Bit Reset R W Bit Reset R W Bit Reset R W Bit Reset R W MMCR Offset 18h 31 30 29 28 27 26 25 24 BNK3_ENB BNK3_END 28 22 0 0 0 0 0 0 0 0 R W R W 23 22 21 20 19 18 17 16 BNK2_ENB BNK2 END 28 22 0 0 0 0 0 0 0 0 R W R W 15 14 13 12 11 10 9 8 BNK1_ENB BNK1 END 28 22 0 0 0 0 0 0 0 0 R W R W 7 6 5 4 3 2 1 0 BNKO BNKO END 28 22 0 0 0 0 0 0 0 0 R W R W Register Description This register controls the SDRAM bank enable and bank ending address that specifies the boundary between the banks Note A programmable reset preserves this register s state See the PRG_RST_ENB bit description on page 3 3 Bit Definitions Bit Name 31 BNK3_ENB 30 24 28 22 23 BNK2 Function Bank 3 Enable This bit enables Bank 3 0 Disabled 1 Enabled Bank 3 Ending Address This bit field determines the Bank 3 boundary defined in 4 Mbyte increments This value is compared to physical address bits 28 22 during an SDRAM request to select a bank Bank 3 is selected if physical address bits 28 22 are less than the BNK3_ EN
152. field contains valid information only while the WPV STA bit is set The master s identity is latched when a write protect violation occurs Subsequent write protect violations are not captured until software clears the interrupt by writing a 1 to the WPV STA bit Reserved This bit field should be written to 0 for normal system operation Write Protect Violation Window Number This bit field identifies the programmable address region window PARO PAR15 in which the write protect violation occurred This bit field contains valid information only while the WPV STA bit is set The PARx window number is latched when a write protect violation occurs Subsequent write protect violations are not captured until software clears the interrupt by writing a 1 to the WPV STA bit Elan SC520 Microcontroller Register Set Manual System Address Mapping Registers Programmable Address Region O PARO Programmable Address Region 1 PAR1 Programmable Address Region 2 PAR2 Programmable Address Region 3 PAR3 Programmable Address Region 4 PAR4 Programmable Address Region 5 PAR5 Programmable Address Region 6 PAR6 Programmable Address Region 7 PAR7 Programmable Address Region 8 PARS Programmable Address Region 9 PAR9 Programmable Address Region 10 PAR10 Programmable Address Region 11 PAR11 Programmable Address Region 12 PAR1 2 Programmable Address Region 13 PAR13 Programmable Address Region 14 PAR14 Programmable Address Region 15
153. floating point unit FPU error interrupt request for DOS compatible error handling Bit Definitions Bit Name 7 0 FPUERR_RST Programming Notes Function Clear FPU Error Interrupt Request Any write to this register address clears the interrupt request that is generated by an Am5 86 CPU floating point unit error The CPU asserts the ferr signal internally At the conclusion of the write to this register the CPU s ignne signal is asserted internally to allow non control instructions to be executed This function is provided for systems that require DOS compatible FPU error handling Elan SC520 Microcontroller Register Set Manual 12 61 AMD Programmable Interrupt Coniroller Registers 12 62 Elan SC520 Microcontroller Register Set Manual 1 13 1 13 2 Table 13 1 ENS 3 AMD AMD PROGRAMMABLE INTERVAL TIMER REGISTERS OVERVIEW This chapter describes the programmable interval timer PIT registers of the lanSC520 microcontroller There are three PIT channels The PIT module is one of four lanSC520 microcontroller timer modules The other timer modules are described in the following chapters Chapter 15 Software Timer Registers E Chapter 14 General Purpose Timer Registers E Chapter 16 Watchdog Timer Registers The PIT register set consists of 10 direct mapped I O registers used to configure control and read status for the three PIT channels It also includes the Sys
154. from the RTC index specified in the RTCIDX register see page 17 2 Elan SC520 Microcontroller Register Set Manual 17 3 Real Time Clock Registers RTC Current Second RTCCURSEC Address 70h 71h RTC Index 00h 7 6 5 4 3 2 1 0 Bit SECOND 7 0 Reset X X X X X X X X RW RW Register Description This register is the RTC current second initialization and read back register Bit Definitions Bit Name Function 7 0 SECOND 7 0 RTC Current Second Software initializes the seconds value for the RTC by writing data to this bit field in binary or binary coded decimal BCD format The seconds component of the RTC time can be read from this bit field The RTC logic updates this bit field once per second Valid values for this bit field range from 0 to 59d If a value greater than 59d is programmed the bit field value increments up to FFh wraps around to 0 and only then does the value remain in the valid range Programming Notes Software can suspend updating of this register via the SET bit in the RTCCTLB register see page 17 16 Software selects binary or BCD format via the DATE_MODE bit in the RTCCTLB register 17 4 Elan SC520 Microcontroller Register Set Manual Real Time Clock Registers AMDA RTC Alarm Second RTCALMSEC Address 70h 71h RTC Index Oth 7 6 5 4 3 2 1 0 Bit SECOND 7 0 Reset X X X X X X X X R W R W
155. information at reset configure reset behavior and provide reset status Three direct mapped I O registers are used to provide PC AT compatible reset related functions See the Elan SC520 Microcontroller User s Manual order 22004 for details about reset generation Table 3 1 and Table 3 2 list each type of reset register in offset order with the corresponding description s page number REGISTERS Reset Generation MMCR Registers Register Name Mnemonic MMCR Offset Page Number System Board Information SYSINFO Reset Configuration RESCFG Reset Status RESSTA Reset Generation Direct Mapped Registers Register Name Mnemonic I O Address Page Number SCP Data Port SCPDATA SCP Command Port SCPCMD System Control Port A SYSCTLA Elan SC520 Microcontroller Register Set Manual 3 1 AMD Reset Generation Registers System Board Information SYSINFO Memory Mapped MMCR Offset D70h 7 6 5 4 3 2 1 0 Bit RST LD 7 0 Reset R W R Register Description This read only register contains the state that was latched on the RSTLD7 RSTLDO pins at the assertion of PWRGOOD Bit Definitions Bit Name Function 7 0 RST_LD 7 0 Reset Latched Input Data The microcontroller initializes this bit field at the assertion of the PWRGOOD signal by latching the state of the shared RSTLD7 RSTLDO pins The information in this bit field remains static after it is lat
156. is no logic to avoid spurious pulses while enabling this pin as an output or changing clock frequencies The target device should be held in reset while the CLK_TST_SEL CLK_PIN_DIR and CLK_PIN_ENB bit fields are configured to enable the pin as an output with the desired frequency then the target device can be released from reset The CLKTIMER CLKTEST pin can be enabled as an input CLKTIMER if an external oscillator is to be used for the programmable interval timer PIT For example a 1 19318 MHz CLKTIMER input can be used to provide PC AT compatible time of day operation without changing PIT counter values See the PIT chapter of the Elan SC520 Microcontroller User s Manual order 22004 for details While the pin is being enabled as an input itis synchronized to the CPU clock to prevent spurious pulses from occurring in the PIT Function Reserved This bit field should be written to 0 for normal system operation CLKTEST Pin Output Clock Select 000 32 768 kHz RTC clock 001 1 8432 MHz UART clock 010 18 432 MHz UART clock 011 1 1892 MHz PIT clock 100 1 47456 MHz PLL1 output 101 36 864 MHz PLL2 output 110 111 Disabled pin stays Low Reserved This bit field should be written to 0 for normal system operation CLKTIMER CLKTEST Pin Direction This bit determines whether the CLKTIMER CLKTEST pin is an input CLKTIMER or output CLKTEST As an input this pin provides the clock for the programmable
157. is set the CH6_CBUF_VAL bit in the in the GRPDMABCVAL register becomes effective see page 11 25 0 Disable buffer chaining 1 Enable buffer chaining enhanced mode only Buffer Chaining Enable for Channel 5 This bit enables buffer chaining via the Channel 5 Next Address and Channel 5 Next Transfer Count registers See the register descriptions beginning on page 11 28 and page 11 36 When this bit is set the CH5 VAL bit in the in the GRPDMABCVAL register becomes effective see page 11 25 0 Disable buffer chaining 1 Enable buffer chaining enhanced mode only Buffer Chaining Enable for Channel 3 This bit enables buffer chaining via the Channel 3 Next Address and Channel 3 Next Transfer Count registers See the register descriptions beginning on page 11 26 and page 11 34 When this bit is set the CH3 VAL bit in the in the GRPDMABCVAL register becomes effective see page 11 25 0 Disable buffer chaining 1 Enable buffer chaining enhanced mode only This register is ignored unless enhanced mode is enabled Enhanced mode is enabled by setting the ENH MODE ENB bit in the GPDMACTL register see page 11 4 lan SC520 Microcontroller Register Set Manual 11 21 AMD Buffer Chaining Status GPDMABCSTA GP DMA Controller Registers Memory Mapped MMCR Offset D99h 7 6 3 2 1 0 B B CH7 EOB CH6 EOB CH5 EOB CH3 EOB STA STA STA STA Reset 0 0 0 0 0 0 R
158. mode Slave 11 Buffered mode Master In the lanSC520 microcontroller these bits are internally fixed to 00b 1 Automatic EOI Mode 0 Normal EOI the interrupt handler must send an End of Interrupt command to the PIC s 1 Auto EOI the EOI is automatically performed after the second interrupt acknowledge signal from the CPU In the ElanSC520 microcontroller this bit is internally fixed to 0 The Slave 1 PIC and Slave 2 PIC do not support automatic EOI mode 0 PM Microprocessor Mode 0 2 8080 8085 mode 1 2 8086 mode In the lanSC520 microcontroller design this bit is internally fixed to 1 Programming Notes The PIC s initialization control word S2PICICWX registers 1 4 must be programmed in sequence Writing to Port 0024h with bit 4 1 causes the S2PICICW1 register to be written and also resets the PIC s internal state machine and the internal S2PICICWx register pointer Then S2PICICWx registers 2 4 can be programmed by sequential writes to Port 0025h Each time Port 0025h is written to following the write to S2PICICW1 the internal register pointer points to the next S2PICICWx register S2PICICW1 and S2PICICW2 must always be programmed Also the S2PICICWS register must always be programmed in this design because the SNGL bit in S2PICICW1 is internally fixed to 0 The S2PICICWA register is skipped if the IC4 bit in S2PICICW1 is 0 Software is expected to initialize this register S2PICICWA if the IC4 bit is set in the
159. not affected by a PCI bus reset A PCI bus reset is initiated by setting the PCI bit in the HBCTL register see page 6 3 This register must be accessed as a doubleword Accesses that are less than a doubleword in width are treated as normal PCI bus or if so mapped GP bus I O accesses No configuration cycles are generated if the access is not to the entire doubleword In the lanSC520 microcontroller the doubleword starting at OCF8h must not be mapped to the GP bus The ElanSC520 microcontroller does not generate special cycles In other words setting the BUS NUM bit field to 00h the DEVICE NUM bit field to 11111b the FUNCTION NUM bit field to 111b and the REGISTER NUM field to 00000b does not generate a special cycle Instead this setup generates a PCI bus configuration write cycle 6 16 Elan SC520 Microcontroller Register Set Manual PCI Bus Host Bridge Registers AMDA PCI Configuration Data PCICFGDATA Direct Mapped I O Address OCFCh 31 30 29 28 27 26 25 24 Bit CFG_DATA 31 24 Reset X X X X X X X X R W R W 23 22 21 20 19 18 17 16 Bit CFG_DATA 23 16 Reset X X X X X X X X R W R W 15 14 13 12 11 10 9 8 Bit CFG_DATA 15 8 Reset X X X X X X X X R W R W 7 6 5 4 3 2 1 0 Bit CFG_DATA 7 0 Reset X X X X X X X X R W R W Register Description Software reads or writes this registe
160. only then does the value remain within the valid range Programming Notes Software can suspend updating of the RTC via the SET bit in the RTCCTLB register see page 17 16 Software selects binary or BCD format via the DATE MODE bit in the RTCCTLB register 17 12 Elan SC520 Microcontroller Register Set Manual Real Time Clock Registers AMDA RTC Current Year RTCCURYR Address 70h 71h RTC Index 09h 7 6 5 4 3 2 1 0 Bit YEAR 7 0 Reset X X X X X X X X R W R W Register Description This register used to initialize and read back the RTC current year Bit Definitions Bit Name Function 7 0 YEAR 7 0 RTC Current Year Software initializes current year value for the RTC by writing data to this bit field in either binary or binary coded decimal BCD formats The RTC logic updates this bit field once per second Valid values for this bit field range from 0 to 99d If a value greater than 99d is programmed the bit field value increments up to FFh wraps around to 0 and only then does the value remain within the valid range Programming Notes Software can suspend updating of the RTC via the SET bit in the RTCCTLB register see page 17 16 Software selects binary or BCD format via the DATE MODE bit in the RTCCTLB register Refer to the RTC chapter in the Elan SC520 Microcontroller User s Manual order 22004 for guidelines on storing current century information to address year 2000 issue
161. out exponent as shown in the Exponent column The selected exponent determines the time out duration according to the following equation Time out duration 29 Ponent CPU Frequency where Time out duration is the time out period in seconds exponent is the value selected from Table 16 2 CPU Frequency is the operating speed of the CPU in Hz When multiple bits are set in the EXP SEL field the least significant bit set is used to select the exponent Table 16 2 Watchdog Timer Exponent Selections Time Out Time Out Interval Interval Exponent 33 000 MHz 33 333 MHz N Infinity Infinity 496 us 492 us 508 ms 503 ms 1 025 1 015 2 03 s 2 015 4 07 s 4 03 s 8 13 s 8 05 s 16 275 16 11 s 32 54 s 32 21 s XX X XXX KL Oo oOjolojo 2 xij xix ojo For example to program maximum time out of about 32 seconds the EXP_SEL field is set to 80h The time out value can then be calculated as follows for the ElanSC520 microcontroller with a 33 000 MHz CPU clock Time out interval 2 33 000 MHz crystal frequency 29 33 000 000 32 54 seconds Programming Notes The watchdog timer can only be programmed after special keyed sequences are written to this address Two special keyed sequences are recognized m The key sequence of 3333h followed by CCCCh is called the write key and is used to open this Watchdog Timer Control WDT
162. page 11 24 Software should write a 1 to this bit CH6 EOB STA to acknowledge the transfer completion and clear the interrupt condition This acknowledgment is usually done in the interrupt handling routine if the interrupt is enabled Writing O to this bit has no effect If this bit is 0 writing a 1 to it has no effect This bit s value when read is meaningful only if buffer chaining is enabled End of Current Buffer in Channel 5 This bit is set by the GP bus DMA controller when the current buffer transfer is completed 0 The event has not occurred or software cleared this bit by writing a 1 12 The current buffer transfer is completed In addition an interrupt is generated if bit CH5 INT ENB is 1 in the GPDMABSINTENB register see page 11 24 Software should write a 1 to this bit 5 EOB STA to acknowledge the transfer completion and clear the interrupt condition This acknowledgment is usually done in the interrupt handling routine if the interrupt is enabled Writing 0 to this bit has no effect If this bit is 0 writing a 1 to it has no effect This bit s value when read is meaningful only if buffer chaining is enabled Elan SC520 Microcontroller Register Set Manual GP DMA Controller Registers AMDA Bit Name Function 0 CH3 EOB End of Current Buffer in Channel 3 STA This bit is set by the GP bus DMA controller when the current buffer transfer is completed 0 The event has not occurred or software cleared this
163. page 11 85 Master DMA Channel 4 7 Status MSTDMASTA 00DOh page 11 86 Master DMA Channel 4 7 Control MSTDMACTL 00DOh page 11 87 Master Software DRQ n Request MSTDMASWREQ 00D2h page 11 89 Master DMA Channel 4 7 Mask MSTDMAMSK 00D4h page 11 90 Master DMA Channel 4 7 Mode MSTDMAMODE 00D6h page 11 91 Master DMA Clear Byte Pointer MSTDMACBP 00D8h page 11 93 Master DMA Controller Reset MSTDMARST OODAh page 11 94 Master DMA Controller Temporary MSTDMATMP 00DAh page 11 95 Master DMA Mask Reset MSTDMAMSKRST 00DCh page 11 96 Master DMA General Mask MSTDMAGENMSK OODEh Elan SC520 Microcontroller Register Set Manual page 11 97 1 9 AMD Table 1 2 Register Name Floating Point Error Interrupt Clear UART 2 Configuration Register Overview Direct Mapped I O Registers Continued Mnemonic FPUERRCLR l O Address FOh 02F8 02FFh Page Number page 12 61 UART 2 Transmit Holding UART2THR 02F8h page 18 7 UART 2 Receive Buffer UART2RBR 02F8h page 18 8 UART 2 Baud Clock Divisor Latch LSB UART2BCDL 02F8h page 18 9 UART 2 Baud Clock Divisor Latch MSB UART2BCDH 02F9h page 18 10 UART 2 Interrupt Enable UART2INTENB 02F9h page 18 11 UART 2 Interrupt ID UARTZ2INTID 02FAh page 18 12 UART 2 FIFO Control UART2FCR
164. page number REGISTERS Software Timer MMCR Registers Register Name Mnemonic MMCR Offset Page Number Software Timer Millisecond Count SWTMRMILLI page 15 2 Software Timer Microsecond Count SWTMRMICRO page 15 3 Software Timer Configuration SWTMRCFG page 15 4 Elan SC520 Microcontroller Register Set Manual 15 1 AMD Software Timer Millisecond Count SWTMRMILLI Memory Mapped Software Timer Registers MMCR Offset C60h 15 14 13 12 11 10 9 8 Bit MS CNT 15 8 Reset 0 0 0 0 0 0 0 0 R W R 7 6 4 3 2 1 0 Bit MS_CNT 7 0 Reset 0 0 0 0 0 0 0 0 R W Register Description This register contains the current Bit Definitions Bit 15 0 Name MS ONT 15 0 Programming Notes A 32 bit read of the SWTMRMILLI register address is broken up into two 16 bit reads The first 16 bit read returns the SWTMRMILLI register and latches the SWTMRMICRO register see page 15 3 The second 16 bit read returns the newly latched SWTMRMICRO register contents Thus the 32 bit value returned includes the correct millisecond and microsecond values at the time of software s 32 bit read with the millisecond value stored in the lower 16 bits and the microsecond value stored in the upper 16 bits Byte 8 bit reads of the SWTMRMILLI register are not allowed 15 2 millisecond count of the software timer Function 16 bit Millisecond Count This
165. position 1 of the high priority queue 0011 PCI master connected to REQ3 and GNT3 is in position 1 of the high priority queue 0100 PCI master connected to REQ4 and GNT4 is in position 1 of the high priority queue 0101 1110 Reserved 1111 No master is in position 1 of the high priority queue Reserved This bit field should be written to 0 for normal system operation PCI Bus Arbiter High Priority 0 This bit defines which PCI master is in position 0 of the high priority queue 0000 PCI master connected to REQO and GNTO is in position 0 of the high priority queue 0001 PCI master connected to and GNT1 is in position 0 of the high priority queue 0010 PCI master connected to REQ2 and GNT2 is in position 0 of the high priority queue 0011 PCI master connected to REQ3 and GNT3 is in position 0 of the high priority queue 0100 PCI master connected to REQ4 and GNT4 is in position 0 of the high priority queue 0101 1110 Reserved 1111 No master is in position 0 of the high priority queue Elan SC520 Microcontroller Register Set Manual System Arbitration Registers 5 8 Elan SC520 Microcontroller Register Set Manual CHAPTER ee AMD 6 6 1 6 2 Table 6 1 PCI BUS HOST BRIDGE REGISTERS OVERVIEW This chapter describes the PCI bus host bridge controller registers of the ElanSC520 microcontroller The lanSC520 microcontroller includes an integrated PCI bus host bridge controller
166. read from or written to this bit field immediately after transfer count bits 7 0 are read from or written to this bit field The actual number of transfers is one more than the programmed transfer count value Programming Notes To ensure that the lower byte of this register GPDMAOTO is always accessed first software should precede any access to this register with a write to the SLDMACBP register see page 11 57 to clear the slave DMA byte pointer In PCI bus 2 2 compliant designs software must limit the length of GP bus DMA demand or block mode transfers Very large transfers could cause the PCI Host Bridge target controller to violate the 10 us memory write maximum completion time limit set in the PC Local Bus Specification Revision 2 2 lan SC520 Microcontroller Register Set Manual 11 43 GP DMA Controller Registers Slave DMA Channel 1 Memory Address GPDMA1MAR Direct Mapped I O Address 0002h 7 6 5 4 3 2 1 0 Bit DMA1MAR 15 0 Reset X X X X X X X X R W Register Description This register contains bits 15 0 of the memory address for Channel 1 during DMA operation Bit Definitions Bit Name Function 7 0 DMA1MAR Lower 16 Bits of DMA Channel 1 Memory Address 15 0 This 8 bit field is used in two successive I O accesses to read or write the channel s memory address bits 15 0 Bits 7 0 of the channel s memory address can be read from or written to this bit fi
167. read only bit field increments at a rate of 1000 counts per second This millisecond counter is set to zero at system reset Note When read this counter is automatically reset to 0 This millisecond counter is not reset when the US bit field in the SWTMRMICRO register is read see page 15 3 In order to maintain a millisecond time base this MS ONT bit field must be read at least once every 65 5 seconds When this MS ONT bit field is read the value in the internal free running microsecond up counter is automatically latched into the US bit field in the SWTMRMICRO register The internal microsecond counter increments at a rate of 1 MHz and counts from 0 to 999 It rolls over from 999 back to zero Every time the microsecond counter rolls over the MS ONT bit field is incremented Note that the XTAL FREQ bit in the SWTMRCFG register see page 15 4 must be set appropriately in order for the increment rate to be correct Elan SC520 Microcontroller Register Set Manual Software Timer Registers AMDA Software Timer Microsecond Count SWTMRMICRO Memory Mapped MMCR Offset C62h 15 14 13 12 11 10 9 8 Bit Reserved US ONT 9 8 Reset 0 0 0 0 0 0 0 0 R W RSV R 7 6 5 4 3 2 1 0 Bit US_CNT 7 0 Reset 0 0 0 0 0 0 0 0 R W R Register Description This register contains the current Bit Definitions Bit Name 15 10 Reserved 9 0 US CNT 9 0
168. reading 1 from this bit implies that a write cycle to SDRAM did not occur yet and so the BAD bit field value was not yet applied If the BAD CHK ENB bit is read as a 0 after it was previously set then a write cycle did occur in which the bit field value was applied Force Bad ECC Check Bits This register provides a way for users to specify their own ECC code for error test purposes During write cycles to SDRAM a 7 bit encoded ECC check code sometimes referred to as a syndrome code that represents the associated write data is written to ECC SDRAM This code is automatically generated by the ElanSC520 microcontroller when ECC is enabled If the BAD CHK ENB bit is set the pattern in the BAD bit field is written to the ECC storage location on the following write cycle to SDRAM Note The write buffer should be disabled and the write access should not be cacheable in the Am5 86 CPU write back cache during this procedure to ensure that the write cycle is propagated to the SDRAM when intended The write buffer is disabled via the WB ENB bit in the DBCTL register see page 8 3 The write can be made non cacheable among other ways by putting the cache in write through mode or by disabling the cache completely FRC BAD 6 0 i CHK 6 0 Programming Notes During a master write access to SDRAM the lanSC520 microcontroller generates an ECC check code sometimes referred to as a syndrome code
169. system error signal generates a maskable interrupt 1 2 Assertion of the system error signal generates an NMI Elan SC520 Microcontroller Register Set Manual 6 9 AMD Bit 9 M_RPER_ IRQ_SEL 8 M_DPER_ IRQ_SEL 7 6 Reserved 5 M_RTRTO_ IRQ_ENB 4 M_TABRT_ IRQ ENB 3 M_MABRT_ IRQ ENB 2 M SERR IRQ ENB 1 M RPER IRQ ENB 0 M_DPER_ IRQ_ENB Programming Notes PCI Bus Host Bridge Registers Function Master Received Parity Error Interrupt Select This bit allows the assertion of the parity error signal PERR during a master controller write transaction or during the address phase of a master controller read transaction to generate an NMI instead of a maskable interrupt 0 Master write transactions or master read address phase cycles that detect the parity error signal asserted generate a maskable interrupt 1 Master write transactions or master read address phase cycles that detect the parity error signal asserted generate an NMI Master Detected Parity Error Interrupt Select This bit allows parity errors detected by the master controller during a read transaction to generate an NMI instead of a maskable interrupt 0 Master read transactions that detect a parity error generate a maskable interrupt 1 Master read transactions that detect a parity error generate an NMI Reserved This bit field should be written to 0 for normal system operation Master Retry Time Out Interrupt Enable This bit
170. the LCNT bit is 0 and the CNT1 bit is 1 see page 13 11 In this case also after the one or two bytes of latched count are read subsequent reads return the unlatched count Programming Notes If a read back command is issued by writing the PITRDBACK register with the LSTAT bit clear and the CNT1 bit set see page 13 11 the subsequent read to this address Port 0041h returns the PIT1STA register status byte see page 13 5 If a read back command is issued in which PITRDBACK register bits LSTAT and LCNT are clear and bit CNT1 is set the first subsequent read from this address Port 0041h returns the status byte and the following one or two reads return latched count data as defined by the CTR RW LATCH bit field of the PITMODECTL register see page 13 7 This counter can be configured for either binary coded decimal BCD or 16 bit binary operation viathe PITMODECTL registers BCD bit see page 13 8 The counter range is 0O FFFFh in binary mode or 0 9999d in BCD However the maximum value in either mode can be achieved by clearing this register PIT1CNT to 0 All three PIT counters run at the same rate If the CLK PIN DIR bit is 0 in the CLKSEL register see page 20 9 the CLKTIMER input signal drives the PIT counters Otherwise the PIT counters run at 1 1892 MHz Elan SC520 Microcontroller Register Set Manual 13 3 AMDA Programmable Interval Timer Registers PIT Channel 2 Count PIT2CNT Direct Mapped I O Address 0042h
171. the internal out1 signal which is not used when loopback mode is disabled It is provided for PC AT compatibility and for use as part of the loopback diagnostics 0 In loopback mode the out1 signal forces RINx High deasserted 1 In loopback mode the out1 signal forces RINx Low asserted In loopback mode the internal out1 signal is internally connected to the RINx signal which can be read via the RIN bit in the UARTxMSR register see page 18 23 Other than that the OUT bit has no effect on system operation and can be used as a scratch pad during normal System operation lan SC520 Microcontroller Register Set Manual 18 19 AMD Bit Name 1 RTS 0 DTR Programming Notes 18 20 UART Serial Port Registers Function Request To Send In normal operation loopback mode disabled this bit is the complement of the RTSx signal 0 RTSx is forced High deasserting the signal 1 RTSx is forced Low asserting the signal In loopback mode the RTSx signal is internally connected to the CTSx signal which can be read via the CTS bit in the UARTxMSR register see page 18 23 Data Terminal Ready In normal operation loopback mode disabled this bit is the complement of the DTRx signal 0 2 DTRx is forced High deasserting the signal 1 2 DTRx is forced Low asserting the signal In loopback mode the DTRx signal is internally connected to the DSRx signal which can be read via the DSR bit in the UARTxMSR register
172. the master request is not a burst cycle only the rest of the current cache line is fetched from SDRAM into the read buffer When enabled the read ahead feature applies for all bursted read requests from either the Am5 86 CPU or the PCI bus The GP bus DMA controller does not perform bursted reads During SDRAM sizing or test disabling the read ahead feature might improve performance of the sizing or test algorithm Because most such algorithms test various non contiguous points in SDRAM excessive read ahead thrashing can result Although this does not result in false indications it can result in a slight performance degradation of the test algorithm After the SDRAM sizing or test process is complete the user is free to enable the read ahead feature of the read buffer when desired 3 2 WB_WM 1 0 Write Buffer Watermark This bit field specifies the write buffer s watermark setting i e the amount of allocated buffer space above which the write buffer initiates a write to SDRAM 00 28 doublewords default 01 24 doublewords 10 16 doublewords 11 8 doublewords As data is written into the write buffer a new rank of storage is allocated unless the written data can be merged or collapsed into previous ranks When a write cycle results in a rank allocation that exceeds the watermark setting the write buffer requests service from the SDRAM controller to initiate write transfers to SDRAM A higher watermark settin
173. this register GPDMA6MAR holds address bits 15 0 and address bit 16 is controlled via the GPDMAGPG register see page 11 71 11 82 Elan SC520 Microcontroller Register Set Manual GP DMA Controller Registers AMDA Master DMA Channel 6 Transfer Count GPDMA6TC Direct Mapped I O Address 7 6 5 4 3 2 1 0 Bit DMA6TC 1 5 0 Reset X X X X X X X X RW RW Register Description This register contains bits 15 0 of the transfer count for Channel 6 during DMA operation Bit Definitions Bit Name Function 7 0 DMA6TC DMA Channel 6 Transfer Count 16 Bit Register 15 0 This 8 bit field is used two successive I O accesses to read or write the channel s transfer count bits 15 0 Bits 7 0 of the channel s transfer count can be read from or written to this bit field immediately after a write to the MSTDMACBP register see page 11 93 Bits 15 8 of the channel s transfer count can be read from or written to this bit field immediately after transfer count bits 7 0 are read from or written to this bit field The actual number of transfers is one more than the programmed transfer count value Programming Notes To ensure that the lower byte of this register GPDMA6TC is always accessed first software should precede any access to this register with a write to the MSTDMACBP register see page 11 93 to clear the master DMA byte pointer By default this channel is set up for PC
174. this register S2PICINTMSK has no effect This register S2PICINTMSK cannot be accessed during a Slave 2 PIC initialization control sequence which is initiated by setting the SLCT_ICW1 bit in the S2PICICW1 register see page 12 39 When the S2PICICWx register initialization sequence is not in effect any read or write of Port 0025h accesses the S2PICINTMSK register 12 48 Elan SC520 Microcontroller Register Set Manual Programmable Interrupt Coniroller Registers Slave 1 PIC Interrupt Request S1PICIR Bit Reset R W AMD Direct Mapped Address 00AOh 7 6 5 4 3 2 1 0 IR7 IR6 IR5 IRA IR3 IR2 IR1 IRO x X x X X R R R R R R R R Register Description This register provides a real time status of the interrupt request inputs to the Slave 1 PIC This register latches all incoming interrupt requests and provides individual status of the requests to be acknowledged Bit Definitions Bit Programming Notes Name IR7 IR6 IR5 IR4 IR3 IR2 IR1 IRO Function Interrupt Request 7 0 The IR7 input to the Slave 1 PIC is not asserted 1 The IR input is asserted Interrupt Request 6 0 The IR6 input to the Slave 1 PIC is not asserted 1 The IR6 input is asserted Interrupt Request 5 0 The IR5 input to the Slave 1 PIC is not asserted 1 2 The IR5 input is asserted Interrupt Request 4 0 The IR4 input to the Slave 1 PIC is not asserte
175. timer registers in offset order with the corresponding description s page number REGISTERS General Purpose Timer MMCR Registers Register Name Mnemonic MMCR Offset Page Number GP Timers Status GPTMRSTA page 14 2 GP Timer 0 Mode Control GPTMROCTL page 14 3 GP Timer 0 Count GPTMROCNT page 14 6 GP Timer 0 Maxcount Compare A GPTMROMAXCMPA page 14 7 GP Timer 0 Maxcount Compare B GPTMROMAXCMPB page 14 8 GP Timer 1 Mode Control GPTMR1CTL page 14 9 GP Timer 1 Count GPTMR1OCNT page 14 12 GP Timer 1 Maxcount Compare A GPTMR1MAXCMPA page 14 13 GP Timer 1 Maxcount Compare B GPTMR1MAXCMPB page 14 14 GP Timer 2 Mode Control GPTMR2CTL page 14 15 GP Timer 2 Count GPTMR2CNT page 14 17 GP Timer 2 Maxcount Compare A GPTMR2MAXCMPA page 14 18 Elan SC520 Microcontroller Register Set Manual 14 1 AMD GP Timers Status GPTMRSTA General Purpose Timer Registers Memory Mapped MMCR Offset C70h 7 6 5 4 3 2 1 0 B TENN T2 INT INT TO INT Reset 0 0 0 0 0 0 0 0 R W RSV R W R W R W Register Description This register contains the interrupt status information for the general purpose timers Bit Definitions Bit 7 3 Name Reserved T2_INT_STA T1_INT_STA TO_INT_STA Programming Notes 14 2 Function Reserved This bit field should be written to 0 for normal system operation GP Timer 2 Interrupt Status 0 G
176. to 1 and remains there until another count value is written Before a counter is programmed to generate interrupts the corresponding PITxMAP register see page 12 21 must be configured to route the interrupt to the appropriate interrupt request level and priority 001b Mode 1 Hardware retriggerable one shot Available for PIT Channel 2 only When the Channel 2 counter is programmed the Channel 2 output transitions to 1 After a Low to High transition of the internal gate 2 signal controlled by the PITGATE2 signal or the PIT_GATE2 bit of the SYSCTLB register see page 13 13 the counter output transitions to 0 until the count reaches 0 then the counter output transitions to 1 until the next Low to High transition on the gate input 010b Mode 2 Rate generator Each time the count transitions to 1 the counter output transitions to 0 and remains there for one cycle of the input clock and then the counter output transitions to 1 The count is automatically reloaded and the process repeats By default PC AT compatible systems program Channel 0 for this mode 011b Mode 3 Square wave generator When the count is loaded the counter output transitions to 1 When 1 2 of the count has expired the counter output transitions to 0 When count transitions to 0 the counter output transitions to 1 and count is automatically reloaded By default PC AT compatible systems program Channels 1 and 2 to use this mode to driv
177. to an interrupt channel via the ECC_IRQ_MAP bit field in the ECCMAP register see page 12 20 ECC Enable for All Four Banks This bit enables ECC for all four banks 0 Disabled 1 Enabled When ECC is enabled writes to SDRAM include a write of the error correction code ECC to the SDRAM device s ECC location and reads from SDRAM are checked for a correct ECC Any ECC mismatch is reported in the appropriate registers and the appropriate interrupt is generated if enabled via the MULT_INT_ENB and SGL_INT_ENB bits This register ECCCTL should be modified only when the write buffer and the read ahead feature of the read buffer are disabled in the DBCTL register see page 8 3 Before ECC multi bit or single bit interrupts are enabled the ECCMAP register see page 12 19 must be configured to route the interrupt to the appropriate interrupt request level and priority Elan SC520 Microcontroller Register Set Manual 7 9 AMD ECC Status ECCSTA SDRAM Controller Registers Memory Mapped MMCR Offset 21h 1 0 Bit Reserved MBIT ERR SBIT ERR Reset 0 0 R W RSV R W R W Register Description This register maintains status of the ECC functions if ECC is enabled Note A programmable reset does not preserve this register s state Bit Definitions Programming Notes Name Reserved MBIT_ERR SBIT_ERR Function Reserved This bit field should be written to 0 for normal syst
178. via the corresponding PIOx FNC bit in the PIOPFS31_16 register see page 20 5 then writing to the pin s PIOx SET bit has no effect Although software can perform a 32 bit access of MMCR offset C34h to set bits across all 32 PIO pins with a single instruction the 32 bit access is split into two separate 16 bit accesses with the PIOSET15 0 register being accessed prior to the PIOSETS31 16 register The two writes are not simultaneous Elan SC520 Microcontroller Register Set Manual 20 23 AM Programmable Input Output Registers PIO15 PIOO Clear PIOCLR15 0 Memory Mapped MMCR Offset C38h 15 14 13 12 11 10 9 8 Bit PIO15_ PIO14_ PIO13_ PIO12_ PIO11_ PIO10_ PIOS PIO8 _ CLR CLR CLR CLR CLR CLR CLR CLR Reset x R W W W W W W W W W 7 6 5 4 3 2 1 0 Bit PIO7_ PIO6_ PIO5_ PIO4_ PIO3_ PIO2_ PIO1_ PIOO_ CLR CLR CLR CLR CLR CLR CLR CLR Reset x X x x x x X R W W W W W W W W W Register Description This register is used to make the output level Low selectively for pins PIO15 PIOO Bit Definitions Bit Name Function 15 PIO15 CLR PIO15 Clear 0 No effect 1 Drive the PIO15 signal Low 14 PIO14 CLR PIO14 Clear 0 No effect 1 Drive the PIO14 signal Low 13 PIO13 CLR PIO13 Clear 0 No effect 1 Drive the PIO13 signal Low 12 PIO12 CLR PIO12 Clear 0 No effect 1 Drive the PIO12 signal Low 11 PIO11 CLR PIO11 Clear
179. which point the appropriate action occurs based on the timer configuration options that are set For details see the GPTMROCTL register bits INT_ENB MAX_CNT_RIU MAX_CNT ALT_CMP and CONT_CMP starting on page 14 4 If the maxcount compare register that is in use contains a value other than 0000h and the timer is enabled the timer counts to the programmed maxcount value Elan SC520 Microcontroller Register Set Manual 14 7 AMDA General Purpose Timer Registers GP Timer 0 Maxcount Compare GPTMROMAXCMPB Memory Mapped MMCR Offset C78h 15 14 13 12 11 10 9 8 Bit MCB 15 8 Reset 0 0 0 0 0 0 0 0 R W R W 7 6 5 4 3 2 1 0 Bit MCB 7 0 Reset 0 0 0 0 0 0 0 0 R W R W Register Description This register contains one of the compare values for the GPTMROCNT register see page 14 6 Bit Definitions Bit Name Function 15 0 15 0 GP Timer 0 Maxcount Compare Register B This register contains one of the maximum values that GP Timer 0 can count to before resetting its count register to 0 Programming Notes GP Timer 0 GP Timer 1 each have two maxcount compare registers GPTMRxMAXCMPA and GPTMRxMAXCMPB If the maxcount compare register that is in use contains the value 0000h and the timer is enabled the timer counts to FFFFh at which point the appropriate action occurs based on the timer configuration options that are set For details see the GPT
180. 0 No effect 1 Drive the PIO11 signal Low 10 PIO10 CLR PIO10 Clear 0 No effect 1 Drive the PIO10 signal Low 9 PIO9 CLR PIO9 Clear 0 No effect 1 Drive the PIO9 signal Low 8 PIO8 CLR PIOS Clear 0 No effect 1 Drive the PIO8 signal Low 20 24 Elan SC520 Microcontroller Register Set Manual Bit 7 PIO7 CLR 6 PIO6 CLR 5 PIO5 CLR 4 PIO4 CLR 3 PIOS CLR 2 PIO2 CLR 1 PIO1 CLR 0 CLR Programming Notes Programmable Input Output Registers Function PIO7 Clear 0 No effect 1 Drive the PIO7 signal Low PIO6 Clear 0 No effect 1 Drive the PIO6 signal Low PIO5 Clear 0 No effect 1 Drive the PIOS signal Low 4 Clear 0 No effect 1 Drive the PIO4 signal Low PIO3 Clear 0 No effect 1 Drive the PIO3 signal Low PIO2 Clear 0 No effect 1 Drive the PIO2 signal Low PIO1 Clear 0 No effect 1 Drive the PIO1 signal Low PIOO Clear 0 No effect 1 Drive the PIOO signal Low AMD Each PIOx CLR bit is used to drive the corresponding PIO output Low Writing a 1 to any bit of this register causes the corresponding PIO to be driven Low if it is programmed to be an output via the corresponding PIOx DIR bit in the PIODIR15 0 register see page 20 12 Writing 1 to a pin s PIOx CLR bit overrides any previous write to the pin s PIOx DATA or SET bit see page 20 16 and page 20 20 Writing 0 to any bit in this reg
181. 0 8 bit data 1 16 bit data Data Width Select for GPCS5 This bit is used to select the default data width for the GP bus chip select 5 signal 0 8 bit data 1 16 bit data Data Width Select for GPCS4 This bit is used to select the default data width for the GP bus chip select 4 signal 0 8 bit data 1216 bit data Data Width Select for GPCS3 This bit is used to select the default data width for the GP bus chip select 3 signal 0 8 bit data 1216 bit data Data Width Select for GPCS2 This bit is used to select the default data width for the GP bus chip select 2 signal 0 8 bit data 1216 bit data Data Width Select for GPCS1 This bit is used to select the default data width for the GP bus chip select 1 signal 0 8 bit data 1216 bit data Data Width Select for GPCSO This bit is used to select the default data width for the GP bus chip select 0 signal 0 8 bit data 1216 bit data Elan SC520 Microcontroller Register Set Manual 10 3 General Purpose Bus Controller Registers Programming Notes The GPCSx DW bits are ignored if the GPIOCS16 signal is asserted during an I O access or if the GPMEMCS16 signal is asserted during a memory access The GPIOCS16 signal is ignored if it is asserted during a memory access Similarly the GPMEMCS16 signal is ignored if it is asserted during an I O access Before using one of the GPCS7 GPCSO signals software must set the corresponding GPCSx SEL bit inthe CSPFS re
182. 0 R W R W Register Description This location can be used to hold temporary data and is not required for serial data transfer Bit Definitions Bit Name Function 7 0 SCRATCH Scratch Bits 7 0 General purpose I O location not required for serial data transfer Programming Notes Elan SC520 Microcontroller Register Set Manual 18 25 UART Serial Port Registers 18 26 Elan SC520 Microcontroller Register Set Manual CHAPTER O AMDAN AMD 1 SYNCHRONOUS SERIAL INTERFACE REGISTERS 19 1 OVERVIEW This chapter describes the synchronous serial interface SSI registers of the lanSC520 microcontroller The SSI provides efficient full duplex or half duplex bidirectional communication with peripheral devices that use a 4 pin or 3 pin serial interface The SSI register set consists of five memory mapped configuration region MMCR registers used for SSI control transmit command status and receive functions See the Elan VSC520 Microcontroller User s Manual order 22004 for details about the SSI Table 19 1 lists the SSI registers in offset order with the corresponding description s page number 19 2 REGISTERS Table 19 1 SSI MMCR Registers Register Name Mnemonic MMCR Offset Page Number SSI Control SSICTL page 19 2 SSI Transmit SSIXMIT page 19 4 SSI Command SSICMD page 19 5 SSI Status SSISTA page 19 6 SSI Receive SSIRCV page 19 7 Elan SC520 Microcontroller Regist
183. 0 0 0 0 0 0 0 0 R W R W Register Description This register is used to program the offset time from the beginning of a GP bus cycle for all the GP bus chip selects Bit Definitions Bit Name 7 0 GPCS_OFF 7 0 Programming Notes Function Offset Time for the GP Bus Chip Select This field adjusts the offset time of all the GP bus chip selects The resolution of this parameter is one internal 33 MHz clock period The offset time used is GPCS_OFF 1 internal clock periods i e if GRCS_OFF is 0 the offset time is one clock period Before using one of the GPCS7 GPCS 1 signals software must set the corresponding GPCSx SEL bit inthe CSPFS register see page 20 7 Before using the GPCSO signal software must set the PIO27 SEL bit the PIOPFSS31 16 register see page 20 5 Figure 10 1 on page 10 7 shows the relationships between the various adjustable GP bus timing parameters Elan SC520 Microcontroller Register Set Manual 10 9 General Purpose Bus Controller Registers GP Read Pulse Width GPRDW Memory Mapped MMCR Offset COBh 7 6 5 4 3 2 1 0 Bit GP RD WIDTH 7 0 Reset 0 0 0 0 0 0 0 0 R W R W Register Description This register is used to program the signal width for the read strobes GPIORD and GPMEMRD Bit Definitions Bit Name Function 7 0 GP RD Signal Width for GPIORD and GPMEMRD WIDTH 7 0 This field adjusts the signal pulse
184. 01 Priority P1 Master PIC IRO Highest priority 00010 Priority P2 Master PIC IR1 00011 Priority P3 Slave 1 PIC IRO Master PIC IR2 00100 Priority P4 Slave 1 PIC IR1 00101 Priority P5 Slave 1 PIC IR2 00110 Priority P6 Slave 1 PIC IR3 00111 Priority P7 Slave 1 PIC IR4 01000 Priority P8 Slave 1 PIC IR5 01001 Priority P9 Slave 1 PIC IR6 01010 Priority P10 Slave 1 PIC IR7 01011 Priority P11 Master PIC IR3 01100 Priority P12 Master PIC IR4 01101 Priority P13 Slave 2 PIC IRO Master PIC IR5 01110 Priority P14 Slave 2 PIC IR1 01111 Priority P15 Slave 2 PIC IR2 10000 Priority P16 Slave 2 PIC IR3 10001 Priority P17 Slave 2 PIC IR4 10010 Priority P18 Slave 2 PIC IR5 10011 Priority P19 Slave 2 PIC IR6 10100 Priority P20 Slave 2 PIC IR7 10101 Priority P21 Master PIC IR6 10110 Priority P22 Master PIC IR7 Lowest priority 10111 11110 Disables the interrupt source as an input 11111 NMI source For example if INT_MAP 01101b the interrupt request is mapped to Mas priority P13 in the microcontroller If INT MAP 00000b or any binary value from 10111 11110b the interrupt request is disabled from reaching the microcontroller s PIC If this field is set to 111110 then the interrupt is routed to generate an NMI If bit S2 in the MPICICWS register is cleared see page 12 34 the Slave 1 PIC is bypassed so programming the INT MAP bit field to a value in the r
185. 02FAh page 18 15 UART 2 Line Control UART2LCR 02FBh page 18 17 UART 2 Modem Control UART2MCR 02FCh page 18 19 UART 2 Line Status UART2LSR 02FDh page 18 21 UART 2 Modem Status UART2MSR 02FEh page 18 23 UART 2 Scratch Pad UART 1 UART2SCRATCH 02FFh 03F8 03FFh page 18 25 UART 1 Transmit Holding UART1THR O3F8h page 18 7 UART 1 Receive Buffer UART1RBR O3F8h page 18 8 UART 1 Baud Clock Divisor Latch LSB UART1BCDL O3F8h page 18 9 UART 1 Baud Clock Divisor Latch MSB UART1BCDH O3F9h page 18 10 UART 1 Interrupt Enable UART1INTENB O3F9h page 18 11 UART 1 Interrupt ID UARTIINTID O3FAh page 18 12 UART 1 FIFO Control UART1FCR O3FAh page 18 15 UART 1 Line Control UARTILCR O3FBh page 18 17 UART 1 Modem Control UART1MCR O3FCh page 18 19 UART 1 Line Status UART1LSR O3FDh page 18 21 UART 1 Modem Status UART1MSR O3FEh page 18 23 UART 1 Scratch Pad PCI Bus Configuration Space Index Data 32 bit UART1SCRATCH O3FFh OCF8h OCFCh page 18 25 PCI Configuration Address PCICFGADR OCF8h page 6 15 PCI Configuration Data Configuration Base Address PCICFGDATA OCFCh page 6 17 1 3 PCI HOST BRIDGE INDEXED CONFIGURATION REGISTERS The lanSC520 microcontroller s PCI Host Bridge supports the required PCI
186. 1 Register Name System Address Mapping Configuration Register Overview Mnemonic MMCR Offset AMD Memory Mapped Configuration Region MMCR Registers By Offset Continued Page Number Address Decode Control ADDDECCTL Write Protect Violation Status WPVSTA Programmable Address Region 0 PARO Programmable Address Region 1 PAR1 Programmable Address Region 2 PAR2 Programmable Address Region 3 PARS Programmable Address Region 4 PAR4 Programmable Address Region 5 PAR5 Programmable Address Region 6 PAR6 Programmable Address Region 7 PAR7 Programmable Address Region 8 PAR8 Programmable Address Region 9 PARQ Programmable Address Region 10 PAR10 Programmable Address Region 11 PAR11 Programmable Address Region 12 PAR12 Programmable Address Region 13 PAR13 Programmable Address Region 14 PAR14 Programmable Address Region 15 GP Bus Controller PAR15 C00 C10h GP Echo Mode GPECHO Cooh page 10 2 GP Chip Select Data Width GPCSDW CO1h page 10 3 GP Chip Select Qualification GPCSQUAL C02h page 10 5 GP Chip Select Recovery Time GPCSRT C08h page 10 7 GP Chip Select Pulse Width GPCSPW Co9h page 10 8 GP Chip Select Offset GPCSOFF COAh page 10 9 GP Read Pulse Width GPRDW COBh page 10 10 GP Read Offset GPRDO
187. 1 interrupt programming summary table 18 14 Line Control register 18 17 Line Status register 18 21 MMCR registers table 18 1 Modem Control register 18 19 Modem Status register 18 23 Receive Buffer bit field 18 8 Receive Buffer register 18 8 Receive TC Detected bit field 18 4 Receive TC Interrupt Enable bit field 18 3 Scratch Pad register 18 25 Transmit Holding register 18 7 Transmit Holding Register bit field 18 7 Transmit TC Detected bit field 18 4 Transmit TC Interrupt Enable bit field 18 3 UART1BCDH register 18 10 UART1BCDL register 18 9 UARTI1CTL register 18 3 UART1FCR register 18 15 UART1FCRSHAD register 18 5 UART1INTENB register 18 11 UART1INTID register 18 12 UART1LCR register 18 17 UART1LSR register 18 21 UART1MAP register 12 21 UART1MCR register 18 19 UART1MSR register 18 23 UART1RBR register 18 8 UART1SCRATCH register 18 25 UART1STA register 18 4 UART1THR register 18 7 UART2BCDH register 18 10 UART2BCDL register 18 9 UART2CTL register 18 3 UART2FCR register 18 15 UART2FCRSHAD register 18 5 UART2INTENB register 18 11 UARTA2INTID register 18 12 UART2LCR register 18 17 UART2LSR register 18 21 UART2MAP register 12 21 UART2MCR register 18 19 UART2MSR register 18 23 UART2RBR register 18 8 UART2SCRATCH register 18 25 UART2STA register 18 4 UART2THR register 18 7 UARTx_DIS bit field 2 3 Index 21 AMD UDF Supported bit field 6 20 UDFS bit field 6 20
188. 1 register 12 39 S2PICICW2 register 12 45 S2PICICWS register 12 46 S2PICICWA register 12 47 S2PICINTMSK register 12 48 S2PICIR register 12 37 S2PICISR register 12 38 S2PICOCW2 register 12 41 S2PICOCWS register 12 43 SB bit field 18 17 SB ADDR bit field 7 14 SBCL CD bit field 6 22 SBIT ERR bit field 7 10 SCASx signal 7 4 20 10 SCP Command Port register 3 8 SCP Data Port register 3 7 SCP Reset Detect bit field 3 5 SCP_CMD bit field 3 8 SCP_DATA bit field 3 7 SCP_RST_DET bit field 3 5 SCPCMD register 3 8 SCPDATA register 3 7 SCRATCH bit field 18 25 Scratch Bits bit field 18 25 SCS_DRIVE bit field 20 10 SCSx signal 20 10 SD_RST_DET bit field 3 6 SDQM_DRIVE bit field 20 10 SDQM x signal 20 10 Elan SC520 Microcontroller Register Set Manual Index 17 AMD SDRAM Bank 0 3 Ending Address register 7 7 SDRAM Bank Configuration register 7 5 SDRAM Buffer Control register 8 2 SDRAM CAS Latency bit field 7 4 SDRAM Control register 7 2 SDRAM controller MMCR registers table 7 1 SDRAM ECC Interrupt Mapping bit field 12 20 SDRAM Operation Mode Select bit field 7 3 SDRAM RAS Precharge Delay bit field 7 4 SDRAM RAS to CAS Delay bit field 7 4 SDRAM Refresh Request Speed bit field 7 2 SDRAM Timing Control register 7 4 SECOND bit field 17 4 Select Counter x bit field 13 11 Select ICW1 bit field in MPICICW1 register 12 26 in MPICOCW2 register 12 28 SERR Enable bit field 6 20 SERR signal
189. 11 Trailing Edge Ring Indicator bit field 18 23 Transaction Complete Interrupt Enable bit field 19 2 Transfer Mode bit field in MSTDMAMODE register 11 91 in SLDMAMODE register 11 55 Transmit Holding Register 16450 Compatible Mode or Transmitter FIFO 16550 Compatible Mode Empty bit field 18 21 Transmit Receive Word Length Select bit field 18 18 Transmitter Empty Indicator bit field 18 21 Transmitter FIFO Clear bit field in UARTXFCR register 18 15 in UARTxFCRSHAD register 18 5 TRNMOD bit field in MSTDMAMODE register 11 91 in SLDMAMODE register 11 55 Tx INT STA bit field in GPTMRSTA register 14 2 txdackx internal signal 11 8 TXDRQx Channel Mapping bit field 11 8 internal signal 11 8 18 5 18 15 TXDRQx CHSEL bit field 11 8 TXTC DET bit field 18 4 TXTC bit field 18 3 U UART x Baud Clock Divisor Latch bit field in UARTxBCDH register 18 10 in UARTxBCDL register 18 9 Baud Clock Divisor Latch LSB register 18 9 Baud Clock Divisor Latch MSB register 18 10 Clock Source Enable bit field 18 3 direct mapped registers table 18 1 Disable bit field 2 3 FIFO Control register 18 15 FIFO Control Shadow register 18 5 General Control register 18 3 General Status register 18 4 Elan SC520 Microcontroller Register Set Manual AMD Interrupt Enable register 18 11 Interrupt ID register 18 12 interrupt identification and priority table 18 13 Interrupt Mapping register 12 2
190. 11 15 in GPDMAEXTPG7 register 11 16 DMA Channel x Mask bit field in MSTDMAGENMSK register 11 97 in SLDMAGENMSK register 11 61 DMA Channel x Memory Address bit field in GPDMA4MAR register 11 78 DMA Channel x Memory Address Bits 23 16 bit field in GPDMAOPG register 11 69 in GPDMA1PG register 11 65 in GPDMA2PG register 11 63 in GPDMASPG register 11 64 in GPDMASPG register 11 73 in GPDMAGPG register 11 71 DMA Channel x Memory Address Bits 23 17 bit field in GPDMA7PG register 11 72 DMA Channel x Next Address High bit field in GPDMANXTADDHS register 11 27 in GPDMANXTADDHB register 11 29 GPDMANXTADDH6 register 11 31 in GPDMANXTADDHT register 11 33 DMA Channel x Next Address Low bit field in GPDMANXTADDLS register 11 26 in GPDMANXTADDLS register 11 28 in GPDMANXTADDLE register 11 30 in GPDMANXTADDL7 register 11 32 Index 4 Elan SC520 Microcontroller Register Set Manual DMA Channel x Next Transfer Count High bit field in GPDMANXTTCHG register 11 35 in GPDMANXTTCHB register 11 37 in GPDMANXTTCH6 register 11 39 in GPDMANXTTCH7 register 11 41 DMA Channel x Next Transfer Count Low bit field in GPDMANXTTCLS register 11 34 in GPDMANXTTCLS register 11 36 in GPDMANXTTCL6 register 11 38 in GPDMANXTTCL7 register 11 40 DMA Channel x Transfer Count bit field in GPDMAOTC register 11 43 in GPDMA1TC register 11 45 in GPDMA2TC register 11 47 in GPDMASTC register 11 49 in GPDMA4TC register 11 79 in
191. 12 GP Timer 1 Maxcount Compare A GPTMR1MAXCMPA 14 13 GP Timer 1 Maxcount Compare B GPTMR1MAXCMPB 14 14 GP Timer 2 Mode Control 2 1 14 15 GP Timer 2 Count 2 14 17 GP Timer 2 Maxcount Compare A GPTMR2MAXCMPA 14 18 CHAPTER 15 SOFTWARE TIMER REGISTERS 15 1 15 1 OVervi8W we s xu xps Pare m aS 15 1 15 2 Registers bee 4nce uve NOE RPSL E 15 1 Software Timer Millisecond Count SWTMRMILLI 15 2 Software Timer Microsecond Count SWTMRMICRO 15 3 Software Timer Configuration SWTMRCFG 15 4 CHAPTER 16 WATCHDOG TIMER REGISTERS 16 1 16 1 OVervIew iu eo Rh ee bE Ole is Ua Aha 16 1 16 2 Registers hse a eed SEE a 16 1 Watchdog Timer Control 16 2 Watchdog Timer Count Low 16 4 Watchdog Timer Count High 16 5 Elan SC520 Microcontroller Register Set Manual Table of Contents CHAPTER17 REAL TIME CLOCK REGISTERS 1 dentate tain REDE NU RO ee d 17 2 Hegisters eie ER ERE EIE EE EXE RTC CMOS RAM Index RTC CMOS RAM Data Port RTCDATA RTC Current Seco
192. 13 GPTMR1MAXCMPB register 14 14 GPTMR2ONT register 14 17 GPTMR2CTL register 14 15 GPTMR2MAP register 12 21 GPTMR2MAXCMPA register 14 18 GPTMRSTA register 14 2 GPWROFF register 10 13 GPWRW register 10 12 GPxIMAP register 12 21 H HBCTL register 6 3 HBMSTIRQCTL register 6 9 HBMSTIRQSTA register 6 12 HBTGTIRQCTL register 6 5 Index HBTGTIRQSTA register 6 7 HDR_TYP bit field 6 23 Header Type bit field 6 23 Header Type register 6 23 HI PRI 0 SEL bit field 5 7 HI PRI 1 SEL bit field 5 7 Host Bridge Control register 6 3 Host Bridge Master Interrupt Address register 6 14 Host Bridge Master Interrupt Control register 6 9 Host Bridge Master Interrupt Status register 6 12 Host Bridge Target Interrupt Control register 6 5 Host Bridge Target Interrupt Status register 6 7 HOUR bit field 17 8 HOUR MODE SEL bit field 17 17 I O Hole Access Destination bit field 2 2 I O Pad Drive Strength for MA12 MAO and BA1 BAO bit field 20 11 for MD31 MDO and 6 bit field 20 11 for 5653 5690 bit field 20 10 for SDQM3 SDQM0 bit field 20 10 for SRASA SRASB SCASA SCASB and SWEA SWEB bit field 20 10 Space Enable bit field 6 21 IC4 bit field in MPICICW1 register 12 27 in S1PICICW1 register 12 52 in S2PICICW1 register 12 40 ICE HRST DET bit field 3 5 ICE ON RST bit field 3 3 ICE SRST DET bit field 3 5 ICEMAP register 12 21 ID2 IDO bit field in S1PICICWS register 12 58 in S2PICICWS
193. 14 pin is driven High and the other pins of AD31 AD11 are driven Low 19d The AD30 pin is driven High and the other pins of AD31 AD11 are driven Low 20d The 031 pin is driven High and the other pins of AD31 AD11 are driven Low 21 31d All pins AD31 AD11 are driven Low to 0 but the host bridge does not accept configuration accesses using these DEVICE NUM bit field values so configuration reads or writes with these values result in a Master Abort Performing a configuration read with these values returns FFFFh in the data In a typical system design one of the address pins AD31 AD12 is resistively coupled to each PCI bus device s IDSEL input so a DEVICE NUM bit field value in the range 1 20d selects the corresponding PCI bus device during a type zero configuration cycle For type one configuration cycles if the BUS NUM bit field is not 00h the contents of this bit field are driven unchanged on the PCI bus during the address phase of the cycle 10 8 FUNCTION Function Number NUNM 2 0 This bit field specifies the function number within the device specified by the DEVICE NUM bit field For host bridge configuration cycles if the BUS NUM and DEVICE NUM bit fields are both 0 the function number is ignored because the host bridge is a single function device For all other configuration cycles type zero or type one the contents of this bit field are driven unchanged on the PCI bus during the address phase of the co
194. 2003 for the RTC voltage monitor reference voltage Because the RTC reference voltage is too low to keep the RTC logic operational the RTC date time and CMOS RAM are invalid and the microcontroller performed an RTC only reset as a result An RTC only reset clears this latched status bit 1 Reading this bit causes it to be set to 1 and it remains set until an RTC only reset occurs Note that this bit is not a real time indication of the state of the external RTC backup battery although there can be a relationship For example if the RTC backup battery is removed while main system power is still applied this bit still reads back 1 until main system power is cycled This bit is always set to 0 upon RTC only reset This bit is always set to 1 after an initial read to this register is performed This bit remains set to 1 until an RTC only reset occurs RTC only reset occurs any time the BBATSEN input is sampled to be below the RTC reference voltage during a power on reset Reserved This bit field should be written to 0 for normal system operation The default value for this register RTCSTAD depends on whether an RTC only reset has occurred The RTC only reset occurs when the BBATSEN input is sampled to be below the RTC reference voltage prior to a power on system reset See the Elan SC520 Microcontroller Data Sheet order 22003 for the RTC voltage monitor reference voltage 17 20 Elan SC520 Microcontroller Register Set Manual
195. 31 16 Programmable Input Output Registers Memory Mapped MMCR Offset C32h 15 14 13 12 11 10 9 8 gy PlO3t_ PIO30_ PIO29 PIO28 PIO27 PIO26 PIO25 PIO24 DATA DATA DATA DATA DATA DATA DATA DATA Reset R W RW R W R W R W R W R W R W R W 7 6 5 4 3 2 1 0 pir 23_ PIO22_ PIO21_ PIO20 PIO19 PIO18_ PIO17_ PIO16_ DATA DATA DATA DATA DATA DATA DATA DATA Reset 2 2 2 2 R W RW R W R W R W R W R W R W R W Register Description This register is used to read or write the value for pins PIO31 PIO16 Bit Definitions Bit Name 15 PIO31 DATA 14 DATA 13 PIO29 DATA 12 PIO28 DATA 11 PIO27 DATA 10 26 DATA 9 PIO25 DATA 8 PIO24 DATA 20 18 Function Read or Write the PIO31 Pin 0 PIO31 is Low 1 PIO31 is High Read or Write the PIO30 Pin 0 PIO30 is Low 1 is High Read or Write the PIO29 Pin 0 PIO29 is Low 1 PIO29 is High Read or Write the PIO28 Pin 0 PIO28 is Low 1 PIO28 is High Read or Write the PIO27 Pin 0 PIO27 is Low 1 PIO27 is High Read or Write the PIO26 Pin 0 PIO26 is Low 1 PIO26 is High Read or Write the PIO25 Pin 0 PIO25 is Low 1 PIO25 is High Read or Write the PIO24 Pin 0 24 is Low 1 PIO24 is High Elan SC520 Microcontroller Register Set Manual Programmable Input Output Registers AMD Function 7 PIO23 DATA Read or Write t
196. 4 register 12 59 in S2PICICWA register 12 47 Special Mask Mode bit field in MPICOCWS register 12 30 in S1TPICOCWS register 12 55 in S2PICOCWS register 12 43 Specific EOI Level Select bit field in MPICOCW2 register 12 28 in STPICOCW2 register 12 54 in S2PICOCW2 register 12 41 SRASx signal 7 4 20 10 SRCW DRIVE bit field 20 10 sreset internal signal 3 8 3 9 SSI Busy bit field 19 6 SSI Clock Speed Select bit field 19 2 selections table 19 2 SSI Command register 19 5 SSI Control register 19 2 SSI Data IN bit field 19 7 SSI Data Out bit field 19 4 SSI Interrupt Mapping register 12 21 SSI Inverted Clock Mode Enable bit field 19 3 SSI Inverted Phase Mode Enable bit field 19 3 SSI MMCR registers table 19 1 SSI Vost Significant Bit First Mode Enable bit field 19 3 SSI Receive register 19 7 SSI Status register 19 6 SSI Transaction Complete Interrupt bit field 19 6 SSI Transmit register 19 4 SSI CLK signal 19 3 19 6 in SSICTL register 19 2 19 3 in SSISTA register 19 6 SSI DI signal in SSICTL register 19 3 in SSIRCV register 19 7 SSI DO signal in SSICTL register 19 3 in SSIXMIT register 19 4 SSICMD register 19 5 SSICTL register 19 2 SSIMAP register 12 21 Index 19 AMD SSIRCV register 19 7 SSISTA register 19 6 SSIXMIT register 19 4 Start Address bit field 2 9 Status Register Select bit field in MPICOCWS register 12 30 in S1PICOCWS register 12 55 in S2PICOCWS register 12
197. 41h page 13 5 PIT 2 Status PIT2STA 0042h page 13 5 PIT Mode Control PITMODECTL 0043h page 13 7 PIT Counter Latch Command PITCNTLAT 0043h page 13 10 PIT Read Back Command SCP Data Port System Control Port B SCP Command Port RTC Index Data PITRDBACK SCPDATA SYSCTLB SCPCMD 0043h 0070h 0071h page 13 11 page 3 7 page 13 13 page 3 8 RTC CMOS RAM Index RTCIDX 0070h page 17 2 RTC CMOS RAM Data Port DMA Page and General Registers RTCDATA 0071h 0080 008Fh page 17 3 General 0 GPDMAGRO 0080h page 11 62 Slave DMA Channel 2 Page GPDMA2PG 0081h page 11 63 Slave DMA Channel 3 Page GPDMA3PG 0082h page 11 64 Slave DMA Channel 1 Page GPDMA1PG 0083h 1 8 Elan SC520 Microcontroller Register Set Manual page 11 65 Configuration Register Overview Table 1 2 Register Name General 1 Direct Mapped I O Registers Continued Mnemonic GPDMAGR 1 Address AMD Page Number page 11 66 General 2 GPDMAGR2 page 11 67 General 3 GPDMAGR3 page 11 68 Slave DMA Channel 0 Page GPDMAOPG page 11 69 General 4 GPDMAGR4 page 11 70 Master DMA Channel 6 Page GPDMA6PG page 11 71 Master DMA Channel 7 Page GPDMA7PG page 11 72 Master DMA Channel 5 Page GPDMA5PG page 11 73 General 5 GPDMAGR5 page 11 74 General 6
198. 43 Status Command register 6 19 Stick Parity Enable bit field 18 17 Stop Bits bit field 18 18 STP bit field 18 18 Sub Class Code bit field 6 22 SUB DLY bit field in BOOTCSCTL register 9 2 in ROMCS1CTL register 9 4 in ROMCS2CTL register 9 6 support iii SW Px TRIG bit field in SWINT16 1 register 12 10 12 11 12 12 in SWINT22 17 register 12 13 12 14 SWEx signal 20 10 SWINT16 1 register 12 10 SWINT22 17 register 12 13 SWT Microsecond Count bit field 15 3 SWTMRCFG register 15 4 SWTMRMICRO register 15 3 SWTMRMILLI register 15 2 Sx bit field 12 33 12 34 Sx GINT MODE bit field 12 4 12 5 SYS RST bit field 3 4 SYSARBCTL register 5 2 SYSARBMENB register 5 4 SYSCTLA register 3 9 SYSCTLB register 13 13 SYSINFO register 3 2 system address mapping MMCR registers table 2 1 System Arbiter Concurrent Mode Enable bit field 5 2 Control register 5 2 Master Enable register 5 4 MMCR registers table 5 1 System Board Information register 3 2 System Control Port A register 3 9 System Control Port B register 13 13 System Control Processor Data bit field 3 7 SZ ST ADR bit field 2 8 Index T T APER IRQ ENB bit field 6 5 T APER IRQ SEL bit field 6 5 T APER IRQ bit field 6 8 T DLYTO IRQ ENB bit field 6 5 T DLYTO IRQ SEL bit field 6 5 T DLYTO IRQ STA bit field 6 7 T DLYTR ENB bit field 6 4 T DPER IRQ ENB bit field 6 6 T DPER IRQ SEL bit field 6 5 T DPER IRQ STA bit field 6 8 T IR
199. 5 In enhanced mode this bit field is used with the DMA5TC 15 0 bit field in the GPDMA5TC register see page 11 81 to allow counts up to 16 M 16 777 216 transfers In normal mode the value of this bit field DMASTC 23 16 is ignored Programming Notes Enhanced mode is enabled by setting the ENH MODE ENB bit in the GPDMACTL register see page 11 4 In PCI bus 2 2 compliant designs software must limit the length of GP bus DMA demand or block mode transfers Very large transfers could cause the PCI Host Bridge target controller to violate the 10 us memory write maximum completion time limit set in the PC Local Bus Specification Revision 2 2 11 18 Elan SC520 Microcontroller Register Set Manual GP DMA Controller Registers AMDA GP DMA Channel 6 Extended Transfer Count GPDMAEXTTC6 Memory Mapped MMCR Offset D92h 7 6 5 4 3 2 1 0 Bit DMA6TC 23 16 Reset 0 0 0 0 0 0 0 0 R W RW Register Description This register provides the extended transfer count bits for Channel 6 Bit Definitions Bit Name Function 7 0 DMA6TC DMA Channel 6 Transfer Count Extension 23 16 This bit field provides the higher 8 bits of the transfer count for DMA Channel 6 In enhanced mode this bit field is used with the DMA6TC 15 0 bit field in the GPDMA6TC register see page 11 83 to allow counts up to 16 M 16 777 216 transfers In normal mode the value of this bit field DMA6TC 23 16 is ignored
200. 6 Initialization Control Word 4 register 12 47 In Service register 12 38 Interrupt Mask register 12 48 Interrupt Mode register 12 9 Interrupt Request register 12 37 Operation Control Word 2 register 12 41 Operation Control Word 3 register 12 43 Slave DMA See also DMA GP DMA Master DMA Slave DMA Channel 0 Memory Address register 11 42 Page register 11 69 Transfer Count register 11 43 Slave DMA Channel 0 3 Control register 11 51 Mask register 11 54 Mode register 11 55 Status register 11 50 Slave DMA Channel 1 Memory Address register 11 44 Page register 11 65 Transfer Count register 11 45 Slave DMA Channel 2 Memory Address register 11 46 Page register 11 63 Transfer Count register 11 47 Slave DMA Channel 3 Memory Address register 11 48 Page register 11 64 Transfer Count register 11 49 Slave DMA Clear Byte Pointer register 11 57 Slave DMA Controller Reset register 11 58 Slave DMA Controller Temporary register 11 59 Slave DMA General Mask register 11 61 Slave DMA Mask Reset register 11 60 Slave Software DRQ n Request register 11 53 Index 18 Elan SC520 Microcontroller Register Set Manual Slave x PIC Channel x Interrupt Mode bit field in SL1PICMODE register 12 8 SL2PICMODE register 12 9 Global Interrupt Mode Enable bit field 12 4 12 5 ID 2 0 bit field in S1PICICWS register 12 58 in S2PICICWS register 12 46 SLAVE CBP bit field 11 57 SLAVE MSK RST bit field 11 60 SLAVE RST bit field 11
201. 7 in buffer chaining mode Bit Definitions Bit Name Function 7 0 DMA7_NXT_ DMA Channel 7 Next Transfer Count High TC 23 16 This bit field provides bits 23 16 of the next transfer count to be used by Channel 7 in the buffer chaining mode Programming Notes The value of this register is ignored if buffer chaining mode is not enabled for this channel in the GPDMABCCTL register see page 11 21 In PCI bus 2 2 compliant designs software must limit the length of GP bus DMA demand or block mode transfers Very large transfers could cause the PCI Host Bridge target controller to violate the 10 us memory write maximum completion time limit set in the PCI Local Bus Specification Revision 2 2 lan SC520 Microcontroller Register Set Manual 11 41 GP DMA Controller Registers Slave DMA Channel 0 Memory Address GPDMAOMAR Direct Mapped I O Address 0000h 7 6 5 4 3 2 1 0 Bit DMAOMAR 15 0 Reset X X X X X X X X R W R W Register Description This register contains bits 15 0 of the memory address for Channel 0 during DMA operation Bit Definitions Bit Name Function 7 0 DMAOMAR Lower 16 Bits of DMA Channel 0 Memory Address 15 0 This 8 bit field is used in two successive I O accesses to read or write the channel s memory address bits 15 0 Bits 7 0 of the channel s memory address can be read from or written to this bit field immediately after a write to the SLDMACBP regist
202. 8 Set 0 No effect 1 Set the PIO8 signal High 20 20 Elan SC520 Microcontroller Register Set Manual Bit Name 7 PIO7 SET 6 PlO6 SET 5 PIO5 SET 4 PIO4 SET 3 PIOS SET 2 PIO2 SET 1 PIO1 SET 0 PIOO SET Programming Notes Programmable Input Output Registers Function PIO7 Set 0 No effect 1 Set the PIO7 signal High PIO6 Set 0 No effect 1 Set the PIO6 signal High PIO5 Set 0 No effect 1 Set the PIOS signal High PIO4 Set 0 No effect 1 Set the PIO4 signal High PIO3 Set 0 No effect 1 Set the PIO3 signal High PIO2 Set 0 No effect 1 Set the PIO2 signal High PIO1 Set 0 No effect 1 Set the PIO1 signal High PIOO Set 0 No effect 1 2 Set the PIOO signal High AMD Each PIOx SET bit is used to drive the corresponding PIO output High Writing a 1 to any bit of this register causes the corresponding PIO pin to be driven High if it is programmed to be an output via the corresponding PlOx DIR bit in the PIODIR15 0 register see page 20 12 Writing 1 to a pin s PIOx SET bit overrides any previous write to the pin s PIOx DATA or PIOx CLR bit see page 20 16 and page 20 24 Writing O to any bit in this register has no effect If a PIO pin is programmed to be an input or if the pin is programmed for its interface function via the corresponding PIOx FNC bit in the PIOPFS15 0 register see page 20 3 then writing to the pin s PIOx SET bit has no effect
203. 9 CLR PIO29 Clear 0 No effect 1 Drive the PIO29 signal Low 12 PIO28 CLR PIO28 Clear 0 No effect 1 Drive the PIO28 signal Low 11 PIO27 CLR P1027 Clear 0 No effect 1 Drive the PIO27 signal Low 10 PlO26 CLR PIO26 Clear 0 No effect 1 Drive the PIO26 signal Low 9 PIO25 CLR PIO25 Clear 0 No effect 1 Drive the PIO25 signal Low 8 PlO24 CLR PIO24 Clear 0 No effect 1 Drive the PIO24 signal Low 20 26 Elan SC520 Microcontroller Register Set Manual Bit Name 7 PIO23 CLR 6 PIO22 CLR 5 PIO21 CLR 4 PIO20 CLR 3 PIO19 CLR 2 PIO18 CLR 1 PIO17 CLR 0 16 CLR Programming Notes Programmable Input Output Registers Function PIO23 Clear 0 No effect 1 Drive the PIO23 signal Low PIO22 Clear 0 No effect 1 Drive the PIO22 signal Low PIO21 Clear 0 No effect 1 Drive the PIO21 signal Low PIO20 Clear 0 No effect 1 Drive the PIO20 signal Low PIO19 Clear 0 No effect 1 Drive the PIO19 signal Low PIO18 Clear 0 No effect 1 Drive the PIO18 signal Low PIO17 Clear 0 No effect 1 Drive the PIO17 signal Low PIO16 Clear 0 No effect 1 Drive the PIO16 signal Low AMD Each PIOx CLR bit is used to drive the corresponding PIO output Low Writing a 1 to any bit of this register causes the corresponding PIO pin to be driven Low if it is programmed to be an output via the corresponding PIOx DIR bit in the PIODIR31_16 register se
204. A channel are used to cascade to the slave DMA controller in a PC AT compatible system DMA Channel 4 is not used directly for DMA transfers So this register has no real function it is documented only for ee For the same reason there is no corresponding page register for DMA hannel 4 Programming Notes 11 78 Elan SC520 Microcontroller Register Set Manual GP DMA Controller Registers Master DMA Channel 4 Transfer Count GPDMA4TC AMD Direct Mapped Address 00C2h 7 6 5 4 3 1 0 Bit 4 1 5 0 Reset x x x x x x x R W R W Register Description Because Channel 4 is used to cascade the slave DMA controller to the master DMA controller this register has no real use Bit Definitions Bit 7 0 DMMTC 15 0 Programming Notes Function DMA Channel 4 Transfer Count In a discrete DMA controller this bit field holds the 16 bit transfer count for DMA Channel 4 Because the drq and dack internal signals for this DMA channel are used to cascade to the slave DMA controller in a PC AT compatible system DMA Channel 4 is not used directly for DMA transfers So this register has no real function it is documented only for completeness Elan SC520 Microcontroller Register Set Manual 11 79 AMD GP DMA Controller Registers Master DMA Channel 5 Memory Address GPDMA5MAR Direct Mapped I O Address 00C4h 7 6 5 4 3 2 1 0 Bit
205. ALT CMP bit is 1 see page 14 11 and the GPTMRICNT register value page 14 12 equals the value of either register GPTMR1MAXCMPA page 14 13 or GPTMR1MAXCMPB page 14 14 The ALT CMP bit is 0 and the GPTMR1ONT register value equals the value of the GPTMR1MAXCMPA register only When the INT ENB bit is 0 the timer does not cause the T1 INT STA bit to be set in the GPTMRSTA register see page 14 2 and therefore a timer interrupt is not generated Before GP Timer 1 interrupts are enabled the GPTMR1MAP register see page 12 21 must be configured to route the interrupt to the appropriate interrupt request level and priority GP Timer 1 Maxcount Compare Register In Use This bit can be used by software with the MAX ONT bit to determine where the timer is in its current count sequence 0 Hardware clears this MAX CNT RIU bit when the GPTMR1MAXCMPA register see page 14 13 is being used for comparison to the GP Timer 1 count value 1 Hardware sets this MAX CNT RIU bit when the GPTMR1MAXCMPPB register see page 14 14 is being used for comparison to the GP Timer 1 count value Hardware also clears this bit any time hardware disables the timer by clearing the ENB bit i e at the end of the timer count when in noncontinuous mode See the CONT bit description on page 14 11 Reserved This bit field should be written to 0 for normal system operation GP Timer 1 Maximum Count This bit can be used by software with the MAX CNT
206. ALT_CMP 0 CONT CMP Programming Notes General Purpose Timer Registers AMDA Function GP Timer 1 Prescaler This bit selects the GP Timer 1 clock source when the TMRIN1 input pin is not configured as the timer clock source i e when the EXT_CLK bit is 0 0 The GP Timer 1 clock source is the internal clock 33 000 MHz or 33 333 MHz depending on the crystal frequency 1 The GP Timer 1 is pre scaled by GP Timer 2 i e the internal GP Timer 2 output is used as the input clock source for GP Timer 1 This bit is ignored when external clocking is enabled i e the EXT bit is 1 GP Timer 1 External Clock This bit selects the external GP Timer 1 clock source 0 An internal GP Timer 1 clock source is used as configured via the SEL bit When the timer clock is not being sourced from GP Timer 2 the timer advances every 4th CPU clock period 1 external GP Timer 1 clock source is used i e the TMRIN1 GP Timer 1 advances upon every positive edge driven on the TMRIN1 input pin In this mode the maximum timer input clock frequency is 1 4th of the CPU clock speed GP Timer 1 Alternate Compare This bit selects whether the GP Timer 1 count is compared to a single maximum count register value or alternately to both maximum count register values 0 Single compare mode the timer counts to the GPTMR1MAXCMPA register value see page 14 13 and then resets the GPTMRICNT register value to 0 page 14 12
207. Automatic initialization causes the channel s base address and transfer count registers to be restored to the values they contained prior to the DMA transfer when the transfer count ends The channel is then ready to perform another DMA transfer without processor intervention as soon as the next DMA request is detected Automatic initialization must be disabled when buffer chaining mode is used otherwise unexpected results may occur Operation Select This bit field selects the DMA operation for the channel selected by the MODSEL bit field 00 Verify mode The DMA controller acts normally except that no I O or memory commands are generated and no data is transferred 01 Write transfer Data is transferred from a DMA capable I O or memory mapped device into system memory 10 Read transfer Data is transferred from system memory to a DMA capable I O or memory mapped device 11 Reserved Elan SC520 Microcontroller Register Set Manual 11 91 GP DMA Controller Registers Bit Name Function 1 0 MODSEL 1 0 DMA Channel Select This bit field selects the channel that is to internally latch the other bits written to this register 00 Select Channel 4 01 Select Channel 5 10 Select Channel 6 11 Select Channel 7 Programming Notes 11 92 Elan SC520 Microcontroller Register Set Manual GP DMA Controller Registers AMDA Master DMA Clear Byte Pointer MSTDMACBP Direct Mapped I O Address 00D8h
208. Bit Name Function 7 3 Reserved Reserved This bit field should be written to 0 for normal system operation 2 BUS PARK PCI Bus Arbiter Bus Park SEL This bit controls which PCI master the PCI bus arbiter parks on when the PCI bus is idle 0 Park the PCI bus on the Am5 86 CPU 1 Park the PCI bus on the last PCI master that acquired the bus This bit must be 0 when operating in nonconcurrent mode The BUS PARK SEL bit must not be changed except when the PCI bus is currently parked on the Am5 86 CPU This is the default state after a system reset See the Elan SC520 Microcontroller User s Manual order 22004 for information about system arbiter initialization 1 CNCR MODE System Arbiter Concurrent Mode Enable ENB This bit enables the system arbiter to operate in concurrent mode When operating in nonconcurrent mode the BUS PARK SEL bit must be configured to park on the Am5 86 CPU 0 The system arbiter operates in nonconcurrent mode 1 The system arbiter operates in concurrent mode The CNCR MODE ENB bit must not be changed except during system arbiter initialization after a system reset See the Elan SC520 Microcontroller User s Manual order 22004 for information about system arbiter initialization 0 GNT TO INT PCI Bus Arbiter Grant Time Out Interrupt Enable ENB This bit is used to enable interrupts that are generated when the PCI bus arbiter detects a grant time out 0 Disable PCI bus arbiter interrupts 1 Enable PC
209. C CMOS RAM Index RTCIDX Direct Mapped Address 70h 7 6 5 4 3 2 1 0 Bit Reserved CMOSIDX 6 0 Reset X 0 0 0 0 0 0 0 R W RSV Ww Register Description This register is used to specify the RTC index address to be accessed via the RTCDATA register see page 17 3 Bit Definitions Bit Name 7 Reserved 6 0 CMOSIDX 6 0 Programming Notes Function Reserved RTC CMOS RAM Index This bit field is used to specify the RTC or CMOS RAM index to be read or written via the RTCDATA register see page 17 3 Bit 7 of this register is typically used as the NMI enable bit in PC AT compatible systems In the ElanSC520 microcontroller this function has been moved to the NMI_ENB bit in the PICICR register see page 12 4 See the programmable interrupt controller chapter of the Elan SC520 Microcontroller User s Manual order 22004 for more information 17 2 Elan SC520 Microcontroller Register Set Manual Real Time Clock Registers RTC CMOS RAM Data Port RTCDATA AMD Direct Mapped Address 71h 7 6 5 4 3 1 0 Bit CMOSDATA 7 0 Reset x x x x x x x R W R W Register Description This register is the RTC data port used to access the RTC index specified in the RTCIDX register see page 17 2 Bit Definitions Bit Name 7 0 CMOSDATA 7 0 Programming Notes Function RTC CMOS Data Port This bit field is used to write to or read
210. C Operation Control Word 3 MPICOCWS page 12 30 Master PIC Initialization Control Word 2 MPICICW2 page 12 32 Master PIC Initialization Control Word 3 MPICICW3 page 12 33 Master PIC Initialization Control Word 4 MPICICW4 page 12 35 Master PIC Interrupt Mask MPICINTMSK page 12 36 Slave 2 PIC Interrupt Request S2PICIR page 12 37 Slave 2 PIC In Service S2PICISR page 12 38 Slave 2 PIC Initialization Control Word 1 S2PICICW 1 page 12 39 Slave 2 PIC Operation Control Word 2 S2PICOCW2 page 12 41 Slave 2 PIC Operation Control Word 3 S2PICOCW3 page 12 43 Slave 2 PIC Initialization Control Word 2 S2PICICW2 page 12 45 Slave 2 PIC Initialization Control Word 3 S2PICICW3 page 12 46 Slave 2 PIC Initialization Control Word 4 S2PICICWA Elan SC520 Microcontroller Register Set Manual page 12 47 Table 12 2 Programmable Interrupt Coniroller Registers AMD Programmable Interrupt Controller Direct Mapped Registers Continued Register Name Slave 2 PIC Interrupt Mask Mnemonic S2PICINTMSK Address Page Number page 12 48 Slave 1 PIC Interrupt Request S1PICIR page 12 49 Slave 1 PIC In Service S1PICISR page 12 50 Slave 1 PIC Initialization Control Word 1 S1PICICW1 page 12 51 Slave 1 PIC Operation Control Word 2 S1PICOCW2 page 12 53 Slave 1 PIC Operation Con
211. CD3h 7 6 5 4 3 2 1 0 Bit Reserved BSY TC_INT Reset 0 0 0 0 0 0 0 0 R W RSV R R W Register Description This register reports SSI port busy status and a latched transaction complete status Bit Definitions Bit Name Function 7 2 Reserved Reserved This bit field should be written to 0 for normal system operation 1 BSY SSI Busy This bit reports SSI activity status 0 The port is not busy 1 The port is busy The port is busy active while a receive or transmit operation is in progress This bit is set by the SSI hardware after a command is written and cleared by hardware when the transaction is complete Transaction complete status is also indicated by the TC INT bit Writes to the BSY bit have no effect 0 TC INT SSI Transaction Complete Interrupt This bit indicates transaction complete status 0 No transaction has completed since software cleared this bit 1 A transaction has completed since software cleared this bit Software must clear this bit by writing a 1 The TC INT bit remains set until software acknowledges this completion by writing a 1 When the TC INT bit is set an interrupt request is generated if enabled via the TC INT ENB bit in the SSICTL register see page 19 2 SSI activity is also indicated by the BSY bit Programming Notes This register SSISTA should not be written while the BSY bit is set Also unreliable operation occurs if the SSICTL SSIXMIT o
212. CH2 INT CH1 INT CHO INT MODE MODE MODE MODE MODE MODE MODE MODE 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W Register Description This register controls the individual Slave 2 PIC channel interrupt mode Bit Definitions Bit Programming Notes Name CH7_INT_ MODE CH6_INT_ MODE CH5_INT_ MODE CH4_INT_ MODE CH3_INT_ MODE CH2_INT_ MODE CH1_INT_ MODE CHO_INT_ MODE Function Slave 2 PIC Channel 7 Interrupt Mode 0 Edge sensitive interrupt request detection 1 Level sensitive interrupt request detection Slave 2 PIC Channel 6 Interrupt Mode 0 Edge sensitive interrupt request detection 1 Level sensitive interrupt request detection Slave 2 PIC Channel 5 Interrupt Mode 0 Edge sensitive interrupt request detection 1 Level sensitive interrupt request detection Slave 2 PIC Channel 4 Interrupt Mode 0 Edge sensitive interrupt request detection 1 Level sensitive interrupt request detection Slave 2 PIC Channel 3 Interrupt Mode 0 Edge sensitive interrupt request detection 1 Level sensitive interrupt request detection Slave 2 PIC Channel 2 Interrupt Mode 0 Edge sensitive interrupt request detection 1 Level sensitive interrupt request detection Slave 2 PIC Channel 1 Interrupt Mode 0 Edge sensitive interrupt request detection 1 Level sensitive interrupt request detection Slave 2 PIC Channel 0 Interrupt Mode 0 Edge sensitive interrupt reques
213. COCW2 and for the S2PICOCW3 and S2PICICW1 registers see page 12 43 and page 12 39 Bit Definitions Bit 7 5 Name R_SL_EOI 2 0 SLCT_ICW1 IS OCWS LS 2 0 Function Interrupt Request EOI and Priority Rotation Controls 000 Rotate in auto EOI mode clear 001 Nonspecific EOI 010 No operation 011 Specific EOI 100 Rotate in auto EOI mode set 101 Rotate on nonspecific EOI command 110 Set priority command 111 Rotate on specific EOI command Initialization Control Word 1 Select Software must clear this bit to 0 when writing this address Port 0024h to access either this register S2PICOCW2 or the S2PICOCWS register 0 The write accesses either this register S2PICOCW2 or the S2PICOCWS register see page 12 43 depending on the state of bit 3 1 The write accesses the S2PICICW1 register see page 12 39 Access is OCW3 Software must clear this bit IS_OCW3 and clear SLCT_ICW1 when writing this address Port 0024h to access this register S2PICOCW2 0 The write accesses this register S2PICOCW2 if the SLCT_ICW1 bit is cleared 1 The write accesses the S2PICOCWS register see page 12 43 if the SLCT_ICW1 bit is cleared Specific EOI Level Select Interrupt level that is acted upon when the SL bit 1 see bits 7 5 of this register 000 IRO 001 IR1 010 IR2 011 IR3 100 IR4 101 IR5 110 IR6 111 IR7 Elan SC520 Microcontroller Register Set Manual 12 41 AMD
214. Command Port SCPCMD Direct Mapped I O Address 0064h 7 6 5 4 3 2 1 0 Bit SCP CMD Reset 0 0 0 0 0 0 0 0 R W W Register Description This register is used to emulate system control processor SCP a20 gate and CPU Reset commands Bit Definitions Bit Name Function 7 0 SCP CMD SCP Command The ElanSC520 microcontroller has no external input pins for the a20 gate and CPU reset signals that are normally driven by an external PC AT compatible system control processor SCP In order to maintain software compatibility internal logic is provided to watch this port for SCP command sequences D1h To control the a20 signal write the value D1h to this port then write to the A20 GATE bit of the SCPDATA register see page 3 7 FEh To reset the CPU write the value FEh to this port This pulses the internal CPU sreset signal generating a CPU soft reset The Am5 86 CPU cache state and the ElanSC520 microcontroller MMCR indexed and direct mapped registers are not affected by this soft reset with the exception that the NMI bit in the PICICR register is cleared see page 12 4 Clearing the NMI ENB bit allows software to initialize the stack pointer before setting the NMI ENB bit again after a soft reset Following this reset the SCP RST DET bit in the RESSTA register is set to indicate the source of this reset see page 3 5 Programming Notes There is no internal storage element associa
215. Control Word 1 Select Software must set this bit to 1 when writing this address Port 0024h to access this register S2PICICW1 0 The write does not access this register S2PICICW1 Instead either the S2PICOCW2 register see page 12 41 or the S2PICOCWS register see page 12 43 is written depending on the state of bit 3 1 The write accesses this register S2PICICW1 Subsequent writes to Port 0025h access additional initialization control words See the programming notes for this register S2PICICW1 on page 12 40 3 LTIM Level Triggered Interrupt Mode This bit is the global interrupt mode selection for the Slave 2 PIC 0 Edge sensitive interrupt request detection 1 Level sensitive interrupt request detection If the S2 GINT MODE bit in the PICICR register is set see page 12 4 the LTIM bit determines the interrupt mode for the Slave 2 PIC channels If the S2 GINT MODE bit is cleared the Slave 2 LTIM bit has no meaning and the Slave 2 PIC channel modes can be programmed individually via the SL2PICMODE register see page 12 9 2 ADI Address Interval 0 Interrupt vectors are separated by eight locations 1 Interrupt vectors are separated by four locations In the lanSC520 microcontroller design this bit is internally fixed to 1 lan SC520 Microcontroller Register Set Manual 12 39 AMD Programmable Interrupt Coniroller Registers Bit Name Function 1 SNGL Single PIC 0 Cascade mode S2PICICWS is expected 1 Singl
216. D bit field value but greater than or equal to the value specified by the BNK2_END bit field or the next lower enabled bank s end value if Bank 2 is disabled Bank 2 Enable This bit enables Bank 2 0 Disabled 1 Enabled Elan SC520 Microcontroller Register Set Manual 7 7 AMD Bit 22 16 14 8 Name BNK2_END 28 22 BNK1 ENB BNK1 END 28 22 BNKO BNKO END 28 22 SDRAM Controller Registers Function Bank 2 Ending Address This bit field determines the Bank 2 boundary defined in 4 Mbyte increments This value is compared to physical address bits 28 22 during an SDRAM request to select a bank Bank 2 is selected if physical address bits 28 22 are less than the BNK2 END bit field value but greater than or equal to the value specified by the BNK1 END bit field or the next lower enabled bank s end value if Bank 1 is disabled Bank 1 Enable This bit enables Bank 1 0 Disabled 1 Enabled Bank 1 Ending Address This bit field determines the Bank 1 boundary defined in 4 Mbyte increments This value is compared to physical address bits 28 22 during an SDRAM request to select a bank Bank 1 is selected if physical address bits 28 22 are less than the BNK1 bit field value but greater than or equal to the value specified by the BNKO END bit field or 0 if Bank 0 is disabled Bank 0 Enable This bit enables Bank 0 0 Disabled 1 Enabled Bank 0 Ending Address
217. DMA5MAR 16 1 Reset X X X X X X X X R W R W Register Description This register contains bits 16 1 of the memory address for Channel 5 during DMA operation Bit Definitions Bit Name Function 7 0 DMA5MAR Lower 16 Bits of DMA Channel 5 Memory Address 16 1 This 8 bit field is used in two successive I O accesses to read or write the channel s memory address bits 16 1 for 16 bit DMA transfers Bits 8 1 of the channel s memory address can be read from or written to this bit field immediately after a write to the MSTDMACBP register See page 11 93 Bits 16 9 of the channel s memory address can be read from or written to this bit field immediately after memory address bits 8 1 are read from or written to this bit field Programming Notes To ensure that the lower byte of this register GPDMA5MAR is always accessed first software should precede any access to this register with a write to the MSTDMACBP register see page 11 93 to clear the master DMA byte pointer The value in this register GPDMA5MAR is used with the values in the GPDMA5PG register see page 11 73 and the GPDMAEXTPG5 register see page 11 14 to generate DMA address bits 27 0 By default this channel is set up for PC AT compatibility 16 bit DMA transfers on the master DMA controller For 16 bit transfers this register GPDMA5MAR holds address bits 16 1 and address bit 0 is always 0 i e the 16 bit transfers are word aligned Because of t
218. DR 27 24 increments or decrements if the memory address crosses the 16 Mbyte boundary In normal mode these bits remain constant during the DMA transfer Enhanced mode is enabled by setting the ENH_MODE_ENB bit in the GPDMACTL register see page 11 4 11 14 Elan SC520 Microcontroller Register Set Manual GP DMA Controller Registers AMDA GP DMA Channel 6 Extended Page GPDMAEXTPG6 Memory Mapped MMCR Offset D8Bh 7 6 5 4 3 2 1 0 Bit Reserved DMA6ADR 27 24 Reset 0 0 0 0 0 0 0 0 R W RSV R W Register Description This register provides the extended page address for Channel 6 Bit Definitions Bit Name Function 7 4 Reserved Reserved This bit field should be written to 0 for normal system operation 3 0 DMA6ADR DMA Channel 6 Extended Page Address 27 24 This bit field specifies the highest four memory address bits A27 A24 for Channel 6 Programming Notes The extended page address is used in conjunction with the memory address and the page address registers for the associated channel to make up a 28 bit address A27 A0 In enhanced mode the Channel 6 extended page address bit field DMA6ADR 27 24 increments or decrements if the memory address crosses the 16 Mbyte boundary In normal mode these bits remain constant during the DMA transfer Enhanced mode is enabled by setting the ENH MODE ENB bit in the GPDMACTL register see page 11 4 lan SC520 Microcontroller
219. EQ page 11 89 Master DMA Channel 4 7 Mask MSTDMAMSK page 11 90 Master DMA Channel 4 7 Mode MSTDMAMODE page 11 91 Master DMA Clear Byte Pointer MSTDMACBP page 11 93 Master DMA Controller Reset MSTDMARST page 11 94 Master DMA Controller Temporary MSTDMATMP page 11 95 Master DMA Mask Reset MSTDMAMSKRST page 11 96 Master DMA General Mask Elan SC520 Microcontroller Register Set Manual MSTDMAGENMSK page 11 97 AMD GP DMA Controller Registers GP DMA Control GPDMACTL Memory Mapped MMCR Offset D80h 7 6 5 4 3 2 1 0 CH7 ALT CH6 ALT 5 ALT CH3 ALT Bit SIZE SIZE SIZE SIZE CLK_MODE Reserved MODE ENB Reset 0 0 0 0 0 0 0 0 R W R W R W R W R W R W RSV R W Register Description This register provides control for the enhanced mode and selects the clock frequency Bit Definitions Bit Name 7 CH7_ALT_SIZE 6 CH6_ALT_SIZE 5 CH5_ALT_SIZE 4 CH3_ALT_SIZE 3 2 CLK_MODE 1 Reserved 0 ENH _ Programming Notes 11 4 Function Alternate Size for Channel 7 0 Channel 7 is 16 bits wide 1 Channel 7 is 8 bits wide This bit field is ignored if the ENH_MODE_ENB bit is 0 Alternate Size for Channel 6 0 Channel 6 is 16 bits wide 1 Channel 6 is 8 bits wide This bit field is ignored if the ENH_MODE_ENB bit is 0 Alternate Size for Channel 5 0 Channel 5 i
220. ER_ IRQ_ENB Function Reserved This bit field should be written to 0 for normal system operation Target Delayed Transaction Time Out Interrupt Select This bit allows delayed transaction time outs to generate an NMI instead of a maskable interrupt 0 Delayed transaction time outs generate a maskable interrupt 1 Delayed transaction time outs generate an NMI Target Address Parity Interrupt Select This bit allows address parity errors detected by the target controller to generate an NMI instead of a maskable interrupt 0 Address parity errors generate a maskable interrupt 1 Address parity errors generate an NMI Target Data Parity Interrupt Select This bit allows data parity errors detected by the target controller to generate an NMI instead of a maskable interrupt 0 Data parity errors generate a maskable interrupt 1 Data parity errors generate an NMI Reserved This bit field should be written to 0 for normal system operation Target Delayed Transaction Time Out Interrupt Enable This bit allows delayed transaction time outs to generate an interrupt 0 Delayed transaction time outs do not generate an interrupt 1 Delayed transaction time outs generate an interrupt Target Address Parity Interrupt Enable This bit allows address parity errors detected by the target controller to generate an interrupt 0 Address parity errors do not generate an interrupt 1 Address parity errors generate an interrupt E
221. Enable received data available interrupt in 16450 compatible mode in 16550 compatible mode this bit also enables FIFO trigger level reached interrupt and time out interrupt More detail on time out interrupts can be found in the UARTXINTID register description page 18 12 Programming Notes Table 18 5 on page 18 14 provides a summary of UART interrupt sources When the DLAB bit is 0 in the UARTxLCR register see page 18 17 reads from and writes to this address access the UART x Interrupt Enable UARTXINTENB register When the DLAB bit is 1 in the UARTXxLCR register reads from and writes to this address access the UART x Baud Clock Divisor Latch MSB UARTxBCDH register see page 18 10 Elan SC520 Microcontroller Register Set Manual 18 11 UART Serial Port Registers Direct Mapped UART 2 Interrupt ID UART2INTID Address 2 UART 1 Interrupt ID UART1INTID Address O3FAh 7 6 5 4 3 2 1 0 Bit FIFO_MODE 1 0 Reserved INT_ID 2 0 ae Reset 0 0 0 0 0 0 0 1 R W R R RSV R R R R Register Description This read only register is used to identify UART interrupts and the current FIFO mode Writes to this address access the UART x FIFO Control UARTxFCR register see page 18 15 Bit Definitions Bit Name Function 7 6 FIFO_MODE FIFO Mode Indication 1 0 FIFO is only present when 16550 compatible mode is enabled 00 2 16450 compatible mode is enabled 01 No significance
222. FF COCh page 10 11 GP Write Pulse Width GPWRW CODh page 10 12 GP Write Offset GPWROFF COEh page 10 13 GPALE Pulse Width GPALEW COFh page 10 14 GPALE Offset GPALEOFF C10h Elan SC520 Microcontroller Register Set Manual page 10 15 1 3 AMD Table 1 1 Register Name Programmable Input Output Configuration Register Overview Mnemonic MMCR Offset C20 C3Ah Memory Mapped Configuration Region MMCR Registers By Offset Continued Page Number PIO15 PIOO Pin Function Select PIOPFS15 0 C20h page 20 3 PIO31 PIO16 Pin Function Select PIOPFSS1 16 C22h page 20 5 Chip Select Pin Function Select CSPFS C24h page 20 7 Clock Select CLKSEL C26h page 20 9 Drive Strength Control DSCTL C28h page 20 10 PIO15 PIOO Direction PIODIR15 0 C2Ah page 20 12 PIOS31 PIO16 Direction PIODIRS31 16 C2Ch page 20 14 PIO15 PIOO Data PIODATA15 0 C30h page 20 16 PIO31 PIO16 Data PIODATA31_16 C32h page 20 18 PIO15 PIOO Set PIOSET15 0 C34h page 20 20 PIO31 PIO16 Set PIOSETS31 16 C36h page 20 22 PIO15 PIOO Clear PIOCLR15 0 C38h page 20 24 PIO31 PIO16 Clear Software Timer PIOCLR31 16 C3Ah C60 C62h page 20 26 Software Timer Millisecond Count SWTMRMILLI C60h page 15 2 Software Timer Microsecond Count
223. Function Offset Time for GPALE This field adjusts the offset time of the GPALE signal The resolution of this parameter is one internal 33 MHz clock period The offset time used is GP ALE OFF 1 internal clock periods i e if GP ALE OFF is 0 the offset time is one clock period Figure 10 1 on page 10 7 shows the relationships between the various adjustable GP bus timing parameters Elan SC520 Microcontroller Register Set Manual 10 15 General Purpose Bus Controller Registers 10 16 Elan SC520 Microcontroller Register Set Manual 098 AMD 1 11 11 1 11 2 Table 11 1 GP DMA CONTROLLER REGISTERS OVERVIEW This chapter describes the general purpose bus direct memory access GP bus DMA registers of the ElanSC520 microcontroller The lanSC520 microcontrollers GP DMA controller consists of two cascaded DMA controller devices that provide a total of seven independent channels Channels 0 3 are on the slave controller device and Channels 5 7 are on the master controller device Channel 4 is used for cascading the two devices The GP bus DMA register set includes two groups of registers il 35 memory mapped configuration region MMCR registers are used to specify the extended page address and the operation of each channel in the enhanced mode 52 direct mapped I O registers are used to configure the operation of each DMA controller device master and slave within the DMA controll
224. GPDMASTC register 11 81 in GPDMA6TC register 11 83 in GPDMATTC register 11 85 DMA Channel x Transfer Count Extension bit field in GPDMAEXTTCS register 11 17 in GPDMAEXTTCS5 register 11 18 in register 11 19 in GPDMAEXTTCT7 register 11 20 DMA Mode bit field UARTXFCR register 18 15 in UARTxFCRSHAD register 18 5 DMA_DIS bit field in MSTDMACTL register 11 87 in SLDMACTL register 11 51 DMA_MODE bit field UARTXFCR register 18 15 in UARTxFCRSHAD register 18 5 DMABCINTMAP register 12 21 DMARXx bit field in MSTDMASTA register 11 86 in SLDMASTA register 11 50 DMAx MMAP bit field in GPDMAMMIO register 11 5 DMAx NXT ADR bit field in GPDMANXTADDHS register 11 27 in GPDMANXTADDHB register 11 29 in GPDMANXTADDH6 register 11 31 in GPDMANXTADDHT register 11 33 in GPDMANXTADDLS register 11 26 in GPDMANXTADDLS register 11 28 in GPDMANXTADDLE register 11 30 in GPDMANXTADDL7 register 11 32 Index DMAx NXT TC bit field in GPDMANXTTCHG register 11 35 in GPDMANXTTCH5 register 11 37 in GPDMANXTTCH6 register 11 39 in GPDMANXTTCH7 register 11 41 in GPDMANXTTCL3 register 11 34 in GPDMANXTTCLS register 11 36 in GPDMANXTTCLS6 register 11 38 in GPDMANXTTCL7 register 11 40 DMAxADR bit field in GPDMAEXTPGO register 11 10 in GPDMAEXTPG1 register 11 11 in GPDMAEXTPG2 register 11 12 in GPDMAEXTPG3 register 11 13 in GPDMAEXTPG5 register 11 14 in GPDMAEXTPG6 r
225. HBTGTIRQCTL register see page 6 5 or the Parity Error Response bit PERR RES in the PCISTACMD register see page 6 21 Target Data Parity Interrupt Status This bit is set when the target controller detects a data parity error 0 Data parity error has not occurred 1 Data parity error has occurred This bit is cleared by writing a 1 This bit operates regardless of the corresponding interrupt enable bit T in the HBTGTIRQCTL register see page 6 6 or the Parity Error Response bit PERR RES the PCISTACMD register see page 6 21 This register is reset by a system reset The bits in this register are not affected by a PCI bus reset A PCI bus reset is initiated by setting the PCI RST bit in the HBCTL register see page 6 3 6 8 Elan SC520 Microcontroller Register Set Manual Host Bridge Master Interrupt Control HBMSTIRQCTL AMD PCI Bus Host Bridge Registers Memory Mapped MMCR Offset 66h Bit Reset R W Bit Reset R W 15 14 13 12 11 10 9 8 M RTRTO M TABRT M MABRT M SERR M RPER M DPER SEEDS IRQ SEL IRQ SEL IRQ SEL IRQ SEL IRQ SEL IRQ SEL 0 0 0 0 0 0 0 0 RSV R W R W R W R W R W R W 7 6 5 4 3 2 1 0 M RTRTO M TABRT M MABRT M_SERR_ M_RPER_ M DPER IRQ IRQ_ENB IRQ IRQ ENB IRQ ENB IRQ 0 0 0 0 0 0 0 0 RSV R W R W R W R W R W R W Register Descriptio
226. I bus or GP bus DMA When enabled the write buffer merges or collapses write data during write cycles and merges read data during read cycles During SDRAM sizing or test the write buffer must be disabled to prevent an invalid SDRAM size indicator or false pass status during an SDRAM test algorithm A false pass is possible because the write buffer supports read merging so that previously written data is returned read merged from the write buffer if the read back occurs before the data has migrated to SDRAM This can appear as though SDRAM exists even though it might not If ECC memory is used the write buffer must also be disabled while the SDRAM initialization software initializes ECC memory by writing to each SDRAM location After the SDRAM sizing or test process is complete the user is free to enable the write buffer when desired Programming Notes Software must disable the write buffer i e clear the WB_ENB bit before changing the write buffer watermark WB WM bit field Elan SC520 Microcontroller Register Set Manual 8 3 AMDA Write Buffer and Read Buffer Register 8 4 Elan SC520 Microcontroller Register Set Manual ENS AMDA AMD 1 9 9 1 9 2 Table 9 1 ROM FLASH CONTROLLER REGISTERS OVERVIEW This chapter describes the read only memory ROM or Flash memory controller registers of the ElanSC520 microcontroller The ROM Flash controller supports up to three ROM device chip sel
227. I bus arbiter interrupts Note that the GNT TO STA bit of the PCIARBSTA register see page 5 3 is set on PCI bus arbiter grant time outs regardless of the GNT TO INT ENB bit value This interrupt source shares the interrupt controller input used by any host bridge interrupts enabled in the HBTGTIRQCTL and HBMSTIRQCTL registers see page 6 5 and page 6 9 Before the GNT TO INT bit is set the PCIHOSTMAP register see page 12 17 must be configured to route the interrupt to the appropriate interrupt request level and priority Programming Notes 5 2 Elan SC520 Microcontroller Register Set Manual System Arbitration Registers AMDA PCI Bus Arbiter Status PCIARBSTA Memory Mapped MMCR Offset 71h 7 6 5 4 3 2 1 0 GNT_TO_ Bit STA Reserved GNT TO ID 3 0 Reset 0 0 0 0 1 1 1 1 R W R W RSV R Register Description This register provides grant time out status of the PCI bus arbiter Bit Definitions Bit 7 GNT TO STA 6 4 Reserved 3 0 GNT TO ID 3 0 Programming Notes Function PCI Bus Arbiter Grant Time Out Status This bit is set when the PCI bus arbiter detects a grant time out transaction not started within 16 clocks of the PCI bus going idle The GNT that was asserted when this condition occurs can be read in the TO bit field 0 Grant time out has not occurred 1 Grant time out has occurred This bit TO STA is cleared by writ
228. INO signal or the GPCS5 signal available on the pin The default on reset is TMRINO 0 The pin is TMRINO 1 2 The pin is GPCS5 TMRIN1 or GPCS4 Function Select This bit is used to make either the TMRIN1 signal or the GPCSA signal available on the pin The default on reset is TMRIN1 0 The pin is TMRIN1 1 2 The pin is GPCS4 PITGATE2 or GPCS3 Function Select This bit is used to make either the PITGATE2 signal or the GPCS3 signal available on the pin The default on reset is PITGATE2 0 The pin is PITGATE2 1 The pin is GPCS3 ROMCS2 or GPCS2 Function Select This bit is used to make either the ROMCS2 signal or the GPCS2 signal available on the pin The default on reset is ROMCS2 0 The pin is ROMCS2 1 The pin is GPCS2 Elan SC520 Microcontroller Register Set Manual 20 7 AM DA Programmable Input Output Registers Bit Name Function 1 GPCS1_SEL ROMCS1 or GPCS1 Function Select This bit is used to make either the ROMCS1 signal or the GPCS1 signal available on the pin The default on reset is ROMCS1 0 The pin is ROMCS1 1 The pin is GPCS1 0 Reserved Reserved This bit field should be written to O for normal system operation Programming Notes The GPCSO signal is shared with the PIO27 signal on one pin so it is selected through the PIOPFS31_ 16 register see page 20 5 This register CSPFS should be written early in the microcontroller s initialization routine The bit values to writ
229. INT CHO INT MODE MODE MODE MODE MODE MODE MODE MODE 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W Register Description This register controls the individual Master PIC channel interrupt mode Bit Definitions Bit 1 12 6 Name INT MODE CH6 INT _ MODE CH5 INT _ MODE CH4 INT _ MODE INT _ MODE CH2_INT_ MODE CH1_INT_ MODE Function Master PIC Channel 7 Interrupt Mode 0 Edge sensitive interrupt request detection 1 Level sensitive interrupt request detection Master PIC Channel 6 Interrupt Mode 0 Edge sensitive interrupt request detection 1 Level sensitive interrupt request detection Master PIC Channel 5 Interrupt Mode 0 Edge sensitive interrupt request detection 1 Level sensitive interrupt request detection If the SNGL bit in the MPICICW1 register is set see page 12 26 and the M_GINT_MODE bit of the PICICR register is cleared see page 12 5 setting the CH5_INT_MODE bit causes interrupts to be recognized as level sensitive on channel 5 Clearing the CH5_INT_MODE bit under the same condition causes channel 5 interrupts to be recognized as edge sensitive However if both the SNGL bit and the M_GINT_MODE bit are cleared the CH5_INT_MODE bit value has no meaning because the channel is used for cascading with the Slave 2 controller Master PIC Channel 4 Interrupt Mode 0 Edge sensitive interrupt request detection 1 Level sensitive interrupt reques
230. IO28 pin 0 The pin is PIO28 1 The pin is CTS2 PIO27 or GPCSO Function Select This bit is used to select the functionality of the PIO27 pin 0 The pin is PIO27 1 The pin is GPCSO 26 or GPMEMCS16 Function Select This bit is used to select the functionality of the PIO26 pin 0 The pin is PIO26 1 The pin is GPMEMCS16 PIO25 or GPIOCS16 Function Select This bit is used to select the functionality of the PIO25 pin 0 The pin is PIO25 1 The pin is GPIOCS16 Elan SC520 Microcontroller Register Set Manual 20 5 AM DA Programmable Input Output Registers Bit Name Function 8 PIO24_FNC PIO24 or GPDBUFOE Function Select This bit is used to select the functionality of the PIO24 pin 0 The pin is PIO24 1 The pin is GPDBUFOE 7 PIO23 FNC PIO23 or GPIRQO Function Select This bit is used to select the functionality of the PIO23 pin 0 The pin is PIO23 1 2 The pin is GPIRQO 6 PIO22 PIO22 or GPIRQ1 Function Select This bit is used to select the functionality of the PIO22 pin 0 The pin is PIO22 1 The pin is GPIRQ1 5 PlO21 PIO21 or GPIRQ2 Function Select This bit is used to select the functionality of the PIO21 pin 0 The pin is PIO21 1 2 The pin is GPIRQ2 4 PIO20 FNC PIO20 or GPIRQ3 Function Select This bit is used to select the functionality of the PIO20 pin 0 The pin is PIO20 1 The pin is GPIRQ3 3 PIO19 FNC PIO19 or GPIRQ4 Function Select This bit is used to sele
231. L register 14 10 Index 7 AMD GP Timer x Maxcount Compare Register x bit field in GPTMROMAXCMPA register 14 7 in GPTMROMAXCMPPB register 14 8 in GPTMR1MAXCMPA register 14 13 in GPTMR1MAXCMPB register 14 14 in GPTMR2MAXCMPA register 14 18 GP Timer x Maximum Count bit field in GPTMROCTL register 14 4 in GPTMR1CTL register 14 10 in GPTMR2CTL register 14 16 GP Timer x Permit Enable Bit Write bit field in GPTMROCTL register 14 3 in GPTMR1CTL register 14 9 in GPTMR2CTL register 14 15 GP Timer x Prescaler bit field in GPTMROCTL register 14 5 in GPTMR1CTL register 14 11 GP Timer x Retrigger bit field in GPTMROCTL register 14 4 in GPTMR1CTL register 14 10 GP Timers Status register 14 2 GP Write Offset register 10 13 GP Write Pulse Width register 10 12 GP ALE OFF bit field 10 15 GP ALE WIDTH bit field 10 14 GP ECHO bit field 10 2 GP RD OFF bit field 10 1 1 GP RD WIDTH bit field 10 10 GP RST bit field 3 3 GP WR OFF bit field 10 13 GP WR WIDTH bit field 10 12 GPAEN Function Select bit field 20 4 GPALE signal Function Select bit field 20 4 in GPALEOFF register 10 15 in GPALEW register 10 14 minimum timing table 10 2 Offset register 10 15 Pulse Width register 10 14 GPALEOFF register 10 15 GPALEW register 10 14 GPBHE Function Select bit field 20 4 GPBHE signal 20 4 GPCS OFF bit field 10 9 RECOWVR bit field 10 7 WIDTH bit field 10 8 GPCSDW register 10 3
232. LDMASTA register 11 50 Chip Select Pin Function Select register 20 7 Chip Select Recovery Time bit field 10 7 Chip Select x Device Delay for First Access bit field in ROMCS1CTL register 9 5 in ROMCS2CTL register 9 7 Delay for Subsequent Accesses bit field in ROMCS1CTL register 9 4 in ROMCS2CTL register 9 6 Mode bit field in ROMCS1CTL register 9 4 in ROMCS2CTL register 9 6 SDRAM GP Bus Select bit field in ROMCS1CTL register 9 4 in ROMCS2CTL register 9 6 Width Select bit field in ROMCS1CTL register 9 4 in ROMCS2CTL register 9 6 Elan SC520 Microcontroller Register Set Manual CHMASK bit field in MSTDMAMSK register 11 90 in SLDMAMSK register 11 54 CHx_ALT_SIZE bit field in GPDMACTL register 11 4 CHx_BCHN_ENB bit field 11 21 CHx_CBUF_VAL bit field 11 25 CHx_CNT bit field in PITOCNT register 13 2 in PIT1ONT register 13 3 in PIT2CNT register 13 4 CHx_DIS bit field in MSTDMAGENMSK register 11 97 in SLDMAGENMSK register 11 61 CHx EOB STA bit field 11 22 11 23 CHx INT ENB bit field 11 24 CHx INT MODE bit field in MPICMODE register 12 6 12 7 SL1PICMODE register 12 8 in SL2PICMODE register 12 9 CL CD bit field 6 22 Class Code Revision ID register 6 22 Clear FPU Error Interrupt Request bit field 12 61 Clear To Send bit field 18 23 CLK INV ENB bit field 19 3 CLK MODE bit field 11 4 CLK PIN DIR bit field 20 9 CLK PIN ENB bit field 20 9 CLK SEL bit field 19 2 CLK SRC bit field 18 3
233. MD home page at www amd com and follow the Embedded Processors link These pages provide information on upcoming product releases overviews of existing products information on product support and tools anda list of technical documentation Support tools include online benchmarking tools and CodekKit software tested source code example applications Many of the technical documents are available online in PDF form Questions requests and input concerning AMD s WWW pages can be sent via e mail to web feedback amd com Documentation and Literature Support Data books user s manuals data sheets application notes and product CDs are free with asimple phone call Internationally contact your local AMD sales office for product literature To order literature to www amd com support literature html or in the U S and Canada call 800 222 9323 Third Party Support AMD FusionE86 partners provide an array of products designed to meet critical time to market needs Products and solutions available include emulators hardware and software debuggers board level products and software development tools among others The WWW site and the E86 Family Products Development Tools CD order 21058 describe these solutions In addition mature development tools and applications for the x86 platform are widely available in the general marketplace Elan SC520 Microcontroller Register Set Manual iii AMD iv Elan SC520 Microcontro
234. MRCTL register for a single write m The key sequence of AAAAh followed by 5555h is called the clear count key and is used to clear the current watchdog timer counter Note All keys are written to the WOTMRCTL register address MMCR offset CBOh Normally this register is read only The write key sequence must be written before a value can be programmed into this register after this single value is written the write key sequence must be applied again before another value can be programmed The ENB bit must be 0 before the WRST_ENB bit or the EXP_SEL bit field can be written When the microcontroller is in AMDebug technology mode the WDTMRCTL register can still be accessed in the normal manner However the AMDebug technology stops the count registers from incrementing further to prevent the watchdog timer from causing an interrupt or reset in AMDebug technology mode Elan SC520 Microcontroller Register Set Manual 16 3 Watchdog Timer Registers Watchdog Timer Count Low WDTMRCNTL Memory Mapped MMCR Offset CB2h 15 14 13 12 11 10 9 8 Bit COUNTL 15 8 Reset 0 0 0 0 0 0 0 0 R W R 7 6 5 4 3 2 1 0 Bit COUNTL 7 0 Reset 0 0 0 0 0 0 0 0 R W R Register Description This read only register contains the lower 16 bits of the watchdog timer counter In normal operation the clear count key sequence AAAAh followed by 5555h clears the watchdog timer counte
235. MRD and GPM GPCS6 Qualifier Selection This field is used to qualify the GP bus chip select 6 with GPIORD GPIOWR GPMEMRD or GPMEMWR 00 No qualification Qualify the chip select with write strobes GPIOWR or GPMEMWR 10 Qualify the chip select with read strobes GPIORD or GPMEMRD 11 Qualify t ine nip select with both strobes GPIORD and GPIOWR or GPMEMRD and GPMEMWR GPCS5 Qualifier Selection This field is used to qualify the GP bus chip select 5 with GPIORD GPIOWR GPMEMRD or GPMEMWR 00 No qualification Qualify the chip select with write strobes GPIOWR or GPMEMWR 10 Qualify the chip select with read strobes GPIORD or GPMEMRD 11 Qualify t the Wi P select with both strobes GPIORD and GPIOWR or GPMEMRD and GPM Elan SC520 Microcontroller Register Set Manual 10 5 General Purpose Bus Controller Registers Bit Name Function 9 8 GPCS4_RW GPCS4 Qualifier Selection 1 0 This field is used to qualify the GP bus chip select 4 with GPIORD GPIOWR GPMEMRD or GPMEMWR 00 ee qualification Qualify the chip select with write strobes GPIOWR or GPMEMWR 10 Qualify the chip select with read strobes GPIORD or GPMEMRD 11 Qualify the chip select with both strobes GPIORD and GPIOWR or GPMEMRD and GPMEMWR 7 6 GPCS3 RW GPCS3 Qualifier Selection 1 0 This field is used to qualify the GP bus chip select 3 with GPIORD GPIOWR GPMEMRD or PMEMWR
236. MROCTL register bits INT_ENB MAX_CNT_RIU MAX_CNT ALT_CMP and CONT_CMP starting on page 14 4 If the maxcount compare register that is in use contains a value other than 0000h and the timer is enabled the timer counts to the programmed maxcount value 14 8 Elan SC520 Microcontroller Register Set Manual GP Timer 1 Mode Control GPTMR1CTL Register Description AMD General Purpose Timer Registers Memory Mapped MMCR Offset C7Ah 15 14 13 12 11 10 9 8 Bit ENB P ENB WR INT Reserved Reset 0 0 0 0 0 0 0 0 R W R W R W R RSV 7 6 5 4 3 2 1 0 CONT_ Bit Reserved MAX_CNT RTG PSC SEL EXT CLK ALT CMP CMP Reset 0 0 0 0 0 0 0 0 R W RSV R W R W R W R W R W R W This register is used to control the functionality and modes of operation of GP Timer 1 Bit Definitions Bit 15 14 Name ENB P_ENB_WR Elan SC520 Microcontroller Register Set Manual Function GP Timer 1 Enable 0 GP Timer 1 is inhibited from counting 1 GP Timer 1 counting is enabled If GP Timer 1 was previously enabled via setting the ENB bit and is operating and then software clears the ENB bit by writing a 0 then GP Timer 1 is inhibited from counting but is not reset The various timer status bits and the TMROUT1 output pin also remain stable In this scenario setting this ENB bit again causes the timer to continue from the state that it was in just prior to being
237. MSTDMACTL 11 87 Master Software DRQ n Request MSTDMASWREQ 11 89 Master DMA Channel 4 7 Mask MSTDMAMSK 11 90 Master DMA Channel 4 7 Mode MSTDMAMODE 11 91 Master DMA Clear Byte Pointer 11 93 Master DMA Controller Reset MSTDMARST 11 94 Master DMA Controller Temporary 11 95 Master DMA Mask Reset 5 5 5 11 96 Master DMA General Mask 11 97 CHAPTER 12 PROGRAMMABLE INTERRUPT CONTROLLER REGISTERS 12 1 12 T OVervIe WW uique xd wud BA awed amend 12 1 12 2 Heglstets eus Or Gee them Goats a CER DEPT ds 12 1 Interrupt Control 1 12 4 Master PIC Interrupt Mode 12 6 Slave 1 PIC Interrupt Mode 1 12 8 Slave 2 PIC Interrupt Mode 2 12 9 Software Interrupt 16 1 Control SWINT16 1 12 10 Software Interrupt 22 17 NMI Control SWINT22 17 12 13 Interrupt Pin Polarity 1 12 15 PCI Host Bridge Interrupt Mapping PCIHOSTMAP 12 17 ECC Interrupt Mapping 12 19 Elan SC520 Microcontroller Register
238. OCEh 7 6 5 4 3 2 1 0 Bit DMA7TC 15 0 Reset X X X X X X X X R W Register Description This register contains bits 15 0 of the transfer count for Channel 7 during DMA operation Bit Definitions Bit Name Function 7 0 DMA7TC DMA Channel 7 Transfer Count 16 Bit Register 15 0 This 8 bit field is used two successive I O accesses to read or write the channel s transfer count bits 15 0 Bits 7 0 of the channel s transfer count can be read from or written to this bit field immediately after a write to the MSTDMACBP register see page 11 93 Bits 15 8 of the channel s transfer count can be read from or written to this bit field immediately after transfer count bits 7 0 are read from or written to this bit field The actual number of transfers is one more than the programmed transfer count value Programming Notes To ensure that the lower byte of this register GPDMA7TO is always accessed first software should precede any access to this register with a write to the MSTDMACBP register see page 11 93 to clear the master DMA byte pointer By default this channel is set up for PC AT compatibility 16 bit DMA transfers on the master DMA controller For 16 bit transfers each transfer is two bytes so a transfer count of FFFFh results in a transfer of 128 Kbytes The value in this register GPDMA7TC can be used with the value in the GPDMAEXTTCT7 register see page 11 20 to
239. P page 12 21 GPIRQ3 Interrupt Mapping GP3IMAP page 12 21 GPIRQ4 Interrupt Mapping GP4IMAP page 12 21 GPIRQ5 Interrupt Mapping GP5IMAP page 12 21 GPIRQ6 Interrupt Mapping GP6IMAP page 12 21 GPIRQ7 Interrupt Mapping GP7IMAP page 12 21 GPIRQ8 Interrupt Mapping GP8IMAP page 12 21 GPIRQO Interrupt Mapping GP9IMAP page 12 21 GPIRQ10 Interrupt Mapping Reset Generation GP10IMAP D70 D74h page 12 21 System Board Information SYSINFO D70h Reset Configuration RESCFG D72h Reset Status GP DMA Controller RESSTA D74h D80 DBEh GP DMA Control GPDMACTL D80h page 11 4 GP DMA Memory Mapped I O GPDMAMMIO D81h page 11 5 GP DMA Resource Channel Map A GPDMAEXTCHMAPA D82h page 11 6 GP DMA Resource Channel Map B GPDMAEXTCHMAPB D84h page 11 8 GP DMA Channel 0 Extended Page GPDMAEXTPGO D86h page 11 10 GP DMA Channel 1 Extended Page GPDMAEXTPG 1 D87h page 11 11 GP DMA Channel 2 Extended Page GPDMAEXTPG2 D88h page 11 12 GP DMA Channel 3 Extended Page GPDMAEXTPG3 D89h page 11 13 GP DMA Channel 5 Extended Page GPDMAEXTPG5 D8Ah page 11 14 GP DMA Channel 6 Extended Page GPDMAEXTPG6 D8Bh page 11 15 GP DMA Channel 7 Extended Page GPDMAEXTPG7 D8Ch page 11 16 GP DMA Channel 3 Extended Transfer Count GPDMAE
240. P Timer 2 has not caused an interrupt or software cleared this bit by writing 1 1 GP Timer 2 has caused an interrupt This bit is set when the GP Timer 2 interrupt request is asserted The interrupt request remains asserted until this status bit is cleared Software must write a 1 to clear this bit GP Timer 1 Interrupt Status 0 GP Timer 1 has not caused an interrupt or software cleared this bit by writing 1 1 GP Timer 1 has caused an interrupt This bit is set when the GP Timer 1 interrupt request is asserted The interrupt request remains asserted until this status bit is cleared Software must write a 1 to clear this bit GP Timer 0 Interrupt Status 0 GP Timer 0 has not caused an interrupt or software cleared this bit by writing 1 1 GP Timer 0 has caused an interrupt This bit is set when the GP Timer 0 interrupt request is asserted The interrupt request remains asserted until this status bit is cleared Software must write a 1 to clear this bit Elan SC520 Microcontroller Register Set Manual GP Timer 0 Mode Control GPTMROCTL Register Description AMD General Purpose Timer Registers Memory Mapped MMCR Offset C72h 15 14 13 12 11 10 9 8 Bit ENB P ENB WR INT Reserved Reset 0 0 0 0 0 0 0 0 R W R W R W R RSV 7 6 5 4 3 2 1 0 CONT_ Bit Reserved MAX_CNT RTG PSC_SEL EXT_CLK ALT_CMP CMP Reset 0 0 0 0 0 0 0 0 R W RSV R W R W R W R W R W R W
241. P bus DMA demand or block mode transfers Very large transfers could cause the PCI Host Bridge target controller to violate the 10 us memory write maximum completion time limit set in the PCI Local Bus Specification Revision 2 2 11 38 Elan SC520 Microcontroller Register Set Manual GP DMA Controller Registers AMDA GP DMA Channel 6 Next Transfer Count High GPDMANXTTCH6 Memory Mapped MMCR Offset DBAh 7 6 5 4 3 2 1 0 Bit DMA6_NXT_TC 23 16 Reset 0 0 0 0 0 0 0 0 R W R W Register Description This register provides bits 23 16 of the next transfer count for Channel 6 in buffer chaining mode Bit Definitions Bit Name Function 7 0 DMA6_NXT_ DMA Channel 6 Next Transfer Count High TC 23 16 This bit field provides bits 23 16 of the next transfer count to be used by Channel 6 in the buffer chaining mode Programming Notes The value of this register is ignored if buffer chaining mode is not enabled for this channel in the GPDMABCCTL register see page 11 21 In PCI bus 2 2 compliant designs software must limit the length of GP bus DMA demand or block mode transfers Very large transfers could cause the PCI Host Bridge target controller to violate the 10 us memory write maximum completion time limit set in the PCI Local Bus Specification Revision 2 2 lan SC520 Microcontroller Register Set Manual 11 39 AMDA GP DMA Controller Registers GP DMA Channel 7 Next Transfer Count Low
242. PAR15 31 30 29 28 27 26 AMD Memory Mapped MMCR Offset 88h MMCR Offset 8Ch MMCR Offset 90h MMCR Offset 94h MMCR Offset 98h MMCR Offset 9Ch MMCR Offset AOh MMCR Offset A4h MMCR Offset A8h MMCR Offset ACh MMCR Offset BOh MMCR Offset B4h MMCR Offset B8h MMCR Offset BCh MMCR Offset COh MMCR Offset C4h 25 24 Bit 2 0 ATTR 2 0 PG SZ Se SAD R 24 Reset 0 0 0 0 0 0 0 0 R W R W R W R W R W 23 22 21 20 19 18 17 16 Bit SZ ST ADR 23 16 Reset 0 0 0 0 0 0 0 R W R W 15 14 13 12 11 10 9 8 Bit SZ ST ADR 15 8 Reset 0 0 0 0 0 0 0 0 R W R W 7 6 5 4 3 2 1 0 Bit SZ_ST_ADR 7 0 Reset 0 0 0 0 0 0 0 0 R W R W Elan SC520 Microcontroller Register Set Manual 2 5 AMD Register Description System Address Mapping Registers These registers can be used to map windows of memory address space to SDRAM ROM PCI bus or GP bus or to map windows of I O space to the GP bus These registers are also used to apply noncacheability write protect and nonexecutable attributes to SDRAM and ROM regions Bit Definitions Bit Name 31 29 TARGET 2 0 Function Target of the PARx Window This bit field defines the target destination of the PARx window being configured If no PARx window is enabled i e the TARGET bit field is 000b in all PARx registers the
243. PCI Local Bus Specification Revision 2 2 lan SC520 Microcontroller Register Set Manual 11 49 AMD Slave DMA Channel 0 3 Status SLDMASTA GP DMA Controller Registers Direct Mapped Address 0008h 7 6 5 4 3 2 1 0 Bit DMAR3 DMAR2 DMAR1 DMARO TC3 TC2 TC1 TCO Reset 0 0 0 0 R W R R R R R R R R Register Description This register indicates the request status and terminal count status for Channels 0 3 Bit Definitions Bit Name DMAR3 DMAR2 DMAR1 DMARO TC2 TC1 TCO Programming Notes Bits 3 0 of this register are reset when read Any read from this register SLDMASTA clears bits 3 0 11 50 Function Channel 3 DMA Request 0 Channel 3 DMA request not pending 1 Channel 3 DMA request pending Channel 2 DMA Request 0 Channel 2 DMA request not pending 1 Channel 2 DMA request pending Channel 1 DMA Request 0 Channel 1 DMA request not pending 1 Channel 1 DMA request pending Channel 0 DMA Request 0 Channel 0 DMA request not pending 1 2 Channel 0 DMA request pending Channel 3 Terminal Count 0 Channel 3 terminal count not detected 1 Channel 3 terminal count detected Channel 2 Terminal Count 0 Channel 2 terminal count not detected 1 Channel 2 terminal count detected Channel 1 Terminal Count 0 Channel 1 terminal count not detected 1 Channel 1 terminal count detected Channel 0 Terminal C
244. PIC Operation Control Word 2 S1PICOCW2 Direct Mapped Address 00AOh 7 6 5 4 3 2 1 0 SLCT_ Bit R SL 1 0 IW IS OCW3 LS 2 0 Reset X X X X X X X X R W W Register Description This register provides control for various interrupt priority and end of interrupt EOI modes It also controls write access for this register S1PICOCW2 and for the S1PICOCW3 and S1PICICW1 registers see page 12 55 and page 12 51 Bit Definitions Bit Name 7 5 R_SL_EOI 1 0 4 SLCT_ICW1 3 IS OCWS Function Interrupt Request EOI and Priority Rotation Controls 000 Rotate in auto EOI mode clear 001 Nonspecific EOI 010 No operation 011 Specific EOI 100 Rotate in auto EOI mode set 101 Rotate on nonspecific EOI command 110 Set priority command 111 Rotate on specific EOI command Initialization Control Word 1 Select Software must clear this bit to 0 when writing this address Port OOAOh to access either this register S1PICOCW2 or the S1PICOCWS register 0 The write accesses either this register S1PICOCW2 or the S1PICOCWS register see page 12 55 depending on the state of bit 3 1 The write accesses the S1PICICW1 register see page 12 51 Access is OCW3 Software must clear this bit IS_OCW3 and clear SLCT_ICW1 when writing this address Port OOAOh to access this register S1PICOCW2 0 The write accesses this register S1PICOCW2 if the SLCT
245. PIC global interrupt mode disabled 1 Master PIC global interrupt mode enabled If the M GINT MODE bit is set bit LTIM of the MPICICW1 register see page 12 26 determines the interrupt mode for the Master PIC channels If the M GINT MODE bit and the LTIM bit are set all the Master PIC interrupt channels recognize level sensitive interrupt requests If the M GINT MODE bit is set and the LTIM bit is cleared all the Master PIC interrupt channels recognize edge sensitive interrupt requests If the M GINT MODE bit is cleared the Master bit has no meaning and the Master PIC channels can be programmed individually via the MPICMODE register see page 12 6 to select either edge or level sensitive interrupt recognition For PC AT compatibility bits M GINT MODE and S1 GINT MODE in this register PICICR should be set and bit S2 should be set and bit S5 cleared in the MPICICWS register see page 12 34 In this configuration the Slave 2 controller is bypassed and any interrupt sources mapped to the Slave 2 controller have no effect also interrupt sources can be mapped directly to Master PIC interrupt channel 5 by mapping them to priority P13 Elan SC520 Microcontroller Register Set Manual 12 5 AMD Programmable Interrupt Controller Registers Master PIC Interrupt Mode MPICMODE Bit Reset R W Memory Mapped MMCR Offset DO2h 7 6 5 4 3 2 1 0 CH7 INT CH6 INT CH5 INT CH4_INT_ CH3_INT_ CH2 INT CH1
246. PICICWS register must always be programmed in this design because the SNGL bit in S2PICICW1 is internally fixed to 0 The S2PICICWA register is skipped if the IC4 bit in S2PICICW1 is 0 Elan SC520 Microcontroller Register Set Manual 12 45 AMD Programmable Interrupt Coniroller Registers Slave 2 PIC Initialization Control Word 3 S2PICICW3 Direct Mapped Address 0025h 7 6 5 4 3 2 1 0 Bit Reserved ID2 IDO Reset X X X X X 1 0 1 R W RSV W Register Description This register is the third initialization register of the Slave 2 controller Bit Definitions Bit Name Function 7 3 Reserved Reserved This bit field should be written to 0 for normal system operation This bit field is write only 2 0 ID2 IDO Slave 2 PIC ID 2 0 These bits contain the binary Slave 2 PIC ID 0006 1110 that the PIC responds to on the cascade bus In the lanSC520 microcontroller these bits are internally fixed to 101b Programming Notes The PIC s initialization control word S2PICICWX registers 1 4 must be programmed in sequence Writing to Port 0024h with bit 4 1 causes the S2PICICW1 register to be written and also resets the PIC s internal state machine and the internal S2PICICWx register pointer Then S2PICICWx registers 2 4 can be programmed by sequential writes to Port 0025h Each time Port 0025h is written to following the write to S2PICICW1 the internal register pointer points to the next
247. PIO1 DIR 0 DIR Programming Notes Programmable Input Output Registers Function 9 Input or Output Select This bit programs 9 as an input or output 0 Input 1 Output PIO8 Input or Output Select This bit programs PIO8 as an input or output 0 Input 1 Output PIO7 Input or Output Select This bit programs PIO7 as an input or output 0 Input 1 Output PIO6 Input or Output Select This bit programs PIO6 as an input or output 0 Input 1 Output PIO5 Input or Output Select This bit programs PIO5 as an input or output 0 Input 1 Output 4 Input or Output Select This bit programs PIO4 as an input or output 0 Input 1 Output PIO3 Input or Output Select This bit programs PIOS as an input or output 0 Input 1 Output PIO2 Input or Output Select This bit programs PIO2 as an input or output 0 Input 1 Output PIO1 Input or Output Select This bit programs PIO1 as an input or output 0 Input 1 Output PIOO Input or Output Select This bit programs PIOO as an input or output 0 Input 1 Output AMD The PIOx_DIR bit for each PIO pin chooses if the pin is an input or output After reset all of the PIO signals are inputs with pullup or pulldown termination Before any PIO can be used as an output this register PIODIR15 0 must be programmed to change the PIO from an input to an output The PIOx DIR bit for a pin has no effect if the corresp
248. PIODIR15 0 register 20 12 20 13 in PIODIR31 16 register 20 14 20 15 PIOx FNC bit field in PIOPFS15 0 register 20 3 20 4 in PIOPFS31 16 register 20 5 20 6 PIOx SET bit field in PIOSET15 0 register 20 20 20 21 in PIOSET31 16 register 20 22 20 23 PIT Channel x Count register Channel 0 13 2 Channel 1 13 3 Channel 2 13 4 PIT Counter Latch Command register 13 10 PIT counter mode settings table 13 9 PIT Counter Select bit field in PITCNTLAT bit field 13 10 in PITMODECTL bit field 13 7 in PITRDBACK bit field 13 11 PIT Mode Control register 13 7 PIT Output Channel 2 Enable bit field 13 13 PIT Read Back Command register 13 11 PIT Timer 2 Output Pin State bit field 13 13 PIT x Interrupt Mapping register Channel 0 12 21 Channel 1 12 21 Channel 2 12 21 PIT x Status register Channel 0 13 5 Channel 1 13 5 Channel 2 13 5 PIT GATE 2 bit field 13 13 Index AMD PIT OUT2 ENB bit field 13 13 PIT OUT2 STA bit field 13 13 PITOONT register 13 2 PITOMAP register 12 21 PITOSTA register 13 5 PIT1ONT register 13 3 PIT1MAP register 12 21 PIT1STA register 13 5 PIT2CNT register 13 4 PIT2MAP register 12 21 PIT2STA register 13 5 PITCNTLAT register 13 10 PITGATE2 Function Select bit field 20 7 PITGATE2 signal 13 9 13 13 20 7 PITMODECTL register 13 7 PITOUT2 signal 13 5 13 13 PITRDBACK register 13 11 PM bit field in MPICICW4 register 12 35 in S1PICICW4 register 12 59 in
249. PIOS is Low 1 PIO3 is High 2 PIO2 DATA Read or Write the PIO2 Pin 0 PIO2 is Low 1 PIO2 is High 1 PIO1 DATA Read or Write the PIO1 Pin 0 PIO1 is Low 1 2 PIO1 is High 0 PIOO DATA Read or Write the PIOO Pin 0 PIOO is Low 1 PIOO is High Programming Notes Each PIOx DATA bit is used to read or write the value of the corresponding pin If the pin is configured as a PIO output then writing to this register selects the output level of the pin Note that the output state of a pin programmed to be a PIO can also be controlled via the PIOSET15 0 and PIOCLR15 0 registers see page 20 20 and page 20 24 Reading a pin s PIOx DATA bit when the PIO is an output returns the state the pin was programmed for High or Low Reading a pin s PIOx DATA bit when the pin s interface function is selected via the corresponding PlOx FCN bit in the PIOPFS15 0 register see page 20 3 returns the state of the pin In other words reading a PIOx DATA bit returns the state of the corresponding PIO pin regardless of how the other PIO registers are programmed Although software can perform a 32 bit access of MMCR offset C30h to read or write all 32 PIO pins with a single instruction the 32 bit access is split into two separate 16 bit accesses with the PIODATA15 0 register being accessed prior to the PIODATA31_16 register The two accesses not simultaneous Elan SC520 Microcontroller Register Set Manual 20 17 AMD PIO31 PIO16 Data PIODATA
250. PU PRI bit field 5 6 CPU RST bit field in SCPDATA register 3 7 in SYSCTLA register 3 9 CPUCTL register 4 3 Crystal Frequency bit field 15 4 CSPFS register 20 7 CTR_CMD bit field 13 10 CTR_MODE bit field 13 8 CTR_MODE_STA bit field 13 6 CTR_RW_LATCH bit field 13 7 CTR_SEL bit field in PITMODECTL register 13 7 in PITRDBACK register 13 11 in PTCNTLAT register 13 10 CTS bit field 18 23 CTS2 Function Select bit field 20 5 CTSx signal in UARTxMCR register 18 19 18 20 in UARTxMSR register 18 23 18 24 lan SC520 Microcontroller Register Set Manual Index 3 AMD Current Count High bit field 16 5 Current Count Low bit field 16 4 D D PERR DET bit field 6 20 dackx internal signal 11 51 11 87 DAKSEN bit field in MSTDMACTL register 11 87 in SLDMACTL register 11 51 DAT IN bit field 19 7 DAT OUT bit field 19 4 Data Carrier Detect bit field 18 23 Data Parity Reported bit field 6 20 Data Ready bit field 18 22 Data Set Ready bit field 18 23 Data Terminal Ready bit field 18 20 Data Width Select for GPCSx bit field 10 3 DATA_DRIVE bit field 20 11 DATASTRB signal 7 2 Date Mode bit field 17 17 DATE_MODE bit field 17 17 DAY_OF_MTH bit field 17 11 DAY_OF_WEEK bit field 17 10 Daylight Savings Enable bit field 17 17 DBCTL register 8 2 DCD bit field 18 23 DCD2 Function Select bit field 20 5 DCDx signal 18 19 18 23 DCTS bit field 18 24 DDCD bit field 18 23 DDSR bit field 18 24 Delta Clea
251. Port 5 3 7 SCP Command Port SCPCMD 3 8 System Control Port A 3 9 Elan SC520 Microcontroller Register Set Manual V AMD Table of Contents CHAPTER4 5 86 CPU REGISTERS 4 1 4 1 OVetVIOW ec peek eue EO Romac eRe eet Be 4 1 4 2 Hegisters cesse eme oe eet grece s eed e e eoo Ee Ran d 4 1 Elan SC520 Microcontroller Revision ID 4 2 Am5 86 CPU Control 4 3 CHAPTER5 SYSTEM ARBITRATION REGISTERS 5 1 bil OVervieW mos e eg Se Eee vene 5 1 5 2 Hegisters sees x EE RREEXEC MENTO EY MAR NOD ME ES 5 1 System Arbiter Control SYSARBCTL 5 2 PCI Bus Arbiter Status 1 5 5 3 System Arbiter Master Enable 5 4 Arbiter Priority Control ARBPRICTL 5 6 CHAPTER6 PCI BUS HOST BRIDGE REGISTERS 6 1 6 1 Overview n i rn 6 1 6 2 Registers i cc RS Ep n sea ee TE RR EUER 6 1 Host Bridge Control 1 6 3 Host Bridge Target Interrupt Control HBTGTIRQCTL 6 5 Host Bridge Target Interrupt Status HBTGTIRQSTA 6 7 Host Bridge Master Interrupt Control HBMSTIRQCTL
252. Q ID bit field 6 7 T PURGE RD ENB bit field 6 3 T7 T3 bit field in MPICICW2 register 12 32 in S1PICICW2 register 12 57 in S2PICICW2 register 12 45 Target Address Parity Interrupt Enable bit field 6 5 Select bit field 6 5 Status bit field 6 8 TARGET bit field 2 6 Target Data Parity Interrupt Enable bit field 6 6 Select bit field 6 5 Status bit field 6 8 Target Delayed Transaction Time Out Interrupt Enable bit field 6 5 Select bit field 6 5 Status bit field 6 7 Target FIFO Purge Enable bit field 6 3 Target Interrupt Identification bit field 6 7 Target of the PARx Window bit field 2 6 TC INT bit field 19 6 TC INT ENB bit field 19 2 TCx bit field in MSTDMASTA register 11 86 in SLDMASTA register 11 50 technical support iii TEMT bit field 18 21 TERI bit field 18 23 TF_CLR bit field in UARTxFCR register 18 15 in UARTxFCRSHAD register 18 5 third party support iii THR bit field 18 7 THRE bit field 18 21 Timer 2 Gate Input Control bit field 13 13 Index 20 Elan SC520 Microcontroller Register Set Manual Index TMRINO signal Function Select bit field 20 7 in GPTMROCNT register 14 6 in GPTMROCTL register 14 4 14 5 TMRIN 1 signal Function Select bit field 20 7 in GPTMRICNT register 14 12 in GPTMR1CTL register 14 10 14 11 TMROUTO signal Function Select bit field 20 7 in GPTMROCTL register 14 3 14 5 TMROUT signal Function Select bit field 20 7 in GPTMR1CTL register 14 9 14
253. R Offset 64h 15 14 13 12 11 10 9 8 Bit Reserved T IRQ ID 3 0 Reset 0 0 0 0 1 1 1 1 R W RSV R 7 6 5 4 3 2 1 0 Bit R T DLYTO T APER T DPER IRQ_STA IRQ_STA IRQ_STA Reset 0 0 0 0 0 0 0 0 R W RSV R W R W R W This register contains the host bridge target interrupt status bits and active master identification Bit Definitions Bit 15 12 11 8 7 3 2 Name Reserved T IRQ ID 3 0 Reserved T DLYTO IRQ_STA Function Reserved This bit field should be written to 0 for normal system operation Target Interrupt Identification This bit field reports which PCI bus master was active when the target controller detected an error condition delay transaction time out address parity error data parity error This bit field is only valid when an interrupt status bit is set It is reset to 1111b when the interrupt status is cleared 0000 PCI bus master 0 was active when the error was detected 0001 PCI bus master 1 was active when the error was detected 0010 PCI bus master 2 was active when the error was detected 0011 PCI bus master 3 was active when the error was detected 0100 PCI bus master 4 was active when the error was detected 1111 No error was detected or the bus master value was not latched For example a bus master value is not latched if multiple interrupts are pending and one interrupt status was cle
254. R signal in GPCSQUAL register 10 5 10 6 in GPDMAMMIO register 11 5 in GPWROFF register 10 13 in GPWRW register 10 12 Write Selection Control bit field in MSTDMACTL register 11 87 in SLDMACTL register 11 51 GPIRQx signal Function Select bit field 20 3 20 6 in INTPINPOL register 12 15 12 16 Interrupt Mapping register 12 21 GPMEMCS16 Function Select bit field 20 5 GPMEMC amp x signal 10 4 Elan SC520 Microcontroller Register Set Manual AMD Index 9 AMD GPMEMRD signal Compressed Timing bit field in MSTDMACTL register 11 87 in SLDMACTL register 11 51 in GPCSQUAL register 10 5 10 6 in GPDMAMMIO register 11 5 in GPRDOFF register 10 1 1 in GPRDW register 10 10 GPMEMWR signal in GPCSQUAL register 10 5 10 6 in GPDMAMMIO register 11 5 in GPWROFF register 10 13 in GPWRW register 10 12 Write Selection Control bit field in MSTDMACTL register 11 87 in SLDMACTL register 11 51 GPRDOFF register 10 11 GPRDW register 10 10 GPRDY Function Select bit field 20 4 GPRESET signal reset sources 3 6 Software GP Bus Reset bit field 3 3 GPTC signal Function Select bit field 20 4 in GPDMABCVAL register 11 25 UARTXCTL register 18 3 in UARTXSTA register 18 4 GPTMROCNT register 14 6 GPTMROCTL register 14 3 GPTMROMAP register 12 21 GPTMROMAXCMPA register 14 7 GPTMROMAXCMPB register 14 8 GPTMRICNT register 14 12 GPTMRICTL register 14 9 GPTMR1MAP register 12 21 GPTMR1MAXCMPA register 14
255. RQ ID 23 16 Reset 0 0 0 0 0 0 0 0 R W R 15 14 13 12 11 10 9 8 Bit M AD IRQ ID 15 8 Reset 0 0 0 0 0 0 0 0 R W R 7 6 5 4 3 2 1 0 Bit M AD IRQ ID 7 0 Reset 0 0 0 0 0 0 0 0 R W R Register Description This bit field reports the address of the transaction during which the master controller detected an error condition Bit Definitions Bit Name 31 0 M AD IRQ ID 81 0 Programming Notes Function Master Address Interrupt Identification This bit field reports the address of the transaction during which the master controller detected an error condition If multiple errors are detected only the address of the first error is latched This bit field is only valid when an interrupt status bit is set It is cleared when any interrupt status bit is cleared A value of 00000000h means the address was not latched unless the error happened to occur at address 00000000h For example the address is not latched if multiple interrupts are pending and one interrupt status was cleared When multiple interrupts are pending there is no indication of which interrupt the address corresponds to The M_CMD_IRQ_ID bit field in the HBMSTIRQSTA register see page 6 12 contains the command of the transaction during which the master controller detected an error condition This register is reset by a system reset The bits in this register are not affected by a PCI bus reset A PCI bus reset is initiated by setting the PCI RST b
256. Receive command or Simultaneous Transmit Receive command that was issued via the SSICMD register see page 19 5 After writing a receive command software must wait until the receive transaction is complete before reading this bit field Transaction complete status is indicated by the BSY and TC INT bits in the SSISTA register see page 19 6 or by an interrupt if enabled via the TC INT ENB bit in the SSICTL register see page 19 2 Writes to this bit field IN have no effect This register should not be read while the BSY bit is set in the SSISTA register see page 19 6 Elan SC520 Microcontroller Register Set Manual 19 7 Synchronous Serial Interface Registers 19 8 Elan SC520 Microcontroller Register Set Manual CHAPTER eT AMD 1 2 20 1 20 2 Table 20 1 PROGRAMMABLE INPUT OUTPUT REGISTERS OVERVIEW This chapter describes the programmable input output PIO pins and other multiplexed or configurable pins of the ElanSC520 microcontroller The PIO register set consists of 13 memory mapped configuration region MMCR registers used to configure the programmable I O pins PIOS1 PIOO to enable interface functions for PIO pins and other multiplexed pins and to adjust the drive strength of SDRAM interface pins See the Elan SC520 Microcontroller User s Manual order 22004 for details about PIO pins Table 20 1 lists the PIO registers in offset order with the corresponding description s page
257. Register Set Manual 11 15 AMDA GP DMA Controller Registers GP DMA Channel 7 Extended Page GPDMAEXTPG7 Memory Mapped MMCR Offset D8Ch 7 6 5 4 3 2 1 0 Bit Reserved DMA7ADR 27 24 Reset 0 0 0 0 0 0 0 0 R W RSV R W Register Description This register provides the extended page address for Channel 7 Bit Definitions Bit Name Function 7 4 Reserved Reserved This bit field should be written to 0 for normal system operation 3 0 DMA7ADR DMA Channel 7 Extended Page Address 27 24 This bit field specifies the highest four memory address bits A27 A24 for Channel 7 Programming Notes The extended page address is used in conjunction with the memory address and the page address registers for the associated channel to make up a 28 bit address A27 A0 In enhanced mode the Channel 7 extended page address bit field DMA7ADR 27 24 increments or decrements if the memory address crosses the 16 Mbyte boundary In normal mode these bits remain constant during the DMA transfer Enhanced mode is enabled by setting the ENH MODE ENB bit in the GPDMACTL register see page 11 4 11 16 Elan SC520 Microcontroller Register Set Manual GP DMA Controller Registers AMDA GP DMA Channel 3 Extended Transfer Count GPDMAEXTTC3 Memory Mapped MMCR Offset D90h 7 6 5 4 3 2 1 0 Bit 23 16 Reset 0 0 0 0 0 0 0 0 R W RW Register Description
258. S2PICICW1 register see page 12 40 Ifthe IC4 bitis cleared the ElanSC520 microcontroller uses 01h for the value of this register S2PICICWA However if the S5 bit in the MPICICWS register is cleared see page 12 33 then the Slave 2 controller is bypassed and the value of this register S2PICICWA has no effect Elan SC520 Microcontroller Register Set Manual 12 47 AMD Slave 2 PIC Interrupt Mask S2PICINTMSK Programmable Interrupt Controller Registers Direct Mapped Address 0025h 7 6 5 4 3 2 1 0 Bit IM7 IM6 IM5 IM4 IM3 IM2 IM1 IMO Reset X X X X X x x x R W R W R W R W R W R W R W R W R W Register Description This register provides masking of individual interrupt requests for the Slave 2 controller This register is also known as Operation Control Word 1 in other PC AT compatible designs Bit Definitions Bit Name 7 IM7 6 IM6 5 IM5 4 IM4 3 IM3 2 IM2 1 IM1 0 IMO Programming Notes Function IR7 Mask 0 Unmask IR7 1 Mask IR7 IR6 Mask 0 Unmask IR6 1 Mask IR6 IR5 Mask 0 Unmask IR5 1 Mask IR5 IR4 Mask 0 Unmask IR4 1 Mask IR4 IR3 Mask 0 Unmask IR3 1 Mask IR3 IR2 Mask 0 Unmask IR2 1 Mask IR2 IR1 Mask 0 Unmask IR1 1 Mask IR1 IRO Mask 0 Unmask IRO 1 Mask IRO If the S5 bit in the MPICICWS register is cleared see page 12 33 then the Slave 2 controller is bypassed and the value of
259. S2PICICW4 register 12 47 PORTS80 bit field 11 62 PORT84 bit field 11 66 PORTS85 bit field 11 67 PORTS86 bit field 11 68 PORTS88 bit field 11 70 PORTSC bit field 11 74 PORTSD bit field 11 75 PORTSE bit field 11 76 PORTSF bit field 11 77 POWERGOOD Reset Detect bit field 3 6 PRG_IF bit field 6 22 PRG_RST_ENB bit field 3 3 PRGRESET Detect bit field 3 6 PRGRESET signal in RESCFG register 3 3 3 4 in RESSTA register 3 6 PRGRESET signal in RESSTA register 3 5 PRGRST_DET bit field 3 6 Priority Type bit field in MSTDMACTL register 11 87 in SLDMACTL register 11 51 PRITYPE bit field in MSTDMACTL register 11 87 in SLDMACTL register 11 51 Product Type of Elan SC520 Microcontroller bit field 4 2 PRODUCT_ID bit field 4 2 Program Interface bit field 6 22 Programmable Address Region x register 2 5 programmable I O MMCR registers table 20 1 lan SC520 Microcontroller Register Set Manual Index 15 AMD programmable interrupt controller direct mapped registers table 12 2 MMCR registers table 12 1 programmable interval timer direct mapped registers table 13 1 Programmable Reset Enable bit field 3 3 PSC SEL bit field in GPTMROCTL register 14 5 in GPTMR1CTL register 14 11 PWRGOOD signal in BOOTCSCTL register 9 2 in RESCFG register 3 4 in RESSTA register 3 6 in SYSINFO register 3 2 PWRGOOD DET bit field 3 6 R R bit in R SL EOI bit field 12 28 12 41 12 53 MST ABT bit fiel
260. S2PICICWx register S2PICICW1 and S2PICICW2 must always be programmed Also the S2PICICWS register must always be programmed in this design because the SNGL bit in S2PICICW1 is internally fixed to 0 The S2PICICWA register is skipped if the IC4 bit in S2PICICW1 is 0 If the S5 bitis set in the MPICICWS register see page 12 33 a write to this register S2PICICW3 is always expected in the ElanSC520 microcontroller because the SNGL bit is fixed to 0 in the S2PICICW1 register page 12 40 If the S5 bitis cleared the MPICICW3 register then the Slave 2 controller is bypassed and the value of this register S2PICICWS3 has no effect 12 46 Elan SC520 Microcontroller Register Set Manual Programmable Interrupt Coniroller Registers AMD Slave 2 PIC Initialization Control Word 4 S2PICICW4 Direct Mapped Address 0025h 7 6 5 4 3 2 1 0 Bit Reserved SFNM BUF_M S 1 0 Reset X X X X 0 0 0 1 R W RSV Register Description This register is the fourth initialization register of the Slave 2 controller Bit Definitions Bit Name Function 7 5 Reserved Reserved This bit field should be written to 0 for normal system operation This bit field is write only 4 SFNM Special Fully Nested Mode Enable 0 Normal nested mode 1 Special fully nested mode 3 2 BUF_M S 1 0 Buffered Mode and Master Slave Select 00 Non buffered mode 01 Non buffered mode 10 Buffered
261. S4 Interrupt Request 4 In Service 0 Interrupt request 4 is not being serviced 1 Interrupt request 4 is being serviced 3 IS3 Interrupt Request 3 In Service 0 Interrupt request 3 is not being serviced 1 Interrupt request 3 is being serviced 2 IS2 Interrupt Request 2 In Service 0 Interrupt request 2 is not being serviced 1 Interrupt request 2 is being serviced 1 151 Interrupt Request 1 In Service 0 Interrupt request 1 is not being serviced 1 Interrupt request 1 is being serviced 0 ISO Interrupt Request 0 In Service Programming Notes 0 Interrupt request 0 is not being serviced 1 2 Interrupt request 0 is being serviced This register MPICISR is accessed by first writing a value of OBh to Port 0020h followed by a read back from Port 0020h Because the Slave 1 PIC cascades into Channel 2 of the Master PIC the IS2 bit is asserted if any of the Slave 1 interrupt request levels is asserted Because the Slave 2 PIC cascades into Channel 5 of the Master the 155 bit is asserted if any of the Slave 2 interrupt request levels is asserted Elan SC520 Microcontroller Register Set Manual 12 25 AMD Master PIC Initialization Control Word 1 MPICICW1 Register Description Programmable Interrupt Controller Registers Direct Mapped Address 0020h 7 6 5 4 3 2 1 0 z SLCT_ Bit Reserved ICW1 LTIM ADI SNGL IC4 Reset x x x x x 1 x x R W RSV
262. SET Hard Soft Pin Internal Registers PWRGOOD pin PRGRESET pin SYS_RST bit RESCFG register see page 3 4 Watchdog timer reset event page 16 2 AMDebug technology system reset CPU_RST bit SYSCTLA register page 3 9 SCP soft reset SCPCMD register page 3 7 CPU shutdown typically caused by a triple fault GP_RST bit RESCFG register page 3 3 PCI_RST bit HBCTL register page 6 3 Notes 1 The PRG_RST_ENB bit must be set in the RESCFG register see page 3 3 to enable the reset function on this pin 2 If the PRG_RST_ENB bit is set the SDRAM controller configuration is maintained to support system reset in which SDRAM contents are also maintained 3 Any write of a 1 to the CPU_RST bit causes a soft reset regardless of whether the bit was previously 1 or 0 3 6 Elan SC520 Microcontroller Register Set Manual Reset Generation Registers AMD SCP Data Port SCPDATA Direct Mapped I O Address 0060h 7 6 5 4 3 2 1 0 Bit SCP_DATA Reserved A20_GATE CPU_RST Reset 0 0 0 0 0 0 1 0 R W W Register Description This register is used to emulate system control processor SCP a20 gate control Bit Definitions Bit Name Function 7 0 SCP DATA System Control Processor Data All reads and writes to this port are echoed to the GP bus 1 A20_GATE A20 Gate Data The ElanSC520 microcontroller has no external input pin for the a20 gat
263. SR registers see page 12 24 and page 12 25 and write access for this register MPICOCWS and for the MPICOCW2 and MPICICW1 registers see page 12 28 and page 12 26 Bit Definitions Bit Name 7 Reserved 6 5 SMM 1 0 4 SLCT_ICW1 3 IS OCWS 1 0 RIS 1 0 12 30 Function Reserved This bit field should be written to 0 for normal system operation This I O address changes functions when read See the programming notes for this register MPICOCWS on page 12 31 Special Mask Mode 00 No operation 01 No operation 10 Reset special mask 11 Set special mask Initialization Control Word 1 Select Software must clear this bit to 0 when writing this address Port 0020h to access either this register MPICOCW3 or the MPICOCW2 register 0 The write accesses either this register MPICOCW3 or the MPICOCW2 register see page 12 28 depending on the state of bit 3 1 The write accesses the MPICICW1 register see page 12 26 Access is OCW3 Software must set this bit S OCW3 and clear SLCT_ICW1 when writing this address Port 0020h to access this register MPICOCWS 0 The write accesses the MPICOCW2 register see page 12 28 if the SLCT_ICW1 bit is cleared 1 The write accesses this register MPICOCWS if the SLCT_ICW1 bit is cleared PIC Poll Command A system designer can choose to use the PIC in a non interrupting mode In this case the interrupt controller can be polled for the
264. T and LCNT are clear and bit CNT2 is set the first subsequent read from this address Port 0042h returns the status byte and the following one or two reads return latched count data as defined by the CTR RW LATCH bit field of the PITMODECTL register see page 13 7 This counter can be configured for either binary coded decimal BCD or 16 bit binary operation viathe PITMODECTL registers BCD bit see page 13 8 The counter range is 0O FFFFh in binary mode or 0 9999d in BCD However the maximum value in either mode can be achieved by clearing this register PIT2CNT to 0 All three PIT counters run at the same rate If the CLK PIN DIR bit is 0 in the CLKSEL register see page 20 9 the CLKTIMER input signal drives the PIT counters Otherwise the PIT counters run at 1 1892 MHz 13 4 Elan SC520 Microcontroller Register Set Manual AMD Programmable Interval Timer Registers Direct Mapped Address 0040h Address 0041h Address 0042h PIT Status PITOSTA PIT 1 Status PIT1STA PIT 2 Status PIT2STA 7 6 2 0 Bit OUTPUT NULL_CNT RW 1 0 CTR MODE STA 2 0 BCD Reset 0 0 0 0 R W R R R R Register Description These registers contain the programmed mode and the null count value for each timer channel Bit Definitions Bit Name Function 7 OUTPUT Output State Output signal state for the timer channel Each timer channel has an output that is driven High or Low based on th
265. T1CTL CCOh page 18 3 UART 1 General Status UART1STA CC1h page 18 4 UART 1 FIFO Control Shadow UART1FCRSHAD CC2h page 18 5 UART 2 General Control UART2CTL CC4h page 18 3 UART 2 General Status UART2STA CC5h page 18 4 UART 2 FIFO Control Shadow Synchronous Serial Interface UART2FCRSHAD CC6h CDO CD4h page 18 5 SSI Control SSICTL CDOh page 19 2 SSI Transmit SSIXMIT CD1h page 19 4 SSI Command SSICMD CD2h page 19 5 SSI Status SSISTA CD3h page 19 6 SSI Receive Programmable Interrupt Controller SSIRCV CD4h D00 D5Ah page 19 7 Interrupt Control PICICR DOOh page 12 4 Master PIC Interrupt Mode MPICMODE DO2h page 12 6 Slave 1 PIC Interrupt Mode SL1PICMODE DO3h page 12 8 Slave 2 PIC Interrupt Mode SL2PICMODE DO4h page 12 9 Software Interrupt 16 1 Control SWINT16 1 DO8h page 12 10 Software Interrupt 22 17 NMI Control SWINT22_17 DOAh page 12 13 Interrupt Pin Polarity INTPINPOL D10h page 12 15 PCI Host Bridge Interrupt Mapping PCIHOSTMAP D14h page 12 17 ECC Interrupt Mapping ECCMAP D18h page 12 19 GP Timer 0 Interrupt Mapping GPTMROMAP D1Ah page 12 21 GP Timer 1 Interrupt Mapping GPTMR1MAP D1Bh page 12 21 GP Timer 2 Interrupt Mapping GPTMR2MAP D1Ch page 12
266. Table 17 1 and Table 17 2 list each type of RTC register in offset order with the corresponding description s page number REGISTERS Real Time Clock Direct Mapped Registers Register Name Mnemonic I O Address Page Number RTC CMOS RAM Index RTCIDX 0070h page 17 2 RTC CMOS RAM Data Port RTCDATA Real Time Clock Indexed Registers Register Name RTC Current Second Mnemonic RTCCURSEC 0071h Address 70h 71h RTC Index page 17 3 Page Number page 17 4 RTC Alarm Second RTCALMSEC 70h 71h page 17 5 RTC Current Minute RTCCURMIN 70h 71h page 17 6 RTC Alarm Minute RTCALMMIN 7TOh 71h page 17 7 RTC Current Hour RTCCURHR 70h 71h page 17 8 RTC Alarm Hour RTCALMHR 70h 71h page 17 9 RTC Current Day of the Week RTCCURDOW 70h 71h page 17 10 RTC Current Day of the Month RTCCURDOM 70h 71h page 17 11 RTC Current Month RTCCURMON 70h 71h page 17 12 RTC Current Year RTCCURYR 7TOh 71h page 17 13 RTC Control A RTCCTLA 70h 7 1h page 17 14 RTC Control B RTCCTLB 70h 71h page 17 16 RTC Status C RTCSTAC 70h 71h page 17 18 RTC Status D RTCSTAD 70h 71h page 17 20 General Purpose CMOS RAM 114 bytes Elan SC520 Microcontroller Register Set Manual RTCCMOS 70h 71h page 17 21 17 1 AMD Real Time Clock Registers RT
267. The channel is then ready to perform another DMA transfer without processor intervention as soon as the next DMA request is detected Automatic initialization must be disabled when buffer chaining mode is used otherwise unexpected results may occur Operation Select This bit field selects the DMA operation for the channel selected by the MODSEL bit field 00 Verify mode The DMA controller acts normally except that no I O or memory commands are generated and no data is transferred 01 Write transfer Data is transferred from a DMA capable I O or memory mapped device into system memory 10 Read transfer Data is transferred from system memory to a DMA capable I O or memory mapped device 11 Reserved Elan SC520 Microcontroller Register Set Manual 11 55 GP DMA Controller Registers Bit Name Function 1 0 MODSEL 1 0 DMA Channel Select This bit field selects the channel that is to internally latch the other bits written to this register 00 Select Channel 0 01 Select Channel 1 10 Select Channel 2 11 Select Channel 3 Programming Notes 11 56 Elan SC520 Microcontroller Register Set Manual GP DMA Controller Registers AMDA Slave DMA Clear Byte Pointer SLDMACBP Direct Mapped I O Address 000Ch 7 6 5 4 3 2 1 0 Bit SLAVE CBP 7 0 Reset x x x x x x x x R W W Register Description This register channel provides a mechanism to adjust the byte pointer to t
268. This register provides extended transfer count bits for Channel 3 Bit Definitions Bit Name Function 7 0 DMA3TC DMA Channel 3 Transfer Count Extension 23 16 This bit field provides the higher 8 bits of the transfer count for DMA Channel 3 In enhanced mode this bit field is used with the 15 0 bit field in the GPDMASTC register see page 11 49 to allow counts up to 16 M 16 777 216 transfers In normal mode the value of this bit field DMA3TC 23 16 is ignored Programming Notes Enhanced mode is enabled by setting the ENH MODE ENB bit in the GPDMACTL register see page 11 4 In PCI bus 2 2 compliant designs software must limit the length of GP bus DMA demand or block mode transfers Very large transfers could cause the PCI Host Bridge target controller to violate the 10 us memory write maximum completion time limit set in the PC Local Bus Specification Revision 2 2 lan SC520 Microcontroller Register Set Manual 11 17 AMDA GP DMA Controller Registers GP DMA Channel 5 Extended Transfer Count GPDMAEXTTC5 Memory Mapped MMCR Offset D91h 7 6 5 4 3 2 1 0 Bit DMASTC 23 16 Reset 0 0 0 0 0 0 0 0 R W RW Register Description This register provides the extended transfer count bits for Channel 5 Bit Definitions Bit Name Function 7 0 DMA5TC DMA Channel 5 Transfer Count Extension 23 16 This bit field provides the higher 8 bits of the transfer count for DMA Channel
269. UIP bit field 17 14 UPD INT ENB bit field 17 17 UPD INT bit field 17 19 Update in Progress bit field 17 14 Update Ended Interrupt Enable bit field 17 17 Flag bit field 17 19 URL AND iii literature ordering iii US ONT bit field 15 3 V Valid RAM and Time bit field 17 20 VDR 10 bit field 6 18 Vendor ID bit field 6 18 VGA palette snoop enable bit not implemented 6 21 W wait cycle control bit not implemented 6 21 Watchdog Timer Control register 16 2 Count High register 16 5 Count Low register 16 4 Enable bit field 16 2 exponent selections table 16 3 Interrupt Mapping register 12 21 MMCR registers table 16 1 Reset Detect bit field 3 5 Reset Enable bit field 16 2 WB ENB bit field 8 3 WB FLUSH bit field 8 3 WB TST ENB bit field 7 2 WB WM bit field 8 2 WBMSTRx signal 7 2 WDT RST DET bit field 3 5 WDTMAP register 12 21 WDTMRONTH register 16 5 WDTMRONTL register 16 4 WDTMRCTL register 16 2 WIDTH bit field in BOOTCSCTL register 9 2 in ROMCS1CTL register 9 4 in ROMCS2CTL register 9 6 WLS bit field 18 18 WPV INT bit field 2 2 WPV bit field 2 4 WPV STA bit field 2 4 Index 22 Index WPV_WINDOW bit field 2 4 WPVMAP register 12 21 WPVSTA register 2 4 Write Buffer Enable bit field 8 3 Flush bit field 8 3 Test Mode Enable bit field 7 2 Watermark bit field 8 2 write buffer and read buffer MMCR registers table 8 1 Write Selection Control bi
270. V R W Register Description This register controls the address column width configuration and SDRAM internal bank count for devices installed in each bank Note A programmable reset preserves this register s state See the PRG_RST_ENB bit description on page 3 3 Bit Definitions Bit Name 15 BNK3_BNK_ CNT 14 Reserved 13 12 BNK3_ COLWDTH 1 0 11 BNK2 BNK CNT 10 Reserved BNK2_ COLWDTH 1 0 Function Bank 3 Internal SDRAM Bank Count This bit specifies the number of internal banks supported by the SDRAM devices 0 2 bank device 1 4 bank device Reserved This bit field should be written to 0 for normal system operation Bank 3 Column Address Width These two bits specify the column address width of the SDRAM devices populated in Bank 3 00 8 bit column address 01 9 bit column address 10 10 bit column address 11 11 bit column address Bank 2 Internal SDRAM Bank Count This bit specifies the number of internal banks supported by the SDRAM devices 0 2 bank device 1 4 bank device Reserved This bit field should be written to 0 for normal system operation Bank 2 Column Address Width These two bits specify the column address width of the SDRAM devices populated in Bank 2 00 8 bit column address 01 9 bit column address 10 10 bit column address 11 11 bit column address Elan SC520 Microcontroller Register Set Manual 7 5 AMD Bit Name BNK1 BNK
271. XTTC3 D90h page 11 17 GP DMA Channel 5 Extended Transfer Count GPDMAEXTTC5 D91h page 11 18 GP DMA Channel 6 Extended Transfer Count GPDMAEXTTC6 D92h page 11 19 GP DMA Channel 7 Extended Transfer Count GPDMAEXTTC7 D93h page 11 20 Buffer Chaining Control GPDMABCCTL D98h page 11 21 Buffer Chaining Status GPDMABCSTA D99h page 11 22 Buffer Chaining Interrupt Enable GPDMABSINTENB D9Ah page 11 24 Buffer Chaining Valid GPDMABCVAL D9Bh page 11 25 GP DMA Channel 3 Next Address Low GPDMANXTADDLS DAOh page 11 26 GP DMA Channel 3 Next Address High GPDMANXTADDHS3 DA2h page 11 27 GP DMA Channel 5 Next Address Low GPDMANXTADDL5 DA4h page 11 28 GP DMA Channel 5 Next Address High GPDMANXTADDH5 DA6h page 11 29 GP DMA Channel 6 Next Address Low GPDMANXTADDL6 DA8h 1 6 Elan SC520 Microcontroller Register Set Manual page 11 30 Configuration Register Overview Table 1 1 Register Name GP DMA Channel 6 Next Address High Mnemonic GPDMANXTADDH6 MMCR Offset AMD Memory Mapped Configuration Region MMCR Registers By Offset Continued Page Number page 11 31 GP DMA Channel 7 Next Address Low GPDMANXTADDL7 page 11 32 GP DMA Channel 7 Next Address High GPDMANXTADDH7 page 11 33 GP DMA Channel 3 Next Transfer Count Low GPDMANXTTCL3 page 11 34
272. Z_ST_ADR 15 0 bit field is used to define the starting address of the window within the 64 Kbyte I O space The SZ ST ADR 15 0 bit field is compared to internal Am5 86 CPU bus signals a15 a0 Note If a larger window than the maximum size is required multiple PARx registers can be used Programming Notes Each PARx register must be written as a full 32 bit doubleword The basic trade off with setting the page size in a PARx register is the granularity of the memory region The smaller page size restricts the total size of the region but allows the smaller granularity of 4 Kbytes The larger 64 Kbyte page size is an option when the total region size must be larger than 512 Kbytes but this requires the pages to start on 64 Kbyte boundaries If two PARx windows overlap the lower numbered PARx register s target has priority For example if a memory or I O address falls within the windows defined by both the PARA register and the PAR 13 register reads or writes to that address go to the PAR4 register s target not the one defined in the PAR13 register If a PARx window overlaps the MMCR alias defined by the CBAR register see page 2 9 the MMCR alias has priority with the following exception if a PAR window is configured for PCI and the CBAR register is programmed to overlap with this PAR window andthe PAR window is placed below the top of DRAM then the MMCR is not given priority over the PCI access This configuration could result i
273. _ICW1 bit is cleared 1 The write accesses the S1PICOCWS register see page 12 55 if the SLCT_ICW1 bit is cleared lan SC520 Microcontroller Register Set Manual 12 53 AMD Programmable Interrupt Coniroller Registers Bit Name Function 2 0 LS 2 0 Specific EOI Level Select Interrupt level that is acted upon when the SL bit 1 see bits 7 5 below 000 IRO 001 IR1 010 IR2 011 IR3 100 IR4 101 IR5 110 IR6 111 IR7 Programming Notes If the S2 bit in the MPICICWS3 register is cleared see page 12 34 then the Slave 1 controller is bypassed and programming this register does not affect other registers I O Port OOAOh provides access to different Slave 1 PIC registers based on the data that is written Table 12 10 provides a summary of bit patterns to write for access to each register Table 12 10 Slave 1 PIC I O Port OOAOh Access Summary Same as Table 12 9 Bits Port 00A0h Register Written Next Port 00A0h Read Returns 1 x S1PICOCW2 page 12 53 0 S1PICOCWS page 12 55 1 1 S1PICOCW3 S1PICIR page 12 49 S1PICOCWS3 S1PICISR page 12 50 X S1PICICW1 page 12 51 12 54 Elan SC520 Microcontroller Register Set Manual Programmable Interrupt Coniroller Registers AMD Slave 1 PIC Operation Control Word S1PICOCW3 Direct Mapped Address 00AOh 7 6 5 4 3 2 1 0 z SLCT_ Bit Reserved ESMM_SMM 1 0 ICW1 IS OCWS3 P RR RIS 1 0
274. a 0 during a write cycle access to this register the ENB bit cannot be modified This bit is always read back as a 0 14 3 AMD Bit 13 12 11 6 14 4 Name INT ENB MAX CNT RIU Reserved MAX CNT RTG General Purpose Timer Registers Function GP Timer 0 Interrupt Enable This bit allows the timer to generate an interrupt when the timer counter value reaches a maximum count compare register value 0 GP Timer 0 interrupt request generation is disabled 1 Timer 0 interrupt request generation is enabled If the INT ENB bit is 1 the TO INT STA bit is set in the GPTMRSTA register see page 14 2 and an interrupt is generated when one of the following conditions occurs The ALT CMP bit is 1 see page 14 5 and the GPTMROONT register value page 14 6 equals the value of either register GPTMROMAXCMPA page 14 7 or GPTMROMAXCMPB page 14 8 The ALT CMP bit is 0 and the GPTMROONT register value equals the value of the GPTMROMAXCMPA register only When the INT ENB bit is 0 the timer does not cause the TO INT STA bit to be set in the GPTMRSTA register see page 14 2 and therefore a timer interrupt is not generated Before GP Timer 0 interrupts are enabled the GPTMROMAP register see page 12 21 must be configured to route the interrupt to the appropriate interrupt request level and priority GP Timer 0 Maxcount Compare Register In Use This bit can be used by software with the MAX ONT bit t
275. a ROMCS 1 region ROM or Flash memory devices 110 The window targets a ROMCS2 region ROM or Flash memory devices 111 The window targets an SDRAM region A PARx register is not required to access SDRAM Target an SDRAM region only when applying one of the attributes described in the ATTR bit field Elan SC520 Microcontroller Register Set Manual Bit 28 26 25 ATTR 2 0 PG_SZ System Address Mapping Registers AMDA Function Attribute If the TARGET bit field selects the PCI bus for PARO and PAR1 only this bit field ATTR is ignored If the TARGET bit field selects GP bus I O or memory this bit field ATTR specifies the GP bus chip select that is targeted as follows 000 GPCSO 001 GPCS1 010 GPCS2 011 GPCS3 100 GPCS4 101 GPCS5 110 GPCS6 111 GPCS7 If the TARGET bit field selects SDRAM or one of the ROM Flash chip selects each bit in this bit field ATTR specifies an attribute The attribute bits for the region can be set or cleared independently with the following effect Code execution is allowed in programmed memory region 1xx Code execution is prevented in programmed memory region An attempt to execute code results in a processor exception and returns an illegal operand code FFFFh This attribute is useful for debugging software for example to prevent a program from erroneously executing out of a data region x0x Caching is enabled for the progra
276. able Interrupt Controller Registers Memory Mapped MMCR Offset D14h 15 14 13 12 11 10 9 8 PCI NMI Bit Reserved ENB Reset 0 0 0 0 0 0 0 0 R W RSV R W 7 6 5 4 3 2 1 0 Bit Reserved PCI_IRQ_MAP 4 0 Reset 0 0 0 0 0 0 0 0 R W RSV R W This register maps the internally generated PCI host bridge interrupt to any of the desired interrupt channels or as an NMI It also enables the PCI Host Bridge NMI request as an NMI source Bit Definitions Bit 15 9 Name Reserved PCI NMI ENB Reserved Function Reserved This bit field should be written to O for normal system operation PCI Host Bridge NMI Enable This bit enables the PCI Host Bridge NMI request as an NMI source 0 PCI Host Bridge NMI request disabled as an NMI source 1 PCI Host Bridge NMI request enabled as an NMI source This bit PCI NMI ENB has no effect on the PCI bus Host Bridge interrupt request which can configured to generate an NMI by setting the PCI IRQ MAP bit field to 11111b Reserved This bit field should be written to 0 for normal system operation lan SC520 Microcontroller Register Set Manual 12 17 AMD Programmable Interrupt Coniroller Registers Bit Name Function 4 0 PCI IRQ MAP PCI Host Bridge Interrupt Mapping 4 0 The value in this 5 bit field maps the internally generated PCI Host Bridge interrupt to one of the following interrupt priority channels on the
277. ad 0111 Memory Write 1000 1001 Reserved 1010 Configuration Read 1011 Configuration Write 1100 Memory Read Multiple not used by the lanSC520 microcontroller 1101 Dual Address Cycle not used by the lanSC520 microcontroller 1110 Memory Read Line not used by the ElanSC520 microcontroller 1111 Memory Write and Invalidate not used by the lanSC520 microcontroller If multiple errors are detected only the command of the first error is latched When multiple error interrupts are pending there is no indication of which interrupt the command corresponds to The MSTINTADD register see page 6 14 contains the address of the transaction during which the master controller detected an error condition Reserved This bit field should be written to 0 for normal system operation Elan SC520 Microcontroller Register Set Manual Bit 5 M RTRTO _ IRQ_STA 4 M_TABRT_ IRQ_STA 3 M_MABRT_ IRQ_STA 2 M_SERR_ IRQ_STA 1 M_RPER_ IRQ_STA 0 M_DPER_ IRQ_STA Programming Notes PCI Bus Host Bridge Registers AMDA Function Master Retry Time Out Interrupt Status This bit is set when the master controller retry time out counter expires 0 Master retry time out has not occurred 1 Master retry time out has occurred This bit is cleared by writing a 1 This bit operates regardless of the corresponding interrupt enable bit M_RTRTO_IRQ_ENB in the HBMSTIRQCTL register see page 6 10 Master T
278. after returning from the first handler 6 NMI ENB Master NMI Enable This bit is a read write version of the NMI enable bit that typically resides at direct mapped Port 0070h bit 7 on a PC AT compatible system It has been moved here to facilitate internal design integration with the ElanSC520 microcontroller 0 NMI is gated off from reaching the CPU core 1 NMI propagates to the CPU core If any NMI interrupt sources are active when this bit is set an NMI is generated immediately The NMI_ENB bit is cleared by a CPU soft reset event This allows software to initialize the stack pointer before setting the NMI_ENB bit again after a soft reset See Table 3 3 on page 3 6 for a summary of ElanSC520 microcontroller reset sources 5 3 Reserved Reserved This bit field should be written to 0 for normal system operation 2 S2_GINT_ Slave 2 PIC Global Interrupt Mode Enable MODE This bit provides a global or individual channel interrupt mode for the Slave 2 PIC 0 Slave 2 PIC global interrupt mode disabled 1 Slave 2 PIC global interrupt mode enabled If the S2 GINT MODE bit is set bit LTIM of the S2PICICW1 register see page 12 39 determines the interrupt mode for the Slave 2 PIC channels If the S2 GINT MODE bit and the LTIM bit are set all the Slave 2 PIC interrupt channels recognize level sensitive interrupt requests If the S2 GINT MODE bit is set and the LTIM bit is cleared all the Slave 2 PIC interrupt channels recognize edge sensitive i
279. allows master retry time outs to generate an interrupt 0 Master retry time outs do not generate an interrupt 1 Master retry time outs generate an interrupt Master Target Abort Interrupt Enable This bit allows master controller transactions that are terminated with a target abort to generate an interrupt 0 Master transactions that are terminated with a target abort do not generate an interrupt 1 Master transactions that are terminated with a target abort generate an interrupt Master Abort Interrupt Enable This bit allows master controller transactions that are terminated with a master abort to generate an interrupt 0 Master transactions that are terminated with a master abort do not generate an interrupt 1 Master transactions that are terminated with a master abort generate an interrupt Master System Error Interrupt Enable This bit allows the assertion of the system error signal SERR by a PCI bus agent to generate an interrupt 0 Assertion of the system error signal does not generate an interrupt 1 Assertion of the system error signal generates an interrupt Master Received Parity Error Interrupt Enable This bit allows the assertion of the parity error signal PERR during a master controller write transaction or during the address phase of a master controller read transaction to generate an interrupt 0 Master write transactions or master read address phase cycles that detect the parity error signal asser
280. ame 31 PERR_DET 30 SIG_SERR Function Parity Error Detected This bit is set when a parity error is detected by the host bridge master or target controller 0 Parity error not detected 1 Parity error detected This bit is cleared by writing a 1 Signaled System Error This bit is normally used to indicate thatthe PCI bus agent has asserted the SERR pin however the host bridge does not drive SERR because the interrupt logic is integrated within the ElanSC520 microcontroller 0 SERR pin not asserted by the host bridge This bit is internally fixed to 0 Elan SC520 Microcontroller Register Set Manual 6 19 AMD Bit 29 28 27 26 25 24 23 22 21 20 9 6 20 Name R MST ABT R TGT ABT S TGT ABT S DVSL TIM 1 0 D PERR DET FBTB UDFS 66M CAP Reserved SERR ENB Reserved PCI Bus Host Bridge Registers Function Received Master Abort This bit is set by the host bridge master controller when its transaction is terminated with a master abort 0 Transaction was not terminated with a master abort 1 Transaction was terminated with a master abort This bit is cleared by writing a 1 Received Target Abort This bit is set by the host bridge master controller when its transaction is terminated with a target abort 0 Transaction was not terminated with a target abort 1 Transaction was terminated with a target abort This bit is cleared by writing a
281. ammable Interrupt Controller MMCR Registers Mnemonic MMCR Offset PICICR MPICMODE SL1PICMODE SL2PICMODE SWINT16 1 SWINT22 17 INTPINPOL PCIHOSTMAP ECCMAP GPTMROMAP GPTMR1MAP GPTMR2MAP PITOMAP PIT1MAP PIT2MAP UART1MAP UART2MAP PCIINTAMAP Register Name Page Number Interrupt Control page 12 4 Master PIC Interrupt Mode Slave 1 PIC Interrupt Mode Slave 2 PIC Interrupt Mode Software Interrupt 16 1 Control Software Interrupt 22 17 NMI Control Interrupt Pin Polarity page 12 6 page 12 8 page 12 9 page 12 10 page 12 13 page 12 15 page 12 17 PCI Host Bridge Interrupt Mapping ECC Interrupt Mapping page 12 19 GP Timer 0 Interrupt Mapping page 12 21 GP Timer 1 Interrupt Mapping page 12 21 page 12 21 GP Timer 2 Interrupt Mapping PIT 0 Interrupt Mapping page 12 21 PIT 1 Interrupt Mapping page 12 21 PIT 2 Interrupt Mapping page 12 21 UART 1 Interrupt Mapping page 12 21 UART 2 Interrupt Mapping PCI Interrupt A Mapping page 12 21 page 12 21 Elan SC520 Microcontroller Register Set Manual 12 1 AMD Table 12 1 Table 12 2 12 2 Programmable Interrupt Controller Registers Programmable Interrupt Controller MMCR Registers Continued Register Name PCI Interrupt B Mapping Mnemonic PCIINTBMAP MMCR Offset Page Number page 12 21 PCI Interrupt C Mapping PCIINTCMAP page 12 21 PCI Interrupt D Mapp
282. and checked in the received data The parity bit is located between the last data word bit and the first stop bit in the bit stream Elan SC520 Microcontroller Register Set Manual 18 17 UART Serial Port Registers Bit Name Function 2 STP Stop Bits This bit sets the number of stop bits used based on the character length set in the WSL bit field If WSL 00b 5 bit words 0 1 stop bit 1 21 5 stop bits If WSL 01 11b 6 7 or 8 bit words 0 1 stop bit 1 2 stop bits 1 0 WLS 1 0 Transmit Receive Word Length Select This bit field sets the UART data word length 00 5 bits 01 6 bits 10 7 bits 11 8 bits Programming Notes 18 18 Elan SC520 Microcontroller Register Set Manual UART 2 Modem Control UART2MCR UART 1 Modem Control UART1MCR Register Description AMD UART Serial Port Registers Direct Mapped I O Address 02FCh Address O3FCh 6 5 4 3 2 1 0 Bit Reserved LOOP OUT2 OUT1 RTS DTR Reset 0 0 0 0 0 0 0 R W RSV R W R W R W R W R W This register is used to control the interface with the modem or peripheral device It is used to enable interrupts from the UART enable loopback diagnostic mode or assert RTSx or DTRx Bit Definitions Bit 7 5 4 3 2 Name Reserved LOOP OUT2 OUT1 Function Reserved This bit field should be written to 0 for normal system operation Loopback Mode Diagnostic Mode Enable 0 2
283. ange 00100 01010b does not pass the interrupt request to the CPU However if this bit field is programmed to 0001 1b with the S2 bit cleared the interrupt request is routed to the Master PIC IR2 input If bit S5 in the MPICICWS register is cleared see page 12 33 the Slave 2 PIC is bypassed so programming the INT MAP bit field to a value in the range 01110 10100b does not pass the interrupt request to the CPU However if this field is programmed to 01101b with the S5 bit cleared the interrupt request is routed to Master PIC IR5 input 2 2 5 Programming Notes This register should be programmed only when the corresponding interrupt channel mask bits are set in the PIC For NMls this register should be programmed only when bit NMI_ENBis cleared in the PICICR register see page 12 4 NMI ENB can be set immediately after programming this mapping register to allow NMIs to be passed to the CPU 12 22 Elan SC520 Microcontroller Register Set Manual Programmable Interrupt Coniroller Registers AMD Programming than interrupt source to an interrupt channel results interrupt sharing on that channel Programming more than one interrupt source as an NMI source results in NMI sharing on the CPU s NMI input All interrupt and NMI sources can be found in the following register descriptions W Software Interrupt 16 1 Control page 12 10 Software Interrupt 22 17 NMI Control page 12 13 PCI Host Bridge Interru
284. ange of 0 9999d 0 16 bit binary counter 1 BCD counter Programming Notes Writing to this register PITMODECTL to change the mode for a particular counter resets the control logic and the associated output Reads of this register return an undefined value When a counter s current value is required software should obtain itby issuing a counter latch or read back command viathe PITCNTLAT or PITRDBACK register see page 13 10 or page 13 11 A counter latch or read back command does not stop a counter from running but rather takes a snapshot of the current value Once the count has been latched further latch commands are ignored until all latched count data is read back from the associated count register A read back command is a higher priority command than the counter latch command The counter latch command is a subset of the read back command because only one channel can have its counter latched per counter latch command The programmable interval timer does not provide any way to read back the original count programmed into any of the three count registers 13 8 Elan SC520 Microcontroller Register Set Manual Table 13 2 CTR_MODE Bit Field Setting 000b Mode 0 Programmable Interval Timer Registers Mode Name Interrupt on terminal count AMD PIT Counter Mode Settings Description When the counter is programmed the counter output transitions to 0 When the counter reaches 0 the counter output transitions
285. anual order 22004 for information about PCI bus initialization Elan SC520 Microcontroller Register Set Manual 6 3 AMD Bit 9 8 T_DLYTR_ENB 1 0 Reserved M_WPOST_ ENB Reserved Programming Notes PCI Bus Host Bridge Registers Function Automatic Delayed Transaction Enable This bit forces all PCI bus master reads of microcontroller SDRAM to be treated as delayed transactions unless the host bridge has already completed the transaction from a previous request Setting this bit allows unused PCI bus bandwidth to be used by other PCI bus masters while the read transaction from the first master is being serviced 00 PCI bus reads to SDRAM are not automatically retried as delayed transactions Instead the originating PCI bus master is held in wait states while the host bridge begins the SDRAM read transaction If 32 PCI bus clock cycles pass before the first doubleword has been read from SDRAM by the host bridge target controller the bridge then issues a retry as required for PCI compliance 01 All PCI bus reads to SDRAM are automatically retried as delayed transactions unless the host bridge has already completed the transaction from a previous request This occurs when a PCI bus master has already issued the transaction previously and was issued a retry by the host bridge target controller 10 Reserved 11 Reserved Reserved This bit field should be written to 0 for normal system operation
286. ap the txdrq1 and txdack1 internal signals to a GP DMA channel 0000 Channel 0 0001 Channel 1 0010 Channel 2 0011 Channel 3 All other values are treated as unconnected RXDRQ2 Channel Mapping Map rxdrq2 and rxdack2 internal signals to a GP DMA channel 0000 Channel 0 0001 Channel 1 0010 Channel 2 0011 Channel 3 All other values are treated as unconnected Elan SC520 Microcontroller Register Set Manual GP DMA Controller Registers AMDA Bit Name Function 3 0 RXDRQ1_ RXDRQ1 Channel Mapping CHSEL 3 0 Map the rxdrq1 and rxdack1 internal signals to a GP DMA channel 0000 Channel 0 0001 Channel 1 0010 Channel 2 0011 Channel 3 All other values are treated as unconnected Programming Notes Elan SC520 Microcontroller Register Set Manual 11 9 AMDA GP DMA Controller Registers GP DMA Channel 0 Extended Page GPDMAEXTPGO Memory Mapped MMCR Offset D86h 7 6 5 4 3 2 1 Bit Reserved DMAOADR 27 24 Reset 0 0 0 0 0 0 0 R W RSV R W Register Description This register provides the extended page address for Channel 0 Bit Definitions Bit Name Function 7 4 Reserved Reserved This bit field should be written to 0 for normal system operation 3 0 DMAOADR DMA Channel 0 Extended Page Address 27 24 This bit field specifies the highest four memory address bits A27 A24 for Channel 0 Programming Notes The extended page address is used in conjunction with the
287. aracter is received This latched status bit is automatically cleared by a read from this register UARTxLSR Data Ready 0 There is no received data ready to read 1 In 16450 compatible mode this bit is set when a character has been received and placed in the Receive Buffer register In 16550 compatible mode this bit is set when a character has been received and placed in the Receive FIFO In 16450 compatible mode this bit is automatically cleared by reading the UARTxRBR register see page 18 8 In 16550 compatible mode this bit is automatically cleared by reading the receiver FIFO assuming that no more data is present in the FIFO When a receiver line status interrupt is enabled and detected bits BI FE PE and OE in this register indicate the reason for the interrupt The status bits are valid even when line status interrupts are not enabled 18 22 Elan SC520 Microcontroller Register Set Manual UART 2 Modem Status UART2MSR UART 1 Modem Status UART1MSR Register Description AMD UART Serial Port Registers Direct Mapped I O Address O2FEh I O Address O3FEh 7 6 5 4 3 2 1 0 Bit DCD RI DSR CTS DDCD TERI DDSR DCTS Reset 0 0 0 0 R W R R R R R R R R This read only register contains both real time and latched control line status bits for the UART s DCDx RINx DSRx and CTSx input signals Bit Definitions Bit Name DCD RI DSR CTS
288. arated by eight locations not valid in the ElanSC520 microcontroller 1 Interrupt vectors are separated by four locations In the ElanSC520 microcontroller design this PC AT compatible bit ADI is internally fixed to 1 Single PIC 0 Cascade mode MPICICWS is expected 1 Single PIC in the system MPICICWS is not expected Setting this bit logically removes the Slave 1 and Slave 2 controllers from the Master PIC This routes the interrupt requests that were hooked to IRO of the Slave 1 and Slave 2 controllers directly to interrupt requests IR2 and IR5 of the Master PIC respectively If this bit is set then the internal register pointer skips MPICICWS and points to MPICICWA if MPICICWA was selected to be programmed via the IC4 bit See the programming notes for this register MPICICW1 on page 12 27 Elan SC520 Microcontroller Register Set Manual Programmable Interrupt Coniroller Registers AMD Function 0 IC4 Initialization Control Word 4 Software uses this bit to indicate whether it intends to explicitly program the MPICICW4 register see page 12 35 after writing to the MPICICWSG register see page 12 33 See the programming notes on this page for details 0 The MPICICWA register is initialized internally when this register MPICICW1 is written The PIC does not expect software to write to the MPICICWA register after writing to the MPICICWS register 1 2 The MPICICWA register is not initialized
289. ared Other Reserved When multiple interrupts are pending this bit field represents the PCI bus master active when the first interrupt occurred but there is no way for software to detect which interrupt this is Reserved This bit field should be written to 0 for normal system operation Target Delayed Transaction Time Out Interrupt Status This bit is set when the target controller issues a delayed transaction retry the PCI bus master does not retry the transaction within 215 clocks and the target controller is idle i e no PCI to SDRAM transaction is active on the PCI bus 0 Delayed transaction time out has not occurred 1 Delayed transaction time out has occurred This bit is cleared by writing a 1 The target controller discards the delayed transaction request when this bit is set This bit operates regardless of the corresponding interrupt enable bit T DIYTO IRQ the HBTGTIRQCTL register see page 6 5 Elan SC520 Microcontroller Register Set Manual 6 7 AMD Programming Notes Bit Name T APER IRQ_STA T_DPER_ IRQ_STA PCI Bus Host Bridge Registers Function Target Address Parity Interrupt Status This bit is set when the target controller detects an address parity error 0 Address parity error has not occurred 1 Address parity error has occurred This bit is cleared by writing a 1 This bit operates regardless of the corresponding interrupt enable bit T APER IRQ ENB in the
290. arget Abort Interrupt Status This bit is set when a master controller transaction is terminated with a target abort 0 Master controller transaction has not been terminated with a target abort 1 Master controller transaction has been terminated with a target abort This bit is cleared by writing a 1 This bit operates regardless of the corresponding interrupt enable bit M_TABRT_IRQ_ENB in the HBMSTIRQCTL register see page 6 10 Master Abort Interrupt Status This bit is set when a master controller transaction is terminated with a master abort 0 Master controller transaction has not been terminated with a master abort 1 Master controller transaction has been terminated with a master abort This bit is cleared by writing a 1 This bit operates regardless of the corresponding interrupt enable bit M_MABRT_IRQ_ENB in the HBMSTIRQCTL register see page 6 10 Master System Error Interrupt Status This bit is set when the master controller detects the system error signal asserted 0 Master controller has not detected the system error signal asserted 1 Master controller has detected the system error signal asserted This bit is cleared by writing a 1 This bit operates regardless of the corresponding interrupt enable bit M_SERR_IRQ_ENB in the HBMSTIRQCTL register see page 6 10 Master Received Parity Error Interrupt Status This bit is set when the master controller detects the parity error signal asserted during a master
291. assertion 0 Do not assert the interrupt 1 Assert the interrupt 9 SW P10 TRIG Directly Trigger Priority Level P10 Setting this bit directly asserts a maskable interrupt of priority level P10 Clearing this bit removes this direct interrupt assertion 0 Do not assert the interrupt 1 Assert the interrupt 8 SW P9 TRIG Directly Trigger Priority Level P9 Setting this bit directly asserts a maskable interrupt of priority level P9 Clearing this bit removes this direct interrupt assertion 0 Do not assert the interrupt 1 Assert the interrupt 7 SW P8 TRIG Directly Trigger Priority Level P8 Setting this bit directly asserts a maskable interrupt of priority level P8 Clearing this bit removes this direct interrupt assertion 0 Do not assert the interrupt 1 Assert the interrupt 6 SW P7 TRIG Directly Trigger Priority Level P7 Setting this bit directly asserts a maskable interrupt of priority level P7 Clearing this bit removes this direct interrupt assertion 0 Do not assert the interrupt 1 Assert the interrupt 5 SW P6 TRIG Directly Trigger Priority Level P6 Setting this bit directly asserts a maskable interrupt of priority level P6 Clearing this bit removes this direct interrupt assertion 0 Do not assert the interrupt 1 Assert the interrupt 4 SW P5 TRIG Directly Trigger Priority Level P5 Setting this bit directly asserts a maskable interrupt of priority level P5 Clearing this bit removes this direct i
292. at which the INT ID bit field in the UARTXINTID register see page 18 13 reports that a received data available interrupt is pending If received data available interrupts are enabled in the UARTxINTENB register page 18 11 the system is interrupted when the receive FIFO fills to the trigger level as follows 00 1 byte 01 4 bytes 10 8 bytes 11 14 bytes When the data in the receive FIFO falls below the specified trigger level the interrupt is cleared Reserved This bit field should be written to O for normal system operation DMA Mode This bit is valid only in 16550 compatible mode In 16450 compatible mode the DMA operation is defined as if this bit were set to 0 0 The internal rxdrq signal to the DMA controller goes High when there is at least one character in the receiver FIFO or the UARTx Receive Buffer register see page 18 8 The internal txdrq signal goes High when the transmitter FIFO 16550 compatible mode or the UARTx Transmit Holding register page 18 7 16450 compatible mode is not full 1 The internal rxdrq signal goes High when the trigger level or the time out has been reached and then it goes inactive when there are no more characters in the FIFO or holding register For transmit the internal txdrq signal goes High when the transmitter FIFO is not full and remains High until the transmitter FIFO is completely full Transmitter FIFO Clear Because the direct mapped version of this bit is self clearin
293. ation the PIC supports a special poll command that is invoked by setting this bit 0 Not poll command 1 Poll command Status Register Select 00 No change from last state 01 No change from last state 10 Next Port 0024h read returns the S2PICIR register s contents see page 12 37 11 Next Port 0024h read returns in the S2PICISR register s contents see page 12 38 Elan SC520 Microcontroller Register Set Manual 12 43 AMD Programmable Interrupt Coniroller Registers Programming Notes If the S5 bit in the MPICICWS3 register is cleared see page 12 33 then the Slave 2 controller is bypassed and programming this register does not affect other registers I O Port 0024h provides access to different Slave 2 PIC registers based on the data that is written Table 12 8 provides a summary of bit patterns to write for access to each register Table 12 8 Slave 2 PIC I O Port 0024h Access Summary Same as Table 12 6 Bits Port 0024h Register Written Next Port 0024h Read Returns 6 5 4 3 2 1 0 0 x S2PICOCW2 12 41 1 x 0 S2PICOCWS page 12 43 0 0 0 0 1 0 1 0 S2PICOCWS3 S2PICIR page 12 37 0 0 0 0 1 0 1 1 S2PICOCWS3 S2PICISR page 12 38 0 0 01 x X S2PICICW1 page 12 39 12 44 Elan SC520 Microcontroller Register Set Manual Programmable Interrupt Coniroller Registers AMD Slave 2 PIC In
294. ational setting for the OSC_CTL bit 110 Hold the RTC divider chain in the reset state In this mode the time and date update cycles do not occur This mode is useful for precision setting of the clock Time and date update cycles begin 500 milliseconds after the value of 010b is written to this field 111 Same as 110b All other values are reserved Setting the OSC_CTL value to anything other than 11xb or 010b causes the RTC time base updates to occur at a frequency other than 1Hz These three bits are not affected by an RTC only reset and must be initialized to ensure correct operation Elan SC520 Microcontroller Register Set Manual Bit 3 0 SEL 3 0 Programming Notes Real Time Clock Registers AMDA Function Rate Selection The periodic interrupt output of the RTC is internally tied to the programmable interrupt controller PIC and is available for use The RATE_SEL bit field controls the rate at which periodic interrupts are driven to PIC as follows 0000 Periodic interrupt disabled 0001 3 906 ms 0010 7 812 ms 0011 122 070 us 0100 244 141 us 0101 488 281 us 0110 976 563 us 0111 1 953 ms 1000 3 906 ms 1001 7 812 ms 1010 15 625 ms 1011 31 250 ms 1100 62 500 ms 1101 125 000 ms 1110 250 000 ms 1111 500 000 ms The periodic interrupt is enabled by the PER_INT_ENB bit field in the RTCCTLB register see page 17 16 The PER_INT_FLG bit in the RTCSTAC regist
295. bes the MMCR registers first followed by direct mapped and then indexed register descriptions if any In each chapter registers of each type are listed in ascending hexadecimal order unless descriptions for identical registers for example direct mapped UART registers are combined The remainder of this chapter presents an overview of the registers by type MEMORY MAPPED CONFIGURATION REGION MMCR REGISTERS The lanSC520 microcontrollers memory mapped configuration region MMCR contains all internal peripheral control and configuration registers that are not defined as direct mapped I O PCI indexed or RTC indexed registers After reset the MMCR registers are located in the 4 Kbyte region in memory address space from FFFEFOOO FFFEFFFFh The MMCR registers can be aliased to any 4 Kbyte region in the lower 1 Gbyte address space 00000000h 1FFFFFFh via the l O mapped CBAR register see page 2 9 The MMCR is available at its original location in high memory even if it is via the CBAR register See the memory and I O space chapter in the Elan SC520 Microcontroller User s Manual order 22004 for more detail Table 1 1 on page 1 2 lists all the MMCR registers included in the lanSC520 microcontroller Elan SC520 Microcontroller Register Set Manual 1 1 AMD Table 1 1 Register Name CPU Configuration Register Overview Mnemonic MMCR Offset Memory Mapped Configuration Region MMCR Registers By Offset
296. bit by writing a 1 12 The current buffer transfer is completed In addition an interrupt is generated if bit CH3 INT ENB is 1 in the GPDMABSINTENB register see page 11 24 Software should write a 1 to this bit CH3 EOB STA to acknowledge the transfer completion and clear the interrupt condition This acknowledgment is usually done in the interrupt handling routine if the interrupt is enabled Writing 0 to this bit has no effect If this bit is 0 writing a 1 to it has no effect This bit s value when read is meaningful only if buffer chaining is enabled Programming Notes The interrupt output is shared between the four channels 3 5 6 and 7 If more than one interrupt is asserted and software acknowledges one of the interrupts by setting the corresponding CHx EOB STA bit any other pending interrupts remain asserted Software has the option of acknowledging all pending CHx EOB STA bits and handling all of the interrupts Buffer chaining is enabled separately for each channel in the GPDMABCCTL register see page 11 21 lan SC520 Microcontroller Register Set Manual 11 23 AMD Buffer Chaining Interrupt Enable GPDMABSINTENB Bit Reset R W GP DMA Controller Registers Memory Mapped MMCR Offset D9Ah 3 2 1 0 CH7 INT CH6 INT CH5 INT CH3 INT ESENE ENB ENB ENB ENB 0 0 0 0 RSV R W R W R W R W Register Description This register provides the interrupt enable b
297. bit field in MPICOCWS register 12 30 in STPICOCWS register 12 55 in S2PICOCWS register 12 43 PICICR register 12 4 PIO register programming summary table 20 2 PIO15 PIOO signals Clear register 20 24 Data register 20 16 Direction register 20 12 Pin Function Select register 20 3 Set register 20 20 PIO31 PIO16 signals Clear register 20 26 Data register 20 18 Direction register 20 14 Pin Function Select register 20 5 Set register 20 22 PIOCLR15_0 register 20 24 PIOCLR31 16 register 20 26 PIODATA15 0 register 20 16 PIODATA31_ 16 register 20 18 PIODIR15 0 register 20 12 PIODIR31 16 register 20 14 PIOPFS15 0 register 20 3 Index 14 Elan SC520 Microcontroller Register Set Manual PIOPFS31_16 register 20 5 PIOSET15_0 register 20 20 PIOSET31_16 register 20 22 PIOx Clear bit field in PIOCLR15_0 bit field 20 24 20 25 in PIOCLR31 16 bit field 20 26 20 27 PIOx Function Select bit field in PIOPFS15 0 register 20 3 20 4 in PIOPFS31 16 register 20 5 20 6 PIOx Input or Output Select bit field in PIODIR15 bit field 20 12 20 13 in PIODIR31_ 16 bit field 20 14 20 15 PIOx Set bit field in PIOSET15 bit field 20 20 20 21 in PIOSET31 16 bit field 20 22 20 23 PIOx CLR bit field in PIOCLR15 0 register 20 24 20 25 in PIOCLR31 16 register 20 26 20 27 PIOx DATA bit field in PIODATA15 0 register 20 16 20 17 in PIODATA31 16 register 20 18 20 19 PIOx DIR bit field in
298. bit field should be written to 0 for normal system operation Software NMI Source Setting this bit directly asserts an NMI to the CPU This bit should be cleared by software prior to setting the NMI DONE bit of the PICICR register see page 12 4 0 2 NMI not directly asserted other sources can still assert an NMI 1 Directly assert the NMI to the CPU Directly Trigger Priority Level P22 Setting this bit directly asserts a maskable interrupt of priority level P22 Clearing this bit removes this direct interrupt assertion This is the lowest interrupt priority level 0 Do not assert the interrupt 1 Assert the interrupt Directly Trigger Priority Level P21 Setting this bit directly asserts a maskable interrupt of priority level P21 Clearing this bit removes this direct interrupt assertion 0 Do not assert the interrupt 1 Assert the interrupt Directly Trigger Priority Level P20 Setting this bit directly asserts a maskable interrupt of priority level P20 Clearing this bit removes this direct interrupt assertion 0 Do not assert the interrupt 1 Assert the interrupt Directly Trigger Priority Level P19 Setting this bit directly asserts a maskable interrupt of priority level P19 Clearing this bit removes this direct interrupt assertion 0 Do not assert the interrupt 1 Assert the interrupt Directly Trigger Priority Level P18 Setting this bit directly asserts a maskable interrupt of priority level P18 Clearing
299. bits 15 0 Bits 7 0 of the channel s memory address can be read from or written to this bit field immediately after a write to the SLDMACBP register see page 11 57 Bits 15 8 of the channel s memory address can be read from or written to this bit field immediately after memory address bits 7 0 are read from or written to this bit field Programming Notes To ensure that the lower byte of this register GPDMA3MAR is always accessed first software should precede any access to this register with a write to the SLDMACBP register see page 11 57 to clear the slave DMA byte pointer The value in this register GPDMA3MAR is used with the values in the GPDMASPG register see page 11 64 and the GPDMAEXTPGS register see page 11 13 to generate DMA address bits 27 0 In enhanced mode this channel can be programmed for 16 bit DMA transfers see the descriptions for GRPDMACTL register bits CH3 ALT SIZE and ENH MODE ENB on page 11 4 For 16 bit transfers this register GPDMA3MAR holds address bits 16 1 and address bit 0 is always 0 i e the 16 bit transfers are word aligned Because of this software must load this register with the desired memory address divided by 2 for 16 bit transfers 11 48 Elan SC520 Microcontroller Register Set Manual GP DMA Controller Registers AMDA Slave DMA Channel 3 Transfer Count GPDMA3TC Direct Mapped I O Address 0007h 7 6 5 4 3 2 1 0 Bit 15 0 Re
300. ble Setting this bit causes a break condition to be transmitted to the receiving UART 0 Disable set break 1 Force serial output to spacing state logic 0 regardless of other transmitter activity The break control acts on the SOUTx pin only and has no other effect on the transmitter logic Stick Parity Enable Stick parity forces the parity bit to be always 0 or 1 0 Stick Parity is disabled If parity is enabled by the PENB bit normal parity is used the parity bit dynamically changes so the number of 1 bits in the transmitted data is always odd or even depending on the EPS bit 1 Stick Parity is enabled If parity is enabled the parity bit is always 0 or 1 If bits SP EPS and PENB are 1 the parity bit is generated and checked as 0 If bits SP and PENB are 1 and EPS is 0 the parity bit is generated and checked as 1 Even Parity Select Parity must be enabled via the PENB bit for this bit to have meaning 0 Odd parity The parity bit is manipulated to force an odd number of 1 bits in the transmitted data and the same condition is checked for in the received data 1 Even parity The parity bit is manipulated to force an even number of 1 bits in the transmitted data and the same condition is checked for in the received data Start and stop bits are not included in the parity generation and checking scheme Parity Enable 0 Parity is disabled 1 Parity is enabled A parity bit is generated in the transmitted data
301. ble UART2INTENB page 18 11 UART 2 Interrupt ID UART2INTID page 18 12 UART 2 FIFO Control UART2FCR page 18 15 UART 2 Line Control UART2LCR page 18 17 UART 2 Modem Control UART2MCR page 18 19 UART 2 Line Status UART2LSR page 18 21 UART 2 Modem Status UART2MSR page 18 23 Elan SC520 Microcontroller Register Set Manual 18 1 AMD Table 18 2 18 2 UART Serial Port Registers UART Direct Mapped Registers Continued Register Name UART 2 Scratch Pad Mnemonic UART2SCRATCH Address Page Number page 18 25 UART 1 Transmit Holding UART1THR page 18 7 UART 1 Receive Buffer UART1RBR page 18 8 UART 1 Baud Clock Divisor Latch LSB UART1BCDL page 18 9 UART 1 Baud Clock Divisor Latch MSB UART1BCDH page 18 10 UART 1 Interrupt Enable UART1INTENB page 18 11 UART 1 Interrupt ID UARTIINTID page 18 12 UART 1 FIFO Control UART1FCR page 18 15 UART 1 Line Control UART1LCR page 18 17 UART 1 Modem Control UART1MCR page 18 19 UART 1 Line Status UART1LSR page 18 21 UART 1 Modem Status UART1MSR page 18 23 UART 1 Scratch Pad UART1SCRATCH Elan SC520 Microcontroller Register Set Manual page 18 25 UART Serial Port Registers UART 1 General Control UART1CTL UART 2 General Control UART2CTL AMD Memory Mapped MMCR Offset CCOh MMCR Offset CC4h
302. ble interrupt of priority level P16 Clearing this bit removes this direct interrupt assertion 0 Do not assert the interrupt 1 Assert the interrupt 14 SW P15 TRIG Directly Trigger Priority Level P15 Setting this bit directly asserts a maskable interrupt of priority level P15 Clearing this bit removes this direct interrupt assertion 0 Do not assert the interrupt 1 Assert the interrupt 13 SW P14 TRIG Directly Trigger Priority Level P14 Setting this bit directly asserts a maskable interrupt of priority level P14 Clearing this bit removes this direct interrupt assertion 0 Do not assert the interrupt 1 2 Assert the interrupt 12 SW P13 TRIG Directly Trigger Priority Level P13 Setting this bit directly asserts a maskable interrupt of priority level P13 Clearing this bit removes this direct interrupt assertion 0 Do not assert the interrupt 1 2 Assert the interrupt 11 SW P12 TRIG Directly Trigger Priority Level P12 Setting this bit directly asserts a maskable interrupt of priority level P12 Clearing this bit removes this direct interrupt assertion 0 Do not assert the interrupt 1 2 Assert the interrupt 12 10 Elan SC520 Microcontroller Register Set Manual Programmable Interrupt Coniroller Registers AMD Bit Name Function 10 SW P11 TRIG Directly Trigger Priority Level P11 Setting this bit directly asserts a maskable interrupt of priority level P11 Clearing this bit removes this direct interrupt
303. bled from reaching the microcontroller s PIC The single bit ECC interrupt request cannot be routed as a source for generating an NMI If bit S2 in the MPICICWS register is cleared see page 12 34 the Slave 1 PIC is bypassed so programming the ECC IRQ MAP bit field to a value in the range 00100 01010b does not pass the interrupt request to the CPU However if this bit field is programmed to 00011b with the S2 bit cleared the ECC interrupt request is routed to the Master PIC IR2 input If bit S5 in the MPICICWS register is cleared see page 12 33 the Slave 2 PIC is bypassed so programming the ECC MAP bit field to a value in the range 01110 10100b does not pass the interrupt request to the CPU However if this field is programmed to 01101b with the S5 bit cleared the ECC interrupt request is routed to Master PIC IR5 input Programming Notes This register should be programmed only when the corresponding interrupt channel mask bits are set in the PIC For NMIs this register should be programmed only when bit NMI is cleared in the PICICR register see page 12 4 NMI ENB can be set immediately after programming this register ECCMAP to allow NMIs to be passed to the CPU Programming more than one interrupt source to an interrupt channel results in interrupt sharing on that channel Programming more than one interrupt source as an NMI source results in NMI sharing on the CPU s NMI input All interrupt and NMI sources can b
304. bling this feature results in timing changes on the GP bus that can violate the ISA specification This bit has no effect when the COMPTIM bit is 1 Priority Type 0 Fixed priority 1 Rotating priority Compressed Timing 0 Normal timing 1 Compressed timing Read command signals GPIORD and GPMEMRD have a one clock pulse width Enabling this feature results in timing changes on the GP bus that can violate the ISA specification Disable DMA Controller 0 requests are enabled 1 DMA requests are ignored but DMA registers are available to the CPU The DMA controller should be disabled prior to programming it in order to prevent unintended transfers from occurring during the DMA controller programming operation Care should also be taken to ensure that the DMA controller is idle before disabling it If the DMA controller is performing a transfer when software disables it abnormal system operation can occur lan SC520 Microcontroller Register Set Manual 11 51 GP DMA Controller Registers Bit Name Function 1 0 Reserved Reserved This bit field should be written to 0 for normal system operation Programming Notes If DMA Channel 0 1 2 or 3 is used by an internal UART the DAKSEN DRQSEN WRTSEL and COMPTIM bit fields must be 0 the default 11 52 Elan SC520 Microcontroller Register Set Manual GP DMA Controller Registers AMDA Slave Software DRQ n Request SLDMASWREQ Direct Mapped Re
305. by the write to this register MPICICW1 Software is expected to initialize the MPICICWA register Programming Notes The PIC s initialization control word MPICICWx registers 1 4 must be programmed in sequence Writing to Port 0020h with bit 4 1 causes the MPICICW1 register to be written and also resets the PIC s internal state machine and the internal MPICICWXx register pointer Then MPICICWX registers 2 4 can be programmed by sequential writes to Port 0021h Each time Port 0021h is written to following the write to MPICICW1 the internal register pointer points to the next MPICICWx register MPICICW1 and MPICICW2 must always be programmed The MPICICW3 register is skipped if the SNGL bit in MPICICW1 is 1 The MPICICW4 register is skipped if the IC4 bit in MPICICW1 is 0 I O Port 0020h provides access to different Master PIC registers based on the data that is written Table 12 3 provides a summary of bit patterns to write for access to each register Table 12 3 Master I O Port 0020h Access Summary Bits Port 0020h Register Written Next Port 0020h Read Returns 1 0 x X MPICOCW2 page 12 28 0 x MPICOCWS page 12 30 11 0 1 1 MPICOCW3 MPICIR page 12 24 MPICOCWS MPICISR page 12 25 X MPICICW1 page 12 26 lan SC520 Microcontroller Register Set Manual 12 27 AMD Programmable Interrupt Controller Registers Master PIC Operation Control Word 2 MPICOCW2
306. ce enabled by the GPIORD and GPIOWR signals or a memory mapped I O device enabled by the GPMEMRD or GPMEMWR signals for each channel Bit Definitions Bit Name DMA7 MMAP DMA6 MMAP DMA5 MMAP Reserved DMA3 MMAP DMA2 MMAP DMA1 MMAP DMAO MMAP Programming Notes Function Memory Mapped Device for DMA Channel 7 0 DMA Channel 7 connects to a direct mapped I O device 1 DMA Channel 7 connects to a memory mapped device Memory Mapped Device for DMA Channel 6 0 DMA Channel 6 connects to a direct mapped I O device 1 DMA Channel 6 connects to a memory mapped device Memory Mapped Device for DMA Channel 5 0 Channel 5 connects to a direct mapped I O device 1 DMA Channel 5 connects to a memory mapped device Reserved This bit field should be written to 0 for normal system operation Memory Mapped Device for DMA Channel 3 0 DMA Channel connects to a direct mapped I O device 1 DMA Channel 3 connects to a memory mapped device Memory Mapped Device for DMA Channel 2 0 DMA Channel 2 connects to direct mapped I O device 1 DMA Channel 2 connects to a memory mapped device Memory Mapped Device for DMA Channel 1 0 Channel 1 connects to a direct mapped I O device 1 DMA Channel 1 connects to a memory mapped device Memory Mapped Device for DMA Channel 0 0 DMA Channel 0 connects to a direct mapped I O device 1 DMA Channel 0 connects to a memory mapped device
307. ched Programming Notes These are status only bits used to provide static information to software For example the system hardware designer can configure pullup resistors as needed on the RSTLD7 RSTLDO pins to provide board revision information to software The pullup resistors value should be approximately 10 KO 3 2 Elan SC520 Microcontroller Register Set Manual Reset Configuration RESCFG Register Description AMD Reset Generation Registers Memory Mapped MMCR Offset D72h 6 5 4 3 2 1 0 ICE ON PRG RST Bit Reserved RST ENB GP_RST SYS_RST Reset 0 0 0 0 0 0 0 0 R W RSV R W R W R W R W This register provides a direct read write port to program system reset and GP bus reset It also provides a control bit to enable or disable the programmable system reset function of the PRGRESET pin and another control bit to enable the AMDebug technology Bit Definitions 1 Name Reserved ICE ON RST PRG _ GP_RST Function Reserved This bit field should be written to 0 for normal system operation Enter AMDebug Technology Mode on Next Reset Setting this bit enables the microprocessor to enter AMDebug technology mode after a hard or soft reset has been asserted to the Am5 86 CPU Writes to this bit are ignored if the AMDebug technology mode is not active The AMDebug technology mode is controlled by the software that drives the AMDebug technology port
308. ct the functionality of the PIO19 pin 0 The pin is PIO19 1 The pin is GPIRQ4 2 PIO18 FNC PIO18 or GPIRQ5 Function Select This bit is used to select the functionality of the PIO18 pin 0 The pin is PIO18 1 The pin is GPIRQ5 1 PIO17 FNC PIO17 or GPIRQ6 Function Select This bit is used to select the functionality of the PIO17 pin 0 The pin is PIO17 1 The pin is GPIRQ6 0 16 PIO16 GPIRQ7 Function Select This bit is used to select the functionality of the PIO16 pin 0 The pin is PIO16 1 The pin is GPIRQ7 Programming Notes This register PIOPFSS31 16 should be written early in the microcontroller s initialization routine The bit values to write depend on which pins are to be used for PIO functions as opposed to interface functions This depends on how the microcontroller is used in each particular system design On reset each PIO pin is an input with a pullup or pulldown resistance for termination See the pin list summary table in the Elan SC520 Microcontroller Data Sheet order 22003 Software writes a 1 to the corresponding bit in this register to change a pin to its interface function For example PIO18 shares a pin with the GP bus GPIRQ5 signal so before GPIRQ5 can be used a 1 must be written to the 18 bit To summarize W Abit must be cleared to use the corresponding pin as a programmable I O pin W Abit must be set to 1 to use the corresponding pin for its interface function
309. cycle is addressed 00h Specifies the PCI bus that is connected to the lanSC520 microcontroller s host bridge This causes the host bridge to perform a type zero configuration cycle Other values The host bridge performs a type one configuration cycle In a type one configuration cycle the contents of this bit field BUS NUM are driven unchanged on the PCI bus during the address phase of the cycle If the BUS NUM and DEVICE bit fields are both 0 the configuration cycle does not appear on the PCI bus because this combination addresses the internal PCl indexed registers of the host bridge Elan SC520 Microcontroller Register Set Manual 6 15 PCI Bus Host Bridge Registers Bit Name Function 15 11 DEVICE_NUM Device Number 4 0 This bit field specifies the device to address on the bus that is specified by the BUS NUM bit field For type zero configuration cycles if the BUS NUM bit field is 00h the DEVICE NUM bit field value selects of the following bit patterns to be driven on the PCI bus AD31 AD11 pins during the address phase of the cycle 00d Address the lanSC520 microcontroller s host bridge if the BUS NUM bit field is 00h The cycle is not visible on the PCI bus l e no bit pattern is driven externally 01d The AD12 pin is driven High and the other pins of AD31 AD11 are driven Low 02d The AD13 pin is driven High and the other pins of AD31 AD11 are driven Low The 0
310. d 1 The IR4 input is asserted Interrupt Request 3 0 The IR3 input to the Slave 1 PIC is not asserted 1 2 The IR3 input is asserted Interrupt Request 2 0 The IR2 input to the Slave 1 PIC is not asserted 1 The IR2 input is asserted Interrupt Request 1 0 The IR1 input to the Slave 1 PIC is not asserted 1 2 The IR1 input is asserted Interrupt Request 0 0 The IRO input to the Slave 1 PIC is not asserted 1 2 The IRO input is asserted This register S1PICIR is accessed by first writing a value of OAh to Port 00AOh followed by a read back from Port 00AO0h If the S2 bit in the MPICICWS register is cleared see page 12 34 then the Slave 1 controller is bypassed and any interrupt requests latched in this register S1PICIR are not propagated to the CPU Elan SC520 Microcontroller Register Set Manual 12 49 AMD Slave 1 PIC In Service S1PICISR Programmable Interrupt Controller Registers Direct Mapped Address 00AOh 7 6 5 4 3 2 1 0 Bit IS7 156 155 154 153 152 151 ISO Reset x x x x x x x x R W R Register Description This register indicates the Slave 1 interrupt priority levels that are being serviced Bit Definitions Bit Name Function 7 IS7 Interrupt Request 7 In Service 0 Interrupt request 7 is not being serviced 1 Interrupt request 7 is being serviced 6 IS6 Interrupt Request 6 In Service 0 Interrupt request 6 is not being serviced
311. d 6 20 SL EOI bit field in MPICOCW2 register 12 28 in S1PICOCW2 register 12 53 in S2PICOCW2 register 12 41 ABT bit field 6 20 RAB ENB bit field 8 2 RAS CAS DLY bit field 7 4 RAS PCHG DLY bit field 7 4 Rate Selection bit field 17 15 RATE SEL bit field 17 15 RBR bit field 18 8 Read or Write the PIOx Pin bit field in PIODATA15 0 register 20 16 20 17 in PIODATA31 16 register 20 18 20 19 Read Ahead Feature Enable bit field 8 2 Read back Command bit field 13 11 real time clock direct mapped registers table 17 1 indexed registers table 1 11 17 1 Received Master Abort bit field 6 20 Received Target Abort bit field 6 20 Receiver FIFO Clear bit field in UARTXFCR register 18 15 in UARTxFCRSHAD register 18 5 Receiver FIFO Register Trigger Bits bit field in UARTXFCR register 18 15 in UARTxFCRSHAD register 18 5 Refresh Enable bit field 7 2 Region Size Start Address bit field 2 8 Register Number bit field 6 16 REGISTER NUM bit field 6 16 Index 16 Index REQDMA bit field in MSTDMASWREQ register 11 89 SLDMASWREQ register 11 53 REQSEL bit field in MSTDMASWREQ register 11 89 in SLDMASWREQ register 11 53 Request To Send bit field 18 20 REQx signal 5 4 5 5 5 7 REQx ENB bit field 5 4 5 5 RESCFG register 3 3 Reset Configuration register 3 3 reset generation direct mapped registers table 3 1 MMCR registers table 3 1 reset sources table 3 6 Reset Latched In
312. d decimal BCD formats 0 RTC time and calendar data use BCD encoding 1 RTC time and calendar data use binary encoding Neither internal functions nor RTC only resets affect this bit The RTC time and date configuration registers RTC indexes 0 9h must be reinitialized after software changes the DATE_MODE bit Software should set the SET bit to 1 before changing the DATE_MODE bit and then clear the SET bit afterward 12 24 Hour Mode Select The HOUR_MODE_SEL bit selects whether the hours registers use 12 or 24 hour format 0 RTC hours registers use 12 hour format The AM PM bit of each hours register represents PM when 1 and AM when 0 1 hours registers use 24 hour format Neither internal functions nor RTC only resets affect this bit The RTCCURHR page 17 8 and RTCALMHR page 17 9 registers must be reinitialized after software changes the HOUR_MODE_SEL bit Software should set the SET bit to 1 before changing the HOUR_MODE_SEL bit and then clear the SET bit afterward Daylight Savings Enable The DS_ENB bit enables special daylight savings time updates 0 Special daylight savings time updates do not occur 1 Two special time updates occur automatically when this bit is 1 On the first Sunday in April the time reading that follows 1 59 59 AM is 3 00 00 AM On the last Sunday in October the time reading that follows 1 59 59 AM is 1 00 00 AM Neither internal functions nor RTC only resets affect this bit
313. der 18497 includes the complete instruction set for the integrated Am5 86 CPU Am5x860 Microprocessor Family Data Sheet order 19751 Am486 DX DX2 Microprocessor Hardware Reference Manual order 17965 B 86 Family Products and Development Tools CD order 21058 provides a single source multimedia tool for customer evaluation of AMD products as well as FusionE86 partner tools and technologies that support the E86 family Technical documentation is included on the CD in PDF format To order literature contact the nearest AMD sales office or call the literature center at one of the numbers listed on the back cover of this manual In addition all these documents are available in PDF form on the AMD web site To access the AMD home page go to www amd com Then follow the Embedded Processor link for information about AMD s E86 family of microcontrollers Elan SC520 Microcontroller Register Set Manual Introduction AMD Additional Information The following non AMD documents and sources provide additional information that may be of interest to ElanSC520 microcontroller users PCI Local Bus Specification Revision 2 2 December 18 1998 PCI Special Interest Group 800 433 5177 US 503 693 6360 International www pcisig com IEEE Std 1149 1 1990 Standard Test Access Port and Boundary Scan Architecture order SH16626 NYF Institute of Electrical and Electronic Engineers Inc 800 678 4333 www ieee org PCI System
314. disabled This bit can only be modified set or cleared via software if the P ENB bit of this register is set i e written as 1 during the same write cycle access to this register The ENB bit is automatically cleared by hardware under certain circumstances if noncontinuous mode is selected See the CONT bit description on page 14 11 GP Timer 1 Permit Enable Bit Write 0 Software cannot modify the ENB bit in this write cycle 1 Software can modify the ENB bit in this write cycle This bit allows selective software modifications of the ENB bit When the P WR bit is set during a write cycle access to this register the ENB bit can be modified in that same write cycle When the P ENB Wh bit is written as a 0 during a write cycle access to this register the ENB bit cannot be modified This bit is always read back as a 0 14 9 AMD Bit 13 12 11 6 14 10 Name INT ENB MAX CNT RIU Reserved MAX CNT RTG General Purpose Timer Registers Function GP Timer 1 Interrupt Enable This bit allows the timer to generate an interrupt when the timer counter value reaches a maximum count compare register value 0 Timer 1 interrupt request generation is disabled 1 GP Timer 1 interrupt request generation is enabled If the INT ENB bit is 1 the T1 INT STA bit is set in the GPTMRSTA register see page 14 2 and an interrupt is generated when one of the following conditions occurs The
315. dnesday 5d Thursday 6d Friday 7d Saturday If a value greater than 7d is programmed the bit field value increments up to FFh wraps around to 0 and only then does the value remain within the valid range Programming Notes Software can suspend updating of the RTC via the SET bit in the RTCCTLB register see page 17 16 Software selects binary or BCD format via the DATE MODE bit in the RTCCTLB register 17 10 Elan SC520 Microcontroller Register Set Manual Real Time Clock Registers AMDA RTC Current Day of the Month RTCCURDOM Address 70h 71h RTC Index 07h 7 6 5 4 3 2 1 0 Bit DAY_OF_MTH 7 0 Reset X X X X X X X X R W R W Register Description This register used to initialize and read back the RTC current day of the month Bit Definitions Bit Name Function 7 0 DAY OF MTH RTC Current Day of the Month 7 0 Software initializes the day of month value for the RTC by writing data to this bit field in either binary or binary coded decimal BCD formats The RTC logic updates this bit field once per second Valid values for this bit field range from 1 to 31 However a value in this range is considered invalid if it is inappropriate for the month programmed in the MONTH bit field in the RTCCURMON register see page 17 12 If a value greater than the number of days in the current month is programmed the bit field value increments up to FFh wraps around to 0 and only t
316. e This read only bit indicates the host bridge is not 66 MHz capable 0 The host bridge is not 66 MHz capable Reserved This bit field should be written to 0 for normal system operation SERR Enable This bit is normally used to enable the PCI bus agent to drive the SERR pin however the host bridge does not drive the SERR pin because all interrupt control is integrated within the ElanSC520 microcontroller 0 The SERR pin is not driven by the lanSC520 microcontroller This bit is internally fixed to 0 Reserved This bit field should be written to O for normal system operation Elan SC520 Microcontroller Register Set Manual Programming Notes Bit Name 6 PERR_RES 5 3 Reserved 2 BUS_MAS 1 MEM_ENB 0 lO ENB PCI Bus Host Bridge Registers AMDA Function Parity Error Response This bit controls the host bridge s response to parity errors 0 The host bridge master and target controllers ignore parity errors The host bridge treats transactions that have a parity error address or data as normal transactions In other words it behaves as if nothing is wrong The D_PERR_DET bit see page 6 20 is not set for data parity errors and a target abort is not issued for address parity errors 1 The host bridge master and target controllers report parity errors The host bridge responds to data parity errors by setting the D_PERR_DET bit The host bridge target controller responds to address parity errors by termi
317. e Number page 11 19 GP DMA Channel 7 Extended Transfer Count GPDMAEXTTC7 page 11 20 Buffer Chaining Control GPDMABCCTL page 11 21 Buffer Chaining Status GPDMABCSTA page 11 22 Buffer Chaining Interrupt Enable GPDMABSINTENB page 11 24 Buffer Chaining Valid GPDMABCVAL page 11 25 GP DMA Channel 3 Next Address Low GPDMANXTADDL3 page 11 26 GP DMA Channel 3 Next Address High GPDMANXTADDH3 page 11 27 GP DMA Channel 5 Next Address Low GPDMANXTADDL5 page 11 28 GP DMA Channel 5 Next Address High GPDMANXTADDH5 page 11 29 GP DMA Channel 6 Next Address Low GPDMANXTADDL6 page 11 30 GP DMA Channel 6 Next Address High GPDMANXTADDH6 page 11 31 GP DMA Channel 7 Next Address Low GPDMANXTADDL7 page 11 32 GP DMA Channel 7 Next Address High GPDMANXTADDH7 page 11 33 GP DMA Channel 3 Next Transfer Count Low GPDMANXTTCL3 page 11 34 GP DMA Channel 3 Next Transfer Count High GPDMANXTTCHS page 11 35 GP DMA Channel 5 Next Transfer Count Low GPDMANXTTCL5 page 11 36 GP DMA Channel 5 Next Transfer Count High GPDMANXTTCH5 page 11 37 GP DMA Channel 6 Next Transfer Count Low GPDMANXTTCL6 page 11 38 GP DMA Channel 6 Next Transfer Count High GPDMANXTTCH6 page 11 39 GP DMA Channel 7 Next Transfer Count Low GPDMANXTTCL7 page 11 40 GP DMA Channel 7 Next Transfer Count H
318. e depend on which function is to be used for each pin This depends on how the microcontroller is used in each particular system design On reset each pin s primary function is selected See the pin list summary table in the Elan SC520 Microcontroller Data Sheet order 22003 Software writes a 1 to the corresponding bit in this register to change a pin to its alternate function For example TMROUTO shares a pin with the GP bus GPCS7 signal so before GPCS7 can be used a 1 must be written to the GPCS7 SEL bit To summarize W Abit must be cleared to use the corresponding pin for its primary function W Abit must be set to 1 to use the corresponding pin for its alternate function 20 8 Elan SC520 Microcontroller Register Set Manual Clock Select CLKSEL Register Description AMD Programmable Input Output Registers Memory Mapped MMCR Offset C26h 7 6 5 4 3 2 1 0 CLK_PIN_ CLK_PIN Bit Reserved CLK_TST_SEL 2 0 Reserved DIR ENB Reset 0 1 1 1 0 0 0 0 R W RSV R W RSV R W R W This register is used to set up the CLKTIMER CLKTEST pin Bit Definitions Bit 7 6 4 Name Reserved CLK_TST_ SEL 2 0 Reserved CLK_PIN_DIR CLK_PIN_ ENB Programming Notes The CLKTIMER CLKTEST pin can be configured as an output CLKTEST to drive any of the several internal clocks externally for testing or to drive an external device Caution should be exercised because there
319. e DMA request is deasserted Masking an active channel while it is being granted might cause the system to hang 11 60 Elan SC520 Microcontroller Register Set Manual Slave DMA General Mask SLDMAGENMSK GP DMA Controller Registers AMD Direct Mapped Address OOOFh 3 2 1 0 Bit Reserved CH3_DIS CH2 DIS CH1 DIS CHO DIS Reset 1 1 1 1 R W RSV W W W W Register Description This register provides a mechanism to mask or unmask the DMA request signal to each of Channels 0 3 Bit Definitions Bit Name Function 7 4 Reserved Reserved This bit field should be written to 0 for normal system operation DMA Channel 3 Mask 0 Enable DMA Channel 3 for servicing DMA requests 3 CH3_DIS 1 Disable DMA Channel 3 from servicing DMA requests DMA Channel 2 Mask 0 Enable DMA Channel 2 for servicing DMA requests 2 CH2_DIS 1 Disable DMA Channel 2 from servicing DMA requests 1 CH1_DIS DMA Channel 1 Mask 0 Enable DMA Channel 1 for servicing DMA requests 1 Disable DMA Channel 1 from servicing DMA requests 0 CHO_DIS DMA Channel 0 Mask 0 Enable DMA Channel 0 for servicing DMA requests 1 Disable DMA Channel 0 from servicing DMA requests Programming Notes The same DMA channel masks can be controlled via DMA registers SLDMAMSK see page 11 54 SEDMAMSKRST see page 11 60 and SLDMAGENMSK Before masking an active DMA channel software must ensure that the DMA reque
320. e DRAM refresh and the speaker respectively 100b Mode 4 Software retriggerable strobe When the count is loaded the counter output transitions to 1 When count transitions to 0 the counter output transitions to 0 for one clock period and then transitions to 1 101b Mode 5 Hardware retriggerable strobe Available for PIT Channel 2 only The counter output behaves just as in mode 4 except that the triggering is done on a Low to High transition of the internal gate 2 signal controlled by the PITGATE2 signal or the PIT_GATE2 bit of the SYSCTLB register see page 13 13 A trigger seen during the count reloads the count to the initial value and then counting continues Same as mode 2 Notes Same as mode 3 1 Modes 1 and 5 require a rising edge on the gate input for each timer channel Only PIT Channel 2 has a gate control see the PIT_GATE2 bit in the SYSCTLB register page 13 13 so only PIT Channel 2 is capable of running all modes The gate controls for PIT channels 0 and 1 are fixed internally to 1 so they are capable of operation only in modes 0 2 3 and 4 Elan SC520 Microcontroller Register Set Manual 13 9 AMDA Programmable Interval Timer Registers PIT Counter Latch Command PITCNTLAT Direct Mapped 1 0 Address 0043h 7 6 5 4 3 2 1 0 Bit CTR_SEL 1 0 CTR_CMD 1 0 Reserved Reset 0 0 0 0 0 0 0 0 R W W RSV Register Description This register
321. e PIC in the system S2PICICW3 is not expected not valid in the ElanSC520 microcontroller In the ElanSC520 microcontroller design this bit is internally fixed to 0 Because this bit is internally fixed to 0 software must always write the S2PICICWS3 register after writing S1PICICW2 See the programming notes on this page for details 0 IC4 Initialization Control Word 4 Software uses this bit to indicate whether it intends to explicitly program the S2PICICW4 register see page 12 47 after writing to the S2PICICWS register see page 12 46 See the programming notes on this page for details 0 The S2PICICWA register is initialized internally when this register S2PICICW1 is written The PIC does not expect software to write to the S2PICICWA register 1 2 The S2PICICWA register is not initialized by the write to this register S2PICICW1 Software is expected to initialize the S2PICICWA register after writing to the S2PICICW3 register Programming Notes The PIC s initialization control word S2PICICWX registers 1 4 must be programmed in sequence Writing to Port 0024h with bit 4 1 causes the S2PICICW1 register to be written and also resets the PIC s internal state machine and the internal S2PICICWX register pointer Then S2PICICWx registers 2 4 can be programmed by sequential writes to Port 0025h Each time Port 0025h is written to following the write to S2PICICW1 the internal register pointer points to the next S2PICICWx regi
322. e SLCT_ICW1 bit is cleared 2 0 LS 2 0 Specific EOI Level Select Interrupt level that is acted upon when the SL bit 1 see bits 7 5 of this register 000 IRO 001 IR1 010 IR2 011 IR3 100 IR4 101 IR5 110 IR6 111 IR7 12 28 Elan SC520 Microcontroller Register Set Manual Programmable Interrupt Coniroller Registers AMD Programming Notes I O Port 0020h provides access to different Master PIC registers based on the data that is written Table 12 4 provides a summary of bit patterns to write for access to each register Table 12 4 Master PIC Port 0020h Access Summary Same as Table 12 3 Bits Port 0020h Register Written Next Port 0020h Read Returns 0 x MPICOCW2 page 12 28 x MPICOCWS3 page 12 30 0 1 MPICOCWS MPICIR page 12 24 MPICOCWS MPICISR page 12 25 X MPICICW1 page 12 26 1 x 0 1 1 2 x 0 0 5 0 0 0 lan SC520 Microcontroller Register Set Manual 12 29 AMD Programmable Interrupt Controller Registers Master PIC Operation Control Word 3 MPICOCW3 Direct Mapped Address 0020h 7 6 5 4 3 2 1 0 z SLCT_ Bit Reserved ESMM_SMM 1 0 ICW1 IS OCWS3 P RR RIS 1 0 Reset x 1 x x x R W RSV Register Description This register controls the PIC s mask and poll modes It also controls read access for the MPICIR and MPICI
323. e a one shot system reset event to be generated Setting the SYS_RST bit also causes GP bus and PCI Bus resets to be generated If the PRG bit is 1 setting the SYS bit results in a system reset in which the SDRAM configuration is maintained Programming Notes After a PWRGOOD reset the programmable system reset feature is disabled and can be enabled only by software writing a 1 to the PRG_RST_ENB bit If the PRGRESET pin is asserted after it has been enabled as a programmable reset it causes a programmable reset which does not reset the SDRAM controller configuration or contents This allows the contents of SDRAM to be preserved The PWRGOOD pin always has higher priority than the PRGRESET pin For example if the PRGRESET pin is asserted and PWRGOOD deasserted PWRGOOD is serviced and the PWRGOOD reset event disables the PRGRESET function Unlike most other registers the bits in this register RESCFG are only returned to their reset value by a PWRGOOD reset They are not cleared by any other kind of reset The AMDebug technology trace information is preserved only if a soft reset is generated to the CPU See the Elan SC520 Microcontroller User s Manual order 22004 for details about reset generation Table 3 3 on page 3 6 provides a summary of ElanSC520 microcontroller reset sources and effects 3 4 Elan SC520 Microcontroller Register Set Manual Reset Status RESSTA Bit Reset R W Reset Generation R
324. e configured to route the interrupt to the appropriate interrupt request level and priority Buffer chaining is enabled separately for each channel the GPDMABCCTL register see page 11 21 11 24 Elan SC520 Microcontroller Register Set Manual Buffer Chaining Valid GPDMABCVAL Bit Reset R W GP DMA Controller Registers AMD Memory Mapped MMCR Offset D9Bh 6 3 2 1 0 Reserved CH7_ CH6_ CH5_ CH3_ CBUF VAL CBUF VAL CBUF VAL CBUF VAL 0 0 0 0 0 RSV R W R W R W R W Register Description This register provides the operating interface with the buffer chaining feature Bit Definitions Bit Name Function 7 4 Reserved Reserved This bit field should be written to 0 for normal system operation 3 CH7 _ Chaining Buffer Valid for Channel 7 VAL 0 The channel s Next Address registers and Next Transfer Count registers are not valid Only hardware can clear this bit Writing a 0 has no effect 1 Software sets this bit to indicate that the values of the channel s Next Address registers and Next Transfer Count registers are valid 2 CH6 Chaining Buffer Valid for Channel 6 VAL 0 The channel s Next Address registers and Next Transfer Count registers are not valid Only hardware can clear this bit Writing a 0 has no effect 1 Software sets this bit to indicate that the values of the channel s Next Address registers and Next Transfer Count registe
325. e current mode See the CTR_MODE_STA bit description on page 13 6 for a list of modes 0 Output is Low 1 Output is High The three PIT outputs can be mapped individually to the microcontroller s internal programmable interrupt controller inputs In addition the PIT Channel 2 output can be enabled to drive the PITOUT2 pin See the PIT OUT2 ENB bit description on page 13 13 Null Count When programming a new count value into one of the timers the new value does not take effect until it has actually been transferred to the counting element which can take some time When attempting to read back a count value software can test this bit to determine whether the read back value is valid or not 0 Counter is available for reading 6 NULL CNT 1 Null count read back of the counter is invalid 5 4 RW 1 0 Counter Read Write Operation Control or Counter Latch Command Reflects the last bit setting that was programmed into the corresponding bits 5 4 of the PITMODECTL or PITCNTLAT register for this PIT channel see page 13 7 and page 13 10 00 Counter Latch command PITCNTLAT register 01 Read write counter bits 7 0 only PITMODECTL register 10 Read write counter bits 15 8 only PITMODECTL register 11 Read write counter bits 7 0 followed immediately by bits 15 8 PITMODECTL register Elan SC520 Microcontroller Register Set Manual 13 5 AMD Bit 3 1 Name CTR MODE STA 2 0 BCD Program
326. e cycle Both of these conditions are required for the write to take effect Elan SC520 Microcontroller Register Set Manual 2 9 System Address Mapping Registers Bit Name Function 11 8 Reserved Reserved This bit field should be written to 0 for normal system operation 7 0 MATCH 7 0 Match The bit field is used to prevent illegal writes to this register The data pattern written to this byte must be CBh If any other data pattern is written to these bits the entire 32 bit write is ignored This bit field returns 0 when read Programming Notes This register must be written as a full 32 bit doubleword When the MMCR alias is enabled the 4 Kbyte address range to which the alias is mapped becomes the MMCR regardless of any PARx registers that are enabled in the same 4 Kbyte address range In effect the MMCR alias has higher priority than any of the PARx windows that are enabled 2 10 Elan SC520 Microcontroller Register Set Manual QAwna AMD 3 3 1 3 2 Table 3 1 Table 3 2 RESET GENERATION REGISTERS OVERVIEW This chapter describes the reset generation and reset related registers of the lanSC520 microcontroller The lanSC520 microcontroller provides several microcontroller specific and PC AT compatible reset functions The reset generation register set includes two groups of registers Three memory mapped configuration region MMCR registers are used to provide system board
327. e default state after a system reset See the Elan SC520 Microcontroller User s Manual order 22004 for information about PCI bus initialization 6 24 Elan SC520 Microcontroller Register Set Manual CHAPTER ee Te AMD 1 7 7 1 7 2 Table 7 1 SDRAM CONTROLLER REGISTERS OVERVIEW This chapter describes the synchronous dynamic random access memory SDRAM controller registers of the ElanSC520 microcontroller The ElanSC520 microcontroller includes an integrated SDRAM controller The following are some of the SDRAM controller s main features Synchronous DRAM support iM Support for up to 4 banks E Up to 256 Megabytes of SDRAM B ECC single bit correction multiple bit detection support The SDRAM controller register set consists of ten memory mapped configuration region MMCR registers used for configuration control and status See the Elan SC520 Microcontroller User s Manual order 22004 for details about using the SDRAM controller Table 7 1 lists the SDRAM controller registers in offset order with the corresponding description s page number REGISTERS SDRAM Controller MMCR Registers Page Register Name Mnemonic MMCR Offset Number SDRAM Control DRCCTL page 7 2 SDRAM Timing Control DRCTMCTL page 7 4 SDRAM Bank Configuration DRCCFG page 7 5 SDRAM Bank 0 3 Ending Address DRCBENDADR page 7 7 ECC Control ECCCTL page 7 9 ECC Status ECCSTA page 7 10 ECC Check Bit Position ECCCKBPOS
328. e found in the following register descriptions W Software Interrupt 16 1 Control page 12 10 Software Interrupt 22 17 NMI Control page 12 13 PCI Host Bridge Interrupt Mapping page 12 17 ECC Interrupt Mapping page 12 19 Other interrupt mapping registers 30 page 12 21 12 20 Elan SC520 Microcontroller Register Set Manual Programmable Interrupt Coniroller Registers GP Timer O Interrupt Mapping GPTMROMAP GP Timer 1 Interrupt Mapping GPTMR1MAP GP Timer 2 Interrupt Mapping GPTMR2MAP PIT O Interrupt Mapping PITOMAP PIT 1 Interrupt Mapping PIT1MAP PIT 2 Interrupt Mapping PIT2MAP UART 1 Interrupt Mapping UART1MAP UART 2 Interrupt Mapping UART2MAP PCI Interrupt A Mapping PCIINTAMAP PCI Interrupt B Mapping PCIINTBMAP PCI Interrupt C Mapping PCIINTCMAP PCI Interrupt D Mapping PCIINTDMAP DMA Buffer Chaining Interrupt Mapping DMABCINTMAP SSI Interrupt Mapping SSIMAP Watchdog Timer Interrupt Mapping WDTMAP RTC Interrupt Mapping RTCMAP Write Protect Violation Interrupt Mapping WPVMAP AMDebug Technology RX TX Interrupt Mapping ICEMAP Floating Point Error Interrupt Mapping FERRMAP GPIRQO Interrupt Mapping GPOIMAP GPIRQ1 Interrupt Mapping GP1IMAP GPIRQ2 Interrupt Mapping GP2IMAP GPIRQ3 Interrupt Mapping GP3IMAP GPIRQ4 Interrupt Mapping GP4IMAP GPIRG5 Interrupt Mapping GP5IMAP GPIRQ6 Interrupt Mapping GPGIMAP GPIRQ7 Interrupt Mapping GP7IMAP GPIRGS Interrupt Mapping
329. e page 20 14 Writing 1 to a pin s PIOx CLR bit overrides any previous write to the pin s PIOx DATA or SET bit see page 20 18 and page 20 22 Writing 0 to any bit in this register has no effect If a PIO pin is programmed to be an input or if the pin is programmed for its interface function via the corresponding PIOx FNC bit in the PIOPFSS31 16 register see page 20 5 then writing to the pin s PIOx CLR bit has no effect Although software can perform a 32 bit access of MMCR offset C38h to clear bits across all 32 PIO pins with a single instruction the 32 bit access is split into two separate 16 bit accesses with the PIOCLR15 Oregister being accessed prior to the PIOCLR31_16 register The two writes are not simultaneous Elan SC520 Microcontroller Register Set Manual 20 27 AM DA Programmable Input Output Registers 20 28 Elan SC520 Microcontroller Register Set Manual INDEX Numerics 12 24 Hour Mode Select bit field 17 17 16550 Compatible Mode Error bit field 18 21 16 bit Counter for Programmable Interval Timer Channel 0 bit field 13 2 Channel 1 bit field 13 3 Channel 2 bit field 13 4 16 bit Millisecond Count bit field 15 2 66 MHz Capable bit field 6 20 66M_CAP bit field 6 20 A A10 A8 bit field in MPICICW2 register 12 32 in S1PICICW2 register 12 57 in S2PICICW2 register 12 45 A10 A8 of Interrupt Vector bit field in MPICICW2 register 12 32 in S1PICICW2 register 12 57 in S2PICICW2 register 12
330. e signal that would normally be driven by an external PC AT compatible system control processor SCP In order to maintain software compatibility internal logic is provided to watch the GP bus for SCP a20 gate pin control command sequences Following a write of D1h to the SCPCMD register see page 3 8 a write to this bit A20_GATE has the following effect 0 Internal a20 propagation is disabled address space wraps at 1 Mbyte 1 2 Internal a20 propagation is enabled addresses above 1 Mbyte can be accessed This bit 20 provides one of two sources of a20 gate control The other source is the A20G bit in the SYSCTLA register see page 3 9 A logical OR of these two sources is used to drive the Am5 86 CPU a20m signal Therefore a20 propagates if either source enables a20 to propagate Note that this bit A20 GATE defaults to enabling a20 propagation 0 CPU RST CPU Reset Control On the ElanSC520 microcontroller writing to this bit has no effect On a PC AT compatible system setting this bit to 1 after a write of D1h to the SCP Command Port SCPCMD register would hold the system in reset indefinitely Programming Notes There is no internal storage element associated with this address All accesses to this address go to the GP bus Additionally writes to this address are snooped by the ElanSC520 microcontroller Elan SC520 Microcontroller Register Set Manual 3 7 AMD Reset Generation Registers SCP
331. e written to O for normal system operation 4 lO HOLE Hole Access Destination DEST This bit determines the destination of accesses performed by the Am5 86 CPU to certain I O addresses in the range 0000h to O3FFh 0 The accesses are forwarded to the external GP bus default 1 The accesses are forwarded to the PCI bus I O space I O addresses in the range 0000h to OSFFh that are not occupied by the internal GP bus peripherals are normally reserved for PC AT compatible peripherals Such addresses are referred to as holes in the I O address space See the memory and I O chapter of the Elan SC520 Microcontroller User s Manual order 22004 for details about these holes If a PARx register see page 2 6 is configured to address GP bus I O space within a hole accesses in the defined region are forwarded to the GP bus regardless of the IO DEST bit value The PARx window must not overlap any of the internal peripherals direct mapped I O addresses 3 Reserved Reserved This bit field should be written to 0 for normal system operation 2 2 Elan SC520 Microcontroller Register Set Manual System Address Mapping Registers AMDA Bit Name Function 2 RTC_DIS RTC Disable This bit causes the integrated RTC to be disabled 0 The integrated RTC is enabled 1 The integrated RTC is not used and accesses to the RTC address space are forwarded externally to the GP bus When the internal RTC is disabled the corresponding inte
332. eceive Buffer 1 UART 2 Baud Clock Divisor Latch LSB UART2BCDL UART 1 Baud Clock Divisor Latch LSB UART1BCDL UART 2 Baud Clock Divisor Latch MSB UART2BCDH UART 1 Baud Clock Divisor Latch MSB UART1BCDH UART 2 Interrupt Enable UART2INTENB UART 1 Interrupt Enable UART1INTENB UART 2 Interrupt ID 2 UART 1 Interrupt ID 1 UART 2 FIFO Control 2 UART 1 FIFO Control UART 2 Line Control UART2LCR UART 1 Line Control UART1LCR UART 2 Modem Control UART2MCR UART 1 Modem Control UART1MCR UART 2 Line Status 2 UART 1 Line Status 15 UART 2 Modem Status 2 5 UART 1 Modem Status 1 5 UART 2 Scratch Pad 25 UART 1 Scratch Pad UART1SCRATCH Elan SC520 Microcontroller Register Set Manual xi AMD Table of Contents CHAPTER 19 SYNCHRONOUS SERIAL INTERFACE REGISTERS 19 1 19 1 OVerVIeW scc ossblog a ex e RR E Eun beRERMEDR ERE 19 1 19 2 Heglste s voie ERE ERG EUER ERE EE EE X RAM 19 1 SS GontrolSSIGTEY a urne tms atre ate d pe p a 19
333. ect Mapped I O Address 000Dh 7 6 5 4 3 2 1 0 Bit SLAVE TMP 7 0 Reset 0 0 0 0 0 0 0 0 R W R Register Description This register has no real use in the lanSC520 microcontroller It is included for compatibility only Bit Definitions Bit Name Function 7 0 SLAVE_TMP Slave DMA Controller Temporary Register 7 0 In a discrete DMA controller this bit field is used as a temporary storage buffer when doing memory to memory DMA Memory to memory DMA transfers are not supported in the ElanSC520 microcontroller so this register is included for compatibility reasons only Programming Notes lan SC520 Microcontroller Register Set Manual 11 59 GP DMA Controller Registers Slave DMA Mask Reset SLDMAMSKRST Direct Mapped Address OOOEh 7 6 5 4 3 1 0 Bit SLAVE_MSK_RST 7 0 Reset X X X X X X X R W W Register Description This register provides a mechanism to reset the SLDMAGENMSK register see page 11 61 Bit Definitions Bit Name Function 7 0 SLAVE MSK Slave DMA Reset Mask RST 7 0 Writing any data to this I O address resets the SLDMAGENMSK register see page 11 61 thereby activating the four slave DMA channels Programming Notes The same DMA channel masks can be controlled via DMA registers SLDMAMSK see page 11 54 SLDMAMSKRST and SLDMAGENMSK see page 11 61 Before masking an active DMA channel software must ensure that th
334. ect signals which can be separately enabled Note that a bank of ROM devices can be accessed with a single chip select e g for building a 32 bit ROM space from four 8 bit ROM devices The ROM controller register set consists of three memory mapped configuration region MMCR registers used to configure the ROM controller by programming details about the connected ROM devices operation mode device width device location and timing Configuration information is provided for each chip select See the Elan SC520 Microcontroller User s Manual order 22004 for details about the ROM controller Table 9 1 lists the ROM controller registers in offset order with the corresponding description s page number REGISTERS ROM Controller MMCR Registers Register Name Mnemonic MMCR Offset Page Number BOOTCS Control BOOTCSCTL ROMCS1 Control ROMCS1CTL ROMCS2 Control ROMCS2CTL Elan SC520 Microcontroller Register Set Manual 9 1 AMD ROM Flash Controller Registers BOOTCS Control BOOTCSCTL Memory Mapped MMCR Offset 50h 15 14 13 12 11 10 9 8 Bit Reserved DGP WIDTH 1 0 MODE Reserved Reset 0 0 0 0 0 R W RSV R R R W RSV 7 6 5 4 3 2 1 0 Bit Reserved SUB DLY 1 0 Reserved FIRST DLY 2 0 Reset 0 0 1 1 0 1 1 1 R W RSV R W RSV R W Register Description This register contains configuration information about the location i e SDRAM bus
335. ed immediately by bits 15 8 See the PITxONT register descriptions starting on page 13 2 Note that if a given PIT counter as specified by the CTR_SEL bit field is programmed for only eight bit accesses i e this CTR RW LATCH bit field is 01b or 10b a subsequent write to the count register automatically clears the eight bits of the associated internal 16 bit counting element that were not explicitly written to Elan SC520 Microcontroller Register Set Manual 13 7 AMDA Programmable Interval Timer Registers Bit Name Function 3 1 CTR_MODE 2 0 Counter Mode When this address Port 0043h is written with bits 7 6 11b and bits 5 4 00b the PITMODECTL register is addressed and these bits control the counter operation 000 Mode 0 Interrupt on terminal count 001 Mode 1 Hardware retriggerable one shot for PIT Channel 2 010 Mode 2 Rate generator 011 Mode 3 Square wave generator 100 Mode 4 Software retriggerable strobe 101 Mode 5 Hardware retriggerable strobe for PIT Channel 2 110 Alias for mode 2 111 Alias for mode 3 See Table 13 2 on page 13 9 for more detail on this bit field 0 BCD Binary Coded Decimal Select When this address Port 0043h is written with bits 7 6 11b and bits 5 4 00b the PITMODECTL register is addressed and this bit controls whether the counter indicated by bits 7 6 of this register counts in binary with a range of O FFFFh or in binary coded decimal BCD with a r
336. ed on the eight odd edges 1 3 5 7 9 11 13 15 of the SSI clock The transaction is complete on the last transition of the SSI clock 1 INV SSI Inverted Clock Mode Enable This bit controls the idle state of the SSI clock The clock idle state is independent of the phase of the SSI clock 0 The clock is not inverted and the idle state is High The SSI clock pulses Low eight times 1 The clock is inverted and the idle state is Low The SSI clock pulses High eight times 0 MSBF ENB SSI Most Significant Bit First Mode Enable This bit controls the bit order of data transfers 0 Bits are transmitted and received least significant bit LSB first In this mode the SSI shifts out the LSB of the transmit byte first The first data bit received is stored in the LSB of the receive register and the last data bit received is stored in the most significant bit of the receive register 1 Bits are transmitted and received most significant bit MSB first In this mode the SSI shifts out the MSB of the transmit byte first The first data bit received is stored in the MSB of the receive register and the last data bit received is stored in the LSB of the receive register The configuration applies to both transmit and receive operations Programming Notes This register should not be written while the BSY bit is set in the SSISTA register see page 19 6 Elan SC520 Microcontroller Register Set Manual 19 3 Synchr
337. eed not reproduce the ECC algorithm Table 7 2 provides a few example ECC check codes that are correct for the associated data Table 7 2 Example ECC Check Codes and Associated Data 00000000 0000000 FFFFFFFF 0000000 000000BC 1111111 A5A5A5A5 1100011 cocococo 0101110 00AB0000 1001100 00BC0000 0100000 Elan SC520 Microcontroller Register Set Manual 7 13 AMD ECC Single Bit Error Address ECCSBADD Register Description SDRAM Controller Registers Memory Mapped MMCR Offset 24h 31 30 29 28 27 26 25 24 Bit Reserved SB ADDR 27 24 Reset 0 0 0 0 0 0 0 0 R W RSV R 23 22 21 20 19 18 17 16 Bit SB ADDR 23 16 Reset 0 0 0 0 0 0 0 0 R W R 15 14 13 12 11 10 9 8 Bit SB ADDR 15 8 Reset 0 0 0 0 0 0 0 0 R W R 7 6 5 4 3 2 1 0 Bit SB ADDR 7 2 Reserved Reset 0 0 0 0 0 0 0 0 R W R RSV This register contains the physical address of the location in SDRAM that caused a single bit ECC error Note A programmable reset does not preserve this register s state Bit Definitions Bit 31 28 27 2 1 0 Name Reserved SB_ADDR 27 2 Reserved Programming Notes Function Reserved This bit field should be written to 0 for normal system operation ECC Single bit Error Address This bit field contains the physical address bits 27 2 of the location wh
338. egister 11 13 GPDMAEXTPG register 11 14 GPDMAEXTPG6 register 11 15 GPDMAEXTPG7 register 11 16 GPDMAEXTTCS register 11 17 GPDMAEXTTC5 register 11 18 GPDMAEXTTCE register 11 19 GPDMAEXTTCT7 register 11 20 GPDMAGRO register 11 62 GPDMAGR1 register 11 66 GPDMAGR2e register 11 67 GPDMAGR3 register 11 68 GPDMAGRA register 11 70 GPDMAGRS5 register 11 74 GPDMAGR6 register 11 75 GPDMAGR7 register 11 76 GPDMAGRS register 11 77 Index GPDMAMMIO register 11 5 GPDMANXTADDHG register 11 27 GPDMANXTADDHS5 register 11 29 GPDMANXTADDHG register 11 31 GPDMANXTADDHT register 11 33 GPDMANXTADDLS register 11 26 GPDMANXTADDLS register 11 28 GPDMANXTADDLS register 11 30 GPDMANXTADDL7 register 11 32 GPDMANXTTCHS register 11 35 GPDMANXTTCHS register 11 37 GPDMANXTTCH6 register 11 39 GPDMANXTTCH register 11 41 GPDMANXTTCL3 register 11 34 GPDMANXTTCLS register 11 36 GPDMANXTTCLS6 register 11 38 GPDMANXTTCL7 register 11 40 GPDRQXx signal Channel Mapping bit field 11 6 11 7 Function Select bit field 20 4 in GPDMAEXTCHMAPA register 11 6 11 7 GPDRQx CHSEL bit field 11 6 11 7 GPECHO register 10 2 GPINTx POL bit field 12 15 12 16 GPIOCS16 Function Select bit field 20 5 GPIOCSx signal 10 4 GPIORD signal Compressed Timing bit field in MSTDMACTL register 11 87 in SLDMACTL register 11 51 in GPCSQUAL register 10 5 10 6 in GPDMAMMIO register 11 5 in GPRDOFF register 10 11 in GPRDW register 10 10 GPIOW
339. egister 11 15 in GPDMAEXTPG7 register 11 16 DMAxMAR bit field in GPDMAOMAR register 11 42 in GPDMAOPG register 11 69 in GPDMA1MAR register 11 44 in GPDMA1PG register 11 65 in GPDMA2MAR register 11 46 in GPDMA2PG register 11 63 in GPDMA3MAR register 11 48 in GPDMASPG register 11 64 in GPDMA4MAR register 11 78 in GPDMA5MAR register 11 80 in GPDMA5PG register 11 73 in GPDMA6MAR register 11 82 in GPDMAGPG register 11 71 in GPDMA7MAR register 11 84 in GPDMA7PG register 11 72 DMAXxTC bit field in GPDMAOTC register 11 43 in GPDMA1TC register 11 45 in GPDMA2TC register 11 47 in GPDMASTC register 11 49 in GPDMA4TC register 11 79 in GPDMASTC register 11 81 in GPDMA6TC register 11 83 in GPDMA7TC register 11 85 in GPDMAEXTTCS register 11 17 in GPDMAEXTTC5 register 11 18 in GPDMAEXTTCE register 11 19 in GPDMAEXTTC7 register 11 20 documentation support iii documentation notation table xviii DR bit field 18 22 DRAM Refresh Indicator bit field 13 13 DRCBENDADR register 7 7 DRCCFG register 7 5 DRCCTL register 7 2 DRCTMCTL register 7 4 Elan SC520 Microcontroller Register Set Manual AMD Index 5 AMD Drive Strength Control register 20 10 DRQSEN bit field in MSTDMACTL register 11 87 in SLDMACTL register 11 51 internal signal 11 51 11 87 DS ENB bit field 17 17 DSCTL register 20 10 DSR bit field 18 23 DSR2 Function Select bit field 20 5
340. egister s state Bit Definitions Bit Name 7 6 Reserved 5 0 ECC CHK POS 5 0 Programming Notes Function Reserved This bit field should be written to 0 for normal system operation ECC Data Bit Position This bit field reports the bit location of the single bit ECC error in either the check bit or data bit field The bit position is captured upon the detection of a single bit error and the bit field is inhibited from capturing subsequent error positions until the SBIT ERR bit in the ECCSTA register is cleared by writing a 1 see page 7 10 The data bit field is 32 bits in length and the check bit field is 7 bits in length Combined these two bit fields form a 39 bit word The POS bit field contains the numbered bit position in this 39 bit word of the bit that caused the single bit error Figure 7 2 relates the encoded bit position to the data and check bit fields Figure 7 2 shows the concatenated check and data bit fields and the corresponding ECC CHK POS values Bit 5 of THE ECC CHK POS bit field can be used to identify whether the check bit field or the data bit field contains the bit error If bit 5 is 0 the error is in the data bit field If bit 5 is 1 the error is in the check bit field Figure 7 2 ECC Check Bit and Data Bit Positions Check Bits Data Bits 7 bit 32 bit 6 0 38 lt gt 32 31 48 M 0 ECC CHK POS Values Elan SC520 M
341. egisters AMD Memory Mapped MMCR Offset D74h 7 6 5 4 3 2 1 0 Reserved SCP_RST_ ICE_HRST_ ICE_SRST_ WDT_RST_ SD_RST_ PRGRST_ PWAGOOD DET DET DET DET DET DET 0 0 0 0 0 0 0 1 RSV R W R W R W R W R W R W R W Register Description This register provides status information on the various reset sources implemented in the ElanSC520 microcontroller emulated system control processor SCP generated reset CPU shutdown AMDebug technology system reset AMDebug technology hard reset watchdog timer PWRGOOD signal and PRGRESET signal Bit Definitions Bit Name Reserved SCP RST DET ICE HRST DET ICE SRST _ DET WDT_RST_ DET Function Reserved This bit field should be written to 0 for normal system operation SCP Reset Detect This bit is set when a soft reset is generated by the SCP emulation logic Software clears this bit by writing a 1 0 No SCP reset was detected 1 The CPU soft reset event was from an SCP reset command See the SCPCMD register description on page 3 8 A soft reset event clears the NMI_ENB bit in the PICICR register see page 12 4 This allows software to initialize the stack pointer before setting the NMI_ENB bit again after a soft reset AMDebug Technology Hard Reset Detect This bit is set when a AMDebug technology hard reset is detected Software clears this bit by writing a 1 0 2 No AMDebug technolog
342. eld immediately after a write to the SLDMACBP register see page 11 57 Bits 15 8 of the channel s memory address can be read from or written to this bit field immediately after memory address bits 7 0 are read from or written to this bit field Programming Notes To ensure that the lower byte of this register GPDMA1MAR is always accessed first software should precede any access to this register with a write to the SLDMACBP register see page 11 57 to clear the slave DMA byte pointer The value in this register GPDMA1MAR is used with the values in the GPDMA1 PG register see page 11 65 and the GPDMAEXTPG 1 register see page 11 11 to generate DMA address bits 27 0 11 44 Elan SC520 Microcontroller Register Set Manual GP DMA Controller Registers AMDA Slave DMA Channel 1 Transfer Count GPDMA1TC Direct Mapped 1 0 Address 0003h 7 6 5 4 3 2 1 0 Bit DMA1TC 15 0 Reset X X X X X X X X R W Register Description This register contains bits 15 0 of the transfer count for Channel 1 during DMA operation Bit Definitions Bit Name Function 7 0 DMA1TC DMA Channel 1 Transfer Count 16 Bit Register 15 0 This 8 bit field is used two successive I O accesses to read or write the channel s transfer count bits 15 0 Bits 7 0 of the channel s transfer count can be read from or written to this bit field immediately after a write to the SLDMACBP register see page 11 57
343. em designer must ensure that the GP bus timing is not faster than that shown in Table 10 2 The table shows the minimum GP bus timing register values allowed in echo mode See the corresponding register descriptions beginning on page 10 7 Table 10 2 GP Bus Echo Mode Minimum Timing Offset Pulse Width Register Recovery Time Signal Type Register Value Register Value GP Chip Select GP Read GP Write GPALE Notes 1 The actual time value is the register value plus one Times are in units of one internal 33 MHz clock period 10 2 Elan SC520 Microcontroller Register Set Manual GP Chip Select Data Width GPCSDW Register Description General Purpose Bus Controller Registers AMD Memory Mapped MMCR Offset CO1h 7 6 5 4 3 2 1 0 Bit GPCS7_ GPCS6_ GPCS5_ GPCS4_ GPCS3_ GPCS2_ GPCS1_ GPCSO DW DW DW DW DW DW DW DW Reset 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W This register is used to select the default data width for each of the eight GP bus chip selects Bit Definitions Bit Name GPCS7_DW GPCS6_DW GPCS5_DW GPCS4 DW GPCSS8 DW GPCS2 DW GPCS1 DW GPCSO DW Function Data Width Select for GPCS7 This bit is used to select the default data width for the GP bus chip select 7 signal 0 8 bit data 1216 bit data Data Width Select for GPCS6 This bit is used to select the default data width for the GP bus chip select 6 signal
344. em operation Multi Bit Error Detected 0 The event has not occurred or software cleared this bit by writing a 1 1 A multi bit ECC error has occurred Software must write a 1 to clear this bit and rearm the logic that captures the physical address where the multi bit error occurred The multi bit error physical address can be read from the ECCMBADD register see page 7 15 Single bit ECC Error 0 The event has not occurred or software cleared this bit by writing a 1 1 A single bit ECC error has occurred Software must write a 1 to clear this bit and rearm the logic that captures the physical address and bit position where the single bit error occurred The single bit error physical address can be read from the ECCSBADD register see page 7 14 The single bit error bit position can be read from the ECCCKBPOS register see page 7 11 Software should write to this register ECCSTA only to clear the error status and only after a status bit was read as 1 7 10 Elan SC520 Microcontroller Register Set Manual SDRAM Controller Registers AMDA ECC Check Bit Position ECCCKBPOS Memory Mapped MMCR Offset 22h 7 6 5 4 3 2 1 0 Bit Reserved ECC CHK POS 5 0 Reset 0 0 0 0 0 0 0 0 R W RSV R Register Description This register indicates the particular bit in the 32 bit data word or 7 bit check word that caused the single bit error Note A programmable reset does not preserve this r
345. em operation Programming Notes 11 88 Elan SC520 Microcontroller Register Set Manual Master Software DRQ n Request MSTDMASWREQ Register Description GP DMA Controller Registers AMD Direct Mapped I O Address 00D2h 7 6 5 2 1 0 Bit Reserved REQDMA REQSEL 1 0 Reset 0 0 0 X x x R W RSV W This register is used to initiate a software DMA request for one of Channels 4 7 Bit Definitions Function Reserved Bit Name 7 3 Reserved 2 REQDMA 1 0 REQSEL 1 0 Programming Notes This bit field should be written to 0 for normal system operation Software DMA Request 0 Clear the request bit for the channel selected by the REQSEL bit field 1 Set the request bit for the channel selected by the REQSEL bit field The request bit is cleared internally after the corresponding channel has reached the end of its transfer count DMA Channel Select This bit field selects DMA channel that is to latch the REQDMA bit internally to assert or deassert a DMA request via software 00 Select Channel 4 for internal DMA request per the REQDMA bit 01 Select Channel 5 for internal DMA request per the REQDMA bit 10 Select Channel 6 for internal DMA request per the REQDMA bit 11 Select Channel 7 for internal DMA request per the REQDMA bit Elan SC520 Microcontroller Register Set Manual 11 89 AMD Master DMA Channel 4 7 Mask MSTDMAMSK Register Description
346. en the timer count reaches the GPTMROMAXCMPB register value the timer clears its count value clears the ENB bit and then halts Elan SC520 Microcontroller Register Set Manual 14 5 General Purpose Timer Registers GP Timer O Count GPTMROCNT Memory Mapped MMCR Offset C74h 15 14 13 12 11 10 9 8 Bit CNT 15 8 Reset 0 0 0 0 0 0 0 0 R W R W 7 6 5 4 3 2 1 0 Bit CNT 7 0 Reset 0 0 0 0 0 0 0 0 R W R W Register Description This register contains the current count of GP Timer 0 Bit Definitions Bit Name Function 15 0 CNT 15 0 GP Timer 0 Count Register This bit field contains the current count of GP Timer 0 The count rate depends on the value of the PSC_SEL and EXT_CLK bits in the GPTMROCTL register see page 14 5 and page 14 5 Ifthe EXT CLK and PSC SEL bits are both 0 the count is incremented every fourth processor clock cycle Ifthe EXT CLK bit is 0 and the PSC_SEL bit is 1 the count is incremented each time the GP Timer 2 maxcount is reached Ifthe EXT CLK bit is 1 the count is incremented on every positive edge driven on the TMRINO input pin up to 1 4 of the CPU clock speed This register GPTMROCNT can be read at any time to determine the remaining count duration until a maximum count value is reached at which time this register is reset by hardware This register can also be written at any time If this register is
347. er and to set up the memory address and transfer count for each channel See the Elan SC520 Microcontroller User s Manual order 22004 for details about the GP bus DMA controller Table 11 1 and Table 11 2 list each type of GP bus DMA register in offset order with the corresponding description s page number REGISTERS GP DMA MMCR Registers Page Register Name GP DMA Control Mnemonic GPDMACTL MMCR Offset Number page 11 4 GP DMA Memory Mapped I O GPDMAMMIO page 11 5 GPDMAEXTCHMAPA GPDMAEXTCHMAPB GPDMAEXTPGO GPDMAEXTPG1 GPDMAEXTPG2 GPDMAEXTPG3 GPDMAEXTPG5 GPDMAEXTPG6 GPDMAEXTPG7 GPDMAEXTTC3 GP DMA Resource Channel Map A GP DMA Resource Channel Map B GP DMA Channel 0 Extended Page GP DMA Channel 1 Extended Page GP DMA Channel 2 Extended Page GP DMA Channel 3 Extended Page GP DMA Channel 5 Extended Page GP DMA Channel 6 Extended Page GP DMA Channel 7 Extended Page GP DMA Channel 3 Extended Transfer Count GP DMA Channel 5 Extended Transfer Count page 11 6 page 11 8 page 11 10 page 11 11 page 11 12 page 11 13 page 11 14 page 11 15 page 11 16 page 11 17 GPDMAEXTTC5 page 11 18 Elan SC520 Microcontroller Register Set Manual AMD Table 11 1 Table 11 2 GP DMA Controller Registers GP DMA MMCR Registers Continued Register Name GP DMA Channel 6 Extended Transfer Count Mnemonic GPDMAEXTTC6 MMCR Offset Pag
348. er see page 11 57 Bits 15 8 of the channel s memory address can be read from or written to this bit field immediately after memory address bits 7 0 are read from or written to this bit field Programming Notes To ensure that the lower byte of this register GPDMAOMAR is always accessed first software should precede any access to this register with a write to the SLDMACBP register see page 11 57 to clear the slave DMA byte pointer The value in this register GPDMAOMAR is used with the values in the GPDMAOPG register see page 11 69 and the GPDMAEXTPGO register see page 11 10 to generate DMA address bits 27 0 11 42 Elan SC520 Microcontroller Register Set Manual GP DMA Controller Registers AMDA Slave DMA Channel 0 Transfer Count GPDMAOTC Direct Mapped Address 0001h 7 6 5 4 3 2 1 0 Bit 15 0 Reset X X X X X X X X RW RW Register Description This register contains bits 15 0 of the transfer count for Channel 0 during DMA operation Bit Definitions Bit Name Function 7 0 DMAOTC DMA Channel 0 Transfer Count 16 Bit Register 15 0 This 8 bit field is used two successive I O accesses to read or write the channel s transfer count bits 15 0 Bits 7 0 of the channel s transfer count can be read from or written to this bit field immediately after a write to the SLDMACBP register see page 11 57 Bits 15 8 of the channel s transfer count can be
349. er Set Manual 19 1 Synchronous Serial Interface Registers SSI Control SSICTL Memory Mapped MMCR Offset CDOh 7 6 5 4 3 2 1 0 TC INT PHS INV CLK INV Bit Reserved CLK SEL 2 0 ENB ENB ENB MSBF ENB Reset 0 0 0 0 0 0 0 0 R W RSV R W R W R W R W R W Register Description This register controls the bit order clock idle state clock phase for data drive and latch interrupt enable and clock speed of the SSI Bit Definitions Bit Name Function 7 Reserved Reserved This bit field should be written to 0 for normal system operation 6 4 CLK SEL 2 0 SSI Clock Speed Select The SSI clock SSI_CLK pin frequency is derived from the system clock The CLK SEL bit field selects the frequency of the SSI clock as shown in Table 19 2 Table 19 2 SSI Clock Speed Selections Actual Bit Rate with a Actual Bit Rate with a CLK SEL Bit Selected Nominal Bit 33 000 MHz 33 333 MHz Field Divisor Rate System Clock System CLock 8 MHz 8 250 MHz 8 333 MHz 4 MHz 4 125 MHz 4 167 MHz 2 MHz 2 063 MHz 2 083 MHz 1 MHz 1 031 MHz 1 042 MHz 512 kHz 516 6 kHz 520 8 kHz 256 kHz 257 8 kHz 260 4 kHz 128 kHz 128 9 kHz 130 2 kHz 64 kHz 64 5 kHz 65 1 kHz 3 TC INT ENB Transaction Complete Interrupt Enable This bit is used to enable the TC INT bit of the SSISTA register see page 19 6 to generate an interrupt request 0 No interrupt is generated when the transaction i
350. er might not always return the last value written Note that both reads and writes can have side effects If you see a P be sure to read the bit description and programming notes RSV The bit field is reserved for internal test debug or future expansion This bit field should be written to 0 for normal system operation This bit field always returns 0 when read RSV The bitfield is reserved for compatibility purposes For example the bit field might be ignored during writes to maintain software compatibility If you see a be sure to read the bit description and programming notes Reference Notation MMCR offset 00h lanSC520 microcontroller Memory Mapped Configuration Region MMCR offset register 00h PCI index 00h PCI indexed register 00h Port 00h Direct mapped I O register 00h RTC index 00h RTC and configuration RAM indexed register 00h Elan SC520 Microcontroller Register Set Manual Table 0 1 AMD Introduction Documentation Notation Continued Notation Meaning Pin Naming Pin function during hardware reset Alternative pin function selected by software configuration ROMCS1 An overbar indicates that the signal assumes the logic Low state when asserted GPRESET The absence of an overbar indicates that the signal assumes the logic High state when asserted ads hold A signal name in all lowercase indicates an internal signal ROMCS2 ROMCS
351. er provides latched status for the RTC periodic interrupt event see page 17 18 lan SC520 Microcontroller Register Set Manual 17 15 AMD RTC Control B RTCCTLB Real Time Clock Registers Address 70h 71h RTC Index OBh 7 6 5 4 3 2 1 0 _ ALM_ UPD_ DATE_ HOUR pit SRT INT INT ENB INT ENB Pese ved Mope mope seL PS ENP Reset x 0 0 0 0 x x x R W R W R W R W R W RSV R W R W R W Register Description The RTC Control B register is used to temporarily inhibit RTC updates is in progress to enable RTC interrupts and to control date encoding 12 24 hour mode and daylight savings Bit Definitions Bit 7 6 _ INT_ENB 5 ALM_ INT_ENB 17 16 Function Set 0 Time and date update cycles are enabled and occur once per second 1 Time and date update cycles are disabled and any update in progress is aborted The SET bit feature is useful for allowing time and date registers to be updated by software without being disturbed by an automatic update cycle occurring during the change Neither internal functions nor RTC only resets affect the SET bit The SET bit should be set to 1 while changing the DATE MODE HOUR MODE SEL or DS ENB bits and cleared afterward Periodic Interrupt Enable 0 No RTC periodic interrupt is generated 1 The RTC periodic interrupt is enabled When the PER FLG bit in the RTCSTAC register transiti
352. ere a single bit error occurred The address is captured upon the detection of a single bit error and the bit field is inhibited from capturing subsequent error addresses until the SBIT_ERR bit in the ECCSTA register is cleared by writing a 1 see page 7 10 Note This register does not include byte enables BE from the requesting master therefore only doubleword resolution is provided by the indication Use the ECCCKBPOS register to determine which bit was in error see page 7 11 Reserved This bit field should be written to 0 for normal system operation Elan SC520 Microcontroller Register Set Manual ECC Multi Bit Error Address ECCMBADD Register Description AMD SDRAM Controller Registers Memory Mapped MMCR Offset 28h 31 30 29 28 27 26 25 24 Bit Reserved MB ADDR 27 24 Reset 0 0 0 0 0 0 0 0 R W RSV R 23 22 21 20 19 18 17 16 Bit MB_ADDR 23 16 Reset 0 0 0 0 0 0 0 0 R W R 15 14 13 12 11 10 9 8 Bit MB_ADDR 15 8 Reset 0 0 0 0 0 0 0 0 R W R 7 6 5 4 3 2 1 0 Bit MB ADDR 7 2 Reserved Reset 0 0 0 0 0 0 0 0 R W R RSV This register contains the physical address of the location in SDRAM that caused a multi bit ECC error Note A programmable reset does not preserve this register s state Bit Definitions Bit 31 28 27 2 1 0 Name Reserved MB_ADDR 27
353. erved This bit field should be written to O for normal system operation Current Count High This field contains the high word 30 16 of the watchdog timer current count The counter value is automatically reset when the watchdog timer is enabled Although both the WDTMRCNTH and WDTMRONTL registers can be read with a single 32 bit CPU instruction the 32 bit access is split into two 16 bit accesses See the GP Timer chapter in the Elan VS C520 Microcontroller User s Manual order 22004 for suggestions if it is necessary to read an accurate 32 bit value from the watchdog timer counter Elan SC520 Microcontroller Register Set Manual 16 5 Watchdog Timer Registers 16 6 Elan SC520 Microcontroller Register Set Manual CHAPTER re 1 7 REAL TIME CLOCK REGISTERS 17 1 17 2 Table 17 1 Table 17 2 OVERVIEW A This chapter describes the real time clock RTC registers of the ElanSC520 microcontroller The ElanSC520 microcontroller includes a PC AT compatible RTC The RTC register set includes two groups of registers Two direct mapped I O addresses used to access the RTC configuration space B 14 RTC indexed configuration registers used to set read and configure the RTC B 114bytes of RTC indexed nonvolatile RAM locations used PC AT compatible systems to store various system parameters See the Elan SC520 Microcontroller User s Manual order 22004 for details about the RTC
354. ess of MMCR offset C30h to read or write all 32 PIO pins with a single instruction the 32 bit access is split into two separate 16 bit accesses with the PIODATA15 0 register being accessed prior to the PIODATA31_16 register The two accesses not simultaneous lan SC520 Microcontroller Register Set Manual 20 19 AM Programmable Input Output Registers PIO15 PIOO Set PIOSET15 0 Memory Mapped MMCR Offset C34h 15 14 13 12 11 10 9 8 Bit PIO15_ PIO14_ PIO13_ PIO12_ PIO11_ PIO10_ PIO9_ PIO8_ SET SET SET SET SET SET SET SET Reset x X x x X x R W W W W W W W W W 7 6 5 4 3 2 1 0 Bit PIO7_ PIO6_ PIO5_ PIO4_ PIO3_ PIO2 PIO1 PIOO_ SET SET SET SET SET SET SET SET Reset X X R W W W W W W W W W Register Description This register is used to make the output level High selectively for pins PlO15 PIOO Bit Definitions Bit Name Function 15 PIO15 SET PIO15 Set 0 No effect 1 Set thePIO15 signal High 14 PlO14 SET PIO14 Set 0 No effect 1 Set the PIO14 signal High 13 PIO13 SET PIO13 Set 0 No effect 1 2 Set the PIO13 signal High 12 PIO12 SET PIO12 Set 0 effect 1 Set the PIO12 signal High 11 PIO11 SET PIO11 Set 0 No effect 1 Set the PIO11 signal High 10 PIO10 SET PIO10 Set 0 No effect 1 2 Set the PIO10 signal High 9 PIO9 SET PIO9 Set 0 No effect 1 Set the 9 signal High 8 PIO8 SET PIO
355. f the channel s memory address can be read from or written to this bit field immediately after memory address bits 8 1 are read from or written to this bit field Programming Notes To ensure that the lower byte of this register GPDMA7MAR is always accessed first software should precede any access to this register with a write to the MSTDMACBP register see page 11 93 to clear the master DMA byte pointer The value in this register GPDMA7MAR is used with the values in the GPDMA7PG register see page 11 72 and the GPDMAEXTPG7 register see page 11 16 to generate DMA address bits 27 0 By default this channel is set up for PC AT compatibility 16 bit DMA transfers on the master DMA controller For 16 bit transfers this register GPDMA7MAR holds address bits 16 1 and address bit 0 is always 0 i e the 16 bit transfers are word aligned Because of this software must load this register with the desired memory address divided by 2 for 16 bit transfers In enhanced mode this channel can be programmed for 8 bit DMA transfers see the descriptions for GPDMACTL register bits CH7 ALT SIZE ENH MODE ENB on page 1 1 4 For 8 bittransfers this register GPDMA7MAR holds address bits 15 0 and address bit 16 is controlled via the GPDMA7PG register see page 11 72 11 84 Elan SC520 Microcontroller Register Set Manual GP DMA Controller Registers AMDA Master DMA Channel 7 Transfer Count GPDMA7TC Direct Mapped Address O
356. ffect The PIO is an input The state of the pin can be read at the Data bit Writes to the Data Set and Clear bits have no effect The PIO is an output The 1 that is written to the Clear bit causes this PIO pin to be driven Low The state of the pin can be read at the Data bit in this case the pin is Low The PIO is an output The 1 that is written to the Set bit causes this PIO pin to be driven High The state of the pin can be read at the Data bit in this case the pin is High The PIO is an output The 0 that is written to the Data bit causes this PIO pin to be driven Low The state of the pin can be read at the Data bit in this case the pin is Low The PIO is an output The 1 that is written to the Data bit causes this PIO pin to be driven High The state of the pin can be read at the Data bit in this case the pin is High Notes 1 The Data Register Bit Reads column shows the resulting state of the Data register bit and the corresponding PIO pin 2 X Not used in this operation 3 Input value The Data register bit state always reflects the corresponding pin state whether input or output 4 For a particular PIO output operation only one of the pin s Data Set or Clear bits can be used The state of the unused bits is not important but subsequent writes to these bits can change the PIO pin state 20 2 Elan SC520 Microcontroller Register Set Manual PIO15 PIOO P
357. fication bit field 6 14 Master Command Interrupt Identification bit field 6 12 Master Controller Write Posting Enable bit field 6 4 Master Detected Parity Error Interrupt Enable bit field 6 10 Select bit field 6 10 Status bit field 6 13 Master DMA See also DMA GP DMA Slave DMA Master DMA Channel 4 Memory Address register 11 78 Transfer Count register 11 79 Master DMA Channel 4 7 Control register 11 87 Mask register 11 90 Mode register 11 91 Status register 11 86 Master DMA Channel 5 Memory Address register 11 80 Page register 11 73 Transfer Count register 11 81 Index 12 Index Master DMA Channel 6 Memory Address register 11 82 Page register 11 71 Transfer Count register 11 83 Master DMA Channel 7 Memory Address register 11 84 Page register 11 72 Transfer Count register 11 85 Master DMA Clear Byte Pointer register 11 93 Master DMA Controller Reset register 11 94 Master DMA Controller Temporary register 11 95 Master DMA General Mask register 11 97 Master DMA Mask Reset register 11 96 Master Enable bit field 6 21 Master NMI Enable bit field 12 4 Master PIC Channel x Interrupt Mode bit field 12 6 12 7 Global Interrupt Mode Enable bit field 12 5 I O Port 0020h access summary table 12 27 Initialization Control Word 1 register 12 26 Initialization Control Word 2 register 12 32 Initialization Control Word 3 register 12 33 Initialization Control Word 4 register 12 35 In Service re
358. for the Slave 1 controller This register is also known as Operation Control Word 1 in other PC AT compatible designs Bit Definitions Bit Name 7 IM7 6 IM6 5 IM5 4 IM4 3 IM3 2 IM2 1 IM1 0 IMO Programming Notes Function IR7 Mask 0 Unmask IR7 1 Mask IR7 IR6 Mask 0 Unmask IR6 1 Mask IR6 IR5 Mask 0 Unmask IR5 1 Mask IR5 IR4 Mask 0 Unmask IR4 1 Mask IR4 IR3 Mask 0 Unmask IR3 1 Mask IR3 IR2 Mask 0 Unmask IR2 1 Mask IR2 IR1 Mask 0 Unmask IR1 1 Mask IR1 IRO Mask 0 Unmask IRO 1 Mask IRO If the S2 bit in the MPICICWS3 register is cleared see page 12 34 then the Slave 1 controller is bypassed and the value of this register S1PICINTMSK has no effect This register S1PICINTMSK cannot be accessed during a Slave 1 PIC initialization control sequence which is initiated by setting the SLCT_ICW1 bit in the STPICICW 1 register see page 12 51 When the S1PICICWx register initialization sequence is not in effect any read or write of Port 00A1h accesses the S1PICINTMSK register 12 60 Elan SC520 Microcontroller Register Set Manual Floating Point Error Interrupt Clear FPUERRCLR Programmable Interrupt Controller Registers AMD Direct Mapped Address OOFOh 7 6 5 4 3 2 1 0 Bit FPUERR_RST Reset 0 0 0 0 0 0 0 0 R W W Register Description This register is used to clear the Am5 86 CPU
359. g it always reads back 0 Receiver FIFO Clear Because the direct mapped version of this bit is self clearing it always reads back 0 Elan SC520 Microcontroller Register Set Manual 18 5 UART Serial Port Registers Bit Name Function 0 FIFO_ENB FIFO Enabled 16550 Compatible Mode Enabled 0 The UART is 16450 compatible mode Accesses to receive and transmit FIFOs and to all FIFO control bits except FIFO_ENB in the write only UART x FIFO Control UARTxFCR register are disabled see page 18 15 1 The UART is in 16550 compatible mode Accesses to receive and transmit FIFOs and to all FIFO control bits in the write only UARTXxFCR register are enabled This bit must be 1 when other UARTxFCR register bits are written to or they cannot be programmed Any mode switch clears both FIFOs Programming Notes UARTxFCRSHAD is a shadow register for the write only UART x FIFO Control UARTxFCR register see page 18 15 18 6 Elan SC520 Microcontroller Register Set Manual UART Serial Port Registers AMDA Direct Mapped UART 2 Transmit Holding UART2THR I O Address 02F8h UART 1 Transmit Holding UART1THR I O Address O3F8h 7 6 5 4 3 2 1 0 Bit THR 7 0 Reset 0 0 0 0 0 0 0 0 R W W Register Description This is a write only register used to write data to be transmitted This register can be accessed only when the DLAB bit is in the UARTxLCR register see page 18 17 Bit Def
360. g allows the write buffer to fill higher acquire more master write data before requesting SDRAM service resulting in a greater chance of write data merging or collapsing This is desirable if a large amount of incomplete doubleword writes i e byte word or three byte writes is expected from either the Am5 86 CPU PCI bus or GP bus DMA A lower watermark setting can be used if more complete doublewords are expected and so merging or collapsing of data is less likely A lower watermark causes the write buffer to request SDRAM service at a lower threshold reducing the chance of filling the write buffer 8 2 Elan SC520 Microcontroller Register Set Manual Write Buffer and Read Buffer Register AMDA Bit Name Function 1 WB_FLUSH Write Buffer Flush This bit provides manual control over flushing of the write buffer 0 Writing 0 has no effect Reading 0 after first writing 1 indicates that the flush has completed 1 Writing 1 causes the write buffer to flush Reading 1 indicates that the write buffer is still in the process of being flushed Flushing the write buffer implies that all write buffer data is written out to SDRAM as a high priority before any other SDRAM write or read cycle activity is allowed to take place 0 WB_ENB Write Buffer Enable This bit is used to enable the write buffer 0 The write buffer is disabled 1 The write buffer is enabled The write buffer buffers all write activity from either the Am5 86 CPU PC
361. ge interrupts Elan SC520 Microcontroller Register Set Manual 6 11 AMD Host Bridge Master Interrupt Status HBMSTIRQSTA PCI Bus Host Bridge Registers Memory Mapped MMCR Offset 68h 15 14 13 12 11 10 9 8 Bit Reserved M CMD IRQ ID 3 0 Reset 0 0 0 0 0 0 0 0 R W RSV R 7 6 5 4 3 2 1 0 Bit Reserved M RTRTO M TABRT M MABRT M_SERR_ M_RPER_ M_DPER IRQ STA IRQ STA IRQ STA IRQ STA IRQ STA IRQ STA Reset 0 0 0 0 0 0 0 0 R W RSV R W R W R W R W R W R W Register Description This register contains host bridge master controller interrupt status bits and command interrupt identification Bit Definitions Bit 15 12 11 8 7 6 6 12 Name Reserved M_CMD_ IRQ_ID 3 0 Reserved Function Reserved This bit field should be written to 0 for normal system operation Master Command Interrupt Identification This bit field reports the command of the transaction during which the master controller detected an error condition This bit field is valid only when an interrupt status bit is set It is cleared when the interrupt status is cleared 0000 The command was not latched For example the command is not latched if multiple interrupts are pending and one interrupt status was cleared 0001 Special Cycle not used by the lanSC520 microcontroller 0010 I O Read 0011 I O Write 0100 0101 Reserved 0110 Memory Re
362. gister 12 25 Interrupt Mask register 12 36 Interrupt Mode register 12 6 Interrupt Request register 12 24 Operation Control Word 2 register 12 28 Operation Control Word 3 register 12 30 Master Received Parity Error Interrupt Enable bit field 6 10 Select bit field 6 10 Status bit field 6 13 Master Retry Time Out Interrupt Enable bit field 6 10 Select bit field 6 9 Status bit field 6 13 Master Retry Time Out register 6 24 Master Software DRQ n Request register 11 89 Master System Error Interrupt Enable bit field 6 10 Select bit field 6 9 Status bit field 6 13 Master Target Abort Interrupt Enable bit field 6 10 Select bit field 6 9 Status bit field 6 13 MASTR_CBP bit field 11 93 MASTR_MSK_RST bit field 11 96 MASTR_RST bit field 11 94 MASTR_TMP bit field 11 95 MATCH bit field 2 10 Elan SC520 Microcontroller Register Set Manual MAx signal in DRCCTL register 7 3 in DSCTL register 7 3 20 10 20 11 MAX_CNT bit field in GPTMROCTL register 14 4 in GPTMR1CTL register 14 10 in GPTMR2CTL register 14 16 MAX ONT RIU bit field in GPTMROCTL register 14 4 in GPTMR1CTL register 14 10 MB bit field 7 15 MBIT ERR bit field 7 10 MCA bit field in GPTMROMAXCMPA register 14 7 in GPTMR1MAXCMPA register 14 13 in GPTMR2MAXCMPA register 14 18 MCB bit field in GPTMROMAXCMPPB register 14 8 in GPTMR1MAXCMPB register 14 14 MDx signal 20 10 20 11 MECCx signal 20 10 20 1 1 MEM ENB bit field
363. gister see page 18 21 this bit field contains valid data received over the serial line Reading this bit field returns the last byte received in 16450 compatible mode or the head of the receive FIFO in 16550 compatible mode Programming Notes When the DLAB bit is 0 in the UARTxLCR register see page 18 17 reads from this address access the UART x Receive Buffer UARTXRBR register and writes to this address access the UART x Transmit Holding UARTXTHR register see page 18 7 When the DLAB bit is 1 in the UARTXxLCR register reads from and writes to this address access the UART x Baud Clock Divisor Latch LSB UARTxBCDL register see page 18 9 18 8 Elan SC520 Microcontroller Register Set Manual UART Serial Port Registers AMDA Direct Mapped UART 2 Baud Clock Divisor Latch LSB UART2BCDL Address 02F8h UART 1 Baud Clock Divisor Latch LSB UART1BCDL Address O3F8h 7 6 5 4 3 2 1 0 Bit DIV 7 0 Reset 0 0 0 0 0 0 0 0 R W R W Register Description This register contains bits DIV 7 0 of the16 bit baud rate clock divisor used to generate the 16x baud clock The baud rate clock divisor can only be accessed when the DLAB bit is 1 in the UARTxLCR register see page 18 17 The DIV 15 8 bits are located in the UARTxBCDH register see page 18 10 Bit Definitions Bit Name Function 7 0 DIV 7 0 UART x Baud Clock Divisor Latch When the DLAB bit is 1 in the UARTxLCR register
364. gister see page 20 7 10 4 Elan SC520 Microcontroller Register Set Manual AMD General Purpose Bus Controller Registers GP Chip Select Qualification GPCSQUAL Memory Mapped MMCR Offset CO2h 15 14 13 12 11 10 9 8 Bit GPCS7 RW 1 0 GPCS6 RW 1 0 GPCS5 RW 1 0 GPCS4 RW 1 0 Reset 0 0 0 0 0 0 0 0 R W R W R W R W R W 7 6 5 4 3 2 1 0 Bit GPCS3_RW 1 0 GPCS2_RW 1 0 GPCS1_RW 1 0 GPCSO RW 1 0 Reset 0 0 0 0 0 0 0 0 R W R W R W R W R W Register Description This register is used to qualify the GP bus chip selects with GPIORD GPIOWR GPMEMRD or GPMEMWR The qualifiers that can be used depend on the TARGET bit field in the PARx register for the addressed region see page 2 6 If the TARGET bit field selects GP bus I O the GP bus chip selects can be qualified with GPIORD or GPIOWR If the TARGET bit field selects GP bus memory the GP bus chip selects can be qualified with GPMEMRD or GPMEMWR Bit Definitions Bit Name 15 14 GPCS7 RW 1 0 GPCS6_RW 1 0 13 12 GPCS5_RW 1 0 11 10 Function GPCS7 Qualifier Selection This field is used to qualify the GP bus chip select 7 with GPIORD GPIOWR GPMEMRD or GPMEMWR 00 No qualification Qualify the chip select with write strobes GPIOWR or GPMEMWR 10 Qualify the chip select with read strobes GPIORD or GPMEMRD 11 Qualify fy the Ay select with both strobes GPIORD and GPIOWR or GPME
365. gister Description Address 0009h 7 6 5 4 3 2 1 0 Bit Reserved REQDMA REQSEL 1 0 Reset 0 0 0 0 0 X X X R W RSV This register is used to initiate software DMA request for of Channels 0 3 Bit Definitions Bit 7 3 1 0 Name Reserved REQDMA REQSEL 1 0 Programming Notes Function Reserved This bit field should be written to 0 for normal system operation Software DMA Request 0 Clear the request bit for the channel selected by the REQSEL bit field 1 Set the request bit for the channel selected by the REQSEL bit field The request bit is cleared internally after the corresponding channel has reached the end of its transfer count DMA Channel Select This bit field selects the DMA channel that is to latch the REQDMA bit internally to assert or deassert a DMA request via software 00 Select Channel 0 for internal DMA request per the REQDMA bit 01 Select Channel 1 for internal DMA request per the REQDMA bit 10 Select Channel 2 for internal DMA request per the REQDMA bit 11 Select Channel 3 for internal DMA request per the REQDMA bit Elan SC520 Microcontroller Register Set Manual 11 53 AMD Slave DMA Channel 0 3 Mask SLDMAMSK Register Description GP DMA Controller Registers Direct Mapped Address 000Ah 7 6 5 4 3 2 1 0 Bit Reserved CHMASK MSKSEL 1 0 Reset 0 0 0 0 0 X X X R W RSV W W
366. h BNK1_END BNK1_END BNK1_END Bank 1 8 Mbytes 04h 8 Mbytes 06h 32 Mbytes 10h 800000h 1000000h 2000000h AEG ov _ _ UO _ _ 7FFFFFh FFFFFFh 1FFFFFFh Bank 0 8 Mbytes pee 16 Mbytes p 32 Mbytes EMS he 000000h 000000h 0000000h Total 32 Mbytes 56 Mbytes 192 Mbytes 7 8 Elan SC520 Microcontroller Register Set Manual ECC Control ECCCTL Bit Reset R W SDRAM Controller Registers AMD Memory Mapped MMCR Offset 20h 5 2 1 0 MULT INT SGL INT Reserved ENB ENB ECC ENB 0 0 0 0 RSV R W R W R W Register Description This register controls all the error correction code ECC functions Note A programmable reset preserves this register s state See the PRG_RST_ENB bit description on page 3 3 Bit Definitions Programming Notes Name Reserved MULT_INT_ ENB SGL_INT_ ENB ECC_ENB Function Reserved This bit field should be written to 0 for normal system operation Enable Multi Bit Interrupt This bit enables the ECC non maskable interrupt NMI source to go active on the detection of a multi bit error 0 Disabled 1 Enabled The ECC NMI source must also be enabled via the ECC_NMI_ENB bit in the ECCMAP register see page 12 19 Enable Single bit Interrupt This bit enables the ECC maskable interrupt source to go active on the detection of a single bit error 0 Disabled 1 Enabled The ECC single bit interrupt source must also be mapped
367. h page 17 9 The alarm time can contain wildcards for hour minute or second settings A wildcard is any value from COh to FFh Elan SC520 Microcontroller Register Set Manual Real Time Clock Registers AMDA Bit Name Function 4 UPD_INT_FLG Update Ended Interrupt Flag 0 An RTC update ended event has not occurred since this bit was cleared This bit is cleared after read and is also cleared by an RTC only reset 1 An RTC update ended event has occurred This bit is set upon termination of each time date update cycle 3 0 Reserved Reserved This bit field should be written to 0 for normal system operation Programming Notes Elan SC520 Microcontroller Register Set Manual 17 19 AMD Real Time Clock Registers RTC Status D RTCSTAD I O Address 70h 71h RTC Index ODh 7 6 5 4 3 2 1 0 Bit RTC VRT Reserved Reset 0 0 0 0 0 0 0 R W R RSV Register Description The RTC Status D register provides RTC voltage monitor status Bit Definitions Bit 7 RTC_VRT 6 0 Reserved Programming Notes Function Valid RAM and Time The Valid RAM and Time RTC_VRT bit is used to determine the validity of the RTC time date and CMOS RAM registers 0 Indicates that the RTC backup battery as sensed by the microcontrollers BBATSEN pin was below a fixed reference voltage prior to the application of main system power See the Elan SC520 Microcontroller Data Sheet order 2
368. h the INT FLG status bit is not automatically disconnected from the PIC If the intent is to use an external RTC to drive the RTC interrupt request then all internal RTC interrupt enables bits PER INT ENB ALM INT ENB and UPD INT ENB must be cleared in the RTCCTLB register prior to disabling the internal RTC see page 17 16 Periodic Interrupt Flag 0 An RTC periodic event has not occurred since this bit was cleared This bit is cleared after read and is also cleared by an RTC only reset 1 An RTC periodic event has occurred This bit is set when an RTC periodic event occurs regardless of the state of its interrupt enable bit the PER INT ENB bit in the RTCCTLB register page 17 16 The periodic interrupt rate is configured with the RATE SEL bit field in the RTCCTLA register see page 17 15 Alarm Interrupt Flag 0 An RTC alarm event has not occurred since this bit was cleared This bit is cleared after read and is also cleared by an RTC only reset 1 An RTC alarm event has occurred This bit is set when an RTC alarm event occurs regardless of the state of its interrupt enable bit the INT bit in the RTCCTLB register page 17 16 Alarm events can only occur with a time resolution of one second An alarm event occurs when the current time contained in the RTCCURSEC RTCCURMIN and RTCCURHR registers is equal to the alarm setting configured in the RTCALMSEC RTCALMMIN and RTCALMHR registers see page 17 4 throug
369. he IR1 input is asserted 0 IRO Interrupt Request 0 0 The IRO input to the Master PIC is not asserted 1 The IRO input is asserted Programming Notes This register MPICIR is accessed by first writing a value of OAh to Port 0020h followed by a read back from Port 0020h Because the Slave 1 PIC cascades into Channel 2 of the Master PIC the IR2 bit is a real time status indication that one of the Slave 1 interrupt request inputs is asserted Because the Slave 2 PIC cascades into Channel 5 of the Master PIC the IR5 bit is a real time status indication that one of the Slave 2 interrupt request inputs is asserted 12 24 Elan SC520 Microcontroller Register Set Manual AMD Programmable Interrupt Controller Registers Master PIC In Service MPICISR Direct Mapped Address 0020h 7 6 5 4 3 2 1 0 Bit IS7 156 155 154 153 152 151 ISO Reset x x x x x x x x R W R Register Description This register indicates the Master interrupt priority levels that are being serviced Bit Definitions Bit Name Function 7 IS7 Interrupt Request 7 In Service 0 Interrupt request 7 is not being serviced 1 Interrupt request 7 is being serviced 6 IS6 Interrupt Request 6 In Service 0 Interrupt request 6 is not being serviced 1 Interrupt request 6 is being serviced 5 IS5 Interrupt Request 5 In Service 0 Interrupt request 5 is not being serviced 1 Interrupt request 5 is being serviced 4 I
370. he MODE bit is 0 000 0 wait states 001 1 wait state 010 2 wait states 011 3 wait states 100 4 wait states 101 5 wait states 110 6 wait states 111 7 wait states Programming Notes Elan SC520 Microcontroller Register Set Manual 9 7 AMDA ROM Flash Controller Registers 9 8 Elan SC520 Microcontroller Register Set Manual QAwuna AMD 1 GENERAL PURPOSE BUS CONTROLLER REGISTERS 10 1 OVERVIEW This chapter describes the general purpose GP bus registers of the lanSC520 microcontroller The GP bus is used for glueless connection of 8 and 16 bit devices to the lanSC520 microcontroller To provide the glueless interface the GP bus interface timing and data bus width is programmable The GP bus register set consists of 12 memory mapped configuration region MMCR registers used to configure the GP bus timing and data bus width See the Elan SC520 Microcontroller User s Manual order 22004 for details about the GP bus Table 10 1 lists the GP bus registers in offset order with the corresponding description s 10 2 Table 10 1 page number REGISTERS GP Bus MMCR Registers Register Name GP Echo Mode Mnemonic GPECHO MMCR Offset Page Number page 10 2 GP Chip Select Data Width GPCSDW page 10 3 GP Chip Select Qualification GPCSQUAL page 10 5 GP Chip Select Recovery Time GPCSRT page 10 7 GP Chip Select Pulse Width GPCSPW page 10 8
371. he PIO23 Pin 0 PIO23 is Low 1 PIO23 is High 6 PIO22 DATA Read or Write the PIO22 Pin 0 PIO22 is Low 1 PIO22 is High 5 PIO21 DATA Read or Write the PIO21 Pin 0 PIO21 is Low 1 PIO21 is High 4 PIO20 DATA Read or Write the PIO20 Pin 0 PIO20 is Low 1 PIO20 is High 3 PIO19 DATA Read or Write the PIO19 Pin 0 PIO19 is Low 1 PIO19 is High 2 PIO18 DATA Read or Write the PIO18 Pin 0 PIO18 is Low 1 PIO18 is High 1 PIO17 DATA Read or Write the PIO17 Pin 0 PIO17 is Low 1 PIO17 is High 0 16 DATA Read or Write the PIO16 Pin 0 PIO16 is Low 1 PIO16 is High Programming Notes Each PIOx DATA bit is used to read or write the value of the corresponding pin If the pin is configured as a PIO output then writing to this register selects the output level of the pin Note that the output state of a pin programmed to be a can also be controlled via the PIOSET31 16 and PIOCLR31 16 registers see page 20 22 and page 20 26 Reading a pin s PIOx DATA bit when the PIO is an output returns the state the pin was programmed for High or Low Reading a pin s PIOx DATA bit when the pin s interface function is selected via the corresponding PlOx FCN bit in the PIOPFS31 16 register see page 20 5 returns the state of the pin In other words reading a PIOx DATA bit returns the state of the corresponding PIO pin regardless of how the other PIO registers are programmed Although software can perform a 32 bit acc
372. he RINx signal has not changed from an active to an inactive state since this register UARTxMSR was last read 1 Indicates that the RINx signal changed from an active to an inactive state since the UARTXMSR register was last read Elan SC520 Microcontroller Register Set Manual 18 23 UART Serial Port Registers Bit Name Function 1 DDSR Delta Data Set Read 0 Indicates that the DSRx signal has not changed since this register UARTxMSR was last read 1 Indicates that the DSRx signal changed since the UARTxMSR register was last read 0 DCTS Delta Clear To Send 0 Indicates that the CTSx signal has not changed since this register UARTxMSR was last read 1 Indicates that the CTSx signal changed since the UARTxMSR register was last read Programming Notes Bits DCD RI DSR and CTS are real time status indicators inverted for the corresponding UART input signals DDCD TERI DDSR and DCTS are latched status bits that generate an interrupt if modem status interrupts are unmasked in the UART x Interrupt Enable UARTxINTENB register Reading this register UARTxMSR clears these bits and the associated interrupt 18 24 Elan SC520 Microcontroller Register Set Manual UART Serial Port Registers AMDA Direct Mapped Address O2FFh Address O3FFh UART 2 Scratch Pad UART2SCRATCH UART 1 Scratch Pad UART1SCRATCH 7 6 5 4 3 2 1 0 Bit SCRATCH 7 0 Reset 0 0 0 0 0 0 0
373. he low byte of the memory address and transfer count registers for Channels 0 3 Bit Definitions Bit Name Function 7 0 SLAVE CBP Slave DMA Clear Byte Pointer 7 0 The DMA controller s 16 bit memory address and terminal count registers are accessed by writing or reading consecutive 8 bit values to the same direct mapped I O address A single byte pointer is used across the slave DMA controller to determine which byte is accessed if any of these 16 bit registers is read or written Any access to one of these registers toggles the byte pointer between the low and high bytes A write of any data to this bit field SLAVE CBP clears the byte pointer so that the next memory address or transfer count register access is to the low byte Programming Notes lan SC520 Microcontroller Register Set Manual 11 57 GP DMA Controller Registers Slave DMA Controller Reset SLDMARST Direct Mapped I O Address 000Dh 7 6 5 4 3 2 1 0 Bit SLAVE RST 7 0 Reset 0 0 0 0 0 0 0 0 R W W Register Description This register provides a reset mechanism for Channels 0 3 Bit Definitions Bit Name Function 7 0 SLAVE RST Slave DMA Controller Reset 7 0 A write of any data to this address resets the DMA controller to the same state as a system reset Programming Notes 11 58 Elan SC520 Microcontroller Register Set Manual GP DMA Controller Registers AMDA Slave DMA Controller Temporary SLDMATMP Dir
374. he same state as a system reset Programming Notes 11 94 Elan SC520 Microcontroller Register Set Manual GP DMA Controller Registers AMDA Master DMA Controller Temporary MSTDMATMP Direct Mapped I O Address O0DAh 7 6 5 4 3 2 1 0 Bit MASTR_TMP 7 0 Reset 0 0 0 0 0 0 0 0 R W R Register Description This register has no real use in the lanSC520 microcontroller It is included for compatibility only Bit Definitions Bit Name Function 7 0 MASTR TMP Master DMA Controller Temporary Register 7 0 In a discrete DMA controller this bit field is used as a temporary storage buffer when doing memory to memory DMA Memory to memory DMA transfers are not supported in the ElanSC520 microcontroller so this register is included for compatibility reasons only Programming Notes lan SC520 Microcontroller Register Set Manual 11 95 AMD GP DMA Controller Registers Master DMA Mask Reset MSTDMAMSKRST Direct Mapped Address O0DCh 7 6 5 4 3 1 0 Bit MASTR_MSK_RST 7 0 Reset X X X X X X X R W W Register Description This register provides a mechanism to reset the MSTDMAGENMSK register see page 11 97 Bit Definitions Bit Name Function 7 0 MASTR MSK Master DMA Reset Mask RST 7 0 Writing any data to this I O address resets the MSTDMAGENMSK register see page 11 97 thereby activating the four slave DMA channels Programming Notes The sa
375. he total region size and the starting address of the programmed address space This bit field is used in one of three ways For Memory Space Regions with 4 Kbyte Pages The PG SZ bit is 0 The SZ_ST_ADR 24 18 bit field is used to specify a memory space size of up to 128 pages each 4 Kbytes in size for a maximum PARx window size of 512 Kbytes Pages start on 4 Kbyte boundaries A value of 00h specifies one page 7Fh specifies 128 pages TheSZ ST ADR 17 0 bit field is used to define the starting page of the region within the memory address space The SZ ST ADR 17 90 bit field is compared to internal Am5 86 CPU bus signals a29 a12 For Memory Space Regions with 64 Kbyte Pages The PG_SZ bit is 1 The SZ_ST_ADR 24 14 bit field is used to specify a memory space size of up to 2048 pages each 64 Kbytes in size for a maximum PARx window size of 128 Mbytes Pages start on 64 Kbyte boundaries A value of 000h specifies one page 7FFh specifies 2048 pages TheSZ ST ADR 13 0 bit field is used to define the starting page of the region within the memory address space The SZ ST ADR 13 0 bit field is compared to internal Am5 86 CPU bus signals a29 a16 For I O Space Regions The PG_SZ bit is ignored The SZ_ST_ADR 24 16 bit field is used to specify an I O space size of byte granularity for a total size up to 512 bytes A value of 000h specifies one byte 1FFh specifies 512 bytes The S
376. hen does the value remain in the valid range If the MONTH bit field in the RTCCURMON register is 2d February and the YEAR bit field value in the RTCCURYR register see page 17 13 is a leap year the DAY OF MTH bit field does leap year compensation automatically Programming Notes Software can suspend updating of the RTC via the SET bit in the RTCCTLB register see page 17 16 Software selects binary or BCD format via the DATE MODE bit in the RTCCTLB register lan SC520 Microcontroller Register Set Manual 17 11 Real Time Clock Registers RTC Current Month RTCCURMON Address 70h 71h RTC Index 08h 7 6 5 4 3 2 1 0 Bit MONTH 7 0 Reset X X X X X X X X R W R W Register Description This register used to initialize and read back the RTC current month Bit Definitions Bit Name Function 7 0 MONTH 7 0 RTC Current Month Software initializes current month value for the RTC by writing data to this bit field in either binary or binary coded decimal BCD formats The RTC logic updates this bit field once per second Valid values for this bit field range from 1d to 12d where 1 January 2 March 4 April 5 May July August 9 September 10 11 November 12d December If a value greater than 12d is programmed the bit field value increments up to FFh wraps around to 0 and
377. his software must load this register with the desired memory address divided by 2 for 16 bit transfers In enhanced mode this channel can be programmed for 8 bit DMA transfers see the descriptions for GPDMACTL register bits CH5 ALT SIZE and ENH MODE ENB on page 1 1 4 For 8 bittransfers this register GPDMA5MAR holds address bits 15 0 and address bit 16 is controlled via the GPDMASPG register see page 11 73 11 80 Elan SC520 Microcontroller Register Set Manual GP DMA Controller Registers AMDA Master DMA Channel 5 Transfer Count GPDMASTC Direct Mapped I O Address 00C6h 7 6 5 4 3 2 1 0 Bit 15 0 Reset X X X X X X X X RW RW Register Description This register contains bits 15 0 of the transfer count for Channel 5 during DMA operation Bit Definitions Bit Name Function 7 0 DMA5TC DMA Channel 5 Transfer Count 16 Bit Register 15 0 This 8 bit field is used two successive I O accesses to read or write the channel s transfer count bits 15 0 Bits 7 0 of the channel s transfer count can be read from or written to this bit field immediately after a write to the MSTDMACBP register see page 11 93 Bits 15 8 of the channel s transfer count can be read from or written to this bit field immediately after transfer count bits 7 0 are read from or written to this bit field The actual number of transfers is one more than the programmed transfer count value
378. his bit is set by hardware any time the timer count value reaches its maximum count value GPTMR2MAXCMPA register see page 14 18 The MAX ONT bit is set for this condition regardless of the state of the INT bit The MAX ONT bit can be used to monitor timer status through software polling instead of making use of interrupt generation Reserved This bit field should be written to 0 for normal system operation GP Timer 2 Continuous Mode This bit is used to configure GP Timer 2 for continuous or noncontinuous mode 0 Noncontinuous mode the GPTMR2ONT register see page 14 12 is cleared and the timer halts whenever the count reaches the maximum count value GPTMR2MAXCMPA register see page 14 18 The ENB bit is also cleared by hardware after every counter sequence 1 Continuous mode The timer count is reset to O after it reaches the maximum count value and the timer immediately begins counting again Elan SC520 Microcontroller Register Set Manual General Purpose Timer Registers AMDA GP Timer 2 Count GPTMR2CNT Memory Mapped MMCR Offset C84h 15 14 13 12 11 10 9 8 Bit CNT 15 8 Reset 0 0 0 0 0 0 0 0 R W R W 7 6 5 4 3 2 1 0 Bit CNT 7 0 Reset 0 0 0 0 0 0 0 0 R W R W Register Description This register contains the current count of GP Timer 2 Bit Definitions Bit Name Function 15 0 CNT 15 0 GP Timer 2 Count Register This bit fie
379. his bit programs PIO29 as an input or output 0 Input 1 Output 12 PIO28 DIR PIO28 Input or Output Select This bit programs PIO28 as an input or output 0 Input 1 Output 11 PIO27 DIR PIO27 Input or Output Select This bit programs PIO27 as an input or output 0 Input 1 Output 10 PIO26 DIR PIO26 Input or Output Select This bit programs PIO26 as an input or output 0 Input 1 Output 20 14 Elan SC520 Microcontroller Register Set Manual Bit Name 9 PIO25 DIR 8 PIO24 DIR 7 PIO23 DIR 6 PIO22 DIR 5 PIO21 DIR 4 PIO20 DIR 3 PIO19 DIR 2 PIO18 DIR 1 PIO17 DIR 0 PlO16 DIR Programming Notes Programmable Input Output Registers Function PIO25 Input or Output Select This bit programs PIO25 as an input or output 0 Input 1 Output PIO24 Input or Output Select This bit programs PIO24 as an input or output 0 Input 1 Output PIO23 Input or Output Select This bit programs PIO23 as an input or output 0 Input 1 Output PIO22 Input or Output Select This bit programs PIO22 as an input or output 0 Input 1 Output PIO21 Input or Output Select This bit programs PIO21 as an input or output 0 Input 1 Output PIO20 Input or Output Select This bit programs PIO20 as an input or output 0 Input 1 Output PIO19 Input or Output Select This bit programs PIO19 as an input or output 0 Input 1 Output PIO18 Input or Output Select This bit programs PIO18 as an input or output
380. ically removed from the cascade chain The interrupt request that is hooked to IRO of the Slave 1 controller is now routed directly to interrupt channel 2 of the Master PIC bypassing the Slave 1 controller This is useful where fewer than eight interrupts are needed in a system In this case a single EOI would need to be generated instead of two Channel 1 Slave Cascade Select 0 device attached to IR1 input 1 IR1 input used for slave cascading not valid in the lanSC520 microcontroller In the lanSC520 microcontroller this bit is internally fixed to O Channel 0 Slave Cascade Select 0 device attached to IRO input 1 IRO input used for slave cascading not valid in the lanSC520 microcontroller In the lanSC520 microcontroller this bit is internally fixed to O If bits 55 and S2 of this register MPICICWS3 are cleared both the slave controllers are logically removed from the cascade chain to the Master controller and only eight interrupt request priority levels are available to the user The PIC s initialization control word MPICICWx registers 1 4 must be programmed in sequence Writing to Port 0020h with bit 4 1 causes the MPICICW1 register to be written and also resets the PIC s internal state machine and the internal MPICICWXx register pointer Then MPICICWX registers 2 4 can be programmed by sequential writes to Port 0021h Each time Port 0021h is written to following the write to MPICICW1 the internal regi
381. icrocontroller Register Set Manual 7 11 AMD ECC Check Code Test ECCCKTEST SDRAM Controller Registers Memory Mapped MMCR Offset 23h 7 6 5 4 3 2 1 0 4 BAD_CHK_ E Bit ENB FRC BAD CHK 6 0 Reset 0 0 0 0 0 0 0 0 R W R W R W Register Description This register provides user control of the ECC check code that is written during an SDRAM write cycle This feature is to be used for test and error handler development Note A programmable reset does not preserve this register s state Bit Definitions Bit Name 7 BAD CHK ENB Function Enable Bad ECC Check Bits This bit can be used by test software to enable the BAD bit field to replace the correct ECC codes generated by the ElanSC520 microcontroller ECC logic for only the next single write cycle to SDRAM 0 The BAD bit field does not replace the generated check bits The binary pattern in the FRC BAD bit field has no effect on the ECC codes written to SDRAM during a write cycle 1 The BAD bit field replaces the generated check bits for the next SDRAM write The binary pattern written to the BAD bit field is written out as the 7 bit ECC code during the next write cycle to SDRAM This bit is automatically reset after the BAD bit field value is written to the ECC SDRAM during the following write cycle If this bit BAD CHK ENB was previously set then
382. icroprocessor Mode 0 8080 8085 mode 1 8086 mode In the ElanSC520 microcontroller design this PC AT compatible bit is internally fixed to 1 Initialization of this register is optional unless the IC4 bit is set in the MPICICW1 register see page 12 27 If the IC4 bit is cleared the ElanSC520 microcontroller uses 01h for the value of this register MPICICW4 The PIC s initialization control word MPICICWx registers 1 4 must be programmed in sequence Writing to Port 0020h with bit 4 1 causes the MPICICW1 register to be written and also resets the PIC s internal state machine and the internal MPICICWx register pointer Then MPICICWx registers 2 4 can be programmed by sequential writes to Port 0021h Each time Port 0021h is written to following the write to MPICICW1 the internal register pointer points to the next MPICICWx register MPICICW1 and MPICICW2 must always be programmed The MPICICW3 register is skipped if the SNGL bit in MPICICW1 is 1 The MPICICW4 register is skipped if the IC4 bit in MPICICW1 is 0 Note that AEOI mode is not supported by the Slave 1 PIC or Slave 2 PIC Elan SC520 Microcontroller Register Set Manual 12 35 AMD Master PIC Interrupt Mask MPICINTMSK Programmable Interrupt Controller Registers Direct Mapped Address 0021h 7 6 5 4 3 2 1 0 Bit IM7 IM6 IM5 IM4 IM3 IM2 IM1 IMO Reset X X X X X x x x R W R W R W R W R W R W R W R W R W Register Descri
383. igh GP DMA Direct Mapped Registers Register Name Slave DMA Channel 0 Memory Address GPDMANXTTCH7 Mnemonic GPDMAOMAR I O Address page 11 41 Page Number page 11 42 Slave DMA Channel 0 Transfer Count GPDMAOTC page 11 43 Slave DMA Channel 1 Memory Address GPDMA1MAR page 11 44 Slave DMA Channel 1 Transfer Count GPDMA1TC page 11 45 Slave DMA Channel 2 Memory Address GPDMA2MAR page 11 46 Slave DMA Channel 2 Transfer Count GPDMA2TC page 11 47 Slave DMA Channel 3 Memory Address GPDMA3MAR page 11 48 Slave DMA Channel 3 Transfer Count GPDMASTC page 11 49 Slave DMA Channel 0 3 Status SLDMASTA page 11 50 Slave DMA Channel 0 3 Control SLDMACTL page 11 51 Slave Software DRQ n Request SLDMASWREQ page 11 53 Slave DMA Channel 0 3 Mask SLDMAMSK page 11 54 Slave DMA Channel 0 3 Mode SLDMAMODE page 11 55 Slave DMA Clear Byte Pointer SLDMACBP Elan SC520 Microcontroller Register Set Manual page 11 57 GP DMA Controller Registers Table 11 2 Register Name Slave DMA Controller Reset GP DMA Direct Mapped Registers Continued Mnemonic SLDMARST Address AMD Page Number page 11 58 Slave DMA Controller Temporary SLDMATMP page 11 59 Slave DMA Mask Reset SLDMAMSKRST page 11 60 Slave DMA General Mask SLDMAGENMSK page 11 61 Gene
384. in Function Select PIOPFS15_0 Programmable Input Output Registers AMD Memory Mapped MMCR Offset C20h 15 14 13 12 11 10 9 8 Bit PIO15_ PIO14_ PIO13_ PIO12_ PIO11_ PIO10_ PIO9_ PIO8 _ FNC FNC FNC FNC FNC FNC FNC FNC Reset 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W 7 6 5 4 3 2 1 0 Bit PIO7_ PIO6_ PIO5_ PIO4_ PIO3_ PIO2_ PIO1_ PIOO_ FNC FNC FNC FNC FNC FNC FNC FNC Reset 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Register Description This register allows the programmer to choose the functionality of programmable I O pins PIO15 PIOO Bit Definitions Bit 15 Name PIO15 FNC PlO14 PIO13 FNC PIO12 FNC PIO11 PIO10 FNC PIO9 FNC Function PIO15 or GPIRQ8 Function Select This bit is used to select the functionality of the PIO15 pin 0 The pin is PIO15 1 The pin is GPIRQ8 PIO14 or GPIRQ9 Function Select This bit is used to select the functionality of the PIO14 pin 0 The pin is PIO14 1 The pin is GPIRQ9 PIO13 or GPIRQ10 Function Select This bit is used to select the functionality of the PIO13 pin 0 The pin is PIO13 1 2 The pin is GPIRQ10 PIO12 or GPDACKO Function Select This bit is used to select the functionality of the PIO12 pin 0 The pin is 12 1 The pin is GPDACKO PIO11 or GPDACK1 Function Select This bit is used to select the functionality of the PIO11 pin 0 The pin is PIO11
385. ing PCIINTDMAP page 12 21 DMA Buffer Chaining Interrupt Mapping DMABCINTMAP page 12 21 SSI Interrupt Mapping SSIMAP page 12 21 Watchdog Timer Interrupt Mapping WDTMAP page 12 21 RTC Interrupt Mapping RTCMAP page 12 21 Write Protect Violation Interrupt Mapping WPVMAP page 12 21 AMDebug Technology RX TX Interrupt Mapping ICEMAP page 12 21 Floating Point Error Interrupt Mapping FERRMAP page 12 21 GPIRQO Interrupt Mapping GPOIMAP page 12 21 GPIRQ1 Interrupt Mapping GP1IMAP page 12 21 GPIRQ2 Interrupt Mapping GP2IMAP page 12 21 GPIRQ3 Interrupt Mapping GP3IMAP page 12 21 GPIRQ4 Interrupt Mapping GP4IMAP page 12 21 GPIRQ5 Interrupt Mapping GP5IMAP page 12 21 GPIRQ6 Interrupt Mapping GP6IMAP page 12 21 GPIRQ7 Interrupt Mapping GP7IMAP page 12 21 GPIRQS Interrupt Mapping GP8IMAP page 12 21 GPIRQO Interrupt Mapping GP9IMAP page 12 21 GPIRQ10 Interrupt Mapping GP10IMAP Programmable Interrupt Controller Direct Mapped Registers Register Name Master PIC Interrupt Request Mnemonic MPICIR Address page 12 21 Page Number page 12 24 Master PIC In Service MPICISR page 12 25 Master PIC Initialization Control Word 1 MPICICW1 page 12 26 Master PIC Operation Control Word 2 MPICOCW2 page 12 28 Master PI
386. ing a 1 This bit operates regardless of the corresponding interrupt enable bit GNT TO INT ENB in the SYSARBCTL register see page 5 2 When enabled as an interrupt this source shares the interrupt controller input used by any host bridge interrupts enabled in the HBTGTIRQCTL and HBMSTIRQCTL registers see page 6 5 and page 6 9 Reserved This bit field should be written to O for normal system operation PCI Bus Arbiter Grant Time Out Identification This bit field identifies which GNT was asserted when the PCI arbiter detected a grant time out This bit field is reset to ones by writing a one to the GNT TO STA bit 0000 GNTO was asserted when a grant time out was detected 0001 GNT1 was asserted when a grant time out was detected 0010 GNT2 was asserted when a grant time out was detected 0011 GNT3 was asserted when a grant time out was detected 0100 GNT4 was asserted when a grant time out was detected 0101 1101 Reserved 1110 The Am5 86 CPU GNT was asserted when a grant time out was detected 1111 2 No grant time out was detected or GNT was asserted when a grant time out was detected but not latched Elan SC520 Microcontroller Register Set Manual 5 3 AMD System Arbiter Master Enable SYSARBMENB System Arbitration Registers Memory Mapped MMCR Offset 72h 15 14 13 12 11 10 9 8 Bit Reserved Reset 0 0 0 0 0 0 0 0 R W RSV 7 6 5 4 3 2 1 0
387. initions Bit Name Function 7 0 THR 7 0 UART x Transmit Holding Register When the DLAB bit is 0 in the UART x Line Control UARTxLCR register see page 18 17 and the THRE bit is 1 in the UART x Line Status UARTxLSR register see page 18 21 writing a byte to this bit field causes the byte to be transmitted Programming Notes When the DLAB bit is 0 in the UARTxLCR register see page 18 17 reads from this address access the UART x Receive Buffer UARTxRBR register see page 18 8 and writes to this address access the UART x Transmit Holding UARTxTHR register When the DLAB bit is 1 in the UARTXxLCR register reads from and writes to this address access the UART x Baud Clock Divisor Latch LSB UARTxBCDL register see page 18 9 Elan SC520 Microcontroller Register Set Manual 18 7 UART Serial Port Registers Direct Mapped UART 2 Receive Buffer UART2RBR I O Address 02F8h UART 1 Receive Buffer UART1RBR Address O3F8h 7 6 5 4 3 2 1 0 Bit RBR 7 0 Reset 0 0 0 0 0 0 0 0 R W R Register Description This is a read only register used to read received data This register can be accessed only when the DLAB bit is 0 in the UARTxLCR register see page 18 17 Bit Definitions Bit Name Function 7 0 RBR 7 0 UART x Receive Buffer When the DLAB bit is 0 in the UART x Line Control UARTxLCR register see page 18 17 and the DR bit is 1 in the UART x Line Status UARTxLSR re
388. ins configuration information about the location i e SDRAM bus or GP bus width operation mode and timing of the ROM devices that are attached to the ElanSC520 microcontroller ROMCS1 signal Bit Definitions Bit Name 15 13 Reserved 12 DGP 11 10 WIDTH 1 0 9 MODE 8 6 Reserved 5 4 SUB _DLY 1 0 3 Reserved 9 4 Function Reserved This bit field should be written to 0 for normal system operation Chip Select 1 Device SDRAM GP Bus Select This bit is used to configure the location of the ROM devices that are enabled by ROMCS1 The ROM can be connected either to the SDRAM data bus or to the GP bus 0 ROM is on the GP bus 1 ROM is on the SDRAM data bus Chip Select 1 Device Width Select This bit field is used to configure the width of the ROM selected by ROMCS1 00 ROM is 8 bits wide 01 ROM is 16 bits wide 10 ROM is 32 bits wide 11 ROM is 32 bits wide Chip Select 1 Device Mode This bit is used to configure the mode of the ROM selected by ROMCS1 0 ROM is non page mode 1 ROM is page mode Reserved This bit field should be written to 0 for normal system operation Chip Select 1 Device Delay for Subsequent Accesses This bit field is used to configure the number of wait states for all page mode accesses to the ROM that are subsequent to the first access This bit field applies only if the MODE bit is 1 00 0 wait states 01 1 wait state 10 2 wait states 11 wait states
389. interrupt trigger bit causes an interrupt to be asserted on the corresponding PIC s interrupt channel for as long as the bit is set To use these bits effectively the interrupt service routines should clear the interrupt trigger bit early in the routine Note that for the internal PC AT compatible peripherals and for many PCI peripherals existing drivers in off the shelf operating systems are not aware of these interrupt trigger bits For peripherals with these kinds of interrupt Service routines care must be taken notto set the interrupt trigger bits If this occurs the interrupt gets stuck in the asserted state and the system loops in the interrupt service routine because the routine does not clear the trigger bit 12 12 Elan SC520 Microcontroller Register Set Manual Software Interrupt 22 17 NMI Control SWINT22 17 Bit Reset R W Programmable Interrupt Controller Registers AMD Memory Mapped MMCR Offset DOAh 7 6 5 4 3 2 1 0 SW P22 SW P21 SW P20 SW P19 T SW 18_ SW P17 Reserved NMIETRIG reus TRIG TRIG RIG TRIG TRIG 0 0 0 0 0 0 0 0 RSV R W R W R W R W R W R W R W Register Description This register allows software to generate interrupt priority levels P17 P22 or the nonmaskable interrupt NMI to the CPU Bit Definitions Bit Name Reserved NMI TRIG SW P22 TRIG SW P21 TRIG SW P20 TRIG SW P19 TRIG SW P18 TRIG Function Reserved This
390. interval timer PIT As an output this pin drives the clock selected by the CLK_TST_SEL bit field externally 0 Input CLKTIMER 1 2 Output CLKTEST CLKTIMER CLKTEST Pin Enable The CLKTIMER CLKTEST pin is disabled on reset and must be enabled to function 0 Disabled 1 Enabled Elan SC520 Microcontroller Register Set Manual 20 9 AMD Drive Strength Control DSCTL Programmable Input Output Registers Memory Mapped MMCR Offset C28h 15 14 13 12 11 10 9 8 Bit Reserved SCS DRIVE 1 0 Reset 0 0 0 0 0 0 1 0 R W RSV R W 7 6 5 4 3 2 1 0 Bit SRCW_DRIVE 1 0 SDQM_DRIVE 1 0 MA_DRIVE 1 0 DATA_DRIVE 1 0 Reset 0 0 0 0 0 0 0 0 R W R W R W R W R W Register Description This register controls the drive strengths for the SDRAM interface signals Independent drive strength control is provided for the address bus MA12 MAO bank select bus BA1 BAO SDQM3 SDQM0 bus and SCS3 SCSO The SRASA SRASB SCASA SCASB and SWEA SWEB control signals are grouped into a single drive strength control The data bus MD31 MD0O and ECC bus MECC6 MECOO are also grouped into a single drive strength control Note A programmable reset preserves this register s state See the PRG bit description on page 3 3 Bit Definitions Bit Name 15 10 Reserved 9 8 SCS DRIVE 1 0 7 6 SRCW DRIVE 1 0 5 4 DRIVE 1 0 20 10
391. ion of this parameter is one internal 33 MHz clock period The recovery time used is GPCS_RECOVR 1 internal clock periods i e if GPCS RECOVR is 0 the recovery time is one clock period Programming Notes Before using one of the GPCS7 GPCS 1 signals software must set the corresponding GPCSx SEL bit in the CSPFS register see page 20 7 Before using the GPCSO signal software must set the PIO27 SEL bit in the PIOPFSS31 16 register see page 20 5 Figure 10 1 shows the relationships between the various adjustable GP bus timing parameters Figure 10 1 GP Bus Signal Timing Adjustment GPA25 GPAO K Address Valid GPCSx GPCSOFF 1 E GPCSPW 1 W GPCSRT 1 GPMEMRD or GPIORD lg GPRDOFF 1 a GPRDW 1 zi GPMEMWR or GPIOWR GPWROFF 1 Ei GPWRW 1 E GPALE GPALEOFF 1 GPALEW 1 Beginning of a Bus Cycle E gt Bus Cycle Duration Notes 1 Timing parameter values are in units of one internal 33 MHz clock period 2 Timing parameters in the diagram can be adjusted via the corresponding GP bus registers 3 GPCSOFF GPCSPW GPCSRT must be greater than or equal to GPRDOFF GPRDW GPWROFF GPWRW and GPALEOFF GPALEW 4 Very long GP bus cycles can cause the PCI Host Bridge target controller to violate the 10 us memory write maximum completion time limit set in the PCI Local Bus Specification Revision 2 2 In PCI bus 2 2 co
392. is issued W Burst length always read burst 4 Burst type follow non linear burst Operating mode standard operation W Write burst mode single mode After a command is issued the OPMODE SEL bit field must be cleared to 000b normal SDRAM mode before any further SDRAM access Programming Notes SDRAM refresh cycles should only be enabled via the RFSH ENB bit when the OPMODE SEL bit is 000b This register DRCCTL should be modified only when the write buffer and the read ahead feature of the read buffer are disabled in the DBCTL register see page 8 3 Elan SC520 Microcontroller Register Set Manual 7 3 AMD SDRAM Timing Control DRCTMCTL Register Description SDRAM Controller Registers Memory Mapped MMCR Offset 12h 7 6 5 4 3 2 1 0 Bit Reserved CAS LAT RAS PCHG DLY 1 0 RAS CAS DLY 1 0 Reset 0 0 0 1 1 0 1 0 R W RSV R W R W R W This register controls the SDRAM device timing Note A programmable reset preserves this register s state See the PRG_RST_ENB bit description on page 3 3 Bit Definitions Bit 7 5 Programming Notes Name Reserved CAS_LAT RAS_PCHG_ DLY 1 0 RAS CAS DLY 1 0 Function Reserved This bit field should be written to 0 for normal system operation SDRAM CAS Latency This bit controls the SCASx signal latency timing to all the SDRAM banks 0 Cycle latency is 2T 1 Cycle latency is 3T default Where T
393. is 15 ns one half of the 33 MHz clock cycle To make the CAS LAT bit setting take effect a Load Mode Register command must be issued to the SDRAM devices via the OPMODE SEL bit field of the DRCCTL register see page 7 3 Incorrect operation can occur if the CAS LAT bit is modified and the Load Mode Register command is not issued to the SDRAM devices SDRAM RAS Precharge Delay This bit field determines the SRASx signal precharge delay 00 2T 01 3T 10 4T default 112 6T Where T is 15 ns one half of the 33 MHz clock cycle SDRAM RAS to CAS Delay This bit field determines the SRASx to SCASx delay 00 2T 01 3T 10 4T default 11 Reserved Where T is 15 ns one half of the 33 MHz clock cycle This register DRCTMCTL should be modified only when the write buffer and the read ahead feature of the read buffer are disabled in the DBCTL register see page 8 3 7 4 Elan SC520 Microcontroller Register Set Manual SDRAM Controller Registers SDRAM Bank Configuration DRCCFG Bit Reset R W Bit Reset R W AMD Memory Mapped MMCR Offset 14h 1 gt is 1 12 11 10 9 8 a BNK2_ Reserved BNK8 COLWDTH 1 0 Reserved BNK2_COLWDTH 1 0 0 0 0 0 0 j 5 5 R W RSV R W R W RSV R W BNK1_ BNKO BNK Reserved BNK1_COLWDTH 1 0 Reserved 1 0 0 0 0 0 0 5 R W RSV R W R W RS
394. ister 12 36 Elan SC520 Microcontroller Register Set Manual AMD Programmable Interrupt Controller Registers Slave 2 PIC Interrupt Request S2PICIR Direct Mapped Address 0024h 7 6 5 4 3 2 1 0 Bit IR7 IR6 IR5 IRA IR3 IR2 IR1 IRO Reset X X X X X R W R Register Description This register provides a real time status of the interrupt request inputs to the Slave 2 PIC This register latches all incoming interrupt requests and provides individual status of the requests to be acknowledged Bit Definitions Bit Programming Notes Name IR7 IR6 IR5 IR4 IR3 IR2 IR1 IRO Function Interrupt Request 7 0 The IR7 input to the Slave 2 PIC is not asserted 1 The IR input is asserted Interrupt Request 6 0 The IR6 input to the Slave 2 PIC is not asserted 1 The IR6 input is asserted Interrupt Request 5 0 The IR5 input to the Slave 2 PIC is not asserted 1 The IR5 input is asserted Interrupt Request 4 0 The IR4 input to the Slave 2 PIC is not asserted 1 The IR4 input is asserted Interrupt Request 3 0 The IR3 input to the Slave 2 PIC is not asserted 1 2 The IR3 input is asserted Interrupt Request 2 0 The IR2 input to the Slave 2 PIC is not asserted 1 The IR2 input is asserted Interrupt Request 1 0 The IR1 input to the Slave 2 PIC is not asserted 1 2 The IR1 input is asserted Interrupt Request 0
395. ister Name Mnemonic MMCR Offset Page Number Host Bridge Control HBCTL page 6 3 Host Bridge Target Interrupt Control HBTGTIRQCTL page 6 5 Host Bridge Target Interrupt Status HBTGTIRQSTA page 6 7 Host Bridge Master Interrupt Control HBMSTIRQCTL page 6 9 Host Bridge Master Interrupt Status HBMSTIRQSTA page 6 12 Host Bridge Master Interrupt Address MSTINTADD page 6 14 Elan SC520 Microcontroller Register Set Manual 6 1 AMD PCI Bus Host Bridge Registers Table 6 2 PCI Bus Host Bridge Direct Mapped Registers Register Name mnemonic VO Address Page Number PCI Configuration Address PCICFGADR OCF8h page 6 15 PCI Configuration Data PCICFGDATA OCFCh page 6 17 Table 6 3 PCI Bus Host Bridge Indexed Registers Register Name Mnemonic Address PCI Index Page Number Device Vendor ID PCIDEVID OCF8h 0CFCh page 6 18 Status Command PCISTACMD OCF8h 0CFCh page 6 19 Class Code Revision ID PCICCREVID OCF8h OCFCh page 6 22 Header Type PCIHEADTYPE OCF8h 0CFCh page 6 23 Master Retry Time Out PCIMRETRYTO OCF8h 0CFCh page 6 24 6 2 Elan SC520 Microcontroller Register Set Manual PCI Bus Host Bridge Registers AMDA Host Bridge Control HBCTL Memory Mapped MMCR Offset 60h 15 14 13 12 11 10 9 8 Bit PCI_RST Reserved PORE T_DLYTR_ENB 1 0 Reset 0 0 0 0 0 0 0 0 R W R W RSV R W R W 7 6 5 4 3 2 1 0 M_ Bit Reserved WPOST_ Reserved ENB Re
396. ister has no effect If a PIO pin is programmed to be an input or if the pin is programmed for its interface function via the corresponding PIOx FNC bit in the PIOPFS15 0 register see page 20 3 then writing to the pin s PIOx CLR bit has no effect Although software can perform a 32 bit access of MMCR offset C38h to clear bits across all 32 PIO pins with a single instruction the 32 bit access is split into two separate 16 bit accesses with the PIOCLR15 Oregister being accessed prior to the PIOCLR31_16 register The two writes are not simultaneous Elan SC520 Microcontroller Register Set Manual 20 25 AM Programmable Input Output Registers PIO31 PIO16 Clear PIOCLRS31 16 Memory Mapped MMCR Offset C3Ah 15 14 13 12 11 10 9 8 P031 PIO30_ 1 29_ 1 28_ 1 27_ PIO26_ PIO25_ PIO24_ CLR CLR CLR CLR CLR CLR CLR CLR Reset X X X X X X X X R W 7 6 5 4 3 2 1 0 pir POP PIO22 PIO21 PIO20 PIO19 PIO18_ PIO17_ PIO16_ CLR CLR CLR CLR CLR CLR CLR CLR Reset X X X X X X X X R W w Register Description This register is used to make the output level Low selectively for pins PIO31 PIO16 Bit Definitions Bit Name Function 15 PIO31 CLR PIO31 Clear 0 No effect 1 Drive the PIO31 signal Low 14 PIO30 CLR PIO30 Clear 0 No effect 1 Drive the PIO30 signal Low 13 PIO2
397. it 4 1 causes the S1PICICW1 register to be written and also resets the PIC s internal state machine and the internal S1PICICWx register pointer Then S1PICICWx registers 2 4 can be programmed by sequential writes to Port O0A1h Each time Port 00A1h is written following the write to S1PICICW1 the internal register pointer points to the next S1PICICWx register S1PICICW1 and S1PICICW2 must always be programmed Also the S1PICICWS register must always be programmed in this design because the SNGL bit in S1PICICW1 is internally fixed to 0 The S1PICICWA register is skipped if the IC4 bit in S1PICICW1 is 0 Software is expected to initialize this register 31PICICWA if the IC4 bit is set in the S1PICICW1 register see page 12 52 Ifthe IC4 bitis cleared the ElanSC520 microcontroller uses 01h for the value of this register S1 PICICW4 However if the S2 bit is cleared in the MPICICW3 register see page 12 34 then the Slave 1 controller is bypassed and programming this register S1PICICW4 does not affect other registers Elan SC520 Microcontroller Register Set Manual 12 59 AMD Slave 1 PIC Interrupt Mask S1PICINTMSK Programmable Interrupt Controller Registers Direct Mapped Address OOAth 7 6 5 4 3 2 1 0 Bit IM7 IM6 IM5 IM4 IM3 IM2 IM1 IMO Reset X X X X X x x x R W R W R W R W R W R W R W R W R W Register Description This register provides masking of individual interrupt requests
398. it in the HBCTL register see page 6 3 6 14 Elan SC520 Microcontroller Register Set Manual PCI Configuration Address PCICFGADR Bit Reset R W Bit Reset R W Bit Reset R W Bit Reset R W AMD PCI Bus Host Bridge Registers Direct Mapped Address OCF8h 31 30 29 28 27 26 25 24 ENABLE Reserved 0 0 0 0 0 0 0 0 R W RSV 23 22 21 20 19 18 17 16 BUS_NUM 7 0 0 0 0 0 0 0 0 0 R W 15 14 13 12 11 10 9 8 DEVICE_NUM 4 0 FUNCTION_NUM 2 0 0 0 0 0 0 0 0 0 R W R W 7 6 5 4 3 2 1 0 REGISTER NUM 5 0 Reserved 0 0 0 0 0 0 0 0 R W RSV Register Description This register is used to specify the information to be driven out during the address phase of the next configuration cycle which is initiated by a subsequent read or write of the PCICFGDATA register see page 6 17 Bit Definitions Bit 31 30 24 23 16 Name ENABLE Reserved BUS NUM 7 0 Function Enable 0 Accesses to the PCICFGDATA register see page 6 17 are not converted to configuration cycles on the PCI bus They remain normal I O cycles 1 2 Accesses to the PCICFGDATA register are converted to configuration cycles on the PCI bus Reserved This bit field should be written to 0 for normal system operation Bus Number This bit field specifies the PCI bus number to which the configuration
399. it in the UARTxINTENB register see page 18 11 18 14 Elan SC520 Microcontroller Register Set Manual UART 2 FIFO Control UART2FCR UART 1 FIFO Control UART1FCR Bit Reset R W UART Serial Port Registers AMD Direct Mapped Address 02FAh Address OSFAh 7 6 3 2 1 0 RFRT 1 0 Reserved DMA TF CLR RF CLR FIFO MODE 0 0 0 0 0 0 W W RSV W W W Register Description This is a write only register used to enable and control the FIFO in 16550 compatible mode Reads to this address access the UART x Interrupt ID UARTXINTID register see page 18 12 Bit Definitions Bit 7 6 3 2 1 Name RFRT 1 0 Reserved DMA MODE TF CLR RF CLR Function Receiver FIFO Register Trigger Bits In 16550 compatible mode this bit field specifies the trigger level at which the INT ID bit field in the UARTXINTID register see page 18 13 reports that a received data available interrupt is pending If received data available interrupts are enabled in the UARTxINTENB register page 18 11 the system is interrupted when the receive FIFO fills to the trigger level as follows 00 1 byte 01 4 bytes 10 8 bytes 11 14 bytes When the data in the receive FIFO falls below the specified trigger level the interrupt is cleared Reserved These bits should be written to 0 for normal system operation DMA Mode This bit is valid only in 16550 compatible mode In
400. ite to the SLDMACBP register see page 11 57 Bits 15 8 of the channel s transfer count can be read from or written to this bit field immediately after transfer count bits 7 0 are read from or written to this bit field The actual number of transfers is one more than the programmed transfer count value Programming Notes To ensure that the lower byte of this register GPDMA2TO is always accessed first software should precede any access to this register with a write to the SLDMACBP register see page 11 57 to clear the slave DMA byte pointer In PCI bus 2 2 compliant designs software must limit the length of GP bus DMA demand or block mode transfers Very large transfers could cause the PCI Host Bridge target controller to violate the 10 us memory write maximum completion time limit set in the PC Local Bus Specification Revision 2 2 lan SC520 Microcontroller Register Set Manual 11 47 GP DMA Controller Registers Slave DMA Channel 3 Memory Address GPDMA3MAR Direct Mapped I O Address 0006h 7 6 5 4 3 2 1 0 Bit DMA3MAR 15 0 Reset X X X X X X X X R W R W Register Description This register contains bits 15 0 of the memory address for Channel 3 during DMA operation Bit Definitions Bit Name Function 7 0 DMA3MAR Lower 16 Bits of DMA Channel 3 Memory Address 15 0 This 8 bit field is used in two successive I O accesses to read or write the channel s memory address
401. itialization Control Word 2 S2PICICW2 Direct Mapped Address 0025h 7 6 5 4 3 2 1 0 Bit T7 T3 A10 A8 Reset x x x x x x x R W W W Register Description This register is the second initialization register of the Slave 2 controller Bit Definitions Bit Name Function 7 3 T7 T3 Bits 7 3 of Base Interrupt Vector Number for this PIC The PIC concatenates the T7 T3 bit field value to the 3 bit PIC interrupt request level in the bit 2 0 position to form the interrupt vector For example if bits T7 T3 are programmed to 11110b the IRO channel generates an interrupt FOh vector 2 0 A10 A8 A10 A68 of Interrupt Vector Software should write these to 0 Programming Notes If the S5 bit in the MPICICWS3 register is cleared see page 12 33 then the Slave 2 controller is bypassed and programming this register does not affect other registers The PIC s initialization control word S2PICICWX registers 1 4 must be programmed in sequence Writing to Port 0024h with bit 4 1 causes the S2PICICW1 register to be written and also resets the PIC s internal state machine and the internal S2PICICWx register pointer Then S2PICICWx registers 2 4 can be programmed by sequential writes to Port 0025h Each time Port 0025h is written to following the write to S2PICICW1 the internal register pointer points to the next S2PICICWx register S2PICICW1 and S2PICICW2 must always be programmed Also the S2
402. itions Bit Name Function 31 24 0 7 0 Base Class Code This bit field defines the PCI bus base class code of the host bridge 06h Bridge Device 23 16 CD Sub Class Code 7 0 This bit field defines the PCI bus sub class code for the host bridge 00h Host PCI bridge 15 8 PRG IF 7 0 Program Interface This bit field defines the PCI bus program interface type of the host bridge 00h Host PCI bridge 7 0 REV ID 7 0 Revision I D This bit field defines the host bridge revision number 00h Revision number Programming Notes This register PCICCREVID is register number 2 in the host bridge specific PCI configuration space 6 22 Elan SC520 Microcontroller Register Set Manual Header Type PCIHEADTYPE PCI Bus Host Bridge Registers AMD Address OCFS8h OCFCh PCI Index OEh 6 5 4 3 2 Bit HDR TYP 7 0 Reset 0 0 0 0 0 0 R W R Register Description This register contains the PCI configuration header space header type Bit Definitions Bit 7 0 7 0 Programming Notes Function Header Type This bit field defines the PCI configuration space header format 00h Single function device not PCI to PCI bridge This register PCIHEADTYPE is byte 2 of register number 3 in the host bridge specific PCI configuration space Elan SC520 Microcontroller Register Set Manual 6 23 PCI Bus Host Bridge
403. its for the buffer chaining interrupts An interrupt is generated when the GP bus DMA controller completes the transfer that is in progress Software can use this interrupt to queue up a subsequent transfer Bit Definitions Programming Notes Name Reserved CH7_INT_ ENB CH6_INT_ ENB CH5_INT_ ENB CH3_INT_ ENB Function Reserved This bit field should be written to 0 for normal system operation Interrupt Enable for Channel 7 This bit is applicable only if the Buffer Chaining feature is enabled for this channel 0 End of buffer interrupt for this channel is disabled 1 End of buffer interrupt for this channel is enabled Interrupt Enable for Channel 6 This bit is applicable only if the Buffer Chaining feature is enabled for this channel 0 End of buffer interrupt for this channel is disabled 1 End of buffer interrupt for this channel is enabled Interrupt Enable for Channel 5 This bit is applicable only if the Buffer Chaining feature is enabled for this channel 0 End of buffer interrupt for this channel is disabled 1 End of buffer interrupt for this channel is enabled Interrupt Enable for Channel 3 This bit is applicable only if the Buffer Chaining feature is enabled for this channel 0 End of buffer interrupt for this channel is disabled 1 End of buffer interrupt for this channel is enabled Before buffer chaining interrupts are enabled the DMABCINTMAP register see page 12 21 must b
404. k Divisor Latch MSB UART1BCDH Address O3F9h 7 6 5 4 3 2 1 0 Bit DIV 15 8 Reset 0 0 0 0 0 0 0 0 R W R W Register Description This register contains bits DIV 15 8 of the16 bit baud rate clock divisor used to generate the 16x baud clock The baud rate clock divisor can only be accessed when the DLAB bit is 1 in the UARTxLCR register see page 18 17 The DIV 7 0 bits are located in the UARTxBCDL register see page 18 9 Bit Definitions Bit Name Function 7 0 DIV 15 8 UART x Baud Clock Divisor Latch When the DLAB bit is 1 in the UARTxLCR register see page 18 17 this bit field holds the most significant byte of the 16 bit baud rate clock divisor that is used to generate the 16x baud clock Programming Notes Setting the DIV 15 0 bit field to 0000h in the UARTxBCDL and UARTxBCDH registers is not supported When the DLAB bit is 0 in the UARTxLCR register see page 18 17 reads from and writes to this address access the UART x Interrupt Enable UARTxINTENB register see page 18 1 1 When the DLAB bit is 1 in the UARTXxLCR register reads from and writes to this address access the UART x Baud Clock Divisor Latch MSB UARTxBCDH register The clock source frequency is selected by the CLK_SRC bit in the UARTxCTL register see page 18 3 Table 18 3 on page 18 9 lists the divisor value in decimal and hexadecimal to use with each clock frequency to achieve common baud rates 18 10 Elan SC520 Microcontroller
405. l page 12 10 Software Interrupt 22 17 NMI Control page 12 13 PCI Host Bridge Interrupt Mapping page 12 17 ECC Interrupt Mapping page 12 19 Other interrupt mapping registers 30 page 12 21 12 18 Elan SC520 Microcontroller Register Set Manual ECC Interrupt Mapping ECCMAP Programmable Interrupt Coniroller Registers AMD Memory Mapped MMCR Offset D18h 15 14 13 12 11 10 8 ECC NMI _ Bit Reserved ENB Reset 0 0 0 0 0 0 0 R W RSV R W 7 6 5 4 3 2 0 Bit Reserved ECC IRQ MAP 4 0 Reset 0 0 0 0 0 0 0 R W RSV R W Register Description This register maps the internally generated ECC single bit interrupt to any of the desired interrupt channels It also enables the ECC multi bit error as an NMI source Bit Definitions Bit Name 15 9 Reserved 8 ECC NMI ENB 7 5 Reserved Function Reserved This bit field should be written to 0 for normal system operation ECC NMI Enable This bit enables the ECC multiple bit error as an NMI source 0 ECC multiple bit error disabled as an NMI source 1 ECC multiple bit error enabled as an NMI source Reserved This bit field should be written to 0 for normal system operation Elan SC520 Microcontroller Register Set Manual 12 19 AMD Programmable Interrupt Coniroller Registers Bit Name Function 4 0 ECC IRQ MAP SDRAM ECC Interrupt Mapping 4 0 The value in this 5 bit field maps
406. lan SC520 Microcontroller Register Set Manual 6 5 PCI Bus Host Bridge Registers Bit Name Function 0 T_DPER_ Target Data Parity Interrupt Enable IRQ_ENB This bit allows data parity errors detected by the target controller to generate an interrupt 0 Data parity errors do not generate an interrupt 1 Data parity errors generate an interrupt Programming Notes This register is reset by a system reset The bits in this register are not affected by a PCI bus reset A PCI bus reset is initiated by setting the PCI_RST bit in the HBCTL register see page 6 3 Interrupt status bits are set whenever the associated event occurs regardless of the corresponding interrupt enable bit For a host bridge NMI to propagate to the CPU host bridge NMIs must be enabled via the PCI_NMI_ENB bit in the PCIHOSTMAP register see page 12 17 and NMIs must be enabled via the NMI_ENB bit in the PICICR register see page 12 4 Before host bridge interrupts are enabled the PCIHOSTMAP register see page 12 17 must be configured to route the interrupt to the appropriate interrupt request level and priority The interrupt enabled via the GNT TO INT ENB bit in the SYSARBCTL register see page 5 2 shares the interrupt controller input used by host bridge interrupts 6 6 Elan SC520 Microcontroller Register Set Manual Host Bridge Target Interrupt Status HBTGTIRQSTA Register Description AMD PCI Bus Host Bridge Registers Memory Mapped MMC
407. lan SC520 Microcontroller Register Set Manual Xv AMD xvi Introduction Chapter 18 describes the UART registers E Chapter 19 describes the synchronous serial interface SSI registers Chapter 20 describes the programmable I O PIO registers B The Index lists all registers and bits alphabetically by name and mnemonic Each chapter describes the function s memory mapped configuration region MMCR registers first followed by direct mapped and then indexed register descriptions if any Within each chapter the registers of each type are listed in ascending hexadecimal order unless descriptions for identical registers for example direct mapped UART registers are combined RELATED DOCUMENTS The following documents contain additional information that will be useful in designing an embedded application based on the ElanSC520 microcontroller AMD Documentation In addition to this manual the documentation set for the ElanSC520 microcontroller includes the following documents Flan SC520 Microcontroller User s Manual order 22004 provides a functional description of the microcontroller for both hardware and software designers Flan SC520 Microcontroller Data Sheet order 22003 includes complete pin lists pin state tables timing and thermal characteristics and package dimensions for the ElanSC520 microcontroller Other information of interest The Am4860 Microprocessor Software User s Manual or
408. ld contains the current count of GP Timer 2 The count is incremented every fourth processor clock cycle This register GPTMR2CNT can be read at any time to determine the remaining count duration until a maximum count value is reached at which time this register is reset by hardware This GPTMR2ONT register can also be written at any time If this register is written while the counter is enabled the new value is latched into the GP Timer 2 counter and counting proceeds from this new value Programming Notes Each time this GPTMR2ONT register is incremented its value is compared with the GPTMR2MAXCMPA register see page 14 18 and various actions are taken when a maximum count is reached For details see the GPTMR2CTL register bits INT ENB MAX and CONT starting on page 14 16 lan SC520 Microcontroller Register Set Manual 14 17 General Purpose Timer Registers GP Timer 2 Maxcount Compare A GPTMR2MAXCMPA Memory Mapped MMCR Offset C8Eh 15 14 13 12 11 10 9 8 Bit MCA 15 8 Reset 0 0 0 0 0 0 0 0 R W R W 7 6 5 4 3 2 1 0 Bit MCA 7 0 Reset 0 0 0 0 0 0 0 0 R W R W Register Description This register contains the single compare values for the GPTMR2CNT register see page 14 17 Bit Definitions Bit Name Function 15 0 15 0 GP Timer 2 Maxcount Compare Register A This register contains the maximum value that GP Timer 2
409. ler Register Set Manual GP DMA Controller Registers AMDA Slave DMA Channel 0 3 Mode SLDMAMODE Direct Mapped Register Description I O Address OOOBh 7 6 5 4 3 2 1 0 Bit TRNMOD 1 0 ADDDEC AINIT OPSEL 1 0 MODSEL 1 0 Reset X X X X X X X X R W W w This register indicates the transfer mode for Channels 0 3 Bit Definitions Bit 7 6 3 2 Name TRNMOD 1 0 ADDDEC AINIT OPSEL 1 0 Function Transfer Mode This bit field selects the transfer mode for the channel selected by the MODSEL bit field 00 Demand transfer mode 01 10 Block transfer mode 11 Single transfer mode Cascade mode Only Channel 4 should be programmed for cascade mode All other channels should be programmed for one of the other modes Address Decrement This bit field selects increment or decrement counting for the channel selected by the MODSEL bit field 0 Increment the DMA memory address after each transfer 1 Decrement the DMA memory address after each transfer Automatic Initialization Control This bit field enables automatic initialization for the channel selected by the MODSEL bit field 0 Automatic initialization is disabled 1 Automatic initialization is enabled Automatic initialization causes the channel s base address and transfer count registers to be restored to the values they contained prior to the DMA transfer when the transfer count ends
410. ller Register Set Manual TABLE OF CONTENTS PREFACE CHAPTER 1 CHAPTER 2 CHAPTER 3 INTRODUCTION XV lan SC520 Purpose of this XV Intended XV Overview of this Manual XV Related lt xvi AMD Documentation xvi Additional Information eee xvii Documentation Conventions xviii CONFIGURATION REGISTER OVERVIEW 1 1 1 1 Memory Mapped Configuration Region MMCR Registers 1 1 1 2 Direct Mapped I O 1 7 1 3 PCI Host Bridge Indexed Configuration Registers 1 10 1 4 RTC and CMOS RAM Indexed 1 11 SYSTEM ADDRESS MAPPING REGISTERS 2 1 2 1 iiit qe Soi ten p Met eei ata Vite raton Vae sus 2 1 2 2 RH8gisterS eue ele UL edad e REA PULS 2 1 Address Decode Control 2 2 Write Protect Violation Status WPVSTA 2 4 Programmable Address Region 0 PARO 2 5 Programmable Address Region 1 1
411. lling instead of making use of interrupt generation GP Timer 0 Retrigger This bit determines the control function provided by the GP Timer 0 input pin TMRINO when TMRINO is not configured as the timer clock source i e when the EXT CLK bit is 0 0 A high level on the TMRINO input pin allows the timer to count and a Low level on this pin holds the timer count value constant 1 If the timer is enabled a 0 to 1 edge transition on the TMRINO pin resets the existing GP Timer 0 count value and then counting continues This bit is ignored when external clocking is selected i e when the EXT CLK bitis 1 Elan SC520 Microcontroller Register Set Manual Bit Name 3 PSC_SEL 2 EXT_CLK 1 ALT_CMP 0 CONT CMP Programming Notes General Purpose Timer Registers AMDA Function GP Timer 0 Prescaler This bit selects the GP Timer 0 clock source when the TMRINO input pin is not configured as the timer clock source i e when the EXT_CLK bit is 0 0 The GP Timer 0 clock source is the internal clock 33 000 MHz or 33 333 MHz depending on the crystal frequency 1 The GP Timer 0 is pre scaled by GP Timer 2 i e the internal GP Timer 2 output is used as the input clock source for GP Timer 0 This bit is ignored when external clocking is enabled i e when the EXT bit is 1 GP Timer 0 External Clock This bit selects the external GP Timer 0 clock source 0 internal GP Timer 0 clock source is used a
412. logically removed from the cascade chain The interrupt request that is hooked to IRO of the Slave 2 controller is now routed directly to interrupt channel 5 of the Master PIC bypassing the Slave 2 controller This is useful where fewer than eight interrupts are needed in a system In this case a single EOI would need to be generated instead of two Channel 4 Slave Cascade Select 0 device attached to IR4 input 1 IR4 input used for slave cascading not valid in the ElanSC520 microcontroller In the lanSC520 microcontroller this bit is internally fixed to 0 lan SC520 Microcontroller Register Set Manual 12 33 AMD Bit Programming Notes Name S3 52 51 50 Programmable Interrupt Coniroller Registers Function Channel 3 Slave Cascade Select 0 device attached to IR3 input 1 IR3 input used for slave cascading not valid in the lanSC520 microcontroller In the ElanSC520 microcontroller this bit is internally fixed to 0 Channel 2 Slave Cascade Select 0 device attached to IR2 input 1 IR2 input used for slave cascading This bit allows the Slave 1 controller to be logically cascaded or removed from the Master PIC Since the output of the Slave 1 controller is hard wired to interrupt channel 2 of the Master PIC this bit can be used to make the Slave 1 controller transparent to the user If this bit is set Slave 1 controller is cascaded to the Master PIC If this bit is cleared Slave 1 is log
413. me DMA channel masks can be controlled via DMA registers MSTDMAMSK see page 11 90 MSTDMAMSKRST and MSTDMAGENMSK see page 11 97 Before masking an active DMA channel software must ensure that the DMA request is deasserted Masking an active channel while it is being granted might cause the system to hang 11 96 Elan SC520 Microcontroller Register Set Manual GP DMA Controller Registers Master DMA General Mask MSTDMAGENMSK AMD Direct Mapped Address OODEh 3 2 1 0 Bit Reserved CH7 DIS CH6 DIS CH5 DIS CH4 DIS Reset 1 1 1 1 R W RSV W W W W Register Description This register provides a mechanism to mask or unmask the DMA request signal to each of Channels 4 7 Bit Definitions Bit Name Function 7 4 Reserved Reserved This bit field should be written to 0 for normal system operation DMA Channel 7 Mask 0 Enable DMA Channel 7 for servicing DMA requests 3 CH7 DIS 1 Disable DMA Channel 7 from servicing DMA requests DMA Channel 6 Mask 0 Enable DMA Channel 6 for servicing DMA requests 2 CH6 DIS 1 Disable DMA Channel 6 from servicing DMA requests DMA Channel 5 Mask 0 Enable DMA Channel 5 for servicing DMA requests 1 CH5_DIS 1 Disable DMA Channel 5 from servicing DMA requests DMA Channel 4 Mask 0 Enable DMA Channel 4 for servicing DMA requests 0 CH4_DIS 1 Disable DMA Channel 4 from servicing DMA requests Programming Notes
414. me out occurs when the receive FIFO is not empty and more than four continuous character times have elapsed without more data being placed into or read out of the receive FIFO Reading a character from the receive FIFO clears the time out interrupt See the UARTxLSR and UARTxMSR register descriptions on page 18 21 and page 18 23 for information about the other interrupt events identified by the INT_ID bit field 0 INT NOT PND No Serial Port Interrupt Pending 0 Interrupt pending 1 No Interrupt pending Programming Notes Table 18 5 on page 18 14 provides a summary of UART interrupt sources Interrupts generated by the UART are cleared in a variety of ways depending on the source event For details about clearing a particular event see the event s status bit description Table 18 5 on page 18 14 lists interrupt status registers and bits For additional information see the Elan VS C520 Microcontroller User s Manual order 22004 lan SC520 Microcontroller Register Set Manual 18 13 UART Serial Port Registers Table 18 5 UART Interrupt Programming Summary Enable Status Polled Interrupt Description Register 2 Register Source Event Status Bit Receive DMA transfer count UARTXCTL UARTXSTA UART x Receive TC Detected RXTC_DET F page 18 3 page 18 4 Transmit DMA transfer count UART x Transmit TC Detected TXTC_DET Modem status change UARTXINTENB UARTxMSR Delta data carrier detect DDCD page 18 11 page 18 23
415. memory address and the page address registers for the associated channel to make up a 28 bit address A27 A0 The Channel 0 extended page address bit field DMAOADR 27 24 does not increment or decrement during DMA because this channel does not support enhanced mode 11 10 Elan SC520 Microcontroller Register Set Manual GP DMA Controller Registers AMDA GP DMA Channel 1 Extended Page GPDMAEXTPG1 Memory Mapped MMCR Offset D87h 7 6 5 4 3 2 1 0 Bit Reserved DMA1ADR 27 24 Reset 0 0 0 0 0 0 0 0 R W RSV R W Register Description This register provides the extended page address for Channel 1 Bit Definitions Bit Name Function 7 4 Reserved Reserved This bit field should be written to 0 for normal system operation 3 0 DMA1ADR DMA Channel 1 Extended Page Address 27 24 This bit field specifies the highest four memory address bits A27 A24 for Channel 1 Programming Notes The extended page address is used in conjunction with the memory address and the page address registers for the associated channel to make up a 28 bit address A27 A0 The Channel 1 extended page address bit field DMA1ADR 27 24 does not increment or decrement during DMA because this channel does not support enhanced mode lan SC520 Microcontroller Register Set Manual 11 11 AMDA GP DMA Controller Registers GP DMA Channel 2 Extended Page GPDMAEXTPG 2 Memory Mapped MMCR Offset D88h
416. memory and I O address mapping registers of the ElanSC520 microcontroller The system address mapping register set consists of 18 memory mapped configuration region MMCR registers and one direct mapped I O register used to define the memory and I O map in an lanSC520 microcontroller based system and to control specific attributes of SDRAM and ROM regions See the Elan SC520 Microcontroller User s Manual order 22004 for details about memory and I O space Table 2 1 and Table 2 2 list each type of memory and I O space register in offset order with the corresponding description s page number 2 2 REGISTERS Table 2 1 System Address Mapping MMCR Registers Register Name Mnemonic MMCR Offset Page Number Address Decode Control ADDDECCTL Write Protect Violation Status WPVSTA Programmable Address Region 0 PARO Programmable Address Region 1 PAR1 Programmable Address Region 2 PAR2 Programmable Address Region 3 PAR3 Programmable Address Region 4 PAR4 Programmable Address Region 5 PAR5 Programmable Address Region 6 PAR6 Programmable Address Region 7 PAR7 Programmable Address Region 8 PAR8 Programmable Address Region 9 PARQ Programmable Address Region 10 PAR10 Programmable Address Region 11 PAR 11 Programmable Address Region 12 PAR12 Programmable Address Region 13 PAR13 Programmable Address Region 14 PAR14 Programmable Address Region 15 PAR15 Table 2 2 System Addre
417. microcontroller or as an NMI 00000 Disables the internally generated PCI interrupt from reaching the PIC 00001 Priority P1 Master PIC IRO Highest priority 00010 Priority P2 Master PIC IR1 00011 Priority P3 Slave 1 PIC IRO Master PIC IR2 00100 Priority P4 Slave 1 PIC IR1 00101 Priority P5 Slave 1 PIC IR2 00110 Priority P6 Slave 1 PIC IR3 00111 Priority P7 Slave 1 PIC IR4 01000 Priority P8 Slave 1 PIC IR5 01001 Priority P9 Slave 1 PIC IR6 01010 Priority P10 Slave 1 PIC IR 01011 Priority P11 Master PIC IR3 01100 Priority P12 Master PIC IR4 01101 Priority P13 Slave 2 PIC IRO Master PIC IR5 01110 Priority P14 Slave 2 PIC IR1 01111 Priority P15 Slave 2 PIC IR2 10000 Priority P16 Slave 2 PIC IR3 10001 Priority P17 Slave 2 PIC IR4 10010 Priority P18 Slave 2 PIC IR5 10011 Priority P19 Slave 2 PIC IR6 10100 Priority P20 Slave 2 PIC IR7 10101 Priority P21 Master PIC IR6 10110 Priority P22 Master PIC IR7 Lowest priority 10111 11110 Disables the internally generated PCI interrupt from reaching the PIC 11111 2 NMI source For example if PCI IRQ MAP 01101b the PCI interrupt request is mapped to interrupt priority P13 in the microcontroller If PCI IRQ MAP 00000b or any binary value from 10111 11110b the PCI interrupt request is disabled from reaching the microcontroller s PIC If this field is set to 11111b then the PCI interrupt is routed and e
418. minal count not detected 1 Channel 7 terminal count detected Channel 6 Terminal Count 0 Channel 6 terminal count not detected 1 Channel 6 terminal count detected Channel 5 Terminal Count 0 Channel 5 terminal count not detected 1 Channel 5 terminal count detected Channel 4 Terminal Count 0 Channel 4 terminal count not detected 1 Channel 4 terminal count detected Elan SC520 Microcontroller Register Set Manual Master DMA Channel 4 7 Control MSTDMACTL AMD GP DMA Controller Registers Direct Mapped Address 00DOh Bit Reset R W 7 6 5 4 3 2 1 DAKSEN DRQSEN WRTSEL PRITYPE COMPTIM DMA DIS Reserved 0 0 0 0 0 0 0 RSV Register Description This register provides the control function for Channels 4 7 Bit Definitions Bit Name DAKSEN DRQSEN WRTSEL PRITYPE COMPTIM DMA DIS Function Internal dackx Sense In a discrete DMA controller this bit controls the polarity of all dackx outputs from the slave DMA controller 0 Asserted Low 1 Asserted High System logic external to the DMA controller expects the DMA controller to drive active Low dackx outputs This bit must be written to Ob for proper system operation Internal drqx Sense In a discrete DMA controller this bit controls the polarity of all drqx inputs to the slave DMA controller 0 Asserted High 1 Asserted Low System logic exter
419. ming Notes Programmable Interval Timer Registers Function Counter Mode Status Reflects the last counter mode setting for counters 0 1 or 2 that was programmed into this channel via the MODE bit field of the PITMODECTL register see page 13 8 Gate High unless noted 000 Mode 0 Interrupt on terminal count 001 Mode 1 Hardware retriggerable one shot 010 Mode 2 Rate generator 011 Mode 3 Square wave generator 100 Mode 4 Software retriggerable strobe 101 Mode 5 Hardware retriggerable strobe 110 Alias for mode 2 111 Alias for mode 3 See Table 13 2 on page 13 9 for more detail on counter modes Binary Coded Decimal Select Status Reflects the last BCD setting for counters 0 1 or 2 that was programmed into this channel via the BCD bit field of the PITMODECTL register see page 13 8 0 16 bit binary counter with a range of 0 FFFFh 1 BCD counter with a range of 0 9999 The PITxSTA register is available only after a read back command is issued by writing the PITRDBACK register with the LSTAT bit clear and the appropriate CNTx bit set see page 13 11 13 6 Elan SC520 Microcontroller Register Set Manual Programmable Interval Timer Registers AMDA PIT Mode Control PITMODECTL Direct Mapped I O Address 0043h 7 6 5 4 3 2 1 0 Bit CTR_SEL 1 0 CTR_RW_LATCH 1 0 CTR_MODE 2 0 BCD Reset 0 0 0 0 0 0 0 0 R W Register Description
420. mmed memory region Am5 86 CPU cache 1 Caching is disabled for the programmed memory region This attribute can be used to minimize cache write back cycle overhead in regions that are shared between the Am5 86 CPU and PCI bus masters or GP bus DMA devices Software must flush the cache immediately after setting this attribute xx0 Writes are enabled the programmed memory region xx1 Write protection is enabled writes are disabled in the programmed memory region Write protection prevents writes from occurring in the region s address range Write protect violations are reported by the WPVSTA register see page 2 4 and a corresponding interrupt can be enabled via the WPV INT bit the ADDDECCTL register see page 2 2 Page Size This bit selects the page size of the memory region defined by the SZ ST ADR bit field This bit is ignored during I O cycles 0 4 Kbyte page size selected 1 64 Kbyte page size selected Each PARx window s total size in memory space is defined by the combined settings of the PG SZand SZ ST ADR bit fields The PG SZ bit value affects the window start address resolution the window size resolution and the total size that is possible for the window Elan SC520 Microcontroller Register Set Manual 2 7 System Address Mapping Registers Bit Name Function 24 0 SZ_ST_ADR Region Size Start Address 24 0 This bit field in conjunction with the PG SZ bit is used to specify t
421. mpliant designs software must limit the length of GP bus cycles Elan SC520 Microcontroller Register Set Manual 10 7 General Purpose Bus Controller Registers GP Chip Select Pulse Width GPCSPW Memory Mapped MMCR Offset CO9h 7 6 5 4 3 2 1 0 Bit GPCS WIDTH 7 0 Reset 0 0 0 0 0 0 0 0 R W R W Register Description This register is used to program the pulse width for all the GP bus chip selects Bit Definitions Bit Name Function 7 0 GPCS_WIDTH Signal Width for the GP Bus Chip Selects 7 0 This field adjusts the signal pulse width time of all the GP bus chip selects The resolution of this parameter is one internal 33 MHz clock period The width used is GPCS WIDTH 1 internal clock periods i e if GPCS_WIDTH is 0 the pulse is one clock period wide Programming Notes Before using one of the GPCS7 GPCS 1 signals software must set the corresponding GPCSx SEL bit inthe CSPFS register see page 20 7 Before using the GPCSO signal software must set the PIO27 SEL bit the PIOPFSS31 16 register see page 20 5 Figure 10 1 on page 10 7 shows the relationships between the various adjustable GP bus timing parameters 10 8 Elan SC520 Microcontroller Register Set Manual General Purpose Bus Controller Registers GP Chip Select Offset GPCSOFF AMD Memory Mapped MMCR Offset COAh 7 6 5 4 3 2 1 0 Bit GPCS OFF 7 0 Reset
422. n This register contains bit fields for configuring and enabling host bridge master interrupts Bit Definitions Bit 15 14 13 12 11 10 Name Reserved M RTRTO _ IRQ SEL M TABRT IRQ SEL M MABRT _ IRQ SEL M SERR IRQ SEL Function Reserved This bit field should be written to 0 for normal system operation Master Retry Time Out Interrupt Select This bit allows master retry time outs to generate an NMI instead of a maskable interrupt 0 Master retry time outs generate a maskable interrupt 1 Master retry time outs generate an NMI Master Target Abort Interrupt Select This bit allows master controller transactions that are terminated with a target abort to generate an NMI instead of a maskable interrupt 0 Master transactions that are terminated with a master abort generate a maskable interrupt 1 Master transactions that are terminated with a master abort generate an NMI Master Abort Interrupt Select This bit allows master controller transactions that are terminated with a master abort to generate an NMI instead of a maskable interrupt 0 Master transactions that are terminated with a master abort generate a maskable interrupt 1 Master transactions that are terminated with a master abort generate an NMI Master System Error Interrupt Select This bit allows the assertion of the system error signal SERR to generate an NMI instead of a maskable interrupt 0 Assertion of the
423. n This register controls the Am5 86 CPU s cache write back mode and clock speed Bit Definitions Bit Name 7 5 Reserved 4 CACHE_WR_ MODE 3 2 Reserved 1 0 CPU_CLK_SPD 1 0 Programming Notes Function Reserved This bit field should be written to 0 for normal system operation Cache Write Mode This bit enables the write back mode of the Am5 86 CPU cache 0 Write back mode default 1 Write through mode If this bit is set the cache operates in write through mode regardless of the setting of the NW bit in the processor s internal CRO register or the PWT bit of the corresponding page table entry Reserved This bit field should be written to 0 for normal system operation CPU Clock Speed This bit field specifies the clock speed at which the Am5 86 CPU runs Note that there is a 1 ms delay for the Am5 86 CPU PLL to switch to the new frequency after this bit field is changed 00 Reserved 01 2 100 MHz default 10 133 MHz 11 Reserved The Am5 86 CPU core is reset during a hard reset and the Am5 86 CPU core clock frequency defaults to 100 MHz The Am5 86 CPU core clock frequency remains the same and the cache state and policy are unaffected by a soft reset See the Elan SC520 Microcontroller User s Manual order 22004 for details about hard and soft resets Table 3 3 on page 3 6 provides a summary of ElanSC520 microcontroller reset sources and effects Elan SC520 Microcontroller Registe
424. n system errors due to concurrence of both PCI and internal MMCR accesses PARx windows in the GP bus I O space must not include any of the following direct mapped register addresses CBAR Port FFFCh PCICFGADR Port OCF8h or PCICFGDATA Port OCFCh Also the PARx window must not overlap any direct mapped I O address belonging to an internal peripheral i e GP bus DMA PIC PIT system control ports RTC or UART I O registers When programming a PARx register for GP bus I O space it is best to start the space on a doubleword boundary If an unaligned byte region is specified for I O access the software that accesses the region must directly address the correct byte or bytes For example if a PARx register is programmed for an I O region starting at address xxx1h i e byte1 of the associated doubleword then when the CPU performs a word or doubleword access the entire access is redirected to the PCI bus and byte 1 is not accessed on the GP bus as programmed In this case the byte requested must be directly accessed by the CPU at I O address xxxth 2 8 Elan SC520 Microcontroller Register Set Manual Configuration Base Address CBAR Register Description AMD System Address Mapping Registers Direct Mapped I O Address FFFCh 31 30 29 28 27 26 25 24 Bit ENABLE Reserved ADR 29 24 Reset 0 0 0 0 0 0
425. n this address Port 0043h is written with bits 7 6 11b and bits 5 4 00b this address is redefined for the duration of the current I O write as the PITCNTLAT register see page 13 10 5 LCNT Latch Count Low True 0 Latch count data for the counters selected via bits CNT2 CNTO 1 Do not latch count data for the counters selected via bits CNT2 CNTO 4 LSTAT Latch Status Low True 0 Latch the status byte for the counters selected via bits CNT2 CNTO 1 not latch the status byte for the counters selected via bits CNT2 CNTO 3 CNT2 Select Counter 2 0 Counter 2 is not selected for operations specified by bits LCNT and LSTAT 1 Counter 2 is selected for operations specified by bits LCNT and LSTAT 2 CNT1 Select Counter 1 0 Counter 1 is not selected for operations specified by bits LCNT and LSTAT 1 Counter 1 is selected for operations specified by bits LCNT and LSTAT 1 CNTO Select Counter 0 0 Counter 0 is not selected for operations specified by bits LCNT and LSTAT 1 Counter 0 is selected for operations specified by bits LCNT and LSTAT Elan SC520 Microcontroller Register Set Manual 13 11 AMDA Programmable Interval Timer Registers Bit Name Function 0 Reserved Reserved This bit field should be written to 0 for normal system operation Programming Notes Reads of this register PITRDBACK return an undefined value When a counter s current value is required software should obtain it
426. n to 0 for normal system operation 11 Reserved 10 GPINT10 POL General Purpose Interrupt Request GPIRQ10 Polarity 0 Low to High transition or High level sensitive interrupt 1 High to Low transition or Low level sensitive interrupt 9 GPINT9 POL General Purpose Interrupt Request GPIRQ9 Polarity 0 Low to High transition or High level sensitive interrupt 1 High to Low transition or Low level sensitive interrupt 8 GPINT8_POL General Purpose Interrupt Request GPIRQ8 Polarity 0 Low to High transition or High level sensitive interrupt 1 High to Low transition or Low level sensitive interrupt T GPINT7_POL General Purpose Interrupt Request GPIRQ7 Polarity 0 Low to High transition or High level sensitive interrupt 1 High to Low transition or Low level sensitive interrupt Elan SC520 Microcontroller Register Set Manual 12 15 AMD Programmable Interrupt Coniroller Registers Bit Name Function 6 GPINT6_POL General Purpose Interrupt Request GPIRQ6 Polarity 0 Low to High transition or High level sensitive interrupt 1 High to Low transition or Low level sensitive interrupt 5 GPINT5 POL General Purpose Interrupt Request GPIRQ5 Polarity 0 Low to High transition or High level sensitive interrupt 1 High to Low transition or Low level sensitive interrupt 4 GPINT4_POL General Purpose Interrupt Request GPIRQ4 Polarity 0 Low to High transition or High level sensitive interrupt 1 High to Low transition or Low level
427. nabled as an NMI source If bit S2 in the MPICICWS register is cleared see page 12 34 the Slave 1 PIC is bypassed so programming the PCI IRQ bit field to a value in the range 00100 01010b does not pass the interrupt request to the CPU However if this bit field is programmed to 00011b with the S2 bit cleared the PCI interrupt request is routed to the Master PIC IR2 input If bit S5 in the MPICICWS register is cleared see page 12 33 the Slave 2 PIC is bypassed so programming the PCI IRQ MAP bit field to a value in the range 01110 10100b does not pass the interrupt request to the CPU However if this field is programmed to 01101b with the S5 bit cleared the PCI interrupt request is routed to Master PIC IR5 input o 5 wo Programming Notes This register should be programmed only when the corresponding interrupt channel mask bits are set in the PIC For NMls this register should be programmed only when bit NMI is cleared in the PICICR register see page 12 4 NMI ENB can be set immediately after programming this register PCIHOSTMAP to allow NMls to be passed to the CPU Programming more than one interrupt source to an interrupt channel results in interrupt sharing on that channel Programming more than one interrupt source as an NMI source results in NMI sharing on the CPU s NMI input All interrupt and NMI sources can be found in the following register descriptions W Software Interrupt 16 1 Contro
428. nal to the DMA controller expects the DMA controller to respond to active High drqx inputs This bit must be written to Ob for proper system operation Write Selection Control 0 Late write selection 1 Extended early write selection Write command signals GPIOWR and GPMEMWR are asserted one clock early Enabling this feature results in timing changes on the GP bus that can violate the ISA specification This bit has no effect when the COMPTIM bit is 1 Priority Type 0 Fixed priority 1 Rotating priority Compressed Timing 0 Normal timing 1 Compressed timing Read command signals GPIORD and GPMEMRD have a one clock pulse width Enabling this feature results in timing changes on the GP bus that can violate the ISA specification Disable DMA Controller 0 requests are enabled 1 DMA requests are ignored but DMA registers are available to the CPU The DMA controller should be disabled prior to programming it in order to prevent unintended transfers from occurring during the DMA controller programming operation Care should also be taken to ensure that the DMA controller is idle before disabling it If the DMA controller is performing a transfer when software disables it abnormal system operation can occur lan SC520 Microcontroller Register Set Manual 11 87 GP DMA Controller Registers Bit Name Function 1 0 Reserved Reserved This bit field should be written to 0 for normal syst
429. nating the transaction with a target abort The PERR_RES bit must not be changed except during PCI bus initialization after a system reset See the Elan SC520 Microcontroller User s Manual order 22004 for information about PCI bus initialization Reserved This bit field should be written to 0 for normal system operation Master Enable This enables the host bridge master controller to generate cycles on the PCI bus 1 The host bridge master controller is always enabled This bit is internally fixed to 1 Memory Access Enable This bit enables the host bridge target controller to respond to PCI bus master memory cycles 0 The host bridge target controller is disabled 1 The host bridge target controller is enabled to respond to PCI bus master memory cycles The MEM_ENB bit must not be changed except during PCI bus initialization after a system reset See the Elan SC520 Microcontroller User s Manual order 22004 for information about PCI bus initialization I O Space Enable This bit is normally used to enable the host bridge target controller to respond to PCI bus master I O cycles however the ElanSC520 microcontroller host bridge ignores all I O cycles from PCI bus masters 0 The host bridge does not respond to PCI bus I O cycles This bit is internally fixed to O This register is reset by a system reset or by a PCI bus reset A PCI bus reset is initiated by setting the PCI RST bit in the HBCTL register see page
430. nce Writing to Port 00AO0h with bit 4 1 causes the S1PICICW1 register to be written and also resets the PIC s internal state machine and the internal S1PICICWx register pointer Then S1PICICWx registers 2 4 can be programmed by sequential writes to Port O0A1h Each time Port OOA1h is written to following the write to S1PICICW1 the internal register pointer points to the next S1PICICWx register S1PICICW1 and S1PICICW2 must always be programmed Also the S1PICICWS register must always be programmed in this design because the SNGL bit in S1PICICW1 is internally fixed to 0 The S1PICICWA register is skipped if the IC4 bit in S1PICICW1 is 0 If the S2 bit in the MPICICWS3 register is cleared see page 12 34 then the Slave 1 controller is bypassed and programming this register does not affect other registers Port OOAOh provides access to different Slave 1 PIC registers based on the data that is written Table 12 9 provides a summary of bit patterns to write for access to each register Table 12 9 Slave 1 PIC Port OOAOh Access Summary Bits Port 00A0h Register Written Next Port 00A0h Read Returns 1 x S1PICOCW2 page 12 53 0 S1PICOCWS page 12 55 1 P S1PICOCW3 S1PICIR page 12 49 S1PICOCW3 S1PICISR page 12 50 x S1PICICW1 page 12 51 5 x x 0 0 0 12 52 Elan SC520 Microcontroller Register Set Manual Programmable Interrupt Coniroller Registers AMD Slave 1
431. nd RTCCURSEO RTC Alarm Second RTC Current Minute RTCCURMIN RTC Alarm Minute RTC Current Hour RTC Alarm Hour RTC Current Day of the Week RTCCURDOW RTC Current Day of the Month RTCCURDOM RTC Current Month RTC Current Year RTC Control A RTCCTLA RTC Control B RTCCTLB RTC Status C RTC Status D General Purpose CMOS RAM 114 bytes RTCCMOS CHAPTER 18 UART SERIAL PORT REGISTERS 18 1 QVeIVIOW s iue heise ur ELSE ERE 18 2 Hegisters I bI eene UR CDD Sere Pind Gad eared UART 1 General Control UART 2 General Control 2 UART 1 General Status UART1STA UART 2 General Status UART2STA UART 1 FIFO Control Shadow UART1FCRSHAD UART 2 FIFO Control Shadow UART2FCRSHAD UART 2 Transmit Holding 2 UART 1 Transmit Holding 1 UART 2 Receive Buffer UART2RBR UART 1 R
432. nd being compared to the GPTMROMAXCMPB register If the CONT CMP bit is set alternate compare mode generates a square wave signal on the TMROUTO pin with a frequency and duty cycle determined by the two maximum count register values Note If external clocking is used and the clock is stopped during a count sequence the timer output remains in its previous state i e the state it was in prior to the clock stopping The remaining timer status also remains the same and normal operation commences upon the external clock being driven again See the CONT bit description for a more detailed description of how the comparison registers are used in continuous and noncontinuous modes GP Timer 0 Continuous Mode This bit is used to configure GP Timer 0 for continuous or noncontinuous mode 0 Noncontinuous mode the GPTMROCNT register see page 14 12 is cleared and the timer halts whenever the count reaches the maximum count value The ENB bit is also cleared by hardware after every counter sequence 1 Continuous mode The timer count is reset to O after it reaches the maximum count value A or B and the timer immediately begins counting again If the CONT CMP bit is cleared and the ALT CMP bit is set GP Timer 0 counts to the GPTMROMAXCMPA register value see page 14 13 and then resets the count value After the timer count has been reset the timer continues operation by counting to the GPTMROMAXCMPB register value page 14 14 Wh
433. nfiguration cycle 7 2 REGISTER_ Register Number NUM 5 0 This bit field specifies the register number within the function specified by the FUNCTION NUM bit field For host bridge configuration cycles if the BUS NUM and DEVICE NUM bit fields are both 0 the REGISTER NUM bit field is used to address the host bridge PCl indexed registers see the descriptions beginning on page 6 18 REGISTER NUM bits 5 0 are used as bits 7 2 of the PCI index address to address doublewords in the configuration space Byte locations within a doubleword are addressed by accessing the corresponding bytes of the PCICFGDATA register see page 6 17 For all other configuration cycles type zero or type one the contents of this bit field are driven unchanged on the PCI bus during the address phase of the configuration cycle 1 0 Reserved Reserved This bit field is ignored during writes to this register It always returns 0 when read During the address phase of a configuration cycle address pins AD1 ADO are driven to 00b to indicate a type zero configuration cycle or to 01b to indicate a type one configuration cycle depending on value of the BUS NUM bit field Programming Notes After this register PCICFGADR is written with the requisite information an access must be made to the PCICFGDATA register see page 6 17 to cause the PCI bus configuration cycle to occur on the PCI bus This register is reset by a system reset The bits in this register are
434. nt of the RTC time can be read from this bit field Writing a value of CO FFh to this register makes the hours component of the alarm a wild card For example setting the hours alarm register to COh causes an RTC alarm event to be generated once per hour Note that if this register is written with a wild card when 12 hour mode is selected the ALM AM PM bit is a don t care because an alarm occurs every hour regardless The RTC logic checks once per second to see if an alarm has occurred In 24 hour mode valid values for this bit field range from 0 to 23d and all wild card values In 12 hour mode valid values for this bit field range from 1 to 12d and all wild card values Elan SC520 Microcontroller Register Set Manual 17 9 Real Time Clock Registers RTC Current Day of the Week RTCCURDOW Address 70h 71h RTC Index OGh 7 6 5 4 3 2 1 0 Bit DAY OF WEEK 7 0 Reset X X X X X X X X R W R W Register Description This register used to initialize and read back the RTC current day of the week Bit Definitions Bit Name Function 7 0 DAY OF RTC Current Day of the Week WEEK 7 0 Software initializes the day of week value for the RTC by writing data to this bit field in either binary or binary coded decimal BCD formats The RTC logic updates this bit field once per second Valid values for this bit field range from 1d to 7d where 1d Sunday 2d Monday 3d Tuesday 4d We
435. nterrupt assertion 0 Do not assert the interrupt 1 2 Assert the interrupt 3 SW P4 TRIG Directly Trigger Priority Level P4 Setting this bit directly asserts a maskable interrupt of priority level P4 Clearing this bit removes this direct interrupt assertion 0 Do not assert the interrupt 1 Assert the interrupt 2 SW P3 TRIG Directly Trigger Priority Level P3 Setting this bit directly asserts a maskable interrupt of priority level P3 Clearing this bit removes this direct interrupt assertion 0 Do not assert the interrupt 1 2 Assert the interrupt 1 SW P2 TRIG Directly Trigger Priority Level P2 Setting this bit directly asserts a maskable interrupt of priority level P2 Clearing this bit removes this direct interrupt assertion 0 Do not assert the interrupt 1 2 Assert the interrupt lan SC520 Microcontroller Register Set Manual 12 11 AMD Programmable Interrupt Coniroller Registers Bit Name Function 0 SW_P1_TRIG Directly Trigger Priority Level P1 Setting this bit directly asserts a maskable interrupt of priority level P1 Clearing this bit removes this direct interrupt assertion This is the highest interrupt priority level 0 Do not assert the interrupt 1 2 Assert the interrupt Programming Notes This register SWINT16 1 and register SWINT22 17 provide access to all 22 maskable interrupt priority levels Priority level P1 is the highest priority and priority level P22 is the lowest Setting an
436. nterrupt requests If the S2 GINT MODE bit is cleared the Slave 2 LTIM bit has no meaning and the Slave 2 PIC channels can be programmed individually via the SL2PICMODE register see page 12 9 to select either edge or level sensitive interrupt recognition 12 4 Elan SC520 Microcontroller Register Set Manual Bit Name 1 S1_GINT_ MODE 0 M_GINT_ MODE Programming Notes Programmable Interrupt Coniroller Registers AMD Function Slave 1 PIC Global Interrupt Mode Enable This bit provides a global or individual channel interrupt mode for the Slave 1 PIC 0 Slave 1 PIC global interrupt mode disabled 1 Slave 1 PIC global interrupt mode enabled If the S1 GINT MODE bit is set bit LTIM of the S1PICICW1 register see page 12 51 determines the interrupt mode for the Slave 1 PIC channels If the 1 GINT MODE bit and the LTIM bit are set all the Slave 1 PIC interrupt channels recognize level sensitive interrupt requests If the S1 GINT MODE bit is set and the LTIM bit is cleared all the Slave 1 PIC interrupt channels recognize edge sensitive interrupt requests If the S1 GINT MODE bit is cleared the Slave 1 LTIM bit has no meaning and the Slave 1 PIC channels can be programmed individually via the SL1PICMODE register see page 12 8 to select either edge or level sensitive interrupt recognition Master PIC Global Interrupt Mode Enable This bit provides a global or individual channel interrupt mode for the Master PIC 0 Master
437. ntification for the lanSC520 microcontroller host bridge Bit Definitions Bit Name 31 16 10 15 0 15 0 ID 15 0 Programming Notes Function Device ID 3000h This bit field identifies the lanSC520 microcontroller host bridge PCI bus device Vendor ID 1022h This bit field identifies Advanced Micro Devices Inc as the vendor of the ElanSC520 microcontroller host bridge PCI bus device This register PCIDEVID is register number 0 in the host bridge specific PCI configuration space 6 18 Elan SC520 Microcontroller Register Set Manual Status Command PCISTACMD PCI Bus Host Bridge Registers AMD Address OCF8h OCFCh PCI Index O4h 31 30 29 28 27 26 25 24 R MST R TGT S TGT D PERR Bit DET SIG S DVSL TIM 1 0 DET Reset 0 0 0 0 0 0 1 0 R W R W R W R W R W R R W 23 22 21 20 19 18 17 16 Bit FBTB UDFS 66M_CAP Reserved Reset 1 0 0 0 0 0 0 0 R W R R R RSV 15 14 13 12 11 10 9 8 Bit Reserved SERR_ENB Reset 0 0 0 0 0 0 0 0 R W RSV R 7 6 5 4 3 2 1 0 Bit Reserved PERR RES Reserved BUS MAS MEM IO Reset 0 0 0 0 0 1 0 0 R W RSV R W RSV R R W R Register Description This register contains the PCI configuration header space command and status register bits Bit Definitions Bit N
438. o determine where the timer is in its current count sequence 0 Hardware clears this MAX CNT RIU bit when the GPTMROMAXCMPA register see page 14 7 is being used for comparison to the GP Timer 0 count value 1 Hardware sets this MAX CNT RIU bit when the GPTMROMAXCMPPB register see page 14 8 is being used for comparison to the GP Timer 0 count value Hardware also clears this bit any time hardware disables the timer by clearing the ENB bit i e at the end of the timer count when in noncontinuous mode See the CONT bit description on page 14 5 Reserved This bit field should be written to 0 for normal system operation GP Timer 0 Maximum Count This bit can be used by software with the MAX CNT RIU bit to determine where the timer is in its current count sequence 0 Software must clear this bit by writing a O to it This bit is never automatically cleared by hardware 1 This bit is set by hardware any time the timer count value reaches a maximum count value maximum count value A or maximum count value B This bit cannot be set by software When GP Timer 0 is in alternate compare mode the ALT bit 1 the MAX CNT bit is set whenever the timer 0 count value equals the value of either register GPTMROMAXCMPA see page 14 7 or GPTMROMAXCMPB page 14 8 The MAX ONT bit is set for this condition regardless of the state of the INT bit The MAX ONT bit can be used to monitor timer status through software po
439. ocontroller Register Set Manual Programmable Interrupt Coniroller Registers Interrupt Pin Polarity INTPINPOL AMD Memory Mapped MMCR Offset D10h 15 14 13 12 11 10 9 8 GPINT10 GPINT9 GPINT8_ Bit INTD POL INTC POL INTB POL INTA POL Reserved POL POL POL Reset 0 0 0 0 0 0 0 0 R W R W R W R W R W RSV R W R W R W 7 6 5 4 3 2 1 0 Bit GPINT7 GPINT6 GPINT5_ 4 GPINT3 GPINT2 GPINT1_ GPINTO_ POL POL POL POL POL POL POL POL Reset 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Register Description This register determines the polarity to be used for each external interrupt source Bit Definitions Function PCI Interrupt Request INTD Polarity 0 High to Low transition or Low level sensitive interrupt Bit Name 15 INTD_POL 1 Low to High transition or High level sensitive interrupt PCI Interrupt Request INTC Polarity 0 High to Low transition or Low level sensitive interrupt 14 INTC_POL 1 Low to High transition or High level sensitive interrupt 13 INTB_POL PCI Interrupt Request INTB Polarity 0 High to Low transition or Low level sensitive interrupt 1 Low to High transition or High level sensitive interrupt PCI Interrupt Request INTA Polarity 0 High to Low transition or Low level sensitive interrupt 12 INTA_POL 1 Low to High transition or High level sensitive interrupt Reserved This bit field should be writte
440. of the PITMODECTL register see page 13 7 Either a latched or unlatched free running count value can be read from this bit field CHO CNT A latched count can be read immediately after a counter latch command is issued via the PITCNTLAT register see page 13 10 After the one or two bytes of latched count data are read subsequent reads return the unlatched count A latched count can also be read immediately following a read back command issued via the PITRDBACK register in which the LCNT bit is 0 and the CNTO bit is 1 see page 13 11 In this case also after the one or two bytes of latched count are read subsequent reads return the unlatched count Programming Notes If a read back command is issued by writing the PITRDBACK register with the LSTAT bit clear and the CNTO bit set see page 13 11 the subsequent read to this address Port 0040h returns the PITOSTA register status byte see page 13 5 If a read back command is issued in which PITRDBACK register bits LSTAT and LCNT are clear and bit CNTO is set the first subsequent read from this address Port 0040h returns the status byte and the following one or two reads return latched count data as defined by the CTR RW LATCH bit field of the PITMODECTL register see page 13 7 This counter can be configured for either binary coded decimal BCD or 16 bit binary operation viathe PITMODECTL register s BCD bit see page 13 8 The counter range is 0O FFFFh in binary mode or 0 9999d
441. of one memory mapped configuration region MMCR register See the Elan SC520 Microcontroller Users Manual order 22004 for details about the write buffer and read buffer Table 8 1 lists the DBCTL register and the corresponding description s page number 8 2 REGISTER Table 8 1 Write Buffer and Read Buffer MMCR Register Register Name Mnemonic MMCR Offset Page Number SDRAM Buffer Control DBCTL 40h page 8 2 Elan SC520 Microcontroller Register Set Manual 8 1 AMD SDRAM Buffer Control DBCTL Write Buffer and Read Buffer Register Memory Mapped MMCR Offset 40h 7 6 5 4 3 2 1 0 Bit Reserved RAB ENB WB WN 1 0 WB FLUSH WB ENB Reset 0 0 0 0 0 0 0 0 R W RSV R W R W R W R W Register Description This register controls all the read buffer read ahead and write buffer functions Note A programmable reset does not preserve this register s state Bit Definitions Bit Name Function 7 5 Reserved Reserved This bit field should be written to 0 for normal system operation 4 RAB_ENB Read Ahead Feature Enable This bit is used to enable the read ahead feature of the read buffer 0 The read ahead feature is disabled 1 The read ahead feature is enabled If the master request is a burst cycle two or more doublewords when the current cache line is fetched from SDRAM and stored in the read buffer the following cache line is also prefetched to take advantage of space locality If
442. of the PITMODECTL register see page 13 7 3 0 Reserved Reserved This bit field should be written to 0 for normal system operation Programming Notes Reads of this register PITCNTLAT return an undefined value When a counter s current value is required software should obtain it by issuing a counter latch or read back command via the PITCNTLAT or PITRDBACK register see page 13 10 or page 13 11 A counter latch or read back command does not stop a counter from running but rather takes a snapshot of the current value Once the count has been latched further latch commands are ignored until all latched count data is read back from the associated count register A read back command is a higher priority command than the counter latch command The counter latch command is a subset of the read back command because only one channel can have its counter latched per counter latch command The programmable interval timer does not provide any way to read back the original count programmed into any of the three count registers 13 10 Elan SC520 Microcontroller Register Set Manual Programmable Interval Timer Registers AMDA PIT Read Back Command PITRDBACK Direct Mapped I O Address 0043h 7 6 5 4 3 2 1 0 Bit CTR_SEL 1 0 LCNT LSTAT CNT2 CNT1 CNTO Reserved Reset 0 0 0 0 0 0 0 0 R W W W W RSV Register Description This register allows the status and current count of each channel to be read
443. og Timer MMCR Registers Register Name Mnemonic MMCR Offset Page Number Watchdog Timer Control WDTMRCTL page 16 2 Watchdog Timer Count Low WDTMRCNTL page 16 4 Watchdog Timer Count High WDTMRCNTH page 16 5 Reserved Elan SC520 Microcontroller Register Set Manual 16 1 AMD Watchdog Timer Control WDTMRCTL Watchdog Timer Registers Memory Mapped MMCR Offset CBOh 15 14 13 12 11 10 9 8 Bit ENB WRST_ENB Reserved IRQ FLG Reserved Reset 0 1 0 0 0 0 0 0 R W R W R W RSV R W RSV 7 6 5 4 3 2 1 0 Bit EXP_SEL 7 0 Reset 1 0 0 0 0 0 0 0 R W R W Register Description This register is used to control the watchdog timer This register can only be accessed after writing special keyed sequences as described in the programming notes Bit Definitions Bit 15 14 13 12 16 2 Name ENB WRST_ENB Reserved IRQ_FLG Reserved Function Watchdog Timer Enable This is the watchdog timer enable bit 0 The watchdog timer is disabled 1 The watchdog timer is enabled When this bit is set the current count is automatically reset to 0 the WRST_ENB and EXP_SEL fields become read only and the watchdog timer counter begins counting Before the watchdog timer is enabled with the WRST_ENB bit cleared the WDTMAP register see page 12 21 must be configured to route the interrupt to the appropriate interrupt request le
444. ombinations thereof AMDebug E86 and Elan are trademarks Am486 and Am5 86 are registered trademarks and FusionE86 is a service mark of Advanced Micro Devices Inc Product names used in this publication are for identification purposes only and may be trademarks of their respective companies AMD IF YOU HAVE QUESTIONS WE RE HERE TO HELP YOU The AMD customer service network includes U S offices international offices and a customer training center Expert technical assistance is available from the AMD worldwide staff of field application engineers and factory support staff to answer E86 family hardware and software development questions Frequently accessed numbers are listed below Additional contact information is listed on the back of this manual AMD s WWW site lists the latest phone numbers Technical Support Answers to technical questions are available online through e mail and by telephone Go to AMD s home page at www amd com and follow the Support link for the latest AMD technical support phone numbers software and Frequently Asked Questions For technical support questions on all E86 products send e mail to epd support amd com in the US and Canada or euro tech amd com in Europe and the UK You can also call the AMD Corporate Applications Hotline at 800 222 9323 Toll free for U S and Canada 44 0 1276 803 299 U K and Europe hotline WWW Support For specific information on E86 products access the A
445. on the cascade bus In the lanSC520 microcontroller design these bits are internally fixed to 010b Programming Notes The PIC s initialization control word 81PICICWX registers 1 4 must be programmed in sequence Writing to Port 00AO0h with bit 4 1 causes the S1PICICW1 register to be written and also resets the PIC s internal state machine and the internal S1PICICWx register pointer Then S1PICICWx registers 2 4 can be programmed by sequential writes to Port OOA1h Each time Port 00 1 is written to following the write to S1PICICW1 the internal register pointer points to the next S1PICICWX register S1TPICICW1 and S1PICICW2 must always be programmed Also the S1PICICWS register must always be programmed in this design because the SNGL bit in S1PICICW1 is internally fixed to 0 The S1PICICWA register is skipped if the IC4 bit in S1PICICW1 is 0 If the S2 bit in the MPICICWS register is cleared see page 12 34 a write to this register S1PICICW3 is always expected in the ElanSC520 microcontroller because the SNGL bit is fixed to 0 in the S1PICICW 1 register page 12 52 If the S2 bit in the MPICICWS register is cleared then the Slave 1 controller is bypassed and the value of this register S1PICICW3 has no effect 12 58 Elan SC520 Microcontroller Register Set Manual Programmable Interrupt Coniroller Registers AMD Slave 1 PIC Initialization Control Word 4 S1PICICW4 Direct Mapped I O Address 00A1h
446. onding PIOx_FNC bit is set in the PIOPFS15 0 register see page 20 3 If the PIOx FNC bit is set the corresponding pin is assigned its interface function not its PIO function Although software can perform a 32 bit access of MMCR offset C2Ah to set the direction for all 32 PIO pins with a single instruction the 32 bit access is split into two separate 16 bit accesses with the PIODIR15 0 register being accessed prior to the PIODIR31 16 register The two accesses are not simultaneous Elan SC520 Microcontroller Register Set Manual 20 13 AM DA Programmable Input Output Registers PIO31 PIO16 Direction PIODIR31_16 Memory Mapped MMCR Offset C2Ch 15 14 13 12 11 10 9 8 Bi PIO31_ PIO30 PIO29 PIO28 PIO27 PIO26 PIO25 PIO24 i DIR DIR DIR DIR DIR DIR DIR DIR Reset 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W 7 6 5 4 3 2 1 0 Bic 02 _ PIO22_ PIO21_ PIO20_ PIO19_ PIO18_ PIO17_ PIO16_ DIR DIR DIR DIR DIR DIR DIR DIR Reset 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Register Description This register contains the direction bits for pins PIO31 PIO16 Bit Definitions Bit Name Function 15 PIO31 DIR PIO31 Input or Output Select This bit programs PIO31 as an input or output 0 Input 1 Output 14 PIO30 DIR Input or Output Select This bit programs PIO30 as an input or output 0 Input 1 Output 13 PIO29 DIR PIO29 Input or Output Select T
447. onous Serial Interface Registers SSI Transmit SSIXMIT Memory Mapped MMCR Offset CD1h 7 6 5 4 3 2 1 0 Bit DAT OUT 7 0 Reset 0 0 0 0 0 0 0 0 R W R W Register Description This register is used to write data to be transmitted Bit Definitions Bit Name Function 7 0 DAT OUT 7 0 SSI Data Out Software uses this bit field to write eight bits to be shifted out on the SSI DO pin After writing to this bit field software must write a Transmit command or a Simultaneous Transmit Receive command to the SSICMD register see page 19 5 to send the data The contents of this bit field DAT OUT are not destroyed when transmitted so the user can repeatedly transmit the same data by writing the appropriate transmit command to the SSICMD register Programming Notes This register should not be written while the BSY bit is set in the SSISTA register see page 19 6 19 4 Elan SC520 Microcontroller Register Set Manual Synchronous Serial Interface Registers AMDA SSI Command SSICMD Memory Mapped MMCR Offset CD2h 7 6 5 4 3 2 1 0 Bit Reserved CMD_SEL 1 0 Reset 0 0 0 0 0 0 0 0 R W RSV R W Register Description This register is used to write the transfer command to be executed Bit Definitions Bit Name 7 2 Reserved 1 0 CMD_SEL 1 0 Programming Notes Function Reserved This bit field should be written to 0 for normal system operation
448. ons from 0 to 1 see page 17 18 the RTC periodic interrupt latches the INT FLG bit in the RTCSTAC register to 1 see page 17 18 If the PER INT FLG bit is 1 when the PER INT bit is set by software the INT FLG bit is asserted immediately The PER INT ENB bit is not modified by any internal RTC functions but is cleared by an RTC only reset The periodic interrupt rate is configured with the RATE SEL bit field in the RTCCTLA register see page 17 15 The PER INT FLG bit in the RTCSTAC register provides latched status for the RTC periodic event see page 17 18 Before any RTC interrupt is enabled the RTCMAP register see page 12 21 must be configured to route the interrupt to the appropriate interrupt request level and priority Alarm Interrupt Enable 0 No RTC alarm interrupt is generated 1 The RTC alarm interrupt is enabled When the ALM INT FLG bit in the RTCSTAC register transitions from 0 to 1 see page 17 18 the RTC alarm interrupt latches the FLG bit in the RTCSTAC register to 1 see page 17 18 If the INT FLG bit is 1 when the ALM INT ENB bit is set by software the INT FLG bit is asserted immediately The ALM INT ENB bit is not modified by any internal RTC functions but is cleared by an RTC only reset The alarm interrupt time is configured with the RTCALMSEC 17 5 RTCALMMIN page 17 7 and RTCALMHR page 17 9 registers The ALM INT FLG bit in the RTCSTAC register provides latched statu
449. ontrol and status functions for the RTC as well as user CMOS RAM locations Table 1 4 lists all of the RTC indexed registers in the ElanSC520 microcontroller Table 1 4 Register Name RTC Current Second Real Time Clock Indexed Registers Mnemonic RTCCURSEC Address 70h 71h RTC Index Page Number page 17 4 RTC Alarm Second RTCALMSEC 70h 7 1h page 17 5 RTC Current Minute RTCCURMIN 70h 7 1h page 17 6 RTC Alarm Minute RTCALMMIN 70h 71h page 17 7 RTC Current Hour RTCCURHR 70h 7 1h page 17 8 RTC Alarm Hour RTCALMHR 70h 71h page 17 9 RTC Current Day of the Week RTCCURDOW 70h 7 1h page 17 10 RTC Current Day of the Month RTCCURDOM 70h 71h page 17 11 RTC Current Month RTCCURMON 70h 71h page 17 12 RTC Current Year RTCCURYR 70h 7 1h page 17 13 RTC Control A RTCCTLA 70h 71h page 17 14 RTC Control B RTCCTLB 70h 71h page 17 16 RTC Status C RTCSTAC 70h 7 1h page 17 18 RTC Status D RTCSTAD 70h 7 1h page 17 20 General Purpose CMOS RAM 114 bytes Elan SC520 Microcontroller Register Set Manual RTCCMOS 70h 7 1h page 17 21 AMDA Configuration Register Overview 1 12 Elan SC520 Microcontroller Register Set Manual ENS _ AMDA AMD 1 2 SYSTEM ADDRESS MAPPING REGISTERS 2 1 OVERVIEW This chapter describes the system
450. or GP bus width operation mode and timing of the boot ROM that is attached to the ElanSC520 microcontroller BOOTCS signal Bit Definitions Bit Name 15 13 Reserved 12 DGP 11 10 WIDTH 1 0 9 MODE 8 6 Reserved 5 4 SUB_DLY 1 0 9 2 Function Reserved This bit field should be written to 0 for normal system operation BOOTCS Device SDRAM GP Bus Select This bit reflects the location of the boot ROM device that is enabled with the BOOTCS signal This bit s value is latched from the CFG2 pinstrap when the PWRGOOD pin is asserted The ROM can be connected to either the SDRAM data bus or to the GP bus 0 ROM is on the GP bus 1 ROM is on the SDRAM data bus BOOTCS Device Width Select This bit field reflects the width of the boot ROM This bit field s value is latched from the CFG1 CFGO0 pinstraps when the PWRGOOD pin is asserted 00 ROM is 8 bits wide 01 ROM is 16 bits wide 10 ROM is 32 bits wide 11 ROM is 32 bits wide same as 10b BOOTCS Device Mode This bit is used to configure the mode of the boot ROM device 0 ROM is non page mode 1 ROM is page mode Reserved This bit field should be written to 0 for normal system operation BOOTCS Device Delay for Subsequent Access This bit field is used to configure the number of wait states for all page mode accesses to the ROM that are subsequent to the first access This bit field applies only if the MODE bit is 1 00 0 wait states 01
451. ose register Bit Definitions Bit Name 7 0 PORT84 7 0 Programming Notes 11 66 Function General Purpose R W Register Writes to this bit field are stored internally and propagated to the GP bus Reads from this bit field return the internal register value but are not propagated to the GP bus Elan SC520 Microcontroller Register Set Manual GP DMA Controller Registers AMDA General 2 GPDMAGR2 Direct Mapped I O Address 0085h 7 6 5 4 3 2 1 0 Bit PORT85 7 0 Reset 0 0 0 0 0 0 0 0 R W R W Register Description This is a general purpose register Bit Definitions Bit Name Function 7 0 PORT85 7 0 General Purpose R W Register Writes to this bit field are stored internally and propagated to the GP bus Reads from this bit field return the internal register value but are not propagated to the GP bus Programming Notes Elan SC520 Microcontroller Register Set Manual 11 67 AMD General 3 GPDMAGR3 GP DMA Controller Registers Direct Mapped Address 0086h 7 6 5 4 3 1 0 Bit 86 7 0 Reset 0 0 0 0 0 0 0 R W R W Register Description This is a general purpose register Bit Definitions Bit Name Function 7 0 PORT86 7 0 General Purpose R W Register Writes to this bit field are stored internally and propagated to the GP bus Reads from this bit field return the internal register value but are not
452. ould be written to 0 for normal system operation Chip Select 2 Device SDRAM GP Bus Select This bit is used to configure the location of the ROM devices that are enabled by ROMCS2 The ROM can be connected either to the SDRAM data bus or to the GP bus 0 ROM is on the GP bus 1 ROM is on the SDRAM data bus Chip Select 2 Device Width Select This bit field is used to configure the width of the ROM selected by ROMCS2 00 ROM is 8 bits wide 01 ROM is 16 bits wide 10 ROM is 32 bits wide 11 ROM is 32 bits wide Chip Select 2 Device Mode This bit is used to configure the mode of the ROM selected by ROMCS2 0 ROM is non page mode 1 ROM is page mode Reserved This bit field should be written to 0 for normal system operation Chip Select 2 Device Delay for Subsequent Accesses This bit field is used to configure the number of wait states for all page mode accesses to the ROM that are subsequent to the first access This bit field applies only if the MODE bit is 1 00 0 wait states 01 1 wait state 10 2 wait states 11 wait states Reserved This bit field should be written to 0 for normal system operation Elan SC520 Microcontroller Register Set Manual ROM Flash Controller Registers AMDA Bit Name Function 2 0 FIRST_DLY Chip Select 2 Device Delay for First Access 2 0 This bit field is used to configure the number of wait states for the first access to the ROM and for subsequent accesses if t
453. ount 0 Channel 0 terminal count not detected 1 Channel 0 terminal count detected Elan SC520 Microcontroller Register Set Manual Slave DMA Channel 0 3 Control SLDMACTL AMD GP DMA Controller Registers Direct Mapped Address 0008h Bit Reset R W 7 6 5 4 3 2 DAKSEN DRQSEN WRTSEL PRITYPE COMPTIM DMA_DIS Reserved 0 0 0 0 0 0 RSV Register Description This register provides the control function for Channels 0 3 Bit Definitions Bit Name DAKSEN DRQSEN WRTSEL PRITYPE COMPTIM DMA_DIS Function Internal dackx Sense In a discrete DMA controller this bit controls the polarity of all dackx outputs from the slave DMA controller 0 Asserted Low 1 Asserted High System logic external to the DMA controller expects the DMA controller to drive active Low dackx outputs This bit must be written to 0 for proper system operation Internal drqx Sense In a discrete DMA controller this bit controls the polarity of all drqx inputs to the slave DMA controller 0 Asserted High 1 Asserted Low System logic external to the DMA controller expects the DMA controller to respond to active High drqx inputs This bit must be written to 0 for proper system operation Write Selection Control 0 Late write selection 1 Extended early write selection Write command signals GPIOWR and GPMEMWR are asserted one clock early Ena
454. page 7 11 ECC Check Code Test ECCCKTEST page 7 12 ECC Single Bit Error Address ECCSBADD page 7 14 ECC Multi Bit Error Address ECCMBADD page 7 15 Elan SC520 Microcontroller Register Set Manual 7 1 AMD SDRAM Control DRCCTL Bit Reset R W SDRAM Controller Registers Memory Mapped MMCR Offset 10h 7 6 5 4 3 2 1 0 Vee Reserved RFSH SPD i 0 RFSH_ENB OPMODE SEL 2 0 0 0 0 1 0 0 0 0 RW RES R W RW Register Description This register controls various features of the SDRAM controller Note A programmable reset preserves this register s state See the PRG_RST_ENB bit description on page 3 3 Bit Definitions Bit 7 Name WB_TST_ ENB Reserved RFSH_SPD 1 0 RFSH_ENB Function Write Buffer Test Mode Enable This bit selects the source of the debugging information available on the three system test pins 0 Write buffer test mode is disabled System test mode The three system test pins function as CF DRAM DATASTRB and CF ROM GPCS pins 1 Write buffer test mode is enabled The three system test pins function as WBMSTR2 WBMSTRO for write buffer master trace purposes If the write buffer is enabled WB is set in the DBCTL register see page 8 3 the WBMSTR2 WBMSTRO signals provide write buffer master trace information during write cycles from the write buffer to SDRAM Master trace information specifies which ma
455. ped Address 0081h 7 6 5 4 3 2 1 0 Bit DMA2MAR 23 16 Reset 0 0 0 0 0 0 0 0 R W R W Register Description This register provides bits 23 16 of the memory address for Channel 2 Bit Definitions Bit 7 0 DMA2MAR 23 16 Programming Notes Function DMA Channel 2 Memory Address Bits 23 16 This bit field is used with the values in the GPDMA2MAR register see page 11 46 and the GPDMAEXTPG2 register see page 11 12 to generate DMA address bits 27 0 lan SC520 Microcontroller Register Set Manual 11 63 GP DMA Controller Registers Slave DMA Channel 3 Page GPDMA3PG Direct Mapped Address 0082h 7 6 5 4 3 2 1 0 Bit DMA3MAR 23 16 Reset 0 0 0 0 0 0 0 0 R W R W Register Description This register provides bits 23 16 of the memory address for Channel 3 Bit Definitions Bit Name Function 7 0 DMA3MAR DMA Channel 3 Memory Address Bits 23 16 23 16 For 8 bit transfers the value in this bit field is used with the values in the GPDMASMAR register see page 11 48 and the GPDMAEXTPGS register see page 11 13 to generate DMA address bits 27 0 For 16 bit transfers enhanced mode only bits 7 1 of this bit field hold address bits 23 17 and address bit 16 is located in the GPDMAS3MAR register see page 11 48 Bit 0 of this bit field is not used in 16 bit DMA operation The bit 0 value read back is
456. pped if the IC4 bit in MPICICW H is 0 12 32 Elan SC520 Microcontroller Register Set Manual Master PIC Initialization Control Word 3 MPICICW3 Register Description AMD Programmable Interrupt Controller Registers Direct Mapped Address 0021h 7 6 5 4 3 2 1 0 Bit S7 S6 S5 S4 S3 52 51 50 Reset 0 0 x 0 0 x 0 0 R W This register is the 3rd initialization register of the Master controller Bit Definitions Bit Name S7 S6 S5 S4 Function Channel 7 Slave Cascade Select 0 device attached to IR7 input 1 IR7 input used for slave cascading not valid in the ElanSC520 microcontroller In the lanSC520 microcontroller this bit is internally fixed to O Channel 6 Slave Cascade Select 0 device attached to IR6 input 1 IR6 input used for slave cascading not valid in the lanSC520 microcontroller In the lanSC520 microcontroller this bit is internally fixed to O Channel 5 Slave Cascade Select 0 device attached to IR5 input 1 IR5 input used for slave cascading This bit allows the Slave 2 controller to be logically cascaded or removed from the Master PIC Since the output of the Slave 2 controller is hard wired to interrupt channel 5 of the Master PIC this bit can be used to make the Slave 2 controller transparent to the user If this bit is set Slave 2 controller is cascaded to the Master PIC If this bit is cleared Slave 2 is
457. propagated to the GP bus Programming Notes 11 68 Elan SC520 Microcontroller Register Set Manual GP DMA Controller Registers AMDA Slave DMA Channel 0 Page GPDMAOPG Direct Mapped Address 0087h 7 6 5 4 3 2 1 0 Bit DMAOMAR 23 16 Reset 0 0 0 0 0 0 0 0 R W R W Register Description This register provides bits 23 16 of the memory address for Channel 0 Bit Definitions Bit 7 0 23 16 Programming Notes Function DMA Channel 0 Memory Address Bits 23 16 This bit field is used with the values in the GPDMAOMAR register see page 11 42 and the GPDMAEXTPGO register see page 11 10 to generate DMA address bits 27 0 lan SC520 Microcontroller Register Set Manual 11 69 AMD General 4 GPDMAGR4 GP DMA Controller Registers Direct Mapped Address 0088h 7 6 5 4 3 1 0 Bit 88 7 0 Reset 0 0 0 0 0 0 0 R W R W Register Description This is a general purpose register Bit Definitions Bit Name Function 7 0 PORT88 7 0 General Purpose R W Register Writes to this bit field are stored internally and propagated to the GP bus Reads from this bit field return the internal register value but are not propagated to the GP bus Programming Notes 11 70 Elan SC520 Microcontroller Register Set Manual GP DMA Controller Registers AMDA Master DMA Channel 6 Page GPDMAGPG Di
458. pt Mapping page 12 17 ECC Interrupt Mapping page 12 19 Other interrupt mapping registers 30 page 12 21 Elan SC520 Microcontroller Register Set Manual 12 23 AMD Programmable Interrupt Coniroller Registers Master PIC Interrupt Request MPICIR Direct Mapped I O Address 0020h 7 6 5 4 3 2 1 0 Bit IR7 IR6 IR5 IRA IR3 IR2 IR1 IRO Reset X X X X X R W R Register Description This register provides a real time status of the interrupt request inputs to the Master PIC This register latches all incoming interrupt requests and provides individual status of the requests to be acknowledged Bit Definitions Bit Name Function 7 IR7 Interrupt Request 7 0 The IR7 input to the Master PIC is not asserted 1 The IR input is asserted 6 IR6 Interrupt Request 6 0 The IR6 input to the Master PIC is not asserted 1 The IR6 input is asserted 5 IR5 Interrupt Request 5 0 The IR5 input to the Master PIC is not asserted 1 The IR5 input is asserted 4 IR4 Interrupt Request 4 0 The IR4 input to the Master PIC is not asserted 1 The IR4 input is asserted 3 IR3 Interrupt Request 3 0 The input to the Master PIC is not asserted 1 The IR3 input is asserted 2 IR2 Interrupt Request 2 0 The IR2 input to the Master PIC is not asserted 1 The IR2 input is asserted 1 IR1 Interrupt Request 1 0 The IR1 input to the Master PIC is not asserted 1 T
459. ption This register provides masking of individual interrupt requests for the Master controller This register is also known as Operation Control Word 1 in other PC AT compatible designs Bit Definitions Bit Name IM7 IM6 IM5 IM4 IM3 IM2 IM1 IMO Programming Notes Function IR7 Mask 0 Unmask IR7 1 Mask IR7 IR6 Mask 0 Unmask IR6 1 Mask IR6 IR5 Mask 0 Unmask IR5 1 Mask IR5 If the S5 bit in the MPICICWS register is set see page 12 33 setting the IM5 bit inhibits interrupt requests assigned to Slave 2 controller inputs from reaching the CPU Clearing this bit allows interrupts from Slave 2 controller to be propagated to the CPU IR4 Mask 0 Unmask IR4 1 Mask IR4 IR3 Mask 0 Unmask IR3 1 Mask IR3 IR2 Mask 0 Unmask IR2 1 Mask IR2 If the S2 bit in the MPICICWS register is set see page 12 34 setting the IM2 bit inhibits interrupt requests assigned to Slave 1 controller inputs from reaching the CPU Clearing this bit allows interrupts from Slave 1 controller to be propagated to the CPU IR1 Mask 0 Unmask IR1 1 2 Mask IR1 IRO Mask 0 Unmask IRO 1 Mask IRO This register MPICINTMSK cannotbe accessed during a Master PIC initialization control sequence which is initiated by setting the SLCT_ICW1 bitin the MPICICW1 register see page 12 26 When the MPICICWX register initialization sequence is not in effect any read or write of Port 0021h accesses the MPICINTMSK reg
460. put Data bit field 3 2 Reset Status register 3 5 RESSTA register 3 5 REV D bit field 6 22 REVID register 4 2 Revision I D bit field 6 22 RF CLR bit field in UARTXFCR register 18 15 in UARTxFCRSHAD register 18 5 RFD bit field 13 13 RFRT bit field in UARTXFCR register 18 15 in UARTXFCRSHAD register 18 5 RFSH_ENB bit field 7 2 RFSH_SPD bit field 7 2 RI bit field 18 23 RIN2 Function Select bit field 20 5 Ring Indicator bit field 18 23 RINx signal 18 19 18 23 20 5 ROM controller MMCR registers table 9 1 ROMCS1CTL register 9 4 ROMCS2CTL register 9 6 ROMCSx signal Function Select bit field 20 7 20 8 in PARx registers 2 6 in ROMCS1CTL register 9 4 in ROMCS2CTL register 9 6 RR RIS bit field in MPICOCWS register 12 30 in S1TPICOCWS register 12 55 in S2PICOCWS register 12 43 RST signal in HBCTL register 6 3 reset sources 3 6 RST LD bit field 3 2 RSTLDx signal 3 2 Elan SC520 Microcontroller Register Set Manual RTC Alarm AM PM Indicator bit field 17 9 Hour register 17 9 Minute register 17 7 Second register 17 5 RTC AM PM Indicator bit field 17 8 RTC Control A register 17 14 RTC Control B register 17 16 RTC Current Day of the Month register 17 11 RTC Current Day of the Week register 17 10 RTC Current Hour register 17 8 RTC Current Minute register 17 6 RTC Current Month register 17 12 RTC Current Second register 17 4 RTC Current Year register 17 13 RTC Disable bit field
461. r Note that the clear count key is written to the WDTMRCTL register address see page 16 2 Bit Definitions Bit Name Function 15 0 COUNTL 15 0 Current Count Low This field contains the low word 15 0 of the watchdog timer current count The counter value is automatically reset when the watchdog timer is enabled Programming Notes Although both the WDTMRCNTH and WDTMRONTL registers can be read with a single 32 bit CPU instruction the 32 bit access is split into two 16 bit accesses See the GP Timer chapter in the Elan VS C520 Microcontroller User s Manual order 22004 for suggestions if it is necessary to read an accurate 32 bit value from the watchdog timer counter 16 4 Elan SC520 Microcontroller Register Set Manual Watchdog Timer Registers Watchdog Timer Count High WDTMRCNTH AMD Memory Mapped MMCR Offset CB4h 15 14 13 12 11 10 Bit Reserved COUNTH 14 8 Reset 0 0 0 0 0 0 R W RSV R 7 6 5 4 3 2 Bit COUNTH 7 0 Reset 0 0 0 0 0 0 R W R Register Description This read only register contains the higher 15 bits of the watchdog timer counter In normal operation the clear count key sequence AAAAh followed by 5555h clears the watchdog timer counter Note that the clear count key is written to the WDTMRCTL register address see page 16 2 Bit Definitions Bit Name 15 Reserved 14 0 COUNTH 14 0 Programming Notes Function Res
462. r SSICMD registers are written or if the SSIRCV register is read while the BSY bit is set Hardware updates the BSY and TC INT bits to indicate non busy status transaction complete one half SSI_CLK period after the last edge of a receive transaction or one full SSI_CLK period after the last edge of a transmit transaction The TC INT bit should be used for interrupt operation i e if the TC INT ENB bitis enabled in the SSICTL register see page 19 2 Software must acknowledge clear the TC INT bit by writing a 1 to it after each SSI transaction The BSY bit should be used for polled operation Although the INT bit can be used for polled operation using the BSY bit is more efficient because it does not need to be cleared by software after each transaction Note that if only the polled operation is used the INT ENB bit should not be enabled in the SSICTL register see page 19 2 19 6 Elan SC520 Microcontroller Register Set Manual Synchronous Serial Interface Registers SSI Receive SSIRCV AMD Memory Mapped MMCR Offset CD4h 7 6 5 4 3 2 1 0 Bit DAT IN 7 0 Reset 0 0 0 0 0 0 0 0 R W R Register Description This register is used to read data received from a peripheral device Bit Definitions Bit 7 0 DAT_IN 7 0 Programming Notes Function SSI Data IN Software uses this bit field to read the eight bits shifted in from the SSI DI pin by the last
463. r Set Manual 4 3 AMDA Am5 86 CPU Registers 4 4 Elan SC520 Microcontroller Register Set Manual CHAPTER re Ta AMD 9 5 1 5 2 Table 5 1 SYSTEM ARBITRATION REGISTERS OVERVIEW This chapter describes the system arbiter registers of the lanSC520 microcontroller The lanSC520 microcontroller s system arbiter controls access to the PCI bus and the internal CPU bus The system arbiter register set consists of four memory mapped configuration region MMCR registers that provide control and status functions See the Elan SC520 Microcontroller Users Manual order 22004 for details about the system arbiter Table 5 1 lists the system arbiter registers in offset order with the corresponding description s page number REGISTERS System Arbiter MMCR Registers Register Name Mnemonic MMCR Offset Page Number System Arbiter Control SYSARBCTL PCI Bus Arbiter Status PCIARBSTA System Arbiter Master Enable SYSARBMENB Arbiter Priority Control ARBPRICTL Elan SC520 Microcontroller Register Set Manual 5 1 System Arbitration Registers System Arbiter Control SYSARBCTL Memory Mapped MMCR Offset 70h 7 6 5 4 3 2 1 0 CNCR BUS _ GNT_TO_ Bit Reserved PARK SEL MODE INT ENB ENB Reset 0 0 0 0 0 0 0 0 R W RSV R W R W R W Register Description This register contains control bits for the CPU bus arbiter and the PCI bus arbiter Bit Definitions
464. r To Send bit field 18 24 Delta Data Carrier Detect bit field 18 23 Delta Data Set Ready bit field 18 24 DEV_ID bit field 6 18 Device ID bit field 6 18 Device Number bit field 6 16 Device Select DEVSEL Timing bit field 6 20 Device Vendor ID register 6 18 DEVICE_NUM bit field 6 16 DEVSEL signal 6 20 DGP bit field in BOOTCSCTL register 9 2 in ROMCS1CTL register 9 4 in ROMCS2CTL register 9 6 Directly Trigger Priority Level Px bit field in SWINT16 1 register 12 10 12 11 12 12 in SWINT22 17 register 12 13 12 14 direct mapped I O registers table 1 7 Index Disable DMA Controller bit field in MSTDMACTL register 11 87 in SLDMACTL register 11 51 DIV bit field in UARTxBCDH register 18 10 in UARTxBCDL register 18 9 Divisor Latch Access bit field 18 17 DLAB bit field 18 17 DMA See also GP DMA Master DMA Slave DMA DMA Buffer Chaining Interrupt Mapping register 12 21 DMA Channel Mask bit field in MSTDMAMSK register 11 90 in SLDMAMSK register 11 54 DMA Channel Mask Select bit field in MSTDMAMSK register 11 90 in SLDMAMSK register 11 54 DMA Channel Select bit field in MSTDMAMODE register 11 92 in MSTDMASWREOQ register 11 89 in SLDMAMODE register 11 56 in SLDMASWREQ register 11 53 DMA Channel x Extended Page Address bit field in GPDMAEXTPGO register 11 10 in GPDMAEXTPG1 register 11 11 in GPDMAEXTPG2 register 11 12 in GPDMAEXTPG3 register 11 13 in GPDMAEXTPG5 register 11 14 in GPDMAEXTPG6 register
465. r does not affect other registers The PIC s initialization control word 81PICICWX registers 1 4 must be programmed in sequence Writing to Port 00AO0h with bit 4 1 causes the S1PICICW1 register to be written and also resets the PIC s internal state machine and the internal S1PICICWx register pointer Then S1PICICWx registers 2 4 can be programmed by sequential writes to Port OOA1h Each time Port 00 1 is written to following the write to S1PICICW1 the internal register pointer points to the next S1PICICWX register S1PICICW1 and S1PICICW2 must always be programmed Also the S1PICICWS register must always be programmed in this design because the SNGL bit in S1PICICW1 is internally fixed to 0 The S1PICICWA register is skipped if the IC4 bit in S1PICICW1 is 0 lan SC520 Microcontroller Register Set Manual 12 57 AMD Programmable Interrupt Coniroller Registers Slave 1 PIC Initialization Control Word 3 S1PICICW3 Direct Mapped I O Address 00A1h 7 6 5 4 3 2 1 0 Bit Reserved ID2 IDO Reset X X X X X 0 1 0 R W RSV Register Description This register is the third initialization register of the Slave 1 controller Bit Definitions Bit Name Function 7 3 Reserved Reserved This bit field should be written to 0 for normal system operation This bit field is write only 2 0 ID2 IDO Slave 1 PIC ID 2 0 These bits contain the binary Slave 1PIC ID 000b 111b that the PIC responds to
466. r normal system operation 0 XTAL FREQ Crystal Frequency This field is used to specify the frequency of the crystal used to drive the main system clock Configure this bit appropriately to ensure that the software timer increments at the correct rate for the system 0 Specifies that the system is using a 33 333 MHz crystal 1 Specifies that the system is using a 33 000 MHz crystal Note that this bit has no effect on the general purpose timers programmable interval timer or watchdog timer Programming Notes 15 4 Elan SC520 Microcontroller Register Set Manual CHAPTER ee AMD 16 WATCHDOG TIMER REGISTERS 16 1 OVERVIEW This chapter describes the watchdog timer registers of the ElanSC520 microcontroller The watchdog timer is one of four lanSC520 microcontroller timer modules The other timer modules are described in the following chapters Chapter 15 Software Timer Registers E Chapter 14 General Purpose Timer Registers Chapter 13 Programmable Interval Timer Registers The watchdog timer register set consists of three memory mapped configuration region MMCR registers used to configure control and monitor the status of the watchdog timer See the Elan SC520 Microcontroller User s Manual order 22004 for details about the watchdog timer Table 16 1 lists the watchdog timer registers in offset order with the corresponding description s page number 16 2 REGISTERS Table 16 1 Watchd
467. r to initiate a PCI bus configuration cycle after setting up the PCICFGADR register see page 6 15 Bit Definitions Bit Name Function 31 0 CFG_DATA Configuration Data 31 0 This bit field contains the data for the configuration access cycle read or write Programming Notes The ENABLE bit must be set in the PCICFGADR register for an access to this register PCICFGDATA to result in a PCI bus configuration cycle Otherwise the cycle accesses the PCI bus I O space This register can be accessed as a doubleword word or byte The appropriate CBEx signal combinations are driven on the PCI bus during the data phase of the configuration cycle In the ElanSC520 microcontroller the doubleword starting at OCFCh must not be mapped to the GP bus Elan SC520 Microcontroller Register Set Manual 6 17 AMD Device Vendor ID PCIDEVID Bit Reset R W Bit Reset R W Bit Reset R W Bit Reset R W Register Description PCI Bus Host Bridge Registers Address OCF8h OCFCh PCI Index OOh 81 30 29 28 27 26 25 24 DEV_ID 15 8 0 0 1 1 0 0 0 0 R 23 22 21 20 19 18 17 16 DEV_ID 7 0 0 0 0 0 0 0 0 0 R 15 14 13 12 11 10 9 8 VDR ID 15 8 0 0 0 1 0 0 0 0 R 7 6 5 4 3 2 1 0 VDR ID 7 0 0 0 1 0 0 0 1 0 R This register contains the PCI configuration header space vendor and device ide
468. ral 0 GPDMAGRO page 11 62 Slave DMA Channel 2 Page GPDMA2PG page 11 63 Slave DMA Channel 3 Page GPDMA3PG page 11 64 Slave DMA Channel 1 Page GPDMA1PG page 11 65 General 1 GPDMAGR1 page 11 66 General 2 GPDMAGR2 page 11 67 General 3 GPDMAGR3 page 11 68 Slave DMA Channel 0 Page GPDMAOPG page 11 69 General 4 GPDMAGR4 page 11 70 Master DMA Channel 6 Page GPDMA6PG page 11 71 Master DMA Channel 7 Page GPDMA7PG page 11 72 Master DMA Channel 5 Page GPDMAS5PG page 11 73 General 5 GPDMAGR5 page 11 74 General 6 GPDMAGR6 page 11 75 General 7 GPDMAGR7 page 11 76 General 8 GPDMAGR8 page 11 77 Master DMA Channel 4 Memory Address GPDMA4MAR page 11 78 Master DMA Channel 4 Transfer Count GPDMA4TC page 11 79 Master DMA Channel 5 Memory Address GPDMAS5MAR page 11 80 Master DMA Channel 5 Transfer Count GPDMASTC page 11 81 Master DMA Channel 6 Memory Address GPDMA6MAR page 11 82 Master DMA Channel 6 Transfer Count GPDMA6TC page 11 83 Master DMA Channel 7 Memory Address GPDMA7MAR page 11 84 Master DMA Channel 7 Transfer Count GPDMA7TC page 11 85 Master DMA Channel 4 7 Status MSTDMASTA page 11 86 Master DMA Channel 4 7 Control MSTDMACTL page 11 87 Master Software DRQ n Request MSTDMASWR
469. reads back 0 PIT Timer 2 Output Pin State This status bit directly reflects the state of the output signal on Channel 2 of the programmable interval timer PIT and is sampled before the gate controlled by the PIT OUT2 ENB bit 0 PIT Channel 2 output is Low 1 PIT Channel 2 output is High DRAM Refresh Indicator On the original PC AT the PIT Channel 1 output was used to generate the refresh signal In this design this bit is tied directly to the 32 KHz clock source Bit Name 7 PERR 6 IOCHCK 5 PIT_OUT2_STA 4 RFD 3 2 Reserved Reserved This bit field is ignored in the lanSC520 microcontroller On the original PC AT this bit field was used to enable I O channel check and RAM parity check For software using this register to remain PC AT compatible read modify write operations should be used to preserve this bit field s state PIT Output Channel 2 Enable This bit enables the PIT Channel 2 output to the PITOUT2 pin 0 Do not propagate the PIT Channel 2 output to the PITOUT2 pin The PITOUT2 pin is driven Low 1 Propagate the PIT Channel 2 output to the PITOUT2 pin The PITOUT2 pin is connected to the system speaker in PC AT compatible systems 1 PIT OUT2 ENB 0 PIT GATE2 Timer 2 Gate Input Control This bit drives the gate input signal for PIT Channel 2 The PIT Channel 2 gate input controls the channel s operation if the mode is set appropriately via the channel s CTR MODE bit field in the PITMODECTL regis
470. rect Mapped Address 0089h 7 6 5 4 3 2 1 0 Bit DMA6MAR 23 16 Reset 0 0 0 0 0 0 0 0 R W R W Register Description This register provides bits 23 16 of the memory address for Channel 6 Bit Definitions Bit Name Function 7 1 DMA6MAR DMA Channel 6 Memory Address Bits 23 16 23 16 For 8 bit transfers enhanced mode only the value in this bit field is used with the values in the GPDMA6MAR register see page 11 82 and the GPDMAEXTPG6 register see page 11 15 to generate DMA address bits 27 0 For 16 bit transfers bits 7 1 of this bit field hold address bits 23 17 and address bit 16 is located in the GPDMA6MAR register see page 11 82 Bit 0 of this bit field is not used in 16 bit DMA operation The bit 0 value read back is always the last value written but the bit is not applied to the system address unless 8 bit operation is selected Programming Notes In enhanced mode this channel can be programmed for 8 bit DMA transfers see the descriptions for GPDMACTL register bits CH6 ALT SIZE and ENH MODE ENB on page 11 4 In enhanced mode this register is updated during DMA cycles if the DMA addresses cross the 64 Kbyte boundary for 8 bit transfers or cross the 128 Kbyte boundary for 16 bit transfers lan SC520 Microcontroller Register Set Manual 11 71 AMD GP DMA Controller Registers Master DMA Channel 7 Page GPDMA7PG Direct Mapped I O Address 008Ah
471. register 12 46 ignne internal signal 12 61 IMx bit field in MPICINTMSK register 12 36 in S1PICINTMSK register 12 60 in S2PICINTMSK register 12 48 Initialization Control Word 1 Select bit field in MPICOCWS register 12 30 in S1PICICW1 register 12 51 in STPICOCW2 register 12 53 in S1TPICOCWS register 12 55 in S2PICICW1 register 12 39 in S2PICOCW2 register 12 41 in S2PICOCWS register 12 43 Index 10 Elan SC520 Microcontroller Register Set Manual Index Initialization Control Word 4 bit field in MPICICW1 register 12 27 in S1PICICW1 register 12 52 in S2PICICW1 register 12 40 instruction set xvi INT ENB bit field in GPTMROCTL register 14 4 in GPTMR1CTL register 14 10 in GPTMR2CTL register 14 16 INT FLG bit field 17 18 INT ID bit field 18 13 INT MAP bit field 12 22 INT NOT PND bit field 18 13 Internal dackx Sense bit field in MSTDMACTL register 11 87 in SLDMACTL register 11 51 Internal drgx Sense bit field in MSTDMACTL register 11 87 in SLDMACTL register 11 51 Internal Oscillator Control Bits bit field 17 14 Interrupt Control register 12 4 Interrupt Enable for Channel x bit field 11 24 Interrupt Identification Bit Field bit field 18 13 Interrupt Mapping bit field 12 22 Interrupt Pin Polarity register 12 15 Interrupt Request EOI and Priority Rotation Controls bit field in MPICOCW2 register 12 28 in S1PICOCW2 register 12 53 in S2PICOCW2 register 12 41 Interrupt Request Flag bit field in RTCSTAC
472. register 17 18 in WDTMRCTL register 16 2 Interrupt Request x bit field in MPICIR register 12 24 in S1PICIR register 12 49 in S2PICIR register 12 37 Interrupt Request x In Service bit field in MPICISR register 12 25 in S1PICISR register 12 50 in S2PICISR register 12 38 INTPINPOL register 12 15 INTx signal 12 15 INTx POL bit field 12 15 IO ENB bit field 6 21 lO HOLE DEST bit field 2 2 IOCHCK bit field 13 13 IRQ FLG bit field 16 2 IRx bit field in MPICIR register 12 24 in S1PICIR register 12 49 in S2PICIR register 12 37 Elan SC520 Microcontroller Register Set Manual AMD IRx Mask bit field in MPICINTMSK register 12 36 in STPICINTMSK register 12 60 in S2PICINTMSK register 12 48 IS OCW3 bit field in MPICOCW2 register 12 28 in MPICOCWS register 12 30 in STPICOCW2 register 12 53 in STPICOCWS register 12 55 in S2PICOCW2 register 12 41 in S2PICOCWS register 12 43 ISx bit field in MPICISR register 12 25 in S1PICISR register 12 50 in S2PICISR register 12 38 L Latch Count Low True bit field 13 1 1 Latch Status Low True bit field 13 11 LONT bit field 13 11 Level Triggered Interrupt Mode bit field in MPICICW1 register 12 26 in S1PICICW1 register 12 51 in S2PICICW1 register 12 39 literature support iii LOOP bit field 18 19 Loopback Mode Diagnostic Mode Enable bit field 18 19 Lower 16 Bits of DMA Channel x Memory Address bit field in GPDMAOMAR register 11 42 in GPDMA1MAR regis
473. register 4 3 instruction set xvi MMCR registers table 4 1 AMDebug Technology Hard Reset Detect bit field 3 5 RX TX Interrupt Mapping register 12 21 System Reset Detect bit field 3 5 Arbiter Priority Control register 5 6 ARBPRICTL register 5 6 ATTR bit field 2 7 Attribute bit field 2 7 Automatic Delayed Transaction Enable bit field 6 4 Automatic EOI Mode bit field in MPICICW4 register 12 35 in S1PICICW4 register 12 59 in S2PICICW4 register 12 47 Elan SC520 Microcontroller Register Set Manual Index 1 AMD Automatic Initialization Control bit field in MSTDMAMODE register 11 91 in SLDMAMODE register 11 55 B BAD CHK ENB bit field 7 12 Bank x Column Address Width bit field 7 5 7 6 Enable bit field 7 7 7 8 Ending Address bit field 7 7 7 8 ending address configuration figure 7 8 Internal SDRAM Bank Count bit field 7 5 7 6 Base Class Code bit field 6 22 baud rates divisors and clock source table 18 9 BAx signal 20 10 20 11 BBATSEN signal 17 20 BCD bit field in PITMODECTL register 13 8 in PITXSTA register 13 6 BI bit field 18 21 Binary Coded Decimal Select bit field 13 8 Binary Coded Decimal Select Status bit field 13 6 Bits 7 3 of Base Interrupt Vector Number for this PIC bit field in MPICICW2 register 12 32 in S1PICICW register 12 57 in S2PICICW2 register 12 45 BNKx BNK ONT bit field 7 5 7 6 BNKx COLWDTH bit field 7 5 7 6 BNKx ENB bit field 7 7 7 8 BNKx END bi
474. ress GPDMA1MAR 11 44 Slave DMA Channel 1 Transfer Count GPDMA1TC 11 45 Slave DMA Channel 2 Memory Address GPDMA2MAR 11 46 Slave DMA Channel 2 Transfer Count GPDMA2TC 11 47 Elan SC520 Microcontroller Register Set Manual vii AMD viii Table of Contents Slave DMA Channel 3 Memory Address GPDMA3MAR 11 48 Slave DMA Channel Transfer Count GPDMA3TC 11 49 Slave DMA Channel 0 3 Status _ 11 50 Slave DMA Channel 0 3 Control 11 51 Slave Software DRQ n Request SLDMASWREQ 11 53 Slave DMA Channel 0 3 Mask _ 11 54 Slave DMA Channel 0 3 Mode _ 11 55 Slave DMA Clear Byte Pointer _ 11 57 Slave DMA Controller Reset _ 11 58 Slave DMA Controller Temporary SLDMATMP 11 59 Slave DMA Mask Reset 52 5 5 11 60 Slave DMA General Mask 11 61 General 0 11 62 Slave DMA Channel 2 2 11 63 Slave DMA Channel Page 11 64 Slave DMA Channel 1 Page 1 11 65 General 1
475. rite cycle access to this register the ENB bit cannot be modified This bit is always read back as a 0 14 15 AMD Bit Name 13 INT ENB 12 6 Reserved 5 MAX CNT 4 1 Reserved 0 CONT CMP Programming Notes 14 16 General Purpose Timer Registers Function GP Timer 2 Interrupt Enable This bit allows the timer to generate an interrupt when the timer count value reaches the maximum count compare register value 0 Timer 2 interrupt request generation is disabled 1 GP Timer 2 interrupt request generation is enabled If the INT bit is 1 the T2 INT STA bit is set in the GPTMRSTA register see page 14 2 and an interrupt is generated when the GPTMR2ONT register value page 14 17 equals the value of the GPTMR2MAXCMPA register page 14 18 When the INT ENB bit is 0 the timer does not cause the T2 INT STA bit to be set in the GPTMRSTA register see page 14 2 and therefore a timer interrupt is not generated Before GP Timer 2 interrupts are enabled the GPTMR2MAP register see page 12 21 must be configured to route the interrupt to the appropriate interrupt request level and priority Reserved This bit field should be written to 0 for normal system operation GP Timer 2 Maximum Count This bit can be used by software to determine where the timer is in its current count sequence 0 Software must clear this bit by writing a O to it This bit is never automatically cleared by hardware 1 T
476. rn the internal register value but are not propagated to the GP bus Programming Notes 11 76 Elan SC520 Microcontroller Register Set Manual GP DMA Controller Registers AMDA General 8 GPDMAGRS Direct Mapped I O Address 008Fh 7 6 5 4 3 2 1 0 Bit PORTSF 7 0 Reset 0 0 0 0 0 0 0 0 R W R W Register Description This is a general purpose register Bit Definitions Bit Name Function 7 0 PORT8F 7 0 General Purpose R W Register Writes to this bit field are stored internally Reads from this bit field return the internal register value Programming Notes This general register is slightly different from the other direct mapped general registers No GP bus cycles are generated on writes to this I O address Port 008Fh Elan SC520 Microcontroller Register Set Manual 11 77 AMD GP DMA Controller Registers Master DMA Channel 4 Memory Address GPDMA4MAR Direct Mapped I O Address 00COh 7 6 5 4 3 2 1 0 Bit DMAAMAR 16 1 Reset X X X X X X X X R W R W Register Description Because Channel 4 is used to cascade the slave DMA controller to the master DMA controller this register has no real use Bit Definitions Bit Name Function 7 0 DMA4MAR DMA Channel 4 Memory Address 16 1 In a discrete DMA controller this bit field holds the lower 16 bits of memory address for DMA Channel 4 Because the drq and dack internal signals for this DM
477. rnal UART 1 is disabled the corresponding interrupt request is not automatically disconnected from the PIC If an external UART is to drive the UART 1 interrupt request then all interrupt enables in the UART1CTL and UART1INTENB registers must be cleared see page 18 3 and page 18 11 After the internal UART 1 is disabled a PARx window can be defined to target a GPCSx chip select in the UART 1 I O address space If a PARx window is not used the external UART must fully decode the addresses Programming Notes When the lanSC520 microcontroller comes out of reset the internal RTC and UARTs are enabled If the system application requires the use of an external RTC or UARTS the internal devices should be disabled during the boot process and initialization to prevent potential conflicts When the integrated UARTs are disabled only the I O space accesses associated with these peripherals are forwarded externally The accesses to the MMCR registers for the UARTs are not forwarded externally because these registers are specific to the integrated peripherals Therefore the UART MMCR registers should not be used while the integrated UARTs are disabled Even if the internal RTC or UARTS are disabled setting the IO HOLE DEST bit does not redirect accesses to the disabled peripherals to PCI bus I O space Elan SC520 Microcontroller Register Set Manual 2 3 AMD Write Protect Violation Status WPVSTA System Address Mapping Registers Memo
478. rocontroller Register Set Manual CHAPTER ee Te AMD 1 4 Am5 86 CPU REGISTERS 4 1 4 2 Table 4 1 OVERVIEW This chapter describes the Am5 86 CPU configuration registers of the lanSC520 microcontroller Am5 86 CPU includes a 16 Kbyte unified write back cache and an integrated floating point unit FPU The Am5 86 CPU operates at 100 or 133 MHz The Am5 86 CPU configuration register set consists of two memory mapped configuration region MMCR registers used to control some of the Am5 86 CPU features and read the lanSC520 microcontroller revision ID See the Elan SC520 Microcontroller User s Manual order 22004 for details about the Am5 86 CPU Table 4 1 lists the Am5 86 CPU configuration registers in offset order with the corresponding description s page number This chapter does not document Am5 86 processor registers REGISTERS Am5 86 CPU MMCR Registers Register Name Mnemonic MMCR Offset Page Number lanSC520 Microcontroller Revision ID REVID 00h page 4 2 Am5 86 CPU Control CPUCTL 02h page 4 3 Elan SC520 Microcontroller Register Set Manual 4 1 AMD lan SC520 Microcontroller Revision ID REVID 5 86 CPU Registers Memory Mapped MMCR Offset 00h 15 14 13 12 11 10 9 8 Bit PRODUCT_ID 7 0 Reset 0 0 0 0 0 0 0 0 R W 7 6 5 4 3 2 1 0 Bit MAJORSTEP 3 0 MINORSTEP 3 0 Reset X x X X R W R
479. ror Detected bit field 7 10 N NMI Routine Done bit field 12 4 NMI DONE bit field 12 4 NMI ENB bit field 12 4 NMI_TRIG bit field 12 13 No Serial Port Interrupt Pending bit field 18 13 Null Count bit field 13 5 NULL_CNT bit field 13 5 O OE bit field 18 22 Offset Time for GPALE bit field 10 15 for GPIORD and GPMEMRD bit field 10 11 for GPIOWR and GPMEMWR bit field 10 13 for the GP Bus Chip Select bit field 10 9 Operation Select bit field in MSTDMAMODE register 11 91 in SLDMAMODE register 11 55 OPMODE_SEL bit field 7 3 OPSEL bit field in MSTDMAMODE register 11 91 in SLDMAMODE register 11 55 OSC CTL bit field 17 14 OUT bit field 18 19 OUT bit field 18 19 OUTPUT bit field 13 5 Index 13 AMD Output State bit field 13 5 Overrun Error bit field 18 22 P P bit field in MPICOCWS register 12 30 in S1PICOCWS register 12 55 in S2PICOCWS register 12 43 P ENB bit field in GPTMROCTL register 14 3 in GPTMR1CTL register 14 9 in GPTMR2CTL register 14 15 Page Size bit field 2 7 PAR signal 2 8 Parity Enable bit field 18 17 Parity Error bit field 18 22 Parity Error Detected bit field 6 19 Parity Error Response bit field 6 21 PARx register 2 5 PC AT Channel Check Indicator bit field 13 13 PC AT Parity Error Indicator bit field 13 13 PCI Bus Arbiter Bus Park bit field 5 2 CPU Priority bit field 5 6 Grant Time Out Identification bit field 5 3 Interrupt Enable bit field
480. rrupt bit field 18 11 Enable Single bit Interrupt bit field 7 9 Enable Transmitter Holding Register Empty Interrupt bit field 18 11 Enable UART x Interrupts bit field 18 19 ENB bit field in GPTMROCTL register 14 3 in GPTMR1CTL register 14 9 in GPTMR2CTL register 14 15 in WDTMRCTL register 16 2 End of Current Buffer in Channel x bit field 11 22 11 23 ENH MODE ENB bit field 11 4 Enhanced Mode Enable bit field 11 4 Enter AMDebug Technology Mode on Next Reset bit field 3 3 EOI bit in SL EOI bit field 12 28 12 41 12 53 EPS bit field 18 17 ERDAI bit field 18 11 ERLSI bit field 18 11 ERR IN FIFO bit field 18 21 ESMM SMM bit field in MPICOCWS register 12 30 in STPICOCWS register 12 55 in S2PICOCWS register 12 43 ETHREI bit field 18 11 Even Parity Select bit field 18 17 EXP SEL bit field 16 3 Exponent Select bit field 16 3 EXT bit field in GPTMROCTL register 14 5 in GPTMR1CTL register 14 11 F Fast Back to Back Capable bit field 6 20 FBTB bit field 6 20 FE bit field 18 22 ferr internal signal 12 61 FERRMAP register 12 21 FIFO Enable bit field in UARTXFCR register 18 16 in UARTxFCRSHAD register 18 6 FIFO Mode Indication bit field 18 12 FIFO_ENB bit field in UARTXFCR register 18 16 in UARTxFCRSHAD register 18 6 Elan SC520 Microcontroller Register Set Manual Index FIFO_MODE bit field 18 12 FIRST_DLY bit field in BOOTCSCTL register 9 3 in ROMCS1CTL register
481. rrupt request is not automatically disconnected from the PIC If an external RTC is to drive the RTC interrupt request then all interrupt enables in the RTCCTLB register must be cleared prior to disabling the internal RTC see page 17 16 After the internal RTC is disabled a PARx window can be defined to target a GPCSx chip select in the RTC I O address space If a PARx window is not used the external RTC must fully decode the addresses 1 UART2 DIS UART 2 Disable This bit causes the integrated UART 2 to be disabled 0 The integrated UART 2 is enabled 1 The integrated UART 2 is not used and accesses to the UART 2 I O address space are forwarded externally to the GP bus When the internal UART 2 is disabled the corresponding interrupt request is not automatically disconnected from the PIC If an external UART is to drive the UART 2 interrupt request then all interrupt enables in the UART2CTL and UART2INTENB registers must be cleared see page 18 3 and page 18 11 After the internal UART 2 is disabled a PARx window can be defined to target a GPCSx chip select in the UART 2 I O address space If a PARx window is not used the external UART must fully decode the addresses 0 UART1 DIS UART 1 Disable This bit causes the integrated UART 1 to be disabled 0 The integrated UART 1 is enabled 1 The integrated UART 1 is not used and accesses to the UART 1 I O address space are forwarded externally to the GP bus When the inte
482. rs are valid Chaining Buffer Valid for Channel 5 0 The channel s Next Address registers and Next Transfer Count registers are not valid Only hardware can clear this bit Writing a 0 has no effect 1 CH5 _ VAL 1 Software sets this bit to indicate that the values of the channel s Next Address registers and Next Transfer Count registers are valid 0 CH3 _ Chaining Buffer Valid for Channel 3 VAL 0 The channel s Next Address registers and Next Transfer Count registers are not valid Only hardware can clear this bit Writing a 0 has no effect 1 Software sets this bit to indicate that the values of the channel s Next Address registers and Next Transfer Count registers are valid Programming Notes Achannel s CHx CBUF VAL bitis ignored if buffer chaining is not enabled for the channel Buffer chaining is enabled separately for each channel in the GPDMABCCTL register see page 11 21 If buffer chaining is enabled for a channel and if the channel s CHx VAL bit is set when the end of the buffer is reached i e when the channel s Transfer Count register reaches 0 then the channel s Memory Address and Transfer Count registers are loaded with the values in the channel s Next Address and Next Count registers respectively Then the channel s CHx CBUF VAL bit is cleared by the GP bus DMA controller An interrupt is also generated if the CHx INT bit is set in the GPDMABSINTENB register see page 11 24
483. ry Mapped MMCR Offset 82h 15 14 13 12 11 10 9 8 Bit WPV STA Reserved WPV MSTR 1 0 Reset 0 0 0 0 0 0 0 0 R W R W RSV R 7 6 5 4 3 2 1 0 Bit Reserved WPV WINDOW 3 0 Reset 0 0 0 0 0 0 0 0 R W RSV R Register Description This register provides write protect violation status for the ElanSC520 microcontroller s address decode block Bit Definitions Bit Name 15 WPV_STA 14 10 Reserved 9 8 WPV_MSTR 1 0 7 4 Reserved 3 0 WPV_WINDOW 9 0 Programming Notes Function Write Protect Violation Interrupt Status This bit indicates whether an interrupt request is pending due to a write protect violation 0 Write protect violations interrupt request not pending 1 Write protect violations interrupt request pending Software must write a 1 to this bit to clear the interrupt and the status bit before the hardware can latch subsequent write protect violations This bit provides the status of the interrupt regardless of the setting of the WPV INT bit in the ADDDECCTL register see page 2 2 Reserved This bit field should be written to O for normal system operation Write Protect Violation Master This bit field identifies the master that caused the write protect violation 00 The Am5 86 CPU caused the violation 01 A PCI bus master caused the violation 10 The GP bus DMA controller caused the violation 11 Reserved This bit
484. s lan SC520 Microcontroller Register Set Manual 17 13 AMD Real Time Clock Registers RTC Control A RTCCTLA I O Address 70h 71h RTC Index OAh 7 6 5 4 3 2 1 0 Bit UIP OSC_CTL 2 0 RATE_SEL 3 0 Reset X X X X X X X X R W R R W R W Register Description The RTC Control A register is used to determine if an RTC update is in progress and to control the RTC internal oscillator and periodic interrupt rate Bit Definitions Bit 7 6 4 17 14 Name UIP OSC_CTL 2 0 Function Update in Progress This bit is provided for use by software that needs to modify the time calendar or alarm registers in the real time clock 0 Software has a guaranteed minimum window of 244 us in which modifications to the time calendar and alarm registers are allowed While the UIP bit is 0 the time calendar and alarm information in RTC RAM is not in transition and are fully available to software 1 The time calendar and alarm registers are unavailable for access by software because internal RTC logic is using them Setting the SET bit in the RTCCTLB register see page 17 16 inhibits RTC register update cycles and clears the UIP status bit The UIP bit is a read only bit and is not affected by reset Internal Oscillator Control Bits 010 Enable the RTC divider chain to run at the internal time base frequency which results in one time base update per second This is the normal oper
485. s and Clock Source 18 9 Table 18 4 UART Interrupt Identification and 18 13 Table 18 5 UART Interrupt Programming 18 14 Table 19 1 SSI MMCR Registers 000 cect tenets 19 1 Table 19 2 SSI Clock Speed Selections 0 0 0 0 een eens 19 2 Table 20 1 Programmable I O MMCR 20 1 Table 20 2 PIO Register Programming 20 2 Elan SC520 Microcontroller Register Set Manual xiii AMD Table of Contents xiv Elan SC520 Microcontroller Register Set Manual PREFACE ee AMD 1 INTRODUCTION ELAN SC520 MICROCONTROLLER The Elan SC520 microcontroller is a full featured microcontroller developed for the general embedded market The ElanSC520 microcontroller combines a 32 bit low voltage Am5 86 CPU with a complete set of integrated peripherals suitable for both real time and PC AT compatible embedded applications PURPOSE OF THIS MANUAL This manual includes in reference format the complete set of registers required to configure the ElanSC520 microcontroller and control its peripherals This manual does not document the Am5 86 processor registers Intended Audience This reference manual is intended primarily for programmers who are developing code for the ElanSC520 microcontroller Computer
486. s 16 bits wide 1 Channel 5 is 8 bits wide This bit field is ignored if the ENH MODE ENB bit is 0 Alternate Size for Channel 3 0 Channel 3 is 8 bits wide 1 Channel 3 is 16 bits wide This bit field is ignored if the ENH MODE ENB bit is 0 Note that the Channel 3 default size differs from the Channel 5 7 default size Do not set the CH3 ALT SIZE bit if an internal UART is mapped to Channel 3 via the GPDMAEXTCHMAPB register see page 11 8 Clock Mode 00 Operate the GP bus DMA controller at 4 Mhz 01 Operate the GP bus DMA controller at 8 Mhz 10 Operate the GP bus DMA controller at 16 Mhz 11 Reserved The frequencies shown here are nominal The exact GP bus DMA frequency is derived by dividing the microcontroller s 33 MHz crystal input which can be 33 000 or 33 333 MHz Reserved This bit field should be written to 0 for normal system operation Enhanced Mode Enable 0 Disable enhanced GP DMA mode use normal GP DMA mode 1 Enable enhanced GP DMA mode Elan SC520 Microcontroller Register Set Manual AMD GP DMA Controller Registers GP DMA Memory Mapped 1 0 GPDMAMMIO Memory Mapped MMCR Offset D81h 7 6 5 4 3 2 1 0 7_ DMA6_ DMAS_ Reserveg DMAS_ DMA2_ DMA1_ DMAO_ i MMAP MMAP MMAP Eee MMAP MMAP MMAP MMAP Reset 0 0 0 0 0 0 0 0 R W R W R W R W RSV R W R W R W R W Register Description This register provides the selection of an I O devi
487. s A27 A16 of the next memory buffer to be used by Channel 7 in the buffer chaining mode Programming Notes The value of this register is ignored if buffer chaining mode is not enabled for this channel in the GPDMABCCTL register see page 11 21 lan SC520 Microcontroller Register Set Manual 11 33 AMDA GP DMA Controller Registers GP DMA Channel 3 Next Transfer Count Low GPDMANXTTCL3 Memory Mapped MMCR Offset DBOh 15 14 13 12 11 10 9 8 Bit NXT TC 15 8 Reset 0 0 0 0 0 0 0 0 R W R W 7 6 5 4 3 2 1 0 Bit DMA3_NXT_TC 7 0 Reset 0 0 0 0 0 0 0 0 R W R W Register Description This register provides bits 15 0 of the next transfer count for Channel 3 in buffer chaining mode Bit Definitions Bit Name Function 15 0 DMA3_NXT_ DMA Channel 3 Next Transfer Count Low TC 15 0 This bit field provides bits 15 0 of the next transfer count to be used by Channel 3 in the buffer chaining mode Programming Notes The value of this register is ignored if buffer chaining mode is not enabled for this channel in the GPDMABCCTL register see page 11 21 In PCI bus 2 2 compliant designs software must limit the length of GP bus DMA demand or block mode transfers Very large transfers could cause the PCI Host Bridge target controller to violate the 10 us memory write maximum completion time limit set in the PCI Local Bus Specification Revision 2 2
488. s AMD LIST OF FIGURES Figure 7 1 Examples of Bank Ending Address Configuration 7 8 Figure 7 2 ECC Check Bit and Data Bit Positions 7 11 Figure 10 1 GP Bus Signal Timing Adjustment 10 7 LIST OF TABLES Table 0 1 Documentation xviii Table 1 1 Configuration Region MMCR Registers By Offset 1 2 Table 1 2 Direct Mapped I O 5 lt 1 7 Table 1 3 PCI Indexed Registers 1 11 Table 1 4 Real Time Clock Indexed 5 5 1 11 Table 2 1 System Address Mapping MMCR 5 lt 2 1 Table 2 2 System Address Mapping Direct Mapped 2 1 Table 3 1 Reset Generation MMCR 5 3 1 Table 3 2 Reset Generation Direct Mapped 5 3 1 Table 3 3 Microcontroller Reset Sources 3 6 Table 4 1 5 86 CPU MMCR 5 4 1 Table 5 1 System Arbiter MMCR Registers 5 1 Table 6 1 PCI Bus Host Bridge MMCR
489. s complete 1 The SSI issues an interrupt request when the transaction is complete If the interrupt is disabled software should poll the BSY bit in the SSISTA register see page 19 6 Before the SSI interrupt is enabled the SSIMAP register see page 12 21 must be configured to route the interrupt to the appropriate interrupt request level and priority 19 2 Elan SC520 Microcontroller Register Set Manual Synchronous Serial Interface Registers AMDA Bit Name Function 2 PHS_INV_ENB SSI Inverted Phase Mode Enable This bit configures the SSI clock phase relationship with the incoming and outgoing data 0 Non inverted phase mode data is driven on odd edges of the SSI_CLK signal and latched on even edges When writing data the first bit of a transaction is shifted out on the SSI_DO pin on the first odd SSI clock edge and the remaining bits are shifted out on odd clock edges When reading data the SSI_DI pin state is latched on the eight even edges 2 4 6 8 10 12 14 16 of the SSI clock The transaction is complete one half of an SSI_CLK period after the last clock transition 1 Inverted phase mode data is driven on even edges of the SSI_CLK signal and latched on odd edges When writing data the first bit of a transaction is shifted out on the SSI DO pin one half of an SSI_CLK period before the first odd SSI clock edge and the remaining bits are shifted out on even clock edges When reading data the SSI DI pin state is latch
490. s configured via the PSC SEL bit When the timer clock is not being sourced from GP Timer 2 the timer advances every 4th CPU clock period 1 external GP Timer 0 clock source is used i e the TMRINO pin GP Timer 0 advances upon every positive edge driven on the TMRINO input pin In this mode the maximum timer input clock frequency is 1 4th of the CPU clock speed GP Timer 0 Alternate Compare This bit selects whether the GP Timer 0 count is compared to a single maximum count register value or alternately to both maximum count register values 0 Single compare mode the timer counts to the GPTMROMAXCMPA register value see page 14 7 and then resets the GPTMROONT register value to 0 page 14 6 In this mode the GPTMROMAXCMPB register is not used In single compare mode the TMROUTO pin is high while the counter is counting and being compared to the GPTMROMAXCMPA register The TMROUTO pin is pulsed Low for a single CPU clock cycle after the maximum value is reached 1 Alternate compare square wave mode if the timer is enabled the timer counts to the GPTMROMAXCMPA register value and then resets the GPTMROCNT register to 0 Then the timer counts to the GPTMROMAXCMPB register value page 14 8 and then resets the GPTMROCNT register value to 0 In alternate compare mode the TMROUTO pin is high while the counter is counting and being compared to the GPTMROMAXCMPA register The TMROUTO pin is Low while the counter is counting a
491. s for the RTC alarm event see page 17 18 Before any RTC interrupt is enabled the RTCMAP register see page 12 21 must be configured to route the interrupt to the appropriate interrupt request level and priority Elan SC520 Microcontroller Register Set Manual Bit Name 4 UPD_ INT_ENB 3 Reserved 2 DATE_MODE 1 HOUR MODE_SEL 0 DS ENB Programming Notes Real Time Clock Registers AMDA Function Update Ended Interrupt Enable 0 No RTC update ended interrupt is generated 1 RTC update ended interrupt is enabled When the UPD_INT_FLG bit in the RTCSTAC register transitions from 0 to 1 see page 17 19 the RTC update ended interrupt latches the INT_FLG bit in the RTCSTAC register to 1 see page 17 18 If the UPD_INT_FLG bit is 1 when the UPD_INT_ENB bit is set by software the INT_FLG bit is asserted immediately The UPD_INT_ENB bit is not modified by any internal RTC functions but is cleared by an RTC only reset or by writing the SET bit to 1 The UPD_INT_FLG bit in the RTCSTAC register provides latched status for the RTC update ended event see page 17 19 Before any RTC interrupt is enabled the RTCMAP register see page 12 21 must be configured to route the interrupt to the appropriate interrupt request level and priority Reserved This bit field should be written to 0 for normal system operation Date Mode The DATE_MODE bit selects whether time and calendar updates are to use binary or binary code
492. s for this register S2PICOCW3 and for the S2PICOCW2 and S2PICICW1 registers see page 12 41 and page 12 39 Bit Definitions Bit Name 7 Reserved 6 5 ESMM_SMM 1 0 4 SLCT_ICW1 3 IS OCWS 1 0 RIS 1 0 Function Reserved This bit field should be written to 0 for normal system operation This I O address changes functions when read See the programming notes for this register S2PICOCWS3 on page 12 44 Special Mask Mode 00 No operation 01 No operation 10 Reset special mask 11 Set special mask Initialization Control Word 1 Select Software must clear this bit to 0 when writing this address Port 0024h to access either this register S2PICOCWS or the S2PICOCW2 register 0 The write accesses either this register S2PICOCW3 or the S2PICOCW2 register see page 12 41 depending on the state of bit 3 1 The write accesses the S2PICICW1 register see page 12 39 Access is OCW3 Software must set this bit 15 OCW3 and clear SLCT_ICW1 when writing this address Port 0024h to access this register S2PICOCW3 0 The write accesses the S2PICOCW2 register see page 12 41 if the SLCT_ICW1 bit is cleared 1 The write accesses this register S2PICOCWS3 if the SLCT_ICW1 bit is cleared PIC Poll Command A system designer can choose to use the PIC in a non interrupting mode In this case the interrupt controller can be polled for the status of pending interrupts To support this mode of oper
493. sensitive interrupt 3 GPINT3_POL General Purpose Interrupt Request GPIRQ3 Polarity 0 Low to High transition or High level sensitive interrupt 1 High to Low transition or Low level sensitive interrupt 2 GPINT2 POL General Purpose Interrupt Request GPIRQ2 Polarity 0 Low to High transition or High level sensitive interrupt 1 High to Low transition or Low level sensitive interrupt 1 GPINT1 POL General Purpose Interrupt Request GPIRQ1 Polarity 0 Low to High transition or High level sensitive interrupt 1 High to Low transition or Low level sensitive interrupt 0 GPINTO POL General Purpose Interrupt Request GPIRQO Polarity 0 Low to High transition or High level sensitive interrupt 1 High to Low transition or Low level sensitive interrupt Programming Notes This register should be programmed only when the corresponding interrupt channel mask bits are enabled At system reset the INTx POL bits bits 15 12 of this register INTPINPOL are cleared to enable the active Low PCI interrupt to be used as a default so that no inversion is necessary for the PCI interrupt to be recognized correctly If the INTx pins are to be configured for use as general purpose interrupt sources as opposed to PCI interrupt sources then the correct polarity can be programmed as necessary using this register 12 16 Elan SC520 Microcontroller Register Set Manual PCI Host Bridge Interrupt Mapping PCIHOSTMAP Register Description AMD Programm
494. set 0 0 0 0 0 0 0 0 R W RSV R W RSV Register Description This register contains bit fields for configuring the host bridge controller Bit Definitions Bit Name 15 PCI_RST 14 11 Reserved 10 T PURGE HD Function PCI Bus Reset This bit controls the PCI bus RST signal pin Reading this bit returns the value that was written to it 0 Deassert the PCI bus reset signal 1 2 Assert the PCI bus reset signal Note that a PCI bus reset affects the host bridge specific registers in the PCI configuration space See the PCl indexed register descriptions beginning on page 6 18 The PCI RST bit must be cleared only in accordance with the PCI bus specification Reserved This bit field should be written to 0 for normal system operation Target FIFO Purge Enable This bit is provided for data coherency It forces the host bridge target controller to snoop the target read FIFOs when a PCI bus write transaction occurs 0 The target read FIFOs are not snooped during write transactions 1 The target read FIFOs are snooped during PCI bus write transactions The target controller purges any data in the read FIFOs when the write transaction falls within the same cache line for a read or read line command or within the same 64 doublewords for a read multiple command The T PURGE RD ENB bit must not be changed except during PCI bus initialization after a system reset See the Elan SC520 Microcontroller User s M
495. set X X X X X X X X RW RW Register Description This register contains bits 15 0 of the transfer count for Channel 3 during DMA operation Bit Definitions Bit Name Function 7 0 DMA3TC DMA Channel 3 Transfer Count 16 Bit Register 15 0 This 8 bit field is used two successive I O accesses to read or write the channel s transfer count bits 15 0 Bits 7 0 of the channel s transfer count can be read from or written to this bit field immediately after a write to the SLDMACBP register see page 11 57 Bits 15 8 of the channel s transfer count can be read from or written to this bit field immediately after transfer count bits 7 0 are read from or written to this bit field The actual number of transfers is one more than the programmed transfer count value Programming Notes To ensure that the lower byte of this register GPDMASTO is always accessed first software should precede any access to this register with a write to the SLDMACBP register see page 11 57 to clear the slave DMA byte pointer The value in this register GPDMA3TC can be used with the value in the GPDMAEXTTC3 register see page 11 17 to allow counts of up to 16 M 16 777 216 transfers In PCI bus 2 2 compliant designs software must limit the length of GP bus DMA demand or block mode transfers Very large transfers could cause the PCI Host Bridge target controller to violate the 10 us memory write maximum completion time limit set in the
496. software and hardware architects and system engineers who are designing or are considering designing systems based on this microcontroller may also be interested in the information contained in this document For more information on programming this microcontroller see the Flan SC520 Microcontroller User s Manual order 22004 Overview of this Manual The manual is organized into the following chapters Chapter 1 contains an overview of all the microcontrollers configuration registers Chapter 2 describes the system address mapping registers Chapter 3 describes the reset generation registers Chapter 4 describes the Am5 86 CPU registers Chapter 5 describes the system arbitration registers Chapter 6 describes the PCI host bridge registers Chapter 7 describes the synchronous DRAM SDRAM controller registers Chapter 8 describes the write buffer and read buffer register Chapter 9 describes the ROM Flash memory controller registers Chapter 10 describes the general purpose GP bus controller registers Chapter 11 describes the GP bus DMA controller registers Chapter 12 describes the programmable interrupt controller PIC registers Chapter 13 describes the programmable interval timer PIT registers Chapter 14 describes the general purpose GP timer registers Chapter 15 describes the software timer registers Chapter 16 describes the watchdog timer WDT registers Chapter 17 describes the real time clock RTC registers E
497. software to initialize the stack pointer before setting the NMI bit again after a soft reset 1 PRGRST DET PRGRESET Detect This bit is set when a reset from PRGRESET pin is detected Software clears this bit by writing a 1 0 No PRGRESET pin reset was detected 1 The system reset event was from the PRGRESET pin If the PRG bit is 1 in the RESCFG register see page 3 3 assertion of the PRGRESET pin while PWRGOOD is asserted results in a programmable reset in which the SDRAM configuration is maintained 0 PWRGOOD POWERGOOD Reset Detect DET This bit is set when a reset from the PWRGOOD pin is detected Software clears this bit by writing a 1 0 No PWRGOOD pin reset was detected 1 The system reset event was from the PWRGOOD pin This reset event has higher priority over PRGRESET and disables the PRGRESET function if it is enabled by clearing the PRG_RST_ENB bit in the RESCFG register see page 3 3 Programming Notes Unlike most other registers the bits in this register are only returned to their reset value by a PWRGOOD reset They are not cleared by any other kind of reset The AMDebug technology trace information is preserved only if a soft reset is generated to the CPU See the Elan SC520 Microcontroller User s Manual order 22004 for details about reset generation Table 3 3 provides a summary of ElanSC520 microcontroller reset sources and effects Table 3 3 Microcontroller Reset Sources CPU GPRE
498. ss Mapping Direct Mapped Register Register Name Mnemonic I O Address Page Number Configuration Base Address CBAR FFFCh page 2 9 Elan SC520 Microcontroller Register Set Manual 2 1 AMD Address Decode Control ADDDECCTL System Address Mapping Registers Memory Mapped MMCR Offset 80h 7 4 3 2 1 0 WPV_INT_ lO HOLE Bit ENB Reserved DEST Reserved RTC DIS UART2 DIS UART1 DIS Reset 0 0 0 0 0 0 R W R W RSV R W RSV R W R W R W Register Description This register controls miscellaneous functions in the ElanSC520 microcontroller address decode block Bit Definitions Bit Name Function 7 WPV_INT_ Write Protect Violation Interrupt Enable ENB This bit enables an interrupt request to be generated when a write protect violation occurs 0 Write protect violations do not generate an interrupt request to the CPU 1 Write protect violations generate an interrupt request to the CPU Before the WPV INT bit is set the WPVMAP register see page 12 21 must be configured to route the interrupt to the appropriate interrupt request level and priority The initiator of the access that caused the write protect violation can be the Am5 86 CPU any PCI bus master or the GP bus DMA controller This interrupt can only be generated if at least one of the PARx register windows is enabled and has the write protect attribute selected see page 2 6 6 5 Reserved Reserved This bit field should b
499. st is deasserted Masking an active channel while it is being granted might cause the system to hang lan SC520 Microcontroller Register Set Manual 11 61 GP DMA Controller Registers General 0 GPDMAGRO Direct Mapped I O Address 0080h 7 6 5 4 3 2 1 0 Bit PORT80 7 0 Reset 0 0 0 0 0 0 0 0 R W R W Register Description This is a general purpose register Bit Definitions Bit Name Function 7 0 PORT80 7 0 General Purpose R W Register Writes to this bit field are stored internally and propagated to the GP bus Reads from this bit field return the internal register value but are not propagated to the GP bus Programming Notes In a discrete DMA controller this register would be the DMA Channel 4 Page register but in PC AT compatible systems DMA Channel 4 is used for the cascade function so this register is not used by the DMA subsystem In a PC AT compatible system this I O address Port 0080h is typically used to send BIOS Power on Self Test POST codes to the ISA bus where special hardware can be used to decode the address and display the POST codes In the lanSC520 microcontroller writes to this register are propagated to the GP bus to allow PC AT compatible operation Reads from this register return the internally stored value only 11 62 Elan SC520 Microcontroller Register Set Manual GP DMA Controller Registers AMDA Slave DMA Channel 2 Page GPDMA2PG Direct Map
500. status of pending interrupts To support this PC AT incompatible mode of operation the PIC supports a special poll command that is invoked by setting this bit 0 Not poll command 1 Poll command Status Register Select 00 No change from last state 01 No change from last state 10 Next Port 0020h read returns the MPICIR register s contents see page 12 24 11 Next Port 0020h read returns the MPICISR register s contents see page 12 25 Elan SC520 Microcontroller Register Set Manual Programmable Interrupt Coniroller Registers AMD Programming Notes I O Port 0020h provides access to different Master PIC registers based on the data that is written Table 12 5 provides a summary of bit patterns to write for access to each register Table 12 5 Master PIC Port 0020h Access Summary Same as Table 12 3 Bits Port 0020h Register Written Next Port 0020h Read Returns 0 x MPICOCW2 page 12 28 x MPICOCWS3 page 12 30 0 1 MPICOCWS MPICIR page 12 24 MPICOCWS MPICISR page 12 25 X MPICICW1 page 12 26 1 x 0 1 1 2 x 0 0 5 0 0 0 lan SC520 Microcontroller Register Set Manual 12 31 AMD Programmable Interrupt Coniroller Registers Master PIC Initialization Control Word 2 MPICICW2 Direct Mapped I O Address 0021h 7 6 5 4 3 2 1 0 Bit T7 T3 A10 A8 Reset x x x x x x x R W W W
501. ster S2PICICW1 and S2PICICW2 must always be programmed Also the S2PICICWS register must always be programmed in this design because the SNGL bit in S2PICICW1 is internally fixed to 0 The S2PICICW4 register is skipped if the IC4 bit in S2PICICW 1 is 0 If the S5 bit in the MPICICWS register is cleared see page 12 33 then the Slave 2 controller is bypassed and programming this register does not affect other registers I O Port 0024h provides access to different Slave 2 PIC registers based on the data that is written Table 12 6 provides a summary of bit patterns to write for access to each register Table 12 6 Slave 2 PIC I O Port 0024h Access Summary Bits Port 0024h Register Written Next Port 0024h Read Returns 1 X S2PICOCW2 page 12 41 0 S2PICOCW3 page 12 43 1 1 S2PICOCWS3 S2PICIR page 12 37 S2PICOCWS3 S2PICISR page 12 38 X S2PICICW1 page 12 39 5 x x 0 0 0 12 40 Elan SC520 Microcontroller Register Set Manual Slave 2 PIC Operation Control Word 2 S2PICOCW2 Register Description AMD Programmable Interrupt Controller Registers Direct Mapped Address 0024h 7 6 5 4 3 2 1 0 SLCT_ Bit R SL EOI 2 0 IW IS OCW3 LS 2 0 Reset X X X X X X X X R W W W This register provides control for various interrupt priority and end of interrupt EOI modes It also controls write access for this register S2PI
502. ster pointer points to the next MPICICWx register MPICICW1 and MPICICW2 must always be programmed The MPICICW3 register is skipped if the SNGL bit in MPICICW1 is 1 The MPICICW4 register is skipped if the IC4 bit in MPICICW H is 0 12 34 Elan SC520 Microcontroller Register Set Manual Master PIC Initialization Control Word 4 MPICICW4 Register Description AMD Programmable Interrupt Controller Registers Direct Mapped Address 0021h 7 6 5 4 3 2 1 0 Bit Reserved SFNM BUF_M S 1 0 Reset X X X X 0 0 X 1 R W RSV This register is the fourth initialization register of the Master controller Bit Definitions Bit 7 5 3 2 Name Reserved SFNM BUF M S 1 0 Programming Notes Function Reserved This bit field should be written to 0 for normal system operation This bit field is write only Special Fully Nested Mode Enable 0 Normal nested mode 1 Special fully nested mode Buffered Mode and Master Slave Select 00 Non buffered mode 01 Non buffered mode 10 Buffered mode slave 11 Buffered mode Master In the lanSC520 microcontroller design these bits are internally fixed to 00b Automatic EOI Mode 0 Normal EOI the interrupt handler must send an End of Interrupt command to the PIC s 1 Auto EOI the EOI is automatically performed after the second interrupt acknowledge signal from the CPU M
503. sters contributed to the level rank that is currently being written to SDRAM from the write buffer Contributing masters can be one or more of Am5 86 CPU PCI or GP bus DMA If the write buffer is disabled or during read cycles if the write buffer is enabled the WBMSTR2 WBMSTRO signals reflect the master that is currently requesting SDRAM access Software writes to this bit are ignored when the AMDebug technology mode is active This ensures that microcontroller software cannot remove control of the pins from the software driving the AMDebug technology port If AMDebug technology mode is not active software can write to this bit Refer to the Elan SC520 Microcontroller User s Manual order 22004 for more information about system test mode and write buffer test mode Reserved This bit field should be written to 0 for normal system operation SDRAM Refresh Request Speed These two bits determine the SDRAM refresh request rate 00 7 8 us 01 15 6 Lis default 10 31 2 us 11 62 5 us Refresh Enable 0 SDRAM refresh is disabled This mode should be used for SDRAM detection and sizing algorithms Disabling SDRAM refresh should not be done in normal operation 1 3 SDRAM refresh is enabled Note Refresh cycles are not generated to SDRAM banks that are not enabled via the BNKx ENB bits in the DRCBENDADR register see page 7 7 Elan SC520 Microcontroller Register Set Manual SDRAM Controller Registers AMDA 2
504. sters AMDA Function GPDRQ1 Channel Mappin Map the GPDRQ1 and GPDACK1 pins to a GP DMA channel 0000 Channel 0 0001 Channel 1 0010 Channel 2 0011 Channel 3 0101 Channel 5 0110 Channel 6 0111 Channel 7 All other values are treated as unconnected GPDRQO Channel Mappin Map the GPDRQO and GPDACKO pins to a GP DMA channel 0000 Channel 0 0001 Channel 1 0010 Channel 2 0011 Channel 3 0101 Channel 5 0110 Channel 6 0111 Channel 7 All other values are treated as unconnected Elan SC520 Microcontroller Register Set Manual 11 7 AMD GP DMA Controller Registers GP DMA Resource Channel Map B GPDMAEXTCHMAPB Memory Mapped MMCR Offset D84h 15 14 13 12 11 10 9 8 Bit TXDRQ2 CHSEL 3 0 TXDRQ1 CHSEL 3 0 Reset 1 1 1 1 1 1 1 1 R W R W R W 7 6 5 4 3 2 1 0 Bit RXDRQ2_CHSEL 3 0 RXDRQ1_CHSEL 3 0 Reset 1 1 1 1 1 1 1 1 R W R W R W Register Description This register indicates the channel mapping for the internal serial port request signals txdrq2 txdrq1 and rxdrq2 rxdrg1 Bit Definitions Bit 15 12 TXDRQ2_ CHSEL 3 0 11 8 TXDRQ1_ CHSEL 3 0 7 4 RXDRQ2 CHSEL 3 0 Function TXDRQ2 Channel Mapping Map the txdrg2 and txdack2 internal signals to a GP DMA channel 0000 Channel 0 0001 Channel 1 0010 Channel 2 0011 Channel 3 All other values are treated as unconnected TXDRQ1 Channel Mapping M
505. t detection 1 Level sensitive interrupt request detection There is a global overriding bit S2_GINT_MODE in the PICICR register see page 12 5 When set the S2 GINT MODE bit causes this register SL2PICMODE to have no effect on the interrupt mode programmed for each channel If the S2 GINT MODE bit is set the overriding global interrupt mode for the Slave 2 PIC channels is determined by the LTIM bit in the S2PICICW1 register see page 12 51 If the S2 MODE bit is cleared the LTIM bit has no meaning and the SL2PICMODE register bits take effect for determining each Slave 2 PIC channel s interrupt mode Elan SC520 Microcontroller Register Set Manual 12 9 AMD Programmable Interrupt Coniroller Registers Software Interrupt 16 1 Control SWINT16 1 Memory Mapped MMCR Offset DO8h 15 14 13 12 11 10 9 8 Bit SW_P16 SW P15 SW P14 SW P13 SW P12 SW P11 SW P10 SW P9 TRIG TRIG TRIG TRIG TRIG TRIG TRIG TRIG Reset 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W 7 6 5 4 3 2 1 0 Bit SW_P8 SW_P7 SW_P6 SW_P5 SW_P4 SW_P3 SW_P2 SW_P1 TRIG TRIG TRIG TRIG TRIG TRIG TRIG TRIG Reset 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Register Description This register allows software to generate interrupt priority levels 1 16 to the CPU Bit Definitions Bit Name Function 15 SW P16 TRIG Directly Trigger Priority Level P16 Setting this bit directly asserts a maska
506. t detection Master PIC Channel 3 Interrupt Mode 0 Edge sensitive interrupt request detection 1 Level sensitive interrupt request detection Master PIC Channel 2 Interrupt Mode 0 Edge sensitive interrupt request detection 1 Level sensitive interrupt request detection If the SNGL bit in the MPICICW1 register is set see page 12 26 and the M_GINT_MODE bit of the PICICR register is cleared see page 12 5 setting the CH2_INT_MODE bit causes interrupts to be recognized as level sensitive on channel 2 Clearing the CH2_INT_MODE bit under the same condition causes channel 2 interrupts to be recognized as edge sensitive However if both the SNGL bit and the M_GINT_MODE bit are cleared the CH2_INT_MODE bit value has no meaning because the channel is used for cascading with the Slave 1 controller Master PIC Channel 1 Interrupt Mode 0 Edge sensitive interrupt request detection 1 Level sensitive interrupt request detection Elan SC520 Microcontroller Register Set Manual Programmable Interrupt Coniroller Registers AMD Bit Name Function 0 CHO_INT_ Master PIC Channel 0 Interrupt Mode MODE 0 Edge sensitive interrupt request detection 1 Level sensitive interrupt request detection Programming Notes There is a global overriding bit M_GINT_MODE in the PICICR register see page 12 5 When set the M_GINT_MODE bit causes this register MPICMODE to have no effect on the interrupt mode programmed for each channel If the M GINT MODE
507. t enables a20 propagation a20 propagates by default 0 CPU RST Alternate CPU Core Reset Control Programming Notes Writing a 1 to this bit pulses the internal CPU sreset signal This causes the same type of CPU soft reset to occur that was historically performed by an external system control processor SCP in a PC AT compatible system but much faster The Am5 86 CPU cache state and ElanSC520 microcontroller MMCR indexed and direct mapped registers are not affected by this soft reset with the exception that the NMI ENB bit in the PICICR register is cleared see page 12 4 Clearing the NMI ENB bit allows software to initialize the stack pointer before setting the NMI ENB bit again after a soft reset Following the reset this bit CPU remains set until software clears it This feature can be used by the BIOS as an indication that this bit generated the reset However writing a 1 to the CPU RST bit always generates a soft reset even if the bit was not cleared after a previous reset 0 Do not generate a soft reset to the CPU core 1 Pulse the internal CPU sreset signal Using a read modify write operation to change the A20G_CTL bit can cause an unintended soft reset This happens if the CPU RST bit has been previously set and not cleared by software Always write 0 to the CPU RST bit unless a soft reset is desired Elan SC520 Microcontroller Register Set Manual 3 9 AMD Reset Generation Registers 3 10 Elan SC520 Mic
508. t field 7 7 7 8 BOOTCS Control register 9 2 BOOTCS Device Delay for First Access bit field 9 3 Delay for Subsequent Access bit field 9 2 Mode bit field 9 2 SDRAM GP Bus Select bit field 9 2 Width Select bit field 9 2 BOOTCS signal 1 2 2 6 9 1 9 2 9 3 BOOTCSCTL register 9 2 Break Indicator bit field 18 21 BSY bit field 19 6 BUF bit field in MPICICWA register 12 35 in S1PICICWA register 12 59 in S2PICICWA register 12 47 BUF_M S bit field in MPICICWA register 12 35 in S1PICICWA register 12 59 in S2PICICWA register 12 47 Index 2 Index Buffer Chaining Control register 11 21 Enable for Channel x bit field 11 21 Interrupt Enable register 11 24 Status register 11 22 Valid register 11 25 Buffered Mode and Master Slave Select bit field in MPICICWA register 12 35 in S1PICICW4 register 12 59 in S2PICICWA register 12 47 Bus Number bit field 6 15 BUS MAS bit field 6 21 BUS NUM bit field 6 15 BUS PARK SEL bit field 5 2 C Cache Write Mode bit field 4 3 CACHE WR MODE bit field 4 3 CAS LAT bit field 7 4 CBAR register 2 9 CBEx signal 6 17 CF DRAM signal 7 2 CF ROM GPCS signal 7 2 CFG DATA bit field 6 17 CFGx signal 9 2 9 3 Chaining Buffer Valid for Channel x bit field 11 25 Channel x DMA Request bit field in MSTDMASTA register 11 86 in SLDMASTA register 11 50 Channel x Slave Cascade Select bit field 12 33 12 34 Channel x Terminal Count bit field in MSTDMASTA register 11 86 in S
509. t field in MSTDMACTL register 11 87 in SLDMACTL register 11 51 Write Protect Violation Interrupt Enable bit field 2 2 Interrupt Status bit field 2 4 Master bit field 2 4 Window Number bit field 2 4 Write Protect Violation Interrupt Mapping register 12 21 Write Protect Violation Status register 2 4 WRST_ENB bit field 16 2 WRTSEL bit field in MSTDMACTL register 11 87 in SLDMACTL register 11 51 www amd com iii X XTAL FREQ bit field 15 4 Y YEAR bit field 17 13 Elan SC520 Microcontroller Register Set Manual
510. t vectors are separated by eight locations 1 Interrupt vectors are separated by four locations In the lanSC520 microcontroller design this PC AT compatible bit is internally fixed to 1 lan SC520 Microcontroller Register Set Manual 12 51 AMD Programmable Interrupt Coniroller Registers Bit Name Function 1 SNGL Single PIC 0 Cascade mode S1PICICWS is expected 1 Single PIC in the system S1PICICWS is not expected not valid in the lanSC520 microcontroller In the lanSC520 microcontroller design this bit is internally fixed to 0 Because this bit is internally fixed to 0 software must always write the S1PICICWS3 register after writing S1PICICW2 See the programming notes on this page for details 0 IC4 Initialization Control Word 4 Software uses this bit to indicate whether it intends to explicitly program the S1PICICW4 register see page 12 59 after writing to the S1PICICWSG register see page 12 58 See the programming notes on this page for details 0 The S1PICICWA register is initialized internally when this register 81PICICW 1 is written The PIC does not expect software to write to the S1PICICWA register 1 2 The S1PICICWA register is not initialized by the write to this register S1PICICW1 Software is expected to initialize the S1PICICWA register after writing to the S1PICICW3 register Programming Notes The PIC s initialization control word 81PICICWX registers 1 4 must be programmed in seque
511. te accesses this register S1PICOCW3 if the SLCT_ICW1 bit is cleared PIC Poll Command A system designer can choose to use the PIC in a non interrupting mode In this case the interrupt controller can be polled for the status of pending interrupts To support this PC AT incompatible mode of operation the PIC supports a special poll command that is invoked by setting this bit 0 Not poll command 1 Poll command Status Register Select 00 No change from last state 01 No change from last state 10 Next Port 00AO0h read returns the S1PICIR register s contents see page 12 49 11 Next Port 00AO0h read returns the S1PICISR register s contents see page 12 50 Elan SC520 Microcontroller Register Set Manual 12 55 AMD Programmable Interrupt Coniroller Registers Programming Notes If the S2 bit in the MPICICWS3 register is cleared see page 12 34 then the Slave 1 controller is bypassed and programming this register does not affect other registers Port OOAOh provides access to different Slave 1 PIC registers based on the data that is written Table 12 11 provides a summary of bit patterns to write for access to each register Table 12 11 Slave 1 PIC I O Port 00A0h Access Summary Same as Table 12 9 Bits Port 00A0h Register Written Next Port 00A0h Read Returns 6 5 4 3 2 1 0 0 x SIPICOCW 2 page 12 53 0 0 1 0 x 1 page 12 55
512. ted do not generate an interrupt 1 Master write transactions or master read address phase cycles that detect the parity error signal asserted generate an interrupt Master Detected Parity Error Interrupt Enable This bit allows parity errors detected by the master controller during a read transaction to generate an interrupt 0 Master read transactions that detect a parity error do not generate an interrupt 1 Master read transactions that detect a parity error generate an interrupt This register is reset by a system reset The bits in this register are not affected by a PCI bus reset A PCI bus reset is initiated by setting the PCI bit in the HBCTL register see page 6 3 Interrupt status bits are set whenever the associated event occurs regardless of the corresponding interrupt enable bit Elan SC520 Microcontroller Register Set Manual PCI Bus Host Bridge Registers AMDA For a host bridge NMI to propagate to the CPU host bridge NMIs must be enabled via the PCI_NMI_ENB bit in the PCIHOSTMAP register see page 12 17 and NMIs must be enabled via the NMI_ENB bit in the PICICR register see page 12 4 Before host bridge interrupts are enabled the PCIHOSTMAP register see page 12 17 must be configured to route the interrupt to the appropriate interrupt request level and priority The interrupt enabled via the GNT_TO_INT_ENB bitin the SYSARBCTL register see page 5 2 shares the interrupt controller input used by host brid
513. ted with this address All accesses to this address go to the GP bus Additionally writes to this address are snooped by the ElanSC520 microcontroller 3 8 Elan SC520 Microcontroller Register Set Manual Reset Generation Registers System Control Port A SYSCTLA AMD Direct Mapped Address 0092h 1 0 Bit Reserved A20G CTL CPU RST Reset 0 0 R W RSV R W R W Register Description This register is used for fast alternative control of the CPU soft reset and the a20 signal Bit Definitions Bit Name Function 7 2 Reserved Reserved This bit field should be written to 0 for normal system operation 1 A20G CTL A20 Gate Control This bit can be used to cause the same type of masking of the CPU a20 signal that was historically performed by an external system control processor SCP in a PC AT compatible system but much faster 0 Internal a20 propagation is disabled address space wraps at 1 Mbyte 1 2 Internal a20 propagation is enabled addresses above 1 Mbyte can be accessed This bit A20G_CTL provides one of two sources of a20 gate control The other source is the A20 GATE bit in the SCPDATA register see page 3 7 A logical OR of these two sources is used to drive the Am5 86 CPU a20m signal Therefore a20 propagates if either source enables a20 to propagate Note that this bit A20G_CTL defaults to disabling a20 propagation However because the default state of the A20 bi
514. tem Control Port B SYSCTLB which provides certain PIT related functions See the Elan SC520 Microcontroller User s Manual order 22004 for details about the PIT channels Table 13 1 lists the PIT registers in offset order with the corresponding description s page number REGISTERS Programmable Interval Timer Direct Mapped Registers Page Register Name Mnemonic l O Address Number PIT Channel 0 Count PITOCNT page 13 2 PIT Channel 1 Count PIT1CNT page 13 3 PIT Channel 2 Count PIT2CNT page 13 4 PIT 0 Status PITOSTA page 13 5 PIT 1 Status PIT1STA page 13 5 PIT 2 Status PIT2STA page 13 5 PIT Mode Control PITMODECTL page 13 7 PIT Counter Latch Command PITCNTLAT page 13 10 PIT Read Back Command PITRDBACK page 13 11 System Control Port B SYSCTLB page 13 13 Elan SC520 Microcontroller Register Set Manual 13 1 AMDA Programmable Interval Timer Registers PIT Channel O Count PITOCNT Direct Mapped Address 0040h 7 6 5 4 3 2 1 0 Bit CHO_CNT 15 0 Reset 0 0 0 0 0 0 0 0 R W R W Register Description This register stores the current count values for PIT Channel 0 Bit Definitions Bit Name Function 7 0 CHO_CNT 15 0 16 bit Counter for Programmable Interval Timer Channel 0 This bit field provides read or write access to either the counter high byte only low byte only or low byte followed by high byte as defined by the CTR_RW_LATCH bit field
515. ter 11 44 in GPDMA2MAR register 11 46 in GPDMA3MAR register 11 48 in GPDMA5MAR register 11 80 in GPDMA6MAR register 11 82 in GPDMA7MAR register 11 84 LS bit field in MPICOCW2 register 12 28 in S1PICOCWe register 12 54 in S2PICOCW2 register 12 41 LSTAT bit field 13 11 LTIM bit field in MPICICW1 register 12 26 in STPICICW 1 register 12 51 in S2PICICW1 register 12 39 M M S bit field in MPICICW4 register 12 35 in S1PICICW4 register 12 59 in S2PICICW4 register 12 47 Index 11 AMD M AD IRQ 1 bit field 6 14 M CMD 10 bit field 6 12 M DPER IRQ bit field 6 10 M DPER IRQ SEL bit field 6 10 M DPER IRQ STA bit field 6 13 M GINT MODE bit field 12 5 M MABRT IRQ ENB bit field 6 10 M MABRT IRQ SEL bit field 6 9 M MABRT IRQ STA bit field 6 13 M RETRY TO bit field 6 24 M RPER IRQ bit field 6 10 M RPER IRQ SEL bit field 6 10 M RPER IRQ STA bit field 6 13 M RTRTO IRQ ENB bit field 6 10 M RTRTO IRQ SEL bit field 6 9 M RTRTO STA bit field 6 13 M SERR IRQ bit field 6 10 M SERR IRQ SEL bit field 6 9 M SERR IRQ bit field 6 13 M TABRT IRQ ENB bit field 6 10 M TABRT IRQ SEL bit field 6 9 M TABRT IRQ STA bit field 6 13 M WPOST ENB bit field 6 4 MA DRIVE bit field 20 11 Major Stepping Level bit field 4 2 MAJORSTEP bit field 4 2 Master Abort Interrupt Enable bit field 6 10 Select bit field 6 9 Status bit field 6 13 Master Address Interrupt Identi
516. ter see page 13 8 0 The PIT Channel 2 gate input is controlled by the PITGATE2 pin 1 The PIT Channel 2 gate input is asserted If the PITGATE2 pin is configured for its alternate function then the pin s input to the OR gate is held Low and this bit PIT GATE2 effectively controls the Channel 2 gate input directly Note This bit PIT GATE2 is logically ORed with the PITGATE2 signal Software using this bit should consider the configuration and state of the PITGATE2 pin Elan SC520 Microcontroller Register Set Manual 13 13 AMDA Programmable Interval Timer Registers Programming Notes 13 14 Elan SC520 Microcontroller Register Set Manual CHAPTER O AMD AMD 14 14 1 14 2 Table 14 1 GENERAL PURPOSE TIMER REGISTERS OVERVIEW This chapter describes the general purpose GP timer registers of the ElanSC520 microcontroller There are three GP timers The GP timer module is one of four ElanSC520 microcontroller timer modules The other timer modules are described in the following chapters Chapter 15 Software Timer Registers i Chapter 13 Programmable Interval Timer Registers lI Chapter 16 Watchdog Timer Registers The GP timer register set consists of 12 memory mapped configuration region MMCR registers used to configure and control each of the three GP timers See the Elan SC520 Microcontroller User s Manual order 22004 for details about the GP timers Table 14 1 lists the GP
517. the PCI bus 0 The PCI master request connected to the REQ2 pin is disabled 1 The PCI master request connected to the REQ2 pin is enabled PCI Bus Arbiter Request 1 Enable This bit enables the PCI master request connected to the REQ1 pin If this request is disabled the PCI bus arbiter does not assert GNT1 to allow the PCI master connected to the REQ1 and GNT1 pins to access the PCI bus 0 The PCI master request connected to the REQ pin is disabled 1 The PCI master request connected to the REQ1 pin is enabled Elan SC520 Microcontroller Register Set Manual Bit Name 0 REQO_ENB Programming Notes System Arbitration Registers Function PCI Bus Arbiter Request 0 Enable AMD This bit enables the PCI master request connected to the REQO pin If this request is disabled the PCI bus arbiter does not assert GNTO to allow the PCI master connected to the REQO and GNTO pins to access the PCI bus 0 The PCI master request connected to the REQO pin is disabled 1 The PCI master request connected to the REQO pin is enabled Elan SC520 Microcontroller Register Set Manual AMD System Arbitration Registers Arbiter Priority Control ARBPRICTL Memory Mapped MMCR Offset 74h 31 30 29 28 27 26 25 24 Bit CPU PRI 1 0 Reserved Reset 0 1 0 0 0 0 0 0 R W R W RSV 23 22 21 20 19
518. the PIOPFS31_16 register The two accesses are not simultaneous 20 4 Elan SC520 Microcontroller Register Set Manual Programmable Input Output Registers PIO31 P1016 Pin Function Select PIOPFS31_ 16 AMD Memory Mapped MMCR Offset C22h 15 14 13 12 11 10 9 8 PIGOJ PIO30 PIO29 PIO28 PIO27 PIO26 PIO25 PlO24 FNC FNC FNC FNC FNC FNC FNC FNC Reset 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W 7 6 5 4 3 2 1 0 7181028 PIO22_ PIO21_ PIO20_ PIO19_ PIO18_ PIO17_ PIO16_ FNC FNC FNC FNC FNC FNC FNC FNC Reset 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Register Description This register allows the programmer to choose the functionality of programmable I O pins PIO31 PIO16 Bit Definitions Bit 15 Name PIO31 FNC 29 PIO28 PIO27 26 25 Function PIO31 or RIN2 Function Select This bit is used to select the functionality of the PIO31 pin 0 The pin is PIO31 1 The pin is RIN2 PIO30 or DCD2 Function Select This bit is used to select the functionality of the pin 0 The pin is 1 The pin is DCD2 PIO29 or DSR2 Function Select This bit is used to select the functionality of the PIO29 pin 0 The pin is PIO29 1 The pin is DSR2 P1028 or CTS2 Function Select This bit is used to select the functionality of the P
519. the internally generated SDRAM ECC single bit interrupt to one of the following interrupt priority channels on the microcontroller 00000 Disables the internally generated ECC interrupt from reaching the PIC 00001 Priority P1 Master PIC IRO Highest priority 00010 Priority P2 Master PIC IR1 00011 Priority P3 Slave 1 PIC IRO Master PIC IR2 00100 Priority P4 Slave 1 PIC IR1 00101 Priority P5 Slave 1 PIC IR2 00110 Priority P6 Slave 1 PIC IR3 00111 Priority P7 Slave 1 PIC IR4 01000 Priority P8 Slave 1 PIC IR5 01001 Priority P9 Slave 1 PIC IR6 01010 Priority P10 Slave 1 PIC IR 01011 Priority P11 Master PIC IR3 01100 Priority P12 Master PIC IR4 01101 Priority P13 Slave 2 PIC IRO Master PIC IR5 01110 Priority P14 Slave 2 PIC IR1 01111 Priority P15 Slave 2 PIC IR2 10000 Priority P16 Slave 2 PIC IR3 10001 Priority P17 Slave 2 PIC IR4 10010 Priority P18 Slave 2 PIC IR5 10011 Priority P19 Slave 2 PIC IR6 10100 Priority P20 Slave 2 PIC IR7 10101 Priority P21 Master PIC IR6 10110 Priority P22 Master PIC IR7 Lowest priority 10111 11111 Disables the internally generated ECC interrupt from reaching the PIC o 5 wo For example if IRQ MAP 01101b the ECC interrupt request is mapped to interrupt priority P13 in the microcontroller If IRQ 00000b or any binary value from 10111 11111b the ECC interrupt request is disa
520. this bit removes this direct interrupt assertion 0 Do not assert the interrupt 1 2 Assert the interrupt lan SC520 Microcontroller Register Set Manual 12 13 AMD Programmable Interrupt Coniroller Registers Bit Name Function 0 SW P17 TRIG Directly Trigger Priority Level P17 Setting this bit directly asserts a maskable interrupt of priority level P17 Clearing this bit removes this direct interrupt assertion 0 Do not assert the interrupt 1 2 Assert the interrupt Programming Notes This register SWINT22 17 and register SWINT16 1 provide access to all 22 maskable interrupt priority levels Priority level P1 is the highest priority and priority level P22 is the lowest Setting an interrupt trigger bit causes an interrupt to be asserted on the corresponding PIC s interrupt channel for as long as the bit is set To use these bits effectively the interrupt service routines should clear the interrupt trigger bit early in the routine Note that for the internal PC AT compatible peripherals and for many PCI peripherals existing drivers in off the shelf operating systems are not aware of these interrupt trigger bits For peripherals with these kinds of interrupt Service routines care must be taken notto set the interrupt trigger bits If this occurs the interrupt gets stuck in the asserted state and the system loops in the interrupt service routine because the routine does not clear the trigger bit 12 14 Elan SC520 Micr
521. trol Word 3 S1PICOCWS page 12 55 Slave 1 PIC Initialization Control Word 2 S1PICICW2 page 12 57 Slave 1 PIC Initialization Control Word 3 S1PICICWS page 12 58 Slave 1 PIC Initialization Control Word 4 S1PICICWA page 12 59 Slave 1 PIC Interrupt Mask S1PICINTMSK page 12 60 FPU Error Interrupt Clear FPUERRCLR Elan SC520 Microcontroller Register Set Manual page 12 61 12 3 AMD Interrupt Control PICICR Programmable Interrupt Controller Registers Memory Mapped MMCR Offset DOOh 7 6 4 2 1 0 S2 GINT S1 GINT M GINT Bit NMI DONE Reserved MODE MODE MODE Reset 0 0 0 1 1 1 R W R W R W RSV R W R W R W Register Description This register controls the global interrupt mode for the Master Slave 1 and Slave 2 programmable interrupt controllers slave controller bypass and the global nonmaskable interrupt NMI mask bit Bit Definitions Bit Name Function 7 NMI_DONE NMI Routine Done 0 After this bit is set it is cleared automatically by interrupt controller logic 1 Software sets this bit to indicate that the NMI routine is completed Subsequent NMI events are blocked by the interrupt controller until the NMI_DONE bit is set by software but if an NMI source is active at the time when the handler for another NMI sets this bit then the interrupt controller generates an NMI for the second source shortly
522. unt Low register 11 38 GP DMA Channel 7 Extended Page register 11 16 Extended Transfer Count register 11 20 Next Address High register 11 33 Next Address Low register 11 32 Next Transfer Count High register 11 41 Next Transfer Count Low register 11 40 GP DMA Control register 11 4 GP DMA direct mapped registers table 11 2 GP DMA Memory Mapped I O register 11 5 GP DMA MMCR registers table 11 1 GP DMA Resource Channel Map A register 11 6 GP DMA Resource Channel Map B register 11 8 GPDMAOMAR register 11 42 Index 8 Elan SC520 Microcontroller Register Set Manual GPDMAOPG register 11 69 GPDMAOTC register 11 43 GPDMA1MAR register 11 44 GPDMAt PG register 11 65 GPDMA17TC register 11 45 GPDMA2MAR register 11 46 GPDMA2PG register 11 63 2 register 11 47 GPDMASMAR register 11 48 GPDMASPG register 11 64 GPDMASTC register 11 49 GPDMA4MAR register 11 78 GPDMAGTC register 11 79 GPDMAS5MAR register 11 80 GPDMASPG register 11 73 GPDMASTC register 11 81 GPDMA6MAR register 11 82 GPDMAGPG register 11 71 GPDMAGTO register 11 83 GPDMA7MAR register 11 84 GPDMA7PG register 11 72 GPDMA7TC register 11 85 GPDMABCCTL register 11 21 GPDMABCSTA register 11 22 GPDMABCVAL register 11 25 GPDMABSINTENB register 11 24 GPDMACTL register 11 4 GPDMAEXTCHMAPA register 11 6 GPDMAEXTCHMAPB register 11 8 GPDMAEXTPGO register 11 10 GPDMAEXTPG register 11 11 GPDMAEXTPG2 register 11 12 GPDMAEXTPG3 r
523. used in two successive I O accesses to read write the channel s memory address bits 16 1 for 16 bit DMA transfers Bits 8 1 of the channel s memory address can be read from or written to this bit field immediately after a write to the MSTDMACBP register see page 11 93 Bits 16 9 of the channel s memory address can be read from or written to this bit field immediately after memory address bits 8 1 are read from or written to this bit field Programming Notes To ensure that the lower byte of this register GPDMA6MAR is always accessed first software should precede any access to this register with a write to the MSTDMACBP register see page 11 93 to clear the master DMA byte pointer The value in this register GPDMA6MAR is used with the values in the GPDMAGPG register see page 11 71 and the GPDMAEXTPG6 register see page 11 15 to generate DMA address bits 27 0 By default this channel is set up for PC AT compatibility 16 bit DMA transfers on the master DMA controller For 16 bit transfers this register GPDMA6MAR holds address bits 16 1 and address bit 0 is always 0 i e the 16 bit transfers are word aligned Because of this software must load this register with the desired memory address divided by 2 for 16 bit transfers In enhanced mode this channel can be programmed for 8 bit DMA transfers see the descriptions for GPDMACTL register bits ALT SIZE and ENH MODE ENB on page 11 4 For 8 bittransfers
524. ute Software initializes the alarm minutes value for the RTC by writing data to this bit field in either binary or binary coded decimal BCD format The alarm minutes component of the RTC time can be read from this bit field Writing a value of CO FFh to this bit field makes the minutes component of the alarm a wild card For example setting the hours and minutes alarm registers to COh causes an RTC alarm event to be generated once per minute The wild card based once per minute alarm does not occur unless the hours alarm setting is also a wild card The RTC logic checks once per second to see if an alarm has occurred Valid values for this bit field range from 0 to 59d and all wild card values Software can suspend updating of the RTC via the SET bit in the RTCCTLB register see page 17 16 Software selects binary or BCD format via the DATE MODE bit in the RTCCTLB register Software can enable the RTC alarm as an interrupt via the ALM INT ENB bit in the RTCCTLB register The ALM INT bit in the RTCSTAC register indicates whether an alarm event has occurred see page 17 18 Elan SC520 Microcontroller Register Set Manual 17 7 AMD Real Time Clock Registers RTC Current Hour RTCCURHR Address 70h 71h RTC Index 04h 7 6 5 4 3 2 1 0 Bit AM PM HOUR 6 0 Reset x x x x x R W R W R W Register Description This register used to initialize and read back the RTC current hour
525. vel and priority Watchdog Timer Reset Enable This is a programmable bit to select between a reset or interrupt as the time out action 0 The watchdog timer time out generates an interrupt request if the IRQ_FLG bit is not already set If IRQ_FLG bit is set a system reset is generated instead 1 The watchdog timer time out always generates a system reset When the watchdog timer generates a system reset the WDT_RST_DET bit is set in the RESSTA register see page 3 5 Reserved This bit field should be written to 0 for normal system operation Interrupt Request Flag This bit provides an indication of interrupt events generated by the watchdog timer time out This bit is accessible even after the ENB bit is set 0 No watchdog timer interrupt has occurred 1 Watchdog timer interrupt has occurred This bit is cleared by writing a 1 After a watchdog timer time out occurs if this bit is not cleared before a second time out of the watchdog timer a watchdog timer system reset is generated instead of a second interrupt request Reserved This bit field should be written to 0 for normal system operation Elan SC520 Microcontroller Register Set Manual Watchdog Timer Registers AMDA Bit Name Function 7 0 EXP SEL 7 0 Exponent Select This bit field determines the duration of the watchdog timer time out interval Table 16 2 shows the values for the EXP SEL field The bit values shown in the table are programmed to select a time
526. width time of the GP bus read strobes The resolution of this parameter is one internal 33 MHz clock period The width used is GP RD WIDTH 1 internal clock periods i e if GP RD WIDTH is 0 the pulse is one clock period wide Programming Notes Figure 10 1 on page 10 7 shows the relationships between the various adjustable GP bus timing parameters 10 10 Elan SC520 Microcontroller Register Set Manual General Purpose Bus Controller Registers GP Read Offset GPRDOFF AMD Memory Mapped MMCR Offset COCh 7 6 5 4 3 2 1 0 Bit GP RD OFF 7 0 Reset 0 0 0 0 0 0 0 0 R W R W Register Description This register is used to program the offset time from beginning of a GP bus cycle for GPIORD and GPMEMRD Bit Definitions Bit Name 7 0 GP_RD_OFF 7 0 Programming Notes Function Offset Time for GPIORD and GPMEMRD This field adjusts the offset time of the GP bus read strobes The resolution of this parameter is one internal 33 MHz clock period The offset time used is GP_RD_OFF 1 internal clock periods i e if GP_RD_OFF is 0 the offset time is one clock period Figure 10 1 on page 10 7 shows the relationships between the various adjustable GP bus timing parameters Elan SC520 Microcontroller Register Set Manual 10 11 General Purpose Bus Controller Registers GP Write Pulse Width GPWRW Memory Mapped MMCR Offset CODh
527. written while the counter is enabled the new value is latched into the GP Timer 0 counter and counting proceeds from this new value Programming Notes Each time this GPTMROCNT register is incremented its value is compared with the value of register GPTMROMAXCMPA or GPTMROMAXCMPB see page 14 7 and page 14 8 and various actions are taken when a maximum count is reached For details see the GPTMROCTL register bits INT ENB MAX CNT RIU MAX ONT ALT CMP and CONT CMP starting on page 14 4 14 6 Elan SC520 Microcontroller Register Set Manual General Purpose Timer Registers AMDA GP Timer 0 Maxcount Compare A GPTMROMAXCMPA Memory Mapped MMCR Offset C76h 15 14 13 12 11 10 9 8 Bit MCA 15 8 Reset 0 0 0 0 0 0 0 0 R W R W 7 6 5 4 3 2 1 0 Bit MCA 7 0 Reset 0 0 0 0 0 0 0 0 R W R W Register Description This register contains one of the compare values for the GPTMROCNT register see page 14 6 Bit Definitions Bit Name Function 15 0 15 0 GP Timer 0 Maxcount Compare Register A This register contains one of the maximum values that GP Timer 0 can count to before resetting its count register to O Programming Notes GP Timer 0 and GP Timer 1 each have two maxcount compare registers GPTMRxMAXCMPA and GPTMRxMAXCMPB If the maxcount compare register that is in use contains the value 0000h and the timer is enabled the timer counts to FFFFh at
528. y address can be read from or written to this bit field immediately after a write to the SLDMACBP register see page 11 57 Bits 15 8 of the channel s memory address can be read from or written to this bit field immediately after memory address bits 7 0 are read from or written to this bit field Programming Notes To ensure that the lower byte of this register GPDMA2MAR is always accessed first software should precede any access to this register with a write to the SLDMACBP register see page 11 57 to clear the slave DMA byte pointer The value in this register GPDMA2MAR is used with the values in the GPDMA2PG register see page 11 63 and the GPDMAEXTPG2 register see page 11 12 to generate DMA address bits 27 0 11 46 Elan SC520 Microcontroller Register Set Manual GP DMA Controller Registers AMDA Slave DMA Channel 2 Transfer Count GPDMA2TC Direct Mapped I O Address 0005h 7 6 5 4 3 2 1 0 Bit DMA2TC 15 0 Reset X X X X X X X X R W R W Register Description This register contains bits 15 0 of the transfer count for Channel 2 during DMA operation Bit Definitions Bit Name Function 7 0 DMA2TC DMA Channel 2 Transfer Count 16 Bit Register 15 0 This 8 bit field is used in two successive I O accesses to read or write the channel s transfer count bits 15 0 Bits 7 0 of the channel s transfer count can be read from or written to this bit field immediately after a wr
529. y hard reset was detected 1 The CPU hard reset event was from an AMDebug technology hard reset AMDebug Technology System Reset Detect This bit is set when an AMDebug technology system reset is detected Software clears this bit by writing a 1 0 2 No AMDebug technology system reset was detected 1 The system reset event was from an AMDebug technology system reset If the PRG bit is 1 in the RESCFG register see page 3 3 an AMDebug technology system reset results in a programmable reset in which the SDRAM configuration is maintained Watchdog Timer Reset Detect This bit is set when a watchdog timer system reset is detected Software clears this bit by writing a 1 0 No watchdog timer reset was detected 1 The system reset event was from a watchdog timer time out If the PRG RST bit is 1 in the RESCFG register see page 3 3 a watchdog timer reset results in a programmable reset in which the SDRAM configuration is maintained Elan SC520 Microcontroller Register Set Manual 3 5 AMD Reset Generation Registers Bit Name Function 2 SD RST DET CPU Shutdown Reset Detect This bit is set when a CPU shutdown cycle typically caused by a software triple fault is detected Software clears this bit by writing a 1 0 No CPU shutdown cycle was detected 1 The CPU soft reset event was from a shutdown cycle A soft reset event clears the NMI bit in the PICICR register see page 12 4 This allows

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