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1. Run For Time run 100 rESS x es These Simulator commands run tion Sees are available from HDL Designer 100 Default Cancel 9 14 ModelSim Advanced Debugging Debug Detective Overview Copyright 2002 Mentor Graphics Corporation Notes The simulation control bar in the Debug Detective windows is similar to the one used within the ModelSim environment Each icon represents a function e Run for Time icon used to run the design for a certain duration If you select Choose from the menu a pop up window will appear that allows you to enter the run duration e Run Forever runs the the entire design Also known as the Run All icon ModelSim Advanced Debugging 9 17 December 2002 Debug Detective 9 18 Run to Next Event runs until the first break To resume design execution click on the Continue icon Step single step through the design To exit from a loop use the Step Over icon Restart Simulator restarts the simulation ModelSim Advanced Debugging December 2002 Debug Detective Simulation Probes Simulation Probes Add a probe from the Simulation menu work uart_top struct Read only Block Diagram File Edit View Diagram Simulation Window Help alo MP Fn Step gt Environment gt Breakpoints 1 gt gt Probes Display View Signal Info Restart Simulator i eT as Sy ec IT GL a 0
2. vrork serial_interface struct IBD i xi Ale Edk Yew Table Simuation Yindow Help amp o c gl A sl Blocks IPs Port signal Components order Port Signal Names Interconnect Types IO Ports of the Current Design Multiple Tables Et ER P e 0 XC DS EF BBS we FF Roady y 9 11 ModelSim Advanced Debugging Debug Detective Overview Copyright 2002 Mentor Graphics Corporation This tabular representation of a design lists e the I O ports of the current design the port or signal order the port or signal names and types plus any additional constraints whether the ports or signals are blocks components or reused IP and the interconnect relationship whether you have multiple tables 9 12 ModelSim Advanced Debugging December 2002 Debug Detective State Diagram State Diagram ill State Diagram e Simulation Control e Set Breakpoints e Graphical Animation e Graphical State Coverage e Simulation cross probe Simulation amp Animation Toolbars amp Menus niv 1 AND xmiidt_en 1 Simulation Tools Lx i 84 82584 c BDO X 0 m 7 EF Animation Tools do 9 M M dE om s 9 12 ModelSim Advanced Debugging Debug Detective Overview Copyright 2002 Mentor Graphics Corporation Notes Most engineers are familiar with the state diagramming capabilities You will always have i
3. Profile Source Coverage Breakpoints Execute Macro Tcl Debugger IclPro Debugger Options Edit Preferences Save Preferences Start Comparison Comparison Wizard End Comparison Add 3 Run the compare Options Differences Rules Reload Start Comparison Comparison Wizard Bun Comparison End Comparison Options Differences Rules Reload 6 10 ModelSim Advanced Debugging Waveform Compare Notes 6 10 Compare cae Clocks Using the Menus to Define a Comparison 2 Add signals Start Comparison Comparison Wizard Bun Comparison Add Options Differences Rules Reload a 4 End the compare Copyright 2002 Mentor Graphics Corporation ModelSim Advanced Debugging December 2002 Waveform Compare Waveform Compare Dialog Boxes Waveform Compare Dialog Boxes Dialog boxes to set up a Compare Add Signal Options olx Properties Comparison Method Compare is ETE Options BS Clocked Comparison default clock o Clocks structure_browser min le Continuous Comparison tst_pseudo tst_pseudo 19 Register clock Leading Tolerance Trailing Tolerance Register reset o ns i o ns im Register expected 19 Register storage Net data Specify When Expression r Net expected_w he Select Signals chip pseudo Builder Th
4. dc eorf orrorrn ooof jecoooe OrnrBMooorer ens rr o m ooog oo og OK Cancel 3 15 ModelSim Advanced Debugging Test Benches Copyright 2002 Mentor Graphics Corporation Notes ModelSim Advanced Debugging 3 15 December 2002 Test Benches 3rd Party Test Benches 3rd Party Test Benches All major test bench development tools are integrated with ModelSim sity Synopsys FORTE SpecMan Vera Quickbench Highest level of abstraction Fast execution speed Each has dedicated language for test bench development Requires purchasing and learning new tools 3 16 ModelSim Advanced Debugging Test Benches Copyright 2002 Mentor Graphics Corporation Notes ModelSim Advanced Debugging December 2002 Test Benches Signal Spy Signal Spy Ability to probe through VHDL hierarchy Ability to probe through MixedHDL designs New VHDL Procedure utility init signal driver e init signal spy source destination verbose signal force New VHDL library signal_release e modelsim_lib New Verilog System Task Sinit signal driver e init signal spy source destination verbose signal_force signal release Why use Hierarchy access e VHDL does not allow hierarchical notation e Cannot directly read or change a VHDL signal variable or generic with a hierarchical reference within a mixed language design e Cannot directly access a Verilog object in
5. eese 6 18 T l Compare Command omes bec etd reos s or eter ous dedu bou ae ad ates etna 6 19 Compare Example sksini ie a tox te D essere whist rua etes ete 6 20 Waveform Compare Example 5 1r DR pee Haec c P CEDE PEDE D s ra cod 6 22 when Statement MORTE 6 23 Compressed Waveform Files 2 35onddtite s deliuiatica a recte kn Er aaa bu b Eoi o E 6 24 Disable Enable Pop up s a doe Ee po n exo A t bt ro od 6 25 SUTDITIOESE euis eroe ks tmi cale e ee tut bte a cit Ed cited AS EERE G RUE 6 26 Lab 6 Waveform Compare taa ridi botte ere EP isan EE VEA FUP EHE PERS EROR 6 27 Module 7 FLI and C Models und iinc aono apo qoa a eA aue oy SEEK Phy e xa ave oo eo MEA URY ES iseni 7 1 Module OVePVIe Weis duces ite etes oem tete bonu tene LUE ui a t Oe D caet 7 2 A Was Bop eis ado Hoa cate 7 3 WAY EE DE nee er ene ee e Gest Guasstconed ite di E OLD SA cune epa 7 5 Mihodgs Using FEI essi Fi ED RH Aa UR utto ite Ice hel UD RU 7 7 Benettts of C Interface aote ptt cte be rudi Nan alb o batipede onis 7 8 EEV C FUNCH ONS oda p DOR Ho tette ob te Gar Orb CR elei 7 9 UE CaN DAG crc HC 7 11 Hierarchy Scanno dac do NE ao o ot 7 13 Signals and Variables coo deba cic sense iutwnetgele iia tec v MEA M Ep nA 7 16 Utt Sr is iens est ses uti tue tbassabua eda cest iota efe di Naat eot sut ea enced 7 19 ModelSim Advanced Debugging xi December 2002 Table of Contents TABLE OF CONTENTS Cont Foreign Architecture Initialization
6. l a Hop clk time dan Open dataflow window top pstrb MEAL Drag signal to dataflow Atop paddr 00001001 an IX g top pdata Ti 3 1 window Aides e drivers of signal appear Atop sstib Atop srdy top saddr 00001001 top sdata Hiop data out sOspy CETRTRTETETETETETETETET S UUUUUUUUUUUUIOU iix File Edit view Navigate Trace Tools Window top data_out_s1 spy tH UUUUUUUUUUUUUMUU top data_out_s2spy SSS UU UU By R top data out s3spy i ai y ap i f 0 E e Ke 3e 3 top test define EN i Vtap test delfine2 000000000000 ULIULILIULU UU U LIU au ZIIENII 1255 ns to 2641 ns Extended mode enabled Keep Atap p t out pA 8 10 ModelSim Advanced Debugging Debugging Copyright 2002 Mentor Graphics Corporation Notes 8 10 ModelSim Advanced Debugging December 2002 Debugging Erroneous Data Erroneous Data Back trace cause of error with Dataflow window e same as previous slide showing back tracing X s Use source window to display relevant code while back tracing File Edit Cursor Zoom Compare Bookmark Format Window Sane SHS BB RR eX QQQQR E ELELE File Edit Object Options window E fedele 28 f 268 BAAP 6 compare top data_oi compare top test_de match i Write 10 locations compare top test_de match 73 for a 0 a 10 a a 1 compare top p clk matc
7. est_counter dut inst Vleaf ck bot mm ioj x ge m File Edt Markers Prop Window AUS as ene nter spy_top_clock test_counter dut inst leat Count E test cou tS Io ter Adut M inst c1k test counter spy top count d A inst leaf c1k bot y e test counter spy top reset i ounter dut inat leat resety B x X Stk x sex doooaooor IOI 0 0 sto D Sto HORN OIE tol O O Sto 1 Sti ovo SEE 0 0 Sto D Sto SOK HHI 0 0 sto D sto 00000000 00000000 118t10 sto o0000000 00000000 118t10 sto 00000001 00000001 0 0 Sto D sto 00000001 00000001 113t10 sto 00000001 00000001 11 Sti 0 sto 00000010 00000010 0 0 Sto D sto 00000010 00000010 11 Sti 0 sto 00000010 00000010 9135 ns to 9753 ns p IE ModelSim Advanced Debugging December 2002 Copyright 2002 Mentor Graphics Corporation 3 21 Test Benches Summary Summary This module introduced and explored the application of the following topics Functions of Test Benches Different Types of Test Benches Pros amp Cons of Each of the Different Types of Test Benches 3 21 ModelSim Advanced Debugging Test Benches Copyright 2002 Mentor Graphics Corporation Notes 3 22 ModelSim Advanced Debugging December 2002 Test Benches Lab 3a Tcl Tk Testbench Introduction This lab will take you step by step through the design flow using ModelSim You will first change the working directory get the design compiled simulate it and use
8. Helps you write VHDL or Verilog code View gt Show language templates ipi xi File Edit View Tools Debug Window SSNS JARAH MAURIN Hop 38 ARCHITECTURE RTL OF control IS 39 signal address std_logic_vector counter_size EHP Language Constructs 2 Library Definitions HEJ Entity HAJ Architecture HHP Package ic Configuration f Declarations Statements ERS Stimulus Generators 40 signal control reg std logic vector DOWNTO 41 signal monitor std logic vector DOWNTO 0 42 signal rxd active std logic 43 BEGIN m source proc EEE File Edit View Tools Debug Window esus 2R0a UT mu switching ESS wrb reset 1 module proc clk addr data rw strb rdy Templates J Clock input clk rdy BR New Design Wizard 1 THEN 2 Counter output addr rw strb inout data EHT Language Constructs Stop Simulation EEEE dn Ln 38 Col 0 read only P define addr size Declarations define word size Statements Instantiations 9 reg addr size addr r Ce Decl 10 reg word_size i 0 data r ompiler Directives 11 reg rw r strb r Blocks System Tasks and Functions 13 reg verbose EH Stimulus Generators 1 m 14 wire t_out J Clock n oa 15 wire addr size 0 5 addr addr r 2h Counter Collection of wizards menus and dialogs 16 wire word_si
9. Turn on the performance profiler profile on and run the simulation for 5 13 us time run 5 13 us How long was the ModelSim runtime for the gate level SDF simulation move the decimal point 6 places to get the number of seconds Is this runtime less than what you observed in the math sdo design How much slower or faster was the math opt vhd runtime vs math vhd Now perform a waveform comparison similar to Part 4 of this lab exercise of the RTL simulation to the gate level SDF simulation Open the golden waveform results file gold opt wlf Start the comparison between gold wlf gold and the current open waveform simulation sim Compare the product and count out outputs from the two datasets Run the comparison What is the medium propagation delay difference for the product output between the two datasets ModelSim Advanced Debugging December 2002 Debugging What is the medium propagation delay difference for the count out output between the two datasets What is the propagation delay from data_c input equal 7 to increment out output equal to 7 Is this propagation delay less than what you observed in the math vhd design Why or why not 11 End the comparison when you are completed Close the gold opt dataset and quit the current simulation but do not close ModelSim Part 7 Verilog Gate Level SDF Simulation with a VHDL Testbench Mo
10. Help SE PDF Documentation Command Reference i BS i gdl ESR UE 3 lee ee eee ee Sele ou JES About ModelSim x Release Notes Welcome Menu SE PDF Documentation gt SE HTML Documentation gt Tel Man Pages Technotes Ilf modelsim fib std Debug Detective Bookcase 2 22 ModelSim Advanced Debugging Tcl Tk Overview Copyright 2002 Mentor Graphics Corporation Notes 2 22 ModelSim Advanced Debugging December 2002 Tcl Tk Overview Summary Summary This module introduced and explored the application of the following topics Tcl Tk syntax Key Tcl capabilities The application of Tcl to ModelSim Command substitution Multiple line commands Creating a Simulation Script Using the Saved Transcript Adding buttons to existing windows Executing ModelSim commands from Tcl Tcl Tk script examples 9 9 9 9 9 9 9 2 23 ModelSim Advanced Debugging Tcl Tk Overview Copyright 2002 Mentor Graphics Corporation Notes ModelSim Advanced Debugging 2 23 December 2002 Tcl Tk Overview Lab 2 Using Tcl Scripts and Tk Widgets in Simulation Introduction This lab introduces you to the concept of using Tcl Tk as an aid to simulation and debugging The lab combines a mixture of ModelSim commands Tk widgets and Tcl scripting You will see that you can streamline your simulations using Tcl scripts and you can add push button ease to your simul
11. Note On the Sun platform the script runs in the shelltool window not the ModelSim transcript window When you are done examining the table quit simulation but leave ModelSim open VSIM quit sim 6 Let s take a look at what the Tcl script is doing We can open the file using a text editor by issuing a command from the ModelSim prompt ModelSim notepad cor it do Notice the first thing the script does is to convert bin in from binary to bcd Next the script uses the simulation command force to drive some signal values and uses the set command to set up variables inside the for loop Note also that the variable a 1s declared for the first time in the for loop parameters as follows for set a O0 Sa lt 91 incr a Remember that the dollar sign in front of the variable symbol means the value of the variable You may want to open the VHDL source file and study it so that you can understand what it s doing and how the Tcl testbench drives the process Open the file in Notepad like we did the for the cor_it do file ModelSim gt notepad cordic_core_rtl vhd ModelSim Advanced Debugging 2 25 December 2002 Tcl Tk Overview 2 26 While we re at it let s add the veom command at the top of the file cor_it do so cordic core rtl vhd is compiled when we run the script Make sure to add the command to load the design as well vcom 93 cordic core rtl vhd vsim cordic core add log Save your changes
12. Scepter Scepter DFF Schematic View Compiler SVC Schemgen SDF Software Data Formatter SDL2000 Lcompiler Seamless Seamless C Bridge Seamless Co Designer Seamless CVE Seamless Express Selective Promotion SignaMask OPC Signal Spy Signal Vision Signature Synthesis Simulation Manager SimExpress SimPilot SimView SiteLine2000 SM SmartMask SmartParts SmartRouter SmartScripts Smartshape SNX SneakPath Analyzer SOS Initiative Source Explorer SpeedGate SpeedGate DSV SpiceNet SST Velocity Standard Power Model Format SPMF Structure Recovery Super C Super IC Station Support Services BaseLine SM Support Services ClassLine SM Support Services Latitudes SM Support Services OpenLine SM Support Services PrivateLine SM Support Services SiteLine SM Support Services TechLine SM Support Services RemoteLine SM Symbol Genie Symbolscript SYMED SynthesisWizard System Architect System Design Station System Modeling Blocks Systems on Board Initiative System Vision Target Manager Tau TeraCell TeraPlace TeraPlace GF TechNotes The Ultimate Tool for HDL Simulation TestKompress Test Station Test Structure Builder The Ultimate Site For HDL Simulation TimeCloser Timing Builder TNX ToolBuilder TrueTiming Vlog V Express V Net V
13. mti ScheduleDriver ip gt enum out long val out 0 MTI INERTIAL mti ScheduleDriver used to set enum values 7 25 ModelSim Advanced Debugging FLI and C Models Copyright 2002 Mentor Graphics Corporation Notes ModelSim Advanced Debugging 7 41 December 2002 FLI and C Models Enums and Arrays Cont Enums and Arrays Cont Reading and Setting Arrays static_void eval_array ip inst_rec ip typedef enum BIT_O BIT 1 bit char val_a 8 val_b 8 val_out 8 char enum_literals int i mti_GetArraySignalValue used to read arrays Evaluate array_out lt array_a and array_b mti_GetArraySignalValue ip gt array_a val_a a mti GetArraySignalValue ip gt array b val b for i 0 i lt 8 i if val_a i BIT_1 amp amp val_b i BIT_1 val_out i BIT_1 else val out i BIT 0 mti ScheduleDriver used to set array values 4 mti ScheduleDriver ip gt array out long val out 0 MTI INERTIAL 7 26 ModelSim Advanced Debugging FLI and C Models Copyright 2002 Mentor Graphics Corporation Notes 7 42 ModelSim Advanced Debugging December 2002 FLI and C Models FLI Problems FLI Problems Fatal FLI errors usually result in a crash Fatal bad pointer access Time 63700 ns Iteration 5 Instance testbench textio_inst Fatal error at line 0 Non fatal bugs can lead to wrong simulation results or errors from
14. 2002 Mentor Graphics Corporation Notes We ll limit the discussion to C from here on out Refer to the Foreign Language Interface Reference Manual for information on how to compile and use C 7 8 ModelSim Advanced Debugging December 2002 FLI and C Models FLI C Functions FLI C Functions FLI Callbacks Routines in the C program that ModelSim will call when certain conditions are met i e elaboration complete simulator exiting restart save restore starting and stopping a run etc Hierarchy Scanning Routines for traversing the hierarchy of a design Reading and Setting Signals and Variables Utilities Routines for allocating memory executing commands issuing messages etc Reference the ModelSim FLI Manual FLI Function Definitions 7 7 ModelSim Advanced Debugging FLI and C Models Copyright 2002 Mentor Graphics Corporation Notes There are many FLI callback functions Refer to the ModelSim Foreign Language Interface Reference Manual FLI Function Definitions section A few functions will be discussed here Keep in mind the following There are several FLI functions that work only during certain simulator phases e g mti GetVarImage or only when called from a certain context e g from either inside of a process mti GetNextNextEventTime or outside of a process mti GetNextEventTime ModelSim Advanced Debugging 7 9 December 2002 FLI and C Models 7 10 The
15. Blo e A 9 9 AD R AMS Bl JP i BIET Eb P Do MOOR 9 be Dz M M da S Se BS Simulation time 850 end waiting to xmit shown in red and the previous state finish xmit shown in yellow You can review a limited amount of animation in Debug Detective by using the a and the gt gt buttons to step through each state diagram object Open a Flow Chart 1 Make serial_interface block diagram active 2 Select the status_registers component and choose Open As gt Flow Chart with the RMB A Flow Chart diagram will appear as shown in the diagram below ModelSim Advanced Debugging 9 37 December 2002 Debug Detective 3 Close the project you have been working on by choosing File gt Close gt Project from the ModelSim Main window 4 Exit the ModelSim simulator by choosing File gt Quit from the ModelSim Main window For the latest information about Debug Detective see the web site at http www debugdetective com For the latest information about HDL Designer Series see the web site at http www hdldesigner com For customer support contact hdldesigner_support mentor com 9 38 ModelSim Advanced Debugging December 2002 NOTES ModelSim Advanced Debugging December 2002 Part Number 069776
16. X OE dA OO PE signal Proc signal signal signal syst signal signal signal signal signal signal signal signal signal signal signal signal begin ini ini ini ini ini ini ini ini ini ini ini ini wai end proce cik lt P proc Mere m memo end component a Std logic vector downto Spy On Some Signals process begin init signal spy top ic V prdy r top prdy reg 1 init signal spy top ic A sdata r top sdata reg 1 init signal spy top p rw top Yc V vlog vlog top 1 E strb ray elk std logic 0 essor bus signals pru pstrb prdy std logic paddr std logic vector downto 0 pdata std logic vector downto em bus signals top prdy reg bit top sdata reg std logic vector downto 0 sru sstrb srdy std logic top clk sl std logic top clk bit bit top paddr std logic vector downto 5 top paddr b bit vector downto O top wen std logic saddr std logic vector downto O top addr std logic vector downto O top data out std logic vector downto sa t signal _spy t signal epy t signal spy t signal spy t signal epv t signal spy t signal spy t signal spy t signal epv t signal epy top p addr top Xc V vlog vlog top array top Ne V s1 junk top Vc V vlog top top Nc M s1 3unk array top ic V
17. Example Cont Ranked Output Ranked Profile lol x Samples 870 I a EE eg Nme umetz ma E F mentor_training lab1 arith_stc unsigndb vhd 64 11 F mentor training lab1 arith_ste unsigndb vhd 189 7 F mentor_training lab1 arith_stc unsigndb vhd 216 6 o store array vhd 39 12 yy Hiera rchical Output F mentor_training lab1 testring vhd 99 5 5 F mentor training lab1 control vhd 87 13 4 F mentor_training lab1 testring vhd 97 3 3 F mentor training lab1 control vhd 38 10 3 retrieve array vhd 35 3 F mentor training lab1 arith_ste unsigndb vhd 58 2 2 F mentor_training lab1 arith_ste unsigndb vhd 222 x 2 I E tnenior treining LN F mentor training lab1 control vhd 130 2 2 Lc Akona F mentor training lab1 arith_ste unsigndb vhd 22 2 2 lore array vhd 38 F mentor training lab1 arith_src unsigndb vhd 69 2 2 E e tinbnl drin F mentor training El retrieve array vhd 35 F mentor training lab1 arith src unsigndb vhd 216 R anke d By In F mentor_training lab1 testring vhd 99 F mentor_training lab1 testring vhd 97 Highlight gt 5 In 6 Spent In On Function 4 17 ModelSim Advanced Debugging Analyzing Performance Copyright 2002 Mentor Graphics Corporation Notes If we take a look at the ranked view we can see that the lines are sorted by their in value Therefore the line or function that the simulation spent the most time in will be displayed on the top The
18. Fatal error at Source sequencer vhd line 39 Project debug lab2 Now 63 700 ns Delta 5 sim testbenchitextio_inst Bb 8 To narrow down on the problem we ll re run the simulation with the trace_foreign switch This will create a trace file that shows what FLI calls were made and what their arguments were This will help us determine the location of the bug You can also debug this by inserting print statements in the FLI code and watching how many print messages come out but the trace file is much easier A third option would be to use a C debugger such as gdb but that will be too complicated for this lab There is information on how to do this in the ModelSim User s Guide 9 Quit the current simulation quit sim 10 If you are working on a Unix System skip this step If you are working on a Windows System Comment out line 154 of Source error testbench_error c Recompile and relink testbench_error c If ip void 7 1 ModelSim Advanced Debugging 7 53 December 2002 FLI and C Models 11 12 13 14 15 7 54 Re run ModelSim with the trace_foreign switch as follows vsim trace_foreign 3 testbench There are different levels of tracing level 3 gives the most detailed information It also outputs some other files that can be used to emulate the FLI code s interaction with the simulator This can be useful to create a test case to MTI if you think you ve found a bug in the F
19. IP QuickUse IPSim IS_Analyzer IS_Floorplanner IS_MultiBoard IS_Optimizer IS_Synthesizer ISD Creation SM ITK It s More than Just Tools SM Knowledge Center SM Knowledge Sourcing SM LAYOUT LNL LBIST LBISTArchitect Language Neutral Licensing Lc Lcore Leaf Cell Toolkit Led LED LAYOUT Leonardo LeonardoInsight LeonardoSpectrum LIBRARIAN Library Builder Logic Analyzer on a Chip SM Logic Builder Logical Cable LogicLib ogio Lsim Lsim DSM Lsim Gate Lsim Net Lsim Power Analyst Lsim Review Lsim Switch Lsim XL Mach PA Mach TA Manufacture View Manufacturing Advisor Manufacturing Cable MaskCompose MaskPE MBIST MBISTArchitect MCM Designer MCM Station MDV MegaFunction Memory Builder Memory Builder Conductor Memory Builder Mozart Memory Designer Memory Model Builder Mentor Mentor Graphics Mentor Graphics Support CD SM Mentor Graphics SupportBulletin SM Mentor Graphics SupportCenter SM Mentor Graphics SupportFax SM Mentor Graphics SupportNet Email SM Mentor Graphics SupportNet FTP SM Mentor Graphics SupportNet Telnet SM Mentor Graphics We Mean Business MicroPlan MicroRoute Microtec Mixed Signal Pro ModelEditor ModelSim ModelSim LNL ModelSim VHDL ModelSim VLOG ModelSim SE ModelStation Model Technology
20. c scccessseccssessecsssstesseseceesseneeeseennesees 7 24 Mapping Daba3lYD8S usto ietetio ii dere E Secteur deoa Rest lao anat 7 27 Enumerations Reals and Time seen nemen eene 7 29 PNETAN Me 7 30 Using Checkpoint and Restore With FLI eee etre eterne 7 31 C Architecture Example sai dben mar ae ipe ee code Ta EE ERE CY VELIE DER 7 35 C SUE STAINS aurato tp rettet p a Dro ER o S frc dte eet 7 38 C Subprogram Example 522 siste er enero edet ost sebo den sepu RE 7 39 Eis qnd ATT AY Seso serieei e E eso task ie baka gate UD Erin de eod dpi p aU 7 41 BIETLPEOBIGHIS eio oh at EE tt DN capa Satna eee e bcd quits 7 43 D b gsging Tr cia oed eti etie tie nae t emt ROO etl qe p dene 7 44 Other Examples qc stt o bates icto eut nar eerie a bl ead foedo 7 48 Summa METER E D ELT DO e den chg sates 7 49 Lab 7 ELI Bug imm C 606 s ire ke PERDER ERE e HP SEED Cun 7 50 Module 8 DDG USN ooo T i soei 8 1 M d l hive ata oa eee meer dettes tute huit uod aren ren d ete d tof bod wen 8 2 Whemto Debut lc 8 3 IB IIIA e 8 4 Breakpolnis 2 n Se ret ub i eoe Doha eaa a a A b OPERA eta ecce 8 5 Checkpoint and Restore icone ret ovmeterete te ere e ma tortue re Du eadera nre sands 8 6 lodo M S 8 7 Toggle and Stability Checking zu oae Pts pbi teo hr Taba tend d 8 8 Merea ON oh Goo eem odere dena ustedes Dni cet dies tes canines teed os bend 8 9 Unknown States See Module 1 redisse retina that eed aa La eh
21. 9 6 ModelSim Advanced Debugging December 2002 Debug Detective Debug Detective Functions Debug Detective Functions vu address_decode on address decode on clock divider e 3KB MTI vhdl 3KB Graphical generation of design levels further aids lock divider flo i M e A eaa Source files amp understanding of code e ZT Gp UART C hds2001_Sa examples Hierarchy ui control_operal G 9 adaress decode e Block diagram vi cpu interface a V clock divider i ra va cpu interface E H control operation e l BD HQ epu interface M serial interface M status registers on cpu interface us serial interfaci e State machine 3 an X tester us serial interfac H a uat tb e Flow chart vu status registet BE symbol sb Ee D struct bd on status registei Single level or hierarchical IET sue Block Diagram i e Compact rendering E e Improved Place amp Route BS 11 UART uart top struct bd fH 12 UART clock divider flow sporene Instance Ref Port Map 9 6 ModelSim Advanced Debugging Debug Detective Overview Copyright 2002 Mentor Graphics Corporation Notes This page displays examples of the graphical design aids that are available with Debug Detective Some of these windows and menus may only be ava
22. Compile Selected Click on the Library tab expand the work library and notice the top level entity name is top std Load top std into the simulator with code coverage enabled by typing ModelSim vsim coverage top std Enable the profiler by typing VSIM profile on Run the simulation for 16 ms by typing 4 38 ModelSim Advanced Debugging December 2002 Analyzing Performance VSIM gt time run 16 ms When the simulation is finished the number of microseconds it took to run will be printed in the transcript window Record the number of seconds it took below move the decimal point 6 places to get the number of seconds Decoder run time for Case implementation using stdlogic types with code coverage View the code coverage results by typing VSIM gt view_coverage The Coverage Summary window reports 86 executable lines in decoder case stdlogic vhd with 86 hits executable lines touched during the simulation which equates to 100 code coverage Click on the decoder case stdlogic vhd pathname to display the decoder case stdlogic vhd file in the Source window Notice the number of hits for each executable line of code shown along the left most column in the Source window Export the code coverage results to an ASCII file by typing VSIM coverage report file dec case coverage txt lines View this file with notepad by typing VSIM notepad dec case coverage txt View the profile re
23. ME tal Run Ti 0 Minutes 6 S d nab d un finn ni i fing_inst ringbuf t do C TL_TEMP TLTemp tutorial profiertin AS the simulation runs notice that the arcae Status Bar will show how many samples are taken Sek Halic xm Waveform Compare gt E test_ringbuf test_ringbulf tes f_ Profle quc esci U ring inst ringbuf rtl Source Coverage Profile On BM Package textio Breakpoints Profile Off p Package std logic unsigned hierarchic al profile h 1 View ranked profile z Tcl Debugger Clear Profile Data You can access the sim DEDE ES hierarchical or ranked profile profile Now 90ms D Options simzstd toc Buil 4 information through the menu Edit Preferences Execute Macro Save Preferences 4 12 ModelSim Advanced Debugging Analyzing Performance Copyright 2002 Mentor Graphics Corporation Notes ModelSim Advanced Debugging 4 13 December 2002 Analyzing Performance Graphical Views Graphical Views Ranked Output Samples 870 d a In i o g F mentor training lab1 arith src unsigndb vhd 54 11 E Hierarchical Output F mentor training lab1 arith src unsigndb vhd 183 7 7 F mentor_training lab1 arith_ste unsigndb vhd 216 6 6 Hierarchical Profile Imi xi store array vhd 39 Te 5 m F mentor_training lab1 testring vhd 99 5 B Samples 870 d al Under 2 v x F mentor_training lab1 control
24. MTI would still require a copy of the VHDL verilog part of the design to actually execute a replay but many problems can be resolved with the trace only ModelSim Advanced Debugging 7 47 December 2002 FLI and C Models Other Examples Other Examples Other examples are located in the ModelSim installation directory MODELSIM_HOME modeltech examples foreign e Example 1 FLI test example is to illustrate how to create processes and sensitize them to signals and how to read and drive signals from these processes e Example 2 FLI test example is to illustrate traversal of the design hierarchy creation of a simple gate function creation and sensitization of a process and loading of multiple foreign shared libraries e Example 3 FLI test example is to illustrate how to read a test vector file and use it to stimulate and test a design via FLI function calls e Example 4 FLI test example is to illustrate how to create and use foreign subprograms 7 31 ModelSim Advanced Debugging FLI and C Models Copyright 2002 Mentor Graphics Corporation Notes otes 7 48 ModelSim Advanced Debugging December 2002 FLI and C Models Summary Summary This module introduced and explored the application of the following topics The Foreign Language Interface FLI Benefits of C Interface FLIC Functions Callbacks Hierarchy Scanning Signals and Variables Utilities Foreign Architecture Init Mapping of Da
25. ModelViewer ModelViewerPlus MODGEN Monet Mslab Msview MS Analyzer MS Architect MS Express MSIMON MTPI SM Nanokernel amp NetCheck NETED Online Knowledge Center SM OpenDoor SM Opsim OutNet P amp RIntegrator PACKAGE PARADE ParallelRoute Autocells ParallelRoute MicroRoute PathLink Parts SpeciaList PCB Gen PCB Generator PCB IGES PCB Mechanical Interface PDLSim Personal Learning Program Physical Cable Physical Test Manager SITE PLA Lcompiler Platform Express PLDSynthesis PLDSynthesis II Power Analyst PowerAnalyst Station Power To Create Precision Precision Synthesis Precision HLS Precision PNR Precision PTC Pre Silicon ProjectXpert ProtoBoard ProtoView QNet QualityIBIS QuickCheck QuickConnect QuickFault QuickGrade QuickHDL QuickHDL Express QuickHDL Pro QuickPart Builder QuickPart Tables QuickParts QuickPath QuickSim QuickSimII QuickStart QuickUse Quick VHDL RAM Lcompiler RC Delay RC Reduction RapidExpert REAL Time Solutions Registrar Reinstatement 2000 SM Reliability Advisor Reliability Manager REMEDI Renoir RF Architect RF Gateway RISE ROM Lcompiler RTL X Press Satellite PCB Station ScalableModels Scaleable Verification SCAP Scan Sequential
26. Review ModelSim Windows Dataflow Window Chase X Dataflow Window Chase X Jump to the Source of an unknown X value Trace gt ChaseX inix File Edit View Navigate Trace Tools Window SiR iim TAL ow HHH AMAIA QQ Bo ni ZNAND 24 NAND 22 stb w NAND 23 test test 1 test2 test Rx EL test in aa S N The unknown on this signal can be traced back to the high impedance on fest in L Extended mode enabled Keep 1 top pitest2 P 1 15 ModelSim Advanced Debugging ModelSim Windows Copyright 2002 Mentor Graphics Corporation Notes A useful debugging tool is locating the source of an unknown X Unknown values are most clearly seen in the Wave window the waveform is red when a value is unknown The steps for tracing an unknown is as follows 1 Load your design 2 Log all signals in the design or any signals that may possibly contribute to the unknown value log r will log all signals in the design 1 24 ModelSim Advanced Debugging December 2002 Review ModelSim Windows 3 Add signals to the Wave window or wave viewer pane and run the design for the desired length of time 4 Place a cursor on the time at which the signal value is unknown 5 Add the signal of interest to the Dataflow window making sure the signal is selected 6 Select Trace gt Trace X or Trace gt Chase X These two commands behave as follows Trace gt Trace X Steps back to t
27. Tcl_Interp interp int argc char argv A command can be added with the same name as a previously added command or even a standard simulator command but only the command added last has any effect If a command is read or deleted the delete callback function is called along with the command parameter so that the old command information can be cleaned up The delete function prototype is void deleteCBname ClientData cmd_param mti_Break requests the simulator to halt Issues an assertion message that says Simulation halt requested by foreign interface The break request is satisfied after the foreign code returns control to the simulator Simulation can be continued by the user after it has been halted by the mti Break command Cannot be called during elaboration mti CreateArrayType creates a new ID type that describes a VHDL array whose bounds are the specified left and right values and whose elements are of the specified element type 7 20 ModelSim Advanced Debugging December 2002 FLI and C Models mti CreateEnumType creates an enumeration type Consists of the specified enumeration literals and its values and are of the specified size The count parameter indicates the number of strings in the literals parameter The left most value of the enumeration type is 0 and is associated with the first literal string the next value is 1 and is associated with the next literal string and so on If more than 256 v
28. The function specified in the foreign attribute is called during elaboration The first parameter is a region ID that can be used to determine the location in the design for this instance The second parameter is the last part of the string in the foreign attribute The third parameter is a linked list of the generic values for this instance The list will be NULL if there are no generics The last parameter is a linked list of the ports for this instance The typedef mtiInterfaceListT in mti h describes the entries in these lists 7 26 ModelSim Advanced Debugging December 2002 FLI and C Models Mapping Data Types Mapping Data Types Many FLI functions have parameters and return values that represent VHDL object values Object values are mapped to the various VHDL data types by a typelD handle identified in the C interface Fora given typelD handle mti GetTypeKind returns a C enumeration of mtiTypeKindT The mapping between mtiTypeKindT values and VHDL data types is as follows mtiTypeKindT value VHDL data type MTI TYPE ACCESS Access type pointer MTI TYPE ARRAY Array composite type MTI TYPE ENUM Enumeration scalar type MTI TYPE FILE File type MTI TYPE REAL Floating point scalar type MTI TYPE RECORD Record composite type MTI TYPE SCALAR Integer amp physical scalar types MTI TYPE TIME Time type 7 14 ModelSim Advanced Debugging FLI and C Models Copyright 2002 Mentor Graphics Corporation Notes
29. The simulator gets stuck evaluating signals over and over without advancing time Each evaluation of a zero delay event will generate one iteration in the simulator In this case the default iteration limit of 5000 iterations was reached Now we will have to find where the problem is and fix it To find the problem first open the source window and then bump up the iteration limit so we can single step past the problem Click on Simulate gt Simulate Options Defaults and change the iteration limit to 5020 The extra 20 iterations should allow us to run just a little further 4 Now go to the source window and click on the step icon The next line to execute should be line 36 or 37 Step a few more times and you ll see the simulator gets stuck on those two lines Notice there is no delay on the and gate or the inverter You can also open the dataflow window at this point It ModelSim Advanced Debugging 8 29 December 2002 Debugging 8 30 will graphically show you what is going on If you double click on the output signal of the and gate in the dataflow window you ll see that it is connected to the input of the or gate You can keep clicking on the outputs and the dataflow window will keep going in circles You have found the loop Bi source Aces Counter error vhd loj x File Edit Object Options Debug Window Gub 2800 O07 G END IF END IF END PROCESS Counter a and b not cs
30. You can start or stop the simulation and save information throughout your simulation from the graphical representations You can then replay and animate the state diagrams and flow ModelSim Advanced Debugging 9 3 December 2002 Debug Detective charts to view transitions The states and transitions will change color as you step through the simulation The block diagrams will also show change in signal values as different colors The graphical representation and animation capabilities of Debug Detective provide considerable debugging value 9 4 ModelSim Advanced Debugging December 2002 Debug Detective Debug Detective Option for ModelSim Debug Detective Option for ModelSim Focused on graphical debug of text based designs Available as snap on option to ModelSim e No impact on designer s existing design flow e No save print export etc Also available with HDL Detective and HDL Designer Series Compliments ModelSim dataflow window Rapid on the fly graphical rendering for debug purposes e Block Diagram Instances amp Processes e Interface Based Design IBD e State Machine e Flow Chart Simulation cross probing cross referencing Animation 9 4 ModelSim Advanced Debugging Debug Detective Overview Copyright 2002 Mentor Graphics Corporation Notes There are four different representations Block Diagrams Interface Base Design State machines and Flow charts Simulation cross probing is availabl
31. and Compare Searching for item values in the Wave window Select an item in the Wave window and then select Edit gt Search to bring up the Wave Signal Search dialog box The Wave Signal Search dialog box allows you to search by the following criteria e Search Type Any Transition Search Type Rising Edge e Search Type Falling Edge e Search Type Search for Signal Value e Search Type Search for Expression Search Options Match Count Note If your signal values are displayed in binary radix see Searching for binary signal value s in the GUI CR 21 for details on how signal values are mapped between a binary radix and std logic Using time cursors in the Wave window When the Wave window is first drawn there is one cursor located at time zero Clicking anywhere in the waveform display brings that cursor to the mouse location You can add cursors to the waveform pane by selecting Insert gt Cursor or by clicking on the Add Cursor button The selected cursor is drawn as a bold solid line all other cursors are drawn with thin dashed lines Remove cursors by selecting them and selecting Edit gt Delete Cursor 1 30 ModelSim Advanced Debugging December 2002 Review ModelSim Windows You can choose a specific cursor by selecting View gt Cursors or by clicking a value in the cursor value pane Making cursor measurements Each cursor is displayed with a time box showing the precise simulation time at the bott
32. and read and drive signal values Used much in the way VHDL is used but with the advantage of C with its ease of reading writing files and communicating with other system functions Foreign Subprogram A foreign subprogram is a VHDL function or procedure that is implemented in C as opposed to VHDL A foreign subprogram reads its in and inout parameters performs some operation s which may include accessing simulator information through FLI function calls writes its inout and out parameters and returns a value function Callback A callback is a C function that is registered with the simulator for a specific reason The registered function is called whenever the reason occurs Callback functions generally perform special processing whenever certain simulation conditions occur Process A process is a VHDL process that is created through the FLI It can either be scheduled for a specific time or be made sensitive to one or more signals that trigger the process to run The process associated with a C function is executed whenever the process is run by the simulator 7 4 ModelSim Advanced Debugging December 2002 FLI and C Models Why FLI Why FLI Ability to integrate models developed in C C into VHDL design e FLI C libraries now supported e Why Use A C C model is available from a Silicon vendor who does not want to give out synthesizable code e Ability to use the power of C C to accomplish tasks th
33. from the pop up menu Click on Auto Generate to resolve all file dependencies and compile the files Click OK twice to return to the ModelSim Main window Load the top design unit into the simulator by expanding the work library view in the Library tab use the left mouse button LMB and double click on the top entity View all windows Type view or select View gt All Windows from the pulldown menu We are going to use the Dataflow window to trace back an unknown We will need to log the signals in this design to provide the information for debugging At the VSIM prompt type add log r You may not want to do this logging when running regression tests as the number of signals you log may impact performance Instead you may want to log only a specific hierarchy of the design For example log r top p logs only the proc instance p module in this example Drag and drop top from the Main window sim tab to the Wave window Select the Verilog module proc in the Main window sim tab The signals for the proc module are now in the Signals window From the Signals window drag and drop the signal out to the Wave window In the Main window type run all or use the run all icon from the Main or Wave window toolbar Zoom the Wave window full use the Zoom Full toolbar icon Look at t out it should go to an unknown state early in the simulation How do you find the root caus
34. or vl vector The vector type will be constrained accordingly if the range does not depend on parameters otherwise it is unconstrained 3 8 ModelSim Advanced Debugging December 2002 Test Benches Setting VHDL Generic Parameters Setting VHDL Generic Parameters VHDL Source code example with generics ENTITY DFF_test IS e Generic names GENERIC oo treg trsu trh trpr dai s e Datatypes treg TIME string time trsu TIME e Values trh TIME ns trpr TIME ModelSim LEE 3 e Specify generic values e Override existing generic values q END DFF test 3 9 ModelSim Advanced Debugging Test Benches Notes ModelSim Advanced Debugging December 2002 STRING 1 ns ns ns ns ns IN std logic IN std logic IN std logic IN std logic OUT std logic 0 Copyright 2002 Mentor Graphics Corporation 3 9 Test Benches Setting VHDL Generic Parameters Cont Setting VHDL Generic Parameters Cont vsim g lt Name gt lt Value gt e Assigns a value to generics that have not received explicit values in generic maps or instantiations e Name generic name as it appears in the VHDL source e Value appropriate value and data type of a VHDL generic vsim g top u1 tpd 20ns tpd generic on the top u1 instance assigned a value of 20 ns vsim gu1 tpd 20ns tpd generic on all instances named u1 vsim gtpd 20ns Affects all gene
35. set PrefCompare defaultVHDLXMatches XU dataset open 0 wlf gold dataset open 5 wlf test quietly WaveActivateNextPane 0 add wave noupdate divider Golden Simulation Results add wave radix hex r gold quietly WaveActivateNextPane add wave noupdate divider Test Simulation Results add wave radix hex r test quietly WaveActivateNextPane add wave noupdate divider Compare data if reset inactive compare start gold test 4 test delayed when condition compare if reset is inactive 20ns before and data change compare add tolL 3 ns tolT 2 ns label reset inactive 20nsbefore gold tst pseudo chip data when 4 200 reset 1 Compare data only when reset equal 1 compare if reset inactive 200 time units before data change compare add tolL 3 ns tolT 2 ns label reset inactive gold tst pse chip data when reset M compare run Compare data only when reset equal 1 compare info compare info primaryonly compare info secondaryonly Test dataset signal path optional if same as the reference path 6 22 ModelSim Advanced Debugging Waveform Compare Copyright 2002 Mentor Graphics Corporation Notes tolL specifies the maximum time the test signal edge is allowed to lead the reference edge in an asynchronous comparison The default is 0 tolT specifies the maximum time the test signal edge is allowed to trail the reference edge in an asynchronous comparison The default is 0 primar
36. us sequencer vhd c testbench error c Compile Testbench io error un Testbench use io winner calc vhd Ix AUCI Dealer vhd FSM Control vhd un Loader vhd un winner calc vhd luu sequencer vhd ivy Black Jack vhd luu Game n vhd uu Testbench io error vhd us Testbench use io vhd ModelSim Advanced Debugging 7 51 December 2002 FLI and C Models 3 Compile the C file testbench error c after compiling the VHDL files Solaris Note You may also compile the C file by executing compile_c_error_sol at the unix shell prompt gcc c ISMTI HOME include Source error testbench error c ld G o tbio error sl testbench error o HP Note You may also compile the C file by executing compile c error hpu at the unix shell prompt gcc c fpic IS MTI HOME include cont next line Source error testbench error c ld b o tbio error sl testbench error o Windows Compile amp link testbench error c with the following commands from the DOS command prompt cd labs lab7 blackjack cl c ISMTI_HOME include SourceNerrorNtestbench error c link dll export init tbio testbench error obj cont next line SMTI_HOME S win32 mtipli lib out tbio error sl 4 Load the simulation click on the sign in front of the work library in the Library tab of the Main window Double click on the testbench entity in the Libra
37. vhd 87 19 4 Nae OOO O O F mentor_training lab1 testring vhd 97 3 3 E F mentor training lab1 control vhd 87 Balle relig decal control vhd S8 10 3 F mentor training lab1 arith_src unsigndb vhd 64 oe 6 3 F mentor_training lab1 arith_sre unsigndb vhd 65 F mentor training lab1 arith_ste unsigndb vhd 58 2 2 LE mentor_training lab1 arith_stc unsigndb vhd 58 F mentor_training lab1 arith_sre unsigndb vhd 222 E 2 tore_array vhd 39 F mentor_training lab1 control vhd 130 2 2 F mentor_training lab1 arith_stc unsigndb vhd 216 F mentor_training lab1 arith_ste unsigndb vhd 223 2 2 F mentor training lab1 arith_ste unsigndb vhd 65 2 2 F mentor_training labl arith_ste unsigndb vhd 189 retrieve array vhd 35 F mentor_training lab1 arith_ste unsigndb vhd 216 170 F mentor_training lab1 testring vhd 99 sorted by in y o F mentor training lab1 testring vhd 97 F mentor training lab1 control vhd 130 Options gt Edit Preferences Pref k ffHighligh Set PrefCoverage rankCutoffHighlight 5 sorted by under 4 13 ModelSim Advanced Debugging Analyzing Performance Copyright 2002 Mentor Graphics Corporation Notes There are two report windows that display the results of the profile The first is the ranked view This displays the lines of code in a league table the line taking most of the simulation time at the top down to the line that takes the least amount of simulation time This table is
38. 17 ModelSim Advanced Debugging Waveform Compare Copyright 2002 Mentor Graphics Corporation Notes If signals in the RTL test design are different in type from the synthesized signals in the reference design registers vs nets for example the Waveform Comparison feature will automatically do the type conversion for you If type differences are too extreme e g integer vs real Waveform Comparison will inform you ModelSim Advanced Debugging 6 17 December 2002 Waveform Compare Using Tcl Commands to Define a Comparison Using Tcl Commands to Define a Comparison dataset open gold wlf Open dataset gold wif gold dataset open test wlf lt Open dataset test wif test compare start gold test Start comparison between gold and test specify signals to compare and how to compare them compare run Run the comparison compare end lt End the comparison 6 18 ModelSim Advanced Debugging Waveform Compare Copyright 2002 Mentor Graphics Corporation Notes 6 18 ModelSim Advanced Debugging December 2002 Waveform Compare Tcl Compare Command compare compare compare compare compare compare compare compare compare compare compare compare compare compare compare compare compare compare compare Tcl Compare Command add lt arguments gt annotate lt arguments gt clock lt arguments gt configure lt arguments gt continue delete recursive lt objec
39. 5 10 Virtual Types m PR 5 14 Combining 51 ONG 16555 eso rop rz Rt es Pesca iaer eea OUR ares Rura poA ERR D esie 5 15 SUMMA Yc TT Ee 5 16 Module 6 Waveform C OImipargauiiiieiieeiebsens Geeakasue ede auku eda dee Ds bnc eR ae areas uio n oi deu MERE ana Nga aa IE aan 6 1 Module CV GRVICW sro bay a tasuticd metu es abite tivi di petu e balipede hs tbid 6 2 Saving Waveform Datasets oett ise EL UR ER EHE Ev vc ep ui tke ovds 6 3 Opening Datasets cecs cod Crpeee dose ton Mb destn a cA e ba loda ua duse ads 6 4 Mahdbing TI ALAS CUS she ao eoi se verte cag rrt asses Gan Eee iu eai E t o aia vido 6 5 x ModelSim Advanced Debugging December 2002 Table of Contents TABLE OF CONTENTS Cont Compare Datasets Using Waveform Compare sse 6 6 Waveform Compar WIZdEG oett dados ri SUI Poveda Pru FUE n dead io a oxi 6 8 Waveform Compare Menus 45 565 eda aerial tetas but tees 6 10 Waveform Compare Dialog BOXES c nores ch ox th NE yere raga depu 6 11 Add Signals Regions orc loe scio eoe ode I P etes rs neben i ee ages 6 12 Difference Sinnai rite ENS nv isis OAM LN MR LE EUM E 6 13 Compare Objects in the List Window sssssssesessessesssseesssesesssresssrrresssrsssssreesse 6 14 Continuous vs Clocked Comparison sese 6 15 Mite Report menassa susan A T nea d sian dal auct EE 6 16 Comparing Hierarchical and Flattened Designs esses 6 17 Using Tcl Commands to Define a Comparison
40. Choose View All in the ModelSim Main window This will bring all the ModelSim windows to the foreground Close the List window since it blocks the Wave window Drag and Drop the total value signal in the waveform window into the DataFlow window This will display the signal driver in the Dataflow window Double click on the total value input signal in the out convert block in the Dataflow window This will display the prO process Double click the total card value input to the prO process and then single click on the counter process in the Dataflow window This will display the Accumulator error vhd file and point to the counter process This is the process that sets the total value value On line 31 you can see that total value is incremented by 20 instead of 10 Use the Edit menu in the Source window to uncheck Read Only Change the 20 to 10 and save the file Re compile the accumulator vhd file using the compile button Select Simulate gt Run Restart or type res in the ModelSim Main window clicking Restart will save all settings Run the design for 50 us Hint type ru and verify a value of 10 is now added to the total value signal when the jack of hearts is dealt around 44 us ModelSim Advanced Debugging 8 31 December 2002 Debugging 10 Type quit sim to end the simulation PART 3 Simulation of Gate Level Netlist A powerful feature and often error prone task
41. Debug Window Help Specify reference dataset name tst pseudo tst pseudo chip pseudo Source Coverage Bun Comparer clock_ibuf Xx CKBUF Breakpoints End Compar I Comparison Wizard Jo xl oats eno Execute Macro Add TEE oe uk reference Reference Dataset clock PAD X_IPAD _____ and test datasets wlf files Sclock CLKINMUP X Tel Debugger Options Either dataset can be a saved wlf file EILINULDIEDTUUED Bene Sdata PADN X DPAD IclPro Debugger Differences 9 2 dataset that is already opened Test Dataset gt Rules Use the Browse buttons to browse Sa Options Relo d a saved dataset or click the dg f Wien E Project Library sim Edit Preferences eload arrow to select a file from the dataset x gosse I Update comparison after each run C Specify Dataset i Downloads waveforn lab_datavtest2wit org Project wavecomp Now 10 a Save Piteences ag T M Compare Wizard Use current sim or test dataset cepere acc Walks you through all the steps to do a compare 6 8 ModelSim Advanced Debugging Waveform Compare Copyright 2002 Mentor Graphics Corporation Notes 6 8 ModelSim Advanced Debugging December 2002 Waveform Compare Waveform Compare Wizard Cont Waveform Compare Wizard Cont i Comparison Wizard With the reference and tes
42. FORMA FormalPro FPGA Advantage FPGAdvisor FPGA BoardLink FPGA Builder FPGASim FPGA Station FrameConnect Galileo Gate Station GateGraph GatePlace GateRoute GDT GDT Core GDT Designer GDT Developer GENIE GenWare Geom Genie HDL2Graphics HDL Architect HDL Architect Station HDL Author HDL Designer HDL Designer Series HDL Detective HDL Inventor HDL Pilot HDL Processor HDL Sim HDLWrite Hardware Modeling Library HIC rules Hierarchical Injection Hierarchy Injection HotPlot Hybrid Designer Hybrid Station IC Design Station IC Designer IC Layout Station IC Station ICbasic ICblocks ICcheck ICcompact ICdevice ICextract ICGen ICgraph ICLink IClister ICplan ICRT Controller Lcompiler ICrules ICtrace ICverify ICview ICX ICX Active ICX Custom Model ICX Custom Modeling ICX Plan ICX Pro ICX Project Modeling ICX Sentry ICX Standard Library ICX Verify ICX Vision IDEA Series Idea Station INFORM IFX Inexia Integrated Product Development Integra Station Integration Tool Kit INTELLITEST Interactive Layout Interconnect Table Interface Based Design IBD IntraStep SM Inventra InventraIPX Inventra Soft Cores IP Engine IP Evaluation Kit IP Factory IP PCB
43. On and Off Clear Profile Results Enable Profiler and View Results Interpret Profile Results Fields Interpret Ranked and Hierarchical Results Differences Coding For Performance RTL Optimization Gate Level Optimization vlog commands vcom commands Other Performance Tips 4 2 ModelSim Advanced Debugging Analyzing Performance Copyright 2002 Mentor Graphics Corporation Notes ModelSim Advanced Debugging December 2002 Analyzing Performance Challenges Challenges What s holding back the performance of your simulation environment e the design data types the test bench coding styles un necessary code 4 3 ModelSim Advanced Debugging Analyzing Performance Notes ModelSim Advanced Debugging December 2002 Copyright 2002 Mentor Graphics Corporation 4 3 Analyzing Performance Code Coverage Integrated Line Coverage Code Coverage Integrated Line Coverage Tightly integrated with ModelSim e No Learning another Tool e No instrumented code e Approx 3 performance impact e Use By ALL designers Line Coverage Can Give e Statement Coverage e Branch Coverage e Limited State Coverage Line Coverage Enough For The Majority e 3rd Party Tool Used For Detailed Analyst 4 4 ModelSim Advanced Debugging Analyzing Performance Copyright 2002 Mentor Graphics Corporation Notes 4 4 ModelSim Advanced Debugging December 2002 Analyzing Performance Ve
44. RTL level design with an asynchronous feedback loop with no delays e Event ordering in Verilog e Long string assignments VHDL a1 lt a0 a2 lt a1 a500 lt a499 e Processes without wait statements or sensitivity lists a lt not b b lt not a 8 14 ModelSim Advanced Debugging Debugging Copyright 2002 Mentor Graphics Corporation Notes 8 14 ModelSim Advanced Debugging December 2002 Debugging Mixed Language Issues Mixed Language Issues ModelSim offers the capability to do mixed language simulation e Mixture of VHDL amp Verilog design files testbenches and libraries Hierarchical access e Cannot directly read or change a VHDL signal variable or generic with a hierarchical reference within a mixed language design e Cannot directly access a Verilog object in the hierarchy if there is an interceding VHDL block e Two options Propagate the value through the ports of all design units in the hierarchy Use the Signal Spy function init signal spy if referencing within a Verilog module init signal spy if referencing within a VHDL module Verilog identifiers e Use the vcom or vlog 93 switch if names are unique by case only 8 15 ModelSim Advanced Debugging Debugging Copyright 2002 Mentor Graphics Corporation Notes ModelSim Advanced Debugging 8 15 December 2002 Debugging Mixed Language Issues Cont Mixed Language Issues Cont Compiling mixed designs w
45. Simulator Restarting the Simulator Animating State Diagrams 9 2 e ModelSim Advanced Debugging Debug Detective Overview Copyright 2002 Mentor Graphics Corporation Notes Debug Detective is an add on product to ModelSim If you are interested in getting Debug Detective please contact your sales representative ModelSim Advanced Debugging December 2002 Debug Detective Design Analysis Design Analysis VHDL Verilog amp Mixed language capabilities Code comprehension for Re use and Review e Design Navigation e Design Visualization Design Documentation e Creation e Maintenance Design Debug e Graphical rendering e Simulation control amp cross probing e Animation 9 3 ModelSim Advanced Debugging Debug Detective Overview Copyright 2002 Mentor Graphics Corporation Notes These capabilities exist to assist you in identifying the areas of the design that you want to take a closer look at The graphical representation is important because it is easier to comprehend relationships of objects It is much easier than understanding relationships based on a textual representation What the Debug Detective capabilities provide is a way to render the graphics so that you see the relationships graphically Graphical analysis includes generating graphical representations of your text based designs controlling the simulation from these graphical representations and animating state diagrams and flow charts
46. The name can be either a full hierarchical name or a relative name A relative name is relative to the current regions set by the simulator s environment command The default current region is the top level region For objects declared in a process the name must include the process label The function can be called only after elaboration is complete and cannot be used to find composite sub elements For example the name cannot be a subscripted array element or a selected record field Also it cannot be used to find a process variable when it is called from a foreign subprogram that is called from the process where the variable is declared mti_GetSignalName gets the simple name of a scalar or top level composite VHDL signal If the signal is a composite sub element then the name returned is the name of the top level composite The returned pointer must not be freed To get the name of a composite sub element signal use mti GetSignalNamelndirect mti GetVarName gets the simple name of a VHDL variable Returns NULL if no information is found The return pointer must not be freed This function cannot be used with variable Ids passed as foreign sub program parameters ModelSim Advanced Debugging 7 17 December 2002 FLI and C Models mti_SetSignalValue sets the value of a VHDL signal Effect takes place immediately The signal can be either an unresolved signal or a resolved signal Setting a signal marks it as active in the current del
47. The typeID handle e Can be obtained for a signal by calling mti GetSignalType e Can be obtained for a variable by calling mti GetVarType VHDL data types are identified in the C interface by a type ID A type ID can be obtained for a signal by calling mti GetSignalType and for a variable by calling mti GetVarTyper ModelSim Advanced Debugging 7 27 December 2002 FLI and C Models Alternatively the mti_CreateScalarType mti_RealType mti_CreateTimeType mti_CreateEnumType and mti_CreateArrayType functions return type IDs for the data types they create Object values for access and file types are not supported by the C interface Values for record types are supported at the non record sub element level Effectively this leaves scalar types and arrays of scalar types as valid types for C interface object values In addition multi dimensional arrays are accessed in the same manner as arrays of arrays Scalar and physical types use 4 bytes of memory TIME and REAL types use 8 bytes An enumeration type uses either 1 or 4 bytes depending on how many values are in the enumeration If it has 256 or fewer values then it uses 1 byte otherwise it uses 4 bytes In some cases all scalar types are cast to long before being passes as a non array scalar object value of any non array scalar signal except TIME and REAL types which can be retrieved using mti GetSignalValue Use mti GetVarValue and mti GetVarValueIndirect fo
48. VHDL and Verilog Identifiers VHDL identifiers for component name port names and generic names are the same as the Verilog identifiers for the module name port names and parameter names If the Verilog identifier is not a valid VHDL 1076 1987 identifier it is converted to a VHDL 1076 1993 extended identifier e Compile with the 93 switch Upper case letters in Verilog identifiers are converted to lowercase in the VHDL identifier except for the following e The Verilog module was compiles with the 93 switch vgencomp should use VHDL 1076 1993 extended identifiers in the component declaration to preserve case in Verilog identifiers that contain uppercase letters e The Verilog module port or parameter names are not unique unless case is preserved vgencomp behaves as if the module was compiled with the 93 switch for those names only 3 8 ModelSim Advanced Debugging Test Benches Copyright 2002 Mentor Graphics Corporation Notes Generic clause A generic clause is generated if the module has parameters A corresponding generic is defined for each parameter that has an initial value that does not depend on any other parameters Port clause A port clause is generated if the module has ports A corresponding VHDL port is defined for each named Verilog port You can set the VHDL port type to bit std logic or vl logic If the Verilog port has a range then the VHDL port type is bit vector std logic vector
49. allows the creation of conditional breakpoints 9 20 ModelSim Advanced Debugging December 2002 Debug Detective Animation Menu and Toolbar Animation Menu and Toolbar File Edit View Diagram Simulation Animation Window Help IEE th 9 JO A f v Move By States Move By Events Ia Ea Goto Next State Ctrl Shift gt Goto Previous State Ctrl Shift lt Goto Time Goto Start Data Capture Global Data Capture applies to Global Capture On all instances in the current Sea ee simulation hierarchy E v Show Animation Global Capture options not in the toolbar Activity Trails tem 4 Clear Captured Events 9 17 ModelSim Advanced Debugging Debug Detective Overview Copyright 2002 Mentor Graphics Corporation aj Link Diagrams N BE t amp P Oo A a 7 ER gt gt bo p M M dE ta oo d Determines whetherresults are recorded for animation Animation T aols Notes Animation is a way to graphically represent the sequences of events through the data flow and state diagrams The objects in those diagrams will change colors to show if they are active or if they have been executed There are a variety of pull down menu options and control buttons First you need to capture a set of simulation results and then run the animation as a post process activity Animation can be controlled with the animation t
50. based on the In column The In column is the amount of time spent on or in that particular line of code or function The hierarchical view displays the break down of each of the lines of code hierarchy A line of code may have functions or procedures that is called these functions and procedures along with the line itself make up the amount of time that is spent under a line of code The hierarchical view is sorted in a league table based on the under percentage The highest to the lowest The lines that take more than 5 of the simulation time are displayed in red The value that is used for this is the in percentage The display value limit can be changed using the options preferences 4 14 ModelSim Advanced Debugging December 2002 Analyzing Performance Understanding In and Under Understanding In and Under Name SUnder In decodera_body wvhd 502 9 4 p_out lt new_state AFTER G lys new_val es function 576 Percentage In 4 Percentage Under 9 4 14 ModelSim Advanced Debugging Analyzing Performance Copyright 2002 Mentor Graphics Corporation Notes Above we can see a single line of VHDL code The line is a concurrent signal assignment that has a time delay controlled by a function This can be used to describe the differences between the under and in percentage The in percentage reports the amount on time that has been spent in or on the line In this case 4 of the simulation time has been sp
51. calling block to a VHDL signal or Verilog register wire Use the path separator to which your simulation is set i e or The path must be contained within double quotes destination Required A full hierarchical path or relative path with reference to the calling block to a Verilog register Use the path separator to which your simulation is set 1 e or A full hierarchical path must begin with a or The path must be contained within double quotes verbose integer Optional Possible values are 1 or 0 Specifies whether a message is reported in the transcript stating that the source is driving the destination Default is 0 no message Returns Nothing ModelSim Advanced Debugging 3 29 December 2002 Test Benches Limitations When depositing the value of a Verilog register wire onto a VHDL signal the VHDL signal must be of type bit bit vector std logic or std logic vector Referencing slices or single bits of a vector is not supported If you do reference a slice or bit of a vector the function will assume that you are referencing the entire vector Example Library modelsim_lib Use modelsim_lib util all entitiy top is end archicture signal top_sigl std_logic begin spy_process process begin init signal spy top uut instl sigl top sig1 1 wait end process spy process end Directions VHDL on top Lab Exercise 1 Change the directory to t
52. close button fixed tcl if you need help creating the procedure The file is located in the labs lab2 cordic core directory The finished procedure is included in this file Once you have finished creating the button procedure you will notice the appearance of a button called Open in the lower right hand corner of the ModelSim window Try clicking the button several times and see what happens ModelSim Advanced Debugging December 2002 Tcl Tk Overview uJ ModelSim SE PLUS 5 6a File Edit View Compile Simulate Tools Window Help a_56 Labs lab3 cordic_core open_close_button t E cl line 36 invalid command name add button while executing add button 0 do C A amp dvanced ModelSim Lab data 55 Labs la b3 cordic core open close button fixed tcl MadelSim E lt No Design Loaded gt When you have finished you may quit ModelSim ModelSim Advanced Debugging 2 31 December 2002 Tcl Tk Overview 2 32 ModelSim Advanced Debugging December 2002 Module 3 Test Benches Objectives Upon completion of this module you will be able to e List the functions of test benches e Describe each of the functions of test benches e List the different test bench implementations Describe features benefits and trade offs of each test bench implementation ModelSim Advanced Debugging 3 1 December 2002 Test Benches Module Overview Module Overview In this module we will dis
53. compatible across platforms This means the simulator can load your design on any supported platform without having to recompile first Though this architecture offers a benefit it also comes with a possible detriment the simulator has to generate platform specific code every time you load your design This impacts the speed with which the design is loaded In many cases design loading time is not that important For example if you re doing iterative design where you simulate the design modify the source recompile and resimulate the load time is just a small part of the overall flow However if your design is locked down and only the test vectors are modified between runs loading time may materially impact overall simulation time particularly for large designs loading SDF files 1 Open a new UNIX Shell window or a Command Prompt on Windows 2 Change the working directory to labs lab8 math 3 Create a new elaboration file using the following command at the shell prompt vsim elab math opt elab t 100ps sdfmax math opt tb t sdf math opt sdo L work L altera math opt tb The elab option generates a file math opt elab which contains the whole elaborated design including all sdf information Use the Is l command or Windows Explorer to check the size of the math opt elab file 4 Start a batch simulation using the previously generated elaboration file vsim c load elab math opt elab do sim elab do ModelSim Ad
54. discuss User Interface Features Common to All Menus Individual Window Features Where to Go for Help 1 2 ModelSim Advanced Debugging Model Sim Windows Copyright 2002 Mentor Graphics Corporation Notes ModelSim Advanced Debugging December 2002 Review ModelSim Windows User Interface Main Window controls the simulation Structure Window boxes VHDL circles Verilog Process Window VHDL processes amp concurrent signal assignments Verilog initial always assign amp implicit wire Signals amp Variables Windows display current values of data User Interface Fr boven SE PLUS 56 oth Deku Delete Fie Ed View Compile Simusts Toole Debug Window Heb esl sei wanie Pie Ee ETE z ici xi ioj x ie Edt View Took Debug Windom xj deir 2A rc WaltA bea ol 88 sin sin z Project mixed Mow 2820 ms Detac n simatops a d gt Extended mode enabled heel 1 Ptoc pit out E wave default File Edit View Insert Format Tools Debug Window i E 4 SHS sO KET mim eir LEE 322 ns to 1330 ns Source Window editable color coded Wave amp List Windows historical tracking of selected data s Dataflow Window processes with data read amp data driven Multiple same type Windows for added debug capability 1 3 ModelSim Advanced Debugging Model Sim Windows Notes Copyright 20
55. entries in this report are additive therefore if a function is called by more than one line in the hierarchical view in the ranked view they will be added together 4 18 ModelSim Advanced Debugging December 2002 Analyzing Performance Example Cont Example Cont Ranked Output Ranked Profile lol x Samples 870 d E mx 2 o g Nme 000000 i a O F mentor_training lab1 arith_stc unsigndb vhd 64 F mentor training lab1 arith_sre unsigndb vhd 189 7 F mentor_training lab1 arith_stc unsigndb vhd 216 6 store_array vhd 39 12 F mentor training labl testring vhd 99 5 F mentor training lab1 control vhd 87 Hierarchical Output F mentor_training lab1 testring vhd 97 F mentor training lab1 contral vhd 98 retrieve_artay vhd 35 F mentor_training lab1 control vhd 87 F tient r training abi arth sic unsondb dias F mentor_training lab1 arith_stc unsigndb vhd 64 11 Foinentor einn eir Pant sie Fungi vida F mentor training lab1 arith_src unsigndb vhd 65 F mentor training lab1 control vhd F mentor_training lab1 arith_sreyAnsigndb vhd 223 F mentor_training lab1 arith jfc unsigndb vhd 65 F mentor training lab1 arith_stc unsigndb vhd 58 NNNYNHYN CO CO CO 4d CH lore array vhd 38 F mentor training lab1 arith src unsigndb vhd 216 F mentor training lab1 arith_src unsigndb vhd 189 F mentor training lab1 arith src unsig
56. for the Tk root window is a single dot ie e Consists of a child name appended to the pathname of its parent Uses the character Must be unique among its siblings other widget children of its parent Example The pathname of the top level frame whose parent is the Main window could be frametop A button widget whose parent is frametop could be frametop button1l 2 17 ModelSim Advanced Debugging Tcl Tk Overview Copyright 2002 Mentor Graphics Corporation Notes ModelSim Advanced Debugging 2 17 December 2002 Tcl Tk Overview Tk Commands Tk Commands Used for writing GUI applications Some Tk commands are e button Create and manipulate button widgets e toplevel toplevel BETIS label anyone there Create and manipulate top level widgets e scale Create and manipulate scale widgets e label Create and manipulate label widgets pack e pack R say goodbye Geometry manager that packs around edges of cavity e frame Create and manipulate frame widgets e scrollbar Create and manipulate scrollbar widgets 2 18 ModelSim Advanced Debugging Tcl Tk Overview Copyright 2002 Mentor Graphics Corporation Notes 2 18 ModelSim Advanced Debugging December 2002 Tcl Tk Overview Simple Tk Example Simple Tk Example toplevel foo label foo lbl text anyone there button foo bl text say hello command foo lb
57. inside the design They are ModelSim Advanced Debugging 3 31 December 2002 Test Benches 3 32 top c_ wen top p addr top c_ s1 junk_array Use the sim tab of the Main window to navigate down to the instances where these signals are contained Select the instances as indicated below and View Source Select the signal in the signals window and right click to bring up a pop up window Choose Signal Declaration The source window should now highlight where the signal is declared If it s not obvious from looking at the code you can select the Tools Describe menu item in the Source window to display exactly how the signal is declared Write down how the signal is declared here top c_ wen top p addr top c_ s1 junk_array Now select the top design unit and go to the source window Remove the read only flag on the source file by selecting the Edit Read Only menu item Then add three signal declarations for the mirrored signals which will hold the values for the lower level signals Note that since the top level is VHDL you ll have to use std logic orstd logic vector with a similar range for signals that are mirrored from Verilog signals signal top wen reg signal top address output signal top junk array Now add the init signal spy call to the process in the top level VHDL code Find the process and add 3 lines one for each spied signal Save your changes in the source window ModelSi
58. list window From the List window notice that int goes from 0 to 1 at 9750 ns You can optionally add signals to the simulation log without displaying them in the Wave or List window by choosing Simulation gt Display gt Add Log You can also open any other simulator window by choosing Simulation gt View from the menu For example you may wish to use this menu to open the ModelSim Source or Structure windows ModelSim Advanced Debugging 9 33 December 2002 Debug Detective Show IBD View 1 Make the uart top block diagram active 2 Double click and open down into the serial_interface component A block diagram now appears showing two components xmit_rcv_control and status registers 3 Select the status registers component and choose Diagram gt Show IBD from the menu The following IBD view appears UARTserial_interface struct IBD File Edit View Table Simulation Window Help doe Mg ADOWNTOD fd logivector Moe Mg doge vedor Btd_logic_vector PAET EE ho XE 6 ED RUBBER 8 XBR E Ready Open a State Machine View 1 Make the IBD view active and select the xmit rcv control component column heading Choose Simulation gt Environment gt Selected from the menu 9 34 ModelSim Advanced Debugging December 2002 Debug Detective 2 Make ModelSim Main window active and click the button on the toolbar The following state machine diagram appea
59. machine is running the less cycles spent on simulation 4 33 ModelSim Advanced Debugging Analyzing Performance Copyright 2002 Mentor Graphics Corporation Notes ModelSim Advanced Debugging 4 35 December 2002 Analyzing Performance General Performance Issues Cont General Performance Issues Cont The following tips help maximize simulator performance e Wave List or Log only the signals of interest e Use checkpoint restore to avoid re simulating the same portions of a design e If possible run in non GUI or batch mode e Run in a timescale fine enough to catch the smallest events expected e g if the SDF file units are in nanoseconds and the values in the timing triplets have only two significant figures 12 23 32 then 10s of Pico seconds is sufficient Additional Info http www model com resources pdf optimizing perf 56b pdf 4 34 ModelSim Advanced Debugging Analyzing Performance Copyright 2002 Mentor Graphics Corporation Notes 4 36 ModelSim Advanced Debugging December 2002 Analyzing Performance Summary Summary This module introduced and explored the application of the following topics Code Coverage Coding for Performance The Performance Analyzer Managing the Profiler and Results RTL Optimization Gate Level Optimization vlog Commands vcom Commands General performance Tips o gt 9 9 9 9 9 9 9 4 35 ModelSim Advanced Debugging Analyzing Performance C
60. newline character is provided at the end of the message by default mti_Realloc this function works like the C realloc function on memory allocated by mti Malloc If the specified size is larger than the size of memory already allocated to the origptr parameter then new memory of the required size is allocated and initialized to zero the entire content of the old memory is copied into the new memory and a pointer to the new memory is returned Otherwise a pointer to the old memory is returned Any memory allocated by mti Realloc is guaranteed to be checkpointed and restored just like memory allocated by mti Malloc Memory allocated by mti Realloc can be freed only by mti Free mti Realloc automatically checks for NULL pointer In the case of an allocation error the function issues the same error message as mti Malloc mti FatalError requests the simulator to immediately halt the simulation and issue an assertion message with the text Fatal Foreign module requested halt A call to this function does not return control to the caller and simulation cannot be continued ModelSim Advanced Debugging 7 23 December 2002 FLI and C Models Foreign Architecture Initialization Foreign Architecture Initialization First create and compile an architecture with FOREIGN attribute e The string value of the attribute is used to specify the name of a C initialization function and the name of the object file to lo
61. on the button that says Compute Differences Now Finally click Finish Run the simulation for 10 us The comparison results will automatically appear in the wave window and the transcript window will show you a summary of the differences You can zoom in on the differences in the wave window If you click on the find first difference icon in the wave window the leftmost red transition icon a cursor will be put on top of the first difference and the signal that failed is selected You will probably need to zoom in a lot to see the difference When you ve zoomed in enough to see the red highlighted difference place your mouse cursor over the difference and right click it Try the Diff Info Annotate Diff Ignore Diff menu items Notice how the highlighting of the difference changes each time Also try expanding and collapsing the signal that had the difference When it s expanded you can see the golden gold typical timing signal next to the test sim maximum timing signal Now we ll close the current comparison and also the current simulation Select the menu item Tools Waveform Compare End Comparison Then type quit sim to quit vsim but keep ModelSim up ModelSim Advanced Debugging December 2002 Waveform Compare 12 Now we ll perform a more complicated comparison but this time there is a script to do it all for you Go back to the ModelSim Main window Select Tools Execute Mac
62. only 12 of the simulation time iix Samples 1729 dA vij In n Name Under mea o W top fixed tb vhd 28 decoder integer vhd 72 decoder integer vhd 74 decoder integer vhd 73 decoder integer vhd 75 decoder integer vhd 86 decoder integer vhd 78 decoder integer vhd 120 decoder integer vhd 158 decoder integer vhd 132 decoder integer vhd 180 decoder integer vhd 108 decoder integer vhd 144 Quit the simulator quit f Sp See Sse se Se 2 NOM ON OO AD These various runs illustrate how coding style can affect simulation run time We can significantly shorten run times without altering functionality Figure out how much improvement we made to the design by entering the results below ModelSim Advanced Debugging December 2002 Analyzing Performance Slowest simulation run time from the select one case if 35 668 integer increment run w o code coverage seconds Fastest simulation run time from the select one case if v Id 668 integer increment run w o code coverage seconds Ratio of slowest fastest run times xfaster ModelSim Advanced Debugging 4 43 December 2002 Analyzing Performance 4 44 ModelSim Advanced Debugging December 2002 Module 5 Virtual Signals Objectives Upon completion of this module you will be able to e Describe what virtual objects are and their role in debugging e Explain the purpose of virtual signal
63. pointer to the current context ModelSim Advanced Debugging 7 11 December 2002 FLI and C Models mti AddLoadDoneCB adds the specified function to the elaboration done callback list The same function can be added multiple times possibly with a different parameter each time At the end of the elaboration all callbacks in the list are called with their respective parameters These callbacks are also called at the end of a restart of a cold restore vsim restore mti_AddLoadDoneCB must be called from a foreign initialization function in order for the callback to work Specify the function either in the foreign attribute string of a foreign architecture or in the foreign string option of a vsim command mti_AddQuitCB adds a simulator exit callback The same function can be added multiple times with possibly a different parameter each time When the simulator exits all callbacks in the list are called with their respective parameters When the quit sim command is given to vsim quit callbacks are not called because the simulator is not quitting completely Only restart callbacks are called mti_AddRestartCB adds a simulator restart callback The same function can be added multiple times with possibly a different parameter each time When the simulator restarts all callbacks in the list are called with their respective parameters before the simulator is restarted The callback function should do a cleanup operation including freeing a
64. process reset begin if reset O then To fix it modify the source code to add a delay to either the inverter or the and gate First you ll have to make the source code editable by unchecking the Edit read only menu item Now add the delay to one of the two gates For example change the inverter to be b lt not c after 100 ns Save the change by clicking the save button the floppy drive symbol in the source window toolbar Then click the compile button in the same toolbar the leftmost button After successfully recompiling restart the design Use the restart icon in the main window toolbar or type restart f Add all the signals in the entire design to the logfile This will be useful in the next section The signals won t appear in the wave window but ModelSim will capture all their values during this run Type add log r ModelSim Advanced Debugging December 2002 Debugging 10 Run the design for 50 us PART 2 Logic Error Bug l In the Wave window select View Zoom Zoom Range Enter the values 38us to 48us and Apply Select the total value signal in the waveform view and right mouse click This will display a context sensitive menu Select the Radix and set it to unsigned Notice that when the jack of hearts is dealt look at the delt card and delt suit signal 20 is added to the total value which is incorrect as a face card has a value of 10
65. separate each level of the hierarchy When you are finished your command should look as follows button footer b2 ModelSim Advanced Debugging 2 29 December 2002 Tcl Tk Overview 2 30 7 The next step is to configure the button We will configure the button much like we configured the button in the first exercise of this lab but this time we will use the configure command to describe the functionality of the button Configure the button using the text command and width arguments For example configure the text to say Open the command to read in the open_windows procedure and the width to be 8 Finish writing the button s configuration on the line below then copy the line to the open close button tcl file footer b2 configure Here a hint on how to create a procedure within a procedure Place the name of the procedure within curly braces and pass in a value for the void parameter as follows command open windows 0 The final line of the procedure should place the button on the lower right hand side of the ModelSim window You will do this exactly as you did in Step 11 of the first exercise Use the pack command and the side argument Make sure to enclose the entire procedure within curly braces You should have typed a left hand curly brace 1 on the line declaring the procedure Step 5 so you need to place a right hand curly brace 3 on the final line You can reference the file open
66. simulator command The string must contain the command just as it would be typed at the VSIM prompt The results of the command are transcribed in the vsim transcript Any command that changes the state of simulation such as run restart restore etc cannot be sent from a foreign architecture subprogram or callback that is executing under the direct control of vsim mti AddCommand adds a user defined simulator command The case of the command name is significant The simulator command interpreter subsequently recognizes the command and calls the command function whenever the command is recognized The entire command line the command and any arguments is ModelSim Advanced Debugging 7 19 December 2002 FLI and C Models passed to the command function as a character string The command function prototype is void commandFuncName void command A command can be added with the same name as a previously added command or even a standard simulator command but only the command added last has any effect mti_AddTclCommand adds a user defined Tcl command The case of the command name is significant The simulator command interpreter subsequently recognizes the command and calls the function along with its parameter and user supplied arguments whenever the command is recognized The function must return a valid Tcl status for example TCL OK or TCL ERROR The command function prototype is int commandFuncName Client cmd_param
67. tb vhd file is located in the labs lab8 math src directory Simulate vsim the testbench math opt tb with the SDF maximum timing switch sdfmax along with specifying the correct instance to apply to the SDF file The SDF file math opt sdo is located in the labs lab8 math sdf directory You will need to specify search library paths L switches for the altera library and the work library to allow ModelSim to find the Verilog cell primitives located in the altera library Also it may be necessary to edit the post P amp R Verilog netlist math opt vo depending on where the file resides and where the ModelSim working directory is pointing If math opt vo resides in the labs lab8 math sdf directory and the ModelSim working directory points to labs lab8 math then edit line 58 of math opt vo to read parameter SDFFILE sdf math opt sdo Open the ModelSim wave window add all top level signals from the testbench math opt tb Turn on the performance profiler profile on and run the simulation for 5 13 us time run 5 13 us How long was the ModelSim runtime for the Verilog gate level SDF simulation move the decimal point 6 places to get the number of seconds ModelSim Advanced Debugging December 2002 Debugging Is this runtime less than what you observed in the VHDL math_opt sdo design How much slower or faster was the Verilog runtime vs VHDL 7 Quit the current simulation quit sim when compl
68. the Dataflow and Wave windows and note how easy it is to debug your design ModelSim Advanced Debugging 1 41 December 2002 Review ModelSim Windows 6 You are finished Quit the simulatior by typing quit at the ModelSim prompt 1 42 ModelSim Advanced Debugging December 2002 Module 2 Tcl Tk Overview Objectives Upon completion of this module given required tools students shall Describe key Tcl capabilities Describe Tcl syntax and commands Describe Tk syntax and commands Describe the application of Tcl to ModelSim Perform command substitution Execute multiple line commands Add buttons to existing windows Execute ModelSim commands from Tcl Describe where to go for help ModelSim Advanced Debugging 2 1 December 2002 Tcl Tk Overview Module Overview Module Overview Tcl capabilities Examples Tcl syntax Application of Tcl Command Substitution Multiple Line Commands Examples of Tk syntax Adding buttons to existing windows Executing ModelSim commands from Tcl Examples of Tcl Tk scripts 9 9 9 9 9 9 9 9 2 2 ModelSim Advanced Debugging Tcl Tk Overview Copyright 2002 Mentor Graphics Corporation Notes ModelSim Advanced Debugging December 2002 Tcl Tk Overview Why Tcl Tk Why Tcl Tk TcI Tk Scripting User Interface Language of Choice e Powerful scripting language Allows designers to create their own simulation scripts Easy to create scripts in any te
69. the hierarchy if there is an interceding VHDL block e Monitor drive or force release an item from anywhere in the hierarchy 3 17 ModelSim Advanced Debugging Test Benches Copyright 2002 Mentor Graphics Corporation Notes Why would you want to or need to use Signal Spy l VHDL does not have an inherent method of allowing you to probe internal signals like Verilog does Signal Spy allows you to probe any signal at any level within a VHDL or mixed VHDL Verilog design Use Signal Spy to probe internal signals from your test bench 1 Set up Signal Spy Example init signal spy ModelSim Advanced Debugging 3 17 December 2002 Test Benches 2 Specify the signal path top c s s0 data out 3 Define the destination for the value Example init signal spy top c s sO0 data out data out sOspy 4 Use the signal in your testbench Example signal data out sOspy std logic vector 15 0 Now you have access to any signal at any level 3 18 ModelSim Advanced Debugging December 2002 Test Benches Signal Spy Cont Signal Spy Cont New signal probing capability for ModelSim VHDL testbench signal s t r std_logic init_signal_spy top ul s s init signal spy top ul t2 vl s t init signal spy top ul t2 v2 r r Can check any signal in any other VHDL or Verilog module WITHOUT having to modify your code Greatly simplifie
70. time run 16 ms Enter the run time here Decoder run time for If implementation using stdlogic types View the profile results as a ranked profile by typing VSIM view profile ranked Note that 2196 of the simulation time 1s spent on a conversion function converting an integer to std logic vector line 30 ofthe top loop tb vhd file The std logic vector to integer conversion function line 32 of decoder if stdlogic vhd consumes 19 of the simulation time Approx 40 of the simulation time was spent converting std logic signals to integers and vice versa ModelSim Advanced Debugging December 2002 Analyzing Performance A logical way to speed up the simulation is to avoid converting between the two data types For the next step we have already re coded part of the design to use integers wherever possible in order to avoid doing the conversion This is actually quite common many designs manipulate std logic vector by doing adds subtracts conversions etc which are very expensive in simulation time Whenever it s possible to use integers the simulation will run much faster 3 Run the re coded integer version of the decoder block Close the Ranked Profile window and go back to the Project tab of the ModelSim Main window First compile the decoder_integer vhd file following the steps described in Steps 1 and 2 and then compile the testbench top loop int tb vhd Go to the Library tab and load t
71. to detect when the winstrobe signal goes high You can execute this in the Main window because ModelSim accepts Tcl commands interactively Show that here Answer A common command you would give the when statement to execute when the condition becomes true would be the stop command This tells the simulator to break when the condition becomes true In this case we re not going to use this but instead set a Tcl variable that is already defined to stop the simulation So in the body of the when command we ll put the following Tcl code there Set running 1 We also want to display who won the hand The winner signal in the design is high when the dealer won the hand and low when the player won There is also a Tcl function already defined that draws a picture of who won The function is draw winners picture and it takes one parameter ModelSim Advanced Debugging December 2002 Test Benches 9 10 11 12 13 which is true when the dealer won and false when the player won It then draws the corresponding picture to the screen In this exercise write a Tcl statement that calls the draw function with the correct parameter to indicate who won Hint use the examine command and brackets Answer Now if we piece together the when command the set command to stop the simulation and the tcl statement to draw the winner we ll have fixed the design The follow
72. to the cor it do file and run the script ModelSim do cor it do Another way to run the script would be to execute the menu option Tools gt Execute Macro but if you have a lot of debugging to do it might be faster to create a Tk button widget so that all you had to do to re run the script is click on the button When you are finished type quit sim For this next part of the lab we will create a button called Run Script and bind it to the do cor it do command Before we create the widget button we ll review a few Tk basics Tk widgets are objects such as buttons scrollbars lists pop up menus pull down menus option menus the text widget and the canvas widget Tk also provides container widgets such as toplevel and frame widgets You create widgets by using built in Tk commands The Tk extension provides UI controls for the development of Tcl based GUI applications The generic widget classes determine the appearance and behavior of the widget For example button radiobutton and checkbutton could all belong to the Tk button class Buttons are meant to be clicked and trigger an event or series of events Each Tk widget is its own window and is uniquely identified by its name The name of the widget reflects the hierarchy in which it is placed For example t1 f1 b1 might indicate a top level frame called t1 a frame placed inside of t1 called f1 and a button inside of the frame called b1 ModelSim Adv
73. traversing the design with the region traversal functions mti_CreateRegion allows you to create a region with an illegal HDL name Refer to mti CreateSignal for more information about naming conventions and style mti_Delta gets the simulator iteration count for the current time step mti_Free frees simulator managed memory This function cannot be used for memory allocated by direct calls to malloc mti Malloc allocates a block of memory of the specified size from an internal simulator memory pool and returns a pointer to it The memory is initialized to zero Memory allocated by this function is automatically checkpointed On restore this memory is guaranteed to be restored to the same location with the values it contained at the time of the checkpoint This memory can be freed only by mti Free mti Malloc automatically checks for a NULL pointer In the case of an allocation error the function issues the following error message and aborts the simulation Memory allocation function Please check your system for available memory and swap space mti Now returns the low order 32 bits of the current simulation time The time units are equivalent to the current simulator time unit setting 7 22 ModelSim Advanced Debugging December 2002 FLI and C Models mti_PrintMessage prints a message to the Main window and in the transcript file One or more newline characters can be included in the message string however a
74. vhd 130 2 2 lab arith_stc unsigndb vhd 216 F mentor_training lab1 arith_stc unsigndb vhd 223 2 2 F mentor training lab1 arith_sre unsigndb vhd 65 2 2 g g ab1 arith_src unsigndb vhd 189 El retrieve_array vhd 35 0 E i E 19 7o Simulation Time Lf deor tairihg abl arith_ste unsigndb vhd 216 Under This Line F mentor_training labl testring vhd 99 F mentor_training labl testring vhd 9 F mentor_training labl control vhd 130 4 15 ModelSim Advanced Debugging Analyzing Performance Copyright 2002 Mentor Graphics Corporation Notes If we look a little closer at the report windows we can understand how they are interconnected and can used to understand what is happening in the simulation Here we can see that 1996 of the simulation time has been taken under this particular line of code The hierarchical view orders the parent lines using the under percentage from the highest to the lowest It is possible to collapse the children functions by press the sign on each line 4 16 ModelSim Advanced Debugging December 2002 Analyzing Performance Example Cont Example Cont Ranked Output Samples 870 d E nz 4 o g Name 000 unet ma E F mentor_training lab1 arith_stc unsigndb vhd 64 11 11 F mentor_training lab1 arith_ste unsigndb vhd 189 7 F mentor training lab1 arith_stce unsigndb vhd 216 5 5 store array vhd 39 Te 5 H ierarchical Output F mentor training lab1 testring vh
75. 0000 end if end if cout vector cout then assert false report Cout is amp to char cout amp amp Expected value is amp to char vector cout initial monitor stime rst clk count Enamodule 3 6 ModelSim Advanced Debugging Test Benches Copyright 2002 Mentor Graphics Corporation Notes 3 6 ModelSim Advanced Debugging December 2002 Test Benches VHDL Test Benches Design Units in Verilog VHDL Test Benches Design Units in Verilog ModelSim automatically detects cross HDL instantiations e Nowrapper file is needed e The necessary adaptation conversions are performed automatically Use VHDL test bench Verilog design units for best performance e The design unit must be a module UDPs are not allowed e The ports are named ports Verilog allows unnamed ports e The ports are not connected to bi directional pass switches It is not possible to model pass switches in VHDL e Instantiate the Verilog module as a component in the VHDL The interface to the module is extracted from the library in the form of a component by running vgencomp Given a library and a module name vgencomp writes a component declaration to standard output vgencomp lt module_name gt 3 7 ModelSim Advanced Debugging Test Benches Copyright 2002 Mentor Graphics Corporation Notes ModelSim Advanced Debugging 3 7 December 2002 Test Benches VHDL and Verilog Identifiers
76. 0000000 EL ER Bt Ek 9 SPO BES EY m RS Elf Add probes to view values of selected signals x A Add a probe from from the tester Simulation toolbar 10 9 15 ModelSim Advanced Debugging Debug Detective Overview Copyright 2002 Mentor Graphics Corporation Li LI Notes You are able to select signals in the block diagram and assign probes to them This allows you to display signal values directly on the block diagram There is synchronization between the probes and the simulation environment The probes update and display the signal values based on the current selected time in the simulation ModelSim Advanced Debugging 9 19 December 2002 Debug Detective Breakpoints Breakpoints work uart_top struct Read only Block Diagram ioj xj File Edit View Diagram Simulation Window Help Set a breakpoint from the amp o c 2 end i 744 9 Simulation menu Environment 2 b Breakpoints gt ay Ez Probes Delete b b Display View Signal Info Disable Restart Simulator Report i Delete All div perm 00000000 ta Enable mi enable write lear flags cpu interface n Breakpoint s Add a breakpoint Edit Selected Set a breakpoint from the Simulation menu East 9 16 ModelSim Advanced Debugging Debug Detective Overview Copyright 2002 Mentor Graphics Corporation Notes You can control breakpoints and create breakpoints The breakpoint s dialog box
77. 02 Mentor Graphics Corporation The examples in this module illustrate ModelSim s graphic interface within a Windows environment however ModelSim s UI is designed to provide consistency across all supported platforms The OS determines the basic window management frames but ModelSim controls all internal window features such as menus buttons and scroll bars The ModelSim GUI is based on Tcl Tk You are able to customize your simulation environment through easily accessible preference variables and configuration commands which allows control over the use and placement of windows menus menu options and buttons ModelSim Advanced Debugging December 2002 1 3 Review ModelSim Windows The ModelSim simulation and debugging environment consists of nine window types Multiple windows of each type can be used during simulation with the exception of the Main window To make additional windows select File gt New gt Window from the Main window A brief description of each window follows Main window The initial window that appears upon startup All subsequent ModelSim windows are launched from this one Dataflow window Displays the physical connectivity of your design and lets you trace events List window Shows the simulation values of selected VHDL signals and variables and Verilog nets and register variables in tabular format Process window Displays a list of processes in the selected design region or selected
78. 1 label hdsbpl uart tb il int stop The when id command will set the desired breakpoint although it may not display the breakpoint graphically as a red circle on the int signal on the block diagram ModelSim Advanced Debugging December 2002 Debug Detective 3 Run the simulator for the default timestep 100 nano seconds by using the Ell button or by choosing Simulation gt Run gt For Time from the menu in the block diagram window Notice that the ModelSim window shows the message Simulation stop requested This indicates that a breakpoint has been set and that the simulator has been stopped temporarily Notice that yellow boxes now appear on some of the signals on the block diagram These boxes indicate that no change has occurred to the value of each of these signals 4 Run the simulator until there are no more events scheduled by using the button from the simulation tool bar or by choosing Simulation gt Run gt Forever from the block diagram menu A change in value of the int signal from 0 to 1 occurs and now appears on the block diagram Make the wave window active once more and notice that the same signal int also shows the value 1 This corresponds to the signal shown on the block diagram 5 Make the uart top block diagram active 6 Use the button from the Simulation toolbar or choose Simulation gt Display gt Add List from the block diagram menu to add the selected signals to a simulator
79. 14 Creating a Simulation Script sei oxo eii eroe araensatiosupenennateiceelacecsieteorentumatanaaiaels 2 15 Simulation Script Example rude ore eta Tiesto eap DE none Re rea 2 16 TE Widget OVervie W esicscenets e eei fasutsisecc tace o a edis ooa 2 17 TkCommandsi uicta etate aid as cies eot se ese ea eed Games est o entes 2 18 Simple ki Exam Phe 25a ucc teo eet b tovt e eroe bte et Edo dede 2 19 horn Mee c M E 2 20 Additional Tel Tk Resources 422g ones ceres ry erctrt o rere e ex uo E Ceo Feat eee ee ee 2 22 SITUA ATTE OS TETUER 2 23 Lab 2 Using Tcl Scripts and Tk Widgets in Simulation 2 24 Module 3 Test Benelhies iniecta ene idive ata dee do casia eu esa qug dea Erogo dns veau Reo eases qo DEAE Mea CE EC e DV a Sa RAE oaea 3 1 Module Vet View este cete t bp nO Has Et 3 2 Function cocido esses bad wel Sow ue esL da Le Edict tcd P erae 3 3 TIraplergctitatlOfi rods errs Woe Ora miro rosa Ud Cie cy bles ta oma a Reed pe a aa 3 4 viii ModelSim Advanced Debugging December 2002 Table of Contents TABLE OF CONTENTS Cont Comparison of Different Test Bench Methods cccccccecccccceeeesssseeeeeeeeeeeseees 3 5 HIDE Test Bene Bes eese oe ded e ioo atur toe tero da eco ct cian oa a dio rigid 3 6 VHDL Test Benches Design Units in Verilog 3 7 VHDL and Verilog Identifiers os osa oe eo ee ter ha co tacebacrwascanepeesvanees 3 8 Setting VHDL Generic Parameters zxxucuiiteusenidaubes been e t Rice ep o
80. 2 Mentor Graphics Corporation Notes 8 6 ModelSim Advanced Debugging December 2002 Debugging Bus Checks Bus Checks Bus Contention Detects conflicts on nodes with multiple drivers Error message issued identifying problem nodes You have to specify nodes to be checked Write checking messages to a file default is to screen Commands check contention add lt node_name gt check contention config file lt filename gt time lt limit gt check contention off lt node_name gt Bus Float e Detects nodes that are in the high impedance state for a user defined limit e Commands check float add lt node_name gt check float config file lt filename gt time lt limit gt check float off lt node_name gt Time limit that a node may be in contention Time limit that a node may be floating 8 7 ModelSim Advanced Debugging Debugging Copyright 2002 Mentor Graphics Corporation Notes ModelSim Advanced Debugging 8 7 December 2002 Debugging Toggle and Stability Checking Toggle and Stability Checking Toggle checking Counts transitions on specified signals Issues report of toggle statistics Can help identify areas in the design that have high activity Can help identify areas in the design that are not properly simulated Commands toggle add lt node_name gt toggle report file lt filename gt toggle reset lt node_name gt Stability checking e Detects when activity has not set
81. A second run with different testbench stimulus also takes 20 minutes to load and 20 minutes to run If you generate an elaboration file on the first run you eliminate the 20 minute ModelSim Advanced Debugging 4 33 December 2002 Analyzing Performance elaboration and SDF annotation time for the second and subsequent runs Loading an elaboration file takes seconds instead of minutes In many cases design loading time is not that important For example if you are doing iterative design where you simulate the design modify the source recompile and re simulate the load time is just a small part of the overall flow However if your design is locked down and only the test vectors are modified between runs loading time may materially impact overall simulation time particularly for large designs loading SDF files 4 34 ModelSim Advanced Debugging December 2002 Analyzing Performance General Performance Issues General Performance Issues In general simulation load and run times increase when you simulate with timing information The following tips help maximize simulator performance e Run on the fastest machine possible Fast means lots of local memory and a fast CPU e If possible the design being simulated should be located on the machine running the simulation Files stored elsewhere have to cross the network and thus slow run times e Run the job on a machine that is not running other jobs The more tasks the
82. HDLnet VHDLwrite Verinex ViewCreator ViewWare Virtual Library Virtual Target Virtual Test Manager TOP VR Process SM VRTX VRTXmc VRTXoc VRTXsa VRTX32 Waveform DataPort We Make TMN Easy Wiz o matic WorkXpert xCalibre xCalibrate Xconfig XlibCreator Xpert Xpert API XpertBuilder Xpert Dialogs Xpert Profiler XRAY XRAY MasterWorks XSH Xtrace Xtrace Daemon Xtrace Protocol Zeelan Zero Tolerance Verification Zlibs Third Party Trademarks The following names are trademarks registered trademarks and service marks of other companies that appear in Mentor Graphics product publications Adobe the Adobe logo Acrobat the Acrobat logo Exchange FrameMaker FrameViewer and PostScript are registered trademarks of Adobe Systems Incorporated Altera is a registered trademark of Altera Corp AM188 AMD AMD K6 and AMD Athlon Processor are trademarks of Advanced Micro Devices Inc Apple and Laserwriter are registered trademarks of Apple Computer Inc ARIES is a registered trademark of Aries Technology AMBA ARM ARMulator ARM7TDMI ARM7TDMI S ARM9TDMI ARM9E S ARM946E S ARM966E S EmbeddedICE StrongARM TDMI and Thumb are trademarks or registered trademarks of ARM Limited ASAP Aspire C FAS CMPI Eldo FAS EldoHDL Eldo Opt Eldo UDM EldoVHDL Eldo XL Elga Elib Elib Plus ESim Fidel Fideldo GENIE GENLIB HDL A
83. IS TET 9 9 Block Diagram Toolbar 23e buit ertet d bene nee a deett E 9 10 Interface Based CSI CNN So tats cela ettet so Meet ited cane tu ode doti beoe 9 1 Slate id Oat cts nrc etosetrbte dorsa Menit obi tubo bte oet boda owes 9 13 Flow Chatt rst cited E Q 9 15 Simulation Control 5 ci FE Rex E SEE ERE Ba ade e ROO UE NEP ean 9 17 SIMU SHON PrODES osuere eet Posee e Heec o Ys td eed Sv tiie vet doen 9 19 Breakpoint Siar vias ret odi sha toa ican tesaihe Eon dst iud teu SER Odeon e ix te duces acne 9 20 Animation Menu and Toolbar 4 oe ERR ea eoa agb lette up pole 9 2 Animation TOI DAE docete o ese a ioe erste io he ese t es 9 23 Animation Activity Trail ades e ied te eo p ER das e salves ER Pres 9 25 Sammary do ros dacanta sev ras E e E e ite ed R vdcut ati d tn o s Pre ambu asodE 9 26 Lab 9 Debug Detective Tutorial Optional Lab seeseseesss 9 27 ModelSim Advanced Debugging xiii December 2002 Table of Contents xiv TABLE OF CONTENTS Cont ModelSim Advanced Debugging December 2002 About This Training Workbook About This Training Workbook This document is the ModelsSim Advanced Debugging training workbook which teaches students the advanced debugging concepts and techniques available using the Mentor Graphics ModelSim tool Audience The information in this course is intended for HDL designers who have some prior knowledge of the ModelSim tool and are seeking to broaden their kn
84. LI interface Run the simulation again with run all The ModelSim GUI may close after executing this command however the mti_trace file will still be generated Relaunch ModelSim and continue with step 13 You can now look at the generated file by typing notepad mti_trace at the ModelSim prompt Look at this file and you ll see for each FLI call the C code makes to the simulator the simulator recorded entering the function and exiting it and what the parameters were Go to the bottom of the file and you see that it entered a function called mti_GetSignalValue but never exited So the crash occurred in this function Look up the file a few lines and you ll see a line similar to Callback 66 trace_14 0x2921396 for Prt_Bust Time 0 63700 Iteration 5 Note If you have difficulty finding the line do a search for Prt_Bust The Callback number and or time may be somewhat different from the line above This shows that the FLI code that called the crashing function called from a process named Prt_Bust This process was created in the FLI code by this statement procBust mti CreateProcess Prt Bust cont next line mitVoidFuncPtrT evalBust ip ModelSim Advanced Debugging December 2002 FLI and C Models 16 Open the C code used in the design by going to the Project tab in the main window and double clicking on the file testbench_error c Go to line 68 and you ll see the above line The first paramet
85. MDT MGS MEMT MixVHDL Model Generator Series MGS Opsim SimLink SimPilot SpecEditor Success SystemEldo VHDeLDO and Xelga are registered trademarks of ANACAD Electrical Engineering Software a unit of Mentor Graphics Corporation Avant and Star Hspice are trademarks of Avant Corporation AVR is a registered trademark of Atmel Corporation Cadence Affirma signalscan Allegro Analog Artist Composer Concept Design Planner Dracula GDSII GED HLD Systems Leapfrog Logic DP NC Verilog OCEAN Physical DP Pillar Silicon Ensemble Spectre Verilog Verilog XL Veritime and Virtuoso are trademarks or registered trademarks of Cadence Design Systems Inc CAE Plus and ArchGen are registered trademarks of Cynergy System Design CalComp is a registered trademark of CalComp Inc Canon is a registered trademark of Canon Inc BJ 130 BJ 130e BJ 330 and Bubble Jet are trademarks of Canon Inc Centronics is a registered trademark of Centronics Data Computer Corporation ColdFire and M Core are registered trademarks of Motorola Inc Ethernet is a registered trademark of Xerox Corporation Foresight and Foresight Co Designer are trademarks of Nu Thena Systems Inc FLEXIm is a trademark of Globetrotter Software Inc GenCAD is a trademark of Teradyne Inc Hewlett Packard HP LaserJet MDS HP UX PA RISC APOLLO DOMAIN and HPare registered trademarks of Hewlett Packard Company HCL eXceed and HCL eXceed W are registered trademark o
86. ModelSim Advanced Debugging Student Workbook December 2002 GNiphice Copyright Mentor Graphics Corporation 2002 All rights reserved This document contains information that is proprietary to Mentor Graphics Corporation and may not be duplicated in whole or in part in any form without written consent from Mentor Graphics In accepting this document the recipient agrees to make every reasonable effort to prevent the unauthorized use of this information This document is for information and instruction purposes Mentor Graphics reserves the right to make changes in specifications and other information contained in this publication without prior notice and the reader should in all cases consult Mentor Graphics to determine whether any changes have been made The terms and conditions governing the sale and licensing of Mentor Graphics products are set forth in written agreements between Mentor Graphics and its customers No representation or other affirmation of fact contained in this publication shall be deemed to be a warranty or give rise to any liability of Mentor Graphics whatsoever MENTOR GRAPHICS MAKES NO WARRANTY OF ANY KIND WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OR MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE MENTOR GRAPHICS SHALL NOT BE LIABLE FOR ANY INCIDENTAL INDIRECT SPECIAL OR CONSEQUENTIAL DAMAGES WHATSOEVER INCLUDING BUT NOT LIMITED TO LOST PROFITS ARISING OUT
87. ModelSim Advanced Debugging Tcl Tk Overview Copyright 2002 Mentor Graphics Corporation Notes 2 10 ModelSim Advanced Debugging December 2002 Tcl Tk Overview Curly Braces Curly Braces Curly braces provide another way of grouping information into words e No substitution is performed on the text between curly braces set z x y is expr x y iu ModelSim SE PLUS 5 6 with Debug Detective File Edit View Compile Simulate Tools Debug Window Help ee S28 fl wA ELELEE OP i US EMI top std top std loop tb Bf i dec 20424 dec 2042 lf Package std logic unsigned VSIM 17 gt setz x y is expr x y zl x y is expr x y VSIM 18 gt Project perflab Now 10 ms Delta 2 sim top_std A 2 11 ModelSim Advanced Debugging Tcl Tk Overview Notes ModelSim Advanced Debugging December 2002 Copyright 2002 Mentor Graphics Corporation Tcl Tk Overview Control Structures Control Structures Tcl provides a complete set of control structures e Conditional execution e Looping e Procedures Tcl command structures are commands that take Tcl scripts as arguments proc setRand global gotRand noRandSeed Create and load the random number seed to the deck if gotRand set seed expr int rand 65536 else If the version of Tcl is pre 8 0 we have no rand or srand so we drive an arbitrary value i
88. ModelSim Advanced Debugging December 2002 Waveform Compare Continuous vs Clocked Comparison Continuous vs Clocked Comparison wave default File Edit Cursor Zoom Format Window SHS 4B RK kT QQQRiE min tst_pseudo clock 1 min tst pseudo reset 1 min tst_pseudo expected uU min tst pseudo storage Dae 0D0Tc min tst pseudo data 0 max tst_pseudo clock max tst_pseudo reset 1 max tst_pseudo expected i max tst pseudo storage Oo007 00007 Oe y0 ODO71 aos 1 max tst_pseudo data 0 E tst pseudo clock tst pseudo reset SS 4 tst pseudo clocked expected 0 min tst_pseudo expected 0 max tst_pseudo expected 1 FHA tst pseudo clocked data uU GHA tst pseudo expected 1 compare tst_pseudo expected 1262537 ps Diff number 4 id diff0031 From 1240 ns to 1320 ns min tst_pseudo expected 0 max tst_pseudo expected 1 1047814 ps to 1292027 ps 6 15 ModelSim Advanced Debugging Waveform Compare Copyright 2002 Mentor Graphics Corporation Notes Asynchronous comparison shown as red crosshatch over entire length of differences Synchronous comparison shown as red diamonds at beginning and end of clock period where differences exist ModelSim Advanced Debugging 6 15 December 2002 Waveform Compare Write Report Write Report Save a text file of the comparison differences compare info write lt filename gt wav
89. Notes Additional control capabilities for block diagrams include add wave delete wave add list and delete list You also have the ability to explore signal information and the ability to place the signal values or the signal states on the diagram itself 9 10 ModelSim Advanced Debugging December 2002 Debug Detective Interface Based Design Interface Based Design The IBD is an alternative view for block diagram You can switch from one to the other The IBD was built on the block diagram data model which means that most of the features of the block diagram editor will be available in IBD The tool preserves the full synchronization between both views after editing Table Show Block Diagram lt Diagram Show IBD View as Block Diagram D as IBD 9 10 ModelSim Advanced Debugging Debug Detective Overview Copyright 2002 Mentor Graphics Corporation Notes The interface based design or IBD is a tabular representation of a design You can toggle between the block diagram view and the IBD view The IBD might be a faster way to interpret the design depending on the type of information you are seeking ModelSim Advanced Debugging 9 11 December 2002 Debug Detective Interface Based Design Cont Interface Based Design Cont
90. OF OR RELATED TO THIS PUBLICATION OR THE INFORMATION CONTAINED IN IT EVEN IF MENTOR GRAPHICS CORPORATION HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES RESTRICTED RIGHTS LEGEND 03 97 U S Government Restricted Rights The SOFTWARE and documentation have been developed entirely at private expense and are commercial computer software provided with restricted rights Use duplication or disclosure by the U S Government or a U S Government subcontractor is subject to the restrictions set forth in the license agreement provided with the software pursuant to DFARS 227 7202 3 a or as set forth in subparagraph c 1 and 2 of the Commercial Computer Software Restricted Rights clause at FAR 52 227 19 as applicable Contractor manufacturer is Mentor Graphics Corporation 8005 S W Boeckman Road Wilsonville Oregon 97070 7777 A complete list of trademark names appears in a separate Trademark Information document This is an unpublished work of Mentor Graphics Corporation Part Number 069776 Trademark Information Mentor Graphics Trademarks The following names are trademarks registered trademarks and service marks of Mentor Graphics Corporation 3D Design A World of Learning SM ABIST Arithmetic BIST AccuPARTner AccuParts AccuSim ADEPT ADVance MS ADVance RFIC AMPLE Analog Analyst Analog Station AppNotes SM ARTgrid ArtRouter ARTshape ASICPlan ASIC Vector Inte
91. RTL e All source files for the design must be compiled in one vlog invocation to use the fast switch e Gives an extra 2 3x performance boost The O5 switch adds additional optimizations By Default ModelSim runs in debug optimized mode e Torun ModelSim in performance optimized mode add two vlog command line switches 05 fast list of files or f filelist txt gt e Significantly faster simulation performance e Module boundaries are flattened and loops are optimized so some levels of debugging hierarchy are eliminated 4 22 ModelSim Advanced Debugging Analyzing Performance Copyright 2002 Mentor Graphics Corporation Notes ModelSim Advanced Debugging 4 23 December 2002 Analyzing Performance Verilog Gate Level Verilog Gate Level How do you improve performance e Create separate work directories for the cell library and rest of design Multi million gate level netlist may require hour s to compile While working on optimizations you want to limit multiple compiles to ASIC library ONLY e Compile cell library with fast e Compile Device Under Test and Testbench WITHOUT fast e WARNING Compilation of large netlist with fast will be very slow and may require as much memory to compile as it does to elaborate may fill tmp space before complete 4 23 ModelSim Advanced Debugging Analyzing Performance Copyright 2002 Mentor Graphics Corporation Notes 4 24 ModelSim Advanced Debugging Dece
92. Ret 3 9 E Test Benches o oet deret ait ad onn Anis RISE FOR A 3 13 Tel Test Benches 2o a at OE t bU ERI LERRA singe ERES E eaea E Saha 3 14 Interactive GUI Test Benches iure ene omi re retreat abide dscns e eed 3 15 SEGA Ald Test BeHCIIeS 2 58820 ud c ete liba E rane stunt nied est ea ia stas vut Los 3 16 SOMA SS DN asc sut toas eR tudo a ON bu Tate aee A E 3 17 init signal spy VHDL Ut ity ce o eo ai S i bte c deo eod 3 20 init_signal_spy Verilog Task ooo teo Eee ett trabise eos ees 3 21 Summary ienen a TE 3 22 Lab Sac Tel Tk Testbencb 5i e EHI FRE ERE ane puir a ateraia 3 23 173b 32 STOMA S Dy uoces orta p e eerte pe eMe ED e rena t a ure ER S etri re o VI vi Eat 3 27 Module 4 Analyzing Performance eeesec iei co hune rin ri rena Ex daudicnceeatauaiacsedsueunsavencatesnsduecodvonne 4 1 Module COVOEVIEW arasan eese bees bert tesa ede iat Rede e bees a estamos 4 2 Chall up T 4 3 Code Coverage Integrated Line Coverage eeesssssseeeeeeeeeene 4 4 Verification C Oode COVOEAe oen onore eet Deco oed pe Moe Iu duele Ra VER 4 5 Misses Reporting and Exclusion 2 rato oer EOD TID EXE Eae resti E dr docet 4 6 EXISTER 2er N b ped ih tape ote Leia 4 7 Managing Coverage Data ose too dod Cura add epoca bets Luo ases 4 8 Merging Coverage Report GUI 2o eit xp a Ib VR OR UE EP enden 4 9 Pertorimance Analyzer erorar aiea tuli be ddidi AT E 4 10 Profile O I RE 4 12 Taking Samples 4 ies
93. SDF waveform comparison Verilog gate level SDF simulation with a VHDL testbench Optimized gate level SDF simulation with a VHDL testbench Gate level SDF batch simulation with a VHDL testbench RTL simulation and changing VHDL generics from the command line PART 1 Iteration Limit Bug 8 28 l First open ModelSim and select File gt New Project Create a project in the labs lab8 blackjack directory called iteration lab Select Compile gt Project Defaults and make sure the Use 1993 Language Syntax option is checked Next add all of the VHDL files in the labs lab8 blackjack iteration directory Sort by compile order Project tab RMB Compile gt Compile Order Make sure the compilation order is as follows ModelSim Advanced Debugging December 2002 Debugging packages vhd Aces_Counter_error vhd Accumulator error vhd DataPath vhd FSM_Control vhd Black_Jack vhd Dealer vhd Sequencer vhd winner calc vhd Game On vhd Loader vhd TestBench vhd Compile the entire project by selecting Auto Generate Load the simulation by double clicking on the testbench entity in the Library tab Open the wave window and add all the top level signals to it Then do a run all The simulation should immediately stop and display this message Iteration limit reached Possible zero delay oscillation See the manual This error is due to some logic in the design feeding back on itself without any non zero delay
94. Second line compiles the top level unit without hiding the ports The top level ports must be visible for simulation 8 26 ModelSim Advanced Debugging Debugging Copyright 2002 Mentor Graphics Corporation Notes 8 26 ModelSim Advanced Debugging December 2002 Debugging Summary Summary This Module introduced and explored the application of the following topics Reasons for debug Debugging Tasks Breakpoints Checkpoint and Restore Bus Checks Toggle and Stability Checking Batch Mode Simulation Unknown States Erroneous Data Iteration Violations Mixed Language Issues SDF Instance Specification Generic Mismatches More Useful vcom and viog Commands 9 9 9 9 9 9 9 9 9 9 94 9 9 8 27 ModelSim Advanced Debugging Debugging Copyright 2002 Mentor Graphics Corporation Notes ModelSim Advanced Debugging 8 27 December 2002 Debugging Lab 8 Debug Introduction This exercise explores various techniques used in debugging designs Parts 1 amp 2 of this lab will use the blackjack design There will be a series of bugs that you will have to find in order to get correct simulation results Parts 3 10 explore simulating a back annotated post Place amp Route P amp R netlist in ModelSim and includes the following Simulation of a gate level netlist Waveform comparison of RTL simulation to gate level SDF simulation Optimizing the math design Simulation of optimized RTL design and
95. Sim Advanced Debugging December 2002 Debugging More Useful vcom amp vlog Commands More Useful vcom amp vlog Commands nodebug e Nota speed switch e Disables debugging data Models compiled with no debugging features e Do not compile with this option until done debugging e Cannot see inside the model Cannot set breakpoints Cannot single step within the code No internal views in Source Structure Signal Process and Variable windows e Design units compiled with nodebug can only instantiate other nodebug design units 8 25 ModelSim Advanced Debugging Debugging Copyright 2002 Mentor Graphics Corporation Notes nodebug provides protection for proprietary design information The Verilog protect compiler directive provides similar protection but this directive is a proprietary Cadence encryption algorithm that is not available to ModelSim All Design units that are compiled with nodebug can only instantiate design units or modules that are also compiled with nodebug ModelSim Advanced Debugging 8 25 December 2002 Debugging More Useful vcom amp viog Commands Cont More Useful vcom amp viog Commands Cont nodebug e VHDL vcom nodebug ports level3 vhd level2 vhd vcom nodebug top vhd e Verilog vlog nodebug ports level3 v level2 v vlog nodebug top v First line compiles amp hides the internal data plus the ports of the lower level design units
96. Tools gt Waveform Compare gt End Comparison and close ModelSim quit f ModelSim Advanced Debugging 6 29 December 2002 Waveform Compare 6 30 ModelSim Advanced Debugging December 2002 Module 7 FLI and C Models Objectives At the end of this module you will be able to Define Foreign Language Interface FLT Describe how to use FLI Describe ModelSim supported FLI capabilities Describe the Benefits of C Modeling Describe How to Declare Foreign models C models within VHDL designs Explain How FLI Maps to VHDL Datatypes Describe How to Use Checkpoint and Restore Using FLI Describe How to Debug FLI problems ModelSim Advanced Debugging 7 1 December 2002 FLI and C Models Module Overview Module Overview In this module we will discuss What FLI is and how we use it The Benefits of C Modeling C Functions C Callbacks C Subprograms e Examples of MTI functions Initializing Foreign Architecture Mapping Datatypes Using Checkpoint and Restore with FLI C Architecture Example C Subprogram Example Debugging Example 9 9 9 9 9 7 2 ModelSim Advanced Debugging FLI and C Models Copyright 2002 Mentor Graphics Corporation Notes ModelSim Advanced Debugging December 2002 FLI and C Models What Is FLI What Is FLI Procedural interface between VHDL simulator and other software programs C interface into ModelSim Fir architectures functions and procedures can be
97. Window e List Window e Wave Window Accessed using examine Setusing force Created by menu selections or virtual signal command 5 4 ModelSim Advanced Debugging Virtual Signals Copyright 2002 Mentor Graphics Corporation Notes Virtual signals are aliases for combinations or subelements of signals written to the logfile by the simulation kernel Virtual signals may be displayed by the signals list or wave window accessed by the examine command and set using the force command Virtual signals may be created by menu selections in the signals wave or list windows or created by the virtual signal command 5 4 ModelSim Advanced Debugging December 2002 Virtual Signals Virtual Signals Cont Virtual Signals Cont Automatically saved with the list or wave format Internally Created Virtual Hierarchical Context User defined Name virtual signal en patto instal lt path gt mpl eyqressionSting lt name AL x Parent Region Text String Expression 5 5 ModelSim Advanced Debugging Virtual Signals Copyright 2002 Mentor Graphics Corporation Notes virtual signal env lt path gt install lt path gt implicit lt expressionString gt lt name gt Creates a new signal known only by the GUI not the kernel that consists of concatenations of signals and subelements as specified in lt expressionString gt Cannot handle bit selects and slices of Verilog registers Optio
98. a E X Extended mode enabled Keen 1 Atop p NAND 24 2 1 14 ModelSim Advanced Debugging ModelSim Windows Copyright 2002 Mentor Graphics Corporation L Notes The Dataflow window allows you to explore the physical connectivity of your design You can expand the view from process to process which allows you to see the drivers receivers of a particular signal net or register Use menu commands buttons on the toolbar or your mouse to expand the view of your design To expand with the mouse simply double click a signal register or process Depending on the item you click the view will expand to show the driving process and interconnect the reading process and interconnect or both ModelSim Advanced Debugging 1 21 December 2002 Review ModelSim Windows Alternatively you can select a signal register or net and use one of the toolbar buttons or menu commands As you expand a view the layout of the design may adjust to best show the connectivity You can quickly transverse through many components in your design To help mark the path the items you have expanded are marked highlighted in green The Embedded Wave Viewer The embedded wave viewer closely resembles in appearance and operation the stand alone Wave window Access the embedded wave viewer by using the View gt Show Wave command or clicking on the wave viewer icon in the dataflow window When you place and move cursors in the embedded wav
99. a breakpoint in the first FLI function that is called by your application code An easy way to set an entry point is to put a call to ModelSim Advanced Debugging 7 45 December 2002 FLI and C Models mti_GetProduct as the first executable statement in your application code Then after vsim has been loaded into the debugger set a breakpoint in this function Once you have set the breakpoint run vsim with the usual arguments e g run c top On HP UX you might see some warning messages that vsim doesn t have debugging information available This is normal If you are using Exceed to access an HP machine it is recommended that you run vsim in command line or batch mode because the NT machine might hang if you run vsim in GUI mode Click on the go button or use F5 to execute vsim in wdb When the breakpoint is reached the shared library containing your application code has been loaded In some debuggers you must use the share command to load the FLI application s symbols Again on HP UX you might see a warning about not finding dld flags in the object file This warning can be ignored You should see a list of libraries loaded into the debugger It should include the library for your FLI application Alternatively you use share to load only a single library At this point all of the FLI application s symbols should be visible You can now set breakpoints in and single step through your FLI application code 7 46 ModelS
100. ab8 math part6_compare_2 do Part 7 steps 1 6 labs lab8 math math opt mp2 verilog gate do type quit sim before going to next script Part 8 steps 1 6 labs lab8 math math opt mp2 verilog gate fast do type quit sim when done Part 10 steps 1 4 labs lab8 math sim_generic do 8 46 ModelSim Advanced Debugging December 2002 Module 9 Debug Detective Objectives Upon completion of this module you will be able to Describe the primary functions of Debug Detective List and describe block diagrams state diagrams and flow charts Locate the descriptions of the Debug Detective GUI short cuts Demonstrate the use of strokes within Debug Detective windows Demonstrate opening Debug Detective parent and child design views Add and remove signals to and from the ModelSim Wave and List windows Add and remove simulation probes Report and manipulate breakpoints from Debug Detective windows Run the simulator with Debug Detective capabilities active Animate state diagrams ModelSim Advanced Debugging 9 1 December 2002 Debug Detective Module Overview Module Overview In this module we will discuss Debug Detective Design Analysis o 9 9 9 9 9 9 9 9 9 9 Debug Detective ModelSim Debug Detective Functions Debug Detective User Interface Simulation Toolbar Highlighting Reporting Signal Information Adding Removing Simulation Probes Manipulating Reporting on Breakpoints Setting Simulator Environment Running the
101. ad Example attribute foreign of mult architecture is mult init mult so parameter the parameter is optional used by the initialization function ModelSim searches for the object files in the following order e MGC_WD lt so gt or lt so gt If MGC WD is not set then it will use Note so files are shared object files e lt so gt the path specified in the Foreign attribute string above e within LD LIBRARY PATH SHLIB PATH on HP only recommended e MGC HOME lib so e MODEL TECH so e MODEL TECH so 7 12 ModelSim Advanced Debugging FLI and C Models Copyright 2002 Mentor Graphics Corporation Notes The FOREIGN attribute string contains 3 parts For the following declaration ATTRIBUTE foreign OF arch name ARCHITECTURE IS app init app so parameter the attribute parses this way app init The name of the initialization function for this architecture This part is required See The C initialization function section in the Foreign Language Interface Reference Manual 7 24 ModelSim Advanced Debugging December 2002 FLI and C Models app so The so file extension is the extension for the shared object file ModelSim does a search for these types of files in order to parse foreign attributes strings The path to the shared object file to load This part is required See Location of shared object files section in the Foreign La
102. al therefor the function always uses the region set by the latest call to mti_FirstSignal mti_NextSignal returns a handle to the next signal in the region set by the latest call to mti_NextSignal Function returns NULL if there are no more signals mti_FirstLowerRegion returns a handle to the first subregion of the specified region mti NextRegion can be used to get the subsequent subregions of the specified region The function can be used to get the subsequent subregions of the specified region mti_NextRegion gets the next region at the same level as a region Returns a handle to the next VHDL or Verilog region at the same level of hierarchy as the specified VHDL or Verilog region The function returns NULL if there are no more regions at this level If the next reg id is a handle to a Verilog region then it can be used with PLI functions to obtain information about or access objects in the Verilog region mti FirstProcess gets the first VHDL process in a region Returns a handle to the first process in the specified region Can be used to get the subsequent processes in the specified region mti FirstProcess resets the region used by previous calls to mti FirstProcess and mti NextProcess therefor the function always uses the region set by the latest call to mti FirstProcess mti NextProcess gets the next VHDL process in a region Returns a handle to the next process in the region set by the latest call to mti FirstProce
103. als Structure Find searching for values locating cursors Various windows Combining items in List windows Wave and List windows Combining items in Wave window Sorting HDL items All windows except Dataflow Multiple window copies All windows except Main window Menu tear off All windows Customizing menus and buttons All windows Tree window hierarchical view Structure Signals Variables Wave 1 4 ModelSim Advanced Debugging Model Sim Windows Copyright 2002 Mentor Graphics Corporation Notes For an in depth discussion on each ModelSim window review the Graphical Interface chapter in the ModelSim User Manual 1 6 ModelSim Advanced Debugging December 2002 Review ModelSim Windows Main Window Main Window ModelSim gt prompt before design is loaded e View Help edit libraries edit File Edit View Compile Simulate Tools Debug Window Help source code create projects 2 Se Hf mahda Be e Hu VSIM gt prompt after design is ogic_1164 body T ModelSim SE PLUS 5 6 with Debug Detective Loading C Modeltech_5 6 win32 modelsim_ lib util body l oad ed Loading C Modeltech_5 6 win32 verilog vl types body n P ae Loading work top only e Transcribes simulator activity Loading work proc Loading work cache Commands Loading work std logic util body Loading work cache set only Messages Loading work memory lef Assertio
104. alues are used in the enumeration type then 4 bytes must be used to store the values otherwise 1 byte should be used mti_CreateSignal creates a new VHDL signal If the name is not NULL then the signal will appear in the Signals window All signal names that do not begin with a are converted to lowercase Signal names starting and ending with are treated as VHDL extended identifiers and are used unchanged mti_CreateSignal 0 allows you to create a signal with an illegal VHDL name This might be useful for integrators who provide shared libraries for use by end customers and is an easy way to avoid potential name conflicts with HDL signals The following naming style is recommended lt PREF IX name Where PREFIX is 3 or 4 characters that denote your software to avoid name conflicts with other integration software and name is the name of the signal Enclosing the entire name in angle brackets makes it an illegal HDL name Do not use characters in the name that will cause Tcl parsing problems This includes spaces the path separator or square brackets and dollar signs If you must use these characters then use an escaped name by putting the backslash at both ends of the name mti_CreateProcess creates a new VHDL process If the name is not NULL then it will appear in the Process window otherwise it does not The specified function is called along with its parameter whenever the process executes and it exe
105. anced Debugging December 2002 Tcl Tk Overview 10 11 ec 99 Recall from the lecture that the main window widget is and subsequent levels are separated by a period indicating hierarchy Tk commands can be categorized into four groups Commands for creating and destroying widgets Commands used to communicate geometry management Commands associated with each widget within a particular hierarchy of an application Commands for communication between widgets other applications and data We will create our button widget interactively in the ModelSim transcript window The first step is to create the button b widget using the button command ModelSim button b1 text Run Script command do cor it do The text argument tells the Tk interpreter what to call the button widget and the command argument tells it what to do when the button is pressed After you hit lt Enter gt type the following at the ModelSim prompt ModelSim pack b1 side left This command tells the Tk interpreter where to place the button ModelSim Advanced Debugging 2 27 December 2002 Tcl Tk Overview f ModelSim SE PLUS 5 6 with Debug Detective Bl x File Edit View Compile Simulate Tools Debug Window Help 871 actual 999 dif 128 angle 88 x 000001000101 v 011011010000 cos 34 actual 36 dif 2 sin 872 actual 999 dif 127 angle 89 x 000000101001 v 011011010000 cos 20 actual 18 dif 2 sin 872 ac
106. ast fast slow slow fast 3 5 ModelSim Advanced Debugging Test Benches Notes ModelSim Advanced Debugging December 2002 medium low low low high Ease of Use Performance Level of Abstraction Notes most portable requires s w skills scripts and do files difficult to automate requires Copyright 2002 Mentor Graphics Corporation 3 5 Test Benches HDL Test Benches HDL Test Benches Most portable solution VHDL Fast execution Verilog instantiate the component uut adderN generic map N port map a gt a b gt b DETEN Obea ee a win e gt Gil sum gt sum esum i Ej Bs f d i f E cout gt cout module test_counter provide stimulus and check the result test process reg clk rst variable vector test record t vire 7 0 count variable found error boolean false begin counter 5 10 dut count clk rst for i in test patterns range loop vector test patterns i initial Clock generator apply the stimuls begin a lt vector a clk 0 b lt vector b i 10 forever 10 clk clk cao e voeren etor wait for the outputs to settle sns wait for 100 ns initial Test stimulus check the results begin if sum vector sum then rst 0 assert false report Sum is amp to string sum 5 rst i amp Expected amp to string vector sum 4 rst 0 found error true 5
107. at would otherwise be difficult in VHDL allows VHDL sub programs to be replaced by a C C function e Access to the internal state of the simulation for easy integration of third party tools To use the FLI we create a foreign architecture and compile it VHDL 87 and 93 define a mechanism for loading foreign architectures and subprograms e Attribute FOREIGN string e FOREIGN attribute declared in package STANDARD for VHDL 93 7 4 ModelSim Advanced Debugging FLI and C Models Copyright 2002 Mentor Graphics Corporation Notes The string value of the attribute is used to specify the name of a C initialization function and the name of an object file to load When the simulator elaborates the architecture the initialization function 1s called Parameters to the function include a list of ports and a list of generics See Mapping to VHDL data Types in the Foreign Language Interface Manual Declaring the FOREIGN String Starting with VHDL 93 the FOREIGN attribute is declared in package STANDARD With the 1987 version you need to declare the attribute yourself You can declare it in a separate package or you can declare it directly in the architecture This will also work with VHDL 93 ModelSim Advanced Debugging 7 5 December 2002 FLI and C Models The FOREIGN Attribute String The value of the FOREIGN attribute is a string containing three parts For the following declaration ATTRIBUTE forei
108. atas Comparison reached signal difference li mit at time 8070684 ps Found 100 differences New tab in main window opened for each dataset Open Multiple logfiles previously saved and VSIM 13 sim tst_pseu Z renamed Prefix Dataset Name e Examples Example sim top alu out ModelSim dataset open gold wlf view top alu out gold wlf opened as dataset gold golden top alu out ModelSim add wave 6 4 ModelSim Advanced Debugging Waveform Compare Copyright 2002 Mentor Graphics Corporation Notes Design signals and region names can be fully specified over multiple wlf files by using the dataset name as a prefix in the path Example sim top alu out view top alu out golden top alu out 6 4 ModelSim Advanced Debugging December 2002 Waveform Compare Managing Datasets Managing Datasets Use the Dataset Browser to view and manage your datasets View gt Datasets Main Window Dataset Browser ox Dame Joone Tuo reme E wave add View gold2 wif tst pseudo Simulation max sdf wave_add View test2 wilf Open Dataset Close Dataset Make Active Rename Dataset 6 5 ModelSim Advanced Debugging Waveform Compare Copyright 2002 Mentor Graphics Corporation Notes ModelSim Advanced Debugging December 2002 Waveform Compare Compare Datasets Using Waveform Compare Compare Datasets Using Waveform Com
109. ation Generic Mismatches More Useful vcom and vlog Commands 8 2 ModelSim Advanced Debugging Debugging Copyright 2002 Mentor Graphics Corporation Notes ModelSim Advanced Debugging December 2002 Debugging When to Debug When to Debug Not getting successful compilation e Code syntax errors e Library problems e Dependencies Not getting correct or expected simulation results Testbench issues Assert messages to main window Value Change Dump VCD compares Waveform compares List output differences ModelSim user interface has many powerful debugging capabilities 8 3 ModelSim Advanced Debugging Debugging Copyright 2002 Mentor Graphics Corporation Notes ModelSim Advanced Debugging December 2002 Debugging Debugging Tasks Debugging Tasks Detection Test Bench Symptoms Capture Store amp Analyze Data Possible Causes Window Cross Probing Backtracking Isolation Design Probing amp Control Virtuals amp TCL TK Resolution Verification 8 4 ModelSim Advanced Debugging Debugging Copyright 2002 Mentor Graphics Corporation Notes 8 4 ModelSim Advanced Debugging December 2002 Debugging Breakpoints Breakpoints Two types of breakpoints are supported e Breakpoints on lines of source code Click on line of code or use bp command bp filename lt line gt If filename and line number missing then existing breakpoints are disp
110. ation sim Compare the product and count out outputs from the two datasets Run the comparison What is the medium propagation delay difference for the product output between the two datasets What is the medium propagation delay difference for the count out output between the two datasets What is the propagation delay from data c input equal 7 to increment out output equal to 7 ModelSim Advanced Debugging December 2002 Debugging 5 Let s say that upon review of our design spec I can tolerate a 6 ns pin to pin Tco for the product output and an 8 ns pin to pin Tco for the count out output End the current waveform comparison compare end and start a new comparison with trailing edge tolerance tolT of 6 ns for product and 8 ns for count out We are only interested in trailing edge tolerances due to the RTL simulation being an edge triggered functional simulation while the gate level post P amp R SDF simulation has timing and propagation delays calculated in the paths and gates Disregarding the initial differences at t 0 when some bits are undefined were the differences in the product output filtered out Were the differences in the count out filtered out Continue to examine the comparison of other outputs and different trailing edge tolerances 6 End the comparison when you are completed Close the gold dataset and quit the current simu
111. ations using Tk The files we will use for this lab are cordic_core_rtl vhd and cor_it do The cordic_core_rtl vhd file contains the code that takes input values from vectors x and y performs sine and cosine calculations and adjustments on the inputs and outputs the angle and the difference The cor_it do file is a scripting file that contains Tcl commands and serves as the design s testbench Directions Creating a Tk Button to Run a Simulation Script 1 To set up the lab invoke ModelSim and change directory to the labs lab2 cordic core directory use the cd command or the File Change Directory menu 2 First we will create a work library and a logical mapping to it ModelSim gt vlib work ModelSim gt vmap work work 3 Next we will compile the file cordic_core_rtl vhd using the 93 switch ModelSim vcom 93 cordic_core_rtl vhd 4 Now we will load the design into the simulator memory ModelSim vsim cordic core 5 Once the design is loaded into memory we can run the Tcl script cor it do 2 24 ModelSim Advanced Debugging December 2002 Tcl Tk Overview VSIM gt do cor_it do Watch the ModelSim transcript window You may have to expand it horizontally and vertically in order to see the complete table You should see a table in the transcript window that shows angles in degrees from 0 to 90 along with corresponding input vectors actual and calculated values for sine and cosine and the differences
112. b exercise for the optimized design 1 The use of the LPM function Ipm mult in mult opt vhd requires the compilation of the RTL simulation models for the LPM library Within ModelSim you need to create an Ipm library and compile the 220pack vhd and 220model vhd VHDL files into this Ipm library The 220pack vhd and 220model vhd files reside in the labs lab8 math Ipmsim directory Use the vcom 87 switch when compiling these two files The LPM library must be compiled before the design files and testbench are compiled Compile the optimized design files adder opt vhd alu opt vhd count opt vhd fsm vhd increment opt vhd mult opt vhd math opt vhd in ModelSim Compile the testbench math opt tb vhd after compiling all the RTL design files 2 Simulate the testbench and create the golden waveform results file gold opt wlf 3 Compile the post P amp R design math_opt vho with ModelSim using the vcom 93 switch The math opt vho and math opt sdo files are located in ModelSim Advanced Debugging 8 37 December 2002 Debugging 10 8 38 the labs lab8 math sdf directory Don t forget about the VITAL library elements Simulate vsim the math opt tb vhd testbench with the SDF maximum timing switch sdfmax along with specifying the correct instance to apply to the SDF file Use the name sim opt wlf for the results fle Open the ModelSim wave window add all top level signals from the testbench math opt tb
113. b8 math After changing the directory in ModelSim type vlib work in the ModelSim Main window 8 32 ModelSim Advanced Debugging December 2002 Debugging to create the working library Next compile the design files adder vhd alu vhd count vhd fsm vhd increment vhd mult vhd and math vhd and the testbench math tb vhd 2 Simulate the testbench and create a golden waveform results file gold wlf ModelSim vsim wlf gold wlf t 100ps math tb VSIM add wave VSIM run all VSIM quit sim 3 The post P amp R netlist contains VITAL library elements that need to be compiled by ModelSim We need to create an alt vtl library and compile the alt vtl vhd and alt vtl cmp VHDL files into this alt vtl library The alt vtl vhd and alt vtl cmp files reside in the labs lab8 math vhdl93 vital v3 0 directory Use the veom 93 switch when compiling these two files Now compile the post P amp R design math vho in ModelSim using the vcom 93 switch The vho and sdo files were generated from Altera s MA X plus II tool targeting the ACEX EPIK50FC256 1 programmable device The math vho and math sdo files are located in the labs lab8 math sdf directory Recompile also the testbench math tb vhd 4 Simulate the math tb vhd testbench with the SDF maximum timing switch sdfmax Make sure to properly specify the correct instance to apply to the SDF file as you do so Apply the simulator resolution of 100 ps because this is the val
114. ce Things to Avoid Cont Coding for Performance Things to Avoid Cont Initializing constants in loops rather than statically defining them where they are declared Treat vectors as atomic avoid assigning to individual bits if possible e simulator can treat vector as one object rather than n Make sure to use the fast switch for Verilog designs 4 20 ModelSim Advanced Debugging Analyzing Performance Copyright 2002 Mentor Graphics Corporation Notes ModelSim Advanced Debugging 4 21 December 2002 Analyzing Performance Coding for Performance Things to Avoid Cont Coding for Performance Things to Avoid Cont Make sure you don t have too many signals in your sensitivity list e break up processes into multiple ones with separate sensitivity lists begin procedure E A B procedure F C D inefficient process A B C D end process inefficient 2x Faster efficient 1 process A begin procedure E A B end process efficient 1 efficient 2 process C begin procedure F C D end process efficient 2 B D 4 21 ModelSim Advanced Debugging Analyzing Performance Notes 4 22 Copyright 2002 Mentor Graphics Corporation ModelSim Advanced Debugging December 2002 Analyzing Performance Faster Verilog Simulations Faster Verilog Simulations Use the fast switch for best performance Verilog
115. cteccton dene nerse rra eE e e ES E N E NRE 4 13 Graphical VIG S se aret uA ael test ELA UD RA Dp MER e E ACIE 4 14 Understanding In and BIe t soc dee tbt ebbe tn feta at oak 4 15 Example ect nns crete s a Me sicot apr etie doc Abos tuf nabs Kb aa 4 16 ModelSim Advanced Debugging December 2002 Table of Contents TABLE OF CONTENTS Cont Coding for Performance Things to Avoid cccececccceeescceeeeeneeeeeeteeeeeensnes 4 20 Paster Verilog Similan coin edet epc meo aeea tane eas CH I ao rA e nee 4 23 Verilop Grate We vel Zahl te ot ectetur iate tUe 4 24 ylos Commands zii ceti dachte ee E doen e iod OR ee d nemi 4 26 vlog Commands for Gate Level Simulation sess 4 28 vlog Commands for RTL Simulation essere 4 30 vlog Commands MR 4 31 yeon Commands aeree r rosse t host E N EEEE E red eenean 4 32 Usine Elaboration Piles eana a EEE E E EE 4 33 General Performance I8SU6S a e thi aah ote aeee blue ee d Db haeie 4 35 SUMMAATY ereas enipe e E ea E ea E e EES EA TEN e ONE E EEEE E EEO EPERE E GEENEN 4 37 Lab 4 Analyzing Performing 5iooeo eiecit et d tpop eer ER Uie Pete Eget edes 4 38 Module 5 Virtual Sisal eee S 1 hs veniae ieu EE 5 2 WAV al DISCUS s S D ve E EN encase ten ee Gaon dons uda P at e UE 5 3 WU aS IE C P PT T 5 4 Virtual REGIONS ect e teet bt b centre eee ot bet ecce Nem Mte deat clade vcr eer 5 9 Virtual EUBCUORBS cootra ttv utet do ddaedei simus ETEA
116. cuss Types of Test Benches Modeling Techniques for Each Test Bench Pros and Cons of Each Test Bench vgencomp VHDL Generics Signal Spy 9 9 9 9 3 2 ModelSim Advanced Debugging Test Benches Copyright 2002 Mentor Graphics Corporation Notes 3 2 ModelSim Advanced Debugging December 2002 Test Benches Functions Functions Test Benches can provide the following functions 9 9 9 Stimulus Generation for Unit Under Test UUT Stimulus Application to Unit Under Test UUT Monitor of actual outputs of UUT Compare equivalence of actual outputs of UUT with expected outputs Assertion Violation for non equivalence between actual and expected outputs of UUT Stimulus Stimulus Monitor Data Set One or Many 3 3 ModelSim Advanced Debugging Test Benches Copyright 2002 Mentor Graphics Corporation Notes ModelSim Advanced Debugging 3 3 December 2002 Test Benches Implementation Implementation Test Bench functions may be implemented as any combination of the following e HDL C via FLI PLI Tcl Interactive GUI 3rd Party Testbench tools 3 4 ModelSim Advanced Debugging Test Benches Copyright 2002 Mentor Graphics Corporation Notes 3 4 ModelSim Advanced Debugging December 2002 Test Benches Comparison of Different Test Bench Methods Comparison of Different Test Bench Methods HDL C Tcl GUI 3rd Party medium hard easy easy medium f
117. cutes either at the time specified in a call to mti_ScheduleWakeup or whenever one of the signals to which it is sensitive changes If the process is created during the elaboration phase from inside of a foreign architecture instance then the process is automatically executed once at time zero after all signals have been initialized If the process is created either after elaboration is complete or from any other context such as from an initialization function that executes as a result of the loading of a foreign shared library by the foreign option to vsim then the process is not run automatically but must be ModelSim Advanced Debugging 7 21 December 2002 FLI and C Models scheduled or sensitized You are able to create a process with an illegal HDL name Refer to mti_CreateSignal for the rules on how to do this mti_CreateRegion creates anew VHDL region with the specified name under the specified parent region The name is converted to lower case unless it is an extended identifier If the name is NULL then the region is hidden If the parent region is NULL then the new region is not connected to the design hierarchy The new region can be created below either a VHDL region or a Verilog region The new region is of type accForeign and of fulltype accShadow see acc vhdl h If a region is created with no name or with no parent the returned handle to the region must be saved as there is no way to find the region by name or by
118. d 99 5 5 Hierarchical Profile F mentor training lab1 control vhd 87 19 4 F mentor training lab1 testring vhd 37 3 3 Samples 870 d aj Under E F mentor_training lab1 contral vhd 98 10 3 retrieve array vhd 35 6 3 F mentor_training lab1 control vhd 87 F mentor training lab1 arith_ste unsigndb vhd 58 2 2 L Fumantor uaningAati dh sv undandb dd F mentor_training lab1 arith_sre unsigndb vhd 222 E 2 LF mentor_training lab1 arith src unsigndb vhd 65 F mentor_training lab1 control vhd 130 2 2 Li perio arena abt faith stead F F mentor_training lab1 arith_stc unsigndb vhd 223 2 2 fore ay vhi F mentor training lab1 arith_stc unsigndb vhd 65 2 2 F mentor training l f sic unsigndb vhd 216 BEL lab1 arith src unsigndb vhd 189 ELeefieve array vhd 35 F mentor training lab1 arith_ste unsigndb vhd 216 F mentor training lab1 testring vhd 93 1 9 F mentor_training lab1 testring vhd 97 4 in 11 2 2 under F mentor_training lab1 control vhd 130 4 16 ModelSim Advanced Debugging Analyzing Performance Copyright 2002 Mentor Graphics Corporation Notes The 19 is made up by adding the time spent on this parent line of code plus the time spend under the functions that support this line In this case the simulation spent 4 in the line and 15 under in 3 different functions ModelSim Advanced Debugging 4 17 December 2002 Analyzing Performance Example Cont
119. daryName mti GetProcessName These are a few examples of C routines called by ModelSim to traverse the hierarchy 7 9 ModelSim Advanced Debugging FLI and C Models Copyright 2002 Mentor Graphics Corporation Notes mti GetTopRegion returns the region ID of the first top level region in the design hierarchy This function can be used to get additional top level regions Top level regions are VHDL architectures and packages and Verilog modules If the region id is a handle to a Verilog region then it can be used with PLI functions to obtain information about and access objects in the Verilog region mti GetCurrentRegion gets the current elaboration region during elaboration or the current environment during simulation During elaboration this function returns the region ID of the current elaboration region During simulation the function returns the region ID of the current environment set by the environment command The region ID returned can be either a VHDL region or a Verilog ModelSim Advanced Debugging 7 13 December 2002 FLI and C Models region A handle to a Verilog region can be used with PLI functions to obtain information about or access objects in the Verilog region mti_FirstSignal returns a handle to the first VHDL signal in the specified region Can be used to get the subsequent VHDL signals in the specified region mti_FirstSignal resets the region used by previous calls to mti_FirstSignal and mti_NextSign
120. delSim Advanced Debugging Analyzing Performance Copyright 2002 Mentor Graphics Corporation Notes 4 6 ModelSim Advanced Debugging December 2002 Analyzing Performance Exclusion Exclusion A Green X denotes lines has been excluded from execution a source testnaghd TTE File Edit View Tools Debug Window f 5 i zm ad IN mem m 1 esa tB S wissisimime ni x wrb lt 0 E csb lt 1 switch lt 0000 IF test true THEN FOR data value IN O0 TO 11 LOOP mf switch lt conv std logic vector data value WAIT FOR 100 NS wrb lt 0 csb xe 0t WAIT FOR 100 NS wrb lt 1 WAIT FOR 200 NS WAIT FOR 200000 NS END LOOP SSS Imi Lm 1 Cok 0 readonl 5 4 7 ModelSim Advanced Debugging Analyzing Performance Copyright 2002 Mentor Graphics Corporation Notes ModelSim Advanced Debugging December 2002 Analyzing Performance Managing Coverage Data Managing Coverage Data Clearing Code Coverage from Previous Simulations e All line number execution count data is reset coverage clear Creating Coverage Reports e Textual output of coverage statistics coverage report file lt filename gt Reloading Coverage Data from Previous Reports e Gather statistics from multiple simulation runs into a single report e Merge coverage results using command line coverage reload filename incremental keep 4 8 ModelSim Advanc
121. delSim offers the capability to do mixed language simulation This could be any mixture of VHDL and Verilog design files testbenches and libraries Many people like to use Verilog gate level simulation due to faster runtimes vs VHDL gate level simulations using VITAL models In this exercise we will examine the steps involved with this form of mixed language simulation We will use the VHDL testbench math opt tb vhd with a Verilog gate level netlist math opt vo SDF timing file math opt sdo and Verilog UDP and cell primitives alt max2 vo The vo and sdo files were generated from Altera s MA X plus II tool targeting the ACEX EPIK50FC256 1 programmable device The post P amp R Verilog netlist contains Verilog cell library elements that need to be compiled by ModelSim We need to create an altera library and compile the alt max2 vo file into this altera library The alt max2 vo file resides in the labs lab8 math sdf directory and must be compiled before the design file and testbench are compiled ModelSim Advanced Debugging 8 39 December 2002 Debugging 8 40 Create an altera library Compile the Verilog gate level cell primatives alt_max2 vo into the altera library Create the work library Compile the post P amp R Verilog netlist math opt vo into the work library The math opt vo file is located in the labs lab8 math sdf directory Compile the testbench math opt tb vhd into the work library The math opt
122. e default NH 2 5 ni x File Edit Cursor Zoom Compare Bookmark Format Window m Qi Se e go p D 9 qw i oH Start Comp zi 4 i aa Ae de 3 Compariso Run Comparison End Comparison sim tst_pseudo cl sim tst_pseudo re sim tst_pseudo e sim tst_pseudo st sim tst_pseudo dd compare tst_psel compare tst_psel 3909496 ps to 3910402 ps Ai 6 16 ModelSim Advanced Debugging Waveform Compare Copyright 2002 Mentor Graphics Corporation Notes 6 16 ModelSim Advanced Debugging December 2002 Waveform Compare Comparing Hierarchical and Flattened Designs Comparing Hierarchical and Flattened Designs Y Problem Hierarchical RTL and flattened synthesis designs may have some differences e Different hierarchies e Different signal names e Buses broken down into 1 bit signals at the gate level design Y Solution Use the compare add command when e Hierarchy is different in the test design and the reference design Specify which region path in the test design corresponds to that in the reference design e Flattened design causes test signal names to be different from the reference signal names Specify which signal in the test design corresponds to which signal in the reference design e Buses have been bit blasted Rebuild the bus in the test design to look at differences from one bus to another compare add rebuild 6
123. e between the graphical representations animation and the simulation environment ModelSim Advanced Debugging 9 5 December 2002 Debug Detective Debug Detective Introduction Debug Detective Introduction Diagrams rendered from ModelSim Source Structure Workspace or Wave windows In memory rendering No Save Print export etc when using snap on LEXETCEUECECE E GNEMMRAN 30333 3366 Provides most existing simulation cross probing and animation capabilities Control simulation from laid Graphical view and ModelSim directly jan ompraais ane 3 T np lolx Optionally specify diagram type for each level Cross Probe to from Fb Ed are Bockmak Format View Windov SHS B IA eri RAJA i R EA Isic CE E E Un la ModelSim Windows I 2 JEL Si EP EL OD C XD ET 6 EF bo ba M M ten tad oa d Simulation lime 10150 4 FM neto 1747 ns 9 5 e ModelSim Advanced Debugging Debug Detective Overview Copyright 2002 Mentor Graphics Corporation Li LI Notes Notice the different colored states that appear in the State Diagram window This is a result of animation and stepping through your simulation The block diagram will be discussed in more detail later in this module Notice that each of the windows of the graphic representation have additional control buttons These are to control the simulation and animation
124. e Structure window and Signals window are linked Change signals view by clicking on a different region in the Structure window Selecting HDL item types to view The View gt Filter menu selection allows you to specify which HDL items are shown in the Signals window Multiple options can be selected Forcing signal and net values The Edit gt Force command displays a dialog box that allows you to apply stimulus to the selected signal or net Multiple signals can be selected and forced The force dialog box remains open until all signals are either forced skipped or until the dialog box is closed To cancel a force command use the Edit NoForce command or issue the force command from the command line prompt ModelSim Advanced Debugging 1 19 December 2002 Review ModelSim Windows Process Window Process Window FIG process File Edit View Window Ready H SSIGNHTS top m Ready HASSIGNHIB top m Ready line 34 top c s3 Ready line 32 top c s3 Read line 34 top c s2 Read line 34 top c sl Read line 32 top c sl Ready line 34 top c s Ready line 32 top c s Ready HASSIGNH20 2 top c Ready HASSIGNH2ORT top c Ready HASSIGNH20 top c lt Ready gt HASSIGNHIS T top c Active Processes situ 1 13 ModelSim Advanced Debugging ModelSim Windows Notes Active In Region Processes Dragand Drop e Place all variables of process into anot
125. e math opt vo file is located in the labs lab8 math sdf directory Compile the testbench math opt tb vhd into the work library The math opt tb vhd file is located in the labs lab8 math src directory Simulate vsim the testbench math opt tb with the SDF maximum timing switch sdfmax along with specifying the correct instance to apply to the SDF file The SDF file math opt sdo is located in the labs lab8 math sdf directory You will need to specify search library paths L switches for the altera library and the work library to allow ModelSim to find the Verilog cell primitives located in the altera library Open the ModelSim wave window add all top level signals from the testbench math tb Turn on the performance profiler profile on and run the simulation for 5 13 us time run 5 13 us How long was the ModelSim runtime for the Verilog gate level SDF simulation move the decimal point 6 places to get the number of seconds Is this runtime less than what you observed in the non optimized Verilog design How much slower or faster was the optimized Verilog runtime vs non optimized Verilog Quit ModelSim when completed quit f ModelSim Advanced Debugging December 2002 Debugging Part 9 Batch Simulation With Elaboration File In this exercise we will generate an elaboration file and use this file as source for a batch simulation The ModelSim compiler generates a library format that is
126. e of the unknown signal ModelSim Advanced Debugging December 2002 Review ModelSim Windows Chase X using the Dataflow window Now we will trace the cause of an unknown using the Dataflow window 1 Use the updated Dataflow window to find the root cause of the unknown on t out Select t out in the Wave window and drag it into the Dataflow window Add a cursor to the Wave window Slide the cursor so that the value of t_ out changes values Note the Dataflow window values change with the location of the active cursor 2 Place the cursor over the first unknown value for the _out signal at 65 ns Using the Dataflow window trace back to the cause of the X on _out by double clicking the test input strength X of the NAND 24 gate Next double click the test2 input strength X of the NAND 22 gate Notice there is a HiZ and a 1 on the inputs of NAND 23 that result in an X unknown Select the NAND 23 gate in the Dataflow window and notice the Source window updates to the line of code representing this NAND gate NAND A E Y A B Y 0 0 1 0 1 1 0 X 1 0 Z 1 1 0 1 1 1 0 1 X X I Z X 3 Clear the Dataflow window using the menu Edit gt Erase all Next select t out in the Wave window and drag it into the Dataflow window Click on the output signal t out and use the RMB to select Chase X from the menu Notice that the Dataflow window shows the path to the source of the unknown Th
127. e window the signal values update in the Dataflow pane Another scenario is to select a process in the Dataflow pane which automatically adds all the signals attached in the process into the wave viewer pane You can find items by name by selecting Edit gt Find Symbol Mapping An interesting factoid useful for those engineers who want to create their own symbols The Dataflow window has built in mappings for all Verilog primitives For components other than Verilog primitives you can define a mapping between processes and built in symbols This is done through a file containing name pairs one per line where the first name is the concatenation of the design unit and process names DUname Processname and the second name is the name of a built in symbol For example xorg only pl XOR org only pl OR andg only pl AND 1 22 ModelSim Advanced Debugging December 2002 Review ModelSim Windows Entities and modules are mapped the same way AND2 AND a 2 input AND gate Note that for primitive gate symbols pin mapping is automatic User defined symbols You can also define your own symbols using an ASCII symbol library file format for defining symbol shapes This capability is made possible by Concept Engineering s Nlview M widget Symlib format For specific details on this widget go to www model com products documentation nlviewSymlib html or read the ModelSim User s Manual ModelSim Advanced Debugging 1 23 December 2002
128. ecause the method used is statistical it is not necessary to run the simulation for the complete during Normally 3000 to 4000 samples is enough to determine what is happening this means that the simulation only has to be run for between 30 and 60 seconds ModelSim Advanced Debugging 4 11 December 2002 Analyzing Performance Profile On Profile On Turn on the Profiler prior to running the simulation profile on M ModelSim SE PLUS 5 6 with Debug Detective In File Edit View Compile Simulate Tools Debug Window Help Se SB E w v i08 M aveform Compare gt i SS ERRAT TT eae t ringbuf test_ringbuf test_r Profile n ring inst ringbuf rtl Source Coverage a Breakpoints Profile Off MM Package textio MM Package std logic unsigned View hierarchical profile Execute Macro BE Package std logic arith ODE eer View ranked profile BM Package std logic 1154 Tcl Debugger Clear Profile Data B Package standard TelPro Debugger Options Edit Preferences em Save Preferences Project profile Now Ons Delta 0 sim test_ringbuf Build A 4 11 ModelSim Advanced Debugging Analyzing Performance Copyright 2002 Mentor Graphics Corporation Notes 4 12 ModelSim Advanced Debugging December 2002 Analyzing Performance Taking Samples Taking Samples im ModelSim SE PLUS 5 6 with Debug Detective 0 abn hgh tt test ringbuf tes
129. ed Debugging Analyzing Performance Copyright 2002 Mentor Graphics Corporation Notes 4 8 ModelSim Advanced Debugging December 2002 Analyzing Performance Merging Coverage Report GUI Merging Coverage Report GUI Merge results from two or more analyses using the GUI e From the coverage_summary window e File gt Open gt Coverage gt Merge Coverage Merge Coverage Reports x Coverage File Name To Read From 1 Browse Rules To Use During Merge Clear out accumulated coverage data v Keep coverage data for files not in the current design OK Cancel e Specify one or more saved coverage reports to merge into the current analysis e Clear current analysis coverage stats before merging into the saved reports e Include coverage data for all merged files even if not part of the current design 4 9 ModelSim Advanced Debugging Analyzing Performance Copyright 2002 Mentor Graphics Corporation Notes ModelSim Advanced Debugging December 2002 Analyzing Performance Performance Analyzer Performance Analyzer VHDL Verilog Mixed C Behavioral Register Transfer Level and Gates Uncovers The Impact of Non Accelerated VITAL Library Cells Un needed Signals On Sensitivity List Un necessary Testbench Code e Architectural Bottlenecks Statistical Profiler e Shows Of Run Time Per Line e 100 Samples per second simulation runtime default samp
130. ed generic ded e Select Edit Change p une e Variable Name A ipd 000 000 000 000 000 00 VHDL Generic Name e Value Appropriate data type sim top c amp AL WAYS 44 No quotation marks for arrays Variable Name Value Ehange Cancel 3 12 ModelSim Advanced Debugging Test Benches Copyright 2002 Mentor Graphics Corporation Notes 3 12 ModelSim Advanced Debugging December 2002 Test Benches C Test Benches C Test Benches Microsoft Developer Studio tester c B Eie Edt View Inset Project Build Toole Window Heb lal x 8 c me s ew BS Mlowe I HOS a a s e amp i amp n Most flexible solution e can do virtually anything in C Hardest to implement Least portable This procedure is called by the simulator as a result of an mti_ScheduleWakeup call Its purpose is to process all drive test data specified for the current timestep It schedules drivers for drive points by calling mti ScheduleDriver For test points it reads the port values by calling either nti GetSignalValue or nti Get rraySignalValue It then compares the current values with the expected values and prints an error message if they don t match kK X X X X static void test value proc inst rec ptr ip char actual val MAX PORT WIDTH char buf 100 char expected val MAX PORT WIDTH H har eis array val e especially for VHDL int portnum i wid
131. en NULL is returned The returned handle can be freed with mti free The driver remains in effect even if the handle is freed The first driver in the signal s driver list is returned so you cannot tell which particular driver it is For this reason it is not recommended to use this command to drive values from an FLI application Use this function to determine whether or not a signal has any drivers mti FindPort finds a port signal in a port interface list The search is not case sensitive 7 16 ModelSim Advanced Debugging December 2002 FLI and C Models mti_FindSignal finds a VHDL signal by name The signal name can be either a full hierarchical name or a relative name A relative name is relative to the current region set by the simulator s environment command The default current region is the foreign architecture region during elaboration and the top level region after elaboration is complete The name of a package signal must contain the name of the package During elaboration signals in design units that have not yet been instantiated will not be found by the function If the specified name is for an input port that has been collapsed due to optimizations the handle that is returned is a handle to the actual signal connected to that port This command can not be used to find either sub elements that are composites or multi dimensional array sub elements mti_FindVar finds a VHDL variable generic or constant by name
132. en cd tb Meese toos Mie dat Sa Gr bc ER T taf eps 1 26 WAVE AVdBdOo Wee E niedis sbdeo epe out leo S Yt UE er Ur et tam Ed Duft Ere eae 1 28 Eist WHdOW iouiosebcxiie loo basado pe detti t be ec Det Ce bound 1 32 Modelsiti Help 4 niet fee Re octo eve Debe er tst cr eleva el nae 1 35 SUMMAA aceite No dose e opu OR ON beat lotte Ad oe Mo etai donet deb Be dide eso d Rear aas 1 36 Lab 1 Simulation and Debugging with the Dataflow Window 1 37 ModelSim Advanced Debugging vii December 2002 Table of Contents TABLE OF CONTENTS Cont Module 2 WOT OVervIGW scssstescsssossssssssssocsssosescsossissssesnesisssossorosssesossissdsessrssessssesssssesttsss iiss 2 1 Module Overiew a ee en Reet tette 2 2 My el DR esce eedvet ree cess sues Co b dr ndo rad tosta eau et Pc t eee eua 2 3 dE ES ciu dT Cm x eT TT 2 4 dae asl 2 5 To Omas s e ed Eo foe On tse miei tst Cees een Renee 2 6 Basie Eel Syntax Seo oecescu perte dre sis incor ede med etl Fast Meath dads dvi n eivai e 2 7 deum ARIA ISS MR C 2 8 Command Substitution oos tp RE Cra Pei e cie 2 9 Ur M C E 2 10 METI PC Seats te aon tcd eco stie est eret nareca ue te dti io cl uentus 2 11 Control SEIEUCIUEBS 13 eset ome tet estet tO EO i i ene eld E NR EEER UE 2 12 Simulation Commands a aces ideo FE EIE Tre retine amer 2 13 Tel Script Example eorr sats e stet asad iE e rir a FE Due Fr hase rw de d ed a RR 2
133. en specify compare method 6 11 ModelSim Advanced Debugging Waveform Compare Copyright 2002 Mentor Graphics Corporation L Notes ModelSim Advanced Debugging December 2002 6 11 Waveform Compare Add Signals Regions or Clocks Add Signals Regions or Clocks uJ ModelSim SE PLUS 5 6 with Debug Detective File Edit View Compile Simulate Tools Debug Window es Bre a w _ ist pseudo reform Compare gt Source Coverage Breakpoints Profile r Execute Macro Tcl Debugger TelPro Debugger Edit Preferences Save Preferences 4 Project Library sim gold compare 6 12 ModelSim Advanced Debugging Waveform Compare Notes 6 12 Options gt Help E TA Start Comparison Comparison Wizard Bun Comparison be run End Comparison Compare by Signal Options Compare by Region Differences id Rules Reload Copyright 2002 Mentor Graphics Corporation ModelSim Advanced Debugging December 2002 Waveform Compare Differences Differences lolx File Edt Ourso Zoom Compas Bookmark Format Andoa SHS SRB RA He QQ QQw Er i EUM ga hee i og The diff designation in the Values column relates to the position of the cursor compere tst_peeuda match compera tat_ceeuda match compere tst_pseude mo ch compere Isl psesida metch f cL
134. end executing this single line of VHDL code The under percentage in this case 9 is the amount of time that has been spent executing this line of VHDL code plus any function or procedure that this line calls In this case the 9 would include the time spent within the dlys function A simple subtraction of the in value from the under value tells us how much time was spent just supporting this line ModelSim Advanced Debugging 4 15 December 2002 Analyzing Performance Example Example Ranked Output Ranked Profile ioj x Samples 870 4 x nz 2l e W Hierarchical Output Nme Under lta Fierachical Pioli BE F mentor_training lab1 arith_src unsigndb vhd 64 11 11 fal F mentor_training labl arith_stc unsigndb vhd 189 7 7 Samples 870 oa x Under z e g F mentor_training lab1 arith_stc unsigndb vhd 216 6 6 store_array vhd 39 12 5 F mentor training lab1 testring vhd 99 5 5 F mentor training lab1 control vhd 87 13 4 E F mentor _taining labt control vhd 87 F mentor_training lab1 testring vhd 97 3 3 F mentor_training labl arith_stc unsigndb pad F mentor_training lab1 control vhd 38 0 3 F mentor_training labl arilh src upsfidb vhde5 2 i vhd vm j n ee ee i e 3 F mentor_training lab1 aritbA fc unsigndb vhd 58 F 4mentor_training lab1 arith_ste unsigndb vhd 58 2 2 F mentor_training lab1 arith_stc unsigndb vhd 222 2 2 Bl store aray vhd 33 F mentor training lab1 control
135. er 2002 Review ModelSim Windows Add HDL items to the List window as follows e Drag and drop e Main window command line You may add items using a List window format file but you must first save a format file for the design you are simulating The saved file can then be used as a DO file Add HDL items to your List window Edit and format the items to create the view you want e Save the format file start with a blank List window and run the DO file in one of two ways o From the command line do my list format o Select File gt Load from the window menu You may also edit and format HDL items in the List window To edit Select the item s label at the top of the List window or one of its values from the listing Move copy or remove the item by selecting commands from the List window Edit menu You can also click drag to move items within the window To format an item select the item s label at the top of the List window or one of its values from the listing Select View gt Signal Properties from the List window A List Signals Properties dialog box appears which allows you to set the item s label label width triggering and radix Saving List window data to a file Select File gt Write List in the List window to save the data in either tabular events or TSSI format ModelSim Advanced Debugging 1 33 December 2002 Review ModelSim Windows Tabular writes a text file that looks like the window lis
136. er 2002 Tcl Tk Overview Basic Tcl Syntax Basic Tcl Syntax Tcl scripts are made up of commands Separate commands by newlines or semicolons Each command consists of one or more words separated by spaces Commands all have the same basic form set inc 11 dataset open test2 wlf test force clk 1 10 O 20 The following example has four words one command followed by three arguments expr 4 3 This command computes the sum of 4 and 3 and returns 7 All Tcl commands return results Empty string returned if a command has no meaningful result Reference Tcl Primer http www scriptics com advocacy primer html Slides 3 7 3 13 2 7 ModelSim Advanced Debugging Tcl Tk Overview Copyright 2002 Mentor Graphics Corporation Notes ModelSim Advanced Debugging December 2002 Tcl Tk Overview Tcl Variables Tcl Variables Tcl enables you to store values in variables e The set command is used to read and write variables e set x 64 The command returns the new value of the variable e set x Reads the value of a variable by invoking set with only a single argument e A variable is created automatically the first time it is set Tcl variables don t have types Any variable can hold any value e Use variable substitution to use the value of a variable in a command expr x 7 The command adds the value of the variable to seven 2 8 ModelSim Advanced Debugging Tcl Tk Overview Copyrigh
137. er to mti_CreateProcess is the process name to create this is the one with the problem The second parameter is the name of the C function to call when the process is scheduled So this is the part of the C code that called mti_GetSignalValue when it crashed 17 Now search down the source file for the function named evalBust It is at line 150 If you look a couple lines down in the function you see it calls mti GetSignalValue Whenever an FLI object calls one of the FLI interface functions functions that start with mti and that FLI interface function crashes there is a good chance that one of the parameters is wrong In this case mti GetSignalValue only takes one parameter and that is a mtiSignalIDT pointer for the signal whose value it is to get 18 The parameter is ip which is the instance pointer to the whole data structure used by the FLI code If you look down a line there is a print statement that is trying to print the total This parameter to mti GetSignalValue should really be a pointer to the signal value which is ip Total not ip That is the bug 19 Fix the C code by editing line 155 of testbench error c with the following val mti GetSignalValue ip Total If you are on a Unix System comment out line 154 of testbench_error c ip void 1 Quit the simulator quit sim if necessary and recompile and relink testbench_error c Reload the simulator vsim testbench Run the simulator
138. erview fe ModelSim SE PLUS 5 6a me x File Edit View Compile Simulate Tools Window Help Se SBM a 10x tt ERROR invalid command name add button Error in macro C Advanced_ModelSimLab_dat a BBXLabsMab3 cordic coresopen close button t El Ee Mi work c line 36 asil vital2000 invalid command name add button while executing add button 0 Library ModelSim E Run Script lt No Design Loaded gt lt No Context gt 4 3 Let s create a simple procedure called add button which will create the Open Close button in the lower right hand corner of the ModelSim window Let s open the Tcl source file and add our procedure Invoke notepad at the ModelSim prompt Jill modelsim fib Hn ModelSim notepad open close button tcl 4 Look towards the bottom of the file You will see a comment telling you where to add the procedure Uncomment the lines between the dashed lines and put your procedure there 5 First we will declare the procedure as follows proc add button void Remember that the procedure body is written within curly braces 6 Recall that a button widget in Tk is created by the button command Create a button called b2 and place it in the footer section of the window For example make footer the parent and b2 the child Separate the hierarchy with a period Remember from the lecture that the top level of the hierarchy is designated as a period and periods
139. eted Do not quit ModelSim Part 8 Optimized Gate Level SDF Simulation With a VHDL Testbench This exercise is identical to part 7 except we will compile the optimized Verilog gate level libraries alt max2 vo with the vlog fast switch When compiling Verilog gate level designs it is recommended to Compile the cell library alt max2 vo using fast Compile the device under test math opt vo without fast Compile the testbench math opt tb vhd without fast Create separate work directories for the cell library and the rest of the design Note Do not follow this recommendation when the testbench has hierarchical references in the cell library Optimizing the library alone would result in unresolved references In such a case compile the library design and testbench with fast in one invocation of the compiler The hierarchical reference cells are then not optimized In this exercise there are no hierarchical references in the testbench so we will follow the above recommendations 1 Compile the Verilog gate level cell primatives alt max2 vo into the altera library using the fast switch Enable access to internal registers and nets by using the acc rn switch with vlog ModelSim Advanced Debugging 8 41 December 2002 Debugging 8 42 The alt max2 vo file resides in the labs lab8 math sdf directory Create the work library Compile the post P amp R Verilog netlist math opt vo into the work library Th
140. ew memory of the required size is allocated and initialized to zero the entire content of the old memory is copied into the memory and a pointer to the new memory is returned Otherwise a pointer to the old memory is returned ModelSim Advanced Debugging 7 31 December 2002 FLI and C Models Any memory allocate by mti_Realloc is guaranteed to be checkpointed and restored just like memory allocated by mti_Malloc Memory allocated by mti_Realloc can be freed only by mti_Free Mti Realloc automatically checks for a NULL pointer In the case of an allocation error mti Realloc issues the following error message and aborts the simulation Memory allocation failure Please check your system for available memory and swap space 7 32 ModelSim Advanced Debugging December 2002 FLI and C Models Using Checkpoint and Restore With FLI Cont Using Checkpoint and Restore With FLI Cont Second Feature Explicit Functions to Save and Restore Data e Use to save pointers to data structures and IDs returned from FLI functions Pointers must be global not variables e Must explicitly save and restore your allocated memory structures if you choose not to use the provided MTI memory allocation functions Note The restores must be performed in the same order as the saves e The save and restore of data structures is maintained by simulation kernel e If user declares own data storage the user
141. f Hummingbird Communications Ltd HyperHelp is a trademark of Bristol Technology Inc Installshield is a registered trademark and service mark of InstallShield Corporation IBM PowerPC and RISC Systems 6000 are trademarks of International Business Machines Corporation I DEAS and UG Wiring are registered trademarks of Electronic Data Systems Corporation IKON is a trademark of Tahoma Technology IKOS and Voyager are registered trademarks of IKOS Systems Inc Imagen QMS QMS PS 820 Innovator and Real Time Rasterization are registered trademarks of MINOLTA QMS Inc imPRESS and UltraScript are trademarks of MINOLTA QMS Inc ImageGear is a registered trademark of AccuSoft Corporation Infineon TriCore and C165 are trademarks of Infineon Technologies AG Intel i960 i386 and i486 are registered trademarks of Intel Corporation Java and all Java based trademarks and logos are trademarks or registered trademarks of Sun Microsystems Inc Linux is a registered trademark of Linus Torvalds MemoryModeler MemMaker are trademarks of Denali Software Inc MIPS is a trademark of MIPS Technologies Inc MS DOS Windows 95 Windows 98 Windows 2000 and Windows NT are registered trademarks of Microsoft Corporation MULTI is a registered trademark of Green Hills Software Inc NEC and NEC EWS4800 are trademarks of NEC Corp Netscape is a trademark of Netscape Communications Corporation Novas Debussy and nWave are trademarks or registered t
142. ftyp testbench dut interface sdf testbench e The INSTANCE hierarchical path would now be testbench dut ramwrn_1 which is a valid region in this design You can also correct this from the GUI e Simulate Simulate SDF tab Add Apply to Region 8 20 ModelSim Advanced Debugging Debugging Copyright 2002 Mentor Graphics Corporation Notes 8 20 ModelSim Advanced Debugging December 2002 Debugging Generics Mismatches Generics Mismatches SDF errors can occur when there are generic mismatches in the SDF file and the instance being annotated Example 8 21 ModelSim Advanced Debugging Debugging Copyright 2002 Mentor Graphics Corporation s Notes ModelSim Advanced Debugging 8 21 December 2002 Debugging Missing Generics Missing Generics The Problem e The SDF file contains delay and timing constraint data for cell instances in the design e Each type of SDF timing construct is mapped to the name of a generic e When those specific generics do not exist in the cell instance an error will occur The Solution e Get the generics in the VITAL VHDL gate level model s to match the SDF file e This may require a change in the SDF file achange in the VITAL models or achange of which VITAL models are being referenced e There are no command line switches or ModelSim commands that can resolve the errors e ModelSim is merely reporting a mismatch in the exi
143. g December 2002 Analyzing Performance vlog Commands for Gate Level Simulation Cont vlog Commands for Gate Level Simulation Cont nocheck e Increase the performance of fast opt switch e Supported in ModelSim release 5 5b and newer e Only effective with Verilog gate level designs with fast opt nocheckCLUP Allows connectivity loops in a cell to be optimized nocheckDNET Allows both the port amp the delayed port created for negative setup hold to be used in the functional section of the cell nocheckOPRD Allows an output port to be read internally by the cell nocheckSUDP Allows a sequential UDP to drive another sequential UDP nocheckALL Enables all nocheck arguments 4 28 ModelSim Advanced Debugging Analyzing Performance Copyright 2002 Mentor Graphics Corporation Notes ModelSim Advanced Debugging 4 29 December 2002 Analyzing Performance vlog Commands for RTL Simulation vlog Commands for RTL Simulation Batch Mode can be optimized for Debug or Performance Object visibility e fast opt impacts design visibility e nets ports and registers may be unavailable for viewing e PLI access handles may be missing Use acc to retain access to specific design objects For maximum performance use only as needed acc lt spec gt module gt indicates all children of a module used to separate multiple modules spec can be p access to regi
144. ght blue circle top prw Nets registers variables and Htop pstib d t Atop prdy named events top ped r e Virtual items orange diamond top pdata Virtual signals busses and ENA functions a Htop stdy e Comparison items yellow triangle top saddr uuuuuuuu Htop sdata Comparison region and comparison grum signals Wave window panes resizable Pathname Pane e e Values Panes e Waveform Pane e Cursor Panes Left shows current simulation time and value for each cursor Ons to 1 us Z Right shows absolute value for each cursor and relative time between cursors 1 17 ModelSim Advanced Debugging ModelSim Windows Copyright 2002 Mentor Graphics Corporation a Notes Note Constants generics and parameters are not viewable in the List or Wave window Add HDL items to the wave window by doing one of the following e Drag and drop e Command line e Wave window format file 1 28 ModelSim Advanced Debugging December 2002 Review ModelSim Windows Dividers Dividing lines can be placed in the pathname and values window panes by selecting Insert gt Divider from the Wave window Dividers aid debugging by allowing you to separate signals from each other After you have added a divider you can change its name and size by clicking the RMB windows or middle mouse button unix and select Divider Properties from the pop up menu Drag and drop a divider to the desired locat
145. gn files in the blackjack Source directory using a script ModelSim do compile do ModelSim Advanced Debugging 3 23 December 2002 Test Benches 3 24 Click on the Library tab in the Main window expand the work library and find the testbench entity Double click on it to load the design Let s add the top level signals of the design to the Wave window First open the Wave window by selecting the menu View Wave Then from the Sim tab in the Main window drag and drop the top level testbench into the Wave window This will add all the signals at that level of hierarchy Next we re going to load some Tcl code that displays the blackjack table and cards Type do black tcl This will print a bunch of messages to the transcript window and it creates a button labeled Build in the lower right corner of the main window you may need to grow the main window so you can see the button Click on the button to build the blackjack table We can now run the simulation and play blackjack Click on the Start button to start the simulation Let it run for a while so that it plays several hands You might notice that the simulation runs too fast to really see who won each hand We re going to fix that Hit the Stop button There is a signal in the Wave window that goes high after every hand It is called winstrobe We can trigger off that signal to stop the simulation Now try to write a when expression
146. gn of arch name ARCHITECTIRE IS app init app so parameter The attribute string parses as follows app init The name ofthe initialization function for this architecture This part is required app so The path to the shared object file to load This part is required parameter A string that is passed to the initialization function This part is optional and is preceded by a semicolon Page 7 24 discusses the foreign init as well 7 6 ModelSim Advanced Debugging December 2002 FLI and C Models Who is Using FLI Who is Using FLI Third Party Tools e Power tools e Backplane tools e Internal co simulation tools Model developers e Logic Modeling etc e Customers Those who prefer C for complex functions and procedures e Customers 7 5 ModelSim Advanced Debugging FLI and C Models Copyright 2002 Mentor Graphics Corporation Notes ModelSim Advanced Debugging December 2002 7 7 FLI and C Models Benefits of C Interface Benefits of C Interface Faster e Dynamic allocation of RAMs and ROMs e File I O e String Formatting More Capabilities and Flexibility e Clibraries are more mature and robust than VHDL e Some capabilities are limited in VHDL String Formatting File access System resources Silicon vendors protect their synthesizable code while providing simulation model 7 6 ModelSim Advanced Debugging FLI and C Models Copyright
147. h E d E compare top p Ndyc match i write a a compare top p Naddr diff E 1 gold top p addr B Read back 10 locations for ja 0 a lt 10 a a 1 begin BEEE e a iar match read a d gold top sddr r 00000000 moot ha i 81 N if d aj sim top p addr_r UUUUUUU0 00 T dataflow a E compare top p data match E File Edit Yiew Navigate Trace Tools wW S compare top p Nw r match compare top p Nstib match Si Radi BI OT FA Lee HHH E 2 41 compare top p verbi match compare top p t_out diff 1999 ns to 2054 ns 4 Extended mode enabled Keep 0 P 8 11 ModelSim Advanced Debugging Debugging Copyright 2002 Mentor Graphics Corporation Notes ModelSim Advanced Debugging 8 11 December 2002 Debugging Searching for Expressions 8 12 ModelSim Advanced Debugging Debugging Searching for Expressions 9 9 9 Edit Search wave default File Edi Cursor Zoom Compare Bookmark Format Window BEES swai taB hk iege ge 2t 2i tri QQQQ i ef i ELEVEL EY top clk top prw top pstib top prdy E top paddr g HOJER top sstrb A top srdy top saddr top sdata 2070 ns to 3070 ns Notes 8 12 Search for edges or specific values Search for combinations of signal values Find the number of occurrences of comp
148. he ModelSim simulator Open a Block Diagram 1 Select uart top design unit from the ModelSim sim tab window and click the button from the toolbar Two messages should now appear in the ModelSim window as the block diagram opens for the first time HDS is starting up Connected to HDS The uart top block diagram now appears directly underneath the ModelSim window once a connection has been made to the Debug Detective The uart top design consists of four components address decode cpu interface serial interface and clock divider ModelSim Advanced Debugging 9 29 December 2002 Debug Detective B For ModelSim v5 6 users on Solaris platforms Note If you experience various items in the Block Diagram Flow Chart State Machine or IBD views being shown as all black you may need to set the Private Colour Map to restore the desired colors Set the Private Colour Map as follows 1 2 3 4 From the ModelSim Main window select Debug gt Options gt Private Colour Map Quit the current simulation and close ModelSim Re invoke ModelSim You should now see desired colors for the Block Diagram Flow Chart State Machine amp IBD views 2 You can identify the names of each of these components by dragging the mouse to reveal information contained within each of the tool tips Alternatively you can use the button to enlarge the diagram and view each of the components uart uart_top struct Block Diagram I
149. he labs lab3 vhdl spy directory 2 Compile the design do compile do or lib work log cache v log memory v log proc v S3 4 4d 3 30 ModelSim Advanced Debugging December 2002 Test Benches vcom 93 util vhd vcom 93 set vhd vcom 93 top vhd 3 Load the design and open all windows vsim top do view The design is a mixedhdl design with VHDL and Verilog ES structure Of x File Edit Window Bii topfonly p proc Task read Task write EH c cache H Function hash 29 Task update mru 9 Function pick set D Task sysread Task syswrite k Function get hit Fl s0 cache set only Bl 1 cache set only Bl s2 cache set only Ml s3 cache set only 9 m memory lll Package std logic util lll Package vl types lll Package util lll Package std logic 1154 lll Package standard sim top Ai In the ModelSim Source window you will see the inclusion of the new modelsim lib library for the top level source file top vhd library modelsim_lib use modelsim lib util all Select the modelsim lib library from the ModelSim Main window Library tab and note the mapping for this library Using the right mouse button RMB select Properties from the pop up menu Answer The utility init signal spy can now be used in a process The use of spy requires a destination location as well as a source 4 For this lab we are going to spy on 3 signals down
150. he last driver of an unknown value e Trace gt Chase X Jumps to the source of an unknown value ModelSim Advanced Debugging 1 25 December 2002 Review ModelSim Windows Variables Window Variables Window ma variables Iof x File Edit View Window SS OS 8 sel size word size size dly line_34 ER data_mem 6600000000000000 UUUU atag mem Xxx ULL UU UU UU valid mem true false false false false sim top_vh cache sO line__34 1 16 ModelSim Advanced Debugging Model Sim Windows Notes Lists names of HDL items e VHDL constants generics and variables e Verilog register variables Path to current process is shown at lower left Sort ascending descending or declaration order Change value of selected HDL item Find forward or reverse search View items in Wave or List windows or in log file Drag and Drop out Track single step breakpoints process window Copyright 2002 Mentor Graphics Corporation The Variables window is divided into two panes On the left the list of HDL items within the current process are in view On the right the current value s associated with each name are displayed The pathname of the current process is displayed at the bottom of the window If you wish the internal variables of your design can remain hidden See Source code security and nodebug in the ModelSim User Manual You can change the value of a VHDL var
151. he top int entity by double clicking on it Turn on the profiler you can type prof to do the last command starting with prof and run the simulation time run 16 ms or just time Enter the run time here Decoder run time for If implementation using INTEGER types The simulation time should be much shorter now using the type integer ModelSim v5 6 incorporates an aggressive loop optimization for faster simulation run times The following exercise may run slower than the current one 4 Re run the simulation one more time using the following arithmetic increment construct address lt address 1 after cycletime Go through the same steps as before Use the decoder_integer vhd design file and the top_fixed_tb vhd testbench the same file as the last run but the loop has been replaced with the above increment line Compile these files reload the simulation turn on the profiler and time the run for 16 ms using the following commands VSIM gt quit sim ModelSim gt vcom decoder integer vhd ModelSim Advanced Debugging 4 41 December 2002 Analyzing Performance 4 42 ModelSim gt vcom top_fixed_tb vhd ModelSim gt vsim top_int VSIM gt profile on VSIM gt time run 16 ms Enter the run time here Decoder run time using the increment line instead of the loop If you bring up the Ranked Profile window Tools Profile View ranked profile you can see that the increment line line 28 used
152. her window Click on Process e View next statement to be executed e Local process variables displayed in window e Select which process of pending processes to execute next Process Status e Ready ready to execute e Wait scheduled for later e Done already executed Copyright 2002 Mentor Graphics Corporation The Process window shows all active pending processes or all processes in current region Select View gt Active to see all processes scheduled to run during the current simulation cycle Select View gt In Region to see those processes in the currently selected region only Selecting a process in the Process window updates the Dataflow Signals Source Structure and Variables window 1 20 ModelSim Advanced Debugging December 2002 Review ModelSim Windows Dataflow Window Dataflow Window Explore physical connectivity of design Trace events that propagate through design Identify cause of unexpected outputs File Edit View Navigate Trace Tools Window Be Edt Yew eee ie Widow amp ilk m i4 BIBOSAL c o yE Mu t M aM d 2 29 wi DEUM D 23 test NAND 24 EM NAND 22 test m CE mw m Extended mode enabled Keep 1 Aop p t out ESI tae Rea FR Di QQQk istis sk sd 2d The embedded wave viewer helps you to OUS top p t out trace the cause of an unexpected output 2820 ns it
153. hin a library by selecting the design unit with the right mouse button windows or middle mouse button Unix and choosing Edit from the pop up menu ModelSim Advanced Debugging 1 11 December 2002 Review ModelSim Windows Simulation Tab Simulation Tab The Simulation sim tab shows the design structure of a loaded design v ModelSim SE PLUS 5 6 with Debug Detective File Edi View Compile Simulate Tools Debug Window Help dg BAH wala ee XI Loading C Modeltech_5 6 win32 modelsim_lib util E E top toplonly body i Loading C Modeltech 5 5 win32 verilog v types p proc body c cache Loading work top only d m memory Loading work proc lf Package std logic util Loading work cache Package vl types Loading work std logic util body Loading work cache set only Loading work memory Compile of cache v was successful VSIM 2 Project mixed Now Ons Delta 0 sim top y 1 8 ModelSim Advanced Debugging Model Sim Windows Copyright 2002 Mentor Graphics Corporation Notes From the Simulation Tab you can drag and drop regions and or signals to other windows VHDL items are indicated by a dark blue square icon You can view signals variables component instantiations generate statements block statements and packages Verilog items are indicated by a lighter blue circle icon You can view parameters registers nets module instantiation
154. iable constant or generic or a Verilog register variable Move the pointer to the desired name and click to highlight the selection then select Edit gt Change in the Variables window to bring up a dialog box that lets you specify a new value 1 26 ModelSim Advanced Debugging December 2002 Review ModelSim Windows Note that Variable Name is a term that is used loosely in this case to signify VHDL constants and generics as well as VHDL and Verilog register variables You may enter any value that is valid for that variable An array value must be specified as a string without surrounding quotation marks To modify the values in a record you need to change each field separately Click on a process in the Process window to change the Variables window To find HDL items in the Variables window select Edit gt Find You can also do a quick search find from the keyboard When the Variables window is active each time you type a letter the highlighter will move to the next item whose name begins with that letter ModelSim Advanced Debugging 1 27 December 2002 Review ModelSim Windows Wave Window Wave Window View Results of simulation e HDL waveforms and their values wave E nix File Edit View Insert Format Tools Debug Window MDL Values you can view SUS SBR RACTIR ai RAR Fi das e VHDL items dark blue square 1082 4 Signals and process values TENES s h purs e Verilog items li
155. ilable if you have the full HDL Designer Series product These screens display the graphical block diagram and interface based design IBD spreadsheet representations of your text based design hierarchy You can toggle between the IBD and the block diagram Each of the different types of objects are described in detail later in this module ModelSim Advanced Debugging 9 7 December 2002 Debug Detective Using Debug Detective Using Debug Detective Choose your design from the ModelSim window and click on the Show as Graphics button Or Select the View menu click on Show as Graphic and choose Block diagram J Modelsim SE PLUS 5 6 with Debug Detective Ioj xj File Edit View Compile Simulate Tools Debug Window Help 8s BAH ofA Oe z uart_tb uart tb struct E i0 tester flow i1 uart top struct lf Package textio Loading work clock divider flow Loading work cpu interface struct Loading work control operation fsm Loading work serial interface struct Loading work status_registers spec Loading work mit rcv control fsm VSIM 2 Project VART Now Ons Delta 0 sim uart_tb Z 9 7 ModelSim Advanced Debugging Debug Detective Overview Copyright 2002 Mentor Graphics Corporation Notes 9 8 ModelSim Advanced Debugging December 2002 Debug Detective Block Diagrams Block Diagrams work uart_top struc File Edit Vie agram Sim
156. ility to visualize and debug a chosen design under test This gives the designer the ability to render Block Diagrams Interface Based Design IBD State Machine and Flow Chart descriptions on the fly whilst simulating designs in the ModelSim simulator This exercise shows how to use Debug Detective from the ModelSim Simulator and use HDL Designer Series HDS diagrams to drive simulation by adding probing signals and breakpoints to a design State Machines can also be animated allowing you to visualize the dynamics of the state machine code Debug Detective can be used when a compiled HDL design unit is double clicked and loaded into a ModelSim project The compiled design is then rendered in Debug Detective allowing the user to show each design component graphically Directions Invoke ModelSim Start with one of the following for UNIX at the shell prompt vsim for Windows your option from a Windows shortcut icon from the Start menu or from a DOS prompt modelsim exe Project Files The files that we will use in this lab are located at Windows c labs lab9 dd_tutorial_ref uart_vhdl Unix users student labs lab9 dd tutorial ref uart vhdl ModelSim Advanced Debugging 9 27 December 2002 Debug Detective Create a New Project 1 Select File gt New gt Project from the menu The Create Project dialog box will appear 2 Enter the following information into the Create Project dialog box Project Name UART P
157. im Advanced Debugging December 2002 FLI and C Models FLI Problems Cont FLI Problems Cont Use the trace_foreign lt n gt switch to enable FLI tracing 1 create log file only mti trace 2 create replay only mti data mti init mti replay mti top 3 create both vsim c test pseudo trace foreign 3 Callback 1 trace 0 0x2411023 for array monitorl Time 0 100 Iteration 1 Entering mti GetArraySignalValue ERROR arg 1 to mti GetArraySignalValue type mtiSignalIdT was not supplied by an mti call arg 2 is void 0x24189f8 returned void 0x2 0x2 0x2 0x2 0x2 0x2 0x2 0x2 0 Exiting mti GetArraySignalValue Callback 1 returned status 0x0 Time 0 0 Iteration O End of foreign interface trace 7 30 ModelSim Advanced Debugging FLI and C Models Copyright 2002 Mentor Graphics Corporation Notes The FLI interface tracing feature is available for tracing user foreign language calls made to the MTI VHDL FLI Foreign interface tracing creates two kinds of traces a human readable log of what functions were called the value of the arguments and the results returned and a set of C language files to replay what the foreign interface did The purpose of the logfile is to aid you in debugging FLI code The primary purpose of the replay facility is to send the replay file to MTI support for debugging co simulation problems or debugging FLI problems for which it is impractical to send the FLI code
158. im Advanced Debugging December 2002 Review ModelSim Windows Library Tab Library Tab The Library tab shows the compiled design units e Expand the library to reveal the design units J ModelSim SE PLUS 5 6 5 x File Edit View Compile Simulate Tools Debug Window Help Csi se a clue ae Compile of util vhd was successful Compile of memory v was successful tt Compile of proc v was successful Compile of set vhd was successful Compile of top vhd was successful tt Compile of cache v was successful 6 compiles 0 failed with O error s Project mixed No Design Loaded gt y ModelSim SE PLUS 5 6 with Debug Detective File Edi View Compile Simulate Tools Debug Window Help Ss se FT ose BP Xl tt Loading C Modeltech_5 6 win32 modelsim_lib util Ef body Loading C Modeltech_5 6 win32 verilog v_types body 1 cache E cache set 1 memory 14 proc P std_logic_util Compile of cache v was successful VSIM 2 sim S Project mixed Now Ons Delta 0 sim top A 1 7 ModelSim Advanced Debugging Model Sim Windows Copyright 2002 Mentor Graphics Corporation Notes Click on the sign in front of the library name to expand the library Refresh or recompile from here Double clicking on a design unit loads it for simulation Menu options Compile gt Compile You can edit design units wit
159. ing code shows it all together this is what you need to enter into ModelSim at the VSIM command prompt to get it to stop and draw the winner every hand Type as shown with carriage returns when testbench winstrobe 1 set running 1 draw winners picture examine testbench winner After you enter this on the ModelSim command line and assuming there weren t any mistakes you can click the continue button on the blackjack table to resume the simulation Now the simulator will stop after each hand so you ll now have to keep hitting continue to keep it running Notice the bitmaps of the winner each time The last step of this lab is to see if you can to change the colors of the buttons on the blackjack table Open the black tcl file to determine where the buttons are defined Then change the background colors for the start stop and continue buttons to green red and yellow respectively Use the background option followed by the color at the end of each line for the start stop and continue buttons Stop and quit the Blackjack GUI display Type the following at the ModelSim prompt ModelSim do black tcl ModelSim Advanced Debugging 3 25 December 2002 Test Benches 14 Click on the Build button to see the buttons with the new background colors 3 26 ModelSim Advanced Debugging December 2002 Test Benches Lab 3b Signal Spy Introduction The ability to access registers or signals though hierarch
160. integer IN integer vhdl enum IN severity level vhdl real IN real vhdl array IN string attribute FOREIGN of in params procedure is in params app so 7 38 ModelSim Advanced Debugging December 2002 FLI and C Models C Subprogram Example C Subprogram Example VHDL package pkg is procedure sdk_to_string_sulv vhdl_array IN bit vector format array IN string return array OUT string return len OUT integer attribute foreign of sdk to string sulv is sdk to string sulv sdk to string sulv so end package body pkg is procedure sdk to string sulv vhdl array IN bit vector format array IN string return array OUT string return len OUT integer is begin report ERROR foreign subprogram sdk to string sulv not called end end You must also write a subprogram body for the subprogram but it will never be called The C program gets called 7 23 ModelSim Advanced Debugging FLI and C Models Copyright 2002 Mentor Graphics Corporation Notes ModelSim Advanced Debugging December 2002 7 39 FLI and C Models C Subprogram Example Cont C Subprogram Example Cont include mti h include lt stdio h gt void sdk_to_string_sulv mtiVariableIdT vhdl_array IN bit_vector mtiVariableIdT format_array IN string mtiVariableIdT return_array OUT string int return len OUT integer static char buf 32 fstring 32 rst
161. ion Delete a divider by selecting it and pressing the lt Delete gt key on your keyboard or select Delete from the pop up menu Splitting Window Panes The pathnames values and waveform s window panes of the Wave window display can be split to accommodate signals from one or more datasets Select Insert gt Window Pane from the Wave window This creates a space below the selected waveset and makes the new window active Combining items in the Wave window Combine signals in the Wave window to form busses To create a bus select one or more signals in the Wave window then select Tools gt Combine Signals The Combine Selected Signals dialog box appears and allows you to specify the name of the newly created bus It also allows you to specify the order the selected signals are indexed in the bus You can also choose to remove the selected signals from the Wave window once the bus is created You can also edit and format HDL items from the Wave window Select the item in the Wave window then choose commands from the Edit menu You can also click drag to move items within the pathnames and values panes ModelSim Advanced Debugging 1 29 December 2002 Review ModelSim Windows Formatting an item Select the item s label in the pathname or its waveform in the waveform pane then select View gt Signals Properties from the Wave window The resulting Wave Signal Properties dialog box appears and has three tabs View Format
162. is is a shortcut to get the same results as step 72 Again note ModelSim Advanced Debugging 1 39 December 2002 Review ModelSim Windows that the Signals window and Source window change to reflect the selected process or signal 4 You can also display an embedded waveform window Show Wave button in the Dataflow toolbar dataflow IOl x File Edit View Navigate Trace Tools Window S Fad BANNAH Je e 9 Xe 3e 3c 9 BABA QAQQ Hp FNAND 22 test in rw test aL Ex test ML an 1 40 ModelSim Advanced Debugging December 2002 Review ModelSim Windows iz dataflow oO x File Edit View Navigate Trace Tools Window SB Rad X B I amp OO 7 Mi Je e KE amp 098 B ni NAND 24 tesi HNAND 22 sth test test m SS LBA IALA RAE of ee eE Jtop p rw top p test_in 2820 ns ns JEn n Extended mode enabled Keep 1 top p ANAND 23 This is a full functional waveform window that is tied to the active process in the Dataflow window This feature can help eliminate the need to set a breakpoint and re simulate The cause of the error is the nand gate on line 24 of proc v Note the HiZ and a known value on its input that result in an X 5 Click on the component you wish to view to load the signals in the attached Wave window Notice the inputs and output of the NAND 23 gate are displayed in the embedded waveform window Experiment with
163. is responsible for saving and restoring that memory e Model must be coded assuming that the code could reside in a different memory location when restored Reference the ModelSim FLI Manual for list of checkpoint and restore commands 7 18 ModelSim Advanced Debugging FLI and C Models Copyright 2002 Mentor Graphics Corporation Notes There are other FLI functions that are part of checkpoint and restore mti RestoreBlock e mti RestoreChar e mti RestoreLong mti RestoreShort mti RestoreString ModelSim Advanced Debugging 7 33 December 2002 FLI and C Models mti_SaveBlock mti_SaveList mti_SaveLong mti_SaveShort mti_saveString The above list is not by any means a comprehensive list of all of the FLI checkpoint and restore commands For a description of checkpoint and restore commands functions and what they do see the ModelSim Foreign Language Interface Manual 7 34 ModelSim Advanced Debugging December 2002 FLI and C Models C Architecture Example C Architecture Example entity and_gate is port in1 in2 bit outi out bit Initialization function end VHDL architecture only of and gate is attribute foreign string attribute foreign of only architecture is and gate init gates so Object code begin end 7 19 ModelSim Advanced Debugging FLI and C Models Copyright 2002 Mentor Graphics Corporation Notes Starting with VHDL 93 the FOREIGN attribute is declared i
164. is simulating the back annotated post Place amp Route netlist in ModelSim In this exercise we will simulate a VHDL RTL design save a golden waveform result and simulate the gate level VHDL post P amp R netlist with its corresponding SDF timing file We will use a new design shown below called math vhd for this exercise Our Design math vhd CONSTANT w POSITIVE 8 data_a w 1 0 mult vhd a w 1 0 4 a w 1 w 2 X p Product w 1 0 clock clock Teset a w 2 1 0 pem adderyhd 1 add out w 2 1 0 a w 1zw 2 data_b w 1 0 b w 1 0 bbIw 1 wi i mE i Sum 3 0 5 state fsm_out 2 0 clock amp a w 2 1 0 fsm data out 2 0 reset ib w 2 1 0 l ok reset sel clock reset g count vhd data c w 1 0 c w 1 0 fsm out 2 clock UpDn count out w 1 0 clock reset Counter reset fsm out 2 increment vhd alu vhd a ke i 3 Tw 1 0 Increment s w 1 0 increment out w 1 0 cw E0 ALU gt clock reset The VHDL source files and testbench for this design are located in the labs lab8 math src directory Take some time to review and understand the operation of math vhd and the six lower level VHDL files 1 Within ModelSim change the directory to labs la
165. ison of signal data from module tst pseudo in dataset min amp typ Comparison will be evaluated based on the definition of clk clocked data will be name displayed in the Wave window 6 20 ModelSim Advanced Debugging Waveform Compare Copyright 2002 Mentor Graphics Corporation Notes 6 20 ModelSim Advanced Debugging December 2002 Waveform Compare Compare Example Cont Compare Example Cont compare clock rising offset 4 ns clock delay4 UE oe Define a clocked compare strobe clock delay4 that samples 4 ns after the rising edge of signal min tst pseudo clk compare add clock clock delay4 label clocked delay4 data min tst pseudo data typ tst pseudo data Fi Clocked comparison of signal data from module tst_pseudo in dataset min amp typ Comparison will be evaluated based on the definition of clock_delay4 clocked_delay4_data will be name displayed in the Wave window compare run compare info write compare info txt compare info Run the comparison Save comparison results to file Display comparison results in Main window 6 21 ModelSim Advanced Debugging Waveform Compare Copyright 2002 Mentor Graphics Corporation Notes ModelSim Advanced Debugging 6 21 December 2002 Waveform Compare Waveform Compare Example transcript on Waveform Compare Example onerror resume Test asynch compare with delayed subexpression when condition
166. ith fast e All children of Verilog must be Verilog also e Can instantiate Verilog compiled with fast in VHDL VHDL cannot modify the parameters of the Verilog module Verilog gate level simulation e Faster runtimes vs VHDL e Do not need overhead of VITAL models SDF for mixed VHDL amp Verilog designs e VITAL cells amp Verilog cells can be annotated from the same SDF file e access via SDF command line options sdfmin sdftyp sdfmax instance sdf filename Search Libraries e vsim L command searches the specified library for precompiled modules Use in Verilog SDF simulation to specify cell primitives amp work libraries 8 16 ModelSim Advanced Debugging Debugging Copyright 2002 Mentor Graphics Corporation Notes 8 16 ModelSim Advanced Debugging December 2002 Debugging Issues With SDF Instance Specification Issues With SDF Instance Specification Use the simulator s SDF command line options to specify the SDF files the desired timing values and design instances e sdfmin e sdftyp instance 7 filename e sdfmax vsim sdfmax testbench u1 uart_top sdf testbench Make sure the SDF file points to the correct instance e Instance paths in the SDF file are relative to the instance to which the SDF is applied e If the instance name is omitted the SDF file is applied to the top level of the design Usually incorrect The model is usually i
167. ivity Trail Animation Activity Trail Activity Trails color code Red Current State Box Yellow Previous State Box Blue Previously visited State Box 9 19 ModelSim Advanced Debugging Debug Detective Overview Copyright 2002 Mentor Graphics Corporation Notes Here are the results of animation Red indicates the current state Yellow indicates the immediate preceding state Blue indicates all states that have been visited during the animation capture time You are able to set breakpoints directly on the state machine diagram as well Click on the state diagram on the spot you want to add the breakpoint A circle will designate that a breakpoint has been added ModelSim Advanced Debugging 9 25 December 2002 Debug Detective Summary Summary Debug Detective Design Analysis Debug Detective ModelSim Debug Detective Functions Debug Detective User Interface Simulation Toolbar Highlighting Reporting Signal Information Adding Removing Simulation Probes Manipulating Reporting on Breakpoints Running the Simulator Restarting the Simulator Animating State Diagrams 9 9 9 9 9 9 9 9 9 o 9 20 ModelSim Advanced Debugging Debug Detective Overview Copyright 2002 Mentor Graphics Corporation Notes 9 26 ModelSim Advanced Debugging December 2002 Debug Detective Lab 9 Debug Detective Tutorial Optional Lab Introduction Debug Detective provides the text based designer with the ab
168. l config text hello foreground green button foo b2 text say goodbye command foo lbl config text goodbye foreground red pack foo lbl foo bl foo b2 padx 10 pady 10 foo is the top level or parent anyone there b1 and b2 are buttons widgets They are children of foo is 4 say goodbye 2 19 ModelSim Advanced Debugging Tcl Tk Overview Copyright 2002 Mentor Graphics Corporation Notes ModelSim Advanced Debugging 2 19 December 2002 Tcl Tk Overview Monitors Monitors 1001 Iv Break On Value SENE on mE Logic Analyser RLIT Sub Dymanic Micro Code Monitor 00110010001000000000000000000001 29 Subtract 1 from R 2 Micro Code proc build_window global test_lines line_number RegABreak RegABreakV RegBBreak ResultBreak toplevel monitor label monitor labell relief raised bd 2 width 10 text RegA grid monitor labell row 1 column 1 label monitor valuel font Tahoma 16 justify right width 20 text XXXXXXXX grid monitor valuel row 1 column 2 checkbutton monitor cbl text Break On Value variable RegABreak grid monitor cbl row 1 column 4 bind wave tree Bl Motion tget value at cursor bind wave tree lt Button 1 gt get value at cursor 2 20 ModelSim Advanced Debugging Tcl Tk Overview Copyright 2002 Mentor Graphics Corporation Notes 2 20 ModelSim Advanced Debugging December 2002 Tcl Tk Overview Mo
169. lation but do not close ModelSim Part 5 Optimizing the Math Design Optional Upon examination of the math vhd design hopefully you have spotted opportunities to rewrite some of the VHDL in the lower level modules to result in faster simulation run times synthesis into fewer gates synthesis into faster maximum frequency operation and less propagation delay and simplification of the VHDL code in general adder vhd Instead of using two adders and one multiplexor rewrite this module to use two multiplexors and one adder Adders are more expensive with regards to silicon gates area and have more propagation delay than multiplexors counter vhd Instead of using one adder one subtractor and one multiplexor to control the updn direction control rewrite ModelSim Advanced Debugging 8 35 December 2002 Debugging this module to use one adder and one multiplexer to control the updn direction control Adders subtractors are more expensive with respect to silicon gates area and have more propagation delay than multiplexers alu vhd Look carefully at this design and do the math What is the output f assigned Synthesis tools typically do not optimize arithmetic structure Thus you must be very careful when writing any VHDL code that includes any arithmetic operators Rewrite this module to simplify the output f mult vhd Instead of using the behavioral multiply operator use an LPM function The use of LPMs Librar
170. layed RMB to disable remove breakpoint or use bd command bd filename lt line gt Toggles click again to enable disable existing breakpoint No limit to the number of break points e Conditional break points when condition action when b 1 and c 0 stop Used with VHDL signals and Verilog nets and registers Also use bp command with Tcl commands bp filename lt line gt if now 100 then cont GUl access via menu Tools gt Breakpoints 8 5 ModelSim Advanced Debugging Debugging Copyright 2002 Mentor Graphics Corporation Notes ModelSim Advanced Debugging December 2002 Debugging Checkpoint and Restore Checkpoint and Restore Checkpoint saves the simulation kernel state of the design e This includes the vsim wlf file the list of the HDL items shown in the List amp Wave windows the file pointer postions for files opened and the state of foreign architectures checkpoint filename Restore restores the state of the design saved by checkpoint restore filename or vsim restore filename Useful for long simulations e Putin periodic checkpoints in anticipation of simulation error e Restore back to state prior to simulation error Add more signals to monitor for debugging purposes Continue simulation Note Only supported when using the same version of ModelSim 8 6 ModelSim Advanced Debugging Debugging Copyright 200
171. le Simulate Tools Debug Window Help es BE fF myn Ea ae i A View Signals Drag and Drop signals Loading work top only E top top only h perio nok por um oading work cache b etwee n Ww I n d OWS Loading work std logic util body east Loading work cache set only m memory Loading work memory WM Package std logic util Compile of cache v was successful Tiris OMNIS File Edi View Add Tools Debug Window Pack i structure Ill Package uti view signals E Gi signals sim Fec iran Eie Eat Ven Add Tots Debug Wird Project mixed Now Ons Delta 0 SX E spi UUUUUUUUUUUUUUUU data_out_ UUUUUUUUUUUUUUUU data_out UUUUUUUUUUUUUUUU UUUUUUUUUUUUUUUU UUUUUUUUUUUUUUUU UUUUUUUUUUUUUUUU sim top p sim top 1 12 ModelSim Advanced Debugging ModelSim Windows Copyright 2002 Mentor Graphics Corporation Notes Displays the names and values at the end of the current simulation run e VHDL Signals Generics and Shared Variables Verilog Nets Register Variables Named Events and Module Parameters Values do not change dynamically with movement of the Wave window cursor From the Signals window you can e Drag and Drop to Wave List and Dataflow windows 1 18 ModelSim Advanced Debugging December 2002 Review ModelSim Windows Force Apply Stimulus e Filter Choose signal types for viewing inout etc e View Declarations e Set Breakpoints
172. le collected every 10 ms profile interval command e 3000 to 4000 Samples enough to determine what is happening 4 10 ModelSim Advanced Debugging Analyzing Performance Copyright 2002 Mentor Graphics Corporation Notes When a simulation environment is executed the user normally has to accept the time required to run the simulation The performance analyzer built into ModelSim allows the user to display what parts of the model are taking the largest percentage of simulation run time The profiling will work for all modeling languages supported and also at all levels of abstraction It can uncover problems such as a VITAL gate level cell that has not been globally accelerated due to it being non level 1 compliant It will uncover processes with un necessary signals on th sensitivity list causing it to be triggered too much Some testbenches include code that is not necessary for a particular test but still taking simulation time Design bottlenecks can also be easily located 4 10 ModelSim Advanced Debugging December 2002 Analyzing Performance The Profiler collects samples with respect to real time not simulation time A sample is taken every 10 ms default during the simulation run At the sample point the simulator will be executing a line of code or a function of the kernel All of these samples are collected and presented to the user in an easy to understand format based on the amount of simulation time spent in the users code B
173. lex expressions Wave Signal Search window wave BES m Signal Name s sim top pdata Search Type C Any Transition C Rising Edge C Falling Edge C vae oS oS Search Forward Search Reverse alue m Search Options 4 Match Count Search Results Status Found only 3 matches Time 2320ns Done Copyright 2002 Mentor Graphics Corporation ModelSim Advanced Debugging December 2002 Debugging Iteration Violations Iteration Violations Iteration violations are errors in which the simulator cannot resolve all of the events that occur at a given timestep Most commonly caused by zero delay loops in user s code Default iteration limit is 5000 e can be changed in Options gt Simulation Options dialog box Simulator stops immediately upon hitting iteration limit Error Iteration limit reached Possible zero delay oscillation See the manual Time 63700 ns Iteration 5 Instance testbench textio_inst User can debug it by increasing iteration limit and single stepping 8 13 ModelSim Advanced Debugging Debugging Copyright 2002 Mentor Graphics Corporation Notes ModelSim Advanced Debugging 8 13 December 2002 Debugging Iteration Violations Cont Iteration Violations Cont When debugging iteration limit problems look for situations like the following e Missing or incorrectly applied SDF annotation to a netlist e
174. location is selected Click the Browse button navigate to the labs lab6 directory and select all the files Then click Open 3 Compile all the files in the project Do this by picking the Compile gt Compile All menu item 4 Runa simulation using SDF typical timing The waveforms from this run will be used for comparisons against subsequent runs Save the waveforms as the golden results vsim sdftyp chip time sim sdf wlf gold wlf tst pseudo add wave run 10 us quit sim lt THIS IS IMPORTANT so the waveform file gets closed ModelSim Advanced Debugging 6 27 December 2002 Waveform Compare 10 11 6 28 Now let s re run the simulation but this time we ll run with SDF maximum timing Invoke vsim as before but with the sdfmax switch instead and specifying a different wlf file Also add the top level signals to the waveform window vsim sdfmax chip time sim sdf wlf max wlf tst pseudo add wave Invoke the Compare Wizard Choose the menu pick Tools Waveform Compare Comparison Wizard For the reference dataset use the Browse button and select the gold wlf file created earlier For the test dataset use the current simulation Also check the box labeled Update comparison after each run Then select Next Choose the Compare AII Signals option and click Next Click Next again answer no to when it asks you if you want to add more signals Then click
175. m Advanced Debugging December 2002 Test Benches Spy_On_Some_Signals process begin init_signal_spy lt lower_signal_path gt lt top_mirrored_signal gt 1 wait end process Spy_On_Some_Signals Now recompile the top vhd file with the new changes vcom 93 top vhd Restart the simulation restart f and add all the top level signals to the design add wave Simulate by doing a run all and you should see the spied on signals in the wave window ModelSim Advanced Debugging 3 33 December 2002 Test Benches 3 34 ModelSim Advanced Debugging December 2002 Module 4 Analyzing Performance Objectives Upon completion of this module you will be able to Describe challenges to achieve the best performance of simulations Describe the Performance Analyzer capabilities and value e Describe Code Coverage Benefits and Value Describe things to avoid in models that negatively impact performance List the different graphical views of performance analysis results Describe the in and under information in performance analysis results e List ways to improve Verilog RTL and Verilog gate level simulations List certain Verilog commands List certain VHDL commands ModelSim Advanced Debugging 4 1 December 2002 Analyzing Performance Module Overview Module Overview In this module we will discuss 9 9 9 9 9 Code Coverage Performance Analyzer Turn Profiling
176. m Files Significantly smaller wlf files in 5 5 e 6x smaller on average e worst we ve seen is only 3x smaller e some files will be 100 1000x smaller depending on repetitiveness of data such as clocks NO PERFORMANCE HIT Can be enabled by either e modelsim ini file setting Turn on 1 or off 0 WLF file compression The default is 1 compress WLF file WLFCompress 1 e TCL variable Set WLFCompress 1 e defaults to Enabled 6 24 ModelSim Advanced Debugging Waveform Compare Copyright 2002 Mentor Graphics Corporation Notes 6 24 ModelSim Advanced Debugging December 2002 Waveform Compare Disable Enable Pop up Disable Enable Pop up install_dir tcl vsim pref tcl The following control the popup info box By setting the popup off delay to 0 the popup will remain indefinitely or until there is mouse motion The value is time in milliseconds The time for the popup to appear is controlled by the popup delay The popup can be disabled altogether using the popup enabled flag Set to non zero value to modify duration of popup set PrefCompare PopupDelay 1000 set PrefCompare PopupOff 0 4 4 Set to dus and popup remains set PrefCompare PopupEnabled 1 se until mouse movement Set to zero to disable popup 6 25 ModelSim Advanced Debugging Waveform Compare Copyright 2002 Mentor Graphics Corporation ModelSim Advanced Debugging 6 25 December 2002 Wavef
177. mber 2002 Analyzing Performance Verilog Gate Level Cont Verilog Gate Level Cont Use the fast switch for cell libraries 2 3x Faster e Cached evaluator improves performance e Cache Management Algorithms e Architecture specific optimizations 2 4x smaller memory footprint use per cell 2 6x Faster SDF annotation algorithm e additional 30 memory reduction pela 4 24 ModelSim Advanced Debugging Analyzing Performance Copyright 2002 Mentor Graphics Corporation Notes ModelSim Advanced Debugging 4 25 December 2002 Analyzing Performance vlog Commands vlog Commands O5 capital oh 5 Maximum optimization Optimizes loops and case statements Recommended use with large sequential blocks only Other uses may increase compile times Use with or without fast Verify optimized design behaves the same as the original version e Other Levels O0 minimum Work around bugs Increase debugging visibility on a specific cell Place breakpoints on source lines that have been optimized out 01 enable PE level optimization 04 enable standard SE optimization 4 25 ModelSim Advanced Debugging Analyzing Performance Copyright 2002 Mentor Graphics Corporation Notes 4 26 ModelSim Advanced Debugging December 2002 Analyzing Performance vlog Commands Cont vlog Commands Cont topt e Optimizes designs that have been previously compiled unoptimized without
178. mpractical to send the FLI code MTI would still require a copy of the VHDL Verilog part of the design to actually execute a replay but many problems can be resolved with the trace only 7 44 ModelSim Advanced Debugging December 2002 FLI and C Models Debugging Tracing Cont Debugging Tracing Cont FLI tracing e vsim trace_foreign 1 mydesign Creates a logfile e vsim trace_foreign 3 mydesign Creates a logfile and a set of replay files e vsim trace_foreign 1 tag 2 mydesign Creates a logfile with a tag of 2 Add debug information to the C function e printf Ormti printmessage e ifdef debug Add commands to FLI to dump internal data print status e mti AddCommand or mti AddTclCommand Create internal signals e mti_CreateSignal 7 29 ModelSim Advanced Debugging FLI and C Models Copyright 2002 Mentor Graphics Corporation Notes In order to debug your FLI code in a debugger your application code must be compiled with the debugging information for example by using the g option You must then load vsim into a debugger Even though vsim is stripped most debuggers will still execute it On Solaris AIX and Linux you can use either gdb or ddd e g ddd which vsim On HP UX you can use the wdb debugger from HP e g wdb which vsim It is available for download at www hp com go wdb Since initially the debugger recognizes only vsim s FLI function symbols you need to place
179. n env optional specifies a hierarchical context for the signal names in lt expressionString gt so they don t all have to be full paths Option install optional causes the newly created signal to become a child of the specified region ModelSim Advanced Debugging 5 5 December 2002 Virtual Signals Option implicit optional is used internally to create virtuals that are automatically saved with the list or wave format Arg lt expressionString gt required is a text string expression in the MTI GUI expression format See TBD for a full and updated description Arg lt name gt required is the user defined name of the virtual signal 5 6 ModelSim Advanced Debugging December 2002 Virtual Signals Virtual Signals Cont Virtual Signals Cont virtual signal install sim testbench chipa alu a 19 downto 13 amp Ichipa decode inst amp chipa mode stuff Ichipa alu a is of type std logic vector Ichipa decode inst is a user defined enumeration Ichipa mode is of type integer Produces sim testbench stuff which is a record type add wave sim testbench stuff added to the waveform window virtual signal chip instruction 23 21 address mode Produce alias chip address mode 5 6 ModelSim Advanced Debugging Virtual Signals Copyright 2002 Mentor Graphics Corporation Notes Examples of virtual signals virtual signal install sim testbench chipa alu a 19 downto 13 amp chi
180. n Statements Project mixed Now Ons Delta 0 sim top P Command Editing e Click on VSIM gt or ModelSim gt prompt to retrieve command Different views of Design e Double click on compile errors to show relevant source code Up down arrows for history cmd unix style history supported 1 5 ModelSim Advanced Debugging Model Sim Windows Copyright 2002 Mentor Graphics Corporation Notes The Main window is divided into two panes the workspace on the left and a transcript command line window on the right The workspace provides access to projects libraries compiled design units and the simulation dataset structure You can hide the workspace by selecting View gt Hide Show Workspace The workspace can display four tabs Project Library Structure and Compare Additionally multiple datasets show up as extra tabs in this window In the transcript portion of the Main window ModelSim maintains a running transcript history of commands When you are running a simulation ModelSim ModelSim Advanced Debugging 1 7 December 2002 Review ModelSim Windows displays a VSIM prompt which enables you to interactively enter commands within the graphic interface Variable settings determine the filename used for saving the Main window transcript Setting the PrefMain and or TranscriptFile in modelsim ini logs output to the specific file The default is in the modelsim ini is set to transcript You can use the saved
181. n on seed Pick another to get a different sequence of cards set seed noRandSeed puts Seed from TCL is seed force top seed 10 seed E xb ok 2 12 ModelSim Advanced Debugging Tcl Tk Overview Copyright 2002 Mentor Graphics Corporation Notes 2 12 ModelSim Advanced Debugging December 2002 Tcl Tk Overview Simulation Commands Simulation Commands ModelSim simulation commands are Tcl based Some examples e force Force command allows you to apply stimulus interactively to VHDL signals and Verilog nets and registers e run The run command advances the simulation by the specified number of timesteps e restore The restore command restores the state of a simulation that was saved with a checkpoint command during the current invocation of VSIM called a warm restore e quit Exits the simulator e restart Reloads the design and resets the simulation time to zero 2 13 ModelSim Advanced Debugging Tcl Tk Overview Copyright 2002 Mentor Graphics Corporation Notes ModelSim Advanced Debugging 2 13 December 2002 Tcl Tk Overview Tcl Script Example Tcl Script Example array set comp_command packages vhd vcom accumulator vhd vcom aces_Counter v vlog FSM_control v vlog game_on v vlog testbench vhd vcom proc bench amount units set before_run clock seconds run Samount Sunits set after_run clock seconds set total run expr Safter_run before
182. n package STANDARD With the 1987 version you need to declare it yourself Declare it in a separate package or directly in the architecture This also works with VHDL 93 ModelSim Advanced Debugging 7 35 December 2002 FLI and C Models C Architecture Example Cont C Architecture Example Cont The following is the C model of the two input AND gate include lt stdio h gt include mti h typedef struct mtiSignalIdT inl mtiSignalIdT in2 mtiDriverIdT out1 inst_rec void do_and void param inst_rec ip inst_rec param mtilnt32T vall val2 mtilnt32T result vall mti GetSignalValue ip gt inl val2 mti GetSignalValue ip gt in2 result vall amp val2 mti ScheduleDriver ip gt outl result 0 MTI INERTIAL 7 20 ModelSim Advanced Debugging FLI and C Models Copyright 2002 Mentor Graphics Corporation Notes This is the same model as provided in lt modeltech_install_dir gt examples foreign example_two gates c NOTE RECORD generics are not supported in FLI 7 36 ModelSim Advanced Debugging December 2002 FLI and C Models C Architecture Example Cont C Architecture Example Cont void and_gate_init Initialization function is passed mtiRegionIdT region gt P i char kparam region hierarchical location mtiInterfaceListT generics ptr to param from foreign attr mtiInterfaceListT ports ptr to generics ptr to ports inst rec i
183. ndb vhd 216 F mentor Fiala neng vhd 99 0 _ o 6 In 4 i zh tnm F mentor Waning ab control vhd 130 4 18 ModelSim Advanced Debugging Analyzing Performance Copyright 2002 Mentor Graphics Corporation Notes This can be seen by looking at the 6 of time spent in the function at line 216 of the std unsigned package in the ranked view In the hierarchical view you will see this line show up under two separate lines One takes 4 and the other 2 making the total of 6 shown in the ranked view ModelSim Advanced Debugging 4 19 December 2002 Analyzing Performance Coding for Performance Things to Avoid Coding for Performance Things to Avoid Large arrays of signals e use variables or shared variables if possible e large memory impact 100x math operations on std logic vectors e these operations are accelerated but still it s faster to use integers Gate level simulation e use Verilog gate level with VHDL testbench it s faster than VITAL Use concurrent assignments rather than processes with wait statements e good clk not clk after 100 ns e bad Process begin while not suspend loop elk lt 0 wait for 100 ns clk lt 1 end loop wait end process 4 19 ModelSim Advanced Debugging Analyzing Performance Copyright 2002 Mentor Graphics Corporation Notes 4 20 ModelSim Advanced Debugging December 2002 Analyzing Performance Coding for Performan
184. ndow ModelSim 1 Make the ModelSim window active and choose View gt Signals from the menu The signals window will appear showing all the signals on the block diagram The message view signals will appear in the ModelSim window ModelSim Advanced Debugging 9 31 December 2002 Debug Detective 2 Add a l Make the wave window active and notice that the same signals appear as those previously shown in the signals window Make the uart top block diagram active by clicking inside the window Select the c k div en signal Notice that when this signal is selected both the wave and the signals windows now highlight the same signal This allows you to monitor both signal values as they change during simulation You can select multiple signals by using enit Ler mouse button or by dragging a box crossing the required signals Breakpoint and Run the Simulator Make the uart top block diagram active by clicking inside the window and use the button to zoom into the serial interface component on the block diagram Select the int signal and use the button to add a breakpoint to the diagram Notice that a red circle appears on the int signal on the block diagram For ModelSim v5 6 users on Solaris platforms Note The Add Breakpoint button will not set a breakpoint in the 9 32 serial interface component on the block diagram Instead type the following command in the ModelSim Main window when id
185. nen sanete sno XV PATIOS aT EA PEE OE AEE MC e am hue PALM up nue e eR E XV What this COUTSE TS Ol ou ecrees eese sci bis oe mette de tee cnn Ghee es clot Erste eu XV PETE GUISE Knowledge uu noctis ctn eae aaae Qd E EE XV About the ISeterence Ste too T E a ne RON Eee Bre hems Efe RETE EE EE CEA ON Sidus xvi Module 1 Review ModelSim Windows essssssssscooeoeooesseesssessosoccecesoecesssossococceoseeesecessessoo 1 1 Mod le OVerVde W seeren reene a it ots AA EA oto terc dr Sedo d certc 1 2 User Interlace anean At ss Paw br T ETE E a 1 3 Common Window Beat res 2o mam e a bie been de tticet P acta br dca 1 6 INE WW A OWN as otis coto cio Fiesta Stat o ket coe cra i Cs boo d eO ed eoe EAE OG ES oe Leo0id 1 7 Project AD METTE 1 9 TENT AES JE AD se ccr 1 11 STATUE ON cred oral aac cas blc eet o E Pd ibo ats madi ER Ld 1 12 M ltple Datdse 8 oc ee eater pr fener eRe ree taion me meteece Uren rennet Keren aay sane ree acre 1 13 DOULCE WING OW 4 aote o ves Cota o Resta bul eser e ra bavi t ela de ELE ERR SRL Deve MUERTA E 1 14 Language TOHplales quintentdens tec dta E RE E 1 16 SiBrals WIDUOWS ice te n NOSE EP e QUSE APER a FRU Ede E UU ra ee HERI DN Feo Passt ee 1 18 Process Window eco tarot ad ee esa ee ait desis e tance US Parc Rut ee od itu ona 1 20 Dataflow WIIOOW asciende etri tati boe e vata ca YO e op rb b Red Ee eee ste odd 1 21 Dataflow Window Chase X isnt det Fro Fert Eve P Free bee eet EEG 1 24 Varnables Window nere et Caco Se
186. nguage Interface Reference Manual e Parameter A string that is passed to the initialization function This part is preceded by a semicolon and is optional If the initialization function has a leading or the VHDL architecture body will be elaborated in addition to the foreign code If is used see example below the VHDL will be elaborated first If is used the VHDL will be elaborated after the foreign initialization function is called Unix environment variables can also be used within the string as in this example ATTRIBUTE foreign of arch_name ARCH app_init SCAB apposo ModelSim Advanced Debugging December 2002 TECTURE S 7 25 FLI and C Models Foreign Architecture Init Cont Foreign Architecture Init Cont C Initialization function calls FLI functions to create and sensitize a process to be called during simulation e Allocates memory to hold variables for this instance Registers callbacks for save and restore Saves handles of signals in port list Creates drivers on ports to be driven Creates one or more processes Sensitizes processes to a list of signals The declaration of an initialization function is init func mtiRegionIdT region char param mtilnterfaceListT generics mtilnterfaceListT ports 7 13 ModelSim Advanced Debugging FLI and C Models Copyright 2002 Mentor Graphics Corporation Notes Entry point for the foreign C model
187. nitial state and then you can multiple normal states The interconnects or the interfaces between those bubbles you can define both conditions and signal assignments There are different ways that you can create them Either Mealy or Moore or a hybrids of Mealy and Moore machines Also you have priorities that you can attach to the interfaces Here this is what you will see as the result of rendering a graphic representation from a state diagram or a state machine in your code And this would be post animation So you will see the colors change as we step through the results of the analysis You first have to run the analysis and save the results and then you can step through an animation to help you determine what is going on within your ModelSim Advanced Debugging 9 13 December 2002 Debug Detective state machine You have animation and simulation control within the state diagram 9 14 ModelSim Advanced Debugging December 2002 Debug Detective Flow Chart Flow Chart Flow Chart e Simulation Control e Set Breakpoints e Simulation cross probe Simulation amp Animation Toolbars amp Menus n L Simulation Tools E EU Et E2 8 P OD 06 OS EP 6 ER I p4 I Animation Tools do b M M dti os d 9 13 ModelSim Advanced Debugging Debug Detective Overview Copyright 2002 Mentor Graphics Corporation Notes Some people prefer flow charts There are a lot of te
188. nitors Cont Monitors Cont 1001 IV Break On Value Break On Value Break On Value 00110010001000000000000000000001 29 Subtract 1 from R 2 Bind Cursor Movement ModelSim EE Plus 5 3d jor x File Edit Design View Run Macro Options Window Help Zoom Format Window s O fl wy BP view 3 c1 o1 D2 0000000000000001 structure signals variables process source wave list dataflow 68966548 VSIM 5 build window ls half acc 787658404 VSIM 6 gt run all cl ol a 9 cl ol b 1 Break on Reg 1001 Simulation stop requested Vol result 8 run ol ccode 0100 a1 carryout 1 VSIM 8 gt B21 overflow 0 Now 763us Delta 3 sit testbench cl ol VA 762961 ns m el I 4 gt x 762181 ns to 763040 ns 2 21 ModelSim Advanced Debugging Tcl Tk Overview Copyright 2002 Mentor Graphics Corporation 7 Notes ModelSim Advanced Debugging 2 21 December 2002 Tcl Tk Overview Additional Tcl Tk Resources Additional Tcl Tk Resources T ModelSim SE PLUS 5 6 File Edit View Compile Simulate Tools Debug Window Help ModelSim Help e Help gt Tcl Help e Help gt Tcl Man Pages Tcl Tk Books Manuals Newsgroups ga std_devslopers e comp lang tcl Web Help a e http www model com resources tcltk asp e http scriptics com Atthe ModelSim or VSIM prompt e VSIM gt help command name gt
189. nstantiated under a testbench or larger system simulation 8 17 ModelSim Advanced Debugging Debugging Copyright 2002 Mentor Graphics Corporation Notes ModelSim Advanced Debugging 8 17 December 2002 Debugging SDF Instance Specification SDF Instance Specification Example ramwrn_1 8 18 ModelSim Advanced Debugging Debugging Copyright 2002 Mentor Graphics Corporation s Notes 8 18 ModelSim Advanced Debugging December 2002 Debugging Issues With SDF Instance Specification Cont Issues With SDF Instance Specification Cont Example The problem e The instance hierarchical path mentioned does not exist testbench ramwrn_1 in the loaded design e By default the hierarchical path that is used is the top level entity concatenated with the instance path that exists in the sdf file ramwrn 1 and block 1 8 19 ModelSim Advanced Debugging Debugging Copyright 2002 Mentor Graphics Corporation Notes ModelSim Advanced Debugging 8 19 December 2002 Debugging Fixing Instance Specification Problems Fixing Instance Specification Problems The Fix e Specify the region in ModelSim e The correct region is the testbench entity name testbench e The instance name is not ramwrn_1 It is the design s instantiation name dut within testbench e The correct hierarchical path and command line syntax working from the C Designs directory vsim sd
190. ntiations in the VHDL source files There is no space between G and lt Name gt lt Value gt 8 44 ModelSim Advanced Debugging December 2002 Debugging 3 T Set a few Force values to toggle the clock clk the active low reset rst and the updn direction control LO count down HI count up Run the simulation for an adequate amount of time to test count up count down and rollover Examine the count_opt q output in the ModelSim wave window and verify that it is 16 bits Simulate counter_opt again and assign the generic N with a different value ModelSim provides the capability to debug your code and exercise what if scenarios by changing the value of generics within ModelSim before going back to the VHDL source files and updating the generic values Quit ModelSim when completed quit f Lab 8 Scripts Part 3 step 1 labs lab8 math compile do Part 3 step 2 labs lab8 math sim_gold do Part 3 steps 3 6 labs lab8 math math mp2 vhdl gate do Part 4 steps 1 4 labs lab8 math part4 compare 1 do Part 4 steps 5 labs lab8 math part4 compare 2 do Part 4 steps 6 labs lab8 math part4 compare 3 do Part 6 step 1 labs labS math compile opt do Part 6 step 2 labs lab8 math sim_gold_opt do Part 6 steps 3 6 labs lab8 math math opt mp2 vhdl gate do Part 6 steps 7 10 labs lab8 math part6 compare 1 do ModelSim Advanced Debugging 8 45 December 2002 Debugging Part 6 steps 11 labs l
191. ny allocated memory and resetting global static variables When quit sim command is given to vsim restart callbacks are called because the simulator is not completely quitting but may be restarting the previous design or loading a new design mti_AddRestoreCB adds a simulator restore callback The same function can be added multiple times with possibly a different parameter each time During a restore all callbacks in the list are called with their respective parameters The callback function should restore its saved state at this time mti_AddRestoreCB 0 must be called from a foreign initialization function in order for the callback to work Specify the function either in the foreign attribute string of a foreign architecture or in the foreign string option of a vsim command mti AddSimStatusCB adds a simulator run status change callback The same function can be added multiple times with possibly a different parameter each time Whenever the simulator run status changes all callbacks in the list are called with their respective parameters pull a second parameter of type int which is 1 when the simulator is about to start a run and 0 when the run completes 7 12 ModelSim Advanced Debugging December 2002 FLI and C Models Hierarchy Scanning Hierarchy Scanning mti_GetTopRegion mti_NextRegion mti_GetCurrentRegion mti FirstProcess mti_FirstSignal mti NextProcess mti NextSignal mti GetPrimaryName mti FirstLowerRegion mti GetSecon
192. ogic 1164 body podio ANN Loading d 55b2b win32 verlog v_typestbods reg spy top reset Loading work middelonb reg spy top clock Loading work counter 1t do wave do run al i reg 7 7 spy top count fo wave do run al view structure view source view signals 7 0 t es Ht INFO int_signal_spy Driving py lop count with test_counte dut inst LEAF Count ia AA I un t INFO ini signal spy Driving spy_top_reset with test_counter dut inet leaf reset 1730 int 1t INFO ini signal spy Driving spy_top_clock with test_counter dut ins Vieaf ckk bot Hi Break at Teounter v ne 23 middie 5 10 dut inst count cik rst signals MSIM 2 gt _notenad wave dn is initial Clock generator INow 10009 ns Delta 0 simest counter E begin clk 5 i xi EE oi 10 forever 10 elk lel Fie Edt Window File Edt View Window sud Axel niddelorj initial Test stimulus begin leaf counter 0 Package vl types ree 5 rst i 4 rst o 10000 stop end Package std logic 1164 Package standard initial sim test cNinter egt spy top count i d Rk X 1 SQ cri HES he pone moo misen te ka test counter py top clock spy top clock 1 end amit_signal_spy test_counter dut inst LEAF Count init_signal_spy test_counter dut inst leaf reset init_signal_spy test_counter dut inst leaf clk bot z Iz
193. oj x File Edit View Diagram Simulation Window Help t x Ca d 9 PAP R7 A z me gt ull 4 es IE HHHTSOFXNSEEIES 4 pm NS Ready 9 30 Z ModelSim Advanced Debugging December 2002 Debug Detective Once the diagram is opened from ModelSim an additional simulation toolbar becomes available This will enable you to support cross probing between the simulator and source design objects in Debug Detective Toolbars are normally displayed automatically at the bottom of the diagram windows However they can be undocked moved docked or hidden in the same way as the other toolbars in the HDL Designer Series tools Add Probes to the Design 1 Make the uart top block diagram active 2 Choose Edit gt Select All from the menu and select all of the signals on the diagram Finally click the 8 button in the block diagram toolbar to add probes to the design You will notice that the probes are added to the block diagram and they also appear as a list in the ModelSim window You can use the shortcut Ctrl A to select all of the signals in a block diagram 3 Add a wave window to the design by using the button in the block diagram toolbar This will display all of the selected signals View and Monitor the Signals Debug Detective allows you to monitor signal values as they change during simulation This can be achieved by using either the signals or the wave wi
194. olbar Block Diagram Toolbar 1st select the signals in the block diagram EL ty fy Su OM p R EBET ERE Delete Wave Highlight Object Just Fre data Juant _tb i1 enable_rey_clk enable Delete All Probes en Add List Signal Info Add Probe _ J Delete List Delete Probe I m 704 ns to 1747 ns E Signal uart_tb 11 data_in EE 1 Aray 7 downto 0 of eit Yemen Ae 2 Fle Edi Markers Prop Window l Value 00000000 nsa fuart_tb ii inty uart_th it ser_if select l MAE dua d ds T delta uart_tb il data_iny H D Signal uart tb data n uarL tb ii clk div en uart tb fl xmitdt en4 0 Driver uari tb iD tester top fubrt tb it clr 0 Signal uart_tb data_in 6 O Driver uart tb il tester top 0 Signal uart_tb data_in 5 100 40 O 1 0 00000000 110 0 Driver uart tb i tester top 600 0 O 1 0 00000110 110 0 Signal uart_tb data_in 4 2200 0 O 1 0 00000000 110 O Driver uart tb iD tester top 3700 42 0 0 0 00000000 001 j 0 Signal uart_tb data_in 3 5 Ll O Driver uart_th iD tester_top PE Pz 0 Signal uart_tb data_in 2 0 Driver uart_tb i0 tester_top 0 Signal uart_tb data_in T 0 Driver uart_tb i0 tester_top 0 Signal uart_tb data_in Q O Driver uart_tb il tester_top ii i zi 9 9 ModelSim Advanced Debugging Debug Detective Overview Copyright 2002 Mentor Graphics Corporation
195. om When you have more than one cursor each time box appears in a separate track at the bottom of the display ModelSim also adds a delta measurement showing the time difference between two adjacent cursor positions Clicking in a waveform display allows the cursor closest to the mouse to position itself to the selected position Another way to position multiple cursors is to use the mouse in the time box tracks at the bottom of the display There are also toolbar buttons Find Previous Transition and Find Next Transition that you can move the cursors with ModelSim Advanced Debugging 1 31 December 2002 Review ModelSim Windows List Window List Window Display the results of simulation in tabular format e Tracks time and delta in the left pane BS list lolx File Edit View Tools Debug Window ns tst_pseudo clock tst_pseudo storage delta tst_pseudo reset tst_pseudo expected tst pseudo data 0 000 0 X X X XXXXXXXXXXXXXXXXXXXX BPS um d 1 18 ModelSim Advanced Debugging ModelSim Windows Copyright 2002 Mentor Graphics Corporation Notes HDL items you can view e VHDL items Signals processes and shared variables e Verilog items Nets and registers variables Comparison items Comparison registers and comparison signals e Virtual items Virtual signals and functions Note Constants generics and parameters are not viewable in the List or Wave windows 1 32 ModelSim Advanced Debugging Decemb
196. on of the following topics Virtual objects e Signals Regions Functions Types How to create and use virtual objects 5 13 ModelSim Advanced Debugging Virtual Signals Copyright 2002 Mentor Graphics Corporation Notes 5 16 ModelSim Advanced Debugging December 2002 Module 6 Waveform Compare Objectives Upon completion of this module you will be able to Describe Waveform Compare features Describe the asynchronous and synchronous Waveform Compare capabilities Demonstrate the Waveform Compare Wizard List Tcl commands applicable to Waveform Compare Describe compressed waveform files wlf wolf files ModelSim Advanced Debugging 6 1 December 2002 Waveform Compare Module Overview Module Overview In this module we will discuss Saving Waveform Datasets Opening Datasets Viewing Dataset Structure Managing Datasets Comparing Waveforms Adding Signals Regions and Clocks Compare Objects in List Window Comparing Hierarchical and Flattened Designs Datasets and Tcl Commands ft 9 9 9 9 9 9 6 2 ModelSim Advanced Debugging Waveform Compare Copyright 2002 Mentor Graphics Corporation Notes ModelSim Advanced Debugging December 2002 Waveform Compare Saving Waveform Datasets Saving Waveform Datasets Basic Method e Runa simulation and save the the reference dataset as the golden results ModelSim gt vsim wlf gold wlf testbench name gt or VSIM gt quit
197. onditions when evaluated C Fiedlengh Simulation time D start 4 Active Clock Edges Off Mark conditions when evaluated only Control the animation activity Cancel p 9 18 ModelSim Advanced Debugging Debug Detective Overview Copyright 2002 Mentor Graphics Corporation Notes You can control the activity trail by specifying a maximum number of events and specified conditions for evaluation This data will determine when it should be evaluated The active clock edges setting controls the animation activity based on the clock timing When starting leave everything in its default position which is typically where most people leave the settings If you are already into your simulation process and you know that your problems manifest themselves at for instance 300 microseconds down stream then you can run just to that point Start the activity trail from that point for a fixed length and then capture that data set Use the camera icon to capture the data This method should be a more efficient mechanism for helping to identify your problem ModelSim Advanced Debugging 9 23 December 2002 Debug Detective When you go back to view your diagram and look at the animation you may see some differences Initially there are no colors displayed As you step through the animation you will see the changes in color 9 24 ModelSim Advanced Debugging December 2002 Debug Detective Animation Act
198. oolbar by using the buttons e Left double arrow Step backward through animation history e Right double arrow Step forward through animation history ModelSim Advanced Debugging 9 21 December 2002 Debug Detective e Right arrow with circle Sets view mode to step by states e Right arrow with hourglass Move to a specified simulation time Left arrow with line Move to the start of simulation time e Right arrow with line Move to latest simulation time The button on the right that looks like gears is the Cause button It moves the ModelSim Wave and List windows to the current animation time The rightmost button that looks like a broken chain is the Link Diagrams button It links all currently animated diagrams 9 22 ModelSim Advanced Debugging December 2002 Debug Detective Animation Toolbar Animation Toolbar In Capture mode the State Machine and Animation Tools Flow Chart objects become white to display the simulation progress Data Capture Clear Captured Events Activity Trails 3 work xmit_rcv_control fsm Xmit_current_state 2 of 2 Read only State Diagn Ini x Ele Edt View Disgram Simulation Animation Window Help Show Animation Applies to all windows in the current simulation x r Capture r Display Maximum number of events C From Start ST al 10000 C From Time gt gt bo bx K M in tad 92 B Ou C
199. opyright 2002 Mentor Graphics Corporation Notes ModelSim Advanced Debugging 4 37 December 2002 Analyzing Performance Lab 4 Analyzing Performance Introduction This lab will allow the study of the performance impacts of using different coding styles data types and design structure We will also use code coverage to examine simulation coverage results The design is a circuit that decodes 24 Bit Input Vectors with 20 comparisons It is made up of approx 2500 Gates It is developed to study the effect of coding styles of large decode blocks Directions To set up the lab invoke ModelSim and change directory File Change Directory to the labs lab4 decoder20x24 directory Then create a new project file by choosing the File New Project menu item For the project name use perflab Click on Add Existing File in the Add items to the Project dialog box Click on Browse and select all the vhd files in the decoder20x24 directory Leave the radio button checked that says Reference from current location Close the Add items to the Project dialog box after the files have been added to the project 1 First we will simulate the decoder design that is implemented as a large case statement To do this select the decoder case stdlogic vhd file and right click on it Then select Compile gt Compile Selected Compile the testbench top loop tb vhd by right clicking on it and selecting Compile gt
200. ore lines or coverage on optimized packages Coverage is started by using the coverage switch on VSIM There is a bar graph that allows you to view a summary of what is going on in each file Also the line counts are annotated onto the source window Most designer have more then one set of vectors to apply to the UUT ModelSim also supports appending simulation coverage runs ModelSim Advanced Debugging 4 5 December 2002 Analyzing Performance Misses Reporting and Exclusion Misses Reporting and Exclusion coverage_summary Elle Coverage Report src control vhd stc leltieve vhd stc tingil vhd stc store vhd C Apps Modeltech win32 vhd _sr C Apps Modeltech win32 vhdl_src C Apps Modeltech win32 vhdl_sre C Apps Modeltech win32 vhdl_st FOR data value IN 0 TO 11 LOOP New Misses Window switch lt conv std logic vector data value 4 New Reporting mcn csb BUD WAIT FOR 100 NS Misses Excluded BE File Edit View Tools Debug Window SsUS X B t OA H oN OTH wrb lt 0 csb lt 1 switch lt 0000 IF test true THEN FOR data value IN O TO 11 LOOP Exclude Files And Or Lines Es r 7 MM vatan t 7 Ll Exclude Ei a Do Not Exclude Coverage on Selected Lines using RMB Do Not Enctude Ente Fie Cancel 0 WAIT FOR 200 o WAIT FOR 200 o END LOOP I 4 gt testring vhd EES E Ln 1 Cok 0 readony 4 6 Mo
201. orm Compare Summary Summary This module introduced and explored the application of the following topics Waveform Datasets Dataset and ModelSim Commands Comparing Waveforms Adding Signals Regions and Clocks Setting Compare Objects in the List Window Saving Compare Differences 9 9 9 9 9 6 26 ModelSim Advanced Debugging Waveform Compare Copyright 2002 Mentor Graphics Corporation Notes 6 26 ModelSim Advanced Debugging December 2002 Waveform Compare Lab 6 Waveform Compare Introduction The purpose of this lab is to familiarize you with how to do waveform comparisons Many customers will want to use this feature to verify that their design changes didn t break anything unexpected Without this feature users have in the past had to resort to saving VCD or list window files and writing C or perl scripts to validate that the results are still correct Setting up a waveform compare is very easy In this lab you ll run two simulations and compare the differences Then you ll run a compare against two existing waveform files using an existing script Directions 1 Open ModelSim and create a new project file Pick the menu item File gt New Project Type in wavecomp for your project name and put it in the labs lab6 directory 2 Add the files by using the right mouse button RMB and select Add to Project Existing File Make sure the radio button labeled Reference from current
202. owledge of advanced debugging techniques using ModelSim It is assumed that the student has some prior design experience What this course is not e An exhaustive examination of design flow Instead this course explores advanced simulation debugging techniques using ModelSim e An explanation of FPGA or ASIC technology HDL language constructs or design e An introduction to ModelSim Prerequisite Knowledge e Students should have some prior knowledge of the ModelSim tool e Students should have the ability to read write and understand HDL code e Students should understand schematic digital simulation and HDL design concepts ModelSim Advanced Debugging xv December 2002 About This Training Workbook e Those students who do not have previous experience with ModelSim are encouraged to take HDL Simulation With ModelSim About the References The ModelSim tool contains online help and or the complete online manual set Students are encouraged to refer to these materials during the course of the class xvi ModelSim Advanced Debugging December 2002 Module 1 Review ModelSim Windows Objectives Upon completion of this module you will be able to e List the different windows available in ModelSim e Describe some basic features of each window Describe where to go for help ModelSim Advanced Debugging 1 1 December 2002 Review ModelSim Windows Module Overview Module Overview In this module we will
203. p mtiSignalldT outp mtiProcessIdT proc ip inst rec mti Malloc sizeof inst rec Allocate Memory for Instance ip gt inl mti_FindPort ports inl 4 Save Ids for Signals Drivers ip gt in2 mti FindPort ports in2 outp mti FindPort ports outl Create Output Driver ip gt outl mti CreateDriver outp Create Process mti Sensitize proc ip inl MTI EVENT proc mti CreateProcess pl do and ip es Sensitize Process to Inputs mti Sensitize proc ip gt in2 MTI EVENT 7 21 ModelSim Advanced Debugging FLI and C Models Copyright 2002 Mentor Graphics Corporation Notes ModelSim Advanced Debugging 7 37 December 2002 FLI and C Models C Subprograms C Subprograms To call a foreign C subprogram you must write a VHDL subprogram declaration that has the equivalent VHDL parameters and return type Then use the FOREIGN attribute to specify which C function and module to load The syntax of the FOREIGN attribute is almost identical to the syntax used for foreign architectures Functions e With integer or enumeration return value e Inputs include integer enumeration real time and array Procedures e INs and INOUTs include integer enumeration real time and array e Access types not allowed of class signal 7 22 ModelSim Advanced Debugging FLI and C Models Copyright 2002 Mentor Graphics Corporation Notes Example procedure in params vhdl
204. pa decode inst amp chipa mode stuff Assuming chipa mode is of type integer and chipa alu a is of type std logic vector and chipa decode inst is a user defined enumeration this example creates a signal sim testbench stuff which is a record type with three fields corresponding to the three specified signals ModelSim Advanced Debugging 5 7 December 2002 Virtual Signals virtual signal chip instruction 23 21 address_mode This creates a three bit signal chip address_mode as an alias to the specified bits 5 8 ModelSim Advanced Debugging December 2002 Virtual Signals Virtual Regions Virtual Regions virtual region creates a new user defined design hierarchy region virtual region lt parentPath gt lt regionName gt lt parentPath gt e Full path to the region that will become the parent of the new region e Required lt regionName gt e Name you want for the new region e Required 5 7 ModelSim Advanced Debugging Virtual Signals Copyright 2002 Mentor Graphics Corporation Notes ModelSim Advanced Debugging 5 9 December 2002 Virtual Signals Virtual Functions Virtual Functions Known only by the GUI not the kernel Notaliases of combinations or elements of signals logged by the kernel Logical operations on logged signals Can be displayed in e Signals Window e List Window e Wave Window Expand Children Accessed using examine Can no
205. pare Compare the results of simulation e The current simulation against a saved waveform file e Asave waveform file against another saved waveform file e Different parts of the current simulation Two modes of operation e Continuous comparison With or without tolerances Specify the maximum time a test signal edge is allowed to lead or trail a reference signal e Clocked comparison Rising or Falling edge Delayed Clock Compare Ease of use e Scrollbars identify mis compared areas e Search for next previous mis compare e Annotate comments to waveform 6 6 ModelSim Advanced Debugging Waveform Compare Copyright 2002 Mentor Graphics Corporation Notes 6 6 ModelSim Advanced Debugging December 2002 Waveform Compare Compare Datasets Using Waveform Compare Cont Compare Datasets Using Waveform Compare Cont The Waveform Compare feature can be run in 3 different ways e Using the Comparison Wizard e Using the Menus e Using TCL commands Can be run in batch mode or interactively Can perform a transaction based compare Integrated with waveform database 6 7 ModelSim Advanced Debugging Waveform Compare Copyright 2002 Mentor Graphics Corporation Notes ModelSim Advanced Debugging 6 7 December 2002 Waveform Compare Waveform Compare Wizard Waveform Compare Wizard Te ModelSim SE PLUS 5 6 with Debug Detective ND o x File Edit view Compile Simulate Tools
206. poration Notes ModelSim Advanced Debugging 2 15 December 2002 Tcl Tk Overview Simulation Script Example Simulation Script Example Sample of a Eile Edit view Insert Format Tools Table Window Help 48 x User Defined Dc B amp l tT s 5m amp eeo c e Brmsa ET i Plain Text gt Courier New 10 z B Z U m mm m EE D 4 ii Simulation Script g e Delete Library work if existing file delete force work Create Library work vlib work Compile decoder using case statement testbench vcom decoder case stdlogic vhd vcom top loop tb vhd Load simulation vsim top std profile on Run simulation time run 16777214 ns view profile ranked puts t 52 c puts Look at the profile window notice the run time puts for the decoder using a CASE statement puts and press RETURN to continue puts Wait for Return key gets stdin quit sim 3 gt Page 1 Sec 1 gs at in Col REG pre s DR rr ae 2 16 ModelSim Advanced Debugging Tcl Tk Overview Copyright 2002 Mentor Graphics Corporation Notes 2 16 ModelSim Advanced Debugging December 2002 Tcl Tk Overview Tk Widget Overview Tk Widget Overview Tk widgets e Create a Tk widget by a Tcl command of the same name Invoking this command allows various ways to manipulate the widget depending upon the arguments Pathname e Pathname
207. r variables 7 28 ModelSim Advanced Debugging December 2002 FLI and C Models Enumerations Reals and Time Enumerations Reals and Time Enumeration object values are Real and Time types signals equated to the position number and variables require eight of the corresponding identifier bytes to store them Equivalent in a VHDL type declaration For to the following structures example e mtiTime64 structure defined in mti h defines low word and C Interface Values high word Type std_ulogic is e C double data type ur n GetSignalValuelndirect used to 0 2 obtain pointer to Signals bcr A GetVarValuelndirect used to n u E obtain pointer to Variables LU 6 H 7 8 7 15 ModelSim Advanced Debugging FLI and C Models Copyright 2002 Mentor Graphics Corporation Notes ModelSim Advanced Debugging 7 29 December 2002 FLI and C Models Arrays Arrays Arrays e The C type void is used for array type object values to point to the first element of the array of C type char for enumerated types double for REAL types mtiTime64T for TIME types mtilnit32T in all other cases e First element equals left bound of index range e Last element equals right bound of index range e Reminder std ulogic vector is an array of Enumerations The array is not NULL terminated as you would expect for a C string so you must call mti TickLength
208. rademarks of Novas Software Inc OakDSPCore is a registered trademark for DSP Group Inc Oracle Oracle8i and SQL Plus are trademarks or registered trademarks of Oracle Corporation PKZIP is a registered trademark of PKWARE Inc Pro CABLING and HARNESSDESIGN are trademarks or registered trademarks of Parametric Technology Corporation Quantic is a registered trademark of Quantic EMC Inc QUASAR is a trademark of ASM Lithography Holding N V Red Hat is a registered trademark of Red Hat Software Inc SCO and the SCO logo are trademarks or registered trademarks of Caldera International Inc Sneak Circuit Analysis Tool SCAT is a registered trademark of SoHaR Incorporated SPARC is a registered trademark and SPARCstation is a trademark of SPARC International Inc Sun Microsystems Sun Workstation and NeWS are registered trademarks of Sun Microsystems Inc Sun Sun 2 Sun 3 Sun 4 OpenWindows SunOS SunView NFS and NSE are trademarks of Sun Microsystems Inc SuperH is a trademark of Hitachi Ltd Synopsys Design Compiler DesignWare Library Compiler LM family PrimeTime SmartModel Speed Model Speed Modeling SimWave and Chronologic VCS are trademarks or registered trademark of Synopsys Inc TASKING is a registered trademark of Altium Limited Teamwork is a registered trademark of Computer Associates International Inc Tensilica and Xtensa are registered trademarks of Tensilica Inc Times and Helvetica are registered
209. ration ModelSim Advanced Debugging December 2002 Review ModelSim Windows Lab 1 Simulation and Debugging with the Dataflow Window Introduction This lab covers the simulation and debugging of a mixed design using the ModelSim Dataflow window The purpose of this lab is to show how fast and easy it is to simulate a design and to Chase X using the Dataflow window e g to trace the source of an unknown on the output of a signal Preparing and running the simulation 1 Start with one of the following for UNIX at the shell prompt vsim for Windows your option from a Windows shortcut icon from the Start menu or from a DOS prompt modelsim exe 2 Create a new project and call it mixed Make sure that the new project points to the labs lab1 directory From the Main window File gt Change Directory C labs lab1l File gt New gt Project mixed 3 Add source files to the project From the Add items to the Project dialog box select Add Existing File Add the following files select Reference from current location cache v memory v proc v set vhd top vhd util vhd The first three files are Verilog files the last three are the VHDL files ModelSim Advanced Debugging 1 37 December 2002 Review ModelSim Windows 1 38 Click Close to close the Add items to the Project dialog box Click the RMB in the Project tab view of the Main window Select Compile gt Compile Order
210. re are others that have slightly different behavior depending on when they are called and from which context e g mti_GetCurrentRegion and mti GetCallingRegion There are also several FLI functions that can be used on Verilog regions in addition to VHDL regions e g mti GetTopRegion Functions arguments are required unless marked as optional ModelSim Advanced Debugging December 2002 FLI and C Models FLI Callbacks FLI Callbacks mti_ScheduleWakeup mti AddEnvCB mti AddLoadDoneCB mti AddQuitCB mti AddRestartCB mti AddRestoreCB mti AddSimStatusCB These are a few examples of C routines called by ModelSim when certain conditions are met 7 8 ModelSim Advanced Debugging FLI and C Models Copyright 2002 Mentor Graphics Corporation Notes mti ScheduleWakeup schedules a VHDL process to wake up at a specific time A process can have no more than one pending wake up call A call to mti ScheduleWakeup cancels a prior pending wake up call for the specified process regardless of the delay values Delay time units are equivalent to the current simulator time unit setting mti AddEnvCB add an environment change callback The same function can be added multiple times with possibly a different parameter each time Whenever the simulator environment changes for example when the environment command is used all callbacks in this list are called with their respective parameters plus a second parameter that is a
211. replaced with code Other software programs can read or modify simulated values during simulation Delay logic values Design structure read only Useto link virtually any type of application into an HDL simulation Delay calculators and back annotators Custom output displays C language models Hardware modelers Co simulation environments e g digital and analog simulators Custom user interfaces and debug utilities Reading writing test vector files 7 3 ModelSim Advanced Debugging FLI and C Models Copyright 2002 Mentor Graphics Corporation Notes FLI routines are C programming language functions that provide procedural access to information within ModelSim A user written application can use these functions to traverse the hierarchy of an HDL design get information about and set the values of VHDL objects in the design get information about a simulation and control to some extent a simulation run The header file mti h externs all of the FLI functions and types that can be used by an FLI app Some definitions Foreign Architecture A foreign architecture is a design unit that is instantiated in a design but that does not generally contain any VHDL code Instead it is a link to a C model that can communicate to the rest of the design through the ports of ModelSim Advanced Debugging December 2002 7 3 FLI and C Models the foreign architecture Normally you would use a C model to create processes
212. rfaces Aspire Assess2000 SM AutoActive AutoCells AutoDissolve AutoFilter AutoFlow AutoLib AutoLinear AutoLink AutoLogic AutoLogic BLOCKS AutoLogic FRGA AutoLogic VHDL AutomotiveLib AutoPAR AutoTherm AutoTherm Duo AutoThermMCM AutoView Autowire Station AXEL AXEL Symbol Genie BISTArchitect BIST Compiler SM BIST In Place SM BIST Ready SM Board Architect Board Designer Board Layout Board Link Board Process Library Board Station Board Station Consumer BOLD Administrator BOLD Browser BOLD Composer BSDAtrchitect BSPBuilder Buy on Demand Cable Analyzer Cable Station CAECO Designer CAEFORM Calibre Calibre CB Calibre DRC Calibre DRC H Calibre Interactive Calibre LVS Calibre LVS H Calibre MDPview Calibre MGC Calibre OPCpro Calibre ORC Calibre PRINTimage Calibre PSMgate Calibre RVE Calibre WORKbench Calibre xRC CAM Station Capture Station CAPITAL CAPITAL Analysis CAPITAL Bridges CAPITAL Documents CAPITAL H CAPITAL Harness CAPITAL Harness Systems CAPITAL H the complete desktop engineer CAPITAL Insight CAPITAL Integration CAPITAL Manager CAPITAL Manufacturer CAPITAL Support CAPITAL Systems Cell Builder Cell Station CellFloor CellGraph CellPlace CellPower CellRoute Cen
213. rics named tpd vsim G lt Name gt lt Value gt e Same as g but will override values set in generic maps or instantiations 3 10 ModelSim Advanced Debugging Test Benches Copyright 2002 Mentor Graphics Corporation Notes 3 10 ModelSim Advanced Debugging December 2002 Test Benches Setting VHDL Generic Parameters Cont Setting VHDL Generic Parameters Cont Menu Simulate gt Simulate CL nix Design VHDL Verilog Libraries SDF Options e Add button allows you to eu specify generics values within l Wake Tver naa the current simulation Modif e Generic Name LM g lt Name gt lt Value gt Deet e Value VITAL TEXTIO Files STD INPUT T Disable Timing Checks Appropriate data type e Override Instance Use Vital 2 2b SDF Mapping default is Vital 95 r STD OUTPUT G lt Name gt lt Value gt Disable Glitch Generation Browse E ox Load m Genetic Name tpd Generic Name 1ns 3 11 ModelSim Advanced Debugging Test Benches Copyright 2002 Mentor Graphics Corporation Notes ModelSim Advanced Debugging 3 11 December 2002 Test Benches Setting VHDL Generic Parameters Cont Setting VHDL Generic Parameters Cont GUI Variables Window L variables e Viewable VHDL items File Edit View Window variables meem constants Ken generics a e Highlight the desir
214. rification Code Coverage Verification Code Coverage No Compiler Impact Start vsim With The coverage Switch vsim coverage work test bench rt1 Graphical and or Report File Feedback Extra column displays e File By File Bar Graph which lines of code e Line Annotation have been executed lx Sage 3 Se Pe nm E File Coverage Report al Pathname a ste eontral vhd AD O AND rxda last value i THEN src retrieve vhd 5 EE RXD Mark at sre tingtishd 12 write line out string Primar y Channel stc store vhd 12 writeline OUTPUT X z 178 END IF Ci Apps Modeltech win32 vhd src l 28 179 IF rxdb event AND rxdb O AND rxdb last value 1 THEN o 180 write line out string RXDB Mark at o 1851 write ne out o 182 xdc O AND rxdc last value 1 THEN RXDC Mark at 191 write line out now 182 writeline OUTPUT line out oe eee eee 165 write line out string RXDC Mark at 28 194 END PROCESS 186 write line out now zl 195 5 f control hd testing vhd Ls Misses Excluded Ln 1 Cok D readony 7 4 5 ModelSim Advanced Debugging Analyzing Performance Copyright 2002 Mentor Graphics Corporation Notes LI Line coverage is performed on the executable lines therefore it is possible to switch off some of the optimizations to see m
215. ring 64 char sul 1 U x Qn r vgn Ww p pm ea char foo val int len i mtiTypeIdT type copy vhdl string format and null terminate it mti GetArrayVarValue format array fstring type mti GetVarType format array C len mti TickLength type fstring len 0 get pointer to input bit_vector type mti _GetVarType vhdl array len mti TickLength type mti GetArrayVarValue vhdl array buf for iz0 i len it buf i sul buf i buf len 0 sprintf rstring fstring buf return_len strlen rstring Get pointer to result and store string to it val mti GetArrayVarValue return array NULL strncpy valrstring return len 7 24 ModelSim Advanced Debugging FLI and C Models Copyright 2002 Mentor Graphics Corporation Notes 7 40 ModelSim Advanced Debugging December 2002 FLI and C Models Enums and Arrays Enums and Arrays Reading and Setting Enums static void eval_enum ip Hint inst_rec ip DefineEnums to Make Code Readable P Example std ulogic U X 0 1 Z W L H enum boolean FALSE TRUE val a val b val out char enum literals Evaluate enum out enum a and enum b mti GetSignalValueused to read enums mti GetSignalValue ip enum a i val_b mti_GetSignalValue ip gt enum_b if val_a TRUE amp amp val_b TRUE val_a val_out TRUE else val_out FALSE we
216. ro and double click on the cmp2 do file This will execute the macro file which loads two datasets and sets up a comparison The interesting part here is that the miscompares of the signals are being filtered by the when condition set up in the macro If you edit the cmp2 do file type notepad cmp2 do look at the compare signal lines There are two comparisons for signal a and two for signal b The first comparison for each signal is a straightforward continuous compare The second compare only compares the signals when the state signal has a value of reading Maximize the wave window so you can see the waveforms in detail Look at the red markings for signal a and signal a reading Signal a reading is the gated compare and you can see that there are less differences than those on signal a Same is true for signal b There were also tolerances put on the signal comparisons Zoom in on some of the differences and see if you can find where the tolerances removed all or part of the miscompares Use the cursors to measure the area of the differences that were affected by the tolerances Was this a leading or trailing tolerance What was its value For signal a how many differences between the simple compare and the complex compare were filtered by the when reading condition How many differences were filtered by the tolerances When finished close the current comparison
217. roject Location Windows c labs lab9 dd_tutorial_ref uart_vhdl Unix users student labs lab9 dd tutorial ref uart vhdl Default Library Name work The message Loading Project UART will appear in the ModelSim window 3 Click on Close in the Add items to the Project dialog box Create a New Library 1 Using the right mouse button RMB click in the Main window in the library tab and select New gt Library from the pop up menu The Create a New Library dialog box will appear 2 Select the map to an existing library button and enter the following information into the Create a New Library dialog box Library Name UART Library Maps to select work from the drop down menu pick PROMPT vlib UART vmap UART work 3 Click the OK button 9 28 ModelSim Advanced Debugging December 2002 Debug Detective Compile the HDL Files To compile the HDL files run the following command from the ModelSim simulator do compile do Load the Design 1 Expand the work library in the library tab of the Main window Using the left mouse button LMB double click on uart_tb This will load the design 2 The ModelSim window now appears in Debug Detective mode The compiled design should now appear in the window on the sim tab in the ModelSim window Notice that the Show As Graphics w button appears on the ModelSim toolbar This button will enable you to view HDL Designer Series HDS diagrams on the fly while simulating designs in t
218. rs and a ModelSim source window showing the state machine source code uart xmit_rcv_control fsm Xmit_current_state 2 i OF x File Edi View Diagram Simulation Animation Window Help Blo 4 9 9 B Bh A B EL RL EIEL FP RO WSs m 7 gt gt pe DE M Di mrt Oe a BR Ready Z Animate the State Machine 1 Make the state diagram window active and resize the state diagram if necessary Enable animation data capture by clicking on the button and ModelSim Advanced Debugging 9 35 December 2002 Debug Detective notice that the state diagram is redrawn as an animation view with all the colors drained except for the finish_xmit state which is now shown in red 2 I JES File Edit View Diagram Simulation Animation Window Help Alo A PDA h A A work xmit_rcy_control fsm Xmit_current state b E E ET RP OD Oo 26 06 E7 oe fh bo 3 M M iaa dud oe d S Simulation time 9750 start PA 2 Run the simulator for the default timestep 100 nano seconds by using the l button or by choosing Simulation gt Run gt For Time in the state diagram window 9 36 ModelSim Advanced Debugging December 2002 Debug Detective Two states are now animated in the state diagram The current state e work xmit rcv controlfsm Xmit_current state Ex Bj x File Edit View Diagram Simulation Animation Window Help
219. rting test run 1000 force reset O0 force ready 1 run 100 force ready 0 run all when clk event and clk 1 and b 01100111 j set c examine bin testbench uut txblock c if c 1 echo Error test of signal C failed C c stop variable substitution use the variable s value contents passed to Tcl command as single word nested command evaluated amp substituted grouping command no substitution performed 3 14 ModelSim Advanced Debugging Test Benches Copyright 2002 Mentor Graphics Corporation Notes 3 14 ModelSim Advanced Debugging December 2002 Test Benches Interactive GUI Test Benches Interactive GUI Test Benches File Edit Cursor Zoom Compare Bookmark Format Window Very interactive v SES tei IA eX IA Fi Difficult to automate puie sy Slow execution speed mm top prw top pstrb top prdy Atop paddr top pdata zi list r Lx File Edi Markers Prop Window E T a at Ld wt te ns top p clk top p dete top p verbose top p rdy top p addr_r top p ay lected Signal top p addr4 top p dy top p rw4 top p rw_ry Signal Name EAEE ftop p strb top p strb r4 Value 1 00 0 1 0000 o o0 0009 00 O 1 0000 o o0 0009 p Kind 0 1 0000 o 00 0009 Freeze Drive Deposit O 1 0000 o 01 0009 D 0 zzzz o 0009 0 0 zzzz 01 0009 Delay For 0 Cancel After
220. run echo Run Time total run Seconds foreach module array names comp command comp command module module vsim work testbench bench 300 us quit sim 2 14 ModelSim Advanced Debugging Tcl Tk Overview Copyright 2002 Mentor Graphics Corporation Notes 2 14 ModelSim Advanced Debugging December 2002 Tcl Tk Overview Creating a Simulation Script Creating a Simulation Script Create your own simulation script using ModelSim commands and Tcl Start by saving the existing simulation s transcript and use it as an example e Modify it as needed M ModelSim SE PLUS 5 6 Compiling architecture tb1 of math_opt_tb Loading package my pack gt H ing entity E Close gt Loading entity increment opt Loading package Ipm components Import d t Loading entity mult opt Save 8t Model Technology ModelSim SE vcom 5 5 Com Delete gt piler 2002 03 Mar 15 2002 one Loading package standard Change Directory Loading package std logic 1154 UTE TP Loading package numeric std Compiling entity math_opt_tb HHHrHHHH Add to Project d Save Transcript As Loading entity math_opt ModelSim gt E lt No Context A Recent Directories _ Clear Transcript Recent Projects gt Quit Design Loaded gt 2 15 ModelSim Advanced Debugging Tcl Tk Overview Copyright 2002 Mentor Graphics Cor
221. run all You should now observe a successful simulation run Click on the Break icon to stop the simulation You have successfully corrected the FLI error ModelSim Advanced Debugging 7 55 December 2002 FLI and C Models Note Line 154 of testbench error c is a construct just for this lab to make sure the ModelSim will reliably crash on every platform step 7 7 56 ModelSim Advanced Debugging December 2002 Module 8 Debugging Objectives Upon completion of this module you will be able to Describe reasons to debug e List the sequence of debugging tasks Describe each of the two types of breakpoints Describe assertions and an example of an application of assertions Describe different methods of gathering and storing symptoms of errors Describe how to determine possible causes of errors e List three different methods to isolate exact causes of errors Describe how to resolve the following types of errors o Erroneous Data o Erratic Data o Iteration Violations o SDF Problems e Demonstrate debugging methods ModelSim Advanced Debugging 8 1 December 2002 Debugging Module Overview Module Overview In this module we will discuss 9 9 9 9 9 9 SO FH 9 9 9 9 When to debug Debugging Tasks Breakpoints Checkpoint and Restore Bus Checks Toggle and Stability Checking Batch Mode Simulation Unknown States Erroneous Data Iteration Violations Mixed Language Issues SDF Instance Specific
222. run time range checking Can result in a 2X speed increase Range checking can be enable using rangecheck noindexcheck for arrays O5 e Same as for vlog 4 31 ModelSim Advanced Debugging Analyzing Performance Copyright 2002 Mentor Graphics Corporation Notes 4 32 ModelSim Advanced Debugging December 2002 Analyzing Performance Using Elaboration Files Using Elaboration Files Compile Once vcom and or viog Run Elaboration Step Once vsim elab filename Simulate Multiple times vsim load_elab filename Standard ModelSim Flow vcom vsim vsim vsim COMPILE ELAB SIM SIM Optional ModelSim Flow using Elaboration File vsim vsim vsim vsim vcom elab load elab load elab load elab Time Savings CIC ACCENT NN NND 4 32 ModelSim Advanced Debugging Analyzing Performance Copyright 2002 Mentor Graphics Corporation Notes Elaboration refers to the process of generating native code for your platform The ModelSim simulator vsim elaborates every time you load a design If elaboration is a significant part of your overall simulation run time you can isolate the elaboration phase to improve your throughput In other words you create an elaboration file once and then simulate it multiple times Elaboration files can be used for RTL or gate level runs For example a multi million gate level run may take 20 minutes to elaborate and annotate SDF timing and an additional 20 minutes to run
223. ry tab 5 Notice that the last message during the elaboration phase was Loading tbio_error sl This is the compiled object for the C code used in the test bench 6 Run the design by typing run all 7 The design will stop abruptly and print a message similar to this Fatal Bad pointer access Time 63700 ns Iteration 5 Instance testbench textio inst Fatal error at line 0 7 52 ModelSim Advanced Debugging December 2002 FLI and C Models This error is coming from inside the ModelSim kernel These errors are caused by the internal data structures in ModelSim getting trashed somehow This can be due to either a bug in ModelSim or a bug in the user s PLI or FLI code This lab uses FLI code so we would be suspicious of the problem being in the FLI code and not the simulator x ModelSim SE PLUS 5 6 with Debug Detective File Edi View Compile Simulate Tools Debug Window Help Se SB E w4 E testbench testbench rtl game inst game_on graphical Wf load cards loader rtl m textio_inst testbench_io a lf Package black jack package Wf Package textio tka BP we GetModuleFileN ame Cannot create a file when that file already El exists GetModuleFileName Cannot create a file when that file already exists Fatal SIGSEGV Bad pointer access Time 63700 ns Iteration 5 Instance testbench textio_inst
224. s named forks named begins tasks and functions Virtual items are indicated by an orange diamond icon 1 12 ModelSim Advanced Debugging December 2002 Review ModelSim Windows Multiple Datasets Multiple Datasets Multiple datasets are shown as extra tabs y ModelSim SE PLUS 5 6 with Debug Detective File Edit View Compile Simulate Tools Debug Window Help esite E 100000 EL s Et 3 m Poi US opened as dataset gold tst_pseudo tst_pseudo compare start gold sim compare options track compare add recursive all wave Created 5 comparisons compare run Compare waiting for simulation to be run VSIM amp Project wavecomp gold tst_pser A4 1 9 ModelSim Advanced Debugging Model Sim Windows Copyright 2002 Mentor Graphics Corporation Notes Each dataset you open creates a Structure tab in the Main window workspace The tab is labeled with the name of the dataset and displays the same data as the basic Structure window Signal pathnames included in a waveform comparison are denoted by yellow triangles in the compare tab ModelSim Advanced Debugging 1 13 December 2002 Review ModelSim Windows Source Window Source Window Recompile code directly from the Source window e Tools gt Compile Set Breakpoints from the Source window e Click on blue line numbers designates executable code e Tools gt Breakpoints Menu options for Describe
225. s regions and functions e Explain how to create virtual signals regions and functions List some virtual commands and describe how to use them ModelSim Advanced Debugging 5 1 December 2002 Virtual Signals Module Overview Module Overview In this module we will discuss Virtual Objects e Virtual Signals e Virtual Regions e Virtual Functions e Virtual Types 5 2 ModelSim Advanced Debugging Virtual Signals Notes Copyright 2002 Mentor Graphics Corporation ModelSim Advanced Debugging December 2002 Virtual Signals Virtual Objects Virtual Objects Objects created in the user interface to display combinations or expressions of logged signals in the design Do not exist in kernel Supported in ModelSim v5 3 and newer Object Types e Virtual Signals e Virtual Regions e Virtual Functions e Virtual Types 5 3 ModelSim Advanced Debugging Virtual Signals Copyright 2002 Mentor Graphics Corporation Notes Virtual objects are signal like or region like objects created in the GUI that do not exist in the ModelSim simulation kernel ModelSim supports the following types of virtual objects e Virtual Signals e Virtual Functions e Virtual Regions e Virtual Types ModelSim Advanced Debugging 5 3 December 2002 Virtual Signals Virtual Signals Virtual Signals Aliases for combinations of signals Aliases for sub elements of signals Can be displayed in e Signals
226. s testbench development and debug for VHDL amp mixed language environments 3 18 ModelSim Advanced Debugging Test Benches Copyright 2002 Mentor Graphics Corporation Notes ModelSim Advanced Debugging 3 19 December 2002 Test Benches it signal spy VHDL Utility init signal spy VHDL Utility Modelsim SE EE PL Beta 3 B File Edit Design View Project Run Compare Macro Options Window Help top vhd Options Window en dug acm EFI 100 4 ELEY R 39 r1 2660 Reading from addr 08 2700 Read hit to set 3 2740 Reading from addr 09 2780 Read hit to set 3 Read Write test done Note stop proc v 75 _ Time 2820 ns Iteration O Instance top p Break at proc v line 75 signals VSIM 2 gt add wave top_prdy_reg view variables variables destroy variables CEI vsim 5 gt Now 2 820 ns Delta 0 structure Fie Edit window View Window prdy paddr pdata top prd reg 0 Package vl types Package util Package std logic 1164 Parkane standard wave default iDi xi File Edit Cursor zoom Compare Bc Format Window SHS e NO 3D QQQ EF LETH ie fle 28 of Aopo o Aop top_cik_bit o Ztop c eo Ztop to 30000000 top tap_paddr_b Aop c_ V paddr 8 Aop c_ s0 bot_std Ztop srdy vloa top r anay aray log opb 2 ankb Ztop c V 4 top aab 00000000 ZtopAc V arayb pooo0000
227. sim ModelSim gt copy vsim wlf gold wlf More Complex Method using SDF back annotation e Runa simulation using the SDF timing and save the waveform as the golden results At the ModelSim prompt type vsim sdftyp chip time_sim sdf wlf gold wlf tst pseudo add wave run 10 us quit sim 6 3 ModelSim Advanced Debugging Waveform Compare Copyright 2002 Mentor Graphics Corporation Notes All methods Make sure to type quit sim after the simulation has finished This ensures that the waveform file gets closed Method using SDF back annotation Using sdftyp will run the simulation using typical SDF timing The other two choices are sdfmin and sdfmax ModelSim Advanced Debugging 6 3 December 2002 Waveform Compare Opening Datasets Opening Datasets Method of displaying multiple waveform logfiles Default waveform saved as vsim wlf Can be saved and renamed for later use ud Modelsim SE PLUS 5 6 with Debug Detective Display signals from j Modelsim 5 6 wi H di fferen t lo files wi f files File Edit Yiew Compile Simulate Tools Debug Window Help g s SB HF woel Et oP we simultaneously e Same wave or list window tst_pseudo tst_pseudo chip pseudo clock ibuf X CKBUF GND 0 X ZERO Project wavecomp Now 1 us Delta 2 Max total difference per signal limit of 10 O reached on signal compare tst pseudo A datac d
228. ss Function returns NULL if there are no more processes mti GetPrimaryName gets the primary name of a region entity package or module Returns the primary name of the specified VHDL or Verilog region that an entity package or module name If the region is not a primary design unit then the parent primary design unit is used The return pointer must not be freed 7 14 ModelSim Advanced Debugging December 2002 FLI and C Models mti_GetSecondaryName gets the secondary name of a VHDL region namely an architecture name If the region is not a secondary design unit then the parent secondary design unit is used NULL is returned if the region is a VHDL package or a Verilog region that was not compiled with fast mti_GetProcessName gets the name of a VHDL process The returned pointer must not be freed ModelSim Advanced Debugging 7 15 December 2002 FLI and C Models Signals and Variables Signals and Variables mti_FindDriver mti_GetSignalName mti FindPort mti GetVarName mti FindSignal mti SetSignalValue mti FindVar mti SetVarValue These are a few examples of C routines called by ModelSim to modify or examine signals variables 7 10 ModelSim Advanced Debugging FLI and C Models Copyright 2002 Mentor Graphics Corporation Notes mti FindDriver determines if a VHDL signal has any drivers on it If no drivers are found for a scalar signal or if any element of an array signal does not have a driver th
229. st benches implemented as flow charts so if you render your test bench as a diagram you will see a flow chart by default You also have simulation and animation control from within the flow chart window Flow chart objects e Light blue square box action box e Dark blue square box with double border hierarchical action box e Yellow diamond Decision box ModelSim Advanced Debugging 9 15 December 2002 Debug Detective 9 16 Red octagonal box wait box Purple rounded rectangle Start End box Green oval Start end loop box Yellow polygon start end case box ModelSim Advanced Debugging December 2002 Debug Detective Simulation Control Simulation Control Simulation Tools x 1 EL ET ROG 306 EP I EB BE EJ IE U 4 79 3 ef Step Restart Simulator Step Over s z 5 ModelSim SE PLUS 5 5e with Debug Detective loj x File Edit Design View Project Run Compare Macro Options Run to Next Event Window Help Sum simum u Continue Y zl hds add probe uart_tb I1 start smit hds add probe uart tb l1 enable write hds add probe uart tb l1 enable rcv clk H hds add probe uart_tb I1 ser if data hds add probe uart_tb I1 int hds add probe uart tb l1 enable smit cl hds add probe uart_tb I1 sout E Now Ojns Delta 0 E uart_tb uart_tb struc fimi Bf 10 tester flow i1 uart top struc Project UART Run Forever
230. sters n access to nets p access to ports b access to individual bits of a vector access to Line number 4 29 ModelSim Advanced Debugging Analyzing Performance Copyright 2002 Mentor Graphics Corporation Notes 4 30 ModelSim Advanced Debugging December 2002 Analyzing Performance vlog Commands vlog Commands fast e Allows parameter propagation and global optimization e Must compile source code for entire design no incremental compilation e Once the design is compiled it can be simulated in the usual way e vlog O5 fast debugCellOpt testbench v cpu rtl v Compiles all modules in testbench v and cpu rtl v using global optimizations e vlog O5 fast opt1l debugCellOpt testbench v cpu rtl v Assigns the secondary name opt1 to the optimized modules e vlog O5 fast debugCellOpt tacc rn testbench v cpu rtl v Enables register and net access in all modules 4 30 ModelSim Advanced Debugging Analyzing Performance Copyright 2002 Mentor Graphics Corporation Notes ModelSim Advanced Debugging 4 31 December 2002 Analyzing Performance vcom Commands vcom Commands rangecheck e Enabled by default e Enables run time range checking Verifies that a scalar value defined with a range subtype is always assigned a value within its range e Range checking can be disabled using norangecheck norangecheck Disabled by default Disables
231. sting data 8 22 ModelSim Advanced Debugging Debugging Copyright 2002 Mentor Graphics Corporation Notes 8 22 ModelSim Advanced Debugging December 2002 Debugging Missing Generics Cont Missing Generics Cont The last two generics in the example are tsetup_d_cp_negedge_posedge tsetup_d_cp_posedge_posedge The associated lines in the SDF file are CELL CELLTYPE reg INSTANCE reg1 TIMINGCHECK SETUP negedge D posedge CP 0 5 0 7 0 9 8 23 ModelSim Advanced Debugging Debugging Copyright 2002 Mentor Graphics Corporation Notes ModelSim Advanced Debugging 8 23 December 2002 Debugging Missing Generics Cont Missing Generics Cont Possible cause of the problem e The VITAL gate level model was written with no edge specifier associated with the D port and would look like the following Entity reg IS GENERIC tsetup d cp noedge posedge VitalDelayType 2 0 75 ns i PORT The corresponding SDF entry that would work with this generic would be SETUP D posedge CP 0 5 0 7 0 9 The SDF file expects the VITAL model to contain generics that are unique to the rising and falling edge of D The VITAL model was written with no regard to the rising or falling edge of D Contact your ASIC or FPGA vendor for further assistance 8 24 ModelSim Advanced Debugging Debugging Copyright 2002 Mentor Graphics Corporation Notes 8 24 Model
232. sults as a ranked profile by typing VSIM view profile ranked Note that 24 of the simulation time is spent on line 32 of the decoder case stdlogic vhd file Click on this line in the Ranked Profile window to display the decoder case stdlogic vhd file in the Source window Line 32 is a conversion function converting std logic vector to integer ModelSim Advanced Debugging 4 39 December 2002 Analyzing Performance 4 40 Close the Ranked Profile window and the Coverage Summary window Reset the coverage data statistics by typing coverage clear in the ModelSim Main window Quit the current simulation quit sim and resimulate vsim top_std with profiling profile on and without code coverage for 16 ms time run 16 ms Compare the simulation run time with code coverage off Decoder run time for Case implementation using stdlogic types w o code coverage Code Coverage consumed minimal overhead run time Now go back to the Project tab and recompile the design but this time use the decoder if stdlogic vhd file select the file right click and select Compile Compile Selected This will compile the same decoder implemented as an if statement instead of a case statement Recompile the testbench top loop tb vhd by right clicking on it and selecting Compile Compile Selected Load top std into the simulator vsim top std turn on the profiler profile on and then run the simulation again
233. t 2002 Mentor Graphics Corporation Notes 2 8 ModelSim Advanced Debugging December 2002 Tcl Tk Overview Command Substitution Command Substitution Command Substitution e Use the results of one command in an argument to another command set x 64 set y expr x 2 Nested Commands e Tcl treats everything between square brackets as a nested Tcl command e The nested command is evaluated and substituted into the bracketed text e Inthe example above the second argument of the second set command will be 128 2 9 ModelSim Advanced Debugging Tcl Tk Overview Copyright 2002 Mentor Graphics Corporation Notes ModelSim Advanced Debugging December 2002 Tcl Tk Overview Quotes Quotes Double quotes allow you to specify words that contain spaces set x 128 set y 64 set z x y is expr x y Everything between the quotes is passed to the set command as a single word uJ ModelSim SE PLUS 5 6 with Debug Detective File Edit View Compile Simulate Tools Debug Window Help Se BBE 14E SE ER 96 M P i 0S VSIM 13 gt set x 128 El EMI top std top std loop tb it 128 lf i dec 20424 dec 202 VSIM 14 set y 64 Bf Package std_logic_unsigned 64 Bf Package pkg dec 2024 VSIM 15 gt setz x y is expr x y Package numeric std 128 64 is 192 sim ee Project perflab Now 10 ms Delta 2 sim top_std Z4 2 10
234. t ns az s az cs delta 0 0 101 az5 10 0 000 state0 20 0 001 Statel 30 0 010 STATE2 40 0 011 my state3 50 0 100 foobar4 60 0 101 az5 70 0 110 rose6 80 0 111 yoyo 5 11 ModelSim Advanced Debugging Virtual Signals Notes Copyright 2002 Mentor Graphics Corporation The virtual type command creates a new enumerated type known only by the GUI not the kernel Virtual types are used to convert signal values to character strings The command works with signed integer values up to 64 bits virtual types list of strings lt name gt 5 14 ModelSim Advanced Debugging December 2002 Virtual Signals Combining Signals Combining Signals Signals or busses can be combined together into new busses These are created using Virtual Signals Combine Selected Signals Name control sianals P of Indexes c A ending C Descending wave default File Edit Cursor Zoom Compare Bookmark Format Window SHS B RK eT AQQQMiE ftap clk top prwy top pstrb top prdy top control signals top paddr top pdata top smw top sstrb Atop srdy Atop saddr top sdata 1853 ns to 2294 ns 5 12 ModelSim Advanced Debugging Virtual Signals Copyright 2002 Mentor Graphics Corporation Notes ModelSim Advanced Debugging 5 15 December 2002 Virtual Signals Summary Summary This module introduced and explored the applicati
235. t be set using force Inverse of a signal a type conversion or an OR reduction of the XOR of two vector signals 5 8 ModelSim Advanced Debugging Virtual Signals Copyright 2002 Mentor Graphics Corporation Notes Virtual functions behave in the GUI like signals but are not aliases of combinations or elements of signals logged by the kernel They consist of logical operations on logged signals and may be dependent on simulation time They may be displayed in the signals wave or list windows accessed by the examine command but cannot be set by the force command An example would be a virtual function defined as the inverse of a given signal a type conversion on a signal or a the OR reduction of the XOR of two vector signals 5 10 ModelSim Advanced Debugging December 2002 Virtual Signals Virtual Functions Cont Virtual Functions Cont Internally Created Virtual Hierarchical Context User defined Name virtual function env pati install pato impli expressionSting lt name gt ZO ud Parent Region Text String Expression Can Handle bit selects or slices of Verilog registers 5 9 ModelSim Advanced Debugging Virtual Signals Copyright 2002 Mentor Graphics Corporation Notes virtual function env lt path gt install lt path gt implicit lt expressionString gt lt name gt Creates a new signal known only by the GUI not the kernel that consists of logical operations on exis
236. t datasets selected the next step is to selecta comparison method Comparison Method After you specify datasets select signals to compare Compare All Signals compares all IS i signals in the test dataset against the signals in the reference dataset C Compare Top Level Ports Comparison Wizard I ed x Compare Top Level Ports compares C Specify Comparison by Signal Click the yes button and then next to the top level ports of the selected ii datasets Specify Comparison by Region add more signals to the comparison Would you like to add more signals to the comparison Specify Comparison by Signal opens Cc the structure browser to allow you to Yes select specific signals for comparison No Specify Comparison by Region opens the Add Comparison by Region dialog to allow selection of a specific reference region Comparison Wizard E lini xi lt Previous Next Click the button to compute the differences Compute Differences Now 7 Clicking the button runs the compare Compare waveforms are automatically created lt Previous Next Cancel Copyright 2002 Mentor Graphics Corporation 6 9 ModelSim Advanced Debugging Waveform Compare Notes ModelSim Advanced Debugging 6 9 December 2002 Waveform Compare Waveform Compare Menus 1 Start a compare Waveform Compare Menus rm Compare
237. tPath gt end info lt arguments gt list expand options lt arguments gt reload lt rulesFilename gt lt diffsFilename gt reset run lt startTime gt lt endTime gt savediffs lt diffsFilename gt saverules expand lt rulesFilename gt see lt arguments gt start lt arguments gt stop update Refer to the ModelSim Command Reference manual for further details on the compare command 6 19 ModelSim Advanced Debugging Waveform Compare Copyright 2002 Mentor Graphics Corporation Notes Refer to the ModelSim Command Reference manual for further details on the compare command ModelSim Advanced Debugging 6 19 December 2002 Waveform Compare Compare Example Compare Example dataset open min wlf min lt Open dataset min wlf min dataset open typ wlf typ ap Open dataset typ wif typ compare start maxtotal 1000 min typ lt Begin a new comparison and set upper limit to 1000 differences to record compare add recursive p Compare all signals in entire region design COmpare pos wage gps oo lt Continuous Compare of signal clk from module YP P tst pseudo in dataset min amp typ compare clock rising clk min tst pseudo clk Define a clocked compare strobe named clk that will sample signals on the rising edge of signal min tst_pseudo clk compare add clock clk label clocked data min tst pseudo data typ tst pseudo data Clocked compar
238. ta If the new value is different from the old value then an event occurs on the signal in the current delta If the specified signal is of type array real or time then the value type is considered to be void instead of long This function cannot be used to set the value of a signal of type record but it can be used to set the values on the individual scalar or array sub elements Setting a resolved signal is not the same as driving it After a resolved signal is set it may be changed to a new value the next time its resolution function is executed mti ScheduleDriver and mti ScheduleDriver64 can be used to drive a value onto a signal mti SetVarValue sets the value of a VHDL variable Effective immediately If the variable is of type array real or time then the value type is considered to be void instead of long This function cannot be used to set the value of a variable of type record but it can be used to set the values of the individual scalar or array sub elements 7 18 ModelSim Advanced Debugging December 2002 FLI and C Models Utilities Utilities mti Command mti CreateRegion mti AddCommand mti Delta mti AddTclCommand mti Free mti Break mti Malloc mti CreateArrayType mti Now mti CreateEnumType mti PrintMessage mti CreateSignal mti Realloc mti CreateProcess mti FatalError 7 11 ModelSim Advanced Debugging FLI and C Models Copyright 2002 Mentor Graphics Corporation Notes mti Command executes a
239. ta Types Using Checkpoint and Restore with FLI FLI C functions and Subprogram Examples Debugging and Tracing FLI Problems 9 9 9 9 7 32 ModelSim Advanced Debugging FLI and C Models Copyright 2002 Mentor Graphics Corporation Notes ModelSim Advanced Debugging 7 49 December 2002 FLI and C Models Lab 7 FLI Bug in C Code Introduction This lab explores various techniques used in debugging an FLI bug in C code We will use a slightly different version of the blackjack design used in the Tcl Tk testbench lab exercise There will be a bug that you will have to find in order to get correct simulation results Directions 1 To set up the lab invoke ModelSim and change directory to the labs lab7 blackjack directory use the cd command or the File Change Directory menu item Open ModelSim and select File Open gt Project Choose the Fli mpf project to load 2 Once loaded recompile the entire project In the ModelSim Main window click once using the right mouse button RMB Select Compile gt Compile Order When the Compile Order window loads select Auto Generate 7 50 ModelSim Advanced Debugging December 2002 FLI and C Models Compile Order Mj ModelSim SE PLUS 5 6 Reading C Modeltech_5 6 tcl vsim pref tcl Loading project debug_lab2 Dealer vhd ModelSim gt pwd FSM Control vhd C ModelSim Downloads debug blackjack Game_On vhd ModelSim gt Loader vhd packages vhd
240. terface toolkit part of Tcl Tk Allows scripts to create graphical objects e Set of calls which can be called from the Tcl language e Creates graphical widgets that can be used to build the interface to a tool e Used for creating new windows dialog boxes menus buttons key bindings and much more ModelSim GUI is mostly implemented in Tk e Allows easily extensible U I Modify ModelSim U I or add custom features 3rd Party Integration accomplished with Tk e Sometimes C is used as well 2 5 ModelSim Advanced Debugging Tcl Tk Overview Copyright 2002 Mentor Graphics Corporation Notes ModelSim Advanced Debugging 2 5 December 2002 Tcl Tk Overview Tcl Commands Tcl Commands Some builtin Tcl simulation commands are listed below append cd error flush glob info llength Isort pwd return string source 2 6 ModelSim Advanced Debugging Tcl Tk Overview Notes array break case catch close concat continue eof eval exec expr file for foreach format gets global history if incr insert join lappend list lindex lrange lreplace Isearch open pid proc puts read regexp regsub rename scan seek set split switch tell time trace unset uplevel upvar while Copyright 2002 Mentor Graphics Corporation For help on any of the commands listed here type help lt command name gt at the VSIM gt or ModelSim gt prompt Example vs1 M gt help force ModelSim Advanced Debugging Decemb
241. th is_array long now long sigval noFLI standard testpoint xcur testpoint now nti Now for cur testpoint testpoints cur testpoint cur testpoint cur testpoint nxt portnum cur testpoint portnum width tester ports portnun width is array tester ports portnun is array type if cur_testpoint gt type DRIVE if is exray if ip gt verbose sprintf buf TIME 4d drive signal 4s with value c n now tester ports portnum name convert enum to nvl9 char cur testpoint test val nti PrintMessage buf nti ScheduleDriver ip drivers portnun long cur testpoint test val 0 MTI INERTIAL else char tmpstring MAX PORT WIDTH convert enuns to nvl9 string cur testpoint test val tmpstring width if ip gt verbose sprintf buf TIME 4d drive signal array Xs with value s n now tester ports portnun name tmpstring nti PrintMessage buf mti ScheduleDriver ip drivers portnun long cur testpoint test val 0 MTI INERTIAL a a 4 gt Ready in1 Colt REC COL OVR READ A 3 13 ModelSim Advanced Debugging Test Benches Copyright 2002 Mentor Graphics Corporation Notes ModelSim Advanced Debugging December 2002 3 13 Test Benches Tcl Test Benches Tcl Test Benches Quick and easy to implement Medium level of abstraction Force clk 0 0 1 50 rep 100 Slow execution force reset 1 echo sta
242. the fast option Supported in ModelSim release 5 5c and newer Same optimization as fast Merges always blocks Performs cell and gate level optimization In lines combines instantiated modules Reduces eliminates events Improves memory performance e Supports incremental compilation Loads design units from the libraries and regenerates optimized code vlog t topt lt lib gt lt module gt vlog topt cpu_rtl Top level module is cpu rtl vlog topt testbench globals Design has two top level modules testbench amp globals 4 26 ModelSim Advanced Debugging Analyzing Performance Copyright 2002 Mentor Graphics Corporation Notes ModelSim Advanced Debugging 4 27 December 2002 Analyzing Performance vlog Commands for Gate Level Simulation vlog Commands for Gate Level Simulation debugCellOpt e Produces Transcript window output that identifies why certain cells in the design were not optimized e Used only with Verilog gate level libraries with fast opt switch e write cell_report command produces text file listing all modules Module top Architecture fast Module bottom cell Architecture fast Both top amp bottom compiled with fast bottom was optimized cell after the name of optimized module top was not optimized 4 27 ModelSim Advanced Debugging Analyzing Performance Copyright 2002 Mentor Graphics Corporation Notes 4 28 ModelSim Advanced Debuggin
243. the inverse of chip section1 clk virtual function install chip std logic vector amp chip vlog rega rega slv Creates a std logic vector equivalent of a verilog register rega and installs it as chip rega slv 5 12 ModelSim Advanced Debugging December 2002 Virtual Signals virtual function chip addr 11 0 Oxfab addr_eq_fab Creates a boolean signal chip addr eq fab that is true when chip addr 11 0 is equal to hex fab and false otherwise It is ok to mix VHDL signal path notation with Verilog part select notation virtual function gate chip siga XOR rtl chip siga siga di Creates a signal that is non zero only high during times at which a signal chip siga of the gate level version of a design does not match chip siga of the rtl version of a design ModelSim Advanced Debugging 5 13 December 2002 Virtual Signals Virtual Types Virtual Types Commonly used to create enumerations for array values in conjunction with virtual functions Known only by the GUI not the kernel VHDL code signai s s lt 000 010 100 110 after 10 after 30 after 50 after 70 ns ns ns ns 001 011 101 dag std logic vector 2 downto after after after after 0 i dole ns ns ns ns TCL code virtual type state0 State1 STATE2 my state3 foobar4 az5 rose6 yoyo7 mystate virtual function mystate s cs add list cs List outpu
244. the power of Tcl Tk to display simulation results This will involve adding some missing Tcl code to finish the design The design itself is a self contained Blackjack game written at the RTL Register Transfer Level level Blackjack is a card game where the aim is to have a hand of cards that adds up to score 21 Picture cards have a value of 10 and the Ace can have a value of 1 or 11 Black jack is the name given to a score of 21 with a picture card and an Ace The test bench for the design generates the clock and loads the playing cards into the internal memory There is a sequencer in the design that has a pseudo random number generator which selects the location in memory of the card to deal next This card is presented to the internal state machine that decides whether another card should be dealt based on a stick value The stick value can be adjusted as it is a generic on the entity of the state machine There is an accumulator that adds the values of the cards and presents the values at the outputs The design includes both VHDL and Verilog RTL code which is a common problem encountered when using IP It shows how simple and straightforward it is to mix HDL s in the simulator and still have the benefits of full debug Directions 1 To set up the lab invoke ModelSim and change directory to the labs lab3 blackjack directory use the cd command or the File Change Directory menu item 2 Next we need to compile all the desi
245. the simulator Can be debugged by e using the trace capability of ModelSim e adding fprintf stderr calls to C code and re running e attaching a debugger such as gdb to ModelSim 7 27 ModelSim Advanced Debugging FLI and C Models Copyright 2002 Mentor Graphics Corporation Notes ModelSim Advanced Debugging 7 43 December 2002 FLI and C Models Debugging Tracing Debugging Tracing FLI Tracing Creates a logfile to aid the debugging of FLI code e Captures FLI calling sequence in an ASCII file e FLI can be replayed at MTI without user s compiled code to debug problems e If design is crashing this feature can be used to find out which call is crashing the simulator Most probable cause is bad pointer provided by the user code Invoke the trace vsim trace foreign action tag lt name gt Action Result create log only writes a local file called mti trace tag create replay only writes local files called mti data tag c mti init tag c mti replay tag c and mti top tag c create both log and replay 7 28 ModelSim Advanced Debugging FLI and C Models Copyright 2002 Mentor Graphics Corporation Notes The purpose of the logfile is to aid you in debugging FLI code The primary purpose of the replay facility is to send the replay file to MTI support for debugging co simulation problems or debugging FLI problems for which it is i
246. ting Ns delta a b cin sum cout 0 0 X X U X U Events writes a text file containing transitions during simulation Q0 0 a X b X cin U sum X cout U TSSI writes a file in standard TSSI format 1 34 ModelSim Advanced Debugging December 2002 Review ModelSim Windows ModelSim Help ModelSim Help x ModelSim SE PLUS 5 6 with Debug Detective File Edit View Compile Simulate Tools Debug Window Help ai B A 2 10 E nd dg Be E 104 About ModelSim ILL cor Release Notes E top top only i r CE NU c cache f SE PDF Documentation gt i gees m memory SE HTML Documentation gt Start Here Guide Quick Guide 3 Tale lt a Tel Man Pages Command Referenc Project mixed Now 2 820 ns Delta 0 Technotes Tutorial Debug Detective Bookcase FLI Reference PDF Bookcase Help gt SE PDF Documentation gt Users Manual For Additional Help TechNotes Design Tips and More www model com 1 19 ModelSim Advanced Debugging ModelSim Windows Copyright 2002 Mentor Graphics Corporation Notes You can access all of ModelSim s help documentation through the help menu ModelSim Advanced Debugging 1 35 December 2002 Review ModelSim Windows Summary Summary Overview of ModelSim Windows ModelSim Help 1 20 ModelSim Advanced Debugging ModelSim Windows Notes 1 36 Copyright 2002 Mentor Graphics Corpo
247. ting signals and simulation time as described in lt expressionString gt Can handle bit selects and slices of Verilog registers The virtual function will show up in the wave and signals window as an expandable object if it references more than a single scalar signal The children correspond to the inputs of the virtual function This allows the virtual function to be expanded in the wave window to see the values of each of the input waveforms which could be useful when using virtual functions to compare two signal values ModelSim Advanced Debugging 5 11 December 2002 Virtual Signals Virtual Functions Cont Virtual Functions Cont virtual function not chip section1 clk clk_n Ichip section1 clk n becomes inverse virtual function install chip std logic vector chip vlog rega rega slv Converts and installs into chip virtual function chip addr 11 0 Oxfab addr eq fab Boolean Signal true when signal equals hex FAB virtual function gate chip siga XOR rtl chip siga siga diff High when chip siga of the gate level version of a design does not match chip siga of the rtl version of a design add wave siga diff this adds the above function to the waveform window 5 10 ModelSim Advanced Debugging Virtual Signals Copyright 2002 Mentor Graphics Corporation Notes Examples of virtual functions virtual function not chip sectionl clk clk n Creates a signal chip sectionl clk n which is
248. tled within a defined period e User specifies clock period strobe time e Monitors the entire design e Commands clock period elapsed time within each clock cycle check stable off check stable on file lt filename gt period lt time gt strobe lt time gt 8 8 ModelSim Advanced Debugging Debugging Copyright 2002 Mentor Graphics Corporation Notes 8 8 ModelSim Advanced Debugging December 2002 Debugging Verification Verification Run simulation in batch mode monitoring desired signals e Can be used from the command line no GUI c command line vsim c wlf batchrun1 wlf testbench lt my_batch1 do Invoke simulation with view option e Invokes the simulator to view a saved vsim wlf file e Does not consume a full simulator license e You can view multiple data sets wIf files e Permits easy fast viewing of signals vsim view batchrun1 wlf Note The view option is only supported if viewing the vsim wlf file in the SAME version of ModelSim as the one used to generate it 8 9 ModelSim Advanced Debugging Debugging Copyright 2002 Mentor Graphics Corporation Notes ModelSim Advanced Debugging December 2002 Debugging Unknown States See Module 1 Unknown States See Module 1 Back tracing an Unknown File Edit Cursor Zoom Compare Bookmark Format Window R Find si nal in uestion SHS Le RA ENRAIAR s g q fe He de si i i Move cursor to unknown s VER
249. to get its length 7 16 ModelSim Advanced Debugging FLI and C Models Copyright 2002 Mentor Graphics Corporation Notes A STRING data type is represented as an array of enumeration values The array is not NULL terminated as you would expect for a C string so you must call mti TickLength to get its length 7 30 ModelSim Advanced Debugging December 2002 FLI and C Models Using Checkpoint and Restore With FLI Using Checkpoint and Restore With FLI In order to use checkpoint restore with the FLI any data structures that have been allocated in foreign models and certain IDs passed back from mti function calls must be explicitly saved and restored Main Feature Set of Memory Allocation Functions e Automatically restored to same memory location Uses pointers e Must use a set of MTI memory allocation function calls mti Malloc and mti Free e Memory allocated by a function call will be restored to the same location in memory automatically 7 17 ModelSim Advanced Debugging FLI and C Models Copyright 2002 Mentor Graphics Corporation Notes Memory allocated by one of the functions will be automatically restored for you to the same location in memory ensuring that pointers into the memory will still be valid mti Realloc works like the C realloc function on memory allocated by mti Malloc If the specified size 1s larger than the size of memory already allocated to the origptr parameter then n
250. to run during the current simulation cycle Signals window Displays the names and values of VHDL signals generics and shared variables along with Verilog nets register variables named events and module parameters in the selected design region Source window Displays the HDL source code for the design Your source code may remain hidden if you wish ModelSim Advanced Debugging December 2002 Review ModelSim Windows e Structure window Displays the hierarchy of structural elements such as VHDL component instances packages blocks generate statements and Verilog model instances In ModelSim 5 5 and later this same information is displayed in the Main window workspace e Variables window Displays the values of VHDL constants generics and variables along with Verilog register variables in the current selected process Wave window Displays waveforms and current values for VHDL signals and variables along with Verilog nets and register variables you have selected Current and previous simulations can be compared side by side in the Wave window ModelSim Advanced Debugging 1 5 December 2002 Review ModelSim Windows Common Window Features Common Window Features GUI Features Feature Feature applies to these windows Quick access toolbars Dataflow Main Source and Wave windows Drag and Drop All Windows Command history Main window command line Automatic window updating Dataflow Process Sign
251. trademarks of Linotype AG TimingDesigner and QuickBench are registered trademarks of Forte Design Systems Tri State Tri State Logic tri state and tri state logic are registered trademarks of National Semiconductor Corporation UNIX Motif and OSF 1 are registered trademarks of The Open Group in the United States and other countries Versatec is a trademark of Xerox Engineering Systems Inc ViewDraw Powerview Motive and PADS Perform are registered trademarks of Innoveda Inc Crosstalk Toolkit XTK Crosstalk Field Solver XFX Pre Route Delay Quantifier PDQ and Mentor Graphics Board Station Translator MBX are trademarks of Innoveda Inc Visula is a registered trademark of Zuken Redac VxSim VxWorks and Wind River Systems are trademarks or registered trademarks of Wind River Systems Inc XVision is a registered trademark of Tarantella Inc X Window System is a trademark of MIT Massachusetts Institute of Technology Z80 is a registered trademark of Zilog Inc ZSP and ZSP400 are trademarks of LSI Logic Corporation Other brand or product names that appear in Mentor Graphics product publications are trademarks or registered trademarks of their respective holders Updated 2 13 02 Table of Contents TABLE OF CONTENTS Trademark Information 4 ena eese eieesro n ped ae rano n ua Y aha nonna k ana tua tui ve aoro o bre ua auk iii About This Training Workbook eee eese eere eene eene tn nen
252. transcript file as a macro DO file 1 8 ModelSim Advanced Debugging December 2002 Review ModelSim Windows Project Tab Project Tab The Project tab manages the files in your design J ModelSim SE PLUS 5 6 File Edit View Compile Simulate Tools Debug Window Help appa Reading C Modeltech_5 6 tcl vsim pref tcl Loading project perflab Loading project mixed esi Be er ou x Nae fee ree t i cachev Edit Compile of cache v was successful memory v STE successful n i d Simulate Compile All successful a Compile Qutof Date f successful top vhd Add to Project gt Compile Order successful util vhd Remove from Project Close Project Compile Report Compile Summary lt No Context gt Customize View E 4 Properties Project mixed 1 6 ModelSim Advanced Debugging Model Sim Windows Copyright 2002 Mentor Graphics Corporation Notes In the Project tab you can add files then Compile them Set specific options such as setting the compile option VHDL 93 on selected modules e Double click the file to perform an edit Use Windows Explorer to change the associated program type ModelSim Advanced Debugging December 2002 Review ModelSim Windows Files can be any type SDF Waveform Text documents Tcl Do txt etc Spreadsheets C C Verilog VHDL ModelS
253. tricity CEOC CheckMate CHEOS Chip Station ChipGraph CommLib Concurrent Board Process SM Concurrent Design Environment Connectivity Dataport Continuum Continuum Power Analyst CoreAlliance CoreBIST Core Builder Core Factory CTIntegrator DataCentric Model DataFusion Datapath Data Solvent dBUG Debug Detective DC Analyzer Design Architect Design Architect Elite DesignBook Design Capture Design Manager Design Station DesignView DesktopASIC Destination PCB DFTAdvisor DFTArchitect DFTInsight DirectConnect SM DSV Direct System Verification DSV Documentation Station DSS Decision Support System ECO Immunity SM EDT Eldo EldoNet ePartners EParts E3LCable EDGE Engineering Design Guide for Excellence SM Empowering Solutions Engineer s Desktop EngineerView ENRead ENWrite ESim Exemplar Exemplar Logic Expedition Expert2000 SM Explorer CAECO Layout Explorer CheckMate Explorer Datapath Explorer Lsim Explorer Lsim C Explorer Lsim S Explorer Ltime Explorer Schematic Explorer VHDLsim ExpressI O FabLink Falcon Falcon Framework FastScan FastStart FastTrack Consulting SM First Pass Design Success First Pass success SM FlexSim FlexTest FDL Flow Definition Language FlowTabs FlowXpert
254. tual 1000 dif 128 angle 90 x 000000001001 v 011010010000 cos 4 actual 1 dif 3 sin 8 40 actual 1000 dif 160 a A tl EIB viel2000 VSIM 10 gt quit sim Jh ieee R ModelSim gt button b1 text Run Script command do cor it do ei modelsim Ib s gb ModelSim pack b1 side left si lt No Context y 12 After you have pressed lt Enter gt a second time notice the appearance of the Run Script button in the lower left hand corner of the ModelSim window Click on the button You should see the cor it do script executing in the ModelSim transcript window Run Script Now 37 400 ns Delta 2 Creating a Button to Open and Close ModelSim Windows You have seen how easy it is to create a simple button widget that helps you speed up the simulation and debugging process For this next exercise we will explore writing a simple procedure to create a button that will open and close four ModelSim windows The script we will be using is the Tcl script file open close button tcl 1 For this step let s run the Tcl script open close button tcl In the ModelSim Main window select Tools gt Execute Macro Select open close button tcl 2 You will notice that as you try to run the script ModelSim generates an error message This is because the procedure add button which creates the Open Close button is missing 2 28 ModelSim Advanced Debugging December 2002 Tcl Tk Ov
255. ue the sdf file is using to annotate the timing See header section of the math sdo file vsim wlf sim wlf t 100ps sdfmax math tb t sdf math sdo math tb 5 Open the ModelSim wave window add all top level signals from the testbench math tb vhd 6 Turn on the performance profiler profile on and run the simulation for 5 13 us time run 5 13 us ModelSim Advanced Debugging 8 33 December 2002 Debugging How long was the ModelSim runtime for the gate level SDF simulation Move the decimal point 6 places to get the number of seconds If all went correctly you should be looking at a successful gate level VHDL post P amp R netlist simulation with its corresponding SDF timing file If you encountered errors continue to debug You most likely will have trouble with your vsim sdfmax command for ModelSim Refer back to the lecture notes for assistance Upon completion do not close ModelSim Continue on to Part 4 Part 4 Waveform Comparison of RTL Simulation to Gate Level SDF Simulation Optional Now we will perform a waveform comparison of the RTL simulation to the gate level SDF simulation Instead of using the GUI we want to use compare commands from the command line within the ModelSim Main window Refer back to the lecture notes for assistance l 2 8 34 Open the golden waveform results file gold wlf Start the comparison between gold wlf gold and the current open waveform simul
256. ulation Window Help AIP P A 9h A MA lol x 0 serial_interface 01011010 WEHSSCFWEEEEIE Opens a window on the parent diagram Z 9 8 ModelSim Advanced Debugging Debug Detective Overview Notes Block Diagrams Traverse Hierarchy Control simulation 9 9 9 Set Signal Breakpoints amp Probes Add Remove signals to from Wave List Log Setenvironment Object information Driver Drivers for uart top i4 zeros 7 0 00000000 Signal uart_top i4 zeras DD000000 Driver uart_top i4 line_165 SIM 23 gt Project UART Now 100 ns Delta 1 Copyright 2002 Mentor Graphics Corporation Block diagrams are one of the most useful aspects of the Debug Detective You can traverse the hierarchy of a design graphically to view lower levels as block diagrams state machine diagram or truth tables It is easy to traverse up and down the hierarchies of the structure of your design Using the block diagram allows you to control the simulation You can set signal breakpoints select signals and add probes to your block diagram along with adding signals to the Wave or List windows This let you control and monitor object information from a graphical representation You also have cross probing capabilities between the ModelSim windows and the graphical views ModelSim Advanced Debugging December 2002 Debug Detective Block Diagram To
257. ur simulation is set 1 e or A full hierarchical path must begin with a or The path must be contained within double quotes verbose Returns Nothing Limitations integer Optional Possible values are 1 or 0 Specifies whether a message is reported in the transcript stating that the source is driving the destination Default is 0 no message When depositing the value of a VHDL signal onto a Verilog register the VHDL signal must be of type bit bit vector std logic or std logic vector module Reg top sigl initial begin Sinit signal spy top uut instl sig1 top sigl 1 end endmodule 3 28 ModelSim Advanced Debugging December 2002 Test Benches VHDL util package The util package is included in ModelSim versions 5 5 and later It serves as a container for various VHDL utilities The package is part of the modelsim_lib library that is located in the modelsim install tree and mapped in the default modelsim ini file init signal spy The init signal spy utility deposits the value of a VHDL signal or Verilog register wire onto an existing VHDL signal This allows you to reference signals registers or wires at any level of the hierarchy from within a VHDL architecture e g a test bench Syntax init signal spy source destination verbose Arguments Description source Required A full hierarchical path or relative path with reference to the
258. uror to da 8 10 Erroneous Data Gau aec tates otecd bn bete thao T e bob B Ute din 8 11 Searching for Expressions ostia Oe IR ESAE EROS eO ETE EAE ER o EEG 8 12 Iteration Violations eode sententie rr tels creer demi nanos FOU ke ead radit taa ae 8 13 Mixed Eangou ge ISSUES ve cop Mau Gee o RO EM b 8 15 Issues With SDF Instance Specification c cc cceccsessecceccessscceeeesessseeseeeeeeees 8 17 SDE Instance Specification austro eee fereet fcc bes e bii cats ictu fessa fe dd 8 18 xii ModelSim Advanced Debugging December 2002 Table of Contents TABLE OF CONTENTS Cont Fixing Instance Specification Problems cccceeececeeeeneceeeeneeeeseneeeeneeeeeeenes 8 20 Generics Mismate hes aratan e aeee a pho e o PI Oro Ree Rene ae AC 8 21 MEETUPS E NT TTD T T IT 8 22 More Useful vcom amp vlog Commands sese 8 25 S MmMMary 15 eese eee a bececares ue ea Dc ah cud osse bos tesi dedos d 8 27 Lab 8 Debut cond UNE HII en aedi onde dard ope AID 8 28 Module 9 Debug Detective T 9 1 Module Verde Woo te sree tee tbt uda dM suut omis 9 2 DEST ATA Ae 9 3 Debug Detective Option for ModelSim 0 0 0 cee ecccsseeesseecceseneeceeseeeeeeeneeeentaaees 9 5 Debug Detective Introduction acoso attri e canister tet es toa aa gotas tipa tod 9 6 Debug Detective FUNGOS 24 5 neenon CON EGER REESE 9 7 Using Debug Detective oso creto re ber ebrei bees eg Neues e Pd s d 9 8 Block Dia Or anis NOR
259. vanced Debugging 8 43 December 2002 Debugging The sim_elab do file contains the following commands add log profile on time run 5 13 us profile off 5 Is this runtime less than what you observed in the previous simulation using the ModelSim GUI 6 Open the vsim wlf file with the view option of vsim Add all signals to the wave window and look at the results 7 Quit ModelSim when completed quit f Part 10 RTL Simulation and Changing VHDL Generics From the Command Line Optional Both the math vhd and the math_opt vhd designs were written with extensive use of VHDL generics Generics are very useful in VHDL designs to allow for quick design changes without the need to change parameter values throughout the design hierarchy and in multiple design files Now let s use ModelSim to assign the value of the generic N in counter_opt vhd during a RTL simulation 1 Compile the optimized counter count opt vhd in ModelSim 2 Simulate the counter opt and assign the generic N with a value of 16 Use the vsim g lt Name gt lt Value gt or G lt Name gt lt Value gt option The g lt Name gt lt Value gt option assigns a value to all specified VHDL generics that have not received explicit values in generic maps and instantiations There is no space between g and lt Name gt lt Value gt The G lt Name gt lt Value gt option will override generics that received explicit values in generic maps and insta
260. vlog top top ic V si junkb top Nc V vlog topb top Nc V si junk arrayb top Nc V vlog to Ye V YsO4A date out top date out Ve V Ys04A data out top data out top Ne V YsO4A7addr top addr 1 top Nc M cl1k top clk sl 1 Ye M elk top clk bit t signal spy top ic V Npaddr48l top paddr t signal spy top ic V Npaddr48i top paddr b 1 t signal spy top Vc X wen t ss Spy On Some Signals top wen not clk after 20 ns port map clk paddr pdata prw pstrb prady ache port map clk paddr pdata prw pstrb prdy saddr sdata sru sstrb sra ry port wap clk saddr sdata srw sstrb srd y f Dpo ml 3 19 ModelSim Advanced Debugging Test Benches Notes 3 20 Copyright 2002 Mentor Graphics Corporation ModelSim Advanced Debugging December 2002 Test Benches init_signal_spy Verilog Task 3 20 ModelSim Advanced Debugging Test Benches Notes init_signal_spy Verilog Task SL EA Pia File Edit Design View Project Run Compare Macro Options Window Help File Edt Object Options Window es BO fl wath OF Si BAA 09 1 vsim do do wave do run al view structure view source view signals test counter Ft haodule test counter z Loading work test counter Loading d 55b2b win32 std standard Loading d 55b2b win32 ieee std l
261. vpare tst pesa dill v con para tet peo id5 Gif con pere tst_pseuos Tail oY E pare isl_ pseudo Difference markers TOE RE UI La EN THE MONNA AAI MOM ANOA o Pathnames of all test signals are designated as yellow triangles Differences are marked by the red Xs 6 13 ModelSim Advanced Debugging Waveform Compare Copyright 2002 Mentor Graphics Corporation Notes ModelSim Advanced Debugging 6 13 December 2002 Waveform Compare Compare Objects in the List Window Compare Objects in the List Window Differences are highlighted with a yellow background ini x e Tab on selected column to Fie Edt View Tools Window move to next difference sex Umen per REY zal elts Use the RMB to select options 2700 40 1 1 L 00001000 00001000 222222 2705 0 il 0 0 00001000 00001000 000000C i 2720 0 o 0 D 00001000 00001000 000000t e Examine 2740 0 1 n 0 00001000 00001000 oononoc 2745 0 1 1 1 00001001 OOUD1000 zzzzzzz e Annotate Diff 2755 40 1 1 1 00901001 00001001 222222 z 2760 0 o 1 L 00001001 00001001 ZZZZ22z e Ignore Diff 2700 0 1 1 1 00001001 00001001 ZZZZZZz 2785 0 a n n 00001001 00001001 00OONAC 2800 0 o O D 00001001 00001001 000000t 2920 40 O D 00001001 00001001 ocooaoc AZ Annotate Diff Ignore Diff 6 14 ModelSim Advanced Debugging Waveform Compare Copyright 2002 Mentor Graphics Corporation Notes Shift Tab to move backwards 6 14
262. what object is and Examine value object has MM source cache y _ O xj e Tools gt Examine Fie Edt View Tools Debug Window e Tools gt Describe 504 2O0e FT WANN OO Di ts r sstrb r 0 111 posedge clk sstrb r E ais A cir 113 assign pE pdata top c sdata r 2 820 ns 114 posedge clk while srdy 0 B posedge clk CEEECOEECEEEGEER 115 deassign prdy r prdy r 1 id 116 deassign sdata r sdata r bz 117 sdata_r bz OK 118 end gl 4l top vhd cache v gt J Obiect not found assign un 113 Col 18 read only 4 1 10 ModelSim Advanced Debugging ModelSim Windows Copyright 2002 Mentor Graphics Corporation Notes Highlight signal port name then Drag and Drop to Wave or Dataflow window You can edit code from Source window e Remove read only option first Edit gt read only Source code can remain hidden for security use nodebug e Blue line numbers denote executable lines e Blue arrow denotes a process you have selected in the Process window 1 14 ModelSim Advanced Debugging December 2002 Review ModelSim Windows e Red diamonds denote file line breakpoints Hollow diamonds denote disabled file line breakpoints e File tabs represent open files e Template pane displays Language Templates ModelSim Advanced Debugging December 2002 Review ModelSim Windows Language Templates Language Templates
263. xt editor Tcl commands allow designers to control simulation interactively at the ModelSim prompt Tkallows designers to customize the UI Open source Bind Tcl with objects coded in C or other compiled languages Easy to port code to different host platforms No recompilation necessary after Ul changes Tcl Tk is interpreted Allows rapid prototyping and modifying of application e ModelSim has a built in Tcl interpreter 2 3 ModelSim Advanced Debugging Tcl Tk Overview Copyright 2002 Mentor Graphics Corporation Notes ModelSim Advanced Debugging 2 3 December 2002 Tcl Tk Overview Tcl Overview Tcl Overview Tcl stands for Tool Command Language e Application independent scripting language Using Tcl with ModelSim gives you these features e Command history like that in C shells e Full expression evaluation and support for all C language operators A full range of math and trig functions Support of lists and arrays Regular expression pattern matching Procedures The ability to define your own commands Command substitution nested commands Robust scripting language for macros 2 4 ModelSim Advanced Debugging Tcl Tk Overview Copyright 2002 Mentor Graphics Corporation Notes Some examples of using Tcl script are provided in the ModelSim documentation 2 4 ModelSim Advanced Debugging December 2002 Tcl Tk Overview Tk Overview Tk Overview Tk is the graphical user in
264. y has been a strength of Verilog VHDL does not have this capability To traverse hierarchy of a mixed HDL or VHDL design had required the FLI or PLI ModelSim v5 5 and newer introduces a VHDL ability to probe through VHDL hierarchy The new VHDL library modelsim lib is now mapped to in the modelsim ini file There is also a new Verilog system task that provides the same ability with Verilog This provides access to all levels of the design regardless of the language Verilog init signal spy The init signal spy system task deposits the value of a VHDL signal or Verilog register wire onto an existing Verilog register This system task allows you to reference VHDL signals at any level of hierarchy from within a Verilog module or reference Verilog registers wires at any level of hierarchy from within a Verilog module when there is an interceding VHDL block Syntax Sinit signal spy source destination verbose ModelSim Advanced Debugging 3 27 December 2002 Test Benches Arguments source Description Required A full hierarchical path or relative path with reference to the calling block to a VHDL signal or Verilog register wire Use the path separator to which your simulation is set i e or The path must be contained within double quotes destination string Required A full hierarchical path or relative path with reference to the calling block to a Verilog register Use the path separator to which yo
265. y of Parameterized Modules or optimized macros may be re quired at times in order to achieve your desired perfor mance and utilization increment vhd Instead of implementing this module with an 8 bit incrementer counter and a potential 8 bit multi plexer feeding an 8 bit adder rewrite this module to guarantee the use of just one incrementer counter and one adder If time does not permit for rewriting the above VHDL files reference the math opt vhd design for the next part of this lab exercise Part 6 Simulation of Optimized RTL Design and SDF Waveform Comparison Optional Next we will perform RTL simulation on the math opt vhd design create a golden database for this new design and then compare this golden database to a gate level SDF simulation The VHDL source files and test bench for this optimized design are located in the labs lab8 math src directory Take some time to review and understand the operation of the re written optimized VHDL code for these five lower level files 8 36 ModelSim Advanced Debugging December 2002 Debugging adder_opt vhd Implemented as two multiplexers and one adder count_opt vhd Implemented as one adder and one multiplexer alu_opt vhd Simplified to a wire mult_opt vhd Uses an LPM multiplier instead of the operator increment opt vhd Slight VHDL coding trick to simplify and eliminate potential mux generation Complete the following steps similar to Part 3 of this la
266. yonly differences on individual bits secondaryonly differences on aggregates bus 6 22 ModelSim Advanced Debugging December 2002 Waveform Compare when Statement when Statement ES File Edit Cursor Zoom Compare Bookmark Format Window Bei hk RK ge Jee BB BBE Golden Simulation Results gold tst_pseudo clock compare data only gold tst_pseudo reset goldi tst pseudo expected when reset equal 1 SI TR gold tst pseudo data 200 time units before gold tst_pseudo chip clock gold tst_pseudo chip reset data change gold tst_pseudo chip data goldi tst pseudo chip store merrer Seer g E m oi Test Sinulation fRegults testi tst pseudo cloeh testi tst pseudo reset testi tst pseudo expected testi tst pseudo storage testi tst pseudo data testi tst pseudo chip clock testi tst pseudo chip data testi tst pseudo chipsetUfe po000 Y Y Y 1L X X3 Tompare data if reset inactive E reset inactive 20nsbefore reset equal 1 EF reset inactive gold tst_pseudo chip data testi tst pseudo chip data compare data only A when reset equal 1 178700 p 0 ps to 1116700 ps 6 23 ModelSim Advanced Debugging Waveform Compare Copyright 2002 Mentor Graphics Corporation Notes Refer to the ModelSim Command Reference manual for further details on the when command ModelSim Advanced Debugging 6 23 December 2002 Waveform Compare Compressed Waveform Files Compressed Wavefor
267. ze i 0 5 data data r Stop Simulation 17 wire 5 rw rw r strb st zl b control vhd Empty proc v jsf Jol s gt I Ti Ln Co 0 2 1 11 ModelSim Advanced Debugging ModelSim Windows Copyright 2002 Mentor Graphics Corporation Notes Create code for new designs language constructs logic blocks etc Usage Open an existing HDL file in the Source window or select File gt New to create one from scratch Once the file is open select View gt Show Language Templates A pane with the available templates appears in the Source window Double click on an item in the list to begin creating code Some items bring up wizards while others insert code directly into your HDL file 1 16 ModelSim Advanced Debugging December 2002 Review ModelSim Windows Code that is inserted into your existing code may contain yellow or gray highlighted fields o Yellow highlighting indicates a field that needs a name Double clicking the yellow object enables you to enter the name Note that all yellow objects with the same label e g block_label will change to whatever name you enter This ensures matching fields remain in synch o Gray highlighting indicates that a context menu with additional commands is available ModelSim Advanced Debugging 1 17 December 2002 Review ModelSim Windows Signals Window Signals Window Imi ModelSim SE PLUS 5 6 with Debug Detective File Edit View Compi

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