HPC46400E Slow Clock Mode and HDLC
Contents
1. HPC46400E Slow Clock Mode and HDLC Based Wakeup This application note is intended to provide a guide to use of the new Slow Clock power save feature of the HPC46400E In particular this note discusses the motivation constraints and some recommendations for using it with an HDLC sig nalled wakeup The Slow Clock feature allows the HPC46400E to enter a low power mode while maintaining its ability to perform DMA transfers from one of the HDLC receivers at a bit rate of up to 1 megabit second The motivation for this feature is to be able to wake up the processor to full speed opera tion on receipt of a valid HDLC message The previously implemented Power Save modes Halt and Idle do not meet this need since in order to guarantee the lowest possible power consumption they hold certain on chip peripherals including the HDLC and DMA sections in their Reset states The HDLC channels are therefore unable to trigger an exit from these modes on receipt of a frame indeed they are not running at all and require software set up on exit from these modes before they can continue oper ation The Slow Clock feature described here is available only as of Revision B of the device Devices of Revision B or later can be identified by the value FB hex or lower appearing in the REVREG register The convention of decrementing the REVREG value with successive revision steps is due to the fact that the first devices in this family di2. TL DD 11413 3 34 35 36 37 0000 38 39 0000 40 4 0001 42 0001 43 0005 44 000A 45 000E 46 000F 47 0013 48 49 0015 50 0015 51 0019 52 001A 53 54 001c 55 56 57 58 59 60 61 62 001C 63 0021 64 0026 65 002B 66 67 0030 68 0035 69 70 71 72 003A 73 003F 74 75 76 77 78 79 80 0040 81 82 83 84 85 86 0040 ee Errors 60 B601A810 81080140D9 B601A810 46 B601101F 942B B6011017 42 9424 A1000142AB A1020144AB A1040146AB A1060148AB 830001A8D9 83000104D9 83300140DB 3E form Proposed code in critical path If CRC error kill receiver by turning off SSR bit iff Slow Check again and branch to decide whether to re initialize If not then we have a good frame go to full speed and continue Even if CRC is bad we want to process normally if not SLOW Cycles 5 15 16 20 16 5 15 7 16 5 7 SLOW_BAD DMA is already off re initialize pointer and error registers These assume a worst case application Split Frame mode i with a non zero header length In any other mode only Note AND is faster than LD here i Reset and restart receiver ard return from interrupt 2 In Slow Mode 400 ns per CK2 error or not SLOW mode sect CODE ROM16 JP n A lt interrupt gt INTSERV IFBIT CRCR HD1EST f R AND DMRiRCL PWRPAT IFBIT CRCR HD1LEST JP BAD_CRC RBIT SLOW FEXT JMP NORM_FLOW i BAD_CRC IFBIT SLOW FEXT
3. that the channel be tempo rarily disabled to avoid these registers being altered by both software and DMA concurrently with chaotic results Dis abling the channel creates a short dead time during which a following message will be lost We will here examine the code required to accomplish this and the times implied The following assumptions are made for purposes of analy sis e 20 MHz crystal clock e Data rate of 1 Mbps e The Channel 1 HDLC receiver will be used for the wake up monitoring This choice is purely arbitrary e One Wait state on CPU accesses two Wait states on DMA accesses to allow Ready requests from off chip devices e The HPC is placed in a jump to self loop while it is in the low power state Other instructions besides a jump to self are not intended to be forbidden this assumption is made only for the sake of time analysis as a simple rea sonable case e The same interrupt service code will be entered regard ess of whether the HPC was in Slow Clock mode when he HDLC frame was received This is usually implied if he code is in read only memory When an End of Message interrupt comes in the following time constraints apply e A second garbage frame may trigger another EOM in errupt in as little as 15 ws DMA might happen within 5 ws Any processing must take this into account al hough any frame received this early cannot be valid A valid frame could not be rec
4. the Ready feature Wait states requested by off chip logic or the HOLD feature off chip DMA are activated for long periods but there is no unusual consideration required for these cases Note that the extra ALE pulses that appear while performing 16 bit accesses on an eight bit external bus are not points at which DMA can occur These are best comprehended as Wait states instead If you are going to be using the HPC in eight bit mode read the section of the User s Manual titled Bus State Sequences carefully this is Section 10 2 1 of the May 1990 edition SPECIFIC RECOMMENDATIONS FOR HDLC BASED WAKEUP In a relatively clean HDLC environment it is a straightfor ward process to simply clear the SLOW bit on receipt of an HDLC End of Message EOM interrupt Having processed the HDLC frame the service routine can then examine its environment and decide whether to re enter Slow Clock mode before returning If however the HDLC input is noisy and or power con sumption must absolutely be minimized it may instead be desirable for the EOM interrupt service routine to check that the message has been received with a good CRC before exiting from Slow Clock mode The remainder of this discus sion will center around this case If an HDLC message is received with a bad CRC certain DMA pointers will have been changed by hardware and they must be restored to their earlier values before the rou tine returns This also requires
5. 413 RRD B5M75 Printed in U S A dn ye M Peseg D1GH PUL spo X901 MOIS 300t9t dH VL8 NV Power consumption in Slow Clock mode with a 20 MHz crystal drops to slightly under 1 of its full speed value This is based on bench measurements as of this writing data sheet limits have not yet been determined Further division beyond a factor of four was considered but rejected on the grounds that 1 The resulting bit rate allowed on the HDLC channels is impacted and no longer meets the need for a 1 Mbit second bit rate and 2 At a division factor of 4 nearly all of the power dissipa tion is coming from the crystal oscillator itself additional division would gain little While in Slow Clock mode two important limits change with respect to the HDLC channels 1 The sampling circuitry which monitors the asynchronous HDLC bit clock inputs the HCK pins is running at 1 4 of its full speed rate Therefore for reliable sampling the maximum HDLC clock frequency drops from approxi mately 1 4 of the crystal frequency to 4 of the frequen cy For example at full speed with a 20 MHz crystal at tached the absolute maximum HCK frequency is 5 MHz specified in the data sheet slightly slower for test integri ty With the SLOW bit set however this becomes 1 25 MHz again minus a small amount still to be deter mined at this writing 2 The bus bandwidth has also been reduced by a factor of four Any DMA cycles wi
6. JP SLOW_BAD JMP NORM_FLOW 7 resetting SSR automatic hardware action R LD DMR1CA1 BUFADDR1 w R LD DMR1DA1 BUFADDR2 w R LD DMR1CA2 BUFADDR3 w R LD DMR1DA2 BUFADDR4 w AND HD1EST 0 AND MSGPND 0 XOR DMR1RCL 0x30 i RETI i Normal flow if not CRC NORM_FLOW 0 Warnings RETT end 0 i Somewhere in here PWRPAT must be updated to reflect that we are at full speed two pointers need to be reloaded CA1 amp DA1 or CAl amp CA2 since an Interrupt Overrun would kill the channel by 21 21 21 18 18 44 CK2 97 6 us TL DD 11413 4 HPC46400E Slow Clock Mode and HDLC Based Wakeup is actually skipped but the process of skipping happens to take the same amount of time as a JP instruction e On normal messages in Slow Clock mode the total delay to normal operation can be measured as all instructions executed to the point that the code at label NORM_ FLOW begins execution Counting also the jump to self and the hardware interrupt service time this amounts to 91 slow clocks totalling 36 4 ws plus 8 fast clocks 0 8 us 37 2 us total Note that the change of clock frequencies takes effect at the beginning of the last clock cycle of the RBIT SLOW instruction hence the eight fast clocks instead of just the seven in the JMP NORM__FLOW instruction CONCLUSIONS On the second page of the listing the tabulation to the right of the code is keeping track
7. d not have the Entry into SLOW mode CK2 WR Bus XXX XXXXXXXXXX Exit from SLOW mode CK2 WR Bus XYOUQUYOOY XX National Semiconductor Application Note 814 Brian Marley February 1993 register at all and the value read from a non existent regis ter is FF hex in the HPC family THE SLOW CLOCK FEATURE The Slow Clock feature is controlled only by software ex cept that a hardware Reset to the HPC will clear it A pro gram will enter Slow Clock mode by writing a 1 to the SLOW bit which is bit 7 of the FEXT register shown below To come back to full speed operation software only has to reset the SLOW bit FEXT Byte at 0110 Hex 7 6 5 4 3 2 1 0 SLOW n a n a n a n a n a SIFFT2 SIFFT1 While the SLOW bit is a 1 the CKI input from the crystal oscillator is divided by four before being used by any on chip ogic except the CKO pin of course which is driving the oscillator Note that the CK2 clock output is affected by the change its frequency is divided by four matching the rate of on chip events The diagram below shows the timing involved in the entry and exit of Slow Clock mode The rising edge of the WR Strobe is the trigger for the switch in frequencies Note that all Write transfers both on chip and off chip are visible on the bus pins TL DD 11413 1 TL DD 11413 2 1995 National Semiconductor Corporation TL DD11
8. eived in less than 38 us e f there is a CRC error the entire interrupt routine will be running in Slow mode It needs to restore the receiver s DMA pointer registers clear out errors and acknowl edge the interrupt before returning It must accomplish this in as little time as possible Tying this into the con sideration above we want to simplify the handling by guaranteeing that there are no additional EOM inter rupts pending e Pushing initializing and restoring processor registers is a detriment to performance in this case The time penalties involved in performing memory to memory instructions are less than the overhead of initializing the pointer regis ters for more efficient forms Any saving of the machine state is postponed until after the processor has exited from Slow mode We handle this by quickly checking the CRC Error status bit and turning off the receiver if it is seen and if the processor is in Slow mode This is accomplished by ANDing the re ceiver s control register with a mask placed in Basepage RAM before the processor went into Slow mode Variables involved are PWRPAT a one byte Basepage variable that contains OxEF if the HPC is in Slow Mode and OxFF otherwise It is ANDed with the low byte of the DM1RC register thus clearing the SSR bit if the processor is in Slow mode BUFADDR1 four 16 bit locations in Basepage memory BUFADDR2 holding the initial values of the four DMA BUFADDR3 point
9. er registers DMR1CA1 DMRI1DA1 BUFADDR4 DMR1CA2 and DMR1DA2 From these val ues the DMA registers are restored if a bad HDLC message is received while the HPC is in Slow mode FEXT The new register at address 0x0110 contain ing the SLOW bit in bit position 7 Other symbols are register and bit names as used in the User s Manual NSC ASMHPC Version 2 2 Nov 5 15 25 1991 EOM Wakeup Code for Interrupt Service 1 2 3 4 5 0Q1A8 6 0140 7 0110 8 0104 9 10 0142 11 0144 12 0146 13 0148 14 15 16 17 0007 18 0000 19 20 21 22 0000 23 24 0000 25 0002 26 0004 27 0006 28 29 0008 30 31 0000 32 title Registers HD1EST DMR1RCL FEXT MSGPND ow DMR1CA1 DMR1DAL DMR1CA2 DMR1IDA2 Bits SLOW CRCR Variables sect DATA Base EOMWAKE 20 Feb 92 18 0 PAGE 1 EOMWAKE EOM Wakeup Code for Interrupt Service 0x01A8 b 0x0140 b 0x0110 b 0x0104 b 0x0142 w 0x0144 w Ox0146 w 0x0148 w ow BUFADDR1 dsw 1 BUFADDR2 dsw 1 BUFADDR3 dsw 1 BUFADDR4 dsw 1 PWRPAT dsb 1 endsect The HDLC Error register for Channel 1 The Receiver Control register for Channel 1 The new Feature Extension register The Messages Pending register The DMA address registers for Receiver 1 Slow Mode in FEXT CRC Error flag in HD1EST Four words holding values to restore into the DMA pointer registers Power Mode indicator pattern OxEF Slow OxFF Normal
10. ll be impacted by an additional latency due to the fact that any processor bus cycle al ready in progress will be slower to complete and the DMA transfers themselves will be slower to complete BUS BANDWIDTH IN SLOW MODE DMA transfers must be considered since they will be occur ring during the first HDLC message received in Slow Mode before the interrupt is set pending from the Receiver and therefore before software has had the opportunity to exit from Slow Mode The bus bandwidth issue varies somewhat depending on the exact situation A DMA cycle occupies either four or five bus states each bus state corresponding to one cycle of Ck2 as listed below e one Idle bus state TI inserted by the DMA section whenever it takes control of the bus from the CPU core one Address state TA during which the DMA address is presented one or two Wait states TW depending on whether the Ready feature is enabled this feature allows off chip log ic to request additional Wait states during DMA cycles as well as CPU cycles e One Data transfer state TD during which data is actual ly transferred Ata 1 Mbps HDLC bit rate bytes become ready for DMA at a rate of one per every 8 us corresponding to one DMA cycle per every 20 bus states at 20 MHz in Slow Clock mode Therefore DMA activity occupies at most only 1 4 of the bus bandwidth in the absence of off chip Ready or HOLD requests DMA LATENCY As explained above bus occupanc
11. of the number of CK2 clocks during which the HDLC Receiver is effectively off while a message with a bad CRC is being processed in Slow Clock mode A clock count is shown in parentheses when that particular instruction is not executed in this flow As we can see the delay is slightly under 100 us The following measurements of overhead can also be made in the receipt of normal messages e On normal messages while not in Slow Clock mode the first six instructions after the label INTSERV constitute the additional overhead This amounts to 79 cycles of CK2 or 7 9 ws The JP instruction in this flow LIFE SUPPORT POLICY NATIONAL S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or 2 A critical component is any component of a life systems which a are intended for surgical implant into the body or b support or sustain life and whose failure to perform when properly used in accordance support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or AN 814 with instructions for use provided in the labeling can effectiveness be reasonably expected to result in a significant injury to the user National Semicond
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13. y is not a serious item however the latency in granting the bus to the DMA section can be In the HPC bus DMA is only granted at a point where an address would have been issued a TA state The fact that the bus is idle does not in itself equate to an oppor tunity for DMA There is only a problem if the HPC is allowed to execute Multiply or Divide instructions while in Slow Clock mode These instructions occupy the bus exclusively for long peri ods of time up to 67 bus states between DMA opportuni ties assuming one Wait state data memory speed while performing their calculation within a Read Modify Write op eration Even with the on chip 3 level FIFO in the DMA sec tion then use of these instructions will guarantee DMA overruns in SLOW mode assuming a 20 MHz crystal and 1 Mbps data rate The next most significant instructions are the Bit instructions with the addressing mode X B b which present a gap in DMA opportunities of seven bus states regardless of Wait states Also some instructions perform a Read Read Modi fy Write operation occupying the bus for up to 9 bus states assuming 1 Wait state data memory These times are small compared to the amount of time 24 ws 60 bus states accounted for by the FIFO buffering in the DMA sec tion hence they should be insignificant No other instructions occupy the bus in this manner for longer than two bus states between memory accesses Oth er impacts could be felt if
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