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SN8P1919

1. 0 0 0 15 625K 27 968K 31 25K 62 5K 0 0 1 7 8125K 13 98K 15 625K 31 25K 0 1 0 3 90625K 6 99K 7 8125K 15 625K 0 1 1 1 953125K 3 49K 3 90625K 7 8125K 1 0 0 976Hz 1 748K 1 953125K 3 90625K 1 0 1 488Hz 874Hz 976Hz 1 953125K 1 1 0 244Hz 437Hz 488Hz 976Hz 1 1 1 122Hz 218Hz 244 Hz 488Hz Note In general application set PGIA Chopper working clock is 2K Hz but set clock to 250Hz when High clock is 32768 crystal or in Internal Low clock mode SONiX TECHNOLOGY CO LTD Page 118 Preliminary Version 0 4 Ss NX SN8P1919 D D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 10 4 3 AMPCHS PGIA CHANNEL SELECTION 091H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 AMPCHS CHS3 CHS2 CHS1 CHSO R W R W R W R W R W After Reset 0 0 0 0 CHS 3 0 PGIA Channel Selection CHS 3 0 Selected Channel V X X Output Input Signal Type 0000 Al1 Al1 V Al1 Al1 x PGIA Gain Differential 0001 Al2 Al2 V Al2 Al2 x PGIA Gain Differential 0010 Al1 ACM V Al1 ACM x PGIA Gain Single ended 0011 Al1 ACM V Al1 ACM x PGIA Gain Single ended 0100 Al2 ACM V Al2 ACM x PGIA Gain Single ended 0101 Al2 ACM V Al2 ACM x PGIA Gain Single ended 0110 ACM ACM V ACM ACM x PGIA Gain Input Short 0111 Reserved N A N A 1000 Vis 04V lt 4 NA Others
2. Bit 4 0 P10W P14W Port 1 wakeup function control bits 0 Disable P1n wakeup function 1 Enable P1n wakeup function SONiX TECHNOLOGY CO LTD Page 61 Preliminary Version 0 4 Ss NX SN8P1919 N D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC INTERRUPT 6 1 OVERVIEW This MCU provides three interrupt sources including three internal interrupts TO TCO TC1 and two external interrupt INTO INT1 The external interrupt can wakeup the chip while the system is switched from power down mode to high speed normal mode Once interrupt service is executed the GIE bit in STKP register will clear to O for stopping other interrupt request On the contrast when interrupt service exits the GIE bit will set to 1 to accept the next interrupts request All of the interrupt request signals are stored in INTRQ register INTEN Interrupt Enable Register INTO Trigger gt Em R l POtIRQ gt Interrupt Vector Address 0008H INT1 Trigger gt gt INTRQ Int t TORA nterrup gt Global Interrupt Request Signal TO Time Out _ gt 5 Bit Enable TCO Time Out ___ oe R Latchs TC1IRQ Gating TCO Time Out gt gt Note The GIE bit must enable during all interrupt operation 6 2 INTEN INTERRUPT ENABLE REGISTER INTEN is the interrupt request control register
3. Note1 The Charge pump delay 200ms and 100ms can avoid VDD drop when CR2032 battery application If VDD source came from AA or AAA dry battery the delay time can be shorten to 50ms Note2 Please refer the SN8P1919 EV_Board manual for the detail XBOMOV XBOBSET command SONiX TECHNOLOGY CO LTD Page 116 Preliminary Version 0 4 SNSPI919 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC SONIX 10 4 PGIA Programmable Gain Instrumentation Amplifier SN8P1919 includes a low noise chopper stabilized programmable gain instrumentation amplifier PGIA with selection gains of 1x 12 5x 50x 100x and 200x by register AMPM The PGIA also provides two types channel selection mode 1 Two fully differential input 2 One fully differential input and Two single ended inputs 3 Four single ended inputs it was defined by register AMPCHS 10 4 1 AMPM Amplifier Mode Register Bit7 Bit6 Bits Bit4 Bits Bit2 090H__ Biti Bito AMPM CHPENB BGRENB FDS1 FDSO GS2 GSI GSO AMPENB 0 0 0 1 1 1 0 After Reset 0 Bito AMPENB PGIA function enable control bit 0 Disable PGIA function 1 Enable PGIA function Bit 3 1 GS 2 0 PGIA Gain Selection control bit GS 2 0 PGIA Gain 000 12 5 001 50 010 100 011 200 100 101 110 Reserved 111 1 Note When selected gain is 1x PGIA can be disabled AMPENB 0 for power saving Bit 5 4 FDS 1 0
4. Note Please set ADC relative registers first than enable ADC function bit darla aiii AA Example ADC Reference Voltage Changes ADC Init ADC_Enable ADC_Wait ADC_Read ADC_RVS1 ADC_RVS82 MOV XBMOV MOV XBOMOV MOV XBOMOV XBOBSET XBOBTS1 JMP XBOBCLR XBOMOV BOMOV XBOMOV BOMOV MOV XBOMOV XBOBTS1 JMP XBOBCLR XBOMOV BOMOV XBOMOV BOMOV MOV XBMOV XBOBTS1 JMP XBOBCLR XBOMOV BOMOV XBOMOV BOMOV A 00000000B ADCM A A 0236 ADCKS A A 00h DFM A FADCENB FDRDY ADC_Wait FDRDY A ADCDH Data_H_Buf A A ADCDL Data_L_Buf A A 00001101B ADCM A FDRDY B FDRDY A ADCDH Data_H_Buf A A ADCDL Data_L_Buf A A 00001111B ADCM A FDRDY B FDRDY A ADCDH Data_H_Buf A A ADCDL Data_L_Buf A SONiX TECHNOLOGY CO LTD Selection ADC Reference voltage V R R Set ADCKS 236 for ADC working clock 100K 4M X tal Set ADC as continuous mode and WRSO 0 25 Hz Enable ADC function Check ADC output new data or not Wait for Bit DRDY 1 Output ADC conversion word Move ADC conversion High byte to Data Buffer Move ADC conversion Low byte to Data Buffer Don t disable ADC when change Reference Votlage Selection ADC Reference voltage internal V 1 2V 0 4V Check ADC output new data or not Wait for Bit DRDY 1 Output ADC conversion word Move ADC conversio
5. Note It is easy to understand the rules of SONIX program from demo programs given above These points are as following 1 The address 0000H is a JMP instruction to make the program starts from the beginning 2 The address 0008H is interrupt vector 3 User s program is a loop routine for main purpose application SONiX TECHNOLOGY CO LTD Page 16 Preliminary Version 0 4 Ss NX SN8P1919 D D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 2 1 2 2 LOOK UP TABLE DESCRIPTION In the ROM s data lookup function X register is pointed to high byte address bit 16 bit 23 Y register is pointed to middle byte address bit 8 bit 15 and Z register is pointed to low byte address bit O bit 7 of ROM After MOVC instruction executed the low byte data will be stored in ACC and high byte data stored in R register gt Example To look up the ROM data located TABLE1 BOMOV X TABLE1 H To set lookup table1 s high address BOMOV Y TABLE1 M _ To set lookup table1 s middle address BOMOV Z TABLE1 L To set lookup table1 s low address MOVC To lookup data R OOH ACC 35H Increment the index address for next address INCMS Z Z 1 JMP F Z is not overflow INCMS Y Z is overflow Y Y 1 JMP F Y is not overflow INCMS X Y is overflow X X 1 NOP MOVC To lookup data R 51H ACC 05H TABLE DW 0035H To define a word 16 bits data DW 5105H
6. cc s scccsececscsssenseceeecceeesesesssaeeeceeeceesessasaeeeeeeeesenes 113 5 3 1 CPM Charge Pump Mode Rey tE a a 113 3 3 2 CPCKS Charge Pump Cl ARES AR 115 5 4 PGIA PROGRAMMABLE GAIN INSTRUMENTATION AMPLIFIER ccccoocccconcnononcnnnnnccnnnnccnonncconnnccnnnncnnn 117 5 4 1 AMPM Amplifier OLER cceisig st carers aa cans tedeedantye Gasdun deren sndasacsenaaecauyecamaaeeetacde 117 5 4 2 AMPCKS PGIA CLOCK SELECTION ti 118 5 4 3 AMPCHS PGIA CHANNEL SELECTION ssisconissdtsnntssaisencanatsagunaddnnuissyteavisaacaannsageandaeiveeieiens 119 5 4 4 Temperature Sensor AA eR RER NE ENEE EAE 120 5 5 16 BITADC rongini a 123 5 5 1 ADCM ADC Mode Reta A a A A dd 123 D2 ADCGKS ADC Ci ii 126 5 5 3 ADCDL ADC Low Byte Data Registert sxc ivecssinsideasnsiscsaatinadavaesitadaaboachinaatagi dames tuacaateacsabunnions 127 JIA ADCDH ADC High Byte Data a 127 5 3 5 DFM ADC Digital Filter Mode Register susu a taa a 128 5 5 6 LBTM Low Battery Detect Register RRIAAA AAAAAA 131 DS Analog Setting and APP AA Ai c 132 6 APPLICATION CIRCUIT a 134 6 1 SCALE LOAD CELL APPLICATION CIRCUIT a Aia 134 6 2 THERMOMETER APPLICATION CIRCUS 135 7 DEVELOPMENT TOOLS cin 137 7 1 DEVELOPMENT TOOL VERSION A A 137 7 1 1 ICE In circuit CMUIAHON unicidad RT 137 7 1 2 OIP WUE aseos 137 7 1 3 IDE Integrated Development Environment ooonoooccnnnonocnncnnnonnnnnnnononnnnnannnonnnnnnn nn nncnnn nn nnnnnnns 137 7 2 OTP PROGRAMMING PIN TO TRANSITION BOARD MAPPING sscssccese
7. Ss WN MX SN8P1919 Y wy D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 2 1 4 DATA MEMORY RAM 256 X 8 bit RAM RAM location 000h General purpose area DOOh 07Fh of Bank O To store general purpose data 128 bytes BANK 0 one a 080h System register O80h OFFh of Bank 0 To store system registers 128 bytes OFFh End of bank 0 area 100h General purpose area 100h 17Fh of Bank 1 To store general BANK 1 f purpose data 128 bytes 17Fh f FOOh LCD RAM area Bank 15 To store LCD display data BANK 15 f 32 bytes F1Fh End of LCD Ram SONiX TECHNOLOGY CO LTD Page 23 Preliminary Version 0 4 Ss NX SN8P1919 D D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 2 1 5 SYSTEM REGISTER 2 1 5 1 SYSTEM REGISTER TABLE Qo ee aene a 9 A B Cc D E F fe 4 R z v x Tras RaANK oPrion ucom _ Amem aupcrs ameors abem ADCKS cem cecks orm aocor aoco iem _ E A e A en ee eae Ea IONES INESIS OSEA INES EOS RECO HE E E PEC RC Peer Pepe Pam ra es wrra venoso TcoR POL Pen Deo m e es ps tom toc com rooc rom rere TCHR STP Pour Pur pour Pur Ps em fez _ 2 1 5 2 SYSTEM REGISTER DESCRIPTION L H Working amp HL addressing register R Working register and ROM look up data buffer Y Z Working YZ
8. The external reset circuit also use external reset IC to enhance MCU reset performance This is a high cost and good effect solution By different application and system requirement to select suitable reset IC The reset circuit can improve all power variation SONiX TECHNOLOGY CO LTD Page 48 Preliminary Version 0 4 ON O Q xX SN8P1919 Y WS D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 4 SYSTEM CLOCK 4 1 OVERVIEW The micro controller is a dual clock system There are high speed clock and low speed clock The high speed clock is generated from the external oscillator circuit or on chip 16MHz high speed RC oscillator circuit IHRC 16MHz The low speed clock is generated from LXIN LXOUT by 32768 crystal or RC oscillator circuit Both the high speed clock and the low speed clock can be system clock Fosc The system clock in slow mode is divided by 4 to be the instruction cycle Fcpu Normal Mode High Clock Fcpu Fhosc 4 Fhosc 4M 8M crystal Fcpu Fhosc 16 Fhosc IHRC Slow Mode Low Clock Fcpu Flosc 4 4 2 CLOCK BLOCK DIAGRAM STPHX HOSC OE it Fhosc lo Fcpu Fhosc 4 Fhosc 4M crystal Fosc l XOUT Fcpu Fhosc 16 Fhosc IHRC Le fee gt gt Fosc CPUM 1 0 Flosc o Fcpu Flosc 4 HOSC High_CIk code option Fhosc External high speed clock Internal high speed RC clock Flosc External low speed clock Fosc System clock source
9. gt ADCConversionData X 31250 External and Internal Reference Circuit Table External Ref Circuit RVS1 0 AVE Ref R Ref R AVSS Internal Reference Circuit IRVS 1 AVE 3 0V IRVS 1 AVE 2 4V IRVS 1 AVE 1 5V IRVS 0 AVE 3 0V IRVS 0 AVE 2 4V AVE 3 0V AVE 2 4V AVE 1 5V AVE 3 0V AVE 2 4V REF REF 0 96V REF 0 6V REF 0 8V 0 2V 0 4V 1 2V E 0 4V REF REF 0 32V REF REF SONiX TECHNOLOGY CO LTD Page 124 Preliminary Version 0 4 Ss NX SN8P1919 D D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC ADCM xxx0x00xB V REF REF V R R ADC Reference Voltage from External R R ADCM xxx0110xB V REF REF V 1 2V 0 4V 0 8V AVE 3 0V ADC Reference Voltage from Internal 1 2V and 0 4V ADCM xxx0010xB V REF REF V 0 8V 0 4V 0 4V AVE 3 0V ADC Reference Voltage from Internal 0 8V and 0 4V ADCM xxx0111xB V REF REF V 1 2V 0 4V 0 8V AVE 3 0V ADC Reference Voltage from Internal 1 2V and 0 4V and ADC output is Voltage measurement result SONiX TECHNOLOGY CO LTD Page 125 Preliminary Version 0 4 SONIX 10 5 2 ADCKS ADC Clock Register SNSPI919 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 094H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ADCKS ADCKS7 ADCKS6 ADCKS5 ADCKS4 ADCKS3 ADCKS2 ADCKS1 ADCKSO R W Ww Ww Ww Ww Ww Ww Ww W After R
10. 1 JMP COSTEP Else jump to COSTEP COSTEP NOP BOMOV A BUFO Move BUFO value to ACC BOBTSO FZ To skip if Zero flag 0 JMP C1STEP Else jump to C1STEP C1STEP NOP If the ACC is equal to the immediate data or memory the PC will add 2 steps to skip next instruction CMPRS A 12H To skip if ACC 12H JMP COSTEP Else jump to COSTEP COSTEP NOP SONiX TECHNOLOGY CO LTD Page 29 Preliminary Version 0 4 Ss WN NX SN8P1919 Y WS D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC If the destination increased by 1 which results overflow of OxFF to 0x00 the PC will add 2 steps to skip next instruction INCS instruction INCS BUFO JMP COSTEP Jump to COSTEP if ACC is not zero COSTEP NOP INCMS instruction INCMS BUFO JMP COSTEP Jump to COSTEP if BUFO is not zero COSTEP NOP If the destination decreased by 1 which results underflow of 0x00 to OxFF the PC will add 2 steps to skip next instruction DECS instruction DECS BUFO JMP COSTEP Jump to COSTEP if ACC is not zero COSTEP NOP DECMS instruction DECMS BUFO JMP COSTEP Jump to COSTEP if BUFO is not zero COSTEP NOP SONiX TECHNOLOGY CO LTD Page 30 Preliminary Version 0 4 SONIX 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC SNSPI919 MULTI ADDRESS JUMPING Users can jump around the multi address by either JMP instruction or ADD M A instruction M PCL to activate
11. 1 fcpu 2 293 ms Fosc 3 58MHz Ao 1 fcpu Pe T E 500 ms Fosc 32768Hz 1 fcpu 2 25 16 65 5s Fosc 16KHz 3V 1 fcpu 2 16 1s Fosc 16KHZ 3V 16K ae 16 0 5s 3V gt Example Stop high speed oscillator BOBSET FSTPHX To stop external high speed oscillator only gt Example When entering the power down mode sleep mode both high speed oscillator and internal low speed oscillator will be stopped BOBSET FCPUMO To stop external high speed oscillator and internal low speed oscillator called power down mode sleep mode SONiX TECHNOLOGY CO LTD Page 50 Preliminary Version 0 4 S WN 9 NX SN8P1919 N D A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC SONiX TECHNOLOGY CO LTD Page 51 Preliminary Version 0 4 SO WN xX SN8P1919 D D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 4 4 SYSTEM HIGH CLOCK The system high clock is from internal 16MHz oscillator RC type or external oscillator The high clock type is controlled by High_Clk code option High_Clk Code Option Description IHRC 16M The high clock is internal 16MHz oscillator RC type XIN and XOUT pins are general purpose I O pins 4M The high clock is external oscillator The typical frequency is 4MHz 4 4 1 INTERNAL HIGH RC The chip is built in RC type internal high clock 16MHz controlled by IHRC_16M code options In IHRC_16M mode the system
12. Chopper Low frequency setting Note Set FDS 1 0 11 for all applications Bit6 BGRENB Band Gap Reference voltage enable control bit 0 Disable Band Gap Reference Voltage 1 Enable Band Gap Reference Voltage Note1 Band Gap Reference voltage must be enable FBRGENB before following function accessing 1 Charge pump Regulator 2 PGIA function 3 16 bit ADC function 4 Low Battery Detect function Note2 PGIA can t work in slow mode unless gain selection is 1x Bit7 CHPENB Chopper clock Enable control pin 0 Disable Chopper clock Chopper clock set to High 1 Enable Chopper clock Note Set CHPENB 1 for all applications SONiX TECHNOLOGY CO LTD Page 117 Preliminary Version 0 4 Ss NX SN8P1919 D D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 10 4 2 AMPCKS PGIA CLOCK SELECTION 092H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 AMPCKS AMPCKS1 AMPCKS1 AMPCKSO R W Ww W Ww After Reset 0 0 0 Bit 2 0 AMPCKS 2 0 register sets the PGIA Chopper working clock The suggestion Chopper clock is 1 95K Hz 4MHz 1 74K 3 58MHz PGIA Clock Fepu 32 28 AMPCKS Refer to the following table for AMPCKS 2 0 register value setting in different Fosc frequency High Clock AMPCKS2 AMCKS1 AMPCKSO OM 3 58M 4M IHRG 3M
13. Fcpu Instruction cycle SONiX TECHNOLOGY CO LTD Page 49 Preliminary Version 0 4 Ss NX SN8P1919 D D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 4 3 OSCM REGISTER The OSCM register is an oscillator control register It controls oscillator status system mode OCAH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OSCM WTCKS WDRST_ WDRATE CPUM1 CPUMO CLKMD STPHX 0 Read Write R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 Bit 1 STPHX External high speed oscillator control bit 0 External high speed oscillator free run 1 External high speed oscillator free run stop Internal low speed RC oscillator is still running Bit 2 CLKMD System high Low clock mode control bit 0 Normal dual mode System clock is high clock 1 Slow mode System clock is external low clock Bit 4 3 CPUM 1 0 CPU operating mode control bits 00 normal 01 sleep power down mode 10 green mode 11 reserved Bit5 WDRATE Watchdog timer rate select bit 0 Fopy 2 Va Fea Bit6 WDRST Watchdog timer reset bit 0 No reset 1 clear the watchdog timer s counter The detail information is in watchdog timer chapter Bit7 WTCKS Watchdog clock source select bit 0 Feru 1 internal RC low clock The WTCKS bit will be set as 1 when Int_16k_RC Always_On selected in the code option WTCKS WTRATE CLKMD err Timer Overflow Time
14. External Reset Circuit Active CPUM1 CPUMO 01 Normal Mode CLKMD 1 CLKMD 0 A CPUM1 CPUMO 10 Slow Mode A PO P1 Wake up Function Active TO Timer Time Out Green Mode External Reset Circuit Active System Mode Switching Diagram Operating mode description POWER DOWN MODE NORMAL SLOW GREEN SLEEP REMARK EHOSC Running By STPHX By STPHX Stop Ext LRC Running Running Running Stop CPU instruction Executing Executing Stop Stop TO timer Active Active Active Inactive Active if TOENB 1 TCO timer Active Active Active Inactive Active if TCOENB 1 TC1 timer Active Active Inactive Inactive Active if TC1ENB 1 Watchdog timer By Watch_Dog By Watch_Dog By Watch_Dog By Watch_Dog Refer to code option 9 Code option Code option Code option Code option description Internal interrupt All active All active TO TCO All inactive External interrupt All active All active All active All inactive PO P1 TO TCO Wakeup source Reset PO P1 Reset EHOSC External high clock Ext LRC External low clock SONiX TECHNOLOGY CO LTD Page 57 Preliminary Version 0 4 S NX SN8P1919 D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 5 2 SYSTEM MODE SWITCHING gt Example Switch normal slow mode to power down sleep mode BOBSET FCPUMO Set CPUMO 1
15. OCAH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OSCM WTCKS WDRST_ WDRATE CPUM1 CPUMO CLKMD STPHX 0 Read Write R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 Bits WDRATE Watchdog timer rate select bit 0 Foru 2 1 Fopy 2 Bit6 WDRST Watchdog timer reset bit 0 No reset 1 clear the watchdog timer s counter The detail information is in watchdog timer chapter Bit7 WTCKS Watchdog clock source select bit 0 Foru 1 internal RC low clock Watchdog timer overflow table WTCKS WTRATE CLKMD Watchdog Timer Overflow Time 1 fopu 27 16 1 fcpu 2 16 1 fcpu 2 16 T EN a0 0 1s Fosc 16KHZ 3V 16K 512 16 0 5s 3V 293 ms Fosc 3 58MHz 500 ms Fosc 32768Hz 65 5s Fosc 16KHZ 3V Note The watchdog timer can be enabled or disabled by the code option SONiX TECHNOLOGY CO LTD Page 77 Preliminary Version 0 4 S NS xX SN8P1919 Y WS D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC Watchdog timer application note is as following e Before clearing watchdog timer check I O status and check RAM contents can improve system error e Don t clear watchdog timer in interrupt vector and interrupt service routine That can improve main routine fail e Clearing watchdog timer program is only at one part of the program This way is the best structure to enhance the watchdog timer function gt Ex
16. PGIA 16 bit ADC 1 2 STACK OPERATION 1 2 1 OVERVIEW The stack buffer has 8 level These buffers are designed to push and pop up program counter s PC data when interrupt service routine and CALL instruction are executed The STKP register is a pointer designed to point active level in order to push or pop up data from stack buffer The STKnH and STKnL are the stack buffers to store program counter PC data RET CALL RETI INTERRUPT A PCH PCL STACK Buffer STACK Buffer STACK Level High Byte Low Byte TKP 7 STKP 1 STKP 1 gt STKP 6 STKP 5 STKP STKP 4 STKP 3 STKP 2 STKP 1 STKP 0 SONiX TECHNOLOGY CO LTD Page 37 Preliminary Version 0 4 Ss NX SN8P1919 D D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 1 2 2 STACK REGISTERS The stack pointer STKP is a 3 bit register to store the address used to access the stack buffer 13 bit data memory STKnH and STKnL set aside for temporary storage of stack addresses The two stack operations are writing to the top of the stack push and reading from the top of stack pop Push operation decrements the STKP and the pop operation increments each time That makes the STKP always point to the top address of stack buffer and write the last program counter value PC into the stack buffer The program counter PC value is stored in the stack buffer before a CALL instruction executed or during i
17. Rao AO Rao X P5 2 Cx AVE X P5 1 CR P5 3 J a a R x Q a a P5 7 yb jf 3 3888813 82 b z0 Z z I X gt gt LO0O SA x xX i I C i I I t He ASM X tal CAVE yy vB 1 Lago 2 C Cavoor AVDDR Cavopcp CAVDD j Cov0o 10K E 04 20pF 20pF SONiX TECHNOLOGY CO LTD Page 135 Preliminary Version 0 4 Ss NX SN8P1919 D D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 1 2 INSTRUCTION TABLE Field Mnemonic Description MOV A M A lt M MOV M A M lt A BOMOV A M A lt M bnak 0 BOMOV M A M bank 0 A MOV A Ael BOMOV Ml M amp I M only for Working registers R Y Z RBANK 8 PFLAG XCH A M A lt gt M BOXCH A M A lt M bank 0 MOVC R A lt ROM Y Z ADC A M A lt A M C if occur carry then C 1 else C 0 ADC M A M lt A M C if occur carry then C 1 else C 0 ADD A M A lt A M if occur carry then C 1 else C 0 ADD M A M lt A M if occur carry then C 1 else C 0 BOADD M A M bank 0 lt M bank 0 A if occur carry then C 1 else C 0 ADD A A lt A if occur carry then C 1 else C 0 SBC A M A lt A M C if occur borrow then C 0 else C 1 SBC M A M lt A M C if occur borrow then C 0 else C 1 SUB A M A lt A M if occur borrow then C 0 else C 1 SUB M A M lt A M if occur borrow then C 0 else C 1 SUB A l A lt A if occur borrow then C 0 else C 1 DAA To adjust ACC s data format from HEX to DEC MUL AM R A lt A M The LB of product stored in Acc
18. SNSP1I919 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC Enable TC1 interrupt function Enable TC10UT Buzzer function Enable PWM function Enable TC1 timer Page 99 Preliminary Version 0 4 Ss NX SN8P1919 D D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 8 5 PWMO MODE 8 5 1 OVERVIEW PWM function is generated by TCO timer counter and output the PWM signal to PWMOOUT pin P5 4 The 8 bit counter counts modulus 256 bits The value of the 8 bit counter TCOC is compared to the contents of the reference register TCOR When the reference register value TCOR is equal to the counter value TCOC the PWM output goes low When the counter reaches zero the PWM output is forced high The ratio duty of the PWMO output is TCOR 256 MAX PWM PWM duty range TCOC valid value TCOR valid bits value Frequency Remark Fcpu 4MHz 0 256 255 256 0x00 OxFF 0x00 OxFF 7 8125K Overflow per 256 count The Output duty of PWM is with different TCOR Duty range is from 0 256 255 256 0 tess 128 254 255 0 da 128 254 255 TCO Clock WU LU UL UL l i l i i TCOR 00H Low i l TCOR 01H i i High l TCOR 80H i l l l l TCOR FFH Low i SONiX TECHNOLOGY CO LTD Page 100 Preliminary Version 0 4 Ss NX SN8P1919 D D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 8 5 2 TCOIRQ AND PWM DUTY In PWM mode
19. SONiX TECHNOLOGY CO LTD Page 81 Preliminary Version 0 4 S NS xX SN8P1919 Y AS D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 8 2 4 TO TIMER OPERATION SEQUENCE TO timer operation sequence of setup TO timer is as following Stop TO timer counting disable TO interrupt function and clear TO interrupt request flag BOBCLR FTOENB TO timer BOBCLR FTOIEN TO interrupt function is disabled BOBCLR FTOIRQ TO interrupt request flag is cleared Set TO timer rate MOV A 0xxx0000b The TO rate control bits exist in bit4 bit6 of TOM The value is from xO00xxxxb x111xxxxb BOMOV TOM A TO timer is disabled Set TO clock source from Fcpu or RTC BOBCLR FTOTB Select TO Fcpu clock source BOBSET FTOTB Select TO RTC clock source Set TO interrupt interval time MOV A 7FH BOMOV TOC A Set TOC value Set TO timer function mode BOBSET FTOIEN Enable TO interrupt function Enable TO timer BOBSET FTOENB Enable TO timer SONiX TECHNOLOGY CO LTD Page 82 Preliminary Version 0 4 S ONiN SN8P1919 w D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 8 3 TIMER COUNTER 0 TCO 8 3 1 OVERVIEW The TCO is an 8 bit binary up counting timer TCO clock sources came internal clock for counting a precision time The internal clock source is from Fcpu or Fosc controlled by TCOX8 flag to get faster clock source Fosc If TCO timer occurs an overflow it wi
20. TC1ENB TCIRATE2 IE TGARATEO ALOAD1 oe eee TC1C3 TC1C7 TC1C3 TC1R7 GIE STKPB3 STKPB2 STKPB1 STKPBO Oa E RO ee _ __ POR gt P15R P14R P13R_ P12R PUR POR Coa P56R_ vu al N pe a o los PMR P20R gt P33R P32R PR P30R P57R P56R HL7 QYZ7 R W SONiX TECHNOLOGY CO LTD Page 25 Preliminary Version 0 4 Ss NX SN8P1919 D D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC Address Remarks OFOH S7PC7 S7PC6 S7PC5 S7PC4 S7PC3 S7PC2 S7PC1 S7PCO OF IH s7Pc12 s7Pc11 s7PCt0 S7PC9 S7PC8 S6PC7 S6PC6 S6PC4 s6PC12 S6PC11 S5PC7 S5PC5 S5PCA S5PC3 S5PC12 S5PC11 S4PC7 S4PC5 S4PCA S4PC3 SWPC12 S4PC 1 S3PC7 S3PC4 S3PC3 3PC12 S2PC7 S2PC4 s2Pc12 S1PC7 S1PC4 OFDH S4PC12 S1PC11 S1PC10 s1PC9 S1PC8 SOPC7 SOPC4 OFFH _ Ll sorc12 sorc11 soPcro soPCe SoPcs Note To avoid system error make sure to put all the 0 and 1 as it indicates in the above table All of register names had been declared in SN8ASM assembler One bit name had been declared in SN8ASM assembler with F prefix code bObset bObcIr bset bclr instructions are only available to the R W registers Ap ha SONiX TECHNOLOGY CO LTD Page 26 Preliminary Version 0 4 N N y SN8
21. sleep mode Note The external low speed clock can t be turned off individually It is controlled by CPUMO CPUM1 bits of OSCM register SONiX TECHNOLOGY CO LTD Page 55 Preliminary Version 0 4 Ss NX SN8P1919 Y WS D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 4 5 2 SYSTEM CLOCK MEASUREMENT Under design period the users can measure system clock speed by software instruction cycle Fcpu This way is useful in RC mode gt Example Fcpu instruction cycle of external oscillator BOBSET POM 0 Set PO 0 to be output mode for outputting Fcpu toggle signal Qu BOBSET P0 0 Output Fcpu toggle signal in low speed clock mode BOBCLR P0 0 Measure the Fcpu frequency by oscilloscope JMP B Note Do not measure the RC frequency directly from XIN the probe impendence will affect the RC frequency SONiX TECHNOLOGY CO LTD Page 56 Preliminary Version 0 4 SONIX SNSPI919 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 5 SYSTEM OPERATION MODE 5 1 OVERVIEW The chip is featured with low power consumption by switching around four different modes as following PO P1 Wake up Function Active PO P1 Wake up Function Active TO Timer Time Out External Reset Circuit Active Normal mode High speed mode Slow mode Low speed mode Power down mode Sleep mode Green mode Power Down Mode Sleep Mode
22. 1 7 PIN CIRCUIT DIAGRAMS 00 a 11 2 CENTRAL PROCESSOR UNIT CPU seesesessossosessoscssesessossosessoseosesessossosessosesesessessoseosesessessesessosees 13 2 1 MEMORY MAP pronar naa tdt e 13 2 1 1 PROGRAM MEMORY ROM A AAA 13 LLLI CHECKSUM CALCULATION o ienen a E E EE a E E a 21 2 1 2 CODE OF TION TABLE Ao 22 2 1 3 DATA MEMORIA AAA AAA AAA AAA 23 2 14 SYSTEM REGISI BER AA A A A aE 24 214 1 SS TE MOREGIS TER TAB LB ni alas o E E E aie 24 2142 SYSTEM REGISTER DESCRIPTION cas 24 2 1 4 3 BIT DEFINITION of SYSTEM REGISTER scsiccsssacecatenenseadseeiseescneeaaciusocseesesssecedenscdenspess 25 lt TO PORT MEER E E A E E EA 74 3 1 VOPORTMODE increas ae cas 74 22 FEAR PULLUP REGISTER ci is 75 3 3 VO PORT DATA REGISTER cont a 76 lt A CERO srt dto dina 79 3 4 1 OVERVIEW A AA AAA A aaa 79 3 4 2 TOM MODE REGISTER id 80 3 4 3 TOC COUNTING REISER das 81 3 4 4 TO TIMER OPERATION SEQUENCE aa 82 4 LCD DRIVER sininanjpoi panal 106 4 1 LCDMI REGISTER sens a it Ree ee artis 106 4 2 OPTION REGISTER DESCRIPTION cacas dadas oacias sis 107 4 3 LCDTIMING iii tado 109 4 4 LCD RAM LOCATION ori a E A A antsy cutie dee a 111 S CHARGE PUMP PGIA AND ADC ono nia cana inline delia 112 SONiX TECHNOLOGY CO LTD Page 3 Preliminary Version 0 4 Ss WN NX SN8P1919 Y WS D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 5 1 OVERVIEW eere E EE AE EA T O E E OE 112 32 ANALOG INPUT tt 112 5 3 VOLTAGE CHARGE PUMP REGULATOR CPR
23. 3 Bit 2 Bit 1 Bit 0 POUR PO1R POOR Read Write W W After reset 0 0 0E1H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 BitO P1UR P15R P14R P13R P12R PAR P10R Read Write W W W W W W After reset 0 0 0 0 0 0 0E2H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 BitO P2UR P21R P20R Read Write W W After reset 0 0 0E3H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 BitO P3UR P33R P32R P31R P30R Read Write W W W W After reset 0 0 0 0 OE5H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P5UR P57R P56R P55R P54R P53R P52R P51R P50R Read Write W W W W W W W W After reset 0 0 0 0 0 0 0 0 Note PnUR is Write Only Register gt Example I O Pull up Register MOV A HOFFH Enable Port1 Pull up register BOMOV P1UR A SONiX TECHNOLOGY CO LTD Preliminary Version 0 4 Page 75 Ss NX SN8P1919 D D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 7 3 VO PORT DATA REGISTER ODOH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PO P01 POO Read Write R W R W After reset 0 0 0D1H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O P1 P15 P14 P13 P12 P11 P10 Read Write R W R W R W R W R W R W After reset 0 0 0 0 0 0 0D2H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P2 P21 P20 Read Write R
24. 7 LQFP80 Table 1 1 Selection table of SN8P1919 1 2 MIGRATION TABLE Migration SN8P1919 Series to SN8P1909 Series Item SN8P1919 SN8P1909 PGIA Gain setting 1x 12 5x 50x 100x 200x 1x 16x 32x 64x 128x PGIA Temperature Drift Good Not Good AVE Voltage 3 0V 2 4V or 1 5V No AVE Internal ADC Reference Voltage V R R 0 8V 0 64Vor 0 4V External only Battery Detect Method By Comparator or By ADC By ADC only Temperature Sensor Build In External ACM 1 2V Voltage Not Change with Sink current Change with Sink current Charge pump clock frequency CPCKS 4 Bit Selection 2 Bit Selection Chopper clock frequency AMPCKS 3 Bit Selection 2 Bit Selection Charge pump Regulator working in slow mode Yes No Operating Current Consumption Less More Slow mode Current Consumption Less More LCD Bias Voltage 1 3 or 1 2 Bias 1 3 or 1 2 Bias Internal 16M RC Oscillator Yes No Easy Layout for AO to X Yes No P2 1 0 I O Available when Fosc IHRC No OTP Programming Method Serial Method Parallel Method PGIA Input Channels 2 Differential or 4 Single ended 3 Differential VLCD and VLCD1 Voltage Can be Different Must be the Same Charge Pump enable cause VDD drop in CR2032 No Yes Positive pin to AVDDCP Positive pin to AVDDCP AVDDCP Capacitor Negative pin to VDD Negative pin to GND Positive pin to AVDDR Positive pin to ACM ACM Capa
25. Auto mode Charge Pump Regulator PGIA ADC CPRENB CPON CPAUTO AVDDRENB Status Status AVDDR Function 0 OFF OFF OV Not Available 1 OFF ON See Note1 See Note1 1 Auto Mode ON 3 8V Available 1 Always ON ON 3 8V Available In Auto Mode Charge Pump ON OFF depended on VDD voltage Auto Mode Description Charge Pump Regulator AVDDR PGIA ADC CPRENB CPON CPAUTO AVDDRENB VDD Status Status Output Function gt 4 1V OFF ON 3 8V Available 1 0 1 1 lt 4 1V ON ON 3 8V Available Note 1 When Charge Pump is OFF and Regulator is ON VDD voltage must be higher than 4 1V to make sure AVDDR output voltage for PGIA and ADC functions are working well Charge Pump Regulator AVDDR PGIA ADC CPRENB CPON CPAUTO AVDDRENB VDD Status Status Output Function gt 4 1V OFF ON 3 8V Available 1 0 0 1 lt 4 1V OFF ON VDD Not Available Note 1 For normally application set CP as Auto mode CPAUTO 1 is strongly recommended Note 2 If VDD is higher than 5 0V don t set Charge Pump as Always ON mode Note 3 Band Gap Reference voltage must be enable first FBRGENB before following function accessing Reference AMPM register for detail information 1 Charge pump Regulator 2 PGIA function 3 16 bit ADC function 4 Low Battery Detect function SONiX TECHNOLOGY CO LTD Page 114 Pr
26. BOBCLR BOBCLR BOBSET Go into green mode BOBCLR BOBSET FTOIEN FTOENB FTOIEN FTOIRQ FTOENB FCPUMO FCPUM1 To disable TO interrupt service To disable TO timer To set TO clock Fcpu 64 To set TOC initial value 74H To set TO interval 10 ms To disable TO interrupt service To clear TO interrupt request To enable TO timer To set CPUMx 10 Note During the green mode with TO wake up function the wakeup pins reset pin and TO can wakeup the system back to the last mode TO wake up period is controlled by program and TOENB must be set SONiX TECHNOLOGY CO LTD Page 59 Preliminary Version 0 4 Ss NX SN8P1919 D D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 1 3 WAKEUP 1 3 1 OVERVIEW Under power down mode sleep mode or green mode program doesn t execute The wakeup trigger can wake the system up to normal mode or slow mode The wakeup trigger sources are external trigger PO P1 level change and internal trigger TO timer overflow Power down mode is waked up to normal mode The wakeup trigger is only external trigger PO P1 level change Green mode is waked up to last mode normal mode or slow mode The wakeup triggers are external trigger PO P1 level change and internal trigger TO timer overflow 1 3 2 WAKEUP TIME When the system is in power down mode sleep mode the high clock oscillator stops When w
27. BUFO BUFO is from 0 to 4 JMP_A 5 The number of the jump table listing is five 0X0100 JMP AOPOINT ACC 0 jump to AOPOINT 0X0101 JMP A1POINT ACC 1 jump to A1POINT 0X0102 JMP A2POINT ACC 2 jump to A2POINT 0X0103 JMP A3POINT ACC 3 jump to ASPOINT 0X0104 JMP A4POINT ACC 4 jump to A4POINT SONiX TECHNOLOGY CO LTD Page 20 Preliminary Version 0 4 SONIX 2 1 2 4 CHECKSUM CALCULATION SNSPI919 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC The last ROM address is reserved area User should avoid these addresses last address when calculate the Checksum value gt Example The demo program shows how to calculated Checksum from 00H to the end of user s code MOV A END_USER_CODE L BOMOV END_ADDR1 A Save low end address to end_addr1 MOV A fEND_USER_CODE M BOMOV END_ADDR2 A Save middle end address to end_addr2 CLR Y Set Y to OOH CLR Z Set Z to OOH MOVC BOBSET FC Clear C flag ADD DATA1 A Add A to Data1 MOV A R ADC DATA2 A Add R to Data2 JMP END CHECK Check if the YZ address the end of code AAA INCMS Z Z Z 1 JMP B If Z OOH calculate to next address JMP Y_ADD 1 If Z OOH increase Y END_CHECK MOV A END_ADDR1 CMPRS A Z Check if Z low end address JMP AAA If Not jump to checksum calculate MOV A END_ADDR2 CMPRS A Y If Yes check if Y middle end address JMP AAA If Not jump to checksum calculate JMP CHECKSUM_END If Yes checks
28. Bit 3 Bit 2 Bit 1 Bit 0 P1M P15M P14M P13M P12M P11M P10M Read Write R W R W R W R W R W R W After reset 0 0 0 0 0 0 0C2H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P2M P21M P20M Read Write R W R W After reset 0 0 0C3H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P3M P33M P32M P31M P30M Read Write R W R W R W R W After reset 0 0 0 0 OC5H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P5M P57M P56M P55M P54M P53M P52M P51M P50M Read Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 Bit 7 0 PnM 7 0 Pn mode control bits n 0 5 0 Pn is input mode 1 Pn is output mode Note 1 Users can program them by bit control instructions BOBSET BOBCLR 2 Port 2 is shared with XIN and XOUT 3 Port 3 is shared with LCD gt Example I O mode selecting CLR P1M Set all ports to be input mode CLR P2M MOV A 0FFH Set all ports to be output mode BOMOV P1M A BOMOV P2M A BOBCLR P1M 0 Set P1 0 to be input mode BOBSET P1M 0 Set P1 0 to be output mode SONiX TECHNOLOGY CO LTD Page 74 Preliminary Version 0 4 SONIX 7 2 I O PULL UP REGISTER SNSPI919 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC OEOH Bit 7 Bit 6 Bit 5 Bit 4 Bit
29. Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 6 7 INT1 P0 1 INTERRUPT OPERATION When the INT1 trigger occurs the PO1IRQ will be set to 1 no matter the PO1IEN is enable or disable If the PO1IEN 1 and the trigger event PO1IRQ is also set to be 1 As the result the system will execute the interrupt vector ORG 8 If the PO1IEN 0 and the trigger event PO1IRQ is still set to be 1 Moreover the system won t execute interrupt vector even when the PO1IRQ is set to be 1 Users need to be cautious with the operation under multi interrupt situation Note The interrupt trigger direction of P0 1 is controlled by PEDGEN bit gt Example INT1 interrupt request setup BOBSET FPO1IEN Enable INT1 interrupt service BOBCLR FPO1IRQ Clear INT1 interrupt request flag BOBSET FGIE Enable GIE gt Example INT1 interrupt service routine ORG 8 Interrupt vector JMP INT_SERVICE INT_SERVICE Push routine to save ACC and PFLAG to buffers BOBTS1 FP01IRQ Check P01IRQ JMP EXIT_INT PO1IRQ 0 exit interrupt vector BOBCLR FP01IRQ Reset PO1IRQ are INT1 interrupt service routine EXIT_INT Pop routine to load ACC and PFLAG from buffers RETI Exit interrupt vector SONiX TECHNOLOGY CO LTD Page 68 Preliminary Version 0 4 N No VAY SN8P1919 S S E X 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 6 8 TO INTERRUPT OPERATION When the TOC counter occurs ove
30. D N E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 1 6 marking Definition 16 1 INTRODUCTION There are many different types in Sonix 8 bit MCU production line This note listed the production definition of all 8 bit MCU for order or obtain information This definition is only for Blank OTP MCU 16 2 MARKING INDETIFICATION SYSTEM SN8 X PART No X X X Material Temperature Range Shipping Package Device ROM Type Title SONiX TECHNOLOGY CO LTD Page 144 B PB Free Package G Green Package 0 C 70 C W Wafer H Dice Q LQFP 1919 P OTP SONIX 8 bit MCU Production Preliminary Version 0 4 SONiM 16 3 MARKING EXAMPLE SNSPI919 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC Name ROM Type Device Package Temperature Material SN8P1919QB OTP 1919 LQFP 0 C 70 C PB Free Package SN8P1919QG OTP 1919 LQFP 0 C 70 C Green Package 16 4 DATECODE SYSTEM XX XX XXXXX SONiX Internal Use Day Month Year SONiX TECHNOLOGY CO LTD Page 145 1 January 2 February 9 September A October B November C December 03 2003 04 2004 05 2005 06 2006 Preliminary Version 0 4 Ss NX SN8P1919 D a D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC SONIX reserves the right to make change without further notice to any products herein to improve reliability function or design SONI
31. Define ACCBUF for store ACC data CODE ORG 0 OOOOH JMP START Jump to user program address ORG 8 Interrupt vector BOXCH A ACCBUF Save ACC in a buffer PUSH Save 0x80 0x87 working registers and PFLAG register to buffers POP Load 0x80 0x87 working registers and PFLAG register from buffers BOXCH A ACCBUF Restore ACC from buffer RETI End of interrupt service routine START The head of user program pis User program JMP START End of user program ENDP End of program SONiX TECHNOLOGY CO LTD Page 15 Preliminary Version 0 4 SONIX SNSPI919 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC gt Example Defining Interrupt Vector The interrupt service routine is following user program DATA ACCBUF CODE ORG JMP ORG JMP ORG START JMP MY_IRQ BOXCH PUSH POP BOXCH RETI ENDP DS 1 0 START MY_IRQ 10H START A ACCBUF A ACCBUF Define ACCBUF for store ACC data 0000H Jump to user program address Interrupt vector 0008H Jump to interrupt service routine address 0010H The head of user program User program End of user program The head of interrupt service routine Save ACC in a buffer Save 0x80 0x87 working registers and PFLAG register to buffers Load 0x80 0x87 working registers and PFLAG register from buffers Restore ACC from buffer End of interrupt service routine End of program
32. Detect Low Detect Watchdog _ Overflow Ny Watchdog Normal Run Watchdog Reset watchdog Stop System Normal Run j j System Status system Stop i Power On External Watchdog Delay Time Reset Delay Reset Delay Time Time SONiX TECHNOLOGY CO LTD Page 40 Preliminary Version 0 4 Ss NX SN8P1919 D D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 3 2 POWER ON RESET The power on reset depend on LVD operation for most power up situations The power supplying to system is a rising curve and needs some time to achieve the normal voltage Power on reset sequence is as following e Power up System detects the power voltage up and waits for power stable e External reset System checks external reset pin status If external reset pin is not high level the system keeps reset status and waits external reset pin released System initialization All system registers is set as initial conditions and system is ready Oscillator warm up Oscillator operation is successfully and supply to system clock Program executing Power on sequence is finished and program executes from ORG 0 3 3 WATCHDOG RESET Watchdog reset is a system protection In normal condition system works well and clears watchdog timer by program Under error condition system is in unknown situation and watchdog can t be clear by program before watchdog timer overflow Watchdog
33. Note During the sleep only the wakeup pin and reset can wakeup the system back to the normal mode gt Example Switch normal mode to slow mode BOBSET FCLKMD To set CLKMD 1 Change the system into slow mode BOBSET FSTPHX To stop external high speed oscillator for power saving gt Example Switch slow mode to normal mode The external high speed oscillator is still running BOBCLR FCLKMD To set CLKMD 0 gt Example Switch slow mode to normal mode The external high speed oscillator stops If external high clock stop and program want to switch back normal mode It is necessary to delay at least 20ms for external clock stable BOBCLR FSTPHX Turn on the external high speed oscillator BOMOV Z 54 If VDD 5V internal RC 32KHz typical will delay DECMS Z 0 125ms X 162 20 25ms for external clock stable JMP B BOBCLR FCLKMD Change the system back to the normal mode Example Switch normal slow mode to green mode BOBSET FCPUM1 Set CPUM1 1 Note If TO TCO timer wakeup function is disabled in the green mode only the wakeup pin and reset pin can wakeup the system backs to the previous operation mode SONiX TECHNOLOGY CO LTD Page 58 Preliminary Version 0 4 SONIX SNSPI919 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC gt Example Switch normal slow mode to Green mode and enable TO wakeup function Set TO timer wakeup function BOBCLR BOBCLR
34. PGIA 16 bit ADC 6 11 MULTI INTERRUPT OPERATION Under certain condition the software designer uses more than one interrupt requests Processing multi interrupt request requires setting the priority of the interrupt requests The IRQ flags of interrupts are controlled by the interrupt event Nevertheless the IRQ flag 1 doesn t mean the system will execute the interrupt vector In addition which means the IRQ flags can be set 1 by the events without enable the interrupt Once the event occurs the IRQ will be logic 1 The IRQ and its trigger event relationship is as the below table Interrupt Name Trigger Event Description POOIRQ P0 0 trigger controlled by PEDGE TOIRQ TOC overflow For multi interrupt conditions two things need to be taking care of One is to set the priority for these interrupt requests Two is using IEN and IRQ flags to decide which interrupt to be executed Users have to check interrupt control bit and interrupt request flag in interrupt routine SONiX TECHNOLOGY CO LTD Page 72 Preliminary Version 0 4 Ss NX SN8P1919 D D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC gt Example Check the interrupt request under multi interrupt operation ORG 8 Interrupt vector JMP INT_SERVICE INT_SERVICE Push routine to save ACC and PFLAG to buffers INTPOOCHK Check INTO interrupt request BOBTS1 FPOOIEN Check POOIEN JMP INTPO1CHK Jump check to next interrupt B
35. PnM PnUR a a e gt Input Bus Pin e Output Bus Port2 structure Pull Up Oscillator PnM Code Option gt PAM PASES re gt Input Bus Pin Output ce E ee Output Bus gt Int Osc SONiX TECHNOLOGY CO LTD Page 11 Preliminary Version 0 4 SON N SN8P1919 N D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC Port3 structure Pull Up PnM P3SEG PnM PnUR wag gt Input Bus Pin Lea pera y Output Bus Int LCD SEG SONiX TECHNOLOGY CO LTD Page 12 Preliminary Version 0 4 Ss NX SN8P1919 D D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 2 CENTRAL PROCESSOR UNIT CPU 2 1 MEMORY MAP 2 1 1 PROGRAM MEMORY ROM 6K words ROM 0000H User reset vector 0001H Jump to user start address 0002H General purpose area Jump to user start address 0003H Jump to user start address 0004H ral Reserved 0007H 0008H Interrupt vector User interrupt vector 0009H User program 000FH 0010H General purpose area 0011H 17FEH 17FFH End of user program 2 1 2 RESET VECTOR 0000H A one word vector address area is used to execute system reset Power On Reset NTO 1 NPD 0 Watchdog Reset NTO 0 NPD 0 External Reset NTO 1 NPD 1 After power on reset external reset or watchdog timer overflow reset t
36. Reserved N A N A Note 1 V Al Al Al voltage Al voltage Note 2 V Al ACM Al voltage ACM voltage Note 3 The purpose of Input Short mode is only for PGIA offset testing Note 4 When CPR is Disable or system in stop mode signal on analog input pins must be Zero 0 V including Al Al X X R and R or it will cause the current consumption from these pins AMPCHSJ 3 0 0000 AMPCHSJ 3 0 0010 Al Al1 Alt ACM l i a ee e cae te Loa AMPCHSJ 3 0 0011 AMPCHS 2 0 0110 r OR l l Alt lACM l ACM i Mr i eee ee J SONiX TECHNOLOGY CO LTD Page 119 Preliminary Version 0 4 SNSPI919 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC N No WAY NONA 10 4 4 Temperature Sensor TS In applications sensor characteristic might change in different temperature also To get the temperature information SN8P1919 build in a temperature senor TS for temperature measurement Select the respective PGIA channel to access the Temperature Sensor ADC output AMPCHS 3 0 1000 Note1 When selected Temperature Sensor PGIA gain must set to 1x or the result will be incorrect Note2 Under this setting X will be the V TS voltage and X will be 0 4V Note3 The Temperature Sensor was just a reference data not real air temperature For precision application please use external Thermister
37. TCOC TCOR 131 MOV A 01100000B BOMOV TCOM A Set the TCO rate to Fcpu 4 MOV A 131 Set the auto reload reference value BOMOV TCOC A BOMOV TCOR A BOBSET FTCOOUT Enable TCO output to P5 4 and disable P5 4 I O function BOBSET FALOAD1 Enable TCO auto reload function BOBSET FTCOENB Enable TCO timer Note Buzzer output is enable and PWMOOUT must be 0 SONiX TECHNOLOGY CO LTD Page 89 Preliminary Version 0 4 Ss NX SN8P1919 D D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 8 3 7 TCO TIMER OPERATION SEQUENCE TCO timer operation includes timer interrupt event counter TCOOUT and PWM The sequence of setup TCO timer is as following e Stop TCO timer counting disable TCO interrupt function and clear TCO interrupt request flag BOBCLR FTCOENB TCO timer TCOOUT and PWM stop BOBCLR FTCOIEN TCO interrupt function is disabled BOBCLR FTCOIRQ TCO interrupt request flag is cleared Set TCO timer rate Besides event counter mode MOV A 0xxx0000b The TCO rate control bits exist in bit4 bit6 of TCOM The value is from xO00xxxxb x111xxxxb BOMOV TCOM A TCO interrupt function is disabled Set TCO timer clock urce BOBCLR FTCOX8 Select TCO Fcpu internal clock source or BOBSET FTCOX8 Select TCO Fosc internal clock source Note TCOX8 is useless in TCO external clock source mode Set TCO timer auto load mode BOBCLR FAL
38. To set an immediate data 12H into ACC gt Example Move the immediate data 12H to R register BOMOV R 12H To set an immediate data 12H into R register Note In immediate addressing mode application the specific RAM must be 0x80 0x87 working register 2 2 2 DIRECTLY ADDRESSING MODE The directly addressing mode moves the content of RAM location in or out of ACC gt Example Move 0x12 RAM location data into ACC BOMOV A 12H To get a content of RAM location 0x12 of bank 0 and save in ACC gt Example Move ACC data into 0x12 RAM location BOMOV 12H A To get a content of ACC and save in RAM location 12H of bank 0 2 2 3 INDIRECTLY ADDRESSING MODE The indirectly addressing mode is to access the memory by the data pointer registers H L Y Z Example Indirectly addressing mode with HL register BOMOV H 0 To clear H register to access RAM bank 0 BOMOV L 12H To set an immediate data 12H into L register BOMOV A HL Use data pointer HL reads a data from RAM location 012H into ACC Example Indirectly addressing mode with YZ register BOMOV Y 0 To clear Y register to access RAM bank 0 BOMOV Z 12H To set an immediate data 12H into Z register BOMOV A YZ Use data pointer YZ reads a data from RAM location 012H into ACC SONiX TECHNOLOGY CO LTD Page 36 Preliminary Version 0 4 Ss NS NX SN8P1919 Y WS D E A 8 Bit Micro Controller with Charge pump Regulator
39. V3 0 Number Pin 1 VDD GND 14 22 45 VSS CE Di D3 D2 D5 D4 D7 K 8 P1 0 P1 1 0 P1 2 7 11 12 13 14 De 15 16 17 Hs AST 19 J J 20 P1 3 3 39 4 SONiX TECHNOLOGY CO LTD Page 139 Preliminary Version 0 4 Ss NX SN8P1919 D D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 1 4 ELECTRICAL CHARACTERISTIC 14 1 ABSOLUTE MAXIMUM RATING Supply voltage Vib ciuionscicissiid ios 0 3V 6 0V Input in voltage Vin E A adds Vss 0 2V Vop 0 2V Operating ambient temperature Topr cocococcccccccccccncncococononncncncncnnnanininananos 0 C 70 C Storage ambient temperature Tstop 2 cececeeceececeeceeeeeeeeeeseeeseeneaneaeeeeans 40 C 125 C 14 2 ELECTRICAL CHARACTERISTIC All of voltages refer to Vss VDD 5 0V Fosc 4MHz Fcpu 1MHZ ambient temperature is 25 C unless otherwise note PARAMETER DESCRIPTION UNIT Operating voltage Normal mode Vpp a S Caa so ss v RAM Data Retention voltage e ee Input High Voltage Vw Vop o o OR Vn Vss Voo 5v_ 5o 100 130 ke VO port input leakage current l exs Pulkup resistor disable Vw Von 2 uA sink current _lol_ Voe Vss 0 5V 8 15 mA INTn trigger pulse width INTO INT1 interrupt request pulse width Ac yt Idd1 Low de normal Mode Vdd 5V 4Mhz IHRCI 1 8 ae qow Borer tat ee normal Mode Vdd 5V 4Mhz IHRCI ldd3 Low Power
40. W R W After reset 0 0 0D3H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P3 P33 P32 P31 P30 Read Write R w R W R W R W After reset 0 0 0 0 OD5H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P5 P57 P56 P55 P54 P53 P52 P51 P50 Read Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 gt Example Read data from input port BOMOV A PO Read data from Port 0 BOMOV A P1 Read data from Port 4 BOMOV A P3 Read data from Port 4 gt Example Write data to output port MOV A HOFFH Write data FFH to all Port BOMOV P1 A BOMOV P5 A gt Example Write one bit data to output port BOBSET P1 0 Set P1 0 to be 1 BOBCLR P1 0 Set P1 0 to be 0 SONiX TECHNOLOGY CO LTD Page 76 Preliminary Version 0 4 SONIX 8 TIMERS SN8P1919 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 8 1 WATCHDOG TIMER WDT The watchdog timer WDT is a binary up counter designed for monitoring program execution If the program goes into the unknown status by noise interference WDT overflow signal raises and resets MCU The instruction that clears the watchdog timer BOBSET FWDRST should be executed within a certain period If an instruction that clears the watchdog timer is not executed within the period and the watchdog timer overflows reset signal is generated and system is restarted
41. Wait_10ms Delay 10ms for AVDDR Voltage Stabilize ACM_Enable XBOBSET FACMENB Enable ACM Voltage 1 2v CALL Wait_5ms Delay 5ms for ACM Voltage Stabilize AVE_Enable XBOBSET FAVENB Enable AVE Voltage 3 0V 2 4V 1 5V CALL Wait_10ms Delay 10ms for AVE Voltage Stabilize PGIA_Init MOV A 11110110B XBOMOV AMPM A Enable Band Gap Set FDS 11 CHPENB 1 PGIA Gain 200 MOV A 00000100B XBOMOV AMPCKS A Set AMPCKS 100 for PGIA working clock 1 9K 4M X tal MOV A 00h XBOMOV AMPCHS A Selected PGIA differential input channel Al1 Al1 PGIA_Enable XBOBSET FAMPENB Enable PGIA function si V X X Output V Al1 Al1 x 200 gt Note 1 Enable Charge Pump Regulator before PGIA working gt Note 2 Please set PGIA relative registers first then enable PGIA function bit SONiX TECHNOLOGY CO LTD Page 121 Preliminary Version 0 4 SONIX Example PGIA channel change PGIA_Init PGIA_Enable PGIA_Sensor PGIA_TS XBOBSET MOV XBOMOV MOV XBOMOV MOV XBOMOV MOV XBOMOV A 11110110B AMPM A A 00000100B AMPCKS A A 00000000B AMPCHS A FAMPENB A 11110111B AMPM A A 00000001B AMPCHS A A 11110001B AMPM A A 00001000B AMPCHS A SONiX TECHNOLOGY CO LTD SNSPI919 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC Enable Band Gap Set FDS 11 CHPENB 1 PGIA Gain 200 Set AMPCKS 100 for PGIA working clock
42. and HB stored in R register ZF affected f by Acc AND A M A lt A and M AND M A M lt A and M AND A l A lt Aandl OR A M A lt AorM OR M A M lt AorM OR Al A lt Aor A M A lt A xor M M lt A xor M A lt Axorl A b3 b0 b7 b4 lt M b7 b4 b3 b0 A R l T H M E T l C SWAP P SWAPM M M b3 b0 b7 b4 M b7 b4 b3 b0 R RRC M A lt RRC M O RRCM M M lt RRC M C RLC M A lt RLC M E RLCM M M RLC M S CLR M M lt 0 S BCLR M b M b 0 BSET M b M b lt 1 BOBCLR M b M bank 0 b lt 0 BOBSET M b M bank 0 b lt 1 CMPRS A l ZF C lt A I IA 1 then skip next instruction B CMPRS A M ZFC lt A M If A M then skip next instruction R INCS M A lt M 1 If A 0 then skip next instruction A INCMS M M lt M 1 If M 0 then skip next instruction N DECS M A lt M 1 IfA 0 then skip next instruction C DECMS M M amp M 1 If M 0 then skip next instruction H BTSO M b If M b 0 then skip next instruction BTS1 M b If M b 1 then skip next instruction BOBTSO M b If M bank 0 b 0 then skip next instruction BOBTS1 M b If M bank 0 b 1 then skip next instruction JMP d PC15 14 lt RomPages1 0 PC13 PCO lt d CALL d Stack lt PC15 PC0 PC15 14 lt RomPages1 0 PC13 PCO lt d M PC lt Stack l PC lt Stack and to enable global interrupt S To push working registers 080H 087H into buffers Cc POP To pop working registers 080H 087H from buffers NOP No oper
43. and ROM addressing OPTION RCLK options register PFLAG ROM page and special flag register RBANK RAM bank select register AMPM PGIA mode register AMPCHS PGIA channel selection AMPCKS PGIA clock selection ADCM ADC s mode register ADCKS ADC clock selection CPM Charge pump mode CPCKS Charge pump clock selection DFM Decimation filter mode ADCDL ADC low byte data buffer ADCDH ADC high byte data buffer PAM Port N input output mode register P1W Port 1 wakeup register Py Port N data buffer PyUR Port N pull up register INTEN Interrupt enable register INTRQ Interrupt request register LCDM1 LCD mode register OSCM Oscillator mode register TOM Timer O mode register PCH PCL Program counter TOC Timer 0 counting register TCOM Timer Counter 0 mode register TC1M Timer Counter 1 mode register TCOC Timer Counter O counting register TC1C Timer Counter 1 counting register TCOR Timer Counter 0 auto reload data buffer STKP Stack pointer buffer LBTM Low Battery Detect Register HL RAM HL indirect addressing index pointer STKO STK7 Stack 0 stack 7 buffer YZ RAM YZ indirect addressing index pointer SONiX TECHNOLOGY CO LTD Page 24 Preliminary Version 0 4 Ss NX SN8P1919 D D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 2 1 5 3 BIT DEFINITION of SYSTEM REGISTER ORBITZ RBIT6 ORBITS RBIT4 RBIT3 RBIT2 RBIT1 RBITO RW R_ NT No e J e gt ZR PLA lo TE RB
44. and find out the mapping system rate Adjust the system rate to the value and the system exits the dead band issue This way needs to modify whole program timing to fit the application requirement External reset circuit The external reset methods also can improve brown out reset and is the complete solution There are three external reset circuits to improve brown out reset including Zener diode reset circuit Voltage bias reset circuit and External reset IC These three reset structures use external reset signal and control to make sure the MCU be reset under power dropping and under dead band The external reset information is described in the next section SONiX TECHNOLOGY CO LTD Page 44 Preliminary Version 0 4 Ss NX SN8P1919 D D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 3 5 EXTERNAL RESET External reset pin is Schmitt Trigger structure and low level active The system is running when reset pin is high level voltage input The reset pin receives the low voltage and the system is reset The external reset operation actives in power on and normal running mode During system power up the external reset pin must be high level input or the system keeps in reset status External reset sequence is as following e External reset System checks external reset pin status If external reset pin is not high level the system keeps reset status and waits external reset pin released System initia
45. ert pt o o n C A Positive capacitor terminal for charge pump regulator Pe A _ Negative capacitor terminal for charge pump regulator VPP RST OTP ROM programming pin System reset input pin Schmitt trigger structure active low normal stay to high XINXOUT_ 1O External High clock oscillator pins RC mode from XIN POO INTO PortO 0 and shared with INTO trigger pin Schmitt trigger Built in pull up resisters POA INTA PortO 1andshared with INT1 trigger pin Built in pull up resisters Com s0 O _ COM0O COM3 LCD driver common port _____________________ P1f5 0 VO Port1 0 Port 1 5 bi direction pins wakeup pins Built in pull up resisters P2rt0 O Port2 0 Port2 1 bi direction pins Built in pull up resisters Share with Xin Xout P5 3 P5 4 VO pi direction pins Built in pull up resisters Shared with PWM TCOUT P5 0 2 5 7 P3a o3 VO pbi direction pins Built in pull up resisters Share with SEG28 31 LBATIN1 2 ComparatorInputPin SEGO SEG31 O LCD driver segment pins gt SS SONiX TECHNOLOGY CO LTD Page 10 Preliminary Version 0 4 S Q xX SN8P1919 D wd D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 1 7 PIN CIRCUIT DIAGRAMS Port 0 Port 4structure Pull Up PnUR Pin e gt Input Bus Port1 Port5 structure Pull Up PnM lt
46. multi address jumping function Program Counter supports ADD M A ADC M A and BOADD M A instructions for carry to PCH when PCL overflow automatically For jump table or others applications users can calculate PC value by the three instructions and don t care PCL overflow problem Note PCH only support PC up counting result and doesn t support PC down counting When PCL is carry after PCL ACC PCH adds one automatically If PCL borrow after PCL ACC PCH keeps value and not change gt Example If PC 0323H PC 0323H PC 0328H MOV BOMOV MOV BOMOV gt Example If PC 0323H PC 0323H BOADD JMP JMP JMP JMP PCH 03H PCL 23H A 28H PCL A Jump to address 0328H A 00H PCL A Jump to address 0300H PCH 03H PCL 23H PCL A PCL PCL ACC the PCH cannot be changed AOPOINT If ACC 0 jump to AOPOINT A1POINT ACC 1 jump to A1POINT A2POINT ACC 2 jump to A2POINT A3POINT ACC 3 jump to A3POINT 2 1 7 H L REGISTERS The H and L registers are the 8 bit buffers There are two major functions of these registers e can be used as general working registers e can be used as RAM data pointers with HL register 081H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H HBIT7 HBIT6 HBIT5 HBIT4 HBIT3 HBIT2 HBIT1 HBITO Read Write R W R W R W R W R W R W R W R W After reset X X X X X X X X 080H Bit 7 Bit 6 Bit 5
47. oni IIS ldd4 Low Power O Input Low Voltage SONiX TECHNOLOGY CO LTD Page 140 Preliminary Version 0 4 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC Stop High Clock Slow mode Vdd 5V Ext 32768hz rs Idd10 Stop High eae ccs Slow mode ae 5V Ext 32768hz 200 ELA El Idd11 Stop High Clock LCD ON CPR ON Vdd 3V Ext 32768hz 250 500 ua Green mode Vdd 5V Ext 32768hz_ 10 20 uA Idd12 Stop High Clock E LCD OFF CPR OFF Vdd 3V Ext 32768hz 5 10 uA Green mode Vdd 5V Ext 32768hz 20 40 uA ldd13 Stop High Clock z LCD ON CPR OFF Vdd 3V Ext 32768hz 20 uA Green mode Vdd 5V Ext 32768hz 200 400 uA Idd14 Stop High Clock 5 LCD ON CPR OFF Vdd 3V Ext 32768hz 250 500 uA uta almas EA Epa ua i Vdd 3V foz 5 wl Internal High Clock Freq Fro Internal High RC Oscillator Frequency 14 16 18 MHz Fopu Finrc 16 LVD detect level Internal POR detect level These parameters are for design reference not tested gt Note Analog Parts including Charge Pump Regulator CPR PGIA and ADC SONiX TECHNOLOGY CO LTD Page 141 Preliminary Version 0 4 NX SN8P1919 D D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC All of voltages refer to Vdd 3 8V Fosc 4MHz ambient temperature is 25 C unless otherwise note PARAMETER SYM DESCRIPTION MIN TYP MAX UNIT Analog to Digita
48. sensor HH In 25C V TS will be about 0 8V and if temperature rise 10C V TS will decrease about 15mV if temperature drop 10C V TS will increase about 15mV Example Temperature V TS V REF REF ADC output 15 0 815V 0 8V 16211 25 0 800V 0 8V 15625 35 0 785V 0 8V 15039 By ADC output of V TS can get temperature information and compensation the syste Note1 The V TS voltage and temperature curve of each chip might different Calibration in room temperature is necessary when application temperature sensor Note2 The typical temperature parameter of Temperature Sensor is 1 5mV C SONiX TECHNOLOGY CO LTD Page 120 Preliminary Version 0 4 Ss NX SN8P1919 Y WS D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC Example PGIA setting Fosc 4M X tal CPREG_Init XBOBSET FBGRENB Enable Band Gap Reference voltage MOV A 00001011b XBOMOV CPCKS A Set CPCKS as slowest clock to void VDD dropping MOV A 00011100B f XBOMOV CPM A Set AVE 3 0V CP as Auto mode and Disable AVDDR AVE ACM voltage before enable Charge pump CP_Enable XBOBSET FCPRENB Enable Charge Pump CALL Wait_200ms Delay 200ms for Charge Pump Stabilize MOV A 0000100b XBOMOV CPCKS A Set CPCKS as 15 6K for 10mA current loading CALL Wait_100ms Delay 100ms for Voltage Stabilize AVDDR_Enable XBOBSET FAVDDRENB Enable AVDDR Voltage 3 8V CALL
49. timer overflow occurs and the system is reset After watchdog reset the system restarts and returns normal mode Watchdog reset sequence is as following Watchdog timer status System checks watchdog timer overflow status If watchdog timer overflow occurs the system is reset System initialization All system registers is set as initial conditions and system is ready Oscillator warm up Oscillator operation is successfully and supply to system clock Program executing Power on sequence is finished and program executes from ORG 0 Watchdog timer application note is as following eo Before clearing watchdog timer check I O status and check RAM contents can improve system error e Don t clear watchdog timer in interrupt vector and interrupt service routine That can improve main routine fail e Clearing watchdog timer program is only at one part of the program This way is the best structure to enhance the watchdog timer function Note Please refer to the WATCHDOG TIMER about watchdog timer detail information SONiX TECHNOLOGY CO LTD Page 41 Preliminary Version 0 4 Ss NX SN8P1919 D D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 3 4 BROWN OUT RESET 3 4 1 BROWN OUT DESCRIPTION The brown out reset is a power dropping condition The power drops from normal voltage to low voltage by external factors e g EFT interference or external loading changed The brown out reset would ma
50. to improve brown out reset as following eo LVD reset Watchdog reset Reduce the system executing rate External reset circuit Zener diode reset circuit Voltage bias reset circuit External reset IC Note 1 The Zener diode reset circuit Voltage bias reset circuit and External reset IC can completely improve the brown out reset DC low battery and AC slow power down conditions 2 For AC power application and enhance EFT performance the system clock is 4MHz 4 1 mips and use external reset Zener diode reset circuit Voltage bias reset circuit External reset IC The structure can improve noise effective and get good EFT characteristic SONiX TECHNOLOGY CO LTD Page 43 Preliminary Version 0 4 Ss NX SN8P1919 D D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC LVD reset VDD Power yss l Power is below LVD Detect Voltage and System Reset System Normal Run System Status system stop lPower On Delay Time The LVD low voltage detector is built in Sonix 8 bit MCU to be brown out reset protection When the VDD drops and is below LVD detect voltage the LVD would be triggered and the system is reset The LVD detect level is different by each MCU The LVD voltage level is a point of voltage and not easy to cover all dead band range Using LVD to improve brown out reset is depend on application requir
51. zero CLR YZ END_CLR End of clear general purpose data memory area of bank 0 SONiX TECHNOLOGY CO LTD Page 33 Preliminary Version 0 4 S WN 9 NX SN8P1919 N D A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC SONiX TECHNOLOGY CO LTD Page 34 Preliminary Version 0 4 SONIX 2 1 7 3 R REGISTERS SNSPI919 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC R register is an 8 bit buffer There are two major functions of the register e Can be used as working register e For store high byte data of look up table MOVC instruction executed the high byte data of specified ROM address will be stored in R register and the low byte data will be stored in ACC 082H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R RBIT7 RBIT6 RBIT5 RBIT4 RBIT3 RBIT2 RBIT1 RBITO Read Write R W R W R W R W R W R W R W R W After reset z z E Note Please refer to the LOOK UP TABLE DESCRIPTION about R register look up table application SONiX TECHNOLOGY CO LTD Page 35 Preliminary Version 0 4 Ss NX SN8P1919 D D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 2 2 ADDRESSING MODE 2 2 1 IMMEDIATE ADDRESSING MODE The immediate addressing mode uses an immediate data to set up the location in ACC or specific RAM gt Example Move the immediate data 12H to ACC MOV A 12H
52. 1 the C terminal of the PNP transistor outputs high voltage and MCU operates normally When VDD is below 0 7V x R1 R2 R1 the C terminal of the PNP transistor outputs low voltage and MCU is in reset mode Decide the reset detect voltage by R1 R2 resistances Select the right R1 R2 value to conform the application In the circuit diagram condition the MCU s reset pin level varies with VDD voltage variation and the differential voltage is 0 7V If the VDD drops and the voltage lower than reset pin detect level the system would be reset If want to make the reset active earlier set the R2 gt R1 and the cap between VDD and C terminal voltage is larger than 0 7V The external reset circuit is with a stable current through R1 and R2 For power consumption issue application e g DC power system the current must be considered to whole system power consumption Note Under unstable power condition as brown out reset Zener diode rest circuit and Voltage bias reset circuit can protects system no any error occurrence as power dropping When power drops below the reset detect voltage the system reset would be triggered and then system executes reset sequence That makes sure the system work well under unstable power situation SONiX TECHNOLOGY CO LTD Page 47 Preliminary Version 0 4 Ss NX SN8P1919 D D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 3 6 5 External Reset IC
53. 1 9K 4M X tal Selected PGIA differential input channel Al1 Al1 Enable PGIA function V X X Output V Al1 Al1 x 200 Don t Disable PGIA when change PGIA CH Enable Band Gap Set FDS 11 CHPENB 1 PGIA Gain 200 Selected PGIA as Differential channel V X X Output V AI2 A12 x 200 Don t Disable PGIA when change PGIA CH Enable Band Gap Set FDS 11 CHPENB 1 PGIA Gain 1x Selected PGIA as Temperature Sensor ch V X X Output V TS 0 4 x 1 Page 122 Preliminary Version 0 4 S SN8P1919 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC NiX 10 5 16 Bit ADC 10 5 1 ADCM ADC Mode Register 093H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ADCM IRVS RVS1 RVSO ADCENB R W R W R W R W R W After Reset 0 0 0 0 0 Bito ADCENB ADC function control bit 0 Disable 16 bit ADC 1 Enable 16 bit ADC Bit1 RVS 0 ADC Reference Voltage Selection bit 0 Selection ADC as normal operation from X X 1 Selection ADC as VDD voltage detect Bit2 RVS 1 ADC Reference Voltage Selection bit 1 0 Selection ADC Reference voltage from External reference R R 1 Selection ADC Reference voltage from Internal reference Bit3 IRVS Internal Reference Voltage Selection 0 Internal Reference Voltage V REF REF is AVE 0 133 When AVE 3 0V V REF REF 0 4V 1 Internal Reference Volt
54. 128 Bit 3 TC1X8 TC1 internal clock source control bit 0 TC1 internal clock source is Fcpu TC1RATE is from Fcpu 2 Fcpu 256 1 TC1 internal clock source is Fosc TC1RATE is from Fosc 1 Fosc 128 Bit 6 4 110 fcpu 4 111 fcpu 2 Bit 7 TOENB TO counter control bit 0 Disable TO timer 1 Enable TO timer SONiX TECHNOLOGY CO LTD TORATE 2 0 TO internal clock select bits 000 fcpu 256 001 fcpu 128 Page 85 Preliminary Version 0 4 N y SONIX 8 3 4 TCOC COUNTING REGISTER TCOC is an 8 bit counter register for TCO interval time control SNSPI919 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC ODBH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TCOC TCOC7 TCOC6 TCOC5 TCOC4 TCOC3 TCOC2 TCOC1 TCOCO Read Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 The equation of TCOC initial value is as following TCOC initial value 256 TCO interrupt interval time input clock TCOC valid TCOC value 0 Ox00 0xFF 00000000b 11111111b Fcpu 2 Fcpu 256 1 Fosc 1 0x00 OxFF 00000000b 11111111b Overflow per 256 count Fosc 128 SONiX TECHNOLOGY CO LTD Page 86 Overflow per 256 count Preliminary Version 0 4 Ss NX SN8P1919 D D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC gt Example To set 10ms interval time for TCO interrupt TCO clock source is
55. 2 segment pins in the SN8P1919 The LCD scan timing is 1 4 duty and 1 2 OR 1 3 bias structure to yield 128 dots LCD driver 9 1 LCDM1 REGISTER LCDM1 register initial value xx0x 00x1 089H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LCDM1 LCDBNK LCDENB LCDBIAS P3SEG R W R W R W R W R W After Reset 0 0 0 0 Bit5 LCDBNK LCD blank control bit 0 Normal display 1 All of the LCD dots off Bit3 LCDENB LCD driver enable control bit 0 Disable 1 Enable Bit2 LCDBIAS LCD Bias Selection Bit 0 LCD Bias is 1 3 Bias 1 LCD Bias is 1 2 Bias BitO P3SEG SEG 28 31 and P3 0 P3 3 Selection 0 PIN 46 49 as LCD function Must connect VLCD1 to VLCD 1 PIN 46 49 as P3 lO function Must connect VLCD1 to VDD Note1 When SEG28 31 as LCD function Must connect VLCD1 to VLCD Note2 When SEG28 31 as P3 IO function Must connect VLCD1 to VDD Note3 In Dice form package of SN8P1919 two external pads of V1 V2 are available for fine tune the LCD bias voltage and current Note4 In 1 3 bias setting V1 1 3 VLCD V2 2 3 VLCD In 1 2 bias setting please short V1 and V2 then V1 V2 1 2VLCD Note5 Pads V1 V2 only available in Dice form RH SONiX TECHNOLOGY CO LTD Page 106 Preliminary Version 0 4 Ss NX SN8P1919 D D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC P3SEG 0 Pin46 49 as LCD SEG P3SEG 1 Pin46 49 as P3 IO Por
56. 3 XBIT2 XBIT1 XBITO Read Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 Note Please refer to the LOOK UP TABLE DESCRIPTION about X register look up table application 2 1 7 2 Y Z REGISTERS The Y and Z registers are the 8 bit buffers There are three major functions of these registers e can be used as general working registers e can be used as RAM data pointers with YZ register can be used as ROM data pointer with the MOVC instruction for look up table 084H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Y YBIT7 YBIT6 YBIT5 YBIT4 YBIT3 YBIT2 YBIT1 YBITO Read Write R W R W R W R W R W R W R W R W After reset 083H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Z ZBIT7 ZBIT6 ZBIT5 ZBIT4 ZBIT3 ZBIT2 ZBIT1 ZBITO Read Write R W R W R W R W R W R W R W R W After reset Example Uses Y Z register as the data pointer to access data in the RAM address 025H of banko BOMOV Y 00H To set RAM bank 0 for Y register BOMOV Z 25H To set location 25H for Z register BOMOV A YZ To read a data into ACC Example Uses the Y Z register as data pointer to clear the RAM data BOMOV Y 0 Y 0 bank O BOMOV Z 07FH Z 7FH the last address of the data memory area CLR_YZ_BUF CLR YZ Clear YZ to be zero DECMS Z Z 1 if Z 0 finish the routine JMP CLR_YZ_BUF Not
57. Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 L LBIT7 LBIT6 LBIT5 LBIT4 LBIT3 LBIT2 LBIT1 LBITO Read Write R W R W R W R W R W R W R W R W After reset X X X X X X X X Example If want to read a data from RAM address 20H of bank_0 it can use indirectly addressing mode to SONiX TECHNOLOGY CO LTD Preliminary Version 0 4 Page 31 O WN gt MX SN8P1919 Y Ss D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC access data as following BOMOV H 00H To set RAM bank 0 for H register BOMOV L 20H To set location 20H for L register BOMOV A HL To read a data into ACC Example Clear general purpose data memory area of bank 0 using HL register CLR H H 0 bank 0 BOMOV L 07FH L 7FH the last address of the data memory area CLR_HL_BUF CLR HL Clear HL to be zero DECMS L L 1 if L 0 finish the routine JMP CLR_HL_BUF Not zero CLR HL END_CLR End of clear general purpose data memory area of bank 0 SONiX TECHNOLOGY CO LTD Page 32 Preliminary Version 0 4 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC Ss i NX SN8P1919 2 1 7 1 X REGISTERS X register is an 8 bit buffer There are two major functions of the register e can be used as general working registers can be used as ROM data pointer with the MOVC instruction for look up table 085H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 X XBIT7 XBIT6 XBIT5 XBIT4 XBIT
58. DW 2012H Note The X Y registers will not increase automatically when Y Z registers crosses boundary from OxFF to 0x00 Therefore user must take care such situation to avoid loop up table errors If Z register is overflow Y register must be added one If Y register is overflow X register must be added one The following INC_XYZ macro shows a simple method to process X Y and Z registers automatically gt Example INC_XYZ macro INC_XYZ MACRO INCMS Z Z 1 JMP F Not overflow INCMS Y gt Y 1 JMP F Not overflow INCMS X X 1 NOP Not overflow Qu ENDM SONiX TECHNOLOGY CO LTD Page 17 Preliminary Version 0 4 Ss NX SN8P1919 Y WS D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC gt Example Modify above example by INC_XYZ macro BOMOV X TABLE1 H To set lookup table1 s high address BOMOV Y TABLE1 M _ To set lookup table1 s middle address BOMOV Z TABLE1 L To set lookup table1 s low address MOVC To lookup data R OOH ACC 35H INC_XYZ Increment the index address for next address MOVC To lookup data R 51H ACC 05H TABLE1 DW 0035H To define a word 16 bits data DW 5105H DW 2012H The other example of loop up table is to add X Y or Z index register by accumulator Please be careful if carry happen gt Example Increase Y and Z register by BOADD ADD instruction BOMOV X TABLE1 H To set lookup table1 s high address B
59. ESEL1 AVESELO AVE Voltage po gov 3 0V 1 Y gt 2 gt 3 gt 3 gt 3 gt pan OA pa po po Reserved Bit5 AVENB AVE voltage output control bit 0 Disable AVE output Voltage 1 Enable AVE output Voltage Bit6 AVDDRENB Regulator AVDDR voltage Enable control bit 0 Disable Regulator and AVDDR Output voltage 3 8V 1 Enable Regulator and AVDDR Output voltage 3 8V Bit7 ACMENB Analog Common Mode ACM voltage Enable control bit 0 Disable Analog Common Mode and ACM Output voltage 1 2V 1 Enable Analog Common Mode and ACM Output voltage 1 2V Note1 30ms delay is necessary for output voltage stabilization after set CPRENB 1 Note2 All current consumptions from AVDDR and AVE including PGIA and ADC will time 2 when Charge Pump was Enabled Note3 Before Enable Charge pump Regulator Must enable Band Gap Reference BGRENB 1 first Note4 Before Enable ACM voltage Enable AVDDR voltage first Note5 Before Enable PGIA and ADC Must enable Band Gap Reference BGRENB 1 ACM ACMENB 1 and AVDDR AVDDRENB Note6 CPR can work in slow mode but CPCKS AMPCKS register value must be reassigned x KK KK SONiX TECHNOLOGY CO LTD Page 113 Preliminary Version 0 4 SONIX SNSPI919 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC Bit CPRENB CPON and CPAUTO are Charge Pump working mode control bit By these three bits Charge Pump can be set as OFF Always ON or
60. FF 7 8125K Overflow per 256 count The Output duty of PWM is with different TC1R Duty range is from 0 256 255 256 oO 1 12800 254 255 0 1 12800 254 255 TC1 Clock i i i TC1R 00H l Low l i High i TC1R 01H_ Law i High j i l TC1R 80H Low i i High l l TC1R FFH i Low i SONiX TECHNOLOGY CO LTD Page 103 Preliminary Version 0 4 Ss NX SN8P1919 D D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 8 6 2 TC1IRQ AND PWM DUTY In PWM mode the frequency of TC1IRQ is depended on PWM duty range From following diagram the TC1IRQ frequency is related with PWM duty TC1 Overflow TC1IRQ 1 OxFF TC1C Value 0x00 PWM1 Output Duty Range 0 255 8 6 3 PWM PROGRAM EXAMPLE gt Example Setup PWM1 output from TC1 to PWM1OUT P5 3 The external high speed oscillator clock is 4MHz Fcpu Fosc 4 The duty of PWM is 30 256 The PWM frequency is about 1KHz The PWM clock source is from external oscillator clock TC1 rate is Fcpu 4 The TC1RATE2 TC1RATE1 110 TC1C TC1R 30 MOV A 01100000B BOMOV TC1M A Set the TC1 rate to Fcpu 4 MOV A 30 Set the PWM duty to 30 256 BOMOV TC1C A BOMOV TCAR A BOBSET FPWM10UT Enable PWM1 output to P5 3 and disable P5 3 I O function BOBSET FTC1ENB Enable TC1 timer Note The TC1R is write only register Don t process them using INCMS DECMS instruction
61. Fcpu TCOKS 0 TCOX8 0 and no PWM output PWMO lt 0 High clock is external 4MHz Fcpu Fosc 4 Select TCORATE 010 Fcpu 64 TCOC initial value N TCO interrupt interval time input clock 256 10ms 4MHz 4 64 256 10 2 4 106 4 64 100 64H The basic timer table interval time of TCO TCOX8 0 TCORATE TeocLOCK One step max 256 One step max 256 31250 us 15625 us 7812 5 us 3906 25 us 1953 125 us Fosc 128 Fosc 64 SONiX TECHNOLOGY CO LTD Page 87 Preliminary Version 0 4 Ss NX SN8P1919 D D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 8 3 5 TCOR AUTO LOAD REGISTER TCO timer is with auto load function controlled by ALOADO bit of TCOM When TCOC overflow occurring TCOR value will load to TCOC by system It is easy to generate an accurate time and users don t reset TCOC during interrupt service routine Note Under PWM mode auto load is enabled automatically The ALOADO bit is selecting overflow boundary OCDH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TCOR TCOR7 TCOR6 TCOR5 TCOR4 TCOR3 TCOR2 TCOR1 TCORO Read Write W W W W W W W W After reset 0 0 0 0 0 0 0 0 The equation of TCOR initial value is as following TCOR initial value 256 TCO interrupt interval time in These parameters decide TCO overflow time and valid value as follow table TCOR valid TCOR value 0 0x00 0xFF 00000000
62. Hz 25 Hz 20 Hz 25Hz 12 5 Hz 10 Hz Note 1 AC power 50 Hz noise will be filter out when output word rate 25Hz Note 2 AC power 60 Hz noise will be filter out when output word rate 20Hz Note 3 Both AC power 50 Hz and 60 Hz noise will be filter out when output word rate 10Hz Note 4 Clear Bit DRDY after got ADC data or this bit will keep High all the time Note 5 Adjust ADC clock ADCKS and bit WRSO can get suitable ADC output word rate HH HHH SONiX TECHNOLOGY CO LTD Page 128 Preliminary Version 0 4 SONIX Example Charge Pump PGIA and ADC setting Fosc 4M X tal CPREG Init CP_Enable AVDDR_Enable ACM_Enable AVE_Enable PGIA_Init PGIA_Enable ADC Init ADC_Enable QADC Wait ADC_Read XBOBSET MOV XBOMOV MOV XBOMOV XBOBSET CALL MOV XBOMOV CALL XBOBSET CALL XBOBSET CALL XBOBSET CALL MOV XBOMOV XBOMOV XBOBSET MOV XBOMOV MOV XBOMOV MOV XBOMOV XBOBSET XBOBTS1 JMP XBOBCLR XBOMOV BOMOV XBOMOV BOMOV FBGRENB A 00001011b CPCKS A A 00011100B CPM A FCPRENB Wait_200ms A 0000100b CPCKS A Wait_100ms FAVDDRENB Wait_10ms FACMENB Wait_5ms FAVENB Wait_10ms A 11110110B AMPM A A 00000100B AMPCKS A A 00h AMPCHS A FAMPENB A 00000000B ADCM A A 0236 ADCKS A A 00h DFM A FADCENB FDRDY ADC_Wait FDRDY A ADCDH Data_H
63. N8P1919 D D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC AMENDENT HISTORY Version Date Description VER 0 1 First issue VER 0 2 May 2006 1 Update spec of normal mode current 2 Update AVDDCP ACM capacitor connection 3 Update CPR enable disable AVDDCP connection 4 Remove P1 5 wake up function 5 Update application diagram VER 0 3 Sep 2006 1 Modified CPCKS AMPCKS ADCKS as write mode register 2 Limit the ADC Linear range as 28125 in ADC chapter and elec Char 3 Add TS Temperature sensor elec Spec 4 Change CPCKS as 15 6K 5 Modified ACM elec Spec 6 Modified PGIA offset of elec Spec VER 0 4 1 Add Marking Definition 2 Modify ELECTRICAL CHARACTERISTIC VER 0 5 Jan 2009 1 Modified P52 P51 description in Low Battery Detection Register 2 Modified P52 P51 circuit in Application circuit 3 Error correction NTO amp NPD as SONiX TECHNOLOGY CO LTD Page 2 Preliminary Version 0 4 Ss NX SN8P1919 Y WS D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC Table of Content AMENDENT HISTORY opa becca eevee ae ached seed aaa xen telat E 2 1 PRODUCT OVERVIEW csicssvistictesencuscesvissutssin devessviadskesenseucsavasatecintsnetdiantatsce tauetavnetaseinsaucsanniatscanauncns 6 1 1 SELECTION TABLE tds 6 1 2 MIGRATION EARTE ocur ll idad 6 LA FEATURES os smtp iaoo tonic dis 7 4 SYSTEM BLOCK DIAGRAM ssp 8 1 5 PIN ASSIGNMENT ssp iii 9 16 PINDESCRIPTIONS insta As 10
64. NKS3 RBNKS2 RBNKS1 RBNKSO R W RBANK _ io toons rooms poses en icon LCDBNK LCDENB_ LCDBIAS P3SEG R W LCDM1 BGRENB GS2 CHS3 092H_ AMPCKS7 AMPCKS6_ AMPCKS5 AMPCKS4 AMPCKS3 AMPCKS2 AMPCKS1 AMPCKSO gt IRVS ADCKS7 ADCKS6 ADCKS5 ADCKS4 ADCKS3 ACMENB AVDDRENB AVENB AVSEL1 AVSELO CPCKS7 CPCKS6 CPCKS5 CPCKS4 CPCKS3 ADCB7 ADCB6 ADCB5 ADCB4 ADCB3 ADCB15 ADCB14 ADCB13 ADCB12 ADCB11 O9AH LBTO P510 LBTENB RW LBTrM_ OBFH PEDGEN PooG1 Poco Rw PEDGE ocon J gt Phaw Pisw prw Piw Piow w Piw ociH SC PaM Pi4M P413M Prm Prim P10M RW PiM_ oc2H RM Pm rRwpem ocsH PaM P32M_ Pam P30m RW pP3m TCIRQ TCOIRQ TORQ POWRQ POOIRQ RW INTRQ TCHEN TCOIEN TOIEN f PO1IEN POOIEN R W INTEN TOR OCDH TCOR7 TCOR6 TCOR5 TCOR4 TCOR3 TCOR2 TCOR1 TCORO W TCOR PC7 f Pe cts Peio Pcs Pes OT RW IPCH A O SO A A E A o p PS Pa Pt P2 Pa Pio rw E le MA Es o_o O a Po ew P57 TOENS TORATE2 TORATET TORATEO Toc7 toce tocs toca Toca toc2 Toci Toco Rw toc ODAH TCOENB TCORATE2 TEA AIE TCOR ATEO 7 ALOADO Peares TCOM ODBH TCOC7 TCOC6 TCOC5 TCOC4 TCOC3 TCOC2 TCOCA TCOCO R W TCOC ODCH
65. OADO Enable TCO auto reload function or BOBSET FALOADO Disable TCO auto reload function pa Set TCO interrupt interval time TCOOUT Buzzer frequency or PWM duty cycle Set TCO interrupt interval time TCOOUT Buzzer frequency or PWM duty MOV A 7FH TCOC and TCOR value is decided by TCO mode BOMOV TCOC A Set TCOC value BOMOV TCOR A Set TCOR value under auto reload mode or PWM mode SONiX TECHNOLOGY CO LTD Page 90 Preliminary Version 0 4 SONIX Set TCO timer function mode or or or E BOBSET BOBSET BOBSET BOBSET Enable TCO timer BOBSET FTCOIEN FTCOOUT FPWMOOUT FTCOGN FTCOENB SONiX TECHNOLOGY CO LTD SNSP1I919 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC Enable TCO interrupt function Enable TCOOUT Buzzer function Enable PWM function Enable TCO green mode wake up function Enable TCO timer Page 91 Preliminary Version 0 4 Ss WN NX SN8P1919 Y wy D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 8 4 TIMER COUNTER 1 TC1 8 4 1 OVERVIEW The TC1 is an 8 bit binary up counting timer TC1 clock source came from internal clock for counting a precision time The internal clock source is from Fcpu or Fosc controlled by TC1X8 flag to get faster clock source Fosc If TC1 timer occurs an overflow it will continue counting and issue a time out signal to trigger TC1 interrupt to request interrupt servi
66. OBTSO FPOOIRQ Check POOIRQ JMP INTPOO INTPO1CHK Check INT1 interrupt request BOBTS1 FPO1IEN Check PO1IEN JMP INTTOCHK Jump check to next interrupt BOBTSO FPO1IRQ Check PO1IRQ JMP INTPO1 INTTOCHK Check TO interrupt request BOBTS1 FTOIEN Check TOIEN JMP INTTCOCHK Jump check to next interrupt BOBTSO FTOIRQ Check TOIRQ JMP INTTO Jump to TO interrupt service routine INTTCOCHK Check TCO interrupt request BOBTS1 FTCOIEN Check TCOIEN JMP INTTC1CHK Jump check to next interrupt BOBTSO FTCOIRQ Check TCOIRQ JMP INTTCO Jump to TCO interrupt service routine INTTC1CHK Check T1 interrupt request BOBTS1 FTC1IEN Check TC1IEN JMP INT_EXIT Jump check to next interrupt BOBTSO FTC1IRQ Check TC1IRQ JMP INTTC1 Jump to TC1 interrupt service routine INT_EXIT Pop routine to load ACC and PFLAG from buffers RETI Exit interrupt vector SONiX TECHNOLOGY CO LTD Page 73 Preliminary Version 0 4 Ss NX SN8P1919 D D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC F I O PORT 7 1 1 0 PORT MODE The port direction is programmed by PnM register All I O ports can select input or output direction OCOH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POM P11M P10M Read Write R W R W After reset 0 0 0C1H Bit 7 Bit 6 Bit 5 Bit 4
67. OMO 1 2 VLCD vss VLCD COM1 1 2 VLCD vss VLCD COM2 1 2 VLCD vss VLCD COM3 1 2 VLCD __ VSS VLCD SEGO 1010b 1 2 VLCD VSS ON OFF ON OFF ON OFF ON OFF VLCD SEGO 0101b 1 2 VLCD VSS OFF ON OFF _ ON OFF ON _OFF ON LCD Drive Waveform 1 4 duty 1 2 bias SONiX TECHNOLOGY CO LTD Page 109 Preliminary Version 0 4 SONIX LCD Clock COMO COM1 COM2 COM3 SEGO 1010b SEGO 0101b SNSP1I919 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 1 Frame 1 Frame ON OFF ON OFF ON OFF _ ON OFF lt A gt lt __ gt lt gt lt lt gt lt OFF ON EE g ON PL ON EE ON LCD Drive Waveform 1 4 duty 1 3 bias SONiX TECHNOLOGY CO LTD Page 110 VLCD 2 3 VLCD 1 3 VLCD VSS VLCD 2 3 VLCD 1 3 VLCD VSS VLCD 2 3 VLCD 1 3 VLCD VSS VLCD 2 3 VLCD 1 3 VLCD VSS VLCD 2 3 VLCD 1 3 VLCD VSS VLCD 2 3 VLCD 1 3 VLCD VSS Preliminary Version 0 4 Ss NX SN8P1919 D D E A 8 Bit Micro Controller with Charge pump Reg
68. OMOV Y TABLE1 M To set lookup table1 s middle address BOMOV Z TABLE1 L To set lookup table s low address BOMOV A BUF Z Z BUF BOADD Z A BOBTS1 FC Check the carry flag JMP GETDATA FC 0 INCMS Y FC 1 Y 1 JMP GETDATA Y is not overflow INCMS X Y is overflow X X 1 NOP GETDATA MOVC To lookup data If BUF 0 data is 0x0035 If BUF 1 data is 0x5105 If BUF 2 data is 0x2012 TABLE1 DW 0035H To define a word 16 bits data DW 5105H DW 2012H SONiX TECHNOLOGY CO LTD Page 18 Preliminary Version 0 4 Ss NX SN8P1919 D D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 2 1 2 3 JUMP TABLE DESCRIPTION The jump table operation is one of multi address jumping function Add low byte program counter PCL and ACC value to get one new PCL The new program counter PC points to a series jump instructions as a listing table It is easy to make a multi jump program depends on the value of the accumulator A When carry flag occurs after executing of ADD PCL A it will not affect PCH register Users have to check if the jump table leaps over the ROM page boundary or the listing file generated by SONIX assembly software If the jump table leaps over the ROM page boundary e g from xxFFH to xx00H move the jump table to the top of next program memory page xx00H Here one page mean 256 words Note Program counter can t carry from PCL to PCH when PCL is ove
69. P1919 S NS a X 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 2 1 5 4 ACCUMULATOR The ACC is an 8 bit data register responsible for transferring or manipulating data between ALU and data memory If the result of operating is zero Z or there is carry C or DC occurrence then these flags will be set to PFLAG register ACC is not in data memory RAM so ACC can t be access by BOMOV instruction during the instant addressing mode gt Example Read and write ACC value Read ACC data and store in BUF data memory MOV BUF A Write a immediate data into ACC MOV A 0FH Write ACC data from BUF data memory MOV A BUF The system doesn t store ACC and PFLAG value when interrupt executed ACC and PFLAG data must be saved to other data memories PUSH POP save and load 0x80 0x87 system registers data into buffers Users have to save ACC data by program gt Example Protect ACC and working registers DATA ACCBUF DS 1 Define ACCBUF for store ACC data CODE INT_SERVICE BOXCH A ACCBUF Save ACC to buffer PUSH Save PFLAG and working registers to buffer POP Load PFLAG and working registers form buffers BOXCH A ACCBUF Load ACC form buffer RETI Exit interrupt service vector Note To save and re load ACC data users must use BOXCH instruction or else the PFLAG Register might be modified by ACC operation SONiX TECHNOLOGY CO LTD Page 27 Preliminary
70. Ss NX SN8P1919 D ce D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC SN8P1919 USER S MANUAL Preliminary Specification Version 0 5 SONIiX 8 Bit Micro Controller SONIX reserves the right to make change without further notice to any products herein to improve reliability function or design SONIX does not assume any liability arising out of the application or use of any product or circuit described herein neither does it convey any license under its patent rights nor the rights of others SONIX products are not designed intended or authorized for us as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the SONIX product could create a situation where personal injury or death may occur Should Buyer purchase or use SONIX products for any such unintended or unauthorized application Buyer shall indemnify and hold SONIX and its officers employees subsidiaries affiliates and distributors harmless against all claims cost damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of the part SONiX TECHNOLOGY CO LTD Page 1 Preliminary Version 0 4 Ss NX S
71. TC1 interrupt interval time input clock These parameters decide TC1 overflow time and valid value as follow table TC1C valid TC1C value 0 Fcpu 2 Fcpu 256 Ox00 OxFF 00000000b 11111111b Overflow per 256 count See Ox00 OxFF 00000000b 11111111b Overflow per 256 count gt Example To set 10ms interval time for TC1 interrupt TC1 clock source is Fcpu and no PWM output PWM1 0 High clock is external 4MHz Fcpu Fosc 4 Select TC1RATE 010 Fcpu 64 TC1C initial value 256 TC1 interrupt interval time input clock 256 10ms 4MHz 4 64 256 10 2 4 106 4 64 100 64H SONiX TECHNOLOGY CO LTD Page 94 Preliminary Version 0 4 Ss NX SN8P1919 D D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC The basic timer table interval time of TC1 TC1X8 0 TCACLOCK Low speed mode Fepu 32768Hz 4 Fepu 128 4000 ms High speed mode Fcpu 4MHz 4 Low speed mode Fcpu 32768Hz 4 Max overflow interval One step max 256 Max overflow interval One step max 256 Fosc 128 Fosc 8 0512ms_ 2us 625ms 488 281us 1 us Fosc 4 0 256 ms tus 31 25 ms 244 141 us 0 128 ms 15 625 ms 122 07 us 111 Fosc 1 0 064 ms 0 25 us 7 813 ms 61 035 us SONiX TECHNOLOGY CO LTD Page 95 Preliminary Version 0 4 Ss NX SN8P1919 D D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 8 4 5 TC1R AUTO LOAD REGISTER TC1 timer is with auto l
72. TCOR the PWM will output logic High when TCOC TCOR the PWM will output logic Low If TCOC is changed in certain period the PWM duty will change immediately If TCOR is fixed all the time the PWM waveform is also the same TCOC TCOR TCOC overflow and TCOIRQ set v v v v v OxFF TCOC Value 0x00 PWMO Output 1 2 3 4 5 6 7 Period lt gt lt gt lt gt a Above diagram is shown the waveform with fixed TCOR In every TCOC overflow PWM output High when TCOC TCOR PWM output Low Note Setting PWM duty in program processing must be at the new cycle start SONiX TECHNOLOGY CO LTD Page 102 Preliminary Version 0 4 Ss NX SN8P1919 D D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 8 6 PWM1 MODE 8 6 1 OVERVIEW PWM function is generated by TC1 timer counter and output the PWM signal to PWM1OUT pin P5 3 The 8 bit counter counts modulus 256 bits The value of the 8 bit counter TC1C is compared to the contents of the reference register TC1R When the reference register value TC1R is equal to the counter value TC1C the PWM output goes low When the counter reaches zero the PWM output is forced high The ratio duty of the PWM1 output is TC1R 256 MAX PWM PWM duty range TC1C valid value TC1R valid bits value Frequency Remark Fcpu 4MHz 0 256 255 256 0x00 0xFF 0x00 Ox
73. Version 0 4 Ss NX SN8P1919 D D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 2 1 6 PROGRAM FLAG The PFLAG register contains the arithmetic status of ALU operation system reset status and LVD detecting status NTO NPD bits indicate system reset status including power on reset LVD reset reset by external pin active and watchdog reset C DC Z bits indicate the result status of ALU operation 086H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PFLAG NTO NPD C DC Z Read Write R W R W R W R W R W After reset 0 0 0 Bit 7 6 NTO NPD Reset status flag NTO NPD Reset Status 0 O Watch dog time out 0 1 Reserved 1 O Reset by LVD 1 1 Reset by external Reset Pin Bit 2 C Carry flag 1 Addition with carry subtraction without borrowing rotation with shifting out logic 1 comparison result 20 0 Addition without carry subtraction with borrowing signal rotation with shifting out logic O comparison result lt 0 Bit 1 DC Decimal carry flag 1 Addition with carry from low nibble subtraction without borrow from high nibble 0 Addition without carry from low nibble subtraction with borrow from high nibble Bit O Z Zero flag 1 The result of an arithmetic logic branch operation is zero O The result of an arithmetic logic branch operation is not zero Note Refer to inst
74. X SN8P1919 D D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 6 3 INTRQ INTERRUPT REQUEST REGISTER INTRQ is the interrupt request flag register The register includes all interrupt request indication flags Each one of the interrupt requests occurs the bit of the INTRQ register would be set 1 The INTRQ value needs to be clear by programming after detecting the flag In the interrupt vector of program users know the any interrupt requests occurring by the register and do the routine corresponding of the interrupt request 0C8H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O INTRQ TC1IRQ TCOIRQ TOIRQ PO1IRQ POOIRQ Read Write R W R W R W R W R W After reset 0 0 0 0 0 Bit 0 POOIRQ External P0 0 interrupt INTO request flag 0 None INTO interrupt request 1 INTO interrupt request Bit 1 PO1IRQ External P0 1 interrupt INT 1 request flag 0 None INT1 interrupt request 1 INT1 interrupt request Bit 4 TOIRQ TO timer interrupt request flag 0 None TO interrupt request 1 TO interrupt request Bit 5 TCOIRQ TCO timer interrupt request flag 0 None TCO interrupt request 1 TCO interrupt request Bit 6 TC1IRQ TC1 timer interrupt request flag 0 None TC1 interrupt request 1 TC1 interrupt request 6 4 GIE GLOBAL INTERRUPT OPERATION GIE is the global interrupt control bit All interrupts start work after the GIE 1 It is nece
75. X does not assume any liability arising out of the application or use of any product or circuit described herein neither does it convey any license under its patent rights nor the rights of others SONIX products are not designed intended or authorized for us as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the SONIX product could create a situation where personal injury or death may occur Should Buyer purchase or use SONIX products for any such unintended or unauthorized application Buyer shall indemnify and hold SONIX and its officers employees subsidiaries affiliates and distributors harmless against all claims cost damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of the part Main Office Address 9F NO 8 Hsien Cheng 5th St Chupei City Hsinchu Taiwan R O C Tel 886 3 551 0520 Fax 886 3 551 0523 Taipei Office Address 15F 2 NO 171 Song Ted Road Taipei Taiwan R O C Tel 886 2 2759 1980 Fax 886 2 2759 8180 Hong Kong Office Address Flat 3 9 F Energy Plaza 92 Granville Road Tsimshatsui East Kowloon Tel 852 2723 8086 Fax 852 2723 9179 Technical Support by Ema
76. _Buf A A ADCDL Data_L_Buf A SONiX TECHNOLOGY CO LTD SNSPI919 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC Enable Band Gap Reference voltage Set CPCKS as slowest clock to void VDD dropping Set AVE 3 0V CP as Auto mode and Disable AVDDR AVE ACM voltage before enable Charge pump Enable Charge Pump Delay 200ms for Charge Pump Stabilize Set CPCKS as 15 6K for 10mA current loading Delay 100ms for Voltage Stabilize Enable AVDDR Voltage 3 8V Delay 10ms for AVDDR Voltage Stabilize Enable ACM Voltage 1 2v Delay 5ms for ACM Voltage Stabilize Enable AVE Voltage 3 0V 1 5V Delay 10ms for AVE Voltage Stabilize Enable Band Gap Set FDS 11 CHPENB 1 PGIA Gain 200 Set AMPCKS 100 for PGIA working clock 1 9K 4M X tal Selected PGIA differential input channel Al1 Al1 Enable PGIA function V X X Output V Al1 Al1 x 200 Selection ADC Reference voltage V R R Set ADCKS 236 for ADC working clock 100K 4M X tal Set ADC as continuous mode and WRSO 0 ADC conversion rate 25 Hz Enable ADC function Check ADC output new data or not Wait for Bit DRDY 1 Output ADC conversion word Move ADC conversion High byte to Data Buffer Move ADC conversion Low byte to Data Buffer Page 129 Preliminary Version 0 4 SONIX SNSP1I919 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC
77. age V REF REF is AVE 0 266 When AVE 3 0V V REF REF 0 8V Bit4 Always Set to 0 invs RVS1 RVSO AVESEL 1 0 ee Voltage AD Channel Input ENE ADCIN ADCIN LX 0 oa 11 CAN 10 Teee on om 11 AVE 3 0V 10 NEON lae an Oo om oT EREE mee oa Mm External Ref Voltage VOX lt 04V X VOX lt 04V lt 0 4V V X X lt 0 32V O V0G X lt 08V X O V0G X lt 08V lt 0 8V vV MENE X lt 0 MENE V X K lt 0 4V K Ref Voltage IAVE VERSO VERSO Sea Coan aves 30V VDD 3 16 VDD 2 16 ro 41 1 064V 032V yr A AVE 2 4V 0s6v_ 032V Note1 The ADC conversion data is combined with ADCDH and ADCDL register in 2 s compliment with Note2 The Internal Reference Voltage is divided from AVE so the voltage will follow the changing with sign bit numerical format and Bit ADCB15 is the sign bit of ADC data Refer to following formula to calculate ADC conversion data value AVE 3 0V 2 4V 1 5V which selected by AVESEL 1 0 SONiX TECHNOLOGY CO LTD Page 123 Preliminary Version 0 4 Ss NX SN8P1919 D D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC ADCIN ADCIN REF REF ADCIN ADCIN REF REF Note The internal reference voltage are generated from AVE voltage X 31250 ADCIN gt ADCIN gt ADCConversionData ADCIN lt ADCIN
78. aked up from power down mode MCU waits for 2048 external high speed oscillator clocks as the wakeup time to stable the oscillator circuit After the wakeup time the system goes into the normal mode Note Wakeup from green mode is no wakeup time because the clock doesn t stop in green mode The value of the wakeup time is as the following The Wakeup time 1 Fosc 2048 sec high clock start up time Note The high clock start up time is depended on the VDD and oscillator type of high clock Example In power down mode sleep mode the system is waked up After the wakeup time the system goes into normal mode The wakeup time is as the following The wakeup time 1 Fosc 2048 0 512 ms Fosc 4MHz The total wakeup time 0 512 ms oscillator start up time SONiX TECHNOLOGY CO LTD Page 60 Preliminary Version 0 4 Ss WN NX SN8P1919 Y WS bs E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 5 2 1 P1W WAKEUP CONTROL REGISTER Under power down mode sleep mode and green mode the I O ports with wakeup function are able to wake the system up to normal mode The Port 0 and Port 1 have wakeup function Port 0 wakeup function always enables but the Port 1 is controlled by the P1W register OCOH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P1W P14W P13W P12W P11W P10W Read Write W W W W W After reset 0 0 0 0 0
79. ample An operation of watchdog timer is as following To clear the watchdog timer counter in the top of the main routine of the program Main Check I O de Check RAM Err JMP 1O or RAM error Program jump here and don t Clear watchdog Wait watchdog timer overflow to reset IC Correct 1 O and RAM are correct Clear watchdog timer and execute program BOBSET FWDRST Only one clearing watchdog timer of whole program CALL SUB1 CALL SUB2 JMP MAIN SONiX TECHNOLOGY CO LTD Page 78 Preliminary Version 0 4 Ss NX SN8P1919 D D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 8 2 TIMER 0 TO 8 2 1 OVERVIEW The TO is an 8 bit binary up timer and event counter If TO timer occurs an overflow from FFH to 00H it will continue counting and issue a time out signal to trigger TO interrupt to request interrupt service The main purposes of the TO timer is as following 8 bit programmable up counting timer Generates interrupts at specific time intervals based on the selected clock frequency RTC timer Generates interrupts at real time intervals based on the selected clock source RTC function is only available in TOTB 1 Green mode wakeup function TO can be green mode wake up time as TOENB 1 System will be wake up by TO time out TO Rate Fcpu 2 Fcpu 256 TOENB Internal Data Bus re TOTB Pepu gt gt TOC 8 Bit Binary Up Co
80. amplifier PGIA with selectable gains of 1x 12 5x 50x 100x and 200x in the ADC to accommodate these applications 10 2 ANALOG INPUT Following diagram illustrates a block diagram of the PGIA and ADC module The front end consists of a multiplexer for input channel selection a PGIA Programmable Gain Instrumentation Amplifier and the A 2 ADC modulator To obtain maximum range of ADC output the ADC maximum input signal voltage V X X should be close to but can t over the reference voltage V R R Choosing a suitable reference voltage and a suitable gain of PGIA can reach this purpose The relative control bits are RVS 1 0 bits Reference Voltage Selection in ADCM register and GS 2 0 bits Gain Selection in AMPM register AMPCHSI 3 0 Al1 Al1 Rao AO Al2 a 16 bit PGIA ADC X Al2 1x 200x T 3 16 VDD ADC Ref AO Voltage emperature 2 16 VDD Sensor Rao L ADCM 7 0 Wo ollo Input Short Amro 3 z Block Diagram of PGIA ADC module Note 1 The low pass filter Rao Rao and Cx will filter out chopper frequency of PGIA Note 2 The recommend value of Cx is 0 1 u F Rao Rao 100K This capacitor needs to place as close chip as possible SONiX TECHNOLOGY CO LTD Page 112 Prelimin
81. arge pump clock as 1011 to avoid VDD dropped Note2 In general application CP working clock is about 13K 15K Hz in normal mode 2K Hz in slow mode External Low Clock mode Note3 The Faster of Charge pump clock AVE can load more current Note4 In slow mode or Green mode Set CPCKS 0x00 for AVDDR AVE ACM can supply the max current SONiX TECHNOLOGY CO LTD Page 115 Preliminary Version 0 4 Ss NX SN8P1919 N D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC Example Charge Pump setting Fosc 4M X tal CPREG_Init XBOBSET FBGRENB Enable Band Gap Reference voltage MOV A 00001011b XBOMOV CPCKS A Set CPCKS as slowest clock to void VDD dropping MOV A 00011100B XBOMOV CPM A Set AVE 3 0V CP as Auto mode and Disable AVDDR AVE ACM voltage before enable Charge pump CP_Enable XBOBSET FCPRENB Enable Charge Pump CALL Wait_200ms Delay 200ms for Charge Pump Stabilize MOV A 0000100b XBOMOV CPCKS A Set CPCKS as 15 6K for 10mA current loading CALL Wait_100ms Delay 100ms for Voltage Stabilize AVDDR_Enable XBOBSET FAVDDRENB Enable AVDDR Voltage 3 8V CALL Wait_10ms Delay 10ms for AVDDR Voltage Stabilize ACM_Enable XBOBSET FACMENB Enable ACM Voltage 1 2v CALL Wait_5ms Delay 5ms for ACM Voltage Stabilize AVE_Enable XBOBSET FAVENB Enable AVE Voltage 3 0V 2 4V 1 5V CALL Wait_10ms Delay 10ms for AVE Voltage Stabilize
82. ary Version 0 4 Ss NX SN8P1919 D D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 10 3 Voltage Charge Pump Regulator CPR SN8P1919 is built in a CPR which can provide a stable 3 8V pin AVDDR and 3 0V 2 4V 1 5V pin AVE with maximum 10mA current driving capacity Register CPM can enable or disable CPR and controls CPR working mode another register CPCKS sets CPR working clock to 4KHz Because the power of PGIA and ADC is come from AVDDR turn on AVDDR AVDDRENB 1 first before enabling PGIA and ADC The AVDDR voltage was regulated from AVDDCP In addition the CP will need at least 10ms for output voltage stabilization after set CPRENB to high 10 3 1 CPM Charge Pump Mode Register 095H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CPM ACMENB AVDDRENB AVENB AVESEL1 AVESELO CPAUTO CPON CPRENB R W R W R W R W R W R W R W R W R W After Reset 0 0 0 0 0 0 0 0 Bito CPRENB Charge Pump Regulator function enable control bit 0 Disable charge pump and regulator 1 Enable charge pump and regular Bit1 CPON Change Pump always ON function control bit CPRENB must 1 0 Charge Pump On Off controlled by bit CPAUTO 1 Always turn ON the charge pump regulator Bit2 CPAUTO Charge Pump Auto Mode function control bit 0 Disable charge pump auto mode 1 Enable charge pump auto mode Bit3 4 AVESEL 1 0 AVE voltage selection control bit AV
83. ation Note 1 Processing OSCM register needs to add extra one cycle 2 If branch condition is true then S 1 otherwise S 0 SONiX TECHNOLOGY CO LTD Page 136 Preliminary Version 0 4 Ss NX SN8P1919 D D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 1 3 Development Tools 13 1 Development Tool Version 13 1 1 ICE In circuit emulation e SNS8ICE 1K S8KD 2 Full function emulates SN8P1919 series SN8ICE1K ICE emulation notice Operation voltage of ICE 3 0V 5 0V m Recommend maximum emulation speed at 5V 4 MIPS e g 16MHZ crystal and Fcpu Fhosc 4 m Use SN8P1919 EV KIT to emulation Analog Function 13 1 2 OTP Writer e Easy Writer V1 0 OTP programming is controlled by ICE without firmware upgrade suffers Please refer easy Note S8ICE2K doesn t support SN8P1919 serial emulation writer user manual for detailed information o MP EZ Writer V1 0 Stand alone operation to support SN8P1919 mass production Note Writer 3 0 doesn t support SN8P1919 OTP programming 13 1 3 IDE Integrated Development Environment SONIX 8 bit MCU integrated development environment include Assembler ICE debugger and OTP writer software e For SN8ICE 1K SN8IDE 1 99V or later e For Easy Writer and MP Easy Writer SN8IDE 1 99V or later e M2IDE V1 0X doesn t support SN8P1919 SONiX TECHNOLOGY CO LTD Page 137 Preliminary Version 0 4 Ss NS NX SN8P1919 Y WS D E A 8 Bit Mic
84. b 11111111b Fcpu 2 Fcpu 256 Fosc 1 sad 28 0x00 OxFF 00000000b 11111111b gt Example To set 10ms interval time for TCO interrupt TCO clock source is Fcpu TCOX8 0 and no PWM output PWMO 0 High clock is external 4MHz Fcpu Fosc 4 Select TCORATE 010 Fcpu 64 TCOR initial value 256 TCO interrupt interval time input clock 256 10ms 4MHz 4 64 256 10 2 4 106 4 64 100 64H SONiX TECHNOLOGY CO LTD Page 88 Preliminary Version 0 4 Ss NX SN8P1919 D D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 8 3 6 TCO CLOCK FREQUENCY OUTPUT BUZZER Buzzer output TCOOUT is from TCO timer counter frequency output function By setting the TCO clock frequency the clock signal is output to P5 4 and the P5 4 general purpose l O function is auto disable The TCOOUT frequency is divided by 2 from TCO interval time TCOOUT frequency is 1 2 TCO frequency The TCO clock has many combinations and easily to make difference frequency The TCOOUT frequency waveform is as following TCO Overflow Clock TCOOUT Buzzer Output Clock gt Example Setup TCOOUT output from TCO to TCOOUT P5 4 The external high speed clock is 4MHz The TCOOUT frequency is 0 5KHz Because the TCOOUT signal is divided by 2 set the TCO clock to 1KHz The TCO clock source is from external oscillator clock TOC rate is Fcpu 4 The TCORATE2 TCORATE1 110
85. ble in RTC mode The TO interval time is fixed at 0 5 sec SONiX TECHNOLOGY CO LTD Page 80 Preliminary Version 0 4 Ss NX SN8P1919 D D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 8 2 3 TOC COUNTING REGISTER TOC is an 8 bit counter register for TO interval time control OD9H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TOC TOC7 TOC6 TOC5 TOC4 TOC3 TOC2 TOC1 TOCO Read Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 The equation of TOC initial value is as following TOC initial value 256 TO interrupt interval time input clock gt Example To set 10ms interval time for TO interrupt High clock is external 4MHz Fcpu Fosc 4 Select TORATE 010 Fcpu 64 TOC initial value 256 TO interrupt interval time input clock 256 10ms 4MHz 4 64 256 10 2 4 108 4 64 100 64H The basic timer table interval time of TO TORATE TOCLOCK High speed mode Fcpu 4MHz 4 Low speed mode Fcpu 32768Hz 4 Max overflow interval One step max 256 Max overflow interval One step max 256 Fcpu 256 65 536 ms 8000 ms 31250 us Fcpu 128 32 768 ms 4000 ms 15625 us Fcpu 64 16 384 ms 2000 ms 7812 5 us 500 ms 250 ms 125 ms 62 5 ms Fcpu 32 8 192 ms 1000 ms 3906 25 us gt Note TOC is not available in RTC mode The TO interval time is fixed at 0 5 sec
86. both read only registers gt Note2 The ADC conversion data is combined with ADCDH ADCDL in 2 s compliment with sign bit numerical format and Bit ADCB15 is the sign bit of ADC data ADCB15 0 means data is Positive value ADCB15 1 means data is Negative value VV V ADC output must keep inside this range Note3 The Positive Full Scale Output value of ADC conversion is 0x7A12 Note4 The Negative Full Scale Output value of ADC conversion is Ox85EE Note5 Because of the ADC design limitation the ADC Linear range is 28125 28125 decimal The MAX ADC conversion data Decimal Value 2 s compliment Hexadecimal 0x7A12 31250 0x4000 16384 0x1000 4096 0x0002 2 0x0001 1 0x0000 0 OxFFFF 1 OxFFFE 2 OxF000 4096 0xC000 16384 Ox85EE 31250 SONiX TECHNOLOGY CO LTD Page 127 Preliminary Version 0 4 SONIX 10 5 5 DFM ADC Digital Filter Mode Register SNSPI919 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 097H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DFM WRSO DRDY R W R W After Reset 0 0 Bito DRDY ADC Data Ready Bit 1 ADC output update new conversion data to ADCDH ADCDL 0 ADCDH ADCDL conversion data are not ready Bit2 WRS 1 0 ADC output Word Rate Selection Output Word Rate ADC clock 200K ADC clock 100K ADC clock 80K 50
87. buffer are CALL instruction and interrupt service Under each condition the STKP decreases and points to the next available stack location The stack buffer stores the program counter about the op code address The Stack Save operation is as the following table Stack Buffer a Low Byte sail Pee ee ed Free pa AA o sron STKOL pa 1 o 4 STKIH s Ea o sien one 24 o 1 1 SIKH STKL A I STKAL Y ee STKSL STK6H STK6L Stack Over error There are Stack Restore operations correspond to each push operation to restore the program counter PC The RETI instruction uses for interrupt service routine The RET instruction is for CALL instruction When a pop operation occurs the STKP is incremented and points to the next free stack location The stack buffer restores the last program counter PC to the program counter registers The Stack Restore operation is as the following table STKP Register Stack Buffer head peice evel STKPB2 STKPBI_ STRPBO High Byte Low Byte PERRA ren STK7L STK6H STK6L STK5H STK5L STK4H STK4L o sma sma a f smm se o smo smo 71 Fe Fe a STK3H STK3L SONiX TECHNOLOGY CO LTD Page 39 Preliminary Version 0 4 O NX SN8P1919 D D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 3 RESET 3 1 OVERVIEW The system would be reset in three conditions as following Power on reset Watchdog reset Brown out r
88. ce TC1 overflow time is OXFF to 0X00 normally Under PWM mode TC1 overflow is decided by PWM cycle controlled by ALOAD1 and TC1OUT bits The main purposes of the TC1 timer is as following 8 bit programmable up counting timer Generates interrupts at specific time intervals based on the selected clock frequency Buzzer output PWM output TC10UT Internal P5 3 I O Circuit lt ___ ALOAD1 Buzzer Auto Reload 10412 lx A a P5 3 TC1R Reload oE ALOAD1 TC10UT TC1 Rate Data Buffer Fcpu 2 Fcpu 256 TC1X8 R PWM10UT Compare PWM Fopu TC1ENB E gt S gt Load gt Fosc gt TC1C gt 8 Bit Binary Up TC1 Time Out Counting Counter TC1 Rate Fosc 1 Fosc 128 CPUMO 1 SONiX TECHNOLOGY CO LTD Page 92 Preliminary Version 0 4 SONIX 8 4 2 TC1M MODE REGISTER SNSPI919 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC ODCH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TC1M TC1ENB TCitrate2 TClrate1 TC1rateO ALOAD1 TC1OUT PWM10UT Read Write R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 Bit O PWM10UT PWM output control bit 0 Disable PWM output 1 Enable PWM output PWM duty controlled by TC1O0UT ALOAD1 bits Bit 1 TC1OUT TC1 time out toggle signal output control bit Only valid whe
89. citor i i Negative pin to ACM Negative pin to GND Table 1 2 SN8P1919 Migration Table SONiX TECHNOLOGY CO LTD Page 6 Preliminary Version 0 4 SNSPI919 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC SONIX 1 3 FEATURES Memory configuration OTP ROM size 6K 16 bits RAM size 256 8 bits bank 0 bank 1 8 levels stack buffer LCD RAM size 4 32 bits VO pin configuration Input only PO Bi directional P1 P2 P3 P5 Wakeup PO P1 Pull up resisters PO P1 P2 P3 P5 External interrupt PO Powerful instructions Four clocks per instruction cycle All instructions are one word length Most of instructions are 1 cycle only Maximum instruction cycle is 2 JMP instruction jumps to all ROM area All ROM area look up table function MOVC Programmable gain instrumentation amplifier Gain option 1x 12 5x 50x 100x 200x Build In PGIA Temperature Compensation Resistance 16 bit Delta Sigma ADC with 14 bit noise free Three ADC channel configurations Two fully differential channel One differential and Two single ended channels Four single ended channels SONiX TECHNOLOGY CO LTD Five interrupt sources Three internal interrupts TO TCO TC1 One external interrupts INTO INT1 Single power supply 2 4V 5 5V On chip watchdog timer On chip charge pump regulator with 3 8V voltage output and 10mA driven current On chip regulator with 3 0V 2 4V 1 5V
90. clock is from internal 16MHz RC type oscillator and XIN XOUT pins are general purpose I O pins e IHRC High clock is internal 16MHz oscillator RC type XIN XOUT pins are general purpose l O pins 4 4 2 EXTERNAL HIGH CLOCK External high clock includes three modules Crystal Ceramic RC and external clock signal The high clock oscillator module is controlled by High_Clk code option The start up time of crystal ceramic and RC type oscillator is different RC type oscillator s start up time is very short but the crystal s is longer The oscillator start up time decides reset time length 4MHz Crystal 4MHz Ceramic SONiX TECHNOLOGY CO LTD Page 52 Preliminary Version 0 4 Ss NX SN8P1919 D D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 4 4 2 1 CRYSTAL CERAMIC Crystal Ceramic devices are driven by XIN XOUT pins For high normal low frequency the driving currents are different High_Clk code option supports different frequencies 12M option is for high speed ex 12MHz 4M option is for normal speed ex 4MHz XIN CRYSTAL XOUT MCU UH 20pF 20pF VDD SSA Note Connect the Crystal Ceramic and C as near as possible to the XIN XOUT VSS pins of micro controller 4 4 2 2 EXTERNAL CLOCK SIGNAL Selecting external clock signal input to be system clock is by RC option of High_Clk code option The external clock signal is input from XIN
91. cro will check the ROM boundary and move the jump table to the right position automatically The side effect of this macro maybe wastes some ROM size gt Example If jump table crosses over ROM boundary will cause errors JMP_A MACRO VAL IF 1 amp OXFFOO VAL amp OXFFOO JMP OXFF ORG OXFF ENDIF ADD PCL A ENDM Note VAL is the number of the jump table listing number gt Example JMP_A application in SONIX macro file called MACRO3 H BOMOV A BUFO BUFO is from 0 to 4 JMP_A 5 The number of the jump table listing is five JMP AOPOINT ACC 0 jump to AOPOINT JMP A1POINT ACC 1 jump to A1POINT JMP A2POINT ACC 2 jump to A2POINT JMP A3POINT ACC 3 jump to ASPOINT JMP A4POINT ACC 4 jump to A4POINT If the jump table position is across a ROM boundary OxOOFF 0x0100 the JMP_A macro will adjust the jump table routine begin from next RAM boundary 0x0100 gt Example JMP_A operation Before compiling program ROM address BOMOV A BUFO BUFO is from 0 to 4 JMP_A 5 The number of the jump table listing is five OX00FD JMP AOPOINT ACC 0 jump to AOPOINT OXOOFE JMP A1POINT ACC 1 jump to A1POINT OXOOFF JMP A2POINT ACC 2 jump to A2POINT 0X0100 JMP A3POINT ACC 3 jump to ASPOINT 0X0101 JMP A4POINT ACC 4 jump to A4POINT After compiling program ROM address BOMOV A
92. e with VDD voltage The structure can improve slight brown out reset condition Note The R2 100 ohm resistor of Simply reset circuit and Diode amp RC reset circuit is necessary to limit any current flowing into reset pin from external capacitor C in the event of reset pin breakdown due to Electrostatic Discharge ESD or Electrical Over stress EOS 3 6 3 Zener Diode Reset Circuit R1 33K ohm R3 40K ohm The zener diode reset circuit is a simple low voltage detector and can improve brown out reset condition completely Use zener voltage to be the active level When VDD voltage level is above Vz 0 7V the C terminal of the PNP transistor outputs high voltage and MCU operates normally When VDD is below Vz 0 7V the C terminal of the PNP transistor outputs low voltage and MCU is in reset mode Decide the reset detect voltage by zener specification Select the right zener voltage to conform the application SONiX TECHNOLOGY CO LTD Page 46 Preliminary Version 0 4 Ss NX SN8P1919 D D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 3 6 4 Voltage Bias Reset Circuit The voltage bias reset circuit is a low cost voltage detector and can improve brown out reset condition completely The operating voltage is not accurate as zener diode reset circuit Use R1 R2 bias voltage to be the active level When VDD voltage level is above or equal to 0 7V x R1 R2 R
93. eeescecseeceseeeseeeeneesnaeenseesees 138 7 2 1 The pin assignment of Easy and MP EZ Writer transition board SOCKet oooooocononocccconannnonn 138 7 2 2 The pin assignment of Writer V3 0 transition board SOCKet oooooococoninoconccononnnnnnnanonnnnnnanonnnnos 138 7 2 3 SNSP1919 Series Programming Pin Mapping i 139 ELECTRICAL CHARACTERISTICS 140 8 1 ABSOLUTE MAXIMUM RATING id ita 140 8 2 ELECTRICAL CHARACTERS TC 140 9 PACKAGE INFORMATION sia 143 9 1 LQFP 0 PIN ai char voll cece vege sa yawniiseun a ed one die a 143 10 MARKING DEFINITION scsnsscssssecssotasenssuvassccesesenvadysisvussevbasencseussbedsonssteavvinessontevetieneastessovanscedseaannis 144 SONiX TECHNOLOGY CO LTD Page 4 Preliminary Version 0 4 SON N SN8P1919 D D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 10010 INTRODUCTION seran 144 10 2 MARKING INDE TIFICATION SYSTEM csi 144 TOS MARKING EXAMPLE comia E T Aa Ni 145 10 4 DATECODE SYSTEM santi sd 145 SONiX TECHNOLOGY CO LTD Page 5 Preliminary Version 0 4 Ss NX SN8P1919 D D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 1 PRODUCT OVERVIEW 1 1 SELECTION TABLE Timer ADC PWM Wakeup CHIP ROM RAM Stack LCD vO SIO _ Package To TCO TC1 Bit Buzzer Pin no SN8P1908 8K 16 512 8 8 4 24 V V V 17 16 2 T7 LQFP64 SN8P1909 8K 16 512 8 8 432 V V V 20 16 2 1 T LQFP80 SN8P1919 6K 16 256 8 8 4 32 Vj V V 22 16 2
94. eliminary Version 0 4 SONIX 10 3 2 CPCKS Charge Pump Clock Register SNSPI919 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 096H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CPCKS CPCKS3 CPCKS2 CPCKS1 CPCKSO R W Ww Ww Ww W After Reset 0 0 0 0 CPCKS 3 0 register sets the Charge Pump working clock the suggestion Charge Pump clock is 13K 15K Hz Normal mode 2K Slow mode Charge Pump Clock Fepu 4 24CPCKSJ 3 0 Refer to the following table for CPCKS 3 0 register value setting in different Fosc frequency Fosc CPCKS3 CPCKS2 CPCKS1 CPCKSO 32768Hz 2M 3 58M lAMIHRC 18M 0 0 0 0 2 048K 125K 223 75K 250K 500K 0 0 0 1 NA 62 5K 111 88K 125K 250K 0 0 1 0 NA 31 25K 55 94K 62 5K 125K 0 0 1 1 NA 15 625K 27 97K 31 25K 62 5K 0 1 0 0 NA 7 8125K 13 985K 15 625K 31 25K 0 1 0 1 NA 3 90625K 6 99K 7 8125K 15 625K 0 1 1 0 NA 1 953215K 3 495K 3 90625K 7 8125K 0 1 1 1 NA 0 976K 1 75K 1 953215K 3 90625K 1 0 0 0 NA 0 488K 0 875K 0 976K 1 953215K 1 0 0 1 NA 0 244K 0 438K 0 488K 0 976K 1 0 1 0 NA 0 122K 0 219K 0 244K 0 488K 1 0 1 1 NA 0 61K 0 11K 0 122K 0 244K 1 1 0 0 NA 0 3K 0 055K 0 061K 0 122K 1 1 0 1 NA 0 15K 0 028K 0 03K 0 61K 1 1 1 0 NA 0 075K 0 014K 0 015K 0 3K 1 1 1 1 NA 0 037K 0 007K 0 008K 0 15K Note1 When enable charge pump Set Ch
95. ement and environment If the power variation is very deep violent and trigger the LVD the LVD can be the protection If the power variation can touch the LVD detect level and make system work error the LVD can t be the protection and need to other reset methods More detail LVD information is in the electrical characteristic section Watchdog reset The watchdog timer is a protection to make sure the system executes well Normally the watchdog timer would be clear at one point of program Don t clear the watchdog timer in several addresses The system executes normally and the watchdog won t reset system When the system is under dead band and the execution error the watchdog timer can t be clear by program The watchdog is continuously counting until overflow occurrence The overflow signal of watchdog timer triggers the system to reset and the system return to normal mode after reset sequence This method also can improve brown out reset condition and make sure the system to return normal mode If the system reset by watchdog and the power is still in dead band the system reset sequence won t be successful and the system stays in reset status until the power return to normal range Reduce the system executing rate If the system rate is fast and the dead band exists to reduce the system executing rate can improve the dead band The lower system rate is with lower minimum operating voltage Select the power voltage that s no dead band issue
96. en the TC1C counter overflows the TC1IRQ will be set to 1 no matter the TC1IEN is enable or disable If the TC1IEN and the trigger event TC1IRQ is set to be 1 As the result the system will execute the interrupt vector If the TC1IEN O the trigger event TC1IRQ is still set to be 1 Moreover the system won t execute interrupt vector even when the TC1IEN is set to be 1 Users need to be cautious with the operation under multi interrupt situation Example TC1 interrupt request setup BOBCLR FTC1IEN Disable TC1 interrupt service BOBCLR FTC1ENB Disable TC1 timer MOV A 20H a BOMOV TCM A Set TC1 clock Fcpu 64 MOV A 74H Set TC1C initial value 74H BOMOV TCIC A Set TC1 interval 10 ms BOBSET FTC1IEN Enable TC1 interrupt service BOBCLR FTC1IRQ Clear TC1 interrupt request flag BOBSET FTC1ENB Enable TC1 timer BOBSET FGIE Enable GIE Example TC1 interrupt service routine ORG 8 Interrupt vector JMP INT_SERVICE INT_SERVICE Push routine to save ACC and PFLAG to buffers BOBTS1 FTC1IRQ Check TC1IRQ JMP EXIT_INT TC1IRQ 0 exit interrupt vector BOBCLR FTC1IRQ Reset TC1IRQ MOV A 74H BOMOV TCIC A Reset TC1C eae TC1 interrupt service routine EXIT_INT Pop routine to load ACC and PFLAG from buffers RETI Exit interrupt vector SONiX TECHNOLOGY CO LTD Page 71 Preliminary Version 0 4 Ss NX SN8P1919 D D E A 8 Bit Micro Controller with Charge pump Regulator
97. ersion 0 4 SONIX 1 5 PIN ASSIGNMENT SN8P1919 LQFP80 SNSPI919 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC COM1 COMO VLCD R R X X AO AO Al2 Al2 Al1 Al1 AVSS ACM AVDDR AVE AVDDCP C VDD SONiX TECHNOLOGY CO LTD SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 VLCD1 SEG28 P3 0 SEG29 P3 1 SEG30 P3 2 SEG31 P3 3 VSS VPP RST P1 5 P1 4 P1 3 NMornnontwnonnaoereneneee 2200 0000000000000000 oonnuunuunununvuunuunnuuuu wy 000000000 NNN NNN NNNNA 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 10 60 2 59 3 58 4 57 5 56 6 55 7 54 8 53 9 52 10 51 11 SN8P1919 50 12 49 13 48 14 47 15 46 16 45 17 44 18 43 19 42 20 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 DAZE OTN OOF SOUS TFT SOCwReEenornA PALE ZZE ERRE ERER ZE oz ea X33 gf 2255 5 SOAS Page 9 Preliminary Version 0 4 Ss NX SN8P1919 D D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 1 6 PIN DESCRIPTIONS VDD VSS AVSS_ P Powersupply input pins fordigital analogcircuit po veD P CDPowersupplyimput AVDDR P __ Regulator power output pin Voltage 3 8V _ S O T output 3 0V 2 4V 1 5V for Sensor Maximum output current 10 mA el ae AE Pump Voltage output Connect a 10uF or higher capacitor to ground Al Positive reference Positive reference input o ee aoao a gat A
98. eset External reset When any reset condition occurs all system registers keep initial status program stops and program counter is cleared After reset status released the system boots up and program starts to execute from ORG 0 The NTO NPD flags indicate system reset status The system can depend on NTO NPD status and go to different paths by program 086H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PFLAG NTO NPD C DC Z Read Write R W R W R W R W R W After reset 0 0 0 Bit 7 6 NTO NPD Reset status flag Condition Description Watchdog reset Watchdog timer overflow Reserved Power on reset and LVD reset Power voltage is lower than LVD detecting level External reset External reset pin detect low level status Finishing any reset sequence needs some time The system provides complete procedures to make the power on reset successful For different oscillator types the reset time is different That causes the VDD rise rate and start up time of different oscillator is not fixed RC type oscillator s start up time is very short but the crystal type is longer Under client terminal application users have to take care the power on reset time for the master terminal requirement The reset timing diagram is as following VDD LVD Detect Level Power ss VDD External Reset vss A External Reset External Reset High
99. eset 0 0 0 0 0 0 0 Bit O PWMOOUT PWM output control bit 0 Disable PWM output 1 Enable PWM output PWM duty controlled by TCOOUT ALOADO bits Bit 1 TCOOUT TCO time out toggle signal output control bit Only valid when PWMOOUT 0 0 Disable P5 4 is I O function 1 Enable P5 4 is output TCOOUT signal Bit 2 0 Disable TCO auto reload function 1 Enable TCO auto reload function Bit 6 4 TCORATE 2 0 TCO internal clock select bits ALOADO Auto reload control bit Only valid when PWMOOUT 0 00 Fopu 256 Fose t28 Fopu 2 Bit 7 0 Disable TCO timer 1 Enable TCO timer SONiX TECHNOLOGY CO LTD TCOENB TCO counter control bit Page 84 Preliminary Version 0 4 SONiM 8 3 3 TC1X8 TCOX8 TCOGN FLAGS SNSPI919 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 0D8H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TOM TOENB TOrate2 TOrate1 TOrateO TC1X8 TCOX8 TCOGN TOTB Read Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 Bit O TOTB RTC clock source control bit 0 Disable RTC TO clock source from Fcpu 1 Enable RTC Bit 1 TCOGN Enable TCO Green mode wake up function 0 Disable 1 Enable Bit 2 TCOX8 TCO internal clock source control bit 0 TCO internal clock source is Fcpu TCORATE is from Fcpu 2 Fcpu 256 1 TCO internal clock source is Fosc TCORATE is from Fosc 1 Fosc
100. eset 0 0 0 0 0 0 0 0 ADCKS 7 0 register sets the ADC working clock the suggestion ADC clock is 100K Hz Refer the following table for ADCKS 7 0 register value setting in different Fosc frequency ADC Clock Fosc 256 ADCKS 7 0 2 ADCKS 7 0 Fosc ADC Working Clock 246 4M 4M 10 2 200K 236 4M 4M 20 2 100K 243 4M 4M 13 2 154K 231 4M 4M 25 2 80K ADCKS 7 0 Fosc ADC Working Clock 236 8M 8M 20 2 200K 216 8M 8M 40 2 100K 231 8M 83M 25 2 160K 206 8M 8M 50 2 80K gt Note In general application ADC working clock is 100K Hz SONiX TECHNOLOGY CO LTD Page 126 Preliminary Version 0 4 SONIX 10 5 3 ADCDL ADC Low Byte Data Register SNSPI919 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 098H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ADCDL ADCB7 ADCB6 ADCB5 ADCB4 ADCB3 ADCB2 ADCB1 ADCBO R W R R R R R R R R After Reset 0 0 0 0 0 0 0 0 10 5 4 ADCDH ADC High Byte Data Register 099H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ADCDH ADCB15 ADCB14 ADCB13 ADCB12 ADCB11 ADCB10 ADCB8 ADCB9 R W R R R R R R R R After Reset 0 0 0 0 0 0 0 0 ADCDL 7 0 Output low byte data of ADC conversion word ADCDH 7 0 Output high byte data of ADC conversion word gt Note1 ADCDL 7 0 and ADCDH 7 0 are
101. gram as interrupt occurrence 2 The buffer of PUSH POP instruction is only one level and is independent to RAM or Stack area gt Example Store ACC and PAFLG data by PUSH POP instructions when interrupt service routine executed DATA ACCBUF DS 1 ACCBUF is ACC data buffer CODE ORG 0 JMP START ORG 8 JMP INT_SERVICE ORG 10H START INT_SERVICE BOXCH A ACCBUF Save ACC in a buffer PUSH Save 0x80 0x87 working registers and PFLAG register to buffers POP Load 0x80 0x87 working registers and PFLAG register from buffers BOXCH A ACCBUF Restore ACC from buffer RETI Exit interrupt service vector ENDP SONiX TECHNOLOGY CO LTD Page 66 Preliminary Version 0 4 N N y SN8P1919 S S E X 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 6 6 INTO P0 0 INTERRUPT OPERATION When the INTO trigger occurs the POOIRQ will be set to 1 no matter the POOIEN is enable or disable If the POOIEN 1 and the trigger event POOIRQ is also set to be 1 As the result the system will execute the interrupt vector ORG 8 If the POOIEN 0 and the trigger event POOIRQ is still set to be 1 Moreover the system won t execute interrupt vector even when the POOIRQ is set to be 1 Users need to be cautious with the operation under multi interrupt situation Note The interrupt trigger direction of P0 0 is control by PEDGE register OBFH Bit 7 Bi
102. hen the chip will restart the program from address 0000h and all system registers will be set as default values It is easy to know reset status from NTO NPD flags of PFLAG register The following example shows the way to define the reset vector in the program memory gt Example Defining Reset Vector ORG 0 0000H JMP START Jump to user program address ORG 10H START 0010H The head of user program User program SONiX TECHNOLOGY CO LTD Page 13 Preliminary Version 0 4 OQ NX SN8P1919 N D E yA 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC ENDP End of program SONiX TECHNOLOGY CO LTD Page 14 Preliminary Version 0 4 Ss NX SN8P1919 D D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 2 1 2 1 INTERRUPT VECTOR 0008H A 1 word vector address area is used to execute interrupt request If any interrupt service executes the program counter PC value is stored in stack buffer and jump to 0008h of program memory to execute the vectored interrupt Users have to define the interrupt vector The following example shows the way to define the interrupt vector in the program memory Note PUSH POP instructions only process 0x80 0x87 working registers and PFLAG register Users have to save and load ACC by program as interrupt occurrence gt Example Defining Interrupt Vector The interrupt service routine is following ORG 8 DDATA ACCBUF DS 1
103. ication One is using P5 0 and P5 1 which can avoid power consumption in sleep mode the another is using P5 0 only The second way will leak a small current in power down mode but can use P5 1 for Input application These two circuits are following LBTENB 1 P5110 1 LBTENB 1 P5110 0 P5 1 as LBT function No leakage current in sleep mode P5 1 as Input port Leak current in sleep mode Low Battery Voltage Ri R2 LBTO 1 VDD lt 2 4V 1 33MQ 0 66MQ VDD lt 3 6V 1 5MQ 0 5M0 VDD lt 4 8V Note Get LBTO 1 more 10 times in a raw every certain period ex 20 ms to make sure the Low Battery signal is stable SONiX TECHNOLOGY CO LTD Page 131 Preliminary Version 0 4 Ss NX SN8P1919 D D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 10 5 7 Analog Setting and Application The most applications of SN8P1919 were for DC measurement ex Weight scale Pressure measure In different applications had each Analog capacitor setting to avoid VDD drop when Charge pump enable or can save cost Following table indicate different applications setting which MCU power source came from CR2032 battery AA AAA dry battery or external Regulator Resistance and Capacitor Table AO Povere A AE Xen faos P acm AVDDR c c Cavoo CR2032 2 4 3V 100K CR2032 4 4 6V Note 1 When MCU source from CR2032 battery the AVE loading can t over 3mA for example the Load cell resi
104. il Sn8fae sonix com tw SONiX TECHNOLOGY CO LTD Page 146 Preliminary Version 0 4
105. including one internal interrupts one external interrupts enable control bits One of the register to be set 1 is to enable the interrupt request function Once of the interrupt occur the stack is incremented and program jump to ORG 8 to execute interrupt service routines The program exits the interrupt service routine when the returning interrupt service routine instruction RETI is executed OC9H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTEN TC1IEN TCOIEN TOIEN PO1IEN POOIEN Read Write R W R W R W R W R W After reset 0 0 0 0 0 Bit 0 POOIEN External P0 0 interrupt INTO control bit 0 Disable INTO interrupt function 1 Enable INTO interrupt function Bit 1 PO1IEN External P0 1 interrupt INT 1 control bit O Disable INT1 interrupt function 1 Enable INT interrupt function Bit 4 TOIEN TO timer interrupt control bit 0 Disable TO interrupt function 1 Enable TO interrupt function Bit 5 TCOIEN TCO timer interrupt control bit 0 Disable TCO interrupt function 1 Enable TCO interrupt function SONiX TECHNOLOGY CO LTD Page 62 Preliminary Version 0 4 Ss WN 9 NX SN8P1919 N D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC Bit 6 TC1IEN TC1 timer interrupt control bit 0 Disable TC1 interrupt function 1 Enable TC1 interrupt function SONiX TECHNOLOGY CO LTD Page 63 Preliminary Version 0 4 Ss N
106. ke the system not work well or executing program error VDD System Work Well Area System Work Error Area VSS Brown Out Reset Diagram The power dropping might through the voltage range that s the system dead band The dead band means the power range can t offer the system minimum operation power requirement The above diagram is a typical brown out reset diagram There is a serious noise under the VDD and VDD voltage drops very deep There is a dotted line to separate the system working area The above area is the system work well area The below area is the system work error area called dead band V1 doesn t touch the below area and not effect the system operation But the V2 and V3 is under the below area and may induce the system error occurrence Let system under dead band includes some conditions DC application The power source of DC application is usually using battery When low battery condition and MCU drive any loading the power drops and keeps in dead band Under the situation the power won t drop deeper and not touch the system reset voltage That makes the system under dead band AC application In AC power application the DC power is regulated from AC power source This kind of power usually couples with AC noise that makes the DC power dirty Or the external loading is very heavy e g driving motor The loading operating induces noise and overlaps with the DC power VDD drops by the noise and the sys
107. l Converter E O a Operating current Ipp_apc Run mode 3 8V 1000 Power down current Stop mode 3 8V ES 1 R R Input Range External Ref HE R R Input Range Internal Ref poz 20 v aras om pocrane sane Ton os reine nate ass maga re ocre sos ef rompas vw of v e ae Oo OPA S Currentconsumption consumption loo Pona Run mode 38V mode 3 8V tet Stop mode 3 8V EEES Input offset voltage a Bandwidth O PGIA Gain Range GR VDD 3 8V a 200x PGIA Input PGIAImputRange Vopin VDD VDD 3 8V 8V ec ad E DOT TT RS A a Band gap Reference Band gap Reference Voltage 1 1 150 1 210 210 1 270 270 Reference Voltage e Operatingcurent current tac Run mode Run mode 38V 3 8V Charge pump regulator 2 Supplyvotage Vers Normalmode 24 s v RegutsorcupvatageAVOOR Vane pas far aos vo og ommensetage vin Ja tet ter __ og opaca ho P O wwe JO o po O Mardmngeapeay fe Ja CY Viene eapety we Ta ma Note When Charge Pump enable current consumption will be time 2 of ADC PGIA CPR and Loading from AVE AVDDR SONiX TECHNOLOGY CO LTD Page 142 Preliminary Version 0 4 Ss NX SN8P1919 D D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 1 5 PACKAGE INFORMATION 15 1 LQFP 80 PIN SONiX TECHNOLOGY CO LTD Page 143 Preliminary Version 0 4 SNSPI919 SONIX
108. lization All system registers is set as initial conditions and system is ready Oscillator warm up Oscillator operation is successfully and supply to system clock Program executing Power on sequence is finished and program executes from ORG 0 The external reset can reset the system during power on duration and good external reset circuit can protect the system to avoid working at unusual power condition e g brown out reset in AC power application 3 6 EXTERNAL RESET CIRCUIT 3 6 1 Simply RC Reset Circuit R1 47K ohm 100 ohm This is the basic reset circuit and only includes R1 and C1 The RC circuit operation makes a slow rising signal into reset pin as power up The reset signal is slower than VDD power up timing and system occurs a power on signal from the timing difference Note The reset circuit is no any protection against unusual power or brown out reset SONiX TECHNOLOGY CO LTD Page 45 Preliminary Version 0 4 Ss NX SN8P1919 D D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 3 6 2 Diode amp RC Reset Circuit R1 47K ohm 100 ohm This is the better reset circuit The R1 and C1 circuit operation is like the simply reset circuit to make a power on signal The reset circuit has a simply protection against unusual power The diode offers a power positive path to conduct higher power to VDD It is can make reset pin voltage level to synchroniz
109. ll continue counting and issue a time out signal to trigger TCO interrupt to request interrupt service TCO overflow time is OxFF to 0X00 normally Under PWM mode TCO overflow is decided by PWM cycle controlled by ALOADO and TCOOUT bits The main purposes of the TCO timer is as following 8 bit programmable up counting timer Generates interrupts at specific time intervals based on the selected clock frequency Green mode wake up function TCO can be green mode wake up timer System will be wake up by TCO time out Buzzer output PWM output TCOOUT Internal P5 4 I O Circuit ALOADO Buzzer le puto Reload gt TC0 2 P5 4 TEOR Reload lt b ALOADO TCOOUT TCO Rate ata Buffer Fcpu 2 Fcpu 256 TCOX8 A IR PWMOOUT c PWM Ecpu TCOENB bil aa a I 2 As a x Load gt N rS Fosc y Tcoc LA gt 8 Bit Binary Up TCO Time Out Counting Counter TCO Rate Fosc 1 Fosc 128 CPUMO 1 SONiX TECHNOLOGY CO LTD Page 83 Preliminary Version 0 4 SONIX 8 3 2 TCOM MODE REGISTER SNSPI919 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC ODAH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TCOM TCOENB TCOrate2 TCOrate1 TCOrateO ALOADO TCOOUT PWMOOUT Read Write R W R W R W R W R W R W R W After r
110. n High byte to Data Buffer Move ADC conversion Low byte to Data Buffer Don t disable ADC when change Reference Votlage Selection ADC as Voltage Measure Check ADC output new data or not Wait for Bit DRDY 1 Output ADC conversion word Move ADC conversion High byte to Data Buffer Move ADC conversion Low byte to Data Buffer Page 130 Preliminary Version 0 4 N y SNSPI919 S MS E X 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 10 5 6 LBTM Low Battery Detect Register SN8P1919 provided two different way to measure Power Voltage One is from ADC reference voltage selection It will be more precise but take more time and a little bit complex The another way is using build in Voltage Comparator divide power voltage and connect to P5 1 bit LBTO will output the P5 2 voltage Higher or Lower than ACM 1 2V 09AH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LBTM LBTO P5110 LBTENB R W R R W R W After Reset 0 0 0 Bito LBTENB Low Battery Detect mode control Bit 0 Disable Low Battery Detect function 1 Enable Low Battery Detect function Bit1 P5110 Port 5 1 Input LBT function control bit 0 Set P51 as I O Port 1 Set P51 as LBT function Bit2 LBTO Low Battery Detect Output Bit 0 P5 2 LBT voltage Higher than ACM 1 2V 1 P5 2 LBT voltage Lower than ACM 1 2V There are two circuit connections for LBT appl
111. n PWM10UT 0 0 Disable P5 3 is I O function 1 Enable P5 3 is output TC1OUT signal Bit 2 ALOAD1 Auto reload control bit Only valid when PWM10UT 0 0 Disable TC1 auto reload function 1 Enable TC1 auto reload function Bit 6 4 TC1RATE 2 0 TC1 internal clock select bits TC1RATE 2 0 TC1X8 0 TC1X8 1 00m Fepu 256 Fosc 128 Fcpu 128 Fosc 64 Fepu 64 Fosc 32 Fepu 32 Fosc 16 Fepu 16 Fcpu 8 Fepu 4 Fepu 2 Bit 7 TC1ENB TC1 counter control bit 0 Disable TC1 timer 1 Enable TC1 timer 8 4 3 TC1X8 FLAG 0D8H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O TOM TC1X8 Read Write R W After reset 0 Bit 3 TC1X8 TC1 internal clock source control bit SONiX TECHNOLOGY CO LTD 0 TC1 internal clock source is Fcpu TC1RATE is from Fcpu 2 Fcpu 256 1 TC1 internal clock source is Fosc TC1RATE is from Fosc 1 Fosc 128 Page 93 Preliminary Version 0 4 Ss NX SN8P1919 D D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 8 4 4 TC1C COUNTING REGISTER TC1C is an 8 bit counter register for TC1 interval time control ODDH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TC1C TC1C7 TC1C6 TC1C5 TC1C4 TC1C3 TC1C2 TC1C1 TC1CO Read Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 The equation of TC1C initial value is as following TC1C initial value 256
112. nterrupt service routine Stack operation is a LIFO type Last in and first out The stack pointer STKP and stack buffer STKnH and STKnL are located in the system register area bank 0 ODFH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 STKP GIE STKPB2 STKPB1 STKPBO Read Write R W R W R W R W After reset 0 1 1 1 Bit 2 0 STKPBn Stack pointer n O 2 Bit 7 GIE Global interrupt control bit 0 Disable 1 Enable Please refer to the interrupt chapter gt Example Stack pointer STKP reset we strongly recommended to clear the stack pointers in the beginning of the program MOV A 00000111B BOMOV STKP A OFOH 0FFH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 STKnH snPC12 SnPC11 SnPC10 SnPC9 SnPC8 Read Write R W R W R W R W R W After reset 0 0 0 0 0 OFOH 0FFH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 STKnL SnPC7 SnPC6 SnPC5 SnPC4 SnPC3 SnPC2 snPC1 SnPCO Read Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 STKn STKnH STKnL n 7 0 SONiX TECHNOLOGY CO LTD Page 38 Preliminary Version 0 4 Ss NX SN8P1919 D D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 1 2 3 STACK OPERATION EXAMPLE The two kinds of Stack Save operations refer to the stack pointer STKP and write the content of program counter PC to the stack
113. o matter the TCOIEN is enable or disable If the TCOIEN and the trigger event TCOIRQ is set to be 1 As the result the system will execute the interrupt vector If the TCOIEN 0 the trigger event TCOIRQ is still set to be 1 Moreover the system won t execute interrupt vector even when the TCOIEN is set to be 1 Users need to be cautious with the operation under multi interrupt situation gt Example TCO interrupt request setup BOBCLR FTCOIEN Disable TCO interrupt service BOBCLR FTCOENB Disable TCO timer MOV A 20H a BOMOV TCOM A Set TCO clock Fcpu 64 MOV A 74H Set TCOC initial value 74H BOMOV TCOC A Set TCO interval 10 ms BOBSET FTCOIEN Enable TCO interrupt service BOBCLR FTCOIRQ Clear TCO interrupt request flag BOBSET FTCOENB Enable TCO timer BOBSET FGIE Enable GIE gt Example TCO interrupt service routine ORG 8 Interrupt vector JMP INT_SERVICE INT_SERVICE Push routine to save ACC and PFLAG to buffers BOBTS1 FTCOIRQ Check TCOIRQ JMP EXIT_INT TCOIRQ 0 exit interrupt vector BOBCLR FTCOIRQ Reset TCOIRQ MOV A 74H BOMOV TCOC A Reset TCOC ees TCO interrupt service routine EXIT_INT Pop routine to load ACC and PFLAG from buffers RETI Exit interrupt vector SONiX TECHNOLOGY CO LTD Page 70 Preliminary Version 0 4 N No yy SNSPI919 S S E X 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 6 10 TC1 INTERRUPT OPERATION Wh
114. oad function controlled by ALOAD1 bit of TC1M When TC1C overflow occurring TC1R value will load to TC1C by system It is easy to generate an accurate time and users don t reset TC1C during interrupt service routine Note Under PWM mode auto load is enabled automatically The ALOAD1 bit is selecting overflow boundary ODEH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 BitO TC1R TC1R7 TC1R6 TC1R5 TC1R4 TC1R3 TC1R2 TC1R1 TC1RO Read Write W W W W W W W W After reset 0 0 0 0 0 0 0 0 The equation of TCAR initial value is as following TC1R initial value 256 TC1 interrupt interval time in These parameters decide TC1 overflow time and valid value as follow table TC1R valid TC1R value J 0x00 0xFF 00000000b 11111111b Fcpu 2 Fcpu 256 dd 28 0x00 OxFF 00000000b 11111111b gt Example To set 10ms interval time for TC1 interrupt TC1 clock source is Fcpu TC1X8 0 and no PWM output PWM1 0 High clock is external 4MHz Fcpu Fosc 4 Select TC1RATE 010 Fcpu 64 TC1R initial value 256 TC1 interrupt interval time input clock 256 10ms 4MHz 4 64 256 10 2 4 106 4 64 100 64H SONiX TECHNOLOGY CO LTD Page 96 Preliminary Version 0 4 Ss NX SN8P1919 D D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 8 4 6 TC1 CLOCK FREQUENCY OUTPUT BUZZER Buzzer output TC10UT is from TC1 timer counter frequency o
115. output voltage On chip 1 2V Band gap reference for battery monitor On chip Voltage Comparator Build in ADC reference voliage V R R 0 8V 0 64V or 0 4V Build In Temperature Sensor LCD driver 1 3 or 1 2 bias voltage 4 common 32 segment Dual clock system offers five operating modes Internal high clock RC type up to 16 MHz External high clock Crystal type up to 8 MHz Normal mode Both high and low clock active Slow mode External Low clock only Green mode Period wake up by TO Sleep mode Both high and low clock stop Package LQFP80 Page 7 Preliminary Version 0 4 SNSPI919 SONIX Y WS D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 1 4 SYSTEM BLOCK DIAGRAM INTERNAL lt gt PC HIGH RC OTP lt gt IR EXTERNAL ROM HIGH OSC EXTERNAL LOW OSC Y TIMING GENERATOR SYSTEM REGISTERS INTERRUPT CONTROL TIMER amp COUNTER LVD Low Voltage Detector WATCHDOG TIMER m gt Charge Pump gt Regulator gt PGIA gt Comparator 16 BIT ADC Internal Reference Internal ADC Channel for Battery Detect l l PO P1 P2 P3 Figure 1 1 Simplified system block diagram SONiX TECHNOLOGY CO LTD Page 8 AVDDCP AVDDR AVE AI Al LBTIN2 1 R R Preliminary V
116. pin XOUT pin is general purpose I O pin External Clock Input XIN XOUT MCU VSS VDD Note The GND of external oscillator circuit must be as near as possible to VSS pin of micro controller SONiX TECHNOLOGY CO LTD Page 53 Preliminary Version 0 4 Ss NX SN8P1919 D D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 4 5 SYSTEM LOW CLOCK The system low clock source is the external low speed oscillator The low speed oscillator can use 32768 crystal or RC type oscillator circuit 4 5 1 1 CRYSTAL Crystal devices are driven by LXIN LXOUT pins The 32768 crystal and 10uF capacitor must be as near as possible to MCU LXIN 32768HZ LXOUT MCU Cc Cc 10pF 4 5 1 2 RC Type LXOUT LXIN 22pF av L a M C U 35pF 6V T VDD I VSS The external low clock supports watchdog clock source and system slow mode controlled by CLKMD Flosc External low oscillator Slow mode Fcpu Flosc 4 SONiX TECHNOLOGY CO LTD Page 54 Preliminary Version 0 4 SON N SN8P1919 Y Ss D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC In power down mode the external low clock will be Stop gt Example Stop internal low speed oscillator by power down mode BOBSET FCPUMO To stop external high speed oscillator and internal low speed oscillator called power down mode
117. quence of setup TC1 timer is as following Stop TC1 timer counting disable TC1 interrupt function and clear TC1 interrupt request flag BOBCLR FTC1ENB TC1 timer TC1OUT and PWM stop BOBCLR FTC1IEN TC1 interrupt function is disabled BOBCLR FTC1IRQ TC1 interrupt request flag is cleared Set TC1 timer rate Besides event counter mode MOV A 0xxx0000b The TC1 rate control bits exist in bit4 bit6 of TC1M The value is from xO00xxxxb x111xxxxb BOMOV TC1M A TC1 timer is disabled Set TC1 timer clock source Select TC 1 Fcpu Fosc internal clock source BOBCLR FTC1X8 Select TC1 Fepu internal clock source or BOBSET FTC1X8 Select TC1 Fosc internal clock source Note TC1X8 is useless in TC1 external clock source mode Set TC1 timer auto load mode BOBCLR FALOAD1 Enable TC1 auto reload function or BOBSET FALOAD1 Disable TC1 auto reload function Set TC1 interrupt interval time TC1OUT Buzzer frequency or PWM duty cycle Set TC1 interrupt interval time TC1OUT Buzzer frequency or PWM duty MOV A 7FH TC1C and TC1R value is decided by TC1 mode BOMOV TCIC A Set TC1C value BOMOV TCAR A Set TCAR value under auto reload mode or PWM mode SONiX TECHNOLOGY CO LTD Page 98 Preliminary Version 0 4 SONIX Set TC1 timer function mode BOBSET FTC1IEN or BOBSET FTC10UT or BOBSET FPWM10UT Enable TC1 timer BOBSET FTC1ENB SONiX TECHNOLOGY CO LTD
118. rflow the TOIRQ will be set to 1 however the TOIEN is enable or disable If the TOIEN 1 the trigger event will make the TOIRQ to be 1 and the system enter interrupt vector If the TOIEN 0 the trigger event will make the TOIRQ to be 1 but the system will not enter interrupt vector Users need to care for the operation under multi interrupt situation gt Example TO interrupt request setup BOBCLR FTOIEN Disable TO interrupt service BOBCLR FTOENB Disable TO timer MOV A 20H a BOMOV TOM A Set TO clock Fcpu 64 MOV A 74H Set TOC initial value 74H BOMOV TOC A Set TO interval 10 ms BOBSET FTOIEN Enable TO interrupt service BOBCLR FTOIRQ Clear TO interrupt request flag BOBSET FTOENB Enable TO timer BOBSET FGIE Enable GIE Example TO interrupt service routine ORG 8 Interrupt vector JMP INT_SERVICE INT_SERVICE Push routine to save ACC and PFLAG to buffers BOBTS1 FTOIRQ Check TOIRQ JMP EXIT_INT TOIRQ O exit interrupt vector BOBCLR FTOIRQ Reset TOIRQ MOV A 74H BOMOV TOC A Reset TOC a TO interrupt service routine EXIT_INT Pop routine to load ACC and PFLAG from buffers RETI Exit interrupt vector SONiX TECHNOLOGY CO LTD Page 69 Preliminary Version 0 4 Ss NX SN8P1919 Y WS D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 6 9 TCO INTERRUPT OPERATION When the TCOC counter overflows the TCOIRQ will be set to 1 n
119. rflow after executing addition instruction gt Example Jump table ORG 0X0100 The jump table is from the head of the ROM boundary BOADD PCL A PCL PCL ACC the PCH can t be changed JMP AOPOINT ACC 0 jump to AOPOINT JMP A1POINT ACC 1 jump to A1POINT JMP A2POINT ACC 2 jump to A2POINT JMP A3POINT ACC 3 jump to ASPOINT In following example the jump table starts at OxOOFD When execute BOADD PCL A If ACC 0 or 1 the jump table points to the right address If the ACC is larger then 1 will cause error because PCH doesn t increase one automatically We can see the PCL 0 when ACC 2 but the PCH still keep in 0 The program counter PC will point to a wrong address 0x0000 and crash system operation It is important to check whether the jump table crosses over the boundary xxFFH to xx00H A good coding style is to put the jump table at the start of ROM boundary e g 0100H gt Example If jump table crosses over ROM boundary will cause errors ROM Address 0X00FD BOADD PCL A PCL PCL ACC the PCH can t be changed 0X00FE JMP AOPOINT ACC 0 0X00FF JMP A1POINT ACC 1 0X0100 JMP A2POINT ACC 2 lt jump table cross boundary here 0X0101 JMP A3POINT ACC 3 SONiX TECHNOLOGY CO LTD Page 19 Preliminary Version 0 4 Ss xX SN8P1919 N D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC SONIX provides a macro for safe jump table function This ma
120. rge pump enable Note 2 IF VDD always over 4 2V set Charge pump as Auto or Disable mode to disable charge pump Note 3 In AA AAA dry battery application delay time is shorter than CR2032 application SONiX TECHNOLOGY CO LTD Page 133 Preliminary Version 0 4 SONIX SNSPI919 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 1 1 APPLICATION CIRCUIT 11 1 Scale Load Cell Application Circuit Note Please refer 10 5 7 for capacitor setting AVE VDD AVDDR D __J AVE CAVE do CAVDDR SONiX TECHNOLOGY CO LTD COM 3 __ COM 2L__ COM 1 __ S J AVSS Q lt o QO a z B T D H AVDDR D Cl vppcP CAVDD SEG 3 VDD Pin20 C VSS C C C Ib Zz Cc Page 134 _ RST ene tok 08 P0 0 L_ P1 0 L P1 1 C P1 2 VSS L_ VDD P5 2 mE P5 1 C P5 3 CLJ EERI P5 7 L __JXOUT L__JLXOUT L XIN LXIN 3 58M 32768 X tal X tal I I 20pF 20pF 20pF 20pF Preliminary Version 0 4 Ss NX SN8P1919 D D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 11 2 Thermometer Application Circuit Note Please refer 10 5 7 for capacitor setting VDD AVDDR f aA MNT OOS Thermopile O ssss O O 35 Al1 gt Q Q Q Q 79 no o Q 9 dp wn _ _ AVE an A AM P1 1 a Al1 P1 2 a Thermisto n A ACM N von
121. ro Controller with Charge pump Regulator PGIA 16 bit ADC 13 2 OTP Programming Pin to Transition Board Mapping 13 2 1 The pin assignment of Easy and MP EZ Writer transition board socket Easy Writer JP1 JP2 Easy Writer JP3 Mapping to 48 pin text tool VSssj2 1 VDD DIP1 1 48 DIP48 CE 4 3 CLK PGCLK DIP2 2 47 DIP47 OE ShiftDat 6 5IPGM OTPCLK DIP3 3 46 DIP46 DO8 7 D1 DIP4 4 45 DIP45 D210 9 D3 DIP5 5 44 DIP44 D4 12 11 D5 DIP6 6 43 DIP43 D6 14 13 D7 DIP7 7 42 DIP42 VPPI16 15VDD DIP8 8 41 DIP41 RST 18 17 HLS DIP9 9 40 DIP40 ALSB PDB 20 19 DIP10 10 39 DIP39 DIP11 11 38 DIP38 JP1 for MP transition board DIP12 12 37 DIP38 JP2 for Writer V3 0 transition board DIP13 13 36 DIP36 DIP14 14 35 DIP35 DIP15 15 34 DIP34 DIP16 16 33 DIP33 DIP17 17 32 DIP32 DIP18 18 31 DIP31 DIP19 19 30 DIP30 DIP20 20 29 DIP29 DIP21 21 28 DIP28 DIP22 22 27 DIP27 DIP23 23 26 DIP26 DIP24 24 25 DIP25 JP3 for MP transition board 13 2 2 The pin assignment of Writer V3 0 transition board socket GND 2 1 VDD CE 4 3 CLK OE 6 5 PGM DO 8 7 D1 Writer V3 0 JP1 Pin Assignment SONiX TECHNOLOGY CO LTD Page 138 Preliminary Version 0 4 S NX SN8P1919 D D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 13 2 3 SN8P1919 Series Programming Pin Mapping OTP Programming Pin of SN8P1919 Series Chip Name SN8P1919 Easy MP EZ Writer OTP IC JP3 Pin Assignment And Writer
122. ruction set table for detailed information of C DC and Z flags SONiX TECHNOLOGY CO LTD Page 28 Preliminary Version 0 4 Ss NX SN8P1919 D D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 1 1 1 PROGRAM COUNTER The program counter PC is a 13 bit binary counter separated into the high byte 5 and the low byte 8 bits This counter is responsible for pointing a location in order to fetch an instruction for kernel circuit Normally the program counter is automatically incremented with each instruction during program execution Besides it can be replaced with specific address by executing CALL or JMP instruction When JMP or CALL instruction is executed the destination address will be inserted to bit O bit 12 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 BitO PC PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PCO After esa 0 0 0 0 0 0 0 0 0 0 0 0 0 PCH PCL ONE ADDRESS SKIPPING There are nine instructions CMPRS INCS INCMS DECS DECMS BTSO BTS1 BOBTSO BOBTS1 with one address skipping function If the result of these instructions is true the PC will add 2 steps to skip next instruction If the condition of bit test instruction is true the PC will add 2 steps to skip next instruction BOBTS1 FC To skip if Carry_flag
123. s gt Example Modify TC1R registers value MOV A 30H Input a number using BOMOV instruction BOMOV TCAR A INCMS BUFO Get the new TC1R value from the BUFO buffer defined by NOP programming BOMOV A BUFO BOMOV TCAR A Note The PWM can work with interrupt request SONiX TECHNOLOGY CO LTD Page 104 Preliminary Version 0 4 Ss NX SN8P1919 D D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 8 6 4 PWM1 DUTY CHANGING NOTICE In PWM mode the system will compare TC1C and TC1R all the time When TC1C lt TC1R the PWM will output logic High when TC1C TCAR the PWM will output logic Low If TC1C is changed in certain period the PWM duty will change immediately If TC1R is fixed all the time the PWM waveform is also the same TC1C TC1R TC1C overflow and TC1IRQ set v v v v v OxFF TC1C Value 0x00 PWM1 Output 1 2 3 4 5 6 7 Period lt gt lt gt lt gt a Above diagram is shown the waveform with fixed TC1R In every TC1C overflow PWM output High when TC1C TC1R PWM output Low Note Setting PWM duty in program processing must be at the new cycle start SONiX TECHNOLOGY CO LTD Page 105 Preliminary Version 0 4 SNSPI919 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC SONIX 9 LCD DRIVER There are 4 common pins and 3
124. ssary for interrupt service request One of the interrupt requests occurs and the program counter PC points to the interrupt vector ORG 8 and the stack add 1 level ODFH Bit 7 Bit 6 Bit5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 STKP GIE STKPB2 STKPB1 STKPBO Read Write R W R W R W R W After reset 0 1 1 1 Bit 7 GIE Global interrupt control bit 0 Disable global interrupt 1 Enable global interrupt gt Example Set global interrupt control bit GIE BOBSET FGIE Enable GIE SONiX TECHNOLOGY CO LTD Page 64 Preliminary Version 0 4 S Q NY SN8P1919 Y AS bs E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC Note The GIE bit must enable during all interrupt operation SONiX TECHNOLOGY CO LTD Page 65 Preliminary Version 0 4 N y SN8P1919 S S E X 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 6 5 PUSH POP ROUTINE When any interrupt occurs system will jump to ORG 8 and execute interrupt service routine It is necessary to save ACC PFLAG data The chip includes PUSH POP for in out interrupt service routine The two instruction only save working registers 0x80 0x87 including PFLAG data into buffers The ACC data must be saved by program Note 1 PUSH POP instructions only process 0x80 0x87 working registers and PFLAG register Users have to save and load ACC by pro
125. stance can t over 1K Note 2 In AA AAA battery application the AVE can loading 10mA current so that the Load cell can be up to 330 ohm Note 3 If VDD always over 4 2V Set Charge pump as Auto or Disable mode so that charge pump will disable and current consumption will not time 2 from AVDDR and AVE Capacitors of AVDDR and C C can be removed and Connect AVDDCP to VDD Note 1 The positive note of Cayppcp connect to AVDDCP and Negative note connect to VDD Note2 The positive note of Cacm connect to AVDDR and Negative note connect to ACM SONiX TECHNOLOGY CO LTD Page 132 Preliminary Version 0 4 Ss NX SN8P1919 D D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC VDD 2 4V 4 2V Analog Capacitor Connection Q O o a i Cavppc Cc CAVDDR AVDDR VDD 4 2V 5 5V Analog Capacitor Connection O xt a Cavor AVDDR AVSS EJ AVDDCP CAVE H LT AVE or avoor lt U Oo CAVE t __ AVE lt ESHAVDDR 0 3 Lic HH Avoocr O lt H Avss Delay Time Charge Pump Enable Delay Enable Enable Enable OMENS Step 1 Step 2 ACM AVDDR AVE CPCKS 00001011B CPCKS 00000100B R2032 2 4 3V R2032 4 4 6V ms 5Oms_ _50ms AA AAA Bat 4 4 6V ms 50ms 50ms External 5VReg ms 50ms 50ms Note 1 In CR2032 application Please set enough delay time or the VDD will drop when Cha
126. t Must connect VLCD1 to VLCD Must connect VLCD1 to VDD LCD Panel LCD Panel E Jos VLCD SEG0 27 VLCD SEG0 27 MCU MCU PIN 46 49 LCD Panel 9 2 OPTION REGISTER DESCRIPTION OPTION initial value xxxx xxx0 088H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OPTION RCLK R W R W After Reset 0 RCLK External low oscillator type control bit 0 Crystal Mode 1 RC mode gt Notel Circuit diagram when RCLK 0 External Low Clock sets as Crystal mode LXIN LXOUT VSS VSS SONiX TECHNOLOGY CO LTD Page 107 Preliminary Version 0 4 SONY SN8P1919 SY WS D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC gt Note2 Circuit diagram when RCLK 1 will enable external Low Clock sets as RC mode LXIN VSS 20P Connect the C as near as possible to the VSS pin of micro controller The frequency of external low RC is decided by the capacitor value Adjust capacitor value to about 32KHz frequency SONiX TECHNOLOGY CO LTD Page 108 Preliminary Version 0 4 O WN Y MX SN8P1919 Y WS D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 9 3 LCD TIMING LCD Clock 1 Frame 1 Frame VLCD C
127. t 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PEDGE PEDGEN P00G1 POOGO R W R W R W Bit7 PEDGEN Interrupt and wakeup trigger edge control bit 0 Disable edge trigger function Port 0 Low level wakeup trigger and falling edge interrupt trigger Port 1 Low level wakeup trigger 1 Enable edge trigger function P0 0 Both Wakeup and interrupt trigger are controlled by POOG1 and POOGO bits P0 1 Wakeup trigger and interrupt trigger is Level change falling or rising edge Port 1 Wakeup trigger is Level change falling or rising edge Bit 4 3 POOG 1 0 Port 0 0 edge select bits 00 reserved 01 falling edge 10 rising edge 11 rising falling bi direction gt Example Setup INTO interrupt request and bi direction edge trigger MOV A 98H BOMOV PEDGE A Set INTO interrupt trigger as bi direction edge BOBSET FPOOIEN Enable INTO interrupt service BOBCLR FPOOIRQ Clear INTO interrupt request flag BOBSET FGIE Enable GIE gt Example INTO interrupt service routine ORG 8 Interrupt vector JMP INT_SERVICE INT_SERVICE Push routine to save ACC and PFLAG to buffers BOBTS1 FPOOIRQ Check POOIRQ JMP EXIT_INT POOIRQ 0 exit interrupt vector BOBCLR FPOOIRQ Reset POOIRQ or INTO interrupt service routine EXIT_INT Pop routine to load ACC and PFLAG from buffers RETI Exit interrupt vector SONiX TECHNOLOGY CO LTD Page 67 Preliminary Version 0 4 N y SN8P1919 S S E X 8
128. tem works under unstable power situation The power on duration and power down duration are longer in AC application The system power on sequence protects the power on successful but the power down situation is like DC low battery condition When turn off the AC power the VDD drops slowly and through the dead band for a while SONiX TECHNOLOGY CO LTD Page 42 Preliminary Version 0 4 Ss NX SN8P1919 D D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 3 4 2 THE SYSTEM OPERATING VOLTAGE DECSRIPTION To improve the brown out reset needs to know the system minimum operating voltage which is depend on the system executing rate and power level Different system executing rates have different system minimum operating voltage The electrical characteristic section shows the system voltage to executing rate relationship System Mini Operating Voltage Vdd V os Normal Operating Area Dead Band Area System Reset Voltage Reset Area System Rate Fcpu Normally the system operation voltage area is higher than the system reset voltage to VDD and the reset voltage is decided by LVD detect level The system minimum operating voltage rises when the system executing rate upper even higher than system reset voltage The dead band definition is the system minimum operating voltage above the system reset voltage 3 4 3 BROWN OUT RESET IMPROVEMENT How to improve the brown reset condition There are some methods
129. the frequency of TCOIRQ is depended on PWM duty range From following diagram the TCOIRQ frequency is related with PWM duty TCO Overflow TCOIRQ 1 OxFF TCOC Value 0x00 PWMO Output Duty Range 0 255 8 5 3 PWM PROGRAM EXAMPLE gt Example Setup PWMO output from TCO to PWMOOUT P5 4 The external high speed oscillator clock is 4MHz Fcpu Fosc 4 The duty of PWM is 30 256 The PWM frequency is about 1KHz The PWM clock source is from external oscillator clock TCO rate is Fcpu 4 The TCORATE2 TCORATE1 110 TCOC TCOR 30 MOV A 01100000B BOMOV TCOM A Set the TCO rate to Fcpu 4 MOV A 30 Set the PWM duty to 30 256 BOMOV TCOC A BOMOV TCOR A BOBSET FPWMOOUT Enable PWMO output to P5 4 and disable P5 4 I O function BOBSET FTCOENB Enable TCO timer Note The TCOR is write only register Don t process them using INCMS DECMS instructions gt Example Modify TCOR registers value MOV A 30H Input a number using BOMOV instruction BOMOV TCOR A INCMS BUFO Get the new TCOR value from the BUFO buffer defined by NOP programming BOMOV A BUFO BOMOV TCOR A Note The PWM can work with interrupt request SONiX TECHNOLOGY CO LTD Page 101 Preliminary Version 0 4 Ss NX SN8P1919 D D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 8 5 4 PWMO DUTY CHANGING NOTICE In PWM mode the system will compare TCOC and TCOR all the time When TCOC lt
130. ulator PGIA 16 bit ADC 9 4 LCD RAM LOCATION RAM bank 15 s address vs Common Segment pin location Como comi com2 coma HH HPA 01H 0 o1H1 01H2 01H3 02H 0 02H 1 02H 2 02H 3 03H 0 03H 1 03H 2 03H 3 pa ea o Ela e a EE RECAM INES DENSA gt Example Enable LCD function Set the LCD control bit LCDENB and program LCD RAM to display LCD panel BOBSET FLCDENB LCD driver SONiX TECHNOLOGY CO LTD Page 111 Preliminary Version 0 4 Ss NX SNS8P1919 D D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 1 Ocharge Pump PGIA and ADC 10 1 OVERVIEW The SN8P1919 has a built in Voltage Charge Pump Regulator CPR to support a stable voltage 3 8V from pin AVDDR and 3 0V 2 4v 1 5V from pin AVE with maximum 10mA current driving capacity This CPR provides stable voltage for internal circuits PGIA ADC from AVDDR and external sensor load cell or thermistor from AVE The SN8P1919 series also integrated A 2 Analog to Digital Converters ADC to achieve 16 bit performance and up to 62500 step resolution The ADC has THREE different input channel modes 1 Two fully differential inputs 2 One fully differential inputs and Two single ended inputs 3 Four single ended inputs This ADC is optimized for measuring low level unipolar or bipolar signals in weight scale and medical applications A very low noise chopper stabilized programmable gain instrumentation
131. um calculated is done Y_ADD_1 INCMS Y Increase Y NOP JMP B Jump to checksum calculate CHECKSUM_END END USER _CODE _ SONiX TECHNOLOGY CO LTD Label of program end Page 21 Preliminary Version 0 4 Ss NX SN8P1919 D D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 2 1 3 CODE OPTION TABLE IHRC High speed internal 16MHz RC XIN XOUT become to P2 0 P2 1 High_Clk bi direction I O pins 4M X tal Standard crystal resonator e g 4M for external high clock oscillator Force Watch Dog Timer clock source come from INT 16K RC Always_ON Also INT 16K RC never stop both in power down and green mode that INT_16K_RC means Watch Dog Timer will always enable both in power down and green mode By_CPUM Enable or Disable internal 16K 3V RC clock by CPUM register ewer ie Law Foie Note 1 In high noisy environment set Watch_Dog as Enable and INT_16K_RC as Always_ON and Enable Noise Filter is strongly recommended 2 Fcpu code option is only available for High Clock Fcpu of slow mode is Flosc 4 3 In high noisy environment disable Low Power is strongly recommended 4 The side effect is to increase the lowest valid working voltage level if enable Low Power and Noise Filter code option 5 Enable Low Power option will reduce operating current except in slow mode SONiX TECHNOLOGY CO LTD Page 22 Preliminary Version 0 4
132. unting Counter f o CPUMO 1 m gt TO Time Out RTC gt TOENB gt Note In RTC mode the TO interval time is fixed at 0 5 sec and isn t controlled by TOC SONiX TECHNOLOGY CO LTD Page 79 Preliminary Version 0 4 SNSPI919 JONiM S D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 8 2 2 TOM MODE REGISTER 0D8H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TOM TOENB TOrate2 TOrate1 TOrateO TC1X8 TCOX8 TCOGN TOTB Read Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 Bit O TOTB RTC clock source control bit 0 Disable RTC TO clock source from Fcpu 1 Enable RTC TO will be 0 5 sec RTC Low clock must be 32768 cyrstal Bit 1 TCOGN Enable TCO Green mode wake up function 0 Disable 1 Enable Bit 2 TCOX8 TCO internal clock source control bit 0 TCO internal clock source is Fcpu TCORATE is from Fcpu 2 Fcpu 256 1 TCO internal clock source is Fosc TCORATE is from Fosc 1 Fosc 128 Bit 3 TC1X8 TC1 internal clock source control bit 0 TC1 internal clock source is Fcpu TC1RATE is from Fcpu 2 Fcpu 256 1 TC1 internal clock source is Fosc TC1RATE is from Fosc 1 Fosc 128 Bit 6 4 TORATE 2 0 TO internal clock select bits 000 fcpu 256 001 fcpu 128 110 fcpu 4 111 fcpu 2 Bit 7 TOENB TO counter control bit 0 Disable TO timer 1 Enable TO timer gt Note TORATE is not availa
133. utput function By setting the TC1 clock frequency the clock signal is output to P5 3 and the P5 3 general purpose I O function is auto disable The TC1OUT frequency is divided by 2 from TC1 interval time TC1OUT frequency is 1 2 TC1 frequency The TC1 clock has many combinations and easily to make difference frequency The TC1OUT frequency waveform is as following TC1 Overflow Clock TC1OUT Buzzer Output Clock gt Example Setup TC10UT output from TC1 to TC1OUT P5 3 The external high speed clock is 4MHz The TC1O0UT frequency is 0 5KHz Because the TC1OUT signal is divided by 2 set the TC1 clock to 1KHz The TC1 clock source is from external oscillator clock TC1 rate is Fcpu 4 The TC1RATE2 TC1RATE1 110 TC1C TC1R 131 MOV A 01100000B BOMOV TC1M A Set the TC1 rate to Fcpu 4 MOV A 131 Set the auto reload reference value BOMOV TCIC A BOMOV TCAR A BOBSET FTC1OUT Enable TC1 output to P5 3 and disable P5 3 I O function BOBSET FALOAD1 Enable TC1 auto reload function BOBSET FTC1ENB Enable TC1 timer Note Buzzer output is enable and PWM10UT must be 0 SONiX TECHNOLOGY CO LTD Page 97 Preliminary Version 0 4 Ss NX SN8P1919 D D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 8 4 7 TC1 TIMER OPERATION SEQUENCE TC1 timer operation includes timer interrupt event counter TC1OUT and PWM The se

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