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1. mm Figure 3 18 Key Buttons and Side Switch System User s Manual 85 CHAPTER 3 2BSYSTEM CONTROL 2 General Purpose LEDs System Architecture IIC line GPIO Expander CPU Board 3 3V 15 LED1 zz _ 50 ipp Board x LED4 LED3 IIC Figure 3 19 Key Buttons and Side Switch System 86 User s Manual CHAPTER 3 2BSYSTEM CONTROL 3 12 Audio LSI Connection 4648 AUDIO V3 MI C 10 E u Binz ur m SCL 2 2 LINEOUT LI N2 2 LINEOUT L f Te zz 2 5 Audio IF LI N3 MIN Audio IF V gus cm ge ROUT LON LINEOUT LINE OUT T udio REFCLKO MUTET 02 DA9052 2 85 150 Audio Figure 3 20 Audio IF Circuit Block Diagram PDN Power down mode H Power Up L Power down Reset and initialize the control register User s Manual 87 CHAPTER 3 2BSYSTEM CONTROL 3 13 Lan9221 Connection with EM1 Lan9221 connection with EM1 is as follows FIFO SEL pin on LAN9221 is connected to ABO 11 2 LAN9221 0 15
2. asa 20 142 IO board Debug Interface CN6 226 aequo bue venae Queries kg 28 2 ccc HELD 24 2l O M NN 24 2 FARTS DEVAS DESCRIP TION vase se iura eto eR Esau LP 25 EMMA CPU ESD uu 25 LIO 25 2923 DDR SDRAM MT46H52M392LECN 6 E 25 2 2 4 Memory MTFC4GDKDI ET or 26 2 2 5 NOR Flash Memory PC28F256P30B85 26 29G INO earache ge ees a ote MOM 26 2 2 7 USB PHY 18 1504 27 27 DDO 27 Audo PPA 612 1 28 2 2 11 NAND Flash Memory K9F1G08U0A NOT MOUNTED the board 28 CHAPTER 3 SYSTEM CONTROL Q a 29 OVS PEN BLOCK DIAGRAM Ou 5 5 29 5 a un opa usut Quan mam na masa Suma Gun um amana D LIEU 30 anu amun apre a 30 922 31 92 0o BANKS 32 Uo 33 Powerbysteim
3. Mobile Family SEMC EM1 EMMA Mobile 1 Development Kit Board ARM Document No 190445001 1 4 Edition Date Published Feb 2010 Shimafuji Electronics Inc Printed in Japan 2 User s Manual The names of other companies and products are registered trademarks or trademarks of respective company These commodities technology or software must be exported in accordance with the export administration regulations of the exporting country Diversion contrary to the low of that country 15 prohibited NOTES FOR CMOS DEVICES 1 Waveform distortion due to input noise or a reflected wave may cause malfunction If the input of the CMOS device stays in the area between VIL MAX and VIH MIN due to noise etc the device may malfunction Take care to prevent chattering noise from entering the device when the input level is fixed and also in the transition period when the input level passes through the area between VIL MAX and VIH MIN 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction If an input pin is unconnected it is possible that an internal input level may be generated due to noise etc causing malfunction CMOS devices behave differently than Bipolar or NMOS devices Input levels of CMOS devices must be fixed high or low by using pull up or pull down circuitry Each unused pin should be connected to V
4. 98 pp 98 SODIMM ui 99 100 TAUE0 60DS 0 9V Y 2 un a uu te tue 101 0 5 102 DFA OAOD Oasis un uuu aaa 102 2 9 0 V004 2 103 104 M 105 MR Oo Pr eee ee 106 MUSEI CUIU RA RIEN PECORE RES 106 MISSE NRI I esr ro 106 106 ma wade Sees 107 LAN9221 EEPROM Address 111 LAN9221 EEPROM Address 0x11 111 Address 111 Montor Fontana Tes T I UU P 112 Modification signal in external 113 User s Manual User s Manual 11 To use this Product safety In this paragraph it explains notes to use this product safety Please read before using the product Please defend the content of the description of this document and use the product Please keep this document near the main body of the product to refer at once when it is necessary content that has been described is the one in this document at the time
5. 31 30 wa o S O 2 ___ 222 PINSEL REFCLKO 07761 X 4 r S S pedo 1 2 EMEN ea 1 eee 1 0 Pazour 0 7 6 User s Manual HR CHAPTER 3 2BSYSTEM CONTROL 3 9 Chip Select 3 9 1 1 5 System Connection Architecture Table 3 7 EM1 S System Connection Architecture 1 Voltage Connected to PCM Codec LSI AK4648 Expansion Connector CN4 5 NTSC IF Pin Multiplexed SPO CSO DA 9052 For Control SPO CS1 LCD For LCD Panel Control SPO CS2 Expansion Connector CN4 5 NTSC IF Pin Multiplexed Expansion Connector CN4 5 DTV IF Pin Multiplexed DTV VI Expansion Connector CN4 5 00 ez N NTSC Encoder NTSC Out 50 51 52 ABO Connector S3 C C microSD Expansion Connector CN4 5 CPU eMMC NAND PAD 10 NAND VI O18 VI CPU 10 port on CPU Board port Mictor type Board VI O18 10 LCD Connector Direct Connector CPU Board LCD Panel connection IO Board VI O18 CPU SB Phy gt USB mini AB Connector U U U U IO 3 1 CP CP CP P P C Codec LSI AK4648 on CPU Board Expansion Connector CN4 5 on IO B
6. 37 EMT GPIO u sk ON tees EH 43 Io m 50 MAX 2A GPIO MMC vU 54 EM1 S System Connection Architecture 77 External Bus Chip Select CSBO to 3 78 SPI 78 Read m a ICS CSS 79 CPU Board SWIC S u u uuu u uu uet 80 owitenes and EBDS T yu Gon 82 lO Board Switches and LEDS e 83 DSW 1 Boot Mode Switch Description 1 84 DSW1 Boot Mode Switch Description 2 84 DA9052 Register USB Charger Detection 92 SIGA20C20YSOGA 2 o edt 93 SF PE 93 0 SOV OG u uuu 94 5657905795 usun aa a ois ews E 95 U o0 AMBE 95 SO DIMMUCNI Terana EE 96 PT MEER ERN 97
7. 7324 Free Push Button Switches for users Switches Push Down Activated Detail Architecture Please see 3 9 3 SW2 3 4 Key Matrix Push MAX7324 Free Push Button Switches for users 6 7 8 Switches Type Push Down Activated Detail Architecture Please see 3 9 3 9 10 11 12 13 14 SW15 Power DC IN AC Adapter Power Switch Switch OFF SW16 Debug Target Slide Type Control DPDT Switch SW17 NTS LSI Slide Type Reset Switch SPDT 1 3 ON ADV7179 Reset is connected to EM1 GIO_P8 OFF ADV7179 Reset is connected to GND It can reduce useless current when NTSC PAL function does not be used swig fe Not Used Continues to next Page 82 User s Manual CHAPTER 3 2BSYSTEM CONTROL Table 3 13 Board Switches and LEDs 2 Switch amp Title Type GPIO Explanation LEDs Assign NTS PM1 Clock Slide Type This Switch set NTSC 27MHz Clock supply to EM1 or not Select SPDT 27MHz Clock supply to EM1 OFF 27MHz Clock not supply to EM1 This signal line is duplicated with PM1 Clock line NTS CLK PM1 CLK So SW19 should set to OFF when PM1 function is used For Detail architecture Please see 3 4 2 USB Mode Slide DA9052 This switch sets USB Mode Select Switch SPDT GIO 1 ON E On USB IF is defined as DEVICE OFF USB IF is defined as HOST 1 2 34 LED Detail Architecture Please see 3 9 3 Color Power Indicator VDDOUT line Green User s Manual
8. m ordo 34 Bocas 35 Lower down Control for Board device e e et euo 36 POWER OUD S 37 333 Backin _ 38 ud SOC DOC _____ 39 3 4 1 Board Clock Tree Structure 39 04 2 TO Board Clock Tree SI Goluru u x u u m Du T u w tatu 40 225 0 41 41 ON BOARD INTERRUPETS EZ u uude hes tna EE 49 48 Be Gall EMMA ee sop yl anh 43 50 54 PIN ETTING 56 SEA 56 LOTES 58 ERR pununa ea TU m 59 So EMEN Rd RC UTE SM TP 60 Bere IS NITET aa __ 61 62 So Am yusa ETN sa sn Ba 64 0 0 9 HRTO 65 ST b
9. D a SP1 CS1 CAM YUV2 WIFI2 NTS CLK PM1 Note 501 DATA1 CAM 23 33 UART2_ UARIZ2 RTSB SP1 51 Note GIO 94 WiFi3 n7 AEE pem few srie mas ERA WiFi 36 PM1 SI Note 7 SD1 CMD CAM YUV5 17 801 HS PM1 SEN Note SP1 SO CAM YUVO 18 GND GIO 10 38 GND 9 19 eno 7 29 39 eno _ GND Jeno 4 SO Note lt gt Note these signals are connected to CN5 on default state IO board because the signal is alternate pin with NTSC signal For connection you need resistor mount to IO board Regarding the modification please refer to Modification for signals in external connector CN4 CN5 02 User s Manual CHAPTER 4 3BCONNECTORS 4 2 5 Debugger CN6 CN9 Table 4 15 2 5767004 2 User s Manual 103 CHAPTER 4 3BCONNECTORS 4 2 6 Battery Connector CN10 Table 4 16 Through Hole TFor Using battery Please contact battery suppler or battery consultants and DIALOG Semiconductor Europe North America Dialog Semiconductor GmbH Dialog North America Neue Strasse 95 440 Oakmead Parkway D 73230 Kirchheim Teck Nabern Sunnyvale CA 94085 Germany USA Phone 49 7021 805 0 Phone 1 888 809 3816 Fax
10. KEY_IN3 U2 LAN9221 GIO 41 INT iix cg Expansion Connector GIO P95 GIO P95 WIFI 1 201 GIO 11 22 GIO P94 GIO P94 WIFI3 GIO P37 GIO P37 WIFIA 26 GIO P10 GIO P10 WIFI5 28 1 I Figure 3 14 IRQ Tree of EM1 Development Kit Board 42 User s Manual CHAPTER 3 2BSYSTEM CONTROL 3 7 EM1 DA9052 and MAX7324 have GPIO Each GPIO is described blow 3 7 1 Mobile1 Table 3 4 1 GPIO Settings Go ps vios dedicated CardDetectforsoo Go Pi vios NANDRBI CAMSTANDY _ NAND RB2 CAM SCLK CAM SCLK R vos nanom Go ps ou CEI _ E NAND CE2 Audio 4 648 vios m SPINTIGEM ox GT Wakeup _ P36 VIO18 ABO A25 PushSW1 P37 VIO18 ABO A26 Wakeup GIO_P41 VIO18 WAIT LAN 9221 IRQ P44 ABO CSB2 LAN9221 RESET GIO P46 VIO18 ABO BENO LCD RESET 27 MU GIO 47 VIO18 ABO BEN USB3329 RESETB vos out Go Pri LCDENAME Pusnsw2 _ Go ps wc Resen Go pes vos or pwm GTRESED Note 1
11. Audio Codec AK4648EC Power source for AK4648 is separated from other power source Audio_V3 This power source line is controllable independently Users can set AK4648 to power down mode by GPIO control Set 9 to low PDN pin of AK4648 will be activated and AK4648 will be set into power down mode For detail information Please see AK4648 Data Sheet USB Phy ISP1504C Users can set AK4648 to power down mode by GPIO control Set GIO P47 to High CS_N PWRDN of AK4648 will be activated and ISP1504C will be set into power down mode For detail information Please see ISP1504C Data Sheet USB Serial FT232RQ No power down mode Converter NOR Flash PC28F256P30B85 power down mode Video Encoder ADV7179 Users can reset ADV7179 when this device does not be used Set SW17 off of IO Board Off Set SW17 of IO Board and GIO P8 set to reset Low For Detail Information Please see ADV7179 Data Sheet LAN Controller LAN9221 Users can reset LAN9221 by GPIO control Set GIO P44 set to reset Low For Detail Information Please see LAN9221 Data Sheet NAND Flash K9F1G08U0A No power down mode Other Devices 36 User s Manual CHAPTER 3 2BSYSTEM CONTROL 3 3 4 Power Supply Source Design Kit Board has two options about power supply source The supply source is selected by JP1 physically And SW20 on IO Board should set to find the status for software point of view Please also refer to 4 1 8 JU
12. ____ 56 oup URT2 SOUTNAND ce 136 v285 az o jaBAD 9 PENAND wee 137 vopour 18 GND VDDOUT 19 so AD10 9 19 2 jop 6 VDDOUT 61 AD12 LCD 22 62 LCD AB LCD 64 LCD 25 EY 2 lxx IE 7 107 147 5 au ju ee m ue jo lua la lcd 1 LAN AB n m AB WR 12 vios VIO18 VIO18 36 37 __ 21 78 ms v3 39 m9 V3 ABA 120 navn 96 User s Manual CHAPTER 4 3BCONNECTORS 4 7 SO DIMM CN8 URTO SOUT URT1 SRIN CAM SCLK GN 501 CAM GND SD1 DATA3 CAM HS LCD RO SD1 DATA2 CAM VS z x LCD R3 _ 2444 9221 127 GND GIO P41 LAN INT GND GND 5 89 GND 129 501 YUV7 10 LCD R4 130 SD1 DATAO CAM YUVG GND 50 GND 131 NTS CLK PM1 16 56 1 5 1 SO C AGND 18 sPocs 18 58 98 Pto wris ____ 138 AGND 19 spo 18 __ 59 uc SDA 99 GIO PI WFM ____ 139 AGND o SPOSO 18 60 uc scet 100 P10 WFI3 40 MPWR 1 GN 61 GIO P10 WFI2 LIN1 GIO P10 WF11 RIN1 23 HsYNc 63 st 103 enon us 43 LINEOUT L 104 LINEOUT R AGND LCD PXCLK2 AGND GND 28 GND ______ 6
13. The connection of the cable and the interface cable is insufficient and the power supply is not turned on causes the breakdown generation of heat a fire and the explosion When moving products cables and power supply are removed The cable etc is damaged and it causes the breakdown generation of heat a fire and the electric shock Caution The power supply turning on and cutting each system follow the procedure described in the manual It causes the breakdown of generation of heat and the equipment to occur User s Manual 13 General Precautions for Handling This Product 1 Circumstances not covered by product guarantee Does not use over voltage and use outside guaranteed temperature range Do not add power to the USB cable and do not add power to the USB interface Do not remove or break S N Serial Number sticker These stickers are required for warranty validation 2 Safety precautions If used for a long time the product may become hot 50 to 60 Be careful of low temperature burns and other dangers due to the product becoming hot It is explained by the previous item 1 Circumstances not covered by product guarantee 3 Warning The board is selling AS IS If board has Faults You and your company acknowledge and agree risk Anytime you examine New Information of this Board and Devices Shimafuji don t pay the ransom that exceeds the price of the product is not paid 4 User s
14. This plastic portion should be inside this metal part Step 5 Insert fully metal parts to be parallel line against the connector Step 7 Final Confirmation 1 confirm whether following distance D1 is same about four portion The concrete distance of this photo is subject to change without notice s Step 8 Final Confirmation 2 when connectors inserted correctly following distance D2 must be 61 11mm approx about any distance between metal part of connectors o PT User s Manual PDF Revision history sion 28 Oct 2009 First edition 4 Feb 2010 NEC Revision 2 3 8 Arase NEC Revision 24 16 Feb 2010 1 Urano 010 DA9052 B silicon th 5 8 Modification for signals in external connector CN4 CN5 17 Mar 2010 1 3 5 9 Connection of CPU board and IO board 4 2 3bEnhanced Connector CN4 gt 77 Note 223821 4 2 4Enhanced Connector CN4 gt 7 Note 223821 5 2 Board installation to Case 5 6 Board Information in EEPROM Factory setting TTable 5 2 L 5 7 Monitor Point and Test Pad Table 5 Ze RANCE L Revision History Rev2 4 Revision History 2 4 huir ri amp 30 RAKE tt NEC Renesas Table 5 2 LAN9221 EEPROM Address 0 11 rev Ey B silicon 1820 0274 Apr 2010 Tab
15. 3 2 1 Memory Bank BANK Description Target Module 0000 0000H BANK 0 NOR FLASH FFFFH EXTERNAL Device 1FFF FFFFH 2000 0000H BANK 2 EXTERNAL Device 2FFF FFFFH 3000 0000H BANK 3 DRAM 3FFF FFFFH 4000 0000H BANK 4 Bus 0 _ 5000 0000H BANK 5 Async Bus 1 5FFF FFFFH 6000 0000H BANK 6 AHB Slave 6FFF 7000 0000H BANK 7 Reserved FFFFH 8000 0000H BANK 8 Reserved 8FFF FFFFH 9000 0000H BANK 9 Reserved 9FFF FFFFH A000 0000H AFFF FFFFH 000 0000H BANK 11 Reserved BFFF FFFFH C000 0000H CFFF FFFFH 0000 0000H BANK 13 Reserved DFFF FFFFH E000 0000H BANK 14 Reserved EFFF FFFFH F000 0000H FFFF FFFFH Figure 3 2 EMMA Mobile1 ALL Memory Bank User s Manual CHAPTER 3 2BSYSTEM CONTROL 3 2 2 BANK 0 1 2 BANK 0 1 2 ABO NOR FLASH External Device NOR 0000 0000H 01FF_FFFFH Ether 2000 0000H 20FF FFFFH example mapping 256Mbit 0000 0000H NOR OFFF 1000 0000H 2000 0000H Ether LAN9221 C S3 exam ple mapping 20FF FFFFH you can choose other address 2FFF FFFFH Figure 3 3 EMMA Mobile1 NOR and Asynchronous 0 No 0 Memory User s Manual 31 CHAPTER 3 2BSYSTEM CONTROL 3 2 3 DRAM AREA BANK 3 MEMC DRAM 3000 0000H 37FF FFFFH 1Gbit 3000 0000H 50 3 FF FFFFH 3800 0000H Reserved Figure 3 4 EMMA Mobi
16. 3171 USB Switchtor Host Mode 91 rol ef USB Charpen Detection Mes De ute sedo 92 4 CONNECTORS uu des ae nass S Bia 93 BOARD CONNECTORS 93 4 1 1 JTAG Connector 93 419 SD Interfaee Conmector GN snot nto 93 ALs JDBCDIntertface Connector uuu uuu o u wa tos s op twn b 94 ATA VSB Interface Connector a eese hne a ST U au S u Gua TRE ERA MES 95 4 1 5 USB Interface from UART Connectors 1 11 1000000000000000000 95 416 Peripheral Connector CN ONG s deepest tia 96 4 1 7 Power LSI 09052 Monitor 9 98 LN SEES DO IBI err s ass 98 222 99 4 2 1 CPU Daughter Board Connectors 99 SNNT 101 4 0 8 Enhanced Connector 102 4900 Snhaneed Connect og ION5 ie EY dee iu i 102 405 Webitoser CNO __ 6_6___ __ 103 12 0 Battery Connector ON TO RS 104 JTAG Connector CN ED u L u ditate ied eot ides duelo a 105 ADS Connector Jl
17. PM1 SEN PM1 51 1 SO NENNEN CAM YUVA CAM YUV3 CAM YUV2 CAM YUV1 CAM YUVO 11b SP1 CS3 SP1 CLK PM1 CLK 59 CHAPTER 3 2BSYSTEM CONTROL 3 8 4 DTV SP2 Pin name xx initial setting DTV BCLK SP2 CLK DTV DATA SP2 5 DTV PSYNC 5 2 50 DTV SP CSO PINSEL_DTV 1 0 CHG_PINSEL_DTV atemavepimslist __ Register 705 19 18 setvaue Broa 92 2 22 232 EMEN 17160 014 0284 ma 60 User s Manual CHAPTER 3 2BSYSTEM CONTROL 3 8 5 5 0 01 Pin name xx CS1 00 CS2 GIO P48 1 0 GIO P4g 1 0 CHG PINSEL G48 MWI SK SI SO CS 49 Switched PINSEL G4B alternative pins list O seus T tea 02524 EMEN 221 era 1981 1710 o o 014 0280 4 2 61 CHAPTER 3 2BSYSTEM CONTROL 3 8 6 LCDC setting LCD PXCLK GIO P5D LCD R 0 5 GIO P 51 56 LCD GI0 5 P 57 62 LCD BD GIO P63 GIO P50 1 0 to GIO Pe3 1 0 PINSEL 1348 Pin name LCD Setting LCD B 1 5 84 68 LCD H amp YN
18. Regarding Board revision please refer to 5 5 Board Revision and 5 6 Board Information in EEPROM 2 and VIO18 are depended DA9052 programming The concrete voltage can refer to 3 3 2 1 0 9052 Connection GIO PO D9052 Power IC Active Low GIO PO is connected to DA9052 nIRQ which is open drain interface EM1 must receive the signal with an internal pull up resistor and must set GIO as interrupt input User s Manual 43 CHAPTER 3 2BSYSTEM CONTROL alo Card inserted Without card Card inserted LOW Without card HIGH 5 01 connector CMe P3 withaut card Card inserted B GIO must be set to pull up alo P5 User s Manual CHAPTER 3 2BSYSTEM CONTROL alo MANDGnat mounted LO write protect alo Lowy 78 reset ali EMT CODECCAKAGAB Lowy 4 reset User s Manual 45 CHAPTER 3 2BSYSTEM CONTROL P1 1 P1 1 VIO P386 shmitt inverter 10k Pa push HIGH open 46 User s Manual CHAPTER 3 2BSYSTEM CONTROL 41 Ethe r amp LANB221 221 IRO IRQ active level pragrammable keep software compatibility with 910111 set active levet HIGH IRO C F
19. _ _ PH 66 7 68 p ED 70 25212 A 78 74 6 5 16 User s Manual T TT 3 9 1 EMI S System Connection 71 3 9 2 External Bus Select to 5 3 78 009 SP TACT CCS iin shales 78 o EC 79 3 41 DIP SWITCHES KEYS GED SPEGCS O 80 B11 Buttonswitehes and LEBs om CPU Boards cco S 80 3 11 2 Key buttons Side Switches LEDs IO 81 3 11 3 IO Board Switches and LEDSs 82 3 11 4 Boot Mode Switch DSW1 on CPU Board 84 3 11 5 General Purpose Key Buttons and LEDs System Architecture 85 o 12 ADD OSPCONNSKCTIONZ 5 __ 87 9 19 CONNECTION W ETH EM uuu 38 Sw 89 SUE MM mM 90 uito doeet pens uoti Qt dudes 91 91
20. 1 0 01 User s Manual 01b 69 CHAPTER 3 2BSYSTEM CONTROL 3 8 11 502 T Pin i nisal Gd n MAMD c 10 Piao FINSEL Pin WAT HAND MAND ALE URT2 MAND CLE MAND 00 MAND 01 s j aic PINSEL 11 Pin 202 MAND WE _ HAND REO FIHSEL IIC2 1 0 PFINSEL ES o ot We 3 oe ABO CLK PINSEL 600 NAND CE2 NAND CE1 LN SEEN oll 7 0 User s Manual CHAPTER 3 2BSYSTEM CONTROL pf altemativepnsit Register Ob 05 10b tb setvaue Oo 11 Ob O CHG_PINSEL_G96 40202 ee 4002 te 1981 GIO P100 Ob O tb PINSEL 6112 17 16 014 021C 15 14 119 13 12 11 10 GIO P117 07 01b 98 P116 MEN as NEN x 71 CHAPTER 3 2BSYSTEM CONTROL x atemavepmslit Register bt 00b 05 19 715 Bra 10 00 290281 02524 232 __ __ EMEN nsa 12212 PINSEL 1 2 0710 0000 00 C014 0290 1
21. 83 CHAPTER 3 2BSYSTEM CONTROL 3 11 4 Boot Mode Switch DSW1 on CPU Board ON ON 4 1234 Example SD Boot setting ON ON OFF ON Figure 3 17 DSW1 Photo and Top view Image Table 3 14 DSW1 Boot Mode Switch Description 1 pema eee EE Na Bit Setting 1 ON ON ON 005 X NORBot 2 2 ON ON OFF 000i JeMMCBot 0 3 ON OFF ON 010b SDBot 4 ON OFF OFF Ob 4J Reeved 0 5 OFF ON ON 7105 X NANDBot 2 6 OFF ON OFF 105 J ABOboot ADSPJTAG Z 7 OFF OFF ON 1059 j eMMCBoot ADSPJTAG 8 OFF OFF OFF 11 SDBoot ADSPJTAG Table 3 15 DSW1 Boot Mode Switch Description 2 BOOT SEL3 Description Bit Setting 1 OFF 1 LSPEEDmodeON L2 0 L SPEED mode OFF For Detail Information for Change Boot mode register and its BOOT SEL bit description Please see EM1 1Chip Usert s Manual 84 User s Manual CHAPTER 3 2BSYSTEM CONTROL 3 11 5 General Purpose Key Buttons and LEDs System Architecture 1 General Purpose Key Buttons System Architecture CPU Board SPO 50 line DA9052 GPIO 0 ADCIN 4 IO Board GPIO Expander REY INO 8 svs EN GPIO_9 PWR_EN KEY 10 EN KEY IN3 GPIO 12 GP FB1 CE
22. ON HIGH LED OFF er Man gt CHAPTER 3 2BSYSTEM CONTROL I2 I3 I5 15 MAX 7 324 TP18 TT 18 TP18 TP2 T P21 TP22 TP23 User s Manual CHAPTER 3 2BSYSTEM CONTROL 3 8 Pin setting 3 8 1 ABO 01 00 10 Glo P11 r 0 t GIO 1 1 0 0 0 10 P16 1 6 te P31 1 6 Glo Pas 1 0 te GIO 7 1 0 332 Pin name ABO xx ABO CLK NTS_CLK ABO ADIOS Pin ABO xx AD 4 15 A17 ABO A18 ABO A19 ABO A20 GIO P 1 amp 27 2 NTS DATAO Glo 5 DATA 1 GIO P30 MTS DATA2 GlO P231 _ 21 26 ABO ADV ABO RDB ABO WAHE ABO WAIT ABO CSBO 2581 ABO CSB2 ABO BENI GIO P 32 37 GIO P38 Glo GIO Glo GIO P43 44 P45 GIO 4 DATAG LATA MTS HS ______ 6 tib setvaue 31 30 GIO P15 29 28 GIO P14 23 22 17 16 ABO CLK PINSEL 600 014 0200H no es es _ nano Res RE _ USB PWR FAULT 1 0 56 User s Manual CHAPTER 3 2BSYSTEM CONT
23. SW17 NTS LSI Reset SW SW19 NTS PM1 Clock Select SW20 use for USB mode switch connected to EM1 GIO P01 J1 NTSC Pal Output J2 AUDIO JACK MIC IN J3 AUDIO JACK LINE OUT 20 User s Manual CHAPTER 1 OBINTRODUCTION 1 3 Power Supply CAUTION The travel adapter is not recommended for AC DC adapter use And should isolate from water and dust Switching AC DC Adapter Manufacture UNIFIVE Product Name US300520 INPUT AC100V 120V AC100V 240V 50 60Hz OUTPUT 5V2A SAFETY PSE MARK UL CUL CE CB BSMI DIMENSION LxWxH 60x44x26 5 mm Plug Type 2 pin IEC Technical Report 60083 JIS C 8303 1 Input Side 26 5 17 60 Dimension is mm 2 Output Side Figure 1 6 AC DC Adapter Image CAUTION If you need to prepare other AC DC adapter for un match AC plug your domestic regulation and so on please must buy same mechanical specification and feeder specification regarding DC side Those are EIAJ2 and OUTPUT 5 2 User s Manual 21 CHAPTER 1 OBINTRODUCTION 1 4 Development Tools Connection 1 4 1 CPU Board ICE Interface CN1 Special Header TET SICA20C20Y GA102 Header ARM 20Pin Special Header ARM 20pin Header SICA20C20Y GA102 Figure 1 7 CPU Board ICE Interface TETC Tokyo Eletech Corporation 3 10 Akihabara Taito ku Tokyo 110 0006 Japan Mail e components tetc co jp TEL 81 0 3 5295 1661 FAX 81 0 3 5295 1775 Web http www tetc co jp le enquete htm On 2
24. __ ____ cio 10 99 CHAPTER 4 3BCONNECTORS Table 4 11 SO DIMM CN2 PIN ianal PIN ianal PIN ianal PIN ianal 1 VBAT 41 12 2 VBAT 82 URT2 RTSB NAND D1 122 EXT V12 3 NAND D2 123 ExT vm 4 124 EXT 5 as EXT V15 VBAT 46 AB AD1 NAND D5 126 EXT V15 T N C 47 AD2 87 127 EXT V15 N C 48 AD3 88 128 EXT V15 AB A1 49 AD4 GND 129 EXT V18 10 AB A2 50 9 jop 130 EXT V18 11 51 AB AD6 EXT V18 12 AB A4 52 92 2 SCL NAND WE 132 EXT V18 13 AB A5 53 GND 93 133 EXT V285 14 134 EXT V285 15 EXT V285 5 apa 56 1812 SOUTNAND cle 136 EXT v285 17 GND AB_AD8 97 137 VDDOUT 18 GND 58 AB_AD9 GND 138 VDDOUT 19 GND 59 AB_AD10 loo _ GND 139 VDDOUT 20 i40 VDDOUT AB A9 61 AB AD12 LCD 3V 22 AB A10 62 102 KEY IN1 142 LCD 3V AB A11 LCD 24 AB A12 64 104 KEY IN3 144 LCD 3V 25 AB A13 5 105 GND 145 26 __ lee 2 107__ GND 28 __ At6 69 50 109 exr vos ws ev O gt O 29 GND GND 70 31 GND 71 51 111 32 GND 72 AB WR 112 EXT VIO3 1 33 17 73 113 018 HEN 34 18 AB ADV 114 VIO18 EU 35 AB A19 75 GND 115 VIO18 pp 36 AB A20 76 116 VIO18 37 NAND V3 Ec 38 AB A22 78 nRESET 18 118 NAND V3 39 23 79 GND 119 NAND V3 p 40 A
25. are short circuited Note above terminal software settings are depend on board software settings Virtual COM port driver and USB driver are maintained supported by FTDI Future Technology Devices International Limited If you have any trouble for above settings please ask to FTDI directly Future Technology Devices International Limited On May 09 Unit 1 2 Seaward Place Centurion Business Park Glasgow G41 1HH United Kingdom Tel 44 0 141 429 2777 Fax 44 0 141 429 2758 E Mail Support support1 ftdichip com E Mail General Enquiries admin1 aftdichip com Web Site URL http www ftdichip com 5 1 2 USB Mini The Development Kit Board can receive a power supply voltage from USB Mini AB Connecter This function needs a Jumper Switch set But a supply current from USB Host is not enough for the Development Kit Board as CPU board IO board and LCD panel 08 User s Manual 5 2 Boardinstallation to Case Approx 32mm Step 2 Upper case installation to Base case with PCB Step 1 installation to Base case by three Screw T Approx 153mm Approx 8 mm 9 9 gt 9 9 9 2 9 Figure 5 1 Case 109 User s Manual 5 3 Address Address sticker is on board Do not remove a MAC Address sticker Image TBD 5 4 Serial Number S N Serial Number sticker is on board Do not remove a S N Serial Number sticke
26. iU UM 106 429 AUDIO Connector J2 boten debes da etude 106 2940 AC Adapter Connector 106 107 43 1 LCD Panel Interface Connector CN a 107 5 OTHER 108 aa E hee atc 108 5 1 1 USB Mini B Connector by using serial port of EM1 108 DD WSB 108 BOARDI A ATON TOZJHBR AS aM i 109 Die NECA ea T eq Ea 110 NUMBER THEN 110 9 295 POA R VISIO E E AE 110 5 6 BOARD INFORMATION IN EEPROM FACTORY 111 MONITOR FOINTAND TEST PAD kiya gua 112 5 8 MODIFICATION FOR SIGNALS IN EXTERNAL CONNECTOR CN4 CN5 seen 113 5 9 CONNECTION OF CPU BOARDAND IO BOA a dees 114 8 User s Manual Figure No Figure 1 1 Figure 1 2 Figure 1 3 Figure 1 4 Figure 1 5 Figure 1 6 Figure 1 7 Figure 1 8 Figure 3 1 Figure 3 2 Figure 3 3 Figure 3 4 Figure 3 5 Figure 3 6 Figure 3 7 Figure 3 8 Figure 3 9 Figure 3 10 Figure 3 11 Figure 3 12 Figure 3 13 Figure 3 14 Figure 3 15 Figure 3 16 Figure 3 17 Figure 3 18 Figure 3 19 Figure 3 20 Figure 3 21 Figur
27. mounted on VBUS line from R42 USB Mini AB connector Current R92 These resistors are 0 ohm and are mounted on 5 0v line from AC measurem R96 adapter ent R93 These resistors are 0 ohm and are mounted on VBAT line to from R97 CN10 which is NMT and for a battery connection Signal TP1 4 648 MCKO Monitor TP2 D9052 VPERI SW TP3 D9052 VMEM SW 4 09052 PWR UP TP5 D9052 GPIO 0 Signal KEY INO DA9052 GPIO 8 Monitor KEY IN1 DA9052 GPIO 9 KEY IN2 DA9052 10 TP10 KEY IN3 DA9052 GPIO 12 TP11 URT1 SOUT EM1 TP12 URT1 SRIN EM1 TP14 D9052 GPIO 0 TP15 CPU Board SW5 EM1 GIO P71 Input for TP16 Expander input 0 MAX7324 Test TP17 Expander input 1 MAX7324 TP18 Expander input 2 MAX7324 TP19 Expander input 3 MAX7324 TP20 Expander input 4 MAX7324 TP21 Expander input 5 MAX7324 TP22 Expander input 6 MAX7324 TP23 Expander input 7 MAX7324 TP24 GND Terminal Signai SRIN ADM3202 Monitor TP5 SOUT ADM3202 GND Pad 2 User s Manual lt R gt 5 8 Modification for signals in external connector CN4 CN5 Following table shows modification point for connection to external connector Alternate signals of NTSC signal is not connected on default state s IO board So when any signal of the table is used through external connector CN4 CN5 it needs modification to use it And after the modification please refer to Connection o
28. 009 You can get information of TETC SICA20C20Y GA102 on TETC web page Please confirm that when you need a interface connector cable of TETC SICA20C20Y GA102 to ICE 22 User s Manual CHAPTER 1 OBINTRODUCTION 1 4 2 10 board Debug Interface CN6 CN9 Debug interface is used 38 Mictor connector The interface is not included ETM trace signal as below pin assignment Header Mictor connector EXT V285 tu 1 MCZ NC3 NCA TRACECLK RESET DBGACK eH RICK wa ka di TMS M i TDI TRACEPKTS 25 2 TRST i 15 2 ZEE TRACEPKT13 TRACEPKT1 12 TRACEPKTD TRACEPKT11 TRACESYNC 2 PIPESTAT1 FIPESTATD CG CG2 38 CG5 2 5 767 004 2 x En C 3 Figure 1 8 Debug Interface CN6 CN9 User s Manual CHAPTER 1 OBINTRODUCTION CHAPTER 2 FUNCTIONS 2 1 Board Function Summary Table 2 1 Board Function Contents CPU Board IO Board CPU Board works independently M1 S Dialog DA9052 MobileDDR 1Gbit 128Mbyte x CPU Board NAND 4 GByte emo IO NOR Flash 256Mbit 32Mbyte Board Nand Flash
29. 01D 0 40200033 EEPROM 0x10 DDR BAO bit 5 0 MEMC DDR CONFIGC2 0xC00A2010 0x00000018 0x37771F1F EEPROM 0x10 DDR bit3 1 Next table shows a recommendation number about related CHG register with MEMC ta DRIVEO 0 0140400 2 90 User s Manual CHAPTER 3 2BSYSTEM CONTROL 3 16 SPI Interface Development Kit board has SPI interface The Chip select state can be confirmed at 3 9 3 SPI Chip Selects This section is described two notes as below Maximum clock speed Clock frequency of SPI interface is 14 28MHz maximum which is depend of a limit of DA9052 specification PMIC DA9052 command order DA9052 has two different of initial start up by silicon revision For common software you need below Before SPI transmission between LCD panel and EM1 DA9052 shall supply LCD PS which is LDO5 The register number is R54 and the value is 0x66 By the command DA9052 LDO5 outputs 3 1V to LCD 3 17 USB Interface 3 17 1 USB Switch for Host Mode When you use USB Host mode following switch and jumper switch must be set Board CircuitName Seting Note refer to CPU JP1 USB Device 2 3 short 4 1 8 JUMPER JP 1 USB Host 1 2 short SW20 USB Device ON 1 2 short Table 3 13 IO Board USB Host OFF 2 3 short Switches and LEDs 2 The Development Kit Board has a switch of VBUS voltage output for Host mode The switch is controlled from two LSI depended on the board revision as below
30. 01b 1 URTO RTSB URTO CTSB alternative pins list 10b NAND OE CAM CLKI PM1 SO SP1 CS5 SP1 54 set value NENNEN fb o 015 059 05 058 2 059 058 O 058 s K was PM1_SO _ 11b 1 8 66 User s Manual CHAPTER 3 2BSYSTEM CONTROL x J aMemaiepimsli o LIMEN NEM ar 4 00 292 esa 232 0 era nsa 0 T T moa 112 Ba User s Manual 67 CHAPTER 3 2BSYSTEM CONTROL 3 8 10 SD1 Pin name SD1 initial setting 5 1 CMD SD1 DATA D 3 5 1 PINSEL 01 Switched by 380 PINSEL SD1 1 0 Pin name SD1 setting I GIO P92 2 1 01 PIMSEL 180 Jetemdivepinslit bit 00 05 19 GIO 27 26 GIO P93 E 0 0 1 CHG_PINSEL_G80 01b URTO CTSB 9 8 GIO P84 5 4 GIO_P82 PM1 SO PM1 SO 3 2 P81 SP1 CS5 1 SI 1 0 GIO P80 SP1 CS4 PM1 SEN 68 User s Manual CHG PINSEL 501 C014 028C CHAPTER 3 2BSYSTEM CONTROL alternative pins list om ly _ era esa _ eo maa S E oO O O 54
31. 1 Board revision Rev1 The MAX1946 USB SW is controlled through ISP1504 USB PHY EXT VIO3 ISP1504 USB PHY MAX1946 USB SW 2 Board revision Rev2 The MAX1946 USB SW is controlled through D9052 GPIO 13 GPIO13 nVDD FAULT D9052 CNO9 for PMIC Mon nVDD FAULT 79 GPIO 13 EXT VIO3 Note Regarding Board revision please refer to 5 5 Board Revision and 5 6 Board Information in EEPROM User s Manual 91 CHAPTER 3 2BSYSTEM CONTROL 3 17 2 USB Charger Detection Development Kit Board can detect USB Charger connection at DA9052 from board revision 2 as below Regarding board revision please refer to 5 5 Board Revision and 5 6 Board Information in EEPROM 1 Board revision 1 CN5 U16 U2 USB mini AB Connector USB PHY ISP1504 DA9052 NC D 2 Board revision 2 CN5 USB mini AB Connector U16 U2 USB PHY USB3329 DA9052 SPK R DM SPK L Table 3 16 DA9052 Register USB Charger Detection Setting USB is automatic USB charger type detection This function enables to detect by hardware before EM1 software working When EM1 software starts after USB charger detection by hardware EM1 software is suggested to set USB 0 because the hardware detection of DA9052 is not needed on software working condition 97 User s Manual 4 5 4 1 CPU Board Connectors 4 1 1 JTAG Connector CN1 T
32. 11 WIFI2 ABO REFCLK xdi WO CAM SCLK CNA LCD PXCLK BCLK SP2 ki LCD IF EXT OUT 32K LCD PXCLK CN7 SPO CLK CSO NTS CLK PM1 CLK U2 Lan Ctrl LAN9221 U5 Video Enc ADV7179 CLOCK Y2 5W19 27 2 Figure 3 11 Clock Source on IO Board Flash Clock Signal Source corresponds to WE RE Signal NOR Flash Clock Signal Source corresponds to AB WR RD Signal 40 User s Manual CHAPTER 3 2BSYSTEM CONTROL 3 5 Reset System 3 5 1 Reset System Architecture CPU Board Board VDDCORE 2 5V U2 Reset DA9052 Control U21 Level Shifter 2 85V1 8V 04 NOR Flash SN74AVC PC28F256 ERR RESET CN3 SYS UP nRESET 18 ABO Connector nShutdown 58 nRESET 2 85V nRESET 18 Button SW1 nRESET CN6 CN9 J TAG Connector ICE RESET ICE RESET JTAG Connector ws eem nSRESET Figure 3 12 Reset System Architecture CPU Board Board U5 Video Encoder SW 17 ADV7179 nRESET CN7 LCD IF LAN9221 C nRE SET GIO P46 LCD RESET GIO P49 CAM RESETZ CN4 Exp Connector Dd 18 RESETZ Figure 3 13 GPIO Base Reset System for Board User s Manual 41 CHAPTER 3 2BSYSTEM CONTROL 3 6 On Board Interrupts IO Board EM1S DA9052 GIO PO nl RQ Key Matrix Side Switc USB WAKEUP GPIO 1 USB PWR KEY INO GPIO 8 9 10 12
33. 3 2 0 PMIC rev PMIC OTP PMIC rev 7 5 device revision on board 000 DA9052 ES 001 DA9052 A silicon 010 DA9052 B silicon PMIC OTP 4 2 OTP data of PMIC device for initial setting at factory 000 DA9052 0 4 001 9052 0 4 modified 010 DA9052 0 9 Reserved R 20 Reserved Table 5 3 LAN9221 EEPROM Address 0x12 7 6 5 4 3 2 0 BD2 NAND 7 With Without of NAND memory on board 0 Without NAND Flash memory 1 With NAND Flash memory BD1 6 4 Board information Data 1 000 IO board revision 1 001 IO board revision 2 010 111 reserved m 9 0000 1111 reserved Note Do not overwrite any data in Board information User s Manual 111 5 7 Monitor Point and Test Below table is shown points of monitor test input or current measurement use which you can use if it is necessary for you A current measurement point in table can be used for the current consumption measurement by using ampere meter Signal monitor points in table can monitor by using oscilloscope or equivalent equipment Test input points are for use of functionality expansion lt gt Table 5 4 Monitor Point and Test Name Use measurem R139 ent R131 The resistor is ohm and is mounted on 1 8v line for EM1 VIO18 R133 The resistor is ohm and is mounted 2 85v line for EM1 VIO3 R129 The resistor is 0 ohm and is mounted on 1 2V line for EM1 PLL circuit R41 These resistors are 0 ohm and are
34. 49 7021 805 100 Fax 1 408 328 9275 Email dialog nabern diasemi com Email NA_sales_enquiries diasemi com Web http www diasemi com Taiwan Dialog Semiconductor Dialog Semiconductor GmbH Mita Kokusai Bldg 16F Taiwan Branch 1 4 28 Mita Minato ku Chu Nan 3rd Factory No 118 Tokyo 108 0073 Chung Hua Road Japan Chu Nan Miao Li 350 Phone 81 3 3769 8123 Taiwan R O C Fax 81 3 3769 8124 Phone 886 37 598 166 Email dialog tokyo diasemi com Fax 886 37 595 026 Email dialog taiwan diasemi com 04 User s Manual CHAPTER 4 3BCONNECTORS 4 2 7 JTAG Connector CN11 Table 4 17 FFC 12BMEP1 PIN Signa ne i n 2 op _____ 105 CHAPTER 4 3BCONNECTORS 4 2 8 NTSC PAL Connector 71 Table 4 18 MR 551L PN Sina DAC output 1 NTS GND 4 2 9 AUDIO Connector J2 J3 Table 4 19 03 772 0 J2 2 DAC output 1 2 3 MIC IN 1 2 LINE OUT R 3 LINE OUT L LINE OUT 4 2 10 AC Adapter Connector J4 Table 4 21 HEC3600 010520 Type EIAJ 2 Input 5 2 06 User s Manual 4 3 4 3 1 LCD CHAPTER 4 3BCONNECTORS LCD Panel Interface Connector CN7 Table 4 22 23 515 0 35 06 5 Jop mses 6 6 __ 28 46 7 asco oor 47 oao 8 as anoo e ozr CATHODE _ 12 osr 00005 oos osr
35. 6mm User s Manual 27 CHAPTER 2 1BFUNCTIONS 2 2 10 Audio LSI AK4648EC The AK4648 is a stereo CODEC with built in Microphone Amplifier Headphone Amplifier and Speaker Amplifier Recording Function 4 Stereo Inputs Selector Stereo MIC Input Full differential or Single ended Stereo Line Input MIC Amplifier Digital ALC Automatic Level Control Wind noise Reduction Filter Stereo Separation Emphasis Programmable EQ Playback Function Digital De emphasis Filter 5 Band Equalizer Soft Mute Digital Volume Digital ALC Automatic Level Control Stereo Separation Emphasis Programmable EQ Stereo Line Output Stereo Headphone Amp Stereo Speaker Amp Analog Mixing 4 Stereo Input I F 2 Bus Ver 1 0 400 kHz Fast Mode Master Slave mode Audio Interface Format MSB First 2 5 complement ADC 16bit MSB justified 125 Mode DAC 16bit MSB justified 16bit L SB justified 16 24bit 125 DSP Mode Package CSP 3 7mm x 3 8mm 2 2 11 NAND Flash Memory K9F1G08U0A MOUNTED on the board The is a 128M x 8 Bit 256M x 8 Bit NAND Flash Memory Memory Cell Array 128M 4 096K bit x 8bit Data Register 2K 64 bit x8bit Cache Register 2K 64 bit x8bit Automatic Program and Erase Page Program 2 64 Byte Block Erase 128K 4 Page Read Operation Page Size 2K Byte Random Read 25 5 Serial Access 30ns Min 3 3v device 50ns Min 1 8
36. 8 TRSTZ 108 NTS HS SP1 SI 29 icp Bi 169 sro rus 109 GND GND 30 LCD BO JTO TDI GND 50 GND 31 EXT OUT 32K 32 REFCLKO r GND ____ 74 GND GN USB MODE 15 otv pata e 1 37 z __ _ oup ___ orv esre y 3 9 enn ta onp 40 2 ____ 120 2 2 N O N J _ B N ES N N IN W o amp 97 CHAPTER 4 3BCONNECTORS 4 1 7 Power LSI 09052 Monitor CN9 Pin 1 signal is different by the board revision The connection is two types as below Regarding Board Revision please refer to 5 5 Board Revision Table 4 8 BM07B SRSS TB E TT 2 fwa 3 4 2 para 5 6 TP _7 lop 4 1 8 JUMPER JP1 Table 4 9 XJ3B 0311 JP1 1 USB SW from MAX1946 2 USB con from to Mini AB 3 VBUS to DA9052 A photo of DEVICE Mode 2 3 set 98 User s Manual CHAPTER 4 3BCONNECTORS 4 2 10 board Connectors 4 2 1 CPU Daughter Board Connectors CN1 CN2 Table 4 10 SO DIMM CN1 EXT URTO SRIN 424 GIO P4 CAM STBY 82 URTO SOUT GIO P49 CAM RESETZ U
37. 95 oss wes pe js A foss 14 te as oors so fs Jes 9 5 00 me User s Manual 107 CHAPTER 4 3BCONNECTORS 5 5 5 1 USB Connection 5 1 1 USB Mini B Connector by using serial COM port of EM1 USB Mini B connector is USB interface by using EM1 serial COM Port EM1 URTO is connected via FT232R FTDI s USB Serial Converter PC connection is as follows 5 1 1 1 Installation for Virtual COM port driver and USB driver 5 1 1 1 1 Download and extract above drivers from FTDI s support site http www ftdichip com Drivers D2XX htm At the time of May 2009 Click the version number from Driver Version portion 5 1 1 1 2 Power ON CPU and boards 5 1 1 1 3 Connect USB mini B of CPU board to USB A of PC by USB cable 5 1 1 1 4 If the PC detects Unknown USB device you can set up these drivers by PC s instruction 5 1 1 2 Connect PC and CPU and boards via COM port 5 1 1 2 1 Power ON CPU and boards 5 1 1 2 2 Connect USB mini B of CPU board to USB A of PC by USB cable 5 1 1 2 3 Start Terminal Software ex Hyper Terminal Tera Term 5 1 1 3 An example of PC terminal software settings Serial COM port Depend on Virtual COM port driver installation Serial COM port Settings for Board Test Program Baud Rate 115 2k Data 8bit Parity none Stop bit 1 bit Flow Control none Fixed CTS RTS lines
38. B A24 GND 120 NAND V3 00 User s Manual 4 2 2 CHAPTER 4 3BCONNECTORS ABO external CN3 Table 4 12 DF17 4 0 60DS 0 5V 57 PN Signal Signa PN Signa 2 __ 2 AA 42 anar eav eao _ 4 __ op jop 6 zs fams 46 aao 8 ABA 8 faao 48 e JAA agas 49 Jaa 12 __ 3 5 as op 09 5 norascso fo fa foro fe 15 3 fasano 5 ExraBcSt pee 17 sz 59 as 38 ABADS 58 nRESET18 49 60 User s Manual 101 CHAPTER 4 3BCONNECTORS 4 2 3 Enhanced Connector CN4 Table 4 13 DF17 4 0 40DS 0 5V 57 PN _ ____ Sg Pin Signal 5 Nol GND sjo EXT vis rime ____ ____ eno rs ono ss voor _ Jp evo Note these signals are not connected to on default state 10 board because the signal is alternate pin with NTS signal For connection you need resistor mount to IO board Regarding the modification please refer to Modification for signals in external connector CN4 CN5 lt R gt 4 2 4 Enhanced Connector CN5 Table 4 14 DF17 4 0 40DS 0 5V 57
39. Button switches and LEDs on CPU Board 1 Location Please see 1 2 1 CPU Board Image 2 Specification Table 3 11 CPU Board Button Switches Switch Title Type GPIO Explanation amp Assign LED __ For Details Please See Reset System Section 5 2 Debug Switch Slide Type Changes Debug Mode On Debug Mode Off Normal Mode Y Fig TOP View of SW2 Debug On OFF You Should set SW2 to ON when you connect debugger ICE and use it Sw3 o j J NtUsd 0 00 SWA Multi Purpose Push Type EM1 Free Push Button for users Switch GIO P36 Push Down Activated For Detail Architecture Please see 3 9 3 SW5 Multi Purpose Push EM1 Free Push Button for uses Switch Type GIO P71 Push Down Activated For Detail Architecture Please see 3 9 3 LED Green GPIO 14 For Detail Architecture Please see 3 9 3 LED Green GPIO 15 Detail Architecture Please see 3 9 3 LED Green 80 User s Manual CHAPTER 3 2BSYSTEM CONTROL 3 11 2 Key buttons Side Switches LEDs on Board 1 Location Key Matrix switch amp General Purpose LEDs Figure 3 16 Top View of Key Matrix Switches and LEDs 2 Location Side Switches other Switches Please see 1 3 2 IO Board Image User s Manual 81 CHAPTER 3 2BSYSTEM CONTROL 3 11 3 IO Board Switches and LEDs Table 3 12 IO Board Switches and LEDs 1 Switch amp Title Type GPIO Explanation LEDs Assign SW1 5 Side Push
40. C GIO PB8 LCD VSYNC GIO LCD ENABLE GIO P64 1 0 to GIO P71 1 0 PINSEL 364 bt oo oe 1145 fib ___ pcs COS 1 Toe 2524 1 Toe oa 112 o gt _ O o re 62 User s Manual CHAPTER 3 2BSYSTEM CONTROL I KIM 21 20 jo 1948 o _ O w GIO R68 qe x O x o User s Manual 63 CHAPTER 3 2BSYSTEM CONTROL 3 8 7 Pin name initial setting GIO PB83 SDA GIO P84 GIO Paa 1 0 GIO Pea 1 0 PINSEL 380 m o em PINSEL 080 _ 64 User s Manual CHAPTER 3 2BSYSTEM CONTROL 3 8 8 URTO URT1 SOUT ___ URTU CTSB GIO P8 SRIN URTU RTSB P86 URTI SOUT GIO_Pag 1 0 GIO CHG_PINSEL_Gs0 mw LL NN 2726 080 User s Manual 65 3 8 9 00 PINSEL G80 014 0214 CHAPTER 3 2BSYSTEM CONTROL GIO 0 210 P81 1 0 CHG_PINSEL_G80 GIO_P93 GIO Ps4 LN
41. CD Panel Control SPO CS2 Not Used VIO3 lO Expansion Connector CN5 IO Board SP2 Expansion Connector 4 IO Board Pin Multiplexed w DTVIF Note VIO3 is depended on DA9052 programming The concrete voltage can refer to 3 3 2 EM1 DA9052 Connection 7 8 User s Manual CHAPTER 3 2BSYSTEM CONTROL 3 10 Connection Table 3 10 Read Write Address Write Address 7bit Read Address 7bit 4648 0 13 00100115 0 13 00100115 7179 2 01010116 2 01010115 7324 Ox5D 10111015 Ox6D 11011015 Note Write and Read address include R W bit of 8bit s LSB 04 Audio Codec lO Board AK4648 Address IIC SCL W 13h R 13h uc 5 SDA gt SDA 010 K9F1A08U0A IIC SCL NAND WE B ur WE IIC SDANAND_ gt R B ADV7179 IIC Address gt SCLOCK IIC SCL W 2Bh R 2Bh CPU Board 011 GPIO Expander fos MAX7324 IIC Address SCL W 5Dh R 6Dh SDA Os Expansion Connector Key Matrix 24 SideSW SDA BE Figure 3 15 Connection tree User s Manual 79 CHAPTER 3 2BSYSTEM CONTROL 3 11 Dip Switches Keys LED Specs This section describes Power switches Reset button Push switches General Purpose Matrix Key buttons Side Switches and General Purpose LEDs Switches Please see Section x x 3 11 1
42. CSM 0 AASd r0SLdSI v 00S lH3dMOnSA WWEEL AWOOE AE E EEGGA LZZ6NV1 OI Jo Joquu S 21 06 151 19930 151 49430 195 IS User s Manual CHAPTER 3 2BSYSTEM CONTROL 3 3 2 EM1 DA9052 Connection 02 DA9052 EM1 S Y1 Interrupt ni RQ GIO_PO USB WAKEUP 32 U D TANE USB PWR FAULT Xt XOUT IN ier GIO P1 a 32KHz Cloc C32K CN5 ACC ID DET USB ontro Connector SPO CSO Board SELECT J SW20 USB MODE VBUCKCORE VBUCKMEM VBUCKPRO V12 12V VDDOUT 12 VA12 1 2V VDD LDO2 6 a VIO3 2 85V VDD LDO1 3 4 5 7 10 Other Figure 3 6 DA9052 EM1 Connection User s Manual 35 CHAPTER 3 2BSYSTEM CONTROL 3 3 3 Power down Control for Board device Table 3 2 Power down control for board devices Device Explanation Type CPU amp Combination of EM1 S and DA9052 is able to realize various power Power LSI down modes For detail Information EMMA Mobile1 S Data Sheet and User s Manual and DA9052 Data Sheet Mobile DDR MT46H32M32LF This device has DPD Deep Power down mode When EM1 S send DPD command to MT46H32M32LF by way of memory interface the device enters to DPD mode For detail information Please see MT46H32M32LF data sheet MTFC4GDKDI No power down mode
43. Control e Chapter 4 Connecters e Chapter 5 Others 4 How to read this manual It is assumed that the readers of this manual have general knowledge of electricity logic circuits and microcontrollers To understand the functions of the board of 1 in detail read this manual according to the CONTENTS To understand LSI functions of EM1 refer to the user s manual of the respective module To understand the electrical specifications of EM1 refer to the Data Sheet 5 Conventions Data significance Higher digits on the left and lower digits on the right Note Footnote for item marked with Note in the text Caution Information requiring particular attention Remark Supplementary information Numeric representation Binary or Decimal Hexadecimal Data type Word 32 bits Half word 16 bits Byte 8 bits 6 Major revised point The revised points can be easily searched by using an lt R gt in the PDF file and specifying it in the Find what field DISCLAIMER This user s manual and development kit board is intended for the evaluation of the Emma mobile 1 and is not intended to be included as part of any final product The designs contained in this document are for reference and example purposes only The information in this document is subject to change without notice No part of this document may be copied or reproduced in any form or by any means without the pri
44. D 0 15 RJ45 AB A 11 AB A 1 24 LAN I F AB A7 LANTE Connector AB A6 line AB A2 AB ALI FIFO SEL U3 EEPROM LAN AB CS3 nCS 93 46 6 AB WR GIO P44 LAN9221 RESET GIO PA41 LAN INT VI O18 Figure 3 21 LAN9221 ABO Connection 98 User s Manual CHAPTER 3 2BSYSTEM CONTROL 3 14 Touch Screen Board DA9052 LCD Connector TSI YN GPIO 3 TSI YP GPI O 4 TSI XN GPIO 5 SPU Coe TSI XP GPIO 6 line TSREF GPIO 7 IO Board LCD Connector LCD Figure 3 22 Touch Screen Control System User s Manual 89 CHAPTER 3 2BSYSTEM CONTROL 3 15 DDR Setting BAO BA1 signal connections are different by the board revision The connections are two types as below Please refer to 5 5 Board Revision about how to recognize And these connections also can recognize by DDR BA01 bit of EEPROM Address s 0x10 of LAN IC on software point of view Please refer to 5 6 Board Information EEPROM EM1 DDR Board Rev 1 EEPROM 0x10 DDR BAO 1 bit 5 0 2 EEPROM 0 10 DDR BAO 1 bit 5 1 MEMC registers in next table is recommendation setting value Regarding MEMC DDR it is different number related to Board revision The EEPROM information can be confirmed by 5 6 Board Information in EEPROM Address Data 0x14141414 0x00000000 0x000F0A03 0x0000000F 0x54443203 0x20DA1042 0x00000
45. DD or GND via a resistor if there is a possibility that it will be an output pin All handling related to unused pins must be judged separately for each device and according to related specifications governing the device 3 PRECAUTION AGAINST ESD A strong electric field when exposed to a MOS device can cause destruction of the gate oxide and ultimately degrade the device operation Steps must be taken to stop generation of static electricity as much as possible and quickly dissipate it when it has occurred Environmental control must be adequate When it is dry a humidifier should be used It is recommended to avoid using insulators that easily build up static electricity Semiconductor devices must be stored and transported in an anti static container static shielding bag or conductive material All test and measurement tools including work benches and floors should be grounded The operator should be grounded using a wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken for PW boards with mounted semiconductor devices 4 STATUS BEFORE INITIALIZATION Power on does not necessarily define the initial status of a MOS device Immediately after the power source is turned ON devices with reset functions have not yet been initialized Hence power on does not guarantee output pin levels I O settings or contents of registers A device is not initialized until the reset signal is received A reset ope
46. G regisiter Polarity 1 active HIGH IRO CFG register buffer type 1 PushPull type 44 GIO P44 LOW LAMBPPI reset User s Manual 47 CHAPTER 3 2BSYSTEM CONTROL 46 20 214 LW panel reset P47 for Board revision 1 USB ISP1504 Low Chip Select Active GIO P47 High Power Down mode GIO P47 for Board revision 2 EM1 USB PHY USB3329 Active Lo P47 RESETB Note Regarding Board revision please refer to 5 5 Board Revision and 5 6 Board Information in EEPROM User s Manual CHAPTER 3 2BSYSTEM CONTROL 51 shmitt inverter 10k cie oie push HIGH ogen 94 94 Glo alo User s Manual 49 CHAPTER 3 2BSYSTEM CONTROL 3 7 2 0 9052 Table 3 5 DA9052 GPIO PAD USEmodeDPSW uss wae oo wym ou GPIO_13 nVDD_FAULT 1946 50 User s Manual CHAPTER 3 2BSYSTEM CONTROL 1 USB HOST DEVICE mode change switch definitian GPIO 1 DEVICE 1 2 HIGH HOST 2 3 SPIO 2 DADS 2 EMT LIS B WAKELIP GPIO 2 is connected to WAKEUP signal as an interrupt factor TSIYX TSIYP TSIXN T
47. MPER JP 1 about JP1 and Table 3 15 IO Board Switches and LEDs 2 about SW20 Table 3 3 CPU Board JUMPER JP 1 p Setting 1 USB SW from MAX1946 E 2 USB con from to Mini AB USB DEVICE MODE 3 VBUS to DA9052 1 USE CASE1 VBUS power supply USB VBUS power supply can drive CPU board only USB power cannot drive CPU board and board configuration JP1 2 3 must be shorted CN5 USB Mini AB USB Power Supply 5V 500mA DC Figure 3 7 CPU Board 2 USE CASE2 AC adapter power supply CPU Board and Board configuration is supplied by AC adapter J4 5V IN 5 AC adapter Figure 3 8 CPU Board and Board User s Manual 37 CHAPTER 3 2BSYSTEM CONTROL 3 3 5 Backup Battery R One coin battery is mounted on the board for power source of the RTC in DA9052 This coin battery is MLA14 capacity is 1 2mAh When the AC adapter or the Lithium ion battery is connected to this board coin battery charge starts automatically ML414 is Rechargeable Li ion battery The battery must avoid using till fully low voltage When the Development Kit Board is not used during long time please detach the coin battery Please remove the battery when the coin battery performance has deteriorated ML414 e faa C n T Figure 3 9 Position of ML414 38 User s Manual CHAPTER 3 2BSYSTEM CONTROL 3 4 C
48. Manual 1 INTRODUCTION Development Kit Board is a reference design board which is mounted a EMMA Mobile 1 This document is information for a software development the demonstration and hardware evaluation The Development Kit Board on EMMA Mobile 1 is embedded low power SOC The board is including components debug l F Function system control Connecter Restriction and more 1 1 Overview The major components of the boards are described below CPU Board IO board LCD 1 1 1 CPU Board PCB 8 layers LSI EMMA mobile S uPD77630A Mobile DDR SDRAM 1Gbit 8 Meg x 32 x 4 Banks FLASH ROM eMMC NAND FLASH 4Gbyte IO board Interface LCD Interface JTAG ICE IF Special Header TET SICA20C20Y GA102 Micro SD Card IF USB Mini AB Interface Com Port Interface USB mini B General purpose switch 2 General purpose LED 2 Sound interface LINE OUT 1 1 2 IO board PCB 6 layers CPU Board Interface LCD Interface NTSC interface RCA Jacks Sound interface LINE OUT MIC 1 Channel Ethernet interface RJ 45 General purpose switch matrix 14 General purpose LED 4 JTAG ICE IF Mictor Expansion interface User s Manual 15 CHAPTER 1 OBINTRODUCTION 1 1 3 LCD Panel Manufacture NEC LCD Technologies Ltd Product NL8048HL 11 01B Type TFT Active matrices LCD Size 99 6 H x 69 5 V x 5 0 D mm typ Interface FH23 51S 0 3SHW HRS Touch Panel Control SPI Color 16777216 8 b
49. Mobile1 S CPU LSI The EMMA Mobile1 is a multimedia processor for mobile applications and low power applications that integrates a logic chip incorporating a CPU and DSP in one package ARM1176JZF S 500 32 KB D cache 32 SPXK701 Max 500 32 KB D cache 32 KB controller Image processing Image processor resizing filtering etc Image rotator 0 90 180 270 Graphics DMA ROP and FILL Image composer LCD output image synthesis 264 4 accelerator Peripheral interfaces Memory interface External bus interface 16 bits Flash memory etc NAND interface Serial interfaces UART I2C audio voice SPI IrDA SD card interface with SDIO Image related interfaces LCD interface terrestrial digital TV interface DTV ITU R BT656 interface NTS General purpose interface ULPI interface Package 481 pin fine pitch BGA package 12 7x12 7 mm 2 2 2 Power LSI DA9052 The DA9052 is a highly integrated PMIC subsystem with supply domain flexibility to support a wide range of application processors associated peripherals and user interface functions Switched DC USB Charger with power path management 4 Buck Converters have DVS 0 5V 3 6V up to 10 Programmable LDO s High PSRR 1 accuracy power Backup Charger 1 1 3 1V up to 6mA 32kHz RTC Oscillator General Purpose ADC with touch
50. N 8 x 8mm EEPROM interface for MAC address storage LAN9221 can load the MAC address automatically after reset 26 User s Manual CHAPTER 2 1BFUNCTIONS 2 2 T USB PHY ISP1504 or USB3329 USB PHY is used as next two options on the board And the USB phy is different by board revision The board information can be confirmed by 6 3 Board Revision and 6 4 Board Information in EEPROM Please refer to USB PHY bit of EEPROM Address s 0x10 for the revision recognizing of software view point The ISP1504 is USB 2 0 Transceiver as below Universal Serial Bus Specification Rev 2 0 On The Go Supplement to the USB 2 0 Specification Rev 1 2 UTMI Low Pin Interface ULPI Specification Rev 1 1 Interfaces to host peripheral and device cores optimized for portable devices or system ASICs with built in USB OTG device core Complete Hi Speed USB physical front end solution that supports high speed 480 Mbit s full speed 12 M bit s and low speed 1 5 M bit s Complete USB physical front end that supports Host Negotiation Protocol and Session Request Protocol SRP Highly optimized ULPI compliant interface 60 MHz 8 bit interface between the core and the transceiver Package 36balls TFBGA 3 5 x 3 5 The USB3329 is USB 2 0 Transceiver as below Highly integrated Hi Speed USB 2 0 transceivers Integrated VBus over voltage protection up to 30V Integrated USB switch Internal ESD protection circuits No extern
51. PIO Base Reset System for Board 41 IRQ Tree of EM1 Development Kit 42 a eed uM M 79 Top View of Key Matrix Switches and 1 81 DSW 1 Photo and Top view 84 Key Buttons and Side Switch System 85 Key Buttons and Side Switch System 86 Audio Circuit Block uu ud 87 CONNECCION 88 Touchscreen Control u u e ua un bec or bee bx ict bee uec Epp dees cs 89 Qc T 109 User s Manual 9 Table 2 1 Table 3 1 Table 3 2 Table 3 3 Table 3 4 Table 3 5 Table 3 6 Table 3 7 Table 3 8 Table 3 9 Table 3 10 Table 3 11 Table 3 12 Table 3 13 Table 3 14 Table 3 15 Table 3 16 Table 4 1 Table 4 2 Table 4 3 Table 4 4 Table 4 5 Table 4 6 Table 4 7 Table 4 8 Table 4 9 Table 4 10 Table 4 11 Table 4 12 Table 4 13 Table 4 14 Table 4 15 Table 4 16 Table 4 17 Table 4 18 Table 4 19 Table 4 20 Table 4 21 Table 4 22 Table 5 1 Table 5 2 Table 5 3 Table 5 4 Table 5 5 LIST OF TABLE Title Page D RETE EET 24 Power System me e 34 Power down control Tor board devices essa RU 36 CPU Board JUMPER NER uu uuu
52. Power System Configuration 3 3 1 Power System Configuration Table 3 1 AYOOCGA 9 dA 62 6 0 99A LNOGGA 4019euu02 uolsuedxg 10 1 V8A GL Synour JOMOd ZGOBVG END 19 5 08V AZ vw 6001 Rt 6NO 9NO 9 05 39 END ON 1X3 c AS8 7 uoisuedx3 5214 GNVN 809136 1001 20 08V NO VUI0Z AOL 6 21 AOL GOT 00 901 9 5 9 lt 9 1nOGGA vod gt JOUIO 00 OIA ds 1 2 dA A9 742 OWINS END 0gv wem EAZATATSINA AZ iod VUOLATSUNS zm dA AO0 E 0 99A 45214 HON 9924829 9094 8 SLOIA FYOOMONAA 960L A8 L OI LCC6NV 1 AZ 8LOIA SIAE JI OC
53. ROL oth i0 Lo 17 15 C014 0204H 15 14 GIO P23 Les Register 4 09 09 ____ ABOBENI 705 29 28 86 BENO 05 ABO CSB3 05 ee 009 00 ob __ CHG PINSEL G16 set value 23 22 01b ABO WAIT NTS 00b PINSEL 632 17 16 2 ss 98 ABOA25 09 Lo Ot a 11 10 AB0_A26 User s Manual 57 CHAPTER 3 2BSYSTEM CONTROL 3 8 2 PMO name initial setting SEN SI PMO SO Glo PFB 1 0 PINSEL G80 6 ____ 31 30 PWM1 00b wwo w nano 25 24 P92 01b oe oe 19 18 GIO P89 01b PINSEL G80 020 0 05 0 2 13 12 GIO P86 RTSB GIO PB 10b we a qom 58 User s Manual 3 8 3 5 5 1 Glo CHG PINSEL G64 014 0210 CHAPTER 3 2BSYSTEM CONTROL Fin MTS NTS MTS NTS HS HTS MTS 1 4 IH Prai CHG PINSEL 364 Pin name o x d INTS DATAS NTS HTS DATA Gk PO 1 40 i 137 CHG PINSEL GBO alternative pins list bit 31 30 29 28 27 26 rom fo 25 24 2532 GIO User s Manual
54. RT1 SRIN CAM SCLK CAM _______ fea uRTi sour 124 sD __ Fu GND SD1 DATA3 CAM HS ss o 126 sp DAIA CAM vs au ico es lar R o _ a e pa la SD1 DATA1 CAM YUV7 aha a hua a M NNNM 11 LED CATHODE 51 GND 91 NTS DATA5 PM1 SE 131 SD1 CMD CAM YUV5 12 LED CATHODE2 52 GND 92 NTS DATA6 PM1 SI 132 501 DATA4 CAM YUVA GND 15 GND GND GND 5 DATA1 CAM YUV1 5 o s o o Jo 136 nts DATA0 SP1 SO CA _ 18 __ 18 __ 58 nc fo prowess 198 AGND 19 SPO CLK 18 SDA 99 GIO P10 WFl4 AGND SPO SO 18 IIC SCL GIO P10 WFIS3 MPWR GIO P10 WFI2 21 GND 61 22 o 162 op 410 Powe 12 C n M E TES LCD PXCLK2 o 106 ler __ sro 107 nts vs spi cik _ GND 68 2 108 poosi fe amas poe fow 3 __ 29 op 4 LCD B2 72 __ 3 ____ 73 oon __ eoon J 3 o zs uss pipt 36 __ __ 9082 cpio 3 Jiwsi jur pap s __ ____ 78 tv sync 3 __ emo que joo so
55. SIXPAGGPIO 3 4 5 8 TSPrNAGPIO 3 TSTYP GPIO 4 TSIXNA GPIO 5 je TSIXP GPIO 6 4344 45 46 XL YD XR YU LC D E NA User s Manual 51 CHAPTER 3 2BSYSTEM CONTROL TSREF amp GPFIO 7 TSREF GPIQ 7 VL DOS TSREF is connected ta VLDO9 2 5 It is a reference voltage af touch panel interface GPIG GPIO 8 GPIO 10 GPIO 12 ACC ID DET amp GPIQO 11 USB connector ALL ID DET ID 11 52 User s Manual CHAPTER 3 2BSYSTEM CONTROL GPIO13 for Board Revision 1 nVDD FAULT GPIO13 D9052 CNO9 for PMIC Mon nVDD 79 GPIO13 for Board Revision 2 GPIO13 nVDD FAULT D9052 CNO9 for PMIC Mon nVDD 79 MAX1946 USB SW Note Regarding Board revision please refer to 5 5 Board Revision and 5 6 Board Information in EEPROM GPIO 14 15 W 249052 for EVE R121 6800 GPIO 14 GPIO 15 J LOW LED ON HIGH LED Mormalhy nothing is connected to EYB is connected to when evaluating DASOS2 User s Manual 53 CHAPTER 3 2BSYSTEM CONTROL 3 7 3 7324 Table 3 6 MAX7324 GPIO P nemaak T 10 11 AX 7324 key matrix EXT VIO3 R40 R41 R42 R43 4 3300 012 13 14 15 LEDS LED4 MAX7324 O12 013 O14 O15 LOW LED
56. able 4 1 SICA20C20Y GA102 13 JTO TDI 15 ICE RESET 4 1 2 SD Interface Connector CN2 Table 4 2 DM3AT SF PEJ User s Manual 93 CHAPTER 4 3BCONNECTORS 4 1 3 LCD Interface Connector CN4 Table 4 3 23 515 0 35 06 PIN Signal ___ 021 R GND ANODE CATHODE adore PT 94 User s Manual CHAPTER 4 3BCONNECTORS 4 1 4 USB Interface Connector CN5 Table 4 4 56579 0579 PIN Signal ___ Signal a fvus e js 2 7 smeo 3 fo js 419 9 smeo 4 1 5 USB Interface from UART Connectors CN6 Table 4 5 UX60SA MB 5ST PIN Signa PIN __ Signa 1 VBUSNC 6 SHED SHIELD 2 D 3 p 8 so a 9 022 User s Manual CHAPTER 4 3BCONNECTORS 4 1 6 Peripheral Connector CN7 CN8 Table 4 6 SO DIMM CN7 hows a ae ire craton forve _ 2 __ ____ 42 o ut oi 122 ext vir 2 __ 43 lenn 8 02 123 EXT v12 4 D3 124 EXT V12 j He M LN 6 VBAT 46 AB AD1 86 NAND D5 126 EXT V15 7 AB AD2 NAND D6 127 EXT V15 9 AB A1 AB AD4 29 EXT V18 EXT V18 11 AB A3 AB AD6 12 AB A4 AB 2 SCL NAND WE EXT V18 2 SCL NAND 133 93 EXT V285 14 AB_A6 94 GIO P7 NAND CEO 134 EXT V285 15 7 GND 95 URT2 SRIN NAND ALE 135 EXT V285
57. al ESD protection circuits required Integrated 3 3V LDO regulator Ability to use the USB connector as single port of connection Switch Hi Speed data battery charging and stereo mono audio accessories mode Variable I O voltage capability power and standby modes of operation to minimize power consumption jitter PLL makes it possible to accept noisy clock sources Supports commercial 0 to 70 C and industrial 40 to 85 C temperature ranges 2 2 8 COM Port FT232RQ The FT232RQ is a USB to serial UART interface Single chip USB to asynchronous serial data transfer interface Entire USB protocol handled on the chip No USB specific firmware programming required Fully integrated 1024 bit EEPROM storing device descriptors and CBUS configuration Supports bus powered self powered high power powered USB configurations UART signal inversion option UHCI OHCI EHCI host controller compatible USB 2 0 Full Speed compatible Package 32pin QFN 5 x 5mm 2 2 9 TV OUT ADV7179KCPZ The ADV7179 is a Video Encoder transfer to PAL NTSC from ITU R1 BT601 BT656 YCrCb 10bit video DAC Multi standard video output CVBS Y C Video input data port CCIR 656 4 2 2 8bit parallel format Composite S video simultaneous output or RGB SCART YUV video output can be set 2 wire MPU serial interface I2C interchangeability and Fast 12C Package 40 pin LFCSP 6x
58. cc EMEN 7 2 User s Manual CHAPTER 3 2BSYSTEM CONTROL 3 8 12 PWM Pin name PWM initial Setting PWW0 GIO GIO P95 GIO Pe4 1 0 GIO Pes 1 0 PINSEL 380 ternative pins list Register 05 405 EMI Lo 29 28 PWMO 27 26 P93 _ PINSEL G80 Poa Manual 73 CHAPTER 3 2BSYSTEM CONTROL 3 8 13 USB Fin name xx USB CLK GIO USB DaTA o7 GIO 7 104 USB DIR _ 105 USB GIO 106 USB GIO 107 GIO Pa6 1 0 to GIO P107 1 0 H l3 95 01 Pin name GIO P1 setting 10 USE WAKEUP 058 PWR GIO Pi GIO 1 1 9 PINSEL 500 p 31 30 GIO_P111 URT2 RTSB 2322 CHG_PINSEL_G96 copo set value 10b 10b 10b 10b 01b 01b 01b 01b 01b 01b 01b 01b 01b 01b 01b 01b 7 4 User s Manual CHAPTER 3 2BSYSTEM CONTROL 402 09 _ _ _ 2 alternative pins list PINSEL G00 17 16 NAND CE1 C014 0200H 15 14 GIO P7 User s Manual 75 CHAPTER 3 2BSYSTEM CONTROL 3 8 14 OSC PLL2 name REFCLKO initial setting OSC12M OUT 01 PINSEL 0 PINSEL
59. ckage solated Multimedia Card MMC interface 4G Byte Flash Memory Package 169 Ball FBGA 12 x 16mm MMC Specification MMC system specification version 4 2 MMC mode protocol compliant Advanced 10 signal interface X1 x4 and x8 1 05 selectable by host mode operation Command classes 550 basic Class 2 block read Class 4 block write Class 5 erase Class 6 WRITE protection Class 7 lock card MMOplus and MMCmobile protocols Password protection Permanent and temporary write protect Supports basic file formats 52 MHz clock speed MAX 416 Mb s data rate MAX backward compatible with previous MMC modes ECC and block management implemented 2 2 5 NOR Flash Memory PC28F256P30B85 PC28F256P30B85 is NumonyxTM StrataFlash Embedded Memory 256MBit 100 ns initial access 25 ns 16 word asynchronous page read mode 52 MHz with zero WAIT states Buffered Enhanced Factory Programming at 2 0 MByte s Typ using 512 word buffer 1 8 V buffered programming at 1 5MByte s Package 64 Ball Easy BGA 10 x 13mm 2 2 6 Ether LAN9224 LAN9221 is a Highly performance 16bit Non PCI 10 100 Ethernet Controller Host bus interface 16bit data bus 1 8 to 3 3V variable voltage I O accommodates wide range of I O signaling Integrated PHY with HP Auto MDIX support Integrated checksum offload engine helps reduce CPU load Package 56 QF
60. e 3 22 Figure 5 1 LIST OF FIGURES Title Page IG u EI TUS 16 CPU BoardAmage MM 17 ri i om 19 19 IO Doard Image ors 20 ACIDC Adapter 21 CRU 22 Debug lite race TONGI cL 23 System Block Saim ag 29 EMMA Mobile ALL Memory Bank ________ ______ 30 EMMA Mobile1 NOR and Asynchronous Bus0 No 0 Memory Map 31 EMMA Mobile DRAM Memory 32 Power System Architecture 33 press ON 35 COP BGAN Ce 37 GPW Board uuu e 37 POSIHOL or 38 Clock Source on CPU ice 39 Clock Source on BO ane TEUER 40 PRESETS VISES Ue d 41 G
61. f CPU board and 10 board for connection of CPU and 10 board Table 5 5 Modification signal in external connector Board Connec Signal pon Default Modification for Alternate signal tor Note 1 use case Note 2 NTS DATA1 NTS DATA3 NTS_DATA4 SP1 SO CAM YUVO NTS DATAO SP1 CS1 CAM YUV2 NTS DATA2 Note1 means not mounted component Note2 After the modification please take care about output signal s wired or Alternate signal cannot use at the same time For the example YUV1 from camera component and NTS DATA1 from is output signal You should not use camera interface and NTSC interface after the modification Regarding place of R78 R87 please refer to following photo 149 _ 1 mnn 2 inm NIIILL ie T FPYFYTYTYIEITITIYIIIITIIIIIIUVI TIYYEITEFTITTL LI W W i LE LJ L T W 4 t i k h 5 113 R 5 9 Connection of CPU board and IO board CPU board and 10 board is connected by two couple of 150 pin connectors If you detach the connectors for a reason please carefully refer to a following procedure for attaching the connectors Step 2 Put CPU board on 10 board Be careful Step 3 Push the connector toward inside and Step 4 Confirm whether metal parts fold a plastic downward with holding the metal parts part about four portion in the side view
62. it digital RGB Pixel 800 H x 480 V 99 6 mm 69 5 esocesececosscececeooseceeececeececeececochmmhececcecciccceoo Figure 1 1 LCD Image CAUTION LCD board has bonded on PCB through Acrylic fiber board LCD must not detach on e That would cause the breakdown which cannot recover 6 User s Manual CHAPTER 1 OBINTRODUCTION 1 2 Connectors 1 2 1 CPU Board Image Debug IF DSW1 Boot mode switch J1 AUDIO Line OUT 5 2 Debug enable Switch 1 inim Ji Sw4 Multi purpose Switch Sw1 Reset Switch Anm 1 P SW5 Multi purpose Switch E md Ir _ SL 7 PS ale te JP1 Jumper LED3 PowerLED CN5 Mini USB AB CN7 SO DIMM Back CN8 SO DIMM Back CN6 COM Port USB Figure 1 2 Board Image User s Manual 17 CHAPTER 1 OBINTRODUCTION CN1 Debug IF Special Connecter that attached SICA20C20Y GA102 CN2 Micro SD Card IF CN4 LCD Interface CN5 Mini USB AB CN6 COM Port USB Mini B CN7 CN8 SO DIMM Back CN9 EVB IF JP1 Jumper VBUS line switch to HOST mode DEVICE mode J1 AUDIO JACK LINE OUT DSW1 DIP Switch Boot mode Select SW1 Reset Switch Board system reset SW2 Debug Switch Debug enable Sw4 SW5 Two general purpose push Switches 18 User s Man
63. le 5 3 LAN9221 EEPROM Address 0x12 gt IH 0 With memory 1 Without NAND memory User s Manual 115
64. le DRAM Memory 32 User s Manual CHAPTER 3 2BSYSTEM CONTROL 4l MESS 1X3 uoisuedx3 1 3 2 Jl 09 31921 41 aoi 155 48410 en i 8091463 nS di Ln c H9tv LIN WA 3196865 zozewav YON PA 95248294 2 4 lt SLOIA sn 4 LA SLN OIHVAQGAJAe dsnie 29 n eyn 9455544 ab _ en 7 ud asn 9yn 2709145 gsn 49 LLN VeEZXVIN Power System 3 3 1S0H NI 100 3 AS XV M asn MS ESN ZIN 2 J9MOd LIN 94440 NOIN 16 9 LOATA jndu 1V8A Are p N9 Mpeg IDDAA jndu vf 4 wo NI 9d AS s Figure 3 5 Power System Architecture 33 User s Manual CHAPTER 3 2BSYSTEM CONTROL
65. lock System 3 4 1 LNO lX3 d21 495 WYD 43 ZISIM T Td 019 khs XID 19 TdS il 19 145 152 12 045 19 045 19 312 SLN Ewa pomo bomo SIN praese HAAD Lexus 05 _ 3015 QS042 IN CEN OLu 39L 041 19S WYD TNO O12433 8 2 9N JS 0520 0 045 CPU Board Clock Tree Structure MOL Olf 2 313 ZdS 128 gt lt u 9 e S x19 12 SLN 251 ZHINLZ 8 ZND UIJWWId OS LL Z1V1X ZHINO 9 TIVLX 2 89 Jr OSIdSI asn 9TN 0250 495 STN _ LNO 1X4 aol ZH MAE 2 89 OND WZI 250 oso IID 250 ZHINO 39 Figure 3 10 Clock Source on CPU Board User s Manual CHAPTER 3 2BSYSTEM CONTROL 3 4 2 Board Clock Tree Structure JTAG SO DI MM ewe CN1 201 n Out JTO RTCK es TO NTS 1 CL SP1_ 775 BCLK 5 2 CLK ee EXT_OUT_32K GIO P11 WIFI2 ABO CLK GIO P
66. nd safety of Shimafuji products customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely To minimize risks of damage to property or injury including death to persons arising from defects in Shimafuji products customers must incorporate sufficient safety measures in their design such as redundancy fire containment and anti failure features f customers wish to use Shimafuji products in applications not intended by Shimafuji they must contact an Shimafuji sales representative in advance to determine Shimafuji willingness to support a given application Note 1 Shimafuji as used in this statement means SHIMAFUJI Electric Incorporated and also includes its majority owned subsidiaries 2 Shimafuji products means any product developed or manufactured by for Shimafuji as defined above 4 User s Manual 1 5 This manual is intended for hardware software application system designers who wish to understand and use board functions of EMMA Mobile1 EM1 a multimedia processor for mobile applications 2 Purpose This manual is intended to explain to users the hardware and software functions of the board of EM1 and be used as a reference material for developing hardware and software for systems that use 3 Organization This manual consists of the following chapters Chapter 1 Introduction Chapter 2 Functions e Chapter 3 System
67. not mounted 4Gbyte LCD Direct Connect IF Audio IF Audio mini Jack Line Out x1 USB IF miniAB Connector x1 CPUBoard MicroSD Card Slot x1 Debug mini JTAG IF Special for ARM Only USB IF for Console miniB Connector x1 Console IF COM Port Interfaces LCD WVGA Size Supports Touch Screen Back light Audio IF Audio mini Jack MIC In x1 Line Out x1 TV Out NTSC PAL LAN I F RJ45 Board Debug mictor type connector x1 General purpose Connector for WLAN BT DTV Camera Module ASYNC Expansion Connector x1 CPU Board IO Board Connector EM Connector Switch x2 LEDs x 2 for General purpose Power LEDx1 CPU Board Dip Switch Boot mode select Debug enable Button SW USB VBUS route select Jumper LED etc Key switch 3x4 LCD side side switch x2 IO Board LEDs for General purpose x4 Dip SW ARM DSP ICE selection Power DC Power supply 5V 2A EIAJ2 Source Li lon Battery Connector Only USB VBUS power supply Board Structure CPU Power LSI Charge function Supports Li lon battery Charge by DC Power supply or USB VBUS R Size Case 154 x 88 x 32mm approx CPU Board PCB 55 6 x 70 0 mm typ IO Board PCB 140 0 x 70 0 mm typ RoHS EU Support AC adapter Electrical Appliance and Material Safety Law Support PSE MARK UL CUL CE CB BSMI Quality Specs Standards Support 24 User s Manual CHAPTER 2 1BFUNCTIONS 2 2 Parts Detail Descriptions 2 2 1 EMMA
68. oard GPIO Expander on IO Board 10 NANDPAD URTO 10 FT232 USB Serial Adaptation LSI on CPU Board RS232 URTO IO Board te Expansion Connector CN4 5 Board URTI URT2 l __ NAND PAD VI O3 Camera VI O18 Expansion Connector CN4 5 VI O18 VI 10 Please GPI O Spec Section 03 Note VIO3 and VIO18 are depended on DA9052 programming The concrete voltage can refer to 3 3 2 EM1 DA9052 Connection User s Manual 77 CHAPTER 3 2BSYSTEM CONTROL 3 9 2 External Bus Chip Select CSBO to CSB3 R Table 3 8 External Bus Chip Select CSBO to CSB3 CSBO VIO18 NOR Flash ABO 50 WAITCTRL 0x02000502 nome 3 ABO CS0 WAITCTRLW 0x00010302 T2 Wz1 T1 W 23 W 2 CSB1 VIO18 Not used CN3 Note1 CSB2 VIO18 LAN9921 as CSB3 VIO18 Ether IF ABO CS3WAITCTRL 0x01000300 ABO CS3WAITCTRL W 0x00000300 Wet TO et _ Note 1 CSB1 is not used in Design Kit Board but is connected to CN3 of IO board for external board 2 CSB2 of chip select signal is not used but it is connected to LAN9921 nRESET as GIO P44 of alternating pin function 3 VIO18 is depended on DA9052 programming The concrete voltage can refer to 3 3 2 EM1 DA9052 Connection 3 9 3 SPI Chip Selects R Table 3 9 SPI Chip Selects Voltage V Board Connection Note SPO CSO 249052 For Control SPO CS1 VIO3 jO LCD For L
69. of making The inquired window address telephone number and the content and the address etc on the homepage might have been changed Please acknowledge it beforehand To mean mark In this document the item to use the product safety has been described as follows ag When you cannot defend the content of the description You damage to personal to harm and the property It is assumed that the user owes the death or the serious illness note 1 and shows the content with high risk The content that the user owes the death or the serious illness WARNING is shown A DANGER AN The people receive injury note 2 Receive the property CAUTION damage note 3 1 Definition of serious illness Losing sight injury Burn high temperature and low temperature Electric shock Fracture The one that squealed remains because of poisoning etc and the one to require going to hospital regularly that hospitalizes and is long term to treat note 2 Definition of injury The one to require hospitalization and a long term going to hospital regularly to treat is said note 3 Definition of property damage It is damage to the building and equipment Alarm display in board products use a The demand handling of the product is classified as follows is a mark that prohibits the act General prohibition Example Contact prohibition The described act is prohibited C The possibility of owing injury by to
70. or written consent of RENESAS Electronics Corporation RENESAS Electronics Corporation assumes no responsibility for any errors which may appear in this document RENESAS Electronics Corporation does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device No license either express implied or otherwise is granted under any patents copyrights or other intellectual property rights of RENESAS Electronics Corporation or others User s Manual 5 Related Documents User s Manual Caution The related documents listed above are subject to change without notice The related documents indicated in this publication may include preliminary versions However preliminary versions are not marked as such Be sure to use the latest version of each document when designing 6 User s Manual 5 CHAPTER 1 INTRODUCTION Mer mr 15 15 LLL 15 UM 6 OU NEN 15 J To 16 12 CONNECTORS nam 17 L2 1 OPU Board estu ta a LI IE M 17 1 2 7 Id S noce NI __ __ 19 1 94 21 1 4 IDEVELOPMENT TOOLS CONNECTION 22 id
71. r Image TBD 5 5 Board Revision Board revision can be confirmed a character on PCB as below Information of Board revision 190441002 1 190441002A Rev2 There is a case that some mounting components are different by a revision of the board Please refer to BOM of the board about the detail information And recognition way for software of board revision can be confirmed in 5 6 Board Information in EEPROM 10 User s Manual 5 6 Board Information Factory setting Development Kit board has information for clarification of board revision on software point of view And the information is related on Board Revision The information is in EEPROM of Ether IC LAN9221 in IO board as below Do not overwrite any data in Board information These data are needed for software to work normally R Table 5 1 LAN9221 EEPROM Address 0x10 7 6 5 4 3 2 1 0 EM1 S D USB PHY DDR BAO1 Name R Bits Contents EM1 S D T EM1 device name on board 0 EM1 S 1 EM1 D USB PHY R USB PHY device name on board 6 0 NXP ISP1504 1 SMSC USB3329 DDR BAO1 5 Two connection between EM1 and DDR P NEIN 0 BAO BA1 and BA1 BAO 1 BAO BAO and 1 1 eMMC 4 eMMC device name on board 3 DDR device name on board 0 Micron MT46H32M32LF without Auto Self Refresh function 1 TBD with Auto Self Refresh function Reserved 222 Reserved 20 Table 5 2 LAN9221 EEPROM Address 0x11 7 6 5 4
72. ration must be executed immediately after power on for devices with reset functions 5 POWER ON OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface as a rule switch on the external power supply after switching on the internal power supply When switching the power supply off as a rule switch off the external power supply and then the internal power supply Use of the reverse power on off sequences may result in the application of an overvoltage to the internal elements of the device causing malfunction and degradation of internal elements due to the passage of an abnormal current The correct power on off sequence must be judged separately for each device and according to related specifications governing the device INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or pull up power supply while the device is not powered The current injection that results from input of such a signal or I O pull up power supply may cause malfunction and the abnormal current that passes in device at this time may cause degradation of internal elements Input of signals during the power off state must be names of other companies and products are the registered trademarks or trademarks of the respective company The information in this document is current as of August 2008 The information is subject to change without notice For actual design in refer to the late
73. screen interface High voltage white LED driver 24V 50mA Boost 3 strings 16bit GPIO bus for enhanced Wake up and peripheral control Dual serial control interfaces Unique USB supply detection and charge current selection Unique ID code capability via OTP memory Package 86LD UFNBA QFN 7x7 2 2 3 DDR SDRAM MT46H32M32LFCM 6 The MTH32M32LFCM 6 Mobile is a Low Power DDR SDRAM Cycle time 6 ns 32 Meg x 32 8 Meg x 32 x 4 banks Package 90 Ball VFBGA 10 x 13mm User s Manual 25 CHAPTER 2 1BFUNCTIONS 2 2 4 EMMC NAND Memory MTFC4GDKDI ET 0000 EMMC NAND Memory is used as next two options on the board And that is different by board revision The board information can be confirmed by 5 5 Board Revision and 5 6 Board Information in EEPROM Please refer to eMMC bit of EEPROM Address s 0x10 for the revision recognizing of software view point The is NAND Flash Memory and MMC one package Simple read write memory using industry standard MMC protocol 4 2 interface solution for embedded and external flash memory 4G Byte Flash Memory Package 153 Ball FBGA 11 5x13mm Low cost embedded solution with Performance increase costs less Dual power supply 3 0V 2 7V 3 3V for NAND Flash 1 8V 3 0V for I O 1 or 4 2 interface X1 x4 x8 bus amp 26 2 52MHz The MTFCAGDKDI is a NAND Flash Memory and MMC in one pa
74. st publications of Shimafuji specification etc for the most up to date specifications of Shimafuji products Not all products and or types are available in every country Please check with a Shimafuji sales representative for availability and additional information No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Shimafuji Shimafuji assumes no responsibility for any errors that may appear in this document Shimafuji does not assume any liability for infringement of patents Copyrights or other intellectual property rights of third parties by or arising from the use of Shimafuji products listed in this document or any other liability arising from the use of such products No license express implied or otherwise is granted under any patents copyrights or other intellectual property rights of Shimafuji or others Descriptions of circuits software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples The incorporation of these circuits software and information in the design of a customer s equipment shall be done under the full responsibility of the customer Shimafuji assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits software and information While Shimafuji endeavors to enhance the quality reliability a
75. ual CHAPTER 1 OBINTRODUCTION 1 2 2 Board Image 1 Front View LED 1 4 General purpose SW2 4 SW6 14 General purpose Switches CN9 Debug IF MICTOR Figure 1 3 10 board Image Front CN9 Debug IF Mictor SW2 4 SW6 14 general purpose Switches LED1 4 general purpose LEDs SW6 __ ____________ Figure 1 4 IO board Key Image Front User s Manual 19 CHAPTER 1 OBINTRODUCTION 2 Back View CN5 Expansion Connecter CN3 ABO expansion J3 Audio LINE OU J2 Audio MIC IN CN1 SO DIMM CN2 SO DIMM Sw1 Side Switch SW5 Side Switch 5117 NTS LSI Reset SW 19 1 CN10 BATTERY NT dE CN6 Debug 1 19044002 00 0M A3 02 0 5 T1 Ether CN7 LCD Interface Sw20 USB mode SW15 Power SW J4 5V Jack NTSC Pal SW16 Debug Target Control Switch CN4 Expansion Connecter Figure 1 5 board Image back CN1 CN2 CARD edge CN3 ABO expansion CN4 CN5 Expansion Connecter CN6 Debug IF Mictor CN7 LCD Interface R CN10 BATTERY Connecter Sw1 SW5 Side Switch x2 SW15 Power Switch SW16 Debug target Control switch CPU or DSP
76. uching he specific location is shown General attention Example High temperature attention The general attention not specified is The possibility of injury by the high shown temperature is shown The example Pull out the power plug It is the one directed to pull out the plug of the AC adapter User s Manual DANGER There is no danger marking in this product The hot section is in a part of the substrate when the AC power supply is connected Please note the high temperature burn The power supply and the plug use the one of ratings 2A that suited the safety standard of the product according to law in country that uses it The use of the unacceptable products causes the breakdown generation of heat a fire and the electric shock Please detach the AC plug from the outlet when you generate smoke a nasty smell an abnormal sound and abnormal generation of heat etc by any chance Using Products as it is It causes a fire the burn and the electric shock Cm This product Shouldn t dismantle and remodel by the customer causes the breakdown smoking a fire and the electric shock It causes a fire and the electric shock damaging it The AC adapter cable is not t pull out of supply entered So connecter is not pull out of supply entered Exception Cable can pull out of power supply Pulling out the connector is not done with the power supply entered It causes a fire and the electric shock damaging it
77. v device Fast Write Cycle Time Program time 200us Typ Block Erase Time 2ms Typ Command Address Data Multiplexed I O Port Package 48 pin TSOP 12x20mm System Control 20 User s Manual SYSTEM CONTROL CHAPTER 3 System Block Diagram 3 1 1012 0 827 021 xis cru ILS QD I qa 9 1981009 ZX MS CMS LMSA Idd suowng z pxe 31 t uuo JOIN JI IND uuoo as 2 ZND aera 0 UUOD soo 4 n nen ern gy 19005 gsn VOU 95 2u3 264 O9plA 238t9bV eun J9po5 f Jul oipny EUN 9n ef 31 Ajuo ped en 22254 t AS AZ AS uuoo J ouAsy uuo 4l 194353 19433 IL 2n L Swine 9 OTND 4 peg useld YON san Ln lt R gt Figure 3 1 System Block Diagram 29 User s Manual CHAPTER 3 2BSYSTEM CONTROL 3 2 Memory Map

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