USER`S MANUAL - Artisan Technology Group
Contents
1. INTERFACE INTERRUPT CHANNELS INTERFACE INPUT REGISTERS FIELD PROGRAMMABLE 1 RAY LOGE E ADDRESS BUS INTERRUPT ENABLE REGISTER 9 CONTROL BUS INTERRUPT TYPE REGISTER ADDRESS DECODING INTERRUPT AND IP INTERRUPT BUS INTERFACE LOGIC POLARITY REGISTER INTERRUPT LINES TATUS REGISTER INPUT BUFFERS AND PROM NON INTERRUPT CONFIGURATION INTERRUPT MEMORY DATA BUS D0 D15 4 7V 45V SUPPLY SUPPLY FILTERING d COMMON GND x P400 BLOCK DIAGRAM DP meo 1 2 501 519 TO AVME9630 9660 CARRIER BOARD P3 OR P4 P5 P6 STRAIN RELIEF 1004 534 50 PIN CONNECTOR 1004 512 NOTE SEVEN DIGIT PART NUMBERS ARE ACROMAG PART NUMBERS X FEET TOP VIEW NON SHIELDED x RIBBON CABLE 2002 211 PIN 1 ON CABLE IS DESIGNATED WITH RED INK FRONT VIEW MODEL 5025 550 SIGNAL CABLE NON SHIELDED MODEL 5025 552 1 0 TERMINATION CONNECTOR 1004 512 N NS 2 tA LA A 2 7 A LA 2 LA 2 2 z 2 2 2 2 2 2 2 z 2 STRAIN RELIEF 1004 534 C ser ow o PT PIN 50 OF P1 amp P2 CONNECT TO GROUND SHIELD P1 TO AVME9630 9660 CARRIER BOARD GROUND SHIELO ON BACK SIDE OF CABLE MODEL 5025 552 1 0 TERMINATION P3 OR P4 PS P6 X FEET TOP VIEW STRAIN RELIEF RIBBON CA2. 9 CABLE MODEL 5025 550 uoc 10 CABLE MODEL 5025 551 10 TERMINATION PANEL MODEL 5025 552 10 TRANSITION MODULE MODEL TRANS GP 10 DRAWINGS Page 4501 434 IP MECHANICAL ASSEMBLY 11 4501 518 IP400 EXAMPLE INPUT CONNECTIONS 11 4501 519 IP400 BLOCK 12 4501 462 CABLE 5025 550 NON SHIELDED 12 4501 463 CABLE 5025 551 SHIELDED 13 4501 464 TERMINATION PANEL 5025 552 13 4501 465 TRANSITION MODULE TRANS GP 14 IMPORTANT SAFETY CONSIDERATIONS It is very important for the user to consider the possible adverse effects of power wiring component sensor or software failures in designing any type of control or monitoring system This is especially important where economic property loss or human life is involved It is important that the user employ satisfactory overall System design It is agreed between the Buyer and Acromag that this is the Buyer s responsibility 1 0 GENERAL INFORMATION The Industrial Pack IP Series 400 module is a 40 channel digital input board This model accepts forty 0 to 60V DC inputs providing up to 160 inputs per 6U VMEbus system slot When mated with the Acromag IP405 Digital Output Module this model can be used for direct loopback monitoring of the
3. input and interrupt registers are all accessed through the 16 bit data bus interface to the carrier board DO D15 5 0 SERVICE AND REPAIR SERVICE AND REPAIR ASSISTANCE Surface Mounted Technology SMT boards are generally difficult to repair It is highly recommended that a non functioning board be returned to Acromag for repair The board can be easily damaged unless special SMT repair and service tools are used Further Acromag has automated test equipment that thoroughly checks the performance of each board When a board is first produced and when any repair is made it is tested placed in a burn in room at elevated temperature and retested before shipment Please refer to Acromag s Service Policy Bulletin or contact Acromag for complete details on how to obtain parts and repair SERIES IP400 INDUSTRIAL I O PACK 40 CHANNEL DIGITAL INPUT MODULE PRELIMINARY SERVICE PROCEDURE Before beginning repair be sure that all of the procedures in Section 2 Preparation For Use have been followed Also refer to the documentation of your carrier board to verify that it is correctly configured Replacement of the module with one that is known to work correctly is a good technique to isolate a faulty module CAUTION POWER MUST BE TURNED OFF BEFORE REMOVING OR INSERTING BOARDS 5 Applications Engineers can provide further technical assistance if required When needed complete repair services are also available from Acr
4. or 1 High level to each channel s respective bit in the Interrupt Polarity Register 4 Enable individual input channel interrupts by writing a 1 to each channel s respective bit in the Interrupt Enable Register 5 Clear pending interrupts by writing a 1 to each channel s respective bit in the Interrupt Status Register Interrupts can now be generated by matching the input level with the selected polarity for programmed interrupt channels SERIES IP400 INDUSTRIAL I O PACK 40 CHANNEL DIGITAL INPUT MODULE General Sequence of Events for Processing an Interrupt 1 The 400 asserts the Interrupt Request 0 Line IREQO in response to an interrupt condition at one or more inputs 2 The AVME9630 9660 carrier board acts as an interrupter in making the VMEbus interrupt request asserts corresponding to the IP interrupt request 3 VMEbus host interrupt handler asserts IACK and the level of the interrupt it is seeking on 01 03 4 When the asserted VMEbus IACKIN signal daisy chained is passed to the AVME9630 9660 the carrier board will check if the level requested matches that specified by the host If it matches the carrier board will assert the IntSel line to the appropriate IP together with carrier board generated address bit A1 to select which interrupt request is being processed A1 low corresponds to IntReg0 A1 high corresponds to IntReq1 5 The 400 puts the appropriat
5. output states The IP400 can be programmed to generate Change Of State COS Low or High level transition interrupts The input threshold is TTL compatible with hysteresis included The IP400 utilizes state of the art Surface Mounted Technology SMT to achieve its high channel density and is an ideal choice for a wide range of industrial control and monitoring applications that require high density high reliability and high performance at a low cost Model Operating Temperature Range 400 0 to 70 C IP400E 40 to 85 C KEY IP400 FEATURES e High Channel Count Interfaces with up to 40 inputs Four units mounted on a carrier board provide up to 160 input channels in a single system slot TTLInput Threshold Input threshold is at TTL levels and includes hysteresis Input Hysteresis Buffered inputs include hysteresis for increased noise immunity Programmable Change of State Level Interrupts Interrupts are software programmable for any bit change of state or level match on up to 12 channels channels 0 11 only e Loopback Compatible with IP405 The P2 pin assignments of the IP400 input module correspond with those of the IP405 output module This provides direct interface capability between these models High Voltage Inputs Inputs are rated to 60 Input channels are non isolated and share a common connection High Impedance Inputs High impedance inputs minimize loading o
6. the appropriate bit position in the input channel Interrupt Status Register The Interrupt Vector Register contains a pointer to an interrupt handling routine The lower 4 bits of this 8 bit number contain the channel number of the interrupting channel The upper 4 bits of this 8 bit number contain a user programmable pointer to complete the vector As such the vector may point to any one of 12 possible locations to access the interrupt handling routine If each of these 8 locations contain the same address the address of a single interrupt handling routine one interrupt handling routine may be used to Service all possible channel interrupts Interrupt service is prioritized with the higher numbered channel having a higher priority over the lower numbered channels Thus Channel 11 has the highest priority and channel 0 the lowest As such if multiple channel interrupts become pending at the same time the pointer corresponding to the highest numbered channel will be delivered first After the highest numbered channel interrupt is serviced and cleared an additional interrupt will be generated for the next highest priority pending interrupt When using interrupts input channel bandwidth should be limited to reduce the possiblity of missing channel interrupts For a given input channel this could happen if multiple changes occur before the channel s interrupt is serviced The response time of the input channels should also be considered w
7. 2 pin assignments Refer to the IP module manual for correct wiring connections to the termination panel Schematic and Physical Attributes See Drawing 4501 464 Field Wiring 50 position terminal blocks with screw clamps Wire range 12 to 26 AWG Connections to AVME9630 9660 P1 50 pin male header with strain relief ejectors Use Acromag 5025 550 x or 5025 551 x cable to connect panel to VME board Keep cable as short as possible to reduce noise and power loss Mounting Termination panel is snapped on the DIN mounting rail Printed Circuit Board Military grade FR 4 epoxy glass circuit board 0 063 inches thick Operating Temperature 40 C to 100 C Storage Temperature 40 C to 100 C Shipping Weight 1 25 pounds 0 6kg packaged 10 TRANSITION MODULE MODEL TRANS GP Type Transition module for AVME9630 9660 boards Application To repeat field I O signals of IP modules A through D for rear exit from VME card cages This module is available for use card cages which provide rear exit for I O connections via transition modules transition modules can only be used in card cages specifically designed for them It is a double height 6U single slot module with front panel hardware adhering to Othe VMEbus mechanical dimensions except for shorter printed circuit board depth Connects to Acromag termination panel 5025 552 from the rear of the card cage and to AVME9630 9660 boards within card cage via flat 50 pin ribb
8. 2x8 ID PROM read on DO D7 Access Times 8MHz Clock ID PROM Read 1 wait state 375ns cycle P M Channel Registers Read 1 wait state 375ns cycle I Interrupt Registers Read 1 wait state 375ns cycle Interrupt Registers Write 1 wait state 375ns cycle Interrupts Handling Format 12 interrupt channels are supported channels 0 11 only An 8 bit vector is provided during interrupt acknowledge cycles on DO D7 The release mechanism is RORA type Release On Register Access SERIES IP400 INDUSTRIAL I O PACK 40 CHANNEL DIGITAL INPUT MODULE APPENDIX CABLE MODEL 5025 550 x Non Shielded MODEL 5025 551 x Shielded Type Flat Ribbon Cable 50 wires female connectors at both ends The x suffix designates the length in feet 12 feet maximum Choose shielded or unshielded cable according to model number The unshielded cable is recommended for digital I O while the shielded cable is recommended for optimum performance with precision analog I O applications Application Used to connect a Model 5025 552 termination panel to the AVME9630 9660 non intelligent carrier board A D connectors both have 50 pin connectors Length Last field of part number designates length in feet user specified 12 feet maximum It is recommended that this length be kept to a minimum to reduce noise and power loss Cable 50 wire flat ribbon cable 28 gage N
9. 551 X Shielded Cable or Model 5025 550 X Non Shielded Cable A Flat 50 pin cable with female connectors at both ends for connecting AVME9630 9660 or other compatible carrier boards to Model 5025 552 termination panels The X of Model denotes the length in feet The unshielded cable is recommended for digital I O while the shielded cable is recommended for optimum performance with precision analog I O applications Termination Panel Model 5025 552 A DIN rail mountable panel that provides 50 Screw terminals for universal field 1 termination Connects to Acromag AVME9630 9660 or other compatible carrier boards via flat 50 pin ribbon cable Model 5025 550 X or 5025 551 X Transition Module Model TRANS GP This module repeats field 1 connections of IP modules A through D for rear exit from the card cage It is available for use in card cages which provide rear exit for I O connections via transition modules transition modules can only be used in card cages specifically designed for them It is a double height 6U single slot module with front panel hardware adhering to the VMEbus mechanical dimensions except for shorter printed circuit board depth It connects to Acromag Termination Panel 5025 552 from the rear of the card cage and to AVME9630 9660 boards within the card cage via flat 50 pin ribbon cable Model 5025 550 X or 5025 551 X INDUSTRIAL I O PACK SOFTWARE LIBRARY Acromag provides an Industrial I O Pack Soft
10. Acromag 9 Series 400 Industrial Pack 40 Channel Digital Input Board USER S MANUAL ACROMAG INCORPORATED 30765 South Wixom Road P O BOX 437 Wixom MI 48393 7037 U S A Tel 248 624 1541 Fax 248 624 9234 Copyright 1995 Acromag Inc Printed in the USA Data and specifications are subject to change without notice 8500 532 D01E003 SERIES IP400 INDUSTRIAL I O PACK 40 CHANNEL DIGITAL INPUT MODULE The information contained in this manual is subject to change without notice Acromag Inc makes no warranty of any kind with regard to this material including but not limited to the implied warranties of merchantability and fitness for a particular purpose Further Acromag Inc assumes no responsibility for any errors that may appear in this manual and makes no commitment to update or keep current the information contained in this manual No part of this manual may be copied or reproduced in any form without the prior written consent of Acromag Inc Table of Contents 1 0 GENERAL KEY IP400 FEATURES esee INDUSTRIAL I O PACK INTERFACE FEATURES SIGNAL INTERFACE INDUSTRIAL I O PACK SOFTWARE LIBRARY PREPARATION FOR 06 UNPACKING AND CARD CAGE CONSID
11. BLE BLACK LINE ON CABLE CONNECTOR 1004 534 2002 261 INDICATES PIN 50 1004 512 POLARIZING KEY 50 PIN CONNECTOR PIN 1 0N CABLE 1004 512 NO MARKINGS STRAIN RELIEF 1004 534 FRONT VIEW NOTE SEVEN DIGIT PART NUMBERS ARE ACROMAG PART NUMBERS XXXX XXX se lt romag erg MODEL 5025 551 SIGNAL CABLE SHIELDED Ato 09 ieri 1e 4501 463 1 2 3 4 5 6 7 8 8 101112131415 16 17 1H 19 20 21 22 23 24 25 26 27 2B 29 30 31 32 33 34 35 36 37 38 39 48 41 42 43 44 45 46 47 49 58 P1 1 2 3 4 5 6 7 8 8 10 111213 1415 16 1718 19 20 21 22 2324 25 26 27 28 29 30 31 32 33 34 35 38 37 38 39 48 41 42 43 44 45 48 47 48 49 50 MODEL 5025 552 TERMINATION PANEL SCHEMATIC G RAIL DIN MOUNTING SHOWN HERE TERMINATION 5 DIN EN 50035 32mm PANEL ACROMAG PART NUMBER 4001 040 T RAIL DIN MOUNTING SHOWN HERE DIN EN 50022 35 SCREWORIVER SLOT FOR REMOVAL FROM RAIL SIDE VIEW NOTES DIMENSIONS ARE IN INCHES MILLIMETERS TOLERANCE 0 020 3 0 5 1 35 7 9 1113 15 17 19 21 23 25 27 28 33 35 37 39 41 43 45 47 48 MODEL 5025 552 TERMINATION PANEL Acromag WIXOM MICH TITLE FRONT VIEW CONNECTORS ON PC BOARD MODEL TRANS GP MODULE SCHEMATIC CONNECTORS ON FRONT PANEL TOP VIEW eon ee re 9 19 233 4 Acto Q9 u we MODEL TRANS
12. ERATIONS BOARD CONFIGURATION CONNEGTOHRS a alae eerte nene IP Field MO Connector Input Noise and Grounding Considerations IP Logic Interface Connector P1 PROGRAMMING ADDRESS MAPS uuu eevee IP Digital Input Registers A B amp C Interrupt Enable Interrupt Type Configuration Register 2 Interrupt Polarity Interrupt Status Interrupt Vector Register IP Identification IP400 PROGRAMMING CONSIDERATIONS 2 Programming Interrupts esee THEORY OF INB UTS LOGIC POWER SERVICE AND REPAIR Z SERVICE AND REPAIR ASSISTANCE PRELIMINARY SERVICE PROCEDURE GENERAL DIGITAL INPUTS ja INDUSTRIAL I O PACK COMPLIANCE 2 0 3 0 4 0 5 0 6 0
13. GP TRANSITION MODULE we
14. HS THE SHORTER LENGTH IS FOR USE WITH 9630 9660 CARRIER BOARDS SHOWN CHECK YOUR CARRIER BOARD TO DETERMINE ITS REQUIREMENTS MOUNTING HARDWARE PROVIDED MAY NOT BE COMPATIBLE WITH ALL TYPES OF CARRIER BOARDS 2 INSERT FLAT HEAD SCREWS ITEM A THROUGH SOLDER SIDE OF MODULE AND INTO HEX SPACERS ITEM B AND TIGHTEN 4 PLACES UNTIL HEX SPACER IS COMPLETELY SEATED 5 3 CAREFULLY ALIGN IP MODULE TO CARRIER BOARD AND PRESS 5 TOGETHER UNTIL CONNECTORS AND SPACERS ARE SEATED 4 INSERT PAN HEAD SCREWS ITEM C THROUGH SOLDER SIDE OF CARRIER BOARD AND INTO HEX SPACERS ITEM B AND TIGHTEN 4 PLACES IP MODULE TO CARRIER BOARD MECHANICAL ASSEMBLY Arenos FEE om 2121 s wp ue cut idu puo CONTACT CLOSURE 402 INPUT MODULE 400 INPUT CHANNEL 4 7 COMMON HANGING INPUTS SHOULD T FTF LOOPBACK MONITORING 400 INPUT CHANNEL 1 NOTE THE 400 INPUT BOARD AND THE 1 405 OUTPUT BOARD SHARE THE SAME P2 I O INTERFACE CONNECTOR PIN ASSIGNMENTS AND ARE DIRECTLY LOOPBACK COMPATIBLE 405 OUTPUT CHANNEL 1 LOGIC INTERFACE IP400 INPUT MODULE IP400 INPUT CHANNEL 4 7V IP400 INPUT MODULE i CARRIER BOARD 400 INPUT CHANNEL 4 7V 100K DIGITAL i COMMON i COMMON i TYPICAL EARTH GROUND IS USUALLY MADE AT CAGE POWER SUPPLY TO AVOID GROUND LOOPS wirow MICH IP400 BLOCK DIAGRAM 170 INPUT BUFFERS LOGIC
15. High to Low is 1 4 typical Limited to TTL levels of 0 8VDC maximum LOW level and 2 0VDC minimum HIGH level Input Resistance 100 Typical Input Hysteresis 200mVDC centered at a 1 5VDC threshold Typical Input Current 560uA Typical at 60V DC Interrupt Input Response Time 250nS minimum to 375nS maximum depending on when the input transition occurs with respect to the 8MHz clock Measured from input transition to INTREQO line assertion Resistance to RFl No digital upsets occur for field strengths up to 10V per meter at 27MHz 151MHz amp 460MHz per SAMA PMC 33 1 test procedures Resistance to EMI Unit has been tested with no digital upsets under the influence of EMI from switching solenoids commutator motors and drill motors ESD Protection Inputs exhibit no degradation of performance with repeated ESD induced voltages to 6KV per DOD STD 1686 INDUSTRIAL I O PACK COMPLIANCE Specification This module meets or exceeds all written Industrial Pack specifications per revision 0 7 1 Electrical Mechanical Interface Single Size IP Module IP Data Transfer Cycle Types Supported Input Output IOSel 16 bit D16 word or 8 bit DO8 EO read of data on DO 15 ID Read 1 5 3
16. LIC Logic Lines are NOT USED by this IP Model 3 0 PROGRAMMING INFORMATION ADDRESS MAPS This board is addressable in the Industrial Pack 1 space to control the acquisition of digital inputs from the field The I O space may be as large as 64 16 bit words 128 bytes using address lines A1 A6 but the IP400 only uses a portion of this space The I O space address map for the IP400 is shown in Table 3 1 Note the base address for the IP module 1 space see your carrier board instructions must be added to the addresses shown to properly access the space Accesses can be performed an 8 bit 008 or 16 bit word 016 basis SERIES IP400 INDUSTRIAL I O PACK 40 CHANNEL DIGITAL INPUT MODULE Table 3 1 IP400 I O Space Address Hex Memory EVEN Byte 08 READ Digital Input Channel Register A CH15 8 READ Digital Input Channel Meet B ODD Byte D07 READ Digital Input Channel Register A CH07 e CHOO READ Digital Input Channel Register B CH31 CH24 23 CH16 READ Digital Input Channel Register C CH39 CH32 OFFF Nor um Driven R W Interrupt Enable Register CH11 CHOO R W Interrupt Type Config Register CH11 o CH00 eT R W Interrupt Polarity LOW Register 15 CH11 o CH00 T R W Interrupt Status Register Bin HIGH OFFF 13 NOT USED P 7F Notes Table 3 1 1 These bits of this register are not driven Pull ups on the carrier board da
17. THROUGH 15 MSB 15 14 13 12 11 10 9 8 REGISTER B INPUT CHANNELS 16 THROUGH 31 MSB 15 14 13 12 11 10 9 8 REGISTER C INPUT CHANNELS 32 THROUGH 39 MSB 15 14 13 12 11 10 9 8 7 6 5 4 32 1 1 1 1 1 11 1 CH39 It is recommended that unused input points not be left floating but pulled high or low The unused upper 8 bits of Register C are Don t Care and will always read high 1 s for D16 accesses Interrupt Enable Register R W The digital input channel Interrupt Enable Register provides a mask bit for each of the 12 possible interrupt channels channels 0 11 only A 0 bit will prevent the corresponding input channel from generating an external interrupt A 1 bit will allow the corresponding input channel to generate an interrupt INTERRUPT ENABLE REGISTER MSB 15 1413 12 11 10 9 8 00 0 0 CH11 LSB 7 6 5 4 3 2 All input channel interrupts are masked 0 following a reset The unused upper 4 bits of this 16 bit register are always driven low 0 s for DOB E or D16 accesses Interrupt Type Configuration COS or H L Register R W The Interrupt Type Configuration Register determines the type of input channel transition that will generate an interrupt for each of the 12 possible interrupt channels channels 0 11 only A 0 bit means that an interrupt will be generated when the input channel level specified by the Interrupt Polarity Register occurs i e Low or High level transiti
18. acle header AMP 173279 3 or equivalent which mates to the male connector of the carrier board AMP 173280 3 or equivalent This provides excellent connection integrity and utilizes gold plating in the mating area Threaded metric M2 screws and spacers are supplied with the module to provide additional stability for harsh environments see Mechanical Assembly Drawing 4501 434 The field and logic side connectors are keyed to avoid incorrect assembly SERIES IP400 INDUSTRIAL I O PACK 40 CHANNEL DIGITAL INPUT MODULE P2 pin assignments are unique to each IP model see Table 2 1 and normally correspond to the pin numbers of the front panel field I O interface connector on the carrier board you should verify this for your carrier board The IP400 P2 connector shares the same signal pinouts with Acromag Model IP405 40 Channel Output Boards making it directly compatible for loopback monitoring of the 1P405 output states Table 2 1 IP400 Field I O Pin Connections P2 Pin Description Number Pin Description Number N4 6 ING 8 9 27 Input Noise and Grounding Considerations This model is non isolated between the logic and field input grounds since input common is electrically connected to the IP module ground Consequently the field MO connections are not isolated from the carrier board and backplane Care should be taken in designing installations without isolation to avoid noise pickup an
19. d ground loops caused by multiple ground connections Refer to Drawing 4501 518 for example input and grounding connections IP Logic Interface Connector P1 P1 of the IP module provides the logic interface to the mating connector on the carrier board This connector is a 50 pin female receptacle header AMP 173279 3 or equivalent which mates to the male connector of the carrier board AMP 173280 3 or equivalent This provides excellent connection integrity and utilizes gold plating in the mating area Threaded metric M2 screws and spacers are supplied with the IP module to provide additional stability for harsh environments see Drawing 4501 434 for assembly details Field and logic side connectors are keyed to avoid incorrect assembly The pin assignments of P1 are standard for all IP modules according to the Industrial I O Pack Specification see Table 2 2 Note that the IP400 does not utilize all of the logic signals defined for the P1 connector and these are indicated BOLD ITALICS Table 2 2 Standard Logic Interface Connections P1 Pin Description Number Pin Description Number 1 eoo CK 2 2 Reset 3 DO 4 DO2 6 D4 8 DO 9 06 10 Do9 13 DwAEn 38 S A 43 INTHeqi 44 Bs 20 45 BS 21 LL STROBE 4 2 A Asterisk is used to indicate an active low signal BOLD ITA
20. d first After the highest numbered channel s interrupt is serviced and cleared an additional interrupt will be generated for the next highest priority channel with an interrupt pending Note that the input channel bandwidth should be limited to reduce the possibility of missing channel interrupts For a specific input channel this could happen if multiple changes occur before the channel s interrupt is serviced INTERRUPT STATUS REGISTER MSB LSB 7654 32 15 1413 12 1110 9 8 0 CH11 All interrupts are cleared following a reset The unused upper 4 bits of this 16 bit register are always driven low 05 for DO8 E or D16 accesses Interrupt Vector Register R W The Interrupt Vector Register maintains an 8 bit interrupt pointer for each of the 12 digital input channel interrupt lines channels 0 11 only The lower 4 bits of the Interrupt Vector Register odd byte address contain the channel number that originated the interrupt The upper 4 bits of the odd addressed byte are user programmable and contain a pointer to the interrupt service routine Interrupts are Served on a priority basis with the higher numbered channels having higher priority i e channel 11 has the highest priority channel 0 the lowest The appropriate interrupt vector is given to the VMEbus Interrupt Handler when an interrupt is being serviced As such it is a pointer to 12 possible interrupt handling routines This allows each digital input c
21. e interrupt vector on the local data bus 000 007 for the 008 O interrupter and asserts ACK to the carrier board The carrier board passes this along to the VMEbus 008 0 and asserts 6 The host uses the vector to form a pointer to an interrupt service routine for the interrupt handler to begin execution 7 Example of Generic Interrupt Handler Actions A Disable the interrupting IP by writing 0 to the appropriate bit in the AVME9630 9660 IP Interrupt Enable Register B Disable the interrupting channel s by writing a 0 to the appropriate bits in the IP400 Interrupt Enable Register C Clear the interrupting channel s by writing a 1 to the appropriate bits in the IP400 Interrupt Status Register D Enable the interrupting channel s by writing a 1 to the appropriate bits in the IP400 Interrupt Enable Register E Clear the interrupting IP by writing a 1 to the appropriate bit in the AVME9630 9660 IP Interrupt Clear Register Enable the interrupting by writing a 1 to the appropriate bit in the AVME9630 9660 IP Interrupt Enable Register 8 If the 400 interrupt stimulus has been removed and no other modules have interrupts pending the interrupt cycle is complete i e the carrier board negates its interrupt request IRQ A If the IP400 interrupt stimulus remains a new interrupt request will immediately follow If the stimulus cannot be removed then the IP400 interru
22. ed by the Interrupt Type Configuration Register INTERRUPT POLARITY HIGH LOW REGISTER MSB 15 1413 12 1110 9 8 000 0CHt1 7654 32 All bits are set to 0 following a reset which means that the inputs will cause interrupts when they are below TTL threshold The unused upper 4 bits of this 16 bit register are always driven low 075 for DOB E or D16 accesses Interrupt Status Register R W The Interrupt Status Register reflects the status of the 12 possible interrupt channels channels 0 11 only A 1 bit indicates that an interrupt is pending for the corresponding channel A channel that does not have interrupts enabled will never set its interrupt status flag A channel s interrupt can be cleared by writing a 1 to its bit position in the Interrupt Status Register writing a 1 acts as a reset signal to clear the set state This is known as the Release On Register Access RORA method as defined in the VME system architecture specification However if the condition which caused the interrupt to occur remains in the case of a level interrupt the interrupt will be generated again unless disabled via the Interrupt Enable Register Note that interrupts are prioritized via hardware within the card Channel 11 has the highest priority channel 0 the lowest priority If multiple input channel interrupts become pending at the same time the vector corresponding to the highest numbered channel will be delivere
23. epresented by 02 Hex SERIES IP400 INDUSTRIAL I O PACK 40 CHANNEL DIGITAL INPUT MODULE The IP400 ID PROM contents are shown in Table 3 2 Note that the base address for the IP module ID space see your carrier board instructions must be added to the addresses shown to properly access the ID PROM Execution of an ID PROM Read operation requires 1 wait state IP400 PROGRAMMING CONSIDERATIONS To make programming and communicating with the board easier Acromag provides you with the Industrial Pack Software Library diskette The functions provided are written in the C programming language and can be linked into your application Refer to the README TXT file in the root directory and the 400 file in the 400 subdirectory on the diskette for details The following sections give some pointers for programming interrupts Programming Interrupts Digital input channels can generate interrupts for the following conditions channels 0 11 only e Change of State COS at selected channels e Input level polarity match at selected input channels Interrupts generated by the 400 use interrupt request line INTREQO Interrupt Request 0 The interrupt release mechanism employed is the Release On Register Access RORA type This means that the interrupter will release the Industrial Pack interrupt request line INTREQO after the interrupt has been cleared by writing a 1 to
24. f the input source and minimize input current e Configuration Jumpers or Switches All configuration is performed through software command with no internal jumpers to configure or switches to set INDUSTRIAL 1 PACK INTERFACE FEATURES e High density Single size industry standard IP module footprint Up to four units may be mounted on a 6U VMEbus carrier board e Local ID Each IP module has its own 32 byte ID PROM which is accessed via data transfers in the ID Read space SERIES IP400 INDUSTRIAL I O PACK 40 CHANNEL DIGITAL INPUT MODULE Supports 16 bit amp 8 bit I O Channel register Read Write is performed through 16 bit D16 or 8 bit 008 data transfer cycles in the IP module I O space e High Speed Acquisition times for all data transfer cycles described in terms of wait states 1 wait state is required for reading the inputs 1 wait state for write operations see specifications for detailed information SIGNAL INTERFACE PRODUCTS See Appendix for more information on compatible products This IP module will mate directly to any industry standard IP carrier board including Acromag AVME9630 9660 3U 6U non intelligent carrier boards Consult the documentation of your carrier board to ensure compatibility with the following interface products since all connections to field signals are made through the carrier board which passes them to the individual IP modules Cables Model 5025
25. hannel to be serviced by its own software handler INTERRUPT VECTOR REGISTER MSB LSB 1514131211109 8 7 6 5 4 321 0 0000 XXX X User Programmable Channel No All bits of this register are set to 0 following a reset The upper 4 bits even byte address of this 16 bit register are driven low 075 The lower 4 bits of the upper byte are driven high 1 s IP ID PROM Read Only 32 Odd Byte Addresses Each IP module contains an identification ID PROM that resides in the ID space per the IP module specification This area of memory contains 32 bytes of information at most Both fixed and variable information may be present within the ID PROM Fixed information includes the IPAC identifier model number and manufacturer s identification codes Variable information includes unique information required for the module The 400 ID PROM does not contain any variable e g unique calibration information ID PROM bytes are addressed using only the odd addresses in a 64 byte block see Table 3 2 Table 3 2 IP400 ID Space Identification 10 PROM Hex Offset From ID ASCII Numeric PROM Base Character Value Address Equivalent Field Description O 1 49 AIIP s have IPAC Not Used Revision 0 Reserved Not Used Driver ID Low Byte Not Used Driver ID High Byte Total Number of ID Notes Table 3 2 1 The model number is represented by a two digit code within the ID PROM the IP400 model is r
26. hen figuring this bandwidth The total response time is the sum of the input buffer response time plus the interrupt logic circuit response time and this time must pass before another interrupt condition will be recognized The following programming examples assume that the IP400 is installed onto an Acromag AVME9630 9660 carrier board consult your carrier board documentation for compatibility details Programming Example for AVME9630 9660 Carrier Boards 1 Clear the Global Interrupt Enable Bit in the Carrier Board Status Register by writing a 0 to bit 3 2 Perform Specific IP Module Programming see the Change of State or Level Match programming examples that follow as required for your application 3 Write to the carrier board Interrupt Level Register to program the desired interrupt level per bits 2 1 8 0 4 Write 1 to the carrier board IP Interrupt Clear Register corresponding to the desired IP interrupt request s being configured 5 Write 1 to the carrier board IP Interrupt Enable Register bits corresponding to the IP interrupt request to be enabled 6 Enable interrupts from the carrier board by writing a 1 to bit 3 the Global Interrupt Enable Bit of the Carrier Board Status Register IP Programming Example for Change of State Interrupts 1 Program the upper 4 bits of the odd addressed byte of the Interrupt Vector Register with the user specified portion of the interrupt vector These 4 b
27. hysteresis Digital input channels of this model can be configured to generate interrupts for Change Of State COS or input level polarity match conditions for selected input channels channels 0 11 only Interrupt service is prioritized with the higher numbered channel having a higher priority over the lower numbered channels An 8 bit interrupt service routine vector is provided during interrupt acknowledge cycles on data lines DO D7 The interrupt release mechanism employed is RORA Release On Register Access Since IP400 40 channel input boards use the same field I O pin assignments P2 as Model IP405 40 channel output boards these units are directly compatible for loopback monitoring of the IP405 output states LOGIC POWER INTERFACE The logic interface to the carrier board is made through connector P1 refer to Table 2 2 Not all of the IP logic P1 pin functions are used P1 also provides 5V and 12V to power the module 12V is not used All I O address decoding control signals interrupt handling and ID access logic is done through a programmable gate array installed on the IP module The program for the gate array is stored in separate PROM memory and loaded upon reset The FPGA also returns the acknowledgement signal required by the carrier board per the IP specification The ID PROM read only installed on the IP module provides the identification for the individual module per the IP specification The ID PROM
28. its combined with the lower 4 bits the interrupting channel number form a pointer to one of 12 possible locations in memory that contain the address of the interrupt handling routine for the interrupting channel 2 Select Change of State interrupts for channels by writing a 1 to each channel s respective bit in the Interrupt Type Register for channels that are to generate interrupts 3 Enable individual input channel interrupts by writing a 1 to each channel s respective bit in the Interrupt Enable Register 4 Clear pending interrupts by writing a 1 to each channel s respective bit in the Interrupt Status Register Change of State Interrupts may now be generated by the input channels programmed above for any Change Of State transition IP Programming Example for Level Polarity Match Interrupts 1 Program the upper 4 bits of the odd addressed byte of the Interrupt Vector Register with the user specified portion of the interrupt vector These 4 bits combined with the lower 4 bits the interrupting channel number form a pointer to one of 12 possible locations in memory that contain the address of the interrupt handling routine for the interrupting channel 2 Select Polarity interrupts for channels by writing a 0 to each 5 respective bit in the Interrupt Type Register for channels that are to generate interrupts 3 Select the desired polarity High Low level for interrupts by writing a 0 Low
29. izes static sensitive components and should only be handled at a static safe workstation CARD CAGE CONSIDERATIONS Refer to the specifications for loading and power requirements Be sure that the system power supplies are able to accommodate the power requirements of the carrier board plus the installed IP modules within the voltage tolerances specified IMPORTANT Adequate air circulation must be provided to prevent a temperature rise above the maximum operating temperature The dense packing of the IP modules to the carrier board restricts air flow within the card cage and is cause for concern Adequate air circulation must be provided to prevent a temperature rise above the maximum operating temperature and to prolong the life of the electronics If the installation is in an industrial environment and the board is exposed to environmental air careful consideration should be given to air filtering BOARD CONFIGURATION Power should be removed from the board when installing IP modules cables termination panels and field wiring Refer to Mechanical Assembly Drawing 4501 434 and your IP module documentation for configuration and assembly instructions Model 400 Input Boards have no jumpers or switches to configure interrupts are configured through software command CONNECTORS IP Field I O Connector P2 P2 provides the field I O interface connector for mating IP modules to the carrier board P2 is a 50 pin female recept
30. omag 6 0 SPECIFICATIONS GENERAL SPECIFICATIONS Operating Temperature 0 to 70 C 40 to 85 E Version Relative Humidity 5 95 Non Condensing Storage Temperature 25 to 85 C 55 to 125 E Version Physical Configuration Single Industrial MO Pack Module Length rte 3 880 in 98 5 mm Willi nette 1 780 in 45 2 mm Board Thickness 0 062 in 1 59 mm Max Component Height 0 314 in 7 97 mm Connectors P1 Logic Interface 50 pin female receptacle header AMP 173279 3 or equivalent P2 Field I O 50 pin female receptacle header AMP 173279 3 or equivalent Power 5 Volts 5 15mA Typical 30mA Maximum 12 Volts 4596 from P1 7 3mA Typical 8 5mA Maximum 12 Volts 4596 from P1 OmA Not Used Non Isolated Logic and field common have a direct electrical connection DIGITAL INPUTS Input Channel Configuration 40 non inverting buffered inputs with a common connection For DC voltage applications only observe proper polarity Channels 0 11 can be configured to generate interrupts Input Signal Voltage Range 0 to 60V DC Maximum Input Signal Threshold TTL compatible 1 5VDC with 200mv of hysteresis typical Thus Low to High threshold is 1 6VDC
31. on cable cable Model 5025 550 X or 5025 551 X Schematic and Physical Attributes See Drawing 4501 465 Field Wiring 50 pin header male connectors 3M 3433 D303 or equivalent employing long ejector latches and 30 micron gold the mating area MIL G 45204 Type II Grade C Connects to Acromag termination panel 5025 552 from the rear of the card cage via flat 50 pin ribbon cable cable Model 5025 550 X or 5025 551 X Connections to AVME9630 9660 50 pin header male connectors 8M 3433 1302 or equivalent employing long ejector latches and 30 micron gold in the mating area per MIL G 45204 Type Il Grade C Connects to AVME9630 9660 boards within the card cage via flat 50 pin ribbon cable cable Model 5025 550 X or 5025 551 X Mounting Transition module is inserted into a 6U size single width slot at the rear of the VMEbus card cage Printed Circuit Board Six layer military grade FR 4 epoxy glass circuit board 0 063 inches thick Operating Temperature 40 C to 85 Storage Temperature 55 C to 105 C Shipping Weight 1 25 pounds 0 6Kg packaged M2x6 Be FLAT HEAD SCREW eee SIDE 2 OF IP MODULE 2 I THREADED M2 lle COMPONENT SIDE SPACER OF CARRIER BOARD 3 3 P1 CONNECTOR FRONT PANEL CONNECTOR OR 19 SCREW 4 ASSEMBLY PROCEDURE 4 1 THREADED SPACERS ARE PROVIDED IN TWO DIFFERENT LENGT
32. on Shielded cable model uses Acromag Part 2002 211 3M Type C3365 50 or equivalent Shielded cable model uses Acromag Part 2002 261 Type 3476 50 or equivalent Headers Both Ends 50 pin female header with strain relief Header Acromag Part 1004 512 8M Type 3425 6600 or equivalent Strain Relief Acromag Part 1004 534 3M Type 3448 3050 or equivalent Keying Headers at both ends have polarizing key to prevent improper installation Schematic and Physical Attributes For Non Shielded cable model see Drawing 4501 462 For Shielded cable model see Drawing 4501 463 Shipping Weight 1 0 pound 0 5Kg packaged TERMINATION PANEL MODEL 5025 552 Type Termination Panel For AVME9630 9660 Boards Application To connect field I O signals to the Industrial I O Pack IP Termination Panel Acromag Part 4001 040 Phoenix Contact Type FLKM 50 The 5025 552 termination panel facilitates the connection of up to 50 field I O signals and connects to the AVME9630 9660 3U 6U non intelligent carrier boards A D connectors only via a flat ribbon cable Model 5025 550 x or 5025 551 x The A D connectors on the carrier board connect the field I O signals to the P2 connector on each of the Industrial Pack modules Field signals are accessed via screw terminal strips The terminal strip markings on the termination panel 1 50 correspond to P2 pins 1 50 on the Industrial I O Pack IP Each Industrial I O Pack IP has its own unique P
33. on interrupt A 1 bit means the interrupt will occur when a Change of State COS occurs at the corresponding input channel i e any state transition Note that interrupts will not occur unless they are enabled see the Interrupt Enable Register INTERRUPT TYPE COS or H L CONFIGURATION REGISTER LSB MSB 15 1413 12 1110 9 8 000 0CHt1 7 6 5 4 32 All bits are set to 0 following a reset which means that the inputs will cause interrupts for the levels specified by the digital input channel Interrupt Polarity Register The unused upper 4 bits of this 16 bit register are always driven low 05 for 8 D16 accesses SERIES IP400 INDUSTRIAL I O PACK 40 CHANNEL DIGITAL INPUT MODULE Interrupt Polarity Register R W The Interrupt Polarity Register determines the level that will cause a channel interrupt to occur for each of the 12 possible interrupt channels channels 0 11 only A 0 bit specifies that an interrupt will occur when the corresponding input channel is BELOW TTL threshold i e a 0 in the digital input channel data register A bit means that an interrupt will occur when the input channel is ABOVE TTL threshold i e a 1 in the digital input channel data register Note that no interrupts will occur unless they are enabled by the Interrupt Enable Register Further the Interrupt Polarity Register will have no effect if the Change of State COS interrupt type is configur
34. pt enable bit should be disabled or reconfigured B If other IP modules have interrupts pending then the interrupt request IRQx will remain asserted This will start a new interrupt cycle 4 0 THEORY OF OPERATION This section describes the basic functionality of the circuitry used on the board Refer to the Block Diagram shown in Drawing 4501 519 as you review this material INPUTS The field I O interface to the carrier board is provided through connector P2 refer to Table 2 1 Field inputs are NON ISOLATED This means that the field return and logic common have a direct electrical connection to each other As such care must be taken to avoid ground loops see Section 2 for connection recommendations Ignoring this effect may cause operation errors and with extreme abuse possible circuit damage Refer to Drawing 4501 518 for example input and grounding connections A Field Programmable Gate Array FPGA is used to generate all the logic necessary to operate the board It is driven by 16 individual input buffers channels 0 15 The balance of the input buffers selectively drive the 16 bit data bus directly Field input signals are tied to the buffer inputs via 100 series connected resistors to limit input current Additionally the buffer inputs are clamped to 4 7V generated from the 12V supply to minimize 5V loading The input signal threshold is TTL compatible The typical threshold is 1 5V DC with about 200mV of
35. ta bus will cause these bits to always read High 1 s 2 The upper 4 bits of these 16 bit registers are driven low 075 3 These registers have no function The upper 4 bits of these 16 bit registers are driven low 05 and pullups on the data bus will cause the lower 12 bits to read high 175 Embedded Not Used addresses occur due to the IP400 s use of the same register architecture as Acromag Model IP408 4 All Read and Write operations require 1 wait state CHOO E Interrupt Vector Register IP Digital Input Registers A B amp C Read Only When the Digital Input Channel Data Registers are read the value read corresponds to the actual state of the input channels at the time of the read A 0 bit means that the corresponding input signal is below TTL threshold a 1 bit means that the corresponding input signal is at or above the TTL threshold approximately 1 6V typical 40 Input channels numbered 0 through 39 may be read Channel Read operations use 8 bit DO8 EO 16 bit D16 words with the lower ordered bits corresponding to the lower numbered channels for the register of interest see below Register A monitors input channels 0 through 15 Register B monitors input channels 16 through 31 Register C monitors input channels 32 through 39 Pullups on the carrier board data bus will cause the upper 8 bits of Register C to read back as high 1 s REGISTER A INPUT CHANNELS 0
36. ware Library diskette Model IPSW LIB M03 MSDOS format to simplify communication with the board AII functions are written in the C programming language and can be linked to your application Refer to the README TXT file in the root directory and the 400 file in the 400 subdirectory on the diskette for more details 2 0 PREPARATION FOR USE UNPACKING AND INSPECTION Upon receipt of this product inspect the shipping carton for evidence of mishandling during transit If the shipping carton is badly damaged or water stained request that the carrier s agent be present when the carton is opened If the carrier s agent is absent when the carton is opened and the contents of the carton are damaged keep the carton and packing material for the agent s inspection For repairs to a product damaged in shipment refer to the Acromag Service Policy to obtain return instructions It is suggested that salvageable shipping cartons and packing material be saved for future use in the event the product must be shipped This board is physically protected with packing material and electrically protected with an anti static bag during shipment However it is recommended that the board be visually inspected for evidence of mishandling prior to applying power CAUTION SENSITIVE ELECTRONIC DEVICES DO NOT SHIP OR STORE NEAR STRONG ELECTROSTATIC ELECTROMAGNETIC MAGNETIC OR RADIOACTIVE FIELDS The board util
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