AXM-D Series and AXM-EDK User`s Manual
Contents
1. 6 BOARD CONFIGURATION 6 any TOR TUAE Tay appear in Default Hardware Configuration 6 this manual and makes no Stan lierna commitment to update or i Panel I O eee ei 6 keep current the information on Isolation Considerations 15 contained in this manual No part of this manual may be 3 0 PROGRAMMING INFORMATION copied or reproduced in any form without the prior written MEMORY MAP iii 16 consent of Acromag Inc Board Status and Reset Register 17 Differential I O Registers 18 Digital Input Output Registers 19 Differential Interrupt Registers 21 4 0 THEORY OF OPERATION DIFFERENTIAL INPUT OUTPUT LOGIC 22 CMOS DIGITAL INPUT OUTPUT LOGIC 23 LVDS INPUT OUTPUT LOGIC 23 LVTTL DIRECT INTERFACE nenne 24 JTAG INTERFACE iii 24 INTERRUPT LOGIC serre 24 PMC XMC BASE BOARD CONNECTION 24 5 0 SERVICE AND REPAIR SERVICE AND REPAIR ASSITANCE 25 PRELIMINARY SERVICE PROCEDURE 25 WHERE TO GET HELP esee 25 Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions Qacromag com http www acromag com AXM D Series and AXM EDK User s Manua2. Dif26 D25 Difa4 LVDS 28 D17 Da 52 DH DIS De Di7 Die AXW EDK 1023 W022 w021 1020 VO19 vote VO17 IO 16 AXW D0i VO23 vo22 Vozi vozo VO 19 vots VO17 vote AXM Do2 Difzs Dif22 Difzi Dif20 Difis Die DIfT7 DTe AXM D03 Dif23 Dif22 DIf21 DIf20 ifie Diiis Difi7 Dire LVDS 20 Hameo i01 i034 MOIS 10 2 TON TO 10 109 68 LAXW Doi vois O14 Vois woi VO Ti voro VOS vos AXW Do2 Difis Difi4 Difis Difi2 DIfti Difto Dio Dif AXW D03 Diis Dita Ditis Diriz Dmi Dii DIO Die LVDS 12 D D6 Hameo 107 i05 0s i04 103 102 i01 09 AXWDoi N07 vos mos Wo4 Vos lo Moi woo AxW Do2 pit Dine Dms Dif Difs bie Dmi owo AXWD03 Di Channels 0 7 are not used in this modue LVDS 4 1 This register definition also applies to the AXM D02 JTAG 2 This register definition also applies to the AXM D04 JTAG Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions Qacromag com http www acromag com AXM D Series and AXM EDK User s Manual Digital I O Mezzanine Board 1 9 Channel read write operations use 8 bit 16 bit or 32 bit data transfers with the lower ordered bits corresponding to the lower numbered channels for the register of interest All input output channels are configured as inputs following a power on or software reset Dat
3. SCSI 3 68 Pin Female Connector Field VO Pin Connections Pin Description Pin Pin Description COMMON COMMON DIFFERENTIAL CHANNELS EA HEALE Digital Channel 8 ARE NUMBERED 8 to 29 Digital Channel 1 RESSE Digital Channel 9 THERE ARE NO Digital Channel 2 Digital Channel 10 DIFFERENTIAL CHANNELS 0 to 7 ON THIS MODULE Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions Qacromag com http www acromag com Digital Channel 3 Digital Channel 4 Digital Channel 5 Digital Channel 6 Digital Channel 7 Differential Ch8 6 8 IN Digital Channel 11 Digital Channel 12 Digital Channel 13 Digital Channel 14 Digital Channel 15 Differential Ch8 Differential Ch9 COMMON Differential Ch104 Differential Ch11 Differential Ch124 Differential Ch134 Differential Ch144 Differential Ch154 Differential Ch162 Differential Ch9 COMMON Differential Ch10 Differential Ch11 Differential Ch12 Differential Ch13 Differential Ch14 Differential Ch15 Differential Ch16 Differential Ch1 7 Differential Ch18 Differential Ch19 COMMON Differential Ch20 Differential Ch21 Differential Ch22 Differential Ch23 Differential Ch24 Differential Ch25 Differential Ch26 Differential Ch27 Differential Ch28 Differential Ch29 Differential Ch17 Differential Ch18 Differential Ch19 COMMON Differential Ch20 Differential Ch21 Differential Ch22 Differential Ch23 Differential Ch24 Differential Ch25 Di
4. Board 3 3 EDK MODULE JTAG PIN FUNCTIONS ION PIN FUNCTION FRONT 1 0 AREA AXM EDK 1 0 LOCATION DRAWING 4502 056A FLAT HEAD 2 56 OPTIONAL FLAT HEAD 2 56 NYLON SCREWS x2 NYLON SCREWS 2 ASSEMBLY PROCEDURE CMC BEZEL AXM MODULE 1 INSERT CMC BEZEL OVER AXM MODULE A I I USE TWO BEZEL SCREWS TO SECURE IF NECESSARY THE PORTION OF THE AXM MODULE I I COVERED BY THE CMC BEZEL IS OUTLINED 2 CAREFULLY ALIGN THE CONNECTORS ON THE PMC MODULE AND THE AXM MODULE PUSH GEMPONENTSIDEGUSQNEDULE TOGETHER B STACKING HEIGHT IS 8 mm i mE CONNECTOR 3 SECURE THE AXM MODULE WITH NYLON STANDOFFS 2 AND WITH 4 SCREWS C TIGHTEN ALL SCREWS CMC BEZEL E um SCREWS 2 AREACOVERED BY ONDER UT 4 THE SCSI CONNECTOR CAN BE FURTHER SECURED TO THE BOARD WITH 2 ADDITIONAL SCREWS D 5 CONNECT THE COMBINED AXM amp PMC MODULE TO THE CARRIER PER THE MANUFACTURE S INSTRUCTIONS PMC MODULE NYLON STANDOFF 2 PMC CONNECTOR J COMPONENT SIDE OF PMC MODULE I H AXM MECHANICAL ASSEMBLY NERA 4502 055A NYLON SCREWS 2 Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http Awww acromag com Digital YO Mezzanine Board 34 AXM D Series and AXM EDK User s Manual a6 L6 LOST S IVd O
5. Table 2 8a AXM EDK Board 34 Pin Double Row 0 1 I O Header Field VO Pin Connections Pin Description Pin Pin Description LVTTL Channel 6 LVTTL Channel 7 LVTTL Channel 10 LVTTL Channel 11 LVTTL Channel 28 LVTTL Channel 29 COMMON COMMON Co co oo ro mo mo ro o 1 aln BID CO CO OD KR PO OO CO AINO Table 2 8b AXM EDK Board Field JTAG Pin Connections 14 Pin 2mm Double Row JTAG Header Pin Description Pin Pin Description common m ___ commons wk common 7 COMMON s or Lana Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com AXM D Series and AXM EDK User s Manual Digital I O Mezzanine Board 1 5 AXM EDK Front I O Auxiliary LVTTL I O Pin Connections SIP Table 2 8c AXM EDK SIP 1 S1 SIP 2 S2 Auxiliary VO Pin Connections Pin Description Pin Pin Description AUX Channel 0 AUX Channel 8 AUX Channel 1 2 AUX Channel 9 AUX Channel 2 3 AUX Channel 10 AUXChane 3 4 AUXChand ii AUX Channel 4 AUX Channels 6 AUXChand i3 AUX Channel 6 AUXChannd7 8 AUX Chane The board is non isolated since there is electrical continuity between the Non Isolation logic and field I O grounds As such the field I O connections are not Considerations isolated from the system Care should be taken in designing installations without isolation to avoid noise pickup and ground loops caused by multiple ground
6. acromag com http www acromag com AXM D Series and AXM EDK User s Manual Digital I O Mezzanine Board 23 2 This register definition also applies to the AXM D04 JTAG Differential I O are provided on the AXM D02 AXM D03 and AXM DX03 DIFFERENTIAL models through the Field I O Connector refer to Table 2 2 to 2 5 Field VO INPUT OUTPUT LOGIC points are NON ISOLATED This means that the field return and logic common have a direct electrical connection to each other As such care must be taken to avoid ground loops Ignoring this effect may cause operation errors and with extreme abuse possible circuit damage Differential channels to the FPGA are buffered using EIA RS485 RS422 line transceivers The transceivers are considered failsafe as a open or short circuit on the I O will not damage the board Field input lines are not terminated External 120 Ohm resistors are recommended on all receivers Signals received are converted from the required EIA RS485 RS422 voltages to the LVTTL levels required by the FPGA Likewise LVTTL signals are converted to the EIA RS485 RS422 voltages for data output transmission The direction control of the differential channels is independently controlled Digital field I O are provided on the AXM D03 AXM DX03 model through CMOS DIGITAL the Field I O Connector refer to Table 2 4 and 2 5 Field I O points are INPUT OUTPUT LOGIC NON ISOLATED This means that the field return and logic common have a direct electrica
7. connections Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 1 6 AXM D Series and AXM EDK User s Manual 3 0 PROGRAMMING INFORMATION AXM EDK amp AXM D GENERIC MEMORY MAP Table 3 2 Memory Map 1 This address space is not defined for this module This space may be used on the base PMC XMC Module Hefer to the base PMC XMC module User s Manual for further information 2 These registers have bits that are reserved for the base PMC XMC module See the register definition later in this manual for further details 3 The bits used in these registers varies for each model Refer to the register descriptions in the following pages for specific module mapping 4 The board will return 0 for all addresses that are Not Used Digital YO Mezzanine Board This Section provides the specific information necessary to program and operate the boards These models are daughter cards intended only for use on specific Acromag PMC XMC modules As such only a small portion of I O memory space is currently reserved for operation of the daughter card The remaining memory space is defined in the base boards User s Manual The generic memory space address map for the board is shown in Table 3 2 The actual bit mapping in the individual registers varies by the mezzanine module and are detailed in the register descriptions later in this manual Note that the base address from the base P
8. data transfers Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http Awww acromag com 1 8 AXM D Series and AXM EDK User s Manual Digital I O Mezzanine Board DIFFERENTIAL Differential amp EDK Input Output Registers Read Write INPUT OUTPUT Base Addr 8004H REGISTERS AXM D2 3 4 differential channels and the AXM D01 and AXM EDK LVTTL channels may be individually accessed via this register at the carrier base address 8004H This includes all 30 differential channels on the AXM D02 AXM D02 JTAG 22 24 differential channels on the AXM D03 AXM DX03 30 LVDS channels on the AXM D04 AXM D04 JTAG 32 general purpose LVTTL channel on the AXM D01 and 30 general purpose LVTTL channels on the AXM EDK Each channel is controlled by its corresponding data bit as shown in the register mapping table below Channel input signal levels are determined by reading this register Likewise channel output signal levels are set by writing to this register Note that the data direction input or output must first be set via theDifferential Direction register at base address plus 8008H Mod Differential VO Register Mapping ba D30 D Das Dav 026 DE DA LAXM EDK nousa 029 w028 1o27 1026 O25 VO24 AxM D01 VO31 VO30 Voze Vo2 vo27 VO26 VO25 1024 AXM D02 NotUsed__ Dif29 Dif28 DI 27 Dif26 Di25 Difz4 AXM D03 NotUsed Dif29 Dif28 Difzz
9. 16 CMOS input output channels on the Front I O for compatible Acromag PMC XMC modules The data direction input output for each channel can be independently controlled Eight change of state interrupt channels are provided on the least significant eight differential channels The AXM EDK board sold with the PMC XMC base boards Engineering Design Kit provides the standard Xilinx JTAG header as well as direct connections to the Xilinx FPGA These general purpose LVTTL Low Voltage TTL I O points allow the user to emulate AXM D modules while using ChipScope Front I O OPERATING MODEL Front I O Type Connector TEMPERATUR E RANGE AXM DO1 64 LVTTL 68 SCSI 40 C to 85 C AXM D02 30 Differential 68 SCSI 40 C to 85 C AXM D02 JTAG 30 Differential 68 SCSI 40 C to 85 C AXM D03 22 Differential amp P 5 feet METTE 68 SCSI 40 C to 85 C AXM DX03 24 Differential amp 5 z peer DIRO 68 SCSI 40 C to 85 C AXM D04 30 LVDS 68 SCSI 40 C to 85 C AXM D04 JTAG 30 LVDS 68 SCSI 40 C to 85 C Xilinx Std JTAG amp o o AXM EDK JTAG amp LVTTL 34 Pin 0 1 Header 49 C to 85 C e Multifunction Modules Various modules allows users to select the Front I O required for their application e Differential Input Output Channels Differential RS485 RS422 can be configured for input or output with independent direction control e Digital Input Output Channels Interface with 5V compliant input output CMOS channels whi
10. 234 Email solutions acromag com http www acromag com 1 2 AXM D Series and AXM EDK User s Manual Digital I O Mezzanine Board AXM D04 Front I O The AXM D04 module has 30 Low Voltage Differential Signaling LVDS channels The data direction of the differential channels numbered 0 to 29 are independently controlled via the Differential Direction Registers The Table 2 6 AXM D04 Board pinout is shown in Table 2 6 Field VO Pin Connections LVDS Ch13 LVDS Ch13 LVDS Ch15 LVDS Ch15 LVDS Ch29 LVDS Ch29 COMMON COMMON O O D D CO1 O1 O1 O1 O1 O1 O1 O1 O71 C1 BH BR BR BR I BR RY RY BR BR CO Gd w GC CO N Ol BR Po OO CO N OD a A V PO CO O CO1 2 GO PO Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com AXM D Series and AXM EDK User s Manual Digital I O Mezzanine Board 1 3 AXM D04 JTAG Front I O The AXM D04 JTAG module has 30 Low Voltage Differential Signaling LVDS channels The data direction of the differential channels numbered 0 to 29 are independently controlled via the Differential Direction Registers The pinout is shown in Table 2 7 Table 2 7 AXM D04 JTAG Board Field I O Pin ci LVDS Ch13 LVDS Ch13 LVDS Ch15 LVDS Ch15 LVDS Ch29 LVDS Ch29 SCSI_TDO SCSI_JTAG_PWR o ojoon oD O1 O1 O1 O1 O1 O1 O1 aj alal BH BR BR BR I BR RR BR BR CO Gd w N ajA O Po 0 CO N OD O01 A
11. 3ISIML at OILVWSHOS N 000000000000 0000000000 20000000000900090000000000C 50000000000100 OO00000000C I 0000000000 oboooooooocooc 20000000coodocopooooooooooc Q3qTiHS AT8IW3SSV 318V9 Nid 89 ISOS cEr 860S TH3QOIlN MAIA LNOH4 20000000000900p0000000000C4 20000000000000b0000000000C L5o0000000oodoobooooooooooC ox pooooooooc X499o08ourgoS8iuo8 5og8autg amp o a 0QOOCOOOOOPOOPOOCOCOOCOOC H 20000000000000p0000000000C a I oo0o0ocooodoobooooocooococ 2000000000odoopooooooooococ eee sw D 3 S Nid L Nid SE Nid amp 230000000000Q900p0000000000C 2000000000000000000000000C amp 000000oooodoobooooooooooC oooocococo oe ooooooooon nnaaabannanannanaonnonaonnaooonnni 2000000000090000000000000C L 2O000000000000000000000000C I2oooocooocooodooboooooooocooc 500000oocooqocopoooooooocooc Sc O00000000000000000000 000000000001 T P pde npa og pad BOaBo Od 5 89 Nid vE Nid 4 o F end R TPA S XS MAIA dOL Id S3HONI 0 0 0 SIHONI 2 87 Zd r Sual3Wz 200000000000900p0000000000C 20000000000000b0000000000C 2000000000odooboooooooocooc IS 20000000000900p0000000000C 2000000000000000000000000C Io00000oooodoobooooooooooC 20000coocoodcopoocoocooocooc E uU OO OM 8808488855808 q85 amp R90NgNBxL Q1 RIB
12. Acromag I AXM D Series and AXM EDK Digital I O Mezzanine Modules USER S MANUAL ACROMAG INCORPORATED Tel 248 295 0310 30765 South Wixom Road Fax 248 624 9234 P O BOX 437 Wixom MI 48393 7037 U S A Copyright 2010 Acromag Inc Printed in the USA Data and specifications are subject to change without notice 8500 796 H 2 AXM D Series and AXM EDK User s Manual Digital I O Mezzanine Board TABLE OF IMPORTANT SAFETY CONSIDERATIONS You must consider the possible negative effects of power wiring CONTENTS component sensor or software failure in the design of any type of control or monitoring system This is very important where property loss or human life is involved It is important that you perform satisfactory overall system design and it is agreed between you and Acromag that this is your responsibility 1 0 General Information The information of this manual KEY FEATURES rece EE eR 4 may change without notice SIGNAL INTERFACE PRODUCTS 5 Acromag makes no warranty ENGINEERING DESIGN KIT 5 of any kind with regard to this BOARD CONTROL SOFTWARE 5 material including but not limited to the implied 2 0 PREPARATION FOR USE warranties of merchantability ang ness Ora parce UNPACKING AND INSPECTION 6 purpose Further Acromag assumes no responsibility for CARD CAGE CONSIDERATIONS
13. G This board utilizes static sensitive components and should only be handled at a static safe workstation CARD CAGE CONSIDERATIONS IMPORTANT Adequate air circulation must be provided to prevent a temperature rise above the maximum operating temperature BOARD CONFIGURATION Default Hardware Configuration Front Panel Field I O Connector Digital YO Mezzanine Board Upon receipt of this product inspect the shipping carton for evidence of mishandling during transit If the shipping carton is badly damaged or water stained request that the carrier s agent be present when the carton is opened If the carrier s agent is absent when the carton is opened and the contents of the carton are damaged keep the carton and packing material for the agent s inspection For repairs to a product damaged in shipment refer to the Acromag Service Policy to obtain return instructions It is suggested that salvageable shipping cartons and packing material be saved for future use in the event the product must be shipped This board is physically protected with packing material and electrically protected with an anti static bag during shipment However it is recommended that the board be visually inspected for evidence of mishandling prior to applying power Refer to the specifications for loading and power requirements Be sure that the system power supplies are able to accommodate the power requirements of the system boards plus the instal
14. M EDK I O are all 3 3V LVTTL The AXM D01 module has 64 LVTTL I O channels connecting directly to the FPGA can be other I O standards This module is for straight thru I O no pull ups or pull downs Custom modules are available for optional pull ups pull downs JTAG and fused power for front I O use The AXM EDK model has a front field I O Xilinx JTAG header It readily connects to any compatible Xilinx programming system such as the MULTIPro Tool or Parallel Cable programming system In general the JTAG interface pins connect only to the Xilinx FPGA See the PMC base board for further information The JTAG interface is powered by 3 3V Eight Channels in each model can be configured to generate interrupts for Change Of State COS and input level polarity match conditions The interrupt is released via a write to the corresponding bit of the Interrupt Status Clear register The channels enabled for interrupt in the example design are Differential Channels 8 to 15 on the AXM D02 AXM D02 JTAG AXM D03 and AXM DX03 LVDS Channels 8 to 15 on the AXM DO4 AXM D04 JTAG LVTTL Channels 8 15 on the AXM EDK and LVTTL Channels 8 15 on the AXM D01 The AXM EDK and AXM D series of extension I O modules are attached to the PMC XMC base board via a high speed 150 pin header The connector provides power to the extension board and multiple logic connections to the base board Note that any PMC XMC base board with a re configurable FPGA will re
15. MC XMC module in memory space must be added to the addresses shown to properly access the board registers Register accesses as 32 16 and 8 bits in memory space are permitted Base D15 Base Addr D00 Addr 000 i 1900 Reserved for base PMC XMC Module DER 7FFC Board Status Register and Software Reset 31 0 Differential amp EDK I O Register Direction Register Differential amp EDK Channels 31 03 800F 31 0 Digital I O Register 8013 Direction Register Digital Channels 31 0 Interrupt Enable Differential Ch 15 8 Interrupt Type Differential Ch 15 8 Interrupt Polarity Differential Ch 15 8 Not Used 8017 Not Used 801B Not Used 801F Not Used 8023 8027 Not Used Not Used go2c 1FFFFC PERE Reserved for base PMC XMC Module This memory map reflects byte accesses using the Little Endian byte ordering format Little Endian uses even byte addresses to store the low order byte The Intel x86 family of microprocessors uses Little Endian byte ordering Big Endian is the convention used in the Motorola 68000 microprocessor family and is the VMEbus convention In Big Endian the lower order byte is stored at odd byte addresses Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions Qacromag com http www acromag com AXM D Series and AXM EDK User s Manual Digital I O Mezzanine Board 1 1 Board Status and Software Reset Register Read Write BOARD STA
16. OO PO CO O CO1 2 GO PO Ol OO CO NI Om O1 Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 1 4 AXM D Series and AXM EDK User s Manual Digital I O Mezzanine Board AXM EDK Front I O The AXM EDK has a standard 34 pin double row 0 1 header for front I O The I O are LVTTL compatible These pin connections can emulate the 30 differential channels on the AXM D02 and AXM D04 models and the 22 24 differential channels on the AXM D03 AXM DX03 model using LVTTL signaling Refer to the Differential I O Register section for further information Front I O connections are listed in Table 2 8a The AXM EDK front I O also includes the standard Xilinx 14 pin 2mm JTAG header This header can be used to directly program the FPGA or to interface with the FPGA debug software ChipScope The pin connections are shown in table 2 8b In addition the AXM EDK contains 16 auxiliary pins that are routed to two 8 pin SIP patterns on the board Note that these are not front panel I O connections Due to height restrictions SIP sockets are not installed This allows for full end user customization These pins correspond to the 16 channels of Digital I O on the AXM D03 AXM DX03 module Refer to the Digital I O Register section for further information The connections are listed in table 2 8c Refer to drawing 4502 056 located at the end of this manual for I O pin locations on the AXM EDK
17. Sv vv v cv Lv Ov 6 8E ZE 96 Se ve ce ZE LE 0 62 8 72 97 S vc E co 120 6L 8LZL SL SL vL EL CL LL OL 6 8 29 S e E 2 L IgL 89 9 99 S9 49 9 Z9 19 09 68 8S ZG 9G SG HG EG CS IS 0S Gp Sp Zi 9v Sh vv Eh Cv Lv Oy 6 ge ZE 9 SE Ve ce ZE IE Oe el 90 S VC ea ee lC 07 6L BL ZL OL SL vL EL CL LL OL 6 829 S ve C Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 3 6 AXM D Series and AXM EDK User s Manual Digital I O Mezzanine Board REVISION HISTORY EGR DOC Description of Revision 28 JAN 14 H LMP Added tables and registers information corresponding to the AXM D02 JTAG and AXM D04 JTAG models Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com
18. TUS AND Base Addr 8000H RESET REGISTER This read write register is used the issue a software reset view and clear pending interrupts and to identify the attached AXM module It may also provide other functions that are defined by the base board Writing a 1 to bit 31 of this register will cause a software reset effecting both the PMC XMC base board and all of the AXM series registers Bits 15 to 13 are used for AXM identification code Bits 0 to 7 or this register reflect the status of each of the Differential I O channels 8 to 15 A Read of this bit reflects the interrupt pending status Read of a 1 indicates that an interrupt is pending for the corresponding differential channel Write of a logic 1 to this bit will release the corresponding differential channel s pending interrupt Writing 0 to a bit location has no effect a pending interrupt will remain pending o Differential Channel mtemuptPendmg Oear J 6 Differential Channel 14 Interrupt Pending Clear Reserved for PMC XMC base board AXM Identification bits Read Only TEE st Some Reset Wite ony ______ Note that if no A module is the register will still read 001 It is up to the end user to differentiate if no mezzanine module is attached 2 All other 3 bit values are reserved for future use 3 Bit function is defined by the base PMC XMC Module This register can be written with either 8 bit 16 bit or 32 bit
19. a S OO LL O0000000000 OOOCOOCOOOOCC 290905n90808 508a8 BIBSBABHBESBRIYNRGASK BA BABRUHA BAS ABLHLHEHLSLE STEVEN LI L ld cH TI3HS30v8 03073lHS Zd Id OL SLOJNNOD 318VO NO GIZIHS ONNOHI e A Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com Digital I O Mezzanine Board 3 5 AXM D Series and AXM EDK User s Manual 0026 LOST MalA LNOYWS A 989 SOND E Le NOLLVNIAH3 L 89 9 99 S9 v9 9 Z9 19 09 6S 8G ZG 9G SG HG ES ZG IS 0S Gp 8v Zi Ov Sh Vv Eb cv Iv Ob 6C 8E LE 9 SE SHILINITTIN 1 ILILILILILILI OUUU SIHONI NI 3HV SNOISNAINIO rece Z LE 0 62 87 22 9 Z vC C2 Z l2 07 6L GL ZI OL GL vL EL ZL IL OL 6 8 Z 9 S 4 E ZL LON Y MAIA dOL ee MIA 30IS A ooooooooooooooooooooooooooooO00000 VA i IE o0o0000000000000000000000000000000 S 3Y3H 138v1 rar 7 IMYIS ICON 39v 1d p A 9 98 ml 07 z eal pas le dL A ne 1 AR LR S o o LC 22 zal 89 Nd Y OLLVIN3HOS TANVd NOILVNIINH3 L 882 8208 1500N 89 9 99 SI v9 9 Z9 19 09 6S 99 ZG 9G SG vS ES ZG IS 0S Gp 8p Ly OV
20. a bits 30 and 31 are not used and will return 0 when read for all but the AXM D01 AXM DX03 module Data bits 0 through 7 in the AXM D03 AXM DX03 module will read back the last data values written to those bits except for bits 0 amp 1 will always read 0 Differential Direction Control Register Read Write DIFFERENTIAL Base Addr 8008H INPUT OUTPUT REGISTERS The data direction input or output of the differential channels is selected via this register at the carrier base address 8008H This includes the direction of all 32 differential channels on the AXM D01 30 differential channels on the AXM D02 AXM D02 JTAG 22 24 differential channels on the AXM D03 AXM DX03 30 LVDS channels on the AXM D04 AXM D04 JTAG and 30 general purpose LVTTL channels on the AXM EDK The direction of each channel is controlled by its corresponding data bit Data bit use varies depending on the module selected The bit mapping corresponds to the Differential and EDK I O Register Independent channel direction control is provided for each differential channel Setting a bit low configures the corresponding channel data direction for input Setting the control bit high configures the corresponding channel data direction for output The default power up state of these registers is logic low Thus all channels are configured as inputs following system reset or power up Reading or writing to this register is possible via 32 bit 16 bit or 8 bit data transf
21. acromag com 2 8 AXM D Series and AXM EDK User s Manual Termination Resistors DIGITAL I O CMOS Digital I O DC Electrical Characteristics Digital Propagation Delay LVDS I O LVDS I O Electrical Characteristics LVDS Propagation Delay Maximum Data Rate Termination Resistors Digital YO Mezzanine Board Termination Resistors Termination resistor are not provided External 120 Ohm termination resistors for EIA RS485 422 differential receivers are recommended CMOS Channel Configuration 16 Channels AXM D02 AXM D02 JTAG of Bi directional CMOS Transceivers Direction controlled as pairs of channels Reset Power Up Condition All Digital Channels Default to Input e Digital I O DC Electrical Characteristics e Von 3 8V minimum e Vor 0 55V maximum e lox 32 0mA e log 32 0mA e Vy 3 5V minimum e Vi 1 5V maximum e Driver Receiver Input to Output Delay 4ns Typical Pull up Resistors 10K pull up resistors to 5V are installed on each CMOS I O line Channel Configuration 30 Channels AXM D04 AXM D04 JTAG Bi directional LVDS signals are independently direction controlled e 247m V Min 454mV Max LVDS Driver Output Voltage with 500 load e 1 37 V Max Common Mode Output Voltage e 50 mV Min to 50mV Max LVDS Input Threshold Voltage e Interface with either standard LVDS TIA EIA 644 or M LVDS TIA EIA 899 for Multipoint Data Interchange e Driver Propagation Delay Time 2 7ns Maximum e Driver O
22. al Ch1 Differential Ch2 Differential Ch3 Differential Char 6 Differential Ch4 Differential Ch5 Differential Ches 8 Differential Che Differential Ch7 9 Diferential Ch7 Differential Ch Differential Cho COMMON 12 COMMON Differential ChTO Differential Chi 1 Differential Ch12 Differential Ch3 Differential Ch 4 QW N N O o ojoj ojo Cc1 O1 O1 O1 O1 O1 O1 O1 OF CT BR BR BR BR BR BR RR BR BR Co Gd CG GC CO N ajA OO Po CO N OD Aa BR GC PO CO O CO DAI GO PO Ol OO OO H Om O1 o Differential Ch15 Differential Chi6 Differential Ch17 2 Differential Ch18 N Co o O c o common 23 COMMON Differential Ch20 Differential chat 25 Differential CR21 Differential Ch22 N oje Differential Ch23 27 Differential Ch23 Differential Ch24 28 Differential Ch24 Differential Ch25 29 Differential Ch25 NO DO Po oo I Differential Ch26 Differential Ch27 Differential Ch28 Differential Ch29 COMMON wo Differential Ch19 Differential Ch19 Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com AXM D Series and AXM EDK User s Manual Digital I O Mezzanine Board 9 The AXM D02 JTAG module has 30 differential I O channels The data direction of the differential channels numbered 0 to 29 are independently controlled via the Differential Direction Register The pi
23. ch can be configured as input or output with independent direction control e LVDS Input Output Channels Low voltage differential signaling can be configured for input or output with independent direction control e Xilinx JTAG Interface The AXM D02 JTAG AXM D04 JTAG and EDK boards provides the standard Xilinx JTAG interface to allow direct programming of the FPGA and an interface with ChipScope e Programmable Change of State Level Interrupts Example code provides interrupts that are software programmable for any bit Change Of State or level on 8 channels Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions Qacromag com http www acromag com AXM D Series and AXM EDK User s Manual Digital I O Mezzanine Board 5 e Example Design The example VHDL design provided in the base board EDK includes control of all I O and eight Change Of State interrupts The AXM D models I O is accessed via a 68 pin SCSI front panel connector Cables and a termination panel are available to interface with these boards Cable Model 5028 432 A 2 meter round 68 conductor shielded cable with a male SCSI 3 connector at both ends and 34 twisted pairs This cable is used for connecting the board to Model 5025 288 termination panels For optimum performance use the shortest possible length of shielded cable Termination Panel Model 5025 288 DIN rail mountable panel provides 68 screw terminals for universal field I O
24. ers Data bits 30 and 31 are not used and will return O when read for all but the AXM D01 AXMDX03 module Data bits 0 through 7 in the AXM D03 AXM DX03 module will read back the last data values written to those bits except for bits 0 amp 1 will always read 0 Digital Input Output Registers Read Write DIGITAL Base Addr 800CH INPUT OUTPUT Digital CMOS input output channels may be individually accessed via this REGISTERS register at the carrier base address 800CH This includes the sixteen CMOS Channels on the AXM D03 AXM DX03 32 upper data channels for the AXM D01 and the sixteen auxiliary LVTTL I O on the AXM EDK module Channel input signal levels are determined by reading this register Likewise channel output signal levels are set by writing to this register The data bits are mapped according to the following table Note that the data direction input or output must first be set via the Digital Direction register at base address plus 8010H Model Digital VO Register Mapping SIE LV a UN D26 D25 D24 ie ae ili AXM D01 1O63 O62 VO61 voso O59 VO58 VO57 VOS6 AXM D02 Not Used Noted AXM DO3 Not Used Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 2 Q AXM D Series and AXM EDK User s Manual Digital I O Mezzanine Board AXM DX03 Not Used AXM D04 No
25. es See Drawing 4501 920 Field Wiring 68 position terminal blocks with screw clamps Wire range 12 to 26 AWG Mounting Termination panel is snapped on the DIN mounting rail Printed Circuit Board Military grade FR 4 epoxy glass circuit board 0 063 inches thick Operating Temperature 40 C to 100 C Storage Temperature 40 C to 100 C Shipping Weight 1 0 pounds 0 5kg packaged Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions Qacromag com http www acromag com AXM D Series and AXM EDK User s Manual Digital I O Mezzanine Board 3 1 CONNECTOR FRONT I O TO PMC INTERFACE dads T BASEBOARD P2 45V Optional Fused Power PI I 43 3V for Front I O Use prota e e e 10K 10K 10K 10K Optional Pull up Resistors 1 00 kx gt 1 00 1 01 gt 1 01 64 i LVTTL I O INPUT OUTPUT e TO FPGA CHANNELS e 1 062 lt gt 1 062 1 063 x gt 1 063 10K S 10K 2 10K 3 10K Optional Pull down Resistors GND e e 9 e GND GND GND JTAG JTAG Optional JTAG from Front I O Use AXM D 1 BLOCK DIAGRAM 4502 156A CONNECTOR TO PMC FRONT I O BASEBOARD INTERFACE P1 P2 DIFF CHANNEL 29 DIFF DIRECTION CONTROL TERMINATION RESISTOR JS DIFF CHANNEL 29 NOT PROVIDED P x Y LVTTL I O TO FPGA 30 RS485 RS422 A DIFFERENTAL INPUT OUTPUT e DIFF CHANNEL 0 CHANNELS DIFF DIRECTION CONTROL F 10K TERMINATION RESISTOR
26. fferential Ch26 Differential Ch27 Differential Ch28 Differential Ch29 AXM D Series and AXM EDK User s Manual Digital I O Mezzanine Board 1 1 The AXM DX03 module has 24 differential I O channels and 16 digital AXM DX03 Front I O CMOS channels The data direction of the differential channels numbered 16 to 39 and digital channels numbered 0 to 15 are independently controlled via the Differential and Digital Direction Registers The pinout is shown in Table 2 5 SCSI 3 68 Pin Female Connector Table 2 5 AXM DX03 Board Pin Description Pin Description Field VO Pin Connections Digital Channel 0 COMMON Digital Channel 1 COMMON Digital Channel 2 Differential Ch24 DIFFERENTIAL CHANNELS Digital Channel 3 4 Differential Ch24 ARE NUMBERED 8 to 29 Digital Channel 4 Differential Ch254 THERE ARE NO DIFFERENTIAL CHANNELS Digital Channel 5 6 Differential Ch25 0 to 7 ON THIS MODULE Digital Channel 6 i Digital Channel 7 Digital Channel 8 Digital Channel 9 Digital Channel 10 Digital Channel 11 Digital Channel 12 Digital Channel 13 Digital Channel 14 Digital Channel 15 COMMON COMMON Differential Ch16 Differential Ch16 Differential Ch17 Differential Ch17 Differential Ch18 Differential Ch18 Differential Ch19 Differential Ch19 Differential Ch20 Differential Ch20 Differential Ch21 Differential Ch21 Differential Ch22 Differential Ch22 Differential Ch23 Acromag Inc Tel 248 295 0310 Fax 248 624 9
27. gt DIFF CHANNEL 0 NOT PROVIDED ee r gt i v AXM D 2 BLOCK DIAGRAM 4502 051A P1 Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 3 2 AXM D Series and AXM EDK User s Manual Digital YO Mezzanine Board ae CONNECTOR TO PMC INTERFAGE DIFF CHANNEL 29 Ra e DIRECTION CONTROL dii pem DIFF CHANNEL 29 TERMINATION RESISTOR NOT PROVIDED 10K 22 RS485 422 E DIFFERENTIAL s 4 CHANNELS DIFF CHANNEL 8 DIRECTION CONTROL LVTTL IO LE TO FPGA TERMINATION RESISTOR p DIFE CHANNEL amp NOT PROVIDED leg J 45V Y DIG CHANNEL 15 DIRECTION CONTROL 10K DIG CHANNEL 15 r gt re 3 10K 16 CMOS Pj DIG CHANNEL 0 DIGITAL e Y DIRECTION CONTROL INPUT OUTPUT 45V CHANNELS DIG CHANNEL 0 10K 10K Imi v AXM D 3 BLOCK DIAGRAM 4502 051A P2 CONNECTOR FRONT I O TO PMC INTERFACE BASEBOARD P2 DIFF CHANNEL 29 P1 DIRECTION CONTROL pes DIFF CHANNEL 29 1 100 Ohms n e v LVTTL I O gt TO FPGA 30 LVDS INPUT OUTPUT e DIFF CHANNEL 0 CHANNELS DIRECTION CONTROL i DIFF CHANNEL 0 100 Ohms i 10K L v AXM D04 BLOCK DIAGRAM 4502 051A P3 Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com AXM D Series and AXM EDK User s Manual Digital I O Mezzanine
28. hen the input channel is high i e a 1 in the differential input channel data register Note that no interrupts will occur unless they are enabled by the Interrupt Enable Register Further the Interrupt Polarity Register will have no effect if the Change of State COS interrupt type is configured by the Interrupt Type Configuration Register The Interrupt Polarity register at the base address offset 801CH is used to control differential channels 8 through 15 as mapped in the Interrupt Enable Register For example channel 8 is controlled via data bit 0 Bits 8 to 15 are not used and will always read as 0 All bits are set to 0 following a reset which means that the inputs will cause interrupts when they are logic low provided they are enabled for interrupt on level This section contains information regarding the hardware of the board A description of the basic functionality of the circuitry used on the board is also provided Note that each section does not necessarily apply to every model Refer to table below to determine the appropriate sections MODEL VOType Interrupts JAG AXM DO1 64 LVTTL 8 Channels T AXM D02 30 Differential 8 Channels 22 Differential amp AXM D03 16 CMOS Digital 8 Channels e 24 Differential amp AXM D04 30 LVDS 8 Channels AXM EDK 30 LVTTL 8 Channels 1 This register definition also applies to the AXM D02 JTAG Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions
29. l Digital I O Mezzanine Board 3 6 0 SPECIFICATIONS TABLE OF CONTENTS PHN SIG ALA aco A A ella lrn 26 ENVIRONMENTAL 11 nennen nnn nnn 26 DIFFERENTIAL INPUT OUTPUT cie 27 DIGITAL INPUT OUTPUT eren 28 LVDS INPUT OUT PUT eere nnn nnn 28 LVTTL INPUT OUTPUT eeeererene mnn nnn 29 APPENDIX CABLE MODEL 5028 432 ceca nnns 30 TERMINATION PANEL MODEL 5025 288 30 DRAWINGS 4502 156 AXM D01 BLOCK DIAGRAM 31 4502 051P1 AXM D02 BLOCK DIAGRAM 31 4502 051P2 AXM D03 BLOCK DIAGRAM 32 4502 051P3 AXM D04 BLOCK DIAGRAM 32 4502 056 AXM EDK I O LOCATION DRAWING 33 4502 055 AXM MECHANICAL ASSEMBLY 33 4501 919 CABLE 5028 432 SHIELDED 34 4501 920 TERMINATION PANEL 5025 288 35 REVISION HISTORY Table i enne 36 Trademarks are the property of their respective owners Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 4 AXM D Series and AXM EDK User s Manual Digital I O Mezzanine Board 1 0 GENERAL INFORMATION Table 1 1 AXM D Series and AXM EDK Models KEY FEATURES The AXM D series of daughter boards offer numerous digital options for Front I O to Acromag s line of re configurable PMC XMC modules The AXM D03 AXM DX03 provides 22 24 differential amp
30. l connection to each other As such care must be taken to avoid ground loops Ignoring this effect may cause operation errors and with extreme abuse possible circuit damage Digital input output signals to the FPGA are buffered using a dual voltage digital transceiver Signals received are converted from 5V CMOS to LVTTL as required by the FPGA Likewise LVTTL signals are converted to 5V CMOS voltages for data output transmission The direction control of the digital channels is independently controlled Each field line has a 10K pullup resistor to 5V Output operation is considered Fail safe That is the Digital Input Output signals are always configured as inputs following a power up or software reset This is done for safety reasons to ensure reliable control under all conditions LVDS I O on the AXM D04 are provided through the Field I O Connector LVDS INPUT OUTPUT refer to Table 2 6 and 2 7 Field I O points are NON ISOLATED This LOGIC means that the field return and logic common have a direct electrical connection to each other As such care must be taken to avoid ground loops Ignoring this effect may cause operation errors and with extreme abuse possible circuit damage LVDS channels 0 31 to the FPGA are buffered using multidrop LVDS line drivers and receivers The drivers and receivers are standard LVDS signaling characteristics TIA EIA 644 with double the current for multipoint applications Field inputs to these receive
31. larity Register occurs i e Low or High level transition interrupt A 1 bit means the interrupt will occur when a Change Of State COS occurs at the corresponding input channel i e any state transition low to high or high to low The Interrupt Type Configuration register at base address 8018H is used to control channels 8 through 15 as mapped in the Interrupt Enable Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 2 2 AXM D Series and AXM EDK User s Manual Digital I O Mezzanine Board 4 0 THEORY OF OPERATION Register For example channel 8 is controlled via data bit 0 Bits 8 to 15 are not used and will always read as O All bits are set to 0 following a reset which means that if enabled the inputs will cause interrupts for the levels specified by the Interrupt Polarity Register Channel read or write operations use 8 bit 16 bit or 32 bit data transfers Note that no interrupts will occur unless they are enabled by the Interrupt Enable Register Interrupt Polarity Register Read Write Base Addr 801C The Interrupt Polarity Register determines the level that will cause a channel interrupt to occur for each of the channels enabled for level interrupts A O bit specifies that an interrupt will occur when the corresponding input channel is low i e a 0 in the differential input channel data register A 1 bit means that an interrupt will occur w
32. led Acromag board within the voltage tolerances specified Adequate air circulation must be provided to prevent a temperature rise above the maximum operating temperature and to prolong the life of the electronics Ifthe installation is in an industrial environment and the board is exposed to environmental air careful consideration should be given to air filtering Remove power from the system before installing board cables termination panels and field wiring The AXM EDK and AXM D Series boards cannot stand alone and must be mated with a compatible Acromag PMC XMC module The default configuration of the control register bits at power up is described in section 3 The front panel connector provides the field I O interface connections For the AXM D series it is a SCSI 3 68 pin female connector AMP 5787394 7 or equivalent employing latch blocks and 30 micron gold in the mating area per MIL G 45204 Type II Grade C Connects to Acromag termination panel 5025 288 from the front panel via round shielded cable Model 5028 432 The AXM EDK board has two front I O connectors The first is a double row 14 pin 2mm header male for JTAG programming This is the standard Xilinx JTAG Header The other I O interface is a double row 34 pin 0 1 header male A standard floppy drive cable can be used to connect to the interface Note neither cables are available from Acromag Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solution
33. ly for technical assistance via telephone or email Contact information is located at the bottom of this page When needed complete repair services are also available Digital I O Mezzanine Board 2 5 5 0 SERVICE AND REPAIR SERVICE AND REPAIR ASSISTANCE PRELIMINARY SERVICE PROCEDURE CAUTION POWER MUST BE TURNED OFF BEFORE REMOVING OR INSERTING BOARDS WHERE TO GET HELP www acromag com Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http Awww acromag com 2 6 AXM D Series and AXM EDK User s Manual Digital I O Mezzanine Board 6 0 SPECIFICATIONS PHYSICAL Unit Weight Including all mounting hardware Connectors Table 6 1 Power Requirements for Example Design ENVIRONMENTAL Single AXM Board Height 11 5 mm 0 453 in Stacking Height 8 0 mm 0 315 in Depth 31 0 mm 1 220 in Width 74 0 mm 2 913 in Board Thickness 0 8 mm 0 031 in AXM EDK 0 430z 0 01218Kg AXM D01 1 360z 0 0386Kg AXM D02 AXM D02 JTAG 1 360z 0 0386Kg AXM D03 1 390z 0 0395Kg AXM DX03 1 390z 0 0395Kg AXM D04 AXM D04 JTAG 1 390z 0 0394Kg e AXM D Front Field I O 68 pin SCSI 3 female receptacle male header AMP 5787394 7 or equivalent e AXM EDK Front Field I O 14 pin 2mm double row male header standard Xilinx JTAG header 34 pin 0 1 double row header Power Requirements i ai AXM D01 Not Used i ote E yes 1 Power source is the base board Current draw is for AXM mod
34. nclosure port air discharge Level 2 4KV enclosure port contact discharge Level 1 2KV I O terminals contact discharge and European Norm EN50082 1 Radiated Emissions Meets or exceeds European Norm EN50081 1 for class B equipment Shielded cable with I O connections in shielded enclosure are required to meet compliance Mean Time Between Failure MIL HDBK 217F Notice 2 at 25 C AXM D01 TBD Hours AXM D02 AXM D02 JTAG 3 559 276 Hours AXM D03 3 921 522 Hours AXM DX03 TBD Hours AXM D04 AXM D04 JTAG 6 534 197 Hours AXM EDK N A No active components Reliability Prediction Channel Configuration 30 AXM D02 AXM D02 JTAG or 22 AXM DIFFERENTIAL I O D04 AXM D04 JTAG Bi directional EIA 485 422 differential signals are independently direction controlled e 1 5 V Min 3 3V Max Differential Driver Output Voltage with 540 load E Rake d dd n Vo e 3 V Max Common Mode Output Voltage Sctica aracteristics e 0 2 Min to 0 05 Max Differential Input Threshold Voltage 7V lt Vcm lt 12V e 15mV Typical Input Hysteresis e 96KO Minimum Input Resistance The receiver contains a fail safe feature that results in a logic high output state if the inputs are unconnected floating or shorted e Driver Input to Output Delay 27ns Typical 40ns Maximum Differential Propagation e Receiver Input to Output Delay 33ns Typical 60ns Maximum Delay Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www
35. nerating an external interrupt A 1 bit will allow the corresponding channel to generate an interrupt The Interrupt Enable register at the base address offset 8014H is used to control channels 8 through 15 via data bits O to 7 Bits 8 to 15 are not used and will always read as 0 All channel interrupts are disabled set to 0 following a power on or software reset Reading or writing to this register is possible via 32 bit 16 bit or 8 bit data transfers Additional steps may be required to enable interrupts Refer to the PMC XMC base module s User s Manual for further information D7 Era D6 p2 Bt po AXM D01 I O 15 VO 14 I O 13 I O 12 O 11 I O 10 I O 9 I O 8 AXM D02 Difi 15 Diff 14 Diff 13 Diff 12 Diff 11 Diff 10 Diff 9 Diff 8 Model Interrupt Register Mapping D5 j D3 AXM D03 Diis Difi4 Difis Dif12 Difii Difio Dimo Die 1 This register definition also applies to the AXM D02 JTAG 2 This register definition also applies to the AXM D04 JTAG Interrupt Type COS or H L Configuration Register DIFFERENTIAL Read Write Base Addr 8018 INTERRUPT REGISTERS The Interrupt Type Configuration Register determines the type of input channel transition that will generate an interrupt for each of the eight possible interrupting channels A 0 bit selects interrupt on level An interrupt will be generated when the input channel level specified by the Interrupt Po
36. nout is shown in AXM D02 JT AG Front I O Table 2 3 SCSI 3 68 Pin Female Connector ECHO AER Pin Description Pin Pin Description DOR EGHORE SCSI TCK COMMON Differential ChO Differential ChO Differential Ch1 Es Differential Ch1 Differential Ch2 Differential Ch2 Differential Ch3 5 Differential Ch3 Differential Ch4 Differential Ch4 Differential Ch5 Differential Ch5 Differential Ch6 8 Differential Ch6 Differential Ch7 9 Differential Ch7 Differential Ch8 Differential Ch9 SCSI_TMS Differential Ch10 Differential Ch11 Differential Ch12 Differential Ch13 Differential Ch14 Differential Ch15 Differential Ch16 Differential Ch17 Differential Ch18 Differential Ch19 SCSI_TDI Differential Ch20 Differential Ch21 Differential Ch22 Differential Ch23 Differential Ch24 Differential Ch25 Differential Ch26 Differential Ch27 Differential Ch28 Differential Ch29 SCSI_TDO Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 1 Q AXM D Series and AXM EDK User s Manual Digital I O Mezzanine Board AXM D03 Front I O The AXM D03 module has 22 differential I O channels and 16 digital CMOS channels The data direction of the differential channels numbered 8 to 29 and digital channels numbered 0 to 15 are independently controlled via the Differential and Digital Direction Registers The pinout is shown in Table 2 4 Table 2 4 AXM D03 Board
37. on Used to connect Model 5025 288 termination panel to the board Length Standard length is 2 meters 6 56 feet Consult factory for other lengths It is recommended that this length be kept to a minimum to reduce noise and power loss Cable 68 conductors 28 AWG on 0 050 inch centers permits mass termination for IDC connectors foil braided shield inside a PVC jacket Connectors SCSI 3 68 pin male connector with backshell Keying The SCSI 3 connector has a D Shell Schematic and Physical Attributes See Drawing 4501 919 Electrical Specifications 30 VAC per UL and CSA SCSI 3 connector spec s 1 Amp maximum at 50 energized SCSI 3 connector spec s Operating Temperature 30 C to 80 C Storage Temperature 40 C to 85 C Shipping Weight 1 0 pound 0 5Kg packed Type Termination Panel For 68 Pin SCSI 3 Cable Connection Application To connect field I O signals to the board Termination Panel Acromag Part 4001 066 The 5025 288 termination panel facilitates the connection of up to 68 field I O signals and connects to the board connectors only via a round shielded cable Model 5028 432 Field signals are accessed via screw terminal strips The terminal strip markings on the termination panel 1 68 correspond to field I O pins 1 68 on the board Each board has its own unique pin assignments Refer to the board manual for correct wiring connections to the termination panel Schematic and Physical Attribut
38. put or output of the digital channels is selected via this register at the carrier base address 8010H This includes the 32 data channels on the AXM D01 sixteen CMOS Channels on the AXM D03 AXM DX03 and the sixteen auxiliary LVTTL I O on the AXM EDK module The direction of each channel is controlled by its corresponding data bit The register mapping is the same as the Digital I O Register Data bits 0 through 15 on the AXM D02 AXM D02 JTAG and AXM D04 AXM D04 JTAG modules are not used and will read back the last data value written to them Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions Qacromag com http www acromag com AXM D Series and AXM EDK User s Manual Digital I O Mezzanine Board 2 1 Independent channel direction control is provided for each digital channel Setting a bit low configures the corresponding channel data direction for input Setting the control bit high configures the corresponding channel data direction for output The default power up state of these registers is logic low Thus all channels are configured as inputs following system reset or power up Reading or writing to this register is possible via 32 bit 16 bit or 8 bit data transfers Interrupt Enable Register Read Write DIFFERENTIAL Base Addr 8014H INTERRUPT The Interrupt Enable Register provides a map bit for each differential REGISTERS channel from 8 to 15 A 0 bit will prevent the corresponding input channel from ge
39. quire the pin definitions provided in the EDK to properly operate the AXM EDK and AXM D series boards Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions Qacromag com http www acromag com AXM D Series and AXM EDK User s Manual Surface Mounted Technology SMT boards are generally difficult to repair It is highly recommended that a non functioning board be returned to Acromag for repair The board can be easily damaged unless special SMT repair and service tools are used Further Acromag has automated test equipment that thoroughly checks the performance of each board When a board is first produced and when any repair is made it is tested placed in a burn in room at elevated temperature and retested before shipment Please refer to Acromag s Service Policy Bulletin or contact Acromag for complete details on how to obtain parts and repair Before beginning repair be sure that all of the procedures in Section 2 Preparation For Use have been followed Also refer to the documentation of your carrier CPU board to verify that it is correctly configured Replacement of the board with one that is known to work correctly is a good technique to isolate a faulty board If you continue to have problems your next step should be to visit the Acromag worldwide web site at http www acromag com Our web site contains the most up to date product and software information Acromag s application engineers can also be contacted direct
40. rs include a 100 ohm termination resistor Signals received are converted from the LVDS voltages to the LVTTL levels required by the FPGA Likewise LVTTL signals are converted to the TIA EIA 644 LVDS voltages for data output transmission The direction control of the LVDS channels is independently controlled Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com DA AXM D Series and AXM EDK User s Manual Digital I O Mezzanine Board LVTTL DIRECT INTERFACE JTAG INTERFACE INTERRUPT LOGIC PMC XMC BASE BOARD CONNECTION The AXM EDK has a total of 46 30 General Purpose and 16 auxiliary channels of LVTTL These I O provide a direct connection through the mezzanine connector to the adjoining FPGA There are no intermediate buffers on the I O As such care must be taken to limit overshoot to 3 6V and to prevent ESD or the FPGA on the PMC XMC base board may be damaged The I O on the AXM EDK are mapped to simulate the various types of I O that can be found on the AXM D series modules Therefore the same registers can be used to simulate the Field I O on the AXM EDK The 30 general purpose I O map to the 30 differential I O on the AXM DO2 AXM D02 JTAG the 22 24 differential I O on the AXM D03 AXM DX03 and 30 LVDS I O on the AXM D04 AXM D04 JTAG The 16 auxiliary I O map to the 16 differential signal on the AXM D03 AXM DX03 Note that regardless of which AXM D module is being emulated the AX
41. s acromag com http www acromag com AXM D Series and AXM EDK User s Manual Digital I O Mezzanine Board y The AXM D01 module has 64 LVTTL I O channels connecting directly to AXM D01 Front I O the FPGA can be other I O standards This module is for straight thru I O no pull ups or pull downs Custom modules are available for optional pull ups pull downs JTAG and fused power for front I O use The pin out is shown in Table 2 1 SCSI 3 68 Pin Female Connector Table 2 1 AXM D01 Board Pin Description Pin Pin Description Pin Field VO Pin Connections Feens 2 COMMON 36 vmo 5 lVHLIOS LVTTL IO 6 6 LVTTL IO 7 40 mos tos sr ivmioi 8 wmon a ivmoi 9 mor 1vnLio4s 26 LlVHLIO47 o ivmiioss 2 LVHLIOSS 66 1vriios2 1 34 vmos Optional fused power for front I O use Optional JTAG for front panel use Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 8 AXM D Series and AXM EDK User s Manual Digital I O Mezzanine Board The AXM D02 module has 30 differential YO channels The data 2 nt AANEDOZ ELORO direction of the differential channels numbered 0 to 29 are independently controlled via the Differential Direction Register The pinout is shown in Table 2 2 Table 2 2 AXM D02 Board Field VO Pin Connections PinDescription Pin Pin Description COMMON COMMON Differential ChO Differenti
42. t Used AXM EDK NotUsed AXM DO1 1 055 I O 54 O 53 I O 52 O 51 I O 50 l O 49 I O 48 AXM DO2 Not Used AXW D3 NoUsd D5 D14 D13 D12 Dii Dio D9 DB AXM EDK AUX 15 AUX 14 AUX18 AUXi2 AUXTi AUX10 AUXS AUXS AXW Doi 1047 W046 lO45 N044 vo4s lO42 VO4i 1040 AXM D92 Not Used fe ee a NE MM AE AXW D03 DIG 5 DIGIA oen DiG i2 DIGI DIGIO DIGI DIG Not Used o D Ds a D3 o bi P AXM EDK AUX7 AUX6 AUXS AUX4 AUX3 AUX2 AUXi AUXO AXW D01 1039 voss O37 Voss Voss VO34 voss 1o32 AXM D02 _ Not Used AXW D03 DIG7 DIGG DIGS DIG4 DIG3 DIG2 DIGI DIGO Not Used 1 This register definition also applies to the AXM D02 JTAG 2 This register definition also applies to the AXM D04 JTAG annel read write operations use 8 bit 16 bit or 32 bit data transfers wi DIGITAL Channel read wri i 8 bit 16 bit or 32 bit d fers with INPUT OUTPUT the lower ordered bits corresponding to the lower numbered channels for REGISTERS the register of interest All input output channels are configured as inputs following a power on or software reset Data bits 0 through 15 on the AXM D02 AXM D02 JTAG and AXM D04 AXM D04 JTAG modules are not used and will read back the last data value written to them Digital Direction Control Register Read Write Base Addr 8010H The data direction in
43. termination Connects to Acromag board via SCSI 3 to twisted pair cable described above Acromag does not provide an engineering design kit specifically for the AXM D modules However an example design for each module is included in the Engineering Design Kit of the PMC XMC base board Furthermore the AXM EDK is included with the Engineering Design Kit of the PMC XMC base board to allow for programming via the JTAG interface Refer to the PMC XMC base board s manual for further information on the available Engineering Design Kit Acromag does not provide board control software specifically for the AXM EDK and AXM D series boards However the AXM EDK and each AXM D module can be accessed via the control software for the base PMC XMC module These products sold separately facilitate the product interface in the following operating systems Windows DLL VxWorks and QNX Refer to the PMC XMC base board s manual for further information SIGNAL INTERFACE PRODUCTS See the Appendix for further information on these products ENGINEERING DESIGN KIT BOARD CONTROL SOFTWARE Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 6 AXM D Series and AXM EDK User s Manual 2 0 PREPARATION FOR USE UNPACKING AND INSPECTION Te J CAUTION SENSITIVE ELECTRONIC DEVICES DO NOT SHIP OR STORE NEAR STRONG ELECTROSTATIC ELECTROMAGNETIC MAGNETIC OR RADIOACTIVE FIELDS WARNIN
44. ule only 2 With of I O as inputs as outputs and at 25 C 3 The AXM EDK and AXM D01 has no components that draw power It is simply a pass though board 4 Floating or shorted I O will have higher current draw 5 Power also applies to the AXM D02 JTAG model 6 Power also applies to the AXM D04 JTAG model Operating Temperature 40 C to 85 C Relative Humidity 5 95 Non Condensing Storage Temperature 55 C to 150 C AXM D01 40 C to 85 C Non Isolated Logic and field commons have a direct electrical connection Radiated Field Immunity RFI Complies with EN61000 4 3 3V m 80 to 1000MHz AM amp 900MHz keyed and European Norm EN50082 1 with no register upsets Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions Qacromag com http www acromag com AXM D Series and AXM EDK User s Manual Digital I O Mezzanine Board 2 74 Conducted R F Immunity CRFI Complies with EN61000 4 6 3V rms 150KHz to 80MHz and European Norm EN50082 1 with no register upsets Electromagnetic Interference Immunity EMI No register upsets occur under the influence of EMI from switching solenoids commutator motors and drill motors Surge Immunity Not required for signal I O per European Norm EN50082 1 Electric Fast Transient EFT Immunity Complies with EN61000 4 4 Level 2 0 5KV at field I O terminals and European Norm EN50082 1 Electrostatic Discharge ESD Immunity Complies with EN61000 4 2 Level 3 8KV e
45. utput Signal Transition Time 1 0ns Maximum e Receiver Propagation Delay Time 4 5ns Maximum e Receiver Output Signal Transition Time 1 5ns Maximum Maximum Data Rate 150MHz 4 Meters shielded cable at 25 C Termination Resistors Non removable 1000 termination resistors are in place for each of the differential channels Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com AXM D Series and AXM EDK User s Manual Digital I O Mezzanine Board 2 O Channel Configuration 46 Channels AXM EDK and 64 Channels AXM LVTTL I O D01 Bi directional LVTTL signals are independently direction controlled Reset Power Up Condition All Digital Channels Default to Input LVTTL I O Characteristics Due to the direct connections from the Field I O to the FPGA all I O characteristics for LVTTL are determined by the FPGA Refer to the FPGA documentation for 3 3V signaling for further information Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 3 0 AXM D Series and AXM EDK User s Manual Digital I O Mezzanine Board APPENDIX CABLE MODEL 5028 432 SCSI 3 to Round Shielded TERMINATION PANEL MODEL 5025 288 Type Round shielded cable 34 twisted pairs SCSI 3 male connector at both ends The cable length is 2 meters 6 56 feet This shielded cable is recommended for all I O applications both digital I O and precision analog I O Applicati
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