"TMS320C6000 Expansion Bus to MC68360
Contents
1. The Auto Vector input function is selected in normal operation Bus arbitration signal Note that the internal bus arbiter of the C6000 is disabled please see Figure 1 Bus arbitration signal Note that the internal bus arbiter of the C6000 is disabled please see Figure 1 User can select interrupt level IRQ1 to IRQ7 Priority level 7 interrupt is a special case Level 7 interrupts are non maskable interrupts NMI IRQ7 is a level sensitive input and must remain low until the second instruction processing module CPU32 returns an interrupt acknowledge cycle for interrupt 7 See the MC68360 User s Manual for a detailed description Because the expansion bus does not have a dedicated interrupt output pin a timer pin TOUT is used as a general purpose output to generate interrupt The auto vector AVEC signal is used to terminate interrupt acknowledge cycles indicating that the QUICC should internally generate a vector auto vector number to locate an interrupt handler routine AVEC is ig nored during all other bus cycles The external bus arbiter used in this interface is shown in Figure 2 TMS320C6000 Expansion Bus to MC68360 Microprocessor Interface 3 4 TEXAS SPRA535A INSTRUMENTS MC68360 TMS320C6202 XHOLDA Figure 2 Block Diagram of External Bus Arbiter Used in Interface Between MC68360 Host and C6000 Expansion Bus 2 Configuration The QUICC is comprised of three modules e CPU32 core e Sys2. AM27 AM11 TCYC3 TCYCO Description Dynamic RAM select This bit determines if the bank is SRAM or DRAM SRAM port size Because external DSACKx is used SPS 1 0 11 Address mask Mask any of the corresponding bits in the associated BR By masking the address bits independently external devices of different address range sizes can be used Any set bit causes the corresponding address bit to be used in the comparison with the address pins Cycle length in clocks Value Set bit to 0 SRAM SPSO 1 SPS1 1 All base address and function code bits will be used in the bank hit comparison all bits of the AM bit field are set to one Because external DSACKx is selected with SPS do not set TCYC to zero TCYC 3 0 1111 The module configuration register MCR that controls the SIM60 configuration can be read or written to at any time Set the BSTM bit of the MCR register to zero to enable asynchronous timing on the bus signals Set the ASTM bit of the MCR register to zero to enable asynchronous timing on the arbitration signals The Port E pin assignment register PEPAR controls the I O pins associated with port E Set the CF1MODE bit field of the PEPAR register to CF1MODE 1 0 00 CONFIG1 input pin function is chosen Set bit 7 of the PEPAR to one to select the WE0 WE3 output functions Set bit 0 of the PEPAR register to zero to select the AVEC input function TMS320C6000 Expansion Bus to MC68360 Mic
3. R W asserted to data bus impedance change 55 Symbol tCHAV tCHAZn tCLSA tSTSA tSTCA tAVSA tCLSN tSNAI tSWA tSN tCHSZ tSNRN tCHRH tCHRL tRAAA tRASA tCHDO tSNDOI tDVSA tDICL tSNDN tSNDI tSHDI tDADV tRWA tAIST tAlHT tDOHC tCHDH tRADC TMS320C6000 Expansion Bus to MC68360 Microprocessor Interface Min ns 14 10 10 75 35 10 10 47 10 10 100 10 25 Max ns 15 16 6 26 16 40 20 20 23 50 40 10 20 ws TEXAS INSTRUMENTS The timing requirements in Table A 1 are provided for quick reference only For detailed description notes and restrictions please see the MC68360 User s Manual wy TEXAS INSTRUMENTS SPRA535A Appendix B TMS320C6000 Timing Parameters Table B 1 TMS320C6000 Timing Parameters Asynchronous Host Port Characteristic Pulse duration XCS low Pulse duration XCS high Setup time expansion bus select signals valid before XCS low Hold time expansion bus select signals valid after XCS low Hold time XCS low after XRDY low Setup time XBE 3 0 XA 5 2 valid before XCS high Hold time XBE 3 0 XA 5 2 valid after XCS high Setup time XDx valid before XCS high Hold time XDx valid after XCS high Delay time XCS low to XDx low impedance Delay time XCS high to XDx invalid Delay time XCS high to XDx high impedance Delay time XRDY low to XDx valid Delay time XCS high to XRDY high Symbol Tw XCSL Tw XCSH
4. Tsu XSEL XCSL Th XCSL XSEL Th XRYL XCSL Tsu XBEV XCSH Th XCSH XBEV Tsu XDV XCSH Th XCSH XDV Td XCSL XDLZ Td XCSH XDIV Td XCSH XDHZ Td XRYL XDV Td XCSH XRYH Min Max ns ns 4Pt 4Pt 1 3 15 Pf 1 3 1 3 0 0 12 4Pt 4 1 0 12 T P is a clock period of the TMS320C6000 core Th XRYL XCSL 3 4 ns for the TMS320C6203 processor The timing requirements in Table B 1 are provided for quick reference only For detailed description notes and restrictions please see the corresponding Fixed Point Digital Signal Processor data sheet TMS320C6000 Expansion Bus to MC68360 Microprocessor Interface 11 di TEXAS SPRA535A INSTRUMENTS Appendix C External Bus Arbiter PAL Equations Synario 3 10 Device Utilization Chart Thu Apr 01 14 13 34 1999 bus_arb bls Module bus arb Input files ABEL PLA file bus arb tt3 Device library P22V10C dev Output files Report file bus arb rep Programmer load file bus arb jed 12 TMS320C6000 Expansion Bus to MC68360 Microprocessor Interface Ww TEXAS INSTRUMENTS SPRA535A Page 2 Synario 3 10 Device Utilization Chart Thu Apr 01 14 13 34 1999 bus_arb bls P22V10C Programmed Logic BBn 0 BBn 0E XHOLDA O BRn XHOLDA O XHOLD XHOLDA D N 9 0 amp XCLKIN XHOLDA Q XHOLD ISTYPE BUFFER XHOLDA C XCLKIN N_9 D BGn N 9 0 4 XHOLD ISTYPE
5. is needed if a 5 V host is used A bus switch can be used to convert voltage for example the SN74CBTD16211 The bus switch is not shown in the diagram Table 1 lists the expansion bus connections Pull up down Resistors MC68360 Host TMS320C6000 Figure 1 Block Diagram of Interface Between MC68360 Host and Expansion Bus TMS320C6000 Expansion Bus to MC68360 Microprocessor Interface INSTRUMENTS Ww TEXAS INSTRUMENTS Expansion Bus Signal XCNTL XW R XD 31 0 XCS XBE 3 0 HRD XHOLD XHOLDA TOUT SPRA535A Table 1 MC68360 to TMS320C6000 Expansion Bus Connections MC68360 Pin A 2 R W D 31 0 CSx WE 0 3 DSACK1 DSACK2 CONFIG 2 0 100 AVEC 0 Glue is required to connect to BR BG BGACK Glue is required to connect to BR BG BGAC IRQx Comments Address bit of MC68360 is used as control signal Indicates a read or write access Data lines Any chip select of MC68360 can be connected to HCS as the chip select signal This also serves as the data strobe signal in this case since DS of MC68360 is not used as data strobe Byte enables The SPS bits in the MC68360 option registers must be set to indicate that DSACK is generated externally by the expansion bus Refer to the MC68360 User s Manual for details The configuration pins are set to CONFIG 2 0 100 Therefore the CPU is enabled global chip select port is 32 bit size and the MBAR register is at OxOO3FFO0
6. 6203C Fixed Point Digital Signal Processor SPRSO86 TMS320C6204 Fixed Point Digital Signal Processor SPRS152 MC68360 User s Manual Motorola Inc hee I i TMS320C6000 Expansion Bus to MC68360 Microprocessor Interface 9 SPRA535A 10 Appendix A MC68360 Timing Requirements Table A 1 Motorola MC68360 Timing Parameters Characteristic CLKO1 high to address FC valid 6 CLKO1 high to address FC invalid 8 CLKO1 low to CS asserted 9 AS to DS or CS asserted 9A AS to CS asserted 9C Address valid to AS CS OE asserted 11 CLKO1 low to CS negated 12 AS DS CS OE WE negated to address FC invalid address hold 13 AS CS OE and DS read width asserted 14 AS DS CS OE width negated 15 CLKO1 high to AS DS R W high impedance 16 AS DS CS WE negated to R W high 17 CLKO1 high to R W high 18 CLKO1 high to R W low 20 R W high to AS CS OE asserted 21 R W low to DS asserted Write 22 CLKO1 high to Data Out valid 23 DS CS WE negated to Data Out invalid Data Out hold 25 Data Out valid to DS asserted write 26 Data In to CLKO1 low Data setup 27 AS DS negated to DSACK negated 28 DS CS OE negated to Data In invalid Data In hold 29 DS CS OE negated to Data In high Z 29A DSACK asserted to DSACK valid Skew 31A R W width asserted write or read 46 Async input setup time 47A Async input hold time 47B Data Out from CLKO1 high 53 CLKO1 high to Data Out high Z 54
7. BUFFER N_9 C XCLKIN TMS320C6000 Expansion Bus to MC68360 Microprocessor Interface 13 4y TEXAS SPRA535A INSTRUMENTS Page 3 Synario 3 10 Device Utilization Chart Thu Apr 01 14 13 34 1999 bus_arb bls P22V10C Chip Diagram P22V10C X XxX H L O B K N B L G I E D n N 9 lt ni po A Be 2 Ol 2827 26 5 25 6 24 7 23 8 22 9 21 0 20 1 1 9 1213 14 15 6 17 18 w UBO HE Xx 14 TMS320C6000 Expansion Bus to MC68360 Microprocessor Interface wy TEXAS INSTRUMENTS Synario 3 10 Device Utilization Chart bus_arb bls P22V10C Resource Allocations SPRA535A Page 4 Thu Apr 01 14 13 34 1999 Device Resource Design Resources Availabl Requirement Unused Input Pins Input 12 3 9 75 Output Pins In Out 10 4 6 60 Output Buried Nodes Input Reg a ee Pin Reg 10 2 8 80 Buried Reg TMS320C6000 Expansion Bus to MC68360 Microprocessor Interface 15 SPRA535A 16 Ws TEXAS INSTRUMENTS Page 5 Synario 3 10 Device Utilization Chart Thu Apr 01 14 13 35 1999 bus_arb bls P22V10C Product Terms Distribution Signal Pin Terms Terms Terms Name Assigned Used Max Unused BBn 18 0 10 10 BRn 26 1 10 9 XHOLDA D 17 Z 8 6 N_9 D 27 2 8 6 List of Inputs Feedbacks Signal Name Pin Pin Type XCLKIN 2 CLK IN BGn 3 INPUT XHOLD 4 INPUT TMS320C6000 Expansion Bus to MC68360 Microprocessor Interfa
8. TS SPRA535A Ons 50ns 100ns 150ns le Sie lv Me LI ee ite Ai SJE A Lg se Me Sti O elt ve s5 so s1 s2 s3 s4 _ 5 S5 tDICL CLKO1 tCHAV tCHAV m tsu XSEL XCSL 4 tSNAI XCNTL A 2 An er TT EN gt tCHRL tRWA a iCHRH i XR W R W XCS CS td XRYL XDV XRDY DSACK a gt td XCSL XDLZ gt td XCSH HDIV XD 31 0 D 31 0 Pove a ana word Figure 3 MC68360 Host Performs Read from Expansion Bus Asynchronous Host Port Interface TMS320C6000 Expansion Bus to MC68360 Microprocessor Interface 7 di TEXAS SPRA535A INSTRUMENTS Ons 25ns 50ns 75ns 100ns 125ns 150ns 175ns LILI LILI LILI LILI LILI LILI LILI LILI ss so s1 sa sg S4 s5 s5 CLKO1 o tCHAV tCHAV SNA XCNTL A 2 PM A a h i tRWA i CHR CHRE po i XRWRW V A HCLSAk tAVSA k k th XCSH HDV XCS CS XRDY DTACK OS JIDOHC tCHDO gt ne tRADC gt gt SNDOI XD 31 0 D 31 0 o word Z 4 Figure 4 MC68360 Host Performs Write to Expansion Bus Interface Table 5 Timing Reguirements for TMS320C6000 C6000 Symbol MC68360 Symbol Parameter C6000 Min MC68360 Min ns ns tw XCSL tSWA Pulse width of HCS low 16 75 tsu SEL XCSL tAVSA Setup time select signals valid before 1 10 XCS low th XCSL SEL tSNAI tSWA Hold time select signals valid after 3 85 XCS low t
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10. ce Ww TEXAS INSTRUMENTS SPRA535A Page 6 Synario 3 10 Device Utilization Chart Thu Apr 01 14 13 35 1999 bus_arb bls P22V10C Unused Resources Pin Pin Product Flip flop Number Type Terms Type 5 INPUT 6 INPUT 7 INPUT 9 INPUT s 10 INPUT 11 INPUT 12 INPUT z 13 INPUT 16 INPUT 19 BIDIR NORMAL 12 D 20 BIDIR NORMAL 14 D 21 BIDIR NORMAL 16 D 23 BIDIR NORMAL 16 D 24 BIDIR NORMAL 14 D 25 BIDIR NORMAL 12 D TMS320C6000 Expansion Bus to MC68360 Microprocessor Interface 17 Ws TEXAS SPRA535A INSTRUMENTS Page 7 Synario 3 10 Device Utilization Chart Thu Apr 01 14 13 35 1999 bus_arb bls P22V10C Fuse Map 44 88 X 132 X X 440 484 X X 4884 X 5368 5412 X X 5456 X X 0 10 5808 XX XXXXXX XXXXXX X 18 TMS320C6000 Expansion Bus to MC68360 Microprocessor Interface IMPORTANT NOTICE Texas Instruments and its subsidiaries Tl reserve the right to make changes to their products or to discontinue any product or service without notice and advise customers to obtain the latest version of relevant information to verify before placing orders that information being relied on is current and complete All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment including those pertaining to warranty patent infringement and limitation of liability TI warrants perfo
11. gure 3 MC68360 Host Performs Read from Expansion Bus Asynchronous Host Port Interface 7 Figure 4 MC68360 Host Performs Write to Expansion Bus Interface 8 Trademarks are the property of their respective owners TMS320C6000 and C6000 are trademarks of Texas Instruments SPRA535A Ws TEXAS List of Tables Table 1 MC68360 to TMS320C6000 Expansion Bus Connections Table 2 Base Register 0 BRO Relevant Bits MC68360 Table 3 Option Register OR Relevant Bits MC68360 Table 4 TMS320C6000 Boot Configuration via Pull Up Pull Down Resistors on XD 31 0 Table 5 Timing Requirements for TMS320C6000 Table 6 Timing Requirements for MC68360 LLL Le Table A 1 Motorola MC68360 Timing Parameters 10 Table B 1 TMS320C6000 Timing Parameters Asynchronous Host Port 11 MC68360 Interface The expansion bus is configured to operate in the asynchronous host port mode Note that the internal expansion bus arbiter is disabled The C6000 requests the expansion bus only if it needs to access a FIFO or asynchronous l O port not shown in the block diagram Figure 1 shows the interface diagram The TMS320C6000 DSP is not 5 V tolerant therefore voltage translation
12. k TEXAS Application Report INSTRUMENTS SPRA535A August 2001 TMS320C6000 Expansion Bus to MC68360 Microprocessor Interface Zoran Nikolic DSP Applications ABSTRACT This application report describes how to interface the Motorola MC68360 quad integrated communications controller QUICC to the Expansion Bus of the Texas Instruments TMS320C6000 C6000 digital signal processor DSP The document contains the following elements e A block diagram of the interface and PAL equations e Information required to configure the MC68360 e Timing diagrams illustrating the interface functionality Note The information presented in this application report has been verified using VHDL simulation Contents di MO6 360 lnterfac n 2205422 E o AA ee eee eet eee 2 2 GORTMGUMATION a aa ea daha aha se Dales og ee See ti 4 3 Timing Verini aNOn a A ae ee eee ea Ma eae ee 6 Ax SRGICIENCES iris Mana see lit ARO AA 9 Appendix A MC68360 Timing Requirements 10 Appendix B TMS320C6000 Timing Parameters 11 Appendix C External Bus Arbiter PAL Equations 12 List of Figures Figure 1 Block Diagram of Interface Between MC68360 Host and Expansion Bus 2 Figure 2 Block Diagram of External Bus Arbiter Used in Interface Between MC68360 Host and C6000 Expansion BUS stas reas Pada Crete des li 4 Fi
13. r should be set to zero to disable parity bus error detection Each SRAM bank has a base register BR and an option register OR The MC68360 has eight identical sets of two registers the BR and OR 4 TMS320C6000 Expansion Bus to MC68360 Microprocessor Interface wy TEXAS INSTRUMENTS SPRA535A The configuration of the BRO and ORO registers is shown in Table 2 and Table 3 Table 2 Base Register 0 BRO Relevant Bits MC68360 Bit Field CSNTQ TRLXQ PAREN V BA31 BA11 Description CS negate timing This bit is used to determine when CS is negated during an internal QUICC or external QUICC MC68030 type bus master write cycle Timing relax This bit delays the beginning of the internal QUICC or external QUICC MC68030 type bus master cycle to relax the timing constraints on the user Parity checking enable Valid Bit Base address Value Set bit to 0 CS negated normally Set bit to 0 do not relax timing 0 Parity checking disabled 1 Content of BRO and ORO pair is valid Base address of SRAM bank 0 was The base address field the upper 21 bits of each set to 0x09000000 BR and the function field are compared to the address on the address bus to determine if a DRAM SRAM region is being accessed by an internal QUICC master The option register is a 32 bit read write register that can be accessed at any time Table 3 Option Register OR Relevant Bits MC68360 Bit Field DSSEL SPS1 SPSO
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15. roprocessor Interface 5 SPRA535A 6 di TEXAS INSTRUMENTS The TMS320C6000 boot configuration is presented in Table 4 Table 4 TMS320C6000 Boot Configuration via Pull Up Pull Down Resistors on XD 31 0 Field Description RWPOL Determines polarity of expansion bus read write signal RWPOL 1 XR W_ HMOD Host mode status in XB HPIC HMOD 0 external host interface is in asynchronous slave mode XARB Expansion bus arbiter status in XBGC XARB 1 internal expansion bus arbiter is disabled FMOD FIFO mode status in XBGC LEND Little endian mode BootMode 4 0 LEND 1 system operates in little endian mode Dictates the boot mode of the device including host port boot ROM boot memory map selection For a complete list of boot modes see the TMS320C6000 Peripherals Reference Guide SPRU190 Timing Verification To verify proper operation two functions have been examined e An MC68360 write to the expansion bus e An MC68360 read from the expansion bus In each instance timing requirements were compared for each of the devices The results are shown in Figure 3 Figure 4 Table 5 and Table 6 The interface was functionally verified using VHDL simulation Synopsys SmartModel of the MC68360 was used in the test bench The timing diagrams shown in Figure 3 and Figure 4 illustrate a read and a write initiated by the MC68360 TMS320C6000 Expansion Bus to MC68360 Microprocessor Interface wy TEXAS INSTRUMEN
16. su XDV XCSH 1 5 tcyc Setup time host data valid before HCS 1 41 tCHDO tCLSN high WRITE SETUP TIME th XCSH XDV tSNDOI Hold time host data valid after HCS 3 10 high tcyc denotes one clock cycle time of the MC68360 At 25 MHz operating frequency tcyc 40 ns th XCSL SEL 3 4 ns for C6203 processor In this case C6000 refers to the C6202 B C6203 and C6204 devices 8 TMS320C6000 Expansion Bus to MC68360 Microprocessor Interface wy TEXAS INSTRUMENTS SPRA535A Table 6 Timing Requirements for MC68360 C6000 Symbol MC68360 Parameter C6000 Min MC68360 Min Symbol ns ns td XCSH HDIV tSNDI Input data hold time from CS negated 0 0 2tcycO tCLSA td XC tDICL Data in valid to clock low 60 1 SL HDV READ SETUP TIME tcyc denotes one clock cycle time of the MC68360 At 25 MHz operating frequency tcyc 40 ns In Figure 3 and Figure 4 timing parameters are named in the same way as those in the data sheets for the TMS320C6000 and MC68360 Actual timing parameter values are listed in Appendix A and Appendix B The tables and timing diagrams above show that the timing parameters for both devices are met in the interface of the MC68360 and TMS320C6000 This interface is based on an MC68360 25 MHz device operating at 3 3 V and a TMS320C6000 device at any frequency 4 References TMS320C6000 Peripherals Reference Guide SPRU190 TMS320C6202 TMS320C6202B Fixed Point Digital Signal Processor SPRS104 TMS320C6203 TMS320C
17. tem integration module SIM60 e Communication processor module CPM The memory controller is a sub block of the SIM60 that is responsible for up to eight general purpose chip select lines The general purpose chip selects are available on lines CS0 CS7 CS0 also functions as the global boot chip select for accessing the boot EPROM The SIM60 supports a glue less interface to expansion bus All internal memory and registers of the MC68360 occupy a single 8 KB memory block that is relocatable along 8 KB boundaries The location is fixed by writing the desired base address of the 8 KB memory block to the MBAR The 8 KB block is divided into two 4 KB sections The RAM occupies the first section the internal registers occupy the second section The LSB least significant bit of the MBAR register indicates when the contents of the MBAR are valid if the bit is equal to one the content is valid The MC68360 general purpose chip selects are controlled by the global memory register GMR and the memory controller status register MSTAT There is one GMR and MSTAT in the memory controller The MSTAT reports write protect violations and parity errors for all banks The 32 bit read write GMR contains selections that are common to the entire memory controller The GMR is used to control global parameters for memory banks The DPS bit field of the GMR register must be set to DPS 1 0 11 to enable external DSACKx response The PBEE bit of the GMR registe
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