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MPC8266ADSPCIUM: MPC8266 ADS PCI User`s Manual

Contents

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10. LON Pe 30 eN 39 Pez SOWOHdSSU zv ev ev 299 71 LS Seaava Sivag fa Lee ezadya oiv 82 zzady elvag 67 72 1200 02150 11 08 d olvada LUE 2 quo 3900 220 g 8 158041 2222 521 01 jon gt qd d LUE 7043 saa 90d 3 721709 edd OZ 709 3 lt 21 08 8200 32 599 d 921 08 97 8200 lag 2043 161408 200 3 821709 6 200 36 621709 SH 9200 0 161908 ZIM ezoa 2 2200 03M 1200 SHOE 0200 39 eds 6 00 230 121 8 0 139 gerd xd 169 40 521908 gy 2009 one 61709 98 ziDd any BS ziv 21 08 88 0100 iM ziaava 9 ay 9 9 800 pid i ggvg 1709 9 Le 5 0 9822 1008 79 Soa oiv 81009 21709 9 vod ey Le
11. JTAG LOGIC definitions signals groups JtagShiftDR JtagShiftDRO JtagShiftDR7 S Reg JtagEn fb 0 0 0 0 0 0 JtagReceiveFull fb 136 MPC8266ADS PCI User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information JtagState JtagStateO JtagState3 JtagShiftIR JtagShiftIRO JtagShiftIR2 JtagIR JtagIRO JtagIR2 FallingTckSignals JtagResetState JtagShiftlrState JtagShiftDrState JtagTdoEnable Read BrdContRegCs B DVal W A27 A28 A29 for simulation only Constant definition JTAG RESET 0 JTAG IDLE 1 JTAG SELECT DR 2 CAPTURE DR 3 JTAG SHIFT DR 4 JTAG DR 5 JTAG PAUSE DR 6 JTAG EXIT2 DR 7 UPDATE DR 8 SELECT IR 9 CAPTURE IR 10 JTAG SHIFT IR 11 JTAG IR 12 PAUSE IR 13 JTAG EXIT2 IR 14 JTAG UPDATE IR 15 STATE JTAG RESET JtagState fb RESET STATE JTAG IDLE JtagState fb JTAG IDLE STATE SELECT DR JtagState fb SELECT DR STATE JTAG CAPTURE JtagState fb CAPTURE DR STATE JTAG SHIFT DR JtagState fb SHIFT S
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13. kK kK K KK BCSR 0 definitions k k PBI 0 DIMM_SIZE_16M 0 L2CACHE INHIBITED 0 L2CACHE FLUSHED 0 L2CACHE LOCKED 0 L2CACHE CLEARED 0 SIGNAL LAMP ON 0 Power Defaults Assignments Gs okk sk sk PBI PON DEFAULT PBI IN ACTIVE DIMM SIZE DEFAULT DIMM SIZE 16M L2CACHE INH PON DEFAULT L2CACHE INHIBITED L2CACHE FLUSH PON DEFAULT L2CACHE_FLUSHED L2CACHE LOCK PON DEFAULT LOCKED L2CACHE CLEAR PON DEFAULT 2 CLEARED SIGNAL LAMPO PON DEFAULT SIGNAL LAMP SIGNAL PON DEFAULT SIGNAL LAMP Data Bits Assignments eee PBI DATA D0 SIZE DATA D1 L2CACHE INH DATA BIT D2 L2CACHE FLUSH DATA BIT D3 L2CACHE LOCK DATA BIT D4 L2CACHE CLEAR DATA 05 132 MPC8266ADS PCI User s Manual For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Support Information SIGNAL LAMPO DATA BIT D6 SIGNAL DATA 07
14. 8201 101 eua pue ZEZA jou JT EZN ZZN 2420 5920 1820 pesn sr TEZA 9 6ENH 195 MPC8266ADS PCI User s Manual For More Information On This Product MOTOROLA Go to www freescale com Freescale Semiconductor Inc Support Information 22 02 Jo 4 1994 1002 22 1 Aepsen lona ev ay Jqunwweumw 926 Axessooeu
15. equations LAdd le LAdd d Add latching the address Output equations SdramAdd oe h7 always enabled when ROW amp NORMAL then SdramAdd RowAddNormal q else when ROW amp SDRAM PBI MODE amp SDRAM 16M then SdramAdd RowAddPBI_16M q else when ROW amp SDRAM PBI MODE amp SDRAM 64M then SdramAdd RowAddPBI_64M q else when COL amp SDRAM NORMAL then SdramAdd ColAddNormal q else when COL amp SDRAM MODE amp SDRAM 16M then SdramAdd ColAddPBI 16M q else when COL amp SDRAM PBI MODE amp SDRAM 64M then SdramAdd ColAddPBI_64M q ifdef SIMULATION END 7 2 4 U22 SDRAM MUX LATCH Low MODULE vmuxlow6 MOTOROLA MPC8266ADS PCI User s Manual For More Information On This Product Go to www freescale com 183 Freescale Semiconductor Inc Support Information TITLE Voyager Sdram 1st Latch Mux This contains the 151 part of Address latch amp mux for Voyager ads sdram The mux is required only with L2 Cache installed on board Otherwise it is not assembled and A 21 28 are shortened to SdramA 7 0 Tn this 2 pinout is changed for 2115 7 Tn this 3 07
16. 8743 ur sau uoduoo TV avys 9 02199 b 15 ISH 4ojonpuoonueg v 1881 188117 5 581217 ul 103NNOO ON SW Ec paca SWL 9 1 193NNO9 ON Xa ear rmx 901 Tn 58 Fer 2930 1939 H19 SV1Z1 153981 N ETERON N uns 0930 SSIWZT SSINZT 094077 Hsmuzi cab STI 0 no EW nyoa 510 10211 Iz 511 N3dV L5 Keale 580217 Le 99210 lt 98211 99215 TO 189 per Bou 7851 sr 89 LIS Nat 104 a 880211 880211 a i IN IM B 25 109 100 9 13 1581 16814 18814 sy 1982 at valu 51 Vie Vie EN 51 04021 SL 510 zu SL LIS AIguyu TENT To 20 2 2 SAVY 2385 ar uu gave aavu aay 191 0 V 091v 9897049 9807149 651vd 9802185 580249 Dadendd 18140 980049 801499 289049 rr 9
17. equations JtagStateReset Trst B only for jtag state machine JtagReset Trst B 4 PORIn_B JtagResetState fb global reset JtagState clk Tck JtagState ar JtagStateReset JtagState ap 0 Standard JTAG state machine state diagram JtagState state JTAG RESET MOTOROLA MPC8266ADS PCI User s Manual 151 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information if Tms then JTAG IDLE else JTAG RESET state IDLE if Tms then JTAG SELECT DR else JTAG IDLE state SELECT DR DR if Tms then JTAG CAPTURE DR else JTAG SELECT IR state JTAG CAPTURE DR if Tms then JTAG SHIFT DR else JTAG EXITI DR state DR if Tms then JTAG EXITI DR else JTAG SHIFT DR state JTAG EXIT1 DR if Tms then JTAG PAUSE DR else JTAG UPDATE DR state JTAG PAUSE DR if Tms then JTAG EXIT2 DR else JTAG PAUSE DR state JTAG EXIT2 DR if Tms then JTAG UPDATE DR else JTAG SHIFT DR state JTAG UPDATE DR 152 MPC8266ADS PCI User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information if Tms then JTAG IDLE else JTAG SELECT DR state SELECT IR if Tms then JTAG CAPTURE IR else JTAG RESET state CAP
18. equations AleOut_B AleIn inverted Ale MOTOROLA MPC8266ADS PCI User s Manual 187 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information AleOut B oe H LAdd le Ale LAdd d Add latching the address Output equations SdramAdd oe hff always enabled when ROW amp SDRAM_NORMAL_MODE then SdramAdd RowAddNormal q else when ROW amp SDRAM_PBI_MODE amp SDRAM_16M then SdramAdd RowAddPBI_16M q else when ROW amp SDRAM_PBI_MODE amp SDRAM_64M then SdramAdd RowAddPBI_64M q else when COL then SdramAdd ColAdd q input open running 0 msb to Isb ifdef SIMULATION END 7 3 Schematics and Bill Of Materials This sectoin shows the schematicds of the MPC8266ADS PCI aith the Bill Of Materials 7 3 1 Schematics Following are the schematics of the board 188 MPC8266ADS PCI User s Manual For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Support Information 80 L 9 19 Sav 99c82dll sped 619099 5 1ez A euy 21601
19. M 451 he 193 MPC8266ADS PCI User s Manual For More Information On This Product MOTOROLA Go to www freescale com Freescale Semiconductor Inc T z 7 19905 1002772 epson oed 4 0 zs mE mew 02199 DELI 15 160946 15 L eoon FON an E SON 30 pal YON T SOWOBd33u VD 5 zv D 9 1 5200 8 8v T voQava 52 200 8 oiv zzadva 120498 ny 020048 id iv LE 8 0048 810048 11008 6801 0000 6 188044 2222 seixo 958 jon osen lad 904 504 120 oeoa edd Ziva soa 004 121 08 E SZ1VO8 szoa 5200 1198 ezoa 2200 1200 0200 39 6 00 230 8100 130 121708 039 peg zzv 12 20078 avaa cV sav
20. 1 3101 v1 4001 5 09 13538 99 avag Svigu 393 1930 EE 0549 1 4 ido 100A B SON 066 066 066 066 4011 1 GANS 819 6 M 0 9 ua oa 5 saj m 1x Ei o 5 Ww 99 1531 Vac M aE am E xm ES SS Bay 10031 tab Y Siaaw Ig v E 45031 31591 NSIHIS3U gt Soo 5 1 4 Er 77 8 t l09H134 390 390 c 6921 2110 YRS Drs XVI XOXUHIS QNnOND SISVHO T Ad xu 55 OSNH 9 E H3XHH134 aul 19 Ye 1 og t m 8 1 OGXHHI33 q9NH 9 809 70 uis 4041 ey ONY 9 E ZQXHH133 298 24 h FR ud xL T Lt USXIHISd uis NXE VENH JUHI ATL vou N3XIHI34 tales ot 5 1 bg bg iau igi Ee z i T ziu viai ogg IE UTOXTHTS 9056 2291 zn UE um TOXlH134 V 6
21. 15 1 vH 1581210 881817 zg 1391 Led 2 103NNO2 ON SL gt SL 103 ON xg 193NNO2 ON 79 a lt L 103 ON zj 25 001 Thea pg ES 793521 a Per V Y er m 20302 93001 1 2529 LE HNIZTu HNIZ TU EN ene 2959 IX ZA 09 9 SSINz1 Huge MEME 551 1 0939 094921 2 094021 HSA HZU 13210 12214 sr 54 TAAT lt 1021 9801 080210 980214 E Nad 9821 9821 3dvziu gt use ERAT lt rq Bel 1 18585217 189 189 1 saa 880210 880610 aaa 1M 1M 19 6 1581 1581 vl 04421 Em ETE 1 58 tela AVY ABTA OV 210 a 88v aay F H 6210 c 13170 zr4 980rnao 22 ary 1210 S8gqendo Saaendd ea g 910 58020149 9210 vd 980789 58andou 999049 d 9 Hr 8 zza 58642 1 1 Oaendd ENS E 1210 VG 251 0 58049 ZW
22. Power Reset S PORIn NODE istype reg buffer synced pon reset k k Logic Rokok kok Rok JtagShiftDRO istype reg buffer shift data register JtagShiftDR1 NODE istype reg buffer JtagShiftDR2 istype reg buffer JtagShiftDR3 NODE istype reg buffer JtagShiftDR4 istype reg buffer JtagShiftDR5 NODE istype reg buffer JtagShiftDR6 istype reg buffer JtagShiftDR7 istype reg buffer 126 MPC8266ADS PCI User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information JtagStateO NODE istype reg buffer state machine JtagStatel NODE istype reg buffer JtagState2 istype reg buffer JtagState3 istype reg buffer JtagResetState NODE istype reg buffer sampling state on falling JtagShiftIrState NODE istype reg buffer sampling state on falling JtagShiftDrState NODE istype reg buffer sampling state on falling JtagTdoEnable istype reg buffer sampling state on falling JtagShiftIRO NODE istype reg buffer Inst Shift register JtagShiftI
23. L damas 5 994905 1994905 a gt 5 ui he ZQXHW1V u 159 198 90 gt x Fr r vas 5 90 10934 8EYOLOIN OOXYWLY LOXYNLY SOXYWLY 22 394 5 Svoasu lt 15910014 2521000 0509 DAD 9 lt gt More Information This Product s Go to www freescale com Freescale Semiconductor Inc 02 10 6 19945 1002 Ze J9quie oN L H3MOd v 925 5 jenen 15 jexueug ISH v 031 6124 9 LOZA 1 24 6201 ST
24. 9219 enu 737991 0219 elzieH 15 ISH Jojonpuoarues Freescale Semiconductor Inc 2N s anor 9900 1001 4000 4900 4900 44001 4900 39001 4400 4900 34001 080209 0 GIAO 8125 Seid 125 111 t 1 1 1 N anor 7 39001 340017 44008 34008 34008 4400 34008 4000 8900 3900 44001 18001 30001 east ixi wo 2615 eal 2 2615 so 5615 25 8815 dil 2515 ozin 57 0 OIQGA olaan olaan 9978DdN olaan OIQGA olaan olaan V For More Information This Product s Go to www freescale com 02 10 v 19945 1002 Ze J9quie oN SHOLO3NNOO 104 v Jequinw juewnoog 925 5
25. 103 7 2 P2 100 10 Base T Ethernet Connector 104 7 3 Connector aee ee ose bt arat M 104 7 4 P4 CPM Expansion Connector 105 7 5 7 9 Connectors 113 7 6 P12 ATX Power Supply Connector 115 7 7 Lattice ISP x tees e eR UN 116 7 8 P17 System Expansion 117 7 9 MPC8266ADS PCI Bill Of Materials 210 VIII PQ2PCIMB Specifications MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc List of Figures 1 1 2 1 2 2 2 3 2 4 2 6 2 7 2 9 2 10 2 11 2 12 2 13 2 14 2 15 3 1 3 2 3 3 3 4 4 1 4 2 4 4 4 5 4 6 4 7 4 8 4 9 4 10 4 11 4 12 4 13 4 14 6 1 List of Figures MPC8266 MB Block Diagram 6 MPC8266ADS PCI Top Side Part Location Diagram 8 VDDL Range Selection JP5 9 VDDL Trimmer R26 0044 00 Acad ERA dS e RIA QC 10 SWA oues bp Ve Sic qas IR M u S qe 11 Hard Reset Configuration Source Selection 3 12 9S WS IDE
26. 3 8 2618 uev T 3400 gt 9 NIVW S9Z8O24W a 20 Ante 1 3uoor 5 6119 0028 A y 2 199 1449 lt __96 A SHE PS 1 L kma S 9 lt 7 w SSIHV 5619 20 aan sun S c lt 6896 0618 Wy 42 0 oup 1 ira 6 usoa muas 910 0 5 d 821 0191 lt 1 lt lt vun o Ln TCOTVOS gt A HSH P yor 154 AAA 230 fog 230 ogg 2 1 82190 28 1 t 5 11709 oly 9 28 9 SIYA P 051709 Eid et O 1Vd viva eu KA 021244 ziv 5 62180 ELIVOH Sia ev LS 8 211 08 iv 2 89190 221709 olg oly 114 08 ola oly 921709 pe 921 0 011908 OLIVG 921708 FL gg Selva 61709 m eu 6lva Telva8 9 81 08 9 9 2911 1 130 5909 130 sisu P 20 ANIC a Selva E oy ISIN 221 08
27. BCSR 1 definitions BCSR_BOOT 0 bcsrConfEn 0 Hard Reset Conf Word from BCSR MEMORY 1 besrConfEn 1 Hard Reset Conf from EEPROM FLASH FLASH_BOOT 0 boot_device_B 0 EEPROM_BOOT 1 boot_device_B 1 ENABLED 0 ATM_RESET_ACTIVE 0 FETH ENABLED 0 FETH_RESET ACTIVE 0 RS232 1 ENABLE 0 RS232 2 ENABLE 0 66 he 28 Power On Defaults Assignments fff fff ENABLE PON DEFAULT ATM ENABLED RESET PON DEFAULT ATM RESET ACTIVE FETH ENABLE PON DEFAULT ENABLED FETH RESET PON DEFAULT FETH RESET ACTIVE RS232 ENABLE PON DEFAULT RS232 1 ENABLE RS232 2 ENABLE PON DEFAULT RS232 2 ENABLE Data Bits Assignments eat CONF WORD DATA 001 BOOT DEVICE DATA BIT D1 ENABLE DATA BIT D2 RESET DATA BIT D3 FETH ENABLE DATA BIT 04 FETH RESET DATA BIT 5 RS232 1 ENABLE DATA BIT D6 RS232 2 ENABLE DATA 07 MOTOROLA MPC8266ADS PCI User s Manual For More Information On This Product Go to www freescale com 133 Freescale Semiconductor Inc Support Information Jtag Command Status reg
28. OOXHHL3J YOXLALV 2204 0gX1H133 olg SOXLALV 2204 20d 59 88 ZOXLNLY oly 7204 95 zaxiHl3J 98 IQX1W1V 9204 02 29 SOXxIHLad ole OOXINLV Sead gia 920d 9155 SHOHL34 9197 2510 560 7204 2OSHILV 20 1 SH 8224 ola N3XHW1Vu ol Su 6204 2 N3XLH134 59 SOSLW1V oL 1510 Suu 054 01 22 ol ol LAXI SH To U3XLH134 Tg N3XLIA1VU Su ox 2 a V For More Information On This Product s Go to www freescale com 02 10 8 19945 1002 Ze J9quie oN 5 2 91901 v Jequinw jueunooq 9215 5 0219 elzieH 15 ISH Freescale Semiconductor Inc 2 lt 1 OIQWH1S4 910 5 10 20 5 ua 013 g 20 a 90 93 so 53 tO 73 50 53 20 10 13 00 03 1590
29. lt gt 1601 ZN P yoy P yo 5 SNN 6 BP TUN CN 230 pg gt 230 ogg 3 5 68141 5 erva sig s LE sig E relva 1709 vig viv LS y 09 y QEIVOH 06190 YLIVG 601 08 021248 ziv L amp 6c1Vd 071213 ziv LS ELVA 291 0 Sg1Vq 801 08 tiv 2 2109 tiv 2 211 0 121 08 ola ow 111709 018 qe ano 921 08 01709 91 OLIVG A ZN 521708 log 82140 61709 8v 9 81V08 9 L jO qO sist P yoy yoy 18 E ig A o 21 08 98 9v 521 0 98 9v S 221 08 221 0 S1VO8 g S1Vd 8 8 vay 181408 6 or 18140 81408 6 oF em 021 08 021 0 ey 5 8194 9 Zelva 9128 6LIVO 1VO8 5128 zy 5 5 SLIVOH 1a ET Shiva 21408 id tv ET 2190 y svT y ov qe 08 ov selva Svag 7 Shiva 21 08 LEIVO 251 0 00 door Hoor 3400 n u en orn Deco eco pezo 190 904 mL 191 MPC8266ADS PCI User s Manual For More Informat
30. 3sea 9 4 ILH xx ur uorado ue ST vZN xx 0930H133 g 303H133 5 T530H134 Ur 2 L 919151 919151 e Nee 9 EIVISI 21151 g 149151 5 OLVISL 0 99 2 1 Aa ZA3H1001 1A3H1001 Y OA3H1001 Ej TOL I Z10DG 1101X3 0101 3 SON 2 wre 214075 TERE TIdOMS Y 0140745 9 1H3A8 0H3A8 258 OF 8258 SON 8541 1104 AS 658 B OLL ell 121 gt esu N3dvziu 10410 MOL 70 ISOH 1089 INI Todt MOK AL ow 5 0 8128 g aaae 22 56 SSH 9S4 0155 854 1558 OSONLVU TSHH134u 2 104 lt Z 1 108 104 Y 108 b N39303u 1991 1089 949 104 Ur 5 N3IH133u N34nad1u HSMAI XOL
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34. 59 2 5 22 840084 2 6 044054 139984 9259 5 cs S 144084 55 0 240059 940084 154 SNMOG TTNd eua y uo spuedep PITY ou ou ou sok sok ou sok sok UOISIAeH cea tIcH 5 ZEA 9 x PIZA vVOCH VISN 5054 6024 x uo uoeozT Jo JEA PEN x jou JO 9 4 jou ue xx 555 1259 254 458 8258 8 8 0949H133 1930H134 XOL 417151 719151 619151 21 151 8 9151 6 017151 XOL A381OO1 eN3W 1001 LA3H T1001 1 C6 OMOLXS 2140 5 0140 5 5 Ng IH3Ad ENEI 8 TASH AS eisy 201 93uv
35. 0900 PLON 98 6500 Fez E J8FOA ZEIV9 VIN SAO ZION 98 89 ezn 42 sar soq 55 d 55 OLON m 9 Lva 5 E 3 feed 5 Twa 8800 89N Fag 5 UST 200 SIg 35 SOA Seva 8500 rr 2500 SON gr 1900 YON vi 0500 10031914 1 6704 Ewa 8704 LON m 90 lt 12 STV 8100 9 550055 ES Eroa P 540059 E YVNEOSH 02 7 i 2001991 2800 2 54 901991 20 2 2 511451 REH oa FPFF a WAIVE 800 vas 52 6 105 E 1094006 72 921 0 6 Seva 3093008 4200 5 12190 LIST 2 2 5 oraav Yt 97 9200 821901 ovs 997 i IYS SE 7 1240 62140 eeoa 095 6raav 8 8200 2600 1330 SZISWWIG 9 Mad 1 12049 8 2100 ieoa 5 551 0 0 5 100 9L 0500 gt 0 siggy 25191 gt 8208 110 5 LON 2200 ary 29 9 zwoa ME
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41. 230 115 115VAC Setting 230VAC Setting Factory set Figure 2 9 Chassis AC Voltage Settings MOTOROLA MPC8266ADS PCI User s Manual 15 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Hardware Preparation and Installation 2 4 Installation Instructions When the MPC8266ADS PCI has been configured as desired by the user it can be installed according to the required working environment as follows Host Controlled Operation Stand Alone 2 4 1 Host Controlled Operation In this configuration the MPC8266ADS PCI is controlled by a host computer via the COP port which is a subset of the JTAG port This configuration allows for extensive debugging using on host debugger The host is connected to the ADS by a COP controller provided by a third party Host Computer Media2COP 16 Wire Flat Cable S ATX Power Supply S L P2 Figure 2 10 Host Controlled Operation Scheme 2 4 2 Stand Alone Operation In this mode the ADS 15 not controlled by the host via the port It may connect to host via one of its other ports e g RS232 port Fast Ethernet port 155 port etc Operating in this mode requires an application program to be programmed into the board s Flash memory 16 MPC8266ADS PCI User s Manual MOTOROLA For More Information On This Product Go to www fr
42. 8266 CLOCK GEN SDRAM 66MHZ Buffers 12 EXPANSION Figure 4 3 Main Clock Generator Scheme MOTOROLA MPC8266ADS PCI User s Manual 51 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Functional Description 4 3 2 PCI Clock The PCI bus clock is derived internally from the main clock input CLKINI The generated PCI clock is output from a PCI dedicated PLL named DLL That clock output is feeding an on board low skew and fast low propagation delay PLL clock distributor which distributes the PCI clock to all on board PCI devices One of the outputs is fed back to the PCI clock to the MPC8266 through CLKIN2 input This clock input is driven to the DLL which synchronizes the DLL output clock to the CLKIN2 input clock and thus maintains low skew between the DLL output and CLKIN2 input All PCI bus timings are referenced to the CLKIN2 input clock Special care was taken when the board layout was done to keep all copper traces away from the Clock Distributor outputs at the same lengths including the output that is fed back to CLKIN2 This is in compliance with the PCI standard to achieve bus synchronization and low skew The PCI clock scheme is shown in Figure 4 4 Low Skew PLL MPC8266 OUTI PCI D
43. Hard Reset Configuration Logic 5 BCSR bcsrConfEn 1 HRESET Conf Word BCSR HRESET BOOT IN FLASH bcsrConfEn 0 amp device B 0 HRESET Conf Word and Boot Code in FLASH BOOT FLASH besrConfEn 1 amp device 0 HRESET Conf Word in BCSR and Boot Code in FLASH HRESET BOOT EEPROM besrConfEn 0 amp boot device 1 HRESET Conf Word and Boot Code in EEPROM BOOT IN bcsrConfEn 1 amp boot device B 1 HRESET Conf Word in BCSR and Boot Code in EEPROM HARD RESET ASSERTION HardReset_B 0 amp SyncHardReset_B fb 0 amp DSyncHardReset_B fb 1 50 ASSERTED 50 B 0 54 ASSERTED Cs4 B 0 FIRST BYTE READ 50 ASSERTED amp DSyncHardReset B fb amp ConfAdd 0 HRESET IN BCSR amp IR SCND BYTE READ CS0 ASSERTED amp DSyncHardReset_B fb amp ConfAdd 1 amp BCSR amp IR THIRD BYTE READ CS0_ASSERTED amp DSyncHardReset_B fb 4 ConfAdd 2 amp HRESET IN 5 amp IR BYTE READ CS0_ASSERTED amp DSyncHardReset_B fb amp ConfAdd 3 amp HRESET BCSR
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45. 8 16 data bus width memory devices This to provide eased access to various communication transceivers EXPWEO controls EXPD 0 7 while EXPWE1 controls EXPD 8 15 These lines may also function as UPM controlled Byte Select Lines which allow control over almost any type of memory device 120 MPC8266ADS PCI User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information Table 7 8 P17 System Expansion Connector Pin No D6 Signal Name Attribute Description GND O Digital Ground Connected to main GND plane of the ADS D7 EXPGL0 O Expansion General Purpose Lines 0 5 L These are buffered 08 GPL 0 5 lines which assist UPM control over memory device if EXPGLI necessary These are output only signals and therefore do not support H D9 EXPGL2 W controlled UPM waits D10 EXPGL3 EXPGL4 D12 EXPGLS D13 GND O Digital Ground Connected to main GND plane of the ADS D14 EXPALE O Expansion Address Latch Enable H This is the buffered MPC8266 s ALE provided for expansion board s use 015 EXPCTL0 O Expansion Control Line 0 This line is a buffered version of MPC8266 s BCTL0 Bus Control Line 0 which serves as W R provided for expansion board s use D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26
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47. ENABLE DATA BIT pin ENABLED amp IPON RESET ENABLE PON DEFAULT ENABLED PON RESET amp ENABLE PON DEFAULT ENABLED then ENABLED else ATM ENABLED state ENABLED if WRITE BCSR 1 amp ENABLE DATA ENABLED RESET ENABLE PON DEFAULT ATM ENABLED PON RESET ENABLE PON DEFAULT ENABLED then ATM ENABLED else IATM ENABLED state diagram AtmRst_B state ATM RESET ACTIVE if WRITE BCSR 1 amp RESET DATA BIT pin RESET ACTIVE amp IPON RESET RESET PON DEFAULT RESET PON RESET RESET PON DEFAULT ATM RESET then IATM RESET ACTIVE else ATM RESET ACTIVE state RESET ACTIVE if WRITE BCSR 1 amp RESET DATA BIT pin RESET ACTIVE amp MOTOROLA MPC8266ADS PCI User s Manual 143 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information IPON RESET RESET PON DEFAULT RESET PON RESET amp RESET PON DEFAULT RESET ACTIVE then ATM RESET ACTIVE else RESET ACTIVE IC I state diagram FEthEn B state
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50. 201 XZON lt 8201 g 139008 Nid 02007 IE 120 O H amp 9975 020 019 01 yz 01 2 BION 19 pes SAL Lion gr 900 LLON Eyd 2909 SION 74 9101 oar 1900 SION E ia EE 0900 TEL SET 5500 Zt TIVON ZENIT 8600 ZION sor 88 88 88190 997 00 LLON gor 5 6 2130 9800 OLON m A 961 0 PE a 5 5 LON SA D SON SplvQ 11872 EI 8800 SON m n ENS 0901 110319 1 8704 von 5 yoq B d SHY Sroa o ls Suv 9101 oat Tod 39 E 6 teva 5700 740953 SyWugsg AGH ALES 2 XOLASI tava srog ES 5191 gz 501451 zzv 0709 15 gt 0 1201 L 040054 4500 08 1993505 200 Sava 2200 198 92007 92170 avs LEE 04508 x 5 ST 2 5 oady Seaav 196 9201 557 NS 8100 M 2 12007 non OWS 098 61009 8 8200 e800 8201 130 6201 IE Ob 039 eoon zady tect 21007 SSIva vigav SH ono 11007
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52. 7 DOLNY OXTOLY SLO LLOd amp QXH LQXH 1IVd 15117 00 2109 21 200 Sur 510199 LLOXH EQXH ELVd ZIOXH PQXH PLvd pd igo suu GX1WS 510 8 04 ELAXH SOXH S Yd SOXHNIV 51 04 vIOXH 9QXH 91vd SAXEN 5 910d Y NILS1M19 10d 194 SIOXL ZOXL8I Vd 21770 T g 5 6 vLOXL 90XLI6 Id T 5 Ly 133 usp Vopr EY 0204 4 saa m E 3NOGObIO 220d LLOXL EQXUZZVd ANT 2204 9 6910 204 Qu T yg BINH _ SINH 5204 10OL9310 92Od VOHWLV 9204 10 2204 SOSHWLV N3 XU SES N S X 5224 SHO AV IOXL OtVd 2 4 NET N3XIWIVU 77774 197 MPC8266ADS PCI User s Manual For More Information On This Product MOTOROLA Go to www
53. INHIBITED PON RESET amp L2CACHE INH PON DEFAULT L2CACHE INHIBITED then L2CACHE INHIBITED else IL2CACHE INHIBITED state diagram L2Flush B state L2CACHE FLUSHED if WRITE BCSR 0 amp L2CACHE FLUSH DATA 2 FLUSHED amp IPON RESET L2CACHE FLUSH PON DEFAULT L2CACHE FLUSHED PON RESET amp L2CACHE FLUSH PON DEFAULT FLUSHED then 140 MPC8266ADS PCI User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information IL2CACHE FLUSHED else L2CACHE FLUSHED state FLUSHED if WRITE BCSR 0 amp L2CACHE FLUSH DATA BIT pin L2CACHE FLUSHED RESET L2CACHE FLUSH PON DEFAULT 2 FLUSHED PON RESET amp L2CACHE FLUSH PON DEFAULT L2CACHE FLUSHED then L2CACHE FLUSHED else IL2CACHE FLUSHED Gs kk sk sk E oR CSCC state diagram L2Lock_B state L2CACHE LOCKED if WRITE BCSR 0 amp L2CACHE LOCK DATA BIT pin LOCKED amp IPON RESET L2CACHE LOCK PON DEFAULT L2CACHE LOCKED PON RESET amp L2CACHE LOCK PON DEFAULT LOCKED then IL2CACHE LOCKED else L2CACHE LOCKED state LOCKED if
54. Reset amp SlotOIntD PON DEFAULT Slot0IntD_Active Reset PCI INTD B then ISlotOIntD Active else SlotOIntD Active MOTOROLA MPC8266ADS PCI User s Manual For More Information On This Product Go to www freescale com 167 Freescale Semiconductor Inc Support Information state SlotOIntD Active if Reset amp 5100130 DEFAULT 510015 Active Reset amp INTD B then SlotOIntD Active else ISlotOIntD Active state diagram 10 state SlotIIntA Active if Reset amp SlotlIntA DEFAULT Slot1IntA Active Reset amp PCI INTD B then ISlotlIntA Active else SlotlIntA Active state Slotl IntA_Active if Reset amp SlotlIntA_PON_DEFAULT SlotlIntA_Active Hard_Reset amp PCI INTD B then SlotlIntA Active else ISlotlIntA Active state diagram Slot1IntB state SlotlIntB_ Active if Reset amp SlotlIntB DEFAULT _ Reset amp PCI INTA B then ISlotlIntB Active else SlotlIntB Active state Slotl IntB_Active if Reset amp SlotlIntB DEFAULT Slot1IntB_Active Reset amp INTA B then SlotlIIntB Active else ISlotlIntB Active k k k k 168 MPC8266ADS
55. 15 jexueus ISH WS 8 diId_ NS 5 woudaa 1009 10jonpuoorueg 6 8 SL C No 440 HOLIMS 01 SAL TT LS Sir id eF 5 Od WS did MS 104 YF SML 514 15 SL Z 040 104 EN CE lod 97 mm 864 5184 50 249 Z Z 3 N399W 8 9 N39494u 8 sn 2211599 104 90 20 S EMS 9 981 199 9 hq O LT rivag 8680 9 6920 9720 ZLINSHd 199 5 VQ LLINSHd 194 7 20 9 21 08 201 6 4 104 id 10 Livag 101NSHd 194 2 8 01 6614 lt 021 SOvHSOHU m 1 5 2 1008 7110473 asog gt 9 S 13 34 130 9614 NS did MS 24 220 SiO a idd 4 92 es 28 710 cB ETE ZJ era 9 i d 4 52 1210 21012 621 04 1 T 8 tad 4 ve 6 SOLNIU EZ SONIVU TMS olvad OSOWLV
56. F 108 198 ddl dl tdl 4 e o avor 4 01 480 2519 iero 9110 cero ozo Sig Dir 108 6H Div 1214599 199 Div 2 2114599 199 8H Div i 1941 Div 2014599 104 Div 101884 194 AE 198 02 10 19945 1002 Ze J9quie oN 19100 YATIOULNOOD 199 v 9219 0219 gt 15 jexuu 151 Jojonpuoarues Freescale Semiconductor Inc sau u zrnb z 101 uqta ST 5914 xx 8VOA CE V9 VIN 22 AldSduHu 0119884 SOLNIU OG1dSI SAS 2 30001 0419 0919 XOL 220 9919 99 WAYAH NorrngHsna 4 SISVHO For More Information On This Product s Go to www freescale com 02 10 L 19945 1002 22 J9quie oN 1 NOISNYdX3 v 9219 Jojonpuoarues
57. IVWugS8g o Su ros non E E 1g 8 Selva 512204 Tod 5 m ms LISON ZE V9 VIN EAT enoa z m Teva g 20d d o 9 6 00 selva 8100 terva 95 100 SESS SIT Svuasu TFOVWHOSH 0 awa 7100 59 awa 100 259 ziva 2 00 89 ZSOWuQSu Loa 959 gt ISOWuqSu aav oya 61 sod M Ivas 8EPNH 226 OViNHISH ONE 8200 0 05 lV NHOSH 89 200 oq dvioiv 2405 QerNH zVINHQSH V9ENH 0 YVOS 9 YvVAHISH L 6 soa av 5 05 224 YVINHOSH OlrNH yeaa e poa N 05 VWugS8g SviNHOSH _ 7 50 9v VOS Y VWugS8 Szaav 200 ov ZVWHGS8 1200 S oa wW 6 06 8 0200 9 v VOrNH LACE 6 00 zv 05 G9INH LIvNHOSH ILVWNHOSH V6ENH iv 01 05 01 05 07 21 06 OSINH SADIO 210000 8201
58. Reset amp Slot2IntA DEFAULT Slot2IntA Active Reset amp INTC B then Slot2IntA Active else Slot2IntA_ Active state diagram Slot2IntB state Slot2IntB_ Active if Reset amp Slot2IntB PON DEFAULT Slot2IntB_Active Reset amp PCI INTD B then ISlot2IntB Active else Slot2IntB Active state Slot2IntB Active if Reset amp Slot2IntB PON DEFAULT Slot2IntB_Active Reset amp INTD B then Slot2IntB Active else Slot2IntB_ Active state diagram Slot2IntC state Slot2IntC Active if Reset amp Slot2IntC DEFAULT Slot2IntC_Active Reset amp PCI INTA B then ISlot2IntC Active else Slot2IntC Active state Slot2IntC_Active if Reset amp Slot2IntC DEFAULT Slot2IntC_Active Reset amp INTA B then Slot2IntC Active else ISlot2IntC Active 170 MPC8266ADS PCI User s Manual For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Support Information state diagram Slot2IntD state Slot2IntD Active if Reset amp Slot2IntD PON DEFAULT Slot2IntD_Active Reset amp PCI INTB B then ISlot2IntD Active else Slot2IntD_Acti
59. ZINSHd ry TI eei eponesod bre HNS8q 104 0 79 bone LIRE Dd nd SIN 1041 IN VINI Od es Ae 194 py OL OGL yg 94 1581 1049 TH 8d x 1 9 Neb 19d AS 0d quo 3404 aol ean Juoi 9901 3004 3901 sero peso sero 7210 60 a NS Td 1015 H 158 108 AS he 95648 1541 EN 1541 707757 22 olay 107709 zv iod z v flay 958 tdv Dd YAV 109 lo 59 1507 10 194 vse 207109 lt 10138 015 438 51040 qo 80 104 609 104 10 09 idv iod idv 104 prav 104 grav iod WV EV piav iod Siav 104 1 138 91041 Vd 104 ONG 3435 1049 085 4 0085 1041 Is ous NOGS 104 1 On
60. kk k k equations KeepPinsConnected TEA_B amp BCTL I KeepPinsConnected com END 7 2 2 U10 PCI Interrupt Controller Code MODULE PCI Interrupt Controller TITLE MPC8265 PCI motherboard ads PCI Interrupt Controller Device declaration k k k kk k k k k k k Pins declaration System i f pins SYSCLK 5 IntContCs_B PIN 20 DVal B PIN 29 MOTOROLA MPC8266ADS PCI User s Manual 157 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information R_B_W PIN 22 BCTLO signal 7 27 8 33 27 34 28 35 29 36 DO PIN 37 istype DI PIN 38 istype D2 PIN 39 istype D3 PIN 40 D4 PIN 12 D5 PIN 11 istype com D6 PIN 10 istype D7 PIN 9 istype PIN 3 D9 PIN 2 istype D10 PIN 1 istype com PIN 48 istype PCI Interrupt Pins PCI PIN 26 istype com buffer PCI Interrupt to PCI INTA B PIN 44 PCI Interrupt from PCI card PCI INTB B PIN 45 PCI Interrupt from PCI card PCI INTC B PIN 46 PCI Interrupt from PCI card PCI INTD_B PIN
61. l3SduHu olg 9 1151 52 ZldOdX3u ol 1SHHl3Ju 319151 9 25 of 38 1 151 01494 30 N3W1Vu E1VISL 81 80 00 219151 o 30 ER 4 E LIVISl 03MdX3U 180100180 019151 61Q0VdX3 Fages 9 e 81Q0vdx3 ol ol 2 U 2 a V 2 a V 82 821 21919 0 821 21919 01 821 219 750 ced Ovd cov oj Wd 5 ores 58 al 1880 vad 828 0120 Sad ver 922 98d Wd 8 Ged 522 184 9 Scd Vd 70 80d 88d 8Vd OIWH1334 22 68d o oza 019 0199 ola OGXHIALV ol LOXHIALV 202 Suu 142 2184 ZQXHW1V 2104 8104 610 2184 01519 4 199 Suu 870 vlad sra 8 3294205 5104 Slad SQXHW1V 1094205 9199 01 35 grad ol A1dXIW1V 2104 1184 ZQXHWLV 919 aXuHl3J ol H8 ZOXLNIV o 8109 3OX8H134 ID era SOX LLY F 6104 0224 2 LOXHHL34 SQXIW1V
62. 5 9207 lod zey 20 D imer Cos E 0874 Teqv Tod 034 BTV ano 1049 159159 ya SIWY T Try 14509 Otte 1 27 t ory Y Pore TO 241 eNO LINSYd IOINSHd 104 O1NI Ogg 199 SV 5 DINI Ddu VO pra Ddu VINI 1049 Svo Ac 191 IGI Tod pO SWL 199 V SNL XOL 5 lt gt ZV 1561 194 1591 1040 TY TH A Q 390 340 3uoi duoi 3uor 001 960 2110 169 A 19d 9910 08 0 210 9210 5210 1994 0 LOIS Ag 10d For More Information On This Product s Go to www freescale com Andy
63. 821 x 5 J llonuoo 1dnu lul Od S1012eUUOO IOd 9 19 99280dlN 22654 4884 WLY 992854 1 WWHaS WOtid33 Pu HSW14 5450948 uoisuedx3 si jjng ueis S eni uonduoseq sau quop eTqeL 189 MPC8266ADS PCI User s Manual For More Information On This Product MOTOROLA Go to www freescale com Freescale Semiconductor Inc Support Information L 1994 1002 72 Wepsen OOTY 900000710 CIO W3lSAS 5928048 equi weunsog 0 1 0 124
64. WRITE BCSR 0 amp L2CACHE LOCK DATA BIT pin L2CACHE LOCKED amp IPON RESET L2CACHE LOCK PON DEFAULT LOCKED PON RESET amp L2CACHE LOCK PON DEFAULT L2CACHE LOCKED then L2CACHE LOCKED else LOCKED kk k kk kk k k state_diagram L2Clear_B state L2CACHE CLEARED if WRITE BCSR 0 amp L2CACHE CLEAR DATA CLEARED amp RESET L2CACHE CLEAR PON DEFAULT L2CACHE_CLEARED PON RESET amp L2CACHE CLEAR PON DEFAULT CLEARED then IL2CACHE CLEARED else L2CACHE CLEARED MOTOROLA MPC8266ADS PCI User s Manual 141 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information state CLEARED if WRITE BCSR 0 amp L2CACHE CLEAR DATA L2CACHE CLEARED amp RESET L2CACHE CLEAR PON DEFAULT CLEARED PON RESET amp L2CACHE CLEAR PON DEFAULT L2CACHE CLEARED then L2CACHE CLEARED else IL2CACHE CLEARED state diagram SignaLampO B state SIGNAL LAMP ON if WRITE BCSR 0 amp SIGNAL LAMPO DATA SIGNAL LAMP amp RESET SIGNAL LAMPO PON DEFAULT SIGNAL LAMP PON RESET amp SIGNAL PON DEFAULT SIGNAL
65. k k k kk kk k k MOTOROLA MPC8266ADS PCI User s Manual 145 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information BCSR 3 ifdef state diagram JtagEn state JTAG ENABLED if WRITE JTAG DOWNLOAD CSR amp JTAG ENABLE DATA BIT pin ENABLED 4 IPON RESET JTAG ENABLE PON DEFAULT JTAG ENABLED PON RESET amp JTAG ENABLE PON DEFAULT JTAG_ENABLED then ENABLED else JTAG ENABLED state ENABLED if WRITE JTAG DOWNLOAD CSR amp JTAG ENABLE DATA BIT pin JTAG ENABLED amp IPON RESET JTAG ENABLE PON DEFAULT ENABLED PON RESET amp JTAG ENABLE PON DEFAULT JTAG ENABLED then JTAG ENABLED else UTAG ENABLED KK K External Read Registers Chip Selects E EE E EE equations Besr2Cs_B oe 4 _ H Besr2Cs READ BCSR 2 Besr4Cs READ 4 Read Registers registers have read BCSR2 and BCSR4 are read externally 146 MPC8266ADS PCI User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale
66. 5 Memory Map and Initialization 5 1 Memory Map All accesses to MPC8266ADS PCI s memory slaves are controlled by the MPC8266 s memory controller Therefore the memory map is reprogrammable to the desire of the user After Hard Reset is performed by the debug station the debugger checks for existence size delay and type of the SDRAM DIMM and FLASH memory SIMM mounted on board and decides on the assignments of CSO and CS4 2 and FLASH and programs the memory controller accordingly The SDRAM E PROM and the FLASH memory respond to all types of memory access 1 problem supervisory program data and DMA This memory map 15 a recommended memory map and since it is soft map devices address may be moved about the map to the convenience of any user There are actually two memory maps which depend on the device assigned to CSO regardless of the boot source The memory address for the device assigned to CSO is always the same as determined in the Hard Reset configuration word Since the FLASH and E PROM require different memory spaces different memory maps are devised for each case For details see Table 3 1 and Table 3 2 Table 5 1 MPC8266ADS PCI Memory Map FLASH or BCSR as Boot Device Address Memory Device Range Type Size Size 00000000 SDRAM DIMM SDCUV6482 SDC8UV6484 64 64 MByte 16 MByte 64 MByte 0
67. 50285089 8541 1104 9 58 9258 8 58 2158 vsu 16014080 25010011 159100 SONW1Vu lt SOHSOBU 9 59959891 9 1 CIMU WOG WOG 03W WOG lt 58214 HNZTu 2 NA mg 109 Y Na lt gt 9 1595210 lt gt 215 761 2 1831 z 1 sum lt gt 201 MPC8266ADS PCI User s Manual For More Information On This Product MOTOROLA Go to www freescale com Freescale Semiconductor Inc Support Information Y 5 oer 19915 1004 Te egunon Tepsenp siEd S928OdW ev SW49dz0d 02199 BIZ0H 15 26309456 181 eraon v quo 3400 40013400 3400 3400 34001 4400 34008 350013001 0000 1619 0610 2110 voro 8 251 920 81102122 8120 told 96 0 9120 e s s s ZN ___ anor 49001 44001 4900 3400 4000 49001 34001 49008 3900 4
68. Bank Based Interleaving Refresh enabled normal operation code address muxing mode 1 A 15 17 on BNKSEL 0 2 9 PSDA10 7 clocks refresh recovery 3 clocks precharge to activate delay 2 clocks activate to read write delay 4 beat burst length 1 clock last data out to precharge 1 clock write recovery time extra cycle on address phase normal timing for control lines 2 clocks CAS latency C2AAB45A PBI in BCSRO should be Set Page Based Interleaving Refresh enabled normal operation code address muxing mode 2 19 on BNKSEL2 PSDA10 7 clocks refresh recovery 3 clocks precharge to activate delay 2 clocks activate to read write delay 4 beat burst length 1 clock last data out to precharge 1 clock write recovery time extra cycle on address phase normal timing for control lines 2 clocks CAS latency 412EB45A PBI in BCSRO should be Cleared Bank Based Interleaving Refresh enabled normal operation code address muxing mode 1 A 15 17 on BNKSEL 0 2 9 5 10 7 clocks refresh recovery 3 clocks precharge to activate delay 2 clocks activate to read write delay 4 beat burst length 1 clock last data out to precharge 1 clock write recovery time extra cycle on address phase normal timing for control lines 2 clocks CAS latency C372B45A PBI in BCSRO should be Set Page Based Interleaving Refresh enabled normal operation code address muxing mode 2 A 16 17 on BNKSE
69. D27 D28 D29 D30 D31 032 GND O Digital Ground Connected to main GND plane of the ADS a MS Bit MOTOROLA MPC8266ADS PCI User s Manual 121 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information 7 2 Programmable Logic Equations There are 4 programmable logic devices on board 1 U14 BCSR 2 UIO PCI Interrupt Controller 3 U22 U23 Address Latch Mux when L2Cache is used 7 2 1 U14 BCSR Code MODULE pq2pcimb TITLE 8265 PCI motherboard ads control status register n this file 2 Prototype B the following changes were made 08 14 01 Added support for default Hard Reset Configuration Word from BCSR by using jumper JP3 Added L2cache support Device declaration Pins declaration System i f pins EL SYSCLK PIN 11 BrdContRegCs B PIN 36 DVal B PIN 43 RBW PIN 86 BCTLO signal BCTLI PIN 64 Alternate Buffers Enable source AT PIN 98 for flash support 8 4 for flash support 27 5 28 7 29 8 122 MPC8266ADS PCI User s Manual For More Information On This Product Go to www fr
70. Traces are as short as possible Clock signals and sensitive strobe signals are shielded and routed as a chain Multilayer with ground and supply layers PCI signals lengths and impedance according to PCI Standard Rev 2 2 102 MPC8266ADS PCI User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information 7 Support Information In this chapter all information needed for support maintenance and connectivity to the MPC8266 ADS PCI is provided 7 1 Interconnect signals The MPC8266ADS PCI interconnects with external devices via the following set of connectors poc Ue LUN TM P1 RS232 ports 1 and 2 P2 100 10 Base T Ethernet port P3 COP JTAG P4 CPM Expansion P5 P6 P10 11 P13 P14 P16 P18 P19 Logic Analyzer MICTOR Connectors P7 P8 P9 PCI Slots Connectors P12 ATX Power Supply Connector P15 Mach Lattice In System Programming ISP P17 System Expansion 7 1 1 P1 5232 ports 1 and 2 Connectors P1 is a dual 9 Pin D Type connectors as described in Table 7 1 Table 7 1 P1 Connector Pin No Signal Name Description 1 CD Carrier Detect output from the MPC8266ADS PCI 2 TX Transmit Data output from the MPC8266ADS PCI 3 RX Receive Data input to the MPC8266ADS PCI 4 DTR Data Terminal Ready input to the MPC8266ADS PCI 5 GND Ground signal o
71. device row starts Fujitsu at A9 12 row lines internal bank interleaving allowed normal AACK operation Depends the SDRAM PPG TBD Not used for the type of SDRAM supplied with the DIMM board Value is specific foran SDRAM DIMM OR3 Depends on the SDRAM TBD Not used for the type of SDRAM supplied with the DIMM board Value is specific foran SDRAM DIMM MOTOROLA MPC8266ADS PCI User s Manual 34 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Operating Instructions Table 3 7 Memory Controller Initializations For 66Mhz as Boot Device Reg Device Type Bus nit value Description hex BR4 SM73228XG1JHBG0 by PPG C3801801 Base at C3800000 32 bit port size no parity Smart Modular Tech GPCM SM73248XG2JHBG0 by C3001801 Base at C3000000 32 bit port size no parity Smart Modular Tech GPCM ASM73288XG4JHBG0 C2001801 Base at C2000000 32 bit port size no parity by Smart Modular Tech GPCM OR4 SM73228XG1JHBG0 by FF800836 8MByte block size CS early negate 6 w s Timing Smart Modular Tech relax SM73248XG2JHBG0 by FF000836 16MByte block size CS early negate 6 w s Smart Modular Tech Timing relax SM73288XG4JHBG0 by FE000836 32MByte block size CS early negate 6 w s Smart Modular Tech Timing relax BR5 PM5350 ATM UNI PPG 04600801 Base at 04600000 8 bit port size no parity GPCM
72. lt 53i geyd Aqui 4 194 berg ca gt 16 Diy 1041 1 7 pzs 1 239 0 041 PA MEREEN EEY 0009 0019 Di 12401 iod 154 Zev gl ov Acer 29 10 d 810 104 E 6 10775 iea dv iod gay 0009 erg Say Tad pzy ONS t C Ae 210 104 msa besg asm 320810 sey 182109 da bod GINI Ddu 28109 728 104 OLY CAMP DINI 154 1220 Vzav 104 ANNINA AIN 8204 109 ZV 6404 558 1 698 Div YINI 1Odu 2 oslav LZE 108 2 9807 04 BAR dad 298 108 foau gt ano 2115 1049 IV 718 1 H 1 ad ano 4 2086 189 Dd BUY Yih 194 T LIB Dir 1085 1048 ZP I3NOGS 104 4518 Lv 0085 19 194 214509 _ 104 OR 411 NSud ore r ase Pei IZINSHd 154 gt Vd SHENI SIN Od mr adem ain 9 DEF 158 1097 T E DH 201 38 esed 10d Wim ous
73. 40 1 M 1 Daendd b 28189 Fo Dandou 99190 nw Haendo 88089 29 wandou wandou 58089 2281 ei ora 225 rriv 02151 23251 23251 H 0281 13261 13251 29140 5 P ar 66190 LLL zu Selva ILL 16140 OL 96190 Q selva egy zo velva idv edy selva 099 619 14 21 04 21 ev lev I V OEY 62 Sv gg 82 921 0 ory sev gzv lt 21 0 Org 2240 sev sev 21 0 Oro ezv 221 0 BO 2240 zzy 12170 1210 key 12 IU 99 s092OdW oy 6LIVG sen sy Shiva 919 81 IN oly 91 oy 91 nv ELLY aly ny uv ov 6v 6v 6140 av 81 0 V ly 9v 9v Sv Sv Siva eva 2 iv 12 ov ov 0140 Jeo9zodiN 193 ON 1 ON 0610 6210 8210 9210 5210 8211 2218 6 10 610 810
74. HARD_RESET_ACTIVE 0 SOFT RESET 0 HARD RESET ASSERTED SyncHardReset B fb HARD RESET ACTIVE data buffers enable BUFFER_DISABLED 1 BUFFER_ENABLED SUFFER_DISABLED BUFFER HOLD OFF HoldOffCnt fb 0 the delay is required for read as well since a fast device eg bcsr may content with the flash eeprom END OF FLASH EEPROM READ DVal amp Cs0 B 54 B B amp DSyncHardReset_B fb end of flash eeprom read cycle not during hard reset config END OF PCI INT CONT READ DVal_B amp PCIIntContCs B amp B end of PCI Interrupt Controller read cycle END OF READ DVal B amp AtmUniCsIn B amp end of atm uni m p i f read cycle END OF OTHER CYCLE DVal B amp 50 B amp Cs4 B amp AtmUniCsIn B amp PCIIntContCs B another access amp AtmUniCsIn B amp W atm uni write or B amp ToolCs1 B amp W tool 1 write or MOTOROLA MPC8266ADS PCI User s Manual 135 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information B amp ToolCs2 B amp B W tool 2 write or IDVal B amp ICs0 B Csd Ws flash eeprom write IDVal B amp PCIIntContCs B amp B PCI int cont write
75. Initially at 102000000 hOFOOFFFF set by hard reset configuration Refer to the MPC8266 User s Manual for complete description of the internal memory map e An 8 Kbyte device is used 16 Kbyte and 32 Kbyte devices can also be used so it appears repeatedly in 8Kbyte multiples starting from C2000000 f Set by hard reset configuration Table 3 2 MPC8266ADS PCI Memory Map E PROM as Boot Device Address Memory Device Range Type Size Size 00000000 SDRAM DIMM SDCUV6482 SDC8UV6484 64 64 MByte OOFFFFFF 16 MByte 64 MByte 01000000 03FFFFFF 28 MPC8266ADS PCI User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 3 2 MPC8266ADS PCI Memory Map E PROM as Boot Device For More Information On This Product Go to www freescale com Address Memor Port Device Tory Range Type Size Size 04000000 Empty Space 5 MByte 044FFFFF 04500000 7 32 32 KByte 04507FFF 04500000 BCSRO 4 Byte 04507FE3 04500004 BCSRI 4 Byte 04507FE7 04500008 BCSR2 4 Byte 04507FEB 0450000C BCSR3 4 Byte 04507FEF 04500010 BCSR4 4 Byte 04507FF3 04500014 BCSR5 4 Byte 04507FF7 04500018 BCSR6 4 Byte 04507FFB 0450001 BCSR7 4 Byte 04507FFF 045
76. Schematics qe od Houma eked oa 188 732 Bill of Materials 210 MOTOROLA MPC8266ADS PCI User Manual V For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table of Contents VI MPC8266ADS PCI User Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc List of Tables List of Tables 1 1 MPC8266ADS PCI specifications 3 2 1 MODCK L E COdIB6 IE x bas Eu ees 2 2 SW2 SDRAM DIMM Configuration EEPROM Slave Address 15 3 1 MPC8266ADS PCI Memory FLASH or BCSR as Boot Device 27 3 2 MPC8266ADS PCI Memory E2PROM as Boot Device 28 3 3 BCSR FLASH Power On Reset Configuration 31 3 4 E2PROM Power On Reset Configuration 31 3 5 SIU REGISTERS PROGRAMMING 22 3 6 Memory Controller Initializations For 66Mhz FLASH as Boot Device 33 3 7 Memory Controller Initializations For 66Mhz E2PROM as Boot Device 34 3 8 Memory Controller Initializations For 66Mhz 36 4 1 BCSR FLASH Hard Reset Configuration Word 42 4 2 E2PROM Hard Reset Configuration Word 44 4
77. ZOXHHLI3J O6INH LOXHHLI3J Q6INH S 0QXHH134 961 1 133 LEY V6INH T 8 6 537 6 S lt TV 5 134 SHY VeNH I 8 H3XHH1334 Y 26 S N3XIHI34 AGX8H133 vov SHNH 27277 H3X1H134 20 Ova 522 Ld ZVd 625 3259 SVd IZENA 9vd ScHV 8Vd S TOIOXUWIV OOXHLV ZQXHW1V OXHIALV SISV ENA ELENA ZOXYNLY TOXIN LV ELNA VOINH STOV VOZNH 9AXINLY t SOXINIV 202 8 YOXLNLV 2137 SOXLW1Y Hov V8INH 981 LOXLLV 81 OOXLNLV Hv VOUNIV Jv SOSHW1V Sav d8INH N3XHIN1 Vu 2051007 VO1W1V sav VETNH NSXLALVU s Go www freescale com For More Information On This Product
78. 15 ISH Freescale Semiconductor Inc HOLO3NNOO 194 194 AS 299 ase LS 9084 1049 097 ecd Pose gt 55 o0 ov olay 5 8 09 108 izolav Hea Fav tod 8 008 159 Sov roov 1 559 Sav 134 IAV 194 757 1 is d Taw zeyd 0198 0 gt lsolav 039 9 1049 ang amp 258 194 ano AEE 1 lt ose N399W woo Sy olay w tap 10 Tay Tod fellow piov lod 104 bray 07109 6009 0380 oa Hyd 10d 1 Pere 5335 1049 088 Noas uu3d DES NOGS 104 7001 MOOT 1
79. 2 3 PRSNT 0 1 PCI Slot 1 Present 0 1 This field holds a code that tells whether PCI 11 R expansion board is pluged in PCI slot 1 and the total power requirements of the board according to the PCI spec The different expansion board types are listed in Table 4 21 4 5 PCI2 PRSNT 0 1 PCI Slot 2 Present 0 1 This field holds a code that tells whether a PCI 11 R expansion board is pluged in PCI slot 2 and the total power requirements of the board according to the PCI spec The different expansion board types are listed in Table 4 21 6 M66EN 66MHz Enable This field shows if one of the expansion boards used is not 1 R capable of operating in 66MHz mode 1 All expansion boards are 66MHz capable 0 One of the expansion boards is not 66MHz capable 7 31 Reserved Un Implemented Table 4 21 PCI Board Present Signal Definitions PCIx PRSNT 0 1 Hex Expansion Configuration 0 Expansion board present 7 5W maximum 1 Expansion board present 25W maximum 2 Expansion board present 15W maximum 3 No expansion board present 4 13 5 BCSR3 and BCSR5 Board Control Status Register 3 amp 5 BCSR3 and BCSR5 are additional control status registers which may be accessed as a word at offset 0x10 to 0x14 from BCSR base address These registers are not implemented They may be read or written but with no valid data nor any effect on the board The description of BCSR
80. 66 MHz Bus Clock Freq Cycle Type Flash Delay nsec 95 Read Access 88 Writeb Access From TS asserted However due internal activity these figures may be larger b The figures in the table refer to the actual write access The write operation continues internally and the device has to be polled for completion The Flash module may be disabled enabled at any time by writing 1 70 respectively to the 1 i e initialization that follow the hard reset sequence at system boot MOTOROLA MPC8266ADS PCI User s Manual For More Information On This Product Go to www freescale com 59 Freescale Semiconductor Inc Functional Description FlashEn bit in BCSR1 The Flash connection scheme is shown in Figure 4 7 FLASH SIMM DATAQ3D ADDRESS 7 29 A 22 0 WEO WEO WEI WE gt WE2 WE3 BCSR POE POE CSI CSI 50 FLASH CSI CS cs 52 54 gt gt 53 CS CS4 PD2 Lg PD3 4 PD4 5 PD5 lt 06 PD6 a PD7 Figure 4 7 FLASH SIMM Connection Scheme As can be seen in Figure 4 7 the FLASH CS is distributed to four CS signals The distribution depends on the size of the FLASH module installed it is read by the BCSR using the PD 1 7 pins The Hard Reset confi
81. 910 na 094981 291 0 191vd 091 0 661901 891901 181401 961901 551 0 ys1va 251 01 18190 051 0 0 1 0 6514 BELY 16140 914 selva velva selva 1 relva OE LV 621 0 821 0 921 0 521 0 21 0 21 0 221 0 12140 021 0 911701 5 ELLY 2 OLIVG 61vd 8170 91 0 S1vd 25741 21 LYG EW eno 3 NEPAL 5 eS MPC8266ADS PCI User s Manual For More Information On This Product 196 Go to www freescale com Freescale Semiconductor Inc Support Information
82. A19 N C Not Connected A20 EXP3 3V O 3 3V Power Out These lines are connected to the main 3 3V plane of the PQ2PCIAI ADS this to provide 3 3V power where necessary for A21 external tool connected A22 A23 A24 A25 N C Not Connected MOTOROLA MPC8266ADS PCI User s Manual 117 For More Information On This Product Go to www freescale com Support Information Freescale Semiconductor Inc Table 7 8 P17 System Expansion Connector Pin No Signal Name Attribute Description A26 EXPVCC 5V Supply Connected to ADS s 5 plane Provided as power supply for external tool 27 28 29 1 A32 1 GND O Digital Ground Connected to main GND plane of the ADS B2 B3 B4 TSTATO I Tool Status 08 7 These lines may be driven by an external tool to be read via BCSR2 of the ADS These lines are pulled up on the ADS by B5 TSTATI 10 resistors See also Table 4 12 BCSR2 Description on page 71 B6 TSTAT2 B7 TSTAT3 B8 TSTAT4 B9 TSTATS B10 TSTAT6 Bll TSTAT7 B12 TOOLREVO I Tool Revision 0 3 These lines should be driven by an external tool with the Tool Revision Code to be read via BCSR2 of the ADS These TOOLREVI lines are pulled up on the ADS by 10 resistors See also Table 4 12 B14 TOOLREV2 BCSR2 Description on page 71 15 TOOLREV3 16 EXTOLIO I External Too
83. For More Information On This Product Go to www freescale com Memory and Initialization Freescale Semiconductor Inc Table 5 1 MPC8266ADS PCI Memory Map FLASH or BCSR as Boot Device Address Range C1FFFFFF C0000000 Memory Type Empty Space Device Name Port Size Memory Size 32 MByte C2007FFF C2000000 2 ATMEL AT28HC64B 32 KByte FDFFFFFF C2008000 Empty Space 1 GByte FEFFFFFF 000000 FF7FFFFF FF000000 FFFFFFFF FF800000 Flash SIMM 16M SIMM SM73248 8M SIMM SM73228 32M SIMM SM73288 32 32 MByte a The device appears repeatedly in multiples of its port size in bytes X depth E g BCSRO appear at memory locations 4700000 4700020 4700040 while BCSR1 appears at 4700004 4700024 4700044 and so on b The internal space of the ATM UNI control port is 256 bytes however the minimal block size tha may be controlled by the GPCM is 32 KBytes Initially at 102000000 hOFOOFFFF set by hard reset configuration Refer to the MPC8266 User s Manual for complete description of the internal memory map e An 8 Kbyte device is used 16 Kbyte and 32 Kbyte devices can also be used so it appears repeatedly in 8Kbyte multiples starting from C2000000 f Set by hard reset configuration Table 5 2 MPC8266ADS PCI Memory Map 2 as Boot Devic
84. JtagShiftIR fb Jtag Instruction Register equations JtagIR clk JtagIR ap JtagReset reset gt bypass JtagIR ar 0 154 MPC8266ADS PCI User s Manual For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Support Information when STATE JTAG UPDATE IR amp NEXT INST DOWNLOAD NEXT INST PON RESET then JtagIR JtagShiftIR fb else when STATE JTAG UPDATE IR amp INST DOWNLOAD NEXT INST PON RESET then JtagIR INST CODE BYPASS else JtagIR JtagIR fb hold value k k k kk kk k k Download Shift Bypass Register equations JtagShiftDR clk Tck JtagShiftDR ar JtagStateReset JtagShiftDR ap 0 when JtagShiftDrState fb amp INST_IS_BYPASS JtagShiftDrState fb amp INST IS DOWNLOAD amp JTAG DOWNLOAD SHIFT REG FULL then JtagShiftDRO JtagShiftDR7 Tdi JtagShiftDRO fb JtagShiftDR 1 fb JtagShiftDR2 fb JtagShiftDR3 fb JtagShiftDR4 fb JtagShiftDR5 fb JtagShiftDR6 fb else JtagShiftDR JtagShiftDR fb hold Receive Full Flag equations JtagReceiveFull clk Tck JtagReceiveFull ar JtagReceiveFullReset com JtagReceiveFull ap 0 when STATE_JTAG_EXIT1_DR amp INST_IS_DOWNLOAD then end of download byte JtagReceiveFull RECEIVE FULL else MOTOROLA MPC8266ADS PCI User s Manua
85. O X2 Du YENI E zn 204 6200 8 10 WHLSAS 99280dN ES RS 12 Tu 00000 Ne AHLHV 50 VEN 8 3 Q O CS 4 H3 14 zu MEM a 10 9 3 eam souvieaovg ana mE TO oat O O O O O LEA ONS T Earn 1949 Sac 9 18084057 zm O O O O O eou aav 5801 104 X d VLSTu 9 920 SE dou MAN sn Ez S ZNH gu 520 HM2gON 104 2149 5 081 301 B 2939008 9 EZE LHMOGOW 19d Hd9 1 OOOO0 ay am 13q 01d9T u Hy Sat SNL M 5380 4 8 O O O O O O O O O O O O O OD OOO O O O O O O O la sui m 59 9 2389 048401 55 z E 1888 R e O OO O O O O O O O O O O O O O O O O O O O O O O NV PEROU 0382 04040144 25 8 93uvds 038 9 52 3043 8 vauvas 205 9 22288799 54888855 15 95 5 lt lt 15 06
86. Read k k k k k k DataOe NODE istype data bus output enable on read PCI Interrupt Request to PQ2 PCI Interrupt NODE istype com generated Interrupt to 2 Chassis Power Switch Buffer Power Buffer NODE istype reg buffer generated Interrupt to PQ2 Creating internal clock generator inv1 istype com keep inv2 NODE istype com keep inv3 NODE istype com keep inv4 NODE istype com keep inv5 NODE istype com keep counter counter counter2 counter3 counter4 counter5 160 MPC8266ADS PCI User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information counter6 counter7 countera0 counteral countera2 countera3 countera4 countera5 countera6 countera7 NODE istype reg buffer k k k k k k H L X Z 1 0 X 27 C D U C D U SIMULATION 1 Signal groups IntReg SlotOIntA SlotOIntB SlotOIntC SlotOIntD SlotlIntA SlotlIntB Slot1IntD Slot2IntA Slot2IntB Slot2IntC Slot2IntD IntMaskReg SlotOIntAMask SlotOIntBMas
87. Table 5 7 Memory Controller Initializations For 66Mhz as Boot Device Init Value Reg Device Type Bus hex Description BRO E PROM PPC 0801 Base at 8 bit port size write protect disabled no parity GPCM OR0 AT28HC64B 70JC by FFFF8846 32 KByte block size cs output half a clock after Atmel address all types access 4 w s Timing relax MOTOROLA MPC8266ADS PCI User s Manual 93 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Memory Map and Initialization Table 5 7 Memory Controller Initializations For 66Mhz as Boot Device Reg Device Type Bus nit vaye Description hex BR1 BCSR PPC 04501801 Base at 04500000 32 bit port size no parity GPCM OR1 FFFF8010 32 KByte block size all types access 1 w s BR2 All SDRAM DIMM PPG 00000041 Base at 0 64 bit port size no parity Sdram Supported machine 1 OR2 SDC2UV6482C 84 FF000C80 16MByte block size 2 banks per device row starts Fujitsu at A9 11 row lines internal bank interleaving allowed normal AACK operation SDC8UV6484C 84 by 002 0 64MByte block size 4 banks device row starts Fujitsu at A9 12 row lines internal bank interleaving allowed normal AACK operation BR3 Depends on the SDRAM TBD Not used for
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89. DP6 as IRQ6 DP7 as IRQ7 Reserved 12 0 Reserved ISB 13 15 910 IMMR initial value 0 0 000000 i e the internal space resides initially at this address 44 MPC8266ADS PCI User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Functional Description Table 4 2 E2PROM Hard Reset Configuration Word Data Prog Offset In Value Field Bus Value Implication Flash Hex Bits Bin Hex BMS 16 0 Boot memory E PROM 0000 10 36 BBD 17 0 is ABB DBB IRQ3 is DBB MMR 18 19 11 Mask Masters Requests Master is PCI LBPC 20 21 01 Local Bus pins function as PCI bus APPC 22 23 10 MODCK1 AP 1 TC 0 functions BKSELO MODCK2 AP 2 TC 1 functions as BKSEL1 MODCK3 AP 8 TC 2 functions as BKSEL2 IRQ7 APE functions as 7 CS11 AP 0 functions as CS11 CS10PC 24 25 01 CS10 BCTL1 DBG_DIS functions as BCTL1 18 45 ALD EN 26 0 PCI Auto Load Enable When high PCI Bridge Configuration is done automatically from the FLASH E PROM is configuration source PPC core should be disabled right after the Hard Configuration Word When low the PPC Core should configure the PCI Bridge Reserved 27 0 Reserved MODCK_HIP 28 31 0101 Determines the Core s frequency of power up reset Core starts at 166 2 Actually not relevant when the PCI is act
90. application s w may be programmed into its Flash memory and ran in exhibitions etc 1 Either on or off board MOTOROLA MPC8266ADS PCI User s Manual 1 For More Information On This Product Go to www freescale com General Information Freescale Semiconductor Inc 1 2 Definitions Acronyms and Abbreviations MPC8266ADS PCI MPC8266 VOYAGER PPC PCI CPM SDRAM VADS Kbyte LSB Isb Mbyte DIMM SIMM TBD UPM EVB GPCM GPL BCSR FLASH ZIF BGA ADI COP SAR UTOPIA PowerQUICC II PCI MotherBoard PowerQuicc 2 with PCI local bus MPC8260 PowerQUICC 2 PowerPC Peripheral Components Interconnect Communication Processor Module Synchronous Dynamic Random Access Memory Voyager Application Development System 1024 bytes Least Significant Byte least significant bit 1048576 bytes Dual In line Memory Module Single In line Memory Module To Be Defined User Programmable Machine Evaluation Board General Purpose Chip select Machine General Purpose Line Board Control and Status Register Non volatile reprogrammable memory Zero Input Force Ball Grid Array Application Development Interface Common On chip Processor Segmentation And Reassembly Universal Test amp OPerations Interface for ATM 1 3 Related Documentation e 8266 User s Manual e VADS Users Manual e 2605 Data Sheet Attp mot sps com books dl156 pdf mpc2605rev6 pdf e PMC SIERRA 5350 Long Form Data Sheet hi
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94. 203 MPC8266ADS PCI User s Manual For More Information On This Product MOTOROLA Go to www freescale com Freescale Semiconductor Inc Support Information 7 z z T 5 lt 02 Si us 1002 ZZ Z Dd 0819 eie 15 994 18 80 10 v M EE 90 946 so PS pno by DDO 200 6818 x 752110 MEM OMTOIOd STH OE 17071009 sin qu qe quo 10a 10d Ls 1s 2 4 LA
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96. 8 v 6 2 ueis s w uonduoseq For More Information This Product s Go to www freescale com lt gt For More Information This Product s Go to www freescale com L 2 2 02 26 ITS 7002 72 SQUISAON bN3 WALSAS 9928044 eu Joquinn jueuinsog zg SASS 58558 558 CCC d C nd und 1 1 0219 12 9 gt gt gt gt 22 2 gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt e
97. Board Control amp Status Register BCSR Controlling Boards Operation e Fast Download support via JTAG Power On Reset Option via Programmable Power On Reset and Hard Reset Configuration via E PROM or via Flash memory for the PQ2 core and PCI module PCI Local Bus is PCI Standard 2 2 compliant 3 PCI slots are available to host up to 3 masters targets cards 3 3V only arbitration is supported by the on chip Arbiter PCI bus supports 25 66 MHz 3 3V devices determined by the user Simple generic Interrupt Controller to handle the PCI interrupts 4 in each PCI slot e form factor board design in a standard case in order to comply with the power requirements for the PCI slots according to the PCI standard Module Enable Indications for all on board modules Highdensity MICTOR Logic Analyzer connectors carrying all 60x and CPM signals for fast logic analyzer connection e 155 Mbps ATM UNI on with Optical I F connected to the MPC8266 UTOPIA I F using the PMC SIERA 5350 100 10 Base T Port on FCC2 with I F controlled using Level One LXT970 Dual RS232 port residing on 5 1 4 SCC2 Module disable 1 low power mode option for all communication transceivers BCSR controlled enabling use of communication ports off board via the expansion connectors Dedicated MPC8266 communication ports expansion connectors for convenient too
98. Core enabled Single MPC8266 60X Bus mode 32 Bit boot port size Exceptions vectored to OxFFFxxxxx Internal space 64 bit slave for external master 8 B2 L2cache signals configured as BADDRx lines DP 1 7 configured as L2 cache and IRQ 6 7 Initial internal space OxOF000000 10 36 Boot memory space OxFE000000 OxFFFFFFFF ABB IRQ2 pin is ABB DBB IRQ3 pin is DBB No masking on bus request lines Local bus pins function as PCI PCI is boot master AP 1 3 configured as BNKSEL 0 2 APE configured as IRQ7 and CS11 as CS11 18 60 510 configured as BCTL1 PCI autoload from FLASH a Programmed into the Flash memory in addresses 0x0 0x8 0x10 amp 0x18 b With L2 Cache Table 5 4 2 Power Reset Configuration EEPROM Init Address Description Value hex hex 0 04 145 Internal arbitration Internal memory controller Core enabled Single MPC8266 60X Bus mode 8 Bit Boot size Exceptions vectored to OxFFFxxxxx Internal space 64 bit slave for external master 8 B2 L2cache signals configured as BADDRx lines DP 1 7 configured as L2 cache and 6 7 Initial internal space 0x0F000000 10 36 Boot memory space OxFE000000 OxFFFFFFFF ABB IRQ2 pin is ABB DBB IRQ3 pin is DBB No masking on bus request lines Local bus pins function as PCI is boot master AP 1 3 configured as BNKSEL 0 2 APE configured as IRQ7 and CS11 as CS11 18 60 CS10 configur
99. ENABLED if WRITE BCSR 1 amp FETH ENABLE DATA ENABLED 4 IPON RESET ENABLE PON DEFAULT ENABLED PON RESET amp FETH ENABLE PON DEFAULT ENABLED then ENABLED else FETH ENABLED state ENABLED if WRITE BCSR 1 amp FETH ENABLE DATA BIT pin FETH ENABLED amp RESET ENABLE PON DEFAULT ENABLED PON RESET amp FETH ENABLE PON DEFAULT FETH ENABLED then FETH ENABLED else IFETH ENABLED state diagram FEthRst_B state RESET ACTIVE if WRITE BCSR 1 amp FETH RESET DATA BIT pin RESET ACTIVE IPON RESET RESET PON DEFAULT FETH RESET ACTIVB PON RESET amp FETH RESET PON DEFAULT IFETH RESET ACTIVB then RESET ACTIVE else FETH RESET ACTIVE state FETH RESET ACTIVE if WRITE BCSR 1 amp FETH RESET DATA BIT pin FETH RESET ACTIVE amp RESET RESET PON DEFAULT FETH RESET PON RESET amp FETH RESET PON DEFAULT RESET then FETH RESET ACTIVE else 144 MPC8266ADS PCI User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information RESET ACTIVE G
100. For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Hardware Preparation and Installation The connectors are arranged in a manner that allows for 1 1 connection with the serial port of an IBM AT or compatibles i e via flat cable The pinout which is identical for both and is shown in Figure 2 13 CD TX RX DTR GND DSR N C CTS N C WN Oo o Figure 2 13 P1A P1B RS232 Serial Port Connector 2 4 5 10 100 Ethernet Port Connection The 10 100 Base T port connector P2 is an 8 pin 909 receptacle RJ45 connector The connection between the 10 100 Base T port to the network is done by a standard cable having two RJ45 8 jacks on its ends The pinout of P2 is described in Table 7 2 P2 100 10 Ethernet Connector on page 104 2 4 6 Memory Installation The MPC8266ADS PCI is supplied with two types of memory modules Synchronous Dynamic Memory DIMM Flash Memory SIMM 2 4 6 1 Flash Memory SIMM Installation To install a memory SIMM it should be taken out of its package put diagonally in its socket U30 no error can be made here since the Flash socket has 80 contacts while the SDRAM socket has 168 and then raised to a vertical position until the metal lock clips are locked See Figure 2 14 1 IBM AT is a trademark of International Business Machines Inc 18 MPC8266ADS PCI User s Manual MOTORO
101. e i su 18 09 gt ac LE SH 10 1 SH 7510 Su anor 591 60 Anon 0193 T z Y 5 MPC8266ADS PCI User s Manual For More Information On This Product 200 Go to www freescale com Freescale Semiconductor Inc Support Information 02 p z 12949 1002 22 Tepsen aed tv 9409209 eni TAVASI 19 18 YUUS 18 LOLON Dir SIGYOULY 540054 190059 95258 40059 240054 244054 844054 SNMOG 13501 5155 eua oTIOgu uo spu d p PITA ou v ou ou Na sok zea EIZA ZEA 9 ETZU jr PIZA POZA VISN 0 76024 uo JEA PEN
102. for read 8 for write extended hold time after read MOTOROLA MPC8266ADS PCI User s Manual 33 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 3 6 Memory Controller Initializations For 66Mhz FLASH as Boot Device Reg OR8 Device Type PCI Interrupt Controller Init Value Bus hex Description PPC 04731801 Base at 04730000 32 bit port size no parity GPCM on PPC bus FFFF8010 32 KByte block size all types access 1 w s Table 3 7 Memory Controller Initializations For 66Mhz Boot Device Init Value n Reg Device Type Bus hex Description BRO 2 FFF00801 Base at 8 bit port size write protect disabled no parity GPCM ORO AT28HC64B 70JC by FFFF8846 32 KByte block size cs output half a clock after Atmel address all types access 4 w s Timing relax BR1 BCSR PPG 04501801 Base at 04500000 32 bit port size no parity GPCM OR1 FFFF8010 32 KByte block size all types access 1 w s BR2 All SDRAM DIMM PPG 00000041 Base at 0 64 bit port size no parity Sdram Supported machine 1 OR2 SDC2UV6482C 84 by FF000C80 16MByte block size 2 banks per device row starts Fujitsu at A9 11 row lines internal bank interleaving allowed normal AACK operation SDC8UV6484C 84 by 002 0 64MByte block size 4 banks
103. 13 98 Added SdramA9 which is latched A10 saving another LCX373 Tn this 4 Rev PILOT 02 18 99 Added support for PBI Page Based Interleaving feature added with PQI rev A To provide that support the following were made Added DimmSize input which provides SDRAM dimm size information Only 16Meg reset default and 64Meg DIMMs are supported This signal originates in BCSR Added PBI indication Since actual seeting is done within the POIL it is the system programmer responsibility to set the correct value for this signal in BCSR to ensure proper operation To make room for the above SdramA 9 8 are moved to another device along with A20 The output of this mux is now qualified with the DimmSize and PBI information to provide the correct address lines to the dimm Tn this 5 Rev 03 21 99 Pinout is changed to 4 64 32 7 48 package In this 6 rev 01 20 00 nverted Polarity for Sdrama 7 0 due to inversion between q and output k k k k k k k Pins declaration 5 Control pins 184 MPC8266ADS PCI User s Manual For More Information On This Product Go to www freescale com MOTOROLA
104. 150 Ju 1922 7719 La ol 55 ISHNIVU 50285089 S1IVO8 zon 5 01 10 01 95 16 750 du Tazz zon ZN3 Suu HSNZ La OA r9 821 N 001 LS IN3 SHU 25010011 vin 730 255 Ju NS SW sio are sivas SAIN aps ono 2101 3 12 810 18814 99 eno 01590 zio 0 L1vag 59 40 1822 281H Sv SEON 19 valu 0101 ve 5 1 08 Tad Dno SOuSOgu WAU vr XL 530 12 55 Ha 5929598 2 SEON 2m voro E L7 6lvag 1604 81vd8 3 WORT quo 230 ezon 318vN3 10 99 ZIVIST E Sa 71 08 Sorusogu m 6201 184 egi SIVISI 0501 Son LE ii 1 SIVISL 09 LS S1vd8 1501000 201 5 5217201 ICE gig 5 ido 3NOOISHu E V T d 00 4 0 tu 8 Evaa 21 dd 9 1109 019181 01908 25 gen 3900 3400 34001 130001 39001 ezo TEOTTVOS asio vero s919 3 zi 3 E m 8SAS T 7 auoo 3400 131007 39001 voor 39001 3007 31007 7 1001951 ezzo zezo szzo vszo
105. 2 13 JPA 23 3214 VPP Source Selector aes eS 24 du OND u as asua dab ey 24 3 2 16 A TM TX Indicator DRE ER RIA ME 24 3 2 17 Fast Ethernet Indicator LD2 24 3 2 18 Fast Ethernet CLSN Indicator LD3 24 3 2 19 Ethernet LINK Indicator LD4 25 3 2 20 Ethernet TX Indicator 105 25 3 221 12V Indicator LD6 s bL Tq GU E VS 25 3 2 22 RX Indicator 107 25 3 2 23 Ethernet RX 8 25 3 2 24 5V Indicator EDO 25 3 2 25 12V Indicator 2010 SS XA RT UE RERO E 25 3 2 26 3 3V 1 25 32 271 RUN Indicator LD12 2 OSES 25 3 228 uet 25 3 2 29 Fast Ethernet Port Initially Enabled LD14 25 2 2 30 4 RS232 Port TON RG DEAE 26 3 2 31 RS232 Port EDIO BEES 26 3 2 32 VDDL Indication 017 1 26 Mem
106. 3 2 19 Ethernet LINK Indicator LD4 The yellow Ethernet Twisted Pair Link Integrity LED indicator LINK lights to indicate good link integrity on the 10 100 Base T port LD4 is off when the link integrity fails 3 2 20 Ethernet TX Indicator LD5 The green Ethernet Receive LED indicator blinks whenever the LXT970 is transmitting data via the 10 100 Base T port 3 2 21 12V Indicator LD6 The green 12V led LD6 indicates the presence of the 12V supply on the ADS 3 2 22 ATM RX Indicator LD7 The green Receive LED indicator blinks whenever the PM5350 ATM UNI 15 receiving cells via port It illuminates only when the transceiver is enabled via BCSRI 3 2 23 Ethernet RX Indicator LD8 The green Ethernet Receive LED indicator blinks whenever the LXT970 is receiving data from the 10 100 Base T port 3 2 24 5V Indicator LD9 The green 5V led LD9 indicates the presence of 5V supply on the ADS 3 2 25 12V Indicator LD10 The green 12V led 1010 indicates the presence of the 12V supply on the ADS 3 2 26 3 3V Indicator LD11 The green 3 3V led LD11 indicates the presence of the 3 3V supply on the ADS 3 2 27 RUN Indicator LD12 When the green RUN led 1012 is lit it indicates that the MPC8266 is performing cycles on the Bus When dark the 8266 is either running internally or stuck 3 2 28 ATM ON LD13 When the yellow ATM ON led is lit it indicates that the ATM
107. 3 PCI Interrupt Register Description 49 4 4 PCI Interrupt Mask Register Description 50 4 5 MPC8266 MB Chip Select Assignments 54 4 6 SDRAM DIMM 84MHz Performance 56 4 7 66 MHz SDRAM DIMM Mode Register Programming 57 4 8 Flash Memory Projected Performance Figures 59 4 9 L2 Cache 2 e ies as Siw ieee ee woes ea wae ee es 64 4 10 BCSRO Description ic wa eae dd 68 4 11 BCSRTJDeSCHDLUOR osos S x DES SOS EY E UR 69 4 12 BCSR2 Description ea 71 4 13 FLASH Presence Detect 7 5 Encoding 12 4 14 FLASH Presence Detect 4 1 Encoding 72 4 15 EXTOOLI 0 3 Assignment 72 4 16 PQ2 Board Version Encoding oss deve IA XR VRAT Wed RE gr ed 73 4 17 PQ2 Board Revision Encoding 73 4 18 External Tool Revision Encoding EN 73 4 19 L2 Cache Size Encoding 222222222522 ed 73 4 21 PCI Board Present Signal Definitions 74 4 20 BC SRA Descript
108. 47 PCI Interrupt from PCI card Reset Logic Pins PORIn 23 power on reset input 25 hard reset input SoftReset_B PIN 24 soft reset input 158 MPC8266ADS PCI User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information Reset configuration support PIN 61 Transfer Error Acknowledge Chassis Power On Pins ChasisPowerIn B PIN 15 Chassis Power Switch PowerOn B PIN 16 istype reg tinvert Power Supply Power On Global OE for ICT Pin OE PIN 14 global for ICT purposes PCI Interrupt Register 2 8k P kok Rokok Slot0IntA NODE istype reg buffer PCI Slot 0 Interrupt A SlotOIntB NODE istype reg buffer PCI Slot 0 Interrupt SlotOIntC NODE istype eg buffer PCI Slot 0 Interrupt C SlotOIntD NODE istype reg buffer PCI Slot 0 Interrupt D SlotlIntA NODE istype reg buffer PCI Slot 1 Interrupt SlotlIntB NODE istype reg buffer PCI Slot 1 Interrupt B SlotlIntC NODE istype reg buffer PCI Slot 1 Interrupt C SlotlIntD NODE istyp
109. 5 00 209 Suu exa o IXH 100 y o SH yr xr 20 1 XL 20 1 Su 89 25104 Zr ua 2510 Suu 8 200589 Sr ald E anot ve cessviow 819 79 560 0697 10 N N N 3101 2 42 20 40 5 900 SH rus amp voa Turgu xu 59 15190 5 u 190 2 SH vz ed rsr IGXI SH zl ua LZ 1510 SHU VI er 5 10 ano 5 815 68869101 9 INJ 1607 10 N N anot gz 79 23 anor 42 012 20 For Information This Product s Go to www freescale com 02 Jo 21 19945 1002 22 Jeque oN A epsen SNMOQ Sdn 104 v jueuinooq 9219 enu v pum ys rexueus 15 Jojonpuoorules iconductor Inc B 8 escale Sem j Ur XOL Fr 2 enor 008 a VA 193981 5 4 0 094921 9 0 04021 94021 lt gt 5 12 922 1591219 0259 bs KS
110. 6 2 10 System Expansion Connector 102 6 24 o eX AP LE una p l UE s 102 Section 7 Support Information 74 Interconnect signals Y ae 103 7 1 1 1 5232 ports 1 and 2 Connectors 103 7 1 2 P2 100 10 Base T Ethernet port Connector 104 143 COP s oap SEE PERDE ash a 104 7 1 4 P4 Expansion Connector 105 7 1 5 P5 P6 P11 P13 P14 P16 P18 P19 Logic Analyzer Connectors 112 7 1 6 P7 P8 P9 PCI Connectors 113 7 1 7 P12 ATX Power Supply Connector 115 7 18 15 Mach Lat ce ISP Connector 115 7 1 9 17 System Expansion 116 7 2 Programmable Logic 122 Weal Code Gergen Sees e Ee REFERRE GO eR ER 122 7 2 U10 PCI Interrupt Controller Code 157 7 2 3 U23 SDRAM MUX LATCH High 179 7 2 4 U22 SDRAM MUX LATCH LOW 183 7 3 Schematics and Bill Of Materials 188
111. 604 OONHI3I 0189 5 4 0 0109 Ted zg 1 wa 202 Suu 2184 029 ZOXYNLY 2104 SS 104 Elad ED Elad 149 Suu vlad ore 3094996 1 5104 9189 SQXHWLV 1093005 9104 5 9189 SQXHWLV ED A1dXIW1V 2104 1184 ZOXYNLY SLE TIO 1 4 5 4 8109 MNOXHHI34 ol 2 610d 0204 IQXSH133 TH SOXLWLV 0209 orm opn ooe 1804 ord 2294 o 42 OOXIHIS4 ore or 2204 5 8204 ole 0 3 ZOXLIALV 8004 Es 204 20 1 33 LOXIWIV 5 T 5 EOX1Hl33 8604 Sq 9204 1 4 5 4 ole VOHWLV 2810 Suu 14 1204 ol Sse DOSHNLV 2 axl Su yg 8204 14 N3XSWLVu 247 SH 6204 N3XIH133 5 4 8 1810 Suu zT 0208 27 AOXBHI33 zg N SH 1204 10 TH NSXINLVU 2 T SH EE ard 2 V Ta pe uyta awqan X RH C MOTOROLA MPC8266ADS PCI User s Manual For More Information On This Product 206 Go to www fre
112. 8 2 L2Caeh a BE 7 doe tated tme Qi eene PG BUS qum ex em da Ae sbs L2 CACHE Support Ren ex RUD eed 4 4 11 1 L2 Cache Configuration amp POS Cu mots Lec BS LM IUE ea ai 42222 2 Rt lee Sat wu uta ete f ele dre 2 122 1006 T PORE 55 T in SR e 4 122 1 LXT970 Control iso tian REDE AES oad Rad MOTOROLA MPC8266ADS PCI User Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table of Contents 4 12 5 RS232 poA eg AI UV et rs 66 4 12 3 1 RS 232 Ports Signal Description 67 4 13 Board Control amp Status Register 67 4 13 1 BCSRO Board Control Status Register O 68 4 13 2 BCSRI Board Control Status Register 69 4 13 3 BCSR2 Board Control Status Register 2 70 4 13 4 BCSR4 Board Control Status Register 4 74 4 13 5 BCSR3 and BCSR5 Board Control Status Regi
113. 9 istype reg D buffer 10 istype reg D buffer istype reg D buffer col MOTOROLA MPC8266ADS PCI User s Manual For More Information On This Product Go to www freescale com 181 Freescale Semiconductor Inc Support Information LA20 NODE istype reg D buffer H L X Z 1 0 X Z C D U C D U SIMULATION 1 Signal groups 2k 2k Add A6 A11 A20 LAdd LA6 LA11 LA20 RowAddNormal LA8 LA10 LA11 RowAddPBI 16 LA7 LA9 LA10 not really required RowAddPBI 64M LA6 LA8 LA9 ColAddNormal LA8 LA10 LA20 16M LA7 LA9 LA20 not really required ColAddPBI 64M LA6 LA8 LA20 SdramAdd SdramA11 SdramA9 SdramA8 ROW 1 COL ROW SIZE 16M 0 SIZE_64M 1 SDRAM 16M DimmSize SIZE 16M SDRAM 64M ISDRAM 16M SDRAM NORMAL MODE PBI 0 SDRAM PBI MODE SDRAM NORMAL MuxCont PBI DimmSize Equations state diagrams 182 MPC8266ADS PCI User s Manual For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Support Information Input Latch
114. Active if WRITE IntMaskReg SlotOIntBMask DATA BIT pin SlotOIntBMask Active Hard Reset SlotOIntBMask DEFAULT SlotOIntBMask Active Hard Reset SlotOIntBMask PON DEFAULT SlotOIntBMask Active then Slot0IntB Mask_ Active else SlotOIntBMask Active state Slot0IntBMask_ Active if WRITE IntMaskReg SlotOIntBMask DATA BIT pin SlotOIntBMask Active amp Hard Reset SlotOIntBMask PON DEFAULT SlotOIntBMask Active Hard Reset amp SlotOIntBMask PON DEFAULT SlotOIntBMask Active then SlotOIntBMask Active else Slot0IntB Mask_ Active state diagram Slot0IntCMask state SlotOIntCMask Active if WRITE IntMaskReg SlotOIntCMask DATA BIT pin SlotOIntCMask Active Hard Reset 810001 DEFAULT SlotOIntCMask Active Hard Reset SlotOIntCMask PON DEFAULT SlotOIntCMask Active then ISlotOIntCMask Active else SlotOIntCMask Active state SlotOoIntCMask Active if WRITE IntMaskReg SlotOIntCMask DATA BIT pin SlotOIntCMask Active amp 172 MPC8266ADS PCI User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information Hard Reset SlotOIntCMask PON DEFAULT SlotOIntCMask Active Hard Reset amp SlotOIntCMask PON
115. B RS232Enl1 RS232En2 B JtagEn fb ReadBcsr0 PBI ReadBesr1 bcsrConfEn 128 DimmsSize L2Inh B L2Flush B L2Lock B 2 B SignaLampO B SignaLampl B boot device B AtmEn B AtmRst B fb FEthEn B MPC8266ADS PCI User s Manual For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Support Information FEthRst RS232Enl RS232En2 B ReadBesr3 0 DrivenContReg PBI DimmSize L2Inh_B L2Flush_B L2Lock_B L2Clear_B SignaLampO B SignaLampl B AtmEn B FEthEn B RS232En1_B RS232En2_B ClockedContReg PBI DimmSize L2Inh B L2Flush B L2Lock B L2Clear B SignaLampO B SignaLampl B AtmEn B AtmRst B FEthEn B FEthRst B RS232Enl RS232En2 B MOTOROLA MPC8266ADS PCI User s Manual 129 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information JtagEn Bcsr0 PBI for simulation DimmsSize L2Inh B L2Flush B L2Lock B L2Clear B SignaLampO SignaLampl B Besr1 bcsrConfEn for simulation boot device B AtmEn B B FEthEn B FEthRst B RS232Enl1 B RS232En2 B JtagEn for simulation ToolCs ToolCs1 B ToolCs2 B FlashCsOut FlashCs4 B FlashCs3 B FlashCs2 B FlashCsl Reset HardReset B SoftReset B ResetEn HardResetEn SoftRese
116. DEFAULT SlotOIntCMask Active then SlotOIntCMask Active else SlotOIntCMask Active state diagram Slot0IntDMask state SlotOIntDMask Active if WRITE IntMaskReg SlotOIntDMask DATA BIT pin SlotOIntDMask Active amp Hard Reset 5100110 PON DEFAULT SlotOIntDMask Active Hard Reset amp SlotOIntDMask PON DEFAULT Slot0IntDMask_Active then ISlotOIntDMask Active else SlotOIntDMask Active state SlotOoIntDMask Active if WRITE IntMaskReg SlotOIntDMask DATA BIT pin SlotOIntDMask Active 4 Hard Reset SlotOIntDMask PON DEFAULT SlotOIntDMask Active Hard Reset SlotOIntDMask PON DEFAULT SlotOIntDMask Active then SlotOIntDMask Active else SlotOIntDMask Active 1 2 EO 2 CO state diagram SlotlIntAMask state Slot IntAMask_ Active if VGR_WRITE_IntMaskReg SlotlIntAMask DATA BIT pin Slot1IntAMask_Active amp Hard_Reset Slot1 IntAMask_PON_DEFAULT Slot1IntAMask Active Hard Reset amp SlotlIIntAMask PON DEFAULT Slot1IntAMask Active then SlotlIntAMask Active else SlotlIntAMask Active state SlotlIntAMask Active if WRITE IntMaskReg SlotlIntAMask DATA BIT pin SlotlIntAMask Active 4 MOTOROLA MPC8266ADS PCI User s Manu
117. Divide MPTPR output by 34 PSRT 1 Generates refresh every 13 4 usec while 16 psec required Therefore is refresh redundancy of 5 4 msec throughout full SDRAM refresh cycle which completes in 27 4 msec Le Application s w may withhold the bus upto app 5 4 msec in a 32 8 msec period without jeopardizing the contents of the ppc bus SDRAM DIMM LSRT No SDRAM on Local Bus which is used for Bus ONLY MPTPR All SDRAMs on board 1900 Divide Bus clock by 26 MPTPR 1 decimal 96 MPC8266ADS PCI User s Manual For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Memory Map and Initialization a Although this BSMA value corresponds to A 17 19 on BKSEL 0 2 when PBI is set only the rele vant BKSEL lines according to number of internal SDARM banks are VALID in this case BKSEL2 b Although this BSMA value corresponds to A 15 17 on BKSEL 0 2 when PBI is set only the rele vant BKSEL lines according to number of internal SDARM banks are VALID in this case BKSEL 1 2 MOTOROLA MPC8266ADS PCI User s Manual 97 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Physical Properties 6 1 6 Physical Properties Power Supply The board gets the power from the ATX Power Supply it seats in an ATX Chassis All the power rails on the board are derived from the ATX Power Supp
118. ED 5 2 m 01104 34 22 1 Sr TH TT Olvdax3 Th 2ASH100L 5 YN 6200 4 1 1 1 1 STgSqX3u ol ore 0A341001 T I orm 5 4 opns LIVISL emm Szddvdx ord Oro ore 919181 lt on 2 Z1d9dX3u 59 18 144 58 19151 veddvdxa 1SuW1vVu 01d9dX3u N3W1Vu 17151 zzaavdxa n 0197 1 ors ZIVISL 5 4 I ofa TEEVEN 2 250100187 2 151 5 000 9 O3Mdx3u 15010018 OLVISL o 8100543 1 20 lt gt Liaavaxa o1 or V 2 V cr ect sedent hs te copre agn a erste P ar cef dit 1 T 1 2 M I 821 219 9 0 821 21919 0 821 CN e 004 TET Tod TET Wd SON ol 254 ol 2 TEN 52 204 529 Vd 5 vod 784 Wd Bev Y d 1 Sad S d 5 4 924 e 98d Wd 9 904 104 184 5 9 See Ad 5 104 olx 80d 889 E 809 68d ted
119. FLASH when it is assigned to CSO and the other to the E7PROM when it is assigned to CSO The two configurations are detailed in Table 3 3 and Table 3 4 respectively Table 3 3 BCSR FLASH Power On Reset Configuration Flash Init Address Value hex Description hex 0 0C 1 Internal arbitration Internal memory controller Core enabled Single MPC8266 60X Bus mode 32 Bit boot port size Exceptions vectored to OxFFFxxxxx Internal space 64 bit slave for external master 8 B2 L2cache signals configured as BADDRx lines DP 1 7 configured as L2 cache and IRQ 6 7 Initial internal space OxOF000000 10 36 Boot memory space OxFE000000 OxFFFFFFFF 2 pin is ABB DBB IRQ3 pin is DBB No masking on bus request lines Local bus pins function as PCI PCI is boot master AP 1 3 configured as BNKSEL 0 2 APE configured as IRQ7 and CS11 as CS11 18 60 510 configured as BCTL1 PCI autoload from FLASH Programmed into the Flash E7PROM memory in addresses 0x0 0x8 0x10 amp 0x18 b With L2 Cache Table 3 4 2 Power On Reset Configuration EEPROM Init Address Value hex Description hex 0 04 149 Internal arbitration Internal memory controller Core enabled Single MPC8266 60X Bus mode 8 Bit Boot size Exceptions vectored to OxFFFxxxxx Internal space 64 bit slave for external master 8 B2 L2cache signals configur
120. More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information SlotOIntD fb SlotlIntA fb Slot1IntB fb Slot1IntC fb Slot1IntD fb 502 Slot2IntB fb Slot2IntC fb Slot2IntD fb PCI Interrupt Register definitions SlotOIntA Active 1 PCI Slot 0 Interrupt A asserted SlotOIntB Active 1 PCI Slot 0 Interrupt B asserted SlotOIntC Active 1 PCI Slot 0 Interrupt C asserted SlotOIntD Active 1 PCI Slot 0 Interrupt D asserted SlotlIntA Active 1 PCI Slot 1 Interrupt A asserted Slot1IntB Active 1 PCI Slot 1 Interrupt B asserted SlotlIntC Active 1 PCI Slot 1 Interrupt C asserted SlotlIntD Active 1 PCI Slot 1 Interrupt D asserted Slot2IntA Active 1 PCI Slot 2 Interrupt A asserted Slot2IntB Active 1 PCI Slot 2 Interrupt B asserted Slot2IntC Active 1 PCI Slot 2 Interrupt C asserted Slot2IntD Active 1 PCI Slot 2 Interrupt D asserted Power On Defaults Assignments SlotOIntA_PON_DEFAULT SlotOIntA Active SlotOIntB PON DEFAULT SlotOIntB Active SlotOIntC PON DEFAULT SlotOIntC Active 5100110 PON DEFAULT SlotOIntD Active SlotlInt PON DEFAULT SlotlIntA Active SlotlIntB PON DEFAULT Slot1IntB Active SlotlI
121. PM5350 RC U6 1 64 Pin_PQFP IC ETHERNET TRANS LEVEL ONE LXT970QC AQC CEIVER MOTOROLA MPC8266ADS PCI User s Manual 213 For More Information This Product Go to www freescale com Freescale Semiconductor Inc Support Information Table 7 9 MPC8266ADS PCI Bill Of Materials Reference Qty Footprint Description Manufacturer Part Number Note U7 U20 U26 U27 4 TSSOP IC 8BIT BUFFER MOTOROLA MC74LCX541DT U8 U11 U24 U31 U32 U33 6 14P TSSOP SMD IC 4BIT BUFFER MOTOROLA MC74LCX125DT U9 1 SOT 23 5 IC VOLTAGE DETEC SEIKO S 80828ANMP EDR TOR 2 010 1 48 64 32 CPLD VANTIS 4 64 32 7 48 012 1 TBGA480 IC CPU MOTOROLA MPC8266 1 TBGA480 480 Pin Socket E TECH BPW480 1265 29BA01H U13 U34 U38 3 TSSOP48 IC 16BIT BUFFER MOTOROLA MC74LCX16244DT U14 1 100PIN_TQFP IC 128 64 CPLD VANTIS M4 128 64 7VC 015 017 2 32 _ IC LOW SKEW MOTOROLA MPC947FA BUFFER U16 1 TO220 IC 3V3 REGULATOR MICREL MIC29500 3 3BT U35 U18 2 241 Pin PBGA IC 2 MOTOROLA MPC2605ZP66 L2Cache U19 1 SO20W IC 8BIT BUFFER ON SEMICONDUCTOR 74ACT541DW U21 1 D2PAK_936 IC 3V3 REGULATOR ON SEMICONDUCTOR LM317D2T U23 U22 2 48 Pin TQFP IC 64 32 CPLD VANTIS M4 64 32 7V C48 L2Cache U25 1 55 48 16 TRANCEIVER SEMICONDUCTOR MC74LCX16245DT U28 1 DIMM 168 PIN IC MEMORY FUJITSU SPDC2UV6482C 100 5 1 DIMM 168 PIN 168PIN D
122. Reset Rstl PIN 19 connected to N O of Reset HardReset_B PIN 16 istype com Actual hard reset output O D SoftReset B PIN 29 istype Actual soft reset output O D PIN 18 connected to of Abort Abr PIN 17 connected to N O of Abort NMIEn NODE istype com enables 5 NMI pin 124 MPC8266ADS PCI User s Manual For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Support Information NMI B PIN 41 istype com Actual NMI pin O O D Data Buffers Enables and Reset configuration support kk kk k k PIN 61 Transfer Error Acknowledge PCIIntContCs B PIN 85 PCI Interrupt Controller Chip Select input DataBufEn B PIN 9 istype com invert data buffer enable ToolCs1 B PIN 30 comm tool cs line 1 ToolCs2 B PIN 91 comm tool cs line 2 ToolDataBufEn B PIN 6 istype com invert tool data buffer enable Hard Reset Configuration Logic boot device B PIN 10 selects EEPROM FLASH_B as boot device bcsrConfEn PIN 66 selects Hard Reset Configuration Source as BCSR or EEPROM FLASH Logic JtagEn NODE istype reg buffer Tdi PIN 56 Tdo NODE istype
123. Semiconductor Inc Support Information Table 7 8 P17 System Expansion Connector Pin No Signal Name Attribute Description C12 IRQ7 I Interrupt Request 7 L Connected to MPC8266 s DP7 CSE1 IRQ7 signal Pulled up on the ADS with a 10 resistor This line is shared with the Fast Ethernet transceiver s interrupt line and therefore when driven by an external tool MUST be driven with an Open Drain gate Failure to do so might result in permanent damage to the MPC8266 and or to ADS logic C13 GND O Digital Ground Connected to main GND plane of the ADS C14 EXPD0 T S Expansion Data 08 15 This is a double buffered version of the PPC bus D 0 15 lines controlled by on board logic These lines will be 5 EXPDI driven only if BTOOLCS1 or BTOOLCS2 are asserted Otherwise they are tristated 1 2 Els The direction of these lines is determined by buffered BCTLO in C17 EXPD3 function of W R C18 EXPD4 C19 5 C20 EXPD6 C21 EXPD7 C22 EXPD8 C23 EXPD9 C24 EXPD10 C25 EXPD11 C26 EXPD12 C27 EXPD13 C28 EXPD14 C29 EXPD15 C30 N C Not Connected C31 C32 DI GND O Digital Ground Connected to main GND plane of the ADS D2 D3 D4 EXPWE0 O Expansion Write Enable 0 1 L These are buffered GPCM Write Enable lines 0 1 They are meant to qualify writes to GPCM controlled D5
124. Semiconductor Inc Support Information equations DataOe READ BCSR 09 VGR READ BCSR 1 Gifdef READ JTAG DOWNLOAD DATA READ JTAG DOWNLOAD CSR HRESET IN BCSR amp 50 ASSERTED amp DSyncHardReset_B fb Data oe DataOe fb when READ BCSR 0 then Data ReadBcsrO else when VGR READ BCSR 1 then Data ReadBcsr1 ifdef else when READ_JTAG_DOWNLOAD_DATA then Data JtagShiftDR fb else when READ JTAG DOWNLOAD CSR then Data JtagC S Reg else when FIRST CFG BYTE READ then Data CfgByte0 else when SCND BYTE READ then Data CfgBytel else when THIRD CFG BYTE READ then Data CfgByte2 else when BYTE READ then Data CfgByte3 brd_ctl Reset Logic k k k kk kk k k equations Reset oe ResetEn Reset 0 open drain MOTOROLA MPC8266ADS PCI User s Manual 147 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information RstDeb1 Rstl amp RstDebl com amp Rst0 Reset push button debouncer AbrDebl amp AbrDebl com amp Abr0 Abort push button debouncer HardResetEn RstDeb1 com amp AbrDebl com both buttons are depressed So
125. T 797 9 1049 104 Sere Div 390T19du 10 dd 18811044 TH SEU Dip 1049 6d v Dir dO1S 249 AGHI Odu 6 Zebu Die INVA 1040 4401 1 avort sut 2001 3801 108 989 9815 489 194 ze10 vero sro 1910 sero erro 9910 c ASTOd LOTS 124 For More Information This Product s Go to www freescale com 02 P Sk 19509 1002 Ze oed Z SHOLOSNNOO 1u tunoog 9219 SW IOdzOd amu Tavusi VTOHO LOMNW 15 151 2 gt gt gt aoj amp m 5 Ls LS 22 amyl NH 619 A 09 20 Sio 89 H 1 I 19d iod a o 8241 Zdl 2241 68H Dir 2115 1248 068 Dir i 1049 168 Div LIND 1044 o 66H Di 3504 269 Dir gt 00 1949 Inm Dir 0039 1049 19d 6 9241 5241 9 9 A 089 4 1881 1040 i ESH Div WoL 199 198 Div 7 101 194 2
126. Tag c Acc poza 838 0 1048 b va 104 227 ano lav 299 TV GINI 1980 T ua HE Zdv 124 DINI 20 194 20 108 qe 8607 lod od 699 VINI foelav belay LES 201 124 080 15d TOY Dozer 19d maar ose Dit 1049 ano Perg 1244 OI 104 ZINS 1049 TW 9 I AAT T 101199 5 9 STV 1Su 78 910104 F SWE 108 1587097 wap STW S am E 199 ddl 191 H 991 p mere os PIS oF pora TO OldL PoMesed LINSHd Deer L Ast beg SIND 301NI SINT 041 Sc INI M Sg Tg g 3901 avor 401 104 S OQ ve d SNL 104 59 Wd 1581 1049 T TH 10d 1 64 TZINSHd 199 i ZLINSHd 194 1 ano SUA AMP LLINSHd 104 4 1 Z01NSUd 194 AS 10d xo V ND 101884 124 uot 340 avor 1 auo 3007 4401 suit 300 3901 3401 A Dd 980 sero 185 A 10d sero mpm ASTOd 2 LOIS T z T T 5 For More Information This Pro
127. UNI transceiver the PM5350 is enabled for communication When it is dark the ATM UNI transceiver is disconnected from the 8266 enabling the use of its associated pins off board via the expansion connectors ON led is controlled by BCSRI 3 2 29 Fast Ethernet Port Initially Enabled LD14 When the yellow ETH ON led is lit it indicates that the fast ethernet port transceiver the LXT970 is initially active When it is dark it indicates that the LXT970 is initially in power down mode enabling the use of its associated FCC2 pins off board via the expansion connectors MOTOROLA MPC8266ADS PCI User s Manual 25 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Operating Instructions The state of LD14 15 controlled by BCSRI This is a soft indication i e since the LXT970 may be controlled via the MII port it is possible that the state of LD14 does not reflect correctly the status of the LXT970 Note Application S W should always seek to match the state of LD14 to the status of the LXT970 so that this indication is made reliable as to the correct status of the LXT970 3 2 30 RS232 Port 1 ON LD15 When the yellow RS232 Port 1 ON led is lit it designates that the RS232 transceiver connected to upper DB9 connector is active and communication via that medium is allowed When darkened it designates that the transceiver is in shutdown mode and it
128. VDDL Level Range 9 2 3 2 Setting VDDL Supply Voltage Level 9 2 3 3 Setting MODCK 1 3 for PLLs Multiplication Factor SW4 6 8 10 2 3 4 Setting Hard Reset Configuration Source 11 239 Setting Boot 5 ua igs See ee n A T 12 2 3 6 Setting MODCKH 0 3 for PLLs Multiplication Factors 13 2 37 Setting PCI MODCK for PCI Bus 13 2 3 8 Setting PCI ARBITER for PCI Mode Enabled 13 2 3 9 Setting PCI DLL for PCI Mode Enabled 13 2 3 10 MPC8260 JTAG s TDI Source Selection 13 2 3 11 SDRAM DIMM Slave Address Selection SW2 14 2 3 12 Setting ATX Chassis AC Power 15 2 4 Installati n InsttuCtioHs he Raed en REPE IE SE 16 2 4 1 Host Controlled Operation 16 2 42 Stand Alone Operation sx eek aka 16 2 53 0 Copnnectors s oie een tees asal 17 2 4 4 Terminal to MPC8266ADS PCI RS 232 Connection 17 2 4 5 10 100 Base T Ethernet Port Connection 18 216 Mem
129. X 08001808 OoooocooooooocooooooooooQooooooQgoOQ0wmwN HH3S 2422 0 Bde 01 06 VIENH Er 3M auod 1040 CE OOOOOm asic 1044 SIMU WOG GIENH Y 5 1nodisxo 4015 1940 9 CONS MEUS 0 94 INS WH 5 WOO zu zeg Samoaa HVd Iod PLV1 LET ERE NOQ 5 Soo USEANOGISIM 1 T mE GEH 7 Ser 0189 x 0155 660 6591 850 157914471 801 EENH 5 eza 1 150 1 FEM 2310001 2521000 9 829 565 OO 044 o 18910018 EENH 233 SONIVU VEENH 1 7500 n ZS Wudsu 2 9 823 559 Tm A 82 23 155 LOY na 2 3 0 00000 ai par um 1NI 1081 o TMU SM m 1M 00000 110 IWN _ LIH 21 22
130. definitions JTAG_ENABLED 1 STATE JTAG ENABLED JtagEn fb JTAG ENABLED Power On Defaults Assignments JTAG ENABLE PON DEFAULT JTAG_ENABLED eng compatible Data Bits Assignments JTAG ENABLE DATA Flash Declarations FLASH ENABLE ACTIVE 0 the presence detect encoding for the below is fictional needs to be updated with real data 29020 PD 8 1 X 2MByte bank SM73228XU1 2 1 X 8 MByte bank SM73248XU2 F_PD 1 2 X 8 MByte banks SM73288XU4 0 4 8 MByte banks FLASH_BANKI CP29020 SM73228XU1 SM73248XU2 amp A8 ft SM73288XU4 amp A7 amp A8 FLASH BANK2 SM73248XU2 amp A8 5 73288 04 amp A7 amp 8 134 MPC8266ADS PCI User s Manual For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Support Information FLASH BANK3 7 amp A8 amp 5 73288 04 FLASH BANKA A7 amp amp SM73288XUA UNI Declarations kk k k k k k kk kk k k Reset Declarations
131. for a CS region is 32KBytes and only A 27 29 lines are decoded by the BCSR for register selection BCSRO BCSR7 are duplicated inside that region The following functions are controlled monitored by the BCSR PBI 60x Bus mode only L2 Cache Inhibit L2 Cache Flush L2 Cache Lock L2 Cache tag Clear UU es MOTOROLA MPC8266ADS PCI User s Manual 67 For More Information On This Product Go to www freescale com Functional Description Freescale Semiconductor Inc 6 ATM Port Control which includes Transceiver Enable Disable Transceiver Reset Fast Ethernet Port Control which includes Transceiver Initial Enable Transceiver Reset RS232 port 1 Enable Disable RS232 port 2 Enable Disable Flash Size Delay Identification CSO assignment after hard Reset to FLASH SIMM E PROM External off board tools Support which include 10 11 12 13 14 15 16 17 Since of the MPC8266 MBs modules are controlled by the BCSR and since they disabled in favor of external hardware the enable signals for these modules are presented at the Tool Identification Tool Revision Tool Status Information S W Option Identification Board revision code Fast download via JTAG optional Power on Reset via JTAG optional PCI cards Present Detect and card type CPM expansion connectors so that off board hardware may be mutually exclusive enabled with on board modul
132. in permanent damage to the MPC8266 and or to board logic 12 GND Digital GND Main GND plane 13 HRESET MPC8266 s Hard Reset L When asserted by an external H W generates Hard Reset sequence for the MPC8266 During that sequence asserted by the for 512 system clocks Pulled Up on the MPC8266 MB using a 1 resistor When driven by an external tool MUST be driven with an Open Drain gate Failure in doing so might result in permanent damage to the MPC8266 and or to board logic N C Not Connected MOTOROLA MPC8266ADS PCI User s Manual 77 For More Information This Product Go to www freescale com Functional Description Freescale Semiconductor Inc Table 4 25 COP JTAG Port Signals Description Pin No Signal Name Attribute Description 15 XBR3 y o Normally configured as XBR3 which has no function with this CKSTOP OUT connector May be configured as CKSTOP OUT Check Stop Out L When asserted Low indicates that the MPC8266 core has entered a Check Stop state 16 GND O Digital GND Main GND plane 4 14 1 Fast Download Support Download rates through the COP port are inherently slow due to very long COP scan chains and the extraneous amount of data transferred In essence an additional to MPC8266 s JTAG machine was added in front of the MPC8266 s JTAG port This machine supports the minimal public set of JTAG
133. is disabled this line may be used for any available function of PB29 C4 FETHRXER PB28 T S Fast Ethernet Receive Error H When this signal is asserted High by the LXT970 while the Ethernet port is enabled and FETHRXCK goes high it indicates that the port is receiving invalid data symbols from the network When the Ethernet port is disabled this line is tristated and may be used for any available function of PB28 C5 FETHCOL PB27 T S Fast Ethernet Port Collision Detected H When this signal is asserted High by the LXT970 while the ethernet port is enabled it indicates a Collision state over the line When the LXT970 is in Full Duplex mode this line is inactive When the Ethernet port is disabled this line is tristated and may be used for any available function of the PB27 MOTOROLA MPC8266ADS PCI User s Manual 109 For More Information On This Product Go to www freescale com Support Information Freescale Semiconductor Inc Table 7 4 P4 CPM Expansion Connector Pin No Signal Name Attribute Description C6 FETHCRS PB26 I O T S Fast Ethernet Carrier Sense H When this signal is asserted High while the Ethernet port is enabled and the LXT970 is in half duplex mode it indicates that either the transmit or receive media are non idle When the LXT970 is in either full duplex or repeater operation i
134. machine defaults to asynchronous connection between TDI input of this machine and the MPC8266 s TDI with a 7 5 nsec delay This allows compatibility with existing debug tools which have not been modified yet to support this machine and can tolerate this delay on the TDI line 3 JTAG Bypass After Power On reset or JTAG reset when this JTAG machine is enabled via BCSR6 and the jumper is set between positions 1 2 factory set it will be found in Bypass mode i e the default instruction of the machine is BYPASS so that when the TAP controller is moved into Shift DR state a single stage shift register is placed between the TDI input of the ADS and the TDI input of the MPC8266 4 14 1 8 Fast Download Operation This section describes the procedure needed to be taken by a debug station programmer so that this machine may be utilized It is assumed here that the jumper remains factory set 1 2 and the board is after Power On reset and initialized The procedure is as follows 1 Enable this JTAG machine by writing 1 to the JTAG bit in BCSR6 The machine is now enabled and in JTAG Bypass mode See Table 4 23 Remember that prior to this oper ation the length of the instruction chain is 8 bit 8266 only while the data scan chain s length depended only on the scan selected within the MPC8266 After this opera tion the length of the instruction chain is 11 bits added 3 bits for this machine preceding MPC8266 s in th
135. reg buffer clocked by falling Tck TdoOut PIN 82 istype com Tck PIN 14 Tms PIN 47 Trst_B PIN 46 PonResetOut PIN 68 istype com active high Auxiliary Pins System Hard Reset Configuration DataOeNODE istype data bus output enable read MOTOROLA MPC8266ADS PCI User s Manual For More Information On This Product Go to www freescale com 125 Freescale Semiconductor Inc Support Information Control Register Enable Protection Reset amp Interrupt Logic Pins C RstDeb1NODE istype keep com reset push button debouncer AbrDeb1NODE istype keep com abort push button debouncer HardResetEnNODE istype com enables T S hard reset pin SoftResetEnNODE istype com enables T S soft reset pin data buffers enable SyncHardReset NODE istype reg buffer synchronized hard reset DSyncHardReset NODE istype reg buffer double synchronized hard reset HoldOffCnt2 HoldOffCntl HoldOffCnt0 NODE istype reg buffer data buf en hold off counter HoldOffIc istype com terminal count for that counter
136. sampled are don t care The PCI MODCK signal which is sampled concurrently with the PCI MODCK 0 3 pins determines the PCI bus clock frequency see Section 2 3 7 When set high it divides the PCI bus frequency by two When reset low the PCI bus frequency is as determined by the MODCK 1 3 and PCI MODCKH 0 3 signals 4 1 2 Reset Hard Reset may be generated on the ADS by the following sources 1 COP JTAG Port 2 Manual Hard reset 3 MPC8266 s internal sources Hard Reset when generated causes the MPC8266 to reset all its internal hardware except for PLL logic re acquires the Hard reset configuration from its current source and jumps to the Reset vector in the exception table Since hard reset resets also the refresh logic for dynamic RAMS their content is lost as well HRESET when asserted is extended internally by the MPC8266 for additional 512 bus clock cycles at the end of which the 8266 waits for 16 bus clock cycles and then re checks the state of the HRESET line HRESET is an open drain signal and must be driven with an open drain gate by which ever external source is driving it Otherwise contention will occur over that line which might cause permanent damage to either board logic and or to the 8266 itself 4 1 2 1 COP JTAG Port Hard Reset To provide convenient hard reset capability for a COP JTAG controller HRESET line appears at the COP JTAG port connector The COP JTAG controller may
137. the addressing scheme matches a 16 MByte DIMM while when High the addressing scheme matches a 64 MBytes DIMM In Single MPC8266 Mode i e without L2 Cache this bit has no effect PON DEF ATT L2C_INH L2 Cache Inhibit When this bit is active low the L2 cache is inhibited and unable to respond to cacheable cycles However bus activity is still monitored by the cache so that it may respond immediately after this signal is negated This signal is connected to the MPC2605 s L2 UPDATE INH This signal has no function in a MPC8266 MB that does not have an L2 Cache installed RW 12 FLUSH L2 Cache Flush When this bit is active low for min 8 bus cycles the MPC2605 initiates a process within which valid lines are marked invalid while dirty lines are written back to memory and marked invalid This signal is connected to the L2 FLUSH signal of the MPC2605 This signal has no function in a MPC8266 MB that does not have an L2 Cache installed RW L2C LOCK L2 Cache Lock When this bit is active low the MPC2605 will stop entering new data into the cache while yet maintaining existing data and responding to cacheable cycles This signal has no function in a MPC8266 MB that does not have an L2 Cache installed RW L2C CLEAR L2 Cache Clear When this bit is active Low for min 8 bus clock cycles the L2 cache invalidates all its entries without flushing the same process as with HRESET asserted How
138. to number of internal SDARM banks are VALID in this case BKSEL 1 2 38 MPC8266ADS PCI User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Functional Description 4 Functional Description In this chapter the various modules combining the MPC8266ADS PCI are described to their design details 4 1 Reset amp Reset Configuration There are several reset sources on the MPC8266 MB 1 Power On Reset 2 Manual Hard Reset 3 Manual Soft Reset 4 PCI bus reset 5 MPC8266 Internal Sources See also the VOYAGER U M 4 1 1 Power On Reset The power on reset to the MPC8266 initializes the processor state after power up A dedicated logic using Seiko S 80728AN DR T1 which is a voltage detector of 2 8V 2 4 asserts PORESET input to the MPC8266 for a period of 2 5sec This time period is long enough to cover also the VDDL stabilization powered by a different voltage regulator It is assumed that the stabilization time for both linear regulators see also Section 6 1 Power Supply are about the same Power On Reset may be generated manually as well by an on board dedicated push button S1 or by the ATX chassis RESET button Power On Reset can also be generated by the JTAG logic which is integrated with BCSR 4 1 1 1 Power On Reset Configuration At the end of Power On reset sequence MODCK 1 3 are sampled by the MPC8266 to configure the various cloc
139. z O IRQ lt gt lt lt k gt Interrupt Figure 4 9 PCI Bus Scheme The clock source for the 8266 is Main Clock 66MHz clock oscillator The PCI Clock is derived internally from the Main Clock and output at DLLOUT That clock is then distributed to each PCI device on the bus in a way that they are all synchronized by keeping all clock traces the same length The PCI Clock is also fed back to the MPC8266 for synchronization and skew elimination purposes An interrupt from any PCI slot is handled by a simple generic Interrupt Controller Each slot can generate up to four interrupts for a total of twelve interrupts that the controller will support It will be made of two register mapped in a dedicated CS region One is an Interrupt Register see Table 4 3 and the second is Interrupt Mask Register see Table 4 4 A simple priority scheme will be devised TBD to allow the controller to support more than one interrupt concurrently 4 11 L2 CACHE Support To enhance benchmarking optional support is provided for L2 Cache Use is done with two MOTOROLA MPC8266ADS PCI User s Manual 63 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Functional Description 2605 devices each containing 256K Bytes of look aside cache along with its control providing a total of 512KByte L2 cache The cache is connect
140. 00 RPP repre ugxu Dade PEN BEAN VPENH MPC8266ADS PCI User s Manual For More Information On This Product 190 Go to www freescale com Support Information Freescale Semiconductor Inc D z T Y 5 02 J z 1002 72 Wepsen eig W3lSAS tV wewnoog SW IOdzOd Tavusl 02199 w h 18 jexueug au AL 230001 39001 rezu 090 1 8710 09 99 52 Sio sid Sio 160498 5 1609 Siaava E 81009 vo vid vid viddV SELXOWL 6200 8 ai 2d 52 6200 e ez 100 lt 32009 1001 9 010 22007 05 28 aren seqava 9zaav 0raava fe 8d Ls 82001 T sa 600 80 80 80
141. 04720000 Empty Space 64 KByte 0472FFFF 04730000 PCI Interrupt 32 32 KByte 04737FFF Controller MOTOROLA MPC8266ADS PCI User s Manual 27 For More Information On This Product Go to www freescale com Operating Instructions Freescale Semiconductor Inc Table 3 1 MPC8266ADS PCI Memory Map FLASH or BCSR as Boot Device Address Memory Device Range Type Size Size 04738000 Empty Space 800 KByte 047FFFFF 04800000 PCI Memory Agents PIMMR via PCI Direct 8 MByte 04FFFFFF 05000000 Empty Space Tool Board is located at 60000000 and 70000000 2 GByte 7FFFFFFF 80000000 PCI Memory PCI Agents GPL WIndows 32 1 Gbyte BFFFFFFF C0000000 Empty Space 32 MByte C1FFFFFF 2000000 ATMEL AT28HC64B 8 32 KByte C2007FFF C2008000 Empty Space 1 GByte FDFFFFFF 000000 Flash SIMM 32M SIMM 32 32 MByte FEFFFFFF 5 73288 FF000000 16M SIMM FF7FFFFF SM73248 FF800000 8M SIMM FFFFFFFF SM73228 a The device appears repeatedly in multiples of its port size in bytes X depth E g BCSRO appear at memory locations 4700000 4700020 4700040 while BCSR1 appears at 4700004 4700024 4700044 and so on b The internal space of the ATM UNI control port is 256 bytes however the minimal block size tha may be controlled by the GPCM is 32 KBytes
142. 08000 Empty Space 1 MByte 045FFFFF 04600000 ATM UNI Proc PMC5350 M P I F 8 32 KByte 04607FFF Control 04608000 Empty Space 1 MByte 046 047000009 MPC8266 32 128 KByte 0471FFFF Internal MAP 04720000 Empty Space 64 KByte 0472FFFF 04730000 PCI Interrupt 32 32 KByte 04737FFF Controller 04738000 Empty Space 800 KByte 047FFFFF 04800000 PCI Memory Agents PIMMR via PCI Direct 8 MByte O4FFFFFF 05000000 Empty Space Tool Board is located at 60000000 and 70000000 2 GByte 7FFFFFFF 29 MPC8266ADS PCI User s Manual MOTOROLA Operating Instructions Freescale Semiconductor Inc Table 3 2 MPC8266ADS PCI Memory Map E PROM as Boot Device Address Range 80000000 BFFFFFFF Memory Type PCI Memory Device Name PCI Agents GPL WIndows Port Size 32 Memory Size 1 Gbyte C1FFFFFF C0000000 Empty Space 32 MByte C2FFFFFF C2000000 C37FFFFF 3000000 C3800000 Flash SIMM 8M SIMM SM73228 16M SIMM SM73248 32M SIMM SM73288 32 32 MByte C4000000 Empty Space 1 GByte FFFFDFFF FFF00000 FFFFFFFF E2PROM ATMEL AT28HC64B 8 32 KByte a The device appears repeatedly in multiples of its port size in bytes X depth E g BCSR0 appears at memory locations 4700000 4700020 4700040 while BCSR1 appears at 4700004 4700024
143. 1 interrupt is masked 50 MPC8266ADS PCI User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Functional Description Table 4 4 PCI Interrupt Mask Register Description BIT MNEMONIC Function DEF 10 MPCI2_INTC Mask PCI Slot 2 INTC Mask PCI Slot 2 Interrupt C 0 R W 0 interrupt is available 1 interrupt is masked 11 MPCI2_INTD Mask PCI Slot 2 INTD Mask PCI Slot 2 Interrupt D 0 R W 0 interrupt is available 1 interrupt is masked 12 31 Reserved Un implemented R W 4 3 Clock Generator There are two main clock circuits on board 1 MPC8266 System Clock 2 PCI Clock 4 3 1 MPC8266 Clock The MPC8266 requires a single clock source as the main clock source All MPC8266 60x bus timings are referenced to the main clock input CLKINI unlike the 8xx family timings of which are referenced to CLKOUT signal The main clock input is in 1 1 ratio to the bus clock with internal skew elimination PLL Use is done with 66MHz 3 3V clock generator X2 which is connected to a low inter skew buffer U17 to split the load between all various clock consumers on both boards Special care is taken to isolate and terminate the clock route between the on board PLL and the 8266 this to provide a clean clock input for proper operation The main clock scheme is shown in Figure 4 3
144. 10 RS11 10Kohm RS12 RS13 RS15 RS16 RS17 RS18 RS19 RS20 RS21 RS22 RS23 RS24 RS25 RS26 RS27 RS28 MOTOROLA MPC8266ADS PCI User s Manual 211 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information Table 7 9 MPC8266ADS PCI Bill Of Materials Reference Qty Footprint Description Manufacturer Part Number Note RS14 1 10P 8R RES NET 10P 8R ROHM RS8A1002J L2Cache 10Kohm R1 R2 R3 R38 R39 R40 R48 10 603 RES ROEDERSTEIN D1151R1FCS R49 R63 R64 R41 R4 2 603 RES 75ohm DRALORIK D11075RFCS R5 R6 R46 R47 R67 5 1206 RES 2R7ohm ROEDERSTEIN D2502R7FCS R7 1 603 RES 51R10hm ROEDERSTEIN D1151R1FCS R8 R9 R11 R13 R14 R15 49 603 RES 4K7ohm ROEDERSTEIN D1104K7FCS R17 R18 R19 R50 R52 R53 R56 R57 R61 R62 R69 R70 R72 R75 R80 R83 R84 R89 R90 R91 R92 R97 R98 R99 R100 R101 R120 R122 R124 R125 R127 R128 R129 R130 R135 R136 R137 R152 R168 R173 R174 R246 R247 R10 R82 2 603 RES 4K7ohm ROEDERSTEIN D1104K7FCS Optional R12 1 1206 RES 100 ROEDERSTEIN D25100RFCS R16 R22 R55 R139 R140 24 603 RES 1Kohm DRALORIK D11001KFCS R142 R144 R147 R151 R154 R155 R156 R158 R160 R167 R170 R178 R181 R216 R217 R234 R235 R236 R237 R20 R60 R68 R74 R115 24 603 RES 43R2ohm ROEDERSTEIN D1143R2FCS R141 R143 R145 R146 R148 R179 R183 R184 R185 R190 R191 R193 R194 R196 R197 R198 R200 R202 R208 R21 1 1206 RES 2K2ohm ROEDERSTEIN D2502K2FCS R119
145. 1000000 03FFFFFF 04000000 Empty Space 5 MByte 044FFFFF 86 MPC8266ADS PCI User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Memory Map and Initialization Table 5 1 MPC8266ADS PCI Memory Map FLASH or BCSR as Boot Device Address Memory Port Memory Device Name Size Size 04500000 BcsR 0 7 a 32 32 KByte 04507FFF 04500000 BCSRO 4 Byte 04507FE3 04500004 BCSRI 4 Byte 04507FE7 04500008 BCSR2 4 Byte 04507FEB 0450000 BCSR3 4 Byte 04507FEF 04500010 BCSR4 4 Byte 04507FF3 04500014 BCSR5 4 Byte 04507FF7 04500018 BCSR6 4 Byte 04507FFB 0450001 BCSR7 4 Byte 04507FFF 04508000 Empty Space 1 MByte 045FFFFF 04600000 UNI Proc PMC5350 I F 8 32 KByte 04607FFF Contro 04608000 Empty Space 1 MByte 046FFFFF 04700000 MPC8266 32 128 KByte 0471FFFF Internal MAP 04720000 Empty Space 64 KByte 0472FFFF 04730000 PCI Interrupt 32 32 KByte 04737FFF Controller 04738000 Empty Space 800 KByte 047FFFFF 04800000 PCI Memory Agents PIMMR via PCI Direct 8 MByte 05000000 Empty Space Tool Board is located at 60000000 70000000 2 GByte 7FFFFFFF 80000000 PCI Memory PCI Agents GPL WIndows 32 1 Gbyte BFFFFFFF MOTOROLA MPC8266ADS PCI User s Manual 87
146. 2289 sz552 59 06999 8255 5 quo quo in 4 i 3900 3900 T AS HINPY GL 629 suze 9928 suze 59 3401 DID gry lt lt 99u 1 260 T nono SON g MONLY uz SON m I Sd SON SOA Mb 34001 0 1 on ao poo puo fero Zoro Te do foro SOA i z gt 5 to www freescale com MPC8266ADS PCI User s Manual For More Information On This Product 198 199 Support Information Freescale Semiconductor Inc MPC8266ADS PCI User s Manual For More Information On This Product Go to www freescale com z p s 02 10 jesus 1002 12 eg pna 13Nu3HldlSV4 u 8H9dz0d 02199 15 24948 151 in 3101 1 3nor 807 S897 T
147. 266 MB Chip Select Assignments Select Assignment Bus Machine 50 Flash SIMM E PROM 60X Buffered GPCM CS1 BCSR 60X Buffered GPCM CS2 SDRAM DIMM single bank 60X Main SDRAM Machine 1 only CS3 SDRAM DIMM 60X Main SDRAM Machine 1 54 E2PROM Flash SIMM 60X Buffered CS5 UNI Microprocessor 60X Main GPCM CS6 Communication Tool M P 60X Buffered GPCM UPMx Interface CS1 CS7 Communication Tool M P 60X Buffered GPCM UPMx Interface CS2 CS8 PCI Interrupt Controller 60 Buffered GPCM CS 9 11 Unused user available a Selection is done by a dip switch b For two banks SDRAM DIMMs 4 7 Synchronous Dram DIMM 60 Bus To enhance performance especially in higher operation frequencies 16 MBytes of SDRAM DIMM is provided on board The SDRAM DIMM is unbuffered from the MPC8266 60X bus and is configured as 2 X X 64 Use is done with SDC2UV6482C 84T S unbuffered 168 pin DIMM by Fyjitsu or compatibles which is composed of eight 2 X 1M X 8 sdram chips 81117822 84 The DIMM s data sheet may be obtained on the Internet at URL Attp 4 After the BCSR is removed from the local memory map there is no way to access it but to re apply power to the MPC8266ADS PCI 1 When an unbuffered CS region is being accessed buffers do not open anyway 2 During read cycles 54 MPC8266ADS PCI User s Manual MOTOROLA For More Information On This Pro
148. 3 and 1 Provided that BCSR is not disabled 74 MPC8266ADS PCI User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Functional Description BCSRS is shown in Table 4 22 Table 4 22 BCSR3 and BCSR5 Description 0 81 MNEMONIC Reserved Function Un Implemented PON DEF ATT 4 13 6 BCSR6 Board Control Status Register 6 BCSR 6 is used for the Fast Download I F Status Control Although it resides only over D 0 7 lines of the PPC data bus it is accessed as a word at offset 0x18 from BCSR base For additional information on that I F see 4 14 1 Fast Download Support on page 78 The description of BCSR6 is shown in Table 4 23 Table 4 23 BCSR6 Description BIT MNEMONIC Function PON DEF ATT JTAG EN JTAG Enable When this bit is active High the JTAG machine for fast download is enabled for use When inactive TDI is asynchronously driven to MTDO In this mode Power On default COP controller S W may operate on the ADS in ENG revision compatible mode R W Reserved Implemented Read 07000000 Writes have no effect JTAG_RX_FULL JTAG Receive Full Flag When this signal is active High it indicates that the JTAG Download register was fully written by the Host and should be read by the download agent running on the ADS After the agent has read data fr
149. 400 34008 3400 35001 8 157 1870 8610 69 01 1257 BLD 26 0 OSI 66 07 2410 Bard 68 01 2122 2810 T 4 onn oada goy OIGGA Hry 5 Hory Tug Hy Hepy 99780dW Siaan Hegy 5 5 MPC8266ADS PCI User s Manual For More Information On This Product 202 Go to www freescale com Freescale Semiconductor Inc Support Information Z P 1894 1002 72 1 emq L SYOLOANNOO 104
150. 4700044 and so on b The internal space of the ATM UNI control port is 256 bytes however the minimal block size that may be controlled by the GPCM is 32 KBytes Initially at 102000000 hOFOOFFFF set by hard reset configuration d Refer to the 8266 User s Manual for complete description of the MPC8266 s internal memory map e An 8 Kbyte device is used 16 Kbyte and 32 Kbyte devices can also be used so it appears repeatedly in 8Kbyte multiples starting from 00000 3 4 8266 Register Programming The MPC8266 provides the following functions on the MPC8266ADS PCI 1 System functions which include PPC Bus SDRAM Controller Local Bus Host to PCI Bridge Chip Select generator 2 Communication functions which include e ATM SAR Fast Ethernet controller UART for terminal or host computer connection The internal registers of the MPC8266 must be programmed after Hard reset as described in the following paragraphs The addresses and programming values are in Hexadecimal base 30 MPC8266ADS PCI User s Manual For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Operating Instructions For more information on the following initializations see the MPC8266 User s Manual 3 4 1 System Initializations The Power On Reset Configuration word is set in the BCSR or FLASH or in the E PROM There are two configuration words one for the BCSR and
151. 5 NODE istype reg D buffer 16 NODE istype reg D buffer LA17 NODE istype reg D buffer 18 NODE istype reg D buffer 19 istype reg D buffer col LA21 NODE istype reg D buffer LA22 NODE istype reg D buffer LA23 NODE istype reg D buffer LA24 NODE istype reg D buffer LA25 NODE istype reg D buffer LA26 NODE istype reg D buffer LA27 NODE istype reg D buffer LA28 NODE istype reg D buffer H L X Z 1 0 X 27 C D U C D U SIMULATION 1 Signal groups 186 MPC8266ADS PCI User s Manual For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Support Information Add A10 A19 A21 A28 LAdd LA10 LA19 LA21 LA28 RowAddNormal LA12 LA19 RowAddPBI 16M LA11 LA18 RowAddPBI 64M LA10 LA17 ColAdd LA21 LA28 SdramAdd SdramA7 SdramA0O ROW 1 COL ROW SIZE 16 0 SIZE_64M 1 SDRAM_16M DimmSize SIZE_16M SDRAM_64M SDRAM_16M SDRAM NORMAL MODE PBI 0 SDRAM PBI MODE SDRAM NORMAL MuxCont PBI DimmSize k k k k k kk k k k k Equations state diagrams Input Latch
152. 7 lines the lower 3 on MODCK 1 3 and the upper four MODCKH 0 3 field read from the Hard Reset configuration source when the PCI is disabled to establish the multiplication factors of the CPM s and Core s PLLs The levels on MODCK 1 3 lines are set using SW4 switches 6 8 When an individual switch is at the OFF position its associated MODCK line is pulled high 1 while when at the ON position the associated MODCK is pulled down 0 SW4 is shown in Figure 2 4 while the various combinations for SW4 6 8 and their associated MODCK 1 3 values are shown in Table 2 1 1 May be either boot FLASH or EEPROM on the ADS 10 MPC8266ADS PCI User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Hardware Preparation and Installation MODCKHO MODCKHO MODCKHI MODCKHI MODCKH2 MODCKH2 MODCKH3 MODCKH3 PCI MODCK PCI MODCK MODCKI MODCKI MODCK2 MODCK2 MODCK3 MODCK3 Sw4 66MHz Bus and 66MHz PCI Bus Factory Set Figure 2 4 SW4 Description Table 2 1 MODCK 1 3 Encoding Lee ix 2 3 4 Setting Hard Reset Configuration Source JP3 The Boot sequence which starts when HRESET is asserted may be from two sources 1 BCSR default Hard Reset Configuration Word CS0 is assumed to be assigned to the FLASH 2 Memories FLASH EEPROM user contr
153. 8 GND O Digital GND Main GND plane 9 N C Not Connected 10 N C Not Connected 7 1 9 P17 System Expansion Connector P17 is a 128 pin 909 DIN 41612 connector which provides a minimal system I F required to interface various types of communication transceivers This connector contains 16 bit lower PPC bus address lines 16 bit higher PPC bus Data lines plus useful GPCM and UPM control lines The pinout of P17 is shown in Table 7 8 116 MPC8266ADS PCI User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information Table 7 8 P17 System Expansion Connector Pin No Signal Name Attribute Description 1 16 O Expansion Address 16 31 This is a Latched Buffered version of the 8266 PPC Address lines 16 31 provided for external tool A2 17 connection avoid reflection these lines series terminated with 43 18 resistors 4 19 5 20 6 21 7 22 8 23 9 24 10 25 26 12 27 A13 EXPA28 14 29 15 0 16 1 17 2 These can connected to positive 12 source from PCI edge s connector thru J3 This line is fused by a 0 5A ressetable poly switch
154. 8266ADS PCI User s Manual 61 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Functional Description unlock a different unique sequence has to be written E PROM Socket DATA 0 7 I O 7 0 ADDRESS 17 31 BCSR mE POE gt 50 E PROM AED gt WE gt cs CS CS4 Figure 4 8 Connection scheme Additional address lines are connected to the socket according to the JEDEC format as an option to use up to 32 KByte To allow proper operation with the L2 Cache the 8266 needs to be set to 60X bus mode in which the address bus for the 2 is latched 4 10 Bus The MPC8266 has a PCI module which enables it to act as an Host Master or a Target On this board the 8266 serves only as a PCI host a bridge between the PCI Bus and the PowerPC core The PQ2 PCI Bridge is designed to connect the PowerPC processor and memory system to the PCI system bus to which I O components are connected The PCI Bridge enables the MPC8266 to gluelessly bridge PCI masters and agents to a PowerPC system host It uses a 32 bit multiplexed address data bus that can run from 25MHz up to 66MHz The interface provides address and data parity with error checking and reporting It also provides three physical address spaces 32 bit address memory 32 bit address I O and the PCI configurat
155. 97 198 199 200 201 C202 C203 C204 C205 C206 C207 C208 C209 C210 C211 212 213 214 215 216 217 218 219 220 224 225 226 230 232 233 247 248 250 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 136 603 100 0603YC104KAT2A C49 C55 C221 C222 C227 228 229 234 235 236 237 239 240 241 242 243 244 245 251 252 20 603 100 0603YC104KAT2A C51 CASE C CAP 100uF 16V AVX TAJD107K016R C95 C109 C128 1206 CAP 22pF AVX 12065A220JAT00J 210 MPC8266ADS PCI User s Manual For More Information On This Product Go to www freescale com MOTOROLA Table 7 9 MPC8266ADS PCI Bill Of Materials Freescale Semiconductor Inc Support Information Reference Qty Footprint Description Manufacturer Part Number Note C171 1 1206 CAP 1500pF AVX 12065A152JAT00J C193 1 CASE A 1uF 25V SIEMENS B45196H5105K109 238 246 249 3 603 10 AVX 06035C103KAT2A Optional D1 D2 D3 3 SMD DIODE TSC LL4004G JP1 JP2 JP3 JP5 JP11 5 HEADER 3Px1ROW MOLEX 87156 0303 JP4 JP6 2 100mi
156. 989 9015 1940 BEN oN PES 0 9 Pzeg 3SA3G geyd 4 1949 y y 238 0 1040 9409 ogy 194 amp aviod TE 20 194 10907 153 25 Fasal g 39 Kao PREP cav 199 29 194 8201 108 6104 28 7 TAY LEE 20 194 104 104 Wd Tou bos Sd ano 048 iodu oo T Sd su ano 159 9d gur prg KIA O zpowosou ZLNSHd pra 2114989 104 841 gy 4 tp ER 199 Odu nm VINI GINI 1941 F L 1 s Ha aL 101 194 Y 78 SAL 108 Y TH lt 974 na E xui lt gt 1581 1547 Tv A 390 2 5001 Uu avor 3uoif 49011 9810 689 sero mio 1 4 Od LOIS
157. Active if WRITE IntMaskReg Slot1lIntCMask DATA BIT pin Slot1IntCMask Active amp 174 MPC8266ADS PCI User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information Hard Reset Slot1IntCMask PON DEFAULT Slot1IntCMask Active Hard Reset amp Slot IntCMask PON DEFAULT Slot1IntCMask Active then SlotlIntCMask Active else ISlot1IntCMask Active state diagram 51001110 state SlotlIntDMask Active if WRITE IntMaskReg Slot1IIntDMask BIT pin Slot1IntDMask Active amp Hard Reset 51001110 PON DEFAULT Slot1IntDMask Active Hard Reset amp 5100110 PON DEFAULT Slot1IntDMask Active then Slotl IntDMask_Active else Slot1lIntDMask_ lt Active state SlotlIntDMask_Active if VGR_WRITE_IntMaskReg Slot1lIntDMask DATA BIT pin Slot1IntDMask_Active 4 Hard Reset Slot1IntDMask_PON_DEFAULT Slot1IntDMask Active Hard Reset amp Slotl1IntDMask_PON_DEFAULT SlotlIntDMask_Active then Slot1IntDMask_Active else SlotlIntDMask_Active 1 state diagram Slot2IntAMask state Slot2IntAMask_ Active if WRITE IntMaskReg Slot2
158. B include the following 1 Since HRESET and SRESET lines appear at the COP JTAG connector it is possible to generate Hard Reset and Soft Reset directly Power On reset however may be remote generated only through JTAG 84 MPC8266ADS PCI User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Functional Description Power On Reset push button Soft Reset push button Abort push button Three dip switches for Wake up clock mode setting Three dip switches for S W options Three dip switches for SDRAM DIMM Configuration Memory Slave Address A dip switch for selecting the source of the default Power On Reset configuration word and PCI configuration Flash or E PROM Since most of the board s logic is controlled BCSR and it is not visible whether a module is enabled or disabled each module has a visible enable indicator The following indicators are available on the MPC8266 MB 1 5V Power 3 3V Power SDRAM 60X Bus enabled Flash memory enabled BCSR On Map Run led ATM Port Enabled Transmit Receive 8 Ethernet Port Enabled Speed Collision Link Integrity Receive Transmit 9 RS232 Port 1 enabled 10 RS232 Port 2 enabled Se abeo MPC8266ADS PCI User s Manual 85 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Memory and Initialization
159. DATA D2 SlotOIntDMask DATA 03 SlotlIntAMask DATA D4 SlotlIntBMask DATA D5 SlotlIntCMask DATA D6 SlotlIntDMask DATA D7 Slot2IntAMask DATA 08 Slot2IntBMask DATA D9 SloIntCMask DATA D10 Slot2IntDMask DATA D11 Reset Declarations HARD RESET 0 Hard Reset HardReset B HARD RESET ACTIVE SOFT RESET ACTIVE 0 Soft Reset SoftReset SOFT RESET ACTIVE MPC8266ADS PCI User s Manual 165 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information ATX Power Declarations PowerOn 0 PowerOff 1 Equations state diagrams equations PCI Interrupt Register equations IntReg clk SYSCLK IntReg ar PON_RESET IntReg ap 0 state diagram SlotOIntA state SlotOIntA Active if Reset amp SlotOInt PON DEFAULT SlotOIntA Active Reset amp PCI INTA B then ISlotOIntA Active else SlotOIntA Active state S
160. EIN D25330RJCS R110 R113 R114 R121 R123 R126 R131 R132 R138 R149 R211 R212 R255 R85 1 1206 RES 2 2 ROEDERSTEIN D2502M2FCS R88 R87 2 1206 RES 270 DRALORIK D25270RFCS R95 R104 R109 3 1206 RES 1Kohm DRALORIK D25CRCW1206 R118 R107 2 1206 RES 1Kohm DRALORIK D25001KFCS R112 R116 R117 3 1206 RES 20 DRALORIK D25020RFCS R134 R206 2 1206 RES 10 ROEDERSTEIN D25010RFCS R159 R162 R177 R180 R186 10 603 RES 22R10hm ROEDERSTEIN D1122R1FCS R187 R222 R223 R228 R230 R164 1 603 RES 10Kohm ROEDERSTEIN D11010KFCS Optional R165 1 603 RES 1Kohm DRALORIK D11001KFCS Optional R175 1 1206 RES 47Kohm ROEDERSTEIN D25047KFCS R176 1 1206 RES O0R5ohm ROEDERSTEIN D250R50FCS R189 R188 2 603 RES 36R5ohm ROEDERSTEIN D1136R5FCS R203 R209 2 603 RES 10Kohm ROEDERSTEIN D11010KFCS L2Cache R207 1 1206 RES ROEDERSTEIN D2505K6FCS Optional R219 1 1206 RES DRALORIK D25 03KJ S Optional R233 R232 2 603 RES 1Kohm DRALORIK D11001KFCS L2Cache R243 R244 R245 R249 R250 8 1206 RES 1K5ohm ROEDERSTEIN D2501K5FCS R251 R252 R253 SW1 SW2 SW3 3 8PIN SMD SWITCH DIP 4 GRAYHIL 90HBWO4SR SW4 1 16PIN SMD SWITCH DIP 8 GRAYHIL 90HBWO08S 1 1 KS12 PUSHBUTTON SPDT C amp K KS12 R23 CQE 52 1 12 PUSHBUTTON SPDT C amp K KS12 R21 CQE S3 1 KS12 PUSHBUTTON SPDT C amp K KS12 R22 CQE U1 1 9P_TH IC FIBER TRANS HP HFBR 5205 CEIVER U2 1 16P_SMT 16 ETHERNET HALO TG22 3506ND MAGNETICS U3 U4 2 SSOP IC RS232 TRANS MOTOROLA MC145583VFEL CEIVER U5 1 128 Pin_PQFP ATM PHY PMC SIERA
161. ENS 61107 RE anor 0 9 19H 0 919 80 5099 idi 05 TH Poser TOXOV 1044 59 oolav 599 517154 00 5 958 104 AE 194 ey booy SSH tv 103 2 8 104 15097 300 558 124 104 TEV 9 759 1 G Faye solae 558 2104 QNO 4 RED 609104 600 w N399W org o 3401 40 piov 104 Tay 104 ons 28 10 104 6 0 6815 20 10 E98 vH Wray 154 E UM Sav 104 0380 T 19870 1049 o Di Vd 104 wuuas 2 Pera 1 1049 2085 1049 m P INOS 104 001 OE 1049 e A Dd 7 901 3001 1949 Dr ZINS 1097 4015 1047 asada T 06H Dir i 2038 1089 5 4 neer i HSASG 1549 1 16H Dir LINO 1041 idu 66H Div t i o 269 OINO 1089 5 4 768 Dir 219 1049 ioa heet DES T 238 O 1090 1 0034 1244 864 n 9 6 E568 0019 D 1049 194 10 104 EV lleilav 104 807 199 TV icy e AE Dd oz TEV ay Oe 9241 6841 199 RS 2009 ano Hav tod sa dao pee L EN
162. FFFF 04800000 PCI Memory Agents PIMMR via PCI Direct 8 MByte 04FFFFFF 05000000 Empty Space Tool Board is located at 60000000 and 70000000 2 GByte 7FFFFFFF 80000000 PCI Memory PCI Agents GPL WIndows 32 1 Gbyte BFFFFFFF MOTOROLA MPC8266ADS PCI User s Manual 89 Memory and Initialization Freescale Semiconductor Inc Table 5 2 MPC8266ADS PCI Memory Map E PROM as Boot Device Address Range C1FFFFFF C0000000 Memory Type Empty Space Device Name Port Size Memory Size 32 MByte C2FFFFFF C2000000 C37FFFFF C3000000 C3800000 Flash SIMM 16M SIMM SM73248 8M SIMM SM73228 32M SIMM SM73288 32 32 MByte FFFFDFFF 4000000 Empty Space 1 GByte FFFFFFFF 00000 ATMEL AT28HC64B 32 KByte a The device appears repeatedly in multiples of its port size in bytes X depth E g BCSRO appears at memory locations 4700000 4700020 4700040 while BCSR1 appears at 4700004 4700024 4700044 and so on b The internal space of the ATM UNI control port is 256 bytes however the minimal block size that may be controlled by the GPCM is 32 KBytes c Initially at 0 000000 hOFOOFFFF set by hard reset configuration d Refer to the MPC8266 User s Manual for complete description of the MPC8266 s internal memory map e An 8 Kbyte device is u
163. Freescale Semiconductor Inc 12 17 01 Rev 0 1 WITH MPC8266ADS PCI User s Manual Board Rev PROTOTYPE B Omer Digital DNA For Information On This Product Go to www freescale com Freescale Semiconductor Inc Motorola reserves the right to make changes without further notice to any products herein Motorola makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Motorola assume any liability arising out of the application or use of any prod uct or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Motorola does not convey any license under its patent rights nor the rights of others Motor ola products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall inde
164. Freescale Semiconductor Inc Support Information Ale B PIN 5 AleIn PIN 209 AleOut B PIN 27istype com inverted AleIn connected externaly to Ale B RCB PIN 33 DimmSize 37 25 Address Input lines row 10 34 15 12 PIN 2 13 PIN 3 14 9 15 10 16 PIN 1 17 PIN 12 18 35 19 PIN 36 col A21 PIN 38 A22 PIN 39 A23 PIN 40 A24 PIN 44 A25 PIN 45 A26 PIN 46 A27 PIN 47 A28 PIN 48 Address Output lines SdramA0 PIN 13istype SdramA1 PIN 14 istype SdramA2 PIN 15 SdramA3 PIN 16istype MOTOROLA MPC8266ADS PCI User s Manual 185 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information 54 4 PIN 20istype SdramA5 PIN 2listype SdramA6 PIN 22istype SdramA7 PIN 23istype Auxiliary Pins LLLI Latched Address lines 10 NODE istype reg D buffer istype reg D buffer 12 istype reg D buffer LA13 NODE istype reg D buffer 14 istype reg D buffer 1
165. HHI3J d d d 1408 3pm Sod 0QXHH133 9 9 9 2204 8 57 90d 0gX1H133 8 8 8 B Am 104 10 50 804 20 3 50 OIQWHL33 52 0 n SHOHISJ 8419 OKENN 18010017 102 133 w ez LOXHINLV 26210014 50 50 H3XHH133 120 2184 6204 98110 rel N3XIHI33 0604 5119 Bx AQXHHI3 9 o3 235 vigd 1604 BE E 8 04 U3XIHI33 9189 s Old 54 x Y Y 9 5 9 5985907 5 0551 z 880 sia 2 sio sia sio oF ra 6 ggyu SI 03751 1295 ubt 19261 DENAU 237151 Sr 12460 8 8 8 8 8 LIL 20 zii y 90 93 8 50 53 em B m Wit 20 EENEN alu vt 20 3 LE I3S3HHu 12420001 100 1353854 35 1SHOdu 207 MPC8266ADS PCI User s Manual For More Information On This Product MOTOROLA Go to www freescale com Freescale Semiconductor Inc Support Information 02 B 6i wg 1002 72 Tepsenp ed i AlddnS weumoog mH 15 jexueus 15 sojonpuoawag
166. High MODULE 26 TITLE Voyager Sdram 2nd Latch This contains 2 nd part of Address latch for Voyager ads sdram MOTOROLA MPC8266ADS PCI User s Manual 179 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information The mux is required only with L2 Cache installed on board Otherwise it is not assembled SdramA 13 8 are connected to voyager s proper address lines Tn this 2 pinout is changed for MAC211SP 7VC Tn this 3 07 13 98 Added SdramA9 which is latched A10 saving another LCX373 Tn this 4 Rev PILOT 02 18 99 Added support for PBI Page Based Interleaving feature added with PQI rev A To provide that support the following were made Added DimmSize input which provides SDRAM dimm size information Only 16Meg reset default and 64Meg DIMMs are supported This signal originates in BCSR Added PBI indication Since actual seeting is done within the POIL it is the system programmer responsibility to set the correct value for this signal in BCSR to ensure proper operation To make room for the above SdramA 9 8 are moved to another device along with A20 Theoutput of this mux is now qualified with the DimmSize a
167. IBUFFER HOLD OFF local data buffers disable data contention protection Since with Voyager hard reset conf is read from flash eeprom during HRESET asserted and since these are all consequitive read cycles and since the cycles following hard reset are also reads boot the hold off state machine may be leftin NO HOLD OFF for HRESET B asserted duration without warrying about contention between flash and data buffers equations HoldOffCnt clk SYSCLK MOTOROLA MPC8266ADS PCI User s Manual 149 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information HoldOffCnt ar 0 HoldOffCnt ap 0 HoldOffTc HoldOffCnt fb 3 when OF FLASH READ END READ amp HoldOffCnt fb 0 HoldOffCnt fb 0 amp HoldOffCnt fb 4 amp DSyncHardReset_B fb then HoldOffCnt HoldOffCnt fb 1 else HoldOffCnt 0 Flash EEPROM Chip Selects equations FlashCsOut oe hf FlashCs1_B CSO_ASSERTED amp FLASH_BANKI amp HRESET BOOT IN FLASH 50 ASSERTED amp FLASH BANKI amp BOOT IN FLASH amp DSyncHardReset CS4 ASSERTED amp FLASH BANKI amp HRESET BOOT EEPROM IN EEPROM FlashCs2 B CSO_ASSERTED amp FLASH BANK2 amp HRESET BOOT IN FLASH 50 A
168. IMM SOCKET AMP 390040 6 U29 1 PLCC 32 IC MEMORY ATMEL AT28HC64B 70JC 1 32PIN PLCC 32PIN PLCC SOCKET AMP 822273 1 U30 1 80PIN SIMM IC MEMORY SMART MODULAR SM73228XG1JHBGO TECHNOLOGIES 1 80PIN SIMM 80PIN SIMM SOCKET AMP 822021 5 U37 U36 2 SSOP48 IC 16BIT LATCH PHILIPS 74ALVT16373DL U40 U39 2 SSOP48 16 TRANS PHILIPS 74ALVT16245DL CEIVER X1 1 4P_TH 19 44 2 5V Clock COMCLOK CM42AH Oscilator 2 1 TH 66MHz 3 3V Clock M TRON M3H16FCD 3V3 Oscilator 66MHz 1 8P_SMD 8P_SMD_Socket PRECIDIP 1109330841105 Y1 1 XTAL SMD CRYSTAL EPSON 505 25MHZ 214 MPC8266ADS PCI User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 8 0JO1O A L 810 e ej 99c82dW 19 SGV 99c82dll Ov 1h SIOJOI 1ez euy 21601 uid x 2 siojo uuoS Dd 10 98UU0D Dd JOMOd UMOQ INd 68654 194194 53 152 e NLY 99Z89dN 21 PU HSV1A SJejng 6 8 2 9
169. ISNVdX3 1u uunoog ev 9209 02199 15 483946 151 Jojonpuootues BOON 1 1 1 quo V E A 821 821 821 1 1 zi O1 O1 1 ia 91 STROS ofre 2 o vu ON SON 0 9150 SLIVOdX3 ops ei 1 TLIVOdX3 o4 1 SLES ELIVOdX3 ol 527 ZLIVOdX3 015 1HIVOdX3 Sea BETA SACO OLIVOdX3 zI GlVOdX3 A SIS 81VddX3 opu aan el Ted zg 210093 oe lt e OT vlVddX3 ofera lt Over ol e TO ol TH I101X3 n I 9 90 Zlvddx3 Ono1x3
170. IV For Information This Product s Go to www freescale com
171. IntAMask DATA BIT pin Slot2IntAMask Active Hard Reset Slot2IntAMask PON DEFAULT Slot2IntAMask Active Hard Reset amp Slot2IntAMask PON DEFAULT Slot2IntAMask Active then ISlot2IntAMask Active else Slot2IntAMask Active state Slot2IntAMask Active if WRITE IntMaskReg Slot2IntAMask DATA BIT pin Slot2IntAMask Active amp MOTOROLA MPC8266ADS PCI User s Manual 175 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information Hard Reset Slot2ZIntAMask PON DEFAULT Slot2IntAMask Active Hard Reset Slot2IntAMask PON DEFAULT Slot2IntAMask_Active then Slot2IntAMask Active else Slot2IntAMask Active 1 ef state diagram Slot2IntBMask state Slot2IntBMask Active if WRITE IntMaskReg Slot2IntBMask DATA BIT pin Slot2IntBMask Active Hard Reset Slot2IntBMask PON DEFAULT Slot2IntBMask_Active Hard Reset amp Slot2IntBMask PON DEFAULT Slot2IntBMask Active then Slot2IntB Mask_ Active else Slot2IntBMask_Active state Slot2IntBMask_ Active if VGR_WRITE_IntMaskReg Slot2IntBMask_DATA_BIT pin Slot2IntBMask_Active amp Hard Reset Slot2IntB Mask_PON_DEFAULT Slot2IntBMask Active Reset amp Slot2IntBMask PON DEFAULT Slot2IntBMask_Active then
172. L 1 2 on 1 7 clocks refresh recovery 3 clocks precharge to activate delay 2 clocks activate to read write delay 4 beat burst length 1 clock last data out to precharge 1 clock write recovery time extra cycle on address phase normal timing for control lines 2 clocks CAS latency LSDMR 0 No SDRAM on Local Bus which is used for PCI Bus ONLY PSRT Bus Supported Sdram PPC 21 Divide MPTPR output by 34 PSRT 1 Generates refresh every 13 4 usec while 16 psec required Therefore is refresh redundancy of 5 4 msec throughout full SDRAM refresh cycle which completes in 27 4 msec Application s w may withhold the bus upto app 5 4 msec in a 32 8 msec period without jeopardizing the contents of the ppc bus SDRAM DIMM LSRT No SDRAM on Local Bus which is used for Bus ONLY MPTPR All SDRAMs on board 1900 Divide Bus clock by 26 MPTPR 1 decimal MOTOROLA MPC8266ADS PCI User s Manual 37 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Operating Instructions a Although this BSMA value corresponds to A 17 19 on BKSEL 0 2 when PBI is set only the rele vant BKSEL lines according to number of internal SDARM banks are VALID in this case BKSEL2 b Although this BSMA value corresponds to A 15 17 on BKSEL 0 2 when PBI is set only the rele vant BKSEL lines according
173. LA For More Information On This Product Go to www freescale com una cxi Freescale Semiconductor Inc Hardware Preparation and Installation CAUTION The memory SIMMs have alignment nibble near their 1 pin It is important to align the memory correctly before it is twisted otherwise damage might be inflicted to both the memory SIMM and its socket 1 2 Flash SIMM Metal Lock Clip E SIMM Socket 1 x SIDE VIEW Figure 2 14 Flash Memory SIMM Insertion 2 4 6 2 SDRAM DIMM Installation The SDRAM DIMM 028 is inserted in different manner The 2 side latches are pulled aside to unlocked position the DIMM is placed in a vertical position similar to its final position between them so that the keys nibbled in the DIMM matches those on the socket and then the DIMM should be pressed evenly and firmly into its place locking the side locks on itself The SDRAM insertion 15 shown in Figure 2 15 MOTOROLA MPC8266ADS PCI User s Manual 19 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Hardware Preparation and Installation TOPSIDE VIEW i 3 D Figure 2 15 SDRAM DIMM Insertion 20 MPC8266ADS PCI User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconducto
174. LAMP ON then ISIGNAL LAMP ON else SIGNAL LAMP ON state SIGNAL LAMP ON if WRITE BCSR 0 amp SIGNAL LAMPO DATA BIT pin SIGNAL LAMP ON amp IPON RESET SIGNAL LAMPO PON DEFAULT SIGNAL LAMP ON t PON RESET amp SIGNAL PON DEFAULT SIGNAL LAMP then SIGNAL LAMP ON else ISIGNAL LAMP ON IC I 28 IC ICO I state diagram SignaLampl B state SIGNAL LAMP ON if WRITE BCSR 0 amp SIGNAL LAMPI DATA SIGNAL LAMP amp IPON RESET SIGNAL LAMPI PON DEFAULT SIGNAL LAMP ON PON RESET amp SIGNAL PON DEFAULT SIGNAL LAMP ON then ISIGNAL LAMP ON else SIGNAL LAMP state SIGNAL LAMP ON if WRITE BCSR 0 amp SIGNAL LAMPI DATA BIT pin SIGNAL LAMP ON amp IPON RESET SIGNAL LAMPI PON DEFAULT SIGNAL LAMP ON t 142 MPC8266ADS PCI User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information PON RESET amp SIGNAL LAMPI PON DEFAULT SIGNAL LAMP ON then SIGNAL LAMP ON else ISIGNAL LAMP ON BCSRI State Machines state diagram AtmEn B state ATM ENABLED if WRITE BCSR 1 amp
175. LL is found cleared Then a byte of valid data may be shifted in 6 Move the TAP to EXITI DR PAUSE DR EXIT2 DR The passage through EXITI DR sets the RX FULL flag in the Download Command amp Status register The agent then can read the valid data from the Download Data register After that data has been read by the agent the JTAG RX FULL is cleared 7 Repeat steps 4 to 6 above until the end of the buffer 4 14 1 9 JTAG Generated Power On Reset Since some of the COP debug stations are Ethernet driven a need may arise to generate Power On Reset from a remote location through the JTAG and to be able to do so when the board is stuck To support such action the PON RESET instruction was introduced When JTAG is enabled in the Download Control amp Status register it is possible to Power On Reset the board through JTAG The way to do it is Move the TAP controller into Shift IR Shift in PON RESET code As a result of the above Power On reset is generated resetting the board including this JTAG machine which goes back into Test Logic Reset state The JTAG bit in the Download Control amp Status register is reset as well Before re initializing the board there is a need to wait about 3 seconds for the board to recover The state of HRESET and SRESET lines of the MPC8266 is visible via the connector 4 15 Switches Jumpers and Indicators The switches and jumpers on the MPC8266 M
176. LLs Core CPM is out of lock hard reset is gen erated 2 Check Stop Reset When the core enters a Check Stop state from some reason hard reset may be generated depended on CSRE bit in the RMR 3 Bus Monitor Reset When the bus monitor is enabled and a bus cycle is not terminated hard reset is generated 4 S W Watch Dog Reset When the S W watch dog is enabled and application s w fails to perform its reset routine it will generate hard reset 5 COP JTAG Reset Internal Hard reset may be forced by driving the HRESET line via the external pin s scan chain Not useful for run time In general the MPC8266 asserts a reset line HARD or SOFT for a period 512 clock cycles after a reset source has been identified A hard reset sequence is followed by a soft reset sequence 4 1 2 4 Hard Reset Configuration When Hard Reset is applied to the MPC8266 externally as well as internally it samples the Hard Reset configuration word This configuration may be taken from an internal default in case RSTCONF is negated during HRESET asserted or taken from the Flash E PROM BCSR MS 8 bits of the data bus in case RSTCONF signal is asserted along with HRESET The default configuration word can be taken from the E PROM BCSR in case the Flash has been tampered with The selection between the BCSR FLASH and the E PROM as the source of the default configuration word is determined by a dedicated dip switch see Section 2 3 5 and a jumper see Se
177. MM Connection Scheme No L2 Cache The SDRAM connection scheme when L2 cache is installed is shown in Figure 4 6 MOTOROLA MPC8266ADS PCI User s Manual 55 For More Information On This Product Go to www freescale com Functional Description Freescale Semiconductor Inc DIMM_SIZE 0 16 1 64M 6 8 7 9 8 10 6 28 9 17 10 18 11 19 20 28 PSDAMUX SDC2UV6482C 84 S2 50 82 SDRAS RAS SDCAS CAS SDWE 3 BANKSEL 1 2 _ 5 4 1 0 2 1 SDRMAII NT 0 PSDAIO y AIO SDRMA9 20 SDRMA 8 0 AGO 2 1 SDDQM 0 7 0 63 026 00 83 CKE CLK 3 6 CLK 1 4 IDCDAT AR xe SDA BCCLK SA 2 0 Serial bip asses Slave Address Setting Switches Figure 4 6 SDRAM DIMM 60x Bus Connection Scheme with L2 Cache The SDRAM performance is shown in Table 4 6 Table 4 6 SDRAM DIMM 84MHz Performance Figures Cycle Type Burst Read Page Miss System Clock Cycles 66MHz Bus Clock Freq System Clock Cycles 66MHz Bus Clock Frequency With 2 6 1 1 1 781511 Burst Read Hit 4 1 1 1 1 1 1 Burst Write Page Miss 481 1 58411 Burst Write Page Hit 28111 1 4841 14 Refresh gb gb 56 MPC8266ADS PCI User s Manual MOTOROLA F
178. MOd v 9215 Tavusl 0219 elzieH 15 ISH Freescale Semiconductor Inc n SOA 104 AS um D 108 19 SNOLLVNOISSG STIVA L ED Andy 999 veo 249 99 1 4801 4401 duOL 920 GEO 860 612 LO 99 LEO 05 toj 920 evo 959 3727 Ly 3727 SHOLIOVdVO 0 HOIH 9 NWA fort NIVW J LHW EHW SHW ZHN HNW o SWIOH ONILNOOW SISVHO XLV 2 SISVHO 1009 4001 4822 A008 3U001 NOLLOSNNOO annou SISVHO NIVW AN ose 2 SISVHO 3 Olaf oji ipw 61 5 O szal 4 9 T sy tts 540 t zi T GSAS 40 99UU0D X
179. N RESET amp PBI PON DEFAULT PBI IN ACTIVB then PBI IN ACTIVE else IPBI IN ACTIVE k kok R Rk state diagram DimmSize state DIMM SIZE 16M MOTOROLA MPC8266ADS PCI User s Manual For More Information On This Product Go to www freescale com 139 Freescale Semiconductor Inc Support Information if WRITE BCSR 0 amp DIMM SIZE DATA BIT pin IDIMM SIZE 16M IPON RESET DIMM SIZE PON DEFAULT DIMM SIZE 16M PON RESET amp DIMM SIZE PON DEFAULT IDIMM SIZE 16M then IDIMM SIZE 16M else DIMM SIZE 16M state DIMM SIZE 16M if WRITE BCSR 0 amp SIZE DATA DIMM SIZE 16M amp IPON RESET DIMM SIZE PON DEFAULT IDIMM SIZE 16M PON RESET amp DIMM SIZE PON DEFAULT DIMM SIZE 16 then DIMM SIZE 16M else IDIMM SIZE 16M 8 R k R state diagram L2Inh B state L2CACHE INHIBITED if WRITE BCSR 0 amp DATA INHIBITED IPON RESET L2CACHE PON DEFAULT L2CACHE INHIBITED PON RESET amp L2CACHE INH PON DEFAULT INHIBITED then IL2CACHE INHIBITED else L2CACHE INHIBITED state INHIBITED if WRITE BCSR 0 amp L2CACHE DATA L2CACHE INHIBITED amp IPON RESET L2CACHE INH PON DEFAULT
180. NTD PCI Slot 1 INTD PCI Slot 1 Interrupt D 0 R 0 no interrupt was requested 1 interrupt was requested and waiting to be handled 8 PCD INTA PCI Slot 2 INTA PCI Slot 2 Interrupt A 0 R 0 no interrupt was requested 1 interrupt was requested and waiting to be handled 9 PCD INTB PCI Slot 2 INTB PCI Slot 2 Interrupt B 0 R 0 no interrupt was requested 1 interrupt was requested and waiting to be handled 10 PCD INTC PCI Slot 2 INTC PCI Slot 2 Interrupt C 0 R 0 no interrupt was requested 1 interrupt was requested and waiting to be handled 11 PCI2_INTD PCI Slot 2 INTD PCI Slot 2 Interrupt D 0 R 0 no interrupt was requested 1 interrupt was requested and waiting to be handled MOTOROLA MPC8266ADS PCI User s Manual 49 For More Information On This Product Go to www freescale com Functional Description Freescale Semiconductor Inc Table 4 3 PCI Interrupt Register Description BIT 12 31 MNEMONIC Reserved Function Un implemented PON DEF ATT R W Also available is an Interrupt Mask Register which provides the user with the option to mask any of the possible PCI interrupt sources It can be read or written at any time and accessed at offset 0x4 from 8 base address The description of the PCI Interrupt Mask Register is in Table 4 4 Table 4 4 PCI Int
181. P When a jumper is located between positions 1 2 of JP11 VPP is drawn from the 12V plane that provides 12 VPP JP11 options are shown in Figure 3 4 KEA Factory Set Figure 3 4 JP10 VPP Source Selection 3 2 15 GND Bridges There 7 GND bridges on the MPC8266ADS PCI These bridges are meant to assist general measurements and logic analyzer connection Warning When connecting to a GND bridge use only IN SULATED GND clips Otherwise un insulated clips may cause short circuits touching HOT points around them Failure in doing so might result in permanent damage to the MPC8266ADS PCI 3 2 16 ATM TX Indicator LD1 The green ATM Receive LED indicator blinks whenever the PM5350 ATM UNI is transmitting cells via the ATM port It illuminates only when the ATM transceiver is enabled via BCSRI 3 2 17 Fast Ethernet Indicator LD2 When the LXT970 is enabled and is in 100 Mbps operation mode the yellow led LD2 lights 3 2 18 Fast Ethernet CLSN Indicator LD3 The red Ethernet Collision LED indicator CLSN lights whenever a collision condition is detected 24 MPC8266ADS PCI User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Operating Instructions on the 10 100 Base T port 1 simultaneous receive and transmit This led functions in this duty provided that bits 7 6 of LXT970 s register 19 are cleared
182. PCI User s Manual For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Support Information state diagram SlotlIntC state SlotlIntC Active if Reset amp SlotlIntC DEFAULT Slot1IntC_Active Hard Reset amp PCI INTB B then ISlotlIntC Active else SlotlIntC Active state Slotl Active if Reset amp SlotlIntC DEFAULT SlotlIntC Active Reset amp INTB B then SlotlIntC Active else ISlotlIntC Active state diagram SlotlIntD state SlotIIntD Active if Reset amp SlotlIntD DEFAULT Slot1IntD_Active Hard Reset amp PCI INTC B then ISlotlIntD Active else SlotlIntD Active state SlotlIntD Active if Reset amp 51001150 DEFAULT SlotlIntD Active Reset B then 51001141 Active else 15101 120 Active state diagram Slot2IntA state Slot2IntA Active if Reset amp Slot2IntA DEFAULT Slot2IntA Active Reset amp PCI INTC B then ISlot2IntA Active else Slot2IntA Active MOTOROLA MPC8266ADS PCI User s Manual For More Information On This Product Go to www freescale com 169 Freescale Semiconductor Inc Support Information state Slot2IntA_ Active if
183. PCI bus frequency is half of what is set by the MODCK lines When switch SW4 5 is at the OFF position its corresponding PCI MODCK line is pulled high 1 enabled while when at the ON position pulled down 0 disabled see Figure 2 4 2 3 8 Setting PCI ARBITER for PCI Mode Enabled The settings of this line determines the operation of the PCI Arbiter When PCI ARBITER is set low the PCI Arbiter in the MPC8266 is enabled When set high the PCI Arbiter is disabled and an external arbiter can be used When switch SW3 2 is at the OFF position its corresponding PCI ARBITER line is pulled high 71 disabled while when at the ON position pulled down 07 enabled see Figure 2 6 2 3 9 Setting DLL for PCI Mode Enabled The settings of this line determines the operation of the DLL for PCI Mode enabled When PCI Mode is enabled the DLL must be enabled When PCI DLL is set low the DLL is disabled When set high the DLL is enabled When switch SW3 3 is at the OFF position its corresponding PCI DLL line is pulled high 71 enabled while when at the ON position pulled down lt 0 disabled see Figure 2 6 2 3 10 MPC8260 JTAG s TDI Source Selection JP1 A new JTAG machine was inserted in front of the MPC8266 s COP JTAG port this to provide fast download capability for the ADS Via it is possible to bypass the new JTAG machine When a jumper is placed between positions 1 2 o
184. R 30 IRQ3 selected BADDR 30 L2 HIT IRGA4 selected as unassigned CPU_BG BADDR 31 IRQ5 as BADDR 31 DPPC 10 11 Data Parity Pin configuration as as EXT BR2 1 EXT BG2 DP2 as EXT DBG2 as EXT DP4 as EXT DP5 as EXT DBG3 DP6 as IRQ6 DP7 as IRQ7 Reserved 12 Reserved ISB 13 15 010 initial value 0 0 000000 i e the internal space resides initially at this address Offset In Flash Hex 8 Value Hex B2 BMS 16 Boot memory Flash at OXFE000000 BBD 17 ABB IRQ2 pin is ABB DBB IRQ3 pin is DBB MMR 18 19 Mask Masters Requests Boot Master is PCI LBPC 20 21 01 Local Bus pins function as PCI bus APPC 22 23 10 MODCK1 AP 1 TC 0 functions as BKSELO MODCK2 AP 2 TC 1 functions as BKSEL1 MODCK3 AP 8 TC 2 functions as BKSEL2 IRQ7 APE functions as IRQ7 CS11 AP 0 functions as CS11 36 CS10PC 24 25 01 CS10 BCTL1 DBG_DIS functions as BCTL1 ALD_EN 26 PCI Auto Load Enable When high PCI Bridge Configuration is done automatically from the FLASH E PROM CPM is configuration master PPC core should be disabled right after the Hard Configuration Word When low the PPC Core should configure the PCI Bridge Reserved 27 Reserved MODCK HIP 28 31 0101 Determines the Core s frequency out of power up reset Co
185. R1 NODE istype JtagShiftIR2 istype reg buffer JtagIRO NODE istype reg buffer Jtag Inst register JtagIR1 NODE istype reg buffer JtagIR2 istype reg buffer JtagReceiveFull istype reg buffer indicates receive shift reg ready for read by memory cont JtagReceiveFullReset NODE istype com resets the receive full flag SReadJtagDownloadData NODE istype reg buffer JtagStateReset NODE istype com jtag state machine only JtagReset NODE istype com global reset TdoEnable NODE istype com enables the muxed TdoOut Misceleneous k k k kk kk k k KeepPinsConnected NODE istype com kkk kK k Equations L X Z 1 0 X Z GDU C D U MPC8266ADS PCI User s Manual For More Information On This Product Go to www freescale com 127 Support Information Freescale Semiconductor Inc SIMULATION 1 Signal groups 1 Add 27 29 Data DO D7 ContReg DimmSize L2Inh_B L2Flush_B L2Lock_B L2Clear_B SignaLampO B SignaLampl B AtmEn B B FEthEn B FEthRst
186. R23 2 1206 RES 150 ROEDERSTEIN D25150RFCS R24 R32 R58 R59 R71 R76 10 603 RES 0ohm ROEDERSTEIN D11000RFCS R111 R150 R153 R213 R25 1 1206 RES 243ohm ROEDERSTEIN D25243RFCS R26 1 Var Res RES VAR 1Kohm BOURNS 3362P 1 102 R27 R28 R30 R108 R133 26 603 RES 10Kohm ROEDERSTEIN D11010KFCS R161 R163 R171 R182 R195 R199 R201 R205 R210 R215 R218 R224 R226 R227 R238 R239 R240 R241 R242 R248 R254 R29 1 1206 RES 110 AVX CR32111J T R31 1 Var Res RES VAR 1Kohm BOURNS 3362P 1 102 Optional R33 R35 2 1206 RES 0ohm ROEDERSTEIN D25000RFCS Optional R34 R36 R37 R204 R214 9 603 RES 0ohm ROEDERSTEIN D11000RFCS R221 R225 R229 R231 R42 R44 R51 3 1206 RES 1330hm DRALORIK D25133RFCS R43 R45 R66 3 1206 RES 82R5ohm DRALORIK D2582R5FCS R54 1 1206 RES 63ohm DRALORIK D2563R4FCS R65 1 1206 RES 22 1 DRALORIK D2522K1FCS 212 MPC8266ADS PCI User s Manual MOTOROLA For More Information On This Product Go to www freescale com Table 7 9 MPC8266ADS PCI Bill Of Materials Freescale Semiconductor Inc Support Information Reference Qty Footprint Description Manufacturer Part Number Note R73 1 1206 RES 1R5ohm ROEDERSTEIN D2501R5FCS R77 R78 R79 R86 R93 R94 13 603 RES 0ohm ROEDERSTEIN D11000RFCS R103 R157 R166 R169 R172 R192 R220 R81 R96 R102 R105 R106 18 1206 RES 330ohm ROEDERST
187. ROM Connection scheme 62 PCIBUs Scheme csse seg xg 63 RS232 Serial Ports Connector 67 Debug Station Connection Schemes 76 COP JTAG Port Connector 76 Fast Download JTAG System 79 JTAG TAP Controller State Diagram 81 MPC8266 MB Power 99 MPC8266ADS PCI User Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc List of Figures X MPC8266ADS PCI User Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 1 General Information 1 1 Introduction This document is an operation guide for the MPC8266ADS PCI board It contains operational functional and general information about the MPC8266ADS PCI This board is meant to serve as platform for s w and h w development around the MPC8266 processor Using its on board resources and a debugger a developer is able to download code run it set breakpoints display memory and registers and connect proprietary h w via the expansion connectors to be incorporated into a desired system with the MPC8266 processor This board could also be used as a demonstration tool 1
188. S 8266 PD 13 4 Port D lines Parallel I O or CPM dedicated lines May be used for any of their available functions A20 PD12 A21 22 PD10 A23 PD9 A24 PD8 A25 PD7 A26 PD6 A27 PD5 A28 PD4 A29 ATMRCLKDIS I ATM Receive Clock Out Disable When active H the ATMRCLK output on pin C29 of this connector is Tri stated When either not connected or driven low ATMRCLK on pin C29 is enabled This provides compatibility with ENG revision of T ECOM communication tools A30 EXPVCC O 5V Supply Connected to ADS s 5 plane Provided as power supply for external tool A31 A32 ATMTXEN PA31 T S Transmit Enabled L When this signal is asserted Low while the ATM port is enabled and ATMTFCLK is rising an octet of data ATMTXD 7 0 is written into the transmit FIFO of the PM5350 When the ATM port is disabled this line may be used for any available function of PA31 B2 ATMTCA PA30 T S ATM Transmit Cell Available H When this signal is asserted High while the ATM port is enabled it indicates that the transmit FIFO of the 5350 is empty and ready to except a new cell When negated it may show either that the transmit FIFO is Full or close to Full depending on 5350 internal programming When the ATM port is disabled this line may be used for any available function of PA30 B3 ATMTSOC PA29 T S ATM Transmit Start Of Cell H When this signal is asserted Hi
189. S OLIVOS IA3871OO1 SE s E lt 0A3H1OOL 81 08 dVOLNOO 310210 EONSe TOOL try 529 7500 99 71 16 go SOrusogu sn 8 11914 SIVISI 20 25 SIVOH lt 0600 odi LEE pu v mmu 11118 917151 Ov 28 5 SIVOH 18010011 yor 5 9 919181 8 v1vag 1_ 4959464 a EERE JjNOOLSHU 1 00 r9 Sid 40 EIVISI za 2012 219161 id 10 21 119151 od 05 Livdg SOA OLVISL 25 gen 4900 44001 49001 T3uoor 40001 lt rra asio sao 690 vero 8910 8 s s 85 8 4900 39001 T3uoor 38001 4900 39001 34001 38001 10014851 gezo ozo zezo 520 erzo 1451 7091451 09 09 s Go www freescale com 02 10 5 19945 1002 J9quie oN 8 HSV13 v Jequinw jueun2oq 925 5 0219 elzieH 15 ISH Freescale Semiconductor Inc 104 2 0 8990 821
190. SCHDLOl s DRE eh 12 JPI DDPSOUSCE Loi Eat EA A 14 S W2 Description za u GC Ras 14 Chassis AC Voltage Settings 15 Host Controlled Operation Scheme 16 Stand Alone Configuration 17 P3 COP JTAG Port Connector 17 1 1 RS232 Serial Port Connector 18 Flash Memory SIMM Insertion 19 SDRAM DIMM Insertion 00965596666 20 SW Description i u ta bw ewe 4h we 22 JP2 Therm Connector cios 23 JP7 Ventilator Supply qu OUR ET RE 23 JP10 VPP Source Selection 24 PCI Host Configuration Registers 46 PCI Interrupt Routing 48 Main Clock Generator Scheme 51 PCI Clock Generator Scheme 52 SDRAM DIMM Connection Scheme No L2 Cache 55 SDRAM DIMM 60x Bus Connection Scheme with L2 56 FLASH SIMM Connection Scheme 60 B2P
191. SSERTED amp FLASH BANK2 4 BOOT IN FLASH amp DSyncHardReset_B fb CS4 ASSERTED amp FLASH BANK2 amp HRESET BOOT IN EEPROM IN EEPROM FlashCs3 B CSO_ASSERTED amp FLASH BANK3 amp HRESET BOOT IN FLASH 50 ASSERTED amp FLASH BANK3 4 BOOT IN FLASH amp DSyncHardReset_B fb CS4 ASSERTED amp FLASH BANK3 amp HRESET BOOT IN BOOT IN EEPROM FlashCs4_B 50 ASSERTED amp FLASH 4 HRESET BOOT IN FLASH 50 ASSERTED amp FLASH amp BOOT IN FLASH amp DSyncHardReset CS4 ASSERTED amp FLASH 4 amp HRESET BOOT IN EEPROM BOOT EEPROM EEpromCs EEpromCs 50 ASSERTED amp HRESET BOOT IN EEPROM CSO ASSERTED amp IN EEPROM amp DSyncHardReset_B fb CS4 ASSERTED amp HRESET BOOT IN FLASH IN FLASH 150 MPC8266ADS PCI User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information k k k UNI Chip Select k k k kk kk k k equations AtmUniCsOut_B oe AtmUniCsOut_B AtmUniCsIn_B Power Reset equations 5 PORIn SYSCLK 5 Baar 0 S PORIn 0 5 B PORIn K K K K K K K LOGIC equations
192. Sandou zw 99049 as 251 0 6 13170 13170 g na ugzndo 9110 E i 771 0 2d 88145 uandu Hands 771 0 9v1vd 22161 2261 Stiva Sia on _ 02161 232151 232151 0281 riad SIM 137151 13251 6 7 60 vll 610 810 810 o Op Srivd 55150 LLL ILL Selva o 9 810 810 gt Zelvd M 1 lvd selva oy sy so HE i FRING ldv Ld vELVO o Uu we S i Telva 099 LZIN Teqaw ZIN ev Telva OIN oady SIN ov 820 L SIN SIN oov 821 0 soy LLTW szaday 82009 2101 ow 821 0 Zelvd Sev LETT zady 12009 SIN 020 12140 921 0 Om zady 92009 22 921 0 Selva RA 9200 lt 2 PN Selva Le veddv ready SIT cov zv LS 82009 220 82140 22140 Eh E zady 22009 858 20 221 12140 8 46092911 oy SP zady rzady er 020 Jso9zodN Telvd 021 0 PV 1Ha ZO oady ZIN eiua OY 021 0 Wel oie sen
193. Slot2IntBMask Active else Slot2IntB Mask_ Active WY ef CG state diagram Slot2IntCMask state Slot2IntCMask Active if WRITE IntMaskReg Slot2IntCMask DATA BIT pin Slot2IntCMask Active Hard Reset Slot2IntCMask DEFAULT Slot2IntCMask_Active Hard Reset amp Slot2IntCMask PON DEFAULT Slot2IntCMask Active then Slot2IntCMask_ Active else Slot2IntCMask Active state Slot2IntCMask Active if WRITE IntMaskReg Slot2IntCMask_DATA_BIT pin Slot2IntCMask Active amp 176 MPC8266ADS PCI User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information Hard Reset Slot2IntCMask PON DEFAULT Slot2IntCMask Active Hard Reset amp Slot2IntCMask PON DEFAULT Slot2IntCMask Active then Slot2IntCMask Active else Slot2IntCMask Active 1 state diagram Slot2IntDMask state Slot2IntDMask Active if WRITE IntMaskReg Slot2IntDMask DATA BIT pin Slot2IntDMask Active amp Hard Reset Slot2IntDMask PON DEFAULT Slot2IntDMask Active Hard Reset amp 51021100 PON DEFAULT Slot2IntDMask_Active then Slot2IntDMask_Active else Slot2IntDMask_ Ac
194. TATE JTAG DR JtagState fb JTAG DR STATE JTAG PAUSE DR JtagState fb PAUSE DR STATE JTAG EXIT2 DR JtagState fb JTAG EXIT2 DR MOTOROLA MPC8266ADS PCI User s Manual For More Information On This Product Go to www freescale com 137 Freescale Semiconductor Inc Support Information STATE JTAG UPDATE DR JtagState fb JTAG UPDATE DR STATE JTAG SELECT IR JtagState fb JTAG SELECT STATE JTAG CAPTURE IR JtagState fb CAPTURE STATE JTAG SHIFT IR JtagState fb SHIFT STATE JTAG EXITI IR JtagState fb EXITI STATE PAUSE IR JtagState fb PAUSE STATE JTAG EXIT2 IR JtagState fb EXIT2 STATE JTAG UPDATE IR JtagState fb UPDATE Instruction codes INST_CODE_BYPASS 7 INST_CODE_EXTEST 0 INST_CODE_DOWNLOAD 1 INST CODE UPLOAD 2 not supported for 1st implementaion INST CODE PON RESET 6 INST CODE UN IMPLEMENTED b011 b100 b101 NEXT INST BYPASS JtagShiftIR fb INST CODE BYPASS NEXT INST EXTEST JtagShiftIR fb INST CODE EXTEST NEXT INST DOWNLOAD JtagShiftIR fb INST CODE DOWNLOAD NEXT INST UPLOAD JtagShiftIR fb INST CODE UPLOAD NEXT INST PON RESET JtagShiftIR fb INST CODE PON RESET NEXT INST UN IMPLEMENTED JtagShiftIR fb INST CODE UN IMPLEMENTED INST 15 B
195. TURE IR if Tms then JTAG SHIFT IR else JTAG EXITI IR state SHIFT IR if Tms then JTAG EXITI IR else JTAG SHIFT IR state IR if Tms then JTAG PAUSE IR else JTAG UPDATE IR state JTAG PAUSE IR if Tms then JTAG EXIT2 IR else JTAG PAUSE IR state EXIT2 IR if Tms then JTAG UPDATE IR else JTAG SHIFT IR state JTAG UPDATE IR if Tms then JTAG IDLE else JTAG SELECT DR k k k MPC8266ADS PCI User s Manual 153 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information Jtag Dedicated State Signals Falling Edge equations FallingTckSignals clk Tck FallingTckSignals ar JtagStateReset FallingTckSignals ap 0 JtagResetState STATE JTAG RESET Active Low JtagShiftIrState STATE JTAG SHIFT IR JtagShiftDrState STATE JTAG SHIFT DR JtagTdoEnable STATE JTAG SHIFT IR STATE JTAG SHIFT DR Jtag Instruction Shift Register equations JtagShiftIR clk JtagShiftIR ap JtagReset reset bypass JtagShiftIR ar 0 when JtagShiftIrState fb amp STATE JTAG ENABLED then JtagShiftIR Tdi JtagShiftIRO fb JtagShiftIR 1 fb else when STATE JTAG CAPTURE IR amp STATE JTAG ENABLED then JtagShiftIR INST CODE BYPASS interim default else JtagShiftIR
196. This Product Go to www freescale com Freescale Semiconductor Inc Support Information Table 7 4 P4 CPM Expansion Connector Pin No Signal Name Attribute Description B23 PA9 T S MPC8266 s Port A 9 0 Parallel or dedicated CPM lines be used for any of their available functions B24 8 25 7 26 6 27 5 28 4 29 B30 PA2 B31 32 PB31 T S Fast Ethernet Transmit Error H When the Ethernet port is enabled this signal will be asserted High by the MPC8266 when an error is discovered in the transmit data stream When the port is operation at 100 Mbps the LXT970 responds by sending invalid code symbols on the line When the Ethernet port is disabled this line may be used for any available function of PB31 C2 FETHRXDV PB30 I O T S Fast Ethernet Receive Data Valid H When this signal is asserted High while the Fast Ethernet port is enabled and FETHRXCK goes high it indicates that data is valid on the MII Receive Data lines FETHRXD 3 0 When the Fast Ethernet port is disabled this line is tristated and may be used for any available function go PB30 C3 FETHTXEN PB29 T S Fast Ethernet Transmit Enable H The MPC8266 will assert High this line to indicate data valid on the FETHTXD 3 0 lines When the Fast Ethernet port
197. U q 30 SoWoud3au wr 02 0159 S d 3 2 010 721 ST LISH 904 3 55 60 5 921 c 2093 80 lt 21 08 ZIdOMS E 1 0021490 oF tyd E 10 or m Ov 5 121908 j 5 N34ngqu m 8 8 5 3 szadyg rq 129 S 163021 2013 d 3 LS 09301 i 991 0 10 81 08 Y LIdOMS 97 00 3 0140 6 2 1 ISO ju 22 89245980 N3IH1334u o NINIVU 50 40 1922 081 SHu o Hsnzu OA v9 82 INJ 3ZISWWIG 25210010 vin 730 lt a T g 280 du 4 gt 92 SWIN onom 98 i 01108801 12 eio 19810 279 01500 amp LU LIVOS 8520 40 Tze 281 2129 i OMOLXS 06 6 211 LE 5 9 0 50285080 SEE EA3HTOOL 26 Mis INNU AN ZABHIOOL 55 L
198. X LNLV SIVGL 5 91401 Su s spuedep pue LSU aq 2191 9391 tv rent i n am 188 m 920088 ve 0 2 LEN N GNnONO SISVHO XD glen 9 uno osesWd Ltr qm sey 101 072 m 9494 1851034 dE 1 912 a Div in S n E 158 34 09 N3XHWLVU 1 0797 22 8801 11999 Juil o TN 28 o amp vam OH Vif v 9 S2IXOWL 87 as 5 I ven 295 vou ST SSH SON Y SeIXO WL P MY L ign cabin Get 5 Tg dGaXLWiV lt 4 ALSXHWIV vena T Vi VY I 1 Tl 28 T 1 1 lt lt gz dip 88 95 5 dSHNIV t 5 5 LL S 19 99 ez Naxeniv 1 34001 340 T 3901 axe 80 7 dQXHW1V 3400 10 E 769 6 0 8 07 LOXHINLV 69 ZOXHILV 99 roxo 20 YO Loo zo za z 555555 23 22 2222 x E 1419 luis 5 5 lt lt lt lt lt 8 8 10 LE 888888 88888 25522 5525 sre 880088 99998 55 58855 8859 m m 88
199. X power connector The female part is soldered to the PCB while the plug is connected to the power supply That way fast connection disconnection of power 18 facilitated 6 2 2 Fast Ethernet Port Connector The Ethernet connector on the MPC8266 MB is a Twisted Pair 100 10 Base T connector Use is done with 90 RJ45 8 connector 6 2 3 ATM 155 Port Connection The ATM 155 I F to the media is optical rather than electrical Use is done with HP s HFBR 5205 optical I F which is placed on the edge of the board for convenient connection 6 2 4 RS232 PortS Connector The RS232 port connector is a stacked 9 pin 90 female D Type connector which saves on board space made of two connectors for two ports 6 2 5 CPM Expansion Connector The CPM expansion connectors carries all CPM pins 1 Port A to Port D signals Use done with DIN 41612 128 pin T H PCB connector residing on the board allowing convenient vertical connection to off board tools Power supply pins are also provided through this connector 6 2 6 COP JTAG Port Connector The debug port connector is a Motorola standard COP JTAG connector for the 60X processors family It is a generic 16 pin 2 X 8 Male SMD 90 protected header connector MOTOROLA MPC8266ADS PCI User s Manual 101 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Physical Properties 6 2 7 Logic Analyzer Connectors To support fast connectio
200. Y 46 04 6184 EAF CIETE 9108 Tiy 18 0204 DSINH E wad ETRY Q6INH F 5 0QXHH133 2204 Ty 2204 Daves cede B6INH 2208 vax 16294 T 9 10X1H133 Srv vdd 39 gt 15809 pay 9 518 9204 5 1 4 1 QaX1 100 2c8d V NH T g 71096133 20 1 SH GN 299 HUHI Foy 1 SUF VAVIOXY 6Zad aan N3X1H134 RED M Fav OOSXLAd AGX8H133 QV E03 1 1 d ANOG Wd 104 E S19 0d 9d YISVY N3Xu rod 3NOQ Sd 81SLVAY1OXLSOd 1 15 Ox19LY 00 804 ONASHLV9Wd 812 04 NASLLVNASNWS Vd Svd lo 538 09 899 Ad 1QXL 810 624 OQXLLVOXLINS eVd T T 95 0154
201. YPASS JtagIR fb INST CODE BYPASS INST IS EXTEST JtagIR fb INST CODE EXTEST INST IS DOWNLOAD JtagIR fb INST CODE DOWNLOAD INST IS UPLOAD JtagIR fb INST CODE UPLOAD INST IS PON RESET JtagIR fb INST CODE PON RESET READ JTAG DOWNLOAD CSR VGR READ BCSR 6 WRITE JTAG DOWNLOAD CSR VGR WRITE BCSR 6 READ JTAG DOWNLOAD DATA VGR READ BCSR 7 RECEIVE FULL 1 JTAG DOWNLOAD SHIFT REG FULL JtagReceiveFull fb RECEIVE FULL 138 MPC8266ADS PCI User s Manual For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Support Information Equations state diagrams X equations BCSR 0 equations ClockedContReg clk SYSCLK ClockedContReg ar 0 ClockedContReg ap 0 DrivenContReg oe hfff state diagram PBI state PBI IN ACTIVE if WRITE BCSR 0 amp PBI DATA PBI IN ACTIVE amp RESET PBI PON DEFAULT PBI IN PON RESET amp PBI PON DEFAULT PBI IN ACTIVE then IPBI IN ACTIVE else PBI IN ACTIVE state IN ACTIVE if WRITE BCSR 0 amp PBI DATA BIT pin PBI IN ACTIVE amp RESET PBI PON DEFAULT PBI IN ACTIVB PO
202. a 61999 95 did HM 0 00 9 nivaa 885 frod 21 08 68 oroa 91 2008 US enu po 10079 viivaa 19 000 100 8 SLIVOH S Ev 5008 i oq 860 510078 7 61008 vod Fer fod gt NUT NE 2200 8 000 200 8 lt lt 00 8 9200 8 08WWIS HSV13 22900799 wie 5555 5555 3588 SSTN quo A1 9 20 sezo vego 0 194 T z 5 Y Support Information MOTOROLA Go to www freescale com MPC8266ADS PCI User s Manual For More Information On This Product 194 Freescale Semiconductor Inc Support Information OQ o wg 1002 Te epson 5 v jequmwweunoq zs 04 Tavusi 02197 18 UAS 15 Y or foor Too Too Tos Foo hos To hoo foor gt von poo pozo 2105 25 LON z 9 0641 Ir 5007 5 gg 0801 i 100 5201 BEATO 8501 T SANG 3qav
203. a 6 adv 6100 HM ein Sina Loe 8 98 Av ES 8 00 81009881 iv 58 9V Sina siy ES IC 9 1 0 siy LOH sady 9 00 StH gina 29 pry LSIH SIH piy 29 S ud LIH riady wady HH giy 8 8A ziv LS L aav _ 510 2 EM T IHd Lord zrady 21009614 LEN 211 oiv 14 Std oiv lua 25 SIT sha pe LE 1 6 ey LS ud 81vd UM iv ES 8aav 8009 p 200 8190 1140 Hg 0v aav 3v M 8 sady 900 611 LEM Siva Siva PA wie 00 00 84 LE _ 611 a zv L8 zy zug Elva 2140 Lu iv zady zady iv LSN 21 0 9 v 9 Lv 0190 IM 000 oady 817 IM 0190 lt gt dav les TE VG s Go to www freescale com 02 1002 Ze J9quie oN 592804 1 ev Jequinn jueunooq 925 Tavusl 15
204. abled When negated the RS232 transceiver for port 2 is in standby mode and SCC2 pins are available for off board use via the expansion connectors RW 8 31 Reserved Un implemented a Required for voltage levels adaptation 4 13 3 BCSR2 Board Control Status Register 2 BCSR2 1 status register which 1 accessed at offset 8 from the BCSR base address Its a read 70 MPC8266ADS PCI User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Functional Description only register which may be read at any time BCSR2s various fields are described in Table 4 12 Table 4 12 5 2 Description BIT MNEMONIC TSTAT 0 7 Function Tool Status 0 7 This field is reserved for external tool status report The exact meaning of each bit within this field is tool unique and therefore will be documented separately per each tool These signals are available at the System expansion connector PON DEF ATT 8 11 TOOLREV 0 3 TOOL Revision 0 3 This field may contain the revision code of an external tool connected to the MPC8266 The various combinations of this field will be described per each tool users manual These signals are available at the System expansion connector The revision option for the external tools are shown in Table 4 18 12 15 EXTTOLI 0 3 External Tools Identification These lines
205. actory Set Figure 2 6 SW3 Description 1 In fact 8 Hard Reset configuration words are read by a configuration master however only the first is rel evant for a single MPC8266 12 MPC8266ADS PCI User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Hardware Preparation and Installation 2 3 6 Setting MODCKH 0 3 for PLLs Multiplication Factors When the Hard Reset configuration word is taken from Flash 51 the functionality of the MODCKH 0 3 bits in the Hard Reset Configuration Word depends on the mode of the PCI When the PCI mode in the MPC8266 is enabled set permanently on this board the MODCKH 0 3 lines are taken from SW4 and the MODCKH 0 3 bits in the Hard Reset Configuration Word are ignored When the PCI mode in the 8266 is disabled not available on this board MODCKH 0 3 are taken from the Hard Reset Configuration Word SW4 1 4 set the upper 4 bits of the MODCK field during Hard Reset Configuration acquisition When an individual switch of SW4 1 4 is at the OFF position its corresponding MODCKH line is pulled high 1 during Hard Reset while when at the ON position pulled down 0 see Figure 2 4 2 3 7 Setting PCI_MODCK for PCI Bus Clock The settings of this line determines the frequency of the PCI bus When PCI MODCK is set low the PCI bus frequency is set by the the MODCK lines When set high the
206. al 173 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information Hard Reset Slot IntAMask PON DEFAULT Slot1IntAMask Active Hard Reset amp SlotlIIntAMask PON DEFAULT SlotlIntAMask Active then SlotlIntAMask Active else ISlotlIntAMask Active state diagram Slot1IntBMask state SlotlIntBMask Active if WRITE IntMaskReg Slot1lIntBMask DATA BIT pin SlotlIntBMask Active Hard Reset Slot1IntBMask PON DEFAULT Slot1IntBMask Active Hard Reset amp SlotIIntBMask PON DEFAULT IntBMask Active then ISlot1IntBMask Active else SlotlIntBMask Active state SlotlIntBMask Active if WRITE IntMaskReg Slot1lIntBMask DATA BIT pin Slot1IntBMask Active amp Hard Reset Slot1IntBMask PON DEFAULT Slot1IntBMask Active Reset amp SlotlIIntBMask PON DEFAULT SlotlIntBMask_Active then SlotlIntBMask Active else 1510 IntBMask Active state diagram 5101 state Slotllnt CMask_ Active if VGR_WRITE_IntMaskReg amp Slotllnt CMask_DATA_BIT pin Slotllnt CMask_Active Hard_Reset Slot1IntCMask_PON_DEFAULT Slot1IntCMask Active Hard Reset amp Slot1IntCMask_PON_DEFAULT Slotllnt CMask_Active then ISlotlIntCMask Active else SlotlIntCMask Active state SlotlIntCMask
207. al of the MPC8266 resetting the transceiver whenever hard reset sequence is taken The LXT970 may also be reset by either asserting the RST bit in BCSRI see Table 4 11 or by asserting bit 0 15 MSB of LXT970 control register via I F To allow external use of FCC2 its pins appear at the CPM expansion connectors and the ethernet transceiver may be Disabled Enabled at any time via the MDIO port The LXT970 is able to interrupt the MPC8266 via IRQ7 line This line is shared also with the CPM expansion connectors Therefore any tool that is connected to IRQ7 or IRQ6 for that matter should drive these lines with an Open Drain buffer Both IRQ6 and IRQ7 are pulled up on the MPC8266 MB 4 12 2 1 LXT970 Control The LXT970 is controlled via the management port which is a 2 wire interface a clock and a bidirectional data line This is in fact a bus 1 up to 32 devices may reside over it while the protocol defines a 5 bit slave address field which is compared against the slave address set to each device by hardware during device reset according to the levels on MF 4 0 pins On the board the slave address is hard set to 500000 The MPC8266 interfaces this port using two pins PC9 for and 10 for MDC There is no special support within the MPC8266 for the port and the protocol is implemented in S W The MDIO port may interrupt a host in 2 ways drivi
208. amp A29 VGR_WRITE_BCSR_2 BrdContRegCs_B amp DVal_B amp R_B_W amp A27 amp A28 amp A29 VGR_WRITE_BCSR_3 BrdContRegCs_B amp DVal_B amp R_B_W amp A27 amp A28 amp 29 VGR_WRITE_BCSR_4 BrdContRegCs_B amp DVal_B amp R_B_W amp A27 amp A28 amp A29 VGR_WRITE_BCSR_5 BrdContRegCs_B amp DVal_B amp R_B_W amp A27 amp A28 6 29 VGR_WRITE_BCSR_6 BrdContRegCs_B amp DVal_B amp R_B_W amp A27 amp A28 amp A29 VGR_WRITE_BCSR_7 BrdContRegCs_B amp DVal_B amp amp 27 amp A28 6 29 VGR_READ_BCSR_0 BrdContRegCs_B amp amp A27 amp A28 amp A29 VGR_READ_BCSR_1 BrdContRegCs_B amp amp A27 amp A28 amp 29 VGR READ BCSR 2 BrdContRegCs_B amp R_B_W amp A27 amp A28 amp A29 MOTOROLA MPC8266ADS PCI User s Manual 131 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information VGR READ BCSR 3 BrdContRegCs B amp R amp A27 amp A28 amp 29 READ BCSR 4 BrdContRegCs B amp W amp 27 6 A28 amp A29 READ BCSR 5 BrdContRegCs_B amp R amp A27 amp A28 amp 29 READ BCSR 6 BrdContRegCs B amp W amp A27 amp A28 amp 29 READ BCSR 7 BrdContRegCs B amp W amp A27 amp A28 amp A29
209. arity GPCM OR1 FFFF8010 32 KByte block size all types access 1 w s BR2 All SDRAM DIMM PPG 00000041 Base at 0 64 bit port size no parity Sdram Supported machine 1 OR2 SDC2UV6482C 84 FF000C80 16MByte block size 2 banks per device row starts Fujitsu at A9 11 row lines internal bank interleaving allowed normal AACK operation SDC8UV6484C 84 by FC002CC0 64MByte block size 4 banks per device row starts Fujitsu at A9 12 row lines internal bank interleaving allowed normal AACK operation BR3 Depends on the SDRAM PPG TBD Not used for the type of SDRAM supplied with the DIMM board Value is specific foran SDRAM DIMM OR3 Depends on the SDRAM TBD Not used for the type of SDRAM supplied with the DIMM board Value is specific foran SDRAM DIMM BR4 E PROM PPC C2000801 Base at C2000000 8 bit port size write protect disabled no parity GPCM 4 AT28HC64B 70JC by FFFF8846 32 KByte block size CS output half a clock after Atmel address all types access 4 w s Timing relax BR5 5350 UNI PPC 04600801 Base at 04600000 8 bit port size no parity GPCM on PPC bus 5 6 32K Byte block size delayed CS assertion early CS and WE negation for write cycle relaxed timing 7 w s for read 8 for write extended hold time after read BR8 PCI Interrupt Controller PPC 04731801 Base at 04730000 32 bit port size no parity on bus OR8 FFFF8010 32 KByte block size all types access 1 w s
210. b tn ama zd SW z p Freescale Semiconductor Inc Support Information L z 02 p H wy 1002 Ze TeqUISAON Aep ORD Ovi dOO jueunoog 9265 654 ov iridoo 3dec 3022 3922 SW I9dz0d YLC dOD 943 uo puedep 654 854 860 600 T sr ugxu wj IDE I3S3HHu t Ei 1353957 5 4ojonpuootueg 8 289 OL O380u Y 18819 20067 t oar 40 34001 SAIN EE 1 qe 5 N a TOA 1 5 soq xu 8 voa bar ou 5 Os UE sur ST os zaxa he su 1 2 or pur 20 99 SH asa EET wa 2610 Suu Poe 00 easoriow 819 9 ZNS 557 anor uo ae 2 4 2 25 T
211. bEnl PIN 92 istype reg buffer RS232 port 1 enable RS232En2 B PIN 93 istype reg buffer RS232 port 2 enable Board Status Registers Chip Selects Besr2Cs B PIN 42 istype com Besr4Cs PIN 32 istype com k k k Flash EEPROM Associated Pins MOTOROLA MPC8266ADS PCI User s Manual 123 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information PDI 71 PD2 69 F_PD3 PIN 67 PD4 PIN 65 Cs0_B PIN 31 flash eeprom chip select input Cs4_B PIN 33 eeprom flash chip select input EEpromCs_B PIN 83 istype com EEPROM chip select FlashCs1 B PIN 58 istype com Flash bank1 chip select FlashCs2 B PIN 48 istype com Flash bank2 chip select FlashCs3 B PIN 45 istype com Flash bank3 chip select FlashCs4 B PIN 55 istype com Flash bank4 chip select k k k k k k k k k k LM PM5350 ATM UNI Associated Pins k k AtmUniCsIn B PIN 22 AtmUniCsOut B PIN 21 istype com remove if short of pins Reset amp Interrupt Logic Pins PORIn_B PIN 97 RstConf B PIN 28 istype Hard Reset master select PIN 20 connected to N C of
212. ceiver is in standby mode within which the receiver outputs are tri stated enabling the use of the corresponding ports pins off board via the expansion connectors Nine pins female D Type stacked connector is used configured to be directly via a flat cable connected to a standard IBM PC like RS232 connector DCD TX TX DTR GND DSR RTS CTS N C ak WD ON O Figure 4 10 RS232 Serial Ports Connector 4 12 3 1 RS 232 Ports Signal Description In the list below the directions and are relative to the MPC8266 MB board i e T means input to the MPC8266 MB e CD Data Carrier Detect This line is always asserted by the MPC8266 MB e TX O Transmit Data e RX Receive Data DTR D Data Terminal Ready This signal is used by the software on the MPC8266 MB to detect if a terminal is connected to the board DSR Data Set Ready This line is always asserted by the MPC8266 MB RTS D Request To Send This line is not connected in the MPC8266 MB e CTS Clear To Send This line is always asserted by the MPC8266 MB 4 13 Board Control amp Status Register BCSR Most of the hardware options on the MPC8266 MB are controlled or monitored by the BCSR which is a 32 bit wide read write register file The BCSR is accessed via the MPC8266s memory controller see Table 4 5 and in fact includes 8 registers BCSRO to BCSR7 Since minimum block size
213. ct lines only one chip select line CSO or CS4 if the is using CSO is used to select the Flash as a whole while distributing chip select lines among the module s internal banks is done by on board programmable logic according to the Presence Detect lines of the Flash SIMM inserted to the MPC8266 MB The access time of the Flash memory provided with the MPC8266 MB is 95 nsec however devices with different delay are supported as well By reading the delay section of the Flash SIMM Presence Detect lines see Table 4 13 the debugger can establish via register ORO in 58 MPC8266ADS PCI User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc case CSO is used or OR4 if CS4 is used the correct number of wait states needed to access the Functional Description Flash SIMM considering 66MHz system clock frequency The control over the Flash is done with the GPCM and a dedicated CSO CS4 region which controls the whole bank During hard reset initialization the debugger or any application S W for that matter reads the Flash Presence Detect lines via BCSR and determines how to program registers BRO amp or amp within which the size and the delay of the region determined The performance of the flash memory is shown in Table 4 8 Table 4 8 Flash Memory Projected Performance Figures Number of System Clock Cycles
214. ction 2 3 4 During hard reset sequence the configuration master reads the Flash or or BCSR memory at addresses 0 8 0x18 0 20 a byte each time to assemble the 32 bit configuration word A total of 64 bytes of data 15 read from D 0 7 to acquire 8 full configuration words for system that may have upto 8 8266 chips The configuration word for a single 8266 is stored in the Flash memory SIMM in the E PROM or as default in the BCSR while the other seven words are not initialized as there are no additional MPC8266 on the MPC8266ADS PCI The default configuration word is shown in Table 4 1 for the FLASH and in Table 4 2 for the 2 PCI module configuration is 256 p In general from any device residing on CSO 2 In general The MPC8266 for which RSTCONF is asserted along with PORST asserted or in particular MPC8266 residing on the MPC8266ADS PCI 3 Although the MPC8266 as configuration master reads 8 configuration words only the 18 configuration word is influential MOTOROLA MPC8266ADS PCI User s Manual 41 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Functional Description Bytes long and should start at address 0x100 There are four possible configuration words e MPC8266ADS PCI without L2 Cache FLASH BCSR is the boot device CSO is assigned to the FLASH and CS4 is assigned to the E PROM e MPC8266ADS PCI witho
215. ctions are loaded into it from JISR when the TAP enters the Update IR state The valid instructions and their associated functions are shown in Table 4 26 Table 4 26 JTAG Instruction Codes Mnemonic Code Bin Function EXTEST 000 Execute Test JTAG public instruction No function with this application since there is no built in test within this JTAG entity Defaults to Bypass DOWNLOAD 001 Download When holds this instruction and the controller is in Shift DR mode the input of the Download Shift register is connected to TDI of the board while the TDO of this machine reflects the status of FULL flag in the Download Control and Status register Data may be shifted in to be read by the download agent running on board When the TAP controller moves into EXITI DR state the Receive Full flag is set in the Download Control amp Status register so that the download agent may learn about the presence of valid data in the JDSR UPLOAD 010 Up Load Not supported with current revision defaults to Bypass SAMPLE 011 Sample Preload public instruction Not implemented since there are no PRELOAD external pins to this JTAG entity Defaults to Bypass Reserved 41007 5101 Reserved un implemented defaults to Bypass PON_RESET 410 Power On Reset When this code is loaded into Power On Reset is generated to the board eventually resetting the TAP con
216. ctive 1 PCI Slot 1 Interrupt C Masked SlotlIntDMask Active 1 PCI Slot 1 Interrupt D Masked Slot2IntAMask Active 1 PCI Slot 2 Interrupt A Masked Slot2IntBMask Active 1 PCI Slot 2 Interrupt B Masked Slot2IntCMask Active 1 PCI Slot 2 Interrupt C Masked Slot2IntDMask Active 1 PCI Slot 2 Interrupt D Masked Power On Defaults Assignments 164 MPC8266ADS PCI User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information SlotOIntAMask PON DEFAULT SlotOIntAMask Active SlotOIntBMask DEFAULT SlotOIntBMask Active SlotOIntCMask PON DEFAULT SlotOIntCMask Active SlotOIntDMask PON DEFAULT SlotOIntDMask Active SlotlIntAMask PON DEFAULT SlotlIntAMask Active SlotlIntBMask PON DEFAULT SlotlIntBMask Active SlotlIntCMask DEFAULT SlotlIntCMask Active SlotlIntDMask PON DEFAULT SlotlIntDMask Active Slot2IntAMask PON DEFAULT Slot2IntAMask Active Slot2IntBMask DEFAULT Slot2IntBMask Active Slot2IntCMask DEFAULT Slot2IntCMask Active Slot2IntDMask PON DEFAULT Slot2IntDMask Active Data Bits Assignments 47k ORF kk SlotOIntAMask_DATA_BIT D0 SlotOIntBMask DATA D1 SlotOIntCMask
217. dS zSu vod 4 0 ISOH 199 1919 MOL 1089 1028 30139GON 194 lt lt 8628 MOL diva v9JOcl 2 3 9 6 9029 MOL VLU OSOWLVU 959 vosd 108 LHMOGON 194 108 108 9 N39494u 1990 114 12401 C6 939 104 orsy uva ocu SOorusogu lt YA Ndjn qu oe HS n14z1u 858 SOZHSOSU 55 22 8580 IN3 SHU 201 Sdn IInd 9154 9259 8154 2158 4 58 758 25910019 16910014 SOWLVU ss 9 59959890 2101 2 1 WOg 9 98021 HNIZ1U XOL MWA a NA 5 14885219 2 1831 Sandou 5 u yor For More Information This Product s Go to www freescale com 02 10 eh 19945 1002 Ze J9quie oN 592804 v
218. directly generate hard reset by asserting low this line 4 1 2 2 Manual Hard Reset To allow run time Hard reset when the COP controller is disconnected from the MPC8266ADS PCI and to support resident debuggers manual Hard is facilitated Depressing both Soft Reset S3 and 52 buttons asserts the HRESET pin of the MPC8266 generating a HARD RESET sequence Since the HRESET line may be driven internally by the 8266 it must be driven to the 8266 with an open drain gate If off board H W connected to the MPC8266ADS PCI is to drive HRESET line then it should do so with an open drain gate this to avoid contention over this line When Hard Reset is generated the 8266 is reset in a destructive manner 1 the hard reset 40 MPC8266ADS PCI User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Functional Description configuration is re sampled and all registers except for the PLL s are reset including memory controller registers reset of which results in a loss of dynamic memory contents To save on board s real estate this button is not a dedicated one but is shared with the Soft Reset button and the ABORT button when both are depressed Hard Reset is generated 4 1 2 3 Internal Sources Hard Reset The MPC8266 has internal sources which generate Hard Reset Among these sources 1 Loss of Lock Reset When one of the P
219. dless of the boot source The memory address for the device assigned to CSO is always the same as determined in the Hard Reset configuration word Since the FLASH and E PROM require different memory spaces different 26 MPC8266ADS PCI User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Operating Instructions memory maps are devised for each case For details see Table 3 1 and Table 3 2 Table 3 1 MPC8266ADS PCI Memory Map FLASH or BCSR as Boot Device Address Memory Port Memory Device Name 5 Range Type Size Size 00000000 SDRAM DIMM SDCUV6482 SDC8UV6484 64 64 MByte OOFFFFFF 16 MByte 64 MByte 01000000 04000000 Empty Space 5 044 04500000 BCSR 0 7 32 32 KByte 04507FFF 04500000 BCSRO 4 Byte 04507FE3 04500004 BCSRI 4 Byte 04507FE7 04500008 BCSR2 4 Byte 04507FEB 0450000C BCSR3 4 Byte 04507FEF 04500010 BCSR4 4 Byte 04507FF3 04500014 BCSR5 4 Byte 04507FF7 04500018 BCSR6 4 Byte 04507FFB 0450001 BCSR7 4 Byte 04507FFF 04508000 Empty Space 1 MByte 045FFFFF 04600000 ATM UNI Proc PMC5350 I F 8 32 KByte 04607FFF Contro 04608000 Empty Space 1 MByte 046FFFFF 04700000 MPC8266 32 128 KByte 0471FFFF Internal
220. duct Go to www freescale com Freescale Semiconductor Inc Support Information L 18945 1002 72 Wepsen H3TIOHINOO 926 Joyonpuootues LOI duoo SI 9914 xx 9 SLONI gt PON 10 l NO Sdt 0 EON 10 5 4 zon 2101 0101 601 101 801 oco zon S 81709 ezon 901 61VO8 8207 son LF 1201 9201 se 220 Son Lar GINI 1044 ion Pee ezon 0 2201 VINI 19 pron 8 1 0119 01 92015 99 99 Y 5091951 oin quo SNS 2 0919 8SAS 810 l SNL 54 5 4 01461 iz E 22 sron 001 Fa 7 vOGLdSI 4 SISVHO 205 MPC8266ADS PCI User s Manual For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Support Information 02 P ZL 19915 1002 772 190 EDU N3 SHO193NNOO NO
221. duct Go to www freescale com Freescale Semiconductor Inc Functional Description www fujitsumicro com products memory sdram mod html while the sdram chips data sheet may be obtained at URL http www fujitsumicro com products memory sdrams html Unlike memory SIMMs which have few presence detect lines for configuration report the DIMMs configuration information is stored in a 256 Byte Serial E PROM residing on the DIMM compatible with PC protocol In fact all necessary information is in the Ist half of the E PROM while the 2nd half is system available On the MPC8266ADS PCI the DIMM s configuration E PROM is connected to the MPC8266 C controller to inquire for SDRAM DIMM s configuration after hard reset sequence The 5 timing is controlled by SDRAM Machine 1 associated with 60X bus via its assigned Chip Select lines See Table 4 5 The SDRAM Machine supports PBI Page Bank Interleave which increases the SDRAM throughput The SDRAM connection scheme when no L2 cache is used 1s shown in Figure 4 5 2 s CSO CS2 53 SDRAS RAS SDCAS CAS SDWE gt BANKSEL 1 2 1 0 7 any SDA10 A10 A19 A9 A 20 28 E p SDDQM 0 7 P DQMB 0 7 4253 0000 63 Lo YSCLK 1 4 Serial EEPROM OK CLK 1 4 Slave Address Setting Switches SA 2 0 Y g SDA 2 ISCCLK SCL SDC2UV6482C 84 Figure 4 5 SDRAM DI
222. e Address Memory Port Memory Device Name Range Type Size Size 00000000 SDRAM DIMM SDCUV6482 SDC8UV6484 64 64 MByte OOFFFFFF 16 MByte 64 MByte 01000000 04000000 Empty Space 5 044 88 MPC8266ADS PCI User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Memory Map and Initialization Table 5 2 MPC8266ADS PCI Memory Map E PROM as Boot Device For More Information On This Product Go to www freescale com Address Memor Port Device Tory Range Type Size Size 04500000 BCSR 0 7 32 32 KByte 04507FFF 04500000 BCSRO 4 Byte 04507FE3 04500004 BCSRI 4 Byte 04507 7 04500008 BCSR2 4 Byte 04507FEB 0450000C BCSR3 4 Byte 04507FEF 04500010 BCSR4 4 Byte 04507FF3 04500014 BCSR5 4 Byte 04507FF7 04500018 BCSR6 4 Byte 04507FFB 0450001C BCSR7 4 Byte 04507FFF 04508000 Empty Space 1 MByte 045FFFFF 04600000 UNI Proc PMC5350 8 32 KByte 04607FFF Contro 04608000 Empty Space 1 MByte 046FFFFF 04700000 MPC8266 32 128 KByte 0471FFFF Internal MAP 04720000 Empty Space 64 KByte 0472FFFF 04730000 PCI Interrupt 32 32 KByte 04737FFF Controller 04738000 Empty Space 800 KByte 047F
223. e reg buffer PCI Slot 1 Interrupt D Slot2IntA NODE istype reg buffer PCI Slot 2 Interrupt Slot2IntB NODE istype reg buffer PCI Slot 2 Interrupt Slot2IntC NODE istype reg buffer PCI Slot 2 Interrupt C Slot2IntD NODE istype reg buffer PCI Slot 2 Interrupt D k kk k k k k PCI Interrupt Mask Register SlotOIntAMask NODE istype reg buffer PCI Slot 0 Interrupt A Mask SlotOIntBMask NODE istype reg buffer PCI Slot 0 Interrupt B Mask SlotOIntCMask NODE istype reg buffer PCI Slot 0 Interrupt C Mask MOTOROLA MPC8266ADS PCI User s Manual For More Information On This Product Go to www freescale com 159 Freescale Semiconductor Inc Support Information SlotOIntDMask NODE istype reg buffer PCI Slot 0 Interrupt D Mask SlotlIntAMask NODE istype reg buffer PCI Slot 1 Interrupt A Mask Slot1IntBMask NODE istype reg buffer PCI Slot 1 Interrupt B Mask Slot1IntCMask NODE istype reg buffer PCI Slot 1 Interrupt C Mask SlotlIntDMask NODE istype reg buffer PCI Slot 1 Interrupt D Mask Slot2IntAMask istype reg buffer PCI Slot 2 Interrupt A Mask Slot2IntBMask NODE istype reg buffer PCI Slot 2 Interrupt B Mask Slot2IntCMask NODE istype reg buffer PCI Slot 2 Interrupt C Mask Slot2IntDMask NODE istype reg buffer PCI Slot 2 Interrupt D Mask kk k k k k Data
224. e chain while the length of the data scan chain is added with either 1 bit bypass 8 bit download preceding the MPC8266 in the chain MSB side 2 When this machine is in Bypass download a s w agent to free memory space Remember that the data scan chain is 1 bit longer than it used to be MSB side This agent basically polls the RX FULL flag in the Download Command amp Status register see Table 4 MOTOROLA MPC8266ADS PCI User s Manual 83 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Functional Description 23 when active reads the Download Data register See Table 4 24 and puts the data byte read where required Obviously the minimum it should know are the base address and size of data buffer being loaded however its level of sophistication is upto the system programmer Run this agent again using the same method 3 Shiftin DOWNLOAD instruction for this machine and BYPASS instruction for the 8266 4 Move controller into Shift DR state 5 Shift in a Byte of data The data shifted out is the state of FULL flag If the byte shifted out does not contain a 0 it indicates that new data was shifted in before the agent was able to read the previous That way the host may become aware of an error situation with the operation of the s w agent To play safe it is recommended to shift in a arbitrary data until FU
225. e to either the boards logic and to the MPC8266 itself 4 1 3 1 COP JTAG Port Soft Reset To provide convenient soft reset capability for a COP JTAG controller SRESET line appears at the COP JTAG port connector P3 The COP JTAG controller may directly generate Soft reset by asserting low this line 4 1 3 2 Manual Soft Reset To allow run time Soft reset when the COP controller is disconnected from the MPC8266ADS PCI and to support resident debuggers a Soft Reset push button is provided When the Soft Reset 46 MPC8266ADS PCI User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Functional Description push button is depressed the SRESET line is asserted to the MPC8266 generating Soft Reset sequence Since the SRESET line may be driven internally by the MPC8266 it must be driven by an drain gate to avoid contention over that line If off board H W connected to the MPC8266ADS PCI is to drive SRESET line then it should do so with an open drain gate this to avoid contention over this line 4 1 3 3 Internal Sources Soft Reset The only internal Soft reset source is the COP JTAG soft reset which may be generated using Public JTAG instructions to shift active value 0 to the SRESET pin the boundary scan chain This is not useful for run time 4 1 4 PCI Bus Reset The PCI Module in the MPC8266 can generate a reset signal ded
226. early negate 6 w s Smart Modular Tech Timing relax SM73288XG4JHBGO by FE000836 32MByte block size CS early negate 6 w s Smart Modular Tech Timing relax BR1 BCSR PPC 04501801 Base at 04500000 32 bit port size no parity GPCM OR1 FFFF8010 32 KByte block size all types access 1 w s BR2 All SDRAM DIMM PPC 00000041 Base at 0 64 bit port size no parity Sdram Supported machine 1 OR2 SDC2UV6482C 84 FF000C80 16MByte block size 2 banks per device row starts Fujitsu at A9 11 row lines internal bank interleaving allowed normal AACK operation SDC8UV6484C 84 by 002 0 64MByte block size 4 banks device row starts Fujitsu at A9 12 row lines internal bank interleaving allowed normal AACK operation BR3 Depends on the SDRAM TBD Not used for the type of SDRAM supplied with the DIMM board Value is specific foran SDRAM DIMM OR3 Depends on the SDRAM TBD Not used for the type of SDRAM supplied with the DIMM board Value is specific foran SDRAM DIMM BR4 E PROM PPC C2000801 Base at C2000000 8 bit port size write protect disabled no parity GPCM OR4 AT28HC64B 70JC by FFFF8846 32 KByte block size CS output half a clock after Atmel address all types access 4 w s Timing relax BR5 5350 UNI PPC 04600801 Base at 04600000 8 bit port size no parity GPCM on PPC bus 5 6 32K Byte block size delayed CS assertion early CS and WE negation for write cycle relaxed timing 7 w s
227. ed Internal space responds as 64 bit slave for external master not relevant for this application a With L2 Cache 3 4 2 Memory Controller Registers Programming The memory controller on the MPC8266ADS PCI is initialized to 66 MHz operation i e registers programming is based on 66 MHZ timing calculation There are two possible initializations for the memory controller e Flash SIMM is assigned to CSO and 2 is assigned to CS4 Flash SIMM is assigned to CS4 and E PROM is assigned to CSO 32 MPC8266ADS PCI User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Both options are shown in Table 3 6 and Table 3 7 Operating Instructions Table 3 6 Memory Controller Initializations For 66Mhz FLASH as Boot Device Init Value Device Bus hex Description BR0 SM73228XG1JHBG0 by PPG FF801801 Base at FF800000 32 bit port size no parity Smart Modular Tech GPCM SM73248XG2JHBG0 by FF001801 Base at FF000000 32 bit port size no parity Smart Modular Tech GPCM SM73288XG4JHBG0 by FE001801 Base at FE000000 32 bit port size no parity Smart Modular Tech GPCM ORO SM73228XG1JHBGO by FF800836 8MByte block size CS early negate 6 w s Timing Smart Modular Tech relax SM73248XG2JHBGO by FF000836 16MByte block size CS
228. ed as BADDRx lines DP 1 7 configured as L2 cache and IRQ 6 7 Initial internal space OxOF000000 10 36 Boot memory space OxFE000000 OxFFFFFFFF 2 pin is ABB DBB IRQ3 pin is DBB No masking on bus request lines Local bus pins function as PCI PCI is boot master AP 1 3 configured as BNKSEL 0 2 APE configured as IRQ7 and CS11 as CS11 18 60 510 configured as BCTL1 PCI autoload from EEPROM a Programmed into the in addresses 0x0 0x8 0x10 amp 0x18 MOTOROLA MPC8266ADS PCI User s Manual 31 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Operating Instructions b With L2 Cache Table 3 5 SIU REGISTERS PROGRAMMING Init Register Value hex Description RMR 0001 Check Stop Reset enabled IMMR 04700000 Internal space 0x047000000 SYPCR FFFFFFC3 Software watchdog timer count FFFF Bus monitor timing FF PPC Bus monitor Enabled Local Bus monitor Enabled S W watch dog disabled S W watch dog if enabled causes reset S W watch dog if enabled prescaled BCR 004C0000 Single MPC8266 60X Bus mode 0 wait states on address tenure No L2Cache 884440003 L2Cache assumed 1 clock hit delay when L2cache available 1 level Pipeline depth Extended transfer mode enabled for PCC Extended transfer mode disabled for Local Buses Odd parity for PPC amp Local Buses External Master delay enabl
229. ed as BCTL1 PCI autoload from EEPROM a Programmed into the E7PROM in addresses 0x0 0x8 0x10 amp 0x18 b With L2 Cache MOTOROLA MPC8266ADS PCI User s Manual 91 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Memory Map and Initialization Table 5 5 SIU REGISTERS PROGRAMMING Init oot Register Value hex Description RMR 0001 Check Stop Reset enabled IMMR 04700000 Internal space 0x047000000 SYPCR FFFFFFC3 Software watchdog timer count FFFF Bus monitor timing FF PPC Bus monitor Enabled Local Bus monitor Enabled S W watch dog disabled S W watch dog if enabled causes reset S W watch dog if enabled prescaled BCR 004C0000 Single MPC8266 60X Bus mode 0 wait states on address tenure No L2Cache 88444000 L2Cache assumed 1 clock hit delay when L2cache available 1 level Pipeline depth Extended transfer mode enabled for PCC Extended transfer mode disabled for Local Buses Odd parity for PPC amp Local Buses External Master delay enabled Internal space responds as 64 bit slave for external master not relevant for this application a With L2 Cache 5 2 2 Memory Controller Registers Programming The memory controller on the MPC8266ADS PCI is initialized to 66 MHz operation i e registers programming is based on 66 MHZ timing calculation There are two possible initializations for the memory controll
230. ed directly over the 60X bus and is supported gluelessly by the 8266 The cache data sheet may be obtained via the internet at URL http mot sps com books dl156 pdf mpc2605revS5 pdf The presence of the L2 Cache calls for the introduction of latch multiplexers over SDRAMs address lines because the MPC2605 snooping logic needs to monitor the address as is linear rather than multiplexed and the bus works by the 60X bus protocol allowing address pipelining These latch multiplexers are soldered in place only in case a cache is installed on board Otherwise they are omitted and bypassed by 0 resistors See also Section 4 7 3 L2 Cache Support Influence On SDRAM Design 4 11 1 L2 Cache Configuration amp Control The cache is configured via 5 configuration lines CFG 0 4 for the following functions 1 Cache size is set by CFG 0 2 The various settings of these lines per each cache module are encoded in Table 4 9 Table 4 9 L2 Cache CFG 0 2 Settings 55 TNT CFG 0 2 256K 000 Reserved 512K 010 1 st Module A26 0 014 2 nd Module 26 1 2 Snoop is Enabled CFG3 driven low for both modules 3 AACK assertion enabled CFG4 driven high for both modules The caches HRESET lines are connected directly to the SRESET line of the MPC8266 so that whenever Soft reset is asserted to by the MPC8266 the cache is reset along with it loosing all data previously stored in it The cache
231. ed on the number of internal banks within a SDRAM DIMM This since the Bank Select line s are inserted between the Column LSB and Row MSB address lines As can be seen from Figure 4 6 PBI and DIMM SIZE signals driven via BCSRO select the correct address line group for a specific DIMM size with PBI set The performance of the SDRAM is decreased by the addition of the external multiplexers of the SDRAMs address lines The effects may be seen in Table 4 6 4 7 4 SDRAM DIMM Configuration Information Unlike memory SIMMs which have few presence detect lines for configuration report the DIMMs configuration information is stored in a 256 Byte Serial EEPROM residing on the DIMM compatible with protocol fact all necessary information 15 in first half of the while the second half is system available On the board the DIMM configuration EEPROM is connected to the MPC8266 controller to inquire for SDRAM DIMM s configuration after hard reset sequence 4 8 Flash Memory SIMM The 8266 is provided with 8Mbyte of 95 nsec flash memory SIMM the 5 73228 by Smart Modular Technology which is composed of four LH28F016SCT L95 chips by Sharp arranged as 2M X 32 in a single bank Support is given also to 16MBytes and 32 MBytes simms The Flash SIMM resides on an 80 pin SIMM socket and is buffered from the 60X bus to reduce capacitive load over it To minimize use of MPC8266s chip sele
232. eescale com Freescale Semiconductor Inc Hardware Preparation and Installation Host Computer 232 gt 7 d gt SS SS SS S Ethernet gt 7 E lt ATM 155 optics ny 722222 Z K MOLE Uy w d 29 2 7772 ut ATX Power Supply ce Els K TUS rai gq P12 ice CIRCE LO o coil ci Figure 2 11 Stand Alone Configuration 2 4 3 COP JTAG Connector P3 The MPC8266ADS PCI COP interface connector P3 is a 16 pin male Header connector The connection between the MPC8266ADS PCI and the COP controller is by a 16 line flat cable supplied with the COP controller board obtained from a third party developer Figure 2 12 shows the pin configuration of the connector TMS SRESET HRESET CKSTP OUT Figure 2 12 P3 COP JTAG Port Connector 2 4 4 Terminal to MPC8266ADS PCI RS 232 Connection A serial RS232 terminal or any other RS232 equipment may be connected to the RS 232 connectors and The RS 232 connectors are a 9 pin female D type connectors arranged in a stacked configuration PIB connected to SCC2 of the MPC8266 is the lower and connected to SCC1 of the MPC8266 is the upper in the stack MOTOROLA MPC8266ADS PCI User s Manual 17
233. eescale com MOTOROLA Freescale Semiconductor Inc Support Information DO PIN 84 istype com DI PIN 78 istype com D2 PIN 80 istype com D3 PIN 59 istype com 4 PIN 70 istype com D5 PIN 57 istype com D6 PIN 60 istype com D7 PIN 72 istype com kk k k Board Control Pins Read Write PIN 44 istype reg buffer Page Base Interleaving DimmSize PIN 53 istype reg buffer Sdram Dimm Size L2Inh_B PIN 15 istype reg buffer flash enable L2Flush_B PIN 54 istype reg buffer 60x bus sdram enable L2Lock_B PIN 35 istype reg buffer bursting sram enable L2Clear_B PIN 34 istype reg buffer local bus sdram enable SignaLamp0_B PIN 79 istype reg buffer status lamp 0 for misc s w visual SignaLamp1_B PIN 81 istype reg buffer status lamp 1 for misc s w visual AtmEn_B PIN 94 istype reg buffer atm uni enable AtmRst_B NODE _istype reg buffer atm uni reset bit AtmRstOut_B PIN 96 istype com atm uni reset driven by register or by HRESET_B FEthEn B PIN 95 istype reg buffer fast ethernet trans enable FEthRst B NODE istype reg buffer fast ethernet trans reset bit FEthRstOut B PIN 3 istype fast eth trans reset driven by register by HRESET RS232
234. el ranges available for VDDL For further information over its function see Section 2 3 1 3 2 9 JP6 IDDL Measurement JP4 resides in IDDL s main current flow To measure IDDL JP6 should be removed using a solder tool and a current meter should be connected instead with wires as short and thick as possible Warning The job of removing JP6 and soldering the cur rent meter connections instead is very delicate and should be done by a skilled technician If this process is done by unskilled hands or re peated more than 3 times permanent damage may occur to the MPC8266ADS PCI 3 2 10 JP2 Thermal Sense Connector There are 2 dedicated pins THERM 0 1 which provide way to take internal temperature 22 MPC8266ADS PCI User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Operating Instructions measurements of the MPC8266 These pins should be connected to GND for normal operation is factory set with a jumper on its 2 3 positions so that THERMI is connected to GND JP2 3 GND 2 X THERM 1 Figure 3 2 JP2 Therm Connector 3 2 11 JP7 Optional Ventilator Supply An optional cooling ventilator for the MPC8266 may be powered via JP7 2 pin header connector not assembled In order to connect a ventilator to JP7 either a 0 1 pitch header should be soldered to it to be connected to a matching female connector or
235. er Hash SIMM is assigned to CS0 and E PROM is assigned to CS4 Flash SIMM is assigned to CS4 and E PROM is assigned to CSO Both options are shown in Table 3 6 and Table 3 7 Table 5 6 Memory Controller Initializations For 66Mhz FLASH as Boot Device Init Value Reg Device Type Bus hex Description BRO SM73228XG1JHBGO by PPC FF801801 Base at FF800000 32 bit port size no parity Smart Modular Tech GPCM SM73248XG2JHBGO by FF001801 Base at FF000000 32 bit port size no parity Smart Modular Tech GPCM SM73288XG4JHBGO by 001801 Base at 000000 32 bit port size no parity Smart Modular Tech GPCM ORO SM73228XG1JHBGO by FF800836 8MByte block size CS early negate 6 w s Timing Smart Modular Tech relax SM73248XG2JHBGO by FF000836 16MByte block size CS early negate 6 w s Smart Modular Tech Timing relax SM73288XG4JHBGO by FE000836 32MByte block size CS early negate 6 w s Smart Modular Tech Timing relax 92 MPC8266ADS PCI User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Memory Map and Initialization Table 5 6 Memory Controller Initializations For 66Mhz FLASH as Boot Device Init Value Device Bus hex Description BR1 BCSR PPG 04501801 Base at 04500000 32 bit port size no p
236. errupt Mask Register Description BIT MNEMONIC Function DEF 0 MPCI0_INTA Mask PCI Slot 0 INTA Mask PCI Slot 0 Interrupt A 0 R W 0 interrupt is available 1 interrupt is masked 1 MPCIO INTB Mask PCI Slot 0 INTB Mask PCI Slot 0 Interrupt B 0 R W 0 interrupt is available 1 interrupt is masked 2 INTC Mask PCI Slot 0 INTC Mask PCI Slot 0 Interrupt C 0 R W 0 interrupt is available 1 interrupt is masked 3 MPCIO INTD Mask PCI Slot 0 INTD Mask PCI Slot 0 Interrupt D 0 R W 0 interrupt is available 1 interrupt is masked 4 Mask PCI Slot 1 INTA Mask PCI Slot 1 Interrupt 0 R W 0 interrupt is available 1 interrupt is masked 5 Mask PCI Slot 1 Mask PCI Slot 1 Interrupt 0 R W 0 interrupt is available 1 interrupt is masked 6 INTC Mask PCI Slot 1 Mask PCI Slot 1 Interrupt 0 R W 0 interrupt is available 1 interrupt is masked 7 MPCI1_INTD Mask PCI Slot 1 INTD Mask PCI Slot 1 Interrupt D 0 R W 0 interrupt is available 1 interrupt is masked 8 MPCI2_INTA Mask PCI Slot 2 INTA Mask PCI Slot 2 Interrupt A 0 R W 0 interrupt is available 1 interrupt is masked 9 MPCI2_INTB Mask PCI Slot 2 Mask PCI Slot 2 Interrupt B 0 R W 0 interrupt is available
237. es 4 13 1 BCSRO Board Control Status Register 0 15 control register the 8266 It is accessed at offset 0 from BCSR base address It may be read or written at any time BCSR0 gets 1ts defaults upon Power On reset BCSR0O fields are described in Table 4 10 Table 4 10 BCSR0 Description BIT MNEMONIC PBI Function Page Base Interleaving 60X mode i e with L2 Cache this bit should reflect system programmer responsibility the state of bit in PSDMR When active High it changes the address Muxing scheme for the SDRAM so that to match a scheme where Bank Select signals are connected below lower row address lines When Inactive the addressing scheme is such that Bank Select lines are taken from the higher order address lines above row address This signal operates in conjunction to DIMM SIZE signal below In Single MPC8266 Mode i e without L2 Cache this bit has no effect PON DEF ATT 68 1 Provided that BCSR is not disabled MPC8266ADS PCI User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Functional Description Table 4 10 5 0 Description BIT MNEMONIC DIMM SIZE Function Sdram DIMM Size 60X mode ie with L2 Cache this bit in conjunction with above controls the address muxing scheme for the Sdram DIMM When Low
238. es HU OR otal roosi oe ORAS DEAE eR Ree T2L UB IRD a at UE tet 422 UNI Interr pt ee eva weed op ER 4 2 3 Fast Ethernet PHY Interrupt 424 22 lt Clock Generator o a A u EE 43 12 MPG8266C1066K pute ud DUE Rad e pU BR 32 POV COCK an bete dade teet d Bus Configuration lt lt E dur FEES 4 41 Single MPC8266 Mode r 00X BUS MOS 5 E esp va aay ee p ee e n B llepnp qmod eoa cuc Chip Select Gener ator exa oif eR s Synchronous Dram DIMM 60X Bus AT SDRAM Programmi es pa 4 7 2 SDRAM Refresh nea i u 4 73 L2 Cache Support Influence SDRAM Design 4 74 SDRAM DIMM Configuration Information Flash Memory SIMM e kk E pu 4 8 1 Flash Programming Voltage 4
239. escale com Freescale Semiconductor Inc Support Information 02 p a wy 1002 ZZ Tepsen SHOLO3NNOO 2 21001 ezs Tavus 0219 18 Jeylu uS LOLON TX 7 E Y lt 910 5 lt ALdXINIV g z A dXHW1V 810d gt 2 6109 Jno 8 ta 5 0204 Too tad 1204 2 2204 02180 8 909 8204 La E 144 9204 9 9 809 2810 Suu E 0 09 201 Su 05 160 a Su 2104 2 1512 SHU 10 TE TOX SH 00 o3 7055005 Su 86 1094045 94 gt T vas QNO T gt Be svouss lt 9104 7159 009 3199 1904 or 8 154 Ziad P 1 1 4 204 EOXUHI34 z z z IDXHHI3 910 8 Lee d 5 5 5 0204 2 o3 LOX
240. esponsibility to avoid such errors The PCI bus is not buffered at all because the PCI Standard is very strict and defines exactly the electrical characteristics of the bus which is buffer free 4 6 Chip Select Generator The memory controller of the 8266 is used as a chip select generator to access on board and off board memories saving boards area reducing cost power consumption and increasing flexibility To enhance off board application development memory modules including the BCSRx may be disabled via 5 in favor of an external memory connected via the expansion connectors That way a CS line may be used off board via the expansion connectors while its 1 Required for Flash E PROM Interrupt Controller and BCSR 2 An address which is covered in a Chip Select region that controls a buffered device 3 allow a configuration word stored in the Flash E PROM memory to become active MOTOROLA MPC8266ADS PCI User s Manual 53 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Functional Description associated local memory is disabled When a CS region assigned to a buffered memory is disabled via BCSR the local data transceivers are disabled during access to that region avoiding possible contention over data lines The MPC8266 chip select assignments to the various memories registers on the MPC8266ADS PCI are shown in Table 4 5 Table 4 5 MPC8
241. esse SEA x 221459 194 20 FENS Teubrs Shaded 1218592 Dd So ET ZN BEZI 3 9780 1114599 9120 ZOINSHd 104 10 108 8 6 4 0201 e asad Cave 20 sog ear 9 M01 1353 1408 1HO8V 96 E NS d E t 5 t 12 104 4 161908 es zs pm Z d d 06199 09 3 521210 200 Soi 8 vad 3 06 821 08 SO1Nu 8 SOWIvU 01908 78 T OSOWIvU v zd 30 uo SOWOud33u Lug D gt 0159 504 3 t oid 09 Odi 0801 6 LLSH S d 3 60 9 921 08 8501 Sr 122 a Zod 3 7 lt 21 08 lt 21709 WT T lav OMS 0031991 57 Sr ids3unu T 230 DASBH apr 80 sson Sion 221 08 41 08 ySOA DEEE UF TO 121 08 104 d SOA 5 L g vlvdg vr son ZION 6200 8 130 zd J 8200 8 25 lt gt sion Es m 193087 evaa t d 3 7716 220079 093921 WH ig 19 911599 99 8901 80079 ES a 2 qux i ven TSHOdU lt lt
242. ever it still monitors the bus so it can immediately respond when this process ends This signal is connected to the L2 TAG CLR of the MPC2605 but has no function when a cache is not installed on the MPC8266 MB RW 6 31 Reserved Un implemented 4 13 2 BCSR1 Board Control Status Register 1 The is a control register the MPC8266 MB It is accessed at offset 4 from BCSR base address It may be read or written at any time BCSRI gets its defaults upon Power On reset The fields are described in Table 4 11 Table 4 11 BCSR1 Description Function DEF ATT 0 Reserved Un implemented 0 R 1 Provided that BCSR 15 not disabled MOTOROLA MPC8266ADS PCI User s Manual 69 For More Information On This Product Go to www freescale com Functional Description Freescale Semiconductor Inc Table 4 11 BCSR1 Description BIT MNEMONIC FLASH_CS0 Function FLASH CS0 When asserted low CS0 is assigned to the FLASH SIMM CS4 is assigned to When negated 50 is assigned to the E PROM and CS4 is assigned to the FLASH SIMM The assignments selection is done via a dedicated jumper PON DEF ATT ATM EN ATM Port Enable When asserted low the ATM UNI chip PM5350 connected to FCC1 is enabled for transmission and reception When negated the ATM transceiver is in standby mode and its associa
243. evice CLOCK GEN DELOUT rect IN 66 MHZ cLKINI our CLKIN2 4 OUT4 PCI Device OUT3 3 Figure 4 4 PCI Generator Scheme 4 4 Bus Configuration The 8266 may be configured in 2 possible bus modes depending the presence of L2 cache on board 1 Single 8266 Mode 2 60X Bus Mode 4 4 1 Single MPC8266 Mode When a L2 Cache is not present on the board the 8266 is configured in Single MPC8266 Mode I e assuming only 8266 on the 60x bus with no support for external master access This allows for internal address multiplexing to occur which makes the external address multiplexers redundant and therefore not assembled This improves SDRAM performance 4 4 2 60X Bus Mode When L2 Cache is installed on the MPC8266ADS PCI the MPC8266 may no longer operate in single MPC8266 mode since the address must be seen as is by the cache That requires the use of the external address multiplexers for the SDRAM In this mode SDRAM performance is decreased due to added wait state caused by the delay associated with the external multiplexers on 1 access in page 52 MPC8266ADS PCI User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Functional Description NOTE In this mode only devices which are 60x com patible or devices which have 64 bit data b
244. f JP1 then the Fast download JTAG machine may be enabled to precede the 8266 in the JTAG chain When a jumper is placed between positions 2 3 of JP1 the Fast download JTAG machine is bypassed and the TDI input goes directly from the COP JTAG connector P3 to the MPC8266 See also 4 14 1 Fast Download Support on page 78 1 HARD bypass Even when the Fast download logic enabled via JP5 it wakes up asynchronously bypassed 2 Through a noise filtering network MOTOROLA MPC8266ADS PCI User s Manual 13 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Hardware Preparation and Installation should be set between 2 3 if problems are encountered with the use of existing COP JTAG debug equipment since this indicates that its software is not capable of using the fast download machine 1 2 3 1 2 3 Fast Download Enabled Fast Download Disabled Factory Setup Figure 2 7 JP1 TDI Source Selection 2 3 11 SDRAM DIMM IC Slave Address Selection SW2 The SDRAM DIMM has a serial configuration EEPROM which is accessed using Pc protocol Each slave device on that bus has an 7 bit address field 3 of which the LSBs within this device may be set externally Since the SDRAM DIMM configuration is read using the MPC8266 s which required for user s application an option is given to change the SDRAM DIMM configura
245. f the MPC8266ADS PCI 6 DSR Data Set Ready output from the MPC8266ADS PCI 7 N C No connect 8 CTS Clear To Send output from the MPC8266ADS PCI MOTOROLA MPC8266ADS PCI User s Manual 103 For More Information On This Product Go to www freescale com Support Information Freescale Semiconductor Inc Table 7 1 P1 Connector Pin No Signal Name N C No connect Description 7 1 2 P2 100 10 Base T Ethernet port Connector P2 is a RJ 45 Type Connector for Twisted Pair Ethernet as described in Table 7 2 Table 7 2 P2 100 10 Base T Ethernet Connector Pin No Signal Name Description 1 Twisted Pair Transmit Data positive output from the MPC8266ADS PCI 2 TPTX Twisted Pair Transmit Data negative output from the MPC8266ADS PCI 3 TPRX Twisted Pair Receive Data positive input to the MPC8266ADS PCI 4 N C Not connected Bob Smith terminated on the MPC8266ADS PCI 5 6 TPRX Twisted Pair Receive Data negative input to the MPC8266ADS PCI 7 N C Not connected Bob Smith terminated on the MPC8266ADS PCI 8 7 1 3 P3 JTAG Connector P7 is a Motorola standard COP JTAG connector for the 60X processors family It is a 16 pin protected header connector as described in Table 7 3 Table 7 3 P3 COP JTAG Connector Pin No Signal Name Attribute Description TDO O Transmit Data Output This the MPC8266 s serial da
246. formation On This Product Go to www freescale com Freescale Semiconductor Inc Support Information the MPC8266 60X bus 60X system and memory controller signals unbuffered The pinout of these connectors is shown in the schematics For signal description of these connectors see the 8266 User s Manual 7 1 6 P7 P8 P9 PCI Connectors These are 2 X 62 3 3V keyed 32 bit PCI connectors The pinout of each connector is available in Table 7 5 For signal descriptions for these connectors see the PCI v2 2 Standard Table 7 5 P7 P8 P9 PCI Connectors neo Side B Comments Side A Comments 1 12V Not Connected TRST 2 TCK 12V 3 Ground TMS 4 TDO TDI 5 5V 5V 6 5V INTA 7 INTB Not Connected INTC Not Connected 8 INTD Not Connected 5V 9 PRSNT1 Connected to GND Reserved Not Connected 10 Reserved Not Connected 3 3V I O 11 PRSNT2 Connected to GND Reserved Not Connected 12 CONNECTOR 3 3 volt key CONNECTOR 3 3 volt key KEY KEY 13 CONNECTOR 3 3 volt key CONNECTOR 3 3 volt key KEY KEY 14 Reserved Not Connected 3 3 Vaux Not Connected 15 Ground RST 16 CLK 3 3 I O 17 Ground GNT 18 REQ Ground 19 3 3V PME Not Connected 20 AD 31 AD 30 21 AD 29 3 3 MPC8266ADS PCI User s Manual For More Information On This Product Go to www freescale com 113 Support Informati
247. freescale com Freescale Semiconductor Inc Support Information z E Y 5 o o s wg 1002772 ISqu amp moN Tepsen v wounsog eag avus 0219 ua 0 18 2915 18 Y ano ano Be EE ARAE 2255255050002020202255 88 HEDDI P2222 NASL uq uo Durpuedep 80000000922200900000000 222222 22222 zo vx 288 991 440X Ur SON Yr aw 1 1 POL SOSH 101 159 ror suntv 8 N3XIW1VU N3HML 08 agn 59 20110881 cena Y Yi v S TI Wy 1 m AlHdXL oa SOSIWIV any OKNY Olver Hu oY 2 LOX LL 8 zival SS 06 78 50 BAI O
248. ftResetEn RstDebl com amp AbrDebl com only reset button depressed TransRst oe 3 transceivers reset always enabled AtmRstOut_B AtmRst_B fb HardReset IFEthRstOut B FEthRst_B fb 4 HardReset_B Hard reset configuration equations RstConf B oe H RstConf_B L NMI generation equations NMIEn B 0 O D NMIEn RstDeb1 com amp AbrDebl com only abort button depressed k k k local data buffers enable k k k k k k kk k k k kk kk k k equations 148 MPC8266ADS PCI User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information SyncHardReset_B clk SYSCLK SyncHardReset_B ar 0 SyncHardReset_B ap 0 DSyncHardReset_B clk SYSCLK DSyncHardReset_B ar 0 DSyncHardReset_B ap 0 SyncHardReset_B HardReset_B DSyncHardReset_B SyncHardReset_B fb DataBufEn_B oe H DataBufEn_B CsO_B covers also hard reset config ICs4 BrdContRegCs PCIIntContCs_B AtmUniCsOut B provides data hold for write ToolCs1 B ToolCs2 amp IBUFFER HOLD OFF ToolDataBufEn B oe ToolDataBufEn_B ToolCs1 ToolCs2 B amp
249. gh by the MPC8266 while the ATM port is enabled it indicates to the 5350 the start of a new cell over ATMTXD 7 0 i e the 1 st octet is present there When the ATM port is disabled this line may be used for any available function of PA29 MOTOROLA MPC8266ADS PCI User s Manual 107 For More Information On This Product Go to www freescale com Support Information Freescale Semiconductor Inc Table 7 4 P4 CPM Expansion Connector Pin No Signal Name Attribute Description B4 ATMRXEN PA28 T S ATM Receive Enable L When this signal is asserted Low while the ATM port is enabled and ATMRFCLKP goes high on octet of data is available at the PM5350 s ATMRXD 7 0 lines When negated while ATMRFCLK goes high data on ATMRXD 7 0 is invalid however driven When the ATM port is disabled this line may be used for any available function for PA28 B5 ATMRSOC PA27 T S Receive Start Of Cell H When this signal is asserted High while the ATM port is enabled it indicates that the 1754 octet of data for the received cell is available at the PM5350 s ATMRXD 7 0 lines This line is updated over the rising edge of ATMRFCLK When the ATM port is disabled this line is tristated and may be used for any available function for PA27 B6 ATMRCA PA26 T S Receive Cell Available H When this signal
250. guration word stored in the FLASH differs from the one stored in the E PROM in the BPS field which is the Boot Port Size the E7PROM is 8 bits while the FLASH is 32 bits 4 8 1 Flash Programming Voltage Support is given to 5V as well as 12V programmable modules The selection between VPP s voltage levels is done via a dedicated jumper To avoid inadvertent programming or erasure of the Flash it is recommended to leave the jumper open so that no VPP is applied to the Flash SIMM 4 8 2 Flash and L2Cache If the L2 cache is installed the MPC8266 needs to be programmed to 60x bus mode This requires the latches for the buffered address bus to the Flash As well as all other slow static devices to be 60 MPC8266ADS PCI User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Functional Description enabled The 3 lowest order address lines for the Flash are provided by the BADDR 27 29 lines of the MPC8266 However BADRR29 function of the MPC8266 is multiplexed with CI Cache Inhibit function over the same pin Therefore prior to enabling the L2Cache any code residing in the Flash should be moved into the PowerPC bus SDRAM prior to changing BADDR29 function to CI via SIUMCR 49 E2PROM Memory The 8266 is provided with 8 KBytes of E PROM memory in a PLCC package The E PROM resides on a socket in case it is desired to replace or re program a different configura
251. h interface controlled 3 Dual RS232 ports residing amp SMC2 4 12 1 ATM Port To support the MPC8266s ATM controller a 155 52Mbps User Network Interface UNI is provided on board connected to FCC1 of MPC8266 via UTOPIA I F Use is done with PM5350 S UNI 155 ULTRA by PMC SIERA Although these transceivers are capable of supporting 51 84Mbps rate support is given to 155 52Mbps only The control over the transceiver is done using the microprocessor interface of the transceiver controlled by the MPC8266 memory controllers GPCM Since the UNI is 5V powered and the 8266 is 3 3V powered 5V intolerant the UNI is buffered LCX buffers from the MPC8266 on both the receive part of UTOPIA interface and the microprocessor control ports The ATM transceiver may be enabled disabled at any time by writing 0 1 respectively to the ATMEN bit in BCSRx When ATMEN is negated 717 the microprocessor control port is also detached from the 8266 and its associated FCC may be used off board via the expansion connectors The transceiver reset input is driven by HRESET signal of the 8266 so that the UNI is reset whenever a hard reset sequence occurs The UNI may also be reset by either asserting RST bit in BCSRI see Table 4 11 or by asserting 717 the RESET bit in the Master Reset and Identify Load Meters register via the UNI microprocessor interface The UNI transmit and rece
252. has 5 control lines that control its operation and state PWRDWN constantly set to high no power down support on the MPC8266 MB e L2FLUSH assertion of which flushes out the cache array This signal is controlled by BCSRO L2MISS INH in fact Cache Lock When Asserted the cache does not change its contents Controlled by BCSRO L2TAG CLR Clears all tag memory Controlled by BCSRO e L2UPDATE INH In fact cache freeze without information loss Controlled by BCSRO the above signals are connected directly to both cache modules 1 i e residing on the same bus as the processor 2 Only single level is allowed with the MPC8266 3 For minimum 8 Bus clock cycles 64 MPC8266ADS PCI User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Functional Description 4 12 Communication Ports The MPC8266 MB has several communication ports to allow convenient evaluation of the features Obviously it is not possible to provide all types of communication interfaces supported by the CPM but it is made convenient to connect any communication interface devices to the 8266 via the CPM Expansion connectors residing on the edge of the mother board The communication ports interfaces provided on the MPC8266 MB are listed below 1 155 Mbps UNI on with Optical interface using the UTOPIA interface 2 100 10 Base T Port on FCC2 wit
253. he TAP controller state diagram is shown in Figure 4 14 1 In a Suicidal manner 80 MPC8266ADS PCI User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Functional Description Test Logic Reset 1 0 Run Test idle Select IR SCAN Update IR 0 Update DR 0 Figure 4 14 JTAG TAP Controller State Diagram 4 14 1 2 JTAG Instruction Shift Register JISR The instruction shift register is a 3 bit register selected during Shift IR state of the TAP controller The instruction is shifted in during that state while the output of the shift register LSB is driven into MTDO to be concatenated to the next device on the chain the 8266 That way all devices on the JTAG chain may be shifted in with the desired instruction for them When the TAP controller moves into Update IR state the JTAG Instruction register is loaded with the value shifted into JISR During JTAG logic reset the JISR is reset into a default state of Bypass MOTOROLA MPC8266ADS PCI User s Manual 81 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Functional Description 4 14 1 3 JTAG Instruction Register JIR The Instruction register holds the current JTAG instruction which determines the logic operation at any given time The instru
254. hen RS232 Port 2 is disabled this line is tristated and may be used for any available function of PC12 D21 T S MPC8266 s Port C 11 Parallel line May be used to any of its available functions D22 10 T S Fast Ethernet Port Management Data Clock This slow clock S W generated qualifies the management data I O to read write the LXT970 s internal registers When the Ethernet port is disabled this line may be used for any available function of PC10 D23 FETHMDIO PC9 T S Fast Ethernet Port Management Data I O This signal serves as bidirectional serial data line qualified by to allow read write the LXT970 s internal registers When the Ethernet port is disabled this line may be used for any available function of 9 D24 8 T S MPC8266 s Port C 8 0 Parallel I O lines be used to any of their available functions D25 PC7 D26 PC6 D27 PC5 D28 PC4 D29 PC3 D30 PC2 D31 PCI D32 PCO The functions in parenthesis are MPC8266 s parallel I Os Normally connected to ATMTFCLK on the ADS MS bit For that matter both 100 Base T and 10 7 1 5 P5 P6 P10 P11 P13 P14 P16 P18 P19 Logic Analyzer MICTOR Connectors These are 38 pin SMT high density matched impedance connector made by AMP They contain 112 MPC8266ADS PCI User s Manual MOTOROLA For More In
255. hich is in fact a non maskable interrupt making the PPC take the reset exception from the reset vector This line may be driven by the MPC8266 as well during soft reset sequence for 512 system clocks This line is pulled up on the ADS with a resistor When driven externally it MUST be driven with an Open Drain gate Failure to do so may result in permanent damage to the 8266 and or to ADS logic 12 GND O Digital GND Main GND plane 13 HRESET O D MPC8266 s Hard Reset L When asserted by an external H W generates Hard Reset sequence for the MPC8266 During that sequence asserted by the MPC8266 for 512 system clocks Pulled Up on the ADS using resistor When driven by an external tool MUST be driven with an Open Drain gate Failure to do so may result in permanent damage to the 8266 and or to ADS logic 14 N C Not Connected 15 XBR3 CKSTOP_OUT Normally configured as XBR3 which has no function with this connector be configured as CKSTP_OUT Check Stop L When asserted Low indicates that the MPC8266 core has entered a Check Stop state 16 GND Digital GND Main GND plane 7 1 4 4 Expansion Connector 4 is a 128 900 DIN 41612 connector which allows for convenient expansion of the MPC8266 s serial ports This connector contains all CPM pins plus power supply
256. icated for PCI devices which reside on the PCI bus This is a reset to the PCI bus which is initiated by the PCI bus Host the 8266 on this board This reset can also be initiated by a Soft PCI Reset by setting a dedicated bit in a PCI control register consult the MPC8266 User Manual for details 4 2 Local Interrupter There are external interrupts which are applied to MPC8266 via its interrupt controller 1 ABORT NMI 2 ATM UNI interrupt 3 Fast Ethernet PHY Interrupt 4 PCI interrupt 4 2 1 ABORT Interrupt The ABORT NMI is generated by a push button When this button is depressed the IRQO input to the MPC8266 is asserted The purpose of this type of interrupt is to support the use of resident debugger if any is made available to the board This interrupt is enabled by setting the MSR EE bit To support external off board generation of an NMI the IRQO line is driven by an open drain gate This allows for an external h w to also drive this line If an external h w indeed does so it is compulsory that IRQO is driven by an open drain or open collector gate 4 2 2 ATM UNI Interrupt To support ATM UNI User Network I F event report by means of interrupt the interrupt output of the UNI INTB is connected to IRQ7 line of the MPC8266 This IRQ7 input is shared with the Fast Ethernet PHY Interrupt Since INTB of the UNI is an open drain output it is possible to connect additional on and off board interrupt req
257. ill Of Materials Reference C287 C1 Qty 2 Footprint 1812 Description CAP 100nF 500V Manufacturer JOHANSON Part Number Note 501S43W104MV4E C2 C3 C9 C10 C11 C13 C14 C50 C69 C70 C71 C78 C84 C85 C90 C91 C100 C101 110 111 179 183 191 223 231 25 CASE 10uF 25V AVX TAJC106K025R C4 1210 CAP 1nF 2KV AVX 1210B102K202NT 5 6 16 17 23 47 68uF 20 TAJD686M020R C7 C19 C20 C25 C26 C33 C37 C38 C39 C40 C41 C42 C46 C75 C77 C80 C81 C82 C83 C86 C87 C88 C89 C92 C96 C97 C103 C105 C106 C112 C116 C117 C118 C119 C120 C124 C125 C126 C127 C129 C130 C131 C132 C136 C137 C138 C139 C140 C143 C144 C145 C146 C147 C149 C150 C154 C155 C157 C158 C159 C161 C165 C166 C173 C174 C180 C185 C186 68 603 CAP 10nF AVX 06035C103KAT2A C8 C12 C15 C27 C30 C31 C32 C34 C35 C36 C43 C45 C48 C52 C53 C54 C65 C66 CASE D CAP 47uF 16V AVX TAJD476K016 C28 C18 1206 CAP 10pF AVX AV12065A100JATJ C21 C22 C24 C29 C44 C56 57 58 59 60 61 62 C63 C64 C67 C68 C72 C73 C74 C76 C79 C93 C94 C98 99 102 104 107 108 C113 C114 C115 C121 C122 123 133 134 135 141 142 148 151 152 153 156 160 162 163 164 167 168 169 170 172 175 176 177 178 181 182 184 187 188 189 190 192 194 195 196 1
258. inserted MPC8266 PERMANENT DAMAGE might be inflicted to the device JP5 selects only a range of Voltage levels on VDDL The actual level is selected by R26 See next paragraph 2 3 2 Setting VDDL Supply Voltage Level After VDDU s Voltage Level Range is selected via 7 5 the actual level of VDDL is tuned via R26 VDDL may be measured upon JP4 using a DVM or any other high input impedance voltage measuring device VDDL level is factory set at the mid range for the appropriate level range but may be changed via R26 Rotating R26 CCW will reduce VDDL voltage down to range low while rotating it CW MOTOROLA MPC8266ADS PCI User s Manual 9 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Hardware Preparation and Installation will increase VDDL upto range high LD17 provides visual indication for VDDL level it illuminates brighter with rise of VDDL VDDL change Vs R26 s rotation direction is shown in Figure 2 3 R26 AV LOW HIGH Figure 2 3 VDDL Trimmer R26 WARNING While in higher ranges of VDDL and higher rang es of internal operation frequencies the MPC8266 might require some sort of COOLING measures to be taken Failure in doing so might result in PERMANENT DAMAGE inflicted to the 8266 2 3 3 Setting MODCK 1 3 for PLLs Multiplication Factor 5444 6 8 After 1K cycles the negation of the Power On Reset signal the MPC8266 samples the
259. instructions required by JTAG rules to be a part of a JTAG chain while having in fact zero pins This machine includes a serial to parallel interface the serial part is driven by JTAG while the parallel is mapped into the PPC bus embedded in BCSR s memory space This configuration allows zero data overhead during downloads The block diagram of the JTAG system on the board is shown in Figure 4 13 1 No Boundary Scan pins Excluding the I F pins which are not count for that matter 78 MPC8266ADS PCI User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Functional Description TDO TDO gt TMS PORST gt 5 y E TCK A 27 29 R_ W DVAL_ D 0 7 TDI A SN N N 5 5 5 N EM Reg BCSR BUS lt 5 Download Cont Status Reg N N B lt Data Shift Reg Download Data N N N N N N TDI gt N N g
260. ion ua ML OM MM Ad 74 4 22 BCSR3 and BCSR5 Description 75 4 23 TIO I b N 75 4 24 BCSR7 Description stoe dE 75 4 25 COP JTAG Port Signals Description 77 4 26 JTAG Instruction Codes 82 5 1 MPC8266ADS PCI Memory FLASH or BCSR as Boot Device 86 5 2 MPC8266ADS PCI Memory Map E2PROM as Boot Device 88 5 3 FLASH Power On Reset Configuration 91 MPC8266ADS PCI User Manual VII For More Information On This Product Go to www freescale com Freescale Semiconductor Inc List of Tables Confidential Proprietary 5 4 E2PROM Power On Reset Configuration 91 5 5 SIU REGISTERS PROGRAMMING 22 5 6 Memory Controller Initializations For 66Mhz FLASH as Boot Device 92 5 7 Memory Controller Initializations For 66Mhz 2 as Boot Device 93 5 8 Memory Controller Initializations For 66Mhz 95 6 1 Expansion Connectors Maximum Current Consumption 99 6 2 Maximum Power Consumption Per Add In Card 99 7 1 PI Connector
261. ion On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Support Information 02 t wg 1002772 1 Kepsen sid avus 0219 eizieg 15 jeyueus 15 Jojonpuootues BOON fior pero 09 od ein AL 30 by 9 810 8 T 67 30 2 S 9 60 lt geen TI 201 0791 240 1 9 sa 6 po 8 130 518 za 9 OciNH 10 la 110093 SSINH E Y m va ava 9 715 50 xnnas VidDdX3u 8SPNH Er
262. ion Per Add In Card Power Rail Add In Card 5V Max system depended 3 3V 7 6 Max system depended 12V 500mA 12V 100mA MOTOROLA MPC8266ADS PCI User s Manual 99 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Physical Properties 6 1 1 5V Rail Some of the MPC8266 MB peripherals not including the PCI Add In cards which should be 3 3V ONLY on the PCI interface but can use 5V for other components on board reside on the 5V bus Since the MPC8266 is not 5V tolerant buffering is provided between 5V peripherals and the 8266 protecting the MPC8266 from the higher voltage level 6 1 2 3 3V Rail The MPC8266 SDRAM PCI Add In cards address and data buffers are powered by the 3 3 bus which is produced from the ATX power supply 6 1 3 5V Stand By Rail The 5V stand by power rail comes from the ATX Power Supply Its only use is to power the logic required to support the power button in the front panel on the ATX chasis 6 1 4 VDDH Rail The MPC8266 s VDDH power bus 3 3V is produced from the 5V bus using a low voltage drop linear voltage regulator made by Micrel the MIC29501 3 3BU A production option is made so that the level on this bus may be varied by means of trimming potentiometer TR2 However this will requires replacing some components This option allows the VDDH to be in the range of 3 0V 3 6V 6 1 5 VDDL Bus The MPC8266
263. ion space The MPC8266 also includes an on chip Arbiter which enables arbitration of up to three PCI masters Only three PCI slots are supported on the MPC8266 MB because of the Arbiter capacity Each slot can host either a PCI master or PCI target The MPC8266 as a Bridge can support more PCI devices but that will require extra slots that can host PCI targets only Therefore to avoid 1 As well as all other slow static devices 62 MPC8266ADS PCI User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Functional Description dedicated slots for PCI targets only three slots are implemented The PCI Bridge is implemented on the PQ2 Local Bus Due to PCI Standard restrictions no other application can reside on the local bus The PCI bus can operate at frequencies of 25MHz up to 66MHz 3 3V only The 3 3V restriction is due to the MPC8266 which is not 5V compliant The PCI bus layout is shown in Figure 4 9 Special care was taken when the layout of the MPC8266ADS PCI was done so that the PCI standard recommendations are followed strictly Main Clock 66MHz JTAG PCI Clock z z MPC8266 Clock PCI Clock EE le PCI Clock Distribution 5 5 Ly CLKINI CLKIN2 4 PCI Clock 2 W W W oO A EN 5 PCI Arbitr gt gt gt
264. is asserted High while the port is enabled and ATMRFCLK goes high it indicates that the PM5350 s receive FIFO is either full or that there are 4 empty bytes left in it PM5350 internal programming dependent When the ATM port is disabled this line is tristated and may be used for any available function of PA26 B7 ATMTXDO 25 ES Transmit Data 7 0 When port is enabled this bus carries the ATM cell octets written to the PM5350 s transmit FIFO This B8 PA24 bus is considered valid only when is asserted and are sampled on the rising edge of ATMTFCLK B ATMTXD2 2 2 pom When the ATM port is disabled these lines may be used for any B10 ATMTXD3 PA22 available respective function ATMTXDA 21 12 5 20 B13 ATMTXD6 PA19 B14 ATMTXD7 PA18 15 ATMRXD7 PA17 T S ATM Receive Data 7 0 When the ATM port is enabled this bus carries the cell octets read from the PM5350 receive FIFO This lines 16 ATMRXD6 16 updated rising edge of 7 5 15 When port 15 disabled these lines are tristated and may be used for any available respective function B18 ATMRXD4 PA14 19 13 20 2 12 21 ATMRXDI 22 10 108 MPC8266ADS PCI User s Manual MOTOROLA For More Information On
265. ive clocks are fed with a 19 44 MHz 20 ppm clock generator 5 V powered while the receive and transmit fifos clocks of the UTOPIA interface are provided by the MPC8266 The MPC8266 can provide the same clock for both UTOPIA transmit and receive or separate clocks for each hard configured The ATM SAR is connected to the physical medium by an optical interface Use is done with HP s HFBR 5205 optical interface which operates at 1300 nm with upto 2 Km transmission range 4 12 2 100 10 Base T Port A fast Ethernet port with T P 100 Base TX I F is provided on the MPC8266 MB This port also supports 10 Mbps ethernet 10 Base T via the same transceiver the LXT970 by Level One 1 Using resistors MOTOROLA MPC8266ADS PCI User s Manual 65 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Functional Description The LXT970 is connected to FCC2 of the MPC8266 interface which is used for both devices control and data path The initial configuration of the LXT970 is done be setting the desired values at 8 configuration signals FDE CFG 0 1 and MF 0 4 The MF 0 4 pins however are controlled by 4 voltage levels this to allow each pin to configure two functions On the MPC8266 MB these pins are driven by factory set resistors connected to a voltage divider allowing future option change during production The LXT970 reset input is driven by HRESET sign
266. ive since the PCI_MODCK 0 3 take presidency a For L2 Cache Boards b Applies only ONCE after power up reset MOTOROLA MPC8266ADS PCI User s Manual For More Information On This Product Go to www freescale com 45 Freescale Semiconductor Inc Functional Description The PCI configuration registers which are set at Hard Reset sequence are shown in Figure 4 1 0 Reserved Address Offset Hex Device ID 0 18 0 Vendor ID 0x1057 00 os Address Register Figure 4 1 PCI Host Configuration Registers 4 1 3 Soft Reset Soft Reset may be generated on the board from the below sources 1 COP JTAG Port 2 Manual Soft Reset 3 Internal MPC8266 source Soft Reset when generated causes the MPC8266 to reset its internal logic while keeping its hard reset configuration and memory controller setup and then jumping to the Reset vector in the exception table Since soft reset does not reset the refresh logic for dynamic RAMS their contents is preserved SRESET when asserted is extended internally by the MPC8266 for an additional 512 bus clock cycles at the end of which the 8266 waits for 16 bus clock cycles and then re checks the state of the SRESET line SRESET is an open drain signal and must be driven with an open drain gate by every external source driving it Otherwise contention will occur over that line which might cause permanent damag
267. k SlotOIntCMask SlotOIntDMask SlotlIntAMask Slot1IntBMask Slot 1IntCMask MOTOROLA MPC8266ADS PCI User s Manual 161 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information Slot1IntDMask Slot2IntAMask Slot2IntBMask Slot2IntCMask Slot2IntDMask Add A27 A29 Data DO D11 Reset B SoftReset B counter counter7 counter6 counter5 counter4 counter3 counter2 counter counterO countera countera7 countera6 countera5 countera4 countera3 countera2 counteral counteraO k kk k k k k Power On Reset definitions 5 0 PON RESET PORIn RESET Register Access definitions IntReg ADD 0 IntMaskReg ADD 1 VGR WRITE IntReg IntContCs B amp DVal B amp R amp A27 amp 28 6 A29 WRITE IntMaskReg IntContCs B 4 DVal B amp amp A27 amp 28 amp A29 READ IntReg lIntContCs B amp B amp A27 amp A28 amp A29 READ IntMaskReg IntContCs B amp W amp A27 amp 28 6 A29 Interrupt Request Definitions IrqOe SlotOIntA fb SlotOIntB fb SlotOIntC fb 162 MPC8266ADS PCI User s Manual MOTOROLA For
268. k modes of the MPC8266 core cpm bus PCI Selection between the MODCK 1 3 combination options is done by means of dip switches Section 2 3 3 on the mother board while PCI MODCKH 0 3 are obtained from the relevant dedicated pins by means of dip switches Section 2 3 6 when the 8266 is in active PCI mode determined by the state of PCI MODE pin If the PCI is set to be inactive the MODCKH 0 3 bits are obtained from the Hard Reset Configuration Word in the Flash or in the E PROM depends on who is the boot device The configuration master is determined upon the rising edge of PORST according to the state of RSTCONF Section 2 3 5 signal driven low this board to set the MPC8266 as a configuration master After power on reset negates the hard reset sequence starts during which many other different MOTOROLA MPC8266ADS PCI User s Manual 39 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Functional Description options are configured see Section 4 1 2 4 Hard Reset Configuration on page 41 among these options are additional clock configuration bits PCI MODCKH 0 3 the most significant bits of the MODCK field which determine additional options for the clock generator Although these bits are sampled whenever the hard reset sequence is entered they are influential only once after power on reset If a hard reset sequence is entered later MODCKH 0 3 although
269. l 155 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information JtagReceiveFull JtagReceiveFull fb maintain value Receive Full Flag Reset SReadJtagDownloadData clk SYSCLK SReadJtagDownloadData ar 0 SReadJtagDownloadData ap 0 SReadJtagDownloadData READ_JTAG_DOWNLOAD_DATA 6 DVal_B JtagReceiveFullReset SReadJtagDownloadData fb Trst_B IPORIn B JtagResetState fb Selection equations Tdo clk Tck Tdo ar 0 Tdo ap JtagStateReset when STATE JTAG SHIFT IR then JtagShiftIR2 fb else when STATE JTAG SHIFT DR amp INST IS BYPASS then Tdo JtagShiftDRO fb else when STATE_JTAG_SHIFT_DR amp INST_IS_DOWNLOAD then Tdo JtagReceiveFull fb when STATE_JTAG_ENABLED then TdoOut Tdo fb else when STATE_JTAG_ENABLED then TdoOut Tdi TdoEnable STATE_JTAG_ENABLED amp JtagTdoEnable fb 156 MPC8266ADS PCI User s Manual For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Support Information ISTATE JTAG ENABLED TdoOut oe TdoEnable com kk kk k k Power On Reset Generation equations PonResetOut oe 1 PonResetOut INST IS PON RESET Auxiliary functions
270. l Identification 09 3 These lines should be driven by an external tool with the Tool Identification Code to be read via BCSR2 of B17 EXTOLII the ADS These lines are pulled up on the ADS by 10 resistors See B18 EXTOLI2 also Table 4 12 BCSR2 Description on page 71 B19 EXTOLI3 B20 N C Not Connected B21 EXP3 3V O 3 3V Power Out These lines are connected to the main 3 3V plane of the PQ2PCIAI ADS this to provide 3 3V power where necessary for B22 external tool connected B23 B24 118 MPC8266ADS PCI User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information Table 7 8 P17 System Expansion Connector Pin No Signal Name Attribute Description B25 Not Connected B26 EXPVCC 5V Supply Connected to ADS s 5 plane Provided as power supply for external tool B27 B28 B29 B30 B31 B32 GND O Digital Ground Connected to main GND plane of the ADS C2 CLK8 Buffered System Clock C3 GND O Digital Ground Connected to main GND plane of the ADS C4 BTOOLCSI O Buffered Tool Chip Select 1 L This is a buffered MPC8266 s CS6 line reserved for an external tool C5 BTOOLCS2 O Buffered Tool Chip Select 2 L This is a buffered MPC8266 s CS7 line reserved for an external tool GND Digital Ground Connected to main GND plane
271. l TH GND BRIDGE 100mil PRECIDIP PD 999 11 11010 JP7 JP8 JP9 JP10 4 2P TH HEADER 2Px1ROW MOLEX 87156 4003 J1 J2 J3 J4 J5 J6 J7 7 5mm TH GND BRIDGE 5mm PRECIDIP PD 999 11 11210 LD1 LD2 LD4 LD7 LD8 LD9 11 LED LED GREEN KINGBRIGHT KPT 3216SGD LD10 LD11 LD12 LD18 LD19 LD3 LD6 LD13 LD14 LD15 6 LED LED YELLOW KINGBRIGHT KPT 3216YD LD16 LD5 1 LED RED KINGBRIGHT 32161 1017 1 LED RED KINGBRIGHT KPT 3216YD L1 L2 L3 L4 L5 5 FERRITE FERRITE BEAD FAIR RITE 2743021447 P1 1 Stacked 9P D CON 9P DUAL EDA 8LE009009D306H Type P2 1 8P 100mil TH CON RJ45 MOLEX 43202 8110 P3 1 16P 2x8 SMD CON 16P HEADER KCC LPH 16SA SG P4 P17 2 128P_DIN_FEM_c CON DIN 128 ERNI 23762 onn_90 P5 P6 P10 P11 P13 P14 9 MICTOR38 CON MICTOR 38P 2 767004 2 16 18 19 P7 P8 P9 3 PCI 2x60 TH CON PCI 32BIT AMP 145154 4 P12 1 10X2 HEADER CON 20P ATX PWR MOLEX 39 29 9202 P15 1 10P 2x5 SMD HEADER 5Px2ROWS SAMTEC TSM 10501 SDV AP Q1 1 08 DUAL 5 SEMICONDUCTOR MMDF4N01HD RN1 RN2 RN3 RN4 RN5 RN6 14 0603X4 RES 8P 4R DALE CRA06S0803430JRT RN7 RN8 RN15 RN23 RN25 RN26 RN38 RN45 RN9 RN10 RN11 RN12 RN13 28 0603X4 RES 8P 22 AVX 4 220 RN14 RN16 RN17 RN18 RN19 RN20 RN21 RN22 RN24 RN27 RN28 RN29 RN30 RN31 RN32 RN33 RN34 RN35 RN37 RN40 RN42 RN43 RN44 RN36 RN39 RN41 3 4X0603 RES NET 8P 4R 0ohm DALE CRA06S0803000RT Not L2Cache RS1 RS2 RS3 RS4 RS5 RS6 27 10P 8R RES NET 10P 8R ROHM RS8A1002J RS7 RS8 RS9 RS
272. lotOIntA_ Active if Reset amp SlotOInt PON DEFAULT Slot0IntA_Active Reset amp B then SlotOIntA Active else Slot0IntA_ Active k k k k k k 166 MPC8266ADS PCI User s Manual For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Support Information state diagram SlotOIntB state SlotOIntB Active if Reset amp SlotOIntB DEFAULT SlotOIntB Active Reset amp PCI INTB B then ISIotOIntB Active else SIotOIntB Active state SlotOIntB Active if Reset amp SlotOIntB DEFAULT SlotOIntB Reset amp B then SIotOIntB Active else ISIotOIntB Active state diagram SlotOIntC state SlotOIntC Active if Reset amp SlotOIntC DEFAULT SlotOIntC Active Reset amp PCI INTC B then ISlotOIntC Active else SlotOIntC Active state SlotOIntC Active if Reset amp SlotOIntC DEFAULT Slot0IntC_Active Reset amp B then SlotOIntC Active else ISlotOIntC Active 24 1 2 RR RK RR R K state diagram SlotOIntD state SlotOIntD Active if
273. ls connection carrying also necessary bus signals for transceivers connection Use is done with 2 X 128 pin DIN 41612 receptacle connectors External Tools identification amp status read capability via BCSR Separate Power On Reset Push Button Soft Hard Reset Push Button and ABORT Push Button ATX Power Supply 1 BCSR controlled for 60x bus mode 2 Hard reset is applied by depressing BOTH Soft Reset amp ABORT buttons 4 MPC8266ADS PCI User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc General Information Multi Range MPC8266 internal logic operation voltage determined at production between three ranges 1 7V to 1 9V 1 8V to 2 0V or 2 3V to 2 7V currently changeable within a range Software Option Switch provides 8 S W options via BCSR e COP JTAG connector for MPC8266 MOTOROLA MPC8266ADS PCI User s Manual 5 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PCI Slot 33 66Mhz 3 3V 33 PCI Slot 33 66Mhz 3 3 60x Bus 4 OPTIONAL Actors PCI Slot 33 66Mhz 3 3V 5 gt 3 3V 5 SDRAM DIMM 16 64 MB
274. ly There are 4 power rails with the 8266 1 2 3 4 VDDH VDDL Internal Logic VCCSYN CPM PLL VCCSYNI Core PLL and there are 5 power rails on the MPC8266 MB 1 98 uo ert 5V Stand 5 V rail V3 3 33V rail VDDL 1 7V 2 5V rail 12V rail MPC8266ADS PCI User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Physical Properties 6 12V rail PCI Connectors MPC8266 MB Logic amp Peripherals 5V 3 3V Expansion Con VCCSYN VCCSYN1 VDDL VDDH ATX Power Supply z MPC8266 Figure 6 1 8266 Power Scheme To support off board application development the power buses are connected to the expansion connectors so that external logic may be powered directly from the board The maximum current allowed to be drawn from the board on each bus also depends on the current drawn by the PCI bus The figures are shown in Table 6 1 Table 6 1 Expansion Connectors Maximum Current Consumption Power Bus Max Current VCC TBD V3 3 TBD The PCI Standard specifies that each Add In card should consume maximum 25Watt from all power sources combined The maximum current consumption allowed per power source for a total of 25Watt according to the PCI Standard is shown in Table 6 2 Table 6 2 Maximum Power Consumpt
275. mnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and rea sonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part Motorola and are registered trademarks of Motorola Inc Motorola Inc is an Equal Opportunity Affirmative Action Employer M For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table of Contents Table of Contents Section 1 General Information 1 1 IntrOdU OM Moers uya OR VOR Edo iR EY 1 1 2 Definitions Acronyms and Abbreviations 2 1 3 Related Documentation 2 LA Specifications sesir eae RVRCERT EE EEG 3 1 5 MPC8266ADS PCI Features 3 Section 2 Hardware Preparation and Installation 2 1 Introduction Re ya 7 2 2 Unpacking 222 qne Ene esr eue une rus 7 2 3 Hardware Preparation 8 2 LIU aa 7 2 3 1 Setting
276. n JP1 JP5 n R26 21 SW2 SW3 Figure 2 1 MPC8266ADS PCI Top Side Part Location Diagram 8 MPC8266ADS PCI User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Hardware Preparation and Installation 2 3 1 Setting VDDL Level Range JP5 To support future revisions of the MPC8266 provisions are taken to provide necessary voltage levels on VDDL to match the process by which MPC8266 is manufactured Via JP5 three voltage level ranges are provided JP5 setting options are shown in Figure 2 2 1 When a jumper is placed between positions 1 2 of JP5 a level range of 2 3V to 2 7V on VDDL is selected This level matches the current specification for the MPC8260 Hip3 2 When a jumper is placed between positions 2 3 of JP5 a level range of 1 7V to 1 9V on VDDL is selected This level range is a preparation for the next revision of the MPC8266 Hip4 3 When a jumper is misplaced for JP5 a level range of 1 8 to 2 0 is selected for VDDL This is in preparation for 2V capable future devices JP5 JP5 JP5 E DE 1 7V 1 9V 2 3V 2 7V 1 8 2 0V Figure 2 2 VDDL Range Selection JP5 WARNING JP5 is Factory Set according to the revision of MPC8266 with which it is assembled Prior to changing a MPC8266 device Extra Care should be taken with JP5 setup If a selected Voltage Range is above the specification for the newly
277. n 6 Physical Properties 6 1 6 2 POWER SUDDIy Li dete E IH EDI OD T sasa AY 98 oO p SV a 100 61525 Rail SV neo ea LU vost oe 100 91 3 Stand By Ratlla 100 E E M SG 100 6 155 VDDE BUS ect kaqqa a 100 O 62 dires ura 100 ORI neto AS atteso m d Exp doe uU Ede 100 COMME CONS u s ARA TE E DIS 101 6 21 ATX Power Connector xdi 101 MPC8266ADS PCI User Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table of Contents 6 2 2 Fast Ethernet Port 101 6 2 3 155 Port Connection 101 624 URS 232 Pons COnnecior eda e e s 101 6 2 5 CPM Expansion Connector 101 6 2 6 Port Connector 101 627 Logic Analyzer Connectors 102 6 2 8 Mach s In System Programming ISP Connector 102 0 29 PCICOnnegtorS i556 9 xx S 4E Eu HER y ROGER CA AU 102
278. n to HPs 16500 Logic Analyzers series for debugging purposes a set of dedicated connectors is provided Use is done with 38 pin SMT high density matched impedance MICTOR connectors made by AMP These connectors carry the unbuffered 60X signals and should be placed as near to the MPC8266 as possible to provide short PCB routes yielding better reflections and crosstalk immunity They do not carry the PCI bus signals due to the restrictions enforced by the PCI Standard There are also connectors for the CPM signals 6 2 8 Mach s In System Programming ISP Connector This is a 10 pin generic 0 100 pitch header connector providing In System Programming capability for Vantis made programmable logic on board 6 2 9 PCI Connectors A set of three standard PCI 3 3V keyed 124 pin 32 bit connectors is provided for connecting up to three PCI Add In cards 6 2 10 System Expansion Connector The System Expansion Connector is 128 pin DIN 41612 connector which provides a minimal system F required to interface to other tool boards which may use the CPM Expansion Connector This connector contains 16 bit lower PPC bus address lines 16 bit higher PPC bus Data lines plus useful GPCM and UPM control lines 6 3 PCB Layout The MPC8266 MB layout was done in a manner suitable for high frequency operation and it follows closely the PCI Standard layout recommendations Following is a list of measures which are taken to meet this design goal
279. nd PBI information to provide the correct address lines to the sdram dimm Tn this 5 Rev PILOT 03 21 99 Pinout changed to M4 64 32 7VC TQFP48 package n this file 6 Rev Pilot 01 20 00 Changed polarity of SdramA8 9 11 since there is an inversion fromthe Q Device declaration Pins declaration 2 Control pins Ale 5 180 MPC8266ADS PCI User s Manual For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Support Information RCB PIN 1 DimmSize 2 PBI PIN 3 Address Input lines row A6 PIN 37 A7 PIN 38 8 39 9 40 10 PIN 44 45 col A20 PIN 46 Address Output lines SdramA8 PIN 9 istype com SdramA9 PIN 24 istype 11 PIN 23 istype Auxiliary Pins Latched Address lines 6 istype reg D buffer LA7 istype reg D buffer 8 istype reg D buffer
280. nector as described in Table 7 6 Table 7 6 P12 ATX Power Supply Connector Pin Signal Pin Signal 1 3 3VDG 11 3 3VDC Sense 2 3 3VDG 12 12VDC 3 Groung 138 Groung 4 5VDC 14 Power_On 5 Groung 15 Groung 6 5VDC 16 Groung 7 Groung 17 Groung 8 Power_OK 18 5VDC 9 5VStand_By 19 5VDC 10 12VDC 20 5VDC 7 1 8 P15 Mach Lattice ISP Connector This is a 10 pin generic 0 100 pitch header connector providing In System Programming ISP MOTOROLA MPC8266ADS PCI User s Manual For More Information On This Product Go to www freescale com 115 Freescale Semiconductor Inc Support Information capability for Latice made programmable logic on board The pinout of P15 is shown in Table 7 7 Table 7 7 P15 Lattice ISP Connector Pin No Signal Name Attribute Description 1 ISPTCK I ISP Test port Clock This clock shifts in out data to from the programmable logic JTAG chain 2 N C Not Connected 3 ISPTMS I ISP Test Mode Select This signal qualified with ISPTCK changes the state of the prog logic JTAG machine 4 GND O Digital GND Main GND plane 5 ISPTDI I ISP Transmit Data In This is the prog logic s JTAG serial data input sampled on the rising edge of TCK 6 5V power supply bus 7 ISPTDO O ISP Transmit Data Output This the prog logic s JTAG serial data output driven by Falling edge of TCK
281. ng low line during IDLE time or b using a dedicated interrupt line FDS MDINT which may also serve as Full Duplex indication This line is connected to MPC8266 s DP7 CSE1 IRQ7 line appearing also at the CPM expansion connectors After the LX970 is reset the FDS MDINT pin wakes up as FDS rather than MDINT and therefore MUST be initially programmed to MDINT function by setting 17 1 bit otherwise IRQ7 may be constantly driven low possibly generating interrupts to the MPC8266 if not masked properly Since IRQ7 may also be driven by any tool connected to the expansion connectors it should be driven with an Open Drain buffer IRQ7 is pulled up on the board 4 12 3 RS232 Ports To assist user s applications and to provide convenient communication channels with both a terminal and a host computer two identical RS232 ports are provided on the MPC8266 MB connected to 5 1 and SCC2 ports of the MPC8266 Use is done with MC145583 transceiver which generates RS232 levels internally using a single 3 3V supply and has a standby mode When the RS232EN1 RS232EN2 bits BCSRI are asserted low the corresponding 1 Also known as MII MDIO port 2 Not supported on the board 66 MPC8266ADS PCI User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Functional Description transceiver is enabled When negated the corresponding trans
282. ntC PON DEFAULT Slot1IntC Active SlotlIntD PON DEFAULT SlotlIntD Active Slo2Int PON DEFAULT Slo2IntA Active MOTOROLA MPC8266ADS PCI User s Manual 163 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information Slo2IntB PON DEFAULT Slot2IntB Active Slo2IntC PON DEFAULT Slot2IntC Active Slo2IntD PON DEFAULT Slo2IntD Active ILL mec Data Bits Assignments SlotOIntA DATA D0 SlotOIntB DATA D1 SlotOIntC DATA D2 SlotOIntD DATA 03 SlotlIntA DATA D4 SlotlIntB DATA 05 SlotlIntC DATA D6 SlotlIntD DATA 07 Slo2IntA DATA D8 Slot2IntB DATA D9 Slot2IntC DATA BIT D10 Slo2IntD DATA D11 PCI Interrupt Mask Register definitions SlotOIntAMask Active 1 PCI Slot 0 Interrupt Masked SlotOIntBMask Active 1 PCI Slot 0 Interrupt B Masked SlotOIntCMask Active 1 PCI Slot 0 Interrupt C Masked SlotOIntDMask Active 1 PCI Slot 0 Interrupt D Masked SlotlIntAMask Active 1 PCI Slot 1 Interrupt A Masked Slot1IntBMask Active 1 PCI Slot 1 Interrupt B Masked Slot1IntCMask A
283. o 77 2 8 2 1220 miso 5 oon y NOA NIA var 18005620171 IMEZSLEZOIN V quo qe n asen aren asp SeIXOWL 5 5 5 5 L 1 280 080 80 180 31 2 avaa 5 oven T Yau SOA quo 5 we T 9rd i 35 1 4 SON 99 g 2 8 E g 8 2 5 8 0015 109 3T 8015 9001 tT 129 m 2 bi 2 bu 2 9 194 4 1 4 4 has ou awa lt Tawa 99 99 99 9 z z 5 47 6101 qe A6 T AL I 34001 e 08 Ls oezo 8901 m lt 4 4 TNASOOA Te __ eso 7 oe 1 NIA 34001 T 8 gar EENT seol a lt SOA anor 39001 3900 MPC8266ADS PCI User s Manual For More Information On This Product 208 Go to www freescale com Support Info
284. o a dedicated debug station for extensive system debug There are several third party debug solutions on the market These debug stations may be connected to the host computer via either Ethernet Parallel Port RS232 or any other media The debug station connection scheme is shown in Figure 4 11 Ethernet Parallel ADS RS232 USB 16 Wire Media 0 0 Media To COP 4 0 lat Cable Figure 4 11 Debug Station Connection To support debug station connection to the COP JTAG port a 16 pin generic header connector is provided on the MPC8266 MB carrying the COP JTAG signals as well as additional signals aiding in system debug The pinout of this connector which is a general Motorola recommendation for including a COP JTAG port in a design is shown in Figure 4 12 and detailed in Table 4 25 TMS SRESET HRESET CKSTP OUT Figure 4 12 COP JTAG Port Connector 1 Not provided with the MPC8266 MB 76 MPC8266ADS PCI User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Functional Description Table 4 25 COP JTAG Port Signals Description Pin No Signal Name TDO Attribute Description Transmit Data Out This the JTAG s serial data output driven by Falling edge of TCK N C Not Connected TDI Transmit Data In This is the JTAG serial da
285. o sk k state diagram RS232En1_B state RS232 1 ENABLE if WRITE BCSR 1 amp RS232 1 ENABLE DATA RS232 1 ENABLE amp IPON RESET RS232 1 ENABLE PON DEFAULT RS232 1 ENABLE PON RESET amp RS232 1 ENABLE PON DEFAULT RS232 1 then IRS232 1 ENABLE else RS232 1 ENABLE state 5232 1 ENABLE if WRITE BCSR 1 amp RS232 1 ENABLE DATA RS232 1 ENABLE amp RESET RS232 1 ENABLE PON DEFAULT RS232 1 ENABLB PON RESET amp RS232 1 ENABLE PON DEFAULT RS232 1 then RS232 1 ENABLE else IRS232 1 ENABLE Gs sk 9k sk sk E oR state diagram RS232En2 B state RS232 2 ENABLE if WRITE BCSR 1 amp RS232 2 ENABLE DATA RS232 2 ENABLE amp RESET RS232 2 ENABLE PON DEFAULT RS232 2 ENABLE PON RESET 4 RS232 2 ENABLE PON DEFAULT RS232 2 then IRS232 2 ENABLE else RS232 2 ENABLE state RS232 2 ENABLE if WRITE BCSR 1 amp RS232 2 ENABLE DATA BIT pin RS232 2 ENABLE amp RESET RS232 2 ENABLE PON DEFAULT RS232 2 PON RESET amp RS232 2 ENABLE PON DEFAULT RS232 2 ENABLB then RS232 2 ENABLE else RS232 2 ENABLE k k k
286. of the ADS C7 ATMEN Port Enable L This line enables the port UNI s output lines towards the MPC8266 An external tool using the same pins as does the ATM port should consult this signal before driving the same lines Failure to do so might result in permanent damage to the PM5350 ATM UNI C8 ATMRST O ATM Port Reset L This signal resets the ATM UNI PM5350 An external tool may use this sienal to its benefit C9 FETHRST O Ethernet Port Reset L This signal resets the LXT970 Ethernet transceiver An external tool may use this signal to its benefit C10 HRESET O D MPC8266 s Hard Reset L When asserted by an external H W generates Hard Reset sequence for the MPC8266 During that sequence asserted by the MPC8266 for 512 system clocks Pulled Up on the ADS using a 1KQ resistor When driven by an external tool MUST be driven with an Open Drain gate Failure to do so might result in permanent damage to the MPC8266 and or to ADS logic IRQ6 I Interrupt Request 6 L Connected to MPC8266 s DP6 CSE0 IRQ6 signal Pulled up on the ADS with a 10 resistor This line is shared with the UNT s interrupt line and therefore when driven external tool MUST be driven with an Open Drain gate Failure to do so may result in permanent damage to the MPC8266 or to ADS logic MOTOROLA MPC8266ADS PCI User s Manual 119 For More Information On This Product Go to www freescale com Freescale
287. olled Hard Reset Configuration Word MOTOROLA MPC8266ADS PCI User s Manual 11 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Hardware Preparation and Installation When a jumper is placed between positions 1 2 of JP3 the Hard Reset Configuration source is a memory FLASH EEPROM as configured by switch SW3 1 When a jumper is set between positions 2 3 of JP3 the Hard Reset Configuration source is the BCSR See Figure 2 5 FLASH EEPROM is Hard Reset BCSR is Hard Reset Configuration Source Configuration Source Factory Setup Figure 2 5 Hard Reset Configuration Source Selection JP3 2 3 5 Setting Boot Source The Hard Reset configuration word read by the MPC8266 while HRESET is asserted may be taken from three sources 1 Flash Memory SIMM 2 EEPROM 3 BCSR For additional information as for the contents of the Hard Reset configuration word see 4 1 2 4 Hard Reset Configuration on page 41 SW3 1 actually assignes CSO to the FLASH default when booting from the BCSR or to the EEPROM When SW3 1 is OFF the Hard Reset configuration word is taken from EEPROM when it is ON the Hard Reset configuration word is taken from the Flash SIMM See Figure 2 6 0 FLASH PCI PCI DLL PCI DLL OFF PCI CONFIG 3 PCI CONFIG 3 SW3 F
288. om the Jtag Download Data Register this bit is cleared This bit is also cleared by either Power On Reset JTAG TAP Reset asserted TRST and by JTAG TAP reset state This bit is Read Only writing it has no effect 8 31 Reserved Un Implemented 4 13 7 BCSR7 Board Control Status Register 7 BCSR7 is used as the JTAG Fast Download I F data register Although it resides only over D 0 7 lines of the PPC data bus it is accessed as word at offset 0x1C from BCSR base During download the host loads this register with serial data through the JTAG I F The download agent running on the board should after polling the asserted JTAG_RX_FULL flag read the data in this register and write it to board s memory BCSR7 is described in Table 4 24 Table 4 24 BCSR7 Description BIT MNEMONIC Function EON ATT DEF 0 7 JTAG_DOWNLO JTAG Data Data shifted into the JTAG Download Data register may be 0 R AD_DATA read here This is a read only field Writes have no effect 8 31 Reserved Un Implemented MOTOROLA MPC8266ADS PCI User s Manual 75 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Functional Description 4 14 COP JTAG Port The COP Control Observation Port is part of the MPC8266 s JTAG machine implemented as set of additional instructions and logic within the JTAG permissions This port may be connected t
289. on Freescale Semiconductor Inc 114 Table 7 5 P7 P8 P9 PCI Connectors Pin Number Side B Comments Side Comments 22 Ground AD 28 23 27 AD 26 24 AD 25 Ground 25 3 3 AD 24 26 3 IDSEL 27 AD 23 3 3 28 Ground AD 22 29 AD 21 AD 20 30 AD 19 Ground 31 3 3V AD 18 32 AD 17 AD 16 33 C BE 2 3 3V 34 Ground FRAME 35 IRDY Ground 36 3 3V TRDY 37 DEVSEL Ground 38 Ground STOP 39 LOCK Not Connected 3 3V 40 PERR SDONE Not Connected 41 3 3V SBO Not Connected 42 SERR Ground 43 3 3V PAR 44 C BE 1 AD 15 45 AD 14 3 3 46 Ground AD 13 47 AD 12 48 AD 10 Ground 49 M66EN Coupled to GND AD 09 using 0 01 capacitor 50 Ground Ground 51 Ground Ground MPC8266ADS PCI User s Manual For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Support Information Table 7 5 P7 P8 P9 PCI Connectors 2 Side Comments Side Comments 52 AD 08 C BE 0 53 AD 07 3 3V 54 3 3V AD 06 55 AD 05 AD 04 56 AD 03 Ground 57 Ground AD 02 58 01 AD 00 59 3 3V I O 3 3V I O 60 ACK64 Not Connected REQ64 Not Connected 61 5V 5V 62 5V 5V 7 1 7 P12 ATX Power Supply Connector This is a standard ATX Form Factor Power Con
290. on PPC bus OR5 FFFF8E36 32K Byte block size delayed CS assertion early CS and WE negation for write cycle relaxed timing 7 w s for read 8 for write extended hold time after read BR8 PCI Interrupt Controller PPC 04731801 Base at 04730000 32 bit port size no parity on bus OR8 FFFF8010 32 KByte block size all types access 1 w s MOTOROLA MPC8266ADS PCI User s Manual 35 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Operating Instructions Table 3 8 Memory Controller Initializations For 66Mhz Reg Device Type Bus TS Description PSDMR SDC2UV6482C 84 PPC 416EB452 Bank Based Interleaving Refresh enabled normal 16 MByte operation code address muxing mode 1 A 15 17 on Single BNKSEL 0 2 A9 on PSDAIO 7 clocks refresh 82 recovery 3 clocks precharge to activate delay 2 clocks 66 activate to read write delay 4 beat burst length 1 clock Bus last data out to precharge 1 clock write recovery time Mode no extra cycle on address phase normal timing for control lines 2 clocks CAS latency 2 452 Page Based Interleaving Refresh enabled normal operation code address muxing mode 2 19 on BNKSEL2 on PSDA10 7 clocks refresh recovery 3 clocks precharge to activate delay 2 clocks activate to read write delay 4 beat burst length 1 clock last data out to precharge 1 clock write recovery time no extra cycle on address
291. or More Information On This Product Go to www freescale com Freescale Semiconductor Inc Functional Description a From TS Asserted First access may be longer due to internal pipeline delay b Not including arbitration overhead 4 7 1 SDRAM Programming After power up the SDRAM needs to be initialized by means of programming to establish its mode of operation The SDRAM is programmed according to the following procedure 1 Issue Precharge All command 2 Issue 8 CBR refresh commands 3 Issue MODE SET command An SDRAM is programmed by issuing a Mode Register Set command During that command data is passed to the Mode Register through the SDRAMs address lines This command is fully supported by the SDARM machine of the MPC8266 Before that can take place the SDRAM machine of the 8266 has to be initialized Mode Register programming values are shown in Table 4 7 Table 4 7 66 MHz SDRAM DIMM Mode Register Programming SDRAM DRAMM Address 5 ode Value Meaning E Reg Field Line A11 MSB Reserved 0 10 Reserved 0 9 0 1 0 Burst Read amp Burst Write Copy Back data cache 1 Burst Read amp Single Write Write Through Data cache A8 Reserved 0 Reserved 0 4 CAS Latency 010 Data Valid 2 Clocks cycles after CAS Asserted Burst 0 Sequential Burst A2 A0 Burst Length 011 8 Burst Length a Act
292. ormal timing for control lines 2 clocks CAS latency C372B452 Page Based Interleaving Refresh enabled normal operation code address muxing mode 2 A 16 17 on BNKSEL 1 2 on 1 7 clocks refresh recovery 3 clocks precharge to activate delay 2 clocks activate to read write delay 4 beat burst length 1 clock last data out to precharge 1 clock write recovery time no extra cycle on address phase normal timing for control lines 2 clocks CAS latency MOTOROLA MPC8266ADS PCI User s Manual 95 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Memory and Initialization Table 5 8 Memory Controller Initializations For 66Mhz Reg Device Type SDC2UV6482C 84 16 MByte DIMM_SIZE in BCSRO should be Cleared SDC8UV6484C 84 64 MByte DIMM_ SIZE should be Set in BCSRO Bus PPC 60 Bus Mode Init Value hex 416 45 PBI BCSRO should be Cleared Description Bank Based Interleaving Refresh enabled normal operation code address muxing mode 1 A 15 17 on BNKSEL 0 2 9 on PSDA10 7 clocks refresh recovery 3 clocks precharge to activate delay 2 clocks activate to read write delay 4 beat burst length 1 clock last data out to precharge 1 clock write recovery time extra cycle on address phase normal timing for control lines 2 clocks CAS latency 2 45 PBI BCSRO
293. ory a osea ce poche D ed obe o agre det va sake 26 MPC8266 Register Programming 30 341 System 31 3 4 2 Memory Controller Registers Programming 32 MPC8266ADS PCI User Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table of Contents Section 4 Functional Description 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 4 10 4 11 4 12 Reset lt fost oi eta etie ta Power ou caza ayq Eee ei 4 1 1 1 Power On Reset Configuration 41 2 Hard Reset n lea ___________ 4 1 2 1 COP JTAG Port Hard Reset 4 1 2 2 Manual Hard Eee 4 1 2 3 Internal Sources Hard Reset 4 1 2 4 Hard Reset Configuration 3 e uy c 4 1 3 1 COP JTAG Port Soft Reset 4 1 3 2 Manual Soft Reset 4 1 3 3 Internal Sources Soft Reset AAA POCLBus Reset a nam uh at
294. ory Installation snin ve gra d ed xa de E DH A dts 18 2 4 6 1 Flash Memory SIMM Installation 18 2 4 6 2 SDRAM DIMM Installation 19 MOTOROLA MPC8266ADS PCI User Manual For More Information This Product Go to www freescale com Freescale Semiconductor Inc Table of Contents Section 3 Operating Instructions 3 1 3 2 3 3 3 4 IMtrOdUCHIONT s fet uuo te Y a 21 Controls and Indicators 21 3 2 1 Power On RESET 5 51 21 322 LABORI 5 52 bana 21 923 SOBPRTRESET SSitelis EX NEMO YEA 21 3 24 HARD RESET Switches S2 amp S3 21 3 2 5 SW3 Reset Configuration Switch 22 3 2 6 SW2 SDRAM DIMM Configuration Memory 2 Slave Address Switch 22 3 27 SWI Software Options Switch eee eee Yee ee tees 22 3 2 8 JP5 VDDL Voltage Level Range Selection 22 3 2 9 JP6 IDDL Measurement 22 3 2 10 JP2 Thermal Sense Connector 22 3 2 11 JP7 Optional Ventilator 23 3 2 12 COP JTAG TDI Source Selection 23 3
295. p Slot IntDMask fb Slot2IntA fb amp Slot2IntAMask fb Slot2IntB fb amp Slot2IntBMask fb Slot2IntC fb amp Slot2IntCMask fb Slot2IntD fb amp Slot2IntDMask fb PCI IrqOe amp Open Drain output IPCI IRQ B PCI Interrupt Interrupt Request shows after OE Generating PowerOn signal to the Power Supply equations invl inv5 com generating internal clock oscilator inv2 linvl com inv3 inv2 com 178 MPC8266ADS PCI User s Manual For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Support Information inv4 inv3 com inv5 inv4 com counter ar 0 counter ap 0 counter clk inv5 com when counter fb 255 then counter 0 else counter counter countera ar 0 countera ap 0 countera clk counter fb 0 when countera fb 255 then countera 0 else countera countera 1 Power Bufferar 0 Power 0 Power Buffer clk countera fb 0 Power Buffer ChasisPowerlIn PowerOn B oe PowerOn B ar 0 PowerOn B ap 0 PowerOn B clk Power Bufferfb Flip Flop toggles everytime the chassis PowerOn H power pushbutton is pressed ifdef SIMULATION END 7 2 3 923 SDRAM MUX LATCH
296. phase normal timing for control lines 2 clocks CAS latency SDC8UV6484C 84 412EB452 Bank Based Interleaving Refresh enabled normal 64 MByte operation code address muxing mode 1 A 13 15 on BNKSEL 0 2 9 on PSDAIO 7 clocks refresh recovery 3 clocks precharge to activate delay 2 clocks activate to read write delay 4 beat burst length 1 clock last data out to precharge 1 clock write recovery time no extra cycle on address phase normal timing for control lines 2 clocks CAS latency C372B452 Page Based Interleaving Refresh enabled normal operation code address muxing mode 2 A 16 17 on BNKSEL 1 2 on 1 7 clocks refresh recovery 3 clocks precharge to activate delay 2 clocks activate to read write delay 4 beat burst length 1 clock last data out to precharge 1 clock write recovery time no extra cycle on address phase normal timing for control lines 2 clocks CAS latency 36 MPC8266ADS PCI User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Operating Instructions Table 3 8 Memory Controller Initializations For 66Mhz Reg Device Type SDC2UV6482C 84 16 MByte DIMM_SIZE in BCSRO should be Cleared SDC8UV6484C 84 64 MByte DIMM_ SIZE should be Set in BCSRO Bus PPC 60X Bus Mode Init Value hex 416EB45A PBI in BCSRO should be Cleared Description
297. pins to provide for easy tool connection as described in Table 7 4 Table 7 4 P4 CPM Expansion Connector Pin No Signal Name Attribute Description 1 RS RXDI PD31 T S When 5232 port 1 is enabled this signal is the receive data line for that port When this port is disabled this signal is tristated and may be used to any available alternate function for PD31 MOTOROLA MPC8266ADS PCI User s Manual 105 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information Table 7 4 P4 CPM Expansion Connector Pin No Signal Name Attribute Description A2 RS TXDI PD30 T S When RS232 port 1 is enabled this signal is the transmit data line for that port When this port is disabled this signal may be used to any available alternate function for PD30 A3 PD29 I O T S MPC8266 s Port D 29 line Parallel or CPM dedicated line May be used for any of it s available functions 4 RS_RXD2 PD28 T S When RS232 port 2 is enabled this signal is receive data line for that port When this port is disabled this signal is tristated and may be used to any available alternate function for PD28 A5 RS TXD2 PD27 8 When RS232 port 2 is enabled this signal is the transmit data line for that port When this port is disabled this signal may be used to an
298. possible to disable it by software 3 2 4 HARD Switches S2 amp 3 When BOTH switches 52 and 53 are depressed simultaneously HARD reset is generated to the 8266 When the MPC8266 is HARD reset all its configuration is lost including data stored in the SDRAMs and MPC8266 has to be re initialized Except for Hard Reset configuration word which is acquired only once after PON Reset MOTOROLA MPC8266ADS PCI User s Manual 21 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Operating Instructions 3 2 5 SW3 Reset Configuration Switch SW3 is a 4 switch Dip Switch For its function see Section 2 3 5 3 2 6 SW2 SDRAM DIMM Configuration Memory I C Slave Address Switch SW2 sets the slave address for the SDRAM DIMM s serial configuration memory For its function see Section 2 3 11 3 2 7 51441 Software Options Switch SWI is 4 switch Dip Switch This switch is connected over SWOPT 0 2 lines which are available at BCSR2 S W options may be manually selected according to SW1 state 5 is factory set to all ON See Figure 3 1 SWOPTO Pulled to 1 SWOPTO Driven to 70 SWOPTI Pulled to 1 SWOPTI Driven to 0 SWOPT 2 Pulled to 71 SWOPT2 Driven to 0 RESERVED SWI Figure 3 1 SW1 Description 3 2 8 5 VDDL Voltage Level Range Selection JP3 selects between 3 different voltage lev
299. r Inc Operating Instructions 3 Operating Instructions 3 1 Introduction This chapter provides necessary information to use the MPC8266ADS PCI in host controlled and stand alone configurations This includes controls and indicators memory map details and software initialization of the board 3 2 Controls and Indicators The MPC8266ADS PCI has the following switches and indicators 3 2 1 Power On RESET Switch S1 The Power On RESET switch S1 performs Power On reset to the 8266 as if the power was re applied to the ADS When the 8266 is reset that way all configuration and all data residing in volatile memories are lost After PORST signal is negated the 8266 re acquires the power on reset and hard reset configuration data from the hard reset configuration source Flash EEPROM BCSR 3 2 2 ABORT Switch S2 The ABORT switch is normally used to abort program execution this by issuing a level 0 interrupt to the MPC8266 If the ADS is in stand alone mode it is the responsibility of the user to provide means of handling the interrupt since there is no resident debugger with the MPC8266ADS PCI The ABORT switch signal is debounced and may be disabled by software 3 2 3 SOFT RESET Switch S3 The SOFT RESET switch S2 performs Soft reset to the MPC8266 internal modules maintaining MPC8266 s configuration clocks chip selects and SDRAMs contents The switch signal is debounced and it is not
300. rature 10 C 30 C room temperature Storage temperature 25 C to 85 C Relative humidity 5 to 90 non condensing Dimensions Length Width Thickness 12 305 mm 9 229 mm 0 063 1 6 mm 1 5 MPC8266ADS PCI Features 64 bit MPC8266 Communication Processor MPC8266 running 66MHz external bus frequency with PCI module functioning as Host Bridge e 16 MByte Unbuffered 168 pin Synchronous Dram DIMM residing on 60X bus controlled by SDRAM machine 1 Support for upto 64 MBytes DIMM single bank only for the 64 MBytes DIMM Optional address Latch Multiplexer is required if a cache MOTOROLA MPC8266ADS PCI User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc General Information module is assembled Support for Automatic DIMM Identification via MPC8266 port and DIMM s serial E PROM Support for PBI Page Based Interleaving in both Single and 60x bus modes Optional 1 2 MByte L2 Cache on board using 2 MPC2605 Look Aside cache modules 8 MByte 80 pin Flash SIMM buffered from 60X bus Support for upto 32 MByte controlled by GPCM 5V 12V Programmable with Automatic Flash SIMM identification via BCSR Support for both On and OFF SIMM Flash reset 5V 12V VPP in circuit programming voltage for Flash SIMM jumper selectable 8 KBytes E PROM buffered from the 60x bus controlled by the GPCM
301. re starts at 166MHz Actually not relevant when the PCI is active since the PCI MODCK 0 3 take presidency 45 a For L2 Cache Boards b Applies only ONCE after power up reset MOTOROLA MPC8266ADS PCI User s Manual For More Information On This Product Go to www freescale com 43 Freescale Semiconductor Inc Functional Description Table 4 2 2 Hard Reset Configuration Word Data Prog Offset In Field Bus Value Implication Flash Bits Bin Hex Value Hex ERB 0 0 Internal Arbitration Selected 0 04 148 1 0 Internal Memory Controller CSO active at system boot CDIS 2 0 Core Enabled EBM 3 071 0 Single MPC8266 Mode for boards without L2Cache 1 60X Bus Mode for boards with L2Cache BPS 4 5 01 8 Bit Boot Port Size CIP 6 0 Sets Core Initial Prefix MSR IP 1 so that system exception table is placed at address OxFFF00100 regardless of FLASH memory size ISPS 7 64 bit internal space for external master accesses In fact don t care on this board since external master is not supported L2CPC 8 9 10 CI BADDR 29 IRQ2 selected as BADDR 29 8 B2 WT BADDR 30 IRQ3 selected as BADDR 30 L2 HIT IRQ4 selected as unassigned CPU BG BADDR 31 IRQ5 as BADDR 31 DPPC 10 11 41 Data Parity Pin configuration as DPO as EXT_BR2 DP1 as EXT_BG2 DP2 as EXT_DBG2 DP3 as EXT_BR3 DP4 as EXT_BG3 DP5 as EXT_DBG3
302. rmation Freescale Semiconductor Inc T S 995 960 i HOIH 3 IHN SHW HW 154 OLHW b 2 SH SHIOH S NILNDOW SISVHO XIV z 7 s 02 10 02 19945 1002 912 Z AlddNS ev 2 sequin stswio 8AH9dz0d 4 v 1 1 n 1 NOILOSNNOO AS 194 199 OSA 194 SISVHO NIVW SNOILVNOISSG STIVA auo trot LJ UJ 8 a 9r vr 5 NIVW auo P LS LA A oss aavan aat Lory SISVHO aw orar T S8AS SON M XIV 209 Go to www freescale com MPC8266ADS PCI User s Manual For More Information On This Product MOTOROLA Support Information Freescale Semiconductor Inc 7 3 22 Bill of Materials The following is the Of Materials for the MPC8266ADS PCI including L2Cache option Table 7 9 MPC8266ADS PCI B
303. rnet port is enabled this clock 25 MHz for 100 Mbps 2 5 MHz for 10 Mbps is normally extracted from the received data and driven to the MPC8266 to qualify out coming transmit data In Slave mode not used with this application this clock should be input to the LXT970 When the Ethernet port is disabled this line is tristated and may be used for any available function of PC18 015 17 5 MPC8266 s Port C 17 15 Parallel I O lines May be used to any of their available functions D16 PC16 D17 PC15 MOTOROLA MPC8266ADS PCI User s Manual 111 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information Table 7 4 P4 CPM Expansion Connector Pin No Signal Name Attribute Description D18 RS_CD1 PC14 T S RS232 Port 1 Carrier Detect L Connected via RS232 transceiver to RS232 DTR18 input allowing detection of a connected terminal to this port This line is simply a input line to the MPC8266 When RS232 Port 1 is disabled this line is tristated and may be used for any available function of PC14 D19 PC13 I O T S MPC8266 s Port C 13 Parallel I O line May be used to any of its available functions D20 RS CD245 12 ES RS232 Port 2 Carrier Detect L Connected RS232 transceiver to RS232 DTR2 input allowing detection of a connected terminal to this port This line is simply a PI O input line to the MPC8266 W
304. roduct Go to www freescale com Freescale Semiconductor Inc Functional Description 4 14 1 5 Download Control and Status Register This register has no direct JTAG access however it enables the operation of this machine and contains status information set by this machine It is available on the PPC Bus memory map designated as BCSR6 For further information on BCSR6 see Table 4 23 and Table 4 23 4 14 1 6 Bypass Register The bypass register is a single stage register which must exist in any JTAG implementation Its purpose is to shorten the scan chain as much as possible for a device residing on the scan chain When the JIR contains the BYPASS code and the TAP controller is in Shift DR state this register is placed between TDI TDO pair of this machine Any un implemented instruction with this machine defaults to the BYPASS instruction 4 14 1 7 JTAG Machine Bypass There are 3 levels of bypass for this JTAG implementation this to provide compatibility with earlier versions of this board and debug tools The bypass options are 1 Hard wired Bypass When a jumper is set between positions 2 3 then the TDI input to the VADS is connected directly to the TDI input of the MPC8266 This allows compati bility with existing debug tools which do not support the use of this machine and might suffer from added delay on TDI 2 Asynchronous Bypass After Power On Reset when a jumper is set between positions 1 2 factory set this
305. s associated SCC1 pins may be used off board via the expansion connectors 3 2 31 RS232 Port 2 ON LD16 When the yellow RS232 Port 2 ON led is lit it designates that the RS232 transceiver connected to P1B lower DB9 connector is active and communication via that medium is allowed When darkened it designates that the transceiver is in shutdown mode and its associated SCC2 pins may be used off board via the expansion connectors 3 2 32 VDDL Indication LD17 The green VDDL indicator led LD17 is lit to indicate a VDDL power activity Since VDDL level may vary LD17 s illumination level also varies accordingly 3 3 Memory All accesses to MPC8266ADS PCI s memory slaves are controlled by the MPC8266 s memory controller Therefore the memory map is reprogrammable to the desire of the user After Hard Reset is performed by the debug station the debugger checks for existence size delay and type of the SDRAM DIMM and FLASH memory SIMM mounted on board and decides on the assignments of CSO and CS4 2 and FLASH and programs the memory controller accordingly The SDRAM E PROM and the FLASH memory respond to all types of memory access 1 problem supervisory program data and DMA This memory map is a recommended memory map and since it is a soft map devices address may be moved about the map to the convenience of any user There are actually two memory maps which depend on the device assigned to CSO regar
306. s internal logic and the PLL are powered with a lower voltage power source voltage of which may be in 3 ranges of levels 2 3V 2 74 1 7 1 9V 1 8V 2 0 Selection between the above range levels is done via a jumper which selects between different resistor values within the VDDU s variable regulator feedback network while the fine tuning within a range is done by means of a trimming potentiometer Changing the voltage to the Core logic of the MPC8266 obviously has an influence over the maximal speed of the core There is the power speed trade off 1 lower operation speeds may be obtained with lower voltage supply 6 1 6 12V Rail The 12V bus from the ATX Power Supply supports the PCI slots and the VPP 12V option from programming the FLASH 6 1 7 12 Rail The 12V bus from the ATX Power Supply supports the PCI slots 100 MPC8266ADS PCI User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Physical Properties 6 2 Connectors The MPC8266 MB has connectors attached to serve the following functions Logic Analyzer Connectors 1 Power Supply 2 100 10 Base T Ethernet port 3 155Mbps port 4 RS232 port 1 5 RS232 port 2 6 CPM Expansion 7 COP JTAG 8 9 Programmable logic In System Programming ISP 10 PCI Connectors 11 System Expansion 6 2 1 ATX Power Connector The ATX power connector is a 20 lead standard AT
307. sed 16 Kbyte and 32 Kbyte devices can also be used so it appears repeatedly in 8Kbyte multiples starting from FFF00000 5 2 The MPC8266 provides the following functions on the MPC8266ADS PCI 1 System functions which include PPC Bus SDRAM Controller Local Bus Host to PCI Bridge Chip Select generator 2 Communication functions which include ATM SAR Fast Ethernet controller UART for terminal or host computer connection MPC8266 Register Programming The internal registers of the MPC8266 must be programmed after Hard reset as described in the following paragraphs The addresses and programming values are in Hexadecimal base For more information on the following initializations see the MPC8266 User s Manual 90 MPC8266ADS PCI User s Manual For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Memory Map and Initialization 5 2 1 System Initializations The Power On Reset Configuration word is set in the FLASH or in the There two configuration words one for the FLASH when it is assigned to CSO and the other to the when it is assigned to CSO The two configurations are detailed in Table 3 3 and Table 3 4 respectively Table 5 3 FLASH Power On Reset Configuration Flash Init Address Description Value hex hex 0 0C aC Internal arbitration Internal memory controller
308. sent Save packing material for storing and reshipping of equipment CAUTION AVOID TOUCHING AREAS OF INTEGRATED CIRCUITRY STATIC DISCHARGE CAN DAMAGE CIRCUITS 2 3 Hardware Preparation To select the desired configuration and ensure proper operation of the MPC8266ADS PCI board changes of the Dip Switch settings may be required before installation The location of the switches indicators Dip Switches and connectors is illustrated in Figure 2 1 The board has been factory tested and is shipped with Dip Switch settings as described in the following paragraphs MOTOROLA MPC8266ADS PCI User s Manual 7 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Hardware Preparation and Installation Parameters can be changed for the following conditions e MPC8266 s Internal Logic Supply Level Range Via e MPC8266 s Internal Logic Supply Level within range VDDL Via R26 e MPC8266 s MODCK 1 3 Determining Core s and CPM s PLLs multiplication factor via SW4 e MPC8266 s Boot Source or Memory FLASH EEPROM MPC8266 s HARD Reset Configuration Source FLASH EEPROM SW3 e MPC8266 s MODCKH 0 3 via SW4 e MPC8266 s PCI MODCK SW4 MPC8266 s PCI ARBITER SW3 e MPC8266 s PCI DLL SW3 e MPC8266 s JTAG s TDI Source Selection 1 1 SDRAM DIMM s Slave Address via SW2 ATX Chassis Main AC Power Selectio
309. serted low 4 2 4 PCI Interrupt Each PCI slot can generate up to four interrupts to a total of twelve 3 slot x 4 interupts each Each PCI expansion board can generate an interrupt at any given time Since there is only one interrupt input available in the MPC8266 an Interrupt Controller is used The Interrupt Controller receives all the possible interrupts from the PCI slots and generate one interrupt IRQ6 to the 8266 simple generic Interrupt Controller is implemented using a CPLD device The Interrupt Controller is implemented as an Interrupt Register and an Interrupt Mask Register The Interrupt Controller has its own dedicated chip select line CS8 A simple priority scheme is devised to prioritize the interrupts from different slots The PCI IRQ routing are according to Figure 4 2 8266 0 1 2 ADDRESS CONTROL Interrupt Controller Figure 4 2 PCI Interrupt Routing Scheme An interrupt request any of the INTx lines will set three interrupt bits in the PCI Interrupt 48 MPC8266ADS PCI User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Functional Description Register if not masked in the Interrupt Mask Register since there are three possible interrupt sources for every INTx line It is up to the user to implement a polling process to verify the real interrupt source by polling the Interrupt Pending bi
310. should be Set Page Based Interleaving Refresh enabled normal operation code address muxing mode 2 19 on BNKSEL2 on PSDA10 7 clocks refresh recovery 3 clocks precharge to activate delay 2 clocks activate to read write delay 4 beat burst length 1 clock last data out to precharge 1 clock write recovery time extra cycle on address phase normal timing for control lines 2 clocks CAS latency 412 45 PBI BCSRO should be Cleared Bank Based Interleaving Refresh enabled normal operation code address muxing mode 1 A 15 17 on BNKSEL 0 2 A9 PSDA10 7 clocks refresh recovery 3 clocks precharge to activate delay 2 clocks activate to read write delay 4 beat burst length 1 clock last data out to precharge 1 clock write recovery time extra cycle on address phase normal timing for control lines 2 clocks CAS latency C372B45A PBI in BCSRO should be Set Page Based Interleaving Refresh enabled normal operation code address muxing mode 2 A 16 17 on BNKSEL 1 2 on 1 7 clocks refresh recovery 3 clocks precharge to activate delay 2 clocks activate to read write delay 4 beat burst length 1 clock last data out to precharge 1 clock write recovery time extra cycle on address phase normal timing for control lines 2 clocks CAS latency LSDMR 0 No SDRAM on Local Bus which is used for Bus ONLY PSRT Al Bus Supported Sdram PPC 21
311. siaav 619 eia LZ oeddy yLaava 619 eia LZ SZLXOTPL 02 210 zia 5 eradyg 02 210 52 Laav lt 8200 8 8200 2 00 8 SL zrady 9 5 010 ora L2 12009 019 grzn Seaava 60 92009 9L 60 50 01009 180 52 sadya 180 55 96 9 im ELEQLLATWEL iM z IMU 18 Ho Pr 22 c vean 220074 99 2007 7008 90 Sd 5 S vi Da 810058 50 22 28 50 a aav lt s S Tou am 81009 za zady geen 00 oa quo lt 00 17 id 7 a o 3000 1001 3400 200 1001 5 lt haona E z aso uso 820 eso eso pozo veen 5 V 09 F c 821 0191 T 18800988 EU aun lt ava gt Uo 9 mp pesn sr T c ST N 21 019 24 9 gt foor foor fuor Poor foor z pozo oun uvas ZD Bel V Tr 59
312. ster3 amp 5 74 4 13 6 BCSR6 Board Control Status 6 75 4 13 7 BCSR7 Board Control Status 7 75 4 14 Port 25534 et ER buc e o ERE x ior ato a 76 4 14 1 Fast Download Support 78 4 14 1 1 JTAG TAP Controller 80 4 14 1 2 JTAG Instruction Shift Register 5 81 4 14 1 3 JTAG Instruction Register JIR 82 41414 Data Shift 82 4 14 1 5 Download Control and Status Register 83 4 14 1 6 Bypass Register 83 4 1417 JTAG Machine Bypass 83 4 14 1 8 Fast Download Operation 83 4 14 1 9 Generated Power On 84 4 15 Switches Jumpers and Indicators 84 Section 5 Memory Map and Initialization 5 1 Memory Map ker 86 52 8266 Register Programming 22220 eel p e EI RR 90 22221 System Dmtializatlolis y ood ee ae esee ive 91 5 2 2 Memory Controller Registers Programming 92 Sectio
313. t o exo 18 jexueug 181 2 8 25999898 EJON DS me FPORHHH SA SVV 82224444444444424242424228428428 78979 GaN ANOOISY gt gt gt gt gt gt gt gt gt gt gt gt gt gt 85007 ZNO 3NOO1SUU PIV 135305 80000000000000000000000000000000 135308 13S3tH 888455288 5 09598358 ecu 206 158047 OV 1040 9 mE MV zy isu 287 11989 87 2139 104 2 1 m WAIN v1o OoO0o0O0o0o000O00000000000000000000wm9N EE 9 soas goena 2140 svuas LE SIND Nd K 7275
314. t Go to www freescale com Freescale Semiconductor Inc Support Information Table 7 4 P4 CPM Expansion Connector Pin No Signal Name Attribute Description C30 GND O Digital Ground Connected to main GND plane of the ADS C31 C32 DI PC31 T S MPC8266 s Port 31 22 Parallel I O lines May be used to any of their available functions D2 PC30 D3 PC29 D4 PC28 05 27 06 26 D7 PC25 D8 PC24 D9 PC23 D10 PC22 ATMTFCLK PC21 5 ATM Transmit FIFO Clock Upon the rising edge of this clock driven by the 8266 while the port is enabled the cell octets are written to the PM5350 s transmit FIFO This clock samples ATMTXD 7 0 ATMTXPTY ATMTXEN and ATMTSOC When the ATM port is disabled this line may be used for any available function of PC21 D12 PC20 T S MPC8266 s Parallel I O Port C 20 Parallel I O line May be used for any of its available functions D13 FETHRXCK PC19 T O T S Fast Ethernet Receive Clock When the Ethernet port is enabled this clock 25 MHz for 100 Mbps 2 5 MHz for 10 Mbps is extracted from the received data and driven to the MPC8266 to qualify incoming receive data When the Ethernet port is disabled this line is tristated and may be used for any available function of PC19 D14 FETHTXCK PC18 T S Fast Ethernet Transmit Clock When the Ethe
315. t Bypass 5 N N N 4 N 5 5 Inst Shift Reg N N gt 4 Inst Reg lt Decode N 5 amp Cont 3 Power On 4 Reset Logic N N N N N N N N N N TAP Cont TMS gt S 5 TRST N gt __ 5 N DATA mmm N TCK CONT w Figure 4 13 Fast Download JTAG System As can be seen in the figure above the JTAG machine includes the following components 1 TAP Controller 2 Instruction Shift register 3 Instruction register MOTOROLA MPC8266ADS PCI User s Manual 79 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Functional Description 4 Data Shift register Download Data register 5 Download Command and Status register 6 Bypass register 4 14 1 1 JTAG TAP Controller The Test Access Port controller 15 a standard 16 state controller Its transitions are determined by the state of TMS upon rising edge of TCK The state Test Logic Reset may be reached synchronously according to rising TCK from any state by simply driving TMS high for 5 consecutive rising edges of TCK The test logic is also reset asynchronously by either driving TRST low by the debug station or by Power On Reset generated by the board s Power Up SW1 depressed or by this logic T
316. t indicates that the receive medium is non idle When the Ethernet port is disabled this line may be used for any available function of PB26 C7 FETHTXD3 PB25 T S Fast Ethernet Transmit Data 3 0 This is the transmit data bus The 8266 drives these lines according to rising edge of FETHTXCK C8 FETHTXD2 PB24 When the ethernet port is disabled these lines may be used for any C9 PB23 available respective function C10 22 C11 FETHRXDO PB21 T S Fast Ethernet Receive Data 3 0 This is the receive data bus The LXT970 drives these lines according to rising edge of FETHRXCK C12 FETHRXDI PB20 When the ethernet port is disabled these lines are tristated and may be C13 FETHRXD2 PB19 used for any available respective parenthesized function 14 FETHRXD3 18 C15 17 5 MPC8266 s Port B 17 4 Parallel lines May be used to any of their available functions C16 PB16 C17 PB15 C18 14 19 13 20 12 C21 11 22 10 C23 PB9 C24 PB8 C25 PB7 C26 C27 PB5 C28 PB4 C29 ATMRCLK O T S ATM Receive Clock A divide by 8 of the ATM line clock recovered by the ATM receive logic Provided to assist Circuit Emulation Tool Enabled only when pin A29 of this connector is either not connected or driven low Otherwise Tri stated 110 MPC8266ADS PCI User s Manual MOTOROLA For More Information On This Produc
317. t 4 1 These lines are connected to the Flash SIMM presence detect lines which encode the type of Flash SIMM mounted on the Flash SIMM socket For the encoding of FLASH PD 4 1 see Table 4 14 a There is additional bit to this field See next on the same table MOTOROLA 1 Provided that BCSR is not disabled MPC8266ADS PCI User s Manual For More Information On This Product Go to www freescale com 71 Functional Description Freescale Semiconductor Inc Table 4 13 FLASH Presence Detect 7 5 Encoding Table 4 14 FLASH Presence Detect 4 1 Encoding FLASH_PD 7 5 FLASH DELAY nsec 000 Not Supported 001 150 010 100 120 011 80 90 100 70 101 111 Not Supported FLASH_PD 4 1 Flash TYPE SIZE Technology 0000 SM73288XG4JHBGO 32 MByte 4 banks of 4 X 2M X 8 by Smart Modular Technology 0001 SM73248XG2JHBGO 16 MByte 2 banks of 4 X 2M X 8 by Smart Modular Technology 0010 SM73228XG1JHBGO 8 MByte 1 bank of 4 X 2M X 8 by Smart Modular 0011 1111 Not Supported Table 4 15 EXTOOLI 0 3 Assignment EXTTOOLI 0 3 External Tool 0 T ECOM MPC8266 Communication tool 1 Reserved 2 T1 Circuit Emulation Tool 3 E Reserved F Tool Non Existent 72 MPC8266ADS PCI User s Manual For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Func
318. t in the PCI device and clear the other two The PCI Interrupt Register be read at any time and accessed at offset from CS8 base address The description of the PCI Interrupt Register is in Table 4 3 Table 4 3 PCI Interrupt Register Description PON BIT MNEMONIC Function DEF ATT 0 PCIO INTA PCI Slot 0 INTA PCI Slot 0 Interrupt A 0 R 0 no interrupt was requested 1 interrupt was requested and waiting to be handled 1 PCI Slot 0 PCI Slot 0 Interrupt 0 R 0 no interrupt was requested 1 an interrupt was requested and waiting to be handled 2 INTC PCI Slot 0 INTC PCI Slot O Interrupt C 0 R 0 no interrupt was requested 1 interrupt was requested and waiting to be handled 3 PCIO INTD PCI Slot 0 INTD PCI Slot 0 Interrupt D 0 R 0 no interrupt was requested 1 an interrupt was requested and waiting to be handled 4 INTA PCI Slot 1 INTA PCI Slot 1 Interrupt A 0 R 0 no interrupt was requested 1 interrupt was requested and waiting to be handled 5 INTB PCI Slot 1 INTB PCI Slot 1 Interrupt B 0 R 0 no interrupt was requested 1 an interrupt was requested and waiting to be handled 6 INTC PCI Slot 1 INTC PCI Slot 1 Interrupt C 0 R 0 no interrupt was requested 1 interrupt was requested and waiting to be handled J PCI1_I
319. tEn TransRst AtmRstOut B FEthRstOut BJ Rst1 RstO Abr Abr1 Abr0 Debounce RstDeb1 AbrDeb1 SyncReset SyncHardReset B DSyncHardReset RstCause PORIn_B Rst1 Rst0 Abr1 Abr0 HoldOffCnt HoldOffCnt2 HoldOffCnt1 HoldOffCnt0 _ F_PD4 F_PD3 F_PD2 F_PD1 Cs Cs0_B Cs4_B BrdContRegCs_B PCIIntContCs_B AtmUniCsIn_B ToolCs1_B ToolCs2_B BufEn DataBufEn_B ToolDataBufEn_B ConfAdd A27 A28 ifndef L2CACHE CfgByteO 0 0 0 0 1 1 0 0 130 MPC8266ADS PCI User s Manual For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Support Information CfgBytel 1 0 1 1 0 0 1 0 CfgByte2 0 0 0 0 0 1 1 0 CfgByte3 0 0 0 0 0 0 0 0 Gifdef L2CACHE CfgByteO 0 0 0 1 1 1 0 0 CfgBytel 1 0 1 1 0 0 1 0 CfgByte2 0 0 0 0 0 1 1 0 CfgByte3 0 0 0 0 0 0 0 0 k k k Power On Reset definitions 5 0 PON RESET S PORIn B fb PON RESET ACTIVE Register Access definitions BCSRO_ADD 0 BCSR1_ADD 1 BCSR2_ADD 2 BCSR3_ADD 3 BCSR4_ADD 4 VGR_WRITE_BCSR_0 BrdContRegCs B amp DVal_B amp R_B_W amp A27 amp A28 amp A29 VGR_WRITE_BCSR_1 BrdContRegCs_B amp DVal_B amp R_B_W amp A27 amp A28
320. ta input sampled by the MPC8266 on the rising edge of TCK This line is pulled up internally by the MPC8266 TRST Test port Reset L When this signal is active Low it resets the JTAG logic This line is pull down on the MPC8266 MB with a 1 resistor to provide constant reset of the JTAG logic QREQ Quiescent Request L When asserted low this line indicates that the MPC8266 desires to enter low power mode This signal may be required by a debug station V3 3 3 3V power supply bus TCK Test port Clock This clock shifts in out data to from the MPC8266 JTAG port Data is driven on the falling edge of TCK and is sampled both internally and externally on it s rising edge is pulled up internally by the 8266 N C Not Connected TMS Test Mode Select This signal qualified with TCK in a same manner as TDI changes the state of the JTAG machine This line is pulled up internally by the MPC8266 10 N C Not Connected SRESET Soft Reset L This is the MPC8266 s soft reset which is in fact non maskable interrupt making the PowerPC take the reset exception from the reset vector This line may be driven by the 8266 as well during sequence for 512 system clocks This line is pulled up on the MPC8266 MB with a 1 resistor When driven externally it MUST be driven with an Open Drain gate Failure in doing so might result
321. ta output driven by Falling edge of TCK GND O Digital GND Main GND plane TDI I Transmit Data In This is the JTAG serial data input of the ADS sampled on the rising edge of TCK TRST I Test port Reset L When this signal is active Low it resets the logic of the 8266 This line is pull down on the ADS with a resistor to provide constant reset of the JTAG logic O Quiescent Request L When asserted low this line indicates that the MPC8266 desires to enter low power mode This signal may be required by a debug station 3v3 O 3 3V power supply bus 104 MPC8266ADS PCI User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information Table 7 3 P3 COP JTAG Connector Pin No Signal Name TCK Attribute I Description Test port Clock This clock shifts in out data to from the JTAG logic Data is driven on the falling edge of TCK and is sampled both internally and externally on it s rising edge is pulled up internally by the MPC8266 N C Not Connected TMS Test Mode Select This signal qualified with TCK in a same manner as TDI changes the state of the JTAG machine This line is pulled up internally by the MPC8266 10 GND Digital GND Main GND plane 11 SRESET O D Soft Reset L This is the MPC8266 s soft reset w
322. ted buffers are in tri state mode freeing all its i f signals for off board use via the expansion connectors RW ATM RST ATM Port Reset When asserted low the ATM port transceiver is in reset state This line is driven also by HRESET signal of the MPC8266 RW FETHIEN Fast Ethernet Port Initial Enable When asserted low the LXT970 s MII port residing on FCC2 is enabled after Power Up or after FETH RST is negated When negated high the LXT970 s MII port is isolated after Power Up or after FETH RST is negated and all signals are tri stated After initial value has been set this signal has no influence over the LXT970 and MII isolation may be controlled via MDIO 0 10 bit RW FETH RST Fast Ethernet port Reset When active low the LXT970 is reset This line is also driven by HRESET signal of the MPC8266 Since MDDIS pin of the LXT970 is driven low with this application the negation of this signal causes all the H W configuration bits to be sampled for initial values and device control is moved to the MDIO channel which is the control path of the MII port RW RS232EN 1 RS232 port 1 Enable When asserted low the RS232 transceiver for port 1 is enabled When negated the RS232 transceiver for port 1 is in standby mode and SCC1 pins are available for off board use via the expansion connectors RW RS232bEN 2 RS232 port 2 Enable When asserted low the RS232 transceiver for port 2 is en
323. the type of SDRAM supplied with the DIMM board Value is specific foran SDRAM DIMM OR3 Depends on the SDRAM TBD Not used for the type of SDRAM supplied with the DIMM board Value is specific foran SDRAM DIMM BR4 SM73228XG1JHBG0 by PPG C3801801 Base at C3800000 32 bit port size no parity Smart Modular Tech GPCM SM73248XG2JHBG0 by C3001801 Base at C3000000 32 bit port size no parity Smart Modular Tech GPCM ASM73288XG4JHBG0 C2001801 Base at C2000000 32 bit port size no parity by Smart Modular Tech GPCM OR4 SM73228XG1JHBG0 by FF800836 8MByte block size CS early negate 6 w s Timing Smart Modular Tech relax SM73248XG2JHBG0 by FF000836 16MByte block size CS early negate 6 w s Smart Modular Tech Timing relax SM73288XG4JHBG0 by FE000836 32MByte block size CS early negate 6 w s Smart Modular Tech Timing relax BR5 PM5350 ATM UNI PPG 04600801 Base at 04600000 8 bit port size no parity GPCM on PPC bus OR5 FFFF8E36 32K Byte block size delayed CS assertion early CS and WE negation for write cycle relaxed timing 7 w s for read 8 for write extended hold time after read BR8 PCI Interrupt Controller PPC 04731801 Base at 04730000 32 bit port size no parity on bus OR8 FFFF8010 32 KByte block size all types access 1 w s 94 MPC8266ADS PCI User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Memory Map and Initiali
324. the ventilator supply wires may be soldered directly to JP7 shown in Figure 3 3 Warning The job of soldering wires or header to J7 is very delicate and should be done by a skilled techni cian If this process is done by unskilled hands or re peated more than 3 times permanent damage may occur to the MPC8266ADS 12V GND 7 Figure 3 3 JP7 Ventilator Supply 3 2 12 JP1 COP JTAG TDI Source Selection JP1 sets the structure of the COP JTAG chain the ADS For further information over its function see Section 2 3 10 3 2 13 JP4 IDDH Measurement 1 4 resides IDDH s main current flow To measure JP4 should be removed using a solder tool and a current meter should be connected with as wires as short and thick as possible MOTOROLA MPC8266ADS PCI User s Manual 23 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Operating Instructions Warning The job of removing JP4 and soldering current meter connections instead is very delicate and should be done by a skilled technician If this process is done by unskilled hand or re peated more than 3 times permanent damage might be inflicted to the MPC8266ADS PCI 3 2 14 JP11 VPP Source Selector JP11 selects the source for VPP programming voltage for the Flash SIMM When a jumper is located between pins 2 3 of JP11 Factory Set the VPP is connected to the VCC plane of the ADS providing 5V VP
325. tion EEPROM slave address for the convenience of the user SW2 is shown in Figure 2 8 SA2 SAI SAO RESERVED SW2 Factory Set Figure 2 8 SW2 Description The various position combinations of SW2 and their associated SDRAM DIMM configuration 14 MPC8266ADS PCI User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Hardware Preparation and Installation EEPROM s slave addresses are shown in Table 2 2 Table 2 2 SW2 SDRAM DIMM Configuration EEPROM Slave Address Slave Address bin Switch 1 Switch 2 Switch 3 1010000 ON ON ON 1010001 ON ON OFF 1010010 ON OFF ON 1010011 ON OFF OFF 1010100 OFF ON ON 1010101 OFF ON OFF 1010110 OFF OFF ON 1010111 OFF OFF OFF SW2 is factory set to 1 2 ON 3 ON 2 3 12 Setting ATX Chassis Main AC Power The ATX Chassis has a Power Supply which can operate from two different AC voltages 115 and 230 It is important that the user will set the proper AC voltage on the Power Supply according to the outlet AC voltage where the chassis is going to be pluged See Figure 2 9 for setting options WARNING Before turning on the power of the ATX chassis make sure that the AC voltage selector is set on the proper AC voltage Failure in doing so will result in PERMANENT DAMAGE inflicted to the chassis power supply
326. tion for the board The E PROM is used only for the purpose of supplying the Reset Configuration Word during power on reset and for storing the PCI configuration data It is used as back up for the Flash memory in case the Flash is not installed or the data it holds is incorrect As a back up it holds the default Hard Reset configuration word and the default PCI configuration The Hard Reset configuration word stored in the E PROM differs from the one stored in the FLASH in the BPS field which is the Boot Port Size 2 is 8 bits while the FLASH is 32 bits It uses a single chip select 50 or CS4 which depends on the chip select used by the Flash The selection of the chip select is done by a dip switch The E PROM connection scheme is shown in Figure 4 8 The device used is ATMEL AT28HC64B a 5V Byte alterable E PROM 150ns access time with byte wide JEDEC pinout Although the device is placed in a socket it can be programmed on board In order to program the device on board it has to be unlocked it can be locked to prevent unauthorized alterations of its contents The lock can be done by hardware or software The hardware lock is done by write inhibit the MPC8266 does not assert WE during write cycles set in the BRx register The software lock is achieved by writing a unique sequence to the device To 1 Itis required to do so anyway since the L2Cache must operate within a full 64 bit data bus environment MOTOROLA MPC
327. tional Description Table 4 16 PQ2 Board Version Encoding Version Number 0 1 Hex PQ2 Board Version 0 Voyager ADS 1 Reserved 2 MPC8266 Add In Card 3 MPC8266 Motherboard Table 4 17 PQ2 Board Revision Encoding Revision Number 0 1 Hex 2 Board Revision 0 ENG Engineering 1 PILOT 2 A 3 Reserved Table 4 18 External Tool Revision Encoding TOOLREV 0 3 hex External Tool Revision 0 ENGINEERING 1 PILOT 2 A 3 F Reserved Table 4 19 L2 Cache Size Encoding L2CSIZE 0 1 L2 Cache Size 00 Reserved 01 512 KBytes 10 Reserved 12 MPC8266ADS PCI User s Manual For More Information On This Product Go to www freescale com 73 Freescale Semiconductor Inc Functional Description 4 13 4 BCSR4 Board Control Status Register 4 BCSRA is a status register which is accessed at offset 0xC from BCSR base address Its a read only register which may be read at any time BCSR4s various fields are described in Table 4 20 Table 4 20 BCSR4 Description BIT MNEMONIC Function Bu ATT 0 1 PCIO PRSNT 0 1 PCI Slot 0 Present 0 1 This field holds a code that tells whether a PCI 11 R expansion board is pluged in PCI slot 0 and the total power requirements of the board according to the PCI spec The different expansion board types are listed in Table 4 21
328. tive state Slot2IntDMask_Active if VGR_WRITE_IntMaskReg Slot2IntDMask_DATA_BIT pin Slot2IntDMask_Active amp Hard Reset Slot2IntDMask_PON_DEFAULT Slot2IntDMask Active Hard Reset amp Slot2IntDMask_PON_DEFAULT Slot2IntDMask_Active then Slot2IntDMask_ Active else Slot2IntDMask_Active Read Registers All registers have read capabilty equations DataOe PON_RESET amp Hard Reset amp VGR_READ_IntReg READ IntMaskReg amp OE Data oe DataOe when READ IntReg MOTOROLA MPC8266ADS PCI User s Manual 177 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information then Data IntReg fb else when VGR READ IntMaskReg then Data IntMaskReg fb Generating Interrupt Request to PQ2 equations PCI Interrupt SlotOIntA fb amp SlotOIntAMask fb PCI Interrupt assertion SlotOIntB fb amp SlotOIntBMask fb depends on the masking of SlotOIntC fb amp SlotOIntCMask fb each PCI interrupt SlotOIntD fb amp SlotOIntDMask fb SlotlIntA fb amp SlotlIntAMask fb SlotlIntB fb amp SlotlIntBMask fb SlotlIntC fb amp SlotlIntCMask fb SlotlIntD fb am
329. tp Awww pmc sierra com PDF_Files 960924 pdf e PMC SIERRA 5350 Errata Notice Attp www pmc sierra com PDF _Files 970171 pdf e PMC SIERA 5350 Reference Design Autp www pmc sierra com PDF Files 961062 pdf MPC8266ADS PCI User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc General Information e LXT970A by Level One Data Sheet Attp www levell com product quickref htmlZnetwork e LXT970 Demo Board User s Guide http Avww levell com product quickref html network 1 4 Specifications The MPC8266ADS PCI specifications are given in Table 1 1 Table 1 1 MPC8266ADS PCI specifications CHARACTERISTICS SPECIFICATIONS Power requirements no other boards attached 5 TBD A Typ TBD A Max 3 3Vdc TBD A Typ TBD A Max 412 4 TBD Max 12 TBD Microprocessor 8266 running 66 MHz Bus Clock Frequency Addressing Total address range on PPC Bus Total address range on Local Bus Flash Memory SIMM PPC Bus Synchronous Dynamic RAM DIMM PPC Bus Synchronous DRAM On Local Bus 4 Giga Bytes 32 address lines 256 KBytes External 18 address lines 4 Giga Bytes Internal 32 address lines internal decoding 8 MByte 32 bits wide expandable to 32 MBytes 16 MByte 64 bits wide Support for up to 64 MByte 4 MBytes organized as 1 Meg X 32 bit Operating tempe
330. troller into Test Logic Reset state As a result the JIR is reset into Bypass code BYPASS Bypass public instruction When the holds this value and controller is in Shift DR state a single bit shift register is placed between the TDI of this JTAG machine 4 14 1 4 Data Shift Register The data shift register 1 an 8 bit shift register shifted in LSB first on the rising edge of TCK When JIR contains the DOWNLOAD code and the controller is in Shift DR state the input of this shift register is connected to TDI input of the board The TDO of this logic on the other hand reflects the state of the FULL status bit in the Download Control amp Status register That way the host may check prior to shifting in data whether the agent has read the previous byte of data When RX FULL flag is active data remains frozen in the register until it is read by the agent That way the host may shift in arbitrary data just to read back the status of JTAG RX FULL Since that flag is set only by the passage through this register will contain the last 8 bits shifted in This register is available on the PPC Bus memory map D 0 7 so it may be read by a download agent running on board It is designated as BCSR7 For additional information on BCSR7 see Table 4 24 and Table 4 24 82 MPC8266ADS PCI User s Manual MOTOROLA For More Information On This P
331. u __ Y 5 FY oS 57120 ta lt O8ENH Sr 120 Svuasu 1 6 WOG 5 8 ENH O Le lt 01494 38 VSENH T Y P V 8 Sr O3MBU VIENH T Sr 03788 WOT 920 Zn 30001 39001 6920 6920 L 2 v 5 o P 19915 1002 ZZ Aepsen leg SNIS 9 preog ev 9219 5 440 Tavus 02199 8 gt NO 840 WHIIGNV WALISNV Idd 2
332. ually SDRAMs AO is connected MPC8266s A28 and so on 4 7 2 SDRAM Refresh The SDRAM is refreshed using its auto refresh mode I e using SDRAM machine one s periodic timer an auto refresh command is issued to the SDRAM every 13 4 usec so that all 2048 SDRAM DIMM rows are refreshed within specified 32 8 msec while leaving an interval of 5 4 msec of refresh redundancy within that window as a safety measure to cover for possible delays 1 In fact each SDRAM component is composed of 2 internal banks each having 2048 rows but they are refreshed in parallel MOTOROLA MPC8266ADS PCI User s Manual 57 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Functional Description in bus availability for the refresh controller 4 7 3 L2 Cache Support Influence On SDRAM Design To support an optional L2 Cache the MPC8266 MB the following measures need to be taken 1 Optional Latches Multiplexers are added over selected address lines See Figure 4 6 These Latches Multiplexers are normally by passed by 0 resistors that are not assem bled in L2cache boards 2 The 8266 supports additional wait state on SDMUX line so that the row address may be allowed to propagate via the Latch Multiplexers in time for the Activate command 3 To support SDRAM PBI Page Based Interleaving the relative location of the Row Address field is shifted up the address lines depend
333. uesters on the same provided that they drive IRQ7 with open drain gate as well When an interrupt request appears in IRQ7 it is MOTOROLA MPC8266ADS PCI User s Manual 47 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Functional Description necessary to check the source of the interrupt whether it s the ATM UNI or the Fast Ethernet PH Y 4 2 3 Fast Ethernet PHY Interrupt To support fast Ethernet Transceiver event report by means of interrupt the interrupt output FDS MDINT of the LX970A is connected to IRQ7 line of the MPC8266 This IRQ7 input is shared with the ATM UNI Interrupt Since the FDS MDINT is an open rain output it is possible to connect additional on and off board interrupt requests on the same IRQ7 provided that they drive the IRQ7 with an open drain gate as well The FDS MDINT is a dual functionality signal on its FDS Full Duplex Status function it indicates whether the LXT970 is configured to Full Half Duplex mode while in its alternate function it serves as the transceivers MDINT active low output In order to achieve this functionality bit 1 in register 17 17 1 must be SET after the board comes out of Hard Reset Setting this bit is allowed through the MDIO port of the LXT970 Data of which is driven sampled by PC9 of the MPC8266 while its Clock is driven by PC10 Failure in doing so will result in IRQ7 pin of the MPC8266 constantly as
334. us and are buffered from the 60x bus can operate on the 60x bus This due to the 60x bus address tenure feature This means that when the L2 Cache is used the Flash EEPROM BCSR and PCI Interrupt Controller are not accesible For further details consult the MPC8266 User Manu al 4 5 Buffering In order to achieve best performance it is necessary to reduce the capacitive load over the 60X bus as much as possible Therefore the slower devices the bus 1 the Flash SIMM EPROM ATM UNI M P interface PCI Interrupt Controller and BCSR are buffered while the SDRAM DIMM and the cache are not buffered from the 60X bus Latches are provided over address and strobe when necessary lines while transceivers are provided for data Use is done with 74ALVT buffers by Philips which are 3 3V operated and 5V tolerant and provide bus hold to reduce pull up pull down resistors count as required by the MPC8266 This type of buffers reduces noise on board due to reduced transitions amplitude To further reduce noise and reflections serial damping resistors are placed over SDRAM DIMM s address and all MPC8266 strobe lines The data transceivers are open only if there is an access to a valid buffered board address or during Hard Reset configuration That way data conflicts are avoided in case an unbuffered memory read or off board memory is read provided that it is not mapped to an address valid on board It is the users r
335. ut L2 Cache 2 is the boot device CSO is assigned to the E PROM and CS4 is assigned to the FLASH e MPC8266ADS PCI with L2 Cache FLASH is the boot device CSO is assigned to the FLASH and CS4 is assigned to the E PROM e MPC8266ADS PCI with L2 Cache E7PROM is the boot device CSO is assigned to the E PROM and CS4 is assigned to the FLASH Table 4 1 BCSR FLASH Hard Reset Configuration Word Data Prog Offset In Value Field Bus Value Implication Flash Hex Bits Bin Hex ERB 0 Internal Arbitration Selected 0 1C 1 0 Internal Memory Controller CSO active at system boot CDIS 2 Core Enabled EBM 3 071 0 Single MPC8266 Mode for boards without L2Cache 1 60X Bus Mode for boards with L2Cache BPS 4 5 11 32 Bit Boot Port Size CIP 6 0 Sets Core Initial Prefix MSR IP 1 so that System exception table is placed at address OxFFF00100 regardless of FLASH memory size ISPS 7 64 bit internal space for external master accesses In fact don t care on this board since external master is not supported 42 MPC8266ADS PCI User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Functional Description Table 4 1 BCSR FLASH Hard Reset Configuration Word Field L2CPC Data Bus Bits 8 9 Prog Value Bin 40 Implication CI BADDR 29 IRG2 selected as BADDR 29 WT BADD
336. ve state Slot2IntD Active if Reset amp Slot2IntD PON DEFAULT Slot2IntD_Active Reset amp B then Slot2IntD Active else 18101214 Active PCI Interrupt Mask Register k k k k equations IntMaskReg clk SYSCLK IntMaskReg ar 0 IntMaskReg ap PON RESET state diagram Slot0IntAMask state SlotOIntAMask Active if WRITE IntMaskReg SlotOIntAMask DATA BIT pin SlotOIntAMask Active amp Hard Reset SlotOIntAMask PON DEFAULT SlotOIntAMask Active Hard Reset amp SlotOIntAMask PON DEFAULT SlotOIntAMask Active then ISlotOIntAMask Active else SlotOIntAMask Active state SlotOoIntAMask Active if WRITE IntMaskReg SlotOIntAMask DATA BIT pin SlotOIntAMask Active amp MOTOROLA MPC8266ADS PCI User s Manual 171 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information Hard Reset SlotO0oIntAMask PON DEFAULT SlotOIntAMask Active Hard Reset SlotOIntAMask PON DEFAULT SlotOIntAMask then SlotOIntAMask Active else ISlotOIntAMask Active 1 ef state diagram Slot0IntBMask state SlotOIntBMask
337. vg uo spuedop pue LSA xx oeadya bi ca 2391 amp pz 620048 py Leet _ 1 585 85 351 720 031 188 E ov v 2071 0 2 ien iv EST Szaava SISVHO o OX ino OSESINd 221 1 884 91 W old 0 2 XTOHWIV 55 d 135193 g 5 T 7 5 0 821 0191 9 i n in N3WLVu S laly 1 18H J33 NSXHIALVU SAT 99 22 V HW1V Dene S 9 S S 1 Z 99 Ka gg YOU Sp Suv 99 Y 20 DOSEWIV SNH Z 24 XL EST NOXIRIV VM 6 dOXIWlV z 35 Veny T i oLvau zdvou THANE goxi KK P o lt lt 88 t e i iZ aS Fg GSHW1V 7 ZN LL to 97 sivau 8 b d 37 22 3400 34001 3o 80 Z 30001 id E 760 90 d 5498 56 50 sa 5 vO va YOXHILV 3 3 rm m OZNY lt lt lt lt lt lt
338. which are available at the CPM expansion connectors are intended to serve as tools identifier On board S W may check these lines to detect The presence of various tools h w expansions at the CPM expansion connectors For the external tools codes and their associated combinations see Table 4 15 16 17 SWOPT 0 1 8 Software Option 0 1 This field shows the state of a dedicated dip switches providing an option to manually change a program flow 18 19 L2CSIZE 0 1 L2 Cache Size 0 1 This filed encodes the size of the L2 Cache present on the MPC8266 MB For the encoding of the various cache sizes see Table 4 19 20 21 BVERN 0 1 Board Version Number 0 1 This field represents the version code hard assigned to the MPC8266 MB See Table 4 16 for version encoding 11 22 28 BREVN 0 1 Board Revision Number 0 1 This field represents the revision code hard assigned to the MPC8266 MB See Table 4 17 for revisions encoding 24 SWOPT2 Software Option 2 This is the LSB of the field Shows the state of a dedicated dip switch providing an option to manually change a program flow 25 27 FLASH PD 7 5 Flash Presence Detect 7 5 These lines are connected to the Flash SIMM presence detect lines which encode the Delay of Flash SIMM mounted on the Flash SIMM socket For the encoding of FLASH PD 7 5 see Table 4 13 28 31 FLASH PD 4 1 Flash Presence Detec
339. y available alternate function for PD27 A6 PD26 ES MPC8266 s PD 26 18 Port D lines Parallel I O or CPM dedicated lines May be used for any of their available functions AT PD25 A8 PD24 A9 PD23 A10 PD22 21 12 PD20 A13 PD19 14 PD18 15 ATMRXPTY PD17 5 Receive Parity Line When the ATM port is enabled this line is connected to the receive parity of the PM5350 ATM UNI When this port is disabled this signal 1 tristated and may be used for any available function of PD17 16 PD16 5 ATM Transmit Parity Line When the ATM port is enabled this line is connected to the transmit parity of the PM5350 ATM UNI When this port is disabled this signal may be used for any available function of PD16 A17 I2CSDA PD15 T S This signal is connected to the serial data line This line may be used off board as an data line for external device A18 I2CSCL PD14 T S This signal is connected to the serial clock line This line may be used off board as an clock line for external device 106 MPC8266ADS PCI User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information Table 7 4 P4 CPM Expansion Connector Pin No Signal Name Attribute Description A19 PD13 T
340. ytes PCI 60 Bus Add 64 Bit Clock 0 Distribution 60 Bus Data amp 8 3 3V 5 60 Bus L2 CACHE Interrupt 512 Controller 64 Bit OPTIONAL 5 v gt 60 Bus buffered FLASH SIMM 8 32MByte 2 8 2 E T 32 Bit oj 1 03 2 V lt E 33V 55V 2 DATA Transceivers amp ES E2PROM SS S a z MPC8266 Address Latches 8 8KByte 2 8 bit SCCI x o 4 9 XE x x MPC8266 Res L Mai eset 5 m s Interrupts z Clock p SCC2 ao di 3 3 5 FCC2 86 5 x LXT970 Magnetics 5 got 5 5 5V m FCCI gt 5 5 PM5350 2 8 Le lt 2 3 3V lt gt 5V b Buffered System Bus zz 4 1 Logic Analyzer CPM e Mictors a amp 2 Figure 1 1 MPC8266 MB Block Diagram 6 MPC8266ADS PCI User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Hardware Preparation and Installation 2 Hardware Preparation and Installation 2 1 Introduction This chapter provides unpacking instructions hardware preparation and installation instructions for the MPC8266ADS PCI 2 2 Unpacking Instructions NOTE Ifthe shipping carton is damaged upon receipt request carrier s agent to be present during unpacking and inspection of equipment Unpack equipment from shipping carton Refer to packing list and verify that all items are pre
341. zation Table 5 8 Memory Controller Initializations For 66Mhz Reg PSDMR Device Type SDC2UV6482C 84 16 MByte SDC8UV6484C 84 64 MByte Bus PPC Single MPC82 66 Bus Mode Init Value hex 416EB452 Description Bank Based Interleaving Refresh enabled normal operation code address muxing mode 1 A 15 17 on BNKSEL 0 2 A9 PSDAIO 7 clocks refresh recovery 3 clocks precharge to activate delay 2 clocks activate to read write delay 4 beat burst length 1 clock last data out to precharge 1 clock write recovery time no extra cycle on address phase normal timing for control lines 2 clocks CAS latency 2 452 Page Based Interleaving Refresh enabled normal operation code address muxing mode 2 19 on BNKSEL2 PSDA10 7 clocks refresh recovery 3 clocks precharge to activate delay 2 clocks activate to read write delay 4 beat burst length 1 clock last data out to precharge 1 clock write recovery time no extra cycle on address phase normal timing for control lines 2 clocks CAS latency 412 452 Bank Based Interleaving Refresh enabled normal operation code address muxing mode 1 A 13 15 on BNKSEL 0 2 A9 on PSDA10 7 clocks refresh recovery 3 clocks precharge to activate delay 2 clocks activate to read write delay 4 beat burst length 1 clock last data out to precharge 1 clock write recovery time no extra cycle on address phase n

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