Home

with DDR3 System Memory

1. Rework Instructions Figure 24 Low Voltage HD Audio Rework Sus Rail 1 25 48 56 58 V1 5S V3 3S T 2225 28 3V33S 1 58 HDA IO Development Kit User s Manual 73 intel Appendix C Programming System BIOS Using a Flash Programming Device The BIOS for the Silver Cascade development board is in two non removable flash devices The flash can be programmed using a bootable DOS device or through a special BIOS programming device that connects to header J8D2 on the board One such programming device is the Dediprog SF100 available from the manufacturer at www dediprog com The Silver Cascade development board required the use of a 2 partition SPI image for SPI 0 and SPI 1 respectively The descriptors are stored on SPI 0 while the BIOS is on SPI 1 To program the flash using a flash programming device 3 Setup the hardware and software of the flash programming device on a host system according to the manufacturers instructions 4 Obtain the latest BIOS image separated into two bin files Store the image files on the host system Disconnect the power supply of the development board Connect the programming device to the development board at J8D2 Set jumpers J9C1 and J9D1 at 1 2 Set jumper J8C1 at 1 2 for SPI 0 Erase the existing image and flash the bin image corresponding to SPI 0 9 Setthe jumper J8C1 at 2 3 for SPI 1 Erase the existing image and flash the bin image corresp
2. PBA D4455 FINU 1HNX64666618 PROCHOT D un 76 Development Kit User s Manual CPU Thermal Solution Heatsink Installation intel 5 Clean the die of the processor with isopropyl alcohol before the heatsink is attached to the processor This ensures that the surface of the die is clean 6 Remove the tube of thermal grease from the package and use it to coat the exposed die of the CPU with the thermal grease See the figure below Figure 27 Step 6 Applying the Thermal Grease 7 Pick up the heatsink and squeeze the activation arm until it comes in contact with the base plate that is attached to the heatsink base This will cause the springs on the heatsink attachment mechanism to compress See the figure below Development Kit User s Manual 77 intel CPU Thermal Solution Heatsink I nstallation Figure 28 Step 7 Squeezing Activation Arm 78 Development Kit User s Manual CPU Thermal Solution Heatsink Installation intel 8 While keeping the activation arm compressed place the heatsink over the pins of the heatsink backplate Lower the heatsink until the lugs have inserted into the base of the heatsink Slide the heatsink over the lugs on the backplate pins so that the base is directly over the processor die and the pins on the backplate have travelled the entire length of the channel in the heatsink base Slowly let go of the activ
3. and IERR and non AGTL signals THERMTRIP and PROCHOT also utilize GTL output buffers All of these signals follow the same DC requirements as AGTL signals however the outputs are not actively driven high during a logical 0 to 1 transition by the processor the major difference between GTL and AGTL These signals do not have setup or hold time specifications in relation to BCLK 1 0 and are therefore referred to as Asynchronous GTL Signals However all of the Asynchronous GTL signals are required to be asserted for at least two BCLKs in order for the processor to recognize them Infrared Data The Infrared Data Association IrDA has outlined a specification for serial Assoc communication between two devices via a bi directional infrared data port The development board has such a port and it is located on the rear of the board between the two USB connectors IMVP6 The Intel Mobile Voltage Positioning specification for the Intel Core 2 Duo Processor It is a DC DC converter module that supplies the required voltage and current to a single processor Media Expansion The Media Expansion Card MEC provides digital display options through Card the SDVO interface The MEC card also incorporates video in via a x1 PCI Express port Pad The electrical contact point of a semiconductor die to the package substrate A pad is only observable in simulations Pillar Rock The name of the developme
4. intel Programming BI OS Using a Bootable USB Device The flash chips that store the BIOS and BIOS extensions on the development board are connected to the SPI bus and are soldered down One method of programming these devices is through software utilities as described below The software files and utilities needed to program the BIOS are contained on the included CD ROM Another method is described in Appendix C Programming System BIOS Using a Flash Programming Device Follow these steps to program the system BIOS using a bootable USB device 1 2 3 Prepare the workspace as outlined in Section 2 5 above Setup the system as outlined in Section 2 6 above Warning Prior to flashing BIOS onto the platform AMT must be disabled in BIOS Failure to do this will render the system inoperable a Switch on the power supply to 1 b Press the Power PWR Button on the development boar C Asthe system starts to boot enter the system BIOS setup by pressing F2 or Del d Navigate to AMT and select disable e Navigate to Save changes and exit f Power off the system by pressing the power PWR button SW1C1 g Turn off the power supply remove power from the board for at least 15 seconds Copy the following files and utilities to the Bootable USB Device e BIOS Image Files spifull bin e BIOS Programming Software Utilities fpt exe DOS SPI Flash Utility fparts txt helper file e MAC Address Programming Software Uti
5. 3 J1G3 gt Open JiG1 gt 2 3 4 4 Power and Reset Push Buttons The development board has two pushbuttons Power and Reset The Power button releases power to the entire board causing the board to boot The Reset button forces all systems to warm reset The two buttons are located near the CPU close to the East edge of the board The Power button is located at SW1C1 and the Reset button is located at SW1C2 Table 20 Power On and Reset Push buttons Description Component Power Button swici Reset Button Swic2 U2E1 Development Kit User s Manual 53 Figure 8 Power On and Reset Buttons a 00 e a SC o as sa ME Bes pan EN g m i EN ans at 3 EJ H i a 4 4 5 Net Detect Button Development Board Physical Reference a Power Button SW1C1 E s pH Reset Button SW1C2 gE c Y im it CPU U2E1 The board has one Net Detect push button switch SW8E1 to support wireless LAN network detection in S0 S5 This button is connected on the SMC KBC GPIO When pressed a manageability wake event is signaled to the ICH9M via SMC KBC manageability planes are powered and the 82567 wireless LAN performs the network detection Figure 9 Net Detect Button EL C C E EI ey DR Si Ben HE M Board n oom B i Edge E ne Net Detect Button SW8E1 54 Development Kit User s Manual Development Board Physical Reference 4 6 LED
6. 3 1Hz clock JOH1 operation clock Ee enable Ng enabled programming Sideband and Test Headers Additional sideband and test headers are located on sheet 46 of the Silver Cascade schematics Development Kit User s Manual 57 intel Appendix A Add In Cards A 1 Of the add in cards described in this appendix only the Port 80 83 Card PCI Expansion Card Thimble Peak 2 and the HDMI and Display Port Video Interface Card Eaglemont are included in the development kit Contact your Intel Representative to obtain cards not included in the kit Port 80 83 Add in Card Included Port 80 83 Add in card plugs to the CRB through TPM header It also provides an additional 10 pin LPC header for LPC supported interfaces Port 80 83 card decodes the LPC bus BIOS POST codes and displays on four 7 segment display It also has optional Intel 82802 Firmware Hub Device footprint for BIOS support Figure 10 Port 80 83 Interposer Card Table 23 TPM Module Header Remote Display Header Display Segment 1 Display Segment 2 Display Segment 3 Display Segment 4 JopeaH Ndl 97 LPC Header Jumper J1 is used for the configurations shown in the following table Port 80 83 Display Configurations Jumper J1 Description Open None AIC Intel 82802 Firmware Hub Device Disabled Display Ports 81 80 1 2 AIC Intel 82802 Firmware Hub Device enabled Display Ports 81 80 2 3 AI
7. BIOS BIOS installation utilities Chipset drivers Intel Embedded Graphics Drivers Intel Active Management Technology AMT software installation kit e Pre assembled development system which includes Silver Cascade development board Plexiglass stand with Acrylic pad Mounting screws and standoffs installed Intel Core 2 Duo processor with 4 MB L2 Cache on 65nm process in the 478 pin Flip Chip Pin Grid Array Micro FCPGA package Installed Processor thermal solution and CPU back plate Intel GM45 Express Chipset Graphics and Memory Controller Hub GMCH GMCH GM45 heatsink I O Controller Hub 9M ICH9M Type 2032 3 V lithium coin cell battery One 512 MByte 200 Pin DDR3 SO DIMM Port 80 display card Power Supply 80 GByte SATA Hard Disk Drive DVD ROM Drive Disk Drive Power and SATA Cables e One HDMI and Display Port add in card codename Eaglemont e One PCI Extension Card codename Thimble Peak 2 e One AC to DC Power Adapter Document Number 320249 001 i n te Getting Started 2 3 18 Additional Required Hardware Not Included in the Development Kit The following additional hardware may be necessary to operate the development board VGA Monitor Any standard VGA or multi resolution monitor may be used The setup instructions in this chapter assume the use of a standard VGA monitor or LCD monitor Keyboard The development board supports
8. Components 29 Tf 25 92 27 33 Document Number 320249 001 42 41 28 43 40 Development Board Physical Reference Table 16 Silver Cascade Development Board Components intel 1 Chipset VR EU5G1 19 SPI flash 1 U8C4 37 Battery B Connector JiH2 2 Trusted Platform J9A1 20 SMC KBC J1A1 38 Battery A Connector J1H1 Module 3 82567 LAN EU8A1 21 Manufacturing Mode J9J1 39 iAMPS connector EU2G1 controller Jumper 4 PCI Express Slot 1 J6B1 22 Virtual Battery Switch SW9H3 40 Intel Core 2 Duo U5E1 processor T9400 5 PCI Express Slot 2 J6D1 23 SATA Direct Connect J8J1 41 VID LEDs CRiB1 CR1B2 CR1B3 CR1B4 CR1B5 CR1B6 CR1B7 6 DB800 Clock Buffer U7C2 24 Front Panel Header J6H5 42 Manual VID Override J2B2 Jumper 7 PCI Gold Fingers S9B1 25 SATA Cable Connect J6J3 43 Teenah Cantiga U5E1 J6J2 8 PCI Express Slot3 J8B3 26 SPI Flash 2 U8C1 44 PCI Express Graphics J6B2 Slot 9 PCI Express Slot4 J8D1 27 SATA Port1 4 Power J5J1 45 DDR3 VR EUAN1 Connector 10 PCI Express Slot5 J7B1 28 Debug XDP CPU J1F1 11 Mott Canyon 4 J9E2 29 Debug XDP ICH9M J8H2 Header 12 SMSC SIO U7E3 30 LVDS Connector J6F1 13 Keyboard Scan J9E1 31 Front Panel USB J6H4 Matrix J6H2 J6J1 14 LPC Docking J9E3 32 CK 505 Derivative EU6H1 Connector 15 LPC Sideband J9G1 33 ATX Power Supply J4Ji Header Connector 16 LPC Slot J8E1 34
9. Electronics IMVP 6 Intel Mobile Voltage Positioning revision 6 or Intel MVP 6 I O Input Output IrDA Infrared Data Association ITP Integrated Test Port KBC Keyboard Controller Development Kit User s Manual I ntroduction Acronym Definition L2 Level 2 Cache LAN Local Area Network LED Light Emitting Diode LPC Low Pin Count LS Low speed Refers to USB LV Low Voltage LVDS Low Voltage Differential Signaling Video Standard mBGA Mini Ball Grid Array MEC Media Expansion Card MHz Mega Hertz MT s Mega Transfers per second NMI Non Maskable Interrupt OEM Original Equipment Manufacturer PEG PCI Express Graphics PCI Peripheral Connect Interface PCIe PCI Express PCM Pulse Code Modulation POST Power On Self Test PS 2 Personal System 2 Keyboard and Mouse Connector PSI2 Power Status Indicator 2 PWM Pulse Width Modulation RAID Redundant Array of Inexpensive Disks RCA Type of Audio and Video Connector RTC Real Time Clock SATA Serial ATA SDVO Serial Digital Video Output SIO Super Input Output SKU SKU Number Stock Keeping Unit Stock Keeping Unit Number SMC System Management Controller SODIMM or SO DIMM Small Outline Dual In line Memory Module SOIC 8 or SOIC 16 Small Outline Integrated Circuit 8 or 16 pin package SPI Serial Peripheral Interface SPWG Standard Panels Working Group
10. Extract all files keep them in the same folder to a single directory of your choice on the host machine or on a floppy disk 2 Connect a NULL modem cable to the serial ports of each platform host and unit to be flashed 3 With the board powered off move the following jumpers to the programming stuffing option J9G2 remove default 1 2 Sets SMC INIT CLK high J7A1 2 3 default 1 2 link the Host Unit to On Board H8 J8B2 2 3 default 1 2 link the Host Unit to On Board H8 J9H1 1 2 default 1 X disable 1 Hz Clock Attach an AC brick or an ATX power supply to the system and power up the board From the directory where you extracted the files run the kscflash ksc bin remote command to program the H8 via the serial port 10 Follow the instructions the flash utility provides 11 With the board powered off return the jumpers to their default setting E SOY UT e Make sure the board is not powered on and the power supply is disconnected before moving any of the jumpers Development Kit User s Manual Development Board Physical Reference Table 22 H8 Programming Jumpers 4 7 2 intel Jumper Reference Default Stuffing Programming Stuffing Designator Option Option 1 Remote H8 J7A1 1 2 normal 2 3 link the Host Unit to On Programming J8B2 operation Board H8 Boot Block 1 2 IN normal OUT set SMC INIT CLK high 2 J9G2 Programming operation to program H8 OUT normal
11. Included sss 69 Rework Irstr ctiODs usceecsexeedes See eg SEENEN e ue eR RARE NEN Een GRE Eege Rin 71 B 1 Internal HDMI Enabling 4 ioira eene NEEN ENNEN nnns nnn ana ni dena 71 B 2 Enabling the Integrated Trusted Platform Module iTPM sssssesse 71 B 3 Enabling External HDMI uiuit uet aie ated NEEN Eege ATA e 72 B 4 SUPPOFE FOr Upham 4 vices cene eene dene kann t nbken nahen ax ER EE RENI EE raa n dna Seege 72 B 5 Low Voltage High Definition HD Audio Rework sees 72 Development Kit User s Manual Appendix C Programming System BIOS Using a Flash Programming Device esueesses 74 Appendix D CPU Thermal Solution Heatsink Installation eee 75 Figures Figure 1 Development Board Block Diagram eset eens eee ee teeta etna eats 25 Figure 2 Silver Cascade Development Board Componente teens ee ee eee 46 Figure 3 Back Panel Connectors NEISES ERENENENR ENNEN NENNEN RN ENN EENS ENNEN REN EK en 48 Figure 4 D Connector to Component Video Cable eect este eeeee eens eaeaeee 49 Figure 5 D Connector to Composite Video Cable n 49 Figure 6 D Connector to S Video Cable sssssssssssesene nennen 49 Figure 7 Location of the Configuration Jumpers Gwitches ssssssssssrrrsrirsrrrrerrreses 50 Figure 8 Power On and Reset Buttons ssssssssssesssesene ennemis emen 54 Figure 9 Net Detect BUEEOTnsuioiiiee circo te oiv Dee d E
12. J6J3 amp J6J2 Port 5 eSATA J7J1 34 These connectors mentioned in Table 10 are for the serial data signals The board has a power connector J5J1 to power the serial ATA hard disk drive A green LED at CR7H1 indicates activity on the ATA channel Development Kit User s Manual Development Board Features n tel The development board shares the power connector for both SATA ports Due to this only one of the serial ATA channel Port1 by default supports hot swapping capability Hot swap on Port 1 can be used only when the Port 4 is not used Y Power cable needs to be connected first to the device on Port 1 before connecting the signal cable When hot swap is not desired both Port 1 and Port 2 can be used A jumper J7H1 is provided to enable hot plug removal on port 1 For jumper setting details refer to Section 4 3 1 Table 18 Note The eSATA drives should be externally powered Hence there is no power supply support for them on the motherboard 3 6 16 USB Connectors ICH9M provides a total of twelve USB 2 0 1 1 ports 6 USB ports 0 2 4 6 8 10 are connected to the back panel I O connector 6 ports 1 3 5 7 9 11 to the front panel I O connector of these ports port 9 is also routed to Docking Four ports 0 2 4 and 6 are routed to a 4 stacked USB connector J3A1 at the back panel The other 2 ports 8 and 10 are routed to the RJ45 Dual USB stacked connector J5A1 at th
13. Step 8 Installing the Heatsink eee ee ee eee eee eens eee eee eee eaten ee 79 Step 9 Plugging in the Fan senes dE EEN ER run NENNEN nang nnn eran ni inn 80 Step 10 Completed Assembly cceceee eee e eee eee teers e eee nemen 81 Development Kit User s Manual 5 Tables Table 1 Text Conventions oiii tes cede dead ida ee QN V LARA EEN kane 9 Table 2 Definitions of Terms ENNER NENNEN ENER NREN ENEE NENNEN ENN NARRA MAR K RENE R ENER 10 Table 2 ACrONY MS E Y 11 TTable 4 Related Documents cent coax eher a hun Ux i aun x me EM AM e 15 Table 5 intel Literature Centers ssnccseccg gess nonet n na set ka SERA RE EES E ce Raga PRAE 15 Table 6 Development Board Feature Set Summary sssessseseeemee 26 Table 7 TV Out Cornnections uxore patet e GENEE DERE EE uM E EARN EA Ee 32 Tabl amp 8 PCIE le ee 33 Table 9 Selection of I O Voltage for the High Definition Audio 34 Table 10 SATA Rote ak eie ies dad ne dime See dee Ex ARA TE SP ORDEI INTRA dE Rie Ee 34 Table 11 USB Ports mapping erattu aene suat ux unu haa nba ina dE agn Paga na ceases 35 Table 12 System Power Management States ssssssssssessnmeeneneee 39 Table 13 System Power Management M Gtates teens ee eeeee teens eaeeeeeenee 40 Table 14 Digital Multi Meter Comparison cssssssssm mener 41 Table 15 System Voltage Rails ccccscecseeenee eases neneseneeeseaeesaaeeseneeee
14. The 82567 component is connected to the ICH9M chipset through the LAN Connect Interface LCI and supports 10 100Mbps link The same device is connected through GLCI interface and supports 1000Mbps link 82567 connect to an RJ45 connector at J5A1 with built in magnetic decoupling Serial Peripheral I nterface SPI The Serial Peripheral Interface on ICH9M can be used to support two compatible flash devices U8C1 or U8B2 U8C4 or U8C3 Both the SPI devices supports for multi package SOIC 8 and SOIC 16 device The SOIC 8 package U8C1 amp U8C4 would support 16 Mb SPI flashes while the SOIC 16 package U8B2 amp U8C3 will support 32Mb or higher SPI flash Unified BIOS code BIOS IAMT LAN resides in these two SPI devices Out of the SOIC 8 and SOIC 16 footprints supported on the board only one of these can be used at a time and on the board the Footprint is arranged one over the other By default U8C1 16Mb on CS 0 and U8C4 16Mb on CS 1 will be stuffed Development Kit User s Manual 33 i n te l Development Board Features Note 3 6 14 SPI programming details are given in Section 2 8 2 Soft Audio Soft Modem Intel High Definition Audio functionality is enabled through the Mott Canyon 4 Daughter Card ICH9M supports 4 Intel High Definition Audio codec All the four are routed to MDC header through resistor stuffing option By default Codec 0 amp 1 will be connected to MDC Card An on board header is provide
15. This appendix gives detailed installation instructions for the Intel Core 2 Duo processor heatsink Text Conventions The notations listed in Table 1 may be used throughout this manual Table 1 Text Conventions Notation Definition The pound symbol appended to a signal name indicates that the signal is active low e g PRSNT1 Variables Variables are shown in italics Variables must be replaced with correct values Instructions Instruction mnemonics are shown in uppercase When you are programming instructions are not case sensitive You may use either uppercase or lowercase Numbers Hexadecimal numbers are represented by a string of hexadecimal digits followed by the character H A zero prefix is added to numbers that begin with A through F For example FF is shown as OFFH Decimal and binary numbers are represented by their customary notations That is 255 is a decimal number and 1111 is a binary number In some cases the letter B is added for clarity Units of Measure The following abbreviations are used to represent units of measure A amps amperes GByte gigabytes KByte kilobytes KO kilo ohms mA milliamps milliamperes MByte megabytes MHz megahertz ms milliseconds mW milliwatts ns nanoseconds pF picofarads Ww watts V volts UA microamps microamperes uF microfarads us microseconds UW microwatts Development Kit User s Manual 1 3 10 intel I ntrodu
16. White Paper Document 603714 available from your Intel Representative If power button on the ATX power supply is used to shut down the system please wait at least 5 seconds before turning the system on again We do not recommend shutting down the system this way Manual VID support for Graphics VR The development board supports manual VID operation for graphics Voltage Regulator Jumper J2H2 is provided to incorporate VID override to allow the overriding of GMCH VID outputs to the graphics VR The intent of this VID override circuit is for ease of debug and testing VID settings are contained in the IMVP6 Specification RS Intel amp IMVP 6 Mobile Processor and Mobile Chipset Voltage Regulation Specification Contact your Intel representative for access to this document Development Kit User s Manual Development Board Features j n te 3 6 26 Debug I nterfaces An XDP Extended Debug Port connector is provided at J1F1 for processor run control debug support This connector is compatible with both XDP and ITP 700 An external adapter is used to interface ITPFlex700 cable to the platform XDP incorporates new run control features on the JTAG interface and allows the user to communicate with the processor or GMCH A port 80 83 display add in card can also be used for debug The port 80 83 add in card could be used on the TPM header located at J9A1 Note The XDP interface is backwards compatible with the ITP interface Howe
17. both PS 2 and USB style keyboards Mouse The development board supports both PS 2 and USB style pointing devices Hard Drives and Optical Disc Drives and cables One SATA hard disk drive and one SATA optical DVD Drive are included in the development kit Up to four SATA drives and two IDE devices master and slave may be connected to the development board An optical disc drive included may be used to load the OS All these storage devices may be attached to the board simultaneously Video Adapter Card Integrated video is output from the VGA connector on the back panel of the development board Alternately a standard PCI Express video adapter card ADD2 card or MEC video adapter card may be used for additional display flexibility Please contact the respective vendors for drivers and software for adapters not provided with this development kit Check the BIOS and the graphics driver where appropriate for the proper video output settings Network Adapter and cables A Gigabit network interface is provided on the development board The network interface will not be operational until after all the necessary drivers are installed A standard PCI PCI Express adapter may be used in conjunction with or in place of the onboard network adapter Please contact the respective vendors for drivers and necessary software for adapters not provided with this development kit You must supply appropriate network cables to utilize the LAN connector or any
18. displayed to port 80h e PCI PCI Express device enumeration and configuration e Integrated video configuration and initialization e Super I O configuration e Active Management Technology e RAID 0 1 support Development Kit User s Manual 29 i n te l Development Board Features 3 5 3 6 3 6 1 3 6 2 3 6 3 3 6 4 30 Thermal Management The objective of thermal management is to ensure that the temperature of each component is maintained within specified functional limits The functional temperature limit is the range within which the electrical circuits can be expected to meet their specified performance requirements Operation outside the functional limit can degrade system performance and cause reliability problems The development kit is shipped with a heatsink thermal solution for installation on the processor This thermal solution has been tested in an open air environment at room temperature and is sufficient for development purposes The designer must ensure that adequate thermal management is provided for if the system is used in other environments or enclosures System Features and Operation The following sections provide a detailed view of the system features and operation of the development board Processor Support The Silver Cascade board design supports the Intel Core 2 Duo processor T9400 U2E1 in a 478 pin Micro FCPGA Flip Chip Pin Grid Array package Processor Voltage Regulators The
19. http www spwg org SRC Source Clock Development Kit User s Manual 13 intel 1 4 1 4 1 I ntroduction Acronym Definition SUT System Under Test TME Technical Marketing Engineer TPM Trusted Platform Module TV or TVO Television Output HBGA Micro Ball Grid Array UHCI Universal Host Controller Interface ULV Ultra Low Voltage USB Universal Serial Bus VGA Video Graphics Adapter VID Voltage Identification WiMAX Wireless Communications Standard WLAN Wireless Local Area Network VREG or VR Voltage Regulator WWAN Wireless Wide Area Network VCC Power Signal x1 x2 etc By 1 By 2 etc refers to number of PCIe Links XDP eXtended Debug Port Development Kit Technical Support Online Support Intel s web site http www intel com provides up to date technical information and product support This information is available 24 hours per day 7 days per week providing technical information whenever you need it 1 4 2 Additional Technical Support If you require additional technical support please contact your Intel Representative or local distributor 14 Development Kit User s Manual I ntroduction 1 5 Related Documents intel Table 4 lists publicly available documents related to this development kit For additional documentation please contact your Intel Representative Table 4 Related Documents 1 5 1 Document Titl
20. intel Intel Core 2 Duo Processor and Intel GM45 Express Chipset with DDR3 System Memory Development Kit User s Manual September 2008 Document Number 320249 001 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS NO LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT Intel products are not intended for use in medical life saving life sustaining critical control or safety systems or in nuclear facility applications Intel may make changes to specifications and product descriptions at any time without notice Intel Corporation may have patents or pending patent applications trademarks copyrights or other intellectual property rights that relate to the presented subject matter The furnishing of documents and other materials and information does not provide any license express or implied by estoppel or otherwise to any such patents trademarks copyrights or other intellectual property rights Designers must not rely on the absence or chara
21. non Sparkle ATX power supplies Only use Sparkle ATX Desktop Power Supplies As the Desktop ATX supplies grew to meet the increased power for those Motherboards their minimum loading requirements also grew When you try to run a mobile platform on it it may not load the 5 0V rail enough to meet the minimum loading requirements for it to maintain regulation Recommended power 20 pin ATX power supplies include e Sparkle Model No FSP300 60BTVS meets this requirement and is an ATX12V 1 1 Spec note that this part may be End Of Life These 20 pin ATX power supplies may also work if you can t find the above model number lower power supplies are probably better e Sparkle SPI FSP250 60BT FSB300 60BT FSB300 60BTV FSP350 FSP400 60GN these supplies work in the lab although are not checked against spec DO NOT use Delta or PowerMan ATX Supplies You may experience the following symptoms when using a non Sparkle supply e post 00 e Blue Screen reporting driver or device issue when using a desktop PCI graphics card e Hanging during boot with PEG or PCI graphics e PCI video only during boot but not available after in Windows 8 Development Kit User s Manual 45 intel 4 Development Board Physical Reference 4 1 Board Components The following figure shows the major components of the Silver Cascade development board and Table 16 gives a brief description of each component Figure 2 Silver Cascade Development Board
22. other installed network cards Other Devices and Adapters The development board functions much like a standard desktop computer motherboard Most PC compatible peripherals can be attached and configured to work with the development board Development Kit User s Manual 2 4 Additional Required Software Not I ncluded in the Development Kit The following additional software may be necessary to operate the development board Operating System The user must supply any needed operating system installation files and licenses Application Software The user must supply any needed application software 2 5 Workspace Preparation Caution The development kit is shipped as an open system to provide flexibility in changing hardware configurations and peripherals in a lab environment Since the board is not in a protective chassis the user is required to take the following safety precautions in handling and operating the board 3 The power supply cord is the main disconnect device to main power AC power The socket outlet should be installed near the equipment and should be readily accessible 4 To avoid shock ensure that the power cord is connected to a properly wired and grounded receptacle 5 Ensure that any equipment to which this product will be attached is also connected to properly wired and grounded receptacles 6 Use a flame retardant work surface 7 Ensure a static free work environment before removing any componen
23. to the board at connector J4J1 The following steps need to be completed by the user 1 2 Attach the included CPU heatsink fan to the top of the CPU heatsink using the four screws provided Plug the fan power in at the CPU Fan connector J2B3 Connect a PS 2 keyboard at connector J1A1 bottom or connect a USB keyboard in one of the USB connectors Connect a PS 2 mouse at connector J1A1 top or a connect a USB mouse in one of the USB connectors If using the chipset s integrated graphics connect a monitor to the VGA Video output connector J2A2 with a VGA cable If using an external graphics card plug a PCIe graphics card in the PCIe x1 slot J8B3 or a PCI Express Graphics card in the PCIE x16 slot J6B2 Connect a monitor to the card For mobile power configuration unplug the ATX power supply from J4J1 Plug a mobile Intel AMPS AC to DC power adapter into J1G9 Optionally plug in a battery pack into J1H1 or J1H2 Do not mix mobile and desktop power configurations Plug in the power cord of the ATX power supply or the Intel AMPS AC brick into a standard 120 V or 240 V AC power outlet Development Kit User s Manual Getting Started i n te 2 6 1 Note Powering up the board Switch the power supply on 1 at the switch on the rear of the supply Press the power button located at SW1C1 As the system boots press F2 to enter the BIOS setup screen Check time date and configuration settings The default setting
24. 5 3 3 26 intel Development Board Features Development Board Key Features Features of the development board are summarized in the following table Table 6 Development Board Feature Set Summary Description Comments Processor Intel Core 2 Duo processor 479 pin Micro FCPGA socket Socket P with T9400 478 pin Micro FCPGA package 6MB L2 cache FSB 667 800 1067 MT s support Chipset Intel GM45 Express Graphics and 1299 pin Micro FCBGA Package Memory Controller Hub GM45 GMCH ICH9M Intel ICH9M I O Controller Hub Memory Two DDR3 SO DIMM slots Maximum 8 GB using 2 Gb technology and stacked SO DIMMs Maximum 4 GB using 2 Gb technology and non stacked SO DIMMs Minimum capacity 256 MB using 512 Mb technology Supports DDR3 Frequency of 800 amp 1067 MHz Video One PCI Express PCIe Graphics Intel GM45 Express Chipset supports four Slot monitors but only has 2 video pipes which tt h One dual channel LVDS Connector p EM Support for SPWG3 5 24 bit color panel support One VGA Connector based on planned SPWG 4 0 ls P PE S Support for two SDVO channels via x16 PCIe ideo Composite video an connector through add in cards Component video S d locki Support for UDI and native HDMI via a x16 pread spectrum clocking PCIe connector usage through Eaglemont and native HDMI through ADD card PCI PCI revision 2 3 compliant 33MHz Three 5V PCI slots are supported through PCI Extension card No PCI s
25. APC X5R 0402 10V 10 0 1uF To route TX8 from Docking connector C6D8 IPN A36096 054 to MCH CAPC X5R 0402 10V 10 0 1uF To route TX10 from Docking connector C6C16 IPN A36096 055 to MCH CAPC X5R 0402 10V 10 0 1uF To route TX10 from Docking C6C17 IPN A36096 056 connector to MCH CAPC X5R 0402 10V 10 0 1uF To route TX9 from Docking connector C6D1 IPN A36096 057 to MCH CAPC X5R 0402 10V 10 0 1uF To route TX9 from Docking connector C6D4 IPN A36096 058 to MCH RESD 0402 5 1 16W 0 R6R1 IPN A93549 001 The AUX signals of the Display Port It connects to MCH on RX9 and RX9 RESD 0402 5 1 16W 0 respectively R6R2 IPN A93549 002 RESD 0402 5 1 16W 0 To connect the level translated Hot R6R3 IPN A93549 003 Plug Docking HPD to MCH 70 Development Kit User s Manual intel Appendix B Rework lI nstructions B 1 I nternal HDMI Enabling Note All rework should use lead free solder in order to keep the board RoHS compliant Follow the instructions below to enable Internal HDMI 1 Unstuff R5T10 Figure 21 iHDMI Rework Instruction 1 F wee o O STUFF V1 5S_TVDAC VCCD TVDAC J ass QDAC uz xw 2 Stuff the following resistors R7V4 R7V3 R7V9 R7V24 and R7F7 All of the resistors should be of value 33 Q Figure 22 iHDMI Rework Instruction 2 HDA BIT CLK 21 27 HDA_RST 21 27 HDA SYNC 2127 HDA SDOUT 21 27 HD SDIN3 21 27 B 2 Enabling the I ntegra
26. BSEL Bus Select Front Side Bus frequency control signals CL Controller Link CMOS Complementary Metal Oxide Semiconductor COM Communications CPU Central Processing Unit processor CRB Customer Reference Board DC Direct Current DC Dual Core DDR Double Data Rate DDR2 Double Data Rate SDRAM version 2 DDR3 Double Data Rate SDRAM version 3 Development Kit User s Manual 11 12 ntel I ntroduction Acronym Definition DIMM Dual Inline Memory Module DMI Direct Memory Interface DOS Disk Operating System DP Display Port DPST or iDPST Intel Display Power Savings Technology EBL Extended Battery Life EC Embedded Controller ECC Error Correcting Code EHCI Enhanced Host Controller Interface EMA Extended Media Access eSATA External SATA Serial ATA ESD Electrostatic Discharge FCBGA Flip Chip Ball Grid Array FCPGA Flip Chip Pin Grid Array FS Full speed Refers to USB FSB Front Side Bus FWH Firmware Hub GbE Gigabit Ethernet GLCI Gigabit LAN Connect Interface GM45 Intel GM45 Express Graphics and Memory Controller Hub GMCH Graphics and Memory Controller Hub GND Ground VSS GPIO General Purpose Input Output HDA High Definition Audio HDMI High Definition Media Interface HS High speed Refers to USB ICH I O Controller Hub ICH9M I O Controller Hub 9M Mobile IDE Integrated Drive
27. C Intel 82802 Firmware Hub Device Disabled Display Ports 83 82 Document Number 320249 001 Add In Cards i n tel A 2 PCI Expansion Card Thimble Peak 2 Included The PCI Expansion Card Thimble Peak 2 is provided to offer 3 PCI slots and one goldfinger PCI slot on the evaluation board The expansion card also contains a floppy disk drive connector parallel port connector and a serial port connector To connect the card slide the horizontal PCI connector on Thimble Peak 2 onto the gold fingers on the development board To connect the LPC bus enabling the floppy disk drive connector parallel port connector and a serial port connector connect the ribbon cable as depicted in Figure 11 CLKRUN protocol is supported on Thimble Peak 2 board for only those PCI cards which support CLKRUN else CLKRUN should be disabled in BIOS Upon boot up the system BIOS automatically detects that the PCI expansion card is present and connected to the system The system BIOS then performs all needed initialization to fully configure the expansion card For additional information see the LPC docking connector on the evaluation board schematics Figure 11 PCI Expansion Card Thimble Peak 2 A 3 Thimble Peak2 J LPC Docking Montevina VVCRB Connector Ribbon Cable HDMI and Display Port Video I nterface Add In Card Eaglemont Included Eaglemont is an Add In Card AIC for testing and val
28. CLR jumper J5H2 Unplug the bootable USB key Verify correct BIOS installation Switch the power supply back on Press the PWR button on the board to power up the system Boot to the BIOS Configuration screen by pressing F2 at the BIOS splash screen In the BIOS main screen check that the Project Version lists the correct version of the BIOS Press the PWR key on the board to power the system back down Re connect the SATA data cable from the hard drive to the development board at connector J6J3 The system is now ready for normal operation 8 Development Kit User s Manual Development Board Features j n te 3 Development Board Features 3 1 Block Diagram Figure 1 Development Board Block Diagram mmm cr FSB 6677 80071 067 Vttz 1 05V y l 7 Dual Channel PCI Express SDVO maium DEHDMI X4 DMI KEY New in Montevina LVDS CRT VGA Clink 0 E gt 33 MHz PCI ICH M PCI E x1 Lane 0 PCI E x1 Lane 1 PCI E x1 Lane 2 12 USB 2 0 SATA port e SATA port 4 hans iml a aues enl H acu bi 3 2 Mechanical Form Factor The development board conforms to the ATX form factor The development board will fit in most standard ATX chassis A list of add in card connector and slot locations is provided in Section 4 1 Internal and rear panel system I O connectors are described in Section 4 2 Development Kit User s Manual 2
29. Cards i n tel Figure 16 AUX Pull Down Rework A 4 OPB AUXP C 2 OP8 AUXN C rl n E The resistors are e Port B R5C9 and R5C5 e Port C R5B5 and R5B4 e Port D R2C1 and R2C2 Intel High Definition Audio I nterposer Card Mott Canyon 4 Not I ncluded The Mott Canyon 4 MC4 Interposer Card is provided to enable Intel High Definition Audio Intel HD Audio and modem functionality on the development board Mott Canyon 4 provides two 30 pin MDC1 0 connectors and one 12 pin MDC1 5 connector supporting up to two Intel HD Audio codecs simultaneously The Interposer plugs into any PCIExpress or PCI slot for mechanical stability and is electrically connected to the platform via a 2x13 ribbon cable from the Mott Canyon 4 card to a 2x8 header J8E1 and 2x4 header J8E2 Headers on Mott Canyon 4 are provided for both modem and audio sideband signals MC4 provides four audio jacks and one modem jack A set of four more audio jacks may be added by using the MC4 paddle card MC4 paddle card also provides one jack each for S PDIF IN and S PDIF OUT For additional information see page 27 of the Silver Cascade schematics A diagram of the MCA interposer and paddle card on a platform is shown in Figure 17 Development Kit User s Manual 63 intel SG Figure 17 Mott Canyon 4 Interposer Card Audio Jacks Mott Canyon IV Card Ribbon Cable Quint S PDIF Jacks Analog Audio Jacks E F G H
30. EAR Ne a ar pre daa ge OEE 33 3 6 13 Serial Peripheral Interface bi 33 3 6 14 Soft Audio Soft Modem cccccccceeee esse esse eeeeeeeeeeseeeseeeseeeneeaners 34 Development Kit User s Manual 3 Appendix A Appendix B 3 0 15 SATA Storage iicet Mx EE SE 34 3 6 16 USB CONMEGCUOMS iecit re on ne rex decent REESEN EEN ee DRE Ra EE EUR 35 3 6 17 LPC Super I O SIO LPC Slot 1 eene sedens ZENS na au 36 3 6 18 Serial TER cocotte Eege maven Eege ware ee RYE UE 36 3 6 19 Intel 82802 Firmware Hub Device Support 36 3 6 20 System Management Controller SMC Keyboard Controller KBC 36 E PA MESURE LTEM 37 3 6 22 Real Time Clock meris ceux sese ieu uie rna seu xe aa EES dee a Riu Rea In cease 37 3 6 23 Thermal Monitoring NNN REENEN ENNEN ER NENNEN ENER NEEN NENNEN NN 37 3 6 24 Power Supply Solution 38 3 6 25 Manual VID support for Graphics VR 38 3 6 26 Debug Interfaces cec eg gen AEN eg ENEE KEE NEEN RR REA RR Rana 39 3 06 27 Board Form FactOr leise ee RE d NEEN dE d deer E Ne dE dE EN 39 3 7 Power Management csssssssssssssee memes enm ene enne nennen nnn nn 39 3 7 1 Power Management Gates 39 3 8 uc mmE 40 3 9 Power Measurement SUpport nmm 40 3 10 Power Supply Usage and Recommendation cesses 45 Development Board Physical Reference sssssssssssssesssesenenennenee nennen 46 4 1 Board Components EE 46 4 2 ehe A a dda went e
31. Intel XScale IPLink Itanium Itanium Inside MCS MMX Oplus OverDrive PDCharm Pentium Pentium Inside skoool Sound Mark The Journey Inside VTune Xeon and Xeon Inside are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries Other names and brands may be claimed as the property of others Copyright 2007 2008 Intel Corporation All Rights Reserved 2 Development Kit User s Manual Contents 1 Wie gelen EE 8 1 1 ellene e EE 8 1 2 Text Conventions geesde rex une tte AEN Ee DEA aa 9 1 3 Glossary of Terms and ACropnvnms memes 10 1 4 Development Kit Technical Support 14 1 4 1 Online SUpport denges er ta nnn SEENEN WEN EENS Fal na RUP E EAR IReRKR T EREXRG 14 1 4 2 Additional Technical Support ssssssssesenem mene 14 1 5 Related Documents dude get desse ceeded es Z ei gd Pa A APRI AEN RR RETI EA 15 1 5 1 Ordering Hard Copies of Documents 15 2 Getting Started assirian tesi de ta ga ERENNERT Ea das 17 2 1 OVETVIEW ge ee GE RN DU HR CE NEN 17 2 2 Development Kit Contents ek dEEERE EEN EE SES ENEE sasa nu sa na ka Ra KG ERR ENEE K ier 17 2 3 Additional Required Hardware Not Included in the Development Kit 18 2 4 Additional Required Software Not included in the Development Kit 19 2 5 Workspace Preparation estet tienen ha ert A EA ReRRR NK AE aE 19 2 6 System Setup and Power Up emen memes 20 2 6 1 Using the AC to DC Pow
32. Memory technology of Memory hardware cache is supported using Support an Intel Turbo Memory Add in card Power ACPI Compliant CO C1 C1E C2 C2E C3 C3E C4E slow C4 Management exit Intel Enhanced Deeper Sleep with Level 5 read and Deep Power Down Technology processor power states for mobility processors SO Power On S3 Suspend to RAM S4 Suspend to Disk S5 Soft Off system power states MO All Wells powered M1 Main Well down Only ME power on M off ME powered off manageability power states Form Factor ATX 2 2 like form factor 10 layer board 12 x 10 2 Miscellaneous Extended Battery Life EBL support Intel amp Display Power Saving Technology Intel DPST 4 0 support SPWG3 5 complaint LVDS panel support Mobile Digital Office initiatives TPM1 2 and support for Trusted Platform Enabling Intel AMT support Lead free design Note Review the document provided with the Development Kit titled Important Safety and Regulatory Information This document contains safety warnings and cautions that must be observed when using this development kit Development Kit User s Manual Development Board Features n te 3 4 3 4 1 Note Software Key Features The driver CD included in the kit contains all software drivers necessary for basic system functionality under the following operating systems Windows XP XP Embedded Windows Vista and Linux Wh
33. Montevina VVCRB PADDLE CARD A 4 1 Mott Canyon 4 Jumper Settings The Mott Canyon 4 Interposer has the ability to select either Primary or Secondary Intel HD Audio functionality for MDCO and MDC1 connectors with two jumper options J16 and J25 See the Table 24 below for details MDC2 supports an Intel High Definition Audio modem only codec The ICH9M supports up to 4 SDATA IN channels 0 1 2 amp 3 MC4 supports three channels 0 1 amp 2 of codecs Mapping of four ICH9M channels on MC4 card can be done using strapping resistors on the development board Three jumpers J27 J28 and J29 are used to select the appropriate SDATA IN channel for MDC The default and optional mapping of SDATA IN signals are shown in Table 24 Please be aware that SDATA IN channels 1 and 2 can also be overridden via jumpers on the evaluation platform If either SDATA IN1 or SDATA_IN2 are not shunted properly on the evaluation platform these lines will not be available to the Mott Canyon 4 Interposer Card Proper operation of the Intel HD Audio interface requires that only one SDATA IN line to be routed to one codec at a time 64 Development Kit User s Manual Add In Cards Table 24 Mott Canyon 4 Configuration Jumper Switches Settings intel Description Default Setting Optional Setting Reference Designator 3 4 for MDCO codec B ACZ_SD_0 Destination 5 6 for MDC1 codec A l MDC 0 1 2 1 2 f
34. RTC Battery BT5H1 17 eSATA connector J7J1 35 Docking connector J9C2 18 ICH9M U7F1 36 Graphics VR EU3G1 Development Kit User s Manual 47 4 2 4 2 1 48 intel Caution Connectors Development Board Physical Reference Many of the connectors provide operating voltage 5V DC and 12V DC for example to devices inside the computer chassis such as fans and internal peripherals Most of these connectors are not over current protected Do not use these connectors for powering devices external to the computer chassis A fault in the load presented by the external devices could cause damage to the computer the interconnecting cable and the external devices themselves This section describes the board s connectors Back Panel Connectors Figure 3 shows the back panel connectors on the board Figure 3 Back Panel Connectors de H 7 o HE o Table 17 Description of Back Panel Connectors Item Description Ref Item Description Ref Des Des J5A1 VGA Bottom Side 1 RJ 45 LAN 2 USB Ports 5 Connector Serial Port J2A2 Top Side Connector 2 IrDA Transceiver UAA1 6 D connector J2A1 3 Thermal Diode no stuff dei 7 PS 2 Keyboard bottom 3141 Mouse Top 4 4 USB Ports J3A1 Note The on board 14 pin D Connector J2A1 6 supplies the necessary signals to support the Composite S Video and Component TV standards Component video and composite video are conne
35. anaeaenaenenaeasa 41 Table 16 Silver Cascade Development Board Components 47 Table 17 Description of Back Panel Connectors enne 48 Table 18 Configuration Jumpers and Switches Gettings 51 Table 19 BSEL Jumper S ttingS sccccccciccscccisiegsesedee cece sad ka da vaga SEN RAN Eana eee REENEN 53 Table 20 Power On and Reset Push buttons sssssssrsssrrssrrusrrnsrrrnnrnnnrrnrnsrnnsrrnns 53 Table 21 LEDS M 55 Table 22 H8 Programming Jumpers 57 Table 23 Jumper J1 Configurations ek NENNEN ENKEN ENNEN KEEN NE NENNEN SEN ENER EEN ENN 58 Table 24 Mott Canyon 4 Configuration Jumper Switches Settings 65 Table 25 Upham IV Default Jumper Switches Gettinges ssssssrsssrrrsrrrrrrrrsrrrrsrrnne 68 Table 26 Board Rework to Support Display Port on Saddlestring 70 Development Kit User s Manual Revision History Document Revision Description Revision Date Number Number 320249 Public launch release September 2008 Note The differences between the Pillar Rock DDR2 and Silver Cascade DDR3 User Guides are in the DDR2 vs DDR3 memory controller interface the Configuration Jumpers and Switches Settings Table and the Development Board Components Table All other components and references are the same between boards Development Kit User s Manual intel Introduction 1 1 Introduction This user s manual describes the
36. ane 4 port 3 can be configured as a x1 port or a x2 port shared with port 4 can be configured via the ICH9M RPC Root Port Configuration register Development Kit User s Manual Development Board Features n tel Table 8 PCI Express Ports I CH9M Default Destination Optional Destination PCI e Port 1 PCIe Slot 1 J6B1 PCIe Docking 1 lane 2 PCIe Slot 2 J6D1 in line with Slot 1 PCIe Docking 2 lane 3 PCIe Slot 3 J8B3 4 PCIe Slot 4 J8D1 in line with Slot 3 C link south routed to this slot WLAN card support through Upham3 Add in card 5 PCIe Slot 5 J7B1 6 GLCI Intel 82567 LAN Muxed with PCIe slot5 only for testing 3 6 11 3 6 11 1 3 6 12 3 6 13 Note Slot 4 also supports controller link Upon a net detect event Slot 4 gets a switched Auxiliary 3 3 V supply PCI Slots The reference board does not have any PCI slots on the motherboard Three 5V PCI slots are supported via the Thimble Peak PCI Extension Card PCI Gold Fingers A gold finger connector S9B1 is also supplied on the development board which allows an external PCI expansion board Thimble Peak 2 to connect to it Thimble Peak 2 has three additional PCI slots allowing the user greater expansion See Appendix A for more information on the Thimble Peak 2 add in card On Board LAN The development board provides 10 100 1000 LAN through EU8A1 Intel 82567 is used on the reference board
37. ation arm until the base of the heatsink makes contact with the processor die The heatsink base should be flat on top of the processor die Figure 29 Step 8 Installing the Heatsink Development Kit User s Manual 79 CPU Thermal Solution Heatsink I nstallation intel Plug the fan connector for the heatsink onto the CPU fan header J2B3 on the 9 motherboard See the figure below The CPU fan header J2B3 is a 3 pin connector with the words CPU Fan printed beside it Figure 30 Step 9 Plugging in the Fan E ZS Ed Once the thermal solution is in place the development kit is ready to use Development Kit User s Manual 80 CPU Thermal Solution Heatsink I nstallation Figure 31 Step 10 Completed Assembly LOST d Development Kit User s Manual 81
38. cted to the development board using a D connector to component video cable with three RCA receptacles at one end and D mating connector on other end not included in the kit S video is connected to the board using a D connector to S Video cable with 4 pin DIN connector one end and D mating connector on other end not included in the kit Development Kit User s Manual ntel Development Board Physical Reference Figure 4 D Connector to Component Video Cable io oo 77777 1 Sui i gt SI A 1 a i Be ed Sie eL oc cu Figure 5 D Connector to Composite Video Cable s S 3 ib 3 gi g E 2 Bt e SCH EI o o o 9 mo d E L l 4 NM Sp X Figure 6 D Connector to S Video Cable S Video Description GND Y Ground GND CSround Y Luminance 4 C Chrominance CHE ee 49 Development Kit User s Manual i n teD Development Board Physical Reference 4 3 Configuration Settings 4 3 1 Configuration Jumpers Switches Caution Do not move jumpers with the power on Always turn off the power and unplug the power cord from the computer before changing jumper settings Else it may damage the board Note Some jumpers may fall off during shipment Jumpers that are only attached to one pin noted as 1 x are more prone to becoming detached Replacing detached 1 x jumpers is not required for prop
39. cteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them Intel processor numbers are not a measure of performance Processor numbers differentiate features within each processor family not across different processor families See http www intel com products processor number for details The Intel Core 2 Duo processor and Intel GM45 Express Chipset may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order Copies of documents which have an order number and are referenced in this document or other Intel literature may be obtained by calling 1 800 548 4725 or by visiting Intel s website at http www intel com BunnyPeople Celeron Celeron Inside Centrino Centrino logo Core Inside Dialogic FlashFile i960 InstantIP Intel Intel logo Intel386 Intel486 Intel740 IntelDX2 IntelDX4 IntelSX2 Intel Core Intel Inside Intel Inside logo Intel Leap ahead Intel Leap ahead logo Intel NetBurst Intel NetMerge Intel NetStructure Intel SingleDriver Intel SpeedStep Intel StrataFlash Intel Viiv Intel vPro
40. ction Notation Definition Signal Names Signal names are shown in uppercase When several signals share a common name an individual signal is represented by the signal name followed by a number while the group is represented by the signal name followed by a variable n For example the lower chip select signals are named CSO Z CS1 CS2 and so on they are collectively called CSn A pound symbol appended to a signal name identifies an active low signal Port pins are represented by the port abbreviation a period and the pin number e g P1 0 Glossary of Terms and Acronyms Table 2 defines terms used in this document Table 2 Definitions of Terms Term Acronym Definition Assisted Gunning Transceiver Logic The front side bus uses a bus technology called AGTL or Assisted Gunning Transceiver Logic AGTL buffers are open drain and require pull up resistors to provide the high logic level and termination AGTL output buffers differ from GTL buffers with the addition of an active pMOS pull up transistor to assist the pull up resistors during the first clock of a low to high voltage transition Asynchronous GTL The processor does not utilize CMOS voltage levels on any signals that connect to the processor As a result legacy input signals such as A20M IGNNE INIT LINTO INTR LINT1 NMI PWRGOOD SMI SLP and STPCLK utilize GTL input buffers Legacy output signals FERR
41. d 2 7 2 8 2 8 1 22 Note Note Power Down Powering down the board There are three options for powering down the system e Power down from the operating system via the Windows Start Menu or equivalent e Press the power button on the motherboard at SW1C1 to begin power down e If the system is hung it is possible to asynchronously shut the system down by holding down the power button SW1C1 continuously for 4 seconds We do not recommend powering down the board by shutting off power at the ATX power supply If the power button on the ATX power supply is used to shut down the system wait at least five seconds before turning the system on again to avoid damaging the system System BIOS A version of the AMI BIOS is pre loaded on the development board Other BIOS vendors also support the Intel Core 2 Duo with Intel GM45 Express Chipset For additional BIOS support please contact your BIOS vendor Configuring the BI OS The default BIOS settings may need to be modified to enable or disable various features of the development board The BIOS settings are configured through a menu driven user interface which is accessible during the Power On Self Test POST Press the F2 key or Delete key during POST to enter the BIOS interface For AMI BIOS POST codes visit http www ami com For BIOS Updates please contact your Intel Sales Representative Development Kit User s Manual Getting Started 2 8 2
42. d at J9E2 and J9E4 for this purpose No direct connection is provided for the Intel High Definition Audio Card on the development board the Mott Canyon 4 card is required to enable the Intel High Definition Audio functionality See Appendix A for more information on the Mott Canyon 4 card The development board supports low voltage LV High definition codecs I O R8E7 R8E8 amp R7H2 R7H3 resistors are used to select between 3 3V I O and 1 5VI O Table 9 Selection of O Voltage for the High Definition Audio 1 O Voltage for the High STUFF NO STUFF Definition Audio 3 3V Default R8E7 R7H3 R8E8 R7H2 1 5V R8E8 R7H2 R8E7 R7H3 3 6 15 Table 10 SATA Storage The development board provides four serial ATA SATA connectors One of the four serial ATA SATA connectors is a direct connect connector located at J8J1 port 0 from ICH9M The other two serial ATA connectors are cable connect connectors located at J6J3 port 1 from ICH9M amp J6J2 port 4 from ICH9M Also the development board supports an eSATA connector located at J7J1 port 5 of ICH9M The eSATA connector is available on the front edge of the board Additionally SATA port 4 can be made available at docking connector by stuffing C7W2 C7W3 C7V13 and C7V14 and making C7H1 C7H2 C7G9 and C7G8 to NO STUFF SATA Ports SATA Port Connection Type Connector Port 0 Direct Connect J8J1 Port 1 amp Port 4 Cable Connect
43. e Location Intel Core 2 Duo Processor on 45 nm Process Datasheet http www intel com design intarch core2duo tech_docs htm Mobile Intel 4 Series Express Chipset Family Datasheet http www intel com design chipset s embedded gm45 techdocs htm Intel 1 O Controller Hub 9 ICH9 Family Datasheet http www intel com design chipset s embedded gm45 techdocs htm Montevina Platform Design Guide For Intel Core 2 Duo Mobile Processor Built on 45 nm Process Technology Mobile Intel amp 45 Express Chipset and 828011 BM I O Controller Hub ICH9M Contact your Intel representative for access to this document Doc 355648 Montevina Platform CRB Schematics Silver Cascade DDR3 Customer Reference Board for Mobile Penryn Processor Cantiga and I CH9M Chipset Contact your Intel representative for access to this document Doc 355669 Ordering Hard Copies of Documents To order hard copies of product literature do the following 1 Determine the SKU Number The SKU number is listed at the bottom of the download page for that document It is also usually the first 6 digits of the name of the PDF file such as 12345612 pdf 2 Call or E mail a Request Call To place an order for a publication or text in hardcopy or CD form please contact the Intel Literature Fulfillment Centers listed in Table 5 Table 5 I ntel Literature Centers Location Telephone N
44. e back panel Six USB ports are routed to USB 2X5 front panel headers Port 1 3 at J6H4 Port 5 7 at J6H2 and Port 9 11 at J6J1 The remaining one USB port is routed to docking connector J9C2 Note The USB Port 9 is routed to the docking station interface by default By changing the straps near ICH9M Port 9 can be routed to the front panel header also The advantage of this scheme is that Port 9 can be tested on the motherboard without using the docking card Table 11 USB Ports mapping USB Port Panel Connector Port 0 Port2 Port4 Back Panel I O Connector J3A1 4 stacked USB Connector Port 6 Port 1 amp Port 3 Front Panel I O Header J6H4 Port 5 amp Port 7 Front Panel I O Header J6H2 Port 8 amp Port 10 Back Panel I O Connector J3A1 RJ45 with Dual USB Connector Port 9 amp Port 11 Front Panel I O Header J6J1 port 9 is routed to J6J1 through strapping option Port 9 Docking Connector J9C2 default Development Kit User s Manual 35 i n te Development Board Features 3 6 17 3 6 18 3 6 19 3 6 20 36 LPC Super I O SIO LPC Slot A SMSC SIO1007 serves as the SIO on the development board and is located at U7E3 Shunting the jumper at J7E1 to the 2 3 positions can disable the SIO by holding it in reset This allows other SIO solutions to be tested in the LPC slot at J8E1 A sideband header is provided at J9G1 for this purpose This sideband header also has signals for LPC power management Info
45. e e UT Ex SR ei d B ed 54 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Port 80 83 Interposer Card ies e igiene ES ENNEN EE V ege EEN 58 PCI Expansion Card Thimble Peak 2 esses 59 Eaglemont Addim Card recie eie erred Da tara e pa xa seh di tia a Fa gn 60 Location of Resistors for Rework before Rework eeseseeseeese 61 Location of Resistors for Rework after Rework teeta 61 Location of Resistors for Rework eene 62 AUX Pull Down Rework ences esee NNN nnne nnn nena hend nna ri aa 63 Mott Canyon 4 Interposer Card 64 Duck Bay 3 Interposer Card 66 Upham IV Interposer Card eere extre beth etr xen ed RR pa N E ENKEN 67 Saddlestring II Docking Conpector eset eee eee eee eee e neta eee 69 iHDMI Rework Instruction 1 0 0 0 cceceee cece eee eee eee emen 71 iHDMI Rework Instruction 2 eNNESE NENNEN ENEE seesecdianavascecdeussteechenases 7i Low Voltage HD Audio Rework Always Rail 72 Low Voltage HD Audio Rework Sus Rail 73 Step 2 Heatsink and Backpolate enne 75 Step 4 Backplate Pins iere terr enne kr enano eoe ii ce 76 Step 6 Applying the Thermal Grease eset esse eee ee eee eeeeeeeeee 77 Step 7 Squeezing Activation Arm sesssen nmn 78
46. emase Loes Reference Designator R1B4 R1P6 R3D1 R2D1 R3R14 0 019 R4G3 R4V10 R5V5 R3V1 R3F4 R4F3 R4F7 R3U2 amp R3U1 41 42 i n te j Development Board Features Component Voltage Supply Reference I nterface Plane Designator GMCH VR 1 05 V 51124_LL1_L V1 05M R4G4 GMCH VR VBATA 1 05S_VIN R4G3 GMCH 1 05V V1 05M VCC_GMCH R5U3 GMCH VCCP V1 05M VCCP_GMCH R4F5 1 05V GMCH 1 05V V1 05M V1 05M_PEG_LR R6E3 GMCH 1 05V V1 05M VCC_DMI R5D7 GMCH V_GFX VCC_GFXCORE VGFX_CORE R3F1 1 05S rees emey overs asee fe Development Kit User s Manual Development Board Features l n tel aca ae TT e Interface Plane Designator L L P uw ce H H H H AN AN LAN CI CI CI CI Ce Vias ue PCIESLOTS T Vias ue PCIESLOTA RECA Development Kit User s Manual 43 44 i n te j Development Board Features eepe cm oom meme Interface Plane Designator Dm jaw aes cor fom De e feor ee me 2 e um _ ss m sw vs qsexmam em m sw ma se mam ew wc sw wem see em EE so fex vs wes e Dmm sw vs wemm we EE EE EE EE m 5 w ass 0 seeewwe mma aw ms meussmwe RW w fess ss saranda ox ms vso f AX Lamm V12_ATX VBATA R4Y2 V12_ATX V12A R4Y1 V5SB_ATX V5SB_ATXA R5H8 Development Kit User s Manual Development Board Features n tel 3 10 Power Supply Usage and Recommendation Do not use
47. er Supply Mobile Power Mode 21 2 7 PoWer DOW ze sert deu de rata v paca ENEE Rt ENEE See des 22 2 8 System BIOS 3 thetic EET 22 2 8 1 Configuring the BIOS crna aoaaa a e EE SE 22 2 8 2 Programming BIOS Using a Bootable USB Device 23 3 Development Board Features NEEN ENNEN ENNEN NENNEN ENER RE NER NENNEN NNN NNN RENE 25 3 1 Block Digranes tere trainee aaa E aT EAA onu ed aul wa RR RT MR RR 25 3 2 Mechanical Formi Factora Ggs eg eg cedent eium ea eg E Ur PEE Ng REN n 25 3 3 Development Board Key Features 26 3 4 Software Key Features e zvekgggue ees diag ENEE EER Re RR d NES aX RERBA dE RER EN eE a 29 3 4 1 AMI BIOS f 29 3 5 Thermal Management ss NKNREREN REENEN see ninian ERR sana a nada NEEN NENNEN NS NEEN 30 3 6 System Features and Operation 30 3 6 1 Processor SupDOFL EE 30 3 6 2 Processor Voltage Regulators ccceeeeeeeee ee eee este teens eases eeeeeneeaee 30 3 6 3 Front Side BUS FSB 5 exer auneenss wt unas n ti ex ropix dates E ieee v E Roa 30 3 6 4 Processor Power Management 30 3 6 5 Processor Active Cooltmng nemen 31 3 6 6 Manual Processor Voltage ID VID Support 31 3 6 7 CHIPSET nnair 31 3 6 8 System Memlory eerta nean rhe yeh Re ia NEEN NEE ESA RT EES gen 31 3 6 9 Video Display si mE 32 3 06 10 PCIE SlOtS iiss MA 32 cR ON EMEN GE cA a sac N E a A a si 33 3 6 12 On Board LAN dee g k Ae
48. er board operation Figure 7 shows the location of the configuration jumpers and switches Table 18 summarizes the jumpers and switches and gives their default and optional settings The board is shipped with the jumpers and switches shunted in the default locations Figure 7 Location of the Configuration Jumpers Switches Mer L6 6 e Y x wu gt isaisa F k ve LI eeo ONES Z Q20 tvt eer 50 Development Kit User s Manual Development Board Physical Reference Table 18 Configuration Jumpers and Switches Settings intel Reference Default Optional Designator Description Setting Setting BSEL2 Refer to BSEL Jumper Settings 1 JiGi Section 4 3 2 for Setting Changes 1 2 1 X BSEL1 Refer to BSEL Jumper Settings 2 J1G3 Section 4 3 2 for Setting Changes 1 2 1 X BSELO Refer to BSEL Jumper Settings 3 J1G5 Section 4 3 2 for Setting Changes 1 2 1 X 4 J2B2 CPU CORE VID All OPEN CPU 1 2 Force the board to 5 J2G1 Force Shutdown 1 X Norma
49. evelopment Board Features 3 6 24 Note Note Note Note 3 6 25 38 Power Supply Solution The development board has the option to be powered from three different power sources an ATX power supply an AC DC switching power supply Mobile Brick or up to 2 external batteries The board contains all of the voltage regulators necessary to power the system up There are two main supported power supply configurations Desktop and Mobile The Desktop solution consists of only using the ATX power supply The Mobile solution consists of using the Mobile iAMPS AC Brick in conjunction with the batteries When the Mobile solution is being used either AC brick or batteries can be plugged in When both AC brick and the batteries are connected at the same time the batteries are monitored and charged if necessary Desktop peripherals including add in cards will not work in mobile power mode If desktop peripherals are used the platform must be powered using desktop power mode Please use an ATX12V 1 1 Spec compliant power supply regardless of Vendor or wattage level an ATX12V rating means V5 min current 20 1 A ATX V5 min current 1 0 A among other differences For example the Sparkle Model No FSP300 60BTVS meets this requirement and is an ATX12V 1 1 Specification compliant power supply This development board uses the Intel AMPS solution for AC brick For more details refer to Intel Adaptive Mobile Power System Intel AMPS
50. idating Display Port and HDMI interfaces supported by the GM45 GMCH The Display Port HDMI signals are multiplexed over PCIe signals of GMCH and are routed to a x16 PCIe slot on the respective motherboards This AIC is an interposer which routes these signals to Display Port HDMI connectors The AIC supports the following connectors e Two Display Port external connector or two HDMI connectors e One embedded Display Port connector Development Kit User s Manual 59 inte Ee Figure 12 Eaglemont Add in Card LAI Footprint a gt Resistor straps Lane 7 4 Lane 11 8 PCle x16 Edge Connector A 3 1 Rework to Change Eaglemont Card from HDMI to Display Port Note All rework should use lead free solder in order to keep the board RoHS compliant 1 Resistors R5D7 R5D5 R5D3 R5C19 R5C16 R5C12 and R5C11 need to be taken off and placed in the ref des R5D6 R5D4 R5D R5C18 R5C17 R5C14 R5C13 and R5C10 In the picture below the highlighted areas show where the resistors should end up Move the vertically mounted resistors horizontally 60 Development Kit User s Manual Add In Cards Figure 13 Location of Resistors for Rework before Rework Fd Xf Ves ws ch b EE b Pk Vis Es ai al alaja a 4 a ajajaja CECE E EE D CE E ETES D ii m Li Borom ae ee d E b e LU D P b P Aal D D4 ROD R D Figu
51. ile every care was taken to ensure the latest versions of drivers were provided on the enclosed CD at time of publication newer revisions may be available Updated drivers for Intel components can be found at http downloadcenter intel com For all third party components please contact the appropriate vendor for updated drivers Software in the kit is provided free by the vendor and is only licensed for evaluation purposes Refer to the documentation in your evaluation kit for further details on any terms and conditions that may be applicable to the granted licenses Customers using the tools that work with Microsoft products must license those products Any targets created by those tools should also have appropriate licenses Software included in the kit is subject to change AMI BIOS This development kit ships with AMI BIOS pre boot firmware from AMI pre installed AMI BIOS provides an industry standard BIOS on which to run most standard operating systems including Windows XP XP Embedded Linux and others The AMI BIOS Application Kit available through AMI includes complete source code a reference manual and a Windows based expert system BIOStart to enable easy and rapid configuration of customized firmware for your system The following features of AMI BIOS are enabled in the development board e DDR2 or DDR3 SDRAM detection configuration and initialization e Intel GM45 Express Chipset configuration e POST codes
52. ing and Channel A PLL DLL in use M off S3 S5 Main well down Powered off or self None Intel ME powered off refresh 3 8 3 9 40 Note The development board also supports CLKRUN Testability The development board provides an Extended Debug Port XDP for testing at J1F1 and direct processor probing The XDP interface is backwards compatible with the older ITP interface as well The user must use an XDP or ITP interface that is compatible with the Intel Core 2 Duo processor T9400 The XDP interface is backwards compatible with the ITP interface However an XDP to ITP converter cable is necessary to use the older ITP tools Also in some cases a resistor change rework is necessary to get the older ITP tools to function properly Please contact your Intel representative for additional details Power Measurement Support Power measurement resistors are provided on the platform to measure the power of most subsystems All power measurement resistors have a tolerance of 1 The value of these power measurement resistors are 2mQ by default Power on a particular subsystem is calculated using the following formula R value of the sense resistor typically 0 0020 V the voltage difference measured across the sense resistor It is recommended that the user use a high precision digital multi meter tool such as the Agilent 344014 digital multi meter Refer to Table 14 for a comparison of a high precision digi
53. l Operation shutdown 6 J2H2 GFX CORE VID All OPEN 7 J3C1 CPU thermal sensor 1 2 3 4 8 J3J2 Power ON Latch 1 X Normal Operation 1 2 Latch the power ON 1 2 Jump power state from 9 JAH1 No ME G3 to M1 support 1 X G3 to M1 1 2 Hot plug removal 10 J432 SATA Power Enable supported 1 X Hot plug not supported 11 J5G1 SRTC RST 1 X Keep ME RTC registers 1 2 Clear ME RTC registers 1 2 Clear the contents of 12 J5H2 CMOS Clear 1 X Normal Operation the CMOS 13 J7A1 In circuit SMC Programming 1 2 Normal Operation 2 3 To Program the H8 2 3 To hold the SIO in 14 J7E1 SIO Reset 1 2 Normal Operation RESET 15 J7H1 SATA interlock switch for porto 1 2 Present 1 X Removed 16 J7H2 TPM PHYSICAL PRESENCE 1 X Not Present 1 2 Present 17 J8B1 PM Lan enable 1 2 LAN Enable 2 3 LAN Disable 18 J8B2 In circuit SMC Programming 1 2 Normal Operation 2 3 To Program the H8 19 J8C1 SELCETING SPIO or SPI1 TO BE 1 X No device selected for 1 2 SPI 0 to be PROGRAMMED Programming Programmed enabled 2 3 SPI 1 to be Programmed enabled 20 J8F2 BIOS recovery 1 X Normal Operation 1 2 for BIOS recovery 21 J8G1 SV Setup 1 X Normal Operation 1 2 SV Setup 1 2 Advanced Single chip 22 J8G3 SMC MD2 1 X mode 23 J8G4 CRB SV Detect 1 X CRB 1 2 SV 1 X No external 24 J8G5 SMC MD1 1 2 Normal Operation Programming 25 J8G6 KBC disable 1 X KBC enabled 1 2 KBC disabled Development Kit User s Manual 51 intel Development Board Phy
54. less LAN System Memory The development board supports a dual channel DRR3 interface There are two DDR3 SO DIMM sockets J4P1 amp J4N1 on the development board The GMCH supports four ranks of memory at 800 or 1067 MT s on the board The maximum amount of memory supported on the Intel GM45 Express Chipset is 8 GB of DDR3 memory by utilizing 2 Gb technology in stacked SO DIMMs and 4 GB of DDR3 memory by utilizing 2 Gb technology in non stacked SO DIMMs Minimum capacity supported is 256 MB using 512 Mb technology There is no ECC support on this development board Development Kit User s Manual 31 n te j Development Board Features Video Display The reference board has six options for displaying video VGA LVDS TVOUT SDVO Display port through Add in card or PCI Express Graphics PEG Display port SDVO and PCI Express Graphics PEG are multiplexed on the same pins within the chipset The development board contains one DP SDVO PCI Express Graphics Slot J6B2 for a PCI Express compatible graphics card or an SDVO compatible graphics card ADD2N amp ADD2R one LVDS connector J6F1 one TV OUT D connector J2A1 and one 15 pin VGA connector J2A2 To support ADD2R with PCI graphic lanes reversed resistor R1U4 should be made NO STUFF By default the voltage supplied to the SDVO PCI Express Graphics slot is switched off in suspend mode and the reset signal is not gated A stuffing option allows the voltage to be supp
55. lied from voltage rails that stay on in suspend mode A different stuffing option allows the reset signal to be gated as well Details of these stuffing options can be referred on page 19 of the Silver Cascade schematics The TV is output through a D connector There are two cables in order to access TV a black D connector to S video IPN C87694 001 and a black D connector to 3 pin component IPN C87695 001 The blue coax pin can be used for composite TV interface To use a non high definition external display with the board change the resolution to 480 lines interlaced 480i in the Internal Graphics Device properties Table 7 TV Out Connections D connector Cable Composite Video Blue Cable TV Component Video Red Reg Green Green Blue Blue S Video D connector to S video Note Composite video and component video both use the same cable 3 6 10 32 PCI e Slots The ICH9M I O Controller Hub ICH9M provides 6 PCIE ports x1 Port 6 is multiplexed with Gigabit LAN Controller Interface The reference board has five x1 PCIe slots J6B1 J6D1 J8B3 J8D1 amp J7B1 Three of the five slots Slot 1 Slot 3 and Slot 5 are located at standard expansion slot locations The fourth and fifth slots Slot 2 and Slot 4 are located in line with Slot 1 and Slot 3 respectively Support for x2 on lane 1 and lane 2 Port 1 can be configured as a x1 port or a x2 port shared with port 2 and on Lane 3 and l
56. lity eeupdate exe e Other helper files contained on the included CD ROM Unplug the hard disk drive HDD SATA cable from the board at connector J6J3 so that the board will boot from the bootable USB key Record the 12 digit MAC Address of the board from the sticker near the CPU Insert the bootable USB key into one of the USB ports on the development board Switch on the power supply to 1 Press the Power PWR button on the development board Wait for the system to boot from the USB key to a DOS prompt From the DOS prompt C gt run the following and make sure that there are no warnings or errors e fpt f spifull bin Development Kit User s Manual 23 24 14 15 16 17 Getting Started From DOS run the following to reprogram the MAC address and make sure that there are no warnings or errors eeupdate nic 1 mac 00XXXXXXXXX XXXXXXXXXXXX is the MAC Address from the sticker From DOS run the following to update the keyboard and system controller flash and make sure that there are no warnings or errors n j k a b c d e 18 kscupdate ksc bin Power the system down by pressing the PWR button Clear the CMOS by performing the following Shunt the CMOS CLR jumper J5H2 near the on board battery Press the PWR button on the board The board will not power on but a couple of LEDs will flash Switch the power supply off to power down the board Remove the CMOS
57. lots on motherboard Only one PCI gold finger on board PCI Express Six x1 PCIe lanes Five x1 connectors One x16 connector Revision 1 0a compliant Two sets of 2 in line x1 PCIe slots Intel 82567 GbE controller LAN on motherboard muxed with one PCIe lane x2 PCIe lanes to docking via resistor stuffing option On Board LAN The Intel 82567 Gigabit Ethernet LAN The Intel 82567 is connected to ICH9M via LCI interface and GLCI interface Wireless Communication Wireless LAN and Bluetooth support via Upham 4 interposer WLAN WiMAX combo card Echo Peak support via Upham 4 Development Kit User s Manual Development Board Features intel Description Comments BIOS SPI Supports two compatible flash device Support for multi vendor SPI Support multi package SOIC 8 amp SOIC 16 device BIOS Intel 82802 Firmware Hub Device Support for 8 Mb Intel 82802 Firmware Hub Device using Port 80 card No Intel 82802 Firmware Hub Device connector on motherboard Support only through port 80 add in card through the TPM header Soft Audio Soft Modem Intel High Definition Audio Intel HD Audio MDC Header Support visa interposer Use Mott Canyon 4 daughter card support via sideband cable HDA routed to docking connector ATA Storage 4 SATA Ports 2 Cable Connector and 1 Direct Connect Connector one eSATA connector Both p
58. ne 48 4 2 1 Back Panel Connectors icis esiste esi NEE SEENEN NA ER NES RAS 48 4 3 Configuration Settings secet e na dE ENNER EES Ra REN Ped nab EES EE 50 4 3 1 Configuration Jumpers dGwitches eee ee eee ee eee eeeeeeaeeeeas 50 4 3 2 BSEL Jumper Settirigs ieri trit Et sia ids DEER BEN 52 4 4 Power and Reset Push Buttons eceee eee e ee eee eee ee eee ee eee eee eee eee ene 53 4 5 Net Detect BULEOM i iouis iiie ie atr ph dE deer rame kae ca vales ee paced dala dj daga d avia d 54 4 6 Np er 55 4 7 uisa ncc EE 56 4 7 1 H8 Programming Headerz meme 56 4 7 2 Sideband and Test Headerg NENNEN NENNEN NENNEN nana nena nuns 57 prep Meis 58 A 1 Port 80 83 Add in Card Included cc ccccceeeseeeeaeecnaeeeseesseceesersaeensenanae 58 A 2 PCI Expansion Card Thimble Peak 2 Included essesesseesesesese 59 A 3 HDMI and Display Port Video Interface Add In Card Eaglemont Included 59 A 3 1 Rework to Change Eaglemont Card from HDMI to Display Port 60 A 3 2 AUX Pull DOWM Rework 2 cra Eegen atr a Er RENE NH 62 AA Intel High Definition Audio Interposer Card Mott Canyon 4 Not Included 63 A 4 1 Mott Canyon 4 Jumper SettingS cccececseeeeee esses eee eee eeeeeeeeeneenas 64 A 5 ExpressCard Module Interposer Duck Bay 3 Not Included 66 A 6 PCI Express Mini Card Interposer Upham IV Not Included 67 A 7 Docking Connector Card Saddlestring II Not
59. nt board in this development kit that uses DDR2 SDRAM Development Kit User s Manual I ntroduction intel Term Acronym Definition Pin The contact point of a component package to the traces on a substrate such as the motherboard Signal quality and timings may be measured at the pin Silver Cascade The name of the development board in this development kit that uses DDR3 SDRAM System Bus The System Bus is the microprocessor bus of the processor System Management Bus A two wire interface through which various system components may communicate VCC CPU core VCC CPU core is the core power for the processor The system bus is terminated to VCC CPU core Table 3 defines the acronyms used throughout this document Table 3 Acronyms Acronym Definition AC Alternating Current ACPI Advanced Configuration and Power Interface ADD2 Advanced Digital Display 2 ADD2N Advanced Digital Display 2 Normal AGTL or AGTL Assisted Gunning Transceiver Logic See also Table 2 above AMI American Megatrends Inc BIOS developer AMPS or iAMPS Intel Adaptive Mobile Power System AMT or iAMT Intel Active Management Technology ATA Advanced Technology Attachment disk drive interface ATX Advance Technology Extended motherboard form factor BGA Ball Grid Array BIOS Basic Input Output System
60. onding to SPI 1 10 Once the programming is successful on both the SPI set J8C1 J9C1 and J9D1 to 1 X 11 Remove the flash programmer connector from J8D2 12 Set the jumper J8H1 at 1 X for booting from the SPI 8 ON Ou Document Number 320249 001 intel Appendix D CPU Thermal Solution Heatsink Installation It is necessary for the Intel Core 2 Duo processor to have a thermal solution attached to it in order to keep it within its operating temperature Caution An ESD wrist strap must be used when handling the board and installing the heatsink fan assembly A heatsink is included in the kit To install the heatsink 1 If not done already attach the CPU fan to the top of the CPU heatsink with 4 screws The label on the fan should face down 2 Remove the heatsink from its package and separate the fan heatsink portion from the heatsink backplate See the figure below Figure 25 Step 2 Heatsink and Backplate 3 Examine the base of the heatsink where contact with the processor die is made This surface should be clean of all materials and greases Wipe the bottom surface clean with isopropyl alcohol Document Number 320249 001 CPU Thermal Solution Heatsink Installation 4 Place the backplate on the underside of the development board so that the pins protrude through the holes in the development board around the processor See the figure below Figure 26 Step 4 Backplate Pins
61. or MDCO codec A 3 8 for MDC1 codecB 177 9 10 for MDC2 codec A 1 2 for MDCO codec A ACZ SD 1 Destination 3 4 for MDCO codec B 2 MDC 0 1 2 5 6 for MDC1 codec A 7 8 for MDC1 codec B J28 9 10 for MDC2 codec A 1 2 for MDCO codec A ACZ SD 2 Destination 3 4 for MDCO codec B 3 MDC 0 1 2 9 10 for MDC2 codec A 5 6 for MDC1 codeca 72 7 8 for MDC1 codec B 4 MDCO Primary Jumper 1 2 for secondary 2 3 for primary J16 5 MDC1 Primary Jumper 1 2 for secondary 2 3 for primary J25 6 3 3V Power Option 1 2 for mobile 2 3 for desktop J24 7 5 0V Power Option 2 3 for desktop 1 2 for mobile J32 MDCO Docking Emulation 8 Switch Enable 1 2 for OFF 2 3 for ON J33 MDCO Docking Emulation x 2 3 for Docking DOCK RST TA Tor Norma Emulation 129 Development Kit User s Manual 65 intel ExpressCard Module I nterposer Duck Bay 3 Not Included The Duck Bay 3 Interposer Card is a modular add in card based on the PCI Express and USB interfaces Duck Bay 3 is provided to enable both 34 mm and 54 mm ExpressCard functionality on the Silver Cascade development board To support the PCI Express interface Duck Bay 3 plugs into PCI Express slot 0 J8C1 and PCI Express slot 2 J8D1 on the board To support the USB interface Duck Bay 3 plugs into the USB front panel header J6H4 Please refer to Figure 18 for a pictorial representation of how Duck Bay 3 attaches to the development board Figure 18 Duck Bay 3 Interposer Card 66 Add In Card
62. ort 0 amp port 1 have interlock switch USB 12 USB 2 0 1 1 Ports 6 ports to Back panel I O connector 5 ports to Front panel I O connector and 1 port to Docking LPC One LPC slot Includes sideband headers SMC KBC Hitachi H8S 2117 micro controller ACPI compliant Two PS 2 ports One scan matrix keyboard connector Clocks CK 505D system clock and DB800M Three 133 166 200 233 400 MHz CPU differential clock pair Twelve 100MhZ PCIe differential pair SRC clocks Twelve 33 MHz PCI clocks 48 MHz USB clock 14 MHz ref clock 96 Mhz Dot clock Spread spectrum clocks RTC Battery backed real time clock Thermal Processor temperature sensor Monitoring Processor Intel MVP6 for processor core Voltage Regulator Power Supply Desktop Mode Mobile Mode ATX Power Supply Battery Pack smart battery support Intel Adaptive Mobile Power System Intel AMPS AC Brick Development Kit User s Manual 27 intel Development Board Features Description Comments Debug Port 80 display Through Add in card Four seven segment Interfaces displays Extended Debug Port XDP XDP connector for processor run control Test points for manageability engine JTAG LAI support Intel AMT Intel Active Management Controller Link to GMCH and to wireless LAN support Technology Intel AMT is supported on the CRBs with MO M1 and M off management states Manageability engine power plane Intel Turbo Intel Turbo
63. re 14 Location of Resistors for Rework after Rework 2 Onthe mid upper left hand section of Eaglemont card resistor locations R5B22 R5B19 R5B18 R5B16 R5B14 R5B11 R5B9 and R5B6 can be identified As mentioned in the procedure above these resistors needs to be taken off and assemble them in the ref des R5B21 R5B20 R5B17 R5B15 R5B13 R5B10 R5B8 and R5B7 Refer the pictures below for resistor location before and after rework As mentioned in the procedure above the vertically mounted resistors need to be removed and assembled horizontally on designated pads Development Kit User s Manual 61 inte SG Figure 15 Location of Resistors for Rework R5B15 R5B16 R5B17 R5B18 R5B19 RSB22 A 3 2 AUX Pull Down Rework 62 All Eaglemont cards both Fabi and Fab2 as delivered from the factory have 100 kQ pull up resistors on AUXP and AUXN These cards should be re worked so that there are 100 kQ pull downs on all AUXP and AUXN signals There are only pull downs on AUX Eaglemont cards that are to be used for Display Port require this re work This is independent of any other re works required In the figure below the resistors are incorrectly pulling up to 3 3V when they should be pulling to GROUND Note All rework should use lead free solder in order to keep the board RoHS compliant Development Kit User s Manual Add In
64. reference board implements an onboard Intel Mobile Voltage Positioning Intel MVP 6 regulator for the processor core supply The core VR solution supports PSI2 The VR will support up to 56 amps Slow C4 exit is supported to reduce perceptible audio noise caused by periodically exiting the C4 state Front Side Bus FSB The Front Side Bus FSB on the development board supports data rates of 667 MT s 167MHz quad pumped FSB 667 800 MT s 200MHz quad pumped FSB 800 amp 1067 MT s 266 MHz quad pumped FSB 1067 The FSB is AGTL and will be running at 1 05V Processor Power Management Intel Core 2 Duo processor T9400 supports CO C6 power states This processor also supports C2E and CAE Additionally the processor supports a new processor state Intel Deep Power Down Technology that brings the CPU leakage power down to the lowest possible DPWR protocol is also supported on the development board through signal H DPWRZ Development Kit User s Manual Development Board Features n tel 3 6 5 3 6 6 3 6 7 3 6 8 Processor Active Cooling The system supports PWM based FAN speed control Fan circuitry is controlled by the signal CPU PWM FAN signal from the EC PWM signal from the H8 is driven high to 3 3 V and low to 0 V at about 40 kHz carrier frequency A 3 pin header J2B3 is provided to support FAN Tacho output measurement for the CPU Manual Processor Voltage I D VI D Support The development board suppo
65. rmation on this header is on sheet 49 of the Silver Cascade schematics and is detailed in the LPC Slot and Sideband Header Specification Serial IrDA The SMSC SIO chip incorporates a serial port and IrDA Infrared as well as general purpose IOs GPIO The Serial Port connector is provided at J2A2 and the IrDA transceiver is located at U6A1 The IrDA transceiver supports SIR slow IR FIR Fast IR and CIR Consumer IR The option to select between these is supported through software and GPIO pin IR_MODE on the SIO Intel 82802 Firmware Hub Device Support It should be noted that the development board does not include an Intel 82802 Firmware Hub Device Intel 82802 Firmware Hub Device support is provided through the TPM header J9A1 A Port 80 card with an Intel 82802 Firmware Hub Device assembled can be used System Management Controller SMC Keyboard Controller KBC A Renesas H8S 2117 U9G2 serves as both System Management Controller SMC and Keyboard Controller KBC for the development board The SMC KBC controller supports two PS 2 ports battery monitoring and charging wake runtime SCI events CPU thermal monitoring Fan control GMCH thermal throttling support LPC docking support and power sequencing control The two PS 2 ports on the development board are for legacy keyboard and mouse The keyboard plugs into the bottom jack and the mouse plugs into the top jack at J1A1 Scan matrix keyboards can be suppor
66. rts manual VID operation for processor VR A jumper J2B2 is provided to incorporate VID override to allow the overriding of CPU VID outputs to the CPU VCC Core VR The intent of this VID override circuit is for ease of debug and testing Chipset The Intel GM45 Express Chipset GM45 Chipset is included on the development board The chipset consists of the GM45 Graphics and Memory Controller Hub GM45 GMCH and the ICH9M I O Controller Hub The GM45 GMCH provides a processor interface at 667 800 or 1067 MHz and two DDR3 memory interfaces running at 800 or 1067 MT s It supports internal graphics integrated LVDS 2 SDVO channels VGA TVO Display port as well as external graphics through ADD in card on a X16 PCI Express Graphics slot It also supports a manageability engine Manageability JTAG signals brought to test point 8 pin header and is connected to the ICH device via a DMI bus The ICH features twelve USB 2 0 1 1 compatible ports six back panel five front panel USB ports and one port to docking 4 Serial ATA channels two cable connects one direct connect one eSATA port an Intel High Definition Audio Intel HD Audio digital link PCI 2 3 compliant interface no slots on board slots provided on thimble peak card LPC bus six general purpose PCI Express 1 1a compliant lanes in which sixth PCI Express lane is used for Gigabit LAN interface ICH9M also provides Manageability support controller link to GMCH and to wire
67. s Duck Bay 3 ExpressCard Module Interposer Front Panel USB Cable Front Panel USB Header 2x35 Development Kit User s Manual Add In Cards A 6 PCI Express Mini Card I nterposer Upham IV Not I ncluded ntel The Upham IV board plugs into the PCI Express slots on The development board It supports the attachment of two independent PCI Express mini cards Complied with Express mini card specification Rev1 0 with USB connection enabled for each The USB interface is implemented using a separate cabling scheme The interposer supports a Bluetooth module and allows the concurrent usage of Bluetooth and PCI Express mini cards The interposer supports any specific feature that may be required for the PCI Express mini card WLAN product This interposer supports the SIM card functionality for the purpose of testing WWAN modules Figure 19 Upham IV I nterposer Card BTiCalexico Coexistence Header y mmh jn Cenmector D m ANN CRB PCIE Slot A CRB PCIE Slot B 77777 f fA Development Kit User s Manual 67 68 intel Add In Cards Table 25 Upham IV Default Jumper Switches Settings Jumper Ref Default Des Setting Description Other options JiB1 1 2 Power to BT LDO from Open 1 X Power Disabled USB J4C1 1 X Channel data to Slot2 Closed 1 2 Enable slot 2 Channel Data to BT through Opamp J2C1 2 3 H W Shutdo
68. s intel The following LEDs provide status of various functions on the development board Table 21 LEDs Function Reference Designator Keyboard number lock CR9G1 Keyboard scroll lock CR9G3 Keyboard caps lock CR9G2 System State SO CR5H4 System State S3 CR5H6 System State S4 CR5H7 System State S5 CR5H5 System State MO M1 CR5H3 SATA Activity CR7H1 VID Setting 0 CR1B1 VID Setting 1 CR1B2 VID Setting 2 CR1B3 VID Setting 3 CR1B4 VID Setting 4 CR1B5 VID Setting 5 CR1B6 VID Setting 6 CR1B7 System Power Good CR7H3 LT Status CR8G1 Development Kit User s Manual 55 i n teD Development Board Physical Reference 4 7 4 7 1 56 Note Other Headers H8 Programming Headers The microcontroller firmware for system management keyboard mouse control can be upgraded in two ways The user can either use a special DOS utility in circuit or use an external computer connected remote to the system via the serial port on the board If the user chooses to use an external computer connected to the system via the serial port there are four jumpers that must be set correctly first Please refer to Table 22 for a summary of these jumpers and refer to Figure 7 for the location of each jumper Required Hardware One Null Modem Cable and a Host Unit with a serial COM port System used to flash the SUT Here is the sequence of events necessary to program the H8 1
69. s should be sufficient for most users 5 Insert an operating system installation disk into the optical drive 6 Press F10 to save and exit the BIOS setup 7 The system reboots begins to install the operating system from the optical drive E e An operating system disk is not included in this kit and operating system installation will not be covered in this User Manual Using the AC to DC Power Supply Mobile Power Mode There are a few limitations to development board operation when using the AC to DC power adapter mobile power mode First do not mix mobile and desktop power configurations Unplug the ATX power supply from connector J4J1 before plugging in the AC to DC Power Adapter to connector J1G9 Second desktop peripherals including add in cards will not work when the board is powered by the AC to DC power adapter or a battery mobile power mode If desktop peripherals are used the development board must be powered using the included ATX power supply desktop power mode Warning Do not mix mobile and desktop power configurations Unplug the ATX power supply from connector J4J1 before plugging in the AC to DC Power Adapter to connector J1G9 or a battery not included to connector J1H1 J1H2 Warning The power supply cord is the main disconnect device from main AC power The power outlet shall be installed near the equipment and shall be readily accessible Development Kit User s Manual 21 i n te Getting Starte
70. scription of conventions used in this manual The last few sections explain how to obtain literature and contact customer support Chapter 2 0 Getting Started This chapter describes the contents of the development kit This chapter explains the basics steps necessary to get the board running This chapter also includes information on how to update the BIOS Chapter 3 0 Development Board Features This chapter provides details on the hardware features of the development board It explains the Power Management and Testability features Chapter 4 0 Development Board Physical Reference This chapter provides a list of major board components and connectors It gives a descript ion of jumper settings and functions The chapter also explains the use of the programming headers Appendix A Add In Cards This appendix contains information on add in cards available from Intel that can be used with the development board Development Kit User s Manual I ntroduction 1 2 intel Appendix B Rework Instructions This appendix contains rework instructions for the development board and for some of the add in cards to enable additional supported features and functionality Appendix C Programming system BIOS using a flash programming device This appendix provides step by step instructions on programming the flash using a flash programming device Appendix D CPU Thermal Solution Heatsink Installation Instructions
71. sical Reference Reference Default Optional Designator Description Setting Setting 26 J8H1 Boot BIOS Strap 1 2 1 X PCI to LPC 27 J9C1 PROGRAMMING SPI1 1 X 1 2 Program SPI 0 28 J9D1 PROGRAMMING SPIO 1 X 1 2 Program SPI 1 29 J9F1 KSC Enable 1 2 1 X 30 J9G2 Boot Block Programming 1 2 Normal Operation 1 X to Program the H8 31 J9H1 NMI 1 X 1 2 Disabled 32 J9H2 SATA interlock switch for porti 1 2 Present 1 X Disabled 33 J9H3 LID Position 1 X 1 2 34 J9H4 Virtual Battery 1 X 1 2 Note A jumper consists of two or more pins mounted on the motherboard When a jumper cap is placed over two pins it is designated as 1 2 When there are more than two pins on the jumper the pins to be shorted are indicated as 1 2 to short pin 1 to pin 2 or 2 3 to short pin 2 to pin 3 When no jumper cap is to be placed on the jumper it is designated as 1 X 4 3 2 BSEL Jumper Settings The jumper settings in Table 19 are provided to accommodate frequency selection for the processor Power On and Reset Push Buttons 52 Development Kit User s Manual Development Board Physical Reference Table 19 BSEL Jumper Settings Processor Intel Core 2 Duo Processor FSB Speed MHz CPU Driven J1G5 gt 1 2 J1G3 gt 1 2 J1G1 gt 1 2 1067 J1G5 gt Open J1G3 gt 2 3 J1G1 gt 2 3 800 J1G5 gt open J1G3 gt open J1G1 gt 2 3 667 J1G5 gt 2
72. tal multi meter Agilent 34401A versus a standard precision digital multi meter Fluke 79 Development Kit User s Manual Development Board Features Table 14 Digital Multi Meter Comparison Example System Sense Resistor Value 0 0022 Voltage Difference Across Resistor 1 492 mV 746 mA Calculated Power 1 113 mW Agilent 34401A 6 2 digit display Fluke 79 3 digit display Specification 0 0030 of reading 0 0030 of range Specification 0 09 2 digits Min Voltage Displayed 1 49193 mV Min Voltage Displayed 1 47 mV Calculated Power 1 1129 mW Calculated Power 1 08 mW Max Voltage Displayed 1 49206 mV Max Voltage Displayed 1 51 mV Calculated Power 1 1131 mW Calculated Power 1 14 mW Error in Power 0 009 Error in Power 0 3 As Table 14 shows the precision achieved by using a high precision digital multi meter versus a standard digital multi meter is 33 times more accurate Table 15 summarizes all the power measurement sense resistors located on the board All sense resistors are 0 002Q unless otherwise noted Reference designators marked with an asterisk are not stuffed on the board Table 15 System Voltage Rails Component Interface CPU VR CPU VR CPU VR CPU CPU GMCH VR GMCH VR GMCH VR GMCH VR GMCH VR GMCH VR GMCH VR Development Kit User s Manual elei mu Ia Joe oeo am usw msnm Loes om La e22
73. ted Trusted Platform Module iTPM 1 Populate a 2 2 kQ resistor at R1T7 on the bottom of the board A 1x2 jumper can be connected to this topology to easily enable and disable the integrated TPM When the Integrated TPM is disabled TPM commands to be sent down to the LPC header on the platform 2 Add 1 KQ to R7U9 3 Connect the 2 pin Jumper on J7H2 Note All rework should use lead free solder in order to keep the board RoHS compliant Document Number 320249 001 i n tel Rework Instructions BA B 5 Note Note Note Enabling External HDMI If using an external HDMI codec depending on the configuration Stuff R7G3 R7G2 R7V8 R7G11 and one of R9E13 or R9E10 depending on the add in card and NoStuff R7V24 R7V8 R7V3 R7V4 R5F7 R9E14 R9E12 R9E8 All rework should use lead free solder in order to keep the board RoHS compliant Support for Upham 4 Stuff R8B5 and R7C1 All rework should use lead free solder in order to keep the board RoHS compliant Low Voltage High Definition HD Audio Rework All rework should use lead free solder in order to keep the board RoHS compliant Follow the steps below to enable the Low Voltage HD Audio 1 Unstuff R8E7 and stuff R8E8 2 Unstuff R7H3 and stuff R7H2 Figure 23 Low Voltage HD Audio Rework Always Rail 72 5 7 10 12 16 27 31 38 42 44 49 51 53 56 59 V3 3A V1 5A HDA IO 2528 45 4V3 3A 1 5A HDA IO Development Kit User s Manual
74. ted via an optional connector at J9E1 Development Kit User s Manual Development Board Features j n te 3 6 21 3 6 22 3 6 23 Clocks The system clocks and spread spectrum clocks are provided by the CK505D EU6H1 clock synthesizer The FSB frequency is determined from decoding the processor BSEL settings The BSEL settings can be manually changed via jumpers J1G5 J1G3 and J1G1 Refer to Table 18 The development board also supports PCIE CLKREQ through the DB800 SRC clock buffer U7C2 In addition this CRB also supports one dual 1x8 PCI fan out buffer U7E4 Real Time Clock An on board battery at BT5H1 maintains power to the real time clock RTC when in a mechanical off state A CR2032 battery is installed on the development board Thermal Monitoring The processor has a thermal diode for temperature monitoring the thermal sensor is located at U3B3 The SMC throttles the processor if it becomes hot If the temperature of the processor rises too high the SMC alternately blinks the CAPS lock LED located at CR9G2 and NUM lock LED located at CR9G1 on the board and the board shuts down The development board supports PWM based FAN speed control As part of the thermal measurement speed of the fan is varied based on the temperature measurement 3 pin fan headers J2B3 and J3C2 are provided to support FAN Tacho output measurement for CPU and GMCH respectively Development Kit User s Manual 37 i n te D
75. these interfaces and reworks that may be required on the board The table below describes the reworks required for routing Display Port to the Docking station Note All rework should use lead free solder in order to keep the board RoHS compliant Development Kit User s Manual 69 intel Add In Cards Table 26 Board Rework to Support Display Port on Saddlestring STUFF UNSTUFF BOM Description CAPC X5R 0402 10V 10 0 1uF C6C11 IPN A36096 043 To disconnect TX11 from MCH to PEG CAPC X5R 0402 10V 10 0 1uF C6C13 IPN A36096 044 To disconnect TX11 from MCH to PEG CAPC X5R 0402 10V 10 0 1uF C6C15 IPN A36096 045 To disconnect TX10 from MCH to PEG CAPC X5R 0402 10V 10 0 1uF C6C18 IPN A36096 046 To disconnect TX10 from MCH to PEG CAPC X5R 0402 10V 10 0 1uF C6D2 IPN A36096 047 To disconnect TX9 from MCH to PEG CAPC X5R 0402 10V 10 0 1uF C6D3 IPN A36096 048 To disconnect TX9 from MCH to PEG CAPC X5R 0402 10V 10 0 1uF C6D7 IPN A36096 049 To disconnect TX7 from MCH to PEG CAPC X5R 0402 10V 10 0 1uF C6D9 IPN A36096 050 To disconnect TX7 from MCH to PEG CAPC X5R 0402 10V 10 0 1uF To route TX11 from Docking connector C6C10 IPN A36096 051 to MCH CAPC X5R 0402 10V 10 0 1uF To route TX11 from Docking C6C12 IPN A36096 052 connector to MCH CAPC X5R 0402 10V 10 0 1uF To route TX8 from Docking connector C6D6 IPN A36096 053 to MCH C
76. ts from their anti static packaging Wear an ESD wrist strap when handling the development board or other development kit components The development board is susceptible to electrostatic discharge ESD damage and such damage may cause product failure or unpredictable operation Development Kit User s Manual 19 2 6 20 intel Getting Started System Setup and Power Up Complete the following steps to operate the reference board These steps should already be completed in the kit Check these items to ensure that nothing came loose during shipment Place one or more DDR3 SO DIMMs in the memory sockets populating J5N1 and or J5P1 The memory sockets are on the bottom side of the development board Place the Intel Core 2 Duo processor T9400 in socket U2E1 and lock in place make sure to align the chip to the pin 1 marking Attach the heatsink for the processor U2E1 Install the configuration jumpers as shown in Section 4 3 1 of this document Replacing detached 1 x jumpers is not required for proper board operation Attach hard drive data cable from development board SATA Connector J6J3 to the drive with the supplied SATA data cable Attach hard drive power from the ATX power supply to the drive Attach optical drive data cable from development board SATA Connector J6J2 to the drive with the supplied SATA data cable Attach optical drive power from the ATX power supply to the drive Connect the ATX power supply
77. umber U S and Canada 1 800 548 4725 International 1 303 675 2148 Fax 1 303 675 2120 Development Kit User s Manual 15 16 nte Introduction Email To order a publication or text in hardcopy or CD form send your request to intelsupport hibbertgroup com Please make sure to include in your e mailed request SKU Company name Your name first last Full mailing address Daytime phone number in case of questions Note Please be aware not all documents are available in all media types Some may only be available as a download Development Kit User s Manual 2 1 2 2 Getting Started intel Getting Started This chapter identifies the development kit s key components features and specifications It also details basic development board setup and operation Overview The development board consists of a baseboard populated with the Intel Core 2 Duo processor the Intel GM45 Express Chipset other system board components and peripheral connectors Development Kit Contents The following hardware software and documentation is included in the development kit Check for damage that may have occurred during shipment Contact your sales representative if any items are missing or damaged e Letter to the Customer e Development Kit User s Manual this document e Software CD ROM which includes see the readme txt file for a complete list of CD ROM contents Embedded system
78. use of the Intel Core 2 Duo Processor and Intel GM45 Express Chipset development kit with DDR3 SDRAM system memory This manual has been written for OEMs system evaluators and embedded system developers This document defines all jumpers headers LED functions and their locations on the development board along with features of the board s subsystems This manual assumes basic familiarity with installing and configuring hardware and software in a personal computer system There are two development board options available as a part of this kit The first option uses DDR2 SDRAM memory The DDR2 development board is referred to as Pillar Rock The second option uses DDR3 SDRAM memory The DDR3 development board is referred to as Silver Cascade All other components and subsystems on the boards are the same unless explicitly noted This manual will cover the features and details of the Silver Cascade development board For the latest information about the Intel Core 2 Duo processor and Intel GM45 Express Chipset Development Kit visit http developer intel com design intarch devkits index htm For design documents related to the Intel Core 2 Duo processor and Intel GM45 Express Chipset please visit Processor http developer intel com design intarch core2duo tech docs htm Chipset http www intel com products embedded chipsets htm Content Overview Chapter 1 0 About This Manual This chapter contains a de
79. ver an XDP to ITP converter cable is necessary to use the older ITP tools Also in some cases a resistor change rework is necessary to get the older ITP tools to function properly Please contact an Intel representative for additional details 3 6 27 Board Form Factor The reference board form factor is similar to the full size ATX specification and uses 10 layer board 12 x 10 2 3 7 Power Management 3 7 1 Power Management States Table 12 and Table 13 list the power management states that have been defined for the development board The system s Controller Link CL operates at various power level called the M states MO is the highest power state followed by M1 and M off Table 12 System Power Management States Kee rege 0000 G0 S0 CO Full on G0 S0 C2 Quick Start STPCLK signal active G0 S0 C3 Deep Sleep CPUSTP signal active G0 S0 C4 C6 Deeper Sleep Voltage to processor core is lowered feature enabled by software G1 S3 Suspend To RAM all switched rails are turned off G1 S4 Suspend To Disk G2 S5 Soft Off G3 Mechanical Off Development Kit User s Manual 39 i n te I Development Board Features Table 13 System Power Management M States M States System Power Wells DRAM Intel ME Clocking States MO SO All wells powered Powered Clock chip powered and PLL DLL in use M1 S3 S5 Main well down In self refresh ME DRAM Clock Chip powered with only controller on using the GMCH clock runn
80. wn for BT Closed 1 2 H W Shutdown enable for BT JAC2 1 X BT clock to Slot2 Closed 1 2 Enable slot 2 Clock to BT clock through Opamp J7D1 1 2 V3 3_aux or V3 3 select Closed 1 2 V3 3_aux f ini PCIE slot 1 EIU Veggie Closed 2 3 Select V3 3 1 2 V3 3 aux 2 3 V3 3 J4D1 1 X V3 3_aux or V3 3 select Closed 1 2 V3 3_aux f ini PCIE slot 2 HU AES Closed 2 3 Select V3 3 1 2 V3 3 aux 2 3 V3 3 J6C1 1 X Channel data to slotO Closed 1 2 Enable slot 1 Channel Data to BT through op amp J6C2 2 3 BT Pri Clock to SlotO Closed 1 2 Enable slot 1 Clock to BT clock through op amp J7B1 1 X Power to BT regulator Closed 1 2 Enable 3 3V AUX power to BT regulator For additional information please refer to the Upham IV User Guide and Upham IV Schematics Development Kit User s Manual Add In Cards In tel A 7 Docking Connector Card Saddlestring 11 Not Included Saddlestring II is a docking station connector card Saddlestring II plugs into the development board by means of a docking connector This add in card has been redesigned to add support for the iAMPS solution supported on the Silver Cascade development board Also Display Port and HDMI features are added from Saddlestring It also retains all the supported features of the original Saddlestring design Figure 20 Saddlestring II Docking Connector Please refer to the Saddlestring II Fab 1 Users Guide for details on using each of

with DDR3 System Memory

Contents

Download Pdf Manuals

Related Search

Related Contents