Home

USER`S MANUAL

1. 7 1 7 3 System Clock Circuit 7 2 7 4 System Clock Control Register 7 3 7 5 Oscillator Control Register 05 7 4 7 6 STOP Control Register en n 7 4 9 1 Port 0 High Byte Control Register POCONH a 9 4 9 2 Port 0 Low Byte Control Register 9 4 9 3 Port 0 Interrupt Control Register 9 5 9 4 Port 0 Interrupt Pending Register 9 5 9 5 Port 1 High Byte Control Register 9 6 9 6 Port 1 Low Byte Control Register 9 7 9 7 Port 1 Pull up Control Register 9 7 9 8 Port 2 High Byte Control Register 2 9 8 9 9 Port 2 Low Byte Control Register 9 9 9 10 Port High Byte Control Register 9 10 9 11 Port Low Byte Control Register 9 11 9 12 Port 4 High Byte Control Register 9 12 9 13 Port 4 Low Byte Control Register 9 13 9 14 Port 5 High Byte Control Register 9 14 9 15 Port 5 Low Byte Control Register
2. E nennen nnns 5 15 Generating Interrupt Vector Addresses 5 16 Nesting Of Vectored en ehh nh 5 16 Instr ction Pointer OS ee Says quqawa a 5 16 Fast Interrupt Processing coe e hee yaq aka 5 16 Chapter 6 Instruction Set ea c DEM 6 1 Data Types al sau C 6 1 Register Addressing ccu eere Lee ee tede tette ak d n ee tes et sss 6 1 Addressing Mode u ee eve E ree ug aa 6 1 Hags Register Flags eec ite E aaa way ee 6 6 Flag Descriptions Suey ha cate cle e co deg Doe e Oe sae DOE d e OU a deg DO 6 7 INSTRUCTION Set NOtatiOn 6 8 Condition u L U E Mm 6 12 Instruction Descriptions ee a 6 13 53 8245 8245 8249 8249 MICROCONTROLLER Table of Contents Continued Table of Contents Continued Part Hardware Descriptions Chapter 7 Clock Circuit CNOI L hA a Gn decor say 7 1 System Clock 2 ror rege Irt tal ee vete a ducto eee bine sau AEE ENE 7 1 Clo
3. 53 8245 8245 8249 8249 BLOCK DIAGRAM TACON 2 Overflow TACON 7 6 Data Bus TACON 3 Pending TAOUT TACON 5 4 Timer A Data Register Read Write Data Bus Pending bit is located at INTPND register NOTE Timer A input clock must be slower than CPU clock Figure 11 2 Timer A Functional Block Diagram 11 4 ELECTRONICS 53 8245 8245 8249 8249 8 8 OVERVIEW The S3C8245 C8249 micro controller has an 8 bit counter called timer B Timer B which can be used to generate the carrier frequency of a remote controller signal Pending condition of timer B is cleared automatically by hardware Timer B has two functions Asanormal interval timer generating a timer B interrupt at programmed time intervals supply a clock source to the 16 bit timer counter module timer 0 for generating the timer 0 overflow interrupt TBCON 6 7 TBCON 2 1 2 M 4 IE To Other Block TBOF P3 0 TBPWM 8 Timer Data Low Byte Register TBCON 4 5 Timer B Data High Byte Register Data Bus NOTES 1 The value of the TBDATAL register is loaded into the 8 bit counter when the operation of the timer B starts If a borrow occurs in the counter the value of the TBDATAH register is loaded into the 8 bit counter However if the next borrow occurs the value of the TBDATAL register is loaded into the 8 bit counter
4. 8 2 3C8245 C8249 Set 1 Bank 0 Register Values after RESET 8 3 53 8245 8249 Set 1 Bank 1 Register Values after nRESET 9 1 3C8245 C8249 Port Configuration Overview 9 2 Port Data Register 13 1 Watch Timer Control Register WTCON Set 1 Bank 1 FAH R W 14 1 LCD Control Register LCON Organization 14 2 Relationship of LCON 0 and LMOD 3 Bit 14 3 LCD Clock Signal LCDCK Frame 14 4 LCD Mode Control Register LMOD Organization D1H 14 5 Maximum Number of Display Digits per Duty Cycle 14 6 LCD Drive Voltage Values 3C8245 P8245 C8249 P8249 MICROCONTROLLER Page Number List of Tables continued Table Title Page Number Number 18 1 VLDCON Value and Detection 18 2 19 1 Absolute Maximum mee mene mne nnne 19 2 19 2 D C Electrical 19 2 19 3 D C Electrical Characteristics of 53 68245 19 5 19 4 A C Electrical 19 6 19 5 Input Output L Lu tis aaa a rede ec 19 7 19 6 Data Re
5. OMUR rectc ere ene iere k aa uQ ere can eene rete unns Logical Excl siVe up ien etin am xr 53 8245 8245 8249 8249 MICROCONTROLLER Page umber xxiii 53 8245 8245 8249 8249 PRODUCT OVERVIEW PRODUCT OVERVIEW S3C8 SERIES MICROCONTROLLERS Samsung s S3C8 series of 8 bit single chip CMOS microcontrollers offers a fast and efficient CPU a wide range of integrated peripherals and various mask programmable ROM sizes Among the major CPU features are Efficient register oriented architecture Selectable CPU clock sources Idle and Stop power down mode release by interrupt Built in basic timer with watchdog function A sophisticated interrupt structure recognizes up to eight interrupt levels Each level can have one or more interrupt sources and vectors Fast interrupt processing within a minimum of four CPU clocks can be assigned to specific interrupt levels 53 8245 8245 8249 8249 MICROCONTROLLER The S3C8245 P8245 C8249 P8249 single chip CMOS Six programmable I O ports including five 8 bit microcontroller are fabricated using the highly ports and one 5 bit port for a total of 45 pins advanced CMOS process based on Samsung s newest CPU architecture Eight bit programmable pins for external interrupts The S3C8245 S3C8249 are a microcontroller with a One 8 bit basic timer for oscillation stabilization 16K byte 32K byt
6. E Sea EREA arere ee espere a Lee eee eae 2 2 Voltage Level Detector Control Register VLDCON 2 7 NJ I mn te AD Converter Control Register ADCON te imer 0 Control Regis i i i ister i ister i High Byte Low Byte Watch Timer Control Reg 5 sg gt N 91 nimi mojo 8 4 ELECTRONI S 53 8245 8245 8249 8249 nRESET POWER DOWN POWER DOWN MODES STOP MODE Stop mode is invoked by the instruction STOP opcode 7FH In Stop mode the operation of the CPU and all peripherals is halted That is the on chip main oscillator stops and the supply current is reduced to less than 3 uA All system functions stop when the clock freezes but data stored in the internal register file is retained Stop mode can be released in one of two ways by a reset or by interrupts for more details see Figure 7 3 NOTE Do not use stop mode if you are using an external clock source because Xy input must be restricted internally to Vas to reduce current leakage Using nRESET to Release Stop Mode Stop mode is released when the nRESET signal is released and returns to high level all system and peripheral control registers are reset t
7. 13 2 Watch Timer Circuit 13 3 Chapter 14 LCD Controller Driver uu MN 14 1 LOD Circuit Diagram mr EET 14 2 LCD RAM Adress AGA enrera isa 14 3 ECD Gontrol Register LOON DOE fet ne Era be exa kaskas 14 4 LGD Mode Register EMOD Matis ee Pet re ero REOR de REOR MENO RES 14 5 TEM 14 7 LCD SEG SEG 14 7 LCD Voltage Driving e De EET Long 14 12 viii 3C8245 P8245 C8249 P8249 MICROCONTROLLER Table of Contents Continued Chapter 15 10 bit Analog to Digital Converter Overview Function DESCHIPLION u Conversion TMN ku dinates A D Converter Control Register ADCON Internal Reference Voltage Levels Block Diagram Chapter 16 Serial 1 0 Interface a c Programming Procedute de thee do Hala re SIO Control Register SIO Pre Scaler Register SIOPS Block Diagra RETE c yasa kaya Serial I O Timing Diagram Chapter 17 Voltage Booster OVEIVIOW saccis e t ER Lu A ERA La Cae Lo Oma e inet UTER Le UP SERM RR TERM ER Function D
8. Interrupt Pending Register 0 0068 Instruction Pointer High Byte nme Instruction Pointer Low Byte Interrupt Priority Interrupt Request LCD Control Registers oricine eite dte ede LCD Mode Control Register Oscillator Control Register essem mme Port 0 Control Register High Port 0 Control Register Low e Port 0 Interrupt Control Port 0 Interrupt Pending Register Port 1 Control Register High Port 1 Control Register Low Port 1 Pull up Control mene mener Port 2 Control Register High Port 2 Control Register Low Port Control Register High Port Control Register Low Port 4 Control Register High Port 4 Control Register Low Port 5 Control Register High Byte Port 5 Control Register Low 53 8245 8245 8249 8249 MICROCONTROLLER Page umber xix List of
9. 4 41 CONTROL REGISTERS 53 8245 8245 8249 8249 TBCON rimer Control Register ECH Set 1 Bank 0 nRESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 Timer Input Clock Selection Bits Elapsed time for low data value Elapsed time for high data value 1 E Elapsed time for low and high data values Invalid setting 2 Ti 3 er B Start Stop Bit Stop timer B Start timer B 1 1 Timer B Mode Selection Bit 3 One shot mode 1 Repeating mode 0 Timer B Output flip flop Control Bit 0 T FF is low 1 T FF is high NOTE selected clock for system 4 42 ELECTRONICS 53 8245 8245 8249 8249 CONTROL REGISTER VLDCON Voltage Level Detector Control Register F6H Set 1 Bank 1 Bit Identifier nRESET Value Read Write Addressing Mode 7 5 ELECTRONI S T 6 5 4 3 2 4 o 0 0 0 0 0 0 0 0 R W R W R W R W R W Register addressing mode only Not used for the S3C8245 C8249 Vin Source Bit Internal source External source VLD Output Bit VN gt V REF when VLD is enabled Vin lt Vege when VLD is enabled VLD Enable disable Bit 0 Disable the VLD Enable the VLD Detection Level Bits 4 43 CONTROL REGISTERS 53 8245 8245 8249 8249 WTCON watch Timer Control Register FAH Set 1 Bank 1 nRESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R
10. 8 bit physical address Figure 2 13 8 Bit Working Register Addressing 2 16 ELECTRONICS 53 8245 8245 8249 8249 ADDRESS SPACES RPO Selects RP1 R11 8 bit address Register 1100 10 11 form instruction 10101 011 address LD R11 R2 0ABH Specifies working register addressing Figure 2 14 8 Bit Working Register Addressing Example ELECTRONICS 2 17 ADDRESS SPACES 53 8245 8245 8249 8249 SYSTEM AND USER STACK The S3C8 series microcontrollers use the system stack for data storage subroutine calls and returns The PUSH and POP instructions are used to control system stack operations The S3C8245 C8249 architecture supports stack operations in the internal register file Stack Operations Return addresses for procedure calls interrupts and data are stored on the stack The contents of the PC are saved to stack by a CALL instruction and restored by the RET instruction When an interrupt occurs the contents of the PC and the FLAGS register are pushed to the stack The IRET instruction then pops these values back to their original locations The stack address value is always decreased by one before a push operation and increased by one after a pop operation The stack pointer SP always points to the stack frame stored on the top of the stack as shown in Figure 2 15 High Address Top of stack Stack contents Stack contents after a call after an instruction interrupt Low Address F
11. the FLAGS register FLAGS 0 to logic one selecting bank 1 register addressing in the set 1 area of the register file Bank 1 is not implemented in some S3C8 series microcontrollers Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4 5F Example The statement SB1 sets FLAGS 0 to 1 selecting bank 1 register addressing if implemented ELECTRONICS 6 77 INSTRUCTION SET S3C8245 P8245 C8249 P8249 SBC subtract with Carry SBC dst src Operation dst dst src c The source operand along with the current value of the carry flag is subtracted from the destination operand and the result is stored in the destination The contents of the source are unaffected Subtraction is performed by adding the two s complement of the source operand to the destination operand In multiple precision arithmetic this instruction permits the carry borrow from the subtraction of the low order operands to be subtracted from the subtraction of high order operands Flags C Setif a borrow occurred src dst cleared otherwise Z Setif the result is 0 cleared otherwise S Setif the result is negative cleared otherwise V Setif arithmetic overflow occurred that is if the operands were of opposite sign and the sign of the result is the same as the sign of the source cleared otherwise D Always set to 1 H Cleared if there is a carry from the most significant bit of the low order four bits of the res
12. 128 3 Decimal Adjust Flag D Add operation completed Subtraction operation completed 1 2 Half Carry Flag No carry out of bit or no borrow into bit 3 by addition or subtraction Addition generated carry out of bit 3 or subtraction generated borrow into bit 3 41 Fast Interrupt Status Flag FIS Interrupt return IRET in progress when read 1 Fastinterrupt service routine in progress when read 0 Bank Address Selection Flag BA Bank 0 is selected Bank 1 is selected ELECTRONICS 4 CONTROL REGISTERS 53 8245 8245 8249 8249 IMR Interrupt Mask Register DDH Set 1 nRESET Value x x x x x x x x Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 Interrupt Level 7 IRQ7 Enable Bit External Interrupts 0 4 0 7 Disable mask 1 Enable unmask 6 Interrupt Level 6 IRQ6 Enable Bit External Interrupts 0 0 0 3 Disable mask 1 Enable unmask 5 Interrupt Level 5 IRQ5 Enable Bit Watch Timer Overflow Disable mask 1 Enable unmask 4 Interrupt Level 4 IRQ4 Enable Bit SIO Interrupt Disable mask 1 Enable unmask 3 Interrupt Level 3 IRQ3 Enable Bit Timer 1 Match Capture or Overflow Disable mask 1 Enable unmask 2 Interrupt Level 2 IRQ2 Enable Bit Timer 0 Match Disable mask 1 Enable unmask Interrupt Level 1 IRQ1 Enable Timer B Match Disable mask 1 Enable unma
13. C lt lt 0 Bits 4 7 3 bits 0 3 C R1 3CH DA R1 R1 3CH 06 If addition is performed using the BCD values 15 and 27 the result should be 42 The sum is incorrect however when the binary representations are added in the destination location using standard binary arithmetic 0001 0101 15 0010 0111 27 0011 1100 3CH DA instruction adjusts this result so that the correct BCD representation obtained 0011 1100 0000 0110 0100 0010 42 Assuming the same values given above the statements SUB 27H R0 C lt H lt 0 Bits 4 7 3 bits 0 3 1 DA R1 R1 lt 31 0 leave the value 31 BCD in address 27H 1 ELECTRONICS 53 8245 8245 8249 8249 DEC Decrement DEC Operation Flags Format Examples dst dst dst 1 The contents of the destination operand are decremented by one C Unaffected Z Setif the result is 0 cleared otherwise S Setif result is negative cleared otherwise V Setif arithmetic overflow occurred cleared otherwise D H Unaffected Unaffected Bytes Cycles Opcode Hex dst 2 4 00 01 Given R1 and register 10H DEC R1 gt R1 02H DEC R gt Register 03H OFH INSTRUCTION SET Addr Mode dst R IR In the first example if working register R1 contains the value 03H the statement DEC R1 decrements the hexadecimal value by one leaving the value 02
14. Figure 5 3 ROM Vector Address Area 5 4 ELECTRONICS 53 8245 8245 8249 8249 INTERRUPT STRUCTURE Table 5 1 Interrupt Vectors Vector Address Interrupt Source Request Reset Clear Decimal Hex Interrupt Priorityin H W S W Value Value Level Level 256 100H Basic timer overflow Reset 226 2 overflow IRQ0 0 Timer A match capture Timer B match IRQ1 Timer 0 match IRQ2 _ E6H EAH Timer 1 overflow IRQ3 i 26 SIO interrupt IRQ4 28 Watch timer overflow IRQ5 ELM IRQS 246 F6H P0 3 external interrupt 244 F4H P0 2 external interrupt 242 F2H P0 1 external interrupt 240 FOH 0 0 external interrupt 224 230 234 232 236 238 lt 2 2 2 2 254 P0 7 external interrupt 252 FCH P0 6 external interrupt 250 FAH P0 5 external interrupt 248 F8H P0 4 external interrupt NOTES 1 Interrupt priorities are identified in inverse order 0 is the highest priority 1 is the next highest and so 2 If two or more interrupts within the same level contend the interrupt with the lowest vector address usually has priority over one with a higher vector address The priorities within a given level are fixed in hardware 3 Timer A or Timer 1 can not service two interrupt sources simultaneously then only one interrupt source have to be used ELECTRONICS 5 5 INTERRUPT STRUCTURE S3C8245 P8245 C8249 P8249 ENABLE DI
15. Relative Address RA Immediate IM ELECTRONICS 3 1 ADDRESSING MODES 53 8245 8245 8249 8249 REGISTER ADDRESSING Register addressing mode R the operand value is the content of a specified register register pair see Figure 3 1 Working register addressing differs from Register addressing in that it uses a register pointer to specify an 8 byte working register space in the register file and an 8 bit register within that space see Figure 3 2 Program Memory Register File 8 bit Register OPERAND Point to One 7 DESDE Register in Register PSI OneOpeand Fe Instruction Example Value used in Instruction Execution Sample Instruction DEC CNTR Where CNTR is the label of an 8 bit register address Figure 3 1 Register Addressing Register File MSB Point to RP0 ot RP1 RPO or RP1 Selected RP points to start 7 register block Program Memory Working Register dst OPCODE 06 OPERAND Working Register Two Operand Instruction Example Sample Instruction ADD 1 R2 Where R1 and R2 are registers in the currently selected working register area Figure 3 2 Working Register Addressing 3 2 ELECTRONICS 53 8245 8245 8249 8249 ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE IR In Indirect Register IR addressing mode the content of the specified register or register pair is the address of the oper
16. 22 5 xvi 53 8245 8245 8249 8249 MICROCONTROLLER List of Programming Tips Description Page Number Chapter 2 Address Spaces Using the Page Pointer for RAM clear Page 0 1 2 5 Setting the Register Pointers aunors ansni ein aint guru eva dn 2 9 Using the RPs to Calculate the Sum of a Series of Registers 2 10 Addressing the Common Working Register 2 14 Standard Stack Operations Using PUSH and 2 19 Chapter 11 8 bit Timer A B To Generate 38 kHz 1 3 duty signal through 3 0 m enne 11 9 To Generate a one pulse signal through 0 11 10 3C8245 P8245 C8249 P8249 MICROCONTROLLER xvii Register Identifier ADCON BTCON CLKCON EMT FLAGS IMR INTPND IPH IPL IPR IRQ LCON LMOD OSCCON POCONL POINT POPND P1CONH P1CONL P1PUR P2CONH P2CONL P3CONL P4CONH P4CONL P5CONH P5CONL List of Register Descriptions Full Register Name N A D Converter Control Register Basic Timer Control System Clock Control External Memory Timing System Flags Register Interrupt Mask
17. 23H XOR RO R1 XOR RO R1 RO OC5H R1 02H RO OE4H R1 02H register 02H 23H XOR 00H 01H Register OOH 29H register 01H 02H XOR 00H 01H Register 00H 08H register 01H 02H register 02H 23H XOR 00H 54H Register 7FH gt gt gt m In the first example if working register RO contains the value 0C7H and if register R1 contains the value 02H the statement RO R1 logically exclusive ORs the R1 value with the RO value and stores the result in the destination register RO ELECTRONICS 53 8245 8245 8249 8249 CLOCK CIRCUIT CLOCK CIRCUIT OVERVIEW The clock frequency generated for the S3C8245 C8249 by an external crystal can range from 1 MHz to 10 MHz The maximum CPU clock frequency is 10 MHz The Xx and Xour pins connect the external oscillator or clock source to the on chip clock circuit SYSTEM CLOCK CIRCUIT The system clock circuit has the following components External crystal or ceramic resonator oscillation source or an external clock source Oscillator stop and wake up functions Programmable frequency divider for the CPU clock fxx divided by 1 2 8 or 16 System clock control register CLKCON Oscillator control register OSCCON and STOP control register STPCON 53 8245 8249 53 8245 8249 Figure 7 1 Main Oscillator Circuit Figure 7 2 Main Oscillator Circuit Crystal or Ceramic Oscillator RC Oscillator ELECTRONI
18. 32 768 kHz Circuit fBOOSTER 4096 HZ 512 HZ fo 128 fxx Main System Clock 4 19 MHz fxt Subsystem Clock 32 768 kHz fw Watch timer Figure 13 1 Watch Timer Circuit Diagram ELECTRONICS 13 3 53 8245 8245 8249 8249 LCD CONTROLLER DRIVER LCD CONTROLLER DRIVER OVERVIEW The S3C8245 C8249 micro controller can directly drive an up to 16 digit 32 segment LCD panel The LCD module has the following components LCD controller driver Display RAM 00H OFH for storing display data in page 4 32 segment output pins SEGO SEG31 Four common output pins COMO COM3 Three LCD operating power supply pins Vi Vi c2 LCD bias by voltage booster LCD bias by voltage dividing resistors Bit settings in the LCD mode register LMOD determine the LCD frame frequency duty and bias and the segment pins used for display output When a subsystem clock is selected as the LCD clock source the LCD display is enabled even during stop and idle modes The LCD control register LCON turns the LCD display on and off and switches current to the charge pump circuits for the display LCD data stored in the display RAM locations are transferred to the segment signal pins automatically without program control CA CB LCD VLCo VLC2 Controller Driver P UJ e S e D c SEG0 SEG31 Figure 14 1 LCD Function Diagram ELECTRONICS 14 1 L
19. 8249 Port 0 Control Register High Set 1 Bank 0 R W INT7 INT6 INT5 P0CONH bit pair pin configuration Schmitt trigger input mode pull up interrupt on falling edge Schmitt trigger input mode interrupt on rising edge Schmitt trigger input mode interrupt on rising or falling edge Output mode push pull Figure 9 1 Port 0 High Byte Control Register Port 0 Control Register Low Byte POCONL E1H Set 1 Bank 0 R W INT2 INT1 POCONL bit pair pin configuration Schmitt trigger input mode pull up interrupt on falling edge Schmitt trigger input mode interrupt on rising edge Schmitt trigger input mode interrupt on rising or falling edge Output mode push pull Figure 9 2 Port 0 Low Byte Control Register POCONL 9 4 ELECTRONICS 53 8245 8245 8249 8249 PORTS Port 0 Interrupt Control Register POINT E2H Set 1 Bank 0 R W INT7 6 INT5 4 2 INT1 INTO bit configuration settings 0 Interrupt Disable 1 Interrupt Enable Figure 9 3 Port 0 Interrupt Control Register Port 0 Interrupt Pending Register POPND E3H Set 1 Bank 0 R W err ee PND7 PND6 PND5 PND4 PND3 PND2 PND1 PNDO POPND bit configuration settings Interrupt request is not pending pending bit clear when write 0 Interrupt request is pending Figure 9 4 Port 0 Interrupt Pending Registe
20. Operation Flags Format Example 6 32 dst src RA If dst src 0 PC PC RA Ir Ir 1 The source operand is compared to subtracted from the destination operand If the result is not 0 the relative address is added to the program counter and control passes to the statement whose address is now in the program counter otherwise the instruction following the CPIUNE instruction is executed In either case the source pointer is incremented by one before the next instruction No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src 3 12 D2 r Ir NOTE Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken Given R1 02H R2 03H and register 03H 04H CPIJNE R1 R2 SKIP R2 04H PC jumps to SKIP location Working register R1 contains the value 02H working register R2 the source pointer the value 03H and general register 03 the value 04H The statement CPIJNE R1 R2 SKIP subtracts 04H 00000100B from 02H 00000010B Because the result of the comparison is non equal the relative address is added to the PC and the PC then jumps to the memory location pointed to by SKIP The source pointer register R2 is also incremented by one leaving a value of 04H Remember that the memory location must be within the allowed range of 127 to 128 ELECTRONICS 53 8245 8245 8249 8249 DA Decimal Adjust INSTRUCTION SET The destination opera
21. The set 2 register area is commonly used for stack operations 2 6 ELECTRONICS 53 8245 8245 8249 8249 ADDRESS SPACES PRIME REGISTER SPACE The lower 192 bytes 00 of the S3C8245 C8249 s four or two 256 byte register pages is called prime register area Prime registers can be accessed using any of the seven addressing modes see Chapter 3 Addressing Modes The prime register area on page 0 is immediately addressable following a reset In order to address prime registers on pages 0 1 2 3 or 4 you must set the register page pointer PP to the appropriate source and destination values Set 1 Bank 0 Bank 1 E CPU and system control ni General purpose LCD Data Peripheral and I O Register Area LCD data register Figure 2 4 Set 1 Set 2 Prime Area Register and LCD Data Register Map ELECTRONICS 2 7 ADDRESS SPACES 53 8245 8245 8249 8249 WORKING REGISTERS Instructions can access specific 8 bit registers or 16 bit register pairs using either 4 bit or 8 bit address fields When 4 bit working register addressing is used the 256 byte register file can be seen by the programmer as one that consists of 32 8 byte register groups or slices Each slice comprises of eight 8 bit registers Using the two 8 bit register pointers RP1 and RPO two working register slices can be selected at any one time to form a 16 byte working register block Using the register pointers you can move this 16 byt
22. Timer B input clock must be slower than CPU clock Figure 11 3 Timer B Functional Block Diagram ELECTRONICS 11 5 8 53 8245 8245 8249 8249 Control Register Set 1 Bank 0 R W Timer B input clock selection bits Timer B output flip flop control bit 00 fxx 0 is low 01 fxx 2 1 TBOF is high 10 fxx 4 mode selection bit 0 One shot mode 1 Repeating mode Timer B interrupt time selection bits 00 Elapsed time for low data value 01 Elapsed time for high data value 10 Elapsed time for low and high data values 11 Invalid setting Timer B start stop bit 0 Stop timer B 1 Start timer B Timer B interrupt enable bit 0 Disable interrupt 1 Enable interrupt Figure 11 4 Timer B Control Register TBCON Timer B Data Register High Byte TBDATAH FAH Set 1 Bank 0 R W Reset Value FFh Timer B Data Register Low Byte TBDATAL EBH Set 1 Bank 0 R W Reset Value FFh Figure 11 5 Timer B Data Registers TBDATAH L 11 6 ELECTRONICS 53 8245 8245 8249 8249 8 TIMER PULSE WIDTH CALCULATIONS tHIGH tLOw 2 tLow To generate the above repeated waveform consisted of low period time t ow and high period time When TBOF 0 ti ow TBDATAL 2 x 1 OH TBDATAL 100H where fx The selected clock TBDA
23. You can also use 8 bit working register addressing to access registers in a selected working register area To initiate 8 bit working register addressing the upper four bits of the instruction address must contain the value 1100 This 4 bit value 1100B indicates that the remaining four bits have the same effect as 4 bit working register addressing As shown in Figure 2 13 the lower nibble of the 8 bit address is concatenated in much the same way as for 4 bit addressing Bit 3 selects either RPO or RP1 which then supplies the five high order bits of the final address the three low order bits of the complete address are provided by the original instruction Figure 2 14 shows an example of 8 bit working register addressing The four high order bits of the instruction address 1100B specify 8 bit working register addressing Bit 4 1 selects RP1 and the five high order bits in RP1 10101B become the five high order bits of the register address The three low order bits of the register address 011 are provided by the three low order bits of the 8 bit instruction address The five address bits from RP1 and the three address bits from the instruction are concatenated to form the complete register address OABH 10101011 Selects or Address These address bits indicate 8 bit oo 8 bit logical working register address addressing Register pointer Three low order bits provides five high order bits
24. cc dst Conditional dst Unconditional If cc is true dst The conditional JUMP instruction transfers program control to the destination address if the condition specified by the condition code cc is true otherwise the instruction following the JP instruction is executed The unconditional JP simply replaces the contents of the PC with the contents of the specified register pair Control then passes to the statement addressed by the PC No flags are affected Bytes Cycles Opcode Addr Mode 2 Hex dst dst 3 8 DA cc 0 to F opc dst 2 8 30 IRR NOTES 1 The 3 byte format is used for a conditional jump and the 2 byte format for an unconditional jump 2 Inthe first byte of the three byte instruction format conditional jump the condition code and the opcode are both four bits Given The carry flag C 1 register 00 01H and register 01 20H JP C LABEL W LABEL 1000H PC 1000H JP 00H 0120H The first example shows a conditional JP Assuming that the carry flag is set to 1 the statement C LABEL replaces the contents of the PC with the value 1000H and transfers control to that location Had the carry flag not been set control would then have passed to the statement immediately following the JP instruction The second example shows an unconditional JP The statement JP 00 replaces the contents of the PC with the contents of the register pair 00H and 01H leaving t
25. external interrupt is serviced when the Stop mode release occurs Following the IRET from the service routine the instruction immediately following the one that initiated Stop mode is executed Using an Internal Interrupt to Release Stop Mode Activate any enabled interrupt causing stop mode to be released Other things are same as using external interrupt How to Enter into Stop Mode There are two ways to enter into Stop mode 1 Handling OSCCON register 2 Handling STPCON register then writing Stop instruction keep the order ELECTRONICS 8 5 nRESET POWER DOWN S3C8245 P8245 C8249 P8249 IDLE MODE Idle mode is invoked by the instruction IDLE opcode 6FH In idle mode CPU operations are halted while some peripherals remain active During idle mode the internal clock signal is gated away from the CPU but all peripherals timers remain active Port pins retain the mode input or output they had at the time idle mode was entered There are two ways to release idle mode 1 Execute a reset All system and peripheral control registers are reset to their default values and the contents of all data registers are retained The reset automatically selects the slow clock fxx 16 because CLKCON 4 and CLKCON 3 are cleared to OOB If interrupts are masked a reset is the only way to release idle mode 2 Activate any enabled interrupt causing idle mode to be released When you use an interrupt to release idle mode the CLKCON 4
26. 22 1 SMDS Product Configuration 5 052 22 2 22 2 TB8245 9 Target Board 22 3 22 3 40 Pin Connectors J101 J102 for 8245 9 22 6 224 53 8240 Cables for 80 QFP 22 6 xiv 53 8245 8245 8249 8249 MICROCONTROLLER List of Tables Table Title Number 1 1 S3C8245 C8249 Pin Descriptions a 2 1 S3C8249 P8249 Register Type Summary 2 2 S3C8245 P8245 Register Type Summary 4 1 Set T Registers 2 u A ee ree Ae fu ete 4 2 Set 1 Bank 0 Registers 02 4 3 Set 1 Bank 1 Registers 5 1 MEUPE 5 2 Interrupt Control Register Overview 5 3 Interrupt Source Control and Data 6 1 Instruction Group e meme 6 2 Flag Notation 6 3 Instruction Set 6 4 Instruction Notation Conventions 6 5 Opcode Quick Reference m 6 6 Condition Codes 8 1 S3C8245 C8249 Set 1 Register and Values after nRESET
27. Baud rate Input clock fxx 4 Pre scaler value 1 or SCK input clock where the input clock is fxx 4 SIO Pre scaler Register SIOPS F2H Set 1 Bank 0 R W Baud rate fxx 4 SIOPS 1 Figure 16 2 SIO Pre scale Registers SIOPS BLOCK DIAGRAM Pending 3 Bit Counter Clear SIOCON 3 SIOCON 1 Interrupt Enable SIOCON 7 SIOCON 4 SIOCON 2 Edge Select Shift Enable SIOCON 5 sck Mode Select SIOPS F2H bank 0 CLK g Bit SIO Shift Buffer SIODATA F1H bank 0 SIOCON 6 LSB MSB First Prescaler Value 1 SIOPS 1 Mode Select Figure 16 3 SIO Functional Block Diagram ELECTRONICS 16 3 SERIAL I O INTERFACE 53 8245 8245 8249 8249 SERIAL 1 TIMING DIAGRAM I I I I I BA d O I I I I SO Y os pos po Y poz J pot X o Transmit IRQS N Complete qe Set SIOCON 3 Figure 16 4 Serial Timing in Transmit Receive Mode Tx at falling SIOCON 4 0 Transmit IRQS Complete p Set SIOCON 3 Figure 16 5 Serial I O Timing in Transmit Receive Mode Tx at rising SIOCON 4 1 16 4 ELECTRONICS 53 8245 8245 8249 8249 VOLTAGE BOOSTER VOLTAGE BOOSTER OVERVIEW This voltage booster works for the power control of LCD generates x VR VLC2 2 x VR VLC1 1 x VR VLCO This voltage booster allows low voltage operation of LCD display with high quality This
28. ELECTRONICS 6 23 INSTRUCTION SET S3C8245 P8245 C8249 P8249 BTJRT Bit Test Jump Relative on True BTJRT Operation Flags Format Example 6 24 dst src b If src b is a 1 then PC dst The specified bit within the source operand is tested If it is a 1 the relative address is added to the program counter and control passes to the statement whose address is now in the PC otherwise the instruction following the BTJRT instruction is executed No flags are affected Bytes Cycles Opcode Addr Mode Note 1 Hex dst src dst 3 10 37 RA rb NOTE Inthe second byte of the instruction format the source address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H BTJRT SKIP R1 1 If working register R1 contains the value 07H 00000111B the statement BTJRT SKIP R1 1 tests bit one in the source register R1 Because it is a 1 the relative address is added to the PC and the PC jumps to the memory location pointed to by the SKIP Remember that the memory location must be within the allowed range of 127 to 128 ELECTRONICS 53 8245 8245 8249 8249 INSTRUCTION SET BXOR sit xor BXOR BXOR Operation Flags Format Examples dst src b dst b src dst 0 lt dst 0 src b or dst b lt dst b src 0 The specified bit of the source or the destination is logically exclusive
29. System Flags Register D5H Set 1 Bit Identifier gt j e s 4 3 2 4 o nRESET Value x x x x x x x gt 0 Read Write RW R W R W RW RW RW RW RW Bit Addressing Register addressing mode only Mode Carry Flag C Operation does not generate a carry or borrow condition Operation generates carry out or borrow into high order bit 7 Zero Flag Z Operation result is 2 value Operation result is zero Sign Flag S Operation generates positive number MSB 0 Operation generates negative number MSB 1 Read only Description of the Bit number W Write only effect of specific MSB Bit 7 R W Read write bit settings LSB Bit 0 Not used Type of addressing nRESET value notation that must be used to Not used address the bit x Undetermined value 1 bit 4 bit or 8 bit 0 2 Logic zero 1 2 Logic one Figure 4 1 Register Description Format 4 4 ELECTRONICS 53 8245 8245 8249 8249 CONTROL REGISTER ADCON A D Converter Control Register F7H Set 1 Bank 1 Bit Identifier o5 4 3 2 a 0 0 0 0 0 0 0 nRESET Value Read Write _ R W R W R W R R W R W R W Addressing Mode Register addressing mode only 7 Not used for the 53 8245 8249 6 4 A D Input Pin Selection Bits 3 End of Conversion bit read only Conversion complete Conversion complete 2 1 Clock Sou
30. TBPWM Output mode push pull 4 28 ELECTRONICS 53 8245 8245 8249 8249 CONTROL REGISTER Port4 control Register High Byte ECH Set1 Bank1 nRESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P4 7 SEG23 Mode Selection Bits o i numan output mode Push pull output mode 5 4 P4 6 SEG22 Mode Selection Bits 7119 3 2 P4 5 SEG21 Mode Selection Bits o o mme Fo t mamwepmp _ o operaen omamo 1 0 P4 4 SEG20 Mode Selection Bits output mode Push pull output mode ELECTRONICS 4 29 CONTROL REGISTERS 53 8245 8245 8249 8249 PACONL Port 4 Control Register Low Byte EDH Set 1 Bank 1 Bit Identifier 7 6 5 a gt o 0 0 0 0 0 0 0 0 nRESET Value Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P4 3 SEG19 Mode Selection Bits Input mode Input mode pull up Open drain output mode Push pull output mode Input mode Input mode pull up Open drain output mode Push pull output mode Input mode 1 Input mode pull up 1 Open drain output mode 1 Push pull output mode Input mode Input mode pull up Open drain output mode Push pull output mode 4 30 ELECTRONICS 53 82
31. Timer 1 match capture H W S W Timer 1 overflow H W S W IRQ3 IRQ4 lt Silo interrupt S W 5 Watch timer overflow Sw P0 0 external interrupt S W P0 1 external interrupt S W 2 external interrupt S W P0 3 external interrupt S W P0 4 external interrupt S W P0 5 external interrupt S W P0 6 external interrupt S W P0 7 external interrupt S W NOTES 1 Within a given interrupt level the low vector address has high priority For example has higher priority than E2H within the level IRQ 0 the priorities within each level are set at the factory External interrupts are triggered by a rising or falling edge depending on the corresponding control register setting Figure 5 2 53C8245 C8249 Interrupt Structure ELECTRONICS 5 3 INTERRUPT STRUCTURE S3C8245 P8245 C8249 P8249 INTERRUPT VECTOR ADDRESSES All interrupt vector addresses for the S3C8245 C8249 interrupt structure are stored in the vector address area of the internal 32 Kbyte ROM OH 7FFFH or 8 16 24 Kbyte see Figure 5 3 You can allocate unused locations in the vector address area as normal program memory If you do so please be careful not to overwrite any of the stored vector addresses Table 5 1 lists all vector addresses The program reset address in the ROM is 0100H Decimal 32 767 32 Kbyte 16 Kbyte Internal Program Memory ROM Area Reset Address Interrupt Vector Address Area
32. open drain K Alternative function push pull output Output mode push pull 5 4 P1 6 SCK o o fwans 71 o tureton seko 3 2 P1 5 SO A T ofwa SSCS o i _ 4 22 ELECTRONICS 53 8245 8245 8249 8249 CONTROL REGISTER P1CONL Port1 Control Register Low Byte E5H Set1 Bank 0 nRESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P1 3 KEREN Alternative function push pull output mode Output mode push pull 5 4 P1 2 T10UT T1PWM o o mame o oup moe eno o Mtema tncion HOUT 13 2 1 1 o 0 1 0 1 0 1 0 Input mode Output mode open drain Alternative function push pull output mode Output mode push pull ELECTRONICS 4 23 CONTROL REGISTERS 53 8245 8245 8249 8249 P1PUP Por 1 Pull up Control Register F5H Set 1 Bank 0 nRESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 P1 7 Pull up Resistor Enable Pull up disable je Pull up enable 6 P1 6 Pull up Resistor Enable Bit Pull up disable EB Pull up enable 5 P1 5 Pull up Resistor Enable Bit Pull up disable 1 Pull u
33. 0 P2 7 ADCO ADC7 Port 2 Converter I O Port 4 lt SI P1 7 SO P1 5 lt gt SCK P1 6 P4 0 P4 7 SEG16 SEG23 P5 0 P5 7 P3 0 P3 4 lt gt ELEGTRONIGS Port 3 I O Port 5 de SEG24 SEG31 Figure 1 1 Block Diagram 1 3 PRODUCT OVERVIEW S3C8245 P8245 C8249 P8249 PIN ASSIGNMENT 80 SEG25 P5 1 SEG24 P5 0 78 SEG23 P4 7 77 1 SEG22 P4 6 SEG21 P4 5 SEG20 P4 4 74 1 SEG19 P4 3 SEG18 P4 2 SEG17 P4 1 71 SEG16 P4 0 SEG26 P5 2 SEG27 P5 3 SEG28 P5 4 SEG29 P5 5 SEG30 P5 6 SEG31 P5 7 P3 0 TBPWM P3 1 TAOUT TAPWM SEG2 P3 2 TACLK SEG1 P3 3 TACAP SDAT SEGO P3 4 SCLK COM3 dubi 53 8245 8249 Vss COM1 XOUT 80 QFP 1420C COMO XIN VLC2 TEST VLC XTIN VLCO XTOUT CA nRESET CB 0 0 0 AVsS PO 1 INT1 AVREF PO 2 INT2 P2 7 ADC7 VVLDREF P0 3 INT3 P2 6 ADC6 P0 4 INT4 P2 5 ADC5 SEG9 SEG8 SEG7 SEG6 SEG5 SEGA SEG3 5 1 5 C3 25 PO 6 INT6 4 26 PO 7 INT7 C4 27 1 C 28 29 P1 4 BUZ 32 P1 5 50 4 33 P1 6 SCK C4 34 P1 7 8 35 P2 0 ADCO C3 36 P2 1 ADC1 37 P2 2 ADC3 38 P2 3 ADC4 C3 39 P2 4 ADC4 L3 40 P1 2 T1OUT T1PWM C4 30 NOTE The sequence of pins in TQFP package is identical with that in QFP package Figure 1 2 S3C8245 C8249 Pin Assignments 80 QFP 1420C 1 4 ELECTRONICS 53 8245 8245 8249 8249 PRODUCT OVERVIEW 80 SEG25 P5 1 79 1 SEG24 P5 0 SEG
34. 3 Timer 0 Data H L Reg Read Write Data Bus NOTES 1 Tobeloaded TODATA value to buffer register for comparing TOCON 3 bit must be set 1 2 0 input clock must be slower than CPU clock Figure 12 2 Timer 0 Functional Block Diagram ELECTRONICS 16 BIT 0 1 Timer 0 Counter Register High Byte TOCNTH F2H Set 1 Bank 1 R Reset Value 00H Timer 0 Counter Register Low Byte TOCNTL F3H Set 1 Bank 1 R Reset Value 00H Figure 12 3 Timer 0 Counter Register TOCNTH L Timer 0 Data Register High Byte TODATAH Set 1 Bank 1 R W Reset Value FFh Timer 0 Data Register Low Byte TODATAL F5H Set 1 Bank 1 R W Reset Value FFh Figure 12 4 Timer 0 Data Register TODATAH L 53 8245 8245 8249 8249 ELECTRONICS 53 8245 8245 8249 8249 16 0 1 16 1 OVERVIEW The 16 bit timer 1 is an 16 bit general purpose timer counter Timer 1 has three operating modes one of which you select using the appropriate T1CON setting Interval timer mode Toggle output at T1OUT pin Capture input mode with a rising or falling edge trigger at the T1CAP pin PWM mode T1PWM Timer 1 has the following functional components Clock frequency divider fxx divided by 1024 256 64 8 or 1 with multiplexer External clock input pin T1CLK 16 bit counter T1CNTH L 16 bit comparator and 16 bit reference data register T1 DATAH L
35. 3 Bit Settings LCON O LMOD 3 COMO0 COM3 SEGO SEG31 x Output low LCD display off Output low LCD display off 1 1 SEG24 SEG27 is selected 5 0 5 3 I O is disabled P4 4 P4 7 I O is selected 1 SEG20 SEG23 is selected P4 4 P4 7 I O is disabled P4 0 P4 3 I O is selected 1 SEG16 SEG19 is selected 4 0 4 3 I O is disabled This bit is used for internal testing only always logic zero Enable LCD initial circuit internal bias voltage 1 Disable LCD initial circuit for external LCD dividing resistors external bias voltage Stop voltage booster clock stop and cut off current charge path 1 Run voltage booster clock run and turn on current charge path 1 Output low LCD display off Output low LCD display off d COM output corresponds to display mode SEG output corresponds to display mode NOTE X means don t care 14 4 ELECTRONICS 53 8245 8245 8249 8249 LCD CONTROLLER DRIVER LCD MODE REGISTER LMOD The LCD mode control register LMOD is mapped to RAM addresses D1H LMOD controls these LCD functions Duty and bias selection LMOD 3 LMOD 0 LCDCK clock frequency selection LMOD 5 LMOD 4 The LCD clock signal LCDCK determines the frequency of COM signal scanning of each segment output This is also referred to as the frame frequency Since LCDCK is generated by dividing the watch timer clock fw the watch timer must be enabled when the LCD display is turned on Reset clears the LMO
36. 7 is push pull output Output mode push pull NOTE When use this port 1 user must be care of the pull up resistance status Figure 9 5 Port 1 High Byte Control Register P1 CONH 9 6 ELECTRONICS 53 8245 8245 8249 8249 PORTS Port 1 Control Register Low P1CONL 5 Set 1 Bank 0 R W P1 0 T1CAP P1 dex P1 2 T1OUT P1 3 T1PWM P1CONL bit pair pin configuration settings Input mode T1CAP T1CLK Output mode open drain Alternative function T1OUT T1PWM other pins are push pull are push pull output mode Output mode push pull When use this port 1 user must be care of the pull up resistance status Figure 9 6 Port 1 Low Byte Control Register P1CONL Port 1 Pull up Control Register P1PUR F5H Set 1 Bank 0 R W Teer eT eT P1 0 17 P1 6 P1 5 P1 4 P1 3 P1 2 P1 1 P1PUP bit configuration settings 0 Pull up Disable 1 Pull up Enable Figure 9 7 Port 1 Pull up Control Register P1PUP ELECTRONICS 5 53 8245 8245 8249 8249 2 Port 2 is an 8 bit I O port that can be used for general purpose I O as A D converter inputs ADCO ADC7 pins are accessed directly by writing or reading the port 2 data register P2 at location F8H set 1 bank 0 To individually configure the port 2 pins P2 0 P2 7 you make bit pair settings in two control registers located in set 1 bank 0 P2ECONL low byte E7H and P2CONH high byte E6H In i
37. 8 bit Timer A B Chapter 19 Electrical Data Chapter 12 16 bit Timer 0 1 Chapter 20 Mechanical Data Chapter 13 Watch Timer Chapter 21 53 8245 8249 OTP Chapter 14 LCD Controller Driver Chapter 22 Development Tools Two order forms are included at the back of this manual to facilitate customer order for S8C8245 P8245 C8249 P8249 microcontrollers the Mask ROM Order Form and the Mask Option Selection Form You can photocopy these forms fill them out and then forward them to your local Samsung Sales Representative 53 8245 8245 8249 8249 MICROCONTROLLER iii Table of Contents Part Programming Model Chapter 1 Product Overview S9G8 Series Microcontrollers oi Perte Ir dete estet Miet Eb ir do E x Reiter oes 1 1 S3C8245 P8245 C8249 P8249 1 1 GIA asam yaa Sakata IMEEM 1 1 WI 1 2 tad 1 3 item DEED 1 4 E MULUS 1 6 Eolo cp Tn 1 7 Chapter 2 Address Spaces a ep ee ci b RR een eee 2 1 Program Memory ROM iota tenete 2 2 Register u wood c aqa dead 2 3 Register Pag
38. 8249 ADDRESS 5 5 PROGRAMMING Standard Stack Operations Using PUSH and POP The following example shows you how to perform stack operations in the internal register file using PUSH and POP instructions LD SPL 0FFH SPL Normally the SPL is set to OFFH by the initialization routine PUSH PP Stack address OFEH PUSH RPO Stack address OFDH PUSH RP1 Stack address OFCH lt PUSH R3 Stack address OFBH lt R3 POP R3 R3 lt Stack address OFBH POP RP1 RP1 lt Stack address OFCH POP RPO RPO lt Stack address OFDH POP PP PP lt Stack address OFEH ELECTRONICS 2 19 53 8245 8245 8249 8249 ADDRESSING MODES ADDRESSING MODES OVERVIEW Instructions that are stored in program memory are fetched for execution using the program counter Instructions indicate the operation to be performed and the data to be operated on Addressing mode is the method used to determine the location of the data operand The operands specified in SAM88RC instructions may be condition codes immediate data or a location in the register file program memory or data memory The S3C8 series instruction set supports seven explicit addressing modes Not all of these addressing modes are available for each instruction The seven addressing modes and their symbols are Register R Indirect Register IR _ Indexed X Direct Address DA Indirect Address IA
39. A B 9 Bit Tero A a eae ieee esas M CM 11 1 SIL UM 11 1 Function 2 21 11 2 Time A Control Register arauaren cte tete pre aa uka de eura ke lade arn gated ae 11 3 BIOCK Diarra METTE 11 4 8 Bit ender the 11 5 OVOIVIBW cher LC S Lan 11 5 Timer B Pulse Width 11 7 Chapter 12 16 bit Timer 0 1 16 Bit Timer iea e ede ap oae ee eg o edo Ove ica Son de dede deg 12 1 oM A OP 12 1 Function Description 12 1 Timer 0 Control Register 12 2 Block Diagram vii ie h a e dade ou eee 12 3 16 BIt Timer Lc y has et Laer eet e tee eR ter ee Lab 12 5 12 5 Function Description ER 12 6 Timer 1 Control Register 1 12 7 a eu DL 12 8 Chapter 13 Watch Timer S CN RC EE 13 1 Watch Timer Control Register WTCON
40. A has the following functional components Clock frequency divider fxx divided by 1024 256 or 64 with multiplexer External clock input pin TACLK 8 bit counter TACNT 8 bit comparator and 8 bit reference data register O pins for capture input or PWM or match output TAPWM TAOUT Timer A overflow interrupt IRQO vector E2H and match capture interrupt IRQO vector generation Timer A control register TACON set 1 EDH read write ELECTRONICS 11 1 8 53 8245 8245 8249 8249 FUNCTION DESCRIPTION Timer A Interrupts IRQ0 Vectors E0H and E2H The timer A module can generate two interrupts the timer A overflow interrupt TAOVF and the timer A match capture interrupt TAINT TAOVF is interrupt level IRQ0 vector E2H TAINT also belongs to interrupt level IRQ0 but is assigned the separate vector address E0H Pending condition of timer interrupts overflow amp match capture can be cleared automatically by hardware where the interrupts are enabled Otherwise pending condition must be cleared manually by software Interval Timer Function The timer A module can generate an interrupt the timer A match interrupt TAINT TAINT belongs to interrupt level IRQ0 and is assigned the separate vector address E0H When timer A match interrupt occurs and is serviced by the CPU the pending condition is cleared automatically by hardw
41. Continued Register File Rega Lucr n T RPO or RPO or RP1 Selected RP points to start of workin Program Memory sehn OFFSET NI OPCODE 2 p 1 of 4 16 Bit block address added to Program Memory offset LSB Selects or Data Memory 8 Bits 16 Bits OPERAND Value used in 16 Bits Instruction LDG R4 04H RR2 The values in the program address RR2 04H are loaded into register R4 LDE R4 04H RR2 Identical operation to LDC example except that external program memory is accessed Sample Instructions Figure 3 8 Indexed Addressing to Program or Data Memory with Short Offset 3 8 ELECTRONICS 53 8245 8245 8249 8249 ADDRESSING MODES INDEXED ADDRESSING MODE Concluded Register File sss RPO or RPO or Selected RP points Program Memory to m of working OFFSET register OFFSET NEXT 2 Bits 4 bit Working dst src L Register Register Address OPCODE Point to Working Pair block p gt ihrer 16 Bit address added to p Program Memory offset LSB Selects or Data Memory 8 Bits 16 Bits OPERAND Value used in 16 Bits w Instruction Sample Instructions LDG R4 1000H RR2 The values in the program address RR2 1000H are loaded into register R4 LDE R4 1000H RR2 Identical operation to LDC example except that external program memory is accessed Figure 3 9 Indexed Addressing to Program or Data M
42. E9H Set 1 Bank 0 R W P3 0 TBPWM P3 P3 2 TACLK P3 3 TACAP P3CONL bit pair pin configuration settings Input mode TACAP TACLK Input mode pull up TACAP Alternative function TAOUT TAPWM TBPWM P3 2 P3 3 is push pull output mode Output mode push pull Figure 9 11 Port 3 Low Byte Control Register PSCONL ELEGTRONIGS 5 53 8245 8245 8249 8249 PORT 4 Port 4 is 8 bit I O port with individually configurable pins Port 4 pins accessed directly by writing or reading the port 4 data register P4 at location in set 1 bank 0 P4 0 P4 7 can serve as inputs with or without pull ups as output open drain or push pull And they can serve as segment pins for LCD also Port 4 Control Registers Port 4 has two 8 bit control registers PACONH for P4 4 P4 7 and PACONL for P4 0 P4 3 A reset clears the PACONH and P4CONL registers to configuring all pins to input mode Port 4 Control Register High Byte PACONH ECH Set 1 Bank 1 R W P4 4 SEG20 P4 a P4 6 SEG22 P4 7 SEG23 P4CONH bit pair pin configuration settings Input mode Input mode pull up Opendrain output mode Output mode push pull NOTE LCD is enabled by LCON 5 SEG signal go out otherwise port 4 1 0 can be selected Figure 9 12 Port 4 High Byte Control Register 9 12 ELECTRONICS 53 8245 8245 8249 8249 PORTS Port 4 Control R
43. Flags Format Example dst src RA If dst src 0 PC RA lt Ir 1 The source operand is compared to subtracted from the destination operand If the result is 0 the relative address is added to the program counter and control passes to the statement whose address is now in the program counter Otherwise the instruction immediately following the CPIJE instruction is executed In either case the source pointer is incremented by one before the next instruction is executed No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src dk G r h NOTE Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken Given R1 02H R2 and register 02H R1 R2 SKIP R2 04H PC jumps to SKIP location In this example working register R1 contains the value 02H working register R2 the value 03H and register 03 contains 02H The statement R1 R2 SKIP compares the R2 value 02H 00000010B to 02H 00000010B Because the result of the comparison is equal the relative address is added to the PC and the PC then jumps to the memory location pointed to by SKIP The source register R2 is incremented by one leaving a value of 04H Remember that the memory location must be within the allowed range of 127 to 128 ELECTRONICS 6 31 INSTRUCTION SET S3C8245 P8245 C8249 P8249 CPIJNE Compare Increment and Jump on Non Equal CPIJNE
44. INT7 Interrupt Pending Bit Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending 6 PO 6 INT6 Interrupt Pending Bit Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending 5 P0 5 INT5 Interrupt Pending Bit Interrupt request is not pending pending bit clear when write 0 Interrupt request is pending 4 P0 4 INT4 Interrupt Pending Bit Interrupt request is not pending pending bit clear when write 0 je Interrupt request is pending 3 P0 3 INT3 Interrupt Pending Bit Interrupt request is not pending pending bit clear when write 0 je Interrupt request is pending 2 P0 2 INT2 Interrupt Pending Bit Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending 41 P0 1 INT1 Interrupt Pending Bit Interrupt request is not pending pending bit clear when write 0 Interrupt request is pending 0 PO O INTO Interrupt Pending Bit Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending ELECTRONICS 4 2 CONTROL REGISTERS 53 8245 8245 8249 8249 P1CONH Port 1 Control Register High Byte E4H Set 1 Bank 0 Bit Identifier 5 3 2 o 0 0 0 0 0 0 0 0 nRESET Value Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P1 7 SI o Input mode SI Output mode
45. IRQ Interrupt Request Register DCH Set 1 nRESET Value 0 0 0 0 0 0 0 0 Read Write R R R R Addressing Mode Register addressing mode only 7 Level 7 IRQ7 Request Pending Bit External Interrupts 0 4 0 7 Not pending FB Pending 6 Level 6 IRQ6 Request Pending Bit External Interrupts 0 0 0 3 Not pending Pending 5 Level 5 IRQ5 Request Pending Bit Watch Timer Overflow Not pending Pending 4 Level 4 IRQ4 Request Pending Bit SIO Interrupt Not pending Pending 3 Level 3 IRQ3 Request Pending Bit Timer 1 Match Capture or Overflow ot pending ending 2 Level 2 IRQ2 Request Pending Bit Timer 0 Match ot pending ending 4 Level 1 IRQ1 Request Pending Bit Timer Match Not pending je Pending 0 Lev I 0 0 Request Pending Match Capture Overflow Not pending Pending 4 14 ELECTRONICS 53 8245 8245 8249 8249 CONTROL REGISTER Lcp control Register D0H Set1 nRESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W _ R W R W R W Addressing Mode ELECTRONI S Register addressing mode only LCD Output Segment and Pin Configuration Bits P5 4 P5 7 I O is selected 1 SEG28 SEG 1 is selected P5 4 P5 7 I O is disabled LCD Output Segment and Pin Configuration Bits P5 0 P5 3 is selected SEG24 SEG27 is selected P5 0 P5 3 I O is disabled LCD Output Segment and
46. JR NZ LOOP ELECTRONICS 53 8245 8245 8249 8249 INSTRUCTION SET DI Disable Interrupts DI Operation Flags Format Example SYM 0 0 Bit zero of the system mode control register SYM 0 is cleared to 0 globally disabling all interrupt processing Interrupt requests will continue to set their respective interrupt pending bits but the CPU will not service them while interrupt processing is disabled No flags are affected Bytes Cycles Opcode Hex opc 1 4 8F Given SYM 01H DI If the value of the SYM register is 01H the statement DI leaves the new value in the register and clears SYM 0 to 0 disabling interrupt processing Before changing IMR interrupt pending and interrupt source control register be sure DI state ELECTRONICS 6 37 INSTRUCTION SET S3C8245 P8245 C8249 P8249 DIV pivide Unsigned DIV dst src Operation dst src dst UPPER REMAINDER dst LOWER QUOTIENT The destination operand 16 bits is divided by the source operand 8 bits The quotient 8 bits is stored in the lower half of the destination The remainder 8 bits is stored in the upper half of the destination When the quotient is gt 28 the numbers stored in the upper and lower halves of the destination for quotient and remainder are incorrect Both operands are treated as unsigned integers Flags Set if the V flag is set and quotient is between 28 and 29 41 cleared otherwi
47. Operation Flags Format Examples dst src dst src m lt m 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file The address of the memory location is specified by a working register pair The contents of the source location are loaded into the destination location The memory address is then decremented The contents of the source are unaffected LDCD references program memory and LDED references external data memory The assembler makes an even number for program memory and an odd number for data memory No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src Given R6 10H R7 33H R8 12H program memory location 1033H and external data memory location 1033H ODDH LDCD R8 RR6 OCDH contents of program memory location 1033H is loaded into R8 and RR6 is decremented by one R8 R6 10H R7 32H RR6 lt RR6 1 LDED R8 RR6 ODDH contents of data memory location 1033H is loaded into R8 and RR6 is decremented by one RR6 lt RR6 1 R8 ODDH R6 10H R7 32H ELECTRONICS 6 55 INSTRUCTION SET S3C8245 P8245 C8249 P8249 LDCI LDEI Load Memory and Increment LDCI LDEI Operation Flags Format Examples 6 56 dst src dst src m rr 1 These instructions are used for user stacks or block transfers of data from program or data memory to the registe
48. Output mode push pull 5 4 P2 2 ADC2 o o mame 13 2 P2 1 ADC1 o o mame 0 o ajus Mtema turton a00 moa 1 0 P2 0 ADCO o ijo 1 Alternative function ADC mode Output mode push pull 4 26 ELECTRONICS 53 8245 8245 8249 8249 CONTROL REGISTER P3CONH Port 3 Control Register High Byte E8H Set 1 Bank 0 nRESET Value 0 0 0 0 0 0 0 0 Read Write R W R W Addressing Mode Register addressing mode only 7 2 Not used for the 53 8245 8249 1 0 P3 4 Mode Selection Bits Fo _ Output mode push pull ELECTRONICS 4 27 CONTROL REGISTERS 53 8245 8245 8249 8249 P3CONL Port3 Control Register Low Byte E9H Set 1 Bank 0 Bit Identifier _ _ 5 a 3 2 o 0 0 0 0 0 0 0 0 nRESET Value Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P3 3 TACAP Mode Selection Bits Input mode TACAP Input mode pull up TACAP Output mode push pull Output mode push pull Input mode TACLK 1 Input mode pull up Output mode push pull 1 Output mode push pull Input mode 1 Input mode pull up 1 0 Alternative function TAOUT or TAPWM 1 Output mode push pull Input mode Input mode pull up Alternative function
49. Register Descriptions continued Register Full Register Name Page Identifier Number PP Register Page 4 33 RP0 02 be ep Mete er ene eeu ie quoc cp o Mete 4 34 Fegister Polnter courte teet A 4 34 SIOCON SIO Gontrol Registet codec ieee entree iy dee u T de a v 4 35 SPH Stack Pointer High Byle u u u eene eene hens 4 36 SPL Stack Pointer LOW Byte He Etre et RR ae addins 4 36 STPCON Stop Control Reglster E Lee uk ER ett s 4 37 SYM System Mode Register 4 38 TOCON Timer 0 Control 4 39 Timer 1 ControL Register coiere irte he ed cedo E Pet 4 40 TACON Timer Control Register eiie E erae EE M 4 41 TBCON Timer B Control 4 42 VLDCON Voltage Level Detector Control 4 43 WTCON Watch Timer Control 4 44 53 8245 8245 8249 8249 MICROCONTROLLER Instruction Mnemonic ADC ADD AND BAND BCP BITC BITR BITS BOR BTJRF BTJRT BXOR CALL CCF CLR COM CPIJE CPIJNE DA DEC DECW DI DIV DJNZ EI ENTER EXIT IDLE INC INCW IRET JP JR LD LDB List of I
50. Schmitt trigger input mode pull up interrupt on falling edge Schmitt trigger input mode interrupt on rising edge ilo Schmitt trigger input mode interrupt on rising or falling edge Output mode push pull CONTROL REGISTERS 53 8245 8245 8249 8249 POINT Porto Interrupt Control Register E2H Set 1 Bank 0 nRESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 7 External Interrupt INT7 Enable Disable interrupt je Enable interrupt 6 P0 6 External Interrupt INT6 Enable Bit Disable interrupt je Enable interrupt 5 0 5 External Interrupt 5 Enable Bit Disable interrupt je Enable interrupt 4 0 4 External Interrupt 4 Enable Bit Disable interrupt je Enable interrupt 3 0 3 External Interrupt INT3 Enable Bit Disable interrupt Enable interrupt 2 0 2 External Interrupt INT2 Enable Bit Disable interrupt Enable interrupt RB 1 P0 1 External Interrupt INT1 Enable Bit Disable interrupt Enable interrupt le 0 P0 0 External Interrupt INT0 Enable Bit Disable interrupt Enable interrupt 4 20 ELECTRONICS 53 8245 8245 8249 8249 CONTROL REGISTER POPND Port o Interrupt Pending Register Set 1 Bank 0 nRESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 P0 7
51. Top EOT Offset Error of EOB Bottom Analog input voltage VIAN Analog input RAN impedance Analog reference AV REF voltage Analog ground AVss Analog input current IADIN Analog block lADC current 2 Linearity ILE AV pee Vpp 5 V AVggr Vpp 5 V AV per Vpp 3 V AVper Vpp 5 V When power down mode NOTES ELECTRICAL DATA x lt lt re 3 2 1 Conversion time is the time required from the moment a conversion operation starts until it ends 2 an operating current during A D conversion ELECTRONI S ELECTRICAL DATA S3C8245 P8245 C8249 P8249 Table 19 8 Voltage Booster Electrical Characteristics TA 25 C Vpp 2 0 V to 5 5 V Vss 0 V Regulated Voltage 5 3 bias 09 Booster Voltage Vici Connect 1 MQ load between 2 co Vss and Vic 0 1 Connect 1 MO load between Vss and Vico 0 1 Regulated Voltage lico 6 uA 1 2 bias 1 4 Booster Voltage Connect 1 MQ load between 2Vico Vss and Vic 0 1 Connect 1 MO load between Vgs and Vico Table 19 9 Characteristics of Voltage Level Detect Circuit 1 0 5 25 C 1 8 VLDCON 1 0 11b Hysteresys Voltage of VLD VLCDCON 1 0 00 Sum of Voltage Booster IVBVLD IVB IVLD IDD4 Voltage Detector and Sub VDD 3 0V idle current 19 10 ELECTRONICS 53 8245 8245 8249 8249 ELECTRICAL DATA Table 19 10 Synchronous SIO Elec
52. Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst 2 8 A0 RR A1 IR Given RO R1 02H register 02H 0FH and register INCW RRO gt RO R1 03H INCW R1i gt Register 02H 10H register 00H In the first example the working register pair RRO contains the value 1AH in register RO and 02H in register R1 The statement INCW RRO increments the 16 bit destination by one leaving the value in register R1 In the second example the statement INCW R1 uses Indirect Register IR addressing mode to increment the contents of general register from OFFH to 00H and register 02H from OFH to 10H A system malfunction may occur if you use a Zero Z flag FLAGS 6 result together with an INCW instruction To avoid this problem we recommend that you use INCW as shown in the following example LOOP INCW RRO LD R2 R1 OR R2 RO JR NZ LOOP ELECTRONICS 6 45 INSTRUCTION SET S3C8245 P8245 C8249 P8249 IRET Interrupt Return IRET Operation Flags Format Example NOTE 6 46 IRET Normal IRET Fast FLAGS SP PC o IP SP SP 1 FLAGS lt FLAGS SP FIS 0 SP lt SP 2 SYM 0 1 This instruction is used at the end of an interrupt service routine It restores the flag register and the program counter It also re enables global interrupts A normal IRET is executed only if the fast interrupt status bit FIS b
53. be selected dynamically by manipulating the 4 6 bits And the pins not used for analog input can be used for normal I O function A D Converter Control Register ADCON F7H Set 1 Bank 1 R W EOC bit is read only Always logic zero Start or enable bit 0 Disable operation 1 Start operation A D input pin selection bits 0 0 0 ADCO Clock Selection bit 00 1 ADC1 0 0 fxx 16 010 ADC2 0 1 fxx 8 0 1 1 ADC3 1 0 4 100 ADC4 1 1 fxx 1 10 1 ADC5 110 ADC6 End of conversion bit 111 ADC7 0 Conversion complete 1 Conversion complete Figure 15 1 A D Converter Control Register ADCON 15 2 ELECTRONICS 53 8245 8245 8249 8249 A D CONVERTER A D Converter Data Register High Byte ADDATAH F8H Set 1 Bank 1 Read Only A D Converter Data Register Low Byte ADDATAL F9H Set 1 Bank 1 Read Only DOCELA Figure 15 2 A D Converter Data Register ADDATAH L INTERNAL REFERENCE VOLTAGE LEVELS In the ADC function block the analog input voltage level is compared to the reference voltage The analog input level must remain within the range AVss to AV pgp usually AVpeF Vpp Different reference voltage levels are generated internally along the resistor tree during the analog conversion process for each conversion step The reference voltage level for the first conversion bit is always 1 2 AVper ELECTRONICS 15 3 A D CONVERTER 53 8245 8245 8249 8249 BLOCK DIAGR
54. cc This specifies under which conditions it is to execute the jump For example a conditional jump with the condition code for equal after a compare operation only jumps if the two operands are equal Condition codes are listed in Table 6 6 The carry C zero Z sign S and overflow V flags are used to control the operation of conditional jump instructions Table 6 6 Condition Codes men Gem rtm 0000 Always false 1000 T Always true 0111 note Carry II II e _ 1111 note No carry II 0110 note Zero 1110 note Not zero 1101 Plus 0101 Minus 0100 Overflow 1100 No overflow 0110 note Equal 0 0 1 1 0 1 II 1110 note Not equal gt 1001 Greater than or equal 0001 Less than 1010 Greater than 0010 Less than or equal OR V 0 OR V 1 S XOR V 0 XOR V 1 O O x II 1111 note Unsigned greater than equal oN II 0111 note Unsigned less than 1011 Unsigned greater than 0 AND Z 0 1 0011 Unsigned less than or equal C OR Z 1 NOTES 1 Itindicates condition codes that are related to two different mnemonics but which test the same flag For example Z and EQ are both true if the zero flag Z is set but after an ADD instruction Z would probably be used after a CP instruction however EQ would probably be used 2 Foroperations involving unsigned numbers the special condition co
55. counter clock input Then the oscillation stabilization time is 62 5 1 32768 x 128 x 16 ms 100 ms Here the warm up time is from the time that the stop release signal activates to the time that basic timer starts counting Figure 7 5 Oscillator Control Register OSCCON STOP Control Register STPCON Set 1 bank 0 R W STOP Control bits Other values Disable STOP instruction 10100101 Enable STOP instruction Figure 7 6 STOP Control Register STPCON 7 4 ELECTRONI S 53 8245 8245 8249 8249 nRESET POWER DOWN nRESET and POWER DOWN SYSTEM nRESET OVERVIEW During a power on reset the voltage at Vpp goes to High level and the nRESET pin is forced to Low level The nRESET signal is input through a schmitt trigger circuit where it is then synchronized with the CPU clock This procedure brings the S3C8245 C8249 into a known operating status To allow time for internal CPU clock oscillation to stabilize the nRESET pin must be held to Low level for a minimum time interval after the power supply comes within tolerance The minimum required time of a reset operation for oscillation stabilization is 1 millisecond Whenever a reset occurs during normal operation that is when both and nRESET are High level the nRESET pin is forced Low level and the reset operation starts All system and peripheral control registers are then reset to their default hardware values In summary the following s
56. d The source data bits one and zero LSB determine whether to write one or both of the register pointers RPO and Bits 3 7 of the selected register pointer are written unless both register pointers are selected RPO 3 is then cleared to logic zero and RP1 3 is set to logic one No flags are affected Bytes Cycles Opcode Addr Mode Hex src src 2 4 31 IM The statement SRP 40H sets register pointer 0 RP0 at location 0D6H to 40H and register pointer 1 RP1 at location 0D7H to 48H The statement SRP0 50 sets RP0 to 50H and the statement SRP1 68H sets RP1 to 68H ELECTRONICS 6 81 INSTRUCTION SET S3C8245 P8245 C8249 P8249 STOP Stop Operation STOP Operation The STOP instruction stops the both the CPU clock and system clock and causes the microcontroller to enter Stop mode During Stop mode the contents of on chip CPU registers peripheral registers and I O port control and data registers are retained Stop mode can be released by an external reset operation or by external interrupts For the reset operation the RESET pin must be held to Low level until the required oscillation stabilization interval has elapsed Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src opc 1 4 7F Example The statement STOP halts all microcontroller operations 6 82 ELECTRONICS 53 8245 8245 8249 8249 INSTRUCTION SET SUB Subtract SUB dst src Operation ds
57. instruction string takes 15 bytes of instruction code rather than 12 bytes and its execution time is 50 cycles rather than 36 cycles 2 10 ELECTRONICS 53 8245 8245 8249 8249 ADDRESS SPACES REGISTER ADDRESSING The S3C8 series register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time With Register R addressing mode in which the operand value is the content of a specific register or register pair you can access any location in the register file except for set 2 With working register addressing you use a register pointer to specify an 8 byte working register space in the register file and an 8 bit register within that space Registers are addressed either as a single 8 bit register or as a paired 16 bit register space In a 16 bit register pair the address of the first 8 bit register is always an even number and the address of the next register is always an odd number The most significant byte of the 16 bit data is always stored in the even numbered register and the least significant byte is always stored in the next 1 odd numbered register Working register addressing differs from Register addressing as it uses a register pointer to identify a specific 8 byte working register space in the internal register file and a specific 8 bit register within that space n Even address Figure 2 8 16 Bit Register Pair ELEC
58. interrupt processing was disabled by executing a DI instruction it will be serviced when you execute the El instruction No flags are affected Bytes Cycles Opcode Hex 1 4 9F Given SYM 00H EI If the SYM register contains the value that is if interrupts are currently disabled the statement El sets the SYM register to 01H enabling all interrupts SYM 0 is the enable bit for global interrupt processing ELECTRONICS 53 8245 8245 8249 8249 INSTRUCTION SET ENTER Enter ENTER Operation Flags Format Example Address IP PC SP 22 SP e SP 2 QSP e IP lt PC PC lt IP IP 2 This instruction is useful when implementing threaded code languages The contents of the instruction pointer are pushed to the stack The program counter PC value is then written to the instruction pointer The program memory word that is pointed to by the instruction pointer is loaded into the PC and the instruction pointer is incremented by two No flags are affected Bytes Cycles Opcode Hex 1 14 1 diagram below shows example of how to use ENTER statement Before Address Data 40 Enter 41 Address 42 Address L 43 Address H Address Enter Address H Address L Address H 110 Routine Memory ELECTRONICS 6 41 INSTRUCTION SET S3C8245 P8245 C8249 P8249 EXIT Exit EXIT Operation Flag
59. of the destination are affected The source is unaffected No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src dst 3 6 47 Rb r NOTE Inthe second byte of the instruction formats the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit in length Given RO 06H and general register OOH 05H LDB R0 00H 2 gt RO LDB 00H 0 RO gt RO 07H register OOH 05H 06H register OOH 04H In the first example destination working register RO contains the value 06H and the source general register 00H the value 05H The statement LD R0 00H 2 loads the bit two value of the 00H register into bit zero of the RO register leaving the value 07H in register RO In the second example is the destination register The statement LD 00H 0 RO loads bit zero of register RO to the specified bit bit zero of the destination register leaving 04H in general register 00H ELECTRONICS 6 51 INSTRUCTION SET S3C8245 P8245 C8249 P8249 LDC LDE Load Memory LDC LDE dst src Operation dst lt src This instruction loads a byte from program or data memory into a working register or vice versa The source values are unaffected LDC refers to program memory and LDE to data memory The assembler makes lrr or r values an even number for program memory and odd an odd number for data memory Flags No flags are affected Format Bytes Cycles Opc
60. processing for each of the eight interrupt levels IRQ0 IRQ7 Interrupt priority register IPR RW Controls the relative processing priorities of the interrupt levels The seven levels of S3C8245 C8249 are organized into three groups A B and C Group A is IRQO and IRQ1 group is IRQ2 IRQ3 and IRQ4 and group C is IRQ5 IRQ6 and IRQ7 Interrupt request register IRQ R This register contains a request pending bit for each interrupt level System mode register SYM R W This register enables disables fast interrupt processing dynamic global interrupt processing and external interface control An external memory interface is implemented in the 53 8245 8249 microcontroller 5 6 ELECTRONICS 53 8245 8245 8249 8249 INTERRUPT STRUCTURE INTERRUPT PROCESSING CONTROL POINTS Interrupt processing can therefore be controlled in two ways globally or by specific interrupt level and source The system level control points in the interrupt structure are Global interrupt enable and disable by El and DI instructions or by direct manipulation of SYM O Interrupt level enable disable settings IMR register Interrupt level priority settings IPR register Interrupt source enable disable settings in the corresponding peripheral control registers NOTE When writing an application program that handles interrupt processing be sure to include the necessary register file address register poi
61. program control instructions use the Relative Address mode to perform conditional jumps The instructions that support RA addressing are BTJRF BTJRT DJNZ CPIJE CPIJNE and JR Program Memory Next OPCODE Displacement Current Instruction OPCODE Sample Instructions Program Memory Address Used Current PC Value Signed Displacement Value JR ULT OFFSET Where OFFSET is a value in the range 127 to 128 Figure 3 13 Relative Addressing ELEGTRONIGS ADDRESSING MODES 53 8245 8245 8249 8249 IMMEDIATE In Immediate addressing mode the operand value used in the instruction is the value supplied in the operand field itself The operand may be one byte or one word in length depending on the instruction used Immediate addressing mode is useful for loading constant values into registers Program Memory OPERAND OPCODE The Operand value is in the instruction Sample Instruction LD RO 0AAH Figure 3 14 Immediate Addressing 3 14 ELECTRONICS 53 8245 8245 8249 8249 CONTROL REGISTER CONTROL REGISTERS OVERVIEW In this chapter detailed descriptions of the 53 8245 8249 control registers are presented in an easy to read format You can use this chapter as a quick reference source when writing application programs Figure 4 1 illustrates the important features of the standard register description format Control register descriptions are arranged in a
62. selecting Voltage Level Detect Control register VLDCON When you write 2 bit data value to VLDCON an established resistor string is selected and the Vy p is fixed in accordance with this resistor Table 18 1 shows specific Vy p of 4 levels Resistor String Voltage Level Detect Control F6H Set 1 Bank 1 R W Reset 00H ExtRef P2CONH 7 6 NOTE The reset value of VLDCON is 00H Figure 18 2 Voltage Level Detect Circuit and Control Register Table 18 1 VLDCON Value and Detection Level a9 v 18 2 ELECTRONICS 53 8245 8245 8249 8249 ELECTRICAL DATA OVERVIEW In this chapter 538245 C8249 electrical characteristics are presented in tables and graphs The information is arranged in the following order Absolute maximum ratings Input output capacitance D C electrical characteristics electrical characteristics Oscillation characteristics Oscillation stabilization time Data retention supply voltage in stop mode Serial I O timing characteristics A Dconverter electrical characteristics ELECTRONICS ELECTRICAL DATA ELECTRICAL DATA S3C8245 P8245 C8249 P8249 Table 19 1 Absolute Maximum Ratings 25 lt 0 3 to 46 5 0 3 to Vpp 0 3 All I O pins active One I O pin active Total pin current for port 100 Table 19 2 D C Electrical Characteristics V V Output current low Output current high On
63. set cleared complemented and tested Bits within a byte are numbered from 7 to 0 where bit 0 is the least significant right most bit REGISTER ADDRESSING To access an individual register an 8 bit address in the range 0 255 or the 4 bit address of a working register is specified Paired registers can be used to construct 16 bit data or 16 bit program memory or data memory addresses For detailed information about register addressing please refer to Section 2 Address Spaces ADDRESSING MODES There are seven explicit addressing modes Register R Indirect Register IR Indexed X Direct DA Relative RA Immediate IM and Indirect IA For detailed descriptions of these addressing modes please refer to Section 3 Addressing Modes ELECTRONICS 6 1 INSTRUCTION SET S3C8245 P8245 C8249 P8249 Table 6 1 Instruction Group Summary Mnemonic Operands Instruction Load Instructions CLR dst Clear LD dst src Load LDB dst src Load bit LDE dst src Load external data memory LDC dst src Load program memory LDED dst src Load external data memory and decrement LDCD dst src Load program memory and decrement LDEI dst src Load external data memory and increment LDCI dst src Load program memory and increment LDEPD dst src Load external data memory with pre decrement LDCPD dst src Load program memory with pre decrement LDEPI dst src Load external data memory with pre increment LDCPI dst src Load program memory with pre incr
64. sources In the S53C8245 C8249 interrupt structure there are sixteen possible interrupt sources When service routine starts the respective pending bit should be either cleared automatically by hardware or cleared manually by program software The characteristics of the source s pending mechanism determine which method would be used to clear its respective pending bit ELECTRONICS 5 1 INTERRUPT STRUCTURE S3C8245 P8245 C8249 P8249 INTERRUPT TYPES The three components of the S3C8 interrupt structure described before levels vectors and sources are combined to determine the interrupt structure of an individual device and to make use of its available interrupt logic There are three possible combinations of interrupt structure components called interrupt types 1 2 and 3 The types differ in the number of vectors and interrupt sources assigned to each level see Figure 5 1 Type 1 One level IRQn one vector V4 one source S4 Type 2 One level IRQn one vector V4 multiple sources S S Type 3 One level IRQn multiple vectors V4 V multiple sources S4 S5 S4 4 Spam In the 53C8245 C8249 microcontroller two interrupt types are implemented Levels Vectors Sources Type 1 91 51 2 S2 Sn 51 3 IRQn 52 NOTES 1 The number of Sn and Vn value is expandable 2 In the S3C8245 C8249 implementation inter
65. subtracts the source value 03H from the destination value 12H and stores the result OFH in destination register R1 ELECTRONICS 6 83 INSTRUCTION SET S3C8245 P8245 C8249 P8249 SWAP swap Nibbles SWAP Operation Flags Format Examples 6 84 dst dst 0 3 dst 4 7 The contents of the lower four bits and upper four bits of the destination operand are swapped C Undefined Z Setif the result is 0 cleared otherwise S Setif the result bit 7 is set cleared otherwise V Undefined D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst 2 4 FO R F1 IR Given Register register 02H 03H and register 03H OA4H SWAP 00H gt Register OOH OE3H SWAP 02H gt Register 02H 03H register 03H 4AH In the first example if general register contains the value 00111110B the statement SWAP 00H swaps the lower and upper four bits nibbles in the OOH register leaving the value OESH 1110001 1B ELECTRONICS 53 8245 8245 8249 8249 INSTRUCTION SET TCM rest Complement Under Mask TCM Operation Flags Format Examples dst src NOT dst AND src This instruction tests selected bits in the destination operand for a logic one value The bits to be tested are specified by setting a 1 bit in the corresponding position of the source operand mask The TCM statement complements the destination operand wh
66. the value 42H and register 42H the value 6FH the statement POPUD 02H 00H loads the contents of register 42H into the destination register 02H The user stack pointer is then decremented by one leaving the value 41H ELECTRONICS 6 65 INSTRUCTION SET S3C8245 P8245 C8249 P8249 POPUI Pop User Stack Incrementing POPUI Operation Flags Format Example 6 66 dst src dst lt src IR lt IR 1 The POPUI instruction is used for user defined stacks in the register file The contents of the register file location addressed by the user stack pointer are loaded into the destination The user stack pointer is then incremented No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc src dst 3 8 93 R IR Given Register 00H 01H and register 01H 70H POPUI 02H 900H gt Register OOH 02H register 01H register 02H 70H If general register OOH contains the value 01H and register 01H the value 70H the statement POPUI 02H 00H loads the value 70H into the destination general register 02H The user stack pointer register 00H is then incremented by one changing its value from 01H to 02H ELECTRONICS 53 8245 8245 8249 8249 INSTRUCTION SET PUSH Push To Stack PUSH Operation Flags Format Examples src SP lt SP 1 SP lt src A PUSH instruction decrements the stack pointer value and loads the contents of the source src into the location add
67. write addressable using Register addressing mode A reset clears TACON to 00H This sets timer A to normal interval timer mode selects an input clock frequency of fxx 1024 and disables all timer A interrupts You can clear the timer A counter at any time during normal operation by writing a 1 to TACON 3 The timer A overflow interrupt TAOVF is interrupt level IRQ0 and has the vector address E2H When a timer overflow interrupt occurs and is serviced by the CPU the pending condition is cleared automatically by hardware Timer A Control Register TACON EDH Set 1 Bank 0 R W Timer A input clock selection bits Timer A match capture interrupt 00 fxx 1024 pending bit 01 fxx 256 0 No interrupt pending 10 fxx 64 0 Clear pending bit write 11 External clock TACLK 1 Interrupt is pending Timer A match capture interrupt enable bit 0 Disable interrupt 1 Enable interrupt Timer A operating mode selection bits 00 Interval mode TAOUT mode 01 Capture mode capture on rising edge Counter running OVF can occur 10 Capture mode Capture falling edge Pt ov rll w interrupt enable Counter running OVF can occur 0 Disable overflow interrupt 11 PWM mode OVF interrupt can occur 1 Enable overflow interrupt Timer A counter clear bit 0 No affect 1 Clear the timer A counter when write Figure 11 1 Timer A Control Register TACON ELECTRONICS 11 3 8
68. 01B in register R1 Because the result of the complement is not the zero flag 2 in the FLAGS register 0 5 is cleared ELECTRONICS 6 19 INSTRUCTION SET S3C8245 P8245 C8249 P8249 BITR Bit Reset BITR Operation Flags Format Example 6 20 dst b dst b 0 The BITR instruction clears the specified bit within the destination without affecting any other bits in the destination No flags are affected Bytes Cycles Opcode Addr Mode Hex dst NOTE Inthe second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H BTR Rit gt R1 05H If the value of working register R1 is 07H 00000111B the statement BITR R1 1 clears bit one of the destination register R1 leaving the value 05H 00000101 ELECTRONICS 53 8245 8245 8249 8249 INSTRUCTION SET BITS Bit set BITS Operation Flags Format Example dst b dst b 1 The BITS instruction sets the specified bit within the destination without affecting any other bits in the destination No flags are affected Bytes Cycles Opcode Addr Mode Hex dst NOTE Inthe second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H BTS R13 o R1 OFH If working register R1 contain
69. 1 WATCH 53 8245 8245 8249 8249 WATCH CONTROL REGISTER WTCON R W re wrcous wrcons wrcona wrcona wrconz wTCON t wrCON pereseT o v v v v j v v Table 13 1 Watch Timer Control Register WTCON Set 1 Bank 1 FAH R W ves WTCON 7 Select fxx 128 as the watch timer clock mew Det Select subsystem clock as watch timer clock WTCON 6 pog Disable watch timer interrupt m Enable watch timer interrupt WTCON 5 4 0 5 kHz buzzer BUZ signal output EXE EJES 1 kHz buzzer BUZ signal output 1 0 2 2 buzzer BUZ signal output ESES 1 4kHz buzzer BUZ signal output WTCON 3 2 EAKA Set watch timer interrupt to 0 5 s ofal 1 Set watch timer interrupt to 0 25 s EJES Set watch timer interrupt to 0 125 s Set watch timer interrupt to 1 955 ms WTCON 1 Disable watch timer clear frequency dividing circuits Enable watch timer Interrupt is not pending clear pending bit when write WTCON 0 NOTE Watch timer clock frequency fw is assumed to be 32 768 kHz Interrupt is pending 13 2 ELECTRONICS 53 8245 8245 8249 8249 WATCH WATCH CIRCUIT DIAGRAM BUZZER Output WTCON WTCON S WTCON 4 WTINT fw 64 0 5 kHz WTCON 3 fw 32 Hd fw 16 2 kHz WTCON 2 fw 8 4 kHz Enable Disable Circuit Frequency Clock vidi WTCON 7 Selector Dividing fvLD 4096 HZ
70. 1H Set 1 Bank 1 nRESET Value 0 0 0 0 0 0 0 Read Write R W R W R W _ R W R W R W R W Addressing Mode Register addressing mode only 7 5 Timer 0 Input Clock Selection Bits 256 4 Not used for the S3C8245 C8249 3 Ti er 0 Counter Clear Bit 3 No effect 1 Clear the timer 0 counter when write 2 0 Counter Enable 3 Disable counting operation 1 Enable counting operation 41 0 Interrupt Enable Bit Disable timer 0 interrupt 1 Enable timer 0 interrupt 0 0 Interrupt Pending Bit No timer 0 interrupt pending when read Clear timer 0 interrupt pending condition when write 0 interrupt is pending ELECTRONICS 4 39 CONTROL REGISTERS 53 8245 8245 8249 8249 T1CON rimer 1 Control Register FBH Set 1 Bank 1 Bit Identifier 5 3 2 o 0 0 0 0 0 0 0 0 nRESET Value Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 5 1 Input Clock Selection Bits DUI as oa fo e SSCS Fs e o 1 1 External clock T1CLK falling edge 1 1 External clock 1 rising edge 4 3 1 Operating Mode Selection Bits olo Interval mode 1 Capture mode Capture rising edge counter running occur 1 Capture mode Capture falling edge counter ru
71. 20 1 4 1 3 S3C8245 C8249 Pin Assignment 80 1212 1 5 1 4 Pin Circuit Type 1 8 1 5 Pin Circuit Type C uu u aaa ede vie deae ed de 1 8 1 6 Pin Circuit Type D 2 P3 u 1 8 1 7 Pin Circuit Type D 4 PO genere dp ieee 1 8 1 8 Pin Circuit Type E 2 PT ieu tp eeepc 1 9 1 9 Pin Circuit Type F 10 2 0 26 1 9 1 10 Pin Circuit F 18 P2 7 VLDREF beide kc ao vea via dde 1 9 1 11 Pin Circuit Type H 5 1 9 1 12 Fir aeieea pct odi ad oe Data AANA 1 10 1 13 Pin Circuit Type H 14 P4 BB is criteri e teste c thea 1 10 2 1 Program Memory Address 5 2 2 2 2 Internal Register File 2 4 2 3 Register Page Pointer 2 5 2 4 Set 1 Set 2 Prime Area Register and LCD Data Register Map 2 7 2 5 8 Byte Working Register Areas 2 8 2 6 Contiguous 16 Byte Working Register Block a 2 9 2 7 Non Conti
72. 23 P4 7 SEG22 P4 6 SEG21 P4 5 75 3 SEG20 P4 4 74 SEG19 P4 3 73 1 SEG18 P4 2 72 L3 SEG17 P4 1 71 1 SEG16 P4 0 70 SEG15 SEG26 P5 2 SEG5 SEG27 P5 3 SEG4 SEG28 P5 4 SEG3 SEG29 P5 5 SEG2 SEG30 P5 6 SEG1 SEG31 P5 7 SEG0 P3 0 TBPWM COM3 P3 1 TAOUT TAPWM 2 P3 2 TACLK S3C8245 C8249 1 P3 3 TACAP SDAT COMO P3 4 SCLK VLC2 VDD 80 TQFP 1212 Vict Vss VLCO XOUT CA XIN CB TEST AVsS XTIN AVREF XTOUT P2 7 ADC7 V LDREF nRESET P2 6 ADC6 PO O INTO P2 5 ADC5 NT4 Ct 24 NT5 9 25 NT6 C4 26 NT7 C4 27 P1 0 T1CAP C4 28 P1 4 BUZ C3 32 P1 5 SO 4 33 1 6 5 34 P1 7 SI 35 P2 0 ADCO c3 36 P0 3 4 5 6 7 1 2 P2 3 ADC4 D 39 P2 4 ADC4 40 P1 1 TICLK 29 P2 1 ADC1 4 37 P2 2 ADC3 4 38 P1 2 T1OUT T1PWM 30 Figure 1 3 53C8245 C8249 Pin Assignments 80 1212 ELECTRONICS 1 5 PRODUCT OVERVIEW S3C8245 P8245 C8249 P8249 PIN DESCRIPTIONS Table 1 1 S3C8245 C8249 Pin Descriptions Pin Circuit Description Type n E D 4 for external interrupts INTO INT7 P0 0 PO 7 I O port with bit programmable pins 20 27 INTO INT7 Schmitt trigger input or output mode with noise filter and interrupt control 1 0 1 7 port with bit programmable pins Input E 2 28 35 SI SO SCK or output mode selected by software BUZ Open drain output mode can be selected by software software assignable pull up T1OUT Alte
73. 24 53 8245 8245 8249 8249 032004 USER S MANUAL S3C8245 P8245 C8249 P8249 8 Bit CMOS Microcontrollers Revision 4 ELECTRONICS NOTIFICATION REVISIONS ORIGINATOR Samsung Electronics LSI Development Group Ki Heung South Korea PRODUCT NAME S3C8245 P8245 C8249 P8249 8 bit CMOS Microcontroller DOCUMENT NAME S3C8245 P8245 C8249 P8249 User s Manual Revision 4 DOCUMENT NUMBER 24 S3 C8245 P8245 C8249 P8249 032004 EFFECTIVE DATE March 2004 SUMMARY As a result of additional product testing and evaluation some specifications published in the S8C8248 C8245 P8245 C8247 C8249 P8249 User s Manual Revision 3 have been changed These changes for S3C8248 C8245 P8245 8247 8249 8249 microcontroller which are described in detail in the Revision Descriptions section below are related to the followings 53 8248 8247 moved Chapter 1 Features Chapter 19 Electrical Data DIRECTIONS Please note the changes in your copy copies of the S3C8248 C8245 P8245 C8247 C8249 P8249 User s Manual Revision 3 Or simply attach the Revision Descriptions of the next page to S3C8248 C8245 P8245 C8247 C8249 P8249 User s Manual Revision 3 REVISION HISTORY 7 Remark 1999 Preliminary Spec for internal release only 1 September 1999 First edition March 2002 Third edition REVISION DESCRIPTIONS 1 DEVICE TYPE The S3C8247 C8248 device type should be moved Product name and d
74. 4 Select No Select Bias Signals in Static Display 14 7 14 5 Select No Select Bias Signals 1 2 Duty 1 2 Bias Display Mode 14 8 14 6 Select No Select Bias Signals 1 3 Duty 1 3 Bias Display Mode 14 8 14 7 LCD Signal and Wave Forms Example 1 2 Duty 1 2 Bias Display Mode 14 9 14 8 LCD Signals and Wave Forms Example in 1 3 Duty 1 3 Bias Display Mode 14 10 14 9 LCD Signals and Wave Forms Example 1 4 Duty 1 3 Bias Display Mode 14 11 14 10 Voltage Dividing Resistor Circuit 14 12 15 1 A D Converter Control Register 15 2 15 2 A D Converter Data Register 15 3 15 3 A D Converter Functional Block Diagram 15 4 15 4 Recommended A D Converter Circuit for Highest Absolute 15 5 16 1 Serial I O Module Control Registers 1 16 2 16 2 SIO Pre scale Registers 16 3 16 3 SIO Functional Block 16 3 16 4 Serial I O Timing in Transmit Receive Mode Tx at falling SIOCON 4 0 16 4 16 5 Serial I O Timing in Transmit Receive Mode Tx at rising SIOCON 4 1 16 4 3C8245 P8245 C
75. 45 8245 8249 8249 CONTROL REGISTER P5CONH Port 5 Control Register High Byte EEH Set 1 Bank 1 Bit Identifier 5 3 2 o 0 0 0 0 0 0 0 0 nRESET Value Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P5 7 SEG31 Mode Selection Bits Input mode ojo fo 1 Input mode pull up 1 Open drain output mode Push pull output mode 5 4 P5 6 SEG30 Mode Selection Bits Input mode ojo fo 1 Input mode pull up Pt o openan 3 2 P5 5 SEG29 Mode Selection Bits Input mode Input mode pull up 1 output mode Push pull output mode Input mode Input mode pull up Open drain output mode Push pull output mode ELECTRONICS 4 31 CONTROL REGISTERS 53 8245 8245 8249 8249 P5CONL Port 5 Control Register Low Byte EFH Set 1 Bank 1 Bit Identifier _ _ 5 2 o 0 0 0 0 0 0 0 0 nRESET Value Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P5 3 SEG27 Mode Selection Bits Input mode Input mode pull up Open drain output mode Push pull output mode Input mode Input mode pull up Open drain output mode Push pull output mode Input mode 1 Input mode pull up 1 Open drain output mode Push pull output mode Input mode Input mode pull up Open drain output mode Push pull output m
76. 49 CONTROL REGISTER STPCON Stop Control Register F4H Set 1 Bank 0 nRESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 STOP Control Bits 10100101 Enable stop instruction Other values Disable stop instruction NOTE Before execute the STOP instruction You must set this STPCON register as 101001010 Otherwise the STOP instruction will not execute ELECTRONICS 4 37 CONTROL REGISTERS 53 8245 8245 8249 8249 SYM System Mode Register DEH Set 1 nRESET Value 0 x x x 0 0 Read Write R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 Not used But must keep 0 6 5 Not used for the 53 8245 8249 4 2 Fast Interrupt Level Selection Bits 1 41 Fast Interrupt Enable Bit 2 Disable fast interrupt processing Enable fast interrupt processing 0 Global Interrupt Enable Bit 3 Disable interrupt processing Enable all interrupt processing NOTES 1 You select only one interrupt level at a time for fast interrupt processing 2 Setting SYM 1 to 1 enables fast interrupt processing for the interrupt level currently selected by SYM 2 SYM 4 3 Following a reset you must enable global interrupt processing by executing an EI instruction not by writing a 1 to SYM O 4 38 ELECTRONICS 53 8245 8245 8249 8249 CONTROL REGISTER TOCON Timer 0 Control Register F
77. 7 external interrupt IRQ7 POCONH EOH bank 0 0 6 external interrupt POINT E2H bank 0 0 5 external interrupt POPND E3H bank 0 P0 4 external interrupt NOTES 1 Because the timer 0 overflow interrupt is cleared by hardware the TOCON register controls only the enable disable functions The TOCON register contains enable disable and pending bits for the timer 0 match capture interrupt 2 Ifa interrupt is un mask Enable interrupt level in the IMR register the pending bit and enable bit of the interrupt should be written after a DI instruction is executed 5 8 ELECTRONICS 53 8245 8245 8249 8249 INTERRUPT STRUCTURE SYSTEM MODE REGISTER SYM The system mode register SYM set 1 DEH is used to globally enable and disable interrupt processing and to control fast interrupt processing see Figure 5 5 A reset clears SYM 1 and SYM 0 to 0 3 bit value for fast interrupt level selection SYM 4 SYM 2 is undetermined The instructions El and DI enable and disable global interrupt processing respectively by modifying the bit 0 value of the SYM register In order to enable interrupt processing an Enable Interrupt El instruction must be included in the initialization routine which follows a reset operation Although you can manipulate 5 0 directly to enable and disable interrupts during the normal operation it is recommended to use the El and DI instructions for this purpose System Mode Register SYM
78. 8249 P8249 MICROCONTROLLER xiii List of Figures Concluded Page Title Page Number Number 17 1 Voltage Booster Block Diagram a 17 2 17 2 Pin Connection Example uuu u LU Su a nennen a EATER Ea enne 17 2 18 1 Block Diagram for Voltage Level 18 1 18 2 Voltage Level Detect Circuit and Control 18 2 19 1 Input Timing for External Interrupts Ports 0 22 19 6 19 2 Input Timing for nRESET 5 enero rte O D net re DRS 19 6 19 3 Stop Mode Release Timing Initiated by 19 7 19 4 Stop Mode main Release Timing Initiated by Interrupts 19 8 19 5 Stop Mode sub Release Timing Initiated by Interrupts 19 8 19 6 Serial Data Transfer m meme enn 19 11 19 7 Clock Timing Measurement at Xy eiu rotes tee toe eee oce eee 19 13 19 8 Operating Voltage 19 14 20 1 Package 80 14206 20 1 20 2 Package 80 1212 20 2 21 1 S3P8245 P8249 Pin Assignments 80 QFP Package 21 2 21 2 Operating Voltage Range 21 7
79. 9 15 xii 3C8245 P8245 C8249 P8249 MICROCONTROLLER List of Figures continued Page Title Page Number Number 10 1 Basic Timer Control Register BTCON a 10 2 10 2 Basic Timer Block 10 4 11 1 Timer A Control Register 11 3 11 2 Timer A Functional Block ee 11 4 11 3 Timer B Functional Block 11 5 11 4 Timer B Control Register 11 6 11 5 Timer B Data Register 11 6 11 6 Timer B Output Flip Flop Waveforms in Repeat Mode 11 8 12 1 Timer 0 Control Register mener 12 2 12 2 Timer 0 Functional Block mener 12 3 12 3 Timer 0 Counter Register mee 12 4 12 4 Timer 0 Data Register 12 4 12 5 Timer 1 Control Register 1 12 7 12 6 Timer 1 Functional Block me mene 12 8 12 7 Timer 1Counter Register 12 9 12 8 Timer 1 Data Register 12 9 13 1 Watch Timer Circuit 13 3 14 1 LCD Function BIET Om 14 1 14 2 LCD Circuit Diagram 14 2 14 3 LCD Display Data RAM Organization essem e 14 3 14
80. 96 as the BT clock The MCU is reseted whenever a basic timer counter overflow occurs During normal operation the application program must prevent the overflow and the accompanying reset operation from occuring To do this the BTCNT value must be cleared by writing a 1 to BTCON 1 at regular intervals If a system malfunction occurs due to circuit noise or some other error condition the BT counter clear operation will not be executed and a basic timer overflow will occur initiating a reset In other words during the normal operation the basic timer overflow loop a bit 7 overflow of the 8 bit basic timer counter is always broken by a BTCNT clear instruction If a malfunction does occur a reset is triggered automatically Oscillation Stabilization Interval Timer Function You can also use the basic timer to program a specific oscillation stabilization interval after a reset or when stop mode has been released by an external interrupt In stop mode whenever a reset or an external interrupt occurs the oscillator starts The BTCNT value then starts increasing at the rate of fxx 4096 for reset or at the rate of the preset clock source for an external interrupt When BTCNT 4 overflows a signal is generated to indicate that the stabilization interval has elapsed and to gate the clock signal off to the CPU so that it can resume the normal operation In summary the following events occur when stop mode is released 1 D
81. AM ADCON 2 1 ADCON 4 6 Select one input pin of the assigned pins Clock To ADCON 3 Selector EOC Flag ADCON O AD C Enable Analog 5 Input Pins Comparator uccessive ADC0 ADC7 U Approximation P2 0 P2 7 Logic amp Register x ADCON O AD C Enable Upper 8 bit is loaded to A D Conversion Data Register ADCEN 0 7 Assign Pins to ADC Input Conversion 10 bit D A Result ADDATAH L Converter F8 F9H Set 1 Bank 1 Figure 15 3 A D Converter Functional Block Diagram 15 4 ELECTRONI S 53 8245 8245 8249 8249 A D CONVERTER Reference Voltage Input Analog ADC0 ADC7 Input Pin S3C8245 C8249 NOTE The symbol R signifies an offset resistor with a value of from 50Q to 1000 If this resistor is omitted the absolute accuracy will be maximum of 3 LSBs Figure 15 4 Recommended A D Converter Circuit for Highest Absolute Accuracy ELECTRONI S 53 8245 8245 8249 8249 SERIAL I O INTERFACE SERIAL I O INTERFACE OVERVIEW Serial I O module SIO can interface with various types of external device that require serial data transfer The components of each SIO function block are 8 bit control register SIOCON Clock selector logic 8 bit data buffer SIODATA 8 bit prescaler SIOPS 3 bit serial clock counter Serial data I O pins SI SO External clock input output pins SCK The SIO module can transmit or receive 8 bit serial data at a frequency determined by its corres
82. ATAH FEH Set 1 Bank 1 R W Reset Value FFh Timer 1 Data Register Low Byte T1DATAL FFH Set 1 Bank 1 R W Reset Value FFh NOTE Pending bit is located in INTPND D2H set1 register Figure 12 8 Timer 1 Data Register T1DATAH L ELECTRONICS 12 9 53 8245 8245 8249 8249 WATCH WATCH OVERVIEW Watch timer functions include real time and watch time measurement and interval timing for the system clock To start watch timer operation set bit1 and bit 6 of the watch timer mode register WTCON 1and 6 to 1 After the watch timer starts and elapses a time the watch timer interrupt is automatically set to 1 and interrupt requests commence in 1 955 ms or 0 125 0 25 and 0 5 second intervals The watch timer can generate a steady 0 5 kHz 1 kHz 2 kHz or 4 kHz signal to the BUZZER output By setting WTCON 3 and WTCON 2 to 11b the watch timer will function in high speed mode generating an interrupt every 1 955 ms High speed mode is useful for timing events for program debugging sequences The watch timer supplies the clock frequency for the LCD controller fj Therefore if the watch timer is disabled the LCD controller does not operate Real time and Watch time measurement Using a main system or subsystem clock source Clock source generation for LCD controller Buzzer output frequency generator Timing tests in high speed mode ELECTRONICS 13
83. B Programmable 8 bit timer Carrier frequency generator 16 Bit Timer Counter 0 Programmable 16 bit timer Match interrupt generates 16 Bit Timer Counter 1 Programmable 16 bit timer nterval capture PWM mode Match capture overflow interrupt Voltage Detector Programmable detection voltage 2 2 V 2 4 V 3 0 V 4 0 V En Disable S W selectable Instruction Execution Times 400 ns at 10 MHz main 122 us at 32 768 kHz subsystem Operating Temperature Range 25 C to 85 C Operating Voltage Range 18Vto5 5V Package Type 80 QFP 1420C e 80 TQFP 1212 ELECTRONICS 53 8245 8245 8249 8249 BLOCK DIAGRAM TAOUT TAPWM P3 1 lt TACLK P3 2 TACAP P3 3 TBPWM P3 0 T1CAP P1 0 4 T1OUT T1PWM P1 2 gt 0 7 INTO INT7 XIN XTIN 8 Bit nRESET Timer Counter A 8 Bit Timer Counter B OSC nRESET 16 Bit Timer Counter 0 16 Bit Timer Counter 1 Port 0 Port and Interrupt Control PRODUCT OVERVIEW XOUT XTouT BUZIPT 4 VVLDREF P2 7 ADC7 Voltage Voltage lt gt Booster lt VLCO VLC2 0 LCD SEG0 SEG15 Driver SEG16 SEG23 P4 0 P4 7 SEG24 SEG31 I P5 0 P5 7 SAM88 RC CPU 544 1056 Byte 16 32 Kbyte Register File ROM Serial Port P1 0 P1 7 lt gt Port 1 A D AVREF gt AVss P2
84. B Clock Source lt fosc Disable Timer B interrupt Select one shot mode for Timer B Stop Timer B operation Set Timer B output flip flop TBOF high LD PSCONL 02H Set P3 0 to TBPWM mode Pulse out LD TBCON 00000101B Start Timer B operation to make the pulse at this point After the instruction is executed 0 75 us is required before the falling edge of the pulse starts 11 10 ELECTRONICS 53 8245 8245 8249 8249 16 0 1 16 0 1 16 BIT TIMER 0 OVERVIEW The 16 bit timer 0 is an 16 bit general purpose timer Timer 0 has the interval timer mode by using the appropriate TOCON setting Timer 0 has the following functional components Clock frequency divider fxx divided by 256 64 8 or 1 with multiplexer from timer B is one of the clock frequencies 16 bit counter TOCNTH L 16 bit comparator and 16 bit reference data register TODATAH L Timer 0 interrupt IRQ2 vector E6H generation Timer 0 control register set 1 Bank 1 read write FUNCTION DESCRIPTION Interval Timer Function The timer 0 module can generate an interrupt the timer 0 match interrupt TOINT TOINT belongs to interrupt level 2 and is assigned the separate vector address E6H The TOINT pending condition is automatically cleared by hardware when it has been serviced Even though TOINT is disabled the application s service
85. BXOR R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM ro Rb 3 JP SRP 0 1 SBC SBC SBC SBC SBC BTJR IRR1 IM r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM r2 b RA 4 DA DA OR OR OR O OR LDB R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM ro Rb 5 POP POP AND AND AND AND AND BITC R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM r1 b COM COM TCM TCM TCM TCM TCM BAND R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM ro Rb 7 PUSH PUSH TM TM TM TM TM BIT R2 IR2 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM r1 b DECW DECW PUSHUD PUSHUI MULT MULT MULT LD RR1 IR1 IR1 R2 IR1 R2 R2 RR1 IR2 RR1 IM RR1 r1 x r2 RL RL POPUD POPUI DIV DIV DIV LD R1 IR1 IR2 R1 IR2 R1 R2 RR1 IR2 RR1 IM RR1 r2 x rl A INCW INCW CP CP CP CP CP LDC RR1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM r1 Irr2 xL CLR CLR XOR XOR XOR XOR XOR LDC R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM r2 Irr2 xL C RRC RRC CPIJE LDC LDW LDW LDW LD R1 IR1 Ir r2 RA r lrr2 RR2 RR1 IR2 RR1 RR1 IML r1 Ir2 SRA SRA CPIJNE LDC CALL LD LD R1 IR1 Irrr2 RA r2 lrr1 IA1 IR1 IM Ir1 r2 E RR RR LDCD LDCI LD LD LD LDC R1 IR1 r1 lrr2 r lrr2 R2 R1 R2 IR1 R1 IM r1 Irr2 xs F SWAP SWAP LDCPD LDCPI CALL LD CALL LDC R1 IR1 r2 lrr1 r2 lrr1 IRR1 IR2 R1 DA1 r2 Irr1 xs ELECTRONICS 53 8245 8245 8249 8249 INSTRUCTION SET Table 6 5 Opcode Quick Reference Continued OPCODE MAP LOWER NIBBLE HEX ELECTRONICS 6 11 INSTRUCTION SET S3C8245 P8245 C8249 P8249 CONDITION CODES The opcode of a conditional jump always contains a 4 bit field called the condition code
86. Byte S3C8245 P8245 Data memory mapped I O Oscillation Sources e Crystal ceramic RC main Crystal for subsystem clock Main system clock frequency 1 10 MHz 8 MHz at 1 8 V 10 MHz at 2 7 V Subsystem clock frequency 32 768 kHz e CPU clock divider 1 1 1 2 1 8 1 16 Two Power Down Modes only CPU clock stops Stop System clock stops Interrupts 6 level 8 vector 8 internal interrupt 2 level 8 vector 8 external interrupt Watch Timer Real time and interval time measurement Clock generation for LCD Four frequency outputs for buzzer sound LCD Controller Driver Maximum 16 digit LCD direct drive capability Display modes static 1 2 duty 1 2 bias 1 3 duty 1 2 or 1 3 bias 1 4 duty 1 3 bias A D Converter Eight analog input channels 50 us conversion speed at 1 MHz fapc clock 10 bit conversion resolution 8 Bit Serial I O Interface 8 bit transmit receive mode 8 bit receive mode e LSB first MSB first transmission selectable Internal external clock source Voltage Booster LCD display voltage supply S W control en disable 3 0 V drive 53 8245 8245 8249 8249 45 Pins 45 configurable I O pins Basic Timer Overflow signal makes a system reset Watchdog function 8 Bit Timer Counter A Programmable 8 bit timer interval capture PWM mode Match capture overflow interrupt 8 Bit Timer Counter
87. CD CONTROLLER DRIVER S3C8245 P8245 C8249 P8249 LCD CIRCUIT DIAGRAM Segment Driver Timing COM Controller Control LCD Voltage Control NOTE fLcp fw 2 fw 27 fw 28 tw 29 Figure 14 2 LCD Circuit Diagram 14 2 ELECTRONI S 53 8245 8245 8249 8249 LCD CONTROLLER DRIVER LCD RAM ADDRESS AREA RAM addresses 00H 0FH of page 4 or page 2 according to ROM size are used as LCD data memory When the bit value of a display segment is 1 the LCD display is turned on when the bit value is 0 the display is turned off Display RAM data are sent out through segment pins SEGO SEQG31 using a direct memory access DMA method that is synchronized with the f c5 signal RAM addresses in this location that are not used for LCD display can be allocated to general purpose use BIT 2 BIT 7 BIT 6 BIT 6 Bm Bm BT2 Bre Figure 14 3 LCD Display Data RAM Organization ELECTRONICS 14 3 LCD CONTROLLER DRIVER S3C8245 P8245 C8249 P8249 LCD CONTROL REGISTER LCON D0H Table 14 1 LCD Control Register LCON Organization LCON 7 P5 4 P5 7 1 0 is selected SEG28 SEG31 is selected P5 4 P5 7 I O is disabled P5 0 P5 3 I O is selected LCON 6 LCON 5 LCON 4 LCON 2 LCON 1 LCON O LCD output low turn display off COM and SEG output Low Cut off voltage booster Booster clock disable 1 COM and SEG output is in display mode turn display on Table 14 2 Relationship of LCON 0 and LMOD
88. CLR 00H clears the destination register OOH value to In the second example the statement CLR 01 uses Indirect Register IR addressing mode to clear the 02H register value to 00H ELECTRONICS 53 8245 8245 8249 8249 INSTRUCTION SET COM Complement COM dst Operation dst NOT dst The contents of the destination location are complemented one s complement all 1s are changed to Os and vice versa Flags C Unaffected Z Setif the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Always reset to O D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst dst 2 4 60 R 61 IR Examples Given R1 07H and register 07H OF1H COM RI gt R1 OF8H gt R1 07H register 07 OEH In the first example destination working register R1 contains the value 07H 00000111B The statement COM R1 complements all the bits in R1 all logic ones are changed to logic zeros and vice versa leaving the value OF8H 11111000B In the second example Indirect Register IR addressing mode is used to complement the value of destination register 07H 11110001B leaving the new value OEH 00001110B ELECTRONICS 6 29 INSTRUCTION SET S3C8245 P8245 C8249 P8249 Operation Flags Format Examples 6 30 dst src dst src The source operand is compared to s
89. CS 7 1 CLOCK CIRCUIT 53 8245 8245 8249 8249 CLOCK STATUS DURING POWER DOWN MODES The two power down modes Stop mode and Idle mode affect the system clock as follows In Stop mode the main oscillator is halted Stop mode is released and the oscillator is started by a reset operation or an external interrupt with RC delay noise filter and can be released by internal interrupt too when the sub system oscillator is running and watch timer is operating with sub system clock In Idle mode the internal clock signal is gated to the CPU but not to interrupt structure timers and timer counters Idle mode is released by a reset or by an external or internal interrupt Stop Release Driving Ability OSCCON 4 Main System Sub system Watch Timer Oscillator Oscillator Circuit Circuit OSCCON 3 OSCCON 0 OSCCON 2 Basic Timer Timer Counter Frequency Watch Timer fxx 128 Dividing STPCON Circuit LCD Controller SIO 11 1 2 1 8 1 16 A D Converter STOP OSC 1 8 1 4096 inst System Clock CPU Clock IDLE Instruction Figure 7 3 System Clock Circuit Diagram 7 2 ELECTRONICS 53 8245 8245 8249 8249 CLOCK CIRCUIT SYSTEM CLOCK CONTROL REGISTER CLKCON The system clock control register CLKCON is located in the bank 0 of set 1 address It is read write addressable and has the following functions Oscillator frequency divide by value After the main oscill
90. D register values to logic zero This produces the following LCD control settings Display is turned off LCDCK frequency is the watch timer clock fw 29 64 Hz The LCD display can continue to operate during idle and stop modes if a subsystem clock is used as the watch timer source The LCD output voltage level is always 3 V supplied by the voltage booster Table 14 3 LCD Clock Signal LCDCK Frame Frequency LCDCK Frequency Static 1 2 Duty 1 3 Duty 1 4 Duty iwi 64 Hz 128 Hz wie 256 Hz 512 Hz NOTE fw is the watch timer clock frequency of 32 768 kHz ELECTRONICS 14 5 LCD CONTROLLER DRIVER S3C8245 P8245 C8249 P8249 Table 14 4 LCD Mode Control Register LMOD Organization D1H LMOD 7 Always logic zero LMOD 6 Always logic zero LMOD 5 LMOD 4 LCD Clock LCDCK Frequency 32 768 kHz watch timer clock fw 29 64 Hz A 32 768 kHz watch timer clock fw 28 128 Hz 1 32 768 kHz watch timer clock fw 27 256 Hz fw 32 768 kHz watch timer clock fw 26 512 Hz o 0711 1 2 duty 1 2 bias ES CN cy 1 _ po ge E a a SSE SE ed NOTE x means don t care Table 14 5 Maximum Number of Display Digits per Duty Cycle LCD Duty LCD Bias COM Output Pins Maximum Seg Display COMO COM2 COMO COM2 0 14 6 ELECTRONICS 53 8245 8245 8249 8249 LCD CONTROLLER DRIVER LCD DRIVE VO
91. DEH Set 1 R W Not used for the S3C8245 C8249 Global interrupt enable bit 0 Disable all interrupts processing 1 Enable all interrupts processing Fast interrupt level selection bits Fast interrupt enable bit 0 Disable fast interrupts processing 1 Enable fast interrupts processing Figure 5 5 System Mode Register SYM ELECTRONICS 5 9 INTERRUPT STRUCTURE S3C8245 P8245 C8249 P8249 INTERRUPT MASK REGISTER IMR The interrupt mask register IMR set 1 DDH is used to enable or disable interrupt processing for individual interrupt levels After a reset all IMR bit values are undetermined and must therefore be written to their required settings by the initialization routine Each IMR bit corresponds to a specific interrupt level bit 1 to IRQ1 bit 2 to IRQ2 and so on When the IMR bit of an interrupt level is cleared to 0 interrupt processing for that level is disabled masked When you set a level s IMR bit to 1 interrupt processing for the level is enabled not masked The IMR register is mapped to register location DDH in set 1 Bit values can be read and written by instructions using the Register addressing mode Interrupt Mask Register IMR DDH Set 1 R W IRQ2 inqa 809 IR IRQ6 2 IRQ7 Interrupt level enable bits 7 4 2 0 0 Disable mask interrupt level 1 Enable un mask interrupt level NOTE Before IMR register is changed to any value all interrupts m
92. H 02H register 01H 05H register 02H 05H If the user stack pointer register 00H for example contains the value 03H the statement PUSHUD 200H 01H decrements the user stack pointer by one leaving the value 02H The 01H register value 05H is then loaded into the register addressed by the decremented user stack pointer 6 68 ELECTRONICS 53 8245 8245 8249 8249 INSTRUCTION SET PUSHUI Push User Stack Incrementing PUSHUI Operation Flags Format Example dst src IR IR 1 dst src This instruction is used for user defined stacks in the register file PUSHUI increments the user stack pointer and then loads the contents of the source into the register location addressed by the incremented user stack pointer No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src dst src 3 8 83 IR R Given Register 00H 03H register 01H 05H and register 04H 2AH PUSHUI 00H 01H gt Register 04H register 01H 05H register 05H If the user stack pointer register OOH for example contains the value 03H the statement PUSHUI 00H 01H increments the user stack pointer by one leaving the value 04H The 01H register value 05H is then loaded into the location addressed by the incremented user stack pointer ELECTRONICS 6 69 INSTRUCTION SET RCF Reset Carry Flag RCF Operation Flags Format Example 6 70 RCF C 0 The
93. H In the second example the statement DEC R1 decrements the value 10H contained in the destination register by one leaving the value OFH ELECTRONICS 6 35 INSTRUCTION SET S3C8245 P8245 C8249 P8249 DECW Decrement Word DECW Operation Flags Format Examples NOTE 6 36 dst dst dst 1 The contents of the destination location which must be an even address and the operand following that location are treated as a single 16 bit value that is decremented by one C Unaffected Z Set if the result is 0 cleared otherwise S Setif the result is negative cleared otherwise V Setif arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 8 80 RR 81 IR Given RO 12H R1 R2 30H register 30H and register 21H DECW RRO gt RO 12H R1 33H DECW R2 gt Register 30H OFH register 20H In the first example destination register RO contains the value 12H and register R1 the value 34H The statement DECW RRO addresses and the following operand R1 as a 16 bit word decrements the value of R1 by one leaving the value 33H A system malfunction may occur if you use a Zero flag FLAGS 6 result together with a DECW instruction To avoid this problem we recommend that you use DECW as shown in the following example LOOP DECW RRO LD R2 R1 OR R2 RO
94. I O pins for capture input T1CAP or PWM or match output T1 PWM T1OUT Timer 1 overflow interrupt IRQ3 vector EAH and match capture interrupt IRQ3 vector E8H generation Timer 1 control register T1CON set 1 FBH Bank 1 read write ELECTRONICS 12 5 16 0 1 53 8245 8245 8249 8249 FUNCTION DESCRIPTION Timer 1 Interrupts IRQ3 Vectors E8H and EAH The timer 1 module can generate two interrupts the timer 1 overflow interrupt T1OVF and the timer 1 match capture interrupt T1OVF is interrupt level IRQ3 vector also belongs to interrupt level IRQ3 but is assigned the separate vector address E8H A timer 1 overflow interrupt pending condition is automatically cleared by hardware when it has been serviced A timer 1 match capture interrupt T1INT pending condition is also cleared by hardware when it has been serviced Interval Timer Function The timer 1 module can generate an interrupt the timer 1 match interrupt T1INT belongs to interrupt level IRQ3 and is assigned the separate vector address E8H When a timer 1 measure interrupt occurs and is serviced by the CPU the pending condition is cleared automatically by hardware In interval timer mode a match signal is generated and T1OUT is toggled when the counter value is identical to the value written to the T1 reference data register T1DATAH L The match signal generates a timer 1 match interrupt T1INT v
95. ICS 53 8245 8245 8249 8249 PRODUCT OVERVIEW Vpp Open drain Enable Pull up Vpp Resistor k P CH Data Pull up Enable Circuit Output Type C Disable ADC amp VLD ME Output Enable Disable d VLDREF Schmitt Trigger To ADC Figure 1 8 Pin Circuit Type E 2 P1 Figure 1 10 Pin Circuit Type F 18 P2 7 VLDgper Pull up Enable Data Circuit Output E Type C Disable ADCEN Data To ADC Figure 1 9 Pin Circuit Type F 10 2 0 2 6 Figure 1 11 Pin Circuit Type H SEG COM ELECTRONICS 1 9 PRODUCT OVERVIEW S3C8245 P8245 C8249 P8249 SEG Output Disable VLCO Figure 1 12 Pin Circuit Type H 4 Pull up Enable Circuit Disable Figure 1 13 Pin Circuit Type H 14 P4 P5 ELECTRONI S 53 8245 8245 8249 8249 ADDRESS SPACES ADDRESS SPACES OVERVIEW The S3C8245 C8249 microcontroller has two types of address space Internal program memory ROM Internal register file A 16 bit address bus supports program memory operations A separate 8 bit register bus carries addresses and data between the CPU and the register file The S3C8245 has an internal 16 Kbyte mask programmable ROM The S3C8249 has an internal 32 Kbyte mask programmable ROM The 256 byte physical register space is expanded into an addressable area of 320 bytes using addressing modes A 16 byte LCD display register file is implemented There are 1 109 mapped registers in t
96. IRQO IRQ7 can be selected for fast interrupt processing Procedure for Initiating Fast Interrupts To initiate fast interrupt processing follow these steps 1 Load the start address of the service routine into the instruction pointer IP 2 Load the interrupt level number IRQn into the fast interrupt selection field SYM 4 SYM 2 3 Write a 1 to the fast interrupt enable bit in the SYM register Fast Interrupt Service Routine When an interrupt occurs in the level selected for fast interrupt processing the following events occur The contents of the instruction pointer and the PC are swapped The FLAG register values are written to the FLAGS FLAGS prime register The fast interrupt status bit in the FLAGS register is set The interrupt is serviced Assuming that the fast interrupt status bit is set when the fast interrupt service routine ends the instruction pointer and PC values are swapped back The content of FLAGS FLAGS prime is copied automatically back to the FLAGS register The fast interrupt status bit in FLAGS is cleared automatically Relationship to Interrupt Pending Bit Types As described previously there are two types of interrupt pending bits One type that is automatically cleared by hardware after the interrupt service routine is acknowledged and executed the other that must be cleared by the application program s interrupt service routine You can select fast interrupt proc
97. L DATA S3C8245 P8245 C8249 P8249 Table 19 2 D C Electrical Characteristics Concluded Ta 25 C to 85 C Vpp 1 Conditions Supply current 1 2 Vpp 5 V 10 10 MHz oscillator 3 MHz 3 MHz crystal oscillator oscillator Vpp 3 V 10 10 MHz crystal oscillator 3 3 MHz crystal oscillator 3 MHz crystal oscillator oscillator Idle mode Vpp 5 V 10 10 MHz eee N oscillator 3 gt 3 MHz 3 MHz crystal oscillator oscillator Idle mode Vpp 3 V 10 10 MHz oscillator 3 MHz 3 MHz crystal oscillator oscillator Sub operating main osc stop Vpp 3 V 10 32 768 2 crystal oscillator OSCCON 4 1 Sub idle mode main osc stop Vpp 3 V 10 32 768 2 crystal oscillator OSCCON 4 1 Ibos Main stop mode sub osc stop Vpp 5 V 10 TA 25 G Vpp V 10 TA 25 C NOTES 1 Supply current does not include current drawn through internal pull up resistors or external output current loads 2 lpp and Ippo include a power consumption of subsystem oscillator gt 3 and lpp4 are the current when the main system clock oscillation stop and the subsystem clock is used And does not include the LCD and Voltage booster and voltage level detector Ipps is the current when the main and subsystem clock oscillation stop B 19 4 ELECTRONI S 53 8245 8245 8249 8249 ELECTRICAL DATA I
98. LTAGE The LCD display is turned on only when the voltage difference between the common and segment signals is greater than Vi cp The LCD display is turned off when the difference between the common and segment signal voltages is less than cp The turn on voltage Vi cp or Vi is generated only when both signals are the selected signals of the bias Table 14 7 shows LCD drive voltages for static mode 1 2 bias and 1 3 bias Table 14 6 LCD Drive Voltage Values LCD Power Supply 1 2 Bias 1 3 Bias NOTE TheLCD panel display may deteriorate if a DC voltage is applied that lies between the common and segment signal voltage Therefore always drive the LCD panel with AC voltage LCD SEG SEG SIGNALS The 32 LCD segment signal pins are connected to corresponding display RAM locations at 00H 0FH Bits 0 3 and 4 7 of the display RAM are synchronized with the common signal output pins COMO COM1 2 and COMS When the bit value of a display RAM location is 1 a select signal is sent to the corresponding segment pin When the display bit is 0 a no select signal is sent to the corresponding segment pin Each bias has select and no select signals COM SEG Figure 14 4 Select No Select Bias Signals in Static Display Mode ELECTRONICS 14 7 LCD CONTROLLER DRIVER S3C8245 P8245 C8249 P8249 COM SEG Figure 14 5 Select No Select Bias Signals 1 2 Duty 1 2 Bias Display Mode COM SEG Figure 14 6 Sele
99. OR POP POPUD POPUI PUSH PUSHUD PUSHUI RCF RET RL RLC RR RRC SBO SB1 SBC SCF SRA SRP SRP0 SRP1 STOP SUB SWAP TCM TM WFI XOR List of Instruction Descriptions Continued Full Register Name N Load Memory uapa t ace E e eee iue Inv e hi od a dee Load Memory and Load Memory and Increment Load Memory with Pre Decrement Load Memory with Pre Increment Load Word diii pae REM dx ess No Operat r Cogita OR POD TOM Stacks EIL Pop User Stack Pop User Stack Incrementing Push to Stacke Lt en uet bi reti reta d of tle Meses Push User Stack mener Push User Stack Incrementing Reset Carry Flag Rotate Left through Carry Rotate RIOM a a uu teas en er mb et RE Ee kaku TR BERE G LE EE ETE uay Rotate Right through Carry Select Bank Ous u A ete he Rer ertet E etude A Select Bank 1 Subtract with Carry Set Carry Flag toii ed o todo ence tede ied a to PE euo Ped dia ls Shift Right Arthimetie us epe Rte Set Register Pointer Slop Operation cysteine Cen te A i Cei a C e a Subtract Swap Nibbles Test Complement under Test under Mask
100. ORed with bit zero LSB of the destination or source The result bit is stored in the specified bit of the destination No other bits of the destination are affected The source is unaffected Unaffected Set if the result is 0 cleared otherwise Cleared to 0 Undefined Unaffected Unaffected r lt no Bytes Cycles Opcode Addr Mode Hex dst src dst 3 6 27 Rb m NOTE Inthe second byte of the 3 byte instruction formats the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H 00000111B and register 01H 03H 00000011B BXOR R1 01H 1 gt R1 06H register 01H 03H BXOR 01H 2 R1 gt Register 01H 07H R1 07H In the first example destination working register R1 has the value 07H 00000111B and source register 01H has the value 03H 00000011B The statement BXOR R1 01H 1 exclusive ORs bit one of register 01H source with bit zero of R1 destination The result bit value is stored in bit zero of R1 changing its value from 07H to O6H The value of source register 01H is unaffected ELECTRONICS 6 25 INSTRUCTION SET S3C8245 P8245 C8249 P8249 CALL Call Procedure CALL Operation Flags Format Examples 6 26 dst SP SP 1 lt PCL SP SP 1 lt lt dst The current contents of the program counter are pushed onto the top of the stack The program co
101. Pin Configuration Bits P4 4 P4 7 I O is selected SEG20 EG23 is selected P4 4 P4 7 I O is disabled LCD Output Segment and Pin Configuration Bits 4 0 4 3 I O is selected SEG16 SEG19 is selected 4 0 4 3 I O is disabled Not used for the S3C8245 C8249 LCD Bias Voltage Selection Bit 0 Enable LCD initial circuit internal bias voltage Disable LCD initial circuit for external LCD driving resister external bias voltage Voltage Booster Enable disable Bit o Stop voltage booster Clock stop and cut off current charge path Run voltage booster Clock run current and turn on charge path LCD Display Control Bit LCD output low turn display off COM and SEG output low cut off voltage booster Booster clock disable COM and SEG output is in display mode turn display on CONTROL REGISTERS 53 8245 8245 8249 8249 LMOD Lcp Mode Control Register D1H Set 1 Bit Identifier nRESET Value Read Write Addressing Mode 7 6 5 4 13 0 T 6 5 4 3 2 4 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W Register addressing mode only Not used for the S3C8245 C8249 LCD Clock LCDCK Frequency Selection Bits 9 iess iz watch ime ELECTRONI S 53 8245 8245 8249 8249 CONTROL REGISTER OSCCON oscillator Control Register F3H Set 1 Bank 0 nRESET Value 0 0 0 0 0 0 0 0 Read Write _ _ _ R W R W R W _ R W Addressing Mode Register address
102. RET Return WFI Wait for interrupt Bit Manipulation Instructions BAND dst src Bit AND BCP dst src Bit compare BITC dst Bit complement BITR dst Bit reset BITS dst Bit set BOR dst src Bit OR BXOR dst src Bit XOR dst src Test complement under mask TM dst src Test under mask 6 4 ELECTRONICS 53 8245 8245 8249 8249 Rotate and Shift Instructions RL dst RLC dst RR dst RRC dst SRA dst SWAP dst CPU Control Instructions CCF DI EI IDLE NOP RCF SBO SB1 SCF SRP src SRP0 src SRP1 src STOP ELECTRONICS INSTRUCTION SET Table 6 1 Instruction Group Summary Concluded Instruction Rotate left Rotate left through carry Rotate right Rotate right through carry Shift right arithmetic Swap nibbles Complement carry flag Disable interrupts Enable interrupts Enter mode No operation Reset carry flag Set bank 0 Set bank 1 Set carry flag Set register pointers Set register pointer 0 Set register pointer 1 Enter Stop mode 6 5 INSTRUCTION SET S3C8245 P8245 C8249 P8249 FLAGS REGISTER FLAGS The flags register FLAGS contains eight bits that describe the current status of CPU operations Four of these bits FLAGS 7 FLAGS 4 can be tested and used with conditional jump instructions two others FLAGS 3 and FLAGS 2 are used for BCD arithmetic The FLAGS register also contains a bit to indicate the status of fast interrupt processing FLAGS 1 and a b
103. RTS Port 5 Control Register Low Byte PSCONL EFH Set 1 Bank 1 R W P5 0 SEG24 P5 NN P5 2 SEG26 P5 3 SEG27 P5CONL bit pair pin configuration settings Input mode Input mode pull up Opendrain output mode Output mode push pull NOTE If LCD is enabled by LCON 6 SEG signal go out otherwise port 5 1 0 can be selected Figure 9 15 Port 5 Low Byte Control Register P5CONL ELECTRONICS 9 15 53 8245 8245 8249 8249 BASIC BASIC OVERVIEW S3C8245 C8249 has an 8 bit basic timer BASIC TIMER BT You can use the basic timer BT in two different ways a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction or signal the end of the required oscillation stabilization interval after a reset or a Stop mode release The functional components of the basic timer block are Clock frequency divider fxx divided by 4096 1024 128 or 16 with multiplexer 8 bit basic timer counter set 1 Bank 0 FDH read only Basic timer control register BTCON set 1 D3H read write BASIC TIMER CONTROL REGISTER BTCON The basic timer control register BTCON is used to select the input clock frequency to clear the basic timer counter and frequency dividers and to enable or disable the watchdog timer function It is located in set 1 address D3H and is read write addressable using Register addressing mode A reset clear
104. SABLE INTERRUPT INSTRUCTIONS El DI Executing the Enable Interrupts El instruction globally enables the interrupt structure All interrupts are then serviced as they occur according to the established priorities NOTE The system initialization routine executed after a reset must always contain an El instruction to globally enable the interrupt structure During the normal operation you can execute the DI Disable Interrupt instruction at any time to globally disable interrupt processing The El and DI instructions change the value of bit 0 in the SYM register SYSTEM LEVEL INTERRUPT CONTROL REGISTERS In addition to the control registers for specific interrupt sources four system level registers control interrupt processing The interrupt mask register enables un masks or disables masks interrupt levels interrupt priority register IPR controls the relative priorities of interrupt levels The interrupt request register IRQ contains interrupt pending flags for each interrupt level as opposed to each interrupt source system mode register SYM enables or disables global interrupt processing SYM settings also enable fast interrupts and control the activity of external interface if implemented Table 5 2 Interrupt Control Register Overview Control Register ID R W Function Description Interrupt mask register IMR RW Bit settings in the IMR register enable or disable interrupt
105. TAH 2 x 1 fx OH lt TBDATAH lt 100H where fx The selected clock When TBOF 1 ti ow TBDATAH 2 x 1 fx lt TBDATAH lt 100H where fx The selected clock TBDATAL 2 x 1 fx OH lt TBDATAL lt 100H where fx The selected clock To make ti ow 24 us and THIGH 15 us fosc 4 MHz fx 2 4 MHz 4 1 MHz When 0 24 us TBDATAL 2 fx TBDATAL 2 x tus TBDATAL 22 thich 15 us TBDATAH 2 TBDATAH 2 1us TBDATAH 13 When TBOF 1 thich 15 us TBDATAL 2 fx TBDATAL 2 x tus TBDATAL 13 24 us TBDATAH 2 TBDATAH 2 1 5 TBDATAH 22 ELECTRONICS 8 53 8245 8245 8249 8249 0 TBDATAL 01 TBDATAH 00H 0 TBDATAL 00H TBDATAH 01 FFH 0 TBDATAL 00H TBDATAH 00H 1 TBDATAL 00H TBDATAH 00H Timer B Clock 1 TBDATAL TBDATAH 1 0 TBDATAL DEH TBDATAH 1EH 1 TBDATAL 7EH TBDATAH 7EH 0 TBDATAL 7 TBDATAH 7EH Figure 11 6 Timer B Output Flip Flop Waveforms in Repeat Mode 11 8 ELECTRONICS 53 8245 8245 8249 8249 8 TIP To generate 38 kHz 1 3duty signal through P3 0 This example sets Timer B to the repeat mode sets th
106. TRONICS 2 11 ADDRESS SPACES 53 8245 8245 8249 8249 Special Purpose Registers General Purpose Register BR RH Bank 1 Bank 1 Control Registers System Registers CFH Register Pointers Each register pointer RP can independently point to one of the 24 8 byte slices of the register file other than set 2 After a reset RPO points to locations COH C7H and RP1 to locations C8H CFH that is to the common working register area LCD Data NOTE In the S3C8245 C8249 microcontroller Registers pages 0 4 are implemented Pages 0 4 contain all of the addressable registers in the internal register file Register Addressing Only Indirect Register Addressing Indexed Addressing Modes Addressing Modes Modes l Can be Pointed by Register Pointer Can be Pointed to By register Pointer Figure 2 9 Register File Addressing 2 12 ELECTRONICS 53 8245 8245 8249 8249 ADDRESS SPACES COMMON WORKING REGISTER AREA COH CFH After a reset register pointers RPO and RP1 automatically select two 8 byte register slices set 1 locations CFH as the active 16 byte working register block RPO COH C7H C8H CFH This 16 byte address range is called common area That is locations in this area can be used as working registers by operations that address any location on any page in the register file Typically these working registers serve as temporary buffers for data operations between
107. W R W R W R W R W Addressing Mode Register addressing mode only 7 Watch Timer Clock Selection Bit EJ Main system clock divided by 2 fxx 128 Sub system clock fxt 6 Watch Timer Interrupt Enable Bit Disable watch timer interrupt Enable watch timer interrupt 5 4 Buzzer Signal Selection Bits o o 05 khz ouzer BUZ sora oaa Co 1 i we buzzer Buz sora ouput SSS 1 ene buzzer BU signal ouput 3 2 Watch Speed Selection Bits po 1 0 25 s Interval 0 125 s Interval 1 955 ms Interval 1 Watch Timer Enable Bit Disable watch timer Clear frequency dividing circuits 1 Enable watch timer 0 Watch Timer Interrupt Pending Bit Interrupt is pending clear pending bit when write Interrupt is pending NOTE Watltch timer clock frequency fw is assumed to be 32 768 kHz 4 44 ELECTRONICS 53 8245 8245 8249 8249 INTERRUPT STRUCTURE INTERRUPT STRUCTURE OVERVIEW The S3C8 series interrupt structure has three basic components levels vectors and sources The SAM8 CPU recognizes up to eight interrupt levels and supports up to 128 interrupt vectors When a specific interrupt level has more than one vector address the vector priorities are established in hardware A vector address can be assigned to one or more sources Levels Interrupt levels are the main unit for interrupt priority assignment and recognition All peripherals and b
108. When pins are enabled for ADC mode by ADCEN the pins can be selected for ADC input by ADCON 6 5 4 Figure 9 9 Port 2 Low Byte Control Register P2CONL ELECTRONICS 9 9 5 53 8245 8245 8249 8249 3 Port is an 5 bit I O port with individually configurable pins Port pins are accessed directly by writing or reading the port data register at location F9H in set 1 bank 0 0 can serve as inputs with or without pull ups as push pull outputs or you can configure the following alternative functions TACLK TAOUT TAPWM and TBPWM Port 3 Control Registers Port has two 8 bit control registers PSCONH for P3 4 and PSCONL for P3 0 P3 3 A reset clears the PSCONH and registers to OOH configuring all pins to input mode You use control registers settings to select input or output mode enable pull up resistors and enable the alternative functions When programming this port please remember that any alternative peripheral I O function you configure using the port 3 control registers must also be enabled in the associated peripheral module Port Control high Register High Byte E8H Set 1 Bank 0 R W Input mode Input mode pull up Output mode push pull Figure 9 10 Port 3 High Byte Control Register 9 10 ELECTRONICS 53 8245 8245 8249 8249 PORTS Port Control Register Low Byte P8CONL
109. a of set 1 is further expanded two 32 byte register banks bank 0 and bank 1 and the lower 32 byte area is a single 32 byte common area In case of S3C8249 P8249 the total number of addressable 8 bit registers is 1122 Of these 1122 registers 16 bytes are for CPU and system control registers 16 bytes are for LCD data registers 50 bytes are for peripheral control and data registers 16 bytes are used as a shared working registers and 1024 registers are for general purpose use page 0 page 4 in case of S3C8245 P8245 page 0 page 2 You can always address set 1 register locations regardless of which of the four register pages is currently selected Set 1 locations however can only be addressed using register addressing modes The extension of register space into separately addressable areas sets banks and pages is supported by various addressing mode restrictions the select bank instructions SB0 and SB1 and the register page pointer PP Specific register types and the area in bytes that they occupy in the register file are summarized in Table 2 1 Table 2 1 S3C8249 P8249 Register Type Summary Register Type Number of Bytes General purpose registers including the 16 byte common 1 040 working register area four 192 byte prime register area and four 64 byte set 2 area LCD data registers CPU and system control registers Mapped clock peripheral control and data registers Total Addressable Bytes General purpo
110. addressed by the stack pointer are loaded into the destination The stack pointer is then incremented by one No flags affected Bytes Cycles Opcode Addr Mode Hex dst dst 2 8 50 R 51 IR Given Register 00H 01H register 01H 1BH SPH 0D8H SPL 0D9H OFBH and stack register 0FBH 55H POP 00H gt Register OOH 55H SP OOFCH POP 00H gt Register OOH 01H register 01H 55H SP OOFCH In the first example general register OOH contains the value 01H The statement POP 00H loads the contents of location 00FBH 55H into destination register OOH and then increments the stack pointer by one Register then contains the value 55H and the SP points to location OOFCH ELECTRONICS 53 8245 8245 8249 8249 INSTRUCTION SET POPUD Pop User Stack Decrementing POPUD Operation Flags Format Example dst src dst src IR IR 1 This instruction is used for user defined stacks in the register file The contents of the register file location addressed by the user stack pointer are loaded into the destination The user stack pointer is then decremented No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc src dst 3 8 92 R IR Given Register 42H user stack pointer register register 42H 6FH and register 02H 70H POPUD 02H 00H gt Register OOH 41H register 02H 6FH register 42H 6FH If general register 00H contains
111. ail and further prepares you for additional information presented in the individual hardware module descriptions in Part Il Chapter 6 Instruction Set describes the features and conventions of the instruction set used for all S3C8 series microcontrollers Several summary tables are presented for orientation and reference Detailed descriptions of each instruction are presented in a standard format Each instruction description includes one or more practical examples of how to use the instruction when writing an application program A basic familiarity with the information in Part will help you to understand the hardware module descriptions in Part II If you are not yet familiar with the S3C8 series microcontroller family and are reading this manual for the first time we recommend that you first read Chapters 1 3 carefully Then briefly look over the detailed information in Chapters 4 5 and 6 Later you can reference the information in Part as necessary Part Il hardware Descriptions has detailed information about specific hardware components of the 3C8245 P8245 C8249 P8249 microcontroller Also included in Part Il are electrical mechanical OTP and development tools data It has 16 chapters Chapter 7 Clock Circuit Chapter 15 10 bit to Digital Converter Chapter 8 nRESET and Power Down Chapter 16 Serial I O Interface Chapter 9 Ports Chapter 17 Voltage Booster Chapter 10 Basic Timer Chapter 18 Voltage Level Detector Chapter 11
112. alted until an interrupt occurs except that DMA transfers can still take place during this wait state The WFI status can be released by an internal interrupt including a fast interrupt Flags No flags are affected Format Bytes Cycles Opcode Hex 1 4 1 2 3 The following sample program structure shows the sequence of operations that follow WFI statement Main program El Enable global interrupt WFI Wait for interrupt Next instruction Interrupt occurs Interrupt service routine Clear interrupt flag IRET Service routine completed ELECTRONICS 6 87 INSTRUCTION SET S3C8245 P8245 C8249 P8249 XOR Logical Exclusive OR XOR Operation Flags Format Examples 6 88 dst src dst dst XOR src The source operand is logically exclusive ORed with the destination operand and the result is stored in the destination The exclusive OR operation results in a 1 bit being stored whenever the corresponding bits in the operands are different otherwise a 0 bit is stored Unaffected Z Setif the result is 0 cleared otherwise S Setif the result bit 7 is set cleared otherwise V Always reset to O D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src 6 B3 r Ir src dst 3 6 B4 R R B5 R IR dst src 3 6 B6 R IM Given RO 0C7H R1 02H R2 18H register OOH 2BH register 01 02H and register 02
113. and Depending on the instruction used the actual address may point to a register in the register file to program memory ROM or to an external memory space see Figures 3 3 through 3 6 You can use any 8 bit register to indirectly address another register Any 16 bit register pair can be used to indirectly address another memory location Please note however that you cannot access locations set 1 using the Indirect Register addressing mode Program Memory Register File PE dee 2 2 20 ADDRESS OPCODE Point to One gt Register Register OneOperand Instruction Example Address of Operand used by Instruction Value used in OPERAND Instruction Execution Sample Instruction RL SHIFT Where SHIFT is the label of an 8 bit register address Figure 3 3 Indirect Register Addressing to Register File ELECTRONICS 3 3 ADDRESSING MODES 53 8245 8245 8249 8249 INDIRECT REGISTER ADDRESSING Continued Register File REGISTER Example Instruction References OPCODE Points to Progam ee ie Address Points to Program Memory Program Memory Sample Instructions Value used in OPERAND ti CALL RR2 nstruction JP RR2 Figure 3 4 Indirect Register Addressing to Program Memory 3 4 ELECTRONICS 53 8245 8245 8249 8249 ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE Continued Register File MSB Points to RPO or RP1 RPO
114. and CLKCON 3 register values remain unchanged and the currently selected clock value is used The interrupt is then serviced When the return from interrupt IRET occurs the instruction immediately following the one that initiated idle mode is executed 8 6 ELECTRONICS 53 8245 8245 8249 8249 PORTS PORTS OVERVIEW The S3C8245 C8249 microcontroller has two nibble programmable and four bit programmable I O ports P0 P5 The port 3 is a 5 bit port and the others 8 bit ports This gives a total of 45 I O pins Each port be flexibly configured to meet application design requirements The CPU accesses ports by directly writing or reading port registers No special I O instructions are required Table 9 1 gives you a general overview of the S3C8245 C8249 I O port functions Table 9 1 53 8245 8249 Port Configuration Overview Configuration Options 1 bit programmable I O port Schmitt trigger input or output mode selected by software software assignable pull up P0 0 PO 7 can be used as inputs for external interrupts INTO INT7 with noise filter and interrupt control 1 bit programmable I O port Input or output mode selected by software open drain output mode can be selected by software software assignable pull up Alternately P1 0 P1 7 can be used as SI SO SCK BUZ T1CAP T1CLK T1OUT T1PWM 1 bit programmable I O port Normal input and AD input or output mode selected by software sof
115. ank address status bit FLAGS 0 to indicate whether bank 0 or bank 1 is currently being addressed FLAGS register can be set or reset by instructions as long as its outcome does not affect the flags such as Load instruction Logical and Arithmetic instructions such as AND OR XOR ADD and SUB can affect the Flags register For example the AND instruction updates the Zero Sign and Overflow flags based on the outcome of the AND instruction If the AND instruction uses the Flags register as the destination then simultaneously two write will occur to the Flags register producing an unpredictable result System Flags Register FLAGS D5H Set 1 RW Carry flag C m Zero flag Z 2 Sign flag S Half carry flag H Overflow V Decimal adjust flag D Figure 6 1 System Flags Register FLAGS 6 6 ELECTRONICS 53 8245 8245 8249 8249 INSTRUCTION SET FLAG DESCRIPTIONS C FIS BA Carry Flag FLAGS 7 The C flag is set to 1 if the result from an arithmetic operation generates a carry out from or a borrow to the bit 7 position MSB After rotate and shift operations it contains the last value shifted out of the specified register Program instructions can set clear or complement the carry flag Zero Flag FLAGS 6 For arithmetic and logic operations the Z flag is set to 1 if the result of the operation is zero For operations that test register bits and for shift and rotate operations the Z flag is s
116. are In interval timer mode a match signal is generated and TAOUT is toggled when the counter value is identical to the value written to the TA reference data register TADATA The match signal generates a timer A match interrupt TAINT vector EOH and clears the counter If for example you write the value 10H to TADATA and to TACON the counter will increment until it reaches 10H At this point the TA interrupt request is generated the counter value is reset and counting resumes Pulse Width Modulation Mode Pulse width modulation PWM mode lets you program the width duration of the pulse that is output at the TAPWM pin As in interval timer mode a match signal is generated when the counter value is identical to the value written to the timer A data register In PWM mode however the match signal does not clear the counter Instead it runs continuously overflowing at FFH and then continues incrementing from OOH Although timer A overflow interrupt is occurred this interrupt is not typically used in PWM type applications Instead the pulse at the TAPWM pin is held to Low level as long as the reference data value is less than or equal to x the counter value and then the pulse is held to High level for as long as the data value is greater than the counter value One pulse width is equal to 256 Capture Mode In capture mode a signal edge that is detected at the TACAP pin opens a gate and loads the curren
117. ared in the interrupt service routine Pending Bits Cleared Automatically by Hardware For interrupt pending bits that are cleared automatically by hardware interrupt logic sets the corresponding pending bit to 1 when a request occurs It then issues an IRQ pulse to inform the CPU that an interrupt is waiting to be serviced The CPU acknowledges the interrupt source by sending an IACK executes the service routine and clears the pending bit to 0 This type of pending bit is not mapped and cannot therefore be read or written by application software In the 53 8245 8249 interrupt structure the timer 0 overflow interrupt IRQO belongs to this category of interrupts in which pending condition is cleared automatically by hardware Pending Bits Cleared by the Service Routine The second type of pending bit is the one that should be cleared by program software The service routine must clear the appropriate pending bit before a return from interrupt subroutine IRET occurs To do this a 0 must be written to the corresponding pending bit location in the source s mode or control register 5 14 ELECTRONICS 53 8245 8245 8249 8249 INTERRUPT STRUCTURE INTERRUPT SOURCE POLLING SEQUENCE The interrupt request polling and servicing sequence is as follows Di oe gt A source generates an interrupt request by setting the interrupt request bit to 1 The CPU polling procedure identifies a pending condition for that
118. ator is activated and the fxx 16 the slowest clock speed is selected as the CPU clock If necessary you can then increase the CPU clock speed fxx 8 fxx 2 or fxx 1 System Clock Control Register CLKCON Set 1 R W 7 o Not used must keep always 0 Not used must keep always 0 Divide by selection bits for CPU clock frequency 00 fxx 16 01 txx 8 10 fxx 2 11 fxx 1 non divided NOTE The fxx can be generated by both main system and sub system oscillator therefore while main system stops peripherals can be operated by sub system Figure 7 4 System Clock Control Register CLKCON ELECTRONICS 7 8 CLOCK CIRCUIT 53 8245 8245 8249 8249 Oscillator Control Register OSCCON Set 1 bank 0 R W er 5 Not used Not used System clock selection bit 0 Main oscillator select 1 Subsystem oscillator select Subsystem oscillator driving ability control bit Subsystem oscillator control bit 0 Strong driving ability 0 Subsystem oscillator RUN 1 Normal driving ability 1 Subsystem oscillator STOP Mainsystem oscillator control bit 0 Mainsystem oscillator RUN 1 Mainsystem oscillator STOP NOTE In strong mode the warm up time is less than 100 ms When the CPU is operated with fxt sub oscillation clock it is possible to use the stop instruction but in this case before using stop instruction you must select fxx 128 for basic timer
119. carry flag is cleared to logic zero regardless of its previous value C Cleared to 0 No other flags are affected Bytes Cycles Given C 1 or 0 The instruction RCF clears the carry flag C to logic zero S3C8245 P8245 C8249 P8249 Opcode Hex CF ELECTRONICS 53 8245 8245 8249 8249 INSTRUCTION SET RET Return RET Operation Flags Format Example PC SP SP lt SP 2 The RET instruction is normally used to return to the previously executing procedure at the end of a procedure entered by a CALL instruction The contents of the location addressed by the stack pointer are popped into the program counter The next statement that is executed is the one that is addressed by the new program counter value No flags are affected Bytes Cycles Opcode Hex opc 1 8 internal stack AF 10 internal stack Given SP 00FCH SP 101AH and PC 1234 RET gt PC 101AH SP 00 The statement RET pops the contents of stack pointer location OOFCH 10H into the high byte of the program counter The stack pointer then pops the value in location 00FEH 1AH into the PC s low byte and the instruction at location 101AH is executed The stack pointer now points to memory location OOFEH ELECTRONICS 6 71 INSTRUCTION SET RL Rotate Left RL Operation dst C lt dst 7 dst 0 dst 7 dst n 1 lt dst n n 0 6 The contents of the destination o
120. ce are unaffected LDCPD refers to program memory and LDEPD refers to external data memory The assembler makes an even number for program memory and odd number for external data memory Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src 2 14 2 r Examples Given RO 77H R6 30H and R7 00 LDCPD RR6 RO RR6 RR6 1 77H contents of RO is loaded into program memory location 2FFFH 3000H 1H RO 77H R6 2FH R7 LDEPD RR6 RO RR6 lt RR6 1 77H contents of RO is loaded into external data memory location 2FFFH 3000H 1H RO 77H R6 2FH R7 OFFH ELECTRONICS 6 57 INSTRUCTION SET S3C8245 P8245 C8249 P8249 LDCPI LDEPI Load Memory with Pre Increment LDCPI LDEPI Operation Flags Format Examples 6 58 dst src m rr 1 dst src These instructions are used for block transfers of data from program or data memory from the register file The address of the memory location is specified by a working register pair and is first incremented The contents of the source location are loaded into the destination location The contents of the source are unaffected LDCPI refers to program memory and LDEPI refers to external data memory The assembler makes an even number for program memory and an odd number for data memory No flags are affected Bytes Cycles Opcode Addr Mode Hex ds
121. ck Status During Power Down 7 2 System Clock Control Register 7 3 Chapter 8 nRESET and Power Down System MRESE e Et 8 1 OVOlViGW 8 1 Normal Mode Reset Operation 8 1 Hardware Reset 8 2 Power Down Modes osie eniai e ads 8 5 jenes DIDI 8 5 die 8 6 Chapter 9 I O Ports MEM ETT 9 1 Port Data Registers Em 9 2 9 3 pe 9 6 POtt 2 ceci Puce 9 8 autcm 9 10 POM RN p tend Pr Sie e sb RE 9 12 POMS 5 C 9 14 Chapter 10 Basic Timer CU 10 1 Basic 10 1 Basic Timer Control Register 10 1 Bask Timer Function Description Qa ecce E 10 3 3C8245 P8245 C8249 P8249 MICROCONTROLLER vii Table of Contents Continued Chapter 11 8 bit Timer
122. cleared otherwise Set if the result is 0 cleared otherwise Set if the result is negative cleared otherwise Set if arithmetic overflow occurs that is if both operands are of the same sign and the result is of the opposite sign cleared otherwise Always cleared to 0 Set if there is a carry from the most significant bit of the low order four bits of the result cleared otherwise 9 Bytes Cycles Opcode Addr Mode Hex dst src 6 13 r Ir opc src dst 3 6 14 R R 6 15 R IR opc dst src 3 6 16 R IM Given R1 10H R2 03H C flag 1 register 01H 20H register 02H 03H and register 03H OAH ADC R1 R2 gt R1 14H R2 03H ADC R1 R2 gt R1 1BH R2 03H ADC 01H 02H gt Register 01H 24H register 02H 03H ADC 01H 02H gt Register 01H 2BH register 02H 03H ADC 01H 11H gt Register 01H 32H In the first example destination register R1 contains the value 10H the carry flag is set to 1 and the source working register R2 contains the value 03H The statement ADC R1 R2 adds 03H and the carry flag value 1 to the destination value 10H leaving 14H in register R1 ELECTRONICS 53 8245 8245 8249 8249 ADD ADD Operation Flags Format Examples dst src dst dst src INSTRUCTION SET The source operand is added to the destination operand and the sum is stored in the destination The contents of the source are unaffected Two s complement addit
123. configures the corresponding module with an internal clock source at the SCK selects receive only operating mode and clears the 3 bit counter The data shift operation and the interrupt are disabled The selected data direction is MSB first Serial I O Module Control Registers SIOCON Set 1 Bank 0 R W SIO shift clock selection bit 0 Internal clock P S Clock 1 External clock SCK Data direction control bit 0 MSB first mode 1 2 LSB first mode SIO mode selection bit 0 Receive only mode 1 Transmit receive mode Shift clock edge selection bit 0 Tx at falling edeges Rx at rising edges 1 Tx at rising edeges Rx at falling edges SIO interrupt pending bit 0 No interrupt pending 0 Clear pending condition when write 1 2 Interrupt is pending SIO interrupt enable bit 0 Disable SIO interrupt 1 Enable SIO interrupt SIO shift operation enable bit 0 Disable shifter and clock counter 1 Enable shifter and clock counter SIO counter clear and shift start bit 0 No action 1 Clear 3 bit counter and start shifting Figure 16 1 Serial I O Module Control Registers SIOCON 16 2 ELECTRONICS 53 8245 8245 8249 8249 SERIAL I O INTERFACE SIO PRE SCALER REGISTER SIOPS The control register for serial 1 interface module SIOPS is located at F2H set 1 bank 0 The value stored in the SIO pre scale registers SIOPS lets you determine the SIO clock rate baud rate as follows
124. ct No Select Bias Signals in 1 3 Duty 1 3 Bias Display Mode 14 8 ELECTRONICS 53 8245 8245 8249 8249 LCD CONTROLLER DRIVER d I I 19 4 VLCo Data Register page 4 address 00H 1 0 LD 00H 31h Data Register page 4 addressO1H 5 6 7 LD 01H 12h Figure 14 7 LCD Signal and Wave Forms Example in 1 2 Duty 1 2 Bias Display Mode ELECTRONICS 14 9 LCD CONTROLLER DRIVER S3C8245 P8245 C8249 P8249 1 I I 2 LO 10 V5 SEG SEG3 2 Data Register page 4 address 00H 0 1 2 3 4567 Data Register page 4 address 01H 4 5 6 7 Data Register page 4 address 02H LD 16h LD 00H 43h LD 02H 33h Figure 14 8 LCD Signals and Wave Forms Example in 1 3 Duty 1 3 Bias Display Mode 14 10 ELECTRONICS LCD CONTROLLER DRIVER S3C8245 P8245 C8249 P8249 2 4 2 3 9 20 SseJppe p sajsibay uvZ amp HIO q1 H O SseJppe p eDed sajsibay U3 amp HOO p sajsibay Figure 14 9 LCD Signals and Wave Forms Example in 1 4 Duty 1 3 Bias Display Mode 14 11 ELECTRONI S LCD CONTROLLER DRIVER S3C8245 P8245 C8249 P8249 LCD VOLTAGE DRIVING METHOD By Voltage Booster Fo
125. d Write R W R W _ _ _ Addressing Mode Register addressing mode only 7 5 Not used for the 5308245 C8249 A 3 CPU Clock System Clock Selection Bits note o SOS cops fee SSCS 2 0 Not used for the S3C8245 C8249 NOTE After a reset the slowest clock divided by 16 is selected as the system clock To select faster clock speeds load the appropriate values to CLKCON 3 and CLKCON 4 ELECTRONICS 4 7 CONTROL REGISTERS 53 8245 8245 8249 8249 Memory Timing Register FEH Set 1 Bank 0 nRESET Value 0 Read Write _ _ _ _ _ _ _ _ Addressing Mode Register addressing mode only 7 0 Not used for the S3C8245 C8249 4 8 ELECTRONI S 53 8245 8245 8249 8249 CONTROL REGISTER FLAGS System Flags Register D5H Set 1 Bit Identifier 7 6 s 4 3 2 t o x x x x x x 0 0 nRESET Value Read Write R W R W R W R W R W R W R R W Addressing Mode Register addressing mode only 7 Carry Flag Operation does generate borrow condition Operation generates a carry out or borrow into high order bit 7 6 Zero Flag Z Operation result is a non zero value Operation result is zero 5 Sign Flag S Operation generates a positive number MSB 0 Operation generates a negative number MSB 1 4 Overflow Flag V Operation result is lt 127 gt 128 IA IV 1 Operation result is gt 127 or lt
126. d select the relationship C gt B gt A The functions of the other IPR bit settings are as follows 5 controls the relative priorities of group interrupts Interrupt group C includes a subgroup that has an additional priority relationship among the interrupt levels 5 6 and 7 IPR 6 defines the subgroup C relationship IPR 5 controls the interrupt group C 0 controls the relative priority setting of IRQO and IRQ1 interrupts ELECTRONICS 5 11 INTERRUPT STRUCTURE S3C8245 P8245 C8249 P8249 Interrupt Priority Register IPR FFH Set 1 Bank 0 R W Group priority Group A D7 D4 D1 0 IRQO gt IRQ1 1 IRQ1 gt IRQ0 0 Undefined Group B 1 B gt C gt A 0 IRQ2 gt IRQ3 IRQ4 0 gt gt 1 IRQ3 IRQ4 gt IRQ2 1 gt gt Subgroup 0 gt gt 0 IRQ3 gt IRQ4 1 gt gt 1 IRQ4 gt IRQ3 0 A gt C gt B Group C 1 Undefined 0 IRQ5 gt IRQ6 IRQ7 1 IRQ6 IRQ7 gt IRQ5 Subgroup C 0 IRQ6 gt IRQ7 1 IRQ7 gt IRQ6 0 0 0 0 1 1 1 1 Figure 5 8 Interrupt Priority Register IPR 5 12 ELECTRONICS 53 8245 8245 8249 8249 INTERRUPT STRUCTURE INTERRUPT REQUEST REGISTER IRQ You can poll bit values in the interrupt request register IRQ set 1 DCH to monitor interrupt request status for all levels in the microcontroller s interrupt structure Each bit corresponds to the interrupt level of the same number bi
127. des UGE ULT UGT and ULE must be used 6 12 ELECTRONICS 53 8245 8245 8249 8249 INSTRUCTION DESCRIPTIONS INSTRUCTION SET This section contains detailed information and programming examples for each instruction in the SAM8 instruction set Information is arranged in a consistent format for improved readability and for fast referencing The following information is included in each instruction description Instruction name mnemonic Full instruction name Source destination format of the instruction operand Shorthand notation of the instruction s operation Textual description of the instruction s effect Specific flag settings affected by the instruction Detailed description of the instruction s format execution time and addressing mode s Programming example s explaining how to use the instruction ELECTRONICS INSTRUCTION SET S3C8245 P8245 C8249 P8249 ADC Add with carry ADC Operation Flags Format Examples dst src dst dst src c The source operand along with the setting of the carry flag is added to the destination operand and the sum is stored in the destination The contents of the source are unaffected Two s complement addition is performed In multiple precision arithmetic this instruction permits the carry from the addition of low order operands to be carried into the addition of high order operands Set if there is a carry from the most significant bit of the result
128. different pages Following a hardware reset register pointers RPO and RP1 point to the common working register area locations COH CFH LCD Data Figure 2 10 Common Working Register Area ELECTRONICS 2 13 ADDRESS SPACES 53 8245 8245 8249 8249 PROGRAMMING Addressing the Common Working Register Area As the following examples show you should access working registers in the common area locations COH CFH using working register addressing mode only Examples 1 LD 0C2H 40H Use working register addressing instead SRP 0C0H LD R2 40H Invalid addressing mode R2 C2H the value in location 40H 2 ADD 0C3H 45H Invalid addressing mode Use working register addressing instead SRP 0C0H ADD R3 445H C3H gt 45H 4 BIT WORKING REGISTER ADDRESSING Each register pointer defines a movable 8 byte slice of working register space The address information stored in a register pointer serves as an addressing window that makes it possible for instructions to access working registers very efficiently using short 4 bit addresses When an instruction addresses a location in the selected working register area the address bits are concatenated in the following way to form a complete 8 bit address The high order bit of the 4 bit address selects one of the register pointers 0 selects RPO 1 selects RP1 The five high order bits in the register pointer select an 8 byte slic
129. e pin active TA 3 gt TA 25 C to 85 C Vpp 1 8 V to 5 5 V Operating voltage fopy 10 MHz 27 Input high voltage All input pins except Vip IL2 2 7 Input low voltage All input pins except Vi 19 2 ELECTRONICS 53 8245 8245 8249 8249 Table 19 2 Electrical Characteristics Continued TA 25 C to 85 C Vpp 1 8 V to 5 5 V Symbol All output pins All output pins Input high leakage Vin Vpp Vin VoD Xn XTN Input low leakage 0 current All input pins except l 12 Output high leakage lg Vpp am Output low leakage lot 0 am 1O Oscillator feed back Vpg 5 0V Ta 25 C 300 resistors Xu Man Pull up resistor RI 1 Vi 0 V Vpp 5 V 410 Bd Port 0 1 2 3 4 5 25 C Ro 0 5 V 10 25 C nRESET only out voltage Vico Ta 25 C 1 3 bias mode Booster run mode 25 1 2 bias mode 1 Out voltage Vict 25 C 1 2 and 1 3 bias 2 cq 0 1 Vice out voltage Vico Ta 25 C 1 3 bias mode 0 1 canny COM output Vop Vice 3 V voltage deviation Vicp COMi IO 15 pA i 0 3 SEG output Voo Vice 3 V voltage deviation Vi cp SEGi IO 15 HA i 0 31 NOTE Low leakage current is absolute value ELECTRONI S ELECTRICAL DATA ELECTRICA
130. e Pointer PP u u 2 5 Register Set 1 ae ev pa Ore A Aiea 2 6 niece 2 6 Prime Register Space nu evo da eli Rude dvd 2 7 Wotking Registets deest eden ob ush qha eie 2 8 Using the Register Points iecur ier 2 9 Register Addressing Em 2 11 Common Working Register Area 2 13 4 bit Working Register 2 14 8 bit Working Register ee ene mene 2 16 System and User Stacks utes oie e PRU dele o Rr E SU ri MERE DURER ERE DU aha 2 18 Chapter 3 Addressing Modes OVOIVIOW Rea Gne tutu St a esos edo ctu edes 3 1 Register Addressing Mode R hressa EGIMUS MUI MESS 3 2 Indirect Register Addressing Mode 3 3 Indexed Addressing Mode X See Xa Ense 3 7 Direct Address Mode DA 3 10 Indirect Address Mode IA 3 12 Relative Address Mode RA ferdinin eiii a Ea te
131. e from the stack POP IMR 5 Execute an IRET Depending on the application you may be able to simplify the procedure above to some extent INSTRUCTION POINTER IP The instruction pointer IP is adopted by all the S3C8 series microcontrollers to control the optional high speed interrupt processing feature called fast interrupts The IP consists of register pair DAH and DBH The names of IP registers are IPH high byte IP15 IP8 and IPL low byte IP7 IP0 FAST INTERRUPT PROCESSING The feature called fast interrupt processing allows an interrupt within a given level to be completed in approximately 6 clock cycles rather than the usual 16 clock cycles To select a specific interrupt level for fast interrupt processing you write the appropriate 3 bit value to SYM 4 SYM 2 Then to enable fast interrupt processing for the selected level you set SYM 1 to 1 5 16 ELECTRONICS 53 8245 8245 8249 8249 INTERRUPT STRUCTURE FAST INTERRUPT PROCESSING Continued Two other system registers support fast interrupt processing The instruction pointer IP contains the starting address of the service routine and is later used to swap the program counter values and When a fast interrupt occurs the contents of the FLAGS register is stored in unmapped dedicated register called FLAGS FLAGS prime NOTE For the S3C8245 C8249 microcontroller the service routine for any one of the eight interrupt levels
132. e mask programmable ROM and watchdog functions system reset embedded respectively Two 8 bit timer counter and two 16 bit The S3P8245 is a microcontroller with a 16K byte timer counter with selectable operating modes one time programmable ROM embedded The S3P8249 is a microcontroller with a 32K byte f one time programmable ROM embedded 8 input A D converter Serial interface Watch timer for real time Using a proven modular design approach Samsung engineers have successfully developed the The S3C8245 P8245 C8249 P8249 is versatile S3C8245 P8245 C8249 P8249 by integrating the microcontroller for camera LCD and ADC application following peripheral modules with the powerful SAM8 etc They are currently available in 80 pin TQFP and core 80 pin QFP package OTP The S3P8245 P8249 are OTP One Time Programmable version of the S3C8245 C8249 microcontroller The S3P8245 microcontroller has an on chip 16K byte one time programmable EPROM instead of a masked ROM The S3P8249 microcontroller has an on chip 32K byte one time programmable EPROM instead of a masked ROM The S3P8245 is comparable to the S3P8245 both in function and in pin configuration The S3P8249 is comparable to the S3P8249 both in function and in pin configuration ELECTRONICS 1 1 PRODUCT OVERVIEW FEATURES Memory e 32K byte S3C8249 P8249 e 16K byte S3C8245 P8245 1056 Byte S3C8249 P8249 e RAM 544
133. e of the register space The three low order bits of the 4 bit address select one of the eight registers in the slice As shown in Figure 2 11 the result of this operation is that the five high order bits from the register pointer are concatenated with the three low order bits from the instruction address to form the complete address As long as the address stored in the register pointer remains unchanged the three bits from the address will always point to an address in the same 8 byte register slice Figure 2 12 shows a typical example of 4 bit working register addressing The high order bit of the instruction INC R6 is 0 which selects RPO The five high order bits stored in RPO 01110B are concatenated with the three low order bits of the instruction s 4 bit address 110B to produce the register address 76H 01110110B 2 14 ELECTRONICS 53 8245 8245 8249 8249 ADDRESS SPACES Selects RPO or Address OPCODE 2 2 444 2 2 4 L ll ttt 4 bit address Register pointer provides three provides five low order bits high order bits w Together they create 8 bit register address Figure 2 11 4 Bit Working Register Addressing RP0 RP1 Selects RP0 R6 OPCODE Register Instruction 01110 address 01101 1110 76H Figure 2 12 4 Bit Working Register Addressing Example ELECTRONICS 2 15 ADDRESS SPACES 53 8245 8245 8249 8249 8 BIT WORKING REGISTER ADDRESSING
134. e oscillation frequency as the Timer B clock source and TBDATAH and TBDATAL to make a 38 kHz 1 3 Duty carrier frequency The program parameters are 8 7955 17 59 165 37 9 kHz 1 3 Duty Timer B is used in repeat mode Oscillation frequency is 4 MHz 0 25 us TBDATAH 8 795 us 0 25 us 35 18 TBDATAL 17 59 us 0 25 us 70 36 Set P3 0 to TBPWM mode ORG START DI LD LD LD ELEGTRONIGS 0100H TBDATAL 70 2 TBDATAH 35 2 TBCON 00000110B P3CONL 02H Reset address Set 17 5 us Set 8 75 us Clock Source lt fxx Disable Timer B interrupt Select repeat mode for Timer B Start Timer B operation Set Timer B Output flip flop TBOF high Set P3 0 to TBPWM mode This command generates 38 kHz 1 3 duty pulse signal through P3 0 8 53 8245 8245 8249 8249 55 PROGRAMMING generate pulse signal through P3 0 This example sets Timer B to the one shot mode sets the oscillation frequency as the Timer B clock source and TBDATAH and TBDATAL to make a 40 us width pulse The program parameters are Timer B is used in one shot mode Oscillation frequency is 4 MHz 1 clock 0 25 us TBDATAH 40 us 0 25 us 160 TBDATAL 1 Set P3 0 to TBPWM mode ORG 0100H Reset address START DI LD TBDATAH 160 2 Set 40 us LD TBDATAL 1 Set any value except 00H LD TBCON 00000001
135. e register block anywhere in the addressable register file except the set 2 area The terms slice and block are used in this manual to help you visualize the size and relative locations of selected working register spaces One working register s ice is 8 bytes eight 8 bit working registers RO R7 or R8 R15 working register block is 16 bytes sixteen 8 bit working registers RO R15 All the registers in an 8 byte working register slice have the same binary value for their five most significant address bits This makes it possible for each register pointer to point to one of the 24 slices in the register file The base addresses for the two selected 8 byte register slices are contained in register pointers RPO and RP1 After a reset RPO and RP1 always point to the 16 byte common area in set 1 COH CFH Slice 32 Slice 31 11111XXX Each register pointer points to one 8 byte slice of the register space selecting a total 16 byte working register block 00000XXX Figure 2 5 8 Byte Working Register Areas Slices 2 8 ELECTRONICS 53 8245 8245 8249 8249 ADDRESS SPACES USING THE REGISTER POINTS Register pointers RPO and RP1 mapped to addresses D6H and D7H in set 1 are used to select two movable 8 byte working register slices in the register file After a reset they point to the working register common area RPO points to addresses COH C7H and RP1 points to addresses C8H CFH To change a register poi
136. ector E8H and clears the counter If for example you write the value 0010H to T1DATAH L and 06H to T1CON the counter will increment until it reaches 0010H At this point the T1 interrupt request is generated the counter value is reset and counting resumes Pulse Width Modulation Mode Pulse width modulation PWM mode lets you program the width duration of the pulse that is output at the T1PWM pin As in interval timer mode a match signal is generated when the counter value is identical to the value written to the timer 1 data register In PWM mode however the match signal does not clear the counter but can generate a match interrupt The counter runs continuously overflowing at FFFFH and then repeat the incrementing from 0000H Whenever an overflow is occurred an overflow OVF interrupt can be generated Although you can use the match or the overflow interrupt in PWM mode interrupts are not typically used in PWM type applications Instead the pulse at the T1PWM pin is held to Low level as long as the reference data value is less than or equal to x the counter value and then pulse is held to High level for as long as the data value is greater than gt the counter value One pulse width is equal to tci k Capture Mode In capture mode a signal edge that is detected at the T1CAP pin opens a gate and loads the current counter value into the T1 data register You can select rising or falling edges to trigger this operation Time
137. egister Low P4CONL EDH Set 1 Bank 1 R W P4 0 SEG16 P4 4 P4 2 SEG18 P4 3 SEG19 P4CONL bit pair pin configuration settings Input mode Input mode pull up Opendrain output mode Output mode push pull NOTE If LCD is enabled by LCON 4 SEG signal go out otherwise port 4 1 0 can be selected Figure 9 13 Port 4 Low Byte Control Register P4CONL ELECTRONICS 9 13 5 53 8245 8245 8249 8249 5 Port 5 is an 8 bit I O port with individually configurable pins Port 5 pins are accessed directly by writing or reading the port 5 data register P5 at location FBH in set 1 bank 0 P5 0 P5 7 can serve as inputs with without pull ups as output open drain or push pull And they can serve as segment pins for LCD also Port 5 Control Registers Port 5 has two 8 bit control registers for P5 4 P5 7 and PSCONL for 5 0 5 3 A reset clears the P5CONH and P5CONL registers to configuring all pins to input mode Port 5 Control Register High Byte PSCONH EEH Set 1 Bank 1 R W P5 4 SEG28 P5 NE P5 6 SEG30 P5 7 SEG31 P5CONH bit pair pin configuration settings Input mode Input mode pull up Opendrain output mode Output mode push pull NOTE If LCD is enabled by LCON 7 SEG signal go out otherwise port 5 1 0 can be selected Figure 9 14 Port 5 High Byte Control Register PSCONH 9 14 ELECTRONICS 53 8245 8245 8249 8249 PO
138. ement LDW dst src Load word POP dst Pop from stack POPUD dst src Pop user stack decrementing POPUI dst src Pop user stack incrementing PUSH SIC Push to stack PUSHUD dst src Push user stack decrementing PUSHUI dst src Push user stack incrementing 6 2 ELECTRONICS 53 8245 8245 8249 8249 INSTRUCTION SET Table 6 1 Instruction Group Summary Continued Mnemonic Operands Instruction Arithmetic Instructions ADC dst src Add with carry ADD dst src Add CP dst src Compare DA dst Decimal adjust DEC dst Decrement DECW dst Decrement word DIV dst src Divide INC dst Increment INCW dst Increment word MULT dst src Multiply SBC dst src Subtract with carry SUB dst src Subtract Logic Instructions AND dst src Logical AND COM dst Complement OR dst src Logical OR XOR dst src Logical exclusive OR ELECTRONICS 6 3 INSTRUCTION SET S3C8245 P8245 C8249 P8249 Table 6 1 Instruction Group Summary Continued Mnemonic Operands Instruction Program Control Instructions BTJRF dst src Bit test and jump relative on false BTJRT dst src Bit test and jump relative on true CALL dst Call procedure CPIJE dst src Compare increment and jump on equal CPIJNE dst src Compare increment and jump on non equal DJNZ r dst Decrement register and jump on non zero ENTER Enter EXIT Exit IRET Interrupt return JP cc dst Jump on condition code JP dst Jump unconditional JR cc dst Jump relative on condition code NEXT Next
139. emory ELECTRONICS 3 9 ADDRESSING MODES 53 8245 8245 8249 8249 DIRECT ADDRESS DA In Direct Address DA mode the instruction provides the operand s 16 bit memory address Jump JP and Call CALL instructions use this addressing mode to specify the 16 bit destination address that is loaded into the PC whenever a JP or CALL instruction is executed The LDC and LDE instructions can use Direct Address mode to specify the source or destination address for Load operations to program memory LDC or to external data memory LDE if implemented Program or Data Memory Memory Address Program Memory Used Upper Address Byte Lower Address Byte o or 1 4 LSB Selects Program OPCODE Memory or Data Memory 0 Program Memory 1 Data Memory Sample Instructions LDC R5 1234H The values in the program address 1234H are loaded into register R5 LDE R5 1234H Identical operation to LDC example except that external program memory is accessed Figure 3 10 Direct Addressing for Load Instructions 3 10 ELECTRONICS 53 8245 8245 8249 8249 ADDRESSING MODES DIRECT ADDRESS MODE Continued Program Memory Next OPCODE Address Used Memory Upper Address Byte Lower Address Byte OPCODE Sample Instructions JP C JOB1 Where JOB1 is a 16 bit immediate address CALL DISPLAY Where DISPLAY is a 16 bit immediate address Figure 3 11 Direct Addressing for Call and Jump Instruct
140. enable the timer 0 interrupt IRQ2 vector E6H you must write TOCON 2 and TOCON 1 to 1 To generate the exact time interval you should write TOCON 3 and 0 which cleared counter and interrupt pending bit To detect an interrupt pending condition when TOINT is disabled the application program polls pending bit 0 When a 1 is detected a timer 0 interrupt is pending When the TOINT sub routine has been serviced the pending condition must be cleared by software by writing a 0 to the timer 0 interrupt pending bit 0 Timer 0 Control Registers TOCON F1H Set 1 Bank 1 R W Timer 0 input clock selection bits Timer 0 interrupt pending bit 000 0 No interrupt pending 010 fxx 256 0 Clear pending bit when write 100 64 1 Interrupt is pending 110 fxx 8 fxx Timer 0 interrupt enable bit 0 Disable interrupt 1 Enable interrupt Not used Timer 0 count enable bit 0 Disable counting operation 1 Enable counting operation Timer 0 counter clear bit 0 No affect 1 Clear the timer 0 counter when write For normal operation TOCON 3 bit must be set 1 Figure 12 1 Timer 0 Control Register 12 2 ELECTRONICS 53 8245 8245 8249 8249 16 0 1 BLOCK DIAGRAM Bits 7 6 5 Data Bus 256 _ 16 bitup Counter HL fxx 64 Xx 6 Read Only 8 Pending 1 1 Counter clear signal TOCON
141. equence of events occurs during a reset operation All interrupt is disabled watchdog function basic timer is enabled Ports 0 3 and set to input mode Peripheral control and data register settings are disabled and reset to their default hardware values program counter is loaded with the program reset address in the ROM 0100H When the programmed oscillation stabilization time interval has elapsed the instruction stored in ROM location 0100H and 0101H is fetched and executed NORMAL MODE nRESET OPERATION In normal masked ROM mode the Test pin is tied to Vgs A reset enables access to the 16 Kbyte on chip ROM The external interface is not automatically configured NOTE To program the duration of the oscillation stabilization interval you make the appropriate settings to the basic timer control register BTCON before entering Stop mode Also if you do not want to use the basic timer watchdog function which causes a system reset if a basic timer counter overflow occurs you can disable it by writing 1010B to the upper nibble of BTCON ELECTRONICS 8 1 nRESET POWER DOWN S3C8245 P8245 C8249 P8249 HARDWARE nRESET VALUES Table 8 1 8 2 8 3 list the reset values for CPU and system registers peripheral control registers and peripheral data registers following a reset operation The following notation is used to represent reset values 1 0 shows the r
142. erval timer mode selects an input clock frequency of fxx 1024 and disables all timer 1 interrupts To disable the counter operation please set T1 CON 7 5 to 111B You can clear the timer 1 counter at any time during normal operation by writing a 1 to TICON 3 The timer 1 overflow interrupt T1OVF is interrupt level IRQ3 and has the vector address EAH When a timer 1 overflow interrupt occurs and is serviced interrupt IRQ3 vector EBH you must write T1CON 1 to 1 To generate the exact time interval you should write T1 CON by the CPU the pending condition is cleared automatically by hardware To enable the timer 1 match capture which clear counter and interrupt pending bit To detect a match capture or overflow interrupt pending condition when T1INT or T1OVF is disabled the application program should poll the pending bit When a 1 is detected a timer 1 match capture or overflow interrupt is pending When her sub routine has been serviced the pending condition must be cleared by software by writing a 0 to the interrupt pending bit Timer 1 Control Register T1 CON FBH Set 1 Bank 1 R W Timer 1 input clock selection bits el 1 interrupt enable 000 fxx 1024 Enable overflow interrupt 010 fxx 256 0 Disable overflow interrupt 100 fxx 64 110 8 Timer 1 match capture interrupt enable bit 001 fou1 0 Disable interrupt 011 External clock T1CLK falling edge 1 Enable interrupt 101 Externa
143. escription Block Diagram Chapter 18 Voltage Level Detector NITE Voltage Level Detector Control Register VLDCON 3C8245 P8245 C8249 P8249 MICROCONTROLLER Table of Contents Concluded Chapter 19 Electrical Data 19 1 Chapter 20 Mechanical Data E tose dentato payaka bac tind Sec soya Lab IE ce 20 1 Chapter 21 S3P8245 P8249 OTP S CN RENE TEE 21 1 Operating Mode 21 4 Chapter 22 Development Tools Gr ELS 22 1 SHINE ket idest tutae Q 22 1 SAMA ASSOIbDIGr 1i acer yer ERE ER EDU ER RE DEI 22 1 SASM88 u 22 1 en i nir LL t b uie tiyu eL 22 1 Target ccm 22 1 TB8245 8249 Target Boatd 22 3 SMDS2 Selection SAME 22 5 us EE 22 5 STOP LED c 22 5 x S3C8245 P8245 C8249 P8249 MICROCONTROLLER List of Figures Figure Title Page Number Number 1 1 S3C8245 C8249 Block Diagram 1 3 1 2 S3C8245 C8249 Pin Assignment 80 14
144. eset bit value as logic one or logic zero respectively means that the bit value is undefined after a reset dash means that the bit is either not used or not mapped but read 0 is the bit value Table 8 1 53 8245 8249 Set 1 Register and Values after nRESET Register Name Bit Values after nRESET LCD Control Register 208 LCD Mode Register 209 Interrupt Pending Register INTPND Basic Timer Control Register 21 Clock Control Register 212 System Flags Register FLAGS I gt om E E S On Register Pointer High Byte 214 N o Register Pointer Low Byte Stack Pointer High Byte IPH IPL SYM Jg g Stack Pointer Low Byte Y gt gt Instruction Pointer High Byte 00 I Instruction Pointer Low Byte Interrupt Request Register N O 1 System Mode Register 2 Register Page Pointer PP 223 Interrupt Mask Register molo N EE 22 22 H L 8 2 ELECTRONICS 53 8245 8245 8249 8249 nRESET POWER DOWN Table 8 2 S3C8245 C8249 Set 1 Bank 0 Register Values after nRESET E z N N IN mi rm 2 2 7 m mim O IN m Port 2 Control Low Register P2CONL 231 Port 3 Control High Registe
145. essing for interrupts with either type of pending condition clear function by hardware or by software Programming Guidelines Remember that the only way to enable disable a fast interrupt is to set clear the fast interrupt enable bit in the SYM register SYM 1 Executing El or DI instruction globally enables or disables all interrupt processing including fast interrupts If you use fast interrupts remember to load the IP with a new start address when the fast interrupt service routine ends ELECTRONICS 5 17 INTERRUPT STRUCTURE S3C8245 P8245 C8249 P8249 NOTES 5 18 ELECTRONICS 53 8245 8245 8249 8249 INSTRUCTION SET INSTRUCTION SET OVERVIEW The SAM8 instruction set is specifically designed to support the large register files that are typical of most SAM8 microcontrollers There are 78 instructions The powerful data manipulation capabilities and features of the instruction set include A full complement of 8 bit arithmetic and logic operations including multiply and divide special I O instructions I O control data registers are mapped directly into the register file Decimal adjustment included in binary coded decimal BCD operations 16 bit word data can be incremented and decremented Flexible instructions for bit addressing rotate and shift operations DATA TYPES The 8 CPU performs operations on bits bytes BCD digits and two byte words Bits in the register file can be
146. et to 1 if the result is logic zero Sign Flag FLAGS 5 Following arithmetic logic rotate or shift operations the sign bit identifies the state of the MSB of the result A logic zero indicates a positive number and a logic one indicates a negative number Overflow Flag FLAGS 4 The V flag is set to 1 when the result of a two s complement operation is greater than 127 or less than 128 It is also cleared to 0 following logic operations Decimal Adjust Flag FLAGS 3 The DA bit is used to specify what type of instruction was executed last during BCD operations so that a subsequent decimal adjust operation can execute correctly The DA bit is not usually accessed by programmers and cannot be used as a test condition Half Carry Flag FLAGS 2 The H bit is set to 1 whenever an addition generates a carry out of bit 3 or when a subtraction borrows out of bit 4 It is used by the Decimal Adjust DA instruction to convert the binary result of a previous addition or subtraction into the correct decimal BCD result The H flag is seldom accessed directly by a program Fast Interrupt Status Flag FLAGS 1 The FIS bit is set during a fast interrupt cycle and reset during the IRET following interrupt servicing When set it inhibits all interrupts and causes the fast interrupt return to be executed when the IRET instruction is executed Bank Address Flag FLAGS 0 The BA flag indicates which register bank in the set 1 a
147. ficant bit position bit 7 was 1 Z Setif the result is 0 cleared otherwise S Setif the result bit 7 is set cleared otherwise V Setif arithmetic overflow occurred that is if the sign of the destination changed during rotation cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 10 R 4 11 IR Given Register register 01H 02H and register 02H 17H C 0 RLC 00H gt Register OOH 54H C 1 RLC 01H gt Register 01H 02H register 02H 2EH In the first example if general register 00H has the value 10101010B the statement RLC 00H rotates OAAH one bit position to the left The initial value of bit 7 sets the carry flag and the initial value of the C flag replaces bit zero of register OOH leaving the value 55H 01010101B The MSB of register OOH resets the carry flag to 1 and sets the overflow flag ELECTRONICS 6 73 INSTRUCTION SET S3C8245 P8245 C8249 P8249 RR Rotate Right RR Operation dst C lt dst 0 dst 7 lt dst 0 dst dst n 1 n 0 6 The contents of the destination operand are rotated right one bit position The initial value of bit zero LSB is moved to bit 7 MSB and also replaces the carry flag C Flags Format Examples 6 74 C Set if the bit rotated from the least significant bit position bit zero was 1 Z Set if the result is 0 cleared otherw
148. file Using the register pointers RP0 and RP1 you can select two 8 byte register slices at one time as active working register space After a reset RP0 points to address C0H in register set 1 selecting the 8 byte working register slice COH C7H 2 0 Not used for the S3C8245 C8249 Register Pointer 1 D7H Set1 nRESET Value 1 1 0 0 1 Read Write R W R W R W R W R W _ _ _ Addressing Mode Register addressing only 7 3 Register Pointer 1 Address Value Register pointer 1 can independently point to one of the 256 byte working register areas in the register file Using the register pointers RP0 and RP1 you can select two 8 byte register slices at one time as active working register space After a reset RP1 points to address C8H in register set 1 selecting the 8 byte working register slice C8H CFH 2 0 Not used for the S3C8245 C8249 4 34 ELECTRONICS 53 8245 8245 8249 8249 CONTROL REGISTER SIOCON sio control Register FOH Set 1 Bank 0 Bit Identifier 5 3 2 o 1 0 0 0 0 0 0 0 nRESET Value Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 SIO Shift Clock Selection Bit Internal clock P S clock 1 External clock SCK 6 Data Direction Control Bit MSB first mode LSB first mode BB 5 SIO Mode Selection Bit Receive only mode 1 Transmit receive mode 4 Shift Edge Selection Tx at falling edges Rx at ri
149. gh byte When you select output mode a push pull circuit is automatically configured In input mode three different selections are available Schmitt trigger input with interrupt generation on falling signal edges Schmitt trigger input with interrupt generation on rising signal edges Schmitt trigger input with interrupt generation on falling rising signal edges Port 0 Interrupt Enable and Pending Registers POINT POPND To process external interrupts at the port 0 pins two additional control registers are provided the port 0 interrupt enable register POINT E2H set 1 bank 0 and the port 0 interrupt pending register POPND E3H set 1 bank 0 The port 0 interrupt pending register POPND lets you check for interrupt pending conditions and clear the pending condition when the interrupt service routine has been initiated The application program detects interrupt requests by polling the POPND register at regular intervals When the interrupt enable bit of any port 0 pin is 1 a rising or falling signal edge at that pin will generate an interrupt request The corresponding POPND bit is then automatically set to 1 and the IRQ level goes low to signal the CPU that an interrupt request is waiting When the CPU acknowledges the interrupt request application software must the clear the pending condition by writing a 0 to the corresponding POPND bit ELECTRONICS 9 3 5 53 8245 8245 8249
150. guous 16 Byte Working Register 2 10 2 8 16 Bit Fiegister Pair toon exon eim o d use cages 2 11 2 9 Register File 1 200000 ener 2 12 2 10 Common Working Register 2 13 2 11 4 Bit Working Register ee 2 15 2 12 4 Bit Working Register Addressing 2 15 2 13 8 Bit Working Register 2 16 2 14 8 Bit Working Register Addressing Example see 2 17 2 15 stack Operations EO tene aa 2 18 3 1 Register Addressing peta zee I MN 3 2 3 2 Working Register Addressing 3 2 3 3 Indirect Register Addressing to Register 2 11 3 3 3 4 Indirect Register Addressing to Program Memory 3 4 3 5 Indirect Working Register Addressing to Register 3 5 3 6 Indirect Working Register Addressing to Program or Data 3 6 3 7 Indexed Addressing to Register 3 7 3 8 Indexed Addressing to Program or Data Memory with Short Offset 3 8 3 9 Indexed Addressing t
151. h byte Timer B data register low byte Timer B control register Timer A control register Timer A counter register Timer A data register Serial I O control register Serial I O data register Serial pre scale register Oscillator control register STOP control register Port 1 pull up control register Port 0 data register Port 1 data register Port 2 data register Port 3 data register Port 4 data register Port 5 data register Basic timer data register External memory timing register Interrupt priority register 4 2 POCONH POCONL P P2 P3 P4 Table 4 2 Set 1 Bank 0 Registers 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 22 22 22 3 3 3 3 3 3 3 3 3 3 4 4 4 4 24 24 24 4 4 4 4 5 6 27 28 29 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 247 248 249 250 51 S3C8245 P8245 C8249 P8249 nw Location FCH is factory use only 254 255 ELECTRONI S 53 8245 8245 8249 8249 CONTROL REGISTER Table 4 3 Set 1 Bank 1 Registers 236 Locations F0H is factory use only ister Timer 0 data register low byte TODATAL ister ELECTRONI S 4 3 CONTROL REGISTERS 53 8245 8245 8249 8249 Bit number s that is are appended to Name of individual the register name for bit addressing bit or related bits Register location Register address the internal Register ID Full Register name hexadecimal register file FLAGS
152. he internal register file Of these 1 040 are for general purpose This number includes a 16 byte working register common area used as a scratch area for data operations four 192 byte prime register areas and four 64 byte areas Set 2 Thirteen 8 bit registers are used for the CPU and the system control and 53 registers are mapped for peripheral controls and data registers Twelve register locations are not mapped ELECTRONICS 2 1 ADDRESS SPACES 53 8245 8245 8249 8249 PROGRAM MEMORY ROM Program memory ROM stores program codes or table data The S3C8249 has 32K bytes internal mask programmable program memory the S3C8245 has 16K bytes The first 256 bytes of the ROM are reserved for interrupt vector addresses Unused locations in this address range can be used as normal program memory If you use the vector address area to store a program code be carelul not to overwrite the vector addresses stored in these locations The ROM address at which a program execution starts after a reset is 0100H Decimal HEX 32 767 7FFFH S3C8249 32K byte 4000H S3C8245 16K byte Interrupt Vector Area Figure 2 1 Program Memory Address Space 2 2 ELECTRONICS 53 8245 8245 8249 8249 ADDRESS 5 5 REGISTER ARCHITECTURE In the S3C8245 C8249 implementation the upper 64 byte area of register files is expanded two 64 byte areas called set 1 and set 2 The upper 32 byte are
153. he value 0120H ELECTRONICS 6 47 INSTRUCTION SET S3C8245 P8245 C8249 P8249 JR Jump Relative JR Operation Flags Format Example 6 48 cc dst If istrue PC dst If the condition specified by the condition code cc is true the relative address is added to the program counter and control passes to the statement whose address is now in the program counter otherwise the instruction following the JR instruction is executed See list of condition codes The range of the relative address is 127 128 and the original value of the program counter is taken to be the address of the first instruction byte following the JR statement No flags are affected Bytes Cycles Opcode Addr Mode 1 Hex dst dst 2 6 ccB RA cc 20 to F NOTE the first byte of the two byte instruction format the condition code and the opcode are each four bits Given The carry flag 1 and LABEL X 1FF7H JR C LABEL X 1FF7H If the carry flag is set that is if the condition code is true the statement JR C LABEL X will pass control to the statement whose address is now in the PC Otherwise the program instruction following the JR would be executed ELECTRONICS 53 8245 8245 8249 8249 INSTRUCTION SET L D Load LD dst src Operation dst lt src The contents of the source are loaded into the destination The source s contents are unaffected Flags No flags are affected F
154. ically ORed with the destination operand and the result is stored in the destination The contents of the source are unaffected The OR operation results in a 1 being stored whenever either of the corresponding bits in the two operands is a 1 otherwise a 0 is stored C Unaffected Z Setif the result is 0 cleared otherwise S Setif the result bit 7 is set cleared otherwise V Always cleared to O D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src 6 43 r Ir opc src dst 3 6 44 R R 45 R IR opc dst src 3 6 46 R IM Given RO 15H R1 2AH R2 01H register 08H register 01H 37H and register 08H 8AH OR RO R1 gt RO 3FH R1 2AH OR RO R2 gt RO 37H R2 01H register 01H 37H OR 00H 01H gt Register 00H register 01H 37H OR 01H 00H gt Register OOH 08H register 01H OBFH OR 00H 02H gt Register 00H In the first example if working register RO contains the value 15H and register R1 the value 2 the statement OR RO R1 logical ORs the RO and R1 register contents and stores the result in destination register RO The other examples show the use of the logical OR instruction with the various addressing modes and formats ELECTRONICS 6 63 INSTRUCTION SET S3C8245 P8245 C8249 P8249 POP Pop From Stack POP Operation Flags Format Examples 6 64 dst dst lt GSP SP lt SP 1 The contents of the location
155. ich is then ANDed with the source mask The zero Z flag can then be checked to determine the result The destination and source operands are unaffected Unaffected Z Setif the result is 0 cleared otherwise S Setif the result bit 7 is set cleared otherwise V Always cleared to O D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src 6 63 r Ir opc src dst 3 6 64 R R 65 R IR opc dst src 3 6 66 R IM Given RO 0C7H R1 02H R2 12H register OOH 2BH register 01 02H and register 02 23H TOM RORI RO OC7H Ri 02H Z 1 TCM R0 R1 gt RO OC7H 02H register 02H 23H 2 TCM 00H 01H 9 Register 2BH register 01H 02H Z 1 TOM 00H 01H gt Register OOH 2BH register 01H 02H register 02H 23H 2 1 00H 34 9 Register 00H 2BH Z 0 In the first example if working register RO contains the value 0C7H 11000111B and register R1 the value 02H 00000010B the statement TCM RO0 R1 tests bit one in the destination register for 1 value Because the mask value corresponds to the test bit the Z flag is set to logic one and can be tested to determine the result of the TCM operation ELECTRONICS 6 85 INSTRUCTION SET S3C8245 P8245 C8249 P8249 TM Test Under Mask TM Operation Flags Format Examples 6 86 dst src dst AND src This instruction tests selected bits in the destination operand for a logic zer
156. igure 2 15 Stack Operations User Defined Stacks You can freely define stacks in the internal register file as data storage locations The instructions PUSHUI PUSHUD POPUI and POPUD support user defined stack operations Stack Pointers SPL SPH Register locations D8H and D9H contain the 16 bit stack pointer SP that is used for system stack operations The most significant byte of the SP address SP15 SP8 is stored in the SPH register D8H and the least significant byte SP7 SP0 is stored in the SPL register After a reset the SP value is undetermined Because only internal memory space is implemented in the S3C8245 C8249 the SPL must be initialized to an 8 bit value in the range 0 The SPH register is not needed and can be used as a general purpose register if necessary When the SPL register contains the only stack pointer value that is when it points to a system stack in the register file you can use the SPH register as a general purpose data register However if an overflow or underflow condition occurs as a result of increasing or decreasing the stack address value in the SPL register during normal stack operations the value in the SPL register will overflow or underflow to the SPH register overwriting any other data that is currently stored there To avoid overwriting data in the SPH register you can initialize the SPL value to FFH instead of 00H 2 18 ELECTRONICS 53 8245 8245 8249
157. in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes This publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of Samsung or others Samsung makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation any consequential or incidental damages Typical parameters can and do vary in different applications All operating parameters including Typicals must be validated for each customer application by the customer s technical experts Samsung products are not designed intended or authorized for use as components in systems intended for surgical implant into the body for other applications intended to support or sustain life or for any other application in which the failure of the Samsung product could create a situation where personal injury or death may occur Should the Buyer purchase or use a Samsung product for any such unintended or unauthorized application the Buyer shall indemnify and hold Samsung and its officers employees subsidiaries affiliates and distributors harmless against al
158. ing mode only 7 5 Not used for the S3C8245 C8249 4 Sub system Oscillator Driving Ability Control Bit Strong driving ability 1 Normal driving ability 3 Main System Oscillator Control Bit Main System Oscillator RUN Main System Oscillator STOP 1 2 Sub System Oscillator Control Sub system oscillator RUN je Sub system oscillator STOP Not used for the S3C8245 C8249 0 System Clock Selection Bit Main oscillator select Subsystem oscillator select NOTE When OSCCONA is set to 0 Sub operating current and sub idle current are large ELECTRONICS 4 1 N CONTROL REGISTERS 53 8245 8245 8249 8249 POCONH Port 0 control Register High Byte EOH Setl Bank 0 nRESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P0 7 INT7 Schmitt trigger input mode pull up interrupt on falling edge 1 Schmitt trigger input mode interrupt rising edge oo Schmitt trigger input mode interrupt on rising or falling edge Output mode push pull 5 4 P0 6 INT6 olo Schmitt trigger input mode pull up interrupt on falling edge 1 Schmitt trigger input mode interrupt rising edge Schmitt trigger input mode interrupt rising falling edge Output mode push pull 3 2 P0 5 INT5 Schmitt trigger input mode pull up interrupt on falling edge Schmitt t
159. ins AVss is internally connected to Vgg FUNCTION DESCRIPTION To initiate an analog to digital conversion procedure at the first you must set ADCEN signal for ADC input enable at port 2 the pin set with 1 can be used for ADC analog input And you write the channel selection data in the A D converter control register ADCON 4 7 to select one of the eight analog input pins ADCO 7 and set the conversion start or enable bit 0 The read write ADCON register is located in set 1 bank 0 at address F3H The pins witch are not used for ADC can be used for normal I O During a normal conversion ADC logic initially sets the successive approximation register to 200H the approximate half way point of an 10 bit register This register is then updated automatically during each conversion step The successive approximation block performs 10 bit conversions for one input channel at a time You can dynamically select different channels by manipulating the channel selection bit value ADCON 6 4 in the ADCON register To start the A D conversion you should set the enable bit ADCON 0 When a conversion is completed ADCON 3 the end of conversion EOC bit is automatically set to 1 and the result is dumped into the ADDATAH L register where it can be read The A D converter then enters an idle state Remember to read the contents of ADDATAH L before another conversion starts Otherwise the previous result will be overwritten by the next conversion resul
160. ion is performed Set if there is a carry from the most significant bit of the result cleared otherwise Set if the result is 0 cleared otherwise Set if the result is negative cleared otherwise lt N O is of the opposite sign cleared otherwise Always cleared to 0 Set if a carry from the low order nibble occurred TO Set if arithmetic overflow occurred that is if both operands are of the same sign and the result Bytes Cycles Opcode Addr Mode Hex dst 6 03 r src dst 3 6 04 R 05 R dst src 3 6 06 R Given R1 12H R2 register 01H 21H register 02H register OAH ADD R1 R2 gt R1 15H R2 03H ADD R1 R2 gt R1 1CH R2 08H ADD 01H 02H gt Register 01H 24H register 02H ADD 01H 02H gt Register 01H 2BH register 02H ADD 01H 25H gt Register 01H 46H src r Ir In the first example destination working register R1 contains 12H and the source working register R2 contains 03H The statement ADD R1 R2 adds 03H to 12H leaving the value 15H in register R1 ELECTRONICS INSTRUCTION SET S3C8245 P8245 C8249 P8249 AND Logical AND AND Operation Flags Format Examples dst src dst dst AND src The source operand is logically ANDed with the destination operand The result is stored in the destination The AND operation results in a 1 bit being stored whenever the corresponding bits in the two
161. ions ELECTRONICS 3 11 ADDRESSING MODES 53 8245 8245 8249 8249 INDIRECT ADDRESS IA In Indirect Address 1 mode the instruction specifies an address located in the lowest 256 bytes of the program memory The selected pair of memory locations contains the actual address of the next instruction to be executed Only the CALL instruction can use the Indirect Address mode Because the Indirect Address mode assumes that the operand is located in the lowest 256 bytes of program memory only an 8 bit address is supplied in the instruction the upper bytes of the destination address are assumed to be all zeros Program Memory lt Next Instruction LSB Must be Zero dst Current Instruction OPCODE Lower Address Byte Program Memory Upper Address Byte Locations 0 255 Sample Instruction CALL 40H The 16 bit value in program memory addresses 40H and 41H is the subroutine start address Figure 3 12 Indirect Addressing 3 12 ELECTRONICS 53 8245 8245 8249 8249 RELATIVE ADDRESS MODE ADDRESSING MODES In Relative Address RA mode a twos complement signed displacement between 128 and 127 is specified in the instruction The displacement value is then added to the current PC value The result is the address of the next instruction to be executed Before this addition occurs the PC contains the address of the instruction immediately following the current instruction Several
162. ise S Set if the result bit 7 is set cleared otherwise V Set if arithmetic overflow occurred that is if the sign of the destination changed during rotation cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst 2 4 0 R E1 IR Given Register OOH register 01 02H and register 02H 17H RR 00H gt Register 00H 98H C 1 RR 01H gt Register 01H 02H register 02H 8BH C 1 In the first example if general register 00H contains the value 31H 00110001B the statement RR 00H rotates this value one bit position to the right The initial value of bit zero is moved to bit 7 leaving the new value 98H 10011000B in the destination register The initial bit zero also resets the C flag to 1 and the sign flag and overflow flag are also set to 1 ELECTRONICS 53 8245 8245 8249 8249 INSTRUCTION SET RRC Rotate Right Through Carry RRC Operation dst dst 7 lt dst 0 dst n dst n 1 n 0 6 The contents of the destination operand and the carry flag are rotated right one bit position The initial value of bit zero LSB replaces the carry flag the initial value of the carry flag replaces bit 7 MSB Flags Format Examples Set if the bit rotated from the least significant bit position bit zero was 1 Z Setif the result is 0 cleared otherwise S Setif the result bit 7 is set cleared otherw
163. ise V Setif arithmetic overflow occurred that is if the sign of the destination changed during rotation cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst Opc dst 2 4 CO R C1 IR Given Register 55H register 01H 02H register 02H 17H and C 0 RRC 00H gt Register OOH 2AH C 1 RRC 01H gt Register 01H 02H register 02H OBH C 1 In the first example if general register OOH contains the value 55H 01010101 the statement RRC rotates this value one bit position to the right The initial value of bit zero 1 replaces the carry flag and the initial value of the C flag 1 replaces bit 7 This leaves the new value 2AH 00101010 in destination register OOH The sign flag and overflow flag are both cleared to 0 ELECTRONICS 6 75 INSTRUCTION SET S3C8245 P8245 C8249 P8249 SB0 Select Bank 0 SB0 Operation BANK lt 0 The SBO instruction clears the bank address flag in the FLAGS register FLAGS 0 to logic zero selecting bank 0 register addressing in the set 1 area of the register file Flags No flags are affected Format Bytes Cycles Opcode Hex 1 4 4 statement SBO clears FLAGS 0 to 0 selecting bank 0 register addressing 6 76 ELECTRONICS 53 8245 8245 8249 8249 INSTRUCTION SET SB1 Select Bank 1 SB1 Operation BANK lt 1 The SB1 instruction sets the bank address flag
164. it one of the FLAGS register OD5H is cleared 0 If a fast interrupt occurred IRET clears the FIS bit that was set at the beginning of the service routine All flags are restored to their original settings that is the settings before the interrupt occurred IRET Bytes Cycles Opcode Hex Normal Opc 1 10 internal stack BF 12 internal stack IRET Bytes Cycles Opcode Hex Fast 1 6 In the figure below the instruction pointer is initially loaded with 100H in the main program before interrupts are enabled When an interrupt occurs the program counter and instruction pointer are swapped This causes the PC to jump to address 100 and the to keep the return address last instruction in the service routine normally is a jump to IRET at address FFH This causes the instruction pointer to be loaded with 100H again and the program counter to jump back to the main program Now the next interrupt can occur and the P is still correct at 100H OH FFH 100H Interrupt Service Routine JP to FFH FFFFH In the fast interrupt example above if the last instruction is not a jump to IRET you must pay attention to the order of the last two instructions The IRET cannot be immediately proceeded by a clearing of the interrupt status as with a reset of the IPR register ELECTRONICS 53 8245 8245 8249 8249 INSTRUCTION SET JP Jump JP JP Operation Flags Format 1 Examples
165. l claims costs damages expenses and reasonable attorney fees arising out of either directly or indirectly any claim of personal injury or death that may be associated with such unintended or unauthorized use even if such claim alleges that Samsung was negligent regarding the design or manufacture of said product 3C8245 P8245 C8249 P8249 8 Bit CMOS Microcontrollers User s Manual Revision 4 Publication Number 24 S3 C8245 P8245 C8249 P8249 032004 2004 Samsung Electronics All rights reserved No part of this publication may be reproduced stored in a retrieval system or transmitted in any form or by any means electric or mechanical by photocopying recording or otherwise without the prior written consent of Samsung Electronics objectives Samsung Electronics microcontroller business has been awarded full ISO 14001 certification BSI Certificate No FM24653 All semiconductor products are designed and manufactured in accordance with the highest quality standards and Samsung Electronics Co Ltd San 24 Nongseo Dong Giheung Gu Yongin City Gyeonggi Do Korea C P O Box 37 Suwon 446 711 TEL 82 31 209 5238 FAX 82 31 209 6494 Home Page URL Http Awww samsungsemi com Printed in the Republic of Korea Preface The S3C8245 P8245 C8249 P8249 Microcontroller User s Manual is designed for application designers and programmers who are using the S3C8245 P8245 C8249 P8249 microcontroller fo
166. l clock T1CLK rising edge 111 Counter stop Timer 1 counter clear bit 0 No effect 1 Clear the timer 1 counter when write Timer 1 operating mode selection bits 00 Interval mode 01 Capture mode capture on rising edge counter running OVF can occur 10 Capture mode capture on falling edge counter running OVF can occur 11 PWM mode OVF amp match interrupt can occur Figure 12 5 Timer 1 Control Register T1CON ELECTRONICS 12 7 16 0 1 53 8245 8245 8249 8249 BLOCK DIAGRAM T1CON 0 T1CON 7 5 Data Bus 1024 _ 256 64 8 fxx 1 gt 0 Vss T1CON 4 3 T1CON 4 3 Counter Clear Signal or Match Timer 1 Data H L Register Data Bus Pending bit is located at INTPND register NOTES 1 16 bit PWM frequency Where 10 MHz clock is used and fxx 8 is selected PWM frequency 1 8 10 MHz x FFFFh 19 07 Hz 2 Timer 1 input clock must be slower than CPU clock Figure 12 6 Timer 1 Functional Block Diagram 12 8 ELECTRONICS 53 8245 8245 8249 8249 16 0 1 1 Counter Register FCH Set 1 Bank 1 R Reset Value 00H Timer 1 Counter Register Low Byte T1CNTL FDH Set 1 Bank 1 R Reset Value 00H Figure 12 7 Timer 1 Control Register T1 CNTH L Timer 1 Data Register High Byte T1D
167. locks can issue interrupt requests In other words peripheral and operations interrupt driven There are eight possible interrupt levels IRQO IRQ7 also called level 0 level 7 Each interrupt level directly corresponds to an interrupt request number IRQn The total number of interrupt levels used in the interrupt structure varies from device to device 53 8245 8249 interrupt structure recognizes eight interrupt levels The interrupt level numbers 0 through 7 do not necessarily indicate the relative priority of the levels They are just identifiers for the interrupt levels that are recognized by the CPU The relative priority of different interrupt levels is determined by settings in the interrupt priority register IPR Interrupt group and subgroup logic controlled by IPR settings lets you define more complex priority relationships between different levels Vectors Each interrupt level can have one or more interrupt vectors or it may have no vector address assigned at all The maximum number of vectors that can be supported for a given level is 128 The actual number of vectors used for S3C8 series devices is always much smaller If an interrupt level has more than one vector address the vector priorities set in hardware S3C8245 C8249 uses sixteen vectors Sources A source is any peripheral that generates an interrupt A source can be an external pin or a counter overflow Each vector can have several interrupt
168. lphabetical order according to register mnemonic More detailed information about control registers is presented in the context of the specific peripheral hardware descriptions in Part II of this manual Data and counter registers are not described in detail in this reference chapter More information about all of the registers used by a specific peripheral is presented in the corresponding peripheral descriptions in Part II of this manual The locations and read write characteristics of all mapped registers in the S8C8245 C8249 register file are listed in Table 4 1 The hardware reset value for each mapped register is described in Chapter 8 RESET and Power Down Table 4 1 Set 1 Registers Basic timer control register R W Clock control register D4H R W System flags register D5H R W Register pointer 0 R W Register pointer 1 R W Stack pointer high byte Stack pointer low byte Instruction pointer high byte Instruction pointer low byte Interrupt request register Interrupt mask register System mode register Register page pointer ELECTRONICS 4 1 CONTROL REGISTERS Register Name Port 0 control High register Port 0 control Low register Port 0 interrupt control register Port 0 interrupt pending register Port 1 control High register Port 1 control Low register Port 2 control High register Port 2 control Low register Port 3 control High register Port 3 control Low register Timer B data register hig
169. must be changed to address other pages After a reset the page pointer s source value lower nibble and the destination value upper nibble are always 0000 automatically selecting page 0 as the source and destination page for register addressing Register Page Pointer PP DFH Set 1 R W we gt 5 Destination register page selection bits Source register page selection bits 0000 Destination Page 0 0000 Source Page 0 NOTE A hardware reset operation writes the 4 bit destination and source values shown above to the register page pointer These values should be modified to address other pages Figure 2 3 Register Page Pointer PP PROGRAMMING TIP Using the Page Pointer for RAM clear Page 0 Page 1 LD PP 00H Destination lt 0 Source 0 SRP 0COH LD RO 0FFH Page 0 RAM clear starts RAMCLO CLR RO DJNZ RO RAMCLO CLR RO RO 00H LD 10 Destination 1 Source 0 LD RO 0FFH Page 1 RAM clear starts RAMCL1 CLR RO DJNZ RO RAMCL1 CLR RO RO 00H NOTE You should refer to page 6 39 and use DJNZ instruction properly when DJNZ instruction is used in your program ELECTRONICS 2 5 ADDRESS SPACES 53 8245 8245 8249 8249 REGISTER SET 1 The term set 1 refers to the upper 64 bytes of the register file locations The upper 32 byte area of this 64 byte space is expanded two 32 byte register banks bank 0 and bank 1 The set regi
170. n case of S3C8245 the characteristic of and Vo is differ with the characteristic of S3C8249 like as following Other characteristics are same each other Table 19 3 D C Electrical Characteristics of S3C8245 TA 25 C to 85 C Vpp 1 8 V to LET Symbol L l Conditions Output high voltage Vout Vpp 5 V loH 1 mA 0 All output pins except Vor Port 3 0 odi in S3C8245 Output low voltage Vou Vpp 5 V 2 mA All output except d Voie Vpp 5 V lou 12 mA Port 3 0 only 5368245 ELECTRONICS 19 5 ELECTRICAL DATA S3C8245 P8245 C8249 P8249 Table 19 4 A C Electrical Characteristics TA 25 C to 85 C Vpp 1 8 V to 5 5 V Interrupt input tINTH 0 0 0 7 Vpp 5 V high low width tINTL P0 0 P0 7 nRESET input low width NOTE User must keep more large value then min value Figure 19 1 Input Timing for External Interrupts Ports 0 nRESET Figure 19 2 Input Timing for nRESET 19 6 ELECTRONICS 53 8245 8245 8249 8249 ELECTRICAL DATA Table 19 5 Input Output Capacitance TA 25 C to 85 C OV Input CN f 1 MHz unmeasured pins capacitance are returned to Vac Output capacitance capacitance Table 19 6 Data Retention Supply Voltage in Stop Mode TA 25 C to 85 Data retention VbppR 2 supply voltage Data retention InppR VpppR 2V supply current nRESET Occurs Oscillation Y Stabili
171. nd is adjusted to form two 4 bit BCD digits following an addition or subtraction operation For addition ADD ADC or subtraction SUB SBC the following table indicates the operation performed The operation is undefined if the destination operand was not the result of a H Flag Before DA O O O O O Bits 0 3 Value Hex 0 9 A F 0 3 0 9 A F 0 3 0 9 A F 0 3 0 9 6 F 0 9 6 F Number Added to Byte 00 06 06 60 66 66 60 66 66 00 00 06 AO 60 9 66 After DA 0 O O Set if there was a carry from the most significant bit cleared otherwise see table 7 S Setif result bit 7 is set cleared otherwise V D H DA dst Operation dst DA dst valid addition or subtraction of BCD digits Instruction Carry Bits 4 7 Before DA Value Hex 0 0 9 0 0 8 0 0 9 ADD 0 A F ADC 0 9 0 A F 1 0 2 1 0 2 1 0 3 0 0 9 SUB 0 0 8 SBC 1 7 1 6 Flags Set if result is 0 cleared otherwise Undefined Unaffected Unaffected Format ELECTRONICS dst Bytes Cycles Opcode Hex 40 41 Addr Mode dst R IR 6 33 INSTRUCTION SET S3C8245 P8245 C8249 P8249 DA Decimal Adjust DA Example 6 34 Continued Given Working register RO contains the value 15 BCD working register R1 contains 27 BCD and address 27H contains 46 BCD ADD R1 RO
172. net et edt ed Det Mick edt 3 13 hu usetcRueSlmee R m 3 14 3C8245 P8245 C8249 P8249 MICROCONTROLLER Chapter 4 Control Registers cae ba Sah 4 1 Chapter 5 Interrupt Structure Sa TI EE 5 1 Interrupt Ty POS LE 5 2 S3C8245 C8249 Interrupt 5 3 interrupt enini crecen ta claw Hoe dave tee Stee dc Oo va hee olive dle dee aly 5 4 Enable Disable Interrupt Instructions El 5 6 System Level Interrupt Control Registers 5 6 Interrupt Processing Control 5 7 Peripheral Interrupt Control Registers 5 8 System Mode Register 5 10 5 9 Interrupt Mask Register 2 2 nennen nnne nens 5 10 Interrupt Priority Register 5 11 Interrupt Request Register IRQ a ev So ede ecouter ew ao MN aO Ta ee OU Yea da Ode 5 13 Interrupt Pending Function Hee hene hh nene 5 14 Interrupt Source Polling Sequence ann nne nnn nennen nnn nnn 5 15 Interrupt Service
173. nning occur PWM mode OVF amp match interrupt can occur 2 1 Counter Enable 3 No effect 1 Clear the timer 1 counter when write 4 Timer 1 Match Capture Interrupt Enable Bit Disable interrupt 1 Enable interrupt 0 1 Overflow Interrupt Enable Disable overflow interrupt E 1 Enable overflow interrupt 4 40 53 8245 8245 8249 8249 CONTROL REGISTER rimer A Control Register EDH Set 1 Bank 0 Bit Identifier nRESET Value Read Write Addressing Mode 7 6 ELECTRONI S S 5 4 3 2 a o 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W Register addressing mode only Timer A Input Clock Selection Bits opopo Operating Mode Selection Internal mode TAOUT mode Capture mode capture rising edge counter running occur Capture mode capture falling edge counter running can occur PWM mode OVF interrupt can occur Timer A Counter Clear Bit 3 No effect 1 Clear the timer A counter when write Ti 3 er A Overflow Interrupt Enable Bit Disable overflow interrupt 1 Enable overflow interrupt Timer A Match Capture Interrupt Enable Bit EW Disable interrupt EN 1 Enable interrupt Timer A Match Capture Interrupt Pending Bit No interrupt pending Clear pending bit write Interrupt is pending
174. nput mode ADC or external reference voltage input are also available Port 2 Control Registers Two 8 bit control registers are used to configure port 2 pins 2 E7H set 1 Bank 0 for pins P2 0 P2 3 and P2CONH E6H set 1 Bank 0 for pins P2 4 P2 7 Each byte contains four bit pairs and each bit pair configures one port 2 pin The 2 and the P2CONL registers also control the alternative functions Port 2 Control Register High Byte 2 E6H Set 1 Bank 0 R W T P2 4 Wa P2 5 ADC5 P2 6 ADC6 2 bit pair configuration Input mode Output mode pull up Alternative function ADC amp VLD External input ENABLE ADCEN signal Gen Output mode push pull If a pin is enabled for ADC mode by ADCEN or ADC amp VLD ENABLE signal normal I O and pull up resistance are disabled When pins are enabled for ADC mode the pins can be selected for ADC input by ADCON 6 5 4 And the P2 7 can be used for VLD external input Figure 9 8 Port 2 High Byte Control Register P2CONH 9 8 ELECTRONICS 53 8245 8245 8249 8249 PORTS Port 2 Control Register Low Byte P2CONL E7H Set 1 Bank 0 R W P2 0 ADCO P2 1 NN P2 2 ADC2 P2 3 ADC3 P2CONL bit pair pin configuration Input mode Input mode pull up Alternative function ADC mode Output mode push pull If a pin is enabled for ADC mode by ADCEN normal I O pull up resistance are disabled
175. nstruction Descriptions Full Register Name N Logical AND Y L eene eee Honda IUE BELAND i eee eau ES Bit Compleient Ave cep eae e UE EU CERE M BIL OSC c cort o Et ttt ur eut demde tree de x tide d uL Bit Test Jump Relative on Bit Test Jump Relative on BIEXOB CR aane eum Ge I a Raa Gall ProcedUre soot eei us e Ee SRI eee eee etc eee 2 redde reae retta E deett oria Suri on Compare Increment and Jump on Compare Increment and Jump on Non Equal see Decimal ePi cS Bern c IE Decrement Word a u Eee ua EE iq ERE DP Mere RE PG MR a Disable Intert pts et ri ot E teu eub e ete Divide Urisigned io Decrement and Jump if 2 0 INCREMENT Iricremernt MOrd c ua suqasqata 53 8245 8245 8249 8249 MICROCONTROLLER umber xxi Instruction Mnemonic LDC LDE LDCD LDED LDCI LDEI LDCPD LDEPD LDCPI LDEPI LDW MULT NEXT NOP
176. nter information El s Q Interrupt Request Register Read only nRESET R IRQ0 IRQ7 Interrupts Interrupt Priority Vector Register Interrupt Cycle Interrupt Mask Register Global Interrupt Control El or SYM 0 manipulation Figure 5 4 Interrupt Function Diagram ELECTRONICS 5 7 INTERRUPT STRUCTURE S3C8245 P8245 C8249 P8249 PERIPHERAL INTERRUPT CONTROL REGISTERS For each interrupt source there is one or more corresponding peripheral control registers that let you control the interrupt generated by the related peripheral see Table 5 3 Table 5 3 Interrupt Source Control and Data Registers Interrupt Source Interrupt Level Register s Location s in Set 1 Timer A overflow TACON EDH bank 0 Timer A match capture TACINT EEH bank 0 TADATA EFH bank 0 TBCON ECH bank 0 TBDATAH TBDATAL EAH EBH bank 0 TOCON TOCNTH F1H F2H bank 1 TOCNTL TODATAH bank 1 TODATAL F5H bank 1 T1CON FBH bank 1 Timer B match Timer 0 match Timer 1 overflow Timer 1 match capture T1CNTH FCH bank 1 TICNTL FDH bank 1 T1DATAH FEH bank 1 T1DATAL FFH bank 1 SIO interrupt IRQ4 SIOCON FOH bank 0 SIODATA F1H bank 0 SIOPS F2H bank 0 Watch timer overflow IRQ5 WTCON FAH bank 1 P0 3 external interrupt IRQ6 POCONL E1H bank 0 0 2 external interrupt POINT E2H bank 0 P0 1 external interrupt POPND E3H bank 0 P0 0 external interrupt P0
177. nter value you load a new value to RPO and or RP1 using an SRP or LD instruction see Figures 2 6 and 2 7 With working register addressing you can only access those two 8 bit slices of the register file that are currently pointed to by RPO and RP1 You cannot however use the register pointers to select a working register space in set 2 COH FFH because these locations can be accessed only using the Indirect Register or Indexed addressing modes The selected 16 byte working register block usually consists of two contiguous 8 byte slices As a general programming guideline it is recommended that RPO point to the lower slice and point to the upper slice see Figure 2 6 In some cases it may be necessary to define working register areas in different non contiguous areas of the register file In Figure 2 7 RPO points to the upper slice and RP1 to the lower slice Because a register pointer can point to either of the two 8 byte slices in the working register block you can flexibly define the working register area to support program requirements PROGRAMMING TIP Setting the Register Pointers SRP 70H RPO lt 70H RP1 lt 78H SRP1 48H RPO lt nochange lt 48H SRP0 0A0H RPO lt nochange CLR RPO RPO lt OOH lt nochange LD RP1 0F8H RPO lt nochange lt OF8H Register File Contains 32 8 Byte Slices 00001XXX 8 Byte Slice 16 Byte RP1 Contiguous Wo
178. nterface pins serial data D 2 10 11 P3 3 P3 4 and clock Vpp Vss Power input pins for CPU operation 12 13 internal and Power input for Writing Main oscillator pins 14 15 SO SCK SI lO Serial I O interface clock signal i 2 Voltage detector reference voltage input 18 Capture input 2 33 35 1 5 1 7 2 7 P3 2 T1OUT T1PWM x E D D D P1 0 P1 1 P1 2 t Timer 1 External clock input Timer 1 output and PWM output d 43 10 i 7 i E 29 i E 30 SEGO SEG15 SEG16 SEG23 SEG24 SEG31 ELECTRONICS 1 7 LCD segment output H 55 70 LCD segment output H 14 4 0 4 7 LCD Segment output H 14 5 0 5 7 LCD power supply 48 50 MC 0 5 1 2 or 4 kHz frequency output for E 2 32 P1 4 buzzer sound with 4 19 MHz main System clock or 32768 Hz subsystem clock Capacitor terminal for voltage booster 46 47 W BN E o 1 IN cow cows 0 LCD common sgnaloupa ss IN Lo Rz PRODUCT OVERVIEW S3C8245 P8245 C8249 P8249 PIN CIRCUITS Vpp D gt P Data 2 Circuit In Output Disable Figure 1 4 Pin Circuit Type B nRESET Figure 1 6 Pin Circuit Type D 2 P3 Pull up P Channel Data EP Enable Output Disable Out Output N Channel Disable Ext INT Input Normal Figure 1 5 Pin Circuit Type C Figure 1 7 Pin Circuit Type D 4 PO 1 8 ELECTRON
179. nterrupt request ELECTRONICS 5 15 INTERRUPT STRUCTURE S3C8245 P8245 C8249 P8249 GENERATING INTERRUPT VECTOR ADDRESSES The interrupt vector area in the ROM 00H FFH contains the addresses of interrupt service routines that correspond to each level in the interrupt structure Vectored interrupt processing follows this sequence Push the program counter s low byte value to the stack Push the program counter s high byte value to the stack Push the FLAG register values to the stack Fetch the service routine s high byte address from the vector location Fetch the service routine s low byte address from the vector location o E D N Branch to the service routine specified by the concatenated 16 bit vector address NOTE 16 bit vector address always begins at an even numbered ROM address within the range of 00H FFH NESTING OF VECTORED INTERRUPTS It is possible to nest a higher priority interrupt request while a lower priority request is being serviced To do this you must follow these steps 1 Push the current 8 bit interrupt mask register IMR value to the stack PUSH IMR 2 Load the IMR register with a new mask value that enables only the higher priority interrupt Execute an El instruction to enable interrupt processing a higher priority interrupt will be processed if it occurs 4 When the lower priority interrupt service routine ends restore the IMR to its original value by returning the previous mask valu
180. o Program or Data 3 9 3 10 Direct Addressing for Load 3 10 3 11 Direct Addressing for Call and Jump Instructions 3 11 3 12 Indirect Addressirig etn gre eren 3 12 3 13 Relative see 3 13 3 14 Immediate Addressing 1d ctore titii eei Xt athe tod etanes Dota A 3 14 4 1 Register Description 4 4 53 8245 8245 8249 8249 MICROCONTROLLER xi List of Figures continued Figure Title Page Number Number 5 1 S3C8 Series Interrupt 5 2 5 2 S3C8245 C8249 Interrupt 5 3 5 3 ROM Vector Address 040000000 5 4 5 4 Interrupt Function Diagram 5 7 5 5 System Mode Register 5 5 9 5 6 Interrupt Mask Register mmm rn 5 10 5 7 Interrupt Request Priority 5 11 5 8 Interrupt Priority Register 5 12 5 9 Interrupt Request Register 5 13 6 1 System Flags Register 5 6 6 7 1 Main Oscillator Circuit Crystal or Ceramic 7 1 7 2 Main Oscillator Circuit RC
181. o their default hardware values and the contents of all data registers are retained A reset operation automatically selects a slow clock fxx 16 because CLKCON 3 and CLKCON 4 are cleared to O0B After the programmed oscillation stabilization interval has elapsed the CPU starts the system initialization routine by fetching the program instruction stored in ROM location 0100H and 0101H Using an External Interrupt to Release Stop Mode External interrupts with an RC delay noise filter circuit can be used to release Stop mode Which interrupt you can use to release Stop mode in a given situation depends on the microcontroller s current internal operating mode The external interrupts in the S3C8245 C82409 interrupt structure that can be used to release Stop mode are External interrupts 0 7 INTO INT7 Please note the following conditions for Stop mode release f you release Stop mode using an external interrupt the current values in system and peripheral control registers are unchanged except STPCON register f you use an internal or external interrupt for stop mode release you can also program the duration of the oscillation stabilization interval To do this you must make the appropriate control and clock settings before entering stop mode When the Stop mode is released by external interrupt the CLKCON 4 CLKCON 3 bit pair setting remains unchanged and the currently selected clock value is used
182. o value The bits to be tested are specified by setting a 1 bit in the corresponding position of the source operand mask which is ANDed with the destination operand The zero Z flag can then be checked to determine the result The destination and source operands are unaffected C Unaffected Z Setif the result is 0 cleared otherwise S Setif the result bit 7 is set cleared otherwise V Always reset to O D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src 6 73 r Ir opc src dst 3 6 74 R R 75 R IR opc dst src 3 6 76 R IM Given RO 0C7H R1 02H R2 18H register 2BH register 01H 02H and register 02H 23H TM RO R1 RO 0 7 1 02H Z 0 TM RO R1 gt RO 0C7H 1 02H register 02H 23H Z 0 TM 00H01H gt Register 00 2BH register 01H 02H Z 70 00H 801H gt Register 00H 2BH register 01H 02H register 02H 23H Z 0 TM 00H 54H gt Register 00H 2BH Z 1 In the first example if working register RO contains the value 0C7H 11000111B and register R1 the value 02H 00000010B the statement TM RO R1 tests bit one in the destination register for a 0 value Because the mask value does not match the test bit the Z flag is cleared to logic zero and can be tested to determine the result of the TM operation ELECTRONICS 53 8245 8245 8249 8249 INSTRUCTION SET WEI wait for Interrupt WFI Operation The CPU is effectively h
183. ocument name should be changed into S3C8245 P8245 C8249 P8249 2 FEATURES The Operating Temperature Range should be changed 40 C to 85 C into 25 C to 85 in the page 1 2 from 19 2 to 19 12 and from 21 4 to 21 7 3 ELECTRICAL DATA Table 19 2 D C Electrical Characteristics Concluded Page 19 4 Ta 25 C to 85 C Vpp 1 8 V to 5 5 V Supply current 1 Main stop mode sub osc Stop Vpp 5 V 10 TA 25 Vpp 3V 10 25 Table 19 12 D C Electrical Characteristics Concluded Page 19 12 Ta 25 C to 85 Vpp 2 0 V to 5 5 V Test Condition Ceramic Stabilization occurs when Vpp is equal to the minimum oscillator voltage range External clock Xy input high and low level width txi Table 21 4 D C Electrical Characteristics Continued Page 19 3 21 5 TA 25 C to 85 C Vpp 1 8 V to 5 5 V Oscillator feed back Rosc4 Vpp2 5 0V 25 resistors Xour 0 V 53 8245 8245 C8249 P8249 8 BIT CMOS MICROCONTROLLERS USER S MANUAL Revision 4 ELECTRONICS Important Notice The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication Samsung assumes no responsibility however for possible errors or omissions or for any consequences resulting from the use of the information contained herein Samsung reserves the right to make changes
184. ode 4 32 ELECTRONICS 53 8245 8245 8249 8249 CONTROL REGISTER PP _ Register Page Pointer DFH Set1 Bit Identifier 7 6 5 4 2 o 0 0 0 0 0 0 0 0 nRESET Value Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 4 Destination Register Page Selection Bits 0 Destnaion paeo 1 1 o Desiaonpae2 111 oli 1 1 Destination page 1 olo Destination page 4 3 0 Source Register Page Selection Bits o o o o suepoo swepe SSCS olofo olse 7 1 1 Source page 1 Source page 4 NOTE Inthe S3CC8249 microcontroller the internal register file is configured as five pages Pages 0 4 The pages 0 3 are used for general purpose register file and page 4 is used for LCD data register or general purpose registers In case of S3C8245 pages 0 1 are used for general purpose and page 2 is used for LCD data register or general purpose registers ELECTRONICS 4 33 CONTROL REGISTERS 53 8245 8245 8249 8249 Register Pointer 0 D6H Set 1 nRESET Value 1 1 0 0 0 Read Write R W R W R W R W R W _ _ _ Addressing Mode Register addressing only 7 3 Register Pointer 0 Address Value Register pointer 0 can independently point to one of the 256 byte working register areas in the register
185. ode Addr Mode Hex dst src 1 dst src 2 10 C3 r Irr 2 2 10 D3 Irr r 3 t e 4 src dst 3 12 F7 XS rr r 5 dst src 4 14 A7 r XL rr 6 src dst 4 14 B7 XL rr r z DA 4 14 r DA 8 opc DA DA 4 14 B7 DA r 9 DA DA 4 14 A7 r DA 10 opc DA 4 14 B7 DA r NOTES 1 The source src or working register pair rr for formats 5 and 6 cannot use register pair 0 1 2 Forformats 3 and 4 the destination address XS rr and the source address XS rr are each one byte 3 Forformats 5 and 6 the destination address rr and the source address rr are each two bytes 4 The DA andr source values for formats 7 and 8 are used to address program memory the second set of values used in formats 9 and 10 are used to address data memory 6 52 ELECTRONICS INSTRUCTION SET LDC LDE Load Memory LDC LDE Continued S3C8245 P8245 C8249 P8249 Examples Given RO 11H R1 34H R2 01H R3 04H Program memory locations 0103H 4FH 0104H 1A 0105H 6DH and 1104H 88H External data memory locations 0103H 0104 2 0105 7DH and 1104H 98H LDC R0 RR2 LDE R0 RR2 LDC note RR2 R0 LDE RR2 R0 LDC R0 401H RR2 LDE RO 01H RR2 LDC note 01H RR2 RO LDE 01H RR2 RO LDC R0 1000H RR2 LDE R0 1000H RR2 LDC R0 1104H LDE R0 1104H LDC note 1105 0 LDE 1105H R0 5 5 RO lt contents of p
186. ol passes to the statement whose address is now in the PC The range of the relative address is 127 to 128 and the original value of the PC is taken to be the address of the instruction byte following the DJNZ statement NOTE Incase of using DJNZ instruction the working register being used as a counter should be set at the one of location to OCFH with SRP SRPO or SRP1 instruction No flags are affected Bytes Cycles Opcode Addr Mode Hex dst dst 2 8 jump taken rA RA 8 no jump r OtoF Given R1 02H and LOOP is the label of a relative address SRP 0COH DJNZ R1 LOOP DJNZ is typically used to control a loop of instructions In many cases a label is used as the destination operand instead of a numeric relative address value In the example working register R1 contains the value 02H and LOOP is the label for a relative address The statement DJNZ R1 LOOP decrements register R1 by one leaving the value 01H Because the contents of R1 after the decrement are non zero the jump is taken to the relative address specified by the LOOP label ELECTRONICS 6 39 INSTRUCTION SET S3C8245 P8245 C8249 P8249 El Enable Interrupts El Operation Flags Format Example 6 40 SYM 0 1 An El instruction sets bit zero of the system mode register SYM 0 to 1 This allows interrupts to be serviced as they occur assuming they have highest priority If an interrupt s pending bit was set while
187. oller has a built in VLD Voltage Level Detector circuit which allows detection of power voltage drop or external input level through software Turning the VLD operation on and off can be controlled by software Because the IC consumes a large amount of current during VLD operation It is recommended that the VLD operation should be kept OFF unless it is necessary Also the VLD criteria voltage can be set by the software The criteria voltage can be set by matching to one of the 4 kinds of voltage below that can be used 2 2 V 2 4 V 3 0 V or 4 0 V V pp reference voltage or external input level External reference voltage The Vi p block works only when VLDCON 2 is set If Vpp level is lower than the reference voltage selected with VLDCON 1 0 VLDCON 3 will be set If Vpp level is higher VLDCON 3 will be cleared When users need to minimize current consumption do not operate the VLD block Vpp Pin Voltage Level VLDCON 3 Detector VLD Out m ExtRef P2 7 Voltage VLD Run Level Setting VLDCON 2 P2CONH 7 6 VLDCON 1 ExtRef Input VLDCON O Enable Set the Level Figure 18 1 Block Diagram for Voltage Level Detect ELECTRONICS 18 1 VOLTAGE LEVEL DETECTOR 53 8245 8245 8249 8249 VOLTAGE LEVEL DETECTOR CONTROL REGISTER VLDCON The bit 2 of VLDCON controls to run or disable the operation of Voltage level detect Basically this Vy p is set as 2 2 V by system reset and it can be changed in 4 kinds voltages by
188. operands are both logic ones otherwise a bit value is stored The contents of the source are unaffected C Unaffected Z Setif the result is 0 cleared otherwise S Setif the result bit 7 is set cleared otherwise V Always cleared to O D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src 6 53 r Ir opc src dst 3 6 54 R R 55 R IR opc dst src 3 6 56 R IM Given R1 12H R2 03H register 01H 21H register 02H 03H register 03H OAH AND R1 R2 gt R1 02H R2 03H AND R1 R2 gt R1 02H R2 AND 01H 02H gt Register 01H 01H register 02H 03H AND 01H 02H gt Register 01H OOH register 02H 03H AND 01H 25H gt Register 01H 21H In the first example destination working register R1 contains the value 12H and the source working register R2 contains 03H The statement AND R1 R2 logically ANDs the source operand 03H with the destination operand value 12H leaving the value 02H in register R1 ELECTRONICS 53 8245 8245 8249 8249 INSTRUCTION SET BAND Bit AND BAND BAND Operation Flags Format Examples dst src b dst b src dst 0 lt dst 0 AND src b or dst b dst b AND src 0 The specified bit of the source or the destination is logically ANDed with the zero bit LSB of the destination or source The resultant bit is stored in the specified bit of the destination No other bits of the destination are affected The source i
189. or RP1 Selected RP points Program Memory to start fo n working register block k RENE Working dst src Register Point to the ADDRESS Address Working Register Pp Go j C 522 2 2 Value used in OPERAND M 2 22 241 Sample Instruction Figure 3 5 Indirect Working Register Addressing to Register File ELECTRONICS 3 5 ADDRESSING MODES 53 8245 8245 8249 8249 INDIRECT REGISTER ADDRESSING Concluded Register File MSB Points to RPO or RP0 or RP1 Selected RP points to start of working register 4 bit Working i block Register Address ee dst src ej Register Next 2 bit Point Pair IE References either Register Pair Program Memory or 1 of 4 Data Memory Program Memory 16 Bit address LSB Selects Program Memory points to or program Data Memory memory or data memory Value used in OPERAND Instruction Sample Instructions LCD R5 RR6 Program memory access LDE R3 RR14 External data memory access LDE RR4 R8 External data memory access Figure 3 6 Indirect Working Register Addressing to Program or Data Memory 3 6 ELECTRONICS 53 8245 8245 8249 8249 ADDRESSING MODES INDEXED ADDRESSING MODE X Indexed X addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address see Figure 3 7 You can use Indexed addressing mode
190. ormat Bytes Cycles Opcode Addr Mode Hex dst src r8 r R r 0toF D7 Ir r opc src dst 3 6 E4 R R E5 R IR D6 IR IM opc src dst 3 6 F5 IR R s r r ELECTRONICS 6 49 INSTRUCTION SET O gt gt gt gt gt gt E gt gt L D Load LD Continued Examples Given RO 01H R1 register 02H 02H LO LD R0 10H LD R0 01H LD 01H R0 LD R1 R0 LD RO R1 LD 00H 01H LD 02H 00H LD 00H 0AH LD O00H 10H LD 00H 02H LD RO LOOP R1 LD LOOP RO R1 6 50 53 8245 8245 8249 8249 OAH register OOH 01H register 01H 20H P 30H and register RO 10H RO 20H register 01H 20H Register 01H 01H RO 01H R1 20H 01H RO 01H R1 OAH register 01H OAH Register OOH 20H register 01H 20H Register 02H 20H register OOH 01H Register OOH OAH Register OOH 01H register 01H 10H Register OOH 01H register 01H 02 register 02H 02H RO OFFH R1 OAH Register RO 01H R1 0AH ELECTRONICS 53 8245 8245 8249 8249 INSTRUCTION SET Load Bit LDB LDB Operation Flags Format Examples dst src b dst b src dst 0 lt src b or dst b lt src 0 The specified bit of the source is loaded into bit zero LSB of the destination or bit zero of the source is loaded into the specified bit of the destination No other bits
191. p enable 4 1 4 Resistor Enable Bit Pull up disable 1 Pull up enable 3 P1 3 Pull up Resistor Enable Bit Pull up disable 1 Pull up enable 2 P1 2 Pull up Resistor Enable Bit Pull up disable Pull up enable 4 1 1 Pull up Resistor Enable Bit Pull up disable Pull up enable le 0 1 0 Resistor Enable Bit Pull up disable 1 Pull up enable 4 24 ELECTRONICS 53 8245 8245 8249 8249 CONTROL REGISTER P2CONH Port 2 Control Register High Byte E6H Set 1 Bank 0 nRESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P2 7NLDREF ADC7 o o mamm o i noame 1 0 Alternative function ADC amp VLD mode Output mode push pull 5 4 P2 6 ADC6 o o mame o Mtema turton a00 moa 3 2 P2 5 ADC5 o o mame Co i imeut mose pa o Meman turton a00 moa 1 0 P2 4 ADC4 o o mame 1 0 Alternative function ADC mode Output mode push pull ELECTRONICS 4 25 CONTROL REGISTERS 53 8245 8245 8249 8249 P2CONL Port 2 Control Register Low Byte E7H Set 1 Bank 0 nRESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P2 3 ADC3 rot 1 0 Alternative function ADC mode
192. perand are rotated left one bit position The initial value of bit 7 is moved to the bit zero LSB position and also replaces the carry flag 53 8245 8245 8249 8249 Flags Format Examples 6 72 Setif the bit rotated from the most significant bit position bit 7 was 1 Z Set if the result is 0 cleared otherwise S Setif the result bit 7 is set cleared otherwise V Setif arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Addr Mode dst R IR Bytes Cycles Opcode Hex Opc dst 2 4 90 91 Given Register 00H register 01H 02H and register 02H 17H RL 00H gt Register OOH 55H C 1 RL 01H gt Register 01H 02H register 02H 2 In the first example if general register OOH contains the value OAAH 10101010B the statement RL OOH rotates the OAAH value left one bit position leaving the new value 55H 01010101B and setting the carry and overflow flags ELECTRONICS 53 8245 8245 8249 8249 INSTRUCTION SET RLC Rotate Lett Through Carry RLC Operation dst dst 0 C C lt dst 7 dst n 1 lt 0 6 The contents of the destination operand with the carry flag are rotated left one bit position The initial value of bit 7 replaces the carry flag C the initial value of the carry flag replaces bit zero Flags Format Examples C Setif the bit rotated from the most signi
193. ponding control register settings To ensure flexible data transmission rates you can select an internal or external clock source PROGRAMMING PROCEDURE To program the SIO modules follow these basic steps i Configure the pins at port SO SCK SI by loading the appropriate value to the P1CONH register if necessary Load an 8 bit value to the SIOCON control register to properly configure the serial I O module In this operation SIOCON 2 must be set to 1 to enable the data shifter For interrupt generation set the serial I O interrupt enable bit SIOCON 1 to 1 When you transmit data to the serial buffer write data to SIODATA and set SIOCON 3 to 1 the shift operation starts When the shift operation transmit receive is completed the SIO pending bit SIOCON O is set to 1 an SIO interrupt request is generated ELECTRONICS 16 1 SERIAL I O INTERFACE SIO CONTROL REGISTER SIOCON 53 8245 8245 8249 8249 control register for serial I O interface module SIOCON is located at FOH set 1 bank 0 It has the control settings for SIO module Clock source selection internal or external for shift clock Interrupt enable Edge selection for shift operation Clear 3 bit counter and start shift operation Shift operation transmit enable Mode selection transmit receive or receive only Data direction selection MSB first or LSB first A reset clears the SIOCON value to 00H This
194. r POPND ELECTRONICS 9 5 5 53 8245 8245 8249 8249 1 Port 1 is an 8 bit I O port with individually configurable pins Port 1 pins are accessed directly by writing or reading the port 1 data register P1 at location F7H in set 1 bank 0 P1 0 P1 7 can serve inputs as outputs push pull or open drain or you can configure the following alternative functions Low byte pins P1 0 P1 3 T1OUT T1PWM High byte pins P1 4 P1 7 SCK SI SO and BUZ Port 1 Control Register Port 1 has two 8 bit control registers P1 CONH for P1 4 P1 7 and P1CONL for 1 0 1 3 A reset clears the P1CONH and P1CONL registers to configuring all pins to input mode You use control registers settings to select input or output mode push pull or open drain and enable the alternative functions When programming the port please remember that any alternative peripheral I O function you configure using the port 1 control registers must also be enabled in the associated peripheral module Port 1 Pull up Resistor Enable Register P1PUP Using the port 1 pull up resistor enable register P1PUP F5H set 1 bank 0 you can configure pull up resistors to individual port 1 pins Port 1 Control Register High Byte P1 CONH Set 1 Bank 0 R W P1CONH bit pair pin configuration settings Input mode SI SCK in Output mode open drain Alternative function SCK out BUZ SO P1
195. r 1 also gives you capture input source the signal edge at the T1CAP pin You select the capture input by setting the value of the timer 1 capture input selection bit in the port 1 control register low P1CONL set 1 bank 0 E5H When P1CONL 1 0 is 00 the T1CAP input or normal input is selected When P1CONL 1 0 is set to 11 normal output is selected Both kinds of timer 1 interrupts can be used in capture mode the timer 1 overflow interrupt is generated whenever a counter overflow occurs the timer 1 match capture interrupt is generated whenever the counter value is loaded into the T1 data register By reading the captured data value in T1DATAH L and assuming a specific value for the timer 1 clock frequency you can calculate the pulse width duration of the signal that is being input at the T1CAP pin 12 6 ELECTRONICS 53 8245 8245 8249 8249 16 0 1 TIMER 1 CONTROL REGISTER T1CON You use the timer 1 control register T1 CON to Select the timer 1 operating mode interval timer capture mode or PWM mode Select the timer 1 input clock frequency Clear the timer 1 counter T1CNTH L Enable the timer 1 overflow interrupt or timer 1 match capture interrupt Clear timer 1 match capture interrupt pending conditions T1CON is located in set 1 and Bank 1 at address FBH and is read write addressable using Register addressing mode A reset clears T1CON to OOH This sets timer 1 to normal int
196. r P3CONH 232 m Port 3 Control Low Register P3CONL S IN S S O S IS Q amp O O ITI TI rm ce o T mi rm gt Timer B Data Register High Byte TBDATAH m a mim ER TI eo I Por Obata Regier m Location FCH is factory use o Basic Timer Data Register BTCNT 25 i 5 41 42 4 IS IS ER 4 CH 1 TI OQ N T 2 2 2 4 n A T TT Tm 7 O Oo 247 i ister Timer B Data Register Low Byte TBDATAL m gt eo ro mim a R B aS a m I ET y External Memory Timing Register 254 Interrupt Priority Register 255 ELECTRONICS 8 3 nRESET POWER DOWN S3C8245 P8245 C8249 P8249 Table 8 3 S3C8245 P8245 Set 1 Bank 1 Register Values after nRESET Register Name Port 4 control High register Port 4 control Low register 2 Port 5 Control High Register 23 Port 5 Control Low Register 239 Locations F0H is factory us T 24 4 4 m j BB m O o ar 3 m rm m ELE m N lt 2 2 I 2 Timer 0 Data Register High Byte TODATAH 4 Timer 0 Data Register Low Byte TODATAL mimim ocolos
197. r application development It is organized in two main parts Part Programming Model Part 1 Hardware Descriptions Part contains software related information to familiarize you with the microcontroller s architecture programming model instruction set and interrupt structure It has six chapters Chapter 1 Product Overview Chapter 4 Control Registers Chapter 2 Address Spaces Chapter 5 Interrupt Structure Chapter 3 Addressing Modes Chapter 6 Instruction Set Chapter 1 Product Overview is a high level introduction to S8C8245 P8245 C8249 P8249 with general product descriptions as well as detailed information about individual pin characteristics and pin circuit types Chapter 2 Address Spaces describes program and data memory spaces the internal register file and register addressing Chapter 2 also describes working register addressing as well as system stack and user defined stack operations Chapter 3 Addressing Modes contains detailed descriptions of the addressing modes that are supported by the S3C8 series CPU Chapter 4 Control Registers contains overview tables for all mapped system and peripheral control register values as well as detailed one page descriptions in a standardized format You can use these easy to read alphabetically organized register descriptions as a quick reference source when writing programs Chapter 5 Interrupt Structure describes the S3C8245 P8245 C8249 P8249 interrupt structure in det
198. r file The address of the memory location is specified by a working register pair The contents of the source location are loaded into the destination location The memory address is then incremented automatically The contents of the source are unaffected LDCI refers to program memory and LDEI refers to external data memory The assembler makes even for program memory and odd for data memory No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src Given R6 10H R7 33H R8 12H program memory locations 1033H and 1034H external data memory locations 1033H ODDH and 1034H 0D5H LDCI R8 RR6 OCDH contents of program memory location 1033H is loaded into R8 and RR6 is incremented by one RR6 lt RR6 1 R8 R6 10H R7 34H LDEI R8 RR6 ODDH contents of data memory location 1033H is loaded into R8 and RR6 is incremented by one RR6 lt RR6 1 R8 ODDH R6 10H R7 34H ELECTRONICS 53 8245 8245 8249 8249 INSTRUCTION SET LDCPD LDEPD Load Memory with Pre Decrement LDCPD LDEPD dst src Operation rr lt rr 1 dst lt src These instructions are used for block transfers of data from program or data memory from the register file The address of the memory location is specified by a working register pair and is first decremented The contents of the source location are then loaded into the destination location The contents of the sour
199. r indirect working register pair Indexed addressing mode Indexed short offset addressing mode Indexed long offset addressing mode Direct addressing mode Relative addressing mode Immediate addressing mode Immediate long addressing mode ELECTRONICS See list of condition codes in Table 6 6 Rn n 0 15 Rn b n 0 15 b 0 7 Rn n 0 15 RRp p 0 2 4 14 reg or Rn reg 0 255 n 0 15 reg b reg 0 255 b 0 7 reg or RRp reg 0 254 even number only where 0 2 14 addr addr 0 254 even number only Rn n 0 15 or reg reg 0 255 0 15 RRp p 0 2 14 RRp or reg 0 254 even only where 0 2 14 Rn reg 0 255 n 0 15 addr RRp addr range 128 to 127 where 0 2 14 addr RRp addr range 0 65535 where 0 2 14 addr addr range 0 65535 addr addr number in the range 127 to 128 that is an offset relative to the address of the next instruction data data 0 255 data data range 0 65535 6 9 INSTR U UCTION SET S3C8245 P8245 C8249 P8249 Table 6 5 Opcode Quick Reference OPCODE MAP LOWER NIBBLE HEX JL p o p 6 DEC DEC ADD ADD ADD ADD ADD BOR R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM ro Rb 1 RLC RLC ADC ADC ADC ADC ADC BCP R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM r1 b R2 2 INC INC SUB SUB SUB SUB SUB
200. r run the voltage booster Make enable the watch timer for fyooster Set LCON 2 to 0 and LCON 1 to 1 for make enable voltage booster Recommendable capacitance value is 0 1 uF CO C1 C2 By Voltage Dividing Resistors Externally For make external voltage dividing resistors Make enable the watch timer Set LCON 2 to 1 and LCON 1 to 0 for make disable voltage booster floating the CA and CB Recommendable 100 Static and 1 3 Bias Mcp 3VatVpp 5 V 1 2 Bias 3 3 V at VDD 5 V Static 1 3 Bias 5 V at VDD 5 V NOTE 3 0V lt VLcp lt 5 5 V Figure 14 10 Voltage Dividing Resistor Circuit Diagram 14 12 ELECTRONI S 53 8245 8245 8249 8249 A D CONVERTER 10 BIT ANALOG TO DIGITAL CONVERTER OVERVIEW The 10 bit A D converter ADC module uses successive approximation logic to convert analog levels entering at one of the eight input channels to equivalent 10 bit digital values The analog input level must lie between the AVper and AV ss values The A D converter has the following components Analog comparator with successive approximation logic D A converter logic resistor string type control register ADCON Eight multiplexed analog data input pins ADCO ADC7 10 bit A D conversion data output register ADDATAH L 10 bit digital input port Alternately port AVper and AVss p
201. rce Selection Bits oop 77 oppe LL 0 Start Enable Bit Disable operation Start operation ELEGTRONEGS 4 5 CONTROL REGISTERS 53 8245 8245 8249 8249 BTCON Basic Timer Control Register D3H Set 1 Bit Identifier 5 3 2 o 0 0 0 0 0 0 0 0 nRESET Value Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 4 Watchdog Timer Function Disable Code for System Reset 0 1 0 Disable watchdog timer function Enable watchdog timer function 3 2 Basic Timer Input Clock Selection Bits a SSS r ojo _ 4 Basic Counter Clear Bit 1 No effect Clear the basic timer counter value 0 Clock Frequency Divider Clear Bit for Basic Timer and Timer Counters 2 effect Clear both clock frequency dividers NOTES 1 When you write a 1 to BTCON 1 the basic timer counter value is cleared to Immediately following the write operation the BTCON 1 value is automatically cleared to 0 2 When you write a 1 to BTCON O the corresponding frequency divider is cleared to Immediately following the write operation the 0 value is automatically cleared to O 3 Thefxxis selected clock for system main OSC or sub OSC 4 6 ELECTRONI S 53 8245 8245 8249 8249 CONTROL REGISTER System Clock Control Register D4H Set 1 nRESET Value 0 0 0 0 0 0 0 0 Rea
202. rea of the internal register file is currently selected bank 0 or bank 1 The BA flag is cleared to 0 select bank 0 when you execute the SBO instruction and is set to 1 select bank 1 when you execute the SB1 instruction ELECTRONICS 6 7 INSTRUCTION SET INSTRUCTION SET NOTATION S3C8245 P8245 C8249 P8249 Table 6 2 Flag Notation Conventions _ Flag Deseription C 2 5 V D H 0 1 6 8 Carry flag Zero flag Sign flag Overflow flag Decimal adjust flag Half carry flag Cleared to logic zero Set to logic one Set or cleared according to operation Value is unaffected Value is undefined Table 6 3 Instruction Set Symbols Destination operand Source operand Indirect register address prefix Program counter Instruction pointer Flags register D5H Register pointer Immediate operand or register address prefix Hexadecimal number suffix Decimal number suffix Binary number suffix Opcode ELECTRONICS 53 8245 8245 8249 8249 INSTRUCTION SET Table 6 4 Instruction Notation Conventions Condition code Working register only Bit b of working register Bit 0 LSB of working register Working register pair Register or working register Bit b of register or working register Register pair or working register pair Indirect addressing mode Indirect working register only Indirect register or indirect working register Indirect working register pair only Indirect register pair o
203. ressed by the decremented stack pointer The operation then adds the new value to the top of the stack No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src 2 8 internal clock 70 R 8 external clock 8 internal clock 8 external clock 71 IR Given Register 40 4FH register 4FH SPH and 00H PUSH 40H gt Register 40H 4FH stack register OFFH 4FH SPH OFFH SPL OFFH PUSH 40H gt Register 40H 4FH register 4FH OAAH stack register OFFH OAAH SPH OFFH SPL OFFH In the first example if the stack pointer contains the value 0000H and general register 40H the value 4FH the statement PUSH 40H decrements the stack pointer from 0000 to OFFFFH It then loads the contents of register 40H into location OFFFFH and adds this new value to the top of the stack ELECTRONICS 6 67 INSTRUCTION SET S3C8245 P8245 C8249 P8249 PUSHUD Push User Stack Decrementing PUSHUD dst src Operation IR lt IR 1 dst src This instruction is used to address user defined stacks in the register file PUSHUD decrements the user stack pointer and loads the contents of the source into the register addressed by the decremented stack pointer Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src opc dst src 3 8 82 IR R Example Given Register 03H register 01H 05H and register 02H PUSHUD 00H 01H gt Register 00
204. rigger input mode interrupt on rising edge ilo Schmitt trigger input mode interrupt on rising or falling edge Output mode push pull 1 0 PO 4 INT4 Schmitt trigger input mode pull up interrupt on falling edge Schmitt trigger input mode interrupt on rising edge Schmitt trigger input mode interrupt rising falling edge Output mode push pull 4 18 ELECTRONICS 53 8245 8245 8249 8249 CONTROL REGISTER POCONL Port 0 Control Register Low Byte E1H Set 1 Bank 0 Bit Identifier nRESET Value Read Write Addressing Mode 7 6 ELECTRONI S s 4 3 2 a o 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W Register addressing mode only P0 3 INT3 Schmitt trigger input mode pull up interrupt on falling edge ola Schmitt trigger input mode interrupt on rising edge KEREN Schmitt trigger input mode interrupt on rising or falling edge Output mode push pull P0 2 INT2 olo Schmitt trigger input mode pull up interrupt on falling edge 1 Schmitt trigger input mode interrupt rising edge Schmitt trigger input mode interrupt rising falling edge Output mode push pull PO 1 INT1 olo Schmitt trigger input mode pull up interrupt on falling edge Schmitt trigger input mode interrupt on rising edge ilo Schmitt trigger input mode interrupt on rising or falling edge Output mode push pull P0 0 INT0 olo
205. rking 00000XXX 8 Byte Slice Register block RPO Figure 2 6 Contiguous 16 Byte Working Register Block ELECTRONICS 2 9 ADDRESS SPACES 53 8245 8245 8249 8249 8 Byte Slice Register File 16 Byte Contains 32 Contiguous 11110 XXX 8 Byte Slices working Register block RPO 7H R15 00000 XXX 8 Byte Slice OH RO RP1 Figure 2 7 Non Contiguous 16 Byte Working Register Block PROGRAMMING Using the RPs to Calculate the Sum of a Series of Registers Calculate the sum of registers 80H 85H using the register pointer The register addresses from 80H through 85H contain the values 10H 11H 12H 13H 14H and 15 H respectively SRPO 80H RPO lt 80H ADD RO R1 RO RO R1 ADC RO R2 RO lt RO R2 C ADC RO R3 RO lt RO ADC R0 R4 RO RO R4 C ADC R0 R5 RO RO R5 C The sum of these six registers 6FH is located in the register RO 80H The instruction string used in this example takes 12 bytes of instruction code and its execution time is 36 cycles If the register pointer is not used to calculate the sum of these registers the following instruction sequence would have to be used ADD 80H 81H 80H 81H ADC 80H 82H 80H 80H 82H C ADC 80H 83H 80H lt 80H 83H C ADC 80H 84H 80H 80H 84H C ADC 80H 85H 80H 80H 85H C Now the sum of the six registers is also located in register 80H However this
206. rnately P1 0 P1 7 can be used as SI SO SCK BUZ T1CLK T1OUT T1PWM selected by software software assignable 2 0 2 7 I O port with bit programmable pins 36 42 ADCO ADC6 normal input and AD input or output mode 43 V selected by software software assignable VLDREF pull up ADC7 pull up 0 0 0 7 be used as inputs P3 0 P3 4 port with bit programmable pins Input 7 11 or push pull output with software assignable pull up Alternately 0 can be used as TACAP TACLK TAOUT TAPWM TBPWM 4 0 4 7 I O port with bit programmable pins Push 71 78 SEG16 SEG23 pull or open drain output and input with software assignable pull up 4 0 4 7 can alternately be used as outputs for LCD SEG 5 0 5 7 I O port with bit programmable pins Push 79 6 SEG24 SEG31 pull or open drain output and input with software assignable pull up 5 0 5 7 can alternately be used as outputs for LCD SEG 1 6 ELECTRONICS 53 8245 8245 8249 8249 PRODUCT OVERVIEW Table 1 1 53 8245 8249 Pin Descriptions Continued Pin Pin Circuit P Type Description Type Numbers note in ADC0 ADC6 converter analog input channels 10 36 42 2 0 2 6 ADC7 18 43 P2 7 5 INTO INT7 20 27 P0 0 P0 7 System reset pin nRESET pull up resistor 250 TEST 0 V Normal MCU operating 5 V Test mode 12 V for OTP writing External interrupt input pins SDAT SCLK Serial OTP i
207. rogram memory location 0104H RO 2 01H R3 04H RO lt contents of external data memory location 0104H RO 2AH R2 01H R3 04H 11H contents of RO is loaded into program memory location 0104H RR2 working registers RO R2 R3 no change 11H contents of RO is loaded into external data memory location 0104H RR2 working registers RO R2 no change RO lt contents of program memory location 0105H 01H RR2 RO 6DH R2 01H R3 04H RO lt contents of external data memory location 0105H 01H RR2 RO 7DH R2 01H R3 04H 11H contents of RO is loaded into program memory location 0105H 01H 0104H 11H contents of RO is loaded into external data memory location 0105H 01H 0104H RO lt contents of program memory location 1104H 1000H 0104 RO 88H R2 01H R3 04H RO lt contents of external data memory location 1104H 1000H 0104H RO 98H R2 01H R3 04H RO lt contents of program memory location 1104H RO 88H RO lt contents of external data memory location 1104H RO 98H 11H contents of RO is loaded into program memory location 1105H 1105H 11H 11H contents of RO is loaded into external data memory location 1105H 1105H 11H NOTE These instructions are not supported by masked ROM type devices 6 54 ELECTRONICS 53 8245 8245 8249 8249 INSTRUCTION SET LDCD LDED Load Memory and Decrement LDCD LDED
208. routine can detect a pending condition of TOINT by the software and execute it s sub routine When this case is used the TOINT pending bit must be cleared by the application subroutine by writing a 0 to the 0 pending bit In interval timer mode a match signal is generated when the counter value is identical to the values written to the TO reference data registers TODATAH L The match signal generates a timer 0 match interrupt TOINT vector and clears the counter If for example you write the value 0010H to TODATAH L and OFH to TOCON the counter will increment until it reaches 10H At this point the TO interrupt request is generated the counter value is reset and counting resumes ELECTRONICS 12 1 16 0 1 53 8245 8245 8249 8249 0 CONTROL REGISTER You use the timer 0 control register to Enable the timer 0 operating interval timer Select the timer 0 input clock frequency Clear the timer 0 counter Enable the timer 0 interrupt and clear timer 0 interrupt pending condition is located set 1 at address F1H and is read write addressable using register addressing mode A reset clears to 00H This sets timer 0 to disable interval timer mode selects the and disables timer 0 interrupt You can clear the timer 0 counter at any time during normal operation by writing a 1 to TOCON 3 To
209. rupt types 1 and 3 are used Figure 5 1 S3C8 Series Interrupt Types 5 2 ELECTRONICS 53 8245 8245 8249 8249 INTERRUPT STRUCTURE S3C8245 C8249 INTERRUPT STRUCTURE The S3C8245 C8249 microcontroller supports sixteen interrupt sources All sixteen of the interrupt sources have a corresponding interrupt vector address Eight interrupt levels are recognized by the CPU in this device specific interrupt structure as shown in Figure 5 2 When multiple interrupt levels are active the interrupt priority register IPR determines the order in which contending interrupts are to be serviced If multiple interrupts occur within the same interrupt level the interrupt with the lowest vector address is usually processed first The relative priorities of multiple interrupts within a single level are fixed in hardware When the CPU grants an interrupt request interrupt processing starts All other interrupts are disabled and the program counter value and status flags are pushed to stack The starting address of the service routine is fetched from the appropriate vector address plus the next 8 bit value to concatenate the full 16 bit address and the service routine is executed Levels Vectors Sources Reset Clear Timer A match capture H W S W IRQO E2H Tv Timer A overflow H W S W IRQI 4 Timer B match H W IRQ2 E6H Timer 0 match H W S W E8H n
210. s Format Example Address IP PC SP 20 21 22 Stack IP lt SP e SP 2 PC lt lt IP 2 This instruction is useful when implementing threaded code languages The stack value is popped and loaded into the instruction pointer The program memory word that is pointed to by the instruction pointer is then loaded into the program counter and the instruction pointer is incremented by two No flags are affected Bytes Cycles Opcode Hex 1 14 internal stack 2F 16 internal stack The diagram below shows one example of how to use an EXIT statement Before After Data Address Data 0052 Address Data Address Data PC 0060 50 PCL old 60 60 Main 51 00 SP 0022 140 Exit 2F IPH 00 1 50 Data Memory 22 Data Memory Stack ELECTRONICS 53 8245 8245 8249 8249 INSTRUCTION SET IDLE idie Operation IDLE Operation The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue Idle mode can be released by an interrupt request IRQ or an external reset operation Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src 1 4 6F _ Example The instruction IDLE stops the CPU clock but not the system clock ELECTRONICS 6 43 INSTRUCTION SET S3C8245 P8245 C8249 P8249 INC Increment INC Operation Flags Format Examples 6 44 dst dst dst 1 The conten
211. s BTCON to 00H This enables the watchdog function and selects a basic timer clock frequency of fxx 4096 To disable the watchdog function you must write the signature code 1010B to the basic timer register control bits 7 4 The 8 bit basic timer counter BTCNT set 1 bank 0 FDH can be cleared at any time during the normal operation by writing a 1 to BTCON 1 To clear the frequency dividers write a 1 to BTCON O ELECTRONICS 10 1 BASIC 53 8245 8245 8249 8249 Basic Control Register Set 1 RW Watchdog timer enable bits Divider clear bit 1010B Disable watchdog function 0 No effect Other value Enable watchdog function 1 Clear dvider Basic timer counter clear bit 0 No effect 1 Clear BTCNT Basic timer input clock selection bits 00 fxx 4096 01 fxx 1024 10 fxx 128 11 16 Figure 10 1 Basic Control Register ELECTRONI S 53 8245 8245 8249 8249 BASIC BASIC FUNCTION DESCRIPTION Watchdog Timer Function You can program the basic timer overflow signal BTOVF to generate a reset by setting BTCON 7 BTCON 4 to any value other than 1010B The 1010B value disables the watchdog function A reset clears BTCON to 00H automatically enabling the watchdog timer function A reset also selects the CPU clock as determined by the current CLKCON register setting divided by 40
212. s the value 07H 000001 11B the statement BITS R1 3 sets bit three of the destination register R1 to 1 leaving the value OFH 00001111B ELECTRONICS 6 21 INSTRUCTION SET S3C8245 P8245 C8249 P8249 BOR sit or BOR BOR Operation Flags Format Examples 6 22 dst src b dst b src dst 0 lt dst 0 OR src b or dst b dst b OR src 0 The specified bit of the source or the destination is logically ORed with bit zero LSB of the destination or the source The resulting bit value is stored in the specified bit of the destination No other bits of the destination are affected The source is unaffected Unaffected Set if the result is 0 cleared otherwise Cleared to 0 Undefined Unaffected Unaffected r lt oO Bytes Cycles Opcode Addr Mode Hex dst src opc dst 3 6 07 Rb ro NOTE Inthe second byte of the 3 byte instruction formats the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit Given R1 07H and register 01H BOR R1 01H 1 gt R1 07 register 01H 03H BOR 01H 2 R1 gt Register 01H 07H R1 07H In the first example destination working register R1 contains the value 07H 00000111B and source register 01H the value 03H 00000011B The statement BOR R1 01H 1 logically ORs bit one of register 01H source with bit zero of R1 destination This leaves the same value 07H in
213. s unaffected Unaffected Set if the result is 0 cleared otherwise Cleared to 0 Undefined Unaffected Unaffected FOSENO Bytes Cycles Opcode Addr Mode Hex dst src dst 3 6 67 Rb ro NOTE Inthe second byte of the 3 byte instruction formats the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H and register 01H 05H BAND R1 01H 1 gt R1 06H register 01H 05H BAND 01H 1 R1 gt Register 01H 05H R1 07H In the first example source register 01H contains the value 05H 00000101B and destination working register R1 contains 07H 00000111B The statement BAND R1 01H 1 ANDs the bit 1 value of the source register 0 with the bit O value of register R1 destination leaving the value 06H 00000110B in register R1 ELECTRONICS 6 17 INSTRUCTION SET S3C8245 P8245 C8249 P8249 BCP Bit Compare BCP Operation Flags Format Example dst src b dst 0 src b The specified bit of the source is compared to subtracted from bit zero LSB of the destination The zero flag is set if the bits are the same otherwise it is cleared The contents of both operands are unaffected by the comparison Unaffected Set if the two bits are the same cleared otherwise Cleared to 0 Undefined Unaffected Unaffected FOSONO Bytes Cycles Opcode Addr Mode Hex dst src NOTE In
214. se Z Set if divisor or quotient 0 cleared otherwise S Set if MSB of quotient 1 cleared otherwise V Set if quotient is gt 28 or if divisor 0 cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst src src dst 3 26 10 94 RR R 26 10 95 RR IR 26 10 96 RR IM NOTE Execution takes 10 cycles if the divide by zero is attempted otherwise it takes 26 cycles Examples Given RO 10H R1 03H R2 40H register 40H 80H DIV RR0 R2 gt RO R1 40H DIV RRO R2 gt RO 03H R1 20H DIV RRO 20H gt RO 03H R1 80H In the first example destination working register pair RRO contains the values 10H RO and 03H R1 and register R2 contains the value 40H The statement DIV RRO R2 divides the 16 bit RRO value by the 8 bit value of the R2 source register After the DIV instruction RO contains the value 03H and R1 contains 40H The 8 bit remainder is stored in the upper half of the destination register RRO RO and the quotient in the lower half R1 6 38 ELECTRONICS 53 8245 8245 8249 8249 INSTRUCTION SET DJNZ pecrement and Jump if Non Zero DJNZ Operation Flags Format Example r dst r lt 1 If r 0 PC dst The working register being used as a counter is decremented If the contents of the register are not logic zero after decrementing the relative address is added to the program counter and contr
215. se registers including the 16 byte common working register area four 192 byte prime register area and four 64 byte set 2 area LCD data registers CPU and system control registers Mapped clock peripheral control and data registers Total Addressable Bytes ELECTRONICS 2 3 ADDRESS SPACES 53 8245 8245 8249 8249 0 0 System Set 2 Peripheral Control Registers General Purpose Register Addressing Mode Data Registers Indirect Register Indexed Mode and Stack Operations System Registers Register Addressing Mode General Purpose Register Register Addressing Mode Prime D Regi Pime ata Registers 1 Data Registers All Addressing Modes 6 All addressing modes LCD Display Reigster 00H NOTE In case of S3C8245 P8245 there are page 0 page 1 and page 4 Page 4 is for LCD display register 16 bytes Figure 2 2 Internal Register File Organization 2 4 ELECTRONICS 53 8245 8245 8249 8249 ADDRESS 5 5 REGISTER PAGE POINTER PP The S3C8 series architecture supports the logical expansion of the physical 256 byte internal register file using an 8 bit data bus into as many as 16 separately addressable register pages Page addressing is controlled by the register page pointer DFH In the S3C8245 C8249 microcontroller a paged register file expansion is implemented for LCD data registers and the register page pointer
216. sing edges Tx rising edges Rx at falling edges 3 SIO Counter Clear and Shift Start Bit No action 1 Clear 3 bit counter and start shifting 2 SIO Shift Operation Enable Bit Disable shifter and clock counter EZ Enable shifter and clock counter 1 SIO Interrupt Enable Bit Disable SIO Interrupt Enable SIO Interrupt EE 0 SIO Interrupt Pending Bit No interrupt pending Clear pending condition when write 1 Interrupt is pending ELECTRONICS 4 35 CONTROL REGISTERS 53 8245 8245 8249 8249 SPH stack Pointer High Byte D8H Set 1 nRESET Value X x x x x x x x Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Stack Pointer Address High Byte The high byte stack pointer value is the upper eight bits of the 16 bit stack pointer address SP15 SP8 The lower byte of the stack pointer value is located in register SPL D9H The SP value is undefined following a reset SPL stack Pointer Low Byte D9H Set 1 nRESET Value x x x x x x x x Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Stack Pointer Address Low Byte The low byte stack pointer value is the lower eight bits of the 16 bit stack pointer address SP7 SPO The upper byte of the stack pointer value is located in register SPH D8H The SP value is undefined following a reset 4 36 ELECTRONICS 53 8245 8245 8249 82
217. sk 0 Inte rupt Level 0 IRQ0 Enable Bit Timer A Match Capture or Overflow Disable mask 1 Enable unmask NOTE When an interrupt level is masked any interrupt requests that may be issued are not recognized by the CPU 4 10 ELECTRONICS 53 8245 8245 8249 8249 CONTROL REGISTER INTPND Interrupt Pending Register D2H Set1 Bit Identifier o5 4 3 2 a E 0 0 0 nRESET Value _ Read Write _ _ _ _ _ R W R W R W Addressing Mode Register addressing mode only 7 3 Not used for the S3C8245 C8249 2 Timer 1 Overflow Interrupt Pending Bit Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending 41 Timer 1 Match Capture Interrupt Pending Bit Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending 0 Overflow Interrupt Pending bit Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending ELECTRONICS 4 11 CONTROL REGISTERS 53 8245 8245 8249 8249 IPH instruction Pointer High Byte DAH Set 1 nRESET Value x x x x x x x x Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Instruction Pointer Address High Byte The high byte instruction pointer value is the upper eight bits of the 16 bit instruction pointer address 15 8 The lower byte of the IP address is located in the IPL regi
218. source The CPU checks the source s interrupt level The CPU generates an interrupt acknowledge signal Interrupt logic determines the interrupt s vector address The service routine starts and the source s pending bit is cleared to 0 by hardware or by software The CPU continues polling for interrupt requests INTERRUPT SERVICE ROUTINES Before an interrupt request is serviced the following conditions must be met Interrupt processing must be globally enabled El SYM 0 1 The interrupt level must be enabled IMR register The interrupt level must have the highest priority if more than one levels are currently requesting service The interrupt must be enabled at the interrupt s source peripheral control register When all the above conditions are met the interrupt request is acknowledged at the end of the instruction cycle The CPU then initiates an interrupt machine cycle that completes the following processing sequence 1 2 3 4 Reset clear to 0 the interrupt enable bit in the SYM register SYM 0 to disable all subsequent interrupts Save the program counter PC and status flags to the system stack Branch to the interrupt vector to fetch the address of the service routine Pass control to the interrupt service routine When the interrupt service routine is completed the CPU issues an Interrupt Return IRET The IRET restores the PC and status flags setting SYM O to 1 It allows the CPU to process the next i
219. stal Stabilization Time TA 25 Cosmao win Mae unt Crystal Normal Vpp 4 5V to 5 5V 1 2 sec mode Crystal Strong Vpp 3 0V to 5 5V sec mode External clock Vpp 2 0V to 5 5V 5 15 us XTn input high and low level width tyqy tyr NOTE Oscillation stabilization time tero is the time required for the oscillator to it s normal oscillation when stop mode is released by interrupts 12 1 8 Supply Voltage V Minimum instruction clock 1 4 x oscillator frequency Figure 19 8 Operating Voltage Range 19 14 ELECTRONICS
220. ster DBH IPL Instruction Pointer Low Byte DBH Set1 nRESET Value x x x x x x x x Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Instruction Pointer Address Low Byte The low byte instruction pointer value is the lower eight bits of the 16 bit instruction pointer address IP7 IPO The upper byte of the IP address is located in the IPH register DAH 4 12 ELECTRONICS 53 8245 8245 8249 8249 CONTROL REGISTER IPR Interrupt Priority Register FFH Set 1 Bank 0 nRESET Value x x x x x x x x Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 4 1 Priority Control Bits for Interrupt Groups A B and C Group priority undefined 0 1 gt gt ifo A gt B gt C B gt A gt C gt gt 4 gt gt 1 0 gt gt Group priority undefined 6 Interrupt Subgroup C Priority Control Bit IRQ6 gt IRQ7 IRQ7 gt IRQ6 E EN EN EN 5 Interrupt Group Priority Control Bit IRQ5 gt IRQ6 IRQ7 1 IRQ6 IRQ7 gt IRQ5 3 Interrupt Subgroup B Priority Control Bit IRQ3 gt IRQ4 IRQ4 gt IRQ3 ES 2 Interrupt Group B Priority Control Bit IRQ2 gt IRQ3 IRQ4 1 IRQ3 IRQ4 gt IRQ2 0 Interrupt Group Priority Control Bit IRQ0 gt IRQ1 IRQ1 gt IRQ0 je ELECTRONICS 4 1 CONTROL REGISTERS 53 8245 8245 8249 8249
221. ster bank instructions SB0 or SB1 are used to address one bank or the other A hardware reset operation always selects bank 0 addressing The upper two 32 byte areas bank 0 and bank 1 of set 1 contains 50 mapped system and peripheral control registers The lower 32 byte area contains 16 system registers DOH DFH and a 16 byte common working register area You can use the common working register area as a scratch area for data operations being performed in other areas of the register file Registers in set 1 locations are directly accessible at all times using Register addressing mode The 16 byte working register area can only be accessed using working register addressing For more information about working register addressing please refer to Chapter 3 Addressing Modes REGISTER SET 2 The same 64 byte physical space that is used for set 1 locations is logically duplicated to add another 64 bytes of register space This expanded area of the register file is called set 2 For the S3C8249 the set 2 address range COH FFH is accessible on pages 0 3 S3C8245 the set 2 address range COH FFH is accessible on pages 0 1 The logical division of set 1 and set 2 is maintained by means of addressing mode restrictions You can use only Register addressing mode to access set 1 locations In order to access registers in set 2 you must use Register Indirect addressing mode or Indexed addressing mode
222. t NOTE Because the A D converter has no sample and hold circuitry it is very important that fluctuation in the analog level at the ADCO ADCT7 input pins during a conversion procedure be kept to an absolute minimum Any change in the input level perhaps due to noise will invalidate the result If the chip enters to STOP or IDLE mode in conversion process there will be a leakage current path in A D block You must use STOP or IDLE mode after ADC operation is finished ELECTRONICS 15 1 A D CONVERTER 53 8245 8245 8249 8249 CONVERSION TIMING The A D conversion process requires 4 steps 4 clock edges to convert each bit and 10 clocks to set up A D conversion Therefore total of 50 clocks are required to complete an 10 bit conversion When fxx 8 is selected for conversion clock with an 8 MHz fxx clock frequency one clock cycle is 1 us Each bit conversion requires 4 clocks the conversion rate is calculated as follows 4 clocks bit x 10 bits set up time 50 clocks 50 clock x 1us 50 us at 1 MHz A D CONVERTER CONTROL REGISTER ADCON A D converter control register ADCON is located at address F7H in set 1 bank 0 It has three functions Analog input pin selection bits 4 5 and 6 End of conversion status detection bit 3 A D operation start or enable bit 0 After a reset the start bit is turned off You can select only one analog input channel at a time Other analog input pins ADCO ADCT7 can
223. t lt dst src The source operand is subtracted from the destination operand and the result is stored in the destination The contents of the source are unaffected Subtraction is performed by adding the two s complement of the source operand to the destination operand Flags C Setif a borrow occurred cleared otherwise Z Setif the result is 0 cleared otherwise S Setif the result is negative cleared otherwise V Setif arithmetic overflow occurred that is if the operands were of opposite signs and the sign of the result is of the same as the sign of the source operand cleared otherwise D Always set to 1 H Cleared if there is a carry from the most significant bit of the low order four bits of the result set otherwise indicating a borrow Format Bytes Cycles Opcode Addr Mode Hex dst src dst 2 4 22 r r src 6 23 r Ir opc src dst 3 6 24 R R 25 R IR opc dst src 3 6 26 R IM Examples Given R1 12H R2 03H register 01H 21H register 02H 03H register 03H OAH SUB R1 R2 gt R1 OFH R2 03H SUB R1 R2 gt R1 08H R2 03H SUB 01H 02H gt Register 01H register 02H 03H SUB 01H 02H gt Register 01H 17H register 02H 03H SUB 01H 90H gt Register 01H 91H C S and V 1 SUB 01H f65H gt Register 01H OBCH C and 5 1 V In the first example if working register R1 contains the value 12H and if register R2 contains the value 03H the statement SUB R1 R2
224. t 0 to IRQO bit 1 to IRQ1 and so on A 0 indicates that no interrupt request is currently being issued for that level A 1 indicates that an interrupt request has been generated for that level IRQ bit values are read only addressable using Register addressing mode You can read test the contents of the IRQ register at any time using bit or byte addressing to determine the current interrupt request status of specific interrupt levels After a reset all IRQ status bits are cleared to 0 You can poll IRQ register values even if a DI instruction has been executed that is if global interrupt processing is disabled If an interrupt occurs while the interrupt structure is disabled the CPU will not service it You can however still detect the interrupt request by polling the IRQ register In this way you can determine which events occurred while the interrupt structure was globally disabled Interrupt Request Register IRQ DCH Set 1 Read only IR IRQ2 IRQ3 IROS IRQ4 IRQ6 IRQ7 Interrupt level request pending bits 0 Interrupt level is not pending 1 Interrupt level is pending Figure 5 9 Interrupt Request Register IRQ ELECTRONICS 5 13 INTERRUPT STRUCTURE S3C8245 P8245 C8249 P8249 INTERRUPT PENDING FUNCTION TYPES Overview There are two types of interrupt pending bits one type that is automatically cleared by hardware after the interrupt service routine is acknowledged and executed the other that must be cle
225. t counter value into the TA data register You can select rising or falling edges to trigger this operation Timer A also gives you capture input source the signal edge at the TACAP pin You select the capture input by setting the value of the timer A capture input selection bit in the port 3 control register PSCONL set 1 bank 0 E9H When P3CONL 7 6 is 00 the TACAP input or normal input is selected When P3CONL 7 6 is set to 11 normal output is selected Both kinds of timer A interrupts can be used in capture mode the timer A overflow interrupt is generated whenever a counter overflow occurs the timer A match capture interrupt is generated whenever the counter value is loaded into the TA data register By reading the captured data value in TADATA and assuming a specific value for the timer A clock frequency you can calculate the pulse width duration of the signal that is being input at the TACAP pin 11 2 ELECTRONICS 53 8245 8245 8249 8249 8 TIMER CONTROL REGISTER You use the timer control register to Select the timer A operating mode interval timer capture mode or PWM mode Select the timer A input clock frequency Clear the timer A counter TACNT Enable the timer A overflow interrupt or timer A match capture interrupt Clear timer A match capture interrupt pending conditions TACON is located set 1 Bank 0 at address EDH and is read
226. t src opc 2 14 F3 r Given RO 7FH R6 21H and R7 LDCPI RR6 R0 RR6 lt 6 1 contents of RO is loaded into program memory location 2200H 21FFH 1H RO 7FH R6 22H R7 00H LDEPI RR6 R0 RR6 lt RR6 1 contents of RO is loaded into external data memory location 2200H 21FFH 1H RO 7FH R6 22H R7 OOH ELECTRONICS 53 8245 8245 8249 8249 LDW Load Word LDW Operation Flags Format Examples dst src dst src INSTRUCTION SET The contents of the source a word are loaded into the destination The contents of the source are unaffected No flags are affected Given src dst src Bytes Cycles Opcode Addr Mode Hex dst src 3 8 C4 RR RR C5 RR IR 4 8 C6 RR IML R4 06H R5 1CH R6 05H R7 02H register register 01H 02H register 02H and register 03H OFH LDW LDW LDW LDW LDW LDW RR6 RR4 00H 02H RR2 R7 04H 01H RR6 1234H 02H 0FEDH gt gt R6 06H R7 1CH R4 06H R5 1CH Register OOH register 01H OFH register 02H 03H register 03H OFH R2 03H R3 OFH Register 04H 03H register 05H OFH R6 12H R7 34H OEDH Register 02H OFH register O3H In the second example please note that the statement LDW 00 02 loads the contents of the source word 02H 03H in
227. tention Supply Voltage in Stop 19 7 19 7 A D Converter Electrical Characteristics 19 9 19 8 Voltage Booster Electrical Characteristics 19 10 19 9 Characteristics of Voltage Level Detect 19 10 19 10 Synchronous SIO Electrical 1 19 11 19 11 Main Oscillator Frequency fep ecce onal eed indeed 19 12 19 12 Main Oscillator Clock Stabilization Time ter mI 19 12 19 13 Sub Oscillator Frequency feo 19 13 19 14 Sub Oscillator crystal Stabilization Time tero 19 14 21 1 Descriptions of Pins Used to Read Write the 21 3 21 2 Comparison of S3P8245 P8249 S3C8245 C8249 21 3 21 3 Operating Mode Selection 21 4 21 4 D C Electrical 21 4 21 5 D C Electrical Characteristics of 53 68245 21 7 22 1 Power Selection Settings for 8245 9 22 4 22 2 Main clock Selection Settings for 8245 9 22 4 22 3 Device Selection Settings for 8245 9 22 5 22 4 The SMDS2 Tool Selection Setting
228. the second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H and register 01H 01H R1 01H 1 gt R1 O7H register 01H 01H If destination working register R1 contains the value 07H 00000111B and the source register 01H contains the value 01H 00000001B the statement R1 01H 1 compares bit one of the source register 01H and bit zero of the destination register R1 Because the bit values are not identical the zero flag bit Z is cleared in the FLAGS register OD5H ELECTRONICS 53 8245 8245 8249 8249 INSTRUCTION SET BITC Bit Complement BITC Operation Flags Format Example dst b dst b NOT dst b This instruction complements the specified bit within the destination without affecting any other bits in the destination Unaffected Set if the result is 0 cleared otherwise Cleared to 0 Undefined Unaffected Unaffected Bytes Cycles Opcode Addr Mode Hex dst NOTE Inthe second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H R11 gt R1 05H If working register R1 contains the value 07H 00000111B the statement BITC R1 1 complements bit one of the destination and leaves the value 05H 000001
229. tination operand Bit zero the LSB replaces the carry flag The value of bit 7 the sign bit is unchanged and is shifted into bit position 6 Flags Format Examples 6 80 C Set if the bit shifted from the LSB position bit zero was 1 Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Always cleared to 0 D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst 2 4 D0 R D1 IR Given Register 9AH register 02H register OBCH and 1 SRA 00H gt Register 00H OCD C 0 SRA 02H gt Register 02H 03H register 03H ODEH C 0 In the first example if general register OOH contains the value 10011010 the statement SRA OOH shifts the bit values in register right one bit position Bit zero 0 clears the flag and bit 7 1 is then shifted into the bit 6 position bit 7 remains unchanged This leaves the value 11001101B in destination register ELECTRONICS 53 8245 8245 8249 8249 INSTRUCTION SET SRP SRP0 SRP1 set Register Pointer SRP SRP0 SRP1 Operation Flags Format Examples src src src If src 1 1 and src 0 Othen RPO 3 7 lt src 3 7 If src 1 Oandsrc 0 1then RP1 3 7 lt src 3 7 If src 1 0 and src 0 Othen RPO 4 7 lt src 4 7 RPO 3 lt 0 4 7 lt src 4 7 1 3 s
230. to access locations in the internal register file or in external memory Please note however that you cannot access locations COH FFH set 1 using Indexed addressing mode In short offset Indexed addressing mode the 8 bit displacement is treated as a signed integer in the range 128 to 127 This applies to external memory accesses only see Figure 3 8 For register file addressing an 8 bit base address provided by the instruction is added to an 8 bit offset contained in a working register For external memory accesses the base address is stored in the working register pair designated in the instruction The 8 bit or 16 bit offset given in the instruction is then added to that base address see Figure 3 9 The only instruction that supports Indexed addressing mode for the internal register file is the Load instruction LD The LDC and LDE instructions support Indexed addressing mode for internal program memory and for external data memory when implemented Register File RPO or RP1 Value used in Instruction points to A OPERAND SEN d working register block Program Memory Two O Base Address Wo peran dst src x L Instruction Point to One of the Example Woking Register 1 of 8 Sample Instruction LD RO BASE R1 Where BASE is an 8 bit immediate value Figure 3 7 Indexed Addressing to Register File ELECTRONICS 3 7 ADDRESSING MODES 53 8245 8245 8249 8249 INDEXED ADDRESSING
231. to the destination word 00H 01H This leaves the value O3H in general register OOH and the value OFH in register 01H The other examples show how to use the LDW instruction with various addressing modes and formats ELECTRONICS 6 59 INSTRUCTION SET S3C8245 P8245 C8249 P8249 MULT Multiply Unsigned MULT Operation Flags Format Examples 6 60 dst src dst lt dst src The 8 bit destination operand even register of the register pair is multiplied by the source operand 8 bits and the product 16 bits is stored in the register pair specified by the destination address Both operands are treated as unsigned integers C Setif result is 255 cleared otherwise Z Setif the result is 0 cleared otherwise S Set if MSB of the result is 1 cleared otherwise V Cleared D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src src dst 3 22 84 RR R 22 85 RR IR 22 86 RR IM Given Register 00H 20H register 01H 03H register 02H 09H register O3H 06H MULT 00H 02H gt Register 00H 01H register 01H 20H register 02H 09H MULT 00H 01H gt Register register 01H 0 MULT 00H 30H gt Register 00H 06H register 01H OOH In the first example the statement MULT 00H 02H multiplies the 8 bit destination operand in the register OOH of the register pair 00H 01H by the source register 02H operand 09H The 16 bit prod
232. trical Characteristics TA 25 C to 85 C Vpp 1 8 V to 5 5 V Vgg 0 V fxx 10 MHz oscillator Figure 19 6 Serial Data Transfer Timing ELECTRONICS 19 11 ELECTRICAL DATA S3C8245 P8245 C8249 P8249 Table 19 11 Main Oscillator Frequency fosc1 TA 25 C to 85 C Vpp 1 8 V to 5 5 V Crystal External clock XIN Vpp 5 V Table 19 12 Main Oscillator Clock Stabilization Time TA 25 C to 85 C Vpp 2 0 V to 5 5 V Test Condition Vpp 2 0 V to 5 5 V Stabilization occurs when Vpp is equal to the minimum oscillator voltage range Xy input high and low level width tyq NOTE Oscillation stabilization time is the time required for the CPU clock to return to its normal oscillation frequency after a power on occurs or when Stop mode is ended by a nRESET signal The nRESET should therefore be held at low level until the time has elapsed 19 12 ELECTRONICS 53 8245 8245 8249 8249 ELECTRICAL DATA 1 fosc1 1 fosc2 XIN XT IN Figure 19 7 Clock Timing Measurement at Xi Table 19 13 Sub Oscillator Frequency fosc2 TA 25 C 85 C Vpp 1 8 V to 5 5 V Lea iat Groot tet onan e Die uno Crystal XTIN XTour Crystal oscillation frequency C1222pF C2 33pF R 39kQ i External Clock XT jy input frequency ELECTRONICS 19 13 ELECTRICAL DATA S3C8245 P8245 C8249 P8249 Table 19 14 Sub Oscillator cry
233. ts of the destination operand are incremented by one C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst opc 1 4 rE r r to F opc dst 2 4 20 R 21 IR Given RO 1BH register OCH and register 1 OFH INC RO gt RO 1CH INC 00H gt Register OOH ODH INC RO gt RO 1BH register 01H 10H In the first example if destination working register RO contains the value 1BH the statement INC RO leaves the value 1CH in that same register The next example shows the effect an INC instruction has on register OOH assuming that it contains the value OCH In the third example INC is used in Indirect Register IR addressing mode to increment the value of register 1BH from OFH to 10H ELECTRONICS 53 8245 8245 8249 8249 INSTRUCTION SET INCW Increment Word Operation Flags Format Examples NOTE dst dst dst 1 The contents of the destination which must be an even address and the byte following that location are treated as a single 16 bit value that is incremented by one C Unaffected Z Setif the result is 0 cleared otherwise S Setif the result is negative cleared otherwise V Setif arithmetic overflow occurred cleared otherwise D Unaffected H
234. tware assignable pull up 1 bit programmable I O port Input or push pull output with software assignable pull up Alternately P3 0 P3 3 can be used as TACLK TAOUT TAPWM TBPWM 1 bit programmable I O port Push pull or open drain output and input with software assignable pull up 4 0 4 7 can alternately be used as outputs for LCD SEG 1 bit programmable I O port Push pull or open drain output and input with software assignable pull up P5 0 P5 7 can alternately be used as outputs for LCD SEG ELECTRONICS 9 1 PORTS 53 8245 8245 8249 8249 PORT REGISTERS Table 9 2 gives you an overview of the register locations of all four S3C8245 C8249 I O port data registers Data registers for ports 0 1 2 3 4 and 5 have the general format shown in Figure 9 1 Table 9 2 Port Data Register Summary Register Name Mnemonic Hex Location WW Po 26 Fo Set Bano WW 9 2 ELECTRONICS 53 8245 8245 8249 8249 PORTS PORT 0 Port 0 is an 8 bit I O Port that you can use two ways General purpose I O External interrupt inputs for INTO INT7 Port 0 is accessed directly by writing or reading the port 0 data register PO at location F6H in set 1 bank 0 Port 0 Control Register POCONH POCONL Port 0 pins are configured individually by bit pair settings in two control registers located in set 1 bank 0 POCONL low byte E1H and POCONH hi
235. ubtracted from the destination operand and the appropriate flags are set accordingly The contents of both operands are unaffected by the comparison Setif a borrow occurred src gt dst cleared otherwise 7 Setif the result is 0 cleared otherwise S Setif the result is negative cleared otherwise V Setif arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src opc dst 2 4 A2 r r src 6 A3 r Ir opc src dst 3 6 A4 R R A5 R IR dst src 3 6 A6 R IM 1 Given 1 02H and R2 OSH CP R1 R2 gt Set the C and S flags Destination working register R1 contains the value 02H and source register R2 contains the value The statement CP R1 R2 subtracts the R2 value source subtrahend from the R1 value destination minuend Because a borrow occurs and the difference is negative C and S are 1 2 Given R1 05H and R2 OAH R1 R2 JP UGE SKIP INC R1 SKIP LD R3 R1 In this example destination working register R1 contains the value 05H which is less than the contents of the source working register R2 OAH The statement R1 R2 generates C 1 and the JP instruction does not jump to the SKIP location After the statement LD R3 R1 executes the value 06H remains in working register R3 ELECTRONICS 53 8245 8245 8249 8249 INSTRUCTION SET CPIJE Compare Increment and Jump on Equal CPIJE Operation
236. uct 0120H is stored in the register pair OOH 01H ELECTRONICS 53 8245 8245 8249 8249 INSTRUCTION SET NEXT Next NEXT Operation Flags Format Example Address lt IP IP lt IP 2 The NEXT instruction is useful when implementing threaded code languages The program memory word that is pointed to by the instruction pointer is loaded into the program counter The instruction pointer is then incremented by two No flags are affected Bytes Cycles Opcode Hex opc 1 10 following diagram shows example of how to use the NEXT instruction Before Data 0120 Address L Address L Address H Address H Routine Memory Memory ELECTRONICS 6 61 INSTRUCTION SET S3C8245 P8245 C8249 P8249 NOP Operation NOP Operation Flags Format Example 6 62 No action is performed when the CPU executes this instruction Typically one or more NOPs are executed in sequence in order to effect a timing delay of variable duration No flags are affected Bytes Cycles Opcode Hex 1 4 When 1 instruction NOP is encountered in a program no operation occurs Instead there is a delay in instruction execution time ELECTRONICS 53 8245 8245 8249 8249 INSTRUCTION SET OR Logical OR OR Operation Flags Format Examples dst src dst dst OR src The source operand is log
237. ue 3521H the address of the first instruction in the program sequence to be executed Assuming that the contents of the program counter and stack pointer are the same as in the first example if program address 0040H contains 35H and program address 0041H contains 21H the statement CALL 40H produces the same result as in the second example ELECTRONICS 53 8245 8245 8249 8249 INSTRUCTION SET CCF Complement Carry Flag CCF Operation Flags Format Example C NOT C The carry flag C is complemented If C 1 the value of the carry flag is changed to logic zero if C O the value of the carry flag is changed to logic one C Complemented No other flags are affected Bytes Cycles Opcode Hex opc 1 4 EF Given The carry flag 0 CCF If the carry flag the CCF instruction complements it in the FLAGS register OD5H changing its value from logic zero to logic one ELECTRONICS 6 27 INSTRUCTION SET CLR clear CLR dst Operation dst 0 Flags Format Examples 6 28 The destination location is cleared to O No flags are affected Bytes Cycles Opcode Hex opc dst 2 4 BO B1 Given Register 00H 4FH register 01H 02H and register 02H CLR 00H gt Register OOH 00H 01H gt Register 01H 02H register 02H OOH 53 8245 8245 8249 8249 Addr Mode dst R IR In Register R addressing mode the statement
238. ult set otherwise indicating a borrow Format Bytes Cycles Opcode Addr Mode Hex dst src 6 33 r Ir opc src dst 3 6 34 R R 35 R IR opc dst src 3 6 36 R IM Examples Given R1 10H R2 03H C 1 register 01H 20H register 02H 03H and register 03H OAH SBC R1 R2 gt R1 OCH R2 08H SBC R1 R2 gt R1 05H R2 register OAH SBC 01H 02H gt Register 01H 1CH register 02H SBC 01H 02H gt Register 01H 15H register 02H register OAH SBC 01H 8AH Register 01H 95H C S and V 1 In the first example if working register R1 contains the value 10H and register R2 the value 03H the statement SBC R1 R2 subtracts the source value 03H and the C flag value 1 from the destination 10H and then stores the result OCH in register R1 6 78 ELECTRONICS 53 8245 8245 8249 8249 SCF set Carry Flag SCF Operation Flags Format Example C lt 1 The carry flag C is set to logic one regardless of its previous value C Setto 1 No other flags are affected Bytes Cycles The statement SCF sets the carry flag to logic one ELECTRONICS INSTRUCTION SET Opcode Hex DF 6 79 INSTRUCTION SET S3C8245 P8245 C8249 P8249 SRA shitt Right Arithmetic SRA Operation dst dst 7 lt dst 7 C lt dst 0 dst dst n 1 n 0 6 An arithmetic shift right of one bit position is performed on the des
239. unter value used is the address of the first instruction following the CALL instruction The specified destination address is then loaded into the program counter and points to the first instruction of a procedure At the end of the procedure the return instruction RET can be used to return to the original program flow RET pops the top of the stack back into the program counter No flags are affected Bytes Cycles Opcode Addr Mode Hex dst opc dst 3 14 F6 DA opc dst 2 12 F4 IRR opc dst 2 14 D4 IA Given RO 85H R1 21H 1 47 and SP 0002H CALL 3521H SP 0000H Memory locations OOOOH 0001H where 4AH is the address that follows the instruction CALL RRO SP 0000H 0000H 0001H 49H CALL 40H gt SP 0000H 0000H 0001H 49H In the first example if the program counter value is 1A47H and the stack pointer contains the value 0002H the statement CALL 3521H pushes the current PC value onto the top of the stack The stack pointer now points to memory location 0000H The PC is then loaded with the value 3521H the address of the first instruction in the program sequence to be executed If the contents of the program counter and stack pointer are the same as in the first example the statement CALL OQRRO produces the same result except that the 49H is stored in stack location 0001H because the two byte instruction format was used The PC is then loaded with the val
240. uring the stop mode a power on reset or an external interrupt occurs to trigger the Stop mode release and oscillation starts 2 If a power on reset occurred the basic timer counter will increase at the rate of fxx 4096 If an interrupt is used to release stop mode the BTCNT value increases at the rate of the preset clock source Clock oscillation stabilization interval begins and continues until bit 4 of the basic timer counter overflows When a 4 overflow occurs the normal CPU operation resumes ELECTRONICS 10 3 BASIC 53 8245 8245 8249 8249 nRESET STOP Bits 3 2 Basic Timer Control Register Y Write 1010xxxxB to Disable Data Bus fxx 4096 fxx 1024 8 Bit Up Counter 1xx 128 Read Only nRESET Start the CPU NOTE NOTE During a power on reset operation the CPU is idle during the required oscillation stabilization interval until bit 4 of the basic timer counter overflows Figure 10 2 Basic Timer Block Diagram 10 4 ELECTRONICS 53 8245 8245 8249 8249 8 8 8 OVERVIEW The 8 bit timer is an 8 bit general purpose timer counter Timer A has three operating modes one of which you select using the appropriate TACON setting Interval timer mode Toggle output at TAOUT pin Capture input mode with a rising or falling edge trigger at the TACAP pin PWM mode TAPWM Timer
241. ust be disable Using instruction is recommended Figure 5 6 Interrupt Mask Register IMR 5 10 ELECTRONICS 53 8245 8245 8249 8249 INTERRUPT STRUCTURE INTERRUPT PRIORITY REGISTER IPR The interrupt priority register IPR set 1 bank 0 FFH is used to set the relative priorities of the interrupt levels in the microcontroller s interrupt structure After a reset all IPR bit values are undetermined and must therefore be written to their required settings by the initialization routine When more than one interrupt sources are active the source with the highest priority level is serviced first If two sources belong to the same interrupt level the source with the lower vector address usually has the priority This priority is fixed in hardware To support programming of the relative interrupt level priorities they are organized into groups and subgroups by the interrupt logic Please note that these groups and subgroups are used only by IPR logic for the IPR register priority definitions see Figure 5 7 GroupA IRQO IRQ1 GroupB IRQ2 IRQ3 IRQ3 GroupC IRQ6 IRQ7 B21 B22 C21 C22 IRQO IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 Figure 5 7 Interrupt Request Priority Groups As you can see in Figure 5 8 IPR 7 IPR 4 and IPR 1 control the relative priority of interrupt groups A B and C For example the setting 001B for these bits would select the group relationship B gt C gt A The setting 101B woul
242. voltage booster circuit provides constant LCD contrast level even though battery power supply was lowered This voltage booster include voltage regulator and voltage charge pump circuit FUNCTION DESCRIPTION The voltage booster has built for driving the LCD The voltage booster provides the capability of directly connecting an LCD panel to the MCU without having to separately generate and supply the higher voltages required by the LCD panel The voltage booster operates on an internally generated and regulated LCD system voltage and generates a doubled and a tripled voltage levels to supply the LCD drive circuit External capacitor are required to complete the power supply circuits The Vpp power line is regulated to get the Vi level which become a base level for voltage boosting Then doubled and a tripled voltage will be made by capacitor charge and pump circuit ELECTRONICS 17 1 VOLTAGE BOOSTER BLOCK DIAGRAM 17 2 Voltage Booster Voltage Regulator 1 5 V 1 3 Bias 53 8245 8245 8249 8249 VR Vict 2 x VR 3 x VR Voltage Regulator Figure 17 1 Voltage Booster Block Diagram COM0 3 3 SEG0 SEG31 i SEG0 SEG31 Voltage Booster Voltage Regulator 1 5 V 1 2 Bias and Static Figure 17 2 Pin Connection Example ELECTRONICS 53 8245 8245 8249 8249 VOLTAGE LEVEL DETECTOR VOLTAGE LEVEL DETECTOR OVERVIEW The S3C8245 C8249 micro contr
243. working register R1 In the second example destination register 01H contains the value 03H 00000011B and the source working register R1 the value 07H 00000111B The statement BOR 01H 2 R1 logically ORs bit two of register 01H destination with bit zero of R1 source This leaves the value 07H register 01H ELECTRONICS 53 8245 8245 8249 8249 INSTRUCTION SET BTJRF Bit Test Jump Relative on False BTJRF Operation Flags Format Example dst src b If src b is a 0 then PC dst The specified bit within the source operand is tested If it is a the relative address is added to the program counter and control passes to the statement whose address is now in the PC otherwise the instruction following the BTJRF instruction is executed No flags are affected Bytes Cycles Opcode Addr Mode Note 1 Hex dst src dst 3 10 37 RA rb NOTE Inthe second byte of the instruction format the source address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H BTJRF SKIP R1 3 gt PC jumps to SKIP location If working register R1 contains the value 07H 00000111B the statement BTJRF SKIP R1 3 tests bit 3 Because it is 0 the relative address is added to the PC and the PC jumps to the memory location pointed to by the SKIP Remember that the memory location must be within the allowed range of 127 to 128
244. zation Time Operating Mode 4 11 Stop Mode gt Data Retention Mode A Execution of STOP Instrction nRESET NOTE twAIT is the same as 4096 x 16 x 1 fxx Figure 19 3 Stop Mode Release Timing Initiated by nRESET ELECTRONICS 19 7 ELECTRICAL DATA S3C8245 P8245 C8249 P8249 Oscillation Stabilization Time Y 4 3 Stop Mode Idle Mode lt Data Retention Mode Execution of STOP Instruction Normal Operating Mode Interrupt is the same as 16 x BT clock Figure 19 4 Stop Mode Main Release Timing Initiated by Interrupts Oscillation Stabilization Time 11 Stop Mode T ND Ul Idle Mode Data Retention Mode Normal Execution of Operating Mode STOP Instruction Interrupt When the case of select the fxx 128 for basic timer input clock before enter the stop mode tWAIT 128 x 16 x 1 32 768 62 5 ms Figure 19 5 Stop Mode Sub Release Timing Initiated by Interrupts 19 8 ELECTRONICS 53 8245 8245 8249 8249 Table 19 7 A D Converter Electrical Characteristics TA 25 to 85 C 2 7 V to 5 5 V Vgg 0 V mew Total accuracy Vpp 5 12V AVper 5 12 V AVss 0 V Symbol Integral CPU clock 10 MHz Error Differential Linearity DLE Error Offset Error of

USER`S MANUAL

Contents

Download Pdf Manuals

Related Search

Related Contents