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1. P10 12V 1 101 GND GND 2 102 2 5V 3 103 15 5 412 104 GND 2 105 33 35V 6 106 GND 8 _ GND 43 3V 9 109 5 10 110 GND m GND 111 zi HDHAU 123 112 13 TST HDRA81 TST HDRA2 1471 114 TST HDHA3 15 HDRA83 TST HDRA4 16 m6 TST 17 _HDRAS E 18 m18 HDRA7 19 m9 _ IST HDRAS 20 120 _ 7 21 88 GND 22 122 TST 89 ST HDRATU 23 123 TST HDRA90 TST HDRATT 24 MIMA TST HDHAST 25 7 7125 _ IST HDRA13 26 26 TST_HDRASS 27 7 127 _ 94 TST HDRATS 28 128 TST HURA95 TST 29 129 ND HDRA17 30 130 _ ST HDHAT8 31 ME zl HDRATS 327 132 GND 33 _ 99 TST HDRA20 34 134 HDRA TST HDHA21 5 7485 ST 22 36 136 RATU TST HDRA23 37 437 _ TST 24 38 a38 TST 104 TST HDHAZS 39 39 5 25 40 140
2. 10GBit Ethernet SFP 2 HSSDC 2 HSSDC 2 SATA1 SATA2 5 4 SMA3 SMA2 5 1 x NE P mom 7 10GBit Ethernet SFP 1 v z gt E P A A 5 5 lt FLASH 64Mb uy a 2 LS WS NS 4096Kb x 16 FLASH 64Mb 4096Kb x16 ke TSOP48 7 0 A SDR SRAM 72Mb DDR SDRAM 1Gb 1Mb x 36 M 71 2 5V 43 16Mx 16X4 TQFP100 TSOP66 SDR SRAM 72Mb B2 154 B7 141 DDR SDRAM 1Gb 1Mb x 36 M 71 16M x 16 X 4 TQFP100 0 2 5 SSTL2 TSOP66 i XC2 SDR SRAM 72Mb 3i B3 154 B6 141 48 DDR SDRAM 1Gb 1Mb x 36 _ _ 43 16M x 16 X 4 TQFP100 2 5V SSTL2 TSOP66 SDR SRAM 72Mb DDR SDRAM 1Gb 1Mb x 36 71 gt 43 16 16 4 TQFP100 TSOP66 PCI PCI BB User IO s 996 1 lane 8 lane PCI Express Rocket IO s 180 9 pins MGT Differential Pairs 492 Figure 24 Bankout Diagram 3 FPGA Configuration The Dini Group developed the SmartMedia Configuration Environment to address the need for a space efficient pre engineered high density configuration solution for systems with single or multiple FPGA s The technology is a groundbreaking in system programm
3. Test Signal Name Connector Test Signal Name FPGA Pin Header Header J1 078 BPAN26 PAN206 J4 43 P10 78 TST 60 U17 P12 J1 079 BP4N21 P4N21 4 45 P10 79 TSL HDRAOL 117 812 1 080 BP4N20 P4N20 14 47 P10 80 TST HDRA62 U17 U5 11 081 No Connect P10 81 TST HDRA63 U17 T12 11 082 No Connect P10 82 TST HDRA64 017 012 J1 083 No Connect P10 83 TST HDRA65 U17 V12 J1 084 No Connect P10 84 TST HDRA66 U17 W12 J1 085 No Connect P10 85 TST_HDRA67 U17 Y12 J1 086 No Connect P10 86 TST_HDRAG8 U17 AA12 J1 087 No Connect P10 87 TST_HDRA69 U17 AB12 J1 088 No Connect P10 88 GND J1 089 No Connect P10 89 TST_HDRA70 U17 N12 J1 090 No Connect P10 90 TST_HDRA71 U17 K5 1 091 No Connect P10 91 TST HDRA72 U17J5 J1 092 No Connect P10 92 TST_HDRA73 U17 AK11 J1 093 No Connect P10 93 1 5V J1 094 No Connect P10 94 TST HDRA74 U17 AK12 11 095 P4NX7 J7 45 P10 95 TST HDRA75 U17 AK5 J1 096 P4NX6 17 47 P10 96 IST HDRA76 U17 AL12 11 097 No Connect P10 97 TST HDRAT7 U17 AU4 11 098 No Connect P10 98 TST 78 U17 AJ12 11 099 No Connect P10 99 GND J1 100 No Connect P10 100 12V J1 101 No Connect P10 101 GND J1 102 MBCK1 J2 27 P10 102 rsr HDRA U17 AP22 11 103 No Connect P10 103 1 5V J1 104 MBCKO 2 28 10 104 GND DN6000K10SE User Guide www dinigroup com 146
4. DN6000K 10SE User Guide www dinigroup com 99 BOARD HARDWARE Signal Name FPGA Pin SSRAM SRAM1_DQC6 U17 K9 08 12 5 1 U17 L9 U8 13 SRAM1_DQD0 U17 M9 U8 18 SRAM1_DQD1 U17 N9 18 19 SRAM1_DQD2 U17 L10 U8 22 SRAM1_DQD3 U17 M10 U8 23 SRAM1_DQD4 U17 N10 U8 24 SRAM1_DQD5 U17 P10 08 25 SRAM1_DQD6 U17 M11 U8 28 SRAM1_DQD7 U17 N11 U8 29 SRAM1_DQPA U8 51 SRAM1_DQPB U17 R11 U8 80 SRAM1_DQPC U17 T11 U8 1 SRAM1_DQPD U17 M12 U8 30 SRAM1 GWn U17 G5 U8 88 SRAM1_LBON U17 D1 U8 31 SRAM1_OEn U17 L5 U8 86 SRAMI ZZ U17 M5 U8 64 SRAM2 0 U17 N2 U9 37 SRAM2 A1 U17 W1 U9 36 SRAM2 A2 U17 V1 U9 35 SRAM2 A3 U17 U1 U9 34 SRAM2 4 U17 R1 U9 33 SRAM2 A5 U17 P1 U9 32 SRAM2 A6 U17 W3 U9 100 SRAM2 A7 U17 Y3 179 99 SRAM2 8 U17 AA3 U9 82 SRAM2 A9 U17 N4 U9 81 SRAM2_A10 U17 V2 U9 44 DN6000K 10SE User Guide www dinigroup com 100 BOARD HARDWARE Signal Name FPGA Pin SRAM2 A11 U17 W2 SRAM2_A12 U17 N3 SRAM2_A13 17 P3 SRAM2_A14 17 83 SRAM2 A15 17 13 SRAM2 A16 17 03 SRAM2 A17 17 02 SRAM2 A18 17 12 SRAM2 A20 SRAM2 ADSCn SRAM2 ADSPn SRAM2 ADVn SRAM2 BWAn 17 N4 SRAM2 BWBn 17 Y4 SRAM2 BWCn U17 AA4 SRAM2 BWDn U17 N5 SRAM2 BWEn U17 P5 SRAM2_CEn U17 T5 SRAM2 DQAO U17 R6 SRAM2 DQA1 U17 T6 SRAM2 DQA2 U17
5. ey 142 12 2 5 12 2 6 Connection between FPGA and the Daughter Card 143 13 MECHANIGAL v 150 APPENDIX Ha 152 1 APPENDIX AETEST INSTALLATION INSTRUCTIONSG cccsssscesssccssseccesscccssseccesecesssecesseecessscessaeecsssecesssecesssecssaeecesseceesseeceasecesssecesaeecessecessaees 152 1 1 DOS and Windows 95 98 ME using 152 1 2 Windows Versions Sa 1 3 S S ATA E A E TE A AAT 1 4 NUI EENE EEEE E NE EAE 154 2 APPENDIX AETEST BASIC C FUNCTIONS 4155 2 1 bar write byte 2 1 1 Description 155 2 12 M ES 155 2 1 3 Inu Eli uec 155 2 1 4 2 2 2 2 1 DESCTIPH 156 2 22 Pul m 156 2 253 ReturnceValuess O EEEN N 156 2 2 4 Notes 156 2 3 bar write dword 2 3 1 Description 157 2 32 Pun M 157 2 3 3 uu In RE 157 2 3 4 Notes P 2 4 WI NI 158 2 4 1 DGS C
6. U U U U U U 9 GPIO LED s 9 1 Status Indicators The DN6000K10SE uses DS1 DS2 to visually indicate the status of the board DS1 is controller by the MCU U4 and the Configuration CPLD controls DS2 DN6000K10SE User Guide Www dinigroup com 126 BOARD HARDWARE Table 32 lists the function of the GPIO LED s The LED s is number from left to right LEDO to LED7 Table 32 GPIO LED s Signal Name Description CPLD LEDOn Always Off CPLD_LED1n Indicates data transfer between SM and FPGA CPLD_LED2n 05 130 052 3 Lights when FPGA is not configured CPLD_LED3n U5 131 052 4 Lights when is active FPGA MCU_LED0n MCU_LED1n MCU_LED2n LED3n Status FPGA Successful Configuration Error during Configuration ot No FPGAs configured 9 2 FPGA GPIO LED s The DN6000K10SE provides 10 GPIO directly connected to the FPGA IO pins Table 33 lists the FPGA GPIO LED s on the DN6000K10SE and is available to the user The signals ate active LOW DN6000K10SE User Guide www dinigroup com 127 BOARD HARDWARE Table 33 FPGA GPIO LED s FPGA U17 AR30 U17 AT30 U17 AN30 U17 AP30 U17 AL30 U17 AM30 U17 AP31 U17 AR31 U17 AM31 1 Express Interface PCI Express is a high performance general purpose I O interconnect defined for a
7. 6 Connection between FPGA and External User Clock Connections 5 7 Connection between FPGA and DDR PLL Clock Driver 8 Connection between FPGA and External PPC Oscillator e 19 Connections between FPGA and Rocket IO Oscillators le 20 PPC Reset e 21 Connection between FPGA and FLASH e 22 Connection between FPGA and SRAM s e 23 Connection between FPGA and DDR SDRAM e 24 Pinout of R14K ST11 Gigabit Fiber Transceiver e 25 Connections between FPGA and R14K ST11 Gig E Fiber e 26 Connections between FPGA and Infniband HSSDC2 e 27 Connections between FPGA and SATA e 28 Connections between FPGA and SMA Connectors e 29 RocketIO e 30 CPU Debug connection to FPGA 31 Combined CPU Trace Debug connection to FPGA 12 32 GPIO LED S sinreteno i tte te P Irene 33 FPGA GPIO LED s e 34 PCI Express Connections to the FPG e 35 CDR Parameters e 36 Connection between the PCI Express connector and the FPGA 37 VoltapeIndicators detenti ees e 38 External Power Connections e 39 Connection between FPGA and the Daughter Card Headers ble 40 bat write byte Arguments ble 41 write word Arguments ble 42 bar write dword Argument ble 43 read byte Arguments ble 44 read word Arguments ble 45 read dword Arguments ble 46 dma buffer allocate Arguments ble 47
8. 27 41 141 5 6 5 28 22 142 7 TST HUHRT07 HDHAZJ 43 ST GND 44 144 109 TST 45 45 5 46 146 TST_HDRATI1 TST_HDRA3Z 47 a47 2 a 48 148 TST HDRAii3 TST HDRA34 49 TST TST HDRA35 501 150 TST 15 TST 51 151 52 52 TST HDRA38 53 53 B 54 154 GND 55 7 255 TST HDRA40 56 156 TST HDRA4T 57 157 TST HDRA42 58 458 TST 4 59 159 TST HDRA123 60 160 _ TST 124 TST 45 61 17 161 25 ST HDRA46 62 162 _ GND ST HDHAT7 63 163 _HDRAT26 48 64 164 TST 127 ST_ADRA49 65 165 DHATZE GND 66 166 5 _ 29 J 67 2167 _ ST HDHAST 68 168 _ 5 69 169 7 TSI HUHATS2 70 7 170 ADRA TST 711 a71 m 72 7 172 HDRA 5 56 73 073 E 74 D HDRAT36 HDRA58 75 75 TST HDHAT37 76 176 TST_HDRAT38 GND 4 377 LL TST HUHATSS ST HDRAGU 78 L178 ST_HDRAGT 79 7779 TST TST_HDRAG2 80 180 TSI HDRAI22 TST 6 81 181 ST HDRAT43 TST HDRA64 82 182 HDRA
9. Two bus bars MP2 and MP3 are installed to prevent flexing of the PWB They are connected to the ground plane and can be used to ground test equipment Be careful not to short any power rails or signals to these metal bars they can carry a lot of current The PCI bracket is also connected to the ground plane at each of the screw mounts Mounting holes are provided for standalone operation The DN6000K10SE conforms to the following dimensions DN6000K10SE User Guide Www dinigroup com 150 BOARD HARDWARE git 4 afa T aT af 4 1 1 3 SDmm 45 152 30 DN6000K10SE User Guide www dinigroup com 151 APPENDIX Chapter Appendix 1 Appendix A AETEST Installation Instructions 1 1 DOS and Windows 95 98 ME using DPMI Precompiled executables aetestdj exe and cwsdpmi exe are included in the CD ROM which is shipped with your DN6000K10SE Logic Emulation board under Source Code PCIE_Software aetest and Source Code PCIE_Software DJGPP respectively If the user is running DOS on a Windows 95 98 ME machine the PC must be booted using a DOS boot disk A DOS boot disk is packaged with the DN6000K10SE The user only needs to follow the steps listed below to run the DPMI version of AETEST F
10. DBG U17 E23 1 81 3 CPU Trace The CPU Trace port accesses the real time trace debug capabilities built into the PowerPC 405 CPU core Real time trace debug mode supports real time tracing of the instruction stream executed by the processor In this mode debug events used to cause external trigger events An external trace tool uses the trigger events to control the collection of trace information The broadcast of trace information occurs independently of external trigger events trace information is always supplied by the processor Real time trace debug does not affect processor performance Real time trace debug mode is always enabled However the trigger events occur only when both internal debug mode and external debug mode are disabled Most trigger events are blocked when either of those two debug modes is enabled Information on the trace debug capabilities how trace debug works and how to connect an external trace tool is available in the RISCWatch Debugger User s Guide 8 1 4 CPU Trace Connector Agilent Windriver has defined a Trace Port Analyzer port for the PowerPC 4xx line of CPU cores that combines the CPU Trace and the CPU Debug interfaces onto a single 38 pin Mictor connector This provides for high speed controlled impedance signaling x 2 Hx x 3 4 x 5 6 TRC DBG HALTn X 715 6 917 8
11. DN6000K10SE User Guide www dinigroup com 141 BOARD HARDWARE 12 2 3 Unbuffered IO The DN3000k10SD Daughter Card provides 66 unbuffered 1 O signals including 5 single ended clock signals available on headers J5 J6 and J7 The function of these signals is position dependent 12 2 4 Buffered IO The DN3000k10SD Daughter Card provides 48 buffered I O signals available on headers J3 and J4 The function of these signals is position dependent U1 U2 and U3 allow for different populating options and devices can be active or passive Active The LCV162245A is used for asynchronous communication between data buses It allows data transmission from the A to the B or from the B to the A bus depending on the logic level at the direction control DIR input The output enable OE input be used to disable the device so that the busses are effectively isolated Passive The FST163245 bus switches are used to connect or isolate two ports without providing any current sink or source capabilities Thus they generate little or no noise of their own while providing a low resistance path for an external driver The output enable OE input be used to disable the device so that the busses effectively isolated 12 2 5 LVDS IO Low voltage differential signaling LVDS is a signaling method used for high speed transmission of binary data over copper It is well recognized that the benefits of balanced data transmis
12. 8 Congratulations You have now programmed the DiN6000K10SE and successfully executed our AETEST utility to exercise various features of the DN6000K10SE DN6000K 10SE User Guide www dinigroup com 15 INTRODUCTION VIRTEX II PRO AAND ISE Chapter Introduction to Virtex l Pro and ISE l Virtex4l Pro The Virtex II Pro FPGA solution is the most technically sophisticated silicon and softwate product development in the history of the programmable logic industry The goal was to revolutionize system architecture from the ground up To achieve that objective the best circuit engineers and system architects from IBM Mindspeed and Xilinx co developed the world s most advanced FPGA silicon product Leading teams from top embedded systems companies worked together with Xilinx software teams to develop the systems software and IP solutions that enabled new system architecture paradigm The result is the first FPGA solution capable of implementing high performance system on a chip designs previously the exclusive domain of custom ASICs yet with the flexibility and low development cost of programmable logic The Virtex II Pro family marks the first paradigm change from programmable logic to programmable systems with profound implications for leading edge system architectures networking applications deeply embedded systems and digital signal processing systems It allows custom user defined system architectures to be
13. DS0 CCLK ROBOCLOCK 1 Output Divider Function Select Controls the divider function of bank 3 amp 4 CCLK of outputs Refer to Table 4 in the datasheet JP4 B7 ROBO1_DS1_CCLK ROBOCLOCK 1 Output Divider Function Select Controls the divider function of bank 3 amp 4 CCLK of outputs Refer to Table 4 in the datasheet ROBO1_FO_DCLK ROBOCLOCK 1 Output Phase Function Select Controls the phase function of bank 1 amp 2 DCLK of outputs Refer to Table 3 in the datasheet ROBO F1 DCLK ROBOCLOCK 1 Output Phase Function Select Controls the phase function of bank 1 amp 2 DCLK of outputs Refer to Table 3 in the datasheet ROBO DS0 ROBOCLOCK 1 Output Divider Function Select Controls the divider function of bank 1 amp 1 DCLK of outputs Refer to Table 4 in the datasheet ROBO1_DS1_DCLK ROBOCLOCK 1 Output Divider Function Select Controls the divider function of bank 1 amp 1 DCLK of outputs Refer to Table 4 in the datasheet JP5 B10 ROBO FS ROBOCLOCK 1 Frequency Select This input must be set according to the nominal frequency NOM Refer to Table 1 in the datasheet ROBO ROBO FBDSO 1 FBDS1 ROBOCLOCK 1 Feedback Output Phase Function Select This input determines the phase function of the Feedback Bank s QFA 0 1 outputs Refer to Table 3 in the datasheet ROBOCLOCK 1 Feedback Divider Function Select
14. FLASHO ADDRO 2 29 FLASHO_DATAO 24 DQO TFIASHO_ADDR2 23 Al 001 733 ADDR3 22 2 3 DQ2 35 DATAS FLASHO_ADDR4 21 003 38 TLASHO 20 4 004 Hio DATAS FLASHO_ADDR6 19 5 fu DQ5 745 FLASHO DATAS E 187 E DQ6 744 FLAEHU DATA ADDRE 8 7 DQ7 5 DATAB _ ADDRS 7 DQ8 32 FLASHO DATAS 5 9 54 a A0 E DQ10 FLASH0 DATATI 4 A11 d DQ11 39 DATAi2 FLASHO_ADDR13 12 hs DQ12 4 1 FLASHO DATAT3 5 ADDHI4 2 1 fu DQ13 43 FLASHO_DATAT4_ 0014 745 FLASHO_DATATS_ FLASHO ADDR16 487 15 5 0015 E 17 ADDR18 16 17 4 FLASHO_ADDR19 15 18 m FLASHO ADDR20 10 A 4 3 FLASHO_ADDR21 3 3V FIASKO ADORE 91 5 9 jpp 18 99V FLASHO_CEn m 37 3 3V FLASHO_OEn 28 2 5V WEn 11 WE 5 47 FPGA DONE 12 27 H GND FLASHO WPn 14 WP GND 46 28F640B3 TSOP48 Figure 41 FLASH Connection The Intel Advanced Boot Block Flash Memory C3 device supports read array mode operations at various IO voltages 1 8V and 3V and erase and program operations at or 12V VPP On th
15. A14 48 13 DQb5 78 SRAM1_DQb6 SRAMI A15 49 14 DQb6 775 SRAMI SRAMI A16 50 15 5 5 DQcO SRAMI A17 43 16 DQc0 3 SRAM1_DQct SRAM1 A18 42 17 DQc SRAMI DQc2 A19 39 se 7 SRAM1 DQc3 SRAM1 A20 38 A20 Dos 418 DQc4 c 9 SRAM1 DQc5 SRAMi ADVn 83 c5 12 SRAM1_DQc 6 SRAMI ADSPn 84 ADV DQc6 13 SRAM1_DQc7 SRAMI ADSCn 85 P 18 SRAMI 0090 SC DQd0 19 SRAM1_DQdt SRAMi BWAn 93 0991 722 SRAMI 5092 SRAMI BWBn 94 Wed DQd2 53 SRAMI DQd3 SRAMI BWCn 95 DQd3 724 SRAMI DQd4 SRAMI BWDn 96 DQd4 25 SRAM1_DQd5 WEd 0995 28 5 6 SRAM1_BWEn 87 0096 259 SRAM1_DQd7 SRAMi GWn 88 0997 G LSL SBAMI SRAM1 LBOn 31 8 89 MODE LBO am SRAMI Dare SRAM1_CEn 97 14 SRAMI 2 972 2 NC 16 CE2 NC SRAM1_OEn 86 zE SRAM1_ZZ 64 22 15 3 3V vss VDD vss VDD vss VDD vss ve vss VDDQ vss VDDQ vss VDDQ vss VDDQ vss VDDQ vss VDDQ CYTCi48iV3S TGFP100 Figure 42 SSRAM Connection The SSRAW s can be stuffed with the following options e Pipelined Flow through Pipelined with NoBL Flow through with NoBL Pipelined ZBT Flow trough
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17. c Ci Ci c c c Ci c c Ci Ci c c Ci Ci GGG DN6000K10SE User Guide www dinigroup com 116 BOARD HARDWARE Signal Name FPGA Pin DDRSDRAM DDR 7B U17 Y34 U28 13 DDR 7B DATAS U17 W33 28 54 DDR 7B DATA9 U17 W34 28 56 DDR 7B DATA10 U17 V31 28 57 DDR_7B_DATA11 U17 U32 28 59 DDR_7B_DATA12 U17 V32 28 60 U U DDR_7B_DATA13 17 V33 28 62 DDR_7B_DATA14 17 U31 28 63 28 65 28 51 28 16 28 47 28 20 28 26 28 27 28 22 28 44 28 24 28 25 28 21 DDR 7B DATA15 U17 T31 DDR_FPGA_7B_UDQS U17 V36 DDR_FPGA_7B_LDQS U17 Y40 DDR_FPGA_7B_UDM U17 U34 DDR FPGA 7B LDM U17 W32 DDR FPGA 7B BAO 17 U36 DDR FPGA 7B 1 17 U37 DDR FPGA 7B CASn 17 R41 DDR FPGA 7B CKE 17 136 DDR FPGA 7B 17 139 DDR FPGA 7B RASn 17 137 DDR FPGA 7B WEn 17 R42 7 RocketlO Transceivers RocketIO transceivers an exciting new feature of the Virtex II Pro family These multigigabit transceivers can transmit data at speeds from 622 Mb s up to 3 125 Gb s determined be the speed grade of the part please refer to the Xilinx datasheet ate c
18. 1 11 178 P4N24 17 3 P10 178 TST HDRA140 U17 AB31 J1 179 P4N23 17 5 P10 179 TST_HDRA141 U17 AA40 J1 180 P4N22 7 7 P10 180 TST HDRA142 U17 AA39 1 181 P4N17 7 9 10 181 TST HDRA143 U17 A 35 J1 182 PAN16 17 11 P10 182 TST HDRA144 U17 A 36 11 193 P4N15 713 10 183 TST HDRA145 U17 AJ33 11 184 GND 12 36 10 184 GND 11 185 P4N14 J7 15 P10 185 TST_HDRA146 U17 AJ34 DN6000K10SE User Guide Www dinigroup com 149 BOARD HARDWARE Daughter Card Connections DN6000K10SE IO Connections Test Signal Name Connector Test Signal Name FPGA Pin Header Header 11 186 P4N9 17 7 10 186 TST HDRA147 U17 A 37 1 187 P4N8 1 19 10 187 TST HDRA148 U17 AJ38 11 188 P4N5 7 21 P10 188 TST HDRA149 U17 AJ41 11 189 P4N4 17 23 10 189 HDRA150 U17 AJ42 11 190 P4N1 7 25 10 190 HDRA151 U17 AJ31 J1 191 17 27 10 191 TST HDRA152 U17 AJ32 11 192 P4NX13 17 29 P10 192 TST_HDRA153 U17 AH33 11 1935 P4NX12 J7 31 P10 193 TST_HDRA154 U17 AH37 J1 194 P4NX9 J7 33 P10 194 TST_HDRA155 U17 AH38 J1 195 No Connect P10 195 GND J1 196 P4NX8 7 35 P10 196 TST HDRA156 U17 AH31 11197 P4NX3 7 37 P10 197 TST_HDRA157 UI7 AH32 11 198 P4NX2 J7 39 P10 198 TST_HDRA158 U17 AJ40 1 199 P4NX1 17 41 10 199 HDRA159 U17 AH40 11 200 P4NX0 J7 43 P10 200 TST_HDRA160 U17 AH41 13 Mechanical
19. PLLZBN DDR CLKOp gt DDR SDRAM BAM x 16 Pm BANK 1 3 0V BANK 0 3 0V DDR DDR SDRAM DDR 64M x 16 com F FPGA pa DDR gt DR XC2VP70 100 125 BANK6 25V CLKOUT DDR Pin XILINX x ele clock BUFFER DDR CLK2p CPLD 57 DDR SDRAM DDR OLK2n iude BANK 4 3 0V BANKS 30V 84486 A A 1 DDR SDRAM B ra NT DDR OSC PLLIB Do f PLLIBN xo N PETS PCIE_REFCLKp RoboClock CYBS4AV DCLKSR gt ECLK SSRAM 2M x 38 gt ATmega 1281 PCIE REFCLKn DCLKO ECC SSRAM gt 2M x98 ECLKO d CLKIN System Clock 100MHz 4 FPGA GCLKOUT sso p cous genau 2 36 Test ECLKS Header A SSRAM 2M x 38 Figure 31 Clocking Block Diagram The clocking structures for the DN6000K10SE include the following features e Two user selectable socketed oscillators X2 X3 One 48 MHz oscillator Two RoboclockII CY7B994V Multi Phase PLL Clock Buffers Exter
20. PROGRAMMING CONFIGURING THE HARDWARE protected by the application of the silver write protect sticker on the card other SmartMedia card is empty and available for user applications configure the with the reference design please skip to Starting SelectMAP Configuration Status messages are reported by the MCU via the RS232 serial port during FPGA configuration It is INOT necessary to have the serial port connection in order to configure the FPGA in SeleccMAP mode However if an error occurs duting the configuration the user would be able to identify possible problems by viewing the configuration status messages See Configuring HyperTerminal on how to setup the serial port 4 1 BitFile Generation for SelectMAP Configuration Configuring the DN6000K10SE Virtex II Pro FPGA requires the generation of bit files by the Xilinx ISE tools NOTE This user guide will not be updated for every revision of the Xilinx tools so please be aware of minor differences The Xilinx ISE 6 11 revision is used here The CPLD and MCU must be programmed before executing the following instructions First a project must be created Open the Xilinx ISE Project Navigator software package Go to the File menu and select New Project A New Project dialog box will pop up shown in Figure 19 New Project x r Enter a Name and Location for the Project Project Name Project Location 0001 06 210 6000106
21. Ni on co 87332 1420 R64 1K Figure 28 CPLD Programming Header 3 2 2 Design Notes the CPLD Oscillator X1 is a 48 MHz oscillator used to clock the Configuration CPLD This part is soldered down to the PWB and is not intended to be user configurable The 48 MHz DN6000K10SE User Guide www d inigroup com 69 BOARD HARDWARE is divided down to 8 MHz in the CPLD to provide the clock for the micro controller U6 The clock signal is labeled MCU_CLK on the schematic The 48 MHz is used directly for the state machines in the Configuration CPLD for controlling the interface to the SmartMedia card The frequency of 48 MHz is interesting because it is the closest frequency to 50 MHz that can be divided by an integer to get 8 MHz The frequency 50 MHz is the fastest that the Virtex II Pro parts can be configured with SelectMap without wait states So FPGA configuration using SelectMap occurs at very nearly the fastest theoretical speed Serial and JTAG configuration of the Virtex II Pro FPGA s are back off positions only The 48 MHz clock can be divided down in the CPLD and used as a clock source to the PWB clock network CPLD_CLKOUT The signals 0 7 are general purpose IO connections between the Configuration CPLD and the FPGA ROBO LOCK 1 2 Indicates that the RoboClock 032 U33 PLL s are locked 0 3 selects the configuration mode of the FPGA refer to Tabl
22. THE SOFTWARE TOOLS CA WINNT 32 aetest_wdm exe ASIC Emulator PCI Controller Driver 49 Write Dword Same Address 22 Read Dword Same Address Write Read Dword Same Address BAR Memory Fill BAR Memory Write BAR Memory Display memory test on SSRAM 1 memory test on SSRAM 2 memory test on SSRAM 3 memory test on SSRAM 4 memory test on DDR full memory test including blockram gt memory test on FPGA block memory bar memory range test bar memory address data bitwise test Main Menu 9 gt Quit PCI BASE ADDRESS bbaie888 1 b3ai ieBBB 2 1212121211516 98000000 5 15 50 68800000 Please select option Figure 6 Memory Menu The possible Memory Menu options and their descriptions are listed below In each description an example transaction will be shown The accesses will focus on SSRAM 4 at the AETEST addtess location of 0x200000 NOTE The AETEST addtess is offset by 2 to the left when compared to the actual SSRAM address For example AETEST address 0x200000 is equivalent to the SSRAM address 0x80000 Write DWORD Opt 1 Write DWORD allows the user to write to any location in the Base Address Registers BAR All 4 gigabytes of PCI memory can be accessed A minimum of 1 to a maximum of 1024 DWORDs can be written in sequential order to the same address Figure 7 shows a typical memory write Once the option is chosen the user must input the
23. buffer free Arguments ble 48 dma_write_dword Arguments ble 49 read dword Argument ble 50 pci rdwr Arguments bl 51 DeviceloConttol Arguments eee 67 ABOUT THIS MANUAL Chapter About This Manual This User Guide accompanies the DN6000K10SE LOGIC Emulation Board For specific information regarding the Virtex II Pro parts please reference the datasheet 1 Manual Contents This manual contains the following chapters Chapter 1 About This Manual how to use this manual and additional resources Chapter 2 Getting Started contains information on the contents of the LOGIC Emulation Kit Chapter 3 Introduction to the Virtex II Pro and ISE an overview of the Vitex I platform and the software features Chapter 4 Introduction to the Software Tools information regarding test software Chapter 5 Programming Configuring the Hardware step by step information on programming and configuring the hardware Chapter 6 Board Hardware detailed description of board hardware 2 Additional Resources additional information go to http www dinigroup com The following table lists some of the resources you can access from this website You can also directly access these resources using the provided URLs Resource Description URL DN6000K 10SE User
24. 0x9000 0x9009 Smart Media Registers 0x900A OxA4PF Not Used DN6000K 10SE User Guide www dinigroup com 66 BOARD HARDWARE Address Location Ox A500 0xA504 FPGA Registers 505 Not Used 3 1 2 MCUJ TAG Interface The ATMega128L micro controller has JTAG interface that can be used for on chip debugging real time emulation and programming of FLASH EEPROM fuses and Lock Bits In order to take advantage of the JTAG interface you must have the Atmel AVR JTAG ICE kit part number ATAVRJTAGICE and AVR studio software that Atmel provides free at www atmel com The JTAG interface for the ATmega128L be accessed through four pins TMS and TDI on header P5 Header P5 as shown in Figure 25 allows for connection to MCU JT AG pins 3 3V 3 3V R66 2 0 cJTAG MCU TCK 1 cJTAG MCU TDO 3 cJTAG TMS 5 7 9 P5 PWRRSTn cJTAG MCU TDI x Figure 25 MCU JTAG Connector 3 1 3 MCU Programming Connector A programming cable for the A Tmega128L is shipped with the DN6000K10SE and mates to the MCU programming header P1 as shown in Figure 26 The programming header is used to download the files to the MCU using the AVR In System Programming Cable PWRRSTn SCK Figure 26 MCU Programming Connector 3 1 4 5232 Interface An RS232 serial port
25. Momentarily depressing the RESET push button S1 causes a narrow 100us soft reset pulse on the signal PWRRSTn If the reset push button is depressed for more than 2s and held PWRRSTn will be asserted continuously LED DS2 2 when lit means that reset is asserted refer the section describing the GPIO LED s PCI PCI X PCI Interface 43 3V 3 3 10k 5 0V MP 5 415v Reset Circuit PWRRSTR LTC1326 FPGA 42 5V XC2VP70 100 125 3 3V FPGA DONE 42 5V Reset Circuit LTC1326 5 gt MCU e ATmega128L Push Button gt ISP Interface JTAG TRSTOUTn FLASH m o M 28F640B3 CU JTAG Header CPLD XC95288XV FPGA_GRSTn PPC JTAG FLASH DEBUG PPC JTAG TRSTh PWARST 28284083 RS232 1CL3221 Note RS232 Tranceiver must be disabled during MCU programming phase in order to avoid contention on the BTXD signal pin Figure 40 Reset Topology Block Diagram Note The Serial Programming Cable SPI when connected to P1 will assert PWRRSTn The CPLD inverts the PWRRSTn signal to PWRRST that is used to disable the transmitter in the RS232 interface U5 during programming of the DN6000K 10SE User Guide www dinigroup com 88 BOARD HARDWARE Depressing the reset push button 51 causes the following sequence of events 1 Resetof the CPLD and MCU 2 R
26. Selectthe type of Top Level module for the Project Top Level Module Type EDIF z Figure 17 New Project Screen Shot Select the input files for the project refer to Figure 18 DN6000K 10SE User Guide ww w dinigroup com 49 PROGRAMMING CONFIGURING THE HARDWARE New Project xi Select the Input File for the Project Input Design rce fpgacode FPGA_SYNTH rev_1 50001 06 edf H Copy Input Design to the Project directory r Selectthe Constraint File for the Project Constraint File Budice Jack DiniGroup 50001 06 Source fpgac Copy Constraint file to the Project directory Back Next Cancel Figure 18 Input File Select the device and the design flow for the project The user must specify a project name and location The correct property values must be selected refer to Figure 19 projet Selectthe Device and Design Flow for the Project Property Name Value Device Family Virtex2P Device xc2vp70 Package 1704 Speed Grade 5 Top Level Module Type EDIF Synthesis Tool N Simulator Other Generated Simulation Language Back Cancel Figure 19 New Project Dialog Box The Project Navigator will create a new project with the required files The DINI Group prefers to use Synplicitys Synplify for synthesis which is recommended for the user a
27. 8 Click OK button 9 Enter the location of the CPLD JED file in the window prompting the file name and click OK The following window would be displayed DN6000K 10SE User Guide www dinigroup com 41 PROGRAMMING CONFIGURING THE HARDWARE untitled Configuration Mode iMPACT File Edit View Mode Operations Output Help D s Hu Boundary Scan Slave SelectMAP Desktop Configuration Right click device to select operations xc95288xv cpld jed For Help press F1 Configuration Mode Boundary Scan Parallel IV 4 Note The device selected should be XC95288XV 10 Select the device right click and select Program option 11 Select the Erase before programming and the Erase option before clicking the OK button DN6000K 10SE User Guide Www w dinigroup com 42 PROGRAMMING CONFIGURING THE HARDWARE Program Options 7 Program Load EPGA Secure Mode Parallel Mode 7 Program Key F Use D4 for Usercode 8 Hex Digits 7 PLA UES Enter up ta 12 The device will be programmed with the file selected If programming was successful the following window will appear DN6000K10SE User Guide www dinigroup com 43 PROGRAMMING CONFIGURING THE HARDWARE untitled Configuration Mode File Edit View Mode Operations Output Help D s Hu
28. Command Prompt aetest_wdm exe Bar Number 0 52 8 Address Chex gt 8128088808 1 Display result 2 Display result and loop indefinitely 3 Don t display result and loop indefinitely lease select 1 esult abcdef45 it a key to continue Figure 8 Memory Read DWORD Figure 8 shows a read of the DWORD from address 0x200000 of SSRAM 4 This read retrieves the data xabcdef45 written in the Write DWORD section See Figure 7 Write Read DWORD Opt 3 Write Read DWORD allows the user to write a DWORD to any location in the Base Address Registers BAR Then the function read back the data stored from the same address Akin to the previous DWORD operation all 4 gigabytes of PCI memory can be accessed Figure 9 shows a typical memory write read operation The user will be prompted once the option is chosen for the BAR to be accessed Then the memory location in hex is required AETEST will prompt the user for the number of DWORDs to write in decimal Each DWORD must be individually entered Finally the user must choose a display option 1 Following the write AETEST will read the DWORD stored at the specified address and display it 2 Sameasoption 1 however the transaction is repeated indefinitely 3 AETEST will repeatedly write then read the DWORD stored at the specified addtess DN6000K10SE User Guide www dinigroup com 30 INTRODUCTION THE SOFTWARE TOOLS 5
29. Prompt aetest_wdm exe Bar Number 5 8 Address Chex gt 812888808 umbers of long words to write Cin decimal 1 long word to write Cin hex 54fedcha 1 Display result 2 Display result and loop indefinitely 3 Don t display result and loop indefinitely lease select S4fedcha 54fedcha it a key to continue Figure 9 Memory Write Read DWORD Figure 9 shows a write read of the DWORD 0x54fedcba from address 0x200000 of SSRAM 4 Bar Memory Fill Opt 4 Memory enables to user to fill a region of PCI memory space with a data selectable pattern All 4 gigabytes of memory space is accessible Figure 10 shows a sample transaction Using Bar Memory Fill the user must first enter the BAR Number to be accessed Then the starting address must be entered in hex and the number of bytes the user wishes to fill in hex and divisible by 4 Finally the user must choose from a selection data patterns 1 Fill with 0 fill all the locations with 0x00000000 clear the memory 2 Data Address fill each DWORD with its address 3 Alternating 0x55555555 and Oxaaaaaaaa 4 OXxffffffff fill all of the memory bits 5 Data Address fill each DWORD with its address inverted DN6000K 10SE User Guide ww w dinigroup com 31 INTRODUCTION THE SOFTWARE TOOLS Command Prompt aetest wdm exe Input bar number 5 gt Input starting address Chex and 32 bit aligned 81
30. FPGA and the HFBR 5710L Gigabit Ethernet Transceiver showing the pins used on the FPGA and the HFBR 5710L Table 25 Connections between FPGA and R14K ST11 Gig E Fiber DN6000K10SE User Guide www dinigroup com 119 BOARD HARDWARE Signal Name FPGA Pin SFP1_TxDp U17 A8 SFP1_TxDn 17 49 RxDp 17 7 RxDn 17 6 SFP2 17 4 SFP2 TxDn 17 5 SFP2 RxDp 17 SFP2_RxDn 17 2 7 2 Infiniband HSSCD2 The InfiniBand Architecture is a high speed point to point serial connection standard These links can operate three levels of link performance 2 5 Gbps 10 Gbps and 30 Gbps The 2 5 Gbps connection it within the range of operation of the Virtex II Pro RocketIO For more information about InfiniBand see http www infinibandta ote home 7 2 1 FPGA to InfiniBand HSSDC2 Connector The connection between the FPGA and the InfiniBand HSSDC2 connector is fairly simple involving only four wires per connector as well as a few discrete components to provide for AC coupling of the signals These connections are shown in Table 26 Table 26 Connections between FPGA and Infniband HSSDC2 Connector 14 6 14 5 14 2 J43 J5 6 15 5 15 2 J53 DN6000K10SE User Guide Www dinigroup com 120 BOARD HARDWARE The InfiniBand connectors have different connections to the FPGA for transmit and receive differentia
31. PCIE PERn6 Pgii PCIE PETp7 EE PNE A 9 5 1 PCIE PETn7 B46 7 GND 46 C304 0 01uF PCIE PERp7 Pgii PCIE PETn7 Bae GND 447 PERp7 PCIE PRSNTh f Bag PER A4g PERM Q 01uF PCIE PERn7 Bag PRSNT2 PERN7 445 GND POL EXPRESS X8 2515 Figure 56 PCI Express Interface 10 3 1 Connection between the PCI connector and the FPGA Table 34 shows the connection between the PCI Express Edge Connector and the FPGA high speed RocketIO Table 34 PCI Express Connections to the FPGA Signal Name Connector FPGA Pin PCIE SMCLK P6 B5 U17 AU20 PCIE SMDAT P6 B6 U17 AY14 PCIE PETpO P6 B14 17 BB3 PCIE 0 P6 B15 17 BB2 cPCIE_PERp0 P6 A16 17 BB4 cPCIE_PERn0 17 5 PCIE cPCIE PERp1 17 BB8 cPCIE_PERn1 17 9 PCIE 2 U17 BB11 17 BB6 U U U U PCIE PEIp1 U17 BB7 U U U DN6000K10SE User Guide www dinigroup com 130 BOARD HARDWARE Signal Name Connector FPGA Pin PCIE 2 P6 B24 17 BB10 cPCIE_PERp2 P6 A25 17 BB12 cPCIE_PERn2 P6 A26 17 BB13 PCIE PETp3 P6 B27 17 BB15 PETn3 P6 B28 17 BB14 cPCIE_PERp3 P6 A29 17 BB16 cPCIE_PERn3 P6 A30 17 BB17 PCIE PETp4 P6 B33 17 BB19 PCIE PETn4 P6 B34 17 BB18 cPCIE_PERp4 P6 A35 17 BB20 cPCIE_PERn4 P6 A36 17 BB21 PCIB PETp5 P6 B37 17 BB23 PCIE PETn5 P6 B38 17 BB22 cPCIE_PERp5 P6 A39 17 BB24 cPCIE_PERn5 P6 A40 17 BB25 PC
32. Syncburst Flow through Figure 43 is the most straightforward type of SSRAM Write data may be accepted on the same clock cycle as the activation signal and address and read data is returned one clock cycle after it is requested Syncburst is designed to allow DN6000K10SE User Guide www dinigroup com 94 BOARD HARDWARE two conttollers to access the same SSRAM using two activation signals ADSC and ADSP an activation with ADSP requires data and byte enables one clock cycle after the address and activation Syncburst Pipelined Figure 44 1s identical except for registered outputs which delay read data an additional clock cycle but may be necessaty for high speed designs 18 2 Memory Address rm Block Register Burst Q gt Control 1 0 Control Logic Figure 43 SSRAM Flow trough Write Control 18 2 Burst 1 0 Address Register Read Control Logic Figure 44 SSRAM Pipeline Zeto Bus Turnaround ZBT SSRAM s are designed to eliminate wait states between reads and writes by synchronizing data Figure 45 accept and return data one clock cycle after the address phase and ZBT Pipeline SSRAMs Figure 46 accept and return data two clock cycles after the address phase This allows the user to begin a write burst DN6000K 10SE User Guide www dinigroup com 95 BOARD HARDWARE immediately after the last word of a read burst because read data wil
33. it is sent driven back to the FPGA The data is compared for correctness This is repeated for all test header signals DN6000K10SE User Guide www dinigroup com 37 INTRODUCTION THE SOFTWARE TOOLS Function Name Desctiption DN3000K10SD w o cables All IO signals on the DN6000K10SE are driven to ground Then the option performs a walking 1s test for all of the test header signals The test checks for shorts on the DN6000K10SE 2 Getting More Information 2 1 Printed Documentation The printed documentation as mentioned previously takes the form of a Pro datasheet and a DN6000K10SE User Guide 2 2 Electronic Documentation Multiple documents and datasheets have been included on the CD 2 3 Online Documentation There is a public access site that can be found on the Dini Group web site at http www dinigroup com DN6000K 10SE User Guide ww w dinigroup com 38 PROGRAMMING CONFIGURING THE HARDWARE Chapter Programming Configuring the Hardware This chapter details the programming and configuration instructions for the DN6000K105E 1 Programming the CPLD Code updates will be posted on the Dini Group website The user is required to purchase the Xilinx Development Tools if in house development is required The tools are available from Xilinx http www xilinx com This section lists detailed instructions for programming the CPLD using the Xilinx ISE 6 11 tools Note
34. 16V 20 3 3V 20 39 29 9202 ELEC Note Pin 14 is connected the GND PSU always ON configuration Figure 58 External Power Connection Note Header J28 is not hot plug able Do not attach power while power supply is ON DN6000K10SE User Guide www dinigroup com 134 BOARD HARDWARE 11 2 2 Power Monitors Two triple supply monitors U2 U3 are used to monitor the 1 5V 2 5V 3 3V 5 0V supplies for more information on these devices please refer to the datasheet for the LT1326 from Linear Technology These power supply monitors also provide a push button reset input that is utilized to reset the various sub circuits of the DN6000K10SE After power up PWRRSTn remains asserted for approximately 200ms 11 2 3 Power Indicators There are on the DN6000K10SE used to indicates the presence of the following voltage sources refer to Table 37 Table 37 Voltage Indicators Voltage Source 2 5V 3 3V 5V 12V 12V PWR_OK 12 Test Header amp Daughter Card Connections 12 1 Test Header The DN6000K10SE offers 200 test header P10 that allows the user connection to discrete FPGA pins refer to Figure 59 DN6000K10SE User Guide Www dinigroup com 135 BOARD HARDWARE Test Header lt lt TST CLKIN
35. All AETEST source code is included on the CD ROM shipped with your DN6000K10SE Logic Emulation kit be installed on a variety of operating systems including e DOS and Windows 95 98 ME using DPMI DOS Protected Mode Interface Windows 98 ME using a VxD driver e Windows 2000 XP Windows WDM e Windows NT e Linux e Solaris Detailed installation instructions for each version may be found in Appendix A AETEST Installation Instructions The AETEST utility program contains the following tests DN6000K10SE User Guide www dinigroup com 24 INTRODUCTION THE SOFTWARE TOOLS PCI Test Memory Tests SRAM amp DDR FLASH Test Daughter Catd Test with or without cables BAR Memory Range Tests AETEST also provides the user with the following abilities Recognize the DN6000K10SE Read FPGA F Revision Display Vendor and Device ID Set PCI Device and Function Number Display all configured PCI devices Various loops for PCI device function and ID numbers Write and Read Configuration DWORD Write DWORD Read DWORD and Write Read DWORD Same Address BAR Memory Fill Write and Display Configure Save BAR s from to a file All of AETEST s tests and functionality are based upon simple C functions Descriptions of a variety of functions may be found in Appendix B AETEST Basic Functions NOTE All of the screen captures are taken from the aetest_wdm exe implementation of the AETEST utili
36. CPLD is needed to handle the counters and state machines associated with the high speed interface to the SmartMedia card Approximately 90 of the resources of this device are utilized so 10 are available to the user The Verilog source code for the CPLD CPLD V is provided on the CD ROM The Configuration CPLD performs the following functions Interface to the Micro Controller Data Bus UPADJ0 15 Conttol Signals UP RDn WRn UP ALE Clock e Interface to the SmartMedia Data Bus SM D 0 7 DN6000K 10SE User Guide www dinigroup com 68 BOARD HARDWARE SM RDYBUSYn Data Bus DJ0 7 Control Signals SM REn SM WEn SM ALE SM CLE SM CEn FPGA Configuration Serial SelectMap Control Signals FRGA_BUSY FPGA_RD WRn FPGA_CSn FPGA_DONE FPGA_INITn FPGA_PROGn Clock FRGA_DCLK FPGA Configuration JTAG Signals FPPGA FPGA_TDI FPGA DONE TDO FPGA TMS SRAM Chip Select Generation Signal SRAM_CSn Signals FPGA_MSEL O 3 LED Indicators Signals CPLD_LEDn 0 3 GPIO to FPGA Signals FPGA_GPIOJ0 7 3 2 1 The CPLD programming header P3 FPGA Configuration MODE Select DipSwitch CPLD Programming Connector s shown in Figure 28 is used to download the files to the CPLD using the Xilinx Parallel IV cable 43 3V P3 3 3V R55 1K cJTAG_CPLD_TMS cJTAG_CPLD_TCK cJTAG CPLD TDI
37. DN6000K10SE User Guide www dinigroup com 162 APPENDIX 2 9 dma write dword dma write dword is a high level function C function which is recommended for development by users of the DN6000K10SE 2 9 1 Description dma write dword allows users of the DN6000K10SE to write a dword of data to any byte aligned location in a DMA buffer 2 9 2 Arguments The arguments for dma write dword are shown in Table 48 They are listed order Table 48 dma_write_dword Arguments Argument Description dma_buffer_handle hndl Handle for a DMA buffer int offset Offset in bytes of the write location in the DMA buffer dword data A dword 32 bit of data for the write operation typedef int dma_buffer_handle typedef unsigned char dword 2 9 3 Return Values successful function call will return zero If 2 is returned DPMI implementation of AETEST is not being used See Notes 2 9 4 Notes The dma_write_dword code is written for use in the DPMI DOS implementation of AETEST DN6000K10SE User Guide www dinigroup com 163 APPENDIX 2 10 dma read dword dma read dword is a high level function C function which is recommended for development by users of the DN6000K10SE 2 10 1 Description read dwotd allows users of the DN6000K10SE to read dword of data from any byte aligned location in a DMA buffer 2 10 2 Arguments The arguments for read dword are shown in Table 49 They are listed
38. Download and unzip the latest programming file for the MCU from the Dini Group website Processor and CPLD update http www dinigroup com 4 Run AVR Studio From the Windows START menu choose PROGRAMS Atmel AVR Studio 4 5 Cancel the Welcome to AVR Studio 4 window by clicking cancel button 6 Select TOOLS STK500 AVRISP JTAG ICE and a new window should appear 7 In the Device list select the Atmega128 and in Flash window point to the location of the MCU programming DN6000K10SE A90 LI Program Fuses LockBits Advanced Board Auto Device Erase Device Programming mode ISP Erase Device Before Programming Parallel Hiah Voltage Serial Verify Device After Programming Input HEX File data workarea dn3000K 1 Program Verify Read EEPROM Use Curent Simulator Emulator EEPROM Memory Input HEX File a Program Verify Read Flash Use Current Simulator Emulator FLASH Memory Getting revisions Hw 0x01 SW Major 0x01 SW Minor OK Getting oscillator parameters P 0 01 0 00 50 0 01 OK 8 Select the Advanced tab and read the device signature by selecting the Read Signature button DN6000K10SE User Guide www dinigroup com 45 PROGRAMMING CONFIGURING THE HARDWARE Head Wal Byte Flash Eeprom Write to Mem
39. This user guide will not be updated for every revision of the Xilinx tools so please be awate of minor differences 1 The DN6000K10SE must be powered with the Xilinx JTAG cable connected to header P3 and the other end to a parallel port on the PC 2 Download the latest programming file for the CPLD from the Dini Group website filename CPLD JED http www dinigroup com 3 RuniMPACT From the Windows START menu choose PROGRAMS Xilinx ISE 6 Accessories iMPACT 4 Select the Configure Devices option and proceed by clicking the NEXT button DN6000K 10SE User Guide ww w dinigroup com 39 PROGRAMMING CONFIGURING THE HARDWARE Operation Mode Selection x What do you want do first C Prepare Configuration Files C Load Configuration File cdf 5 Select the Boundary Scan Mode option and proceed by clicking the NEXT button Configure Devices wantto configure device via lt Boundary Scan Mode Slave Serial Mode SelectMAP Mode Desktop Configuration Mode lt Back Cancel Help 6 Select the Automatically connect to cable and identify Boundary Scan chain option and proceed by clicking the NEXT button DN6000K 10SE User Guide ww w dinigroup com 40 PROGRAMMING CONFIGURING THE HARDWARE Boundary Scan Mode Selection 7 Ifthe process was successful the following window will appear Boundary Scan Chain Contents Summary o L
40. amp Se E E EE 8 Boundary Scan Slave Serial SelectMAP Desktop Configuration xc95288xv cpld jed TDO Programming Succeeded PROGRESS END End Operation a Elapsed time 5 sec w 4 For Help press F1 Configuration Mode _ Boundary Scan Parallel IV 13 The CPLD is now programmed proceed with programming the MCU 2 Programming the MCU Code updates will be posted on the Dini Group website The user is required to purchase the Compiler if in house development is required The compiler is available http www iar com part number is EWA90PCUBLV150 In order to program the MCU install AVR Studio 407 from Atmel http www atmel com This program is freeware and 15 also included on the CD ROM The CPLD must be programmed before the MCU can be programmed see Programming the CPLD This section lists detailed instructions for programming the MCU using the AVR tools Note This user guide will not be updated for every revision of the Atmel AVR tools so please be aware of minor differences 1 The DN6000K10SE must be powered with the Atmel AVR cable connected to MCU ISP header P1 and the other end to a serial port on the PC DN6000K10SE User Guide www dinigroup com 44 PROGRAMMING CONFIGURING THE HARDWARE 2 MCU 5232 serial port is required to complete the initialization phase after the MCU has been programmed See Configuring HyperTerminal 3
41. gt Main Menu Q gt Quit PCI BASE ADDRESS 8 bbaie 1 b3ale800 Please select option Figure 15 Flash Menu The possible Flash Menu options and their descriptions are listed below Flash Display Opt 1 2 Displays Flash Memory content Flash Erase amp Program Test tests 0x10000 bytes Opt 3 4 Erase and Test the first 0x10000 bytes of the flash DN6000K10SE User Guide www dinigroup com 36 INTRODUCTION THE SOFTWARE TOOLS Flash Erase amp Program Test tests entire flash bootblock Opt 5 6 Erase and Test the entire flash including boot block this test takes approximately 5 minutes Flash Erase 0x10000 bytes Opt 7 8 Erase the first 0x10000 bytes of the flash Clear Status Opt G H Clear error status bits in case any errors occurred 1 1 6 Daughter Board Menu Upon entering the Daughter Board Menu from the Main Menu AETEST will output a screen similar to the one shown in Figure 16 Command Prompt aetest_wdm exe el Daughter Board Menu 1 DN388B8K1B8SD with cables to test connections 2 DN3888K18SD without cables to test for shorts M Main Menu Please select option m Figure 16 Daughter Board Menu The possible Daughter Board Menu options and a description can be found in Table 3 Table 5 Daughter Board Options Function Name Description DN3000K10SD w cables The FPGA outputs a signal to the Daughter Board where
42. 1 R257 lt R258 R255 lt R247 82 5 lt 82 5 82 5 lt 82 5 Figure 32 LVPECL Clock Input Terminations Note The schematic shows capacitors in locations C544 C545 C548 C549 These are actually populated with 0 ohm resistors for direct connection to the RoboClock reference inputs The terminating resistors to GDN and 3 3V are not stuffed When using LVPECL make the required hardware changes 4 2 1 Clock Source J umper Header Figure 33 shows JP3 the clock source header connector used to select between different clock soutces Clock Source Jumpers Figure 33 Clock Source Jumper DN6000K 10SE User Guide www dinigroup com 76 BOARD HARDWARE 4 3 RoboClocks Two 3 3V half can oscillator sockets X2 X3 and the signal CPLD_CLKOUT from the Configuration CPLD provide on board input clock solutions The DN6000K10SE is shipped with both a 14 318MHz X2 and 33 33MHz X3 oscillator Neither X2 nor X3 are used by the configuration circuitry so the user is free to stuff any standard 3 3 V half can oscillators in the X2 and X3 positions The oscillators interface to two high speed multi phase RoboClock buffers 4 3 1 RoboClock PLL Clock Buffers The CY7B994V U32 U33 High Speed Multi Phase PLL Clock Buffers offer user selectable control over system clock functions Each chip has 16 output clocks along with two feedback output clocks Two sets of eight output clocks are jumper sel
43. 131 TST HDRA97 U17 M35 DN6000K10SE User Guide www dinigroup com 147 BOARD HARDWARE Daughter Card Connections DN26000K10SE IO Connections Test Signal Name Connector Test Signal Name FPGA Pin Header Header J1 132 P3N80 5 41 10 132 TST HDRA98 U17 AK39 11 133 P3N79 2 3 P10 133 TST HDRA99 U17 AK40 J1 134 P3N78 J24 P10 134 TST HDRA100 U17 L39 11 135 P3N73 J2 6 P10 135 TST_HDRA101 017 138 11 136 P3N72 12 7 P10 136 TST HDRA102 017140 J1 137 P3N71 J2 33 P10 137 TST_HDRA103 U17 K40 11 138 P3N70 J2 34 P10 138 TST_HDRA104 U17 L36 J1 139 P3N65 J5 43 10 139 TST_HDRA105 017 137 J1 140 No Connect P10 140 GND 11141 P3N64 J5 45 P10 141 TST_HDRA106 U17 K42 J1 142 P3N61 J5 47 P10 142 TST_HDRA107 017 36 J1 143 P3N60 J5 49 P10 143 TST_HDRA108 U17 AK31 J1 144 P3N59 6 1 P10 144 TST HDRA109 U17 AK32 11 145 P3N58 6 3 P10 145 TST HDRA110 U17 H37 J1 146 P3N53 J6 5 P10 146 TST HDRA111 U17 D37 J1 147 P3N52 16 7 P10 147 TST HDRA112 U17 E37 J1 148 P3N51 J247 P10 148 TST HDRA113 U17 D36 J1 149 P3N50 J2 18 P10 149 TST_HDRA114 U17 E36 11 150 P3N45 16 9 P10 150 HDRA115 U17 P35 1 151 10 151 GND 11 152 P3N44 6 11 10 152 TST_HDRA116 017 32 1 153 P3N41 16 13 P10 153 5 117 U17 P31 1 154 P3N40 6 15 10 154 TST HDRA118 U
44. 2 1 2 Synthesis Synthesis is one of the most essential steps in your design methodology It takes your conceptual Hardware Description Language HDL design definition and generates the logical or physical representation for the targeted silicon device A state of the art synthesis engine is required to produce highly optimized results with a fast compile and turnaround time To meet this requirement the synthesis engine needs to be tightly integrated with the physical implementation tool and have the ability to proactively meet the design timing requirements by driving the placement in the physical device In addition cross probing between the physical design report and the HDL design code will further enhance the turnaround time Xilinx ISE provides the seamless integration with the leading synthesis engines from Mentor Graphics Synopsys and Synplicity You can use the synthesis engine of out choice In addition ISE includes Xilinx proptietary synthesis technology XST You have options to use multiple synthesis engines to obtain the best optimized result of your programmable logic design 2 1 3 Implementation and Configuration Programmable logic design implementation assigns the logic created during design entry and synthesis into specific physical resources of the target device The term place and route has historically been used to describe the implementation process for FPGA devices and fitting has been used for CPLDs Implement
45. 32 TST HDRA19 U17 H30 J1 033 No Connect P10 33 GND J1 034 BP3N76 P3N76 3 31 P10 34 TST HDRA20 U17 C30 1 035 BP3N75 P3N75 73 33 P10 35 TST_HDRA21 U17 C28 J1 036 BP3N74 P3N74 J3 35 P10 36 TST_HDRA22 U17 C29 11 037 P3N69 2 42 10 37 TST HDRA23 017 14 J1 038 P3N68 2 43 P10 38 TST HDRA24 U17 C13 1 039 BP3N67 P3N67 3 37 P10 39 TST HDRA25 017143 1 040 BP3N66 P3N66 15 59 P10 40 TST HDRA26 U17 L12 1 041 BP3N63 P3N63 J3 41 P10 41 TST HDRA27 U17 C11 1 042 BP3N62 P3N62 J3 43 P10 42 TST_HDRA28 U17 C10 1 043 BP3N57 P3N57 3 45 P10 43 TST HDRA29 U17 C9 J1 044 No Connect P10 44 GND 1 045 BP3N56 P3N56 3 47 P10 45 HDRA30 U17 AG32 11 046 No Connect P10 46 TST HDRA31 U17 AG33 1 047 No Connect P10 47 TST_HDRA32 U17 L20 1 048 BP3N49 P3N49 P10 48 TST HDRA33 U17 K20 1 049 BP3N48 P3N48 J43 P10 49 TST HDRA234 U17 M20 J1 050 P3N47 2 19 10 50 TST HDRA35 U17 M21 DN6000K10SE User Guide www dinigroup com 144 BOARD HARDWARE Daughter Card Connections DN26000K10SE IO Connections Test Signal Name Connector Test Signal Name FPGA Pin Header Header 11 051 P3N46 J2 20 P10 51 TST_HDRA36 U17 AK35 1 052 BP3N43 P3N43 45 P10 52 TST_HDRA37 U17 G19 1 053 BP3N42 P3N42 4 7 P10 53 TST
46. 5 U17 AH8 SRAM3 DQB6 017 8 SRAM3 DQB7 U17 AB9 SRAM3_DQCO U17 AC9 SRAM3_DQC1 U17 AD9 SRAM3_DQC2 U17 AF9 SRAM3_DQC3 U17 AH9 SRAM3_DQC4 017 9 SRAM3_DQC5 U17 AB10 SRAM3 DQC6 U17 AC10 SRAM3_DQC7 U17 AD10 SRAM3_DQD0 U17 AE10 SRAM3_DQD1 U17 AF10 SRAM3_DQD2 DN6000K10SE User Guide U17 AG10 Www dinigroup com Ct Ee 104 BOARD HARDWARE Signal Name FPGA Pin SRAM3 DQD3 U17 AH10 SRAM3 DQD4 U17 AJ10 SRAM3_DQD5 U17 AC11 SRAM3 DQD6 U17 AD11 SRAM3 DQD7 U17 AE11 SRAM3_DQPA U17 AF11 SRAM3_DQPB U17 AG11 SRAM3_DQPC U17 AH11 SRAM3 U17 AJ11 SRAM3 GWn 17 5 SRAM3 LBOn U17 AD1 SRAM3 OEn U17 AF6 SRAM3 ZZ U17 AG6 SRAMA 0 U17 AW1 SRAMA 1 U17 AV1 SRAMA A2 U17 AU1 SRAMA U17 AT1 SRAMA A4 U17 AP1 SRAMA 5 U17 AN1 SRAMA A6 U17 AL3 SRAMA A7 U17 AM3 SRAMA 8 U17 AN3 SRAMA 9 U17 AR3 SRAMA A10 U17 AP2 SRAMA A11 U17 AR2 SRAMA A12 U17 AT2 SRAMA A13 U17 AU2 SRAMA A14 U17 AV2 SRAMA A15 DN6000K 10SE User Guide U17 AW2 www dinigrou
47. 70 X PPC p 12 X VSENSE 13 14 PPC JTAG TCK X715 13 14 16 PPC JTAG 5 17 15 16 185 _ 19 17 18 20 X PPC JTAG 5 21 19 20 55 23 2 24 X PPC TRC TS10 26 TS20 29 27 28 50 TRO 29 30 82 152 X738 31 32 84 PPC TRC TS4 33 34 155 M 22 37 38 59 GND LOC x GND 43 GND GND Figure 55 Combined Trace Debug Connector Pinout DN6000K10SE User Guide Www dinigroup com 125 BOARD HARDWARE 8 1 5 Combined CPU Trace Debug Connection to FPGA Table 31 shows the connection between the Combined CPU Trace and Debug Port 16 The connections to the FPGA are shared with the CPU Trace and CPU Debug interfaces discussed in previous sections Table 31 Combined CPU Trace Debug connection to FPGA Signal Name FPGA Pin Connector PPC_TRC_TCK U17 E24 6 6 DBG U17 E23 16 7 VSENSB 6 12 017 024 16 41 017 023 1615 JTAG 5 U17 C24 6 17 JTAG TDI U17 C23 J6 19 PPC_JTAG_TRSTn 06 79 1621 151 U17 F20 6 24 IRC 152 U17 F19 16 26 17 20 16 28 TRC 52 17 19 16 30 TRG 7153 17 020 6 32 154 17 019 16 34 IRC 155 17 20 16 56 156 17 19 16 38
48. 9 SM_D3 13 SM D4 14 SM 05 15 SM 06 16 SM 07 27 23 28 WP CARD INS WP CARD INS GND RB LVD 2 VCC CGND VCC E21 gt SmartMedia Figure 29 SmartMedia Connector Note Do not press down on the top of the SmartMedia connector J1 if a SmartMedia card is not installed The metal case shorts 3 3V to GND 3 32 SmartMedia connection to CPLD MCU Table 11 shows the connection between the SmartMedia connector and the CPLD MCU Table 11 Connection between CPLD MCU Signal Name CPLD MPU Connector SM DO U6 26 11 6 SM D1 U6 27 1 7 SM D2 U6 28 71 8 DN6000K 10SE User Guide www dinigroup com 71 BOARD HARDWARE Signal Name CPLD MPU Connector SM D3 U6 31 J19 SM_D4 6 33 J143 SM D5 6 34 J144 SM D6 6 35 115 5 D7 6 39 J146 SM CLE U6 20 112 SM ALE U6 21 SM WEn U6 22 1 4 SM RDYBUSYn U6 40 J119 SM_WPn U6 23 15 SM CEn U6 24 11 21 SM REn U6 25 1 20 SM CDn 04 8 T H SM WP1n U4 61 127 U U U U 3 4 Boundary Scan J TAG IEEE 1532 Mode In boundary scan mode dedicated pins are used for configuring the Virtex II Pro device The configuration is done entirely through the IEEE 1149 1 Test Access Port FPGA JTAG interfaces to IO on the CPLD This allows manipulation of the data as required by the application and allows the JTAG chain to become an address on the existing bus The processor c
49. ADDR 1 U17J10 FLASH1 DATAO U17 E15 FLASH1 U17 G13 FLASH1 DATA2 U17J16 FLASH1_DATA3 U17J13 FLASH1_DATA4 U17 K13 FLASH1 DATAS U17 K16 FLASH1 DATAG U17 L16 FLASH1 U17 F17 FLASH1 DATAS U17 F13 FLASH1_DATA9 U17 H13 FLASH1 DATA10 U17 F15 FLASH1 U17 M15 FLASH1_DATA12 017 016 FLASH1 DATA13 U17 E17 FLASH1 DATA14 017 16 FLASH1_DATA15 U17 M13 FLASH1_CEn U17 F10 FLASH1 OEn U17 G16 FLASH1_WEn U17 D17 FLASH1_WPn U17 E12 ae eo c cH e ege 6 2 Synchronous SRAM The Synchronous SRAM U8 U9 U10 U11 memory components on the DN6000K10SE can accommodate up to 2Mb x 36 devices refer to Figure 42 DN6000K 10SE User Guide www dinigroup com 93 BOARD HARDWARE 08 SRAM1 A0 37 52 SRAM1 DQa0 36 0 53 SRAM1_DQa1 2 PIN 56 SRAM1 DQa2 SRAM1_A3 34 DQa2 57 _ SRAM DQa3 SRAMI 4 33 DQa3 58 SRAMI DQa4 32 4 DQa4 SRAMI DQa5 100 5 DQa5 62 DQa6 SRAM1_A7 99 6 DQa6 63 SRAMI DQa7 82 DQa7 SRAM1_DQb0 A9 81 28 0980 69 SRAMI DQbi A10 44 9 772 SRAM1 SRBAMI 45 10 DQb2 73 SRAM1_DQb3 SRAMI A12 46 11 0063 774 SRAM1_DQb4 A13 47 A12 DQb4 775 SRAM1_DQb5
50. BAR Number followed by the address within the specified BAR Then the user needs to input the number of DWORDs to be written in decimal The data to be written must be entered for each DWORD Finally the user must choose to repeat the write access indefinitely or not Pressing any key will stop a looping write DN6000K10SE User Guide www dinigroup com 28 INTRODUCTION THE SOFTWARE TOOLS 5 Prompt aetest wdm exe Bar Number 0 52 8 Address Chex 81280808808 umbers of long words to write Cin decimal 1 long word to write Cin hex abcde oop indefinitely lt or n gt it a key to continue Figure 7 Memory Write DWORD The transaction shown in Figure 7 writes the DWORD Oxabcdef45 to address 0 200000 of SSRAM 4 Read DWORD Opt 2 Read DWORD allows the user to read DWORD from any location in the Base Address Registers BAR Figure 8 shows a typical memory read Once the option is chosen the user must input the Bar Number followed by the address location Then the user is given three options 1 AETEST will read DWORD stored at the specified address and display it 2 Same as option 1 however the transaction is repeated indefinitely 3 AETEST will read the DWORD stored at the specified address repeatedly Options 2 and 3 are useful for debugging read transactions DN6000K10SE User Guide www dinigroup com 29 INTRODUCTION THE SOFTWARE TOOLS
51. BREFCLK configuration uses dedicated routing resources that reduce jitter BREFCLK must enter the FPGA through dedicated clock I O BREFCLK can connect to the BREFCLK inputs of the transceiver and the CLKIN input of the DCM for creation of USRCLKs For more information refer to the Rocket IO User Guide available from the Xilinx website refclk REF_CLK_V_SEL refclk2 REFCLKSEL refclk_out to PCS and PMA brefclk brefclk2 ug024 35 091802 Figure 39 REFCLK BREFCLK Selection Logic 4 7 2 Connections between FPGA and RocketlO Clock Synthesizers The connection between the FPGA and the external oscillators are shown in Table 19 Table 19 Connections between FPGA and Rocket IO Oscillators Signal Name FPGA Pin OSCILLATOR GIGE_CLKn U17 F21 U19 15 GIGE_CLKp U17 G21 U19 14 CLKn U17 G22 U16 15 INFE CLKp U17 F22 U16 14 DN6000K 10SE User Guide www dinigroup com 87 BOARD HARDWARE 4 8 PCI Express Clock Refer to PCI Express Interface section of this manual 5 Reset Topology 5 1 DN6000K10SE Reset The voltage monitor devices from Linear Technology P N LTC1326 U3 U2 allow push button reset function that is used to reset the DN6000K10SE Figure 40 shows the distribution of the reset signal PWRRSTn In addition to controlling the reset the power supplies rails 1 5V 2 5V 3 3V and 5V are monitored for under voltage conditions that will cause the assertion of the PWRRSTn signal
52. FBDIS1 DN6000K10SE User Guide ROBOCLOCK 1 Feedback Disable This input controls the state of QFA 0 1 When HIGH the QFA 0 1 is disabled to the HOLD OFF or HI Z state the disable state is determined OUTPUT MODE When LOW the 0 1 is enabled ww w dinigroup com 10 GETTING STARTED Jumper Installed Description JP5 A9 B9 ROBOCLOCK 1 Output Divider Function Select Controls the divider function of bank 1 amp 1 DCLK of outputs Refer to Table 4 in the datasheet JP5 A10 B10 REFSEL2 ROBOCLOCK 1 Output Divider Function Select Controls the divider function of bank 1 amp 1 DCLK of outputs Refer to Table 4 in the datasheet ROBOCLOCK Z2 Reference Select Input The REFSEL input controls how the reference input is configured When LOW it will use the REFA pair DCLK3 or FPGA_CLKOUT as the reference input When HIGH it will use the REFB pair PLL2BC or PLL2BNC as the reference input This input has an internal pull down JP6 B2 C2 ROBOCLOCK 2 Frequency Select This input must be set according to the nominal frequency fNOM Refer to Table 1 in the datasheet JP6 A4 B4 FBDS02 ROBOCLOCK 2 Feedback Divider Function Select These inputs determine the function of the QFAO and QFA1 outputs Refer to Table 4 in the datasheet JP6 A5 B5 FBDS12 ROBOCLOCK 2 Feedback Divider Function Select These inputs determine the function of the QFAO a
53. HDRA38 U17 AK36 1 054 BP3N39 P3N39 4 9 P10 54 TST HDRA39 1717 19 1 055 No Connect P10 55 GND 1 056 BP3N38 P3N38 4 11 10 56 TST_HDRA40 U17 M19 1 057 BP3N35 P3N35 J4 13 P10 57 TST_HDRA41 U17 L19 1 058 BP3N34 P3N34 4 15 P10 58 TST HDRA42 U17 C17 1 059 BP3N29 P3N29 4 17 P10 59 TST HDRA43 U17 C18 1 060 BP3N28 P3N28 14 19 10 60 TST_HDRA44 U17 E18 1 061 BP3N27 P3N27 4 21 P10 61 TST HDRA45 U17 AM33 1 062 BP3N26 P3N26 4 23 P10 62 TST HDRA46 U17 G18 11 063 P3N23 12 21 P10 63 TST HDRA47 U17 L18 J1 064 P3N22 2 22 P10 64 TST 48 U17 K18 1 065 BP3N19 P3N19 J4 25 P10 65 TST_HDRA49 U17 G17 J1 066 No Connect P10 66 GND 1 067 BP3N18 P3N18 J4 27 P10 67 TST_HDRA5O U17 AN34 1 068 BP3N15 P3N15 J4 29 P10 68 TST HDRAS51 U17 AF41 1 069 BP3N14 P3N14 4 31 P10 69 TST_HDRA52 017 117 11 070 P3N9 2 23 P10 70 TST HDRA53 U17 M17 J1 071 P3N8 2 24 P10 71 TST HDRA54 U17 M18 1 072 BP3N7 P3N7 4 33 P10 72 TST_HDRA55 U17 F16 11 073 BP3N6 P3N6 J4 35 P10 73 TST HDRA56 U17 E16 1 074 BP3N3 P3N3 4 37 P10 74 TST HDRA57 U17 H16 11 075 BP3N2 P3N2 4 39 P10 75 TST HDRASS8 U17 C15 1 076 BP4N27 P4N27 4 41 P10 76 TST HDRA59 U17 C14 J1 077 No Connect P10 77 GND DN6000K10SE User Guide Www dinigroup com 145 BOARD HARDWARE Daughter Card Connections DN26000K10SE IO Connections
54. HyperTerminal Main Menu Options Option Function Description 1 Configure FPGA sin The FPGA will configure in Select MAP mode You can also Using main txt as press the reset button S1 to reconfigure the FPGA in Select the Configuration File MAP mode 2 Interactive FPGA This option takes you to a menu titled Interactive configuration menu Configuration Menu and allows the FPGA to be configured through a set of menu options instead of using the main txt file The menu options are described in 3 Check Configuration This option checks the status of the DONE pin and prints out Status whether or not the FPGA s have been configured along with the file name that was used for configuration DN6000K 10SE User Guide ww w dinigroup com 57 PROGRAMMING CONFIGURING THE HARDWARE Function Description Select file to use in By default the processor uses the file main txt to get the name place of main txt of the bit file to be used for configuration as well as options for the configuration process However a user can put several files that follow the format for main txt on the SmartMedia card that contain different options for the configuration process By selecting the main menu option 4 the user can select a file from a list of files that should be used in place of main txt After selecting a new file to use in place of main txt the user should select Main Menu option 1 to configure the FPGA s according
55. P2 is provided for low speed communication with the MCU The RS 232 standard specifies output voltage levels between 5 to 15 Volts for logical 1 and 5 to 15 Volts for logical 0 Input must be compatible with voltages in the range of 3V to 15V for logical 1 and 3V to 15V for logical 0 This ensures data bits are read correctly even at maximum cable lengths between DTE and DCE specified as 50 feet DN6000K10SE User Guide www dinigroup com 67 BOARD HARDWARE The RS 232 standard has two primaty modes of operation Data Terminal Equipment and Data Communication Equipment These can be thought of as host PC for DTE and as peripheral for DCE The DN6000K10SE operates in the DCE mode only Figure 27 shows the implementation of the serial port on the DN6000K10SE BTXD 43 3V Eu T tiout H x 2 RIOUT ain 3 EN FOCE e mE asaya EN 42 tx FORCEON INVALID 9 C3 0 1uF 2 V 3 Gi v 8 no vee J c 6 0 1uF 0 tuF c2 0 1uF S ae ICC3221 Figure 27 MCU Serial Port There two signals attached to the MCU e Transmit Data e Receive Data TXD and RXD provide bi directional transmission of transmit and receive data No hardware handshaking is supported 3 2 Configuration CPLD The Xilinx XC95288XV U6
56. PERnO PRSNT2 SPUR FER 0259 SUE T PCIE T B19 GND GND PCIE PCIE 1 B20 RSVD A20 C268 0 01 PCIE Pgii PCIE PETn1 BEH PETRI GND FAST cPCIE_PERp Tbe oND 1 A27 CPCIE PERNT_C269 Q 01uF PCIE PERn PCIE PETp2 B23 GND PERn1 7323 2911 PCIE 2 PCIE PET B24 PETp2 GND C274 0 01 PCIE PERp2 PCIE PETRA B25 2 GND A25 f cPCIE 2 PERp2 A26 cPCIE PEHn2 C275 0 01 PCIE PERn2 Pgi PCIE PETp3 827 2 Pgii PCIE PETn3 PETRS Eg GND PERp3 PERIES GND PERp3 PCIE PERn3 30 Revo Peng n3 C276 0 010 PER Bao PRSNT2 GND Hass Pgii PCIE 4 B38 Revo A333 P911 PCIE PETRA 4 4 FOND 6279 0 01 PCIE PERp4 835 A35 cPCIE 1 836 PERp4 A36 CPCIE PERNA C278 0 01 PCIE PERn4 11 PCIE 5 837 POND Patt PGIE PETRS 5 B38 PEPS GND C281 Q 01uF PCIE 5 J B39 9 cPCIE PERpS GND PERpS Hago 0282 0 01uF__PCIE_PERn5 Pgii PCIE_PETp6 Poe eee B41 RED 6 nd A PCIE PETHS pi PCIE_PERp6 RETE B43 PETRS cnn cPCIE 122 Un 844 GND 6 PERS C297 0 01
57. Table 45 bat_tead_dword Arguments Argument Desctiption Possible Values unsigned long barnum BAR number to be accessed BARO 0 BARI 1 BAR2 2 BAR3 3 BAR4 4 BAR5 5 unsigned long byte offset Address Number of bytes to Ox0 bytes in mem space offset data dword data Pointer to a dword of data for the 0 00000000 read operation 32 bits typedef unsigned char dword 2 6 3 Return Values A successful function call will return zeto The dword of data read during the access is placed in the variable location pointed to by data 2 6 4 Notes The source code for bar read dword is portable to each of the operating systems intended for AETEST usage DN6000K10SE User Guide ww w dinigroup com 160 APPENDIX 2 7 dma buffer allocate dma buffer allocate is a high level function C function which is recommended for development by users of the DN6000K10SE 2 7 1 Description buffer allocate allows users of the DN6000K10SE to allocate DMA buffer 2 7 2 Arguments The arguments for dma buffer allocate are shown in Table 46 They are listed in order Table 46 dma buffer allocate Arguments Argument Description buffer handle hndl Pointer to a handle int for the allocated DMA buffer int nbytes Number of bytes of memory to allocate int phy_addr Pointer to an int specifying the physical address of the DMA buf
58. U6 SRAM2 DQA3 U17 W6 SRAM2 DQA4 U17 Y6 SRAM2 DQA5 U17 AA6 SRAM2 DQAG6 U17 P7 SRAM2 DQA7 U17 T7 SRAM2 DQBO 017107 SRAM2 DQB1 U17 V7 17 2 17 4 17 04 1714 U U U U U U SRAM2 A19 U17 R2 U U U U U U eH eae CIC GIG ere DN6000K10SE User Guide www dinigroup com 101 BOARD HARDWARE Signal Name FPGA Pin SSRAM SRAM2 DOB2 U17 W7 09 72 SRAM2 DQB3 U17 Y7 0973 SRAM2 DOQB4 U17 AA7 U9 74 SRAM2 DQB5 U17 P8 U9 75 SRAM2_DQB6 U17 R8 U9 78 SRAM2_DQB7 U17 T8 U9 79 SRAM2 U17 U8 U9 2 SRAM2_DQC1 U17 V8 9 5 SRAM2 DQC2 U17 W8 U9 6 SRAM2 DQC3 U17 P9 U9 7 SRAM2_DQC4 U17 R9 U9 8 SRAM2_DQC5 U17 U9 U9 9 SRAM2_DQC6 U17 W9 119 12 SRAM2 DQC7 U17 Y9 U9 13 SRAM2 DQDO U17 AA9 0918 SRAM2 DQD1 U17 R10 19 19 SRAM2 DQD2 U17 T10 09 22 SRAM2 DQD3 U17 U10 U9 23 SRAM2 DOD4 U17 V10 9 24 SRAM2 DQD5 U17 W10 U9 25 SRAM2_DQD6 U17 V5 09 28 SRAM2 DQD7 U17 AA10 19 29 SRAM2 U17 U11 U9 51 SRAM2 DOQPB U17 V11 U9 80 SRAM2 DOPC U17 W11 09 1 SRAM2 DOPD U17 Y11 009 30 SRAM2 GWn U17 R5 U9 88 SRAM2 LBOn U17 N1 U9 31 SRAM2 OEn U17 W5 U9 86 DN6000K10SE User Guide www dinigroup com 102 BOARD HARDWARE Signal Name FPGA Pin SRAM2 ZZ U17 P6 SRAM3 0 U17
59. aetest_wdm exe NOTE To compile aetest_wdm exe the user must use Visual C 6 0 setupapi lib in version 5 0 does not contain all of the necessary functions 1 3 Linux This version of AETEST has been tested on Red Hat Linux 7 2 kernel version 2 4 x The driver file dndev o and its source code are included the DN6000K10SE CD ROM The scripts dndev_load and dndev unload which are also included the CD ROM used to load and unload the driver Follow the procedures listed below for installation 1 2 Login as root to start the driver and run the program Load the driver type sh dndev load Unload the driver type sh dndev unload After the driver is loaded run the utility aetest_linux The usert may need to run chmod on aetest linux to make it executable y type chmod aetest linux DN6000K10SE User Guide ww w dinigroup com 153 APPENDIX NOTE All text files including scripts are DOS text format with an extra carriage return character after every new line they must be converted 1 4 Solaris The utility and driver are tested on Solaris 7 0 Sparc with the 32 bit kernel Follow the procedures listed below for installation 1 Login as root to install and run AETEST 2 Go to the driver directory make sure the driver file dndev is in the sparc sub directory 3 install the driver run sh dndev install sh 4 To uninstall the driver run sh dndev_uninstall
60. byte is a high level function C function which is recommended for development by users of the DN6000K10SE 2 4 1 Description bar read byte allows users of the DN6000K10SE to read a byte of data from any location in the Base Address Registers BARs of PCI memory All 4 gigabytes of PCI memory is available for access 2 4 2 Arguments The arguments for bar read byte are shown in Table 43 are listed in order Table 43 read byte Arguments Argument Desctiption Possible Values unsigned long barnum BAR number to be accessed BARO 0 BARI 1 BAR2 2 BAR3 3 BAR4 4 or BAR5 5 unsigned long byte offset Address Number of bytes to bytes in mem space offset data byte data Pointer to a byte of data for the 0x00 Oxff read operation 8 bits Itypedef unsigned char byte 2 4 3 Return Values successful function call will return zeto The byte of data read during the access is placed in the variable location pointed to by data 2 4 4 Notes The source code for bar read byte is portable to each of the operating systems intended for AETEST usage DN6000K10SE User Guide ww w dinigroup com 158 APPENDIX 2 5 bar read word read word is a high level function C function which is recommended for development by users of the DN6000K10SE 2 5 1 Description bar read word allows users of the DN6000K10SE to read word of data from any location
61. current driver buffers Built in DDR input and output registers Proprietary high performance SelectLink technology for communications between Xilinx devices High bandwidth data path Double Data Rate DDR link Web based HDL generation methodology SRAM based in system configuration Fast SelectMAP configuration DN6000K10SE User Guide www dinigroup com 19 INTRODUCTION VIRTEX II PRO AAND ISE o Triple Data Encryption Standard DES security option bitstream encryption o 1532 support O Partial reconfiguration o Unlimited reprogrammability o Readback capability e Supported by Xilinx Foundation and Alliance series development systems Integrated VHDL and Verilog design flows ChipScope Pro Integrated Logic Analyzer 0 13 nine layer copper process with 90 nm high speed transistors 1 5V VCCINT core power supply dedicated 2 5V VCCAUX auxiliary and VCCO powet supplies IEEE 1149 1 compatible boundary scan logic support Hip Chip and Wire Bond Ball Grid Array BGA packages in standard 1 00 mm pitch e Each device 100 factory tested 2 Foundation ISE 6 1i ISE Foundation is the industrys most complete programmable logic design environment ISE Foundation includes the industry s most advanced timing driven implementation tools available for programmable logic design along with design entry synthesis and verification capabilities With its ultra fast runtimes Pro
62. cv7c1481v33 PROGRAMMABLE CLOCK SOURCE 882 Ut lt CONTROL NE SWITCH Figure 23 DN6000K10SE Block Diagram 1 1 DN6000K10SE Functionality The components and interfaces featured on the DN6000K10SE include e 2VP70 100 Virtex II Pro FPGA Options DN6000K10SE User Guide www dinigroup com VOLTAGE SOURCES 4 62 BOARD HARDWARE e Flexible and Configurable Clocking Scheme e SmartMedia Configuration e DDRSDRAM 32M x 16 e Synchronous SRAM 512K x 32 36 e FLASH 4M x 16 e PCI Express x1 x4 or x8 1 4 or 8 lane e Two SFP Interfaces used for 10Gbit Ethernet etc Two Infiniband HSSDC 2 Interfaces Two SATA Interfaces Four Multi Gigabit Transceiver MGT channels SMA e One User Clock SMA Interface differential 200 Pin Test Header e CPU Debug and Trace Interfaces in Berg and Mictor connectors NOTE RocketIO interface speed is directly affected by the speed grade of the part Please refer to the Xilinx datasheet 2 Virtex4l Pro FPGA The Virtex II Pro FPGA is situated on the topside of the board For a detailed description of the capabilities of the Virtex II Pro FPGA refer to the datasheet on the Xilinx website 2 1 FPGA 2VP70 Facts The Virtex II Pro Pl
63. direction select and output enable on U2 and U3 respectively 12 2 1 Daughter Card LED s The LED s act as visual indicators representing the presence of active power sources D1 LED indicating 3 3 V present D2 LED indicating 5 0 V present D3 LED indicating 12 V present Under normal operating conditions all LED s should be ON DN6000K10SE User Guide Www dinigroup com 140 BOARD HARDWARE 12 2 2 Power Supply A linear power supply U4 is present to provide level shift translation functions when the board is populated with passive bus switches Resistors R10 and R11 can be used to select alternate voltage sources 5V or 3 3V respectively When used U4 must be removed in order to prevent contention The power supplies is rated as follows e 5 V power supply is rated for 1 A 3 3 V power supply is rated for 1 A 1 5 V power supply is rated for 1 A e 12 V power supply is rated for 0 5 e 12V power supply is rated for 0 5 NOTE Never populate R10 R11 simultaneously this will result in a shorting the 3 3V and 5V power supplies Header J8 allows external connection to the Power Sources refer to Table 38 for connection details Table 38 External Power Connections Pin Function Pin Function J8 1 GND J8 11 GND J8 2 5V 8 12 1 5V J8 3 GND J8 13 GND 18 4 5V J8 14 12V J8 5 GND 18 15 GND 18 6 T3 9V 18 16 T12V 18 7 GND J8 17 GND 18 8 3 3V 18 18 12V
64. in DDR SDRAM Termination The Data signals DQ the Data Strobe 005 and the Data Mask DM signals are point to point signals going from the FPGA to the DDR SDRAM components As mentioned above these signals are controlled impedance and terminated according to the DDR SDRAM specification This termination is covered below in DDR SDRAM Termination The connection of the Data the Data Strobe and the Data Mask signals between the FPGA and the DDR SDRAM components in covered in Table 23 The data data strobe and data mask signals all serve different purposes data signals self evident carrying the raw data between the chips and are bi directional The data strobe signals are responsible for actual clocking in the data on rising and falling edges of the clock Finally the data mask signals can be used to enable or disable the reading and writing of some of the bytes in a 16 bit word transaction DN6000K10SE User Guide ww w dinigroup com 111 BOARD HARDWARE Table 23 Connection between FPGA and DDR SDRAM Signal Name FPGA Pin DDR 6A ADDO 17 AF42 DDR 6A ADD1 17 AF39 DDR ADD2 17 AF36 DDR ADD3 17 AF34 DDR 6A ADD4 17 AF33 DDR ADD5 17 AF35 DDR 6A ADD6 17 AF37 Ci Ci c c Ci c Ci DDR ADDS DDR ADD9 DDR ADD10 DDR 6A ADD11 DDR ADD12 DDR 6A ADD13 17 AE38 DDR 6A DATAO 17 AE31 DDR_6A_DATA1 U17 AF32 DDR DATA2 17 2
65. in order Table 49 read dword Arguments Argument Description dma_buffer_handle hndl Handle for a DMA buffer int offset Offset in bytes of the write location in the DMA buffer dword data Pointer to a dword 32 bit of data for the read operation typedef int dma_buffer_handle typedef unsigned char dword 2 10 3 Return Values A successful function call will return zero 2 is returned the DPMI implementation of AETEST is not being used See Notes 2 10 4 Notes The dma_read_dword code is written for use in the DPMI DOS implementation of AETESI DN6000K10SE User Guide ww w dinigroup com 164 APPENDIX 2 11 pci rdwr rdwr is function used in older revisions of AETEST Users of the DN6000K10SE advised to use current functions such as write dword read dword for development 2 11 1 Description pci rdwr is the primary function for reading and writing to the Base Address Registers BARs 2 11 2 Arguments The arguments for pci rdwr are shown in Table 50 They listed in order Argument Table 50 pci rdwr Arguments Desctiption Possible Values long batnum BAR number to be accessed BARO 0 BARI 1 BAR2 2 BAR3 3 BAR4 4 BAR5 5 long byte_offset Address Number of bytes to offset data 0 0 bytes in BAR s mem space long upper data The upper 32 bits of data for a 64 bit access 0
66. in the Base Address Registers BARs of PCI memory All 4 gigabytes of PCI memory is available for access 2 5 2 Arguments The arguments for read word are shown in Table 44 They are listed in order Table 44 read word Arguments Argument Desctiption Possible Values unsigned long barnum BAR number to be accessed BARO 0 BARI 1 BAR2 2 BAR3 3 BAR4 4 BAR5 5 unsigned long byte offset Address Number of bytes to bytes in mem space offset data wotd data Pointer to a wotd of data for the 0 0000 Oxffff read operation 16 bits Itypedef unsigned char word 2 5 3 Return Values successful function call will return zeto The word of data read during the access is placed in the variable location pointed to by data 2 5 4 Notes The source code for bar read word is portable to each of the operating systems intended for AETEST usage DN6000K10SE User Guide ww w dinigroup com 159 APPENDIX 2 6 bar read dword bar read dwotrd is a high level function C function which is recommended for development by users of the DN6000K10SE 2 6 1 Description bat read dword allows users of the DN6000K10SE to read dwotd of data from any location in the Base Address Registers BARs of PCI memory All 4 gigabytes of PCI memory is available for access 2 6 2 Arguments The arguments for bar_read_dword are shown Table 45 They are listed in order
67. state of QFA 0 1 When HIGH the QFA 0 1 is disabled to the HOLD OFF or HI Z state the disable state is determined bp OUTPUT MODE When LOW the QFA 0 1 is enabled Refer to Table 5 in the datasheet This input has an internal pull down ROBO2 F0 ECLK ROBOCLOCK Z2 Output Phase Function Select Controls the phase function of bank 1 2 3 amp 4 ECLK of outputs Refer to Table 3 in the datasheet ROBO2 F1 ECLK ROBOCLOCK 2 Output Phase Function Select Controls the phase function of bank 1 2 3 amp 4 ECLK of outputs Refer to Table 3 in the datasheet ROBO2 DS0 ECLK ROBOCLOCK 2 Output Divider Function Select Controls the divider DN6000K10SE User Guide www dinigroup com 81 BOARD HARDWARE Signal Name Desctiption Connector function of bank 1 2 3 amp 4 ECLK of outputs Refer to Table 4 in the datasheet 2 051 ROBOCLOCK 2 Output Divider JP6 B10 Function Select Controls the divider function of bank 1 2 3 amp 4 ECLK of outputs Refer to Table 4 in the datasheet 4 3 3 Clock Configuration Headers Figure 35 shows JP4 JP4 and JP6 the RoboClock configuration headers RoboClock Configuration Jumpers 3 3V ROBO2 MODE ROBO 0 K ROBO1 ROBO1 Figure 35 RoboClock Configuration Jumpers 4 3 4 Useful Notes and Hints The RoboClock consistently outputs 32 5MHz signals in cases of improper settings or unaccep
68. verbose level The user can change the verbose level from the current setting current level 2 NOTE If the user goes back to the main menu and configures the FPGA s using main txt the verbose level will be set to whatever setting is specified in main txt Disable Enable The user can disable or enable the sanity check depending on what sanity check for bit the current setting is files NOTE If the user goes back to the main menu and configures the FPGA s using main txt the sanity check will be set to whatever setting is specified in main txt Main menu Returns the user to the Main Menu 4 4 PCBitFile Sanity Check version of the sanity check has been compiled for use on a PC the executable 15 sanityCheck exe which be found on the CD shipped with the DN6000K10SE This allows you to run the sanity check on bit files before copying them onto the Smart Media card This PC bit file sanity check verifies that the right version of Xilinx tools was used and the bitgen options have been set correctly To run the sanity check from the command line V osanityCheck f fpga bit d s See Table 7 for command line options Table 7 Sanity Check Command Line Options Command Line Required or Optional Description Option f Required This option must be followed by the name of the bit file to perform the sanity check on d Optional This option prints out a description of the different bitgen optio
69. with the board when it is plugged into a PCI slot Instead use a molex connector from the host PC s power supply plugged into the board s molex terminal 3 Power ON the test PC and allow booting in DOS mode Note The FPGA programming will commence as soon as the DN6000K10SE is powered on if the SmartMedia card contains the necessary configuration file and bit files In general the FPGA will be programmed prior to the PCI Express devices being configured However some computers have a FastBoot or QuickBoot feature which speeds up booting process of the PC These features ate incompatible with the FPGA programming sequence of the DN6000K10SE as the FPGA may not be configured prior to PCI Express bus activity As a result the DN6000K10SE will not be recognized by the computer Workaround If the computer has a FastBoot or QuickBoot or similar feature it should be disabled Otherwise a soft reset should be performed by simultaneously pressing the CTRL ALT DELETE keys after the computer has completed the Power On Self Test POST This will allow the DN6000K10SE enough time to configure the FPGA so that the computer will recognize the DN6000K10SE device Note The PCI Express spec allows 3 3V to be within 10 But the DN6000K10SE would stay in reset if 3 3V is not within 5 So it is possible for a power supply to be PCI Express compliant but does not work with our board You can measure 3 3V at test p
70. 00000000 long lower data Data the lower 32 bits of a 64 bit access 0x00000000 int command PCI command MEM_READ 0x6 ot MEM_WRITE 0x7 int be Byte Enables 0x00 DWORD BYTE EN 0x08 int dwotdcount Number of DWORDs 1 2 int verify Verify TRUE do not verify access FALSE 2 11 3 ReturnValues 0 0 0 1 When pci rdwr is called with READ as its command argument the returned DWORD is placed into the variable access_memory_dword_read The declaration for access memory dword read is Extern unsigned long access memory dword read DN6000K10SE User Guide ww w dinigroup com 165 APPENDIX 2 11 4 Notes In a typical transaction the byte offset value will be a multiple of 4 resulting DWORD aligned read or write The PCI command will either be a Memory Read or a Memory Write where MEM READ and WRITE are define definitions used in AETEST BARx where x 0 5 are also define definitions in AETEST The byte enable be is often set to DWORD BYTE EN for 32 bit transactions dwordcount is either 1 or 2 indicating a 32 bit or a 64 bit transaction respectively Finally the parameter verify is set to TRUE when the access is to be verified If verification 15 not desired verify 15 set to FALSE DN6000K10SE User Guide ww w dinigroup com 166 APPENDIX 2 12 DeviceloControl DeviceloControl is a l
71. 17 P38 1 155 P3N37 16 17 P10 155 TST_HDRAII9 U17 P37 11 156 P3N36 16 19 10 156 HDRA120 U17 R34 11 157 P3N33 16 21 10 157 TST_HDRA121 U17 R33 1 158 P3N32 J6 23 P10 158 TST_HDRA122 U17 R38 DN6000K10SE User Guide Www dinigroup com 148 BOARD HARDWARE Daughter Card Connections DN26000K10SE IO Connections Test Signal Name Connector Test Signal Name FPGA Pin Header Header 11 159 P3N31 J2 44 P10 159 TST_HDRA123 U17 R37 J1 160 P3N30 J2 45 P10 160 TST HDRA124 U17 R32 J1 161 P3N25 10 28 P10 161 TST HDRA125 U17 R31 J1 162 No Connect P10 162 GND 11 163 P3N24 J6 27 P10 163 TST HDRA126 U17 T35 J1 164 P3N21 16 29 P10 164 TST HDRA127 U17 R35 11 165 P3N20 16 31 P10 165 HDRA128 U17 T40 11 166 P3N17 16 33 P10 166 TST HDRA129 U17 T33 J1 167 P3N16 16 35 P10 167 TST HDRA130 U17 132 11 168 P3N13 16 37 P10 168 HDRA131 017 035 11 169 P3N12 16 39 P10 169 HDRA132 U17 AK38 11 170 P3N11 12 47 P10 170 TST HDRA133 U17 AK37 1 171 P3N10 12 48 10 171 TST HDRA134 U17 W36 11 172 P3N5 J6 41 P10 172 TST HDRA135 U17 W35 11 173 No Connect P10 173 GND J1 174 P3N4 16 43 P10 174 TST HDRA136 U17 AK34 J1 175 P3N1 16 45 P10 175 TST_HDRA137 U17 AK33 11 176 16 47 P10 176 TST_HDRA138 U17 AA36 1 177 P4N25 17 P10 177 TST HDRA139 17
72. 2 POWELL OT ____ _ ___ 1 3 3125 Gbps Transceivers sse 17 1 4 FPGA Fabric 2 FOUNDATION ISE 6 11 2 1 Foundation Features 2 1 1 ire er a scere e AC ERE 2 12 Synthesis see 2 1 3 Implementation and Configuration RE 2 1 4 Board Level Intestato 3 VIRTEX II PRO EMBEDDED DEVELOPMENT KIT eese n enne nn enne 22 INTRODUCTION TO THE SOFTWARE TOOLS eere esee estne tatnen ens 24 1 EXPLORING THE SOFTWARE 0 EXHI EXHI 1 1 hee 1 1 1 Getting Started with AETEST 1 1 2 AY 1 1 3 PCT EXpfess Menu ein 1 1 4 Memory Menu e 1 1 5 Flas Menica ee an TAT EEAO EER AA E ETE E EAE A a EE EER 1 1 6 Daughter Board Menu errin ned eo ORE E RNN EA ETAT EA D enm d DER Pd EP RS 2 GETTING MORE INFORMATION 2 1 Printed Documentation 2 2 Electronic Documentation 2 3 O
73. 208888 Input number of bytes Chex and divisible by 4 Fill with 8 address data 0 55555555 Ux ffffffff data address Figure 10 BAR Memory Fill As in previous function descriptions Figure 10 shows an access of SSRAM 4 Address 0x200000 is used as the starting address and 0x80 bytes are filled Data pattern option 3 is used See option Bar Memory Display for a view of the results of this transaction Bar Memory Write Opt 5 Bat Memory Write enables to user to write a DWORD s to PCI memory space All 4 gigabytes of memory space is accessible Figure 11 shows a sample transaction Once the option is chosen the user must input the BAR Number followed by the address within the specified BAR Then the user needs to input the number of DWORDs to be written in decimal The data to be written must be entered for each DWORD DN6000K10SE User Guide www dinigroup com 32 INTRODUCTION THE SOFTWARE TOOLS Command Prompt aetest wdm exe AR 8 ffset Dword aligned gt 0 01200020 umber of Dwords 1 nter Duord Data xabcdef45_ Figure 11 Bar Memory Write The transaction shown in Figure 11 writes the DWORD Oxabcdef45 to address 0x200020 of SSRAM 4 See option Bar Memory Display for a view of the results of this transaction Bar Memory Display Opt 8 Bat Memory Display enables to user to view 160 DWORDS of PCI memory space All 4 gigabytes
74. 4 3 4 Useful Notes and Hints 82 4 3 5 Customizing the Oscillators 83 4 4 External Clocks 93 4 41 External N 83 4 4 2 Connections between FPGA and External SMA Clock 1 84 45 Clocking T 4 5 1 Clocking Methodology hoe ee NO 84 4 5 2 Connections between FPGA and DDR PLL Clock 85 46 Power PC PPC Clock see teeth 86 4 6 1 Clocking Methodology 86 4 6 2 Connections between FPGA and DDR PLL Clock Buffer 86 47 c Programmable CLOCKS 86 4 7 1 Clocking M 4 7 2 Connections between FPGA and RocketIO Clock Synthesizers E 48 PEE 5 RESET TOPOLOGY 5 1 DN6000K10SE Reset x 3 2 PP edet EN atte EE DOE RON HAIR 6 2 0 ee SERERE ERAT HARE YEAR EXE VERE ANTI 021 SEDASH osse ett s 6 1 1 FLASH Connection to the FPGA 6 2 Synchronous 6 2 1 SSRAM ConfiguratiOn 1 6 2 2 SSRAM qim 6 2 3 SRAM Termination 6 2 4 SSRAM Connection 10
75. 63 2 9 1 Description 163 2 92 ATRUMECMUS 163 2 9 3 EI NU S 163 2 9 4 Notes 163 2 10 EERE 164 2 10 1 ID ub 164 164 164 2 10 2 Arguments 2 10 3 Return Values 2 10 4 Notes 164 2 11 M 165 2 11 1 Ip sn 165 2 11 2 Arguments 165 2 11 3 Return V ales 165 2 11 4 2 12 DeviceloControl 2 12 1 2 12 2 censes PERENNE E 167 2 12 3 Return Values 2 12 4 2 12 5 Derived 169 List of Figures DN6000K105E LOGIC Eniulation Board r ton AR URS HV IE HE ROREM s 7 Figure 2 Default Jumper Setup Figure 3 DN6000K10SE Board Recognition Figure 4 DN6000K10SE Not Found Figure 5 Main Menu Figure 6 Memory Menu Figure 7 Memory Write DWORD Figure 8 Memory Read DWORD Figure 9 Memor
76. 7 is used to supply power to the 2 5V plane that supplies the VDDQ pins of the DDR SDRAM devices According to the JEDEC Specification Double Data Rate DDR SDRAM termination voltage VTT must track 50 of VDDQ over voltage temperature and noise The ML6554 031 is used as a voltage source for DDR termination Connecting the pin to the 2 5V supply allows the regulator to track the VDDQ supply refer to Figure 52 A dedicated VREF output supplies the VREF pins on the FPGA as well as on the DDR SDRAM devices and maintains a less that 40mV offset from VTT 43 3V C526 ES C131 gt 100uF 10v 10v 10V 10V 2 5V D 10 10 10 C527 G TANT TANT TANT 010 IER x H VREF IN VIT 1 251 3 3V_ R205 10K 12 aan 10 C516 4 0 001uF 5 PGND1 13 PGND2 VREF OUT ND Piar PKG GND DDR VREF 07 14 18 16 17 100K 8 97 14 18 16 R186 ML6554 PSOP16 1K Figure 52 DDR VTT Termination Regulator 6 3 6 DDR SDRAM Connection to the FPGA The DDR SDRAM memory components are connected to the FPGA on Bank 6 and Bank 7 As mentioned the connections between the FPGA and the DDR SDRAM are not homogeneous as control and address are handled differently from the data and differently from the clocks However all of these signals are controlled impedance and SSTL2 terminated The termination of these signals is covered
77. 763 954 275 251 64 444 4 eU4aBBf9 7bfdb934 lt back lt j ump gotoXB85 Cq gt uit Figure 12 Bar Memory Display The sample view shown in Figure 12 displays 160 DWORDs of SSRAM 4 data starting at address 0x200000 The data displays the results of the transactions shown in Figure 10 and Figure 11 For Figure 10 alternating DWORDS of Oxaaaaaaaa and 0x55555555 were written starting at address 0x200000 total of 0x80 128 decimal bytes of data were written Then for Figure 11 the DWORD Oxabcdef45 was written to the address 0x200020 It is clear to see the results of the Bar Memory and Bat Memory Write transactions with the Bar Memory Display function SSRAM Memory Test Opt c f SSRAM Memory Test allows the user to test one of the four SSRAMs on the DN6000K10SE DDR SDRAM Memory Test Opt h DDR SDRAM Test allows the user to test all of the DDR SDRAMs on the DN6000K10SE Full Memory Test Opt 1 DN6000K 10SE User Guide ww w dinigroup com 34 INTRODUCTION THE SOFTWARE TOOLS Pull Memory Test tests each of the four SSRAMs and the Virtex II Pro BlockRAM on the DN6000K10SE Memory Tests On FPGA Block Memory Opt n Tests entire FPGA BlockRAM Bar Memory Range Test Opt p Bar Memory Range test is a generic memory test It verifies the functionality of a user selectable range of PCI memory First it prompts the user for a BAR number a starting addre
78. A SmartMedia card is determined to be invalid if either the format of the card does not follow the SSFDC specifications or if it does not contain a file named main txt in the root directory If the configuration was successful a message stating so will appear and the Main Menu will come up Otherwise an error message will appear The LEDs on 051 052 give feedback during and after the configuration process see Table 32 for GPIO LED s for further details DN6000K 10SE User Guide ww w dinigroup com 56 PROGRAMMING CONFIGURING THE HARDWARE After the FPGA has been configured the following Main Menu will appear via the serial port refer to Figure 21 DN5000106 HyperTerminal E x Ele Edit View Transfer Help Dia 218 sole l MAIN MENU Aug 20 2003 12 33 48 Config LIB Revision 1 39 Configure FPGA s using MRIN TAT Interactive FPGA configuration menu Check configuration status Select file to use for configuration List files on Smart Media Select FPGA to program via JTAG Display Contents of a TXT file ENTER SELECTION Connected 1 06 47 Auto detect 96008 N 1 ScROLL caes Capture Print echo Figure 21 Main Menu The HyperTerminal interface gives the user an easy method for handling and monitoring the DN6000K10SE FPGA configuration 4 31 Description of Main Menu Options Table 5 describes the Main Menu options found on the HyperTerminal interface Table 5
79. AD2 SRAM3 A1 U17 AK1 SRAM3 2 U17 AJ1 SRAM3_A3 U17 AH1 SRAM3 4 U17 AF1 SRAM3 A5 U17 AE1 c Hee SRAMS3 U17 AJ3 SRAM3_A7 U17 AB4 SRAM3_A8 U17 AC4 SRAM3_A9 U17 AD4 SRAM3_A10 U17 AJ2 SRAM3 A11 U17 AB3 SRAM3 A12 U17 AC3 SRAM3 A13 U17 AD3 SRAM3 A14 U17 AF3 SRAM3 A15 U17 AG3 SRAM3 A16 U17 AH3 SRAM3 A17 U17 AH2 SRAM3 A18 U17 AG2 SRAM3_A19 U17 AF2 SRAM3_A20 U17 AE2 SRAM3_ADSCn U17 AG4 SRAM3 ADSPn U17 AF4 SRAM3_ADVn U17 AE4 SRAM3_BWAn U17 AE5 SRAM3_BWBn U17 AH12 SRAM3_BWCn U17 AF5 SRAM3_BWDn DN6000K10SE User Guide U17 AG5 Www dinigroup com 28 GG 2 103 BOARD HARDWARE Signal Name FPGA Pin SRAM3 BWEn U17 AH5 SRAM3 CEN U17 AB6 SRAM3 DQAO U17 AH6 SRAM3 DQA1 U17 AJ6 SRAM3 DQA2 17 7 SRAM3 DQA3 17 AC7 c SRAM3_DQA4 c SRAM3 DQA5 17 SRAM3 DQA6 U U U17 AD7 U U 17 AF7 SRAM3 DQAT U17 AG7 SRAM3 DQBO U17 A 7 SRAM3 U17 AD8 SRAM3 DQB2 U17 AE8 SRAM3 DQB3 U17 AF8 SRAM3 DQB4 U17 AG8 SRAM3
80. Active Timing Closure technologies and seamless integration with the industry s most advanced verification products ISE Foundation offers a great design environment for anyone looking for a complete programmable logic design solution 2 1 Foundation Features 2 1 1 Design Entry ISE greatly improves your Time to Market productivity and design quality with robust design entry features ISE provides support for today s most popular methods for design capture including HDL and schematic entry integration of IP cores as well as robust support for reuse of your own IP ISE even includes technology called IP Builder which allows you to capture your own IP and reuse it in other designs ISE s Architecture Wizards allow easy access to device features like the Digital Clock Manager and Multi Gigabit I O technology ISE also includes a tool called PACE Pinout Area Constraint Editor which includes a front end pin assignment editor a DN6000K10SE User Guide www dinigroup com 20 INTRODUCTION VIRTEX II PRO AAND ISE design hierarchy browser and an area constraint editor By using PACE designers are able to observe and describe information regarding the connectivity and resource requirements of a design resource layout of a target FPGA and the mapping of the design onto the FPGA via location atea This rich mixture of design entry capabilities provides the easiest to use design environment available today for your logic design
81. BOARD HARDWARE Daughter Card Connections DN26000K10SE IO Connections Test Header Signal Name Connector Test Header Signal Name FPGA Pin J1 105 No Connect P10 105 3 3V J1 106 MBCK6 15 9 10 106 DCLK1 J1 107 No Connect P10 107 GND J1 108 ECLK1 J5 7 P10 108 GND J1 109 No Connect P10 109 GND J1 110 No Connect P10 110 GND J1 111 P2N5 5 15 10 111 TST 79 U17 AF12 11 112 P2N4 5 17 P10 112 TST_HDRA80 U17 AG12 11 113 P2NX11 2 2 10 113 TST_HDRA81 U17 AE12 11 114 P2NX10 P10 114 TST HDRA82 U17 AD6 11 115 P2NX9 15 19 10 115 TST HDRA83 U17 AD12 11 116 P2NX8 5 21 P10 116 TST_HDRA84 U17 AC6 11 117 P2NX3 5 23 P10 117 TST 85 U17 AC12 11 118 No Connect P10 118 GND J1 119 P2NX2 J5 25 P10 119 TST_HDRA86 U17 P33 J1 120 P3NX11 12 29 P10 120 TST HDR AS7 U17 P34 11 121 P3NX10 2 30 P10 121 TST HDRAS88 U17 N31 11 122 P3NX7 2 31 10 122 TST HDRAS89 U17 N32 11125 P3NX6 2 32 10 123 TST HDRA90 U17 N41 J1 124 P3NX3 J5 27 P10 124 TST_HDRA91 U17 N42 J1 125 P3NX2 5 29 P10 125 TST HDRA92 U17 N39 J1 126 P3NX1 5 31 P10 126 TST HDRA93 U17 N40 J1 127 P3NX0 15 33 P10 127 TST_HDRA94 1017 333 11 128 P3N85 15 35 P10 128 TST HDRA95 U17 N34 11 129 No Connect P10 129 GND 11 130 P3N84 J5 37 P10 130 TST HDRA96 U17 N37 1 131 P3N81 15 29 P10
82. CLK5 J1 011 No Connect P10 11 GND J1 012 BP2N2 P2N2 J3 3 P10 12 TST HDRAO U17 M25 J1 013 P2N1 J2 8 P10 13 HDRA1 U17 K26 J1 014 PZNO 2 9 P10 14 TST HDRA2 U15 AH42 1 015 BP2NX7 P2NX7 125 P10 15 TST HDRA3 U17 D26 J1 016 BP2NX6 P2N X6 J3 7 P10 16 TST HDRA4 U17 AH35 1 017 BP2NX5 P2NX5 J3 9 1017 TST HDRA5 U17 M24 J1 018 BP2NX4 P2NX4 3 11 P10 18 TST HDRAG U17 AG35 11 019 P2NX1 2 10 P10 19 TST HDRA7 U17 AG36 11 020 P2NX0 2 11 P10 20 TST HDRAS U17 AG38 11 021 P3NX9 J2 40 P10 21 TST HDRA9 U17 AG39 11 022 No Connect P10 22 GND 11 023 P3NX8 J241 P10 23 TST HDRA10 U17 F34 DN6000K10SE User Guide www dinigroup com 143 BOARD HARDWARE Daughter Card Connections DN26000K10SE IO Connections Test Signal Name Connector Test Signal Name FPGA Pin Header Header 1 024 BP3NX5 P3NX5 3 13 P10 24 TST HDRA11 U17 C34 1 025 BP3NX4 P3NX4 3 15 P10 25 151 917 033 1 026 BP3N89 P3N89 12 17 P10 26 TST HDRA13 U17 H32 1 027 BP3N88 P3N88 13 49 P10 27 TST HDRA14 117132 1 028 BP3N87 P3N87 19 21 P10 28 TST HDRA15 U17 C33 1 029 BP3N86 P3N86 13 22 P10 29 TST HDRA16 U17 C32 1 030 BP3N83 P3N83 13 25 P10 30 TST HDRA17 1717131 1 031 BP3N82 P3N82 3 27 P10 31 TST HDRA18 U17 G31 1 032 BP3N77 P3N77 3 29 10
83. DDR 6A DATA3 17 AE33 DDR 6A DATA4 17 AD37 DDR_6A_DATA5 17 AD38 DDR DATAG 17 AD31 DDR_6A_DATA7 17 AD32 DDR_6A_DATA8 17 AD33 DDR_6A_DATA9 17 AD34 DDR_6A_DATA10 U17 AC36 DDR_6A_DATA11 U17 AC37 DDR_6A_DATA12 U17 AC31 DDR_6A_DATA13 U17 AC32 17 AE35 17 41 17 AB36 17 AG41 17 AD42 Ci Ci c c Ci U U U U U U U DDR 6A ADD7 U17 AF40 U U U U U U U U U U U U U U U Ce pL DN6000K10SE User Guide www dinigroup com 112 BOARD HARDWARE Signal Name FPGA Pin DDR DATA14 U17 AB33 DDR 6A DATA15 U17 AB34 DDR FPGA 6A UDQS U17 AC34 DDR FPGA 6A 11908 17 AD36 DDR_FPGA_6A_UDM 17 AD39 DDR_FPGA_6A_LDM DDR FPGA 6A BAO 17 AD41 DDR_FPGA_6A_BA1 U U U17 AG31 U U 17 42 6A CASn U17 AB40 DDR_FPGA_6A_CKE U17 AB36 DDR FPGA 6A CSn U17 AC39 DDR FPGA 6A RASn U17 AB37 DDR FPGA 6A WEn U17 AB39 DDR 6B ADDO U17 AT40 DDR_6B_ADD1 U17 AV42 DDR_6B_ADD2 U17 AV40 DDR_6B_ADD3 U17 AW41 DDR_6B_ADD4 U17 AW40 DDR_6B_ADD5 U17 AW42 DDR_6B_ADD6 U17 AV41 DDR_6B_ADD7 U17 AU39 DDR_6B_ADD8 U17 AU41 DDR_6B_ADD9 U17 AU42 DDR 6B ADD10 U17 AT39 DDR_6B_ADD11
84. DN3000K 10SD Daughter Card The Dini Group manufactures a daughter DN3000K10SD card that allows the user connection to the FPGA IO pins The daughter card has the following features Buffered I O Passive and Active Bus Drivers Unbuffered I O e Differential LVDS pairs Note Not available on DN6000K10SE Logic Emulation board Headers for Test Points The daughter card contains headers that may be useful with certain types of oscilloscope probes or when wiring pins to prototype areas Figure 61 is a block diagram of the daughter card DIFFERENTIAL CONNECTOR BCLK1 js ECLK1 4 MBCK6 j DIFF CLOCK J3 J4 J5 J6 J7 50 PIN IDC HEADER UNBUFFERED 0 17 J2 A N DIFF PAIR 0 15 J6 UNBUFFERED 10 0 23 50 PIN MINI D RIBBON CABLE p CONNECTOR 7 UNBUFFERED 10 0 23 LINEAR REGULATOR 12VDC TO 3 3V 3 9VDC J POWER INDICATORS A N 00509 CM BUFFERED I O 0 15 Ut UNBUFFERED l O 0 15 A y 43 3V 5 0 12 0 J3 BUFFERED 1 0 0 7 02 VO 0 15 HEADER BUFFERED 1 0 0 7 41 5V I 3 3V J4 5 0 12 0v 98 BUFFERED 1 0 0 15 03 UNBUFFERED 0 15 12 0 N N y GND 20
85. FSEL ROBOCLOCK 2 Reference Select Input The REFSEL input controls how the reference input is configured When LOW it will use the REFA pair DCLK3 or FPGA_CLKOUT as the reference input When HIGH it will use the REFB pair PLL2BC or PLL2BNC as the reference input This input has an internal pull down ROBO1_MODE ROBOCLOCK 1 Output Mode This pin determines the clock outputs disable state DN6000K10SE User Guide www dinigroup com 80 BOARD HARDWARE Desctiption Connector When this input is HIGH the clock outputs will disable to high impedance HI Z When this input is LOW the clock outputs will disable to HOLD OFP mode When in MID the device will enter factory test mode ROBO2_MODE ROBOCLOCK 2 Output Mode This pin determines the clock outputs disable state When this input is HIGH the clock outputs will disable to high impedance HI Z When this input is LOW the clock outputs will disable to HOLD OFP mode When in MID the device will enter factory test mode ROBO1_FBDIS ROBOCLOCK 1 Feedback Disable This input controls the state of QFA 0 1 When HIGH the QFA 0 1 is disabled to the HOLD OFF or HI Z state the disable state is determined OUTPUT MODE When LOW the QFA 0 1 is enabled Refer to Table 5 in the datasheet This input has an internal pull down ROBO2 FBDIS ROBOCLOCK 2 Feedback Disable This input controls the
86. Guide www dinigroup com 1 ABOUT THIS MANUAL Resource Description URL User Manual This is the main source of technical information The manual should contain most of the answers to your questions Dini Group Web Site The web page will contain the latest manual application notes FAQ articles and any device errata and manual addenda Please visit and bookmark http www dinigroup com Data Book Pages from The Programmable Logic Data Book which contains device specific information on Xilinx device charactetistics including readback boundary scan configuration length count and debugging http suppott xilinx com partinfo databook htm E Mail You may direct questions and feedback to the Dini Group using this e mail address support dinigroup com Phone Support Call us at 858 454 3419 during the hours of 8 00am to 5 00pm Pacific Time FAQ The download section of the web page contains a document called DN6000K10SE Frequently Asked Questions FAQ This document is periodically updated with information that may not be in the User s Manual 3 Conventions This document uses the following conventions An example illustrates each convention 3 1 Typographical The following typographical conventions are used in this document Convention Meaning or Use Example Courier font Courier bold Messages prompts and speed grade program files that the system 100 dis
87. HO DATA2 U17 E33 FLASHO DATA3 U17 E31 FLASHO DATA4 U17 F31 FLASHO DATA5 U17 F33 FLASH0_DATA6 U17 G33 FLASHO DATA7 U17 E34 DN6000K 10SE User Guide www dinigroup com 91 BOARD HARDWARE Signal Name FPGA Pin FLASH FLASHO DATAS U17 L30 U21 30 FLASHO DATA9 U17 D31 U21 32 FLASHO DATA10 017 131 U21 34 FLASHO DATA11 U17 E32 U21 36 FLASHO DATA12 17 832 021 39 FLASHO DATA13 U17 D34 021 41 FLASHO DATA14 U17 H33 U21 43 FLASHO DATA15 U17 H31 U21 45 FLASHO CEn U17 G27 U21 26 FLASHO OEn U17 K32 U21 28 FLASHO WEn U17 33 U21 11 FLASHO WPn U17 M28 U21 14 FLASH1 ADDRO U17 D9 U14 25 FLASH1 ADDR1 U17 D10 U14 24 FLASH1 ADDR2 U17 E11 014 23 FLASH1 ADDR3 U17 H12 U14 22 FLASH1 ADDR4 717 12 014 21 FLASH1 ADDR5 U17 E9 U14 20 FLASH1_ADDR6 U17 F11 U14 19 FLASH1_ADDR7 U17 F9 U14 18 FLASH1_ADDR8 U17 E10 U14 8 FLASH1 ADDR9 U17 H11 U14 7 FLASH1 ADDR10 U17 K12 U14 6 FLASH1 ADDR11 U17 J11 U14 5 FLASH1 ADDR12 U17 J17 U14 4 FLASH1_ADDR13 U17 G10 U14 3 FLASH1_ADDR14 U17 D12 U14 2 FLASH1 ADDR15 U17 D13 014 1 FLASH1 ADDR16 U17 E13 U14 48 DN6000K 10SE User Guide www dinigroup com BOARD HARDWARE Signal Name FPGA Pin FLASH1 ADDR17 U17 H10 FLASH1 ADDR18 U17 K11 FLASH1 ADDR19 U17 F12 FLASH1 ADDR20 U17 G12 FLASH1
88. IE PETp6 P6 B41 17 BB27 PCIE PETn6 P6 B42 17 BB26 cPCIE_PERp6 43 17 28 cPCIE_PERn6 P6 A44 17 BB29 PCIE PEIp P6 B45 17 BB31 PCIE PETn7 P6 B46 17 BB30 cPCIE_PERp7 P6 A47 17 BB32 cPCIE_PERn7 P6 A48 17 BB33 PCIE PRSNTn P6 B48 PCIE PRSNTn P6 A1 PCIE PERSTn P6 A11 U17 AY15 PCIE REFCLKOUTp P6 A13 115 2 PCIE REFCLKOUTn P6 A14 015 1 ee G Ge Eme DN6000K10SE User Guide www dinigroup com 131 BOARD HARDWARE 10 4 PCI Express Clock Interface The serial transceiver input is locked to the input data stream through Clock and Data Recovery CDR a built in feature of the RocketlO transceiver CDR keys off the rising and falling edges of incoming data and derives a clock that is representative of the incoming data rate The derived clock is presented to the FPGA fabric at 1 20th the incoming data rate whether full rate or half rate This clock is generated and remains locked as long as it remains within the specified component range This range is shown in Table 35 A sufficient number of transitions must be present in the data stream for CDR to work properly The CDR circuit is guaranteed to wotk with 8B 10B encoding Further CDR requires approximately 5 000 transitions upon power up to guarantee locking to the incoming data r
89. Installed CLOCKB Desctiption Oscillator X3 connected to RoboClock 1 U32 MODE1 ROBOCLOCK 1 Output Mode This pin determines the clock outputs disable state When this input is HIGH the clock outputs will disable to high impedance HI Z When this input is LOW the clock outputs will disable to HOLD OFF mode When in MID the device will enter factory test mode ROBOCLOCK 2 Output Mode This pin determines the clock outputs disable state When this input is HIGH the clock outputs will disable to high impedance HI Z When this input is LOW the clock outputs will disable to HOLD OFF mode When in MID the device will enter factory test mode ROBOCLOCK 71 Output Divider Function Select Conttols the divider function of bank 1 amp 1 CCLK of outputs Refer to Table 4 in the datasheet REFSEL1 ROBOCLOCK 1 Reference Select Input The REFSEL input controls how the reference input is configured When LOW it will use the REFA pair PLL1A as the reference input When HIGH it will use the REFB pair PLL1BC PLL1BNC as the reference input This input has an internal pull down ROBOCLOCK 1 Frequency Select This input must be set according to the nominal frequency Refer to Table 1 in the datasheet 0501 ROBOCLOCK 1 Feedback Divider Function Select These inputs determine the function of the QFAO and QFA1 outputs Refer to Table 4 in the datasheet
90. ORS m 2 FPGA STATUS LED S i SRAM 32K X8 osc CY62256 xi ADDRESS TERE ur VOLTAGE INDICATORS amie ETAGE INDICATORS powenneoen CONTROL 00000 SMARTMEDIA CONFIGURATION oo o eem SENE PROFPGA Juss DATA AMb X 16 DORVIT T 26 2364088 aves CONFIG pum 01 REGULATOR JUMPERS 2087 us ADDRESS ADDRESS ppmspRAM DDR PLLip SWITCHING 2MbX38 DATA DATA MODULE m 16 pos 148135 contROL 48 64 EE Y dd DCLK O 1 SWITCHING ics 01 2 ADDRESS ADDRESS DDR SDRAM bon MODULE DATA DATA SAM X16 Ir DDR PLL2n ROBOCLOCK Eu SWITCHING 334 10 PLL2 10 MODULE ECLKS ADDRESS ADDRESS DDR SDRAM DDR oaa oara gt camp xis Look ovreresivas contro commo Putas T INDICATORS VOLTAGE 25V MONITOR 42 CONFIG OO eona ADDRESS ADDRESS PLL p reas JUMPERS amp B 2 36 DATE Cou mM RESET 28
91. PIN IDC 74LVC16245APA 200 PIN MICROPAX HEADER 74FST163245PA BOTTOM OF PWB U1 U2 U3 BUFFERS OR LEVEL TRANSLATORS Figure 61 DN3000K10SD Daughter Card Block Diagram The DN3000K10SD Daughter Card provides 16 differential pairs 48 buffered passive active I O and 66 unbuffered I O signals The DN3000K10SD Daughter Card is pictured in Figure 62 DN6000K10SE User Guide Www dinigroup com 138 A m ze i nta Figure 62 DN3000K10S Daughter 03 used bus switches in the passive mode U2 gt 139 www dinigroup com BOARD HARDWARE 7 NOK P N DN3KIODT REV Figure 63 show the assembly drawing of DN3000K10SD Daughter Card IDT74FST163245 devices U1 and the IDT74LVC16245A U1 U2 U3 devices used as bus transceivers in the DN6000K10SE User Guide BOARD HARDWARE active mode The DN3000K10SD has separate enable direction signals for each driver ls I ac E TE e Coe 8L LIL IL 1 LI omn Rent hn 621 5 5 er E B 2290 i rip amp 2 5 4 PLL nit nn e a Figure 63 Assembly drawing for the DN3000K10SD NOTE Signals P4NX7 and P4NX6 are also used for
92. PU Debug External debug mode can be used to alter normal program execution It provides the ability to debug system hardware as well as software The mode supports multiple functions starting and stopping the processor single stepping instruction execution setting breakpoints as well as monitoring processor status Access to processor resources is provided through the CPU Debug port The PPC405 JTAG Joint Test Action Group Debug port complies with IEEE standard 1149 1 1990 IEEE Standard Test Access Port and Boundary Scan DN6000K10SE User Guide Www dinigroup com 123 BOARD HARDWARE Architecture This standard describes a method for accessing internal chip resources using a four signal or five signal interface The PPC405 JTAG Debug port supports scan based board testing and is further enhanced to support the attachment of debug tools These enhancements comply with the IEEE 1149 1 specifications for vendor specific extensions and are compatible with standard JTAG hardware for boundary scan system testing The PPC405 JTAG debug port supports the four required JTAG signals TMS TDI and TDO It also implements the optional TRST signal The frequency of the JTAG clock signal can range from 0 MHz DC to one half of the processor clock frequency The JTAG debug port logic is reset at the same time the system is reset using TRST When TRST is asserted the JTAG controller returns to the test logic reset state Refer t
93. Q3 eA DO DDR FPGA GA ADD5 __36 4 DO4 10 DDR Da DDR FPGA BA ADDE 37 Das H DDR ea Dae DDR FPGA GA ADD7 __38 6 13 DDR 6A Da7 OA 39 7 DQ 54 DDR DOS DDR FPGA ADDS __40 8 55 ___ _ _ 9 DDR FPGA GA ADDiO 28 9 009 57 DDR 6 10 DDR FPGA GA ADDIT __41 A10 AP DQ10 59 DDR 0011 DDR FPCA EACADDI2 a A11 DDR eA Dan DDH FPGA EA ADDT3 17 12 DQ12 85 DDR 6A DOT ps 0913 53 DOTS DDR FPGA 6A BAO DQ14 65 DDR 6A DA 25 pais Le BAI 47 DDR UDM DDR PLL1 45 UDM 725 a DDR_PLLin 46 SDM ck upas 5 DDR_6A_UDQS DDR_FPGA_6A_CKE 44 Lpas DDR FPGA RASn _ 23 14 eA BA NC DDR FPGA 22 BAS NE HS x NC Hy X CS NC BU vrer 9 DDR VREF DNU 3 2 5 VSSQ VDDQ fg VSSQ VDDQ VSSQ VDDQ zs VSSQ VDDQ VSSQ VDDQ vss VDD n vss VOD 733 vss VDD Figure 49 DDR SDRAM Connection 6 3 3 DDR SDRAM Clocking Refer to the DDR Clocking Section 6 3 4 DDR SDRAM Termination DDR SDRAM is based on the SSTL2 JEDEC Standard Stub Series Terminated Logic for 2 5V signaling standard The SSTL2 termination model used for DDR SDRAM has two types of termination e Class 1 Also called SSTL2_I Used for unidirectional signaling Control signals e Class 2 Also c
94. RAM4_DQD6 U17 AM9 SRAM4_DQD7 U17 AN9 SRAM4_DQPA U17 AK10 SRAM4_DQPB U17 AL10 SRAM4_DQPC U17 AM10 SRAM4_DQPD U17 AL11 SRAMA GWn U17 AR4 SRAM4_LBOn U17 AM1 SRAM4_OEn U17 AL5 SRAMA ZZ U17 AM5 SRAM CSn 6 3 DDR SDRAM 127 20 Double Data Rate DDR SDRAM represents enhancement to the traditional SDRAM Instead of data and control signals operating at the same frequency data DN6000K10SE User Guide www dinigroup com 107 BOARD HARDWARE operates at twice the clock frequency while address and control operate at the base clock frequency In other words the data is written or read from the part on every clock transition or twice per clock cycle This effectively doubles the throughput of the memoty device The trade off for such an improvement in throughput is increased complexity in interface logic to the DDR memoty as well as increased complexity in routing the DDR signals on the printed circuit board Additionally this memory has the same latencies as standard SDRAM so that while the data transfers ate twice as fast the latencies associated with DDR SDRAM are on par with standard SDRAM 6 3 1 Basics of DDR Operation DDR SDRAM provides data capture at a rate of twice the clock frequency Therefore DDR SDRAM with a clock frequency of 100 MHz has a peak data transfer rate of 200 MHz or 6 4 Gigabits per second for a 16 bit inter
95. THE DINI GROUP User Guide DN6000K10SE LOGIC EMULATION SOURCE DN6000K 10SE User Manual Version 1 2 The Dini Group 1010 Pearl Street Suite 6 La Jolla CA92037 Phone 858 454 3419 Fax 858 454 1279 support dinigroup com www dinigroup com Table of Contents ABOUT THISMANUA D 1 1 MANUAL CONTENTS 4 2 ADDITIONAL RESOURCES 41 3 ONWVENTIONS 3 1 22 Online Document 4 RELEVANT INFORMATION GEDAAN ELE ORANO E EDENES 4 GETTING STAR 6 1 PRECAUTION n 6 2 THE DN6000K10SE EOGIC EMULATION Rr REB eese VERDE Eons 6 3 INSTALLATION INSTRUCTIONS uideor IROL P RUN RATE 8 3 1 Jumper Setup 227 Jumper 9 3 34 Powering ON the DN6000KTOSE ce CM FOR UO EO BERGEN ERO ETE COE 12 4 PLAYING WITH YOUR DN6000K LOSE A 13 INTRODUCTION TO VIRTEX II PRO AND IS ooo ene tona vaio ene ere eu Rennen 16 1 culo E M 1 1 Summary of Virtex 1I Pro Features 1
96. TTING STARTED t WINNT System32 cmd exe aetest_wdm exe ASIC Emulator PCI Controller Driver PCI Menu Memory Menu Flash Menu Daughter Board Menu Quit PCI BASE ADDRESS bbaie 1 1 2 66000000 66000000 5 8000008 Please select option m 5 From the Main Menu choose Memory Menu The memory menu will now appear A WINNT 32 aetest_wdm exe ASIC Emulator PCI Controller Driver 049 Write Dword Same Address 22 Read Duord Same Address Write Read Duord Same Address BAR Memory Fill BAR Memory Write BAR Memory Display memory test on SSRAM 1 memory test on SSRAM 2 memory test on SSRAM 3 memory test SSRAM 4 memory test on DDR full memory test Cincluding blockram gt memory test FPGA block memory bar memory range test bar memory address data bitwise test Main Menu Q gt Quit PCI BASE ADDRESS bbaie 1 b3aieBBB 2 96000000 88800006 90000008 5 86000000 Please select option 6 The DN6000K10SE features DDR SDRAM SRAM and Flash memory devices The DN6000K10SE specific memory tests are designed to exercise and verify the functionality of those features Select one of the memory devices to be tested DN6000K10SE User Guide www dinigroup com 14 GETTING STARTED cmd exe aetest_wdm exe Duord Same Address gt BAR Memory Fill BAR Memory
97. TWARE TOOLS C WINNT System32 cmd exe aetest wdm exe full memory test Cincluding blockram gt memory test FPGA block memory bar memory range test bar memory address data bitwise test Main Menu Q gt Quit PCI BASE ADDRESS bbaie 1 b3ale 2 5 12717171477 68800008 66688000 6860008 3 Please select option k emory test of a range Cbhitwise address data within a bar ar lt 0 5 0 tarting address offset byte addr 6x61260000 word count of memory range Bx28 umber of Iterations for endless gt 1 top if an error occurs Cy or isplay any errors that occur or one with memory test ress a key Cpossibly twice Figure 14 Bar Memory Address Data Bitwise Test 1 11 5 Flash Menu Upon entering the Flash Menu from the Main Menu AETEST will output a screen similar to the one shown in Figure 15 WINNT System32 cmd exe aetest_wdm exe ASIC Emulator Flash Programming 949 Flashi Display Flash2 Display Flashi Erase amp Program Test tests xi bytes Flash2 Erase amp Program Test tests Ux1880880 bytes Flashi Erase amp Program Test tests entire flash thootblock gt Flash2 Erase amp Program Test tests entire flash thootblock gt Flashi Erase lt 0 10000 bytes Flash2 Erase lt 0 10000 bytes Debug Opti n G gt Clear Status Flashi gt gt Clear Status Flash2 gt
98. These inputs determine the function of QFAT outputs Refer to Table 4 in the datasheet ROBOCLOCK 1 Feedback Divider Function Select These inputs determine the DN6000K10SE User Guide www dinigroup com 79 BOARD HARDWARE Signal Name Description Connector function of the and QFAT outputs Refer to Table 4 in the datasheet ROBO2_FS ROBOCLOCK 2 Frequency Select This JP6 B2 input must be set according to the nominal frequency Refer to Table 1 in the datasheet 2 ROBOCLOCK 2 Feedback Output Phase Function Select This input determines the phase function of the Feedback Bank s QFA 0 1 outputs Refer to Table 3 in the datasheet ROBO2 FBDSO ROBOCLOCK 2 Feedback Divider Function Select These inputs determine the function of QFAT outputs Refer to Table 4 in the datasheet ROBO2 FBDS1 ROBOCLOCK 2 Feedback Divider Function Select These inputs determine the function of and QFA1 outputs Refer to Table 4 in the datasheet OSCA Enable for Oscillator A X4 OSCB Enable for Oscillator B X5 ROBO REFSEL ROBOCLOCK Reference Select Input The REFSEL input controls how the reference input is configured When LOW it will use the REFA pair PLL1A as the reference input When HIGH it will use the REFB pair PLLIBNC as the reference input This input has an internal pull down ROBO2 RE
99. U17 AT42 DDR_6B_ADD12 U17 AN42 DDR_6B_ADD13 U17 AM37 2 e m e ee GH kel Gree ea m x DDR 6B DATAO U17 AR37 DDR 6B DATA1 DN6000K10SE User Guide U17 AT38 Www dinigroup com BOARD HARDWARE Signal Name FPGA Pin DDR 6B DATA2 U17 AP36 DDR 6B DATA3 U17 AP37 DDR_6B_DATA4 U17 AP35 DDR_6B_DATA5 U17 AR36 DDR_6B_DATA6 U17 AN35 DDR_6B_DATA7 U17 AN36 DDR_6B_DATA8 U17 AM34 DDR_6B_DATA9 U17 AM35 DDR_6B_DATA10 17 AL33 DDR 6B DATA11 17 AL34 DDR 6B DATA12 17 AL38 DDR 6B DATA13 17 AL39 DDR 6B DATA14 17 AL31 DDR 6B DATA15 17 AL32 DDR FPGA 6B 0005 17 AL36 DDR FPGA 6B 1005 LG AP39 DDR FPGA 6B UDM 17 ALA0 DDR FPGA 6B LDM 17 AN37 DDR FPGA 6B BAO 17 1 DDR 6B 1 U17 AT41 DDR_FPGA_6B_CASn U17 AM41 DDR_FPGA_6B_CKE U17 AM39 DDR_FPGA_6B_CSn U17 AM38 DDR_FPGA_6B_RASn U17 AN40 DDR_FPGA_6B_WEn U17 AM42 DDR 7A ADDO U17 G41 DDR 7A ADD1 U17 H38 DDR 7A ADD2 U17 H40 DDR 7A ADD3 U17J41 ee are alc SP PG DN6000K10SE User Guide Www dinigroup com 114 BOARD HARDWARE Signal Name FPGA Pin DDR 7A ADD4 017 742 DDR 7A ADD5 U17 H41 DDR 7A ADD6 U17 H39 DDR 7A ADD7 U17 G42 DDR 7 ADD8 U17 G39 DDR 7A ADD9
100. U17 AU22 32 89 CCLKO 17 122 32 36 PCIE REFCLKp U17 AT21 18 14 PCIE_REFCLKn U17 AU21 SYS CLK U17 AN22 FPGA GCLKOUT U17 AN21 eS E C 4 2 Clock Source J umpers The clock source grid JP3 gives the user the ability to customize the clock scheme on the DN6000K10SE A brief description of each pin is given in Table 14 Table 14 Clock Source Signals Signal Name Description Connector CPLD CLKOUT Clock signal from the CPLD Clock signal from oscillator X4 JP3 A1 CLOCKB Clock signal from oscillator X5 JP3 A5 PLLIB Secondary clock input to RoboClock JP3 B4 differential pair with PLL1BN PLLIBN Secondary clock input to RoboClock JP3 B5 differential pair with PLL1B Secondary clock input to RoboClock differential pair with PLL2BN DN6000K10SE User Guide www dinigroup com 75 BOARD HARDWARE Signal Name Description Connector PLL2BN Secondary clock input to RoboClock JP3 B2 differential pair with PLL2BN GND Provides a ground reference for signals in the ribbon cable The PLL clock buffers can accept either LVTTL33 or Differential LVPECL reference inputs refer to Figure 32 43 8V 3 3 43 8V 3 3 o o o R252 R253 R250 lt R251 130 130 130 130 PLL2B C548 Q 1uF PLL2BN C549 0 1 PLLIB C544 0 1uF PLLIBN 4 545 0
101. U17 F42 DDR 7A ADD10 U17 G38 DDR 7A ADD11 U17 F40 DDR 7 ADD12 U17 E42 DDR_7A_ADD13 U17 F36 DDR_7A_DATAO U17 N35 DDR_7A_DATA1 U17 N36 DDR_7A_DATA2 U17 M38 DDR_7A_DATA3 U17 M39 DDR_7A_DATA4 U17 M33 DDR_7A_DATA5 U17 M34 DDR 7A DATAG U17 M31 DDR 7A U17 M32 DDR 7A DATAS U17 L34 DDR 7A DATA9 U17 L35 DDR_7A_DATA10 U17 K36 DDR_7A_DATA11 U17 K35 DDR_7A_DATA12 U17 K38 DDR_7A_DATA13 U17 K37 DDR_7A_DATA14 17 139 DDR 7A DATA15 U17 38 DDR FPGA 7A UDQS U17 K34 DDR FPGA 7A 11908 U17 M41 DDR_FPGA_7A_UDM U17 H36 c Ci Ci c c Ci GIGGING GS DN6000K10SE User Guide www dinigroup com 115 BOARD HARDWARE Signal Name FPGA Pin DDR FPGA 7A LDM 017 142 DDR FPGA 7A BAO U17 F39 DDR_FPGA_7A_BA1 U17 F41 DDR_FPGA_7A_CASn U17 D41 DDR_FPGA_7A_CKE U17 E40 DDR_FPGA_7A_CSn U17 E41 DDR FPGA 7A RASn 17 D42 DDR FPGA 7A WEn 17 D40 DDR 7B ADDO 17 V39 DDR_7B_ADD1 17 V41 DDR_7B_ADD2 17 W37 DDR_7B_ADD3 17 W41 DDR_7B_ADD4 17 W40 DDR_7B_ADD5 17 W39 DDR_7B_ADD6 17 W38 DDR_7B_ADD7 17 V38 DDR_7B_ADD8 17 41 DDR 7B ADD9 17 U40 DDR 7B ADD10 17 U39 DDR 7B ADD11 17 U38 DDR 7B ADD12 17 138 DDR 7B ADD13 17 R40 DDR 7B DATAO U17 AA33 DDR 7B DATA1 U17 AA34 DDR 7B DATA2 17 Y31 DDR 7B DATA3 17 Y32 DDR_7B_DATA4 17 Y36 DDR_7B_DATA5 17 Y37 DDR_7B_DATA6 17 Y33
102. UP UL OM ds 158 2 4 2 Arguments 2 4 3 Ret rneV n p e PEDE NEIN ee e PERITI es LOIN erue 158 2 4 4 NGS T s H 158 2 5 read word 159 2 5 1 Description 159 2 52 Arguments 159 2 5 3 Iun E M RE 159 2 5 4 DORE EAE KHOA APSO HR EUR DARE TONER 159 2 6 read dword 160 2 6 1 Description 160 2 6 2 Nous oer xn M repr Og cm ar 160 2 6 3 Return Values 160 2 6 4 Notes 160 2 7 buffer allocate 161 2 7 1 RR 161 2 72 ae DER ETE EM SEEDS Ye E PME RR RSEN Io HARE EN REIN RHONE 2 7 3 Return Values 27 4 161 2 8 _ Free xz 162 2 81 Description 162 2 8 2 Arguments 162 2 8 3 Ion unb El 162 2 8 4 162 2 9 write dword 1
103. Write BAR Memory Display memory test on SSRAM 1 memory test on SSRAM 2 memory test on SSRAM 3 memory test on SSRAM 4 memory test on DDR full memory test Cincluding blockram gt memory test on FPGA block memory bar memory range test bar memory address data bitwise test Main Menu Q gt Quit PCI BASE ADDRESS bbaie 1 b3aie 2 96000000 88800088 4 68000000 5 00000000 3 Please select option c word count 0 100 top if an error occurs or isplay any errors that occur lt or 7 AETEST Test utility will now test the selected memory device using the memoty controllers available in the PCI reference design Press any key to exit the selected memory device test The test should complete successfully as indicated by the dots WINNT System32 cmd exe aetest wdm exe Mrite Read Duord Same fiddress Memory Fill BAR Memory Urite BAR Memory Display memory test on SSRAM 1 memory test on SSRAM 2 memory test on SSRAM 3 memory test on SSRAM 4 memory test on DDR full memory test including blockram gt memory test on block memory bar memory range test bar memory address data bitwise test Main Menu Q gt Quit PCI BASE ADDRESS bbaie 1 b3aie 2 88800888 90000009 5 9999 3 Please select option c word count 8x188 top if an error occurs or isplay any errors that occur lt or
104. able configuration solution that provides substantial savings in development effort and cost per bit over traditional PROM and embedded solutions for high capacity FPGA systems Virtex II Pro devices ate configured by loading application specific configuration data into internal memory Configuration is carried out using a subset of the device pins some of which are dedicated while others can be reused as general purpose inputs and outputs after configuration is complete SmartMedia is the primary means of configuring the FPGA on the DN6000K10SE board Configuration of FPGA is accomplished using either Serial SelectMAP or the JTAG interface The remainder of this section describes the functional blocks that entail the FPGA configuration environment 3 1 Micro Controller Unit MCU The Atmel A Tmega128L U4 micro controller is used to control the configuration process The ATmega128L provides the following features 128K bytes of In System DN6000K10SE User Guide www dinigroup com 65 BOARD HARDWARE Programmable Flash with Read While Write capabilities 4K bytes EEPROM 4K bytes SRAM 53 general purpose I O lines 32 general purpose working registers Real Time Counter four flexible Timer Counters with compare modes and PWM 2 USARTS byte oriented Two wire Serial Interface an 8 channel 10 bit ADC with optional differential input stage with programmable gain programmable Watchdog Timer with Internal Oscillator an SPI serial
105. alled SSTL2_II O Used for bi directional signaling Data signals Both Class 1 and Class 2 are based on a 50Q controlled impedance environment and termination to VTT a 1 25V power supply DN6000K10SE User Guide www dinigroup com 109 BOARD HARDWARE SSTL2 Class 1 termination is used for unidirectional signaling such as control signals It is based on 500 controlled impedance driver a 500 controlled impedance transmission line and 500 parallel termination to VTT at the receiver Figure 50 shows a basic SSTL2 Class 1 circuit The driver is brought to 50Q by the addition of a 25 series resistor immediately adjacent to the driver implemented using DCI thus no need for an external component Vir 0 5 x Figure 50 SSTL2 Class 1 Termination SSTL2 Class 2 termination is used for bi directional signaling such as data signals It is based on a 500 controlled impedance driver and 50 parallel termination to VTT for the receiver at both ends connected through a 50 controlled impedance transmission line Figure 51 shows a basic SSTL2 Class 2 circuit The driver is brought to 500 by the addition of a 25 series resistor immediately adjacent to the driver Figure 51 SSTL2 Class 2 Termination Note DCI termination must be implemented in the DDR SDRAM controller design DN6000K10SE User Guide www dinigroup com 110 BOARD HARDWARE 6 3 5 SDRAM Power Supply The DATEL 2 5V module U3
106. an then read from or write to the address representing the JTAG chain 3 4 1 FPGA Serial TAG Connector Figure 30 shows P4 the JTAG connector used to download the configuration files to FPGA DN6000K 10SE User Guide www dinigroup com 72 BOARD HARDWARE 43 3V 3 3V 51 1K 1K P4 cFPGA PROGn TMS cFPGA CCLK TCK 1 3 5 7 8 1 I cFPGA DONE TDO 9 cFPGA_DIN TD cFPGA_INITn 87332 1420 Figure 30 FPGA Serial JTAG Connector 3 4 2 FPGA JTAG connection to Configuration CPLD Table 12 shows the connection between the FPGA JTAG connector and the Configuration CPLD Table 12 FPGA JTAG connection to Configuration CPLD Signal Name Connector cFPGA_CCLK TCK P4 6 cFPGA_DONE TDO P4 8 cFPGA_PROGn TMS P4 4 cFPGA_DIN TDI 4 Clock Generation 4 1 Clock Methodology P4 10 The DN6000K10SE Logic Emulation board has a flexible and configurable clocking scheme Figure 31 is a block diagram showing the clocking resource DN6000K10SE User Guide www dinigroup com s and connections 73 BOARD HARDWARE GigE Infiniband RocketlO Synthesizer Synthesizer User CLK 1658442 ICS8442 DOR SMA vos Lvps DDR DCLKSR 150 ahera FPGA GCLKOUT p RoboClock osc ctocka PLL2B CYB944V ECUQU S gt ya eros
107. and External User Clock Connections SMA Signal Name FPGA Pin User Clock Input USERp U17 K21 J17 CLK_USERn U17J21 J16 4 5 DDR Clocking The DDR Clock is generated in the FPGA by using the Digital Clock Managers DCM Clocking for DDR SDRAM requires the transmission of two clocks the positive clock and the negative clock SSTL 2 differential These two clocks are 180 out of phase from each other and their phase alignment must be tightly controlled In order to prevent signal integrity problems and timing differences from becoming an issue it is preferable for each device whether memory or register to have its own clock While it is possible for each device to have a positive and negative clock generated by the FPGA this unnecessarily consumes pins that could be used elsewhere To save these pins an externally DDR SDRAM clock driver is used The clock is routed to the DDR PLL Clock Driver 034 that distributes the individual clocks to the separate DDR devices U27 U28 U29 and U30 4 5 1 Clocking Methodology This section describes the DDR clocking methodology implemented in the reference design refer to Figure 37 The first DCM generates CLKO and CLK90 CLKO directly follows the user supplied input clock one of the clock sources PCI etc This DCM also supplies the CLKDV output which is the input clock divided by 16 used for the AUTO REFRESH counter The second DCM the controller bl
108. apable of various high speed serial standards such as Gigabit Ethernet FiberChannel InfiniBand and XAUI In addition the channel bonding feature ageregates multiple channels allowing for even higher data transfer rates For additional information on RocketIO transceivers see the RocketlO Transceiver User Guide http www xilinx com publications products v2pro userguide ug024 pdf DN6000K10SE board has 10 RocketIO transceivers available on the top side of the FPGA These 10 transceivers implement three different MGT interfaces on board DN6000K10SE User Guide www dinigroup com 117 BOARD HARDWARE including two Gigabit Ethernet Fiber channels two InfiniBand channels and two Serial ATA channels one configured as a Serial ATA Host the other configured as a Serial ATA Device peripheral and four SMA interfaces 7 1 Gigabit Ethernet Fiber Gigabit Ethernet fiber represents a marked evolution over copper Gigabit Ethernet allowing signals to be transmitted 500 meters multi mode or as much as 10km singlemode In addition it provides for high tolerance of EMI and in turn produces little EMI 7 1 1 Agilent HFBR 5710L LP Small Form Factor Pluggable SFP Optical Transceiver J 2 3 While the Virtex II Pro can deliver the speeds required by Gigabit Ethernet it is not capable of transmitting or receiving optical signals directly This capability is added by the inclusion of an Agilent HFBR 5710L LP Small Form Facto
109. ate Once lock is achieved up to 75 missing transitions can be tolerated before lock to the incoming data stream is lost Table 35 CDR Parameters Parameter i Conditions TGJTT REFCLK total 3 125 Gb s jitter peak to peak 2 5 Gb s measuted at the BGA ball BREFCLK for speeds 1 06 Gb s higher than 2 5Gb s In order to satisfy the CDR clock jitter requirements the PCI Express Clock was buffered by a LVDS frequency synthesizer U18 Since the Xilinx PCI Express core requires 125MHz clock signal the 1 58735 U15 synthesize the signal to 125MHz from the standard 100MHz PCI Express signal 10 4 1 Connection between the PCI Express connector and the FPGA The connections between the FPGA and PCI Express clock is documented in Table 36 Table 36 Connection between the PCI Express connector and the FPGA Signal Name FPGA Pin Clock Buffer PCIE REFCLKp U17 AT21 U18 14 PCIE REFCLKn U17 AU21 U18 15 11 Power System The DN6000K10SE supports a wide range of technologies from legacy devices like serial ports to DDR SDRAM and RocketIO multi gigabit transceivers This DN6000K10SE User Guide Www dinigroup com 132 BOARD HARDWARE wide range of technologies requires a wide range of power supplies These are provided on the DN6000K10SE using a combination of switching and linear power regulators The DN6000K10SE can be hosted in a PCI Express slot or it can be used in a standal
110. atform FPGA on board the DN6000K10SE is a FPGA in the FF1704 package capabilities of the 2VP70 base model include e 2PowerPC M 405 processor e 160r 20 Multi Gigabit Transceivers DN6000K 10SE User Guide www dinigroup com 63 BOARD HARDWARE e 996 SelectI O e 8 Digital Clock Managers DCMs 33000 logic slices e 5900 Kbits of block SeleccRAM BRAM 328 18 x 18 bit multiplier blocks The FF1704 package for the FPGA that is used on the DN6000K10SE is a 1 0mm 42 5 x 42 5mm fully populated with four corner balls removed flip chip BGA The PowerPC 405 is capable of operation at 300 MHz and is capable of 420 Dhrystone dependend on the speed grade of the part Each of MGTs capable of 3 125 Gigabits per second in both directions for an aggregate bandwidth of 50 Gigabits per second from the 25 Gbps transmit and 25 Gbps receive The SelectIO are capable of supporting multiple high speed I O standatds from LVDS to SSTL2 to PCI The DCMs are capable of 24 MHz to 420 MHz operation and provide fot clock deskew frequency synthesis and fine phase shifting 2 2 FPGA Bankout Diagram The FPGA is connected directly or indirectly to all other devices on the boatd Figure 24 shows the connections to the FPGA on a per bank basis DN6000K 10SE User Guide www dinigroup com 64 BOARD HARDWARE
111. ation is followed by device configuration where a bitstream is generated from the physical place and route information and downloaded into the target programmable logic device To ensure designers get their product to market quickly Xilinx ISE software provides several key technologies required for design implementation e Ultra fast runtimes enable multiple turns per day ProActive Timing Closure drives high performance results Timing driven place and route combined with push button ease e Incremental Design DN6000K10SE User Guide www dinigroup com 21 INTRODUCTION VIRTEX II AAND ISE e Macro Builder 2 1 4 Board Level Integration Xilinx understands the critical issues such as complex board layout signal integrity high speed bus interface high performance I O bandwidth and electromagnetic interference for system level designers To ease the system level designers challenge ISE provides support to all Xilinx leading FPGA technologies e System IO e XCITE e Digital clock management for system timing control management for electromagnetic interference To really help you ensure your programmable logic design works in context of your entire system Xilinx provides complete pin configurations packaging information tips on signal integration and various simulation models for your board level verification including e BIS models HSPICE models STAMP models 3 Vir
112. bug software as it runs on the processor The PowerPCTM 405 CPU core includes dedicated debug resources that support a vatiety of debug modes for debugging during hardware and software development These debug resources include e Internal debug mode for use by ROM monitors and software debuggers e External debug mode for use JTAG debuggers e Debug wait mode which allows the servicing of interrupts while the processor appears to be stopped e Real time trace mode which supports event triggering for real time tracing Debug modes and events are controlled using debug registers in the processor The debug registers are accessed either through software running on the processor or through the JTAG port The debug modes events controls and interfaces provide a powerful combination of debug resources for hardware and software development tools The JTAG port interface supports the attachment of external debug tools such as the ChipScope Integrated Logic Analyzer a powerful tool providing logic analyzer capabilities for signals inside an FPGA without the need for expensive external instrumentation Using the JTAG test access port a debug tool can single step the processor and examine the internal processor state to facilitate software debugging This capability complies with the IEEE 1149 1 specification for vendor specific extensions and is therefore compatible with standard JTAG hardware for boundary scan system testing 8 1 C
113. ce requirements The dual output LVDS clocks are routed to the top and bottom RocketlO reference clock inputs The PLL architecture for the RocketIO transceivers uses the reference clock as the interpolation source to clock the serial data Removing the reference clock will stop the RX and TX PLLs from working Therefore a reference clock must be provided at all times The serial transceiver input is locked to the input data stream through Clock and Data Recovery CDR a built in feature of the RodketIO transceiver There are eight clock inputs into each RocketIO transceiver instantiation REFCLK and BREFCLK are reference clocks generated from an external sources and presented to the FPGA as DN6000K 10SE User Guide www dinigroup com 86 BOARD HARDWARE differential inputs The reference clocks connect to the REFCLK or BREFCLK ports of the RocketIO multi gigabit transceiver MGT While only one of these reference clocks is needed to drive the MGT BREFCLK or BREFCLK2 must be used for serial speeds of 2 5 Gbps or greater The reference clock also locks a Digital Clock Manager DCM or a BUFG to generate all of the other clocks for the GT Never run a reference clock through a DCM since unwanted jitter will be introduced 4 7 1 Clocking Methodology At speeds of 2 5 Gbps or greater REFCLK configuration introduces more than the maximum allowable jitter to the RocketlO transceiver For these higher speeds BREFCLK configuration is required The
114. ces to external memory e Arithmetic functions Dedicated 18 bit x 18 bit multiplier blocks Fast look ahead carry logic chains e Flexible logic resources Up to 111 232 internal registers latches with Clock Enable Up to 111 232 look up tables LUTs or cascadable variable 1 to 16 bits shift registers Wide multiplexers and wide input function support o Horizontal cascade chain and Sum of Products support DN6000K10SE User Guide www dinigroup com 18 INTRODUCTION VIRTEX II PRO AAND ISE Internal 3 state busing e High performance clock management circuitry Up to eight Digital Clock Manager DCM modules Precise clock de skew Flexible frequency synthesis High resolution phase shifting o 16 global clock multiplexer buffers in all parts e Active Interconnect technology Fourth generation segmented routing structure Fast predictable routing delay independent of fanout Deep sub micron noise immunity benefits Select I O Ultra technology o Up to 852 user I Os Twenty two single ended standards and five differential standards Programmable LVTTL and LVCMOS sink source current 2 mA to 24 mA per I O Digitally Controlled Impedance DCI I O on chip termination resistors for single ended I O standards o PCI support 1 Differential signaling 840 Mb s Low Voltage Differential Signaling I O LVDS with current mode drivers Bus LVDS I O HyperTransport I O with
115. char word 2 2 3 Return Values successful function call will return zeto 2 2 4 Notes The source code for bar write word is portable to each of the operating systems intended for AETEST usage DN6000K10SE User Guide ww w dinigroup com 156 APPENDIX 2 3 bar write dword bar write dword is a high level function C function which is recommended for development by users of the DN6000K10SE 2 3 1 Description bar write dword allows users of the DN6000K10SE to write a dwotd of data to any location in the Base Address Registers BARs of PCI memory All 4 gigabytes of PCI memory is available for access 2 3 2 Arguments The arguments for write dword are shown in Table 42 They are listed in order Table 42 bar write dword Arguments Argument Desctiption Possible Values unsigned long barnum BAR number to be accessed BARO 0 BARI 1 BAR2 2 BAR3 3 BAR4 4 BAR5 5 unsigned long byte offset Address Number of bytes to Ox0 bytes in mem space offset data dword data A dword of data for the write 0 00000000 operation 32 bits typedef unsigned char dword 2 3 3 Return Values A successful function call will return zeto 2 3 4 Notes The source code for bar write dword is portable to each of the operating systems intended for AETEST usage DN6000K10SE User Guide ww w dinigroup com 157 APPENDIX 2 4 bar read byte read
116. d in a x1 slot such as http www getcatalyst com 16 In a typical PCI Express motherboard such as the ASUS P5AD2 it has one PCI Express x16 slot and several x1 slots In such motherboards DN6000K10SE can plugged in a x16 slot directly or in a x1 slot via an adapter described above 10 2 PCI Express Core The PCI Express signals from the edge connector are connected directly to the FPGA so the FPGA must contain logic to interface PCI Express if it is intended to use in a PCI Express slot The DN6000K10OPCIE reference design provided by the Dini Group does not include a free PCI Express core to modify the design you must putchase the Xilinx PCI Express Endpoint core here DO DI PCIEXP The Xilinx Advanced Swtiching Interconnect ASI 1 Lane and 4 Lane Endpoint cores ate high bandwidth scalable and reliable serialinterconnect intellectualproperty building blocks for use with the Virtex II Pro FPGA family These cores are protocol compliant and electrically compatible with the Advanced Switching Core Architecture Specification v1 0 Advanced Switching AS defines a packet switched fabric architecture that supports high availability capabilities such as hot add remove redundant pathways and fabric management fail over AS facilitates the tunneling of neatly any transport network link layer protocol The architecture supports robust low latency transport of chip to chip protocols such as PCI and PCI Ex
117. e aetest_wdm exe icrosoft Windows 20808 Version 5 88 2195 lt C gt Copyright 1985 2000 Microsoft Corp gt aetest aetest Daetest_wdm exe SP_INTERFACE_DEVICE_DATA available for this GUID instance ould not find open DnDeu device Figure 4 DN6000K10SE Not Found DN6000K 10SE User Guide www dinigroup com 26 INTRODUCTION THE SOFTWARE TOOLS AETEST will still run however several DN6000K10SE specific options will not be available 1 1 2 Main Menu Upon powering up and after board recognition the user must merely press a key to enter the Main Menu shown in Figure 5 Emulator PCI Controller Driver 49 PCI Menu Memory Menu Flash Menu Daughter Board Menu Quit PCI BASE ADDRESS bbaie888 1 2 96980080 4 68000000 5 99909999 25151212177 Please select option m Figure 5 Main Menu The possible Main Menu options and a description can be found in Table 2 Table 2 Main Menu Options Function Name Description Read FPGA F Revision Displays the revision of the reference design in FPGA F PCI Menu Takes User to PCI Menu Memory Menu Takes User to Memory Menu Daughter Board Menu Take User to Daughter Board Menu 1 1 3 PCI Express Menu 1 1 4 Memory Menu Upon entering the Memory Menu from the Main Menu AETEST will output a screen similar to the one shown in Figure 6 DN6000K10SE User Guide www dinigroup com 27 INTRODUCTION
118. e 49 DDR SDRAM Connection Figure 50 SSTL2 Class 1 Termination Figure 51 SSTL2 Class 2 Termination Figure 52 DDR VTT Termination Regulator Figure 53 Recommended connections for the HFBR 5710L Den Figure 54 CPU Debug Figure 55 Combined Trace Debug Connector Pinout Figure 56 PCI Express Interface Figure 57 Power Supply Figure 58 External Power Connection Figure 59 Test Header Figure 60 Test Header Pin Numbering Figure 61 DN3000K10SD Daughter Card Block Diagram Figure 62 DN3000K10S Daughter Figure 63 Assembly drawing for the DN3000K10SD List of Tables ble 1 esencia ed DRE M MU ME 2 Main Menu Options le 5 Daughter Board Options e 4 S2 Dipswitch Configuration Settings 5 HyperTerminal Main Menu Options sse 6 HyperTerminal Interactive Configuration Menu Options e 7 Sanity Check Command Line Options e 8 MCU Memory 9 FPGA Configuration Modes e 10 FPGA configuration file sizes 11 Connection between CPLD MCU e 12 JTAG connection to Configuration CPLD e 13 Clocking inputs to the e 14 Clock Source Signals 15 RoboClock Configuration Signals S e e
119. e 9 Table 9 FPGA Configuration Modes Configuration Mode CLK Direction Master Setial Slave Serial In Master SeleccMAP Slave SeleccM AP Boundary Scan Note Grayed options not supported by this design 3 3 SmartMedia The configuration bit file for the FPGA is copied to a SmartMedia card using the SmartDisk FlashPath Floppy Disk Adapter The approximate file size for each possible FPGA option is shown below in Table 10 Note that several BIT files can be put on a 32MB The DN6000K10SE is shipped with two 32 megabyte 3 3V SmartMedia cards The DN6000K10SE support card densities up to 128MB Note Do NOT format the SmartMedia card using the default Windows file format program Smart Media cards come pre formatted from the factory and files can be deleted from the card when they are no longer needed If the SmartMedia requires formatting format the media with the program supplied by the FlashPath SmartMedia floppy adapter software DN6000K 10SE User Guide www dinigroup com 70 BOARD HARDWARE Table 10 FPGA configuration file sizes Pro Bitstream Device Length bits XC2VP70 25 604 096 XC2VP100 33 645 312 SmartMedia Catds ate available from www computers4sure com 3 3 1 SmartMedia Connector Figure 29 shows J1 the SmartMedia connector used to download the configuration files to the 6 SM DO T SM_D1 8 SM_D2
120. e DN6000K10SEC VPP is 3 3V The DN6000K10SC interfaces to the FLASH at 2 5V levels This family of devices is capable of fast programming at 12V not utilized on the DN6000K10SC The C3 device features the following e Enhanced blocking for easy segmentation of code and data or additional design flexibility e Program Suspend to Read command e VCCQ input of 1 65V 2 5V or 2 7V 3 6V on all I Os e Maximum program and erase time specification for improved data storage For more information on this part please refer to the Intel P N TE28F640C3TC80 datasheet 6 1 1 FLASH Connection to the FPGA The FLASH memory components are connected to the FPGA on Bank 0 and Bank 1 as listed in Table 21 The VCCO of the IO banks are connected to 2 5V Table 21 Connection between FPGA and FLASH Signal Name FPGA Pin FLASH U21 25 FLASHO_ADDRO U17 G26 DN6000K10SE User Guide www dinigroup com 90 BOARD HARDWARE Signal Name FPGA Pin FLASHO ADDR1 U17 E27 FLASHO ADDR2 U17 K27 FLASHO ADDR3 U17 E30 FLASHO ADDR4 U17 F30 FLASHO ADDR5 U17 H26 FLASHO ADDR6 U17 L27 FLASHO_ADDR7 U17 26 FLASHO ADDRS8 U17 F27 FLASHO ADDR9 U17 M27 FLASHO ADDR10 U17 G30 FLASHO ADDR11 U17 E28 FLASHO ADDR12 U17 L26 FLASHO ADDR13 U17 H27 FLASHO ADDR14 U17 F28 FLASHO ADDR15 U17 30 FLASHO ADDR16 U17 K30 FLASHO ADDR17 U17 M26 FLASHO ADDR18 U17 27 FLASHO ADDR19 U17 M29 FLASHO ADDR20 U17 D30 FLASHO ADDR21 U17 D27 FLASHO DATAO U17 K31 FLASHO DATA1 U17 M30 FLAS
121. ectable for each chip The feedback clocks are controlled separately Eighteen configurable outputs each drive terminated transmission lines with impedances as low as 50 while delivering minimal and specified output skews at LVTTL levels refer to Figure 34 The outputs are arranged in five banks Banks 1 to 4 of four outputs allow a divide function of 1 to 12 while simultaneously allowing phase adjustments in 625 ps 1300 ps increments up to 10 4 ns One of the output banks also includes an independent clock invert function The feedback bank consists of two outputs which allows divide by functionality from 1 to 12 and limited phase adjustments Any one of these eighteen outputs can be connected to the feedback input as well as driving other inputs Selectable reference input is a fault tolerance feature which allows smooth change over to secondary clock source when the primary clock source is not in operation The reference inputs and feedback inputs are configurable to accommodate either LVTTL ot Differential LVPECL inputs The completely integrated PLL reduces jitter Please refer to the datasheet for more detailed information DN6000K10SE User Guide www dinigroup com 77 BOARD HARDWARE FBKA diei C Phase RES Control Logic FBSEL vco Divide and Phase REFA Detector Gene REFA REFB 8 REFB OUTPUT MODE I ae REFSEL Divide and gt m QFAO Pha
122. eset of FPGA through FPGA_GRSTn signal 3 FPGA configuration is cleared 4 If the dip switch is set for Select configuration option and there is a valid SmartMedia card inserted into the socket then the FPGA will be configured A SmartMedia card is valid if it complies with the SSFDC specification and contains a file named main txt in the root directory If the card is invalid or there is no card present then the FPGA will not be configured 5 The Main Menu will appear in the Terminal Window Note The identical sequence of events occurs at power up 5 2 PPC Reset The DN6000K10SE also contains another RESET push button 53 used to reset the PPC This signal is pulled up on the DN6000K10SE The user is responsible for debouncing the reset signal in the FPGA Table 20 shows the connection between the reset push button and the FPGA Table 20 PPC Reset Signal Name FPGA Pin Push Button Switch PPC_RESETn U17 F24 53 4 6 The DN6000K10SE provides three different memory technologies to the user FLASH Synchronous SRAM and DDR SDRAM various densities 6 1 FLASH The FLASH 14 U21 memory components on the DN6000K10SE can accommodate up to 4M x 16 devices refer to Figure 41 In addition to programming the FPGA and storing bitstreams the FLASH may be used for non volatile storage DN6000K 10SE User Guide www dinigroup com 89 BOARD HARDWARE
123. face In order to maintain high speed signal integrity and stringent timing goals a bi directional data strobe is used in conjunction with SSTL 2 signaling standard as well as differential clocks DDR SDRAM operates as a source synchronous system in which data is captured twice per clock cycle using a bi directional data strobe to clock the data The DDR SDRAM control bus consists of a clock enable chip select row and column addresses bank address and write enable Commands are entered on the positive edges of the clock and data occuts for both positive and negative edges of the clock The double data rate memoty utilizes a differential pair for the system clock and therefore has both a true clock CK complementaty clock signal 6 3 2 DDR SDRAM Configuration The DDR SDRAM memory components on the DN6000K10SE are arranged as 16 bit mode refer to Figure 49 Made up of four discrete parts 027 028 029 030 the components used 64 Mb x 16 parts organized as 16 million deep by 16 bits wide and 4 banks This provides for a total capacity of 128 Mbytes for the system for more information refer to Micron s datasheet PN MT46V64M190 DN6000K10SE User Guide www dinigroup com 108 BOARD HARDWARE DDR FPGA GA ADDO 29 DDR 6A 000 4 DDR 6A DOT 30 DaI 5 DDR 007 ae 52 2 5 DDR FPGA 6A ADD 35 D
124. fer typedef int dma_buffer_handle 2 7 3 Return Values A successful function call will return zero An error will return a non zero value If 1 is returned the allocation failed If 2 is returned the DPMI implementation of AETEST is not being used See Notes An integer indicating the handle for the DMA buffer is placed in the variable location pointed to by bad An integer indicating the physical address of the DMA buffer is placed in the variable location pointed to by 2 7 4 Notes The dma buffer allocate code is written for use in the DPMI DOS implementation of AETEST DN6000K10SE User Guide ww w dinigroup com 161 APPENDIX 2 8 dma buffer free dma buffer free is a high level function C function which is recommended for development by users of the DN6000K10SE 2 8 1 Description buffer free allows users of DN6000K10SE to free memory associated with a previously allocated DMA buffer 2 8 2 Arguments The argument s for dma_buffer_free are shown in Table 47 They are listed in order Table 47 dma_buffer_free Arguments Argument Description dma_buffer_handle hndl Handle for a DMA buffer typedef int dma_buffer_handle 2 8 3 Return Values A successful function call will return zero If 2 is returned the DPMI implementation of AETEST is not being used See Notes 2 8 4 Notes The dma_buffer_free code is written for use in the DPMI DOS implementation of AE TEST
125. i44 E 83 183 145 TST HDRA66 84 184 GND ST 67 85 L185 45 TST_HDRA68 86 186 HDRAT14 TST HDHAS69 87 187 5 HDRA148 GND 88 188 TST HDHAT4S _ 5 HDRA7O 89 189 50 5 71 90 190 _ TST_HDRA72 91 191 HDRA152 TST HDRA73 92 192 HDHA153 1 5V 93 193 54 74 ___94 7 2194 75 9517 7 295 HDRA76 96 196 m 97 197 78 98 198 TST HDHATBB GND 99 199 TST HDHAT52 12V 100 TST_HDRAT60 2 203 201 204 7 52 202 e 205 EM 200 DN6000K10SE User Guide Figure 59 Test Header www dinigroup com gt DCLKk1 136 BOARD HARDWARE 12 1 1 Test Header Connector FCI Micropax connector 200 pin is used as a standard interface to all the Dini Group logic emulation boards This connector has a specified current rating of 0 5 amps per contact See datasheet for more information P N 91294 003 This connector mates to the 200 pin Micropax connector on the daughter card P N 91403 003 12 1 2 Test Header Pin Numbering Figure 60 indicates the pin numbering scheme used on the test headers Mounting Holes Figure 60 Test Header Pin Numbering DN6000K10SE User Guide www dinigroup com 137 BOARD HARDWARE 12 2
126. ide ww w dinigroup com 167 APPENDIX 2 12 4 Notes hDevice CreateFile function should be used to rettieve a handle dwloControlCode See include glentlcodes h which is included with the AETEST source code for example control codes IpInBuffer This parameter can be set to NULL if no input data is required for the operation nInBuffetSize N A IpOutBuffer This parameter can be set to NULL if operation does not produce any output data NOutBufferSize N A IpBytesReturned If the output buffer is too small the call function fails and the returned byte count is zero If the output buffer is full prior to operation completion the call will fail However DeviceloControl will return all of the data in the output buffer and returned byte count will correspond to the amount of data returned IpOverlapped If hDevice was opened with the FILE FLAG OVERLAPPED flag IpOverlapped must point to a valid OVERLAPPED structure Under these conditions the operation is asynchronous i e overlapped operation IpOverlapped is NULL under these conditions the function will fail If the FILE FLAG OVERLAPPED was not used to open hDevice IpOverlapped 15 ignored The operation must complete before DeviceloControl will return DN6000K10SE User Guide www dinigroup com 168 APPENDIX 2 12 5 Derived Functions The following functions are based on DeviceIoControl ConfigRead ConfigW rite OL Contro
127. l be returned before the first write data is required The timing is illustrated in Figure 47 Write Control amp Data Coherency Memory Read Figure 45 SSRAM ZBT Flow trough Write Control amp Data Coherency Memory Block Figure 46 SSRAM 2 Pipeline Setup Hold 1 1 i 1 1 1 1 Write Syncburst Syncburst DSP ZBTPL Phase AD ce jut 1 1 Read Figure 47 Syncburst and ZBT 5 Timing DN6000K 10SE User Guide www dinigroup com 96 BOARD HARDWARE 6 2 1 SSRAM Configuration The DN6000K10SE is factoty stuffed with the Cypress P N CY7C1380B 133AC SSRAM devices please refer to datasheet for more information There are 524 288 x 36 SSRAM cells with advanced synchronous peripheral circuitry and a 2 bit counter for internal burst operation All synchronous inputs gated by registers controlled by a positive edge triggered Clock Input ECLK 1 4 The synchronous inputs include all addresses all data inputs address pipelining Chip Enable CE burst control inputs ADSC ADSP and ADV write enables BWa BWb BWc BWd and BWE and Global Write GW Asynchronous inputs include the Output Enable OE and burst mode control MODE DQa b c d and DPa b c d a b c d each 8 bits wide in the case of DQ and 1 bit wide in the case of DP Addresses and chip enables are registered with eithe
128. l pair between the FPGA and the Serial ATA connector is connected by way of a 0 resistor The resistor is a placeholder to allow for AC coupling if required at a future date The ML300 provides for operation as a Serial ATA host or device 7 4 SMA Connectors The SMA connectots allow fot direct connection the FPGA MGT interfaces DN6000K10SE User Guide www dinigroup com 121 BOARD HARDWARE 7 4 1 FPGA to SMA Connector The DN6000K10SE board provides four discrete MGT channels The connection between the FPGA and the SMA connectors is fairly simple involving only one wire per connector as well as a few capacitors and resistors to AC couple the signals These connections are also shown in Table 28 Table 28 Connections between FPGA and SMA Connectors FPGA Pin Connector 17 A40 J25 17 A41 J27 Please note the RocketIO Tranceiver performance in Table 29 Table 29 RocketIO Performance Speed Grade E RocketIO Tranceiver FF 2 5 2 5 2 0 PowerPC Processor Block 400 350 300 DN6000K10SE User Guide Www dinigroup com 122 BOARD HARDWARE 8 CPU Debug and CPU Trace The DN6000K10SE boatd includes two CPU debugging interfaces the CPU Debug is a vertical header and the Combined CPU Trace and Debug is a vertical mictor connector These connectors can be used in conjunction with third party tools or in some cases the Xilinx Parallel Cable IV to de
129. l pairs The receive differential pair between the FPGA and the InfiniBand HSSDC2 connector is connected by way of a 0 01 uF capacitor This capacitor AC couples the incoming signal to the FPGA The transmit differential pair between the FPGA and the InfiniBand HSSDC2 connector is connected by way of a 0 resistor The resistor is used as a placeholder to allow for AC coupling if desired at a future date 7 3 Serial ATA Serial ATA 1s the next generation of the ATA family of interfaces Providing a higher throughput through a simpler and less expensive cable Serial maintains software compatibility with older ATA implementations 7 3 1 FPGA to Serial ATA Connector The DN6000K10SE board provides for operation as a Serial ATA host or device The connection between the FPGA and the Serial ATA connector is fairly simple involving only four wires per connector as well as a few capacitors and resistors to AC couple the signals These connections are also shown in Table 27 Table 27 Connections between FPGA and SATA FPGA Pin Connector U17 A20 17 6 17 21 17 5 17 419 112 17 18 17 3 17 424 19 6 17 425 19 5 U U U U U U 17 423 192 The Serial connectors have different connections to the FPGA for transmit and receive differential pairs The receive differential pair is connected by way of a 0 01uF capacitor to AC couple the incoming signal to the FPGA The transmit differentia
130. lRead ControlWrite BAR Read Writ QL UnMapBufferAddr GetBufferSise Read OL Writ Map BAR UnMap BAR OL ResetDevice DN6000K10SE User Guide www dinigroup com 169 INTENTIONALLY LEFT BLANK 170
131. lso Consequently edif files are used in the design flow described here DN6000K 10SE User Guide www dinigroup com 50 PROGRAMMING CONFIGURING THE HARDWARE Selecting the edif file in the Module View window the user s Project Navigator box should resemble Figure 20 oject Navigator c DNS000106DN5000106 npl Edt Yew Project Source Erocess Window vr dear GRR twp elo el a xc vp20 51204 5 Creete New Source Design Entry User Constraints implement Design Generate Programming File Figure 20 Project Navigator In the Process for Source window a process is signified by the icon lt In the Process for Source window the user must right click on the Generate Programming File process and select properties The default settings are correct The user should verify a couple important options right click and selecting properties options Configuration Options Tab Configuration Pin Powerdown Pull Up DN6000K10SE User Guide www dinigroup com 51 PROGRAMMING CONFIGURING THE HARDWARE Process Properties EU a Default 4 Default 5 Default 5 Default NoWait Default NoWait Readback Options Tab Security Enable Readback and Reconfiguration www dinigroup com 52 DN6000K10SE User Guide PROGRAMMING CONFIGURING THE HARDWARE Process Properties x General Options Configuratio
132. n Options Startup Options Readback Options Encryption Options Value able Readback and E Property Create ReadBack Data Files Allow SelectMAP Pins to Persist Create Logic Allocation File Create Mask File TN The user can now generate the bit file In the Process for Source window the user must right click on the Generate Programming File process and select Run The bit file will be generated and may be found in the project directory 4 2 Creating Configuration File main txt To control which bit file on the Smart Media is used to configure the FPGA in SelectMAP mode a file named main txt must be created and copied to the root directory of the Smart Media The configuration process cannot be performed without this file Below is a description of the options that can be set in the file a description of the format this file needs to follow and an example of a main txt file 4 2 1 Verbose Level During the configuration process there are three different verbose levels that can be selected for the serial port messages e Level 0 Fatal error messages Bit file errors e g bit file was created for the wrong part bit file was created with wrong version of Xilinx tools or bitgen options are set incorrectly Initializing message will appear before configuration single message will appear once
133. nal Differential User Clock Input SMA Connectors J16 17 e System Oscillator 4 Dedicated RocketlO Clock Synthesizers The clock source selection grid formed JP3 distributes clock signals CLOCKA and CLOCKB to two Roboclock PLL clock buffers 032 033 The clock outputs from the buffers are dispersed throughout the board An external differential clock input USER_CLK option is available through the SMA connectors J16 17 A system oscillator X4 is can be used to clock the Power PC s on each FPGA if required Each FPGA has a dedicated RocketIO clock synthesizer driven by 25MHz crystal DDR clocks DDR_PLLO 3p n are generated by DDR clock buffer 034 that is driven by the FPGA U17 A dedicated 48MHz oscillator X1 clocks the Configuration CPLD U6 which in turn buffers the JTAG clock signal FPGA_TCK as well as the setial parallel clock signal DCLK required for FPGA configuration The connections between the FPGA and various clocking resources are documented in Table 13 covering the clocking inputs and outputs respectively Table 13 Clocking inputs to the FPGA DN6000K10SE User Guide www dinigroup com 74 BOARD HARDWARE Signal Name FPGA Pin Clock Conn Buffer CLK_USERn U17J21 116 CLK_USERp U17 K21 317 U17 F21 19 14 GIGE U17 G21 19 15 CLKp U17 G22 16 14 CLKn U17 F22 16 15 DDR_PLLO U17 J22 34 13 DDR PLLOn U17 K22 34 14 ECLKO U17 AP21 33 89 DCLKO
134. nd QFA1 outputs Refer to Table 4 in the datasheet JP6 A6 B6 FBDIS2 ROBOCLOCK 2 Feedback Disable This input controls the state of QFA 0 1 When HIGH the QFA 0 1 is disabled to the HOLD OFF HI Z state the disable state is determined by OUTPUT MODE When LOW the QFA 0 1 is enabled JP6 A9 B9 ROBOCLOCK 2 Output Divider Function Select Controls the divider function of bank 1 2 3 amp 4 ECLK of outputs Refer to Table 4 in the datasheet JP6 A10 B10 DN6000K10SE User Guide ROBOCLOCK 2 Output Divider Function Select Controls the divider function of bank 1 2 3 amp 4 of outputs Refer to Table 4 in the datasheet www dinigroup com 11 GETTING STARTED 3 3 Powering ON the DN6000K 10SE This section describes what is necessary to power up the DN6000K10SE 1 Install the DN6000K10SE in the test PC Note To use the board s PCI Express interface you need a motherboard with PCI Exptess slots The connector on DN6000K10SE is PCI Express x1 x4 or x8 1 4 8 lanes Most PCI Express motherboards have one x16 slot for graphics and a few x1 slots for I O Note the reference design shipped with the board is a 1 lane design so if you have an 8 lane board and you want to use this reference design an adapter is required 2 Install the SmartMedia card containing the PCI Express reference design into the DN6000K10SE WARNING Do not use a separate ATX power supply
135. ne entty in the main txt file with the following format FPGA F example bit In the above format the F following FPGA is to signal that this entry is for FPGA and FPGA F would then be configured with the bit file example bit The DN6000K10SE only has one FPGA which is FPGA F There can be any number of spaces between the and the configuration file name but they need to be on the same line Comments are allowed with the following rules e All comments must start at the beginning of the line All comments must begin with Ifacomment spans multiple lines then each line should start with Commented lines will be ignored during configuration and are only for the uset s purpose file main txt is NOT case sensitive Example of main txt statt of file main txt Verbose level 2 Sanity check y FPGA fpgaF bit DN6000K 10SE User Guide ww w dinigroup com 55 PROGRAMMING CONFIGURING THE HARDWARE line above configures FPGA with the bit file fpgaF bit end of main txt Given the above example file Verbose level is set to 2 a sanity check on the bit files will be performed and FPGA will be configured with file fpgaF bit NOTE configuration file names have a maximum length of eight 8 characters with an additional three for the extension Do not name your configuration bit files with long file names In addition all file names should be loca
136. nk FlashPath Adapter to copy bit files to the SmartMedia Card s RS232 Serial cable female to female 6ft 5 5 5 IDC 10 pin to DB 9 pin adaptor cable DN6000K 10SE User Guide www dinigroup com 7 GETTING STARTED Jumpers 0 1 x10 Y Documentation Reference CD Optional items that support development efforts not provided Xilinx ISE software cable Coax loop back cables Daughter Card ATAVRISP kit for MCU reprogramming Note The DN6000K10SE is available in an x1 x4 or x8 PCI Express channel configuration This Manual covers all products 3 Installation Instructions 3 1 J umper Setup Figure 2 indicates the factory jumper configuration of the DN6000K10SE DN6000K10SE User Guide www dinigroup com 8 GETTING STARTED JP2 RSS 6 sk 8 SSSA 9 8 2 gSsasgdqidd L ee om 2 ongonbns2 mm a 0505050565 a um NNNM ES MN m fm m 0503 4888 Figure 2 Default Jumper Setup 3 2 J umper Description Table 1 describes the functionality of the installed jumpers on the DN6000K10SE DN6000K 10SE User Guide Www w dinigroup com 9 GETTING STARTED Table 1 Jumper Desctiption Jumper
137. nlineiDocumentatiOn sei DAT LENSES TOR AGS PROGRAMMING CONFIGURING THE HARDWARE 1 PROGRAMMING THE CPLD ei Ee EV ERR ATENE EERE EA EE EO AT EE OR Y RE E RE 39 2 PROGRAMMING THE MCU 44 3 CONFIGURING 2 48 4 CONFIGURING THE FPGA USING SELECTMA Pieci N 48 4 1 File Generation for SelectMAP 49 4 2 Creating Configuration File aeina serea E E EA NEENA Ped A OR MEE Ee das 53 4 2 1 2 D 4 2 2 Sanity Check 4 2 3 8442 Synthesizer Settings 4 2 4 Format of main txt 4 3 Starting Select MAP Configuration 4 3 1 Description of Main ROI TOI 57 44 PC Bit File Sanity Check 2 45 Bitstream m BOARD HARDWARE 1 NRODDU TON TO THE __ ___ __ ______ EA 62 1 1 DN 6000KTOSE 62 2 21 FPGA 2 70 Facts 222 EPGA Bankout Diagram esr
138. ns and their DN6000K 10SE User Guide ww w dinigroup com 59 PROGRAMMING CONFIGURING THE HARDWARE Command Line Required or Optional Description Option different values 5 Optional This option prints out the current bitgen settings found in the file specified with the f option If the bit file passes the sanity check you should see something similar to sanityCheck f fpga_sm bit Performing Sanity Check on File fpga_sm bit DATE 2003 07 16 TIME 10 47 01 PART 2vp70ff1704 PILE SIZE 3262448 bytes ALL BITGEN OPTIONS ARE SET CORRECTLY If the bit file does not pass then a message stating why it didn t pass will print out For example sanityCheck f fpga_sm bit Performing Sanity Check on File fpga_sm bit DATE 2003 17 03 TIME 10 47 01 PART 2vp70ff1704 FILE SIZE 3262448 bytes ERROR PowerDown status pin is enabled you must disable this option to configure the FPGA in SeleccMAP mode 4 5 Bitstream Encryption Virtex II Pro devices have an on chip decryptor using one or two sets of three keys for triple key Data Encryption Standard DES operation Xilinx software tools offer an optional encryption of the configuration data bitstream with a triple key DES DN6000K10SE User Guide www dinigroup com 60 PROGRAMMING CONFIGURING THE HARDWARE determined by the designer keys are stored in the by instruction and retained by a battery connected to
139. number to be accessed BARO 0 BARI 1 BAR2 2 BAR3 3 BAR4 4 or BAR5 5 unsigned long byte offset Address Number of bytes to 0x0 bytes mem space offset data byte data byte of data for the write 0x00 Oxff operation 8 bits typedef unsigned char byte 2 1 3 Return Values successful function call will return zeto 2 1 4 Notes The source code for write byte is portable to each of the operating systems intended for AETEST usage DN6000K10SE User Guide ww w dinigroup com 155 APPENDIX 2 2 bar write word write word is a high level function C function which is recommended for development by users of the DN6000K10SE 2 2 1 Description bar write word allows users of the DN6000K10SE to write a word of data to any location in the Base Address Registers BARs of PCI memory All 4 gigabytes of PCI memory is available for access 2 2 2 Arguments The arguments for write word are shown in Table 41 are listed in order Table 41 write word Arguments Argument Desctiption Possible Values unsigned long barnum BAR number to be accessed BARO 0 BARI 1 BAR2 2 BAR3 3 BAR4 4 BAR5 5 unsigned long byte offset Address Number of bytes to bytes in mem space offset data wotd data A word of data for the write 0 0000 Oxffff operation 16 bits Itypedef unsigned
140. o the PPC405 Processor Block Manual for more information on the debug port signals Information JTAG is found in the IEEE standard 1149 1 1990 8 1111 CPU Debug Connector Figure 54 shows JP1 the vertical header used to debug the operation of software in the CPU This is done using debug tools such as Parallel Cable IV or third party tools This connector cannot be used when the Mictor connector is in use PPC JTAG TDO PPC JTAG TD JTAG 5 149 1 AG TM DBG 2 5V Pin 14 must l be removed HEADER 8X2 Figure 54 CPU Debug Connector 8 1 2 CPU Debug Connection to FPGA The connection between the CPU debug connector and the FPGA are shown in Table 30 These signals are attached to the PowerPC 405 JTAG debug resources using normal FPGA routing resources The JTAG debug resources are not hard wired to particular pins and are available for attachment in the FPGA fabric making it is possible to route these signals to whichever FPGA pins the user would prefer to use Table 50 CPU Debug connection to FPGA Signal Name FPGA Pin Connector U17 D24 JP1 1 PPC JTAG TDI U17 C23 JP1 3 PPC JTAG TRSTn U6 79 1 4 JTAG 17 023 DN6000K10SE User Guide Www dinigroup com 124 BOARD HARDWARE Signal Name FPGA Pin Connector TMS U17 C24 1 9
141. ock DCM2 generates phase shifted version of the user input clock It is used to recapture data from the DOS clock domain during a memory Read Data recaptured in the rclk domain is then transferred to the system clock domain The phase shift value is specific to the system and must be programmed accordingly DN6000K10SE User Guide www dinigroup com 84 BOARD HARDWARE When adequate DCM resources are available a third DCM can be used for better timing margins This DCM is used to generate WCLK a phase shifted version of the system clock WCLK is used to clock data at the DDR IOB registers during Write DCM1 BUFG CLKO clk IBUFG SSTL2 I user 1 90 gt CLK180 CLK270 1 user rst 0 CLKDV ddr clk CLK2X LOCKED OBUF SSTL 2 ddr clkb OBUF 55712 DCM CLK DCM2 RECAPTURE BUFG clkdv_16 gt gt CLK90 CLKFB CLK180 CLK270 CLKDV CLK2X LOCKED locked DCM RCLK PHASE SHIFT optional CLKO wclk CLKIN CLK90 CLKFB CLK180 CLK270 CLKDV CLK2X LOCKED RST DCM WCLK PHASE SHIFT X253 04 070500 Figure 37 DDR DCM Implementation 4 5 2 Connections between FPGA and DDR PLL Clock Buffer The connection between the FPGA and the DDR PLL Clock Driver U34 consists of a SSTL 2 differential pair DDR PLLO can be used as a feedback reference clock input The connecti
142. of memory space is accessible Figure 12 shows a sample view The user will be prompted to choose a starting address upon selecting the Bar Memory Display function Input starting address hex and 32 bit aligneg The address must be in hexadecimal and 32 bit aligned A screen similar to the one shown in Figure 12 will be outputted to the screen after entering the starting address The screen will contain 20 lines of which each line lists 8 DWORDs of data Combining the very first line and the first column on the screen specifies the corresponding address of each DWORD For example the DWORD of data 0x1663669b in column 5 row 6 is associated with 0x200080 column 1 and c row 1 Consequently the address is 0x20008c Some viewing options are listed in the final line of the screen To select an option the user needs to press the key corresponding to the letter number contained in the parentheses The options are Forward View the next 160 DWORDS of data press f DN6000K 10SE User Guide ww w dinigroup com 33 INTRODUCTION THE SOFTWARE TOOLS Back View the previous 160 DWORDS of data press b e Jump View a newly specified location press The user will be prompted for the new address in hex Goto Return to the original address specified at the beginning press 0 Quit Return to Memory Menu press q NTiSystem32 cmd exe aetest wdm exe 4 8 18 14 18 55555555
143. oint TP17 If this is not within 5 of 3 3V please try different power supplies GETTING STARTED 4 Playing with your DN6000K 10SE At this point the DN6000K10SE should be powered on with the PC booted in DOS mode The FPGA should also be programmed with the PCI Express reference design supplied by The Dini Group The ASIC Emulator Test Utility AETEST can now be used in DOS to verify the functionality of the DN6000K10SE 1 If the AETEST utility is not yet installed refer to Appendix A for installation instructions Run the AETEST utility appropriate for the Operating System AETESTDJ EXE for Windows 95 98 ME using DPMI AETEST WDM EXE for Windows 2000 aetest linux for linux The AETEST utlity should now recognize the DN6000K10SE with the DEVICE ID of 0 1611 and its VENDOR ID of Ox17DF es C WINNT System32 cmd exe aetest_wdm exe E inl x icrosoft Windows 2000 Version 5 80 2195 lt C gt Copyright 1985 2080 Microsoft Corp gt 4 aetest Naetest aetest wdm exe ymbolic link is 17df amp deu 16808 amp subsyus 9Bab5678 amp reu 47838 4 750 5808 30 81 Bbida27 6ac7 4d1f 9eb80 1dafi1b7e7131 ound device 174 41600 name DN6888K18S UirtexII Pro Single FPGA board ompiled on Sep 15 2083 at 11 19 42 ress any key 4 Follow the on screen instructions until the Main Menu is displayed DN6000K 10SE User Guide ww w dinigroup com 13 GE
144. ollow the procedures listed below for installation 1 Place the files aetestdj exe cwsdpmi exe The DOS Extender into the same directory on your PC machine 2 Boot into DOS mode if you have not already done so 3 A DOS Boot disk must be used on the Windows machine 4 Runaetestdj exe 1 2 Windows Versions The precompiled executable aetest wdm exe and its source code included in the DN6000K10SE CD ROM The driver file DnDev sys and its corresponding inf file also included in the CD ROM Follow the procedures listed below for installation 1 If the old version of AETEST s NT driver is installed on the machine it must be uninstalled DN6000K10SE User Guide www dinigroup com 152 APPENDIX 9 Start the PC with the DN6000K10SE plugged Windows should recognize the boatd and ask for a driver Note that the board must be configured with a valid bitfile Our reference design will work When the Found New Hardware Wizard box pops up click Next Select Display a list of the known drivers for this device so that I can choose a specific driver Select Other device Select Have Disk Go the directory where Dndev inf is located Source Code PCIE_Software wdmdrv drv and select it Locate the driver file DnDev sys under the directory Source Code PCIE_Software wdmdrtv drtv objchk i386 Click on the proper device and select Next 10 Run
145. one configuration 11 1 In System Operation During in system operation the primary supply to the DN6000K10SE secondary supplies is derived from the PCI Express 3V fingers 11 2 Stand Alone Operation The DN6000K10SE can be used standalone meaning it doesn t have to be plugged into a PCI Express slot An external ATX power supply is used to supply power to the DN6000K10SE in this configuration refer to Figure 57 The external power supply connects to header P11 a Tyco disk drive type of connector During standalone operation the DN6000K10SE has the following power supplies 1 5V 25V t33V e 5V e 12 e 12V The 1 5V and 2 5Vpower supplies are generated from the 3V supply using the External ATX power supply DN6000K10SE User Guide www dinigroup com 133 BOARD HARDWARE Figure 57 ATX Power Supply Any ATX type power supply is adequate The Dini Group recommends a power supply rated for 250W Note The switching regulators in the Power Supply may require and external load to operate within specifications the DN6000K10SE may not meet the minimum load requirements Dini Group recommends attaching old disk drive to one of the spare connectors 11 2 1 External Power Connector Figure 58 indicates the connections to the external power connector This header is fully polatized to prevent reverse connection and is rated for 250V AC at 13A J28 3 3V 17 1 5 584 T C585 100uF 0 1uF
146. ons are shown in Table 17 Table 17 Connection between FPGA and DDR PLL Clock Driver Signal Name FPGA Pin DDR PLL Clock Driver DDR CLK U17 P41 U34 13 DDR CLKn U17 P42 U34 14 DDR PLLO DN6000K 10SE User Guide U17J22 www dinigroup com 034 22 85 BOARD HARDWARE DDR PLLOn U17 K22 U34 23 4 6 Power PC PPC Clock A 3 3 V half can oscillator X4 and the signal SYS CLK provide an external clock source for the PPC The oscillator is socketed and the DN6000K10SE is shipped with a 100MHz oscillator refer to Figure 38 43 3V 3 3V R43 10K X 4 OSCS 1 OE vec lt R37 hi 2 Tana our ES RSYS CL SYS CLK 00MHz gy m Figure 38 PPC External Clock 4 6 1 Clocking Methodology Refer to the Xilinx application notes for more information on this subject 4 6 2 Connections between FPGA and DDR PLL Clock Buffer The connection between the FPGA and the external oscillator are shown in Table 18 Table 18 Connection between FPGA and External PPC Oscillator Signal Name FPGA Pin DDR PLL Clock Driver U27 SYS_CLK U17 AN22 X43 4 7 Rocket IO Programmable Clocks The DN6000K10SE provides two crystal oscillator to differential LVDS frequency synthesizers U16 U19 These frequency synthesizers are serially programmable The use of this variable clock source allows designers to prototype vatious interconnect technologies with different clock sour
147. ory 9 Select the Program tab and program the device by selecting the Program button in the Flash window 10 The device is now programmed and the status window should report the following DN6000K10SE User Guide www dinigroup com 46 PROGRAMMING CONFIGURING THE HARDWARE Fuses Leckie Advanced arallel High Voltage Serial f Use Current Simulator Emulator FLASH Memory Karl F data workarea dn3000K10 uPXDN 11 After programming the processor close all AVR Studio windows and open the HyperTerminal Window Press ENTER to display the first initialization instruction 12 Enter number of FPGAS on board 1 6 1 13 Please select the first FPGA on the board F A E B or D F 14 Please enter selection 1 6 for FPGA F 9 15 The initialization process will then be completed and present the user with the FPGA configuration main menu The FPGA is now ready to be configured see Configuring the FPGA using SelectMap DN6000K10SE User Guide www dinigroup com 47 PROGRAMMING CONFIGURING THE HARDWARE 3 Configuring HyperTerminal A terminal emulator is required to monitor MCU transactions The Dini Group suggests using the Windows based program HyperTerminal Hypertrm exe The configuration file for HyperTerminal DN6000K10SE ht is supplied on the CD ROM or can be downloaded from the Dini Group website The RS232 por
148. ow level function Users of the DN6000K10SE ate advised to use higher level functions such as write dword and bat read dword for development 2 12 1 Description DeviceloControl is used to send commands and receive messages from a specified device on the PCI bus in a Windows environment The QL library is based upon this function A successful DeviceloControl operation will return zero non zero value is tetutned if a failure occuts 2 12 2 Arguments The arguments for the DeviceIoControl method is listed Table 51 They are listed in otder Table 51 DeviceloControl Arguments Argument Description HANDLE hDevice Handle to the device for operation DWORD dwloControlCode Control code for the operation LPVOID IpInBuffer Pointer to a buffer containing data necessary for operation DWORD nInBufferSize Specifies the size in bytes of the buffer pointed to by IpInBuffer LPVOID IpOutBuffer Pointer to a buffer that receives the operation s output data DWORD nOutBufferSize Specifies the size in bytes of the buffer pointed to by IpOutBuffer LPDWORD IpBytesRetutned Pointer to a variable that receives the size in bytes of the data stored into the buffer pointed to by IpOutBuffer LPOVERLAPPED IpOverlapped Pointer to an OVERLAPPED structure 2 12 3 Return Values successful DeviceloControl operation will return zero non zero value is tetutned if a failure occuts DN6000K10SE User Gu
149. p com 105 BOARD HARDWARE Signal Name FPGA Pin A16 U17 AK3 A17 U17 AN2 A18 U17 AM2 SRAM4_A19 U17 AL2 A20 U17 AK2 SRAM4_ADSCn U17 AV3 SRAM4_ADSPn U17 AU3 SRAM4_ADVn U17 AT3 SRAM4_BWAn U17 AW3 SRAM4_BWBn U17 AK4 SRAM4_BWCn U17 AL4 SRAM4_BWDn U17 AM4 SRAM4_BWEn 017 4 SRAM4_CEn 017 DQAO U17 AN5 SRAM4 DQA1 017 5 DQA2 U17 AR5 SRAM4_DQA3 U17 AT5 SRAM4_DQA4 U17 AY5 SRAM4_DQA5 U17 AK6 SRAM4 DQA6 017 6 SRAM4_DQA7 U17 ANG SRAM4 DQBO U17 APG U17 AR6 SRAM4_DQB2 U17 AT6 SRAM4_DQB3 U17 AY6 SRAM4_DQB4 U17 AK7 SRAM4 DQB5 U17 AL7 SRAM4_DQB6 U17 AM7 cca DN6000K10SE User Guide www dinigroup com 106 BOARD HARDWARE Signal Name FPGA Pin SRAM4 DQB7 U17 AN7 SRAM4 DQCO U17 AP7 SRAM4 U17 AR7 SRAM4 DQC2 U17 AU7 SRAM4_DQC3 U17 AV7 SRAM4_DQC4 U17 AW7 SRAM4_DQC5 U17 AK8 SRAM4_DQC6 U17 AL8 SRAM4_DQC7 17 AM8 SRAM4_DQD0 17 AN8 SRAM4_DQD1 17 AP8 SRAM4_DQD2 SRAM4_DQD3 17 SRAM4_DQD4 17 AK9 SRAM4_DQD5 U U U U17 AT8 U U U 17 AL9 S
150. plays Literal commands that you ngdbuild enter in a syntactical statement design_name Garamond bold Commands that you select File gt Open from a menu Keyboard shortcuts Ctrl C DN6000K10SE User Guide www dinigroup com 2 ABOUT THIS MANUAL Convention Meaning or Use Example Variables in a syntax statement ngdbuild design_name fot which you must supply values References to other manuals See the Development System Reference Guide for more information Italic font ar 7 Emphasis in text If a wire is drawn so that it overlaps the pin of a symbol the two nets are not connected An optional entry or ngdbuild opton_name parameter However in bus design name specifications such as bus 7 0 they are required Braces A list of items from which you lowpwr off must choose one ot more Vertical bar Separates items in a list of lowpwr on off choices Vertical ellipsis Repetitive material that has IOB 1 Name QOUT IOB 2 Name CLKIN Horizontal ellipsis Repetitive material that has allow block block_name been omitted loct loc2 locn Prefix or suffix Indicates hexadecimal notation Read from address 0 00110373 returned 4552494 22 Letter P or n Signal is active low INTZ is active low inta is active low 3 2 Online Document The following conventions are used in thi
151. port IEEE std 1149 1 compliant JTAG test interface also used for accessing the On chip Debug system and programming and six software selectable power saving modes The micro controller interfaces to the Configuration CPLD U6 via an 8 bit bus and the SmartMedia interfaces to the CPLD via an 8 bit bus The FPGA interfaces to the CPLD via the JTAG interface and an 8 bit bus used during Serial and SelectMap programming of the FPGA The amount of internal SRAM 4 Kbytes is not large enough to hold the FAT needed for SmartMedia so an external 32K x 8 SRAM U7 was added The micro controller is programmed in system via the serial programming interface SPI The micro controller has the following responsibilities e Reading the SmartMedia card Configuring the Virtex II Pro FPGA e Executing DN6000K10SE self tests Other than FPGA configuration the micro controller has no other function Less than half of the 128KB of FLASH is used for FPGA configuration and utilities so the user is welcome to utilize the rest of the resources of the micro controller for their own applications Instructions for customizing the micro controller are contained in the file Atmegal128L datasheet please reference CD ROM or contact Atmel 3 1 1 Memory The MCU Memory map is listed in Table 8 Table 8 MCU Memory Map Address Location 0x0000 OxOFFF Internal SRAM 0x1000 0x 7FFF External SRAM 0x8000 Ox8FFF Not Used
152. press as well as message oriented push protocols 5 These features enable AS fabric to deliver a unified back plane solution for load store and message based communications AS components implement the PCI Express Base Physical Layer specification PCI Express Base Data Link Layer Flow Control protocol has been enhanced to support Unicast and Multicast traffic 10 3 PCI Express Edge Connector Figure 56 shows P6 the PCI Express edge connector x8 configuration used to interface with the host PC DN6000K10SE User Guide www dinigroup com 129 BOARD HARDWARE 3 3 48 3V 12 Bi v PCIE_PRSNTn Bik 21 12V sav BH 12V FAT PCIE SMCLK B5 5 PCIE_SMDAT A6 i B6 SMDAT HS 43 3V 1 GND His 2339 TMS ag X 3 3V PCIE_ 3 3VAUX_ TRST 3 3 Bit 33VAUX 92V PCIE_PERSTn WAKE PERST PCIE PERSTn REY B12 12 Bra RSVD GND 813 PCIE REFCLKOUTp PETpo T Bi4 GND REFCLK ayy Patt PCIE PCIE_PETnO Bis REFCLK C258 001 PCIE Pgii PCIE B15 GND 18 cPCIE 1 PERO PCIE PCIE
153. r Address Status Processor ADSP or Address Status Controller ADSC input pins Subsequent burst addresses can be internally generated as controlled by the Burst Advance Pin ADV Address data inputs and write controls ate registered on chip to initiate self timed WRITE cycle WRITE cycles can be one to four bytes wide as controlled by the write control inputs Individual byte write allows individual byte to be written Bwa controls DQa and DPa BWb controls DQb and DPb BWe controls DQc and DPc BWd controls DOd and BWa BWb BWc and BWd can be active only with BWE being LOW GW being LOW causes all bytes to be written WRITE pass through capability allows written data available at the output for the immediately next READ cycle This device also incorporates pipelined enable circuit for easy depth expansion without penalizing system performance All inputs and outputs of the CY7C1380B and is JEDEC standard JESD8 5 compatible Note CE2 and CE2n are hard wired on PWB to there respective active states Use SRAM CExn signal to select the individual devices 6 2 2 SSRAM Clocking The SSRAMs clocked directly by RoboClock 2 033 ECLK1 ECLK2 ECLK3 and ECLK4 are LVTTL33 signals and the SSRAMs are LVCMOS25 The CLK interface is level translated by the flowing circuit in Figure 48 43 3V Figure 48 Clock Level Translation DN6000K 10SE User Guide www dinigroup com 97 BOARD HARDWARE 6 2 3 SRAM Termination No
154. r Pluggable SFP Optical Transceiver The HFBR 5710L LP is capable of transmitting approximately 550 meters about 1 3 of a mile The HFBR 5710L LP pinout is shown in Table 24 Table 24 Pinout of R14K ST11 Gigabit Fiber Transceiver Pin Number Description VeeT Transmitter Ground TX Fault Transmitter Fault Indication TX Disable Transmitter Disable MOD Module Definition 2 DEF2 MOD Module Definition 1 DEF1 MOD Module Definition 0 DEFO Rate Sel Not Connected LOS Loss Of Signal VeeR Receiver Ground VeeR Receiver Ground Receiver Ground Inverse Received Data Out Received Data Out DN6000K10SE User Guide Www dinigroup com 118 BOARD HARDWARE Receiver Ground Receivet Power Transmitter Power Transmitter Ground Transmitter Data In Inverse Transmitter Data In Transmitter Ground 7 1 2 FPGA to Transceiver The connections from the FPGA to the Gigabit Ethernet Fiber transceiver are based on Figure 53 The AC coupling capacitor value of 0 1 uF provides for less than 4 ps of pattern dependent jitter PDJ for run lengths of 72 or less LASER DRIVER TX 0 9 amp EYE SAFETY SZ CIRCUITRY SYNC LOOP AGILENT HDMP 1687 RX 0 9 REFCLK 125 MHz Figure 53 Recommended connections for the HFBR 5710L NOTE 4 7 lt RES lt 10 Table 3 details the connection between
155. s document Convention Meaning or Use Example DN6000K 10SE User Guide ww w dinigroup com 3 ABOUT THIS MANUAL Blue Text Cross refetence link to a See the section Additional location in the current file or in Resources for details another file in the current Refer to Title Formats in document Chapter 1 for details Red Text Cross reference link to a See Figure 2 5 in the location in another document Virtex II Pro Handbook Blue underlined text Hyperlink to a website URL Go to http www xilinx com for the latest datasheets 4 Relevant Information Information about PCI can be obtained from the following sources Reference the PCI Special Interest Group for the latest in PCI PCI X Specifications PCI Special Interest Group http www pcisig com 2575 NE Kathryn St 17 Hillsboro OR 97124 FAX 603 693 8344 Other recommended specifications include PCI Industrial Computer Manufacturers Group PICMG http picmg org 401 Edgewater Place Suite 500 Wakefield MA 01880 USA TEL 781 224 1100 FAX 781 224 1239 Suggested reference books available from Amazon Tom Shanley Don Anderson PCI Express System Architecture Inc Mindshare Samir Palnitkar HDI A Guide fo Digital Design Synthesis ISBN 0 13 451675 3 Sundar Rajan Essential VHDL Synthesis Done Right DN6000K10SE User Guide www dinigroup com ABOUT THIS MANUAL Ed
156. se d d Feedback Bank rBDso S Select E ane Matrix m PS 40A0 nis Divide LEG 4 32 mase MM _ Select 4QB0 B gt Matrix 4081 gt Divide and E 1 Bank3 5 Prase aM Select 0 51 gt 0153 Matrix 3QB1 2 gt 20 0 ide and KL SORI Bank 2 2050 gt 2050 eL Select 2080 T Matrix gt 20B1 1F0 gt 1QA0 428 Divide and 1QA1 1 Phase Bank 1 1050 ET Select 1080 Matrix 1QB1 Figure 34 RoboClock Functional Block Diagram 4 3 2 RoboClock Configuration J umpers Header JP4 JP5 and JP7 enable the user to configure the RoboClocks as required These 3 way headers and allow the signal to float MID or be pulled to GND LOW 3 3V HIGH A brief description of each pin is given in Table 15 Table 15 RoboClock Configuration Signals Signal Name Desctiption Connector ROBO F0 CCLK Output Phase Function Select Controls the JP4 B5 phase function of bank 3 amp 4 CCLK of outputs refer to Table 3 in the datasheet ROBO F1 CCLK Output Phase Function Select Controls the JP4 B6 phase function of bank 3 amp 4 CCLK of outputs refer to Table 3 in the datasheet DN6000K 10SE User Guide www dinigroup com 78 BOARD HARDWARE Signal Name Desctiption Connector
157. settings A PC version of the sanity check can be run on your bit files before copying them onto the Smart Media see section PC Bit File Sanity Check for more details 4 2 3 8442 Synthesizer Settings There two 8442 Cock Synthesizers on board the DN6000K10SE Each one is capable of generating a frequency between 31 25 to 700Mhz Note This feature is only available on version 1 6 and up of the MCU 4 2 4 Format of main txt The format of the main txt file is as follows 1 The first nonempty uncommented line main txt should be Verbose level X where X can be 0 1 or 2 If this line is missing or X is an invalid level then the default verbose level will be 2 DN6000K 10SE User Guide ww w dinigroup com 54 PROGRAMMING CONFIGURING THE HARDWARE 2 second nonempty uncommented line in main txt tells whether or not to 6 perform a sanity check on the bit files before configuring an FPGA Sanity check y where stands for yes for no If the line is missing or the character after the 2 is not or n then the sanity check will be enabled For the clock synthesizer the line should read 8442 lt clk gt freq In this case lt clk gt selects the 8442 synthesizer to set up Valid choices are GIGE or INF freq is the desired output frequency and can be any number between 31 25 and 700 For each FPGA that the user wants to configure there should be exactly o
158. sh 5 Run aetest_solaris 6 user may need to run chmod on aetest_solaris to make it executable type chmod aetest_solaris The driver is compiled with the gcc compiler aetest_solaris is compiled with gmake You can download it from the GNU website The make from the Solaris installation does not work with our makefile format NOTE All text files including scripts are DOS text format with an extra carriage return character after every new line they must be converted DN6000K10SE User Guide www dinigroup com 154 APPENDIX 2 Appendix AETEST Basic C424 Functions The AETEST utility program is built on a core of basic C functions These functions perform a variety of PCI accesses e g configuration reads writes memory read wtites and test functions e g memory tests This appendix will describe a handful of these functions 2 1 bar write byte write byte is a high level function C function which is recommended for development by usets of the DN6000K10SE 2 1 1 Description bar write byte allows users of the DN6000K10SE to write a byte of data to any location in the Base Address Registers BARs of PCI memory All 4 gigabytes of PCI memory is available for access 2 1 2 Arguments The arguments for bar write byte are shown in Table 40 They are listed in order Table 40 write byte Arguments Argument Desctiption Possible Values unsigned long barnum BAR
159. sion begin to outweigh the costs over single ended techniques when the signal transmission times approach 10 ns This represents signaling rates of about 30 Mbps clock rates of 60 MHz in single edge clocking systems and above LVDS is defined in the TIA EIA 644 standards Connector J2 is a Mini D Ribbon MDR connector 50 pin manufactured by 3M used specifically for high speed LVDS signaling The connector mates with a standard off the shelf 3M cable assembly P N 14150 EZBB XXX 0LC where XXX is 050 0 5 m 150 15 m 300 3 0 m 500 5 0 m Please contact for further details http www 3m com T DN6000K10SE User Guide www dinigroup com 142 BOARD HARDWARE 12 2 6 Connection between FPGA and the Daughter Card Headers Table 39 shows the IO connections between the DN3000K10SD headers and the FPGA IO pins The VCCO of the IO banks are connected to 2 5V Table 39 Connection between FPGA and the Daughter Card Headers Daughter Card Connections DN6000K10SE IO Connections Test Signal Name Connector Test Signal Name FPGA Pin Header Header j1 001 No Connect P10 1 12V 11 002 No Connect P10 2 GND 11 003 5 1 10 3 2 5 J1 004 No Connect P10 4 5V J1 005 BCLK1 J5 3 P10 5 2 5V J1 006 No Connect P10 6 5V J1 007 CCLK1 J5 5 P10 7 CCLK1 J1 008 No Connect P10 8 GND J1 009 No Connect P10 9 3 3V J1 010 BP2N3 P2N3 J3 1 P10 10 E
160. ss offset a DWORD count and the number of iterations The user is also prompted if the program should stop if error occurs or if the program should display any errors that occur This allows for maximum flexibility when debugging a design with an oscilloscope or debugging any memories or memory locations on your PCI bus The memory test is very complete performing a write then a read to every location a read from every location and then read wtite read test to every location All other memory test options listed in the memory menu are based on this generic memory test function H System32 cmd exe aetest_wdm exe M gt Main Menu Q gt Quit PCI BASE ADDRESS 2 bbaie 1 2 68880008 3 68000008 66660000 5 66000000 Please select option p lemory test of a range within bar ar 68 5578 tarting address offset byte addr 8x8012080008 word count 8x28 lumber of Iterations for endless gt 1 top if an error occurs or isplay any errors that occur or 2 oing write read all read all addr oing lt read write read gt all data cpu_addr gt done vith memory test ress a key Cpossibly twice Figure 13 Bar Memory Range Test Bar Memory Address Data Bitwise Test Opt k Same as BAR Memory Range Test except this tests the data bits one at a time DN6000K 10SE User Guide ww w dinigroup com 35 INTRODUCTION THE SOF
161. synthesized next generation connectivity standards to be seamlessly bridged and complex hardware and software systems to be co developed rapidly with in system debug at system speeds Together these capabilities usher in the next programmable logic revolution 1 1 Summary of Virtex Il Pro Features The Virtex II Pro has an impressive collection of both programmable logic and hard IP that has historically been the domain of the ASICs e High performance FPGA solution including Up to twenty four RocketIO embedded multi gigabit transceiver blocks based on Mindspeed s SkyRail technology DN6000K10SE User Guide www dinigroup com 16 INTRODUCTION VIRTEX II PRO AAND ISE o Up to four IBM PowerPC RISC processor blocks Based Virtex IT FPGA technology Flexible logic resources up to 125 136 Logic Cells SRAM based in system configuration Active Interconnect technology SelectRAM memory hierarchy Up to 556 Dedicated 18 bit x 18 bit multiplier blocks High performance clock management circuitry SelectIOTM Ultra technology o Digitally Controlled Impedance I O 1 2 PowerPC 405 Core Embedded 300 MHz architecture core Low power consumption 0 9 mW MHz Five stage data path pipeline Hardware multiply divide unit Thirty two 32 bit general purpose registers 16 KB two way set associative instruction cache 16 KB two way set associative data cache Memory Managemen
162. t Unit MMU 64entry unified Translation Look aside Buffers TLB Variable page sizes 1 KB to 16 Dedicated on chip memory OCM interface Supports IBM CoreConnect bus architecture Debug and trace support Timer facilities 1 3 RocketlO 3 125 Gbps Transceivers Full duplex serial transceiver SERDES capable of baud rates from 622 Mb s to 3 125 Gb s please reference the Xilinx datasheet for speed grade limitations 80 Gb s duplex data rate 16 channels DN6000K10SE User Guide www dinigroup com 17 INTRODUCTION VIRTEX II PRO AAND ISE Monolithic clock synthesis and clock recovery CDR e Fibre Channel Gigabit Ethernet 10 Gb Attachment Unit Interface and Infiniband compliant transceivers 8 16 or 32 bit selectable internal FPGA interface 10B encoder and decoder 50 75 on chip selectable transmit and receive terminations Programmable comma detection e Channel bonding support two to sixteen channels Rate matching via insertion deletion characters e Four levels of selectable pre emphasis e Five levels of output differential voltage Per channel internal loopback modes 2 5V transceiver supply voltage 1 4 Virtex4l FPGA Fabric Description of the Virtex II Family fabric follows SeleccRAM memory hierarchy o Up to 10 Mb of True Dual Port RAM in 18 Kb block SeleccRAM resoutces o Upto 1 7 Mb of distributed SelectRAM resources o High performance interfa
163. t is configured with the following parameters e Bits per second 9600 e Data bits 8 e Parity None e Stop Bits 1 Flow control None Terminal Emulation VT100 A cable that converts the 5 x 2 header to a is shipped with the DN6000K10SE Insert the 5 x 2 header into the MCU RS232 header P2 P2 is not keyed ensure correct pin orientation Note MCU RS232 Header P2 is not keyed Ensure correct pin orientation Pin 1 is indicated with a letter 1 on the board silkscreen as well as a dot Pin 1 on the 5 X 2 cable header is indicated with a triangular shape printed on the connector female to female RS232 cable is provided with the DN6000K10SE This cable will attach directly to the RS232 port of a PC The Dini Group suggests Jameco as a possible supplier http www jameco com The part number is 132345 Male to female extension cables are part number 25700 4 Configuring the FPGA using SelectMAP The simplest mode of configuration for the DN6000K10SE Virtex II Pro FPGA involves the SelectMAP configuration method using a SmartMedia card The DN6000K10SE ships with two 32 MB SmartMedia cards One of these SmartMedia cards contains a reference design bit file produced for SelectMAP configuration and a file named main txt that sets the configuration options see Creating Configuration File main txt The SmartMedia card containing the reference design has been write DN6000K10SE User Guide www dinigroup com 48
164. table clock inputs This was observed when the CY7B994V part was operating at a nominal frequency of 36 4MHz with FS set LOW Identical clocks were sent to PLL2B and PLL2BN For the CY7B994V part the operating frequency can reach up to 200 MHz However the maximum output frequency is 185MHz This means when 185 MHz lt lt DN6000K10SE User Guide www dinigroup com 82 BOARD HARDWARE 200MHz the output divider must be set to at least 2 Otherwise the RoboClocks will output garbage 4 3 5 Customizing the Oscillators The user can customize the frequency of the clock networks by stuffing different oscillators in X2 and The DN6000K10SE is shipped with 14 318MHz oscillator in location X2 and 33 333MHz oscillator in X3 The RoboClocks are not 5V tolerant so 3 3V oscillators are necessary The Dini Group suggests Digi Key http www digikey com as a possible source for the oscillators Of note is the Epson line of oscillators called the SG 8002 Programmable Oscillators Any frequency between 1 00MHz 106 25MHz can procured in the normal Digi Key shipping time of 24 hours A half can 3 3 V CMOS version is needed with a tolerance of 50ppm The part number for an acceptable oscillator from this family would be SG 8002DC PCB ND e Package SG 8002DC Halfcan Output Enable 3 3 V CMOS e 2450 ppm If the order is placed via the web page the requested frequency to two decimal places is placed in
165. tatus Indicators 126 92 EED s eet eee tete ee ee M e en tee tie e tbe te Ree eode 127 10 PCI EXPRESS INTERFACE 10 1 PCP Express Slots es e B E 128 10 2 POI Express 129 10 3 PCI Express Edge Connector 10 3 1 Connection between the PCI connector and the 130 10 4 PCI Expr ss ClockIntevfaCel s e aceto e oae ht e ERE e een WIRE e LL 132 10 4 1 Connection between the PCI Express connector and the FPGA 132 11 POWER SYSTEM 132 11 1 In System Operation 133 11 2 Stand Alone Operaatiot e RR RR UA OBERE RARE I HERE LI 133 11 2 1 External Power eee 134 11 2 2 Power Monitors 135 11 2 3 Power Indicators 135 12 TEST HEADER amp DAUGHTER CARD CONNECTIONS eee e rine eee eet eerte da raesent ee eene etae ben EUR e eese e 135 12 1 Test Header iiie iens 135 12 1 1 Test Header Connector 4137 12 1 2 Test Header Pin Numbering 137 12 2 DN3000KIOSD Dag hier NR 138 12 2 1 Daughter Card LED a ae a a a e a aa a a aaa 140 12 2 2 Power Supply 141 12 2 3 Unb ffered EEE 142 12 2 4 Buffered
166. te RESO XOU EIE WU EO XR DIEM 3 FPGA CONFIGURATION care 3 1 Micro Controller Unit 3 1 1 MCU Memory 3 1 2 MCU IT AG pU 3 1 3 MCU Programming Connector 67 3 1 4 RS232 Interface 67 3 2 Configuration 68 3 2 1 CPED Programing Connector s n n me da be ep v a o E b HE 69 5 29 Design Notes oi the CPED 69 3 3 SmartMedia 3 3 1 SinartMedia Connector s uo e ER HERR ENERO EATER CR TUR 71 3 3 2 SmartMedia connection 16 CPLD MCU i 71 3 4 Boundary Scan JTAG IEEE 1532 Mode 72 3 4 1 FPGA Serial JTAG Connector 72 3 4 2 FPGA JTAG connection to Configuration CPLD T 4 CLOCK GENERATION m 4 1 Clock e ue ER ERR 4 2 Clock Source Jumpers 42 1 Clock Source Jumper Headers CER Y epe ER yc E RD Ere edes 76 4 3 HG E 77 4 3 1 RoboClock PLL Clock Buffers s 4 3 2 RoboClock Configtiration J fmpers SE tetro denis 78 4 3 3 Clock Configur tion oie 82
167. ted in the root directory of the Smart Media card no subdirectories folders are allowed Since the main txt file controls which bit file is used to configure the FPGA the Smart Media card can contain other bit files OU CUT CIE ee V CI TI TI If using the reference design SmartMedia card that came with the DN6000K10SE then no files need to be copied to the card Otherwise copy your bit file and main txt to the root directory of the SmartMedia card using the FlashPath floppy adapter or some other means Make sure the dipswitch 52 is set for SeleccMAP as shown in Table 4 Table 4 52 Dipswitch Configuration Settings Signal Name Pins Status MSELO Pins1 amp 8 Closed MSEL1 Pins2 amp 7 Open MSEL2 Pins 3 amp 6 Open DIP_SW3 Pins 4 amp 5 X Set up the serial port connection as desctibed above in Configuring HyperTerminal Next place the SmartMedia card in the SmartMedia socket on the DN6000K10SE and turn on the power NOTE the can only go in one way The SmartMedia is hotswappable and can be taken out or put into the socket even when the power is on Once the power has been turned on the configuration process will begin as long as there is a valid SmartMedia card inserted properly in the socket If there 15 not a valid SmartMedia card in the socket then 051 will be lit see Table 32 for GPIO LED s and the Main Menu will appear from the serial port
168. termination is necessary but the option to use DCI is available on all signals 6 2 4 SSRAM Connection to the FPGA The SSRAM memory components are connected to the FPGA on Bank 2 and Bank 3 as listed in Table 22 The VCCO of the IO banks are connected to 2 5V Table 22 Connection between FPGA and SRAM s FPGA Pin 01714 U17 K1 U17J1 U17 G1 U17 F1 U17 E1 U17 F3 U17 G3 U17 H3 U17 K3 U17 H2 U17J2 U17 K2 01712 U17 M2 17 D3 17 3 17 02 SRAM1_ADSCn SRAM1_ADSPn Che Ga Gay Gan Sa Ce C ea Sa Gee DN6000K10SE User Guide www dinigroup com 98 BOARD HARDWARE Signal Name FPGA Pin SRAM1 ADVn 17 13 SRAM1 BWAn U17 G4 SRAM1 BWBn U17 H4 SRAM1_BWCn 1717 74 SRAM1_BWDn U17 L4 SRAM1_BWEn U17 M4 SRAM1_CEn U17 H5 SRAM1_DQAO U17 D6 1 DQA1 U17 E6 SRAM1_DQA2 U17 G6 SRAM1_DQA3 U17 H6 SRAM1_DQA4 U17 J6 SRAM1 DQA5 U17 K6 SRAM1_DQAG6 U17 L6 SRAM1_DQA7 U17 N6 SRAM1 DOBO U17 D7 SRAM1_DQB1 U17 E7 SRAM1_DQB2 U17 F7 SRAM1_DQB3 U17 H7 SRAM1_DQB4 U17J7 SRAM1_DQB5 U17 K7 SRAM1_DQB6 UIT L7 SRAM1_DQB7 U17 M7 SRAM1 U17 N7 SRAM1_DQC1 U17 J8 SRAM1_DQC2 U17 K8 SRAM1_DQC3 U17 L8 SRAM1_DQC4 U17 M8 SRAM1_DQC5 U17 N8 i c
169. tex4l Pro Embedded Development Kit EDK is the Virtex II Pro Embedded Development Kit and is included to provide an existing framework of hardware and software code to explore the capabilities of the Virtex II Pro as well as a basis to build new systems A wide variety of software and hardware tools are used to build a ProTM design EDK The design flow is a tool chain methodology that exists to simplify the entire design process by providing integration between the tools and automating tasks The main focus of the design flow is integrating the programs with each other to accomplish the system design The system design process can be loosely divided into the following tasks e Builds the software application DN6000K10SE User Guide www dinigroup com 22 INTRODUCTION TO VIRTEX II PRO AAND ISE e Simulates the hardware description e Simulates the hardware with the software application e Simulates the hardware into the FPGA using the software application in on chip memory e Runs timing simulation e Configures the bitstream for the FPGA DN6000K10SE User Guide www dinigroup com 23 INTRODUCTION THE SOFTWARE TOOLS Chapter Introduction to the Software Tools This chapter introduces the software tools as well as references to more information 1 Exploring the Software Tools 1 1 AETEST AETEST utility program is used primarily to test and verify the functionality of the DN6000K10SE Logic Emulation board
170. the FPGA is configured level All messages that Level 0 displays Displays configuration type should be DN6000K 10SE User Guide ww w dinigroup com 53 PROGRAMMING CONFIGURING THE HARDWARE Displays current FPGA being configured if the configuration type is set to SeleccMAP Displays a message at the completion of configuration for each FPGA configured e Level 2 All messages that Level 1 displays Options that are found in main txt Bit file names for each FPGA as entered in main txt Maker ID device ID and size of Smart Media card All files found on Smart Media card If sanity check is chosen the bit file attributes will be displayed part package date and time of the bit file During configuration will be printed out after each block 16 KB has successfully been transferred from the Smart Media to the current FPGA 4 2 2 Sanity Check The Sanity Check if enabled verifies that the bit file was created for the right part the right version of Xilinx was used and the bitgen options were set correctly If any of the settings found in the bit file are not compatible with the FPGA a message will appear from the serial port and the user will be asked whether or not they want to continue with the bit file Please see the section Bit File Generation for SeleccMAP Configuration for details on which bitgen options need to be changed from the default
171. the PRGA 6 37 DDDRESDRAM spror i 107 6 3 1 Basics G DDR Operationin 128 108 6 3 2 DDR SDRAM Configuration tette tet 108 6 3 3 DDR SDRAM Clocking 109 6 3 4 DDR SDRAM Termination 109 6 3 5 DDR SDRAM Power Supply 111 6 3 6 DDR SDRAM Connection to the FPGA 111 7 ROCKET JO TRANSCEIVERS otoi reprend _ EIUS 117 7 1 Gigabit Ethernet Fiber 7 1 1 Agilent HFBR 5710L LP Small Form Factor Pluggable SFP Optical Transceiver J2 3 118 7 1 2 FPGA to TransCei ver REP M 119 7 2 Infiniband HSSCD2 7 2 1 FPGA to InfiniBand HSSDC2 120 7 3 121 7 3 1 FPGA to Serial ATA Connector 121 7 4 SMA Connectors 7 4 1 FPGA to SMA Connector 8 CPU DEBUG AND CPU TRACE 8 1 CPU A 123 8 1 1 CPU Debug Connector 124 8 1 2 CPU Debus Connection to FPG E 124 8 1 3 br EN E E E 125 8 1 4 CPU Trace Connector iiien 125 8 1 5 Combined CPU Trace Debug Connection to FPGA 126 9 GPIO EEDJ S eite eren ee getrennt 126 9 1 S
172. the VBATT pin when the device is not powered Virtex II Pro devices can be configured with the corresponding encrypted bitstream using any of the configuration modes described previously A detailed description of how to use bitstream encryption is provided in the Pro Platform FPGA User Guide DN6000K 10SE User Guide ww w dinigroup com 61 BOARD HARDWARE Board Hardware l Introduction to the Board DN6000K10SE Logic Emulation boatd provides for a comprehensive collection of peripherals to use in creating a system around the Virtex II Pro FPGA Figure 23 is a block diagram of the DN6000K10SE Logic Emulation board Chapter ROCKET IO INTERFACES 25V GbEFIBER SFP smaa svaz 5 1 P oro opo ofo sata sata ni lt lt DN6000K10SE GBEFIBER SFP opo opo BLOCK DIAGRAM gt 1 2 2 EE CLOCK ES SMARTMEDIA GiG E SYNTH DSC c PowerPC 405 183264128MB y 160 FPGA CONFIG BIT CLOCK Ml oa INFINIBAND SYNTH Td PowerPC 405 Y PROCESSOR BLOCK 2 Us sma mcu Idi ustRcLock 8 Us i SMA Ir CONNECT
173. the Web Order Notes The datasheet is on the CD ROM for this oscillator Any polarity of output enabled for each oscillator on pin 1 is acceptable Ensure the proper jumper settings for JP3 B9 JP3 B10 See Table 15 for a description 4 4 External Clocks The clock source jumper JP3 allows the user a simple means to attach external clocks to the clock grid The user can attach 10 pin ribbon cable to JP3B C which allows for connection the differential pair inputs of both RoboClocks JP3C ground pins for signal integrity These signals are described in Table 14 Both differential pairs provide some flexibility The user can bring a single 3 3V TTL input It can be attached to either input However the other input must be left open The user can provide a differential clock input to the pair to the RoboClocks 4 4 1 External SMA Clock J16 J17 are SMA connectors to allow an external differential clock USER CLKp n input to the FPGA 017 Resistors R224 R237 allows for AC coupling if required Refer to Figure 36 DN6000K10SE User Guide www dinigroup com 83 BOARD HARDWARE R224 CLK USERnR CLK USERn 3 4 mC 1 9 3 4 USERpR ied USER ed p VAM p Figure 36 External SMA Clock 4 4 2 Connections between FPGA and External SMA Clock Inputs The connection between the FPGA and the external SMA clock inputs are shown in Table 16 Table 16 Connection between FPGA
174. to this new file If the power is turned off or the reset button S1 is pressed the configuration file is changed back to the default main txt List files on This option prints out a list of all the files found on the SmartMedia SmartMedia catd Select FPGA to This option allows the user to select an FPGA to configure via program via JTAG JTAG Display Contents ofa This option allows the use to list the contents of any text file on TXT File the Smart Media card Selecting Option 2 results in the following menu to be displayed refer to Figure 22 DN5000106 HyperTerminal _ x Ele Edit View Transfer Help oel 5 sees ENTER SELECTION 2 INTERACTIVE CONFIGURATION MENU 1 Select bit files to configure FPGA s 2 Set verbose level current level 2 3 Disable sanity check for bit files M Main menu ENTER SELECTION Connected 1 13 25 Auto detect 96008 1 ScRoLL caps Capture Print echo Figure 22 Interactive Configuration Option Menu DN6000K 10SE User Guide ww w dinigroup com 58 PROGRAMMING CONFIGURING THE HARDWARE Table 6 desctibes the Interactive Configuration Menu options Table 6 HyperTerminal Interactive Configuration Menu Options Function Description Select a bit file to The user is able to select a bit file from a list of bit files found on configure FPGA s the SmartMedia card for configuring the FPGA Set
175. ty program unless otherwise noted Certain functions may be missing from the figures However all functions will be discussed in their proper context DN6000K10SE User Guide www dinigroup com 25 INTRODUCTION THE SOFTWARE TOOLS 1 1 1 Getting Started with AETEST Once AETEST is installed and the DN6000K10SE board is powered on the user can execute his her incarnation of AETEST The DN6000K10SE is defined by its DEVICE ID of 0 1600 and its VENDOR ID of 0x17df AETEST should immediately recognize the DN6000K10SE Logic Emulation board shown in Figure 3 AWINNT System32 cmd exe aetest_wdm exe 10 xl icrosoft Windows 2000 Version 5 88 2195 Copyright 1985 2000 Microsoft Corp gt aetest 5 ymbolic link is rae 98ab5678 amp reu 47138 amp 4a758558 amp 0838 27 1dafib e7131 gt ound device 174 41600 name DNGBBBKi1B8S UirtexII Pro Single FPGA board ompiled on 15 2003 at 11 19 42 ress any key Figure 3 DN6000K10SE Board Recognition Upon recognition AETEST will notify the user which device was found In certain implementations the entire configuration space and the configuration of the BARs is sent to the screen immediate following the board recognition notification If AETEST does not recognize the DN6000K10SE AETEST will alert the user See Figure 4 5 C WINNT System32 cmd ex
176. wide variety of future computing and communication platforms Key PCI attributes such as its usage model load store architecture and software interfaces are maintained whereas its parallel bus implementation is replaced by highly scalable fully serial interface PCI Express takes advantage of recent advances in point to point interconnects Switch based technology and packetsized protocol to deliver new levels of performance and features Power Management Quality Of Service QoS Hot Plug Hot Swap support Data Integrity and Error Handling ate among some of the advanced features supported by PCI Express Note Hot Plug Swap is not available on this product 10 1 PCI Express Slots A PCI Express lane represents a set of differential signal pairs one pair for transmission one pair for reception To scale bandwidth a Link may aggregate multiple Lanes denoted by xN where N may be any of the supported Link widths The PCI Express specification describes operations for x1 x2 x4 x8 x12 x16 and x32 Lane widths It is possible for a PCI Express card to be plugged into a slot that was intended for a wider card but not one that was intended for a smaller card For example the DN6000K10SE board in a x8 configuration can be plugged a x8 or x16 slot but not in a x4 or x1 slot However you can purchase an adapter that allows DN6000K10SE User Guide www dinigroup com 128 BOARD HARDWARE an x4 x8 x16 board to be plugge
177. win Breecher The Booster Improve Your IO Performance Dramatically DN6000K10SE User Guide www dinigroup com GETTING STARTED Chapter Getting Started Congratulations on your purchase of the DN6000K10SE LOGIC Emulation Board You can begin by installing the software or by powering on your DN6000KT0 SE If you wish to begin installation please follow the installation instructions The remainder of this chapter describes the contents of the box and how to start using the DN6000K105E LOGIC Emulation Board 1 Precaution The DN6000K10SE is sensitive to static electricity so treat the PCB accordingly The target markets for this product are engineers that are familiar with FPGA s and circuit boards so a lecture in ESD really isn t appropriate and wouldn t be read anyway However the following web page has an excellent tutorial on the Fundamentals of ESD for those of you who are new to ESD sensitive products http www esda ote basics patt1 cfm The DN6000K10SE has been factory tested and pre programmed to ensure correct operation You do not need to alter any jumpers or program anything to see the board work A reference design is included on the enclosed CD Please verify that the board is in working order by following the steps below 2 DN6000K 10SE LOGIC Emulation Kit The DN6000K10SE LOGIC Emulation Kit provides a complete development platform for designing and verifying applications based on the Xilin
178. x Virtex II Pro FPGA family The DN6000K10SE can be hosted in a PCI Express slot or can be used in a stand alone application This DN6000K10SE enables designers to implement embedded processor based applications with extreme flexibility using cores and DN6000K 10SE User Guide www dinigroup com 6 GETTING STARTED customized modules The Virtex II Pro FPGA with its integrated PowerPC processor and powerful Rocket I O Multi Gigabit Transceivers MGT make it possible to develop highly flexible and high speed serial transceiver applications The DN6000K10SE its standard configuration includes PCI Express x1 x4 x8 interface 512K x 36 SRAM 4 16M x 16 DDR SDRAM 4 4M x 16 FLASH 2 an RS232 port for monitor and a SmartMedia interface for configuration There 9 low skew clock sources that are distributed to the and the test header A 200 pin test header allows for connection to individual FPGA s IO banks using a custom daughter Figure 1 shows the DN6000K10SE Logic Emulation Board Figure 1 DN6000K10SE LOGIC Emulation Board DN6000K10SE LOGIC Emulation Kit includes the following DN6000K10SE development board 2VP70 or 2VP100 in the FF1704 package Note Specific speed grade parts required for various RocketIO Power PC operating speeds refer to Xilinx datasheet 32MB SmartMedia Card with reference design and main txt 32M B SmartMedia Card for customer use bla
179. y Write Read DWORD Figure 10 BAR Memory Fill Figure 11 Bar Memory Write Figure 12 Bar Memory Display Figure 13 Bar Memory Range Test Figure 14 Bar Memory Address Data Bitwise Test Figure 15 Flash Menu Figure 16 Daughter Board Menu Figure 17 New Project Screen Shot Figure 18 Input File Figure 19 New Project Dialog Box Figure 20 Project Navigator Figure 21 Main Menu Figure 22 Interactive Configuration Option Menu Figure 23 DN6000K10SE Block Diagram Figure 24 Bankout Diagram Figure 25 MCU JTAG Connector Figure 26 MCU Programming Connector Figure 27 MCU Seri Figure 28 CPLD Programming Header Figure 29 SmartMedia Connector Figure 30 FPGA Serial JTAG Connector Figure 31 Clocking Block Diagram Figure 32 LVPECL Clock Input Terminations Figure 33 Clock Source Jumper Figure 34 RoboClock Functional Block Diagram Figure 35 RoboClock Configuration Jumpers Figure 36 External 5 Clock Figure 37 DDR DCM Implementation Figure 38 PPC External Clock Figure 39 REFCLK BREFCLK Selection Logic Figure 40 Reset Topology Block Diagram Figure 41 FLASH Connection Figure 42 SSRAM Connection Figure 43 SSRAM Flow trough Figure 44 SSRAM Pipeline Figure 45 SSRAM ZBT Flow trough Figure 46 SSRAM ZBT Pipeline Figure 47 Syncburst and ZBT SSRAM Timing Figure 48 Clock Level Translation Figur

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