Home

i960 Microprocessor User`s Guide for Cyclone and PCI

Contents

1. 3 4 1 Hardware Reference DRAM Performance The DRAM controller automatically adjusts wait states based on processor type processor clock frequency and memory speed The controller supports burst transfers using the interleaved banks to maximize performance Table 3 4 lists DRAM performance The default memory configuration uses 70 ns memory At processor frequencies of 25 and 40 MHz wait states are reduced using 60 ns memory Table 3 4 DRAM Access Times Frequency Operation DRAM Speed Clock Cycles Wait States ami 16 MHz Read 60 70ns 3 1 1 1 1 0 0 0 36 Mbytes sec 20 MHz Read 60 70ns 3 1 1 1 1 0 0 0 45 Mbytes sec 25 MHz Read 60ns 3 1 1 1 1 0 0 0 66 Mbytes sec 25 MHz Read 70ns 4 1 1 1 12 2 0 0 0 50 Mbytes sec 33 MHz Read 60 70ns 4 1 1 1 12 2 0 0 0 66 Mbytes sec 40 MHz Read 60ns 4 1 1 1 12 2 0 0 0 80 Mbytes sec 40 MHz Read 70ns 5 2 2 2 1 3 1 1 1 53 Mbytes sec 16 MHz Write 60 70ns 3 2 2 2 1 1 1 1 25 6 Mbytes sec 20 MHz Write 60 70ns 3 2 2 2 1 1 1 1 32 Mbytes sec 25 MHz Write 60ns 3 2 2 2 1 1 1 1 44 5 Mbytes sec 25 MHz Write 70ns 4 2 2 2 1 2 1 1 1 36 Mbytes sec 33 MHz Write 60 70ns 4 2 2 2 12 2 1 1 1 48 Mbytes sec 40 MHz Write 60ns 4 2 2 2 1 2 1 1 1 58 Mbytes sec 40 MHz Write 70ns 4 2 2 2 1 2 1 1 1 58 Mbytes sec NOTES 1 Bandwidths stated are sustained bandwidths not peak 2 The extra cycle is the overhead of DRAM precharge DRAM precharge time only impa
2. DOS based computer with PROCOMM CROSSTALK or other telecommunication programs e UNIX workstation with an external serial port e g SUN Configure the serial port for 1200 115200 baud 8 bits one stop bit no parity Host Debugger Interface Library HDIL Method The MONDB EXE utility provided with MON960 allows you to download execute and debug an application program on the Cyclone EP This utility differs from standard terminal emulation programs in that it allows you to download executable images through a serial or parallel port or via the PCI bus When using the serial port the MONDB EXE utility supports the standard baud rates from 1200 to 115200 baud to communicate and download to the Cyclone EP Downloading via either the parallel port or PCI bus is typically much faster than a serial port actual performance depends on your system s hardware capabilities Refer to MON960 Debug Monitor User s Guide for detailed information Source Level Debugger You may use a source level debugger such as Intel s DB960 GDB960 or other to establish serial communications with the Cyclone EP The MON960 Host Debugger Interface Library HDIL provides the interface between MON960 and these types of debuggers Power Requirements The Cyclone EP requires a stable power source of at least 3 5 A at 5 VDC The included power supply meets these requirements and connects to J7 If a card is designed for the expansion bus which require
3. Hardware Installation Follow these instructions to get your new Cyclone EP running Be sure you have all items listed on the checklist provided with your Cyclone Evaluation Platform Verify Cyclone EP is Functional Warning MAKE SURE YOU ARE GROUNDED BEFORE REMOVING THE ANTI STATIC BAG OTHERWISE SEVERE DAMAGE MAY OCCUR TO THE BOARD 1 Visually inspect the board for any damage that may have occurred during shipment If there are visible defects return the board for replacement 2 Place the board in a static free area always take precautions to minimize static electricity 3 Verify that an 1960 processor module is installed 4 Verify that the SwapROM switch S1 position 3 DIP switch is set to OFF 5 To install the PCI SDK Platform in a host system PCI slot follow the manufacturer s instructions for opening the host system and installing an expansion board in a PCI slot 6 Serial port connection for communicating and downloading connect the RS 232 cable the phone cord from an appropriate port COM1 or COM2 on a PC to J5 on the Cyclone EP Your system has either a DB 9 9 pin or a DB 25 25 pin connector for its RS 232 port Both 9 pin and 25 pin connectors are provided 7 Parallel port connection optional if using MONDB EXE for downloading connect a 25 pin to 25 pin parallel port cable from an appropriate port LPT1 or LPT2 on a PC to J1 on the Cyclone EP 8 Power supply connections not required for th
4. PCI SDK Evaluation Platforms Parts List l n e Table A 1 Cyclone EP PCI SDK Platform Bill Of Materials Sheet 2 of 3 CYCLONE EVALUATION PLATFORM Revised December 994 Bill Of Materials Peay ep 58H 5 A Reference Description Mfg Part Manufacturer 20 1 Ji DB25 Connector 747846 4 AMP 21 1 J5 Connector GM N 66 Kycon 22 2 J3 J4 70 Pin Connector 535697 6 AMP 23 1 J7 Power Connector RAPC 722 Switch Craft 24 1 J2 Surface Mount Connector 1 104652 0 AMP 25 2 U19 J20 SIMM Socket 822134 3 AMP 26 1 U29 Clock Chip CY7B991 7JC Cypress e International 27 1 Q1 Transistor IRF7101 Rectifier 28 1 P1 Jumper Not Installed 10 89 6084 Molex ag Aa A Green LED LTL533 11 Lite On 30 1 CR6 Red LED LTL503 11 Lite On 31 1 CR9 Red LED Package 555 4001 Dialight 32 1 U17 IC MAX233ACWP Maxium 33 1 U24 IC MAX767CAP Maxium 34 1 U9 IC MAX8215CSD Maxium 35 1 U23 PAL PALCE20V8H 7JC Intel 36 1 U7 PAL PAL22V10 15JC Intel 37 1 U8 PCI to 80960 Chip PCI9060 PLX Technology 38 1 R12 Resistor 1 8W 1K 5 BCRY8102JT Beckman R17 R23 R24 R25 A 39 7 R26 R27 R28 Resistor 1 8W 10K 5 BCRY8103JT Beckman 40 1 R21 Resistor 1 8W 10 5 BCRY8100JT Beckman 41 1 R4 Resistor 1 8W 24 9K 1 BCRY82492FT Beckman 42 2 R3 Resistor 1 8W 35 7K 1 BCRY83572FT Beckman 43 3 R11 R14 R29 Resistor 1 8W 00 5 FRJ 55P54891 21 Vishay Dale R2 R5 R7 R9 R10
5. 5V 14 S_BE3 34 S_D22 54 S_A28 74 S_A10 94 c 15 SQSEL 35 D_D21 55 S_A27 75 S_A09 95 16 GND 36 S_D20 56 S_A26 76 S_A08 96 GND 17 SQIRQ1 37 S_D19 57 S_A25 77 S_107 97 SQSDA 18 SQIRQO 38 D_D18 58 S_A24 78 S_A06 98 SQSCL 19 SQBR 39 S_D17 59 5V 79 S_A05 99 12V 20 SQBG 40 D_D16 60 S_A23 80 S_A04 100 i960 Microprocessor User s Guide for Cyclone and PCI SDK Evaluation Platforms 5 17 W Squall II Module Interface ntel e 5 8 Squall Il Module Signal Loading and Logic Selection Selection of logic families for Squall II Modules deals mostly with the edge rate of the outputs CMOS logic families although they use less power than their bipolar predecessors can be very noisy due to very fast edges transitioning full 5 volt swings from rail to rail The high speed 5 volt transitions can result in large under and over shoots ringing and ground bounce Logic families such as ACT FCT and ACL all exhibit such tendencies Newer BiCMOS Logic families such as BCT or ABT are recommended These families like older TTL logic switch between 3 5 v and ground and contain edge control circuitry The same consideration is true for programmable logic Some manufacturers boast of higher speed parts but achieve that objective by increasing the signal edge transitions Designers should evaluate the transitions before deciding to use a part in a Squall II Module design The loading of the Squall II Module interface signals is very i
6. 960 Microprocessor User s Guide for Cyclone and PCI SDK Evaluation Platforms April 1996 Order Number 272577 002 Information in this document is provided in connection with Intel products No license express or implied by estoppel or otherwise to any intellectual property rights is granted by this document Except as provided in Intel s Terms and Conditions of Sale for such products Intel assumes no liability whatsoever and Intel disclaims any express or implied warranty relating to sale and or use of Intel products including liability or warranties relating to fitness for a particular purpose merchantability or infringement of any patent copyright or other intellectual property right Intel products are not intended for use in medical life saving or life sustaining applications Intel may make changes to specifications and product descriptions at any time without notice Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order Copies of documents which have an ordering number and are referenced in this document or other Intel literature may be obtained by calling 1 800 548 4725 or by visiting Intel s website at http www intel com Copyright O Intel Corporation 1996 Third party brands and names are the property of their respective owners 960 Microprocessor User s Guide for Cyclone and PCI SDK Evaluation Platforms intel Contents 1
7. SQxSEI t4 10 Read S_DATA Setup to Clock t5 2 S_DATA hold from Clock t6 Note Note Clock to Output S_BLAST BE 3 0 t7 Note Note Clock to Output S_ADDR 31 02 t8 Note Note Clock to Output S_W R t9 12 S_READY Setup to Clock t10 0 S_READY Hold from Clock DI Note Note Clock to Output S_DATA Write NOTE Signal timing is dependent on the type of i960 processor and the frequency of operation Refer to Intel i960 processor data sheets for this timing information Figure 5 5 Squall II Slave Burst Read Timing Diagram on page 5 11 shows 3 1 1 1 clock cycle read Figure 5 6 Squall II Slave Burst Write Timing Diagram on page 5 12 shows 3 2 2 2 clock cycle write Any number of wait states may be run by Squall module slaves 9600 Microprocessor User s Guide for Cyclone and PCI SDK Evaluation Platforms 5 9 intel Squall II Module Interface Figure 5 4 Squall Il Slave Read and Write Timing Diagram D600A o il ee a r A AAA AAA AA A gt _ 7 o EE A A E eee A E eer o c f Se EE Tekoa paama e EE ee 7 Pa zen Sege vi mt e a ei e wm zm db zi e ze eg e ze D do mm ze mi e zm A ge E N e Ee E ee E E EE ee dr EE EN E EE ee ag peii z y ef Js ar a RR D ee E E SPE Ko E E E E Sa E EB T st Q eg AAA eae L en e e Si ei ei e db a en a S se SR AE AS PES a NN Ee oe EE ez d ee d e aed e Se e db mi e PA e e pe a a A i E D
8. Table 3 12 Parallel Port Status Register Bit Assignments Bit Signal Mnemonic Signal Name 7 not used 6 not used 5 BUSY Bus Busy 4 ACK Acknowledge 3 PPSLCTIN Select In 2 PPFEED Paper Feed 1 PSTROBE Data Strobe 0 PPINIT Port Initialize The parallel port control register is a write only 8 bit register that controls parallel port operation This register also contains an interrupt enable bit PINTEN that enables the parallel port interrupt When the interrupt is enabled an interrupt is signaled when either PSTROBE or PPINIT is asserted The interrupt is cleared when the parallel port data register is read Table 3 12 shows the parallel port control register i960 Microprocessor User s Guide for Cyclone and 3 9 PCI SDK Evaluation Platforms E Hardware Reference l ntel Table 3 13 Parallel Port Control Register Bit Assignments 3 9 Bit Signal Mnemonic Signal Name 7 not used 6 not used 5 not used 4 BUSY_CTRL Busy Control 3 PINTEN Enable Interrupt 2 PPOUT Paper Out 1 PPSEL Select Out 0 PPERR Error Output Z8536 Counter I O Unit CIO The Z8536 device performs several functions on the Cyclone EP The device provides three 16 bit counter timers that may be used to generate interrupts or count events The CIO generates interrupts on the processor s XINT6 signal The CIO also contains three parallel ports which are used
9. Table 5 2 presents the legend for interpreting the pin descriptions i960 Microprocessor User s Guide for Cyclone and PCI SDK Evaluation Platforms n Squall II Module Interface Table 5 2 Pin Description Nomenclature Symbol Description l Input only pin O Output only pin 1 0 Pin may be either an input or output Pin must be connected as described s Synchronous Inputs are synchronous to PMCLK Outputs must meet setup and hold times relative to PMCLK Asynchronous Outputs may be asynchronous to PMCLK A A E Edge Sensitive Output A L Level Sensitive Output While EHOLD and EHLDA are inactive the pin functions in the slave mode SL O Output SL I Input SL 1 O As an input or an output SL When EHOLD and HLDA are asserted the module is in master mode MI Input M O Output M I O As an input or output 9600 Microprocessor User s Guide for Cyclone and 5 5 PCI SDK Evaluation Platforms Squall II Module Interface 5 5 Squall Module Signal Descriptions Table 5 3 Squall Module Signal Descriptions Sheet 1 of 2 Name Type Description S_A 02 31 Se Address Bus carries the upper 30 bits of address The byte enable signals indicate the e S selected byte in each word Data Bus carries 32 16 or 8 bit data depending on the bus width configured in the Memory S_D 00 31 1 0 Region Table For a bus width of 8 bits data lines D 00 07
10. eet eet cteececteia tacts Uer a ECKER EE KEE 4 2 4 4 OMG ACC cnica tras lo 4 2 4 41 Functional Block Sci a cea 4 2 4 42 KICO TMNT cueca ia 4 3 GC Dala Palio dara aba 4 4 4 43 11 Parallel Polacos s egE CS Eed dE 4 4 4 4 3 2 Sonal PO EE 4 5 4 5 DRAM gerett ege rias 4 6 4 5 1 Page Mode DRAM SIMM Review ccooonooccconnncocccccnnnccnccnnnnnnccnnnnannnccnnns 4 6 4 5 1 1 Bank Interleavimg nc na ko TRR 4 6 4 5 1 2 Wait State Performance ooccccccccinnocccinnnnconccnnnnnnnnnnnnnnnnnnnnnnnnnnnnn 4 7 4 5 2 DRAM Controller Implementaion 4 7 4 6 CASA Generali usaras tdt rate 4 9 4 7 Refresh Generation incas 4 9 960 Microprocessor User s Guide for Cyclone and PCI SDK Evaluation Platforms 5 Squall Il Module Interface oooooooooooocociciociccicncccocnonccionncncnnocnonanonnononos 5 1 5 1 Physical Attbutes cnn aran ea aiaa anaE 5 1 5 2 Power Requirements c vxoiociocoriciin ia ci A 5 3 5 3 Squall Il Module Serial EEPROM 00 eee cceceeeeeneeeeeeeeaeeeeeeeaeeeeeesaeeeeeeeeaeeeeeee 5 3 5 4 Squall Il Module Signal Definitions 0 ec eee eeeneeeeeeeeeeee eee eeeaeeeeeeeenaeeeeene 5 4 5 5 Squall Module Signal Descriptions conan ncnnnnnns 5 6 5 6 Squall Module Timing coord EER 5 8 5 6 1 Squall Il Module Slave Timing 5 8 5 6 2 Squall Il Module Master Timing eeeeeeeeeeeeeereserrrssrrrrssrssrensss 5 12 5 7 Squall Il Module CONNECT oococccccnnnncoccccnoncnccnonnn aan ncccnnnnn rc cnn nr rra 5 17 5 8 Squall Il Module
11. etm ere ee Sl A A O PA e Se lt a NEE Ge ki Es g LI LI LI LI Ll LI LI LI L E 2 T a lt x m z a a wn 09 09 wn 09 wn Wal wn any number of wait states are acceptable NOTE Diagram shows two wait states PCI SDK Evaluation Platforms i960 Microprocessor User s Guide for Cyclone and 5 10 W ntel 6 Squall II Module Interface Figure 5 5 Squall Il Slave Burst Read Timing Diagram 1 m 3 4 5 6 7 8 9 10 PMCLK pepe ee gt BA it 41 L Co HR X SQxSEL S_BLAST A S_A 4 31 4 K i i AN Ve K sae LK XX XX S_WIR A EN S_DATA A i l i S_READY A 9600 Microprocessor User s Guide for Cyclone and 5 11 PCI SDK Evaluation Platforms W Squall II Module Interface l ntel e Figure 5 6 Squall Il Slave Burst Write Timing Diagram PMCLK S_ADS SQxSEL i i i aE e E S_BLAST A LS ye by S_A 4 314 E S_Al2 3 B S_W R A S_DATA F S_READY A Se rol Fo E a 2 3 4 5 6 7 8 9 10 KE EE EA ER 1 itt Det UR g Sk gt lt gt lt gt lt gt lt gt lt E N Jes es a x lt gt lt gt lt pi S 5 6 2 5 12 Squall Il M
12. 422 Hitachi 64570 SQ40 Parallel Input with Differential Receivers Table 3 18 Squall Module Compatibility at Maximum CPU Clock Speed 33 MHz CPU Type sQ01 SQ10 sQ11 sQ20 SQ40 80960Sx YES NO NO NO NO 80960Kx YES YES YES NO4 YES 80960Cx YES YES YES YES YES 80960Jx YES YES YES YES YES 80960Hx YES YES YES YES YES NOTES 1 Edge Triggered Interrupt must be translated to level sensitive 2 NCR153C720 device must be accessed by 32 bit CPU 3 HD64570 registers have been mapped to short work boundaries 4 HD64570 registers are mapped requiring 16 bit bus width 80960Kx supports 32 bit bus width only 3 12 PLX PCI 9060 Interface PCI SDK Platform Only PLX Technology s PCI 9060 device provides the PCI SDK Platform with a PCI bus interface allowing high bandwidth data transfer between the PCI SDK Platform and host or target hardware connected to the PCI bus The PCI 9060 has several programmable features designed to allow maximum throughput on the PCI bus Bus Mastering e PCI interrupts host to PCI 9060 and PCI 9060 to host e On chip read and write FIFOs to support PCI burst transfers e Eight 32 bit mailbox registers e Two 32 bit doorbell registers e Two channel bi directional DMA 3 14 i960 Microprocessor User s Guide for Cyclone and PCI SDK Evaluation Platforms In 3 12 1 Hardware Reference PCI 9060 Configuration PCI 9060 configuration is a two step pro
13. 44 10 R13 R30 R31 R32 Resistor 1 8W 470 5 BCRY8471JT Beckman R33 45 1 R20 Resistor 1W 0 04 5 WSL 2512 R040 Vishay Dale 46 5 2 R18 R19 Resistor Package 22 ohms 4814P T01 220 Bourns 47 2 R1 R6 Resistor Package 1K 4816P T02 102 Bourns 48 1 R15 Resistor Package 4 7K 4816P T02 472 Bourns 49 1 EN DIP Switch DHS 45 Mors Asc 50 1 S2 Push Button Switch EP12 D1A BE C amp K A 2 i960 Microprocessor User s Guide for Cyclone and PCI SDK Evaluation Platforms n e Parts List Table A 1 Cyclone EP PCI SDK Platform Bill Of Materials Sheet 3 of 3 CYCLONE EVALUATION PLATFORM Revision 0 01 Revised December1994 CFEVALBD SCH Bill Of Materials 5 Reference Description Mfg Part Manufacturer Texas 51 1 U16 IC TL7705ACD Inistr ments 52 1 Y1 Crystal KDS143 20 KDS America 53 1 U14 IC Z0853606VSC Zilog 54 1 U18 FPGA iFX780 84 10 Intel 55 1 U28 PAL N85C 220 10 Intel 56 1 R34 Resistor 1 8 W 2 2K 5 BCRY8222JT Beckman 9600 Microprocessor User s Guide for Cyclone and A 3 PCI SDK Evaluation Platforms intel Index B Bandwidths 3 5 baud rates on the serial port 3 8 C Centronics interface 4 4 chip selects 4 3 clo 3 10 specific usage 3 10 C language compilers 2 1 Clock Generation 4 1 Clock Signals 4 1 Column Address Strobes 4 6 Console Serial Port 3 8 console serial port 3 8 Counter I O Unit CIO 3 10 CPU module installation 3 2 memory map 3
14. CO E SE ee SQBG IT ttt E EF S_ADS NA EA 1 ptt Lo S_BLAST A S_EXTEND4 Zei 8 A Ir os S_ADDR i e nd e CES S_BEx a i paan X mp em ity uE ae E E te s s Reanve ck E egen SEN Sege 5 16 9600 Microprocessor User s Guide for Cyclone and PCI SDK Evaluation Platforms 5 7 Squall Il Module Connector Squall II Module Interface The Squall II Module interface uses a 100 pin surface mount connector plug Samtec part number for the connector is TFM 150 32 SDLC Table 5 6 shows pin assignments for the Squall IT Module connector Table 5 6 Squall Il Module Pin Assignments Pin Signal Pin Signal Pin Signal Pin Signal Pin Signal 1 S_ADS 21 S_EXTEND 41 GND 61 S_A22 81 S_A03 2 GND 22 GND 42 S_D15 62 S_A21 82 S_A02 3 PMCLK 23 5V 43 S_D14 63 S_A20 83 5V 4 GND 24 S_D31 44 S_D13 64 S_A19 84 S_DO7 5 S_BLAST 25 S_D30 45 S_D12 65 S_A18 85 S_D06 6 S_LOCK 26 S_D29 46 S_D11 66 S_A17 86 SG DO 7 S_W R 27 S_D28 47 S_D10 67 S_A16 87 S_D04 8 GND 28 S_D27 48 S_D09 68 5V 88 S_D03 9 S_READY 29 S_D26 49 S_D08 69 S_A15 89 S_D02 10 RESET 30 S_D25 50 GND 70 S_A14 90 SG DO 11 S_BEO 31 S_D24 51 S_A31 71 S_A13 91 S_D00 12 S_BE1 32 GND 52 S_A30 72 S_A12 92 GND 13 S_BE2 33 S_D23 53 S_A29 73 S_A11 93
15. CPU Memory Map INTal As indicated in Figure 3 2 the memory map is organized to take advantage of the 1960 Cx Hx and Jx processors bus sizing capabilities Memories and 1 O devices are described in the sections following the figure Figure 3 2 DRAM Memory Map for Cyclone EP F000 0000H E000 0000H D000 0000H C000 0000H B00C 0000H B008 0000H B004 0000H B000 0000H A000 0000H 8000 0000H 4000 0000H 0000 0000H CPU Module Flash Boot ROM for 80960Cx Jx Hx Expansion Flash ROM Reserved Squall Module Reserved Parallel Port CIO Serial Port DRAM Reserved PLX PCI 9060 PCI SDK only PCI Bus PCI SDK only CPU Module Flash Boot ROM for 80960Kx Sx EFFF FFFFH E004 0000H E000 0000H Expansion Flash ROM Flash Socket 1 U27 Flash Socket 2 U22 3 4 Interleaved DRAM The Cyclone EP is initially configured with 2 Mbytes of interleaved DRAM This memory located in the SIMM sockets is upgradeable to 8 or 32 Mbytes Figure 3 1 on page 3 1 shows the SIMMs and sockets Section 3 4 2 discusses the DRAM configuration options Access to this DRAM can be shared with the Squall IT Module I O device s DMA controller A priority arbitration circuit ensures that only one device is using the memory at a time 3 4 9600 Microprocessor User s Guide for Cyclone and PCI SDK Evaluation Platforms intel
16. DMA interrupts are signalled by the PCI 9060 XINTO on Cx Hx and Jx INT2 on Sx and Kx As with all local PCI interrupts DMA interrupts are controlled and detected through the Interrupt Control and Status Register E8H To receive a DMA interrupt when a transfer is complete software must set the Local DMA Interrupt Enable bit for the channel in use ensure that the PCI Local Interrupt Enable bit is set and set the Done Interrupt Enable bit in the DMA Mode Register for that channel When a DMA interrupt occurs the Interrupt Control and Status Register E8H indicates the interrupt source The interrupt can be cleared by setting bit 3 of the DMA Command and Status Register 128H for a channel 0 interrupt or bit 11 for a channel interrupt If a PCI master or target abort occurs while the DMA is transferring data bit 25 or 26 of the Interrupt Control and Status Register E8H is set This condition also generates an LSERR interrupt if LSERR is enabled in the Interrupt Control and Status Register E8H i960 Microprocessor User s Guide for Cyclone and 3 33 PCI SDK Evaluation Platforms intel Theory of Operation 4 1 4 2 This chapter describes functionality of the Cyclone Evaluation Platform s subsystems I O Interface describes the general I O implementation Subsections further describe each functional block DRAM Subsystem on page 4 6 similarly defines the DRAM implementation Also covered are Clock Generation R
17. INTO EE 1 1 1 1 Advantages and Features Aen 1 2 1 2 About This Manual iria ad 1 2 1 2 1 Notation Conventions ccccccccccccnccccccncononononononcnnnnnnnnnnnnnnnnnnnnononononnnnnnon 1 3 1 3 Technical Support Schematics and PLD Eouatons rennene 1 3 1 4 Additional Informatio Tu DEE 1 3 2 Getting Started E 2 1 2 1 Pre Installation Considerations cooccccccococooooononanononcncnoncnonononnnnnnnnonononononnnnnn 2 1 2 1 1 Software Development Tools n eercssoras i a 2 1 2 1 2 MON960 Debug Monitor 2 1 2 1 3 Host COMMUNICATIONS occcccccccccnccccccccnononononnnananannncnnnnnnnnnnnnnnnononnnnnnnnon 2 1 2 1 3 1 Terminal Emulation Method 2 2 2 1 3 2 Host Debugger Interface Library HDIL Method 2 2 2 1 3 3 Source Level Debuoger 2 2 2 1 4 Power Requirements niinniin 2 2 2 2 Software Installation ccccccccccccceececesecaeaeeesessessseseseceeeeeceseseeceeeeeeeseeesaeaeaeaaaea 2 3 2 2 1 Installing Software Development Tools 0 0 0 0 ce ceeeceeeeeeeeeteeeeeeenaeeeeeeeaes 2 3 2 3 Hardware Installatton nrnna nnana nnnnnnnnnnnenenenenennnnnnnsn nnna 2 3 2 3 1 Verify Cyclone EP is Functional 2 3 2 4 Creating and Downloading the Example Program 2 4 2 41 MONDB EXE to Cyclone EP Communication Support eee 2 4 24 2 Terminal Emulation to Cyclone EP Communication Suppott 2 6 3 Hardware Reierence cece ce cscscsesesesescscscscsssesesesavasaacseseseseetatanaeaeaes 3 1 3 1 Connectors
18. Map 5 4 ADDRESS DESCRIPTION 7FFH Module specific data see the particular module s user manual O0AH 009H Module revision level 008H i Module version 007H Reserved 005H 004H Interrupt Detection Mode 003H Region Configuration Word 000H Squall Il Module Signal Definitions Squall II Module devices can be accessed by the processor and may access the shared memory via a 100 pin connector This section describes the signals provided on the Squall II Module interface connector The signals are an enhanced set of the 1960 external bus signals Familiarity with the operation of the 1960 external bus helps the user to understand the Squall II Module Interface Refer to the 1960 microprocessor user s manual for detailed explanations The signals are described relative to the circuitry on the Squall IT Module an input to the CPU or memory would be an output from the Squall II Module Master and slave designations are used to describe different operating modes of the Squall Interface The Squall II Module is a slave when it is being accessed by the processor SQBG inactive The Squall II Module is a master when its circuitry has been granted mastership of the shared memory bus SQBG asserted by arbitration circuitry in response to a SQBR All output and I O pins have been provided with the proper pull up resistors on the host board and may be left unconnected if desired
19. Signal Loading and Logic Selection oooooccccninnncccnnnnnnacccccnns 5 18 5 9 Squall Il Module Clock Termimaion 5 19 A AA en A A 1 O EE Index 1 Figures 1 1 Cyclone EP and PCI SDK Platform Functional Block Diaoram 1 1 2 1 Download Messages AANEREN ENEE 2 5 2 2 Program Execution Messages nossas niana ni 2 6 3 1 Cyclone EP and PCI SDK Platform Physical Diagram 3 1 3 2 DRAM Memory Map for Cyclone EP 3 4 3 3 CIO POMA EE 3 11 3 4 ClO Port Bitorial iia a 3 12 3 5 EILER IEN 3 13 3 6 Non Chaining DMA Inmaltzaton 3 31 3 7 Chaining DMA Initialization ooonnnnnnninnnnninnccnnnnnacccnnnncrrccnn naar 3 32 4 1 VO Control State Machine ceciren a EEE ES 4 3 4 2 Parallel Port Timing Signals oonnnocccnnnnnnccinnnncccccnnnnconccnnnnnnrn nn NaN EENE 4 5 4 3 Two way interleaving Aen 4 7 4 4 DRAM State Machine 4 8 5 1 Squall II Module Component Height Allowance 5 1 5 2 Squall Il Module Dimensions ooooonoccccnnnnocccccconanncnonanonnncnnnnnoncnnn nano ncnncnnnnannncnnnns 5 2 5 3 Squall Il Module EEPROM Memory Map 5 4 5 4 Squall Il Slave Read and Write Timing Diagramm 5 10 5 5 Squall Il Slave Burst Read Timing Diagram cecceeeeseeneeeeeeeeeeeeeeeeeeeeeees 5 11 5 6 Squall Il Slave Burst Write Timing Diagram ooonnncccnnnniniccnnnnaccccnnnnercccnnnnarrccnn 5 12 5 7 Squall Il Master Read and Write Timing Diagram seeessseseeseeeeeeeeeeseeren 5 14 5 8 Squall Il Master Burst Read and Write Timing Diagramm 5 15 5 9 Squall Il Mas
20. Sx Kx Jx with multiplexed data and address signals are de multiplexed on the processor module The following timing diagrams show the timing for reads writes and burst cycles Many of the timing parameters are specific to the processor and frequency used Refer to the appropriate 80960 data sheet for these parameters Two mandatory conditions must be met by Squall II Module slave hardware First some 1960 processors do not have internal wait state generation therefore the Squall II interface is designed to always require READY to be returned for all accesses to the Squall II Module address range C000 0000H to CFFF FFFFH Processors with internal wait state generation should be programmed such that the internal wait state generator is disabled and READY is enabled for region C Using the internal wait state generator results in the signal SELSQ not being properly negated at the end of the access The second mandatory function of the Squall II Module circuitry is that READ Y must be asserted for all accesses to region C A timeout circuit is provided but software mistakes are easier to find if they are not relied on by the Squall IT Module hardware i960 Microprocessor User s Guide for Cyclone and PCI SDK Evaluation Platforms INTal Table 5 4 Squall Il Module Slave Timing Squall II Module Interface Name Minimum Maximum Comment ti Note Note Clock to Output S_ADS t2 2 10 Clock to Output
21. and Go bits in the DMA Command Status Register initiates the DMA transfer i960 Microprocessor User s Guide for Cyclone and 3 31 PCI SDK Evaluation Platforms Hardware Reference n 3 12 7 2 DMA Chaining Mode In chaining mode software constructs a list or chain of DMA operations in local memory and writes to the Command Status Register to begin the transfers The PCI 9060 loads the DMA registers with information from the first descriptor block in the chain performs the transfer proceeds to the next descriptor The PCI 9060 can be programmed to interrupt the processor at the end of any transfer at the end of the chain or not at all This is a very efficient way to move blocks of non contiguous memory across the PCI bus while minimizing processor involvement Rather than programming the DMA registers directly in chaining mode values for the PCI Address Local Bus Address Transfer Count and Mode registers are stored in a descriptor block in memory New register values are loaded at the beginning of every transaction until the last descriptor block is processed The descriptor blocks must be quadword aligned and consist of five longwords see Figure 3 7 The longwords in each descriptor block are loaded into the PCI Address Local Bus Address Transfer Count Mode and Next Descriptor registers in that order The first block is loaded into the PCI 9060 automatically when the transfer begins The last block of a chained tran
22. and Shared Run Time register groups are visible from the PCI bus The PCI Configuration group is accessed via configuration space on the host system but the other two groups are accessed at offsets above the PCI 9060 register base address To access PCI configuration registers from the PCI bus host side code must use the appropriate PCI BIOS services The base address for the Local Configuration and Shared Run Time registers may be in either memory I O space or both depending on how the 1960 processor configures the PCI 9060 During start up the BIOS on the host system assigns base addresses to the PCI 9060 Host side code can determine the base address of the PCI 9060 registers by reading the PCI Base Address for Memory Mapped Runtime Registers 10H and the PCI Base Address for I O Mapped Runtime Registers 14H from the PCI Configuration group using configuration cycles A non zero value in these registers indicates that PCI 9060 registers are mapped into the corresponding PCI space It is possible for runtime registers to be mapped into both memory and I O space on the host system Table 3 19 shows the local configuration register offsets Table 3 20 shows the PCI configuration registers If a register will be accessed by the host from the PCI bus create the register address by adding its PCI offset to the base address of either the Memory Mapped Runtime Registers or the I O Mapped Runtime Registers The same PCI offsets should be used whether
23. are used For 16 bits D 00 15 S are used For 32 bits the full bus is used In master mode all transfers with the memory use full data bus Byte Enables select which of the four bytes addressed by A 02 31 are active during an access to a memory region configured as 32 bits data bus width The following describes the usage of the Byte Enable Signals in different data bus configurations 32 bit bus BE3 Byte Enable 3 Enable D 24 31 BE2 Byte Enable 2 Enable D 16 23 BE1 Byte Enable 1 Enable D 08 15 BEO Byte Enable 0 Enable D 00 07 Se St 16 bit bus S BE1 M O BE3 Byte High Enable Enable D 08 15 S BEO S BE2 Not Used BE1 Address bit 1 A 01 BEO Byte Low Enable Enable D 00 07 8 bit bus BE3 Not Used BE2 Not Used BE1 Address Bit 1 A 01 BEO Address Bit 0 A 00 NOTE 16 and 8 bit bus modes are not available with Kx or Sx processor modules S WR Be Write Read is low for read accesses and high for write accesses The operation read or S write is relative to the bus master S ADS vies Address Strobe indicates valid address and the start of a new bus access S_ADS is S asserted for the first clock of an access Ready signals the termination of a data transfer S_READY is used to indicate that read SL O data on the bus is valid or that write data transfer is completed In slave mode the S_READY MI S_READY signal should be asserted to terminate a cycle indicated by SQSEL In master S mode the memo
24. at start up on the host system Expansion ROM on the PCI SDK Platform can be configured as a PCI expansion ROM region by programming two Local Configuration registers on the PCI 9060 The Local Base Address for PCI to Local Expansion ROM and BREQo Control Register 94H see Table 3 27 should be programmed with the base address of the expansion ROM on the local bus Initialization code should clear as many bits in the Range for PCI to Local Expansion ROM Register 90H see Table 3 26 as necessary to address the ROM region the remaining upper bits should be set Unlike RAM region remapping the ROM region is enabled by default To disable the ROM region user code should clear the Enable bit in the PCI Base Address to Local Expansion ROM 30H and clear the Local Base Address Register 94H The Local Bus Region Descriptor for PCI to Local Accesses Register 98H contains control settings for the expansion ROM region Table 3 25 shows the settings required for a ROM region on the PCI SDK Platform See Section 3 12 1 5 Memory Region Configuration Examples on page 3 21 for an illustration of the expansion ROM region configuration Table 3 25 ROM Region Settings Bits Function Setting 1 0 Bus Width 11 32 Bit Bus Width 5 2 Internal Wait States 0 No Wait States 6 READY Input Enable 1 Enabled 7 BTERM Input Enable 0 Disabled 3 12 1 5 Memory Region Configuration Examples MON960 determines the size of in
25. back to the CPU module Squall II Module and on board logic This device guarantees a maximum skew of 250 ps between outputs and 500 ps between the input and the outputs Therefore all clocks on the board are within 1 ns making the design work very straightforward All clock signals are terminated with 22 ohm series resistors i960 Microprocessor User s Guide for Cyclone and 4 1 PCI SDK Evaluation Platforms E Theory of Operation l ntel 4 3 4 4 4 4 1 4 2 Power Monitor and Reset The board reset strobe is provided by a Texas Instruments TL7705A power supply monitor The TL7705A senses board voltage and ensures that the board RESET and RESET signals remain asserted for several milliseconds after board power is stable above 4 6 V The TL7705A also asserts RESET and RESET when the board voltage drops below 4 6 V A reset push button manually triggers the TL7705A to reset the board The Cyclone EP requires only the 5V power supply 12V is only necessary when programming the Flash ROM The PCI SDK Platform receives power from the edge connector no external power supplies are required The 5V power LED D2 indicates that the board power is stable This LED is OFF when the board voltage drops below 4 6 V I O Interface T O design features include e Shares control logic between all devices Low cost low complexity control logic e Uses standard PLDs e Isolates I O subsystem from other board functions The
26. bits of this register are used therefore 8 Mbytes is the maximum transfer size that can be performed in one operation DMA channel functionality is controlled by programming the Mode and Descriptor register bits The Mode Register must be programmed with READY inputs enabled and BTERM inputs disabled for the DMA to operate properly on the PCI SDK Platform Burst mode should be enabled to speed transfers If the Interrupt on End bit is set the PCI 9060 generates a local interrupt to the processor when the DMA transfer completes The Chaining bit determines whether the DMA operates in chaining or non chaining mode and should be clear for non chaining transfers All other values in this register can retain their default settings In non chaining mode the Descriptor Pointer Register serves only to indicate the direction of the DMA transfer Set this bit for transfers from the local bus to the PCI bus and clear it for PCI to local transfers Other bits in this register can be cleared Figure 3 6 Non Chaining DMA Initialization Set DMA mode to non chaining PCI Host Memory N Mode Register Memory Block Set up transfer parameters o Tensor PCI Address Register Local Address Register Transfer Size byte count Register Local Memory Memory Block to Transfer Descriptor Pointer Register set direction only Command Status Register Setting the Enable
27. bus width of 16 bits Yes Yes 11 10 or 11 indicates a bus width of 32 bits Must be 00 expansion flash is 8 bits wide on the PCI SDK Platform Expansion ROM Space Internal Wait States 21 18 Must be 0 Yes Yes 0 Expansion ROM Space READY Input Enable 22 0 disables READY input 1 enables READY input Yes Yes 0 Must be 1 Expansion ROM Space BTERM Input Enable 23 0 disables BTERM input 1 enables BTERM input Yes Yes 0 Must be 0 Memory Space 0 Burst Enable 24 0 disables bursting 1 enables bursting Yes Yes 0 Must be 1 25 Not Used Yes Yes 0 Expansion ROM Space Burst Enable 26 0 disables bursting 1 enables bursting Yes Yes 0 Must be 0 Direct Slave PCI write mode 27 0 PCI 9060 disconnects when the Direct Slave write FIFO is full Yes Yes 0 1 PCI 9060 de asserts TRDY when the write FIFO is full PCI Target Retry Delay Clocks Contains the value multiplied by 8 of the 31 28 number of PCI bus clocks after receiving a PCl Local read or write access Yes Yes 4 and not successfully completing a transfer Only pertains to Direct Slave 32 clocks writes when bit 27 is set to 1 3 20 9600 Microprocessor User s Guide for Cyclone and PCI SDK Evaluation Platforms In 3 12 1 4 Hardware Reference Expansion ROM Region Configuration The PCI specification allows expansion boards to include device specific initialization code in PCI expansion ROM which is executed
28. condition exists If a PCI master requests the local bus on the PCI SDK Platform at the same time that the PCI SDK Platform is attempting to access the local processor s host bus both requests are answered with a RETRY signal RETRY however does not cause either processor to release its local bus so neither request can be completed and the system will deadlock There are two possible resolutions to this problem The first and simplest is to design a system such that memory is shared only on the host or PCI SDK Platform and never both In such a system only one local bus is being shared by more than one processor thereby avoiding the deadlock situation The second solution is somewhat more involved and can be implemented only on the Cx and Hx processors This solution involves a hardware detection of the deadlock condition Once the deadlock has occurred a method of signalling the 1960 processor to abort its current request and relinquish its local bus is needed This allows the host processor s transaction to complete The Cx and Hx processors possess a BACKOFF pin which serves this purpose On a PCI SDK Platform equipped with a Cx or Hx CPU module the PCI 9060 asserts BACKOFF to the processor in the event of a deadlock The processor then relinquishes its local bus and the host s transaction completes The Kx Sx and Jx however lack such a feature Instead logic has been included to assert a false READY signal to these proc
29. for on board control and status such as reading and writing the on board and Squall Module EEPROMs and to read the board s configuration The following subsections outline the Cyclone EP s specific usage of the CIO For detailed programming instructions refer to the Zilog Z8536 Technical Manual Table 3 14 CIO Register Address 3 9 1 3 10 Register Address Description Port C Data B004 0000H User LEDs Port B Data B004 0004H EEPROM Clock amp Data Port A Data B004 0008H Control Bits CIO Control Register B004 000CH CIO Configuration amp Control Counter Timers Three 16 bit counter timers can be used to generate interrupts on the processor s XINT6 signal Counters and 2 can be linked internally to provide a 32 bit counter for longer timing sequences The CIO is clocked with a 4 000 MHz 0 01 clock Internally this signal is divided by 2 which actually clocks the counters with a 2 000 MHz clock Example code for using the counter timers may be found in the MON960 Board Test bt code i960 Microprocessor User s Guide for Cyclone and PCI SDK Evaluation Platforms n e Hardware Reference 3 9 2 CIO Port A Port A an 8 bit input port is used to report CPU and memory module configuration e Bits 0 2 report the CPU module processor type e Bits 3 5 report on the selected CPU module frequency e Bit 6 reports on the speed of the installed DRAM e Bit 7 is the PCI 9060 Installed Bit Example co
30. gain a general understanding of how to use your tools with this board MON960 Debug Monitor The Cyclone EP is equipped with Intel s MON960 an on board software monitor which allows you to execute and debug programs written for 1960 processors The monitor provides program download breakpoint single step memory display and other useful functions for running and debugging a program The Cyclone EP works with source level debuggers such as the DB960 and GDB960 The source level debugger must support the Host Debugger Interface Library HDIL defined by MON960 Host Communications MON960 allows you to communicate and download programs developed for the Cyclone EP across a PC s serial parallel or PCI interface and a UNIX workstation s serial interface The Cyclone EP supports two methods Terminal emulation and Host Debugger Interface Library HDIL 1 Refer to Intel s Solutions960 catalog for a complete list of i960 processor software development and debug tools i960 Microprocessor User s Guide for Cyclone and 2 1 PCI SDK Evaluation Platforms Getting Started ntel e 2 1 3 1 2 1 3 2 2 1 3 3 2 1 4 2 2 Terminal Emulation Method Terminal emulation software on your system communicates to MON960 on the Cyclone EP via an RS 232 serial port Serial downloads via terminal emulation require an intelligent host computer that supports XMODEM a standard transfer protocol General system requirements are
31. generates the proper timing for the read and write strobes READY and the recovery time which many of the I O devices require All timing assumes a 50 MHz processor clock to ensure that all minimum timing requirements are met over the entire range of processor clocks 16 to 50 MHz The state diagram for the I O control state machine is shown in Figure 4 1 Figure 4 1 I O Control State Machine selflash selrom seluart a FS selpp 9600 Microprocessor User s Guide for Cyclone and 4 3 PCI SDK Evaluation Platforms E Theory of Operation l ntel 4 4 3 4 4 3 1 4 4 Data Path Data signals are buffered before connecting directly to I O devices and peripherals The lower eight data signals are passed through a 74ABT245 transceiver before connecting to peripherals or I O devices Peripheral I O address lines are buffered through 74FCT244 s BEO BE1 and A2 are buffered to become IOAO IOA1 and IOA2 respectively These address lines are then used for peripheral device control such as the serial port and timer Parallel Port The parallel port is a full implementation of a Centronix compatible receive only port A program sets up and reads the parallel port by reading or writing three registers Parallel port data register Receives parallel data when the PSTROBE signal is asserted by an external transmit port PSTROBE is used as a latch enable for a 74ABT574 quad D latc
32. operating systems DOS and UNIX 2 1 P parallel port bit assignments 3 9 control register bit assignments 3 10 data lines 4 4 handshaking lines 4 4 interrupts 4 4 timing relationships 4 4 Parallel port control register 3 9 4 4 Parallel port data register 3 9 4 4 parallel port interrupt 3 9 parallel port interrupt enable bit 3 9 Parallel port status register 3 9 4 4 Parallel Port Centronics compatible 3 2 PCI Configuration Registers 1 PCI interrupts 3 27 peripheral I O 4 4 PINTEN 3 9 PLL Internal 4 Power 5 VDC 3 2 Power 5 VDC 12 VDC 3 2 Presence Detect Signals 3 6 R reset push button 4 2 Reset Strobe 4 2 RS 232 port 3 8 S serial port 4 5 interface 4 5 TXD RXD CTS RTS 4 5 serial port configuration 2 2 Serial Port RS 232 3 2 Shared Run Time Registers 3 15 Index 2 SIMM 3 5 SIMM sockets 3 4 SIMMs 3 5 4 6 types supported 3 5 Six position DIP Switch 3 2 Software Development Tools 2 1 source level debuggers 2 1 Squall 5 4 Squall II Module Clock Termination 5 19 Squall II Module Interrupts 5 3 Squall II Module Master Timing 5 12 Squall II Module Physical Dimensions 5 1 Squall II Module Pin Assignments 5 17 Squall II Module Programmable Logic 5 18 Squall U Module Serial EEPROM 1 Squall II Module Signal Descriptions 5 6 Squall II Module Signal Loading 5 18 Squall II Module Slave Timing 5 8 SwapROM switch 3 6 T terminal emulation 2 2 U UART 4 5 Universal Asynchronous Rec
33. s Guide for Cyclone and 4 5 PCI SDK Evaluation Platforms E Theory of Operation l ntel 4 5 4 5 1 4 5 1 1 4 6 DRAM Subsystem Cyclone EP features DRAM and a DRAM controller which operates with all members of the 1960 processor family The DRAM controller runs with minimum wait states at 16 20 25 33 and 40 MHz processor clock frequencies The design uses interleaved banks of fast page mode DRAM to reduce the wait states during burst accesses DRAM may be expanded from 2 Mbytes to 8 or 32 Mbytes of memory Refer to Interleaved DRAM on page 3 4 for related information Page Mode DRAM SIMM Review Page mode DRAM allows faster memory access by keeping the same row address while selecting random column addresses within that row A new column address is selected by deasserting CAS while keeping RAS active and then asserting CAS with the new column address valid to the DRAM Page mode operation works very well with burst buses in which a single address cycle can be followed by up to four data cycles Also all WE pins on the SIMM are tied to a common WE line this line requires the Cyclone EP design to employ early write cycles In an early write cycle the write data is referenced to the falling edge of CASH not the falling edge of WE Each SIMM also has four CAS lines one for each eight nine bits in a 32 bit 36 bit SIMM module The four CAS lines controls writing individual bytes within the SIMM Bank Interlea
34. target abort or master abort while acting as a PCI slave or PCI master LSERR can also be triggered by the PCI 9060 when a PCI parity error occurs during a master or slave transfer Bits 0 and 1 of the Interrupt Control and Status Register E8H are used to enable this local interrupt LSERR is signalled to the Cx Jx and Hx processors on XINT2 and to Sx and Kx processors on the PCI 9060 interrupt line INT2 i960 Microprocessor User s Guide for Cyclone and 3 27 PCI SDK Evaluation Platforms Hardware Reference n e Table 3 33 Interrupt Control Status Sheet 1 of 2 Value after Field Description Read Write Reset Cold PC Reset Enable Local bus LSERR 0 disable 1 enable the PCI 9060 to assert LSERR 0 interrupt output when the PCI bus Target Abort or Master Abort status bit is set in the Yes Yes 0 PCI Status Configuration Register 1 Enable Local bus LSERR when a PCI parity error occurs during a PCI 9060 Master Yes Yes 0 Transfer or a PCI 9060 Slave access 2 Generate PCI bus SERR When this bit is 0 setting it writing a 1 generates a PCI bus Yes Yes 0 SERRA 7 3 Not Used Yes No 0 8 PCI interrupt enable O disable PCI interrupts 1 enable PCI interrupts Yes Yes 1 PCI doorbell interrupt enable 0 disable doorbell interrupts 1 enable doorbell interrupts 9 Yes Yes 0 Used in conjunction with PCI interrupt enable Clear the doorbell interrupt bits
35. that cause the interrupt to clear the interrupt PCI Abort interrupt enable 0 disable 1 enable a master abort or master detect of a target abort to generate a PCI interrupt 10 Yes Yes 0 Used in conjunction with PCI interrupt enable Clear the abort status bits to clear the PCI interrupt PCI local interrupt enable 0 disable 1 enable a local interrupt input to generate a PCI interrupt 11 Yes Yes 0 Used in conjunction with PCI interrupt enable Clear the local bus cause of the interrupt to clear the interrupt Retry Abort Enable 12 0 enable the PCI 9060 to attempt Master Retries indefinitely Yes Yes 0 1 enable the PCI 9060 to treat 256 Master consecutive retries to a Target as a Target Abort 13 PCI doorbell interrupt O not active 1 active Yes No 0 14 PCI abort interrupt 0 not active 1 active Yes No 0 15 Local interrupt O not active 1 active Yes No 0 16 Local interrupt enable O disable 1 enable Yes Yes 1 Local doorbell interrupt enable O disable 1 enable ye Used in conjunction with Local interrupt enable Clear the Local doorbell interrupt bits SES YOS 0 causing the interrupt to clear the interrupt Local DMA channel 0 interrupt enable 0 disable 1 enable 18 Used in conjunction with Local interrupt enable Clear the DMA status bits to clear the SEN Tes S interrupt Local DMA channel 1 interrupt enable 0 disable 1 enable P Used in conjunction with Local interrupt enable Clear the DMA st
36. the registers are mapped in memory or I O space Until the PCI 9060 has been configured by code running on the PCI SDK Platform it will respond to any PCI accesses by signalling RETRY PCI to Local Configuration Before PCI 9060 memory can be accessed through the PCI interface code on the PCI SDK Platform must configure the memory regions which will be visible to PCI masters The PCI 9060 allows one RAM region and one PCI expansion ROM area to be configured as PCI regions Both of these regions are controlled by the contents of registers in the Local Configuration group see Table 3 19 which determine region size location in local memory space and where it will be mapped in PCI space Table 3 20 shows the PCI configuration registers The size and local address are set by programming the Range and Local Base Address registers for the region the location of the region in PCI space is subsequently set in the PCI configuration header by the host system depending on the register control bit settings i960 Microprocessor User s Guide for Cyclone and PCI SDK Evaluation Platforms INTal Hardware Reference Table 3 19 Local Configuration Registers Local PCI Offset from 31 0 Offset from Runtime chip select address Base address 80H Range for PCI to Local Address Space 0 00H 84H Local Base Address re map for PCI to Local Address Space 0 04H 88H Reserved 08H 8CH Reserved OCH 90H Rang
37. 00000H to EOO7FFFFH as PCI expansion ROM To configure this memory as a PCI expansion ROM region the following settings must be made Range for PCI to Local Expansion ROM Register 90H FFF80000H e A512 Kbyte space is being mapped so the lower 19 bits of this register are needed to decode an access The remaining 13 upper bits are set to 1 so these bits are replaced with the contents of the Local Base Address for PCI to Local Expansion ROM 94H The lower 10 bits of this register are not used Local Base Address for PCI to Local Expansion ROM 94H E0000017H e Bits 11 to 31 of this register contain the local address of the expansion ROM Bits 5 to 10 are unused Bit 4 is the Local Bus BREQo Enable and is discussed in Section 3 12 3 Deadlock Configuration on page 3 26 This bit must be enabled for proper operation of the PCI SDK 3 22 i960 Microprocessor User s Guide for Cyclone and PCI SDK Evaluation Platforms intel 3 12 2 Hardware Reference Platform Bits 0 to 3 encode the number of delay clocks to wait before asserting BREQo This value is also discussed in the section on deadlock Setting these bits to 7 selects a 56 clock delay Local Bus Region Descriptor for PCI to Local Accesses Register 98H e All ROM regions on the PCI SDK Platform should use the settings in Table 3 26 for this register Local to PCI Configuration To use the PCI SDK Platform as a PCI bus master the PCI 9060 requires that the port
38. 00H through 7FFFFFFFH The register settings are Local Range for Direct Master to PCI Register OCH COO00000H e Since 30 bits are needed to encode a 1 Gbyte address space the lower 30 bits of this register are cleared 0 the remaining upper 2 bits are set 1 The set bits are replaced by the contents of the upper two bits of the PCI Base Address Register A8H when a local to PCI memory access is detected Local Bus Base Address for Direct Master to PCI Register AOH 40000000H Since the upper two bits of the Local Range Register 9CH are set the upper two bits of this register are used to detect a local access to PCI memory space Effectively this register remaps the PCI address into local address space 3 24 i960 Microprocessor User s Guide for Cyclone and PCI SDK Evaluation Platforms Table 3 30 Local Bus Base Address Register for Direct Master to PCI Memory PCI Base Address for Direct Master to PCI Register A8H 00000005H Hardware Reference e Bits 16 through 31 of this register are the PCI address to remap into local address space the lowest 8 bits are control settings Bit 0 is set to enable the direct master memory access Bit 1 controls direct master I O access enable and is cleared in this example If the PCI SDK Platform were performing I O accesses as well this bit must be set Bit 2 is the LOCK input enable and should be set Bit 4 controls the master PCI read mode and can be cleared Bits 5 to 7 must b
39. 0xA0008000 size 0x6a9c flags 0x20 writing section at 0xA0008000 Section 1 name data address 0xA000ea9c size 0x4 flags 0x40 writing section at 0xA000ea9c Section 2 name bss address 0xA000ea90 size 0x6d0 flags 0x80 noload Download stats 0 050 sec elapsed 545920 bytes sec 533 3Kb sec Starting execution at 0xA0008000 use CTRL C to interrupt gt gt gt Start of sieves test lt lt lt Sieve of Eratosthenes scaled to 10 Iterations Array Size Primes Last Prime BenchTime Bytes Found Sec 8191 1899 16381 0 060 10000 2261 19997 0 073 20000 4202 39989 0 149 40000 7836 79999 0 301 80000 14683 160001 0 610 160000 27607 319993 1 235 Relative to 10 Iterations and the 8191 Array Size Average BenchTime 0 060 sec gt gt gt End of sieves test lt lt lt Program Exit 0 9600 Microprocessor User s Guide for Cyclone and 2 5 PCI SDK Evaluation Platforms Getting Started 2 4 2 intel Terminal Emulation to Cyclone EP Communication Support 1 Invoke the terminal emulation program that you are using to communicate with the Cyclone EP 2 To establish communication between the terminal emulation program and MON960 press lt ENTER gt The MON960 prompt should appear If it does not press the RESET button 3 When the MON960 prompt appears enter do to download gt do 4 Start your terminal emulation program transfer mode and send SIEVE XX The following message display
40. 4 VPP switch 3 3 D data signals 4 4 DB960 2 1 deadlock 3 26 debug monitor MON960 2 1 Dedicated Interrupt Signals 3 7 DMA chaining mode 3 DMA Channel non chaining mode 3 31 DMA Channel programming 3 30 DMA controller 3 4 DMA Transfer Size Register 3 3 1 doorbell registers 3 29 DOS support 2 1 DRAM burst buses 4 6 early write cycles 4 6 features 4 1 4 6 interleaved 3 4 page mode 4 6 performance 3 5 upgrading SIMMs 3 5 wait state performance 4 7 DRAM controller 4 7 DRAM design performance 4 6 SIMMs 3 5 DRAM Memory 3 4 DRAM Speed 35 9600 Microprocessor User s Guide for Cyclone and PCI SDK Evaluation Platforms Driver Receiver RS 232 4 5 E EEPROM Memory 3 13 EPROM support for 4 1 Expansion Bus X Bus 3 2 Expansion ROM 3 6 F Features functional blocks 4 1 UO design 4 2 modem support 4 5 FLASH da voltage 2 2 support for Flash memory 3 6 Flex Logic 4 7 G GDB960 2 1 GNU 960 2 1 H HDIL 2 1 Host communications 2 1 Host Debugger Interface Library HDIL 2 1 interleaved DRAM 3 4 Interleaving 4 6 Interrupt Control and Status Register 3 27 interrupts 3 7 T O data buffer control 4 3 T O subsystem features 4 1 L LED RED GREEN 3 2 LEDs power green 4 2 LEDs user 2 Local Configuration Registers 3 15 Local DMA Registers 3 15 Index 1 Local Init Status bit 3 27 Mailbox registers 3 29 MAX232 4 5 memory system performance 4 6 MONDB EXE utility 2 1 MON960 2 1 O
41. ADY Input Enable 1 Enabled 7 BTERM Input Enable 0 Disabled Table 3 22 Local Address Space 0 Range Register Value after Reset Field Description Read Write cold PC Reset Memory space indicator 0 0 indicates Local address space 0 maps into PCI memory space Yes Yes 0 1 indicates address space 0 maps into PCI I O space If mapped into memory space encoding is as follows Meaning locate anywhere in 32 bit PCI address space locate below 1 Mbyte in PCI address space Yes Yes 0 locate anywhere in 64 bit PCI address space reserved If mapped into I O space bit 1 must be a 0 Bit 2 is included with bits 3 through 31 to indicate decoding range 2 1 2200 N 2010 a If mapped into memory space 1 indicates that reads are prefetchable If 3 mapped into I O space bit is included with bits 2 through 31 to indicate decoding range 0 indicates reads are not prefetchable This must be 0 on the Yes Yes S PCI SDK Platform Specifies which PCI address bits are used to decode a PCI access to local bus 31 4 Space 0 Each bit corresponds to an address bit Bit 31 corresponds to Address Yes Yes FFFO 000H bit 31 Set 1 all bits to be included in decode clear 0 all other bits Used in conjunction with PCI Configuration register 18H Default is 1 Meg Table 3 23 Local Address Space 0 Local Base Address Re map Register Description Value after Reset Field Descr
42. END during a burst access is not allowed and will cause the DRAM controller to function improperly EXTEND should be used during write cycles Squall II Module logic can be used to delay the assertion of ADS until valid data is on the bus making the use of EXTEND unnecessary The DRAM controller will not function correctly if EXTEND is asserted during write cycles Table 5 5 Squall Il Module Master Timing Name Minimum Maximum Comment t1 3 10 Clock to Output SQBG 2 10 E Setup to clock rising edge for SQBR S_ADS S_BLAST S_A31 2 S_W Ri S_BE3 0 t3 0 20 Clock to output D31 0 Read Cycle H 5 D31 0 hold from clock Read Cycle t5 3 10 Clock to Output READY t7 10 Write Data Setup to Clock t8 0 Write Data Hold from Clock t9 0 30 SQBG Inactive to control signals three stated t10 0 a Hold from clock rising edge for SQBR S_ADS S_BLAST S_A31 2 S_W R S_BE3 0 t11 0 SQBR asserted to control outputs driven Figure 5 7 Squall II Master Read and Write Timing Diagram on page 5 14 shows one wait state accesses The number of wait states depends on the clock frequency and memory speed Refresh cycles may delay READY up to 10 additional clock cycles Squall II Modules should be designed to handle fewer wait states Future base boards may incorporate faster memory systems 9600 Microprocessor User s Guide for Cyclone and 5 13 PCI SDK Evaluation Platforms W S
43. I O and peripheral subsystems provide the interface and timing control for all peripherals and registered I O devices on the Cyclone EP The design is simplified considerably by combining the control for all peripheral and registered I O devices The I O section includes the following features e Flash ROMs 28F020 e Serial Port 16C550 UART e Counter Timers Z8536 CIO Parallel Port 74ABT logic and a 22V10 PAL The control logic for the I O devices is located in the iFX780 Flex Logic device This logic generates chip select read and write strobes and ready back to the processor The data signals and A3 2 address signals have been buffered to avoid excessive loading of the processor s signals Functional Blocks The I O design comprises four distinct blocks data path control logic registered I O and I O peripheral devices The schematic for the design is hierarchical i960 Microprocessor User s Guide for Cyclone and PCI SDK Evaluation Platforms n e Theory of Operation 4 4 2 I O Control Timing The chip selects and I O data buffer control are synchronous set and hold flip flops in the iFX780 device The flip flops are set to active upon ADS and the proper address and are held active until BLAST and READY are asserted Note The 80960Kx does not generate BLAST For the Cyclone EP BLAST is generated by a PAL on the CPU module The chip select signals cause the I O control state machine to operate The state machine
44. MM Configurations on page 3 6 shows SIMM module options Use 72 pin SIMM modules with 60 or 70ns Fast Page Mode DRAM DRAM Controller Implementation The DRAM controller the most complex section of the DRAM design is implemented by an Intel 1FX780 Flex Logic device The waveforms are controlled by the state machines implemented in the PLDs This section presents the waveforms and defines these state machines The DRAM controller runs one of four paths through the state machine depending on the processor The primary state machine runs in four different paths depending on the profile determined from processor frequency and memory speed A secondary state machine which determines the bank select during burst cycles runs in two different paths determined by whether the host processor is a 32 or 16 bit processor Table 4 1 shows the profiles Figure 4 4 shows the state diagrams for the DRAM controller 4 7 PCI SDK Evaluation Platforms Theory of Operation n e Table 4 1 DRAM Profiles Profile Frequency Frequency Memory Speed PD3 Read Cycle Write Cycle PFO 16 MHz 010 60 or 70ns Xx 3 1 1 1 3 2 2 2 PFO 20 MHz 011 60 or 70ns X 3 1 1 1 3 2 2 2 PFO 25 MHz 100 60ns 1 3 1 1 1 3 2 2 2 PF1 25 MHz 100 70ns 0 4 1 1 1 1 4 2 2 2 1 PF1 33 MHz 101 60 or 70ns Xx 4 1 1 1 1 4 2 2 2 1 PF1 40 MHz 110 60ns 1 4 1 1 1 1 4 2 2 2 1 PF2 40 MHz 110 70ns 0 5 2 2 2 1 4 2 2 2 1 PF2 50 MHz 111 60ns 1 5 2 2 2 1 4 2 2 2 1 PF3 50 MH
45. Modules oooonocccccnnnooccccccononcccnonncnncncncnnon cnn nnnnn nn cccnnnnnncncnnns 3 14 Squall Module Compatibility at Maximum CPU Clock Speed 33 MHz 3 14 Local Configuration Registers ooocoonnccccccnnnoccccccnncononcnnnnnnannnnnonnno cnn nn nana nnnnr nana 3 17 PCI Configuration Registers A 3 18 Memory Region 0 Settings cnn nn nano EEEE 3 19 Local Address Space 0 Range Register ocoocccccinnicccicnnnonccccnnnnonnnnnnnannnnnnnn nana 3 19 Local Address Space 0 Local Base Address Re map Register Description 3 19 Local Bus Region Descriptor for PCl to Local Access Register Description ooonoccccnnninicinnnnnocccccnnncanccnnnnnancn nan nnnnr cnn narran 3 20 ROM Region Settings uk 3 21 Local Expansion ROM Local Base Address Re map and BREQo Register DescriptiO cimil did O adi 3 22 Local Expansion ROM Range Register Description escenes 3 22 Local Range Register for Direct Master to PCl Description 3 23 PCI Base Address Re map Register for Direct Master to PCl RE de len WEE 3 24 Local Bus Base Address Register for Direct Master to PCl Memory 3 25 Local Base Address for Direct Master to PCI lO CFG Register 2 3 25 PCI Configuration Address Register for Direct Master to PCl lO CFG 3 25 Interrupt COntrol Status wiccestsiveceeersiadecethnvemecauehsnaedanestnnndecuath Eege seele KR seet 3 28 PRAM Gel 4 8 POWer ee KE 5 3 Pin Description Nomenclature 5 5 Squall Module Signal Descriptions
46. OM on every Squall II Module bytes are read from and written to the EEPROMS most significant bit bit 7 first and least significant bit bit 0 last The contents of the on board EEPROM are not defined by Cyclone User software may use this storage for any purpose although it is intended for non volatile storage of an operating system s boot parameters Real time kernels such as VxWorks and pSOSystem use this memory for the storage of boot parameters Squall Il Module Interface The Cyclone EP contains a single Squall IT Module expansion location and connector Cyclone Microsystems has many off the shelf modules available users are also encouraged to build their own modules Chapter 5 contains complete electrical and mechanical specifications of the Squall II Module Table 3 17 lists the Squall II Modules currently available from Cyclone Microsystems Table 3 18 shows the 1960 CPU Squall module compatibility See Section 1 4 Additional Information on page 1 3 for information on how to contact Cyclone Microsystems They are continually developing new modules and will consider the development of custom modules 9600 Microprocessor User s Guide for Cyclone and 3 13 PCI SDK Evaluation Platforms E Hardware Reference l ntel Table 3 17 Available Squall Il Modules Module Description Q01 Ethernet 82596CA SQ10 SCSI 2 NCR 53C710 SQ11 SCSI 2 Wide NCR 530720 SQ20 High Speed Serial with DMA Two RS
47. Switches and LEDs 3 1 3 2 CPU Modules o0ctocontoaia cai dai 3 2 3 2 1 CPU Module Installation 000000nananannnannnannnnnnnnnnnnnnnnsnnnsnsnsnnnnnnnnnnnn nenne 3 2 3 2 2 CPU Module Clock Frequencies oooccocciniccccnnnncoccccconncncccnnnnannccnnnnnnncccn 3 3 3 2 3 i1960 Jx Hx CPU Counter TiMerS ocoinicinncnnnnnnnnnno cinc conncnonnanonanno 3 3 3 24 CPU Module Vpp Switch 3 3 3 3 GPU Memory Map escocia Ao 3 4 3 4 Interleaved DRAM cua dea EEN 3 4 3 4 1 DRAM Performance nsss ana a E E aE iE 3 5 3 4 2 Upgrading SIMM DAME 3 5 3 5 Flash Momo Y ccoo a a cd 3 6 351 SwapROM SWIItch oooococcccnnnnccccccnnonancccnnnnnnnnnnnn cnn cnn anar cnn narran 3 6 3 6 LOTUS ii A a eee eat 3 7 3 7 Console Serial PO eessen geesde a i n ciales 3 8 3 8 Parallel Eenelter eege 3 9 3 8 1 Parallel Port Bit Assignments oooonnccccnnnnoccconnnncoccccnnn eeeeeeeeeteeeeeeeeeeneeneees 3 9 3 9 Z8536 Counter I O Unit CO 3 10 3 9 1 CGounmterifimers iseinean aaaeeeaa aiaa aE naiai 3 10 3 9 2 CIO Por Assad iaa 3 11 3 93 CIO dell inci leona paria 3 12 3 94 CIO Poli ii a 3 12 3 10 Non Volatile Parameter Memory cooococccccnnnicccccnnncoccccnnnnnnncccnn nan c cana crac 3 13 9600 Microprocessor User s Guide for Cyclone and ili PCI SDK Evaluation Platforms 3 11 Squall l ee EIER 3 13 3 12 PLX PCI 9060 Interface PCI SDK Platform Only 3 14 3 12 1 PCI9060 ConfiguratiON naseke e a ee A EE eE 3 15 3 12 1 1 Accessing Configuration Registers ooo
48. are used to decode an access to a particular region User code should clear write a 0 to as many low bits in the Range Register as needed to address the memory region and all remaining higher bits should be set write a 1 The Local Base Address for PCI to Local Address Space 0 Register 84H see Table 3 23 should then be programmed with the local address of the RAM region When a PCI access to the local memory region is performed the PCI address is changed to the local address by the PCI 9060 chip The number of set bits in the Range Register for that region determine the number of bits to be changed This effectively determines the size of the region Memory space enable pre fetch and PCI space are controlled by the contents of the lower bits of the Range and Local Address Registers The Local Bus Region Descriptor for PCI to Local Accesses Register 98H see Table 3 25 contains control settings for ROM region programming Table 3 21 shows the required settings for memory region 0 on the PCI SDK Platform See Section 3 12 1 5 Memory Region Configuration Examples on page 3 21 for an illustration of RAM region configuration on the PCI SDK Platform i960 Microprocessor User s Guide for Cyclone and PCI SDK Evaluation Platforms n Hardware Reference Table 3 21 Memory Region 0 Settings Bits Function Setting 1 0 Bus Width 11 32 Bit Bus Width 5 2 Internal Wait States 0 No Wait States 6 RE
49. ations Positions 1 and 2 select the interrupt source to INT1 and both cannot be ON or OFF simultaneously Likewise positions 3 and 4 select the interrupt source to INT2 and both cannot be ON or OFF simultaneously Table 3 8 80960Sx and Kx Interrupt Sources INT Signal Interrupt Source INTO Counter Timers Z8536 INT1 Serial Port UART 16C550 or Squall Il Module IRQ1 INT2 Parallel Port or PLX PCI 9060 INT3 Squall Il Module IRQO i960 Microprocessor User s Guide for Cyclone and 3 7 PCI SDK Evaluation Platforms Hardware Reference Table 3 9 80960Sx and Kx Interrupt Switch Settings Interrupt Source Pos1 Pos2 Pos3 Pos4 Switch Diagram Serial Port UART PLX PCI 9060 ON OFF OFF ON Squall Il Module IRQ1 OFF ON OFFt ONT PLX PCI 9060 Serial Port UART Parallel Port ON OFF oN OFF Squall II Module IRQ1 OFF ON ON OFF Parallel Port Factory default position 3 7 Console Serial Port The Cyclone EP has a single console port with an RS 232 line interface The port uses a phone plug connector and the board is supplied with a phone jack to DB25 cable The serial port is implemented with a 16C550 UART clocked with a 1 843 MHz clock The device may be programmed to use this clock with the internal baud rate counters The serial port may be run at baud rates between 1200 and 115200 baud Refer to the 16C550 device data book for a detailed description of the regist
50. atus bits to clear the SES 1e S interrupt 20 Local doorbell interrupt O not active 1 active Yes No 0 21 DMA channel 0 interrupt 0 not active 1 active Yes No 0 3 28 i960 Microprocessor User s Guide for Cyclone and PCI SDK Evaluation Platforms intel Hardware Reference Table 3 33 Interrupt Control Status Sheet 2 of 2 Value after Field Description Read Write Reset Cold PC Reset 22 DMA channel 1 interrupt 0 not active 1 active Yes No 0 BIST interrupt O not active 1 active 23 The BIST built in self test interrupt is generated by writing a 1 to bit 6 of the PCI Yes No 0 Configuration BIST register Clearing bit 6 clears the interrupt Refer to the BIST register for a description of self test Direct Master Bus Master indicator 24 0 a Direct Master was not the bus master during a Master or Target abort Yes No 9 1 a Direct Master was the bus master during a Master or Target abort DMA Channel 0 Bus Master indicator 25 0 DMA Channel 0 was not the bus master during a Master or Target abort Yes No d 1 DMA Channel 0 was the bus master during a Master or Target abort DMA Channel 1Bus Master indicator SS 0 DMA Channel 1was not the bus master during a Master or Target abort Yes No 0 1 DMA Channel 1was the bus master during a Master or Target abort PCI 9060 Target Abort indicator 27 0 no abort Yes Yes 0 1 PCI 9060 generated Target Abort after 256
51. cal Expansion ROM Local Base Address Re map and BREQo Register Description Value after Reset Field Description Read Write Cold PC Reset Direct Slave BREQo Delay Clocks Number of local bus clocks in which a Direct Slave HOLD request is pending and a Local Direct Master access is in progress and not being granted the bus HOLDA before asserting 3 0 BREQO Once asserted BREQo remains asserted until the PCI 9060 Se d p receives HOLDA LSB 8 clocks See Section 3 12 3 Deadlock Configuration on page 3 26 for setting this register Local Bus BREQo Enable A 1 value enables the PCI 9060 to assert the si BREQo output Yes ves 0 10 5 Not Used Yes No 0 Re map of PCI Expansion ROM space into a Local address space The bits 31 11 in this register re map replace the PCI address bits used in decode as the Yes Yes FFFFOOOOH Local address bits Table 3 27 Local Expansion ROM Range Register Description S SA Value after Reset Field Description Read Write Cold PC Reset 10 0 Not used Yes Yes 0 Specifies which PCI address bits are used to decode a PCI to local bus expansion ROM Each bit corresponds to an Address bit 31 Set 31 11 1 all bits included in decode clear 0 all others Used in Yes Yes FFFFOOOOH conjunction with PCI Configuration register 30H Default is 64 KBytes MON960 configures the PCI SDK Platform s 512 Kbyte expansion ROM address range E00
52. cess Local 1960 side configuration is performed by user code running on the PCI SDK Platform When this code has finished a bit is set which allows the PCI 9060 to accept PCI accesses from the host system The host side configuration is generally handled by start up code contained in the BIOS on the host system although some cases may require that additional initialization is performed by a device driver or user application Registers on the PCI 9060 are divided into four groups Refer to PLX Technology s PCI 9060 documentation for detailed register descriptions e PCI Configuration Registers e Local Configuration Registers Shared Run Time Registers Local DMA Registers The PCI Configuration Local Configuration and Shared Run Time register groups are accessible to both the local 1960 processor and the host system the Local DMA registers are accessible only to the local processor The PCI Configuration registers are initialized by the host system and need not be programmed from the 1960 side during initialization Local Configuration registers control the mapping of memory from the PCI SDK Platform into PCI space on the host system If memory on the PCI SDK Platform will be accessible from the PCI bus code running on the PCI SDK Platform must initialize several registers in the Local Configuration group In the Shared Run Time register group the Interrupt Control Status E8H and EEPROM Control ECH registers must also be progra
53. consecutive Master retries to a Target 31 28 Not Used Yes No 0 3 12 6 3 12 6 1 Mailbox Registers and Doorbell Interrupts The PCI 9060 provides eight 32 bit bi directional mailbox registers and two 32 bit doorbell registers one PCI to i960 one 1960 to PCI These registers can be used for interprocess communication and synchronization across the PCI bus Values written to the mailbox registers from one side of the bus can be retrieved by the appropriate process running on the other side The PCI 9060 doorbell registers are bitmapped and can indicate 32 different interrupt sources Doorbell interrupts are enabled by setting the appropriate bits in the Interrupt Control and Status Register on the PCI 9060 Using the Mailbox Registers Mailbox registers are included in the local and PCI memory maps when the PCI SDK Platform is present in a host system Refer to PLX PCI 9060 documentation for Mailbox register locations in local and PCI space The Mailboxes latch a value written to them the value can then be read by a process on the other side of the bus Reads to a Mailbox register do not affect the contents does not clear it 9600 Microprocessor User s Guide for Cyclone and 3 29 PCI SDK Evaluation Platforms E Hardware Reference l ntel 3 12 6 2 3 12 6 3 3 12 7 3 30 Generating Doorbell Interrupts Doorbell interrupts to the host system are generated by setting one or more of the bits of the Local to PCI Doorbe
54. cts back to back cycles 3 4 2 9600 Microprocessor User s Guide for Cyclone and Upgrading SIMM DRAM On board DRAM is located in two SIMM sockets as shown in Figure 3 1 The standard configuration is 2 Mbytes of memory and may be upgraded to 8 or 32 Mbytes Table 3 5 shows the modules which you may use The memory modules should use 60 or 70 ns Fast Page Mode DRAM 60 ns memory results in better performance at 25 and 40 MHz operation Use fast page mode x32 or x36 72 pin SIMMs The SIMM block consists of two standard 72 pin SIMM sockets arranged as two banks Both SIMM sockets must contain SIMMs these cannot be left empty The sockets accept the following SIMM types e 256 Kbyte x 32 1 Mbyte e 256 Kbyte x 36 1 Mbyte e 1 Mbyte x 32 4 Mbyte e 1 Mbyte x 36 4 Mbyte e 4 Mbyte x 32 16 Mbyte e 4 Mbyte x 36 16 Mbyte 3 5 PCI SDK Evaluation Platforms E Hardware Reference l ntel Table 3 5 Note 3 5 3 5 1 Note Table 3 6 The x36 SIMM parity bits are not used in this design However the x36 SIMMs are standard for PCs and workstations which makes them more readily available The only penalty is more loading on the address and control lines due to the extra DRAM devices on the x36 SIMM All address and control lines to the SIMMs are terminated with 22 ohm resistors DRAM SIMM Configurations Total Memory both modules Module Type 2 Mbytes 256K x 32 1 Mbyte 8 Mbytes 1M x 32 4 Mby
55. d PCI SDK Evaluation Platforms intel Getting Started 2 2 1 2 1 1 2 1 2 2 1 3 In this chapter step by step instructions show you how to connect the Cyclone EP to a power supply and download and execute an example program This chapter describes Intel s software development tools the MON960 Debug Monitor software installation and hardware configuration Pre Installation Considerations This section provides a general overview of the components required to develop and execute a program on the Cyclone EP The MON960 Debug Monitor User s Guide order number 484290 fully describes several of these components including MON960 commands Host Debugger Interface Library HDIL and the MONDB EXE utility Software Development Tools The Cyclone EP supports many software development tools The installation instructions presented in this chapter were verified using GNU 960 and CTOOLS960 Intel s i960 processor software development tools Advanced C language compilers for the 1960 processor family are available for DOS based systems and a variety of UNIX workstation hosts These products provide execution profiling and instruction scheduling optimizations and also provide an assembler linker and utilities designed for embedded processor software development The instructions in this section explain how to compile link and execute an example program If you are using other software development tools read through this example to
56. de for initializing and reading this register is located in the initialization portion of the MON960 Figure 3 3 shows the bits and bit definitions tables following the figure define the bit functions Figure 3 3 CIO Port A CIO Port A PCI 9060 Installed A 0 not installed Cyclone EP 1 installed PCI SDK Platform DRAM Presence Detect 0 70 ns DRAM 1 60 ns DRAM CPU Module Frequency See Table 3 15 CPU Module Type See Table 3 16 Table 3 15 CIO Port A Bits 5 3 Frequency CPU Module Frequency Signals 16 MHz 010 20 MHz 011 25 MHz 100 33 MHz 101 40 MHz 110 Table 3 16 CIO Port A Bits 2 0 Module Type CPU Module Type Signals 80960Sx 000 80960Kx 001 80960Cx 010 80960Hx 011 i960 Microprocessor User s Guide for Cyclone and 3 11 PCI SDK Evaluation Platforms E Hardware Reference l ntel Table 3 16 CIO Port A Bits 2 0 3 9 3 Module Type CPU Module Type Signals 80960Jx 100 Reserved 101 Reserved 110 Reserved 111 t Reserved for future processors CIO Port B Port B is an 8 bit I O port used to clock read and write the serial EEPROMs located on the Cyclone EP and the Squall II Module Configure the port as open collector bidirectional pins Figure 3 4 shows the pin assignments Section 5 3 Squall II Module Serial EEPROM on page 5 3 discusses the serial EEPROMs and reserved data fie
57. e 0 0 disables decode of Direct Master Memory accesses Yes Yes 0 1 enables decode of Direct Master Memory accesses Direct Master I O Access Enable 1 0 disables decode of Direct Master I O accesses Yes Yes 0 1 enables decode of Direct Master I O accesses LOCK Input Enable 2 0 disables the LOCK input Yes Yes 0 1 enables LOCK input enables PCI locked sequences Direct Master Read Pre fetch Size control 0 the PCI 9060 continues to prefetch read data until the Direct Master access is finished This may result in an additional four un needed Lwords being pre fetched 3 from the PCI bus Yes Yes 0 1 PCI 9060 reads up to four Lwords from the PCI bus for each Direct Master burst read access Do not use this mode for direct master burst reads that exceed four Lwords Direct Master PCI read mode 4 0 PCI 9060 releases the PCI bus when the read FIFO becomes full Yes Yes 0 1 PCI 9060 keeps the PCI bus and deasserts IRDY when the read FIFO becomes full Programmable Almost Full Flag When the number of entries in the 8 deep direct 7 5 master write FIFO exceed this value the output pin DMPAF is asserted low Not Yes Yes 0 Used 15 8 Not Used Yes No 0 31 16 Re map of Local to PCl space into a PCI address space These bits re map Yes Yes 0 replace Local address bits used in decode as the PCI address bits MON960 configures a 1 Gbyte region of PCI memory at PCI address 00000000H through 3FFFFFFFH into local memory space at address 400000
58. e PCI SDK Platform the Cyclone EP has two power connectors J6 and J7 Refer to Section 2 1 4 Power Requirements on page 2 2 for a description of these connectors see Figure 3 1 Cyclone EP and PCI SDK Platform Physical Diagram on page 3 1 to verify locations 9600 Microprocessor User s Guide for Cyclone and 2 3 PCI SDK Evaluation Platforms Getting Started ntel e Warning FAILURE TO PROPERLY CONNECT THE POWER CABLE COULD RESULT IN SEVERE 2 4 2 4 1 2 4 DAMAGE TO THE BOARD If using the power supply provided with the Cyclone EP plug the power supply cable into connector J7 The power supply operates with 120 VAC 60 Hz If using a power supply that provides 5 VDC 12 VDC and ground supply not provided plug the power supply cable into connector J6 The PCI SDK Platform draws power from the PCI bus and should not be connected to an external power supply 9 Check for power within tolerance The 5V and 3 3V LEDs should be lit The 12V and 12V power sources are optional on the standalone board but should be lit when a PCI SDK Platform is installed in a PCI slot Upon power up the Fail LED should turn OFF indicating the processor has passed its self test The green Run LED should light indicating that the processor is performing bus cycles Creating and Downloading the Example Program When you install MON960 on DOS a text file ZZ EXAMPLE C YCLONE IMAGE TXT describes how to compile assemble and lin
59. e cleared on the PCI SDK Platform P i os i Value after Reset Field Description Read Write Cold PC Reset 15 0 Not Used Yes No 0 31 16 Assigns a value to the bits used to decode a Local to PCl memory access Yes Yes 0 Table 3 31 Local Base Address for Direct Master to PCI lO CFG Register e SE Value after Reset Field Description Read Write Cold PC Reset 15 0 Not Used Yes No 0 Assigns a value to the bits used to decode a Local to PCI I O or STE configuration access ae ER Ge Table 3 32 PCI Configuration Address Register for Direct Master to PCI lO CFG Value after Reset configuration cycle 1 allow Local to PCI I O accesses to be converted to a PCI configuration cycle Field Description Read Write Cold PC Reset Configuration Type 1 0 00 Type 0 Yes Yes 0 01 Type 1 7 2 Register Number Yes Yes 0 10 8 Function Number Yes Yes 0 15 11 Device Number Yes Yes 0 23 16 Bus Number Yes Yes 0 30 24 Reserved Yes Yes 0 Configuration Enable Parameters in this table are used to generate the PCI configuration address 31 0 do not allow Local to PCl I O accesses to be converted to a PCI Yes Yes 0 9600 Microprocessor User s Guide for Cyclone and PCI SDK Evaluation Platforms 3 25 E Hardware Reference l ntel 3 12 3 Deadlock Configuration When the PCI SDK Platform is configured to act as a PCI bus master a possible deadlock
60. e for PCI to Local Expansion ROM 10H 94H Local Base Address re map for PCI to Local Expansion ROM and BREQo control 14H 98H Bus Region Descriptors for PCI to Local Accesses 18H 9CH Range for Direct Master to PCl 1CH AOH Local Base Address for Direct Master to PCI Memory 20H A4H Local Base Address for Direct Master to PCI IO CFG 24H A8H PCI Base Address re map for Direct Master to PCI 28H ACH PCI Configuration Address Register for Direct Master to PCl lO CFG 2CH i960 Microprocessor User s Guide for Cyclone and PCI SDK Evaluation Platforms 3 17 Hardware Reference Table 3 20 PCI Configuration Registers 3 12 1 3 3 18 In tal ies rei PCI CFG ship sols t 31 24 23 16 15 8 7 0 Register address Address 00H Device ID Vendor ID 00H 04H Status Command 04H 08H Class Code Revision ID 08H OCH BIST Header Type Latency Timer Cache Line Size DCH 10H PCI Base Address for Memory Mapped Runtime Registers 10H 14H PCI Base Address for I O Mapped Runtime Registers 14H 18H PCI Base Address for Local Address Space 0 18H 1CH 1CH 20H 20H 24H 24H 28H Reserved 28H 2CH Reserved 2CH 30H PCI Base Address to Local Expansion ROM 30H 34H Reserved 34H 38H Reserved 38H 3CH Max_lat Min_Gnt Interrupt Pin Interrupt Line 3CH RAM Region Configuration The range for PCI to Local Address Space 0 Register 80H see Table 3 22 determines which address bits
61. e function of each For a complete list of components refer to Appendix A Parts List Figure 3 1 Cyclone EP and PCI SDK Platform Physical Diagram 25 Pin Parallel Port RS 232 Four Position Connectors for external Centronics compatible Bus Cycle LED green Serial Port DIP Switch ree head SE Power LEDs ASS 5 VDC Cyclone nly User LEDs Fail A red PCI SDK Platform red 5 VDC Reset Pushbutt 9123 45 INS 12V 43 3V 2 AO mm a o CR1 CR2 CR3 CR4 A J5 s2 T fo OOO o DS x A Flash Memory ee SE SE connectors on bottom of CPU module attach here E Xx Pi Modul T nro E attach SIMMs in connectors at 45 angle oo EJ da o E es III CTT EH Ze CECR UI III EJ oi DRAM SIMM d COMER RR TU us O Frequency and VPP switches Squall II Module CPU Module Flash Memory MON960 i960 Microprocessor User s Guide for Cyclone and 3 1 PCI SDK Evaluation Platforms Hardware Reference Table 3 1 External Connectors and LEDs Function Ref Description A one pin connector that interfaces to the primary power supply and cable Power 5 VDC J7 supplied Provides 5 VDC and ground connections Cyclone EP only On the PCI SDK Platform power is supplied through the edge connector A four pin connector that interfaces to a secondary power supply and cable no
62. eiver Transmitter UART 4 5 UNIX support 2 1 V VPP switch 3 3 Vpp Switch 3 3 W wait state performance 4 7 wait states 3 5 4 waveforms 4 7 X X Bus features 4 1 X Bus enabled mode 3 9 Z Z8536 device CIO 3 10 phone plug 3 8 960 Microprocessor User s Guide for Cyclone and PCI SDK Evaluation Platforms
63. em is a asterisks trademark or registered trademark Such brands and names are the property of their respective owners 1 3 Technical Support Schematics and PLD Equations For Technical assistance with the Cyclone EP contact the Intel Technical Support Hotline For information about technical support in other geographical areas contact Intel s North America Technical Support Hotline You can also use your PC with modem to download Cyclone EP and PCI SDK Platform schematics and PLD equations from Intel s Bulletin Board Service BBS North America 800 628 8686 Intel Technical Support Hotline Europe 44 793 696 000 North America 916 356 3600 Intel s Bulletin Board Service BBS supports up to 14 4 Kbps n 8 1 p for schematics and PLD equations Europe 44 793 432 955 1 4 Additional Information To order manuals from Intel contact your local sales representative or Intel Literature Sales 1 800 879 4683 Company Product Document Name Order Number All Intel Solutions960 catalog Intel 270791 i960 Cx Microprocessor User s Manual Intel 270710 80960CA 33 25 16 32 Bit High Performance Embedded Processor Data Sheet Intel 270727 80960Cx 80960CF 33 25 16 32 Bit High Performance Superscalar Processor Data Sheet Intel 272187 80960CF 40 32 Bit High Performance Superscalar Processor Data Sheet Intel 272493 19608 Jx Microprocessor User s Manual I
64. ers and device operation Table 3 10 UART Register Addresses Address Read Register Write Register B000 0000H Receive Holding Register Transmit Holding Register B000 0004H Unused Interrupt Enable Register B000 0008H Interrupt Status Register FIFO Control Register B000 000CH Unused Line Control Register B000 0010H Unused Modem Control Register B000 0014H Line Status Register Unused B000 0018H Modem Status Register Unused Scratchpad Register B000 001CH Scratchpad Register LSB of Divisor Latch MSB of Divisor Latch 3 8 9600 Microprocessor User s Guide for Cyclone and PCI SDK Evaluation Platforms 3 8 Hardware Reference Parallel Port A Centronics PC compatible receive only parallel port is implemented on the Cyclone EP You access and control the parallel port by using three memory mapped registers see Table 3 11 Parallel port data register Parallel port status register Parallel port control register The port uses a DB25 connector with PC compatible pin assignments A cable is included with the Cyclone EP to facilitate downloading of code from a host development workstation or PC Table 3 11 Parallel Port Addresses 3 8 1 Address Read Register Write Register B008 0000H Status Register Control Register B008 0004H Data Register Unused Parallel Port Bit Assignments Table 3 12 shows the read only parallel port status register bit assignments
65. es 3 2 4 9600 Microprocessor User s Guide for Cyclone and Frequency st gengt Pd Switch Diagram 16 MHz ON OFF ON 20 MHz ON OFF OFF 25 MHz OFF ON ON 33 MHz OFF ON OFF 40 MHz OFF OFF ON 50 MHz OFF OFF OFF NOTES 1 On the 80960Sx and Kx CPU Modules the CPU Module Frequency Switch is labeled SW2 On all other 80960 CPU Modules the CPU Module Frequency Switch is labeled SW1 2 CPU module switch position 1 Pos1 is the Vpp switch It is recommended that you leave it OFF Factory default position 960 Jx Hx CPU Counter Timers The 1960 Jx and Hx processors are equipped with two on chip counter timers These timers are clocked at the CPU clock rate which does not correspond exactly with the CPU Module Frequency Switch settings Use Table 3 3 to determine the exact CPU clock frequency CPU Frequency Switch Setting CPU Clock Frequency 16 MHz 16 11 MHz 20 MHz 20 05 MHz 25 MHz 25 06 MHz 33 MHz 33 41 MHz 40 MHz 40 09 MHz CPU Module Vpp Switch The Vpp Switch switch position 1 in Table 3 2 enables disables Vpp to the boot Flash ROMs located on the CPU module It is recommended that this switch remain set to OFF the default setting from the factory When Vpp is enabled switch in ON position the processor may not be able to boot from ROM if the power sequencing of 5V and 12V is not correct PCI SDK Evaluation Platforms Hardware Reference 3 3
66. eset Interrupt and Ready Logic Functional Overview As shown in Figure 1 1 on page 1 1 the main functional blocks and features include e High performance interleaved DRAM subsystem Operates at 2 0 0 0 wait states for burst reads DRAM subsystem is expandable up to 32 Mbytes e I O subsystem provides data buffers and simplified control Supports FLASH from 256 Kbit to 2 Mbit and FLASH an 8 bit memory is used for the monitor and start up diagnostics The Centronics compatible parallel port allows fast download of code or data to the Cyclone EP The asynchronous serial RS 232 port provides transfers up to 115 2 KBaud An Z8536 timer counter provides three 16 bit counters with interrupts e An expansion bus Squall H Module allows expansion cards and external devices direct access to the 960 processor s bus and control signals Clock Generation The Cyclone EP s clocking section must handle the clocking requirements of the various 1960 processors The clock generation circuit is based on an AV9155 01 device which generates a 2x and 1x processor clock based on the FREQ 2 0 switches on the CPU module The AV9155 0 also generates the 1 843 MHz baud rate clock and a 16 MHz clock The 16 MHz clock is later divided to 4 MHz and used for the counter timers and DRAM refresh generation Clock distribution is performed by an CY7BB991 7 device with an internal PLL Output clocks from this device are distributed
67. essors This results in erroneous data being returned in the case of a read but the processor will terminate the cycle allowing the host processor access to its local bus Some method of notifying the 1960 processor that this error has occurred is needed otherwise the erroneous data or incomplete write goes undetected by the i960 processor On the Jx processor an interrupt XINT3 is asserted The Kx and Sx processors however have no free interrupt lines As a result there is no way for these processors to detect the error The XINT3 interrupt on the Jx processor is intended only to inform the system designer that a deadlock error has occurred and is a non recoverable error On the Sx Kx and Jx processors the system designer must ensure that only memory is shared either on the host or PCI SDK Platform but never both The Cx and Hx processors handle the deadlock condition transparently once the PCI 9060 is configured to signal a deadlock On the Jx user code must detect the fatal error interrupt on XINT3 The interrupt should be connected to a handler which provides a signal to the designer that a fatal error has occurred The Local Expansion ROM Local Base Address BREQo Control Register 94H on the PCI 9060 must be configured at initialization to handle the deadlock condition To avoid deadlock the PCI 9060 must be programmed to detect a time out and assert BREQo which either causes the local processor to backoff or in the case o
68. f the Jx causes the processor to be interrupted after the access is complete indicating an error The lower four bits of the Local Expansion ROM Address BREQo Control Register 94H should be set to the number of local bus clocks before a time out is detected and the Local Bus BREQo Enable bit should be set to 1 3 26 i960 Microprocessor User s Guide for Cyclone and PCI SDK Evaluation Platforms INTal 3 12 4 3 12 5 3 12 5 1 Hardware Reference Signalling Init Done Initialization code must set the Local Init Status bit in the EEPROM Control Init Control Register ECH before finishing Until this bit is set the PCI 9060 responds to any attempted master accesses from PCI by signalling RETRY Once this bit is set BIOS code on the host system can proceed with the remainder of the initialization PCI Interrupts The PCI 9060 can be configured to generate PCI interrupts to the host system in response to a number of events Doorbell interrupts which are described in Section 3 12 6 Mailbox Registers and Doorbell Interrupts on page 3 29 provide a simple mechanism for software to send receive signals to from the host processor The PCI 9060 can also be configured to interrupt the host processor if any PCI error conditions such as LSERR or a master or target abort are detected In some applications it may be useful to configure the PCI 9060 to generate a PCI interrupt whenever it generates a local interrupt This allows
69. gner refer to the particular module s user s manual The first four bytes addresses 0 3 contain the module s region configuration word stored in little endian byte ordering bits 7 0 in address 0 The next byte address 4 contains two bits indicating the interrupt detection mode of the Squall II Module s interrupts Interrupts are software configurable in the 1960 processor s Interrupt Control ICON Register to be level low activated or falling edge activated Bit 0 corresponds to SQIRQO XINT4 Bit 1 corresponds to SQIRQ1 XINTSH A zero 0 indicates the interrupt is level low activated A one 1 indicates the interrupt is falling edge activated Bytes 5 and 6 are reserved Bytes 7 and 8 contain the Squall II Module version number in ASCII Users designing their own modules should request a number from Cyclone Microsystems Refer to Section 1 4 Additional Information on page 1 3 for contact information Address 9 contains the module s revision level in binary This field is assigned and incremented by the module designer Bytes OOAH 7FFH are specific to the module Refer to the processor s user s manual As with on board EEPROM bytes are read from and written to the 24C08 EEPROM most significant bit bit 7 first and least significant bit bit 0 last 9600 Microprocessor User s Guide for Cyclone and 5 3 PCI SDK Evaluation Platforms W Squall II Module Interface l ntel e Figure 5 3 Squall Il Module EEPROM Memory
70. h This register connects to the I O data bus as an input only register A read to this register causes the I O timing control to assert the PPDATA_RD signal which enables the data register on the data bus Parallel port status register A read only register used to read the incoming status lines from the parallel port Parallel port control register A write only register whose outputs directly drive the parallel port output signals The parallel port generates an interrupt when the PSTROBE or the PPINIT signal is asserted from an external transmit port The parallel port interrupts are cleared after a read from the parallel data register The parallel Centronics interface has eight data lines PD7 0 and three handshaking lines PBUSY PACK and PSTROBE Figure 4 2 shows the timing relationship between these signals e PSTROBE falling edge causes data to be latched at the parallel port e PACK is a signal line from the parallel port indicating that data has been received e PBUSY is driven to indicate the parallel port is processing the transfer PBUSY is deasserted when data is read from the parallel port register i960 Microprocessor User s Guide for Cyclone and PCI SDK Evaluation Platforms intel Theory of Operation Figure 4 2 Parallel Port Timing Signals 4 4 3 2 co PSTROBE I J PBUSY I cl PPDATA_RD I RD Gg e PACK I Serial Port The Cyclone EP provides one RS 232 serial por
71. h OFF SwapROM Switch ON CPU Module Boot ROM F000 0000H E000 0000H Expansion ROMO U22 E000 0000H F000 0000H Expansion ROM1 U27 E004 0000H F004 0000H If a single Expansion ROM is used as a Boot ROM use location U27 ROM IX so the 1960 processor finds the IBR at the top of the memory map 9600 Microprocessor User s Guide for Cyclone and PCI SDK Evaluation Platforms intel 3 6 Table 3 7 Hardware Reference Interrupts The Cyclone EP has seven interrupt sources The CPU module assumes the interrupts are direct mapped Table 3 7 lists the interrupt sources and the corresponding XINT signals All interrupts are level sensitive except the Squall II Module IRQO and IRQ1 these are dependent on the particular Squall II Module installed Interrupt Sources XINT Signal Interrupt Source XINTO PLX PCI 9060 XINT1 Parallel Port XINT2 PCI 9060 LSERR XINT3 Deadlock Error XINT4 Squall II Module IRQO XINT5 Squall II Module IRQ1 XINT6 Counter Timers 28536 XINT7 Serial Port 16C550 The Sx and Kx processors have only four dedicated interrupt signals A dip switch is provided on the Sx and Kx CPU modules to map the six possible interrupt sources to the four direct mapped interrupt inputs Table 3 8 outlines the interrupt mapping for the Sx and Kx CPU modules The interrupt sources to INT and INT2 are selected using SW 1 on Sx and Kx modules Table 3 9 shows all valid combin
72. hannels are included on the PCI 9060 to facilitate rapid data transfer across the PCI bus Programming is identical for either DMA channel however channel 0 contains a 64 byte deep FIFO intended for high speed data transfer and channel 1 contains a 32 byte FIFO which can be used for slower data or command transfer The two channels can operate concurrently and are both bidirectional In addition both channels support chaining and non chaining operation The DMA controllers can be programmed to interrupt the 1960 processor when they complete a task i960 Microprocessor User s Guide for Cyclone and PCI SDK Evaluation Platforms intel 3 12 7 1 Hardware Reference DMA Non Chaining Mode When a DMA channel is operated in non chaining mode the local processor programs the Mode PCI Address Local Address Transfer Size and Descriptor registers for the DMA channel in question and then sets the Command Status Register to begin the transfer The DMA transfers the number of bytes programmed in the DMA Transfer Size Register and when the operation completes generates a local interrupt if the PCI 9060 is programmed to do so The PCI and Local Address registers should be programmed with the PCI and local addresses for the transfer These registers do not determine transfer direction Addresses programmed into these registers may be unaligned The DMA Transfer Size Register must be set to the number of bytes to be transferred Only the lower 23
73. hapter 5 Squall Design information electrical and physical specifications of the Squall II Module Interface II Module interface are described in this chapter This information is useful when you wish to design and integrate your own Squall Modules If you are using a standard Squall Module refer to the specific module s manual for information on the operation of that module Appendix A Parts This appendix identifies Cyclone Evaluation Platform components and List quantities component reference name as it appears on the PC board description of size or rating and the manufacturer s part number To order replacement parts contact the manufacturer listed in Table A 1 1 2 i960 Microprocessor User s Guide for Cyclone and PCI SDK Evaluation Platforms j ntel m Introduction 1 2 1 Notation Conventions In text hexadecimal numbers are shown with a suffix of H e g XXXX XXXXH Hexadecimal Numbers In code examples and PLD files and in text that refers to specific code examples hex numbers are shown with a prefix of Ox e g OXXXXXXXXX Inverted clock signals are indicated with a trailing pound sign RAS Bold Indicates user entry and or commands Italics Indicates a reference to related documents also used to show emphasis typewriter font Indicates code examples and file directories and names On non Intel company and product names a trailing asterisk indicates the it
74. hes to perform refresh REF is asserted indicating to the CAS generation PAL to assert the CAS signals The RAS is then asserted and the proper number of cycles are waited REF RAS and the CAS are negated and REFPEND is also negated The state machine returns to SO ready to run processor memory cycles i960 Microprocessor User s Guide for Cyclone and 4 9 PCI SDK Evaluation Platforms intel Squall Il Module Interface 5 1 5 Design information electrical and physical specifications of the Squall II Module interface are described in this chapter This information is useful when you wish to design and integrate your own Squall Modules If you are using a standard Squall Module refer to the specific module s manual for information on the operation of that module Physical Attributes The Squall II Module is a printed circuit board which connects to the Cyclone EP The physical dimensions of the Squall II Module interface are illustrated in Figure 5 1 Squall II Module Component Height Allowance on page 5 1 and Figure 5 2 Squall II Module Dimensions on page 5 2 The Cyclone EP has a cutout on the board along the front panel to provide more clearance for connectors mounted on the Squall II Module The Cyclone EP is designed to support one of several Squall II modules These modules allow different I O interfaces to be used Devices on the module may be accessed by the processor in slave mode Devices with DMA controllers
75. ion of PCI space to be accessed is mapped into the local processor s address space The PCI 9060 can access memory or I O space on the PCI bus through region mapping and it can also generate configuration cycles Address mapping is controlled by five registers in the Local Configuration group If the PCI SDK Platform is used to access PCI space the Range for Direct Master to PCI Register 9CH Table 3 28 and PCI Base Address for Direct Master to PCI Register A8H Table 3 29 registers must be programmed for local to PCI accesses PCI memory space and I O space are mapped to separate local processor regions To access PCI memory space the Local Base Address for Direct Master to PCI Memory Register A0H Table 3 30 must be programmed with the local address to which PCI memory space should be mapped For PCI SDK Platform access to PCI I O or configuration spaces the Local Base Address for Direct Master to PCI IO CFG Register A4H Table 3 31 must also be programmed with a local base address If both memory and I O spaces are to be accessed the local base address registers should be programmed with different values to prevent address spaces from overlapping Configuration cycles produced by the PCI 9060 are controlled by the PCI Configuration Address Register ACH Table 3 32 If the Configuration Enable bit in this register is set the PCI 9060 converts I O space accesses to configuration space accesses using the values programmed int
76. iption Read Write Cold PC Reset 0 Space 0 Enable 0 disables Decode of PCI addresses for Direct Slave Yes Yes 0 access to local space 0 1 enables Decode 1 Not Used Yes Yes 0 3 2 If local space 0 is mapped into memory space bits are not used If mapped Yes Yes 0 into I O space bit is included with bits 4 through 31 for re mapping Re map of PCI Address to Local Address Space 0 into a Local Address 31 4 Space The bits in this register will re map replace the PCI Address bits Yes Yes 0 used in decode as the Local Address bits i960 Microprocessor User s Guide for Cyclone and 3 19 PCI SDK Evaluation Platforms E Hardware Reference l ntel Table 3 24 Local Bus Region Descriptor for PCI to Local Access Register Description Value after Reset Field Description Read Write Cold PC Reset Memory Space 0 Local Bus Width 00 indicates a bus width of 8 bits 1 0 01 indicates a bus width of 16 bits Yes Yes 11 10 or 11 indicates a bus width of 32 bits Must be set to 11 32 bit bus width 5 2 Memory Space 0 Internal Wait States Must be 0 Yes Yes 0 Memory Space 0 READY Input Enable 6 0 disables the READY input 1 enables READY input Yes Yes 0 Must be 1 Memory Space 0 BTERM Input Enable 7 0 disables BTERM input 1 enables BTERM input Yes Yes 0 Must be 0 15 8 Not Used Yes Yes 0 Expansion ROM Space Local Bus Width 00 indicates a bus width of 8 bits 17 16 01 indicates a
77. k the example program The text file describes how to create the executable image For this example the image file is named SIEVE XX XX is either Cx Hx Jx Kx or Sx depending on which CPU module you are using If you are using MONDB EXE on DOS to communicate with the Cyclone EP continue to Section 2 4 1 If using a terminal emulation program proceed to Section 2 4 2 Terminal Emulation to Cyclone EP Communication Support on page 2 6 MONDB EXE to Cyclone EP Communication Support To invoke the MONDB EXE utility and download your application program make sure you are in the CYCLONE directory and at the DOS prompt enter DWNLD followed by the name of the image file filename is not case sensitive For example for the Cx CPU module enter DWNLD SIEVE CX DWNLD invokes a batch file DWNLD BAT which contains MONDB EXE commands which configure serial port 1 parallel port 1 and set the baud rate to 19200 You can use a text editor to modify this batch file such that it is correct for your system s configuration Refer to MON960 Debug Monitor User s Guide for a description of all commands Figure 2 1 shows the messages that display during the download If using the serial port the download time increases depending on the baud rate i960 Microprocessor User s Guide for Cyclone and PCI SDK Evaluation Platforms n Getting Started Figure 2 1 Download Messages Section 0 name text address
78. lds Cyclone Microsystems has written code to read and write the serial EEPROMs which is included in the initialization portion of the MON960 Figure 3 4 CIO Port B 3 9 4 3 12 CIO Port B 7 6 5 4 3 2 1 0 Reserved Initialize to 0 Squall Module SDA Squall Module SDK Cyclone EP SDA Cyclone EP SDK CIO Port C Port C is a 4 bit output only port used to drive the four User LEDs CR9 on the Cyclone EP These LEDs are provided as an aid in debugging As shown in Figure 3 1 the leftmost LED is LED 0 which corresponds to CIO Port C bit 0 the rightmost LED is LED 3 which corresponds to CIO Port C bit 3 Setting bits writing a 1 in CIO Port C register turns ON the corresponding LED clearing bits writing a 0 turns the LEDs OFF i960 Microprocessor User s Guide for Cyclone and PCI SDK Evaluation Platforms intel Hardware Reference Figure 3 5 CIO Port C 3 10 3 11 CIO Port C User LED 3 User LED 2 User LED 1 User LED 0 Non Volatile Parameter Memory The Cyclone EP has a 1 Kbyte x8 EEPROM memory which may be used for storing operating system and other default parameters The memory is read and written in a serial fashion using Port B of the CIO Z8536 Refer to a Xicor Inc 24C08 data sheet for technical information Cyclone has written routines to access these devices the routines are included in the initialization portion of MON960 Like the 24C08 EEPR
79. ll Register E4H The host processor can read the Doorbell register to determine which bits are set More than one bit may be set concurrently and the PCI interrupt remains asserted as long as at least one doorbell bit is set This allows the PCI 9060 to signal as many as 32 different interrupts to the host processor PCI masters can generate doorbell interrupts to the 1960 processor by writing the PCI to Local Doorbell Register EOH Setting bits in the PCI to Local Doorbell Register generates an interrupt to the 1960 processor The PCI 9060 signals an interrupt to the local processor as long as at least one bit is set For doorbell interrupts to function the Interrupt Control and Status Register E8H on the PCI 9060 must be programmed to enable the interrupts For local to PCI doorbell interrupts the PCI Interrupt Enable and PCI Doorbell Interrupt Enable bits must be set PCI interrupts must also be enabled and routed on the host system For PCI to local interrupts software must set the Local Interrupt Enable and Local Doorbell Interrupt Enable bits The Interrupt Control and Status Register also contains bits which allow software to poll for PCI or local interrupts Receiving Doorbell Interrupts Provided that interrupts are enabled on the PCI 9060 a PCI to local doorbell interrupt is signalled to the 1960 processor on the PCI 9060 interrupt line XINTO on the Cx Jx and Hx processors INT2 on the Kx and Sx The i960 processor must then p
80. ll always be inactive during slave S EXTEND M O cycles Non burst reads of the DRAM may be extended by asserting EXTEND after ADS S The DRAM controller will hold valid data on the bus and the READY signal active until it detects EXTEND inactive and READY and BLAST asserted The signal should not be asserted on burst or write cycles Reset asserted should cause all the devices and circuitry on the Squall II Module to return RESET A to a known state RESET will be asserted for a minimum of 200ms RESET will always be asserted following power up SL I S_LOCK M O Bus Lock indicates that an atomic ready modify write operation is in progress S Shared Bus Request signals that the Squall Il Module circuitry requested access to the SQBR O shared memory The local bus arbitrator will assert SQBG to grant the Squall II Module bus mastership Shared Bus Grant indicates to a bus requestor that the other shared bus masters have SQBG s relinquished control of the bus The Squall II Module circuitry may now use the shared bus to access the on board shared memory PMCLK CPU Module Output Clock provides a timing reference for all input and output to the processor and the memory Interrupt Request 0 is directly connected to the processor s external interrupt pin XINT4 SQIRQO o This pin may be programmed within the processor as a level low or edge falling activated interrupt source The interrupt priority of this pin may also be programmed
81. mmed from the 1960 side during initialization When complete the configuration code must set the PCI 9060 to allow PCI accesses and the host initialization will begin Note Configure the PCI 9060 for 32 bit 1960 Cx CPU mode regardless of the actual CPU module installed For configuration examples refer to the MON960 configuration code for the PCI 9060 included with the PCI SDK Platform The initial configuration can be divided into the following steps e PCI to local address mapping setup e Local to PCI address mapping setup e Deadlock handling setup 3 12 1 1 Accessing Configuration Registers Code running on the PCI SDK Platform can access configuration registers on the PCI 9060 by adding the offset of the desired register to the PCI 9060 select address 8000 0000H Refer to PLX PCI 9060 documentation for offset values Thus to access Mailbox Register 0 COH the address would be 8000 OOCOH The register descriptions in PLX PCI 9060 documentation indicate whether a register can be read and or written from the local bus Writing to a read only register or bit location on the PCI 9060 has no ill effects the value is simply not latched i960 Microprocessor User s Guide for Cyclone and 3 15 PCI SDK Evaluation Platforms E Hardware Reference l ntel 3 12 1 2 3 16 Once the PCI SDK Platform is initialized by local code some of its configuration registers are accessible to other PCI masters The PCI Configuration Local Configuration
82. mportant The majority of the signals are bussed between the Squall II Module connector the shared memory the processor interface and the PCI bus interface For best results restrict these signals to two loads on each Squall II Module Some signals are routed to an individual Squall II Module and therefore may be more heavily loaded Refer to Table 5 7 for specific loading restrictions Table 5 7 Squall Il Module Signal Loading 5 18 Signal Loads S_A S_D S_BE S_W R S_ADS S_READY S_BLAST S_EXTEND S_LOCK 2 SQSEL 6 RESET 10 SQBG 6 PMCLK 5 i960 Microprocessor User s Guide for Cyclone and PCI SDK Evaluation Platforms W ntel 6 Squall II Module Interface 5 9 Squall Il Module Clock Termination Individual clock signals are driven to each Squall II Module Clock signals should be terminated with an AC termination of 470 pF and 51 ohms to ground as shown in Figure 5 10 Care should be taken to locate the loads close to the end of the signal especially in double sized modules Figure 5 10 Squall Il Module Clock Termination PMCLK 51 Ohms T 470 pF 9600 Microprocessor User s Guide for Cyclone and 5 19 PCI SDK Evaluation Platforms intel Parts List A This appendix identifies Cyclone Evaluation Platform components and quantities component reference name as it appears on the PC board description of size or rating and the manufacturer e part number To
83. ntel 272483 oe 80960JA JF Embedded 32 Bit Microprocessor Data Sheet Intel 272504 i960 Microprocessor User s Guide for Cyclone and 1 3 PCI SDK Evaluation Platforms Introduction i ntel e Company Product Document Name Order Number i960 KA KB Microprocessor Programmer s Reference Manual Intel 270567 80960KB Hardware Designer s Reference Manual Intel 270564 80960Kx 80960KA Embedded 32 Bit Processor Data Sheet Intel 270775 80960KB Embedded 32 Bit Processor With Integrated Floating Point Unit Data Intel 270565 Sheet i960 SA SB Microprocessor Reference Manual Intel 270929 80960Sx 80960SA Embedded 32 Bit Processor With 16 Bit Burst Data Bus Data Sheet Intel 272206 80960SB Embedded 32 Bit Processor With 16 Bit Burst Data Bus and Integrated Intel 272207 Floating Point Unit Data Sheet MON960 Debug Monitor User s Guide Intel 484290 Z8536 CIO Counter Timer Technical Manual Zilog Inc Texas 16C550 Data Sheet Instruments Other 24C08 Serial EEPROM Data Sheet Xicor Inc Data Communications Local Area Networks UARTs Handbook National Semiconductor PLX PCI 9060 User s Guide Data Sheet Technology 800 759 3735 To contact Cyclone Microsystems for additional information about their products Phone 203 786 5536 Cyclone Microsystems 25 Science Park FAX 203 786 5025 New Haven CT 06511 e mail info cyclone com 1 4 9600 Microprocessor User s Guide for Cyclone an
84. o PCI SDK Platform are clearly indicated Unless otherwise noted all references in this manual to Cyclone EP also apply to the PCI SDK Platform References that are specific to PCI SDK Platform are clearly indicated Figure 1 1 Cyclone EP and PCI SDK Platform Functional Block Diagram To VO Panel Connector ONLY E l l l l l l l Interleaved Py Processor gt Clock Distribution DRAM SIMMs Squall Module CPU Flash ROM DRAM Control gt gt PLX 9060 CIO Expansion Parallel UART Based Counter Flash Download RS 232 PCI to ig60 cpu Timers ROM Port Serial Port Bridge with DMA l Phone Jack DB 25 Connector Connection i960 Microprocessor User s Guide for Cyclone and 1 1 PCI SDK Evaluation Platforms Introduction i ntel e 1 1 Advantages and Features As shown in Figure 1 1 and Figure 3 1 Cyclone EP and PCI SDK Platform Physical Diagram the features which make the Cyclone EP useful for evaluation and code development are e Interchangeable 1960 processor modules e DIP switch selectable processor clock referred to as CPU modules frequency e SIMM sockets which support 2 8 or 32 e DRAM controller automatically optimizes Mbytes of DRAM wait states to CPU frequency and memory speed e Flash ROM sockets e RS 232 serial port Three 16 bit co
85. o this register Local to PCI bus options are controlled by settings in the PCI Base Address Register ASH Bit 0 must be set 1 to enable accesses to PCI memory space bit 1 must be set to enable I O accesses Bit 2 controls LOCK input from the PCI bus and should be set Bit 3 controls pre fetch size for PCI master accesses and should be cleared 0 Bit 4 is used to change the behavior of the PCI 9060 when the read FIFO is full It can remain cleared unless there is some reason to change it Bits 5 to 7 control the programmable almost full flag on the PCI 9060 This feature is not implemented on the PCI SDK Platform so these bits should all be cleared Table 3 28 Local Range Register for Direct Master to PCI Description Value after Field Description Read Write Reset Cold PC Reset 15 0 Not Used 64 Kbyte increments Yes No 0 Specifies which Local address bits are used to decode a Local to PCl bus 31 16 access Each bit corresponds to an address bit Bit 31 corresponds to Yes Yes 0 Address bit 31 Set 1 all bits included in decode clear 0 all other bits 9600 Microprocessor User s Guide for Cyclone and 3 23 PCI SDK Evaluation Platforms Hardware Reference intel Table 3 29 PCI Base Address Re map Register for Direct Master to PCI Description Value after Field Description Read Write Reset Cold PC Reset Direct Master Memory Access Enabl
86. odule Master Timing Squall II Module circuits may become masters of the shared bus to perform DMA operations to the shared DRAM DMA controllers gain control of the bus via the SQBR and SQBG signals All signals except the interrupt signals are synchronous to the processor s clock PLCK Set up and hold times must be observed for every rising clock edge Because of the high clock rates the following signals must be driven high before they are three stated ADS BLAST EXTEND and LOCK This ensures that valid levels are observed on every rising clock edge DMA controllers gain control of the bus via the SQBR and SQBG signals Memory cycles may then proceed with the same ADS BLAST and READY protocol used by the 1960 Cx Jx and Hx processors The optional use of the EXTEND signal has been added to the interface to facilitate interfacing slower older DMA controller designs EXTEND may only be used in single transfer read cycles to extend the time valid data is on the data bus During an access with EXTEND asserted the i960 Microprocessor User s Guide for Cyclone and PCI SDK Evaluation Platforms Squall II Module Interface DRAM controller presents valid data on the bus with READY asserted The valid data remains on the bus and READY remains asserted until the DRAM controller samples EXTEND negated at a rising edge of the PMCLK The controller then terminates the read cycle Assert BLAST throughout the cycle Using EXT
87. oll the Interrupt Control and Status Register E8H on the PCI 9060 to determine the cause of the interrupt If a doorbell interrupt is detected software should read the PCI to Local Doorbell Register EOH to determine which interrupts are being signalled Writing a 1 to an active doorbell bit clears the bit and if no other doorbell bits are set clears the interrupt also If other doorbell bits are set the interrupt remains asserted Clearing a bit position which is set indicating an active interrupt does not clear the interrupt Triggering a local to PCI doorbell interrupt generates a PCI interrupt to the host system Since a PCI interrupt from the PCI SDK Platform can be generated by any of several events the host system should poll the Interrupt Control and Status Register E8H on the PCI 9060 to determine the cause of the interrupt Once a doorbell interrupt is identified the host system can identify and clear the interrupt by reading the Local to PCI Doorbell Register E4H and setting any bit positions which are asserted Clearing a bit position which is set indicating an active interrupt does not clear the interrupt If one or more bits in the doorbell register remain set the interrupt to the host processor remains asserted For local to PCI doorbell interrupts to function PCI interrupts must be enabled and routed on the host processor and an appropriate interrupt service routine connected in software DMA Programming Two DMA c
88. on the Squall II Module may access the shared packet DRAM in master mode The Squall IT Module has up to 3 3 inches of front panel space to accommodate I O signals and connectors Each Squall II Module contains a serial EEPROM which allows the processor to determine the type revision and programming information of the specific module The EEPROM is read via the Z8536 CIO device Section 5 3 outlines the use of the EEPROM Currently available Squall II Modules are listed in Table 3 17 Available Squall H Modules on page 3 14 Figure 5 1 Squall Il Module Component Height Allowance i960 Microprocessor User s Guide for Cyclone and PCI Panel 0 034 Interboard Separation Plane Squall Il Module 0 700 Cyclone EP E Cyclone EP i Component Space Interboard Separation Plane 5 1 PCI SDK Evaluation Platforms Squall II Module Interface l n Figure 5 2 Squall Il Module Dimensions 3 650 0 850 100 Pin Connector Samtec TFM 150 32 SDLC all three holes are 0 120 DIA thru A We KI we Z1 U2 AS e U4 Pin 50 SS E oo oi PS Pin 51 123 1234 12 Rev xxxx Z2 CYCLONE MICROSYSTEMS Pin 1 i COPYRIGHT 1995 31 00 o N o y Vv o 0 850 3 535 lt gt 3 850 NOTE Dimensions of J1 placement are to center line of the component in x axis and center line of pins 1 and 51 in y axis For pin assignments refe
89. ooocccccnnocicccnocconcnncnannss 3 15 3 12 1 2 PCI to Local Configuration oooonnnccnnnnnnccccnnnnnonccnnnnnnnccncnnnnnnns 3 16 3 12 1 3 RAM Region Configuration ooooocccccnnconnccnnocononcnnnnnncancnnnnnnnns 3 18 3 12 1 4 Expansion ROM Region Configuration oooionccncnnnnnccnnnncnnnc 3 21 3 12 1 5 Memory Region Configuration Examples 3 21 3 12 2 Local to PCl Configuration ooomocccccnnncccccnnncocccccnnnoncccnonnnanccnnnnnnnncninnns 3 23 3 12 3 Deadlock Configuration ssseeesesseeesnrneeisnnnesrnnnnnsttnnnesttenneennennneennnne 3 26 3 12 4 Signalling Init DONE eaii eect e cette a aaa aa aa A a e a 3 27 3 125 POL Interrupts o aiai i A Aai A 3 27 3 12 5 1 Local PCI Interrupts eroria aAA ASADA Ai 3 27 3 12 6 Mailbox Registers and Doorbell Interrupts AA 3 29 3 12 6 1 Using the Mailbox Heotsterg 3 29 3 12 6 2 Generating Doorbell Interrupts ooooocnnnnnnnnnnnicncnnnncccncnncnnns 3 30 3 12 6 3 Receiving Doorbell Interrupts eee ceeee sense ceeeeenneeeeeeenes 3 30 3 12 7 DMA Programming scisso danaa a 3 30 3 12 7 1 DMA Non Chaining Mode oooocccccnnooccccccononcccconncnnccccnanancnnnnnn 3 31 3 12 7 2 DMA Chaining Mode ccoocooccccnnncoccccnonononononononnn cnn nn nnnnnnnnnnnnnns 3 32 3 12 7 3 DMA Interrupt oooonoccccnnnncccccnnonconccnnnnnnonn cnn nnnnnn a Anai Keka AIia in 3 33 Theory OF OP elation tica tas 4 1 4 1 Sleeve VE 4 1 4 2 Glock Denerati Maraera E e EE eescht 4 1 4 3 Power Monitor and H
90. order replacement parts contact the manufacturer listed in Table A 1 Table A 1 Cyclone EP PCI SDK Platform Bill Of Materials Sheet 1 of 3 CYCLONE EVALUATION PLATFORM Revision 0 01 Bill Of Materials Revised December1994 CFEVALBD SCH 5 Reference Description Mfg Part Manufacturer i Central 1 1 CR8 Diode CMSH1 20 Sgimiconductor Texas 2 1 U13 UART TL16C550AFN instrument 1 U15 Memory EPROM X24C08S8 Xicor 4 2 U22 U27 Non Volatile Memory N28F020 200 Intel 4 U12 U21 U25 U26 IC 74ABT241D National Texas 6 1 U6 IC SN74ABT245DW istrument Texas 7 2 U2 U3 IC SN74ABT574DW iisir ments Texas 8 3 U1 U4 U5 IC SN74LS244DW etrumante 9 1 U10 Clock Chip AV9155 01CW20 ICS C1206C101 10 1 C35 Capacitor 0 01 uF K5RAC Kemet 11 1 C36 Capacitor 0 22 UF TAFAOR22K35RBJ AVX C1 C2 C3 C4 C5 C7 C8 C9 C10 C11 C12 C13 C14 015 C16 C18 C19 C20 e C1206C104 12 33 C21 C22 C23 C24 Capacitor 0 01 uF M5UCA Kemet C26 C27 C28 C29 C30 C31 C33 C37 C38 C39 C41 13 1 C34 Capacitor 4 7 uF 293D475X9035D2T Sprague 14 3 C6 C17 C25 Capacitor 33uF 293D336X9016D2T Sprague 15 1 C40 Capacitor 47uF TPSD476K016R015 AVX 16 1 C32 Capacitor 220uF TPSE227K010R010 AVX i Central 17 1 CR7 Diode CMPSH3 Semicondu tor 18 1 L1 Surface Mount Coil CDR74B Sumida 19 1 J6 Connector 641737 1 AMP 9600 Microprocessor User s Guide for Cyclone and A 1
91. quall II Module Interface l ntel e Figure 5 7 Squall Il Master Read and Write Timing Diagram B610 TD mex Se 1 1 1 1 1 t2 CN i SOBR A a e e fe D tl SQBG p S_ADS A S_BLAST p e Cum S_ADDR e S_DATA A S READY A 5 14 9600 Microprocessor User s Guide for Cyclone and PCI SDK Evaluation Platforms W ntel 6 Squall II Module Interface Figure 5 8 Squall Il Master Burst Read and Write Timing Diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 D612A TD e m a ee ee AE A oa E A A Ei a a PMCLK SQBR SQBG S_ADS S_BLAST S_EXTEND S_ADDR S_W R S_DATA S_READY Figure 5 9 Squall II Master Read Using S_EXTEND on page 5 16 shows a three clock cycle access Refresh cycles may cause READY to be delayed by up to 10 additional clock cycles Read cycle extends by asserting EXTEND Valid data is placed on the bus by the DRAM when READY is asserted Valid data is held on the bus for every rising clock edge in which EXTEND is asserted Cycle ends with BLAST and READ Y asserted and EXTEND negated i960 Microprocessor User s Guide for Cyclone and 5 15 PCI SDK Evaluation Platforms W Squall II Module Interface l ntel e Figure 5 9 Squall Il Master Read Using S_EXTEND wen E PUYVUVUVUVUVUVUVUVUVA s
92. r to Table 5 6 Squall II Module Pin Assignments on page 5 17 5 2 i960 Microprocessor User s Guide for Cyclone and PCI SDK Evaluation Platforms intel 5 2 Table 5 1 5 3 Squall II Module Interface Power Requirements The Squall II Module connectors supply 5v and 12v Make sure you do not exceed the maximum amperage listed in Table 5 1 If power is lead off the module via the front panel or the J6 P2 connector a fuse should be used to prevent damage to the Cyclone EP that may occur due to an incorrect connection Power Supply Volts Squall Connector Pins Maximum Current 5v 5 pins 2 5 Amps Maximum 12v 1 pin 0 5 Amps Maximum 12v 1 pin Not Available GND 10 pins Squall ll Module Serial EEPROM Every Squall II Module has a 24C08 serial EEPROM which the host processor uses to e identify the type and revision of the installed module store any system parameters which might be module dependent EEPROMs are read and written serially using parallel port B of the 8536 CIO device Refer to a 24C08 data sheet for information on how to use the device Routines are available to access these devices To access this code see Section 1 4 Additional Information on page 1 3 Every MON960 ROM for the Cyclone EP reads the serial EEPROMs to properly configure the board The first 10 bytes function identically on all Squall II Modules The remaining memory is assignable by the module s desi
93. rd 72 pin SIMMs 3 2 CPU Modules As shown in Figure 3 1 a CPU module is a smaller board that attaches directly onto the Cyclone EP Several CPU modules are available one for each member of the 1960 processor family Each module contains a i960 processor boot Flash ROM with the MON960 monitor appropriate glue logic and configuration switches 3 2 1 CPU Module Installation CPU modules are easy to install when a few guidelines are observed e Make sure the power is OFF before you install or remove a CPU module Do not peel connectors Peeling is the action of lifting one end of the connector before the other This can bend or break the pins and connectors i960 Microprocessor User s Guide for Cyclone and PCI SDK Evaluation Platforms intel 3 2 2 Note Hardware Reference CPU Module Clock Frequencies The CPU modules have user assignable clock frequencies Make sure you do NOT select a frequency faster than the installed processor is capable of running Table 3 2 outlines the processor frequency switch settings It is recommended that you remove power before you change the switch settings however if you change the switch settings while power is connected press the reset switch to reboot the processor at the new frequency DO NOT select a frequency faster than the installed processor is capable of running Table 3 2 CPU Module Frequency Switch Settings 3 2 3 Table 3 3 19609 Jx Hx CPU Clock Rat
94. ry control circuit asserts S_READY to indicate that valid read data is on the data bus or that a write transfer is complete Select Squallis a select signal for a processor s 256 Mbyte memory region The memory region base address is C000 0000H The designer must return S_READY to the processor SQSEL when this signal is active SQSEL is asserted on the rising edge of PMCLK if S_ADS is S E asserted and A 28 31 C000 0000H SQSEL is negated on the rising edge of PMCLK with S_BLAST and S_READY asserted Burst Last indicates the last transfer in a bus access In slave mode S_BLAST is asserted SL I in the data transfer of burst and non burst accesses after the processor s wait state counter S BLAST M O reaches zero S_BLAST remains active until the clock following the last cycle of the last S data transfer of a bus access If S_READY signal is used to extend wait states the S_BLAST signal remains active until S_READY terminates the access In master mode this signal should be used to indicate to the shared memory the last cycle of a burst access 960 Microprocessor User s Guide for Cyclone and PCI SDK Evaluation Platforms In Squall II Module Interface Table 5 3 Squall Module Signal Descriptions Sheet 2 of 2 Name Type Description Extend may be used by slow Squall II Module masters to extend a shared memory read or SL write cycle Extend has no meaning for slaves and wi
95. s more than 1 0 A you need to obtain a suitable power supply To program FLASH devices you must supply a FLASH programming voltage through J6 J6 uses a standard PC AT power connector pinout that provides 5 VDC and 12 VDC to the board J7 provides 5 VDC only See Figure 3 1 Cyclone EP and PCI SDK Platform Physical Diagram on page 3 1 for J6 J7 locations The PCI SDK Platform draws power from the PCI bus it does not require an external power source The PCI bus also provides the voltages needed for FLASH programming i960 Microprocessor User s Guide for Cyclone and PCI SDK Evaluation Platforms 2 2 2 2 1 2 3 2 3 1 Getting Started Software Installation Installing Software Development Tools If you haven t done so already install your development software CTOOLS960 GNU 960 or other as described in their respective manuals All further references to CTOOLS960 or GNU 960 assume the default directories in the respective installation program were selected You must install the tools before you run the example program as described in Section 2 4 Creating and Downloading the Example Program on page 2 4 The example program provided on the MON960 diskette enables you to use CTOOLS960 or GNU 960 or other to compile a sample application program If you are using other software tools these instructions generally apply however in some steps you will need to refer to their respective manuals for compatible commands
96. s when transfer completes Download complete Start address is XXXXXXX gt 5 To execute your program at the MON960 prompt enter go gt go go go from start or continue from breakpoint The messages in Figure 2 2 display when the program completes times may vary slightly The example program has now been successfully compiled assembled linked downloaded and executed Figure 2 2 Program Execution Messages gt gt gt Start of sieves test lt lt lt Sieve of Eratosthenes scaled to 10 Iterations Array Size Primes Last Prime BenchTime Bytes Found Sec 8191 1899 16381 0 060 10000 2261 19997 0 073 20000 4202 39989 0 149 40000 7836 79999 0 301 80000 14683 160001 0 610 160000 27607 319993 1 235 Average BenchTime 0 061 sec gt gt gt End of sieves test lt lt lt Program Exit 0 gt Relative to 10 Iterations and the 8191 Array Size 2 6 960 Microprocessor User s Guide for Cyclone and PCI SDK Evaluation Platforms intel Hardware Reference 3 The location of the CPU and Squall modules connectors switches and LEDs are described in this chapter Also covered are the memory maps I O and memory operation For the PCI SDK Platform this chapter describes the PCI 9060 interface and operation 3 1 Connectors Switches and LEDs Figure 3 1 shows the physical location of the components you need to understand to use the Cyclone Evaluation Platform Table 3 1 describes th
97. sfer should have the End of Chain bit set in the Mode Register Once the descriptor blocks are set up the 1960 processor initiates the chaining transfer by writing the first descriptor address to the Next Descriptor Address Register and then setting the appropriate channel control bit in the DMA Command Status Register Code should ensure that the channel enable bit for the channel in use is set before starting a transfer Example DMA configuration code is included in the PCI SDK Platform diagnostics which are packaged with the board Figure 3 7 Chaining DMA Initialization 3 32 Set DMA mode to chaining 1st PCI Address PCI Host Memory 1st Local Address Mode Register 1st Transfer Size byte count 1st Memory Block Set up 1st Descriptor Pointer Register 1st only requires Descriptor Pointer Next Descriptor Pointer to Transfer a Next Memory Bloc Descriptor Pointer Register PCI Address to Traneier Setting the Enable and Go bits in the DMA E Command Status Register initiates Transfer Size byte count the DMA transfer Next Descriptor Pointer Command Status Register End of chain a specification bit 1st Memory Block to Transfer Next Memory Block to Transfer i960 Microprocessor User s Guide for Cyclone and PCI SDK Evaluation Platforms In 3 12 7 3 Hardware Reference DMA Interrupts
98. sisan anisninnnnnananin 5 6 Squall Il Module Slave Timing 5 9 Squall Il Module Master Timing 5 13 Squall Il Module Pin Aesionments 5 17 Squall Il Module Signal Loadmg A 5 18 Cyclone EP PCI SDK Platform Bill Of Materials AA A 1 i960 Microprocessor User s Guide for Cyclone and PCI SDK Evaluation Platforms intel Introduction This user s guide describes the Cyclone evaluation platforms for Intel s family of i960 embedded processors e Cyclone EP a standalone general purpose evaluation and development tool e PCI SDK Platform Cyclone EP equipped with a PCI bus interface Part of Intel s PCI I O Software Development Toolkit SDK Both platforms allow you to connect one of several 1960 CPU and Squall modules Using the different CPU modules you can evaluate the various 1960 processors in a system environment or benchmark the performance of the various processors The PCI SDK Platform otherwise identical to the Cyclone EP is equipped with PLX Technology s PCI 9060 a PCI to 80960 bus bridge chip The single chip PCI 9060 features mailbox and doorbell registers that allow command and status information to pass between PCI bus devices and local bus devices It can also generate PCI configuration cycles which enables the PCI 9060 to become the PCI system host Unless otherwise noted all references in this manual to Cyclone EP also apply to the PCI SDK Platform References that are specific t
99. stalled DRAM and configures the DRAM as a PCI memory region Suppose 8 Mbytes of DRAM are located at local address A0000000H through AO7FFFFFH To configure this region to be visible in memory space on the PCI bus the following register settings must be made Local Address Space 0 Range Register 80H FF800000H e An 8 Mbyte space is being mapped so the lower 23 bits are needed to decode an access and must be clear The upper 9 set bits of a PCI to local access to this region are replaced with the contents of the Local Address Space 0 Local Base Address Register 84H Bit 0 is clear so memory is mapped into PCI memory space Bits and 2 are clear so the host system maps this region anywhere in 32 bit PCI address space Bit 3 is clear indicating that the memory in this region is not pre fetchable i960 Microprocessor User s Guide for Cyclone and 3 21 PCI SDK Evaluation Platforms Hardware Reference n Local Address Space 0 Local Base Address Register 84H A0000001H The upper 9 bits of this register replace those used to access the local memory from PCI since 9 bits are set in the Range Register Bit 0 is set enabling PCI accesses to this space Bit 1 is not used and since this region is mapped into memory space bits 2 and 3 are also unused Local Bus Region Descriptor for PCI to Local Accesses Register 98H e All RAM regions on the PCI SDK Platform should use the settings in Table 3 21 for this register Table 3 26 Lo
100. t Power 5 VDC 12 VDC J6 supplied Three of the connector pins connect to 5 VDC 12 VDC and ground Cyclone EP only On the PCI SDK Platform power is supplied through the edge connector CR1 Lit when 5V is in tolerance CR2 Lit when 12V is in tolerance LED GREEN CR3 Lit when 12V is in tolerance CR4 Lit when 3 3V and 5V is in tolerance CR5 Lit when processor is performing bus cycles LED RED CR6 Lit if processor fails self test or CPU module is not installed User LEDs RED CR9 Four user programmable LEDs programmed via CIO Port C Serial Port RS 232 J5 An RJ 11 phone plug connector for serial communication and download Parallel Port Centronics compatible J1 A DB 25 connector for parallel download Allows Squall II Module expansion l O devices are given direct access to the Squall II Interface J2 memory system i960 Processor Module J3 J4 Modules which allow all current and future i960 processors to be used on the CPU Module Cyclone EP and PCI SDK Platform 1 1 Enables VPP to Cyclone EP base board Flash ROMs 1 2 Enables UART Interrupt Request to the NMI Four position DIP Switch 1 S1 3 ROMSWAP causes the addresses of the CPU Module ROM and the base board ROMs to be exchanged If switch is OFF the processor boots from the CPU Module ROM If switch is ON the processor boots from base board ROMs Reset pushbutton 2 Used to manually reset the Cyclone EP DRAM SIMM Sockets U19 U20 Supports up to 32 Mbytes of standa
101. t which is used for communications and program download This port implements the signals for transmit receive clear to send and request Chapter 2 Getting Started contains extensive information on communications and downloading The serial port interface provides asynchronous RS 232 standard communication for monitors or user defined applications The serial port interface consists of two components e 16550CV Universal Asynchronous Receiver Transmitter UART with FIFOs e MAX232 5V Powered RS 232 Driver Receiver National Semiconductor s 16550 UART implements an independent asynchronous serial port on the Cyclone EP The serial port implements a transmit TXD and a receive RXD line The serial port also provides a clear to send CTS and request to send RTS signal to interface to modem applications A 1 843 MHz oscillator provides the baud rate clock for the serial port With this oscillator the 16550 is able to provide serial transmit and receive at up to 115 2 KBaud For more information on programming the 16550 refer to Data Communications Local Area Networks UARTs Handbook National Semiconductor Corporation TXD and RTS from the 16550 are translated to RS 232 compatible signals with a MAX232 buffer receiver chip RXD and CTS are converted into TTL levels by the MAX232 and routed as inputs to the UART chip The MAX232 contains an internal charge pump that generates the RS 232 voltage levels i960 Microprocessor User
102. ter Read Using SG ESTENDA A 5 16 5 10 Squall Il Module Clock Temmimaton 5 19 i960 Microprocessor User s Guide for Cyclone and v PCI SDK Evaluation Platforms Tables vi 3 1 3 3 3 4 3 5 3 6 3 7 3 9 3 10 3 11 3 12 3 13 3 14 3 15 3 16 3 17 3 18 3 19 3 20 3 21 3 22 3 23 3 24 3 25 3 26 3 27 3 28 3 29 3 30 3 31 3 32 3 33 4 1 5 1 5 2 5 3 5 4 5 5 5 6 5 7 A 1 External Connectors and LEDS ou ee eeeeceeeeeeeeeeeeeeeeeeeeeeeeeseeeeeeeeeeeneeeeeeeeeneeeenes 3 2 CPU Module Frequency Switch Settings cccceeeesseeeeeeeeeenneeeeeeesaeeeeeeeeeeaaees 3 3 1960 Jx Hx CPU Clock Rates serias dd 3 3 DRAM Access TIMES vocoicidina tias lana diia 3 5 DRAM SIMM Configurations csee iaae nn 3 6 Flash ROM Addresses A 3 6 INtOrrUpt SQUICES cicien E A 3 7 80960Sx and Kx Interrupt Sources ccooooooocccccconocccccnnncnncnccnanoncnnnnnnnnnnccnnnnnnnnncnnnnns 3 7 80960Sx and Kx Interrupt Switch Settings eeeeeeeeeeeseeeeeeeesereeeererresrrerrnnnrrensn 3 8 UART Register Addresses AANEREN 3 8 Parallel Port Addresses ccicocoiicoimaiincoi a 3 9 Parallel Port Status Register Bit Assignments 0oocoonnnniccccnnnnacccccnnnnanccnnnnncnccnnns 3 9 Parallel Port Control Register Bit Assignments oocccccnnnnnccccnnncccccnnnnonccnncnnnnnnns 3 10 CIO Register Address ooomoccccnnnnccccnnnnncccncnnnnncnn nc nnnnn cnn 3 10 ClO Port A BIS Divina odio 3 11 GIO PortA Bits 2 Oia ia dee 3 11 Available Squall ll
103. tes 32 Mbytes 4M x 32 16 Mbytes Both SIMM modules must be installed SIMM sockets cannot be empty The board has no shunts or switches to change for a memory upgrade Memory speed is indicated by the Presence Detect Signals the DRAM controller automatically adjusts to minimum wait states for the processor frequency and memory speeds The initialization code automatically sizes the memory so user software can take advantage of larger memory modules Flash Memory The Cyclone EP provides two banks of Flash memory a primary memory bank on the CPU module and an expansion bank on the base board The default configuration of this memory is as the boot memory containing the MON960 monitor The second bank of memory is two sockets for Intel 28F020 devices Intel part number N28F020 200 in locations U22 and U27 These memory devices may be used for user application code or using the SwapROM switch as boot memory SwapROM Switch The SwapROM switch third switch on SW1 exchanges the addresses of the CPU module boot ROM and the expansion ROMs to allow the processor to boot from the expansion ROM Table 3 6 shows the address of the Flash ROMs relative to the SwapROM switch Figure 3 1 shows SW1 switch location This feature is supported for all 1960 processors except for Kx and Sx processors These must boot from boot ROMs and therefore must have the SwapROM switch set to OFF Flash ROM Addresses ROM Type SwapROM Switc
104. the host system or another PCI master to receive automatic notification whenever a local interrupt is triggered by the PCI 9060 and take some appropriate action All interrupt enabling and detection on the PCI 9060 is handled through the Interrupt Control and Status Register E8H Table 3 33 If any PCI or local interrupts are used the PCI or Local Interrupt Enable bit in this register must be set in addition to the separate enable bits for the interrupt sources in use Interrupt handling code on the 1960 processor should check the interrupt active bits in the Interrupt Control and Status Register E8H to determine the source of the interrupt and call an appropriate interrupt service routine to process the interrupt Local PCI Interrupts Local interrupts from the PCI 9060 are signalled to the 1960 processor on XINTO for Cx Hx and Jx processors and INT2 for the Sx and Kx Local PCI interrupts may be generated by self test completion BIST either of the DMA channels the PCI to Local Doorbell Register or LSERR Each condition has separate interrupt enable bits in the Interrupt Control and Status Register E8H DMA and doorbell interrupts are discussed separately in the following subsections The BIST interrupt can be generated by local test code by setting bit 6 of the PCI Configuration BIST Register OFH and is typically used by 1960 side diagnostics to indicate completion LSERR can be asserted by the PCI 9060 when it detects a
105. unter timers or one 32 bit Parallel download port Centronics and one 16 bit counter compatible e Squall II Module I O expansion interface e PCI Bus Interface PCI SDK Platform only 1 2 About This Manual This manual contains five chapters one appendix and an index A brief description of each follows Chapter 1 Introduces Intel s Cyclone Evaluation Platform and its features Also Introduction defines notation conventions and related documentation Chapter 2 Getting In this chapter step by step instructions show you how to connect the Started Cyclone EP to a power supply and download and execute an example program This chapter describes Intel s software development tools the MON960 Debug Monitor software installation and hardware configuration Chapter 3 The location of the CPU and Squall modules connectors switches and Hardware LEDs are described in this chapter Also covered are the memory maps Reference T O and memory operation For the PCI SDK Platform this chapter describes the PCI 9060 interface and operation Chapter 4 Theory This chapter describes functionality of the Cyclone Evaluation of Operation Platform s subsystems I O Interface describes the general I O implementation Subsections further describe each functional block DRAM Subsystem similarly defines the DRAM implementation Also covered are Clock Generation Reset Interrupt and Ready Logic C
106. ving Bank interleaving allows the second third and fourth accesses of a burst read to occur in zero wait states The first data access must still pay the entire access penalty Interleaving significantly improves memory system performance by overlapping accesses to consecutive addresses Two way interleaving is accomplished by dividing the memory into two 32 bit banks also referred to as leaves one bank for the even word addresses A2 0 e one bank for odd word addresses A2 1 The two banks are read in parallel and the data from the two banks is multiplexed onto the processor s data bus Multiplexing is implemented via the CASxA and CASxB signals CASH signals in addition to being the Column Address Strobes are also output enable signals for the DRAM Figure 4 3 Two way Interleaving on page 4 7 shows DRAM with a 2 1 1 1 quad word burst read wait state profile being interleaved to generate a 2 0 0 0 wait state system i960 Microprocessor User s Guide for Cyclone and PCI SDK Evaluation Platforms intel Theory of Operation Figure 4 3 Two way Interleaving 4 5 1 2 Note 4 5 2 9600 Microprocessor User s Guide for Cyclone and l l l j l l l l l l CLK I Even Bank Bank A Odd Bank Bank B Processor I A Address W Wait D Data Wait State Performance Table 3 4 DRAM Access Times on page 3 5 shows the wait state performance for the DRAM Table 3 5 DRAM SI
107. within the processor SQIRQ1 O Interrupt Request 1 is the same as SQIRQO except that it is connected to the processor s external interrupt pin XINT3 9600 Microprocessor User s Guide for Cyclone and 5 7 PCI SDK Evaluation Platforms W Squall II Module Interface l ntel e 5 6 5 6 1 5 8 Squall Il Module Timing The Squall Interface signals are an enhanced set of the 1960 Cx processor s bus signals The interface has two modes of operation slave and master In slave mode the processor is accessing devices on the Squall IT Module e In master mode a Squall II Module based DMA controller is accessing the shared memory Squall Il Module Slave Timing This section outlines the signal timing of the Squall IT Module interface when the 1960 processor is reading or writing the Squall II Module The timing for the Squall II Modules in slave mode is difficult to quantify because of the multitude of 1960 processors and frequencies which can be run on the Cyclone EP Most designers will only be concerned with a particular processor at a specific range of frequencies and will not need to concern themselves with all the possible combinations The Cyclone EP local bus and the Squall II Module interface operate like the 1960 CA CF processor s bus interface regardless of which i960 processor module is installed On the Cyclone EP most of the Squall II Module signals are directly connected to the 1960 processor Although processors i e
108. z 111 70ns 0 5 2 2 2 2 4 2 2 2 2 Figure 4 4 DRAM State Machine Va eee Assert REF RAS T Assert REF RAS Assert REF RAS BLAST PF3 W_R arge 4 BLAST PFI BLAST PF2 BLAST PF3 W_R Prech Precharge REPEND BLAST PFO Precharge Idle ADS seldram PFO ADS seldram DEI PF2 PF3 MEMPEND PFO Assert RAS Assert RAS Assert CASEN If PF3 AN Hi assert INCBANK BLAST W R PF3 BLAST W_R PF2 m i W_R PF2 PF3 BLAST W R Assert RAS a Assert CASEN D Assert INCBANK ag ECK W_R PFO gt oa N BLAST W_R PF1 Assert RAS If W_R assert CASEN If WW_R PF2 PF3 a assert INCBANK A XTEND AN P 4 8 9600 Microprocessor User s Guide for Cyclone and PCI SDK Evaluation Platforms 4 7 Theory of Operation CASF Generation The CAS signals to the A and B banks of DRAM are generated from a high speed 20V8 PAL with clock to output timing of 5 ns The BANKSEL signal from the iFX780 determines which set of CASH signals is asserted The processor s BEx signals are used to qualify the CAS signals Refresh Generation CAS before RAS refresh is performed A counter is buried in the iFX780 counting 16 us from the 4 MHz clock Every 16 us the signal REFPEND is asserted If state SO is entered and REFPEND is active the state machine branc

Download Pdf Manuals

Related Search

Related Contents

  医療従事者の健康管理と環境管理 - 公益社団法人 愛知県臨床検査技師会  Télécharger - Ville du Havre  BreezeNET B300 Quick Installation Guide  Kensington Portafolio Duo  JACK Anita.pub-patricia-j  Phonix LGL5CFB mobile phone case  Human Amylase ELISA Kit  Polaroid PLA-4260MTR User's Manual  

Copyright © All rights reserved. Failed to retrieve file