EVBUM2065 - NB3N5573DTGEVB Evaluation Board User`s Manual
Contents
1. http onsemi com 7 NB3N5573DTGEVB 1 Latest revisions shall opply to off specifications 2 Fobricote PCB in accordance with IP A 600 using supplied CAD Dato Boord data viewed from primary side layer 1 Board shall meet the requirements of UL736 with a flammability rating of 94V 0 Vendors UL logo or designotlon dote code and UL rating sholl ba locoted in etch on the secondary side of tha board lf space is limited it is permissible to lacote morkings on secondary legend 3 Moteriola 180 TG FRA or better RoHS Compliant Refer to layer stock up for copper weight ond dielectric thickness 4 Impedance Refer to layer stack up 5 Finish 00005 of Hard Gold aver 0002 Nickel E Soldermask Color Green Type LPI Sides Bottom ONLY 7 Legend sikscreent Na legend allowed on exposed lands Color White permanent organic non conductive epoxy ink B Electrical Test 100 electrical test required and verifiad ta IPC 356 netlist provided Not applicable for double sided boards 9 Worp ond twist shall not exceed 10x 010 per linear inch 10 Toberonces Finished Ploted through hole tolerance is 003 Non ploted through hole tolerance is DOM Board profile 010 11 Conductor widths shall be within 001 of supplied ortwork except for impedance signals 12 Remove all burrs and sharp adgas gt 015 ON Semiconductor and are registered trademarks of Semiconductor2. Components Industries LLC SCILLC SCILLC reserves the right to make changes without further notice to any products herein SCILLC makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does SCILLC assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation special consequential or incidental damages Typical parameters which may be provided in SCILLC data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts SCILLC does not convey any license under its patent rights nor the rights of others SCILLC products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application Buyer shall indemnify and hold SCILLC and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable att
3. gt TBD 7343 BJ2 J13 to 12 310 12 U 0 O GND m a 28 GND e s Ri a E 33 2 Ohms o R2 1 33 2 Ohms 2 y 3 4 3 GND 5 6 7 vi o C41 8 N 45 e GND 22 R7 pan a 5 o 33 2 Ohms R8 x P 33 2 Ohms o 262 gt 8 GND 9 R5 2 O nnu e m 475 Ohms o N Elm o GND o 0 Sd Roz 316 o G 12 Figure 7 Schematic http onsemi com 6 100 Ohms 100 Ohms NB3N5573DTGEVB APPENDIX 3 BILL OF MATERIALS LAMINATION STACKUP AND ASSEMBLY NOTES Table 3 BILL OF MATERIAL El EX Se e 1 du u eee AA ELECTRONICS 2pin Sullins Electronics PEC36SACN CONN HEADER 100 SINGL STR 36 POS Corp J10 J12 J13 J15 J16 Sullins Electronics STCO2SYAN CONN JUMPER SHORTING TIN Corp R1 R2 R7 R8 0402 Panasonic ECG ERJ 2RKF33R2X RES 33 2 1 16W 1 0805 SMD 8 4 R3 R4 R9 R10 0402 YAGEO AMERICA 9C04021A49R8FLHF3 RES 49 9 2 1 16W 1 0805 SMD sirli 55 475 0402 Panasonic ECG ERJ 2RKF49R9X RES 475 Q 1 16W 1 0805 SMD 10 Emerson Network 142 0701 801 CONN JACK END LAUNCH PCB 187 G Power Connectivity Solutions 11 KEYSTONE 5016 PC TEST POINT COMPACT SMT ELECTRONICS AA EST YET mm E n E TT TC S M 50 000 00809 NOT INSTALLED Not Provided Top Metal Inner 1 GND Sana 1 PIQUINO Inner 2 POWER unun Bottom Silkscreen Figure 8 Lamination Stack
4. NB3N5573DTGEVB NB3N5573DTGEVB Evaluation Board User s Manual Device Name NB3N5573DTG TSSOP 16 Board Name NB35573DTGEVB Description The NB3N3573 is a high precision low phase noise clock generator that supports PCI Express and Ethernet requirements The device takes a 25 MHz fundamental mode parallel resonant crystal and generates differential HCSL output at 25 MHz 100 MHz 125 MHz or 200 MHz clock frequencies See datasheet NB3N5573 D www onsemi com The NB3N5573DTGEVB Evaluation board is designed to provide a flexible and convenient platform to quickly program evaluate and verify the performance and operation of the NB3N5573DTG TSSOP 16 Package Case 948F device under test With the device removed this NB3N5573DTGEVB Evaluation board is designed to accept a 16 Lead TSSOP Socket M amp M Specialties Inc 1 800 892 8760 www mmspec com M amp M 50 000 00809 to permit use as an insertion test fixture ON Semiconductor http onsemi com EVAL BOARD USER S MANUAL Board Features Crystal mount source or input external clock source SMA A TSSOP 16 NB3N5573DTG device is solder mounted or the board may be adapted for insertion testing by adding a TSSOP 16 socket Separate supply connectors for VDD banana jack and Anvil Clip and GND banana jack Contents Description Board Features Board Layout Maps Test and Measurement Setup Procedures Appendix 1 Pin to Board Connection Information Ap
5. es must be used to sense the signal levels APPENDIX 1 DEVICE PIN TO BOARD CONNECTION INFORMATION see current Datasheet Table 2 DEVICE PINS TO BOARD CONNECTION Device Device Pin Board Pin Name Connection I O Description SELO LVTTL LVCMOS Frequency select input 0 Internal pullup resistor to VDD See Input datasheet Table 2 2 S1 SEL1 LVTTL LVCMOS Frequency select input 1 Internal pullup resistor to VDD See Input datasheet Table 2 X1 CLK X1 CLK Crystal Interface Oscillator Input from Crystal Single ended 25 Mhz LVTTL LVCMOS Clock Input X2 Crystal Interface Oscillator Output to drive Crystal OE OE LVTTL LVCMOS Input Output Enable Input pin to control CLKx tri states CLKx when LOW open pin defaults to HIGH 7 GND GND Ground Supply DUT and SMA GND Supply All Supply pins must be connected for proper operation CLK1b CLK1b HCSL Output HCSL Invert Output HCSL Output HCSL True Output 12 VDD VD Positive Supply Positive Supply pin All Supply pins must be connected for proper operation CLKOb CLKOb HCSL Output HCSL Invert Output CLKO CLKO HCSL Output HCSL True Output 16 GND GN Ground Supply DUT and SMA GND Supply All Supply pins must be connected for proper operation D ND Ground Supply DUT and SMA GND Supply All Supply pins must be connected for proper operation D http onsemi com NB3N5573DTGEVB APPENDIX 2 SCHEMATIC VDD SOURCE DD 1 R12 TBD 19 a z o TP 5016 jit VDD C
6. ing VDD and GND HCSL CLK CLKb CLK1 and On Test Board SS ee d n NB3N5573 CLKO 8 9828 AL 3320 HESL Driver d RL 3322 AL 3320 2082 MA ee ts eas zs 6 Time Transition Convertor Agilent 14534 250 ps or equivalent 7 Phase noise Analyzer Agilent E5052B or equivalent Step 2 Lab Set Up Procedure 1 Test Supply Setup Board and Device Power Supply Connections are shown in Table 1 VDD Banana Jack or Anvil Clip test point and GND Banana Jack and may be connected by J11 DUTGND and SMA GND CLK1b outputs are directly connected to a LOW impedance 50 Q module scope or probe per Figure 6 Both lines in an HCSL pair must be terminated Figure 6 Typical Termination for Output Driver and Device Evaluation 2 Inputs see Appendix 1 Device Pin to Board Connection Information For a Single Ended input to X1 CLK operation install a zero ohm jumper resistor at R14 Do not install R16 Do not drive X2 Use a LVCMOS Clock amplitude signal at 25 MHz which satisfies datasheet VIH and VIL to drive X1 CLK Input tr tf transition edges should be about 250 ps Use a TTC Time transition Convertor such as Agilent 14534 250 ps or equivalent if needed to slow faster edges Termination of a signal generator may be accomplished by placing a 50 Q resistor to GND at location C42 The mounted crystal does not need to be removed for S
7. ingle Ended input operation For Crystal operation use a fundamental Parallel Resonant crystal see Datasheet section on Recommended Crystal Parameters of 25 MHz The board is supplied with a thru hole 25 MHz crystal installed but alternatively has the tabs for a surface mount crystal The Crystal mount is http onsemi com 4 NB3N5573DTGEVB located on the back underside of the board and is permanently connected to the device inputs by traces Crystal load caps should be mounted from each crystal pin to GND 16 74 20 pP to fine tune frequency Device frequency is selected by LVTTL LVCMOS level inputs SELO and SELI per datasheet Table 2 Jumpers J12 SELO J13 SEL1 may be set to either VDD HI or GND LO or floated open HI to program the output frequency of operation Jumpers may be removed to drive SELO 1b directly with spec VIH or VIL levels Note SELO 1 inputs will default to VDD when left floating open High Impedance probes must be used to sense the LVTTL LVCMOS input signal levels Load cap may be added to fine tune frequency such as 15 pF to GND on both crystal pins Output current reference pin IREF Pin9 has a precision 475 Q resistor R5 installed from the output pin to GND to set the output current Inputs OE1 and OE2 may be jumpered to VEE GND for a LOW level DISABLED using 715 OE1 or J12 OE2 If floated open jumper removed pin will default to a HIGH level ENABLED High Impedance prob
8. orney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part SCILLC is an Equal Opportunity Affirmative Action Employer This literature is subject to all applicable copyright laws and is not for resale in any manner PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT N American Technical Support 800 282 9855 Toll Free ON Semiconductor Website www onsemi com Literature Distribution Center for ON Semiconductor USA Canada P O Box 5163 Denver Colorado 80217 USA Europe Middle East and Africa Technical Support Order Literature http www onsemi com orderlit Phone 303 675 2175 or 800 344 3860 Toll Free USA Canada Phone 421 33 790 2910 Fax 303 675 2176 or 800 344 3867 Toll Free USA Canada Japan Customer Focus Center For additional information please contact your local Email orderlit onsemi com Phone 81 3 5817 1050 Sales Representative EVBUM2065 D
9. pendix 2 Schematic Appendix 3 Bill of Materials Lamination Stackup Figure 1 NB3N5573DTGEVB Evaluation Board Semiconductor Components Industries LLC 2012 February 2012 Rev 1 Publication Order Number EVBUM2065 D PIN3 6 X1 CLK g OE gt 7 MAINE TO PINS NB3N5573DTGEVB BOARD LAYOUT SELO GND Jack Connector VDD Jack Connector VDD ANVIL Connector SEL 4 a y k lt CLK pa CIKI CLKI Figure 2 FRONT Board Layout Figure 3 FRONT Layer Design http onsemi com 2 NB3N5573DTGEVB SELO SELI GND Jack Connector VDD Jack Connector P Crystal PIN3 ss XI CLK jam X2 OE PIN8 TO Figure 4 BACK Board Layout Figure 5 BACK Layer Design http onsemi com 3 NB3N5573DTGEVB TEST AND MEASUREMENT SET UP AND PROCEDURE Step 1 Equipment 1 Signal Generator Agilent 33250A or HP8133 or equivalent 2 Tektronix TDSS000 Oscilloscope 3 Power Supply Agilent 6624A or AG6626A DC or equivalent 4 Digital Voltmeter Agilent 34410A or 34401 or equivalent 5 Matched Cables gt 20 GHz SMA connectors Storm or Semflex or equivalent Table 1 POWER SUPPLY CONNECTIONS Anvil Clip Device Board Banana Jack Test Point Comments VDD GND VDD GND BJ1 BJ2 SUPPLY VDD 3 3 V GND 0 0 V VEE 0 0 V Single supply operation may be accomplished by connect
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