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Curtiss-Wright / DY4 PMC-605 PMC Module Manual

1. TABLE 2 5 PMC Site 2 Pin Assignments Jn3 and Jn4 PMC Site 1 Jn3 32 Bit PCI PMC Site 1 Jn4 32 Bit PCI Pin Signal Name Signal Name Pin Pin Signal Name Signal Name Pin 1 PMC2 PCIR7 GND 2 1 PMC2 IO 1 PMC2 IO 2 2 3 GND C BE 7 4 3 PMC2 IO 3 PMC2 IO 4 4 5 C BE 6 C BE 5 6 5 PMC2 IO 5 PMC2 IO 6 6 7 C BE 4 GND 8 7 PMC2 IO 7 PMC2 IO 8 8 9 VIO PMC2 PAR64 10 9 PMC2 IO 9 PMC2 IO 10 10 11 AD 63 AD 62 12 11 PMC2 IO 11 PMC2 IO 12 12 13 AD 61 GND 14 13 PMC2 IO 13 PMC2 IO 14 14 15 GND AD 60 16 15 PMC2 IO 15 PMC2 IO 16 16 17 AD 59 AD 58 18 17 PMC2 IO 17 PMC2 IO 18 18 19 AD 57 GND 20 19 PMC2 IO 19 PMC2 IO 20 20 21 VIO AD 56 22 21 PMC2_10 21 PMC2 IO 22 22 23 AD 55 AD 54 24 23 PMC2 IO 23 PMC2 IO 24 24 25 AD 53 GND 26 25 PMC2 IO 25 PMC2 IO 26 26 27 GND AD 52 28 27 PMC2 IO 27 PMC2 IO 28 28 29 AD 51 AD 50 30 29 PMC2_10 29 PMC2 IO 30 30 31 AD 49 GND 32 31 PMC2 IO 81 PMC2 IO 32 32 33 GND AD 48 34 33 PMC2 IO 33 PMC2 IO 34 34 35 AD 47 AD 46 36 35 PMC2 IO 35 PMC2 IO 36 36 37 AD 45 GND 38 37 PMC2 IO 37 PMC2 IO 38 38 39 VIO AD 44 40 39 PMC2 IO 39 PMC2 IO 40 40 41 AD 43 AD 42 42 41 PMC2 IO 41 PMC2 IO 42 42 43 AD 41 GND 44 43 PMC2 IO 43 PMC2 IO 44 44 45 GND AD 40 46 45 PMC2 IO 45 PMC2 IO 46 46 47 AD 39 AD 38 48 47 PMC2 IO 47 PMC2 IO 48 48 49 AD 37 GND 50 49 PMC2 IO 49 PMC2 IO 50 5
2. 31 24 23 16 15 11 10 87 21 O0 Func Reg No R Bus No 0 eserved us No Dev No 1 No 0 0x10 0 0 PCI PO 010000000000000000000 000000100 01 0 address 31 11 10 0 In order to generate a Type 1 configuration cycle to access configuration space on a PCI bus on the downstream side of a PCI to PCI bridge other than a PMC 605 the bus number must be greater than zero In this instance the values are passed straight through to the PCI PO bus as follows FIGURE 4 7 Type 1 Configuration Cycle Example 31 24 23 16 15 11 10 87 21 O0 Func Reg No Reserved Bus No 1 Dev No 0 0 1 No 0 0x10 Reserved 00000001 00001 000000100 1 31 24 23 1615 11 10 0 809524 Revision D FEBRUARY 2009 4 13 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com OUTREACH PCI PMC EXPANSION SYSTEM USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING 4 14 809524 REVISION D FEBRUARY 2009 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com INSTALLATION INSTRUCTIONS INSTALLATION OVERVIEW This appendix explains how to install and configure the Outreach Expansion System The Outreach Expansion System consists of one or more Single Board Computers each equipped with a PMC 605 module one or more SVME DMV 210 Carrier Cards each equipped with one or two PMC mod ules one CWCEC PCI PO development backplane i
3. offset 1 Pi Offset 0 0x1000 X 4 offset 0 Master PMC605 CSRs 0x0000 0000 PMC605 CSRs PMC605 CSRs PCI PO Memory map Start of PCI memory Top of RAM Top of RAM 0x0030 2000 0x0020 0000 Slave PMC605 CSRs 0x6030 1000 0x0010 0000 9 0x0000 0000 Master PMC605 CSRs 0x0039 0000 0x0020 0000 Slave SBC RAM 0x0010 0000 Base addresses are as shown for the Master SBC Master SBC RAM 0x0000 0000 TRANSFERRING DATA For example to write data to the RAM on the slave SBC the destination address would be offset 1 0x100000 uint32 slavel79RamBase uint32 uint32 dev memBaseAddr 1 0x100000 uint32 ramData 0x12345678 slavel79RamBase ramData To write to one of the slave CSRs in PCI IO space uint32 slaveCsrloBase uint32 uint32 dev ioBaseAddr 1 0x100 slaveCsrloBase regData 809524 REVISIOND FEBRUARY 2009 4 11 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com OUTREACH PCI PMC EXPANSION SYSTEM USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING PCI PO CONFIGURATION SPACE ADDRESSING Table 4 2 shows the address map for the PCI PO Configuration Space TABLE 4 2 PCI PO Configuration Space Address Map PCI PO Slot No Configuration Space Address Device Num
4. TABLE 3 10 3 Slot Backplane Peripheral Slot 2 Pin No Row E Row D Row C Row B Row A 1 basecard signal basecard signal basecard signal basecard signal basecard signal 2 basecard signal basecard signal basecard signal basecard signal basecard signal 3 basecard signal basecard signal basecard signal basecard signal basecard signal 4 RST CLKO REQO GND GNTO GNTO REQO 5 INTA GND CLK1 REQ1 DESEL not connected not connected 6 GNT1 SERARB 3 IRDY TRDY 45V not connected 7 SERR IDSEL 3 PERR STOP TERMDIS 3 8 PAR FRAME CLOCKDIS 3 CBE3 CBE2 9 basecard signal basecard signal basecard signal basecard signal basecard signal 10 basecard signal basecard signal basecard signal basecard signal basecard signal 11 basecard signal basecard signal basecard signal basecard signal basecard signal 12 CBEO CBE1 ARBDIS_1 ADO AD1 13 AD2 AD3 AD4 AD5 GND 14 AD7 AD6 AD9 AD8 AD11 15 AD10 AD13 AD12 GND AD14 16 AD15 AD16 AD17 AD18 AD19 17 GND AD21 AD20 AD23 AD22 18 AD25 AD24 AD27 AD26 GND 19 AD28 AD29 AD30 AD31 basecard signal Pins carrying PMC 605 signals are cut short to prevent the PCI PO bus from being over extended when a cable is attached to the development backplane 809524 Revision D FEBRUARY 2009 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com OUTREACH PCI PMC EXPANSION SYSTEM USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING
5. ssssssseeemHeee 2 1 SVME DMV 21T0 Block Dlagtatn ze oen erit rhn px x rur car depu mex si sk a ieamkaxamd NE Ee Rap ERE 2 2 SVME DMV 210 Physical LayOU nirisan rnad niais m messem sese emen 2 5 PCI PO Development Backplane Slot Locations 3 Slot Version sssseseeeeeee 3 1 Bus Arbiter Jumper Eocatiohs onere nature eret Er een s e Eae e d ad 3 3 Clock Source J umper Locations 0 cece memes sense emen nnns 3 4 Bus Termination Jumper Locations ssssssssssee teens 3 6 Primary and Secondary PCI Buses sssssssssssesses ee eene 4 2 MGesr scdculmr 4 3 Local PCI Address Map after BAR Configuration sesssssssssseeee mme 4 7 Example of Address Map based on BAR Requirements sss 4 8 Master Slave Memory MappingS ssssssssssrsrsrssrrurrrs enna e enne 4 11 Type 0 Configuration Cycle Example 0 ccc memes 4 13 Type 1 Configuration Cycle Example ssssssssssssmem meme ener 4 13 Outreach PCI PMC Expansion System ssssssssseses ee enna nne nnns A 1 PMG Site LOCAQON E A 3 PCI PO Backplane Installation 0k eee ee EERE EEEE Ennn A 4 809524 Revision D FEBRUARY 2009 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com VII OUTREACH PCI PMC EXPANSION SYSTEM USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING VIII 809524 REvisioN D FEBR
6. OUTREACH PCI PMC EXPANSION SYSTEM USER S MANUAL REVISION HISTORY Rev By 1 JL JL A JP B JP E JP D JP Date June 2000 June 2000 November 2001 June 2002 June 2004 February 2009 CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING Description First engineering release Production release Updated Appendix B to reflect modified PCI PO backplane pins Changed cable requirements in Appendix A as product now uses standard base card cables Changed title of document to reflect new tabset Added J1 JTAG connector information in Chapter 2 Updated Chapter 3 to reflect modified PCI PO backplane pins Changed title of document to reflect new OUTREACH system name Improved the explanation on page 1 3 of JTAG support for the CPLD on the PMC 605 Clarified statement on page 1 8 to indicate that when the bus is parked it is parked on the System Slot Changed description of PCI System Reset RST signal on page 2 3 to remove dependence on the Busmode1 signal Removed the Clock Mask section on page 2 4 since the clock signal will now always be present on the PMC sites dependence on the Busmode1 signal has been removed regardless if a PMC module is installed Updated Table 2 6 to reflect pinout changes signals on PO connector pins PO A4 and P0 CA4 have been swapped that were introduced via ECO number 500000000673 This ECO allows smart PMC modules installed on the SVME DMV 210 to perform DMA cycl
7. 3 14 809524 REVISION D FEBRUARY 2009 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com SYSTEM INTEGRATION CONFIGURATION OF THE PCI PO Bus Cross Reference This section should be read in conjunction with the Intel application note Getting Started with the 21554 Embedded PCI to PCI Bridge number 278210 001 downloadable from the Intel website at http developer intel com For a complete list and description of the Foundation Firmware used with the PMC 605 refer to Appendix A of the Foundation Firmware User s Manual document number 808006 PMC 605 NoN TRANSPARENT PCI PCI BRIDGING The PMC 605 utilizes the Intel 21554 PCI PCI Bridge device The 21554 is a non transparent PCI PCI bridge that acts a gateway to other PCI subsystems It functions as a bridge between two PCI domains the local PCI bus domain and the PCI PO bus domain The 21554 creates a configuration barrier between the two PCI domains Standard hierarchical PCI configuration methods using Type 1 configuration transactions cannot be used to access the configuration space of devices on the opposite side of the 21554 Instead the internal registers of the 21554 such as the Setup Registers Base Address Registers and Address Translation Registers need to be configured before data can propagate between the two PCI domains SVME DMV 210 TRANSPARENT PCI PCI BRIDGING The SVME DMV 210 uses the Intel 2
8. 9 basecard signal basecard signal basecard signal basecard signal basecard signal 10 basecard signal basecard signal basecard signal basecard signal basecard signal 11 basecard signal basecard signal basecard signal basecard signal basecard signal 12 CBEO CBE1 ARBDIS 1 ADO AD1 13 AD2 AD3 AD4 AD5 GND 14 AD7 AD6 AD9 AD8 AD11 15 AD10 AD13 AD12 GND AD14 16 AD15 AD16 AD17 AD18 AD19 17 GND AD21 AD20 AD23 AD22 18 AD25 AD24 AD27 AD26 GND 19 AD28 AD29 AD30 AD31 basecard signal Pins carrying PMC 605 signals are cut short to prevent the PCI PO bus from being over extended when a cable is attached to the development backplane 809524 Revision D FEBRUARY 2009 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com OUTREACH PCI PMC EXPANSION SYSTEM USER S MANUAL 3 SLOT BACKPLANE PERIPHERAL SLOT 1 PIN ASSIGNMENTS The shaded cells in the table below constitute the entire PCI PO bus with some signals originating from the PMC 605 System Slot while others originate from the Peripheral Slot CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING TABLE 3 9 3 Slot Backplane Peripheral Slot 1 Pin No Row E Row D Row C Row B Row A 1 basecard signal basecard signal basecard signal basecard signal basecard signal 2 basecard signal basecard signal basecard signal basecard signal basecard signal 3 basecard signal basec
9. Caution The serial EEPROM is programmed at the factory with values shown in Table 4 1 Once the registers are preloaded they may be changed by application software simply by writing new values to the appropriate register via the PMC 605 Primary or Secondary Interfaces Do not alter the preload enable bit 7 at address O Altering the preload bit will prevent the data being preloaded which in turn prevents the Subvendor ID data being loaded Do not alter the Subvendor ID values at PROM address 0x7 8 9 and OxA Altering the Subvendor ID will prevent the Foundation Firmware from detecting the PMC 605 and cause 809524 REVISIOND FEBRUARY 2009 the PMC 605 FF W Services to be disabled 4 8 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com OUTREACH PCI PMC EXPANSION SYSTEM UsER s MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING TABLE 4 1 Serial EEPROM Factory Default Values Offset Data Description 0 0x80 Preload enable bit 7 Warning Do not change this value 1 0x00 2 0x00 3 0x00 4 0x00 Primary Class code 5 0x80 6 0x06 7 OxD4 Subvendor IDs Warning Do not change this value 8 OxD4 Subvendor IDs Warning Do not change this value 9 0x05 Subvendor IDs Warning Do not change this value A 0x06 Subvendor IDs Warning Do not change this value B 0x00 P
10. AD 46 36 35 PMC1 IO 35 PMC1 IO 36 36 37 AD 45 GND 38 37 PMC1 IO 37 PMC1 IO 38 38 39 VIO AD 44 40 39 PMC1 IO 39 PMC1 IO 40 40 41 AD 43 AD 42 42 41 PMC1 IO 41 PMC1 lO 42 42 43 AD 41 GND 44 43 PMC1 IO 43 PMC1 IO 44 44 45 GND AD 40 46 45 PMC1 IO 45 PMC1 lO 46 46 47 AD 39 AD 38 48 47 PMC1_10 47 PMC1_ 10 48 48 49 AD 37 GND 50 49 PMC1 IO 49 PMC1 IO 50 50 51 GND AD 36 52 51 PMC1 IO 51 PMC1 IO 52 52 53 AD 35 AD 34 54 53 PMC1 IO 53 PMC1 IO 54 54 55 AD 33 GND 56 55 PMC1 IO 55 PMC1 lO 56 56 57 VIO AD 32 58 57 PMC1 IO 57 PMC1 IO 58 58 59 PMC1 PCIR8 PMC1 PCIR10 60 59 PMC1_IO 59 PMC1 IO 60 60 61 PMC1 PCIR9 GND 62 61 PMC1 IO 61 PMC1 lO 62 62 63 GND PMC1 PCIR11 64 63 PMC1 IO 63 PMC1 lO 64 64 2 8 809524 REVISION D FEBRUARY 2009 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING PMC SITE 2 JN1 AND JN2 CONNECTORS SVME DMV 210 CARRIER CARD Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com TABLE 2 4 PMC Site 2 Pin Assignments Jn1 and Jn2 PMC Site 2 Jn1 32 Bit PCI PMC Site 2 Jn2 32 Bit PCI Pin Signal Name Signal Name Pin Pin Signal Name Signal Name Pin 1 PMC_TCK 12V 2 1 412V PMC TRST 2 3 GND PMC2_INTA 4 3 PMC_TMS PMC2_TDO_NC 4 5
11. PMC Site 2 Pin Assignments Jn3 and Jn4 2 cece ee mmm 2 10 VME PO Connector Pin Assignments 0 cc cece eee eee nena tenes 2 11 Pin Assignments for VME P1 Connector ssssssssssess eee eene inns 2 12 Pin Assignments for VME P2 Connector sss teeta eats 2 13 Bus Arbiter Jumper Settings 0 0 00 m strettu nern atenn sese emen ened 3 3 PCI Bus Clock Jumper Settings orent noctem rex ete rentes A ex xxxi weer caer 3 4 System Slot Termination Jumper Settings sss meme emm 3 5 2 Slot Backplane Configuration Pins sssssssssssse meme meme ene 3 7 2 Slot Backplane System Slot 0 Pin Assignments sssssssssseeememm s 3 8 2 Slot Backplane Peripheral Slot 1 Pin Assignments sss 3 9 3 Slot Backplane Configuration Pins sssssssssssse e mmememenem memes 3 10 3 Slot Backplane System Slot O sssssssssssses emen semen enemies 3 11 3 Slot Backplane Peripheral Slot 1 sssssssssememememmn emen 3 12 3 Slot Backplane Peripheral Slot 2 sss eee see enne 3 13 Serial EEPROM Factory Default Values ssssssssssessssemnemenen eene emen 4 4 PCI PO Configuration Space Address Map sssssssssmmeemem meme 4 12 809524 Revision D FEBRUARY 2009 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com OUTREACH PCI PMC EXPANSION SYSTEM USER S MANUAL CURTISS WRIGHT CONTROLS
12. xU that may or may not be installed in either PMC Site 1 or PMC Site 2 on the SVME DMV 210 Carrier Card In order to generate a complete and specific VME P2 Connector Pin Assignments table for your combination of PMC modules and SVME DMV 210 Carrier Card we have developed a pinout configurator application and included it on the Technical Documentation CD ROM for the OUTREACH PCI PMC Expansion System It allows you to generate the pin assignments table specific to your product configuration by selecting from a list of standard CWCEC PMC modules Alternatively you can load pinout information specific to a third party PMC module or one of your own design and generate the SVME DMV 210 VME P2 pin assignments table on that basis The resulting pin assignments table replaces the generic PMC signal names shown in Table 2 8 with signal names specific to the types of PMC modules installed on your SVME DMV 210 carrier card 2 14 809524 Revision D FEBRUARY 2009 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com 3 PCI PO DEVELOPMENT BACKPLANE GENERAL DESCRIPTION The PCI PO development backplane comes in 2 and 3 slot versions order numbers BPL 605 002 and BPL 605 003 The slots are labelled from left to right System Slot 0 Peripheral Slot 1 and Peripheral Slot 2 FIGURE 3 1 PCI PO Development Backplane Slot Locations 3 Slot Version J3 Peripheral Slot 2 S
13. 2009 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING PCI PO DEVELOPMENT BACKPLANE TABLE 3 1 Bus Arbiter Jumper Settings 2 Slot Backplane 3 Slot Backplane Recommended Setting Recommended Setting Set 605 in System Slot 0 as Arbiter Set 605 in System Slot 0 as Arbiter Slot 0 Connect E2 E3 Slot 0 Connect E2 E3 Slot 1 Connect E22 E23 Slot 1 Connect E13 E14 Slot 2 Connect E34 E35 Additional Possible Configurations Additional Possible Configurations Set 605 in Peripheral Slot 1 as Arbiter Set 605 in Peripheral Slot 1 as Arbiter Slot 0 Connect E1 E2 Slot 0 Connect E1 E2 Slot 1 Connect E23 E24 Slot 1 Connect E14 E15 Slot 2 Connect E34 E35 Set 605 in Peripheral Slot 2 as Arbiter Slot 0 Connect E1 E2 Slot 1 Connect E13 E14 Slot 2 Connect E35 E36 FIGURE 3 2 Bus Arbiter Jumper Locations Slot 1 Slot 0 Slot 2 Slot 1 Slot 0 Rear View 2 Slot Backplane Rear View 3 Slot Backplane BPL 605 002 BPL 605 003 The 95 pin connectors mounted on the opposite side of the above circuit car
14. Continuum Support Center web site for additional assistance http csc cwcembedded com Once registered you will have online access to additional or updated technical documentation in addition to software components etc as these items become available For Technical Support contact information go to the CWCEC web site http www cwcembedded com and click on the Contact tab This will bring up a page containing links specific to your needs http www cwcembedded com 1 88 61 html From here you can access additional topics such as Continuum Lifecycle Services Technical Support Professional Services nteroperability Repair and Warranty Software Upgrade Program Lifecycle Support Repair and Curtiss Wright Controls Embedded Computing s standard warranty provides one year Warranty coverage of parts and labor and also features Information Arepair turnaround target of 15 business days Return shipping No fault found coverage Quality Engineering services such as corrective repair reporting and failure analysis when warranted Repairs outside the scope of the warranty are performed for a fixed price for in production cards Fixed prices help customers achieve cost determinism and through streamlined administration associated with fixed prices shorten repair turn around times To obtain and prepare a Return Material Authorization RMA form click on the Repair amp Warranty link available on the Te
15. E4 E5 Slot 1 Connect E16 E17 Slot 2 Connect E32 E33 FIGURE 3 3 Clock Source Jumper Locations Slot 1 Slot 0 Slot 2 Slot 1 Slot 0 Rear View 2 Slot Backplane Rear View 3 Slot Backplane BPL 605 002 BPL 605 003 The 95 pin connectors mounted on the opposite side of the above circuit cards plug into the corresponding PO connectors on the rear of the VME backplane Note 3 4 809524 REVISION D FEBRUARY 2009 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING PCI PO DEVELOPMENT BACKPLANE SYSTEM SLOT TERMINATION JUMPER SETTINGS Each PCI PO system requires one and only one PMC 605 configured to terminate PCI bus signals TERMDIS signal connected to Ground The other PMC 605s should not be set to terminate bus signals TERMDIS signal connected to Vcc While each PMC 605 is capable of terminating bus signals the BPL 605 002 and BPL 605 003 backplanes are tracked so that only the System Slot supports signal termination TABLE 3 3 System Slot Termination J
16. EMBEDDED COMPUTING X 809524 Revision D FEBRUARY 2009 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING PREFACE PURPOSE This manual provides an overview of the OUTREACH PCI PMC Expansion System which is comprised of the PMC 605 PCI PO Bridge Module the SVME DMV 210 Carrier Card and the PCI PO Development Backplane The manual also explains how to install the system and configure the PCI PO bus AUDIENCE This document is intended for readers with a technical understanding of hardware engineering fundamentals as well as an understanding of the VMEbus PCI and CompactPCI architectures SCOPE This manual contains the following chapters Chapter 1 PMC 605 Bridge Module Describes the features functions and pin assignments of the PMC 605 Chapter 2 SVME DMV 210 Carrier Card Describes the features functions and pin assignments of the SVME DMV 210 Carrier Card Chapter 3 PCI PO Development Backplane Describes the PMC 605 s PCI PO 2 and 3 slot development backplanes Chapter 4 System Configuration Explains how to program the base address registers of the PMC 605 and lists the default contents of the EEPROM device Appendix A Installation Instructions Explains how to install the Outreach components into a system RELATED DOCUMENTS Foundation Firmware v8 0 User s Manual CWCEC document 808006 In particul
17. Ground When the arbiter function is enabled REQO and REQ1 signals are inputs to the arbiter signalling that the asserting device requests the use of the PCI PO bus After completing the arbitration process the arbiter asserts the GNTO or GNT1 signal to the requesting device The PMC 605 s arbiter function is disabled when the ARBDIS signal is connected to Vcc When the arbiter function is disabled the role of REQO and GNTO become reversed The REQO pin functions as GNTO i e becomes the Grant 0 input and the GNTO pin functions as REQO i e becomes the Request 0 output In other words REQn signals are always inputs and GNTn signals are always outputs Figure 1 4 illustrates the function of each signal when the PMC 605 s arbiter function is either enabled or disabled FIGURE 1 4 Bus Arbitration and Signal Direction Peripheral Slot 1 Peripheral Slot 2 PMC 605 21554 Arbiter Enabled ARBDIS connected to GND PMC 605 PMC 605 21554 21554 Arbiter Requester Arbiter Requester GNT Arbiter Disabled ARBDIS connected to Vcc Arbiter Disabled ARBDIS connected to Vcc Grant from Enabled Arbiter Request to Enabled Arbiter Grant from Enabled Arbiter A Caution 809524 Revision D FEBRUARY 2009 Request to Enabled Arbiter The ARBDIS signal must not be left open circuit because it is an inp
18. R P EH ERR RENS RUN 1 3 PCl PO Bridge Deschptio Necris nennti aaan e RAN EDAMPE EE DENEN SUFFR NR HMM MP a tUx AM FREUE EE deed 1 4 21554 PCI to PCI Bridge Controller 0 Hmmm sese me mems sisse 1 4 Primary and Secondary PCI BUSes incen ting preavay o ERREUR a ARNE EARR 1 4 PCI PO BUS ArbitratiO Moserin ureri aiea EE e PLN IR TEL ER EI eR cux gta ee NR IA uere exa 1 5 uei deseen 1 6 PCI PO System Slot Termination cisco cerea treten recta stem otl lare dee ed rn EP br ERI Tee dT 1 8 TMCS UO US SP X 1 8 allie O X 1 9 Serial EEPROMEs d endete pan EE E treu tbe trLU nM ILE E OE LI EM EE D TAILS 1 10 PED i i adder texas Rien EAEE dontexi ense bist de menti tee DERE ER teu ede dicla eene ted dcbet i aed 1 10 prece T E E E O E E E E E 1 10 Physical Electrical and Environmental CharacteriSticS s ssssssssrrsrrrrrrrerrnnrrnrrrnnrrnnrrreriterinn 1 11 Dirmensions s iuc ERR ARGENEMU DOR REN MERGE PM M ceded adaa p IPEEPepAPPIM PR N 1 11 Mating COnNGCtOLs UM 1 11 Electrical Characteristics cnp vi e ERR ERE MAREA PERENNE EK ERR IR at eee 1 12 Environmental Characteristies etuer rre cete mdisepekka men bre uc aT DU EM QUEE TANEET MEER RA 1 12 Connector Pini Assignments isi toed receta cce k aser pe erige E ENEIT AEE Ru Fee de seda Ru Er dire xg EE RIDE 1 13 Colinector LoCatlolis sivas cay sang cin tance sid onn E sane ct en toner t
19. Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com OUTREACH PCI PMC EXPANSION SYSTEM USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING 2 SLOT BACKPLANE SYSTEM SLOT 0 PIN ASSIGNMENTS The shaded cells in the table below constitute the entire PCI PO bus with some signals originating from the PMC 605 System Slot while others originate from the Peripheral Slot TABLE 3 5 2 Slot Backplane System Slot 0 Pin Assignments Pin No Row E Row D Row C Row B Row A 1 basecard signal basecard signal basecard signal basecard signal basecard signal 2 basecard signal basecard signal basecard signal basecard signal basecard signal 3 basecard signal basecard signal basecard signal basecard signal basecard signal 4 RST CLKO REQO GND GNTO 5 INTA GND CLK1 REQI DESEL 6 GNT1 SERARB 1 IRDY TRDY 5 V 7 SERR IDSEL_1 PERR STOP TERMDIS 1 8 PAR FRAME CLOCKDIS 1 CBE3 CBE2 9 basecard signal basecard signal basecard signal basecard signal basecard signal 10 basecard signal basecard signal basecard signal basecard signal basecard signal 11 basecard signal basecard signal basecard signal basecard signal basecard signal 12 CBEO CBE1 ARBDIS 1 ADO AD1 13 AD2 AD3 AD4 AD5 GND 14 AD7 AD6 AD9 AD8 AD11 15 AD10 AD13 AD12 GND AD14 16 AD15 AD16 AD17 AD18 AD19 17 GND AD21 AD20 AD23 AD22 18 AD25 AD24 AD27 AD26 GND 19 AD28 AD29 AD30 AD31 basec
20. com CuRTISS WRIGHT CONTROLS EMBEDDED COMPUTING PMC 605 PCI PO BRIDGE MODULE PHYSICAL ELECTRICAL AND ENVIRONMENTAL CHARACTERISTICS Figure 1 7 shows the location of the major components and the mating connectors on the PMC 605 FIGURE 1 7 PMC 605 Physical Layout Component Side Solder Side o o o o a Cl o BR e J1 O O BE po Fakta iE 8 tira pam 5 EE EH SRI es E eas E Asse E Bleje cil ci 22 d ER E 0000000000 _ E isn ts sf S E E een B SCPLD oo Em S z m S sS ck S S E 00000000
21. names shown in the above table with signal names specific to the type of PMC module installed in PMC Site 1 on your SVME DMV 210 carrier card 809524 Revision D FEBRUARY 2009 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com 2 11 OUTREACH PCI PMC EXPANSION SYSTEM USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING VME P1 CONNECTOR PIN ASSIGNMENTS The pin assignments for the VME P1 connector are shown in Table 2 7 TABLE 2 7 Pin Assignments for VME P1 Connector Pin A B C D Z 1 P1A NC1 P1B NC1 P1C NC1 45V P1Z NC1 2 P1A NC2 P1B NC2 P1C NC2 GND GND 3 P1A NC3 P1B NC3 P1C NC3 P1D NC1 P1Z NC2 4 P1A NC4 BGO P1C NC4 P1D NC2 GND 5 P1A NC5 BGO P1C NC5 P1D NC3 P1Z NC3 6 P1A NC6 BG1 P1C NC6 P1D NC4 GND 7 P1A NC7 BG1 P1C NC7 P1D NC5 P1Z NC4 8 P1A NC8 BG2 P1C NC8 P1D NC6 GND 9 GND BG2 GND P1D NC7 P1Z NC5 10 P1A NC9 BG3 P1C_NC9 P1D_NC8 GND 11 GND BG3 P1C_NC10 P1D_NC9 P1Z_NC6 12 P1A_NC10 P1B_NC4 P1C_NC11 P1D_NC10 GND 13 P1A_NC11 P1B_NC5 P1C_NC12 P1D NC11 P1Z NC7 14 P1A NC12 P1B NC6 P1C NC13 P1D NC12 GND 15 GND P1B NC7 P1C NC14 P1D NC13 P1Z NC8 16 P1A NC13 P1B NC8 P1C NC15 P1D NC14 GND 17 GND P1B NC9 P1C NC16 P1D NC15 P1Z NC9 18 P1A NC14 P1B NC10 P1C NC17 P1D NC16 GND 19 GND P1B NC11 P1C NC18 P1D NC17 P1Z NC10 20 P1A NC15 GND P1C NC19 P1D NC18 GND 21 IACK P1B NC
22. not have a pull up on it Inputs should not be left floating A The 21554 PCI to PCI Bridge device does not accept interrupts although it may generate them to either the primary bus PO side or secondary bus host processor side Any PO bus basecard through the PMC 605 card to the host processor card Caution INTERRUPTS interrupt is seen directly by the basecard as long as bit D5 of the LCSR is set to a 1 if bit D5 of the LCSR is set to a 0 default then the PO bus interrupt is withheld from the Interrupts are passed between processor cards using doorbell registers in the 21554 Interrupts from non intelligent cards use the INT line on the PCI PO bus and are buffered 809524 Revision D FEBRUARY 2009 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com 1 8 CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING PMC 605 PCI PO BRIDGE MODULE FIGURE 1 6 Inter Card Interrupt Mechanism System Slot 0 Peripheral Slot 1 Peripheral Slot 2 Basecard Basecard Basecard INTA INTA INTA PMC 605 PMC 605 PMC 605 PCI PO Bus Generating PCI PO The PMC 605 can generate an interrupt on PCI PO bus INTA using the doorbell registers Bus Interrupts in the 21554 This interrupt is routed to INTA on the host PCI bus Inter card Interrupt The PMC 605 uses the 21554 Seconda
23. on your system your PCI PO development backplane may support 2 or 3 slots Be careful not to bend any pins when attaching the PCI PO development backplane and make sure that it is correctly oriented The A1 pin is indicated on each of the PCI PO development backplane s male connectors Each A1 pin should mate with the A1 pins on the VME backplane Refer to Figure A 3 for the correct orientation FiGURE A 3 PCI PO Backplane Installation Rear View VME Backplane 4 J A 4 809524 Revision D FEBRUARY 2009 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING CONNECT BASECARD TO TERMINAL To connect the SBC to a terminal via the PO connector attach the SBC s PO cable to the PO connector on the back of the PCI PO backplane For information on additional ways to connect an SBC to a terminal i e using the front panel or P2 connector refer to the SBC s Getting Started Manual Cross Reference Terminal Settings Use the following settings for your terminal emulation software 9600 baud 8 data bits no parity 1 stop bit APPLY POWER Power on the VME chassis The SBC will power on and run its internal diagnostics which includes diag
24. settings 3 5 2 7 2 8 T TERMDIS signal 1 8 termination System Slot 1 8 transferring data 4 11 translated base registers 4 10 Type 0 Configuration Cycle example 4 13 Type 1 Configuration Cycle example 4 13 U unpacking cards A 2 809524 VERSION D FEBRUARY 2009 Guaranteed 888 88 SOURCE www artisan scientific com CuRTISS WRIGHT CONTROLS EMBEDDED COMPUTING V VME PO Connector pin assignments 2 11 VME P1 Connector pin assignments 2 12 VME P2 Connector pin assignments 2 13 809524 VERSION D FEBRUARY 2009 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com OUTREACH PCI PMC EXPANSION SYSTEM USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING l 4 809524 VERSION D FEBRUARY 2009 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com Looking for more information Artisan Visit us on the web at http www artisan scientific com for more information QUALITY INSTRUMENTATION GUARANTEED Price Quotations Drivers Technical Specifications Manuals and Documentation Artisan Scientific is Your Source for Quality New and Certified Used Pre owned Equipment Tens of Thousands of In Stock Items Fast Shipping and Delivery Equipment Demos Hundreds of Manufacturers Supported Leasing Monthly Rentals Consignment Service Center Repairs InstraView Remote Inspection Experienced Enginee
25. the PMC 605 s arbiter function has no affect on clock selection A Caution CLKDIS must not be left open circuit because it is an input to the CPLD which does not have a pull up on it Inputs should not be left floating The PMC 605 may not be detected by the host processor if this line is left open Also note that there should be only one card on the PCI PO bus that provides the clock source 809524 REvisioN D FEBRUARY 2009 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING PMC 605 PCI PO BRIDGE MODULE PCI PO Clock Table 1 1 and Figure 1 5 describe the different clock source configurations possible with the Source PMC 605 in a two or three slot backplane configuration Configurations TABLE 1 1 Clock Source Configurations Configuration Description Fully Synchronous Clock System Slot The PMC 605 in the system slot receives a 33 MHz clock source from its host card and routes it over the PCI PO bus to the other PMC 605s In this configuration the bus clock source is disabled for all PMC 605s in the system The primary and secondary buses of each PMC 605 module operate at the same clock speed Asynchronous System Slot The PMC 605 in the system slot receives a 33 MHz clock source from its host card to provide timing for its secondary side The PMC 605 s primary bus uses a clock source generated by its on board oscillator see No
26. 0 51 GND AD 36 52 51 PMC2 IO 51 PMC2 IO 52 52 53 AD 35 AD 34 54 53 PMC2 IO 53 PMC2_10 54 54 55 AD 33 GND 56 55 PMC2 IO 55 PMC2 IO 56 56 57 VIO AD 32 58 57 PMC2 IO 57 PMC2 IO 58 58 59 PMC2 PCIR8 PMC2 PCIR10 60 59 PMC2 IO 59 PMCA2 IO 60 60 61 PMC2 PCIR9 GND 62 61 PMC2 IO 61 PMC2 IO 62 62 63 GND PMC2 PCIR11 64 63 PMC2 IO 63 PMC2_lO 64 64 2 10 809524 REVISION D FEBRUARY 2009 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING VME PO CONNECTOR PIN ASSIGNMENTS The pin assignments for the VME PO connector are shown in Table 2 6 SVME DMV 210 CARRIER CARD TABLE 2 6 VME PO Connector Pin Assignments Pin A B C D E F 1 PMC1 IO 11 PMC1 IO 10 PMCA IO 9 PMC1 IO 8 PMC1 IO 7 GND 2 PMC1 IO 16 PMC1 IO 15 PMC1 IO 14 PMC1 IO 13 PMC1 IO 12 GND 3 GND PMC1 IO 18 GND GND PMC1 IO 17 GND 4 PO REQO GND PO GNTO PO CLKO PO_RST GND See Caution See Caution 5 PO_DEVSEL PO REQ1 PO CLK1 NC GND PO_INTA GND 6 5V_NC PO_TRDY PO_IRDY PO SERARB PO GNT14 GND 7 PO TERMDIS PO STOP PO PERR PO IDSEL PO SERR GND 8 CBE 2 CBE 3 PO CLOCKDIS PO_FRAME PO PAR GND 9 GND GND GND GND GND GND 10 PMC1 IO 4 PMC1 IO 2 PMC1 IO 5 PMC1 IO 3 PMC1 IO 1 GND 11 GND GND PMC1 IO 6 GND GND GND 12 PO AD 1 PO AD 0 PO ARBDIS PO CBE 1 PO CBE 0 GND 13 GND PO AD 5 PO_AD 4 PO A
27. 000 ER Bes epee ical o E E H oo 2 E E ESSE SESS Pn1 Pn3 ERE E EISE E SEE SE Ae ae a o DIMENSIONS The PMC 605 is built on a standard PCI Mezzanine Card PMC Printed Wiring Board PWB and is VITA 20 compliant MATING CONNECTORS The connectors Pn1 Pn2 Pn3 and Pn4 are compliant with IEEE P1386 809524 Revision D FEBRUARY 2009 1 11 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com OUTREACH PCI PMC EXPANSION SYSTEM USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING ELECTRICAL CHARACTERISTICS The PMC 605 is powered from the basecard s 5 V rail and operates with a steady state input voltage of 5 0 0 25 volts DC with a maximum current of 0 75 A It draws less than 4 watts of power An on board regulator provides 3 3 V for the 21554 PCI to PCI Bridge device The PMC 605 does not require 3 3 V from its host basecard ENVIRONMENTAL CHARACTERISTICS Table 1 3 shows the complete range of environmental specification limits used to categorize the ruggedization levels of CWCEC products The PMC 605 is available in ruggedization levels 0 and 200 TABLE 1 3 Card Environmental Specification Limits and Ruggedization Levels Operating Storage Operating Storage Sine Random Mechanical Temperature Temperature Humidity Humidity Vibration Vibration Shock note 1 note 4 note 5 Air Cooled 0 C to 50 C 40
28. 05 has a green power on LED that is software controllable via the Local Control and Status Register LCSR After Power up or reset the LED will be initially illuminated The LED is extinguished when the PMC605 is successfully initialized and its diagnostics passed by FF W The Local Control and Status Register LCSR is a byte wide register residing within the address space defined by the PCI Expansion ROM Base Address set within the 21554 PCI to PCI Bridge device The bit definitions of the LCSR are as described in Table 1 2 Local Control and Status Register LCSR D7 D6 D5 D4 D3 D2 D1 DO Not Used Not Used Host INTA LED Control Arbiter Mode Arbiter Clock Source Termina Enable Status tion Status Bit Name Description R W Reset D7 N A N A X X D6 N A N A X X D5 Host INTA Enable 11 Host INTA is enabled R W 0 0 Host INTA is disabled D4 LED Control 1 LED On R W 1 0 LED Off D3 Arbiter Mode 1 Serial Arbitration R As per backplane 0 Parallel Arbitration configuration D2 Arbiter Status 1 Arbiter Disabled IR As per backplane 0 Arbiter Enabled configuration D1 Clock Source 1 Clock Source Disabled IR As per backplane 0 Clock Source Enabled configuration DO Termination Status 1 Termination Disabled IR As per backplane 1 10 0 Termination Enabled configuration 809524 Revision D FEBRUARY 2009 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific
29. 0xD0000100 0x00000100 Memory 2 0xD0002000 0x00001000 Memory 121554 BRDG 0x1011 0x0046 0x00 0x80005800 0 0xD0003000 0x00001000 Memory 1 OxE0002000 0x00000100 I O 2 OxE0002400 0x00000400 I O 3 0xD0400000 0x00400000 Memory 40000000 4 6 809524 Revision D FEBRUARY 2009 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com CuRTISS WRIGHT CONTROLS EMBEDDED COMPUTING SYSTEM INTEGRATION BASE ADDRESS REGISTER INITIALIZATION Once the setup registers have been configured with the information downloaded from the serial EEPROM the FF W initializes the Base Address Registers BARs on the local secondary PCI bus based on the contents of the corresponding setup registers The local PCI address map on the SBC then appears as shown in Figure 4 3 FIGURE 4 3 Local PCI Address Map after BAR Configuration SBC Address map offset 3 0x400 offset 3 offset 2 0x100 offset 2 Start of PCI I O Offset 1 0x400000 PCI PO I O Space PMC605 CSRs PCI PO Memory Space offset 1 Offset 0 0x1000 PMC605 CSRs offset 0 Start of PCI memory 0x0000 0000 The base addresses offsets 0 1 2 and 3 are defined by FF W during initialization and are the values contained in the respective secondary BARs of the 21554 These values can be established by using the CSS function Find device For example pciDeviceStruct dev Find device I21554 DEVICE ID INTEL V
30. 11 BUSMODE2 3 3V 12 13 CLK Ground 14 13 RST BUSMODE3 14 15 Ground GNT 16 15 3 3V BUSMODE4 16 17 REQ 5V 18 17 PCI RSVD Ground 18 19 V I O AD 31 20 19 AD 30 AD 29 20 21 AD 28 AD 27 22 21 Ground AD 26 22 23 AD 25 Ground 24 23 AD 24 3 3V 24 25 Ground C BE 3 26 25 IDSEL AD 23 26 27 AD 22 AD 21 28 27 3 3V AD 20 28 29 AD 19 5V 30 29 AD 18 Ground 30 31 V I O AD 17 32 31 AD 16 C BE 2 32 33 FRAME Ground 34 33 Ground PMC RSVD 34 35 Ground IRDY 36 35 TRDY 3 3V 36 37 DEVSEL 5V 38 37 Ground STOP 38 39 Ground LOCK 40 39 PERR Ground 40 41 SDONE SBO 42 41 3 3V SERR 42 43 PAR Ground 44 43 C BE 1 Ground 44 45 V I O AD 15 46 45 AD 14 AD 13 46 47 AD 12 AD 11 48 47 Ground AD 10 48 49 AD 09 5V 50 49 AD 08 3 3V 50 51 Ground C BE 0 52 51 AD 07 PMC RSVD 52 53 AD 06 AD 05 54 53 3 3V PMC RSVD 54 55 AD 04 Ground 56 55 PMC RSVD Ground 56 57 V I O AD 03 58 57 PMC RSVD PMC RSVD 58 59 AD 02 AD 01 60 59 Ground PMC RSVD 60 61 AD 00 5V 62 61 ACK64 3 3V 62 63 Ground REQ64 64 63 Ground PMC RSVD 64 1 14 809524 REVISION D FEBRUARY 2009 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com PN3 PIN ASSIGNMENTS CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING PMC 605 PCI PO BRIDGE MODULE TABLE 1 5 Pn3 Pin Assignments Pin Signal N
31. 1154 PCI PCI Bridge device The 21154 is a transparent PCI PCI bridge and therefore the internal PCI bus of the SVME DMV 210 is a transparent extension to the PCI PO bus The 21154 does allow configuration transactions to cross the bridge In a system with more than one SBC and one or more SVME DMV 210 cards only one SBC should have responsibility for configuring the 21154 of the SVME DMV 210 card 809524 Revision D FEBRUARY 2009 4 1 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com OUTREACH PCI PMC EXPANSION SYSTEM USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING PMC 605 TERMINOLOGY The PCI local bus refers to the host SBC s PCI local bus and is connected to the secondary side of the 21554 PCI bridge The PCI PO bus connects to the PO backplane and to the primary side of the 21554 As shown in Figure 4 1 Upstream refers to the direction toward the PCI PO bus and Downstream refers to direction toward the local PCI bus FIGURE 4 1 Primary and Secondary PCI Buses Local PCI Bus Secondary I F Downstream PMC 605 Upstream Primary I F PCI PO Bus 4 2 809524 Revision D FEBRUARY 2009 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING SYSTEM INTEGRATION EXAMPLE TRANSFERRING DATA BETWEEN Two S
32. 12 P1C NC20 P1D NC19 P1Z NC11 22 IACK P1B NC13 P1C NC21 P1D NC20 GND 23 P1A NC18 GND P1C NC22 P1D NC21 P1Z NC12 24 P1A NC19 P1B NC14 P1C NC23 P1D NC22 GND 25 P1A NC20 P1B NC15 P1C NC24 P1D NC23 P1Z NC13 26 P1A NC21 P1B NC16 P1C NC25 P1D NC24 GND 27 P1A NC22 P1B NC17 P1C NC26 P1D NC25 P1Z NC14 28 P1A NC23 P1B NC18 P1C NC27 P1D NC26 GND 29 P1A NC24 P1B NC19 P1C NC28 P1D NC27 P1Z NC15 30 P1A NC25 P1B NC20 P1C NC29 P1D NC28 GND 31 12V P1B NC21 12V GND P1Z_NC16 32 5V 5V 5V 5V GND 2 12 809524 REVISION D FEBRUARY 2009 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING VME P2 CONNECTOR PIN ASSIGNMENTS The pin assignments for the VME P2 connector are shown in Table 2 8 SVME DMV 210 CARRIER CARD TABLE 2 8 Pin Assignments for VME P2 Connector Pin A B C D Z 1 PMC2 IO 02 5V PMC2 IO 01 PMC1 IO 19 PMC1 IO 20 2 PMC2 IO 04 GND PMC2 IO 03 PMC1 IO 21 GND 3 PMC2 IO 06 NC PMC2 IO 05 PMC1 IO 23 PMC1 IO 22 4 PMC2 IO 08 NC PMC2 IO 07 PMC1 IO 24 GND 5 PMC2 IO 10 NC PMC2 IO 09 PMC1 IO 26 PMC1 IO 25 6 PMC2 IO 12 NC PMC2 IO 11 PMC1 IO 27 GND 7 PMC2 IO 14 NC PMC2 IO 13 PMC1 IO 29 PMC1 IO 28 8 PMC2 IO 16 NC PMC2 IO 15 PMC1 IO 30 GND 9 PMC2 IO 18 NC PMC2 IO 17 PMC1 IO 32 PMC1 IO 31 10 PMC2 IO 20 NC PMC2
33. 2 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING INSTALL PMC 605 ON BASECARD Cross Reference The PMC 605 should only be installed on an SBC in the PMC slot that routes the PMC 605 s P4 connector to the SBC s PO connector The PMC 605 will not operate correctly if installed in a different basecard PMC slot position FIGURE A 2 PMC Site Location Single Board Computer Sy EUM PMC 605 P2 PO P1 In most cases the PMC 605 will have already been mounted on the basecard at the factory to ensure proper mechanical and thermal mating connections If necessary refer to the Application Note PMC Module Mounting Instructions document 808335 for information about installing your PMC 605 on the basecard INSERT CARDS IN CHASSIS Warning Turn the power off before inserting or removing cards from the VME chassis Failure to do so could damage the card circuitry or cause personal injury About Card Insertion Force Many SBCs employ 160 pin 5 row connectors for the P1 and P2 interfaces Proper mating of these connectors with the VME backplane requi
34. 605 Board PMC 605 Custom Custom w Computer Computer VO Card VOCard 9 26 2 a vd r D VMEbus PCI PO Bus Figure 1 2 shows a functional block diagram of the PMC 605 809524 Revision D FEBRUARY 2009 1 1 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com OUTREACH PCI PMC EXPANSION SYSTEM USER S MANUAL O U n OT c CuRTISS WRIGHT CONTROLS EMBEDDED COMPUTING FIGURE 1 2 PMC 605 Functional Block Diagram Intel 21554 re Embedded PCI Bridge Controller seems Y P Secondary PCI Bus Primary PCI Bus 0 ca Primary Bus P PCI Int gt c Arbiter Functions B u Ye Ss aA a aa GPO a Configuration Settings S Serial EEPROM Bridge 4 Control Pri D bell Int Configuration A Y Y m PCI Int CPLD JTAG Status System Controller Functions LED L Arbiter and Local Control and Status E JTAG Register 3 3V 5V Regulator t 3 3V 809524 Revision D FEBRUARY 2009 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING PMC 605 PCI PO BRIDGE MODULE SUMMARY OF FEATURES Clock Speed Bus Arbitration PCI Bus Clock Synchronous and Asynchronous Operation System Slot Termination P
35. 88 88 SOURCE www artisan scientific com OUTREACH PCI PMC EXPANSION SYSTEM USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING PCI PO Backplane Pin Assignments 0 memes e esie e emen enemies 3 7 2 Slot Backplane Configuration Pins cccece eee mme emen nne eese nn 3 7 2 Slot Backplane System Slot 0 Pin Assignments cece eee eee eene 3 8 2 Slot Backplane Peripheral Slot 1 Pin Assignments ssssssssssssssseenmm meme 3 9 3 Slot Backplane Configuration Pins ccc memes enmememe ses enn 3 10 3 Slot Backplane System Slot 0 Pin Assignments sssssssssssssemmmmmmnee 3 11 3 Slot Backplane Peripheral Slot 1 Pin Assignments sse 3 12 3 Slot Backplane Peripheral Slot 2 Pin Assignments sess mme 3 13 4 System rip Mr c H m 4 1 Configuration of the PCI PO BUS emen sene emen iere emen e enne ee nem nenne een nnn 4 1 PMC 605 Non Transparent PCI PCI Bridging sss Imm enn 4 1 SVME DMV 210 Transparent PCI PCI Bridging csssssse emm 4 1 PMG 605 Terminology mE 4 2 Example Transferring Data Between Two SBCSs ss s sssssssrssrutrrretrn arrn neste enini nns 4 3 Serial EEPROM CornfligU taLbiOn cec ettet eek ER E Ware RERUEM UH D Dep Kd xl RARE AR AGERE 4 3 SVME DMV 179 GPM Map Command With PMC 605 Installed sssseeene 4 5 Base Address Register nitialiZation 0 0c mn mense
36. AD19 50 51 GND AD21 52 53 AD20 AD23 54 55 AD22 AD25 56 57 AD24 AD27 58 59 AD26 GND 60 61 AD28 AD29 62 63 AD30 AD31 64 1 16 809524 REVISION D FEBRUARY 2009 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING PMC 605 PCI PO BRIDGE MODULE J1 TEST JTAG PORT TABLE 1 7 J1 Test JTAG Port Pin Assignments Pin Signal 1 TCK Xilinx amp Bridge 2 TDI Xilinx 3 TMS Xilinx amp Bridge 4 TDO Xilinx connects to TDI of Bridge 5 45V 6 TRST Bridge 7 TDO Bridge SVME DMV 179 On an SVME DMV 179 Single Board Computer the PMC 605 would typically be installed in SBC PO Pin the PMCI interface in order to access the 179 s PO connector Assignments FIGURE 1 9 Location of PMC 605 on a SVME DMV 179 SVME DMV 179 9 P1 PMC 605 PO Table 1 8 describes the PO connector of an SVME DMV 179 with a PMC 605 mounted in the PMC1 interface The shaded boxes represent PCI signals provided by the PMC 605 when plugged into the System Slot on the PCI PO backplane EPEE EEEE EEEE EEEE EN HE E EEEE EEEE EEEE EE Pee Ee a ae a ea a a a PHIL NA LLL C 809524 Revis
37. BCs This section provides an example showing how a system containing two adjacent PowerPC Single Board Computers SBCs fitted with PMC 605s may be configured to transfer data between the RAM of the two SBCs over the PO bus The cards are fitted in slot 1 and 2 of the PO bus The card in slot 1 is designated Master and the card in slot 2 is designated Slave FIGURE 4 2 Example System Ey Jy x Single Custom Custom amp PMC 605 Board PMC 605 PMC PMC i E Computer Computer VO Card I O Card i 9 o a z 7 a a ES T at 1L NV PCI PO Bus SERIAL EEPROM CONFIGURATION The PMC 605 is provided with a serial EEPROM to enable configuration of certain registers at power up or reset This serial EEPROM is programmed at the factory with default values to provide a basic configuration for the 21554 configuration registers These default values can be changed using the PMC 605 service Pmc605 writeSeeprom After the 21554 completes a chip reset it initiates a serial EEPROM read in order to perform a configuration register preload Among other things the preload is used to select the size and type of downstream and upstream address windows by preloading the address setup configuration registers Note A
38. C carrier card that allows users to expand the number of PMC modules that can be driven from one processor card by acting as a host for up to two on board PMC modules The SVME DMV 210 uses the PCI PO bus to provide additional data bandwidth between cards where the VMEBus alone cannot meet the current demand The SVME DMV 210 is used in conjunction with the PMC 605 to expand the PCI bus of a processor card a Single Board Computer or SBC through the PO connector Two SVME DMV 210 cards can be supported by a single SBC expanding the available PMC support to a total of five modules FIGURE 2 1 Sample Application of SVME DMV 210 Carrier Card Single PMC 605 Custom Custom Custom Custom eo e Board PMC pmc 9 PMC mue 28 Computer VO Card VOCad SO VO Card VO Card zo oe as EE 28 So 20 e n Se a 4 l T VMEbus PCI PO Bus 809524 REVISION D FEBRUARY 2009 2 1 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com OUTREACH PCI PMC EXPANSION SYSTEM USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING SUMMARY OF FEATURES Bridge Device PMC Support Interrupts Dimensions Power Requirements Ruggedization Levels 2 2 PMC1 Clock a PMC1 IO PMC 1 Primary i Seconda
39. C to 85 C 0 to 95 0 to 95 N A N A N A Level 0 inlet 4 cfm air non condensing non condensing flow note 6 Air Cooled 20 Cto 65 C 40 Cto 85 C 0 to 100 0 to 100 N A 0 02 g Hz 30 g peak Level 50 inlet 4 cfm air non condensing non condensing 20 2000 Hz half sine flow note 6 pulse 11 ms dura tion Air Cooled 40 C to 71 C 55 C to 85 C 0 to 100 0 to 100 10gpeak 0 04 g Hz 30 g peak Level 100 inlet 4 cfm air non condensing non condensing 15 2000 Hz 15 2000 Hz half sine flow note 6 note 2 pulse 11 ms dura tion Conduction 40 to71 C 55 C to 85 C 0 to 100 0 to 100 10g 0 01 g Hz 40 g peak Cooled card edge non condensing non condensing 15 2000 Hz 15 2000 Hz half sine Level 100 temperature note 3 pulse 11 ms dura tion Conduction 55 C to 85 C 62 C to 125 C 0 to 100 0 to 100 10g 0 1 g2 Hz 40 g peak Cooled card edge non condensing condensing 15 2000 Hz 15 2000 Hz half sine Level 200 temperature note 3 pulse 11 ms dura tion Notes 1 12 1 ooRomNm Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com All levels based on a sweep duration of ten minutes per axis each of three mutually perpendicular axis Displacement limited to 0 10 inches D A from 15 to 44 Hz Displacement limited to 0 436 inches D A from 15 to 21 Hz 60 minutes per axis each of three mutually perpendicular axes Three hits per direction per axis
40. D 3 PO AD 2 GND 14 PO AD 11 PO AD S8 PO AD 9 PO AD 6 PO ADI 7 GND 15 PO AD 14 GND PO AD 12 PO AD 13 PO AD 10 GND 16 PO AD 19 PO AD 18 PO AD 17 PO AD 16 PO AD 15 GND 17 PO AD 22 PO AD 23 PO AD 20 PO AD 21 GND GND 18 GND PO AD 26 PO AD 27 PO AD 24 PO AD 25 GND 19 RESERVED PO_AD 31 PO_AD 30 PO AD 29 PO AD 28 GND A Caution The signals assigned to PO A4 and PO C4 in Table 2 6 have been swapped in this edition of the manual to accurately reflect the current version of the SVME DMV 210 hardware This change was introduced via ECO 500000000673 Table 2 6 shows generic signal names e g PMC1 IO 11 for the PMC module that may or may not be installed in PMC Site 1 on the SVME DMV 210 Carrier Card In order to generate a complete and specific VME PO Connector Pin Assignments table for your combination of PMC module and SVME DMV 210 Carrier Card we have developed a pinout configurator application and included it on the Technical Documentation CD ROM for the OUTREACH PCI PMC Expansion System It allows you to generate the pin assignments table specific to your product configuration by selecting from a list of standard CWCEC PMC modules Alternatively you can load pinout information specific to a third party PMC module or one of your own design and generate the SVME DMV 210 VME PO pin assignments information on that basis The resulting pin assignments table replaces the generic PMC signal
41. DUUM cinacmliaguind A E E E RURTQR MER REN RR TUE A 6 NAG OX l 1 VI 809524 REVISION D FEBRUARY 2009 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING LisT OF FIGURES Figure 1 1 Figure 1 2 Figure 1 3 Figure 1 4 Figure 1 5 Figure 1 6 Figure 1 7 Figure 1 8 Figure 1 9 Figure 2 1 Figure 2 2 Figure 2 3 Figure 3 1 Figure 3 2 Figure 3 3 Figure 3 4 Figure 4 1 Figure 4 2 Figure 4 3 Figure 4 4 Figure 4 5 Figure 4 6 Figure 4 7 Figure A 1 Figure A 2 Figure A 3 Sample Application of PMC 605 PCI PO Bridge Module sss 1 1 PMC 605 Functional Block Diagram sssssssse ene emen rens 1 2 Primary and Secondary PCI Buses ssssssssssseses een eee eee teens 1 4 Bus Arbitration and Signal Direction ssssssssssseee meme memes eren 1 5 PCI PO Clock Source Configurations ssssssssssssseeememmememe nemen eene 1 7 Inter Card Interrupt Mechanism ssssssssesen mme memememe sese eene 1 9 PMC 605 Physical Layout 5r eror reete be ences teins em ERR E UE EXER E E DE FRE RU do 1 11 Connector LOCATIONS i kt RRREREERATXRMEERUR RARRUR KDE IMSEMINE RMR E EM A 1 13 Location of PMC 605 on a SVME DMV 179 ssssssssssmmemememememe seen 1 17 Sample Application of SVME DMV 210 Carrier Card
42. Diagram 809524 Revision D FEBRUARY 2009 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING SVME DMV 210 CARRIER CARD PCI PO BRIDGE DESCRIPTION The SVME DMV 210 uses the Intel 21154 PCI to PCI transparent bridge to connect the PMC modules to the PCI PO bus The bridge has a 32 bit 25 MHz minimum 33 MHz typical Initiator Target PCI primary interface and a 64 bit 25 MHz minimum 33 MHz typical Initiator Target PCI secondary interface It is fully compliant with the PCI Specification Revision 2 1 and supports parity checking on both the PCI PO bus and the PMC bus The use of the 21154 PCI to PCI bridge decouples the PMC PCI bus from the PO PCI bus This will permit concurrent bus activity to occur on the PO bus and PMC PCI bus All devices on the SVME DMV 210 are accessible in the PCI configuration space as well as the PCI memory space and or the PCI I O space For more information on the 21154 bridge device refer to the Intel 21154 PCI to PCI Bridge Datasheet available for download at http developer intel com Cross Reference CONFIGURATION The 21154 configuration registers are initialized from the PCI PO bus by the host processor The 21154 responds to both Type 0 and Type 1 confi
43. E DMV 210 CARRIER CARD Pin Signal Name Signal Name Pin 4 Pin Signal Name Signal Name Pin 4 1 PMC TCK 12V 2 1 412V PMC TRST 2 3 GND PMC1_INTA 4 3 PMC_TMS PMC1_TDO_NC 4 5 PMC1_INTB PMC1_INTC 6 5 PMC_TDI GND 6 7 PMC1 BUSMODE 5V 8 7 GND PMC1 PCIR5 8 9 PMC1_INTD PMC1 PCIR1 10 9 PMC1 PCIR3 PMC1 PCIR6 10 11 GND PMC1 PCIR2 12 11 43 3V 3 3V 12 PMC1_BUSMODE2 13 PMC1_CLK GND 14 13 PMC1_RST GND BUSMODE3 14 15 GND PMC1_GNT 16 15 3 3V GND BUSMODE4 16 17 PMC1_REQ 5V 18 17 PMC1_PCIR4 GND 18 19 VIO AD 31 20 19 AD 30 AD 29 20 21 AD 28 AD 27 22 21 GND AD 26 22 23 AD 25 GND 24 23 AD 24 3 3V 24 25 GND C BE 3 26 25 PMC1_IDSEL AD 23 26 27 AD 22 AD 21 28 27 3 3V AD 20 28 29 AD 19 5V 30 29 AD 18 GND 30 31 VIO AD 17 32 31 AD 16 C BE 2 f 32 33 PMC1 FRAME GND 34 33 GND PMC1 PMCR3 34 35 GND PMC1_IRDY 36 35 PMC1_TRDY 3 3V 36 37 PMC1_DEVSEL 5V 38 37 GND PMC1_STOP 38 39 GND PMC1_LOCK 40 39 PMC1_PERR GND 40 41 PMC1 SDONE PMC1_SBO 42 41 43 3V PMC1 SERR 42 43 PMC1 PAR GND 44 43 C BE 1 GND 44 45 VIO AD 15 46 45 AD 14 AD 13 46 47 AD 12 AD 11 48 47 GND AD 10 48 49 AD 09 5V 50 49 AD 08 3 3V 50 51 GND C BE 0 52 51 AD 07 PMC1_PMCR4 52 53 AD 06 AD 05 54 53 3 3V PMC1_PMCR5 54 55 AD 04 GND 56 55 PMC1 PMCR1 GND 56 57 VIO AD 03 58 57 PMC1_PMCR2 PMC1_PMCR6 58 59 AD 02 AD 01 60 59 GND PMC1 PMCR7 60 61 AD 00 5
44. ELL VIVUNT AP 60S S RAAR J2 Peripheral Slot 1 J1 System Slot 0 3 1 809524 Revision D FEBRUARY 2009 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com OUTREACH PCI PMC EXPANSION SYSTEM USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING BACKPLANE JUMPER CONFIGURATIONS Bus arbiter clock source and signal termination settings are configured via jumpers on the PCI PO Development Backplanes part numbers BPL 605 002 and BPL 605 003 Refer to Table 3 1 to Table 3 3 for details jumper configuration of your PCI PO development backplane may cause your The additional configurations included here are for reference purposes only Adjusting the PMC 605 modules to malfunction Caution Some jumpers on the BPL 605 002 and BPL 605 003 are reserved for future use In particular on the BPL 605 002 jumpers E 10 through E 15 are reserved while on the BPL 605 003 jumpers E 10 E 11 and E 12 as well as E 22 through E 27 are reserved Bus ARBITER JUMPER SETTINGS Each PCI PO system requires one and only one PMC 605 configured as bus arbiter ARBIS signal connected to Ground The other PMC 605s should have bus arbitration disabled ARBIS signal connected to Vcc While each PMC 605 is capable of acting as the bus arbiter the BPL 605 002 and BPL 605 003 backplanes are tracked so that only the System Slot supports a bus arbiter 3 2 809524 Revision D FEBRUARY
45. ENDOR ID 0 amp dev Offset 0 uint32 dev memBaseAddr 0 Secondary CSR Memory BAR Offset 1 uint32 dev memBaseAddr 1 Upstream Memory 1 BAR Offset 2 uint32 dev ioBaseAddr 0 Secondary CSR I O BAR Offset 3 uint32 dev ioBaseAddr 1 Upstream I O BAR Alternatively the Secondary PCI Configuration register defaults can be examined using the GPM command PCID For example to display the contents of the PMC 605 Configuration registers in the PMC slot 1 on a SVME DMV 179 At the GPM prompt type 809524 Revision D FEBRUARY 2009 4 7 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com OUTREACH PCI PMC EXPANSION SYSTEM USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING pcid 0 b The following message will be displayed 40000000 pcid 0 b Configuration Header for bus 0x00 device OxOB function 0x0 Configuration base address 2 0x80005800 device ID 0x0046 vendor ID Ox1011 status regiser 0x0290 command register 0x0007 class code 0x06 sub class code 0x80 programing interface 2 0x00 revision ID 0x01 BIST 0x00 header type 0x00 latency timer 0x00 cache line size 0x08 base address 0 0xD0003000 base address1 OxE0002001 base address 2 OxE0002401 base address3 0xD0400000 base address 4 0x00000000 base address5 0x00000000 cardBus CIS pointer 0x00000000 subsystem ID 0x0605 subsystem vendor ID 0xD4D4 expansi
46. ER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING PCI JTAG TEST SIGNALS The SVME DMV 210 does not support PCI JTAG test signals PMC Bus MODE SIGNALS The PMC Busmode 4 2 signals are tied to the appropriate logic level on the SVME DMV 210 the Busmodel signal from each PMC site is connected to the on board CPLD e the Busmode2 signal is connected to 3 3V e the Busmode3 and Busmode4 signals are connected to Ground The presence of a PMC module is indicated by the assertion of the Busmodel signal of the corresponding PMC site 2 4 809524 Revision D FEBRUARY 2009 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com CuRTISS WRIGHT CONTROLS EMBEDDED COMPUTING SVME DMV 210 CARRIER CARD PHYSICAL ELECTRICAL AND ENVIRONMENTAL CHARACTERISTICS Figure 2 3 shows the location of the major components and the mating connectors on the SVME DMV 210 FiGURE 2 3 SVME DMV 210 Physical Layout j P1 PMC Site 1 1 PMC Site 2 P2 5 DIMENSIONS The SVME DMV 210 is built on a standard VMEbus 6U Printed Wiring Board PWB and is VITA 20 compliant MATING CONNECTORS The connecto
47. IO 19 PMC1 IO 33 GND 11 PMC2 IO 22 NC PMC2 IO 21 PMC1 IO 35 PMC1 IO 34 12 PMC2 IO 24 GND PMC2 IO 23 PMC1 IO 36 GND 13 PMC2 IO 26 5V PMC2 IO 25 PMC1 IO 38 PMC1 IO 37 14 PMC2 IO 28 NC PMC2 IO 27 PMC1 IO 39 GND 15 PMC2 IO 30 NC PMC2 IO 29 PMC1 IO 41 PMC1 IO 40 16 PMC2 IO 32 NC PMC2 IO 31 PMC1 IO 42 GND 17 PMC2 IO 34 NC PMC2 IO 33 PMC1 IO 44 PMC1 IO 43 18 PMC2 IO 36 NC PMC2 IO 35 PMC1 IO 45 GND 19 PMC2 IO 38 NC PMC2 IO 37 PMC1 IO 47 PMC1 IO 46 20 PMC2 IO 40 NC PMC2 IO 39 PMC1 IO 48 GND 21 PMC2 IO 42 NC PMC2 IO 41 PMC1 IO 50 PMC1 IO 49 22 PMC2 IO 44 GND PMC2 IO 43 PMC1 IO 51 GND 23 PMC2 IO 46 NC PMC2 IO 45 PMC1 IO 53 PMC1 IO 52 24 PMC2 IO 48 NC PMC2 IO 47 PMC1 IO 54 GND 25 PMC2 IO 50 NC PMC2 IO 49 PMC1 IO 56 PMC1 IO 55 26 PMC2 IO 52 NC PMC2 IO 51 PMC1 IO 57 GND 27 PMC2 IO 54 NC PMC2 IO 53 PMC1 IO 59 PMC1 IO 58 28 PMC2 IO 56 NC PMC2 IO 55 PMC1 IO 60 GND 29 PMC2 IO 58 NC PMC2 IO 57 PMC1 IO 62 PMC1 IO 61 30 PMC2 IO 60 NC PMC2 IO 59 PMC1 IO 63 GND 31 PMC2 IO 62 GND PMC2 IO 61 GND PMC1 lO 64 32 PMC2 IO 64 5V PMC2 IO 63 5V GND 809524 REVISION D FEBRUARY 2009 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com 2 13 OUTREACH PCI PMC EXPANSION SYSTEM USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING Table 2 8 shows generic PMC module signal names e g PMC2 1O 02 for the PMC modules
48. Looking for more information Artisan Visit us on the web at http www artisan scientific com for more information QUALITY INSTRUMENTATION GUARANTEED Price Quotations Drivers Technical Specifications Manuals and Documentation Artisan Scientific is Your Source for Quality New and Certified Used Pre owned Equipment Tens of Thousands of In Stock Items Fast Shipping and Delivery Equipment Demos Hundreds of Manufacturers Supported Leasing Monthly Rentals Consignment Service Center Repairs InstraView Remote Inspection Experienced Engineers and Technicians on staff in our Remotely inspect equipment before purchasing with our State of the art Full Service In House Service Center Facility Innovative InstraView website at http www instraview com We buy used equipment We also offer credit for Buy Backs and Trade Ins Sell your excess underutilized and idle used equipment Contact one of our Customer Service Representatives today Talk to a live person 888 88 SOURCE 888 887 6872 Contact us by email sales artisan scientific com Visit our website http www artisan scientific com Document Number 809524 Version D Date February 2009 OUTREACH PCI PMC EXPANSION SYSTEM UsER s MANUAL Curtiss Wright Controls Embedded Computing 333 Palladium Drive Ottawa Ontario Canada K2V 1A6 613 599 9199 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com
49. O connector is isolated for each slot The GND signal is common across all slots The REQO line on the System Slot pin C4 is driven by the REQO line on Peripheral Slot 1 pin A4 The REQ1 line on the System Slot pin B5 is driven by the REQ1 line on Peripheral Slot 2 pin A4 The GNTO line on the System Slot pin A4 drives GNTO line on Peripheral Slot 1 pin C4 The GNT1 line on the System Slot pin E6 drives the GNT1 line on Peripheral Slot 2 pin C4 809524 Revision D FEBRUARY 2009 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING PCI PO DEVELOPMENT BACKPLANE 3 SLOT BACKPLANE SYSTEM SLOT 0 PIN ASSIGNMENTS The shaded cells in the table below constitute the entire PCI PO bus with some signals originating from the PMC 605 System Slot while others originate from the Peripheral Slot TABLE 3 8 3 Slot Backplane System Slot 0 Pin No Row E Row D Row C Row B Row A 1 basecard signal basecard signal basecard signal basecard signal basecard signal 2 basecard signal basecard signal basecard signal basecard signal basecard signal 3 basecard signal basecard signal basecard signal basecard signal basecard signal 4 RST CLKO REQO GND GNTO 5 INTA GND CLK1 REQI DESEL 6 GNT1 SERARB 1 IRDY TRDY 5 V 7 SERR IDSEL_1 PERR STOP TERMDIS 1 8 PAR FRAME CLOCKDIS 1 CBE3 CBE2
50. PMC 605 terminates signals when placed in the PCI PO backplane s System Slot It does not terminate signals when placed in a Peripheral Slot See System Slot Termination Jumper Settings on page 3 5 of this manual for information on configuring signal termination The PMC 605 terminates signals as required for a PCI System Slot Controller when the TERMDIS signal is connected directly to Ground The System Slot termination is disabled settings when using the PMC 605 with the PCI PO Development Backplane The term System Slot Controller refers to a PMC 605 when it is configured to provide PCI bus arbitration on the PCI PO distribute the PCI Bus clock across the backplane and provide Cross Reference termination of specific signals In a multi slot system the bus is normally parked on the System slot by the arbiter when the arbiter assigns a card default ownership of the bus This ensures that the majority of the signals on the bus are driven but reduces power requirements by removing the necessity of each card having pull ups Some signals however need to be free for any card to assert These signals cannot be left floating or driven and hence the System Controller provides the pull ups terminations for these signals On the PMC 605 these signals are FRAME TRDY IRDY DEVSEL STOP SERR PERR and INTA The TERMDIS signal must not be left open circuit because it is an input to the CPLD which does
51. PMC2_INTB PMC2_INTC 6 5 PMC_TDI GND 6 7 PMC2_BUSMODE1 5V 8 7 GND PMC2 PCIR5 8 9 PMC2 INTD PMC2 PCIR1 10 9 PMC2 PCIR3 PMC2 PCIR6 10 11 GND PMC2 PCIR2 12 11 3 3V 3 3V 12 PMC2_BUSMODE2 13 PMC2_CLK GND 14 13 PMC2_RST GND BUSMODES 14 15 GND PMC2_GNT 16 15 3 3V GND BUSMODE4 16 17 PMC2_REQ 5V 18 17 PMC2_PCIR4 GND 18 19 VIO AD 31 20 19 AD 30 AD 29 20 21 AD 28 AD 27 22 21 GND AD 26 22 23 AD 25 GND 24 23 AD 24 3 3V 24 25 GND C BE 3 26 25 PMC2 IDSEL AD 23 26 27 AD 22 AD 21 28 27 3 3V AD 20 28 29 AD 19 5V 30 29 AD 18 GND 30 31 VIO AD 17 32 31 AD 16 C BE 2 f 32 33 PMC2 FRAME GND 34 33 GND PMC2 PMCRS3 34 35 GND PMC2_IRDY 36 35 PMC2_TRDY 3 3V 36 37 PMC2_DEVSEL 5V 38 37 GND PMC2_STOP 38 39 GND PMC2_LOCK 40 39 PMC2_PERR GND 40 41 PMC2 SDONE PMC2_SBO 42 41 3 3V PMC2_SERR 42 43 PMC2_PAR GND 44 43 C BE 1 GND 44 45 VIO AD 15 46 45 AD 14 AD 13 46 47 AD 12 AD 11 48 47 GND AD 10 48 49 AD 09 5V 50 49 AD 08 3 3V 50 51 GND C BE 0 52 51 AD 07 PMC2_PMCR4 52 53 AD 06 AD 05 54 53 3 3V PMC2_PMCR5 54 55 AD 04 GND 56 55 PMC2 PMCR1 GND 56 57 VIO AD 03 58 57 PMC2 PMCR2 PMC2 PMCR6 58 59 AD 02 AD 01 60 59 GND PMC2_PMCR7 60 61 AD 00 45V 62 61 PMC2_ACK64 3 3V 62 63 GND PMC2_REQ64 64 63 GND PMC2_PMCR8 64 809524 REvisloN D FEBRUARY 2009 2 9 OUTREACH PCI PMC EXPANSION SYSTEM USER S MANUAL PMC SITE 2 JN3 AND JN4 CONNECTORS CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING
52. Register s Secondary Configuration Space offset Set Base address for Master SBC s RAM using Downstream I O or Memory 1 BAR PciConfigWrite busNo deviceNo functionNo 0x58 0x0 sizeof uint32 Set Base address for Master s PMC605 CSRs in PCI PO memory space PciConfigWrite busNo deviceNo functionNo 0x50 0x300000 sizeof uint32 Set Base address for Masters s PMC605 CSRs in PCI PO I O space PciConfigWrite busNo deviceNo functionNo 0x54 0x00000001 sizeof uint32 Enable the Master PMC605 to respond to PCI cycles and ability to act as master on the PCI PO bus PciConfigWrite busNo deviceNo functionNo 0x44 0x0007 sizeof uint16 Now the Primary BARS on the slave PMC 605 have to be set using the PMC 605 service Pmc605 pciPOConfigWrite The parameters to access a PMC 605 s configuration registers in slot 2 of the PO bus are as follows busNo 0 deviceNo 1 functionNo 0 RegNo Register s Primary Configuration Space offset Set Base address for Slave SBC s RAM using Downstream I O or Memory 1 BAR Pmc605 pciPOConfigWrite busNo deviceNo functionNo 0x18 0x100000 sizeof uint32 Set Base address for Slaves s PMC605 CSRs in PCI PO memory space Pmc605 pciPOConfigWrite busNo deviceNo functionNo 0x10 0x301000 sizeof uint32 Set Base address for Masters s PMC605 CSRs in PCI PO I O space Pmc605_pciPOConfigWrite busNo deviceNo functionNo 0x14 0x00000101 sizeof uint32 Enable the Sl
53. UARY 2009 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING LisT OF TABLES Table 1 1 Table 1 2 Table 1 3 Table 1 4 Table 1 5 Table 1 6 Table 1 7 Table 1 8 Table 2 1 Table 2 2 Table 2 3 Table 2 4 Table 2 5 Table 2 6 Table 2 7 Table 2 8 Table 3 1 Table 3 2 Table 3 3 Table 3 4 Table 3 5 Table 3 6 Table 3 7 Table 3 8 Table 3 9 Table 3 10 Table 4 1 Table 4 2 Clock Source Configuratlohs icon treten Eher ea derer dne ENE le cR re P Ae ede 1 7 Local Control and Status Register LCSR ssssssssssseemem mnn 1 10 Environmental Specification Limits and Ruggedization Levels aseene 1 12 Pril Pn2 PincAsSIgDOSnES site exert eer ded ud Rc d RR tear ERR URNA RUE CR UR RE RE 1 14 Pn3 Pin Assignments eer eie terii b meri Pert ser le gerade EEE EEEE NE b AR Res 1 15 Ph4 Pin Assignments i eire IE RETE E REA aden V RR MP RR UIS 1 16 J1 Test JTAG Port Pin Assignments cceceee eee ee eee memes ene 1 17 Sample SVME DMV 179 PO Connector Pin Assignments sss 1 18 Environmental Specification Limits and Ruggedization Levels ssssssssssesss 2 6 PMC Site 1 Pin Assignments Jn1 and Jn2 eee eee tented 2 7 PMC Site 1 Pin Assignments Jn3 and Jn4 ssssssssssseeme mme 2 8 PMC Site 2 Pin Assignments Jn1 and Jn2 0 cece eee nent aed 2 9
54. V 62 61 PMC1_ACK64 3 3V 62 63 GND PMC1_REQ64 64 63 GND PMC1_PMCR8 64 809524 Revision D FEBRUARY 2009 2 7 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com OUTREACH PCI PMC EXPANSION SYSTEM USER S MANUAL PMC SITE 1 JN3 AND JN4 CONNECTORS CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING TABLE 2 3 PMC Site 1 Pin Assignments Jn3 and Jn4 PMC Site 1 Jn3 32 Bit PCI PMC Site 1 Jn4 32 Bit PCI Pin Signal Name Signal Name Pin Pin Signal Name Signal Name Pin 1 PMC1 PCIR7 GND 2 1 PMC1 IO 1 PMC1 IO 2 2 3 GND C BE 7 4 3 PMC1 IO S PMC1 IO 4 4 5 C BE 6 C BE 5 6 5 PMC1 IO 5 PMC1 lO 6 6 7 C BE 4 GND 8 7 PMC1 IO 7 PMC1 IO 8 8 9 VIO PMC1 PAR64 10 9 PMC1 IO 9 PMC1 IO 10 10 11 AD 63 AD 62 12 11 PMC1 IO 11 PMC1_10 12 12 13 AD 61 GND 14 13 PMC1 IO 13 PMC1 IO 14 14 15 GND AD 60 16 15 PMC1 IO 15 PMC1 IO 16 16 17 AD 59 AD 58 18 17 PMC1_10 17 PMC1_10 18 18 19 AD 57 GND 20 19 PMC1 IO 19 PMC1 IO 20 20 21 VIO AD 56 22 21 PMC1 IO 21 PMC1 IO 22 22 23 AD 55 AD 54 24 23 PMC1_10 23 PMC1_10 24 24 25 AD 53 GND 26 25 PMC1 IO 25 PMC1 IO 26 26 27 GND AD 52 28 27 PMC1 IO 27 PMC1 IO 28 28 29 AD 51 AD 50 30 29 PMC1_10 29 PMC1_10 30 30 31 AD 49 GND 32 31 PMC1 IO 31 PMC1 IO 32 32 33 GND AD 48 34 33 PMC1 IO 33 PMC1 IO 34 34 35 AD 47
55. ame Signal Name Pin 1 PCI RSVD GND 2 3 GND CBE7 4 5 CBE6 CBE5 6 7 CBE4 GND 8 9 V I O PAR64 10 11 AD 63 AD 62 12 13 AD 61 GND 14 15 GND AD 60 16 17 AD 59 AD 58 18 19 AD 57 GND 20 21 V I O AD 56 22 23 AD 55 AD 54 24 25 Ad 53 GND 26 27 GND AD 52 28 29 AD 51 AD 50 30 31 AD 49 GND 32 33 GND AD 48 34 35 AD 47 AD 46 36 37 AD 45 GND 38 39 V I O AD 44 40 41 AD 43 AD 42 42 43 AD 41 GND 44 45 GND AD 40 46 47 AD 39 AD 38 48 49 AD 37 GND 50 51 GND AD 36 52 53 AD35 AD34 54 55 AD33 GND 56 57 V I O AD32 58 59 PCI RSVD PCI RSVD 60 61 PCI RSVD GND 62 63 GND PCI RSVD 64 809524 REVISION D FEBRUARY 2009 1 15 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com OUTREACH PCI PMC EXPANSION SYSTEM USER S MANUAL PN4 PIN ASSIGNMENTS CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING TABLE 1 6 Pn4 Pin Assignments Pin Signal Name Signal Name Pin 4 1 RST PCLKO 2 3 REQO GND 4 5 GNTO INTA 6 7 GND PCLK1 8 9 REQ1 DEVSEL 10 11 GNT1 SERARB 12 13 IRDY TRDY 14 15 5 V SERR 16 17 IDSEL PERR 18 19 STOP TERMDIS 20 21 PAR FRAME 22 23 CLOCKDIS CBE3 24 25 CBE2 CBEO 26 27 CBE1 ARBDIS 28 29 ADO AD1 30 31 AD2 AD3 32 33 AD4 AD5 34 35 GND AD7 36 37 AD6 AD9 38 39 AD8 AD11 40 41 AD10 AD13 42 43 AD12 GND 44 45 AD14 AD15 46 47 AD16 AD17 48 49 AD18
56. ar refer to Appendix A of this document It describes the Foundation Firmware extensions specific to the PMC 605 Getting Started with the 21554 Embedded PCI to PCI Bridge Application Note Intel Corporation document 278210 001 Available for download from website at http developer intel com 809524 Revision D FEBRUARY 2009 XI Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com OUTREACH PCI PMC EXPANSION SYSTEM USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING CONVENTIONS USED IN THIS MANUAL Typographic Conventions This document and the accompanying documents in the documentation package use various icon conventions and abbreviations to make the documents clearer and easier to read These conventions cover typography for such elements as sample software code and keystrokes signal meanings and graphical elements for important information such as warnings or cautions Table 1 lists the typographical conventions used in documents contained in this documentation package TABLE 1 Typographical Conventions Item Keystrokes File Names Directory Names Monitor Displays Firmware Code Signal Conventions XII Convention Example Keys are listed as they appear on most keyboards Type lt Ctrl Alt C gt to return to the previous menu surrounded by marks Combinations of key Type Esc to exit strokes appear within a single se
57. ard signal 3 8 Pins carrying PMC 605 signals are cut short to prevent the PCI PO bus from being over extended when a cable is attached to the development backplane 809524 REVISION D FEBRUARY 2009 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING PCI PO DEVELOPMENT BACKPLANE 2 SLOT BACKPLANE PERIPHERAL SLOT 1 PIN ASSIGNMENTS The shaded cells in the table below constitute the entire PCI PO bus with some signals originating from the PMC 605 System Slot while others originate from the Peripheral Slot TABLE 3 6 2 Slot Backplane Peripheral Slot 1 Pin Assignments Pin No Row E Row D Row C Row B Row A 1 basecard signal basecard signal basecard signal basecard signal basecard signal 2 basecard signal basecard signal basecard signal basecard signal basecard signal 3 basecard signal basecard signal basecard signal basecard signal basecard signal 4 RST CLKO REQO GND GNTO GNTO REQO 5 INTA GND CLK1 REQ1 DESEL not connected not connected 6 GNT1 SERARB 2 IRDY TRDY 5 V not connected 7 SERR IDSEL 2 PERR STOP TERMDIS 2 8 PAR FRAME CLOCKDIS 2 CBE3 CBE2 9 basecard signal basecard signal basecard signal basecard signal basecard signal 10 basecard signal basecard signal basecard signal basecard signal basecard signal 11 basecard sig
58. ard signal basecard signal basecard signal basecard signal 4 RST CLKO REQO GND GNTO GNTO REQO 5 INTA GND CLK1 REQ1 DESEL not connected not connected 6 GNT1 SERARB 2 IRDY TRDY 5 V not connected 7 SERR IDSEL 2 PERR STOP TERMDIS 2 8 PAR FRAME CLOCKDIS 2 CBE3 CBE2 9 basecard signal basecard signal basecard signal basecard signal basecard signal 10 basecard signal basecard signal basecard signal basecard signal basecard signal 11 basecard signal basecard signal basecard signal basecard signal basecard signal 12 CBEO CBE1 ARBDIS 1 ADO AD1 13 AD2 AD3 AD4 AD5 GND 14 AD7 AD6 AD9 AD8 AD11 15 AD10 AD13 AD12 GND AD14 16 AD15 AD16 AD17 AD18 AD19 17 GND AD21 AD20 AD23 AD22 18 AD25 AD24 AD27 AD26 GND 19 AD28 AD29 AD30 AD31 basecard signal 3 12 Pins carrying PMC 605 signals are cut short to prevent the PCI PO bus from being over extended when a cable is attached to the development backplane 809524 REVISION D FEBRUARY 2009 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING PCI PO DEVELOPMENT BACKPLANE 3 SLOT BACKPLANE PERIPHERAL SLOT 2 PIN ASSIGNMENTS The shaded cells in the table below constitute the entire PCI PO bus with some signals originating from the PMC 605 System Slot while others originate from the Peripheral Slot
59. ary PCI bus runs through the P4 connector to the PO connector on the basecard The Primary PCI bus runs at 33 MHz and supports 32 bit addressing and data transfers The Secondary PCI bus is connected to the host basecard s local PCI bus The Secondary PCI bus runs at 33 MHz and supports 64 bit addressing and data transfers FIGURE 1 3 Primary and Secondary PCI Buses PMC 605 m Module i VME PCI Bridge Backplane PCI PO bus Secondary PCI Bus Local Host PCI Bus Pn3 Pn4 Host Basecard Primary PCI Bus PO 1 4 809524 Revision D FEBRUARY 2009 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING PMC 605 PCI PO BRIDGE MODULE PCI PO Bus ARBITRATION Arbitration Scheme PCI PO Bus Arbiter Enable Disable System Slot 0 The PMC 605 can act as the bus arbiter for the PCI PO bus A CPLD provides the arbitration functions the arbitration functions built into the 21554 bridge chip are not used The PMC 605 uses a parallel arbitration scheme in which each card on the PCI PO bus is free to request the use of the bus at any time The PMC 605 acting as bus arbiter grants the bus on a first come first serve basis The PMC 605 acts as the PCI PO bus arbiter when the ARBDIS signal is connected directly to
60. ave PMC605 to respond to PCI cycles and ability to act as master on the PCI PO bus Pmc605_pciPOConfigWrite busNo deviceNo functionNo 0x04 0x0007 sizeof uint16 TRANSLATED BASE REGISTER CONFIGURATION Finally before any memory transactions are forwarded across the 21554 the translated base registers must be configured The translation registers define how the 21554 translates addresses decoded by the 21554 s Primary BARs to somewhere pertinent on the secondary side in this case SBC s RAM and similarly how the 21554 translates addresses decoded by the 21554 s secondary side to a pertinent address on the PCI PO bus Primary side In this example each SBC is responsible for configuring its own PMC 605 Translated Base Registers via the secondary interface but this could equally be done by any PCI PO bus master via the Primary interface 809524 Revision D FEBRUARY 2009 4 9 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com OUTREACH PCI PMC EXPANSION SYSTEM USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING Cross Reference 4 10 Your SBC s Programmer s Reference Manual provides details of the System Memory Map showing the address of the RAM as seen by a local PCI bus Master The parameters to set up the translated base registers are as follows Set the Downstream 1 0 or Mem 1 Translated Base Register to translate addresses deco
61. ber 1 0x800000000 0 2 0x400000000 1 3 0x200000000 2 4 0x100000000 3 PCI PO slots are numbered from left to right when viewed from the front of the chassis That is Slot 1 is the left most slot in the PCI PO backplane The address bit set to one represents the PCI IDSEL signal For configuration Type 0 cycles the upper 21 address bits of the configuration address select the slot and the lower 11 bits determine the function number of the device and register offset within that function for the selected slot Refer to the PCI specification 2 2 for an explanation of Type 0 and 1 configuration cycles ADDRESSING EXAMPLE Suppose you wish to read the Primary CSR and Downstream Memory 0 Base Address Register BAR on the PMC 605 in slot 2 Using the PMC 605 service Pmc605 pciPoConfigRead you would construct the address as follows include pmc605 h include dy4std h uint32 busNo 0 uint32 deviceNo 1 uint32 funcNo 0 4 12 809524 REVISION D FEBRUARY 2009 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING SYSTEM INTEGRATION uint32 regData uint32 regOffset 0x10 regData Pmc605_pciPOConfigRead busNo deviceNo funcNo regOffset sizeof uint32 The above code translates to a PCI PO address as shown in Figure 4 6 FIGURE 4 6 Type 0 Configuration Cycle Example
62. ch Support Contact page identified above XIV 809524 Revision D FEBRUARY 2009 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com 1 PMC 605 PCI PO BRIDGE MODULE GENERAL DESCRIPTION The PMC 605 PCI PO Bridge Module is a single width PMC module that extends the local PCI bus of its host Single Board Computer SBC out to the SBC s PO connector This enables the SBC to communicate with other similarly equipped cards in the VMEbus system over a high speed PCI bus referred to as the PCI PO bus in this manual The PMC 605 performs such functions as Expanding the number of PMC modules attached to a processor card single board computer or digital signal processor Interconnecting multiple processor cards via a high speed PCI secondary backplane Providing a private PCI data path to custom 1 0 cards Figure 1 1 shows a sample application of the PMC 605 The two SBCs use the PMC 605 to access each others shared PCI resources while the SVME DMV 210 Carrier Card extends the PCI bus of each single board computer with additional I O capabilities FIGURE 1 1 Sample Application of PMC 605 PCI PO Bridge Module j SZ a wz WZ Single Single 2 Board FME
63. configuration 1 7 physical characteristics 1 4 2 5 PMC 605 block diagram 1 2 general description 1 1 J1JTAG Port pin assignments 1 17 Pn1 Pn2 pin assignments 1 14 Pn3 pin assignments 1 15 Pn4 pin assignments 1 16 Pmc605 pciPOConfigWrite 4 9 Pmc605 writeSeeprom service 4 3 4 5 Pn1 pin assignments 1 14 Pn2 pin assignments 1 14 Pn3 pin assignments 1 15 Pn4 pin assignments 1 16 power requirements l 2 Artisan Scientific Quality Instrumentation CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING PMC 605 1 12 preload enable bit 4 3 Primary PCI bus 1 4 R random vibration 1 12 2 6 reset 1 9 Reset signal 1 9 ruggedization levels PMC 605 1 12 SVME DMV 210 2 2 S sample application 1 1 Secondary PCI bus 1 4 serial EEPROM 1 3 1 10 configuration 4 3 factory default values 4 4 sign on message A 5 sine vibration 1 12 2 6 slot location A 4 storage humidity 1 12 2 6 storage temperature 1 12 2 6 subsystem vendor ID 1 10 subvendor ID 4 3 SVME DMV 179 PO Connector pinouts 1 18 SVME DMV 210 block diagram 2 2 interrupt handling 2 2 2 3 JTAG support 2 4 SVME DMV 210 PMC Site 1 pin assignments Jn1 and Jn2 pin assignments Jn3 and Jn4 SVME DMV 210 PMC Site 2 pin assignments Jn1 and Jn2 2 9 pin assignments Jn3 and Jn4 2 10 synchronous clock System Slot configuration 1 7 synchronous operation 1 3 system controller SYSCON A 4 System Slot Controller 1 8 System Slot termination 1 3 1 8 System Slot Termination jumper
64. ctors mounted on the opposite side of the above circuit cards plug into the corresponding PO connectors on the rear of the VME backplane 3 6 809524 REvisioN D FEBRUARY 2009 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING PCI PO DEVELOPMENT BACKPLANE PCI PO BACKPLANE PIN ASSIGNMENTS 2 SLOT BACKPLANE CONFIGURATION PINS In a 2 slot backplane each slot has 4 configuration pins that are independent of other slots These control arbiter functions clock source line termination and bus arbitration TABLE 3 4 2 Slot Backplane Configuration Pins Line Description Clock Source The card in System Slot 0 drives a clock out on pins D4 CLKO and C5 CLK1 The peripheral card takes its clock from its D4 pin System Slot pin C5 connects to the peripheral slot s D4 pin Reset The Reset line is common on pin E4 and should only be driven from Slot 0 Interrupts The interrupt line INTA is common on pin E5 5 V Rail The 5 V rail pin A6 that goes to each PO connector is isolated for each slot Ground The GND signal is common across all slots Request Line The REQO line on the System Slot 0 pin C4 is driven by the REQO line on Peripheral Slot 1 pin A4 Grant Line The GNTO line on the System Slot 0 pin A4 drives the GNTO line on Peripheral Slot 1 pin C4 809524 REVISION D FEBRUARY 2009 3 7 Artisan
65. d when a subject being discussed is addressed in depth by another more authoritative document Cross references are also used for document chapters and sections The warning icon indicates procedures in the manual that if not carried out or if carried out incorrectly could cause physical injury electrical damage to equipment or a non recoverable corruption of data Warnings include instructions for preventing such damage Please observe warning icons and read the accompanying text completely before carrying out the procedure The caution icon indicates non catastrophic incidents complex practices or procedures which if not observed could result in damage to the hardware Cautions include specific instructions for avoiding or minimizing these incidents The note icon highlights exceptions and special information Tips provide extra information on the subject matter This could include hints about how to use your current CWCEC card to its maximum potential 809524 Revision D FEBRUARY 2009 XIII Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com OUTREACH PCI PMC EXPANSION SYSTEM USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING TECHNICAL SUPPORT INFORMATION To Access CWCEC Technical Support If you are unable to resolve installation or configuration related difficulties using the guidance provided in this document contact Technical Support or check out the
66. ded by the Primary Downstream I O or Mem 1 BAR to RAM addresses starting at 0x100000 on the SBC PciConfigWrite busNo deviceNo functionNo 0x98 0x100000 sizeof uint32 Set the Upstream I O or Memory 1 Translated Base Register to translate addresses decoded by the Secondary Upstream I O or Mem 1 BAR to PCI PO I O base address 0x0 PciConfigWrite busNo deviceNo functionNo 0xA4 0x0 sizeof uint32 Set the Upstream Memory 1 Translated Base Register to translate addresses decoded by the Secondary Upstream Memory 1 BAR to PCI PO memory base address 0x0 PciConfigWrite busNo deviceNo functionNo 0xA8 0x0 sizeof uint32 809524 Revision D FEBRUARY 2009 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com CuRTISS WRIGHT CONTROLS EMBEDDED COMPUTING SYSTEM INTEGRATION ADDRESS MAP FOR LOCAL PCI AND PO BUSES Master SBC Address map With all the necessary registers now configured the address map for the local PCI and PO buses appears as shown in Figure 4 5 FIGURE 4 5 Master Slave Memory Mappings PCI PO I O ma E Slave SBC Address map offset 3 0x400 PCI PO I O Space PCI PO I O Space offset 3 gt offset 2 0x100 offset 2 Pi PMC605 CSRs PMC605 CSRs Start of PCI 1 0 Offset 1 0x400000 gt 0x0000 0200 PCI PO Memory Space PCI PO Memory Space Slave PMC605 CSRs 0x0000 0100
67. dentified as either BPL 605 002 or BPL 605 003 one standard VME development chassis FIGURE A 1 Outreach PCI PMC Expansion System 809524 REVISIOND FEBRUARY 2009 A 1 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING OUTREACH PCI PMC EXPANSION SYSTEM USER S MANUAL UNPACK CARDS The cards use components that are sensitive to electrostatic discharges They must be kept in their conductive package until just before the installation begins Remove the cards from their protective package only at a grounded workstation while A wearing an approved grounding wrist strap Avoid touching any metal contacts on the cards static discharge can damage integrated circuits Caution CONFIGURE CARDS AND PCI PO DEVELOPMENT BACKPLANE Refer to your SBC s Getting Started Manual for information selecting jumper settings and configuring your SBCs The PMC 605 and the SVME DMV 210 have no user definable jumper settings Configuration is done via the PCI PO development backplane The PCI PO development backplane identified as either BPL 605 002 or BPL 605 003 has jumper settings that configure the bus arbiter the arbitration scheme the system clock and the system controller functions Refer to Chapter 3 for information on modifying the Cross Reference jumper settings 809524 REvisioN D FEBRUARY 2009 A
68. ds plug into the corresponding PO connectors on the rear of the VME backplane Note 809524 REVISIOND FEBRUARY 2009 3 3 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com OUTREACH PCI PMC EXPANSION SYSTEM USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING PCI BUS CLOCK JUMPER SETTINGS Each PCI PO system requires one and only one PMC 605 configured to provide a clock source CLKDIS signal connected to Ground The other PMC 605s should have clock output disabled CLKDIS signal connected to Vcc While each PMC 605 card is capable of providing a clock source the BPL 605 002 and BPL 605 003 backplanes are tracked so that only the System Slot can provide a clock source Note TABLE 3 2 PCI Bus Clock Jumper Settings 2 Slot Backplane 3 Slot Backplane Recommended Setting Recommended Setting 605 in Slot 0 providing clock source 605 in Slot 0 providing clock source Slot 0 Connect E5 E6 Slot 1 Connect E19 E20 Slot 0 Connect E5 E6 Slot 1 Connect E16 E17 Slot 2 Connect E31 E32 Additional Possible Configurations 605 in Slot 1 providing clock source Additional Possible Configurations 605 in Slot 1 providing clock source Slot 0 Connect E4 E5 Slot 1 Connect E20 E21 Slot 0 Connect E4 E5 Slot 1 Connect E17 E18 Slot 2 Connect E31 E32 605 in Slot 2 providing clock source Slot 0 Connect
69. es back to the host card Added note on page 3 2 that summarizes which E jumpers on the BPL 605 002 and BPL 605 008 are reserved Improved Figure 3 2 Figure 3 3 and Figure 3 4 to indicate the correct orientation of the 2 or 3 Slot Development Backplanes and the location of the E jumper straps Corrected errors in Table 3 7 specifically the descriptions of Clock Source Request Line and Grant Line Corrected error in Configure Master s Primary BARs on page 4 9 The Command Register is located at 0x44 not 0x40 as was previously shown Improved Figure A 3 to clarify how the BPL 605 002 and BPL 605 003 Develop ment Backplane modules need to be oriented for correct operation Updated to correct SVME DMV 210 PO pinout table see Table 2 6 on page 2 11 Updated to correct SVME DMV 210 P2 pinout table see Table 2 8 on page 2 13 Updated to address CR 26124 See Install PMC 605 on Basecard on page A 3 for corrected cross reference to document number 808335 809524 VERSION D FEBRUARY 2009 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING COPYRIGHT NOTICE The information in this document is subject to change without notice and should not be construed as a commitment by Curtiss Wright Controls Inc While reasonable precautions have been taken Curtiss Wright Controls Inc assumes no responsibility for any errors tha
70. figured by the fitting of optional zero ohm resistors through the host SBC JTAG interface If the optional zero ohm resistors are not fitted the CPLD must be programmed through an on board header Note that the Intel 21554 is not included as part of the JTAG loop The PMC 605 is available in air cooled and conduction cooled versions LED The PMC 605 has a green software controllable power on LED More information on the PMC 605 features listed above is provided in the following sections Note 809524 Revision D FEBRUARY 2009 1 3 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com OUTREACH PCI PMC EXPANSION SYSTEM USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING PCI PO BRIDGE DESCRIPTION 21554 PCI TO PCI BRIDGE CONTROLLER The PMC 605 uses the Intel 21554 Embedded PCI to PCI Bridge device The 21554 is a non transparent PCI to PCI bridge designed to connect multiple processor domains enabling the host basecard to independently configure and control the local subsystem The 21554 responds to Type 0 configuration cycles For information about this device refer to the Intel s Getting Started with the 21554 Embedded PCI to PCI Bridge Application Dos Note document 278210 001 Manuals and data sheets on the 21554 can be downloaded Cross Reference from Intel s website at http developer intel com PRIMARY AND SECONDARY PCI BUSES The PMC 605 s Prim
71. gnostics A 5 dimensions 1 11 2 5 doorbell registers 1 8 E electrical characteristics 1 12 2 6 environmental specifications PMC 605 1 12 SVME DMV 210 2 6 F factory default values 4 3 features PMC 605 1 3 SVME DMV 210 2 2 initial screen message A 5 input voltage 1 12 inserting or removing cards A 3 installation instructions A 1 INTA signal 1 9 interrupt mechanism 1 9 J JTAG support 1 3 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com OUTREACH PCI PMC EXPANSION SYSTEM USER S MANUAL jumper configurations 3 2 L LED 1 3 1 10 LED behaviour during power up A 5 Local Control and Status Register LCSR 1 10 Local PCI Address Map 4 7 Master Slave memory mappings 4 11 maximum current PMC 605 1 12 SVME DMV 210 2 2 2 6 mechanical shock 1 12 2 6 O on board regulator 1 12 operating humidity 1 12 2 6 operating temperature 1 12 2 6 Outreach PCI PMC Expansion System A 1 P PO pin assignments 1 17 parallel arbitration scheme 1 3 parity checking 2 3 PCI Bus Clock 1 3 PCI Bus Clock jumper settings 3 4 PCI RST signal 2 3 PCI secondary backplane 1 1 PCI System Reset 2 3 PCI PMC carrier card 2 1 PciConfigWrite 4 9 PCI PO backplane installation A 4 PCI PO Bus clock 1 6 configuration 4 1 definition 1 1 PCI PO Bus Arbiter enable disable 1 5 PCI PO configuration space 4 12 PCI PO development backplane 3 1 A 2 Peripheral Slot clocking
72. guration cycles to configure the bridge itself and the PMC modules installed on the SVME DMV 210 Carrier Card PCI SIGNAL ENVIRONMENT The 21154 is a 43 3 V device that is 5 V tolerant Both the PCI PO bus and the PMC bus can use either 43 3 V or 5 V independently of each other The SVME DMV 210 incorporates electronic bus switches that permit either 3 3V or a 5V PMC modules to be added with no need to change the configuration 3 3V or 5V PMC modules can be installed in either PMC module site on the SVME DMV 210 in any combination PCI SYSTEM RESET RST The PCI RST signal from the PCI PO bus is used as the master reset for the SVME DMV 210 A low logic level on this signal resets the 21154 bridge and both PMC sites Reset signals are routed to the reset input of the primary PCI interface of the 21154 bridge The secondary reset output from the 21154 bridge is connected to the CPLD and individual resets are routed to the two PMC sites PCI INTERRUPTS The SVME DMV 210 can generate a single interrupt INTA to the processor card The source can be any of the four PCI interrupts from either of the two PMC modules The processor card can determine the source of the PCI interrupt by interrogating the individual PMC modules installed on the SVME DMV 210 809524 Revision D FEBRUARY 2009 2 3 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com OUTREACH PCI PMC EXPANSION SYSTEM US
73. ion D FEBRUARY 2009 1 17 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com OUTREACH PCI PMC EXPANSION SYSTEM UsER s MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING TABLE 1 8 Sample SVME DMV 179 PO Connector Pin Assignments Pin No Row E Row D Row C Row B Row A 1 CH1DSR CH1RXD CH1TXD ENET UPT2 ENET UPT1 2 PIO 9 PJTAG TMS GND ENET_TXD ENET_TXD 3 PIO 10 CARDFAIL CRESET ENET RXD ENET RXD 4 RST PCLKO REQO GND GNTO 5 INTA GND PCLK1 REQ1 DESEL 6 GNT1 SERARB IRDY TRDY 5 V T SERR IDSEL PERR STOP TERMDIS 8 PAR FRAME CLOCKDIS CBE3 CBE2 9 PIO 7 PIO 5 PIO 3 PIO 1 PIO 0 10 PIO 8 PIO 6 PIO 4 PIO 2 Reserved 11 JTAG TCK JTAG TDI JTAG TRST JTAG TDO Reserved 12 CBEO CBE1 ARBDIS ADO AD1 13 AD2 AD3 AD4 AD5 GND 14 AD7 AD6 AD9 AD8 AD11 15 AD10 AD13 AD12 GND AD14 16 AD15 AD16 AD17 AD18 AD19 17 GND AD21 AD20 AD23 AD22 18 AD25 AD24 AD27 AD26 GND 19 AD28 AD29 AD30 AD31 PIO 11 1 18 To support PMC 605 I O via the SVME DMV 179 PO connector the SVME DMV 179 must be ordered from the factory with support for either I O Mode 1 or I O Mode 4 809524 Revision D FEBRUARY 2009 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com 2 SVME DMV 210 CARRIER CARD GENERAL DESCRIPTION The SVME DMV 210 is a PCI PM
74. itia e qualis EAE OERA ut taies EEEN 1 13 Pnl Pn2 Pin Assightrments cete Ee nrbes red vi Piero reel Miter ndi rore ede Ter b UE dE ad 1 14 Pan Pil ASSIgOETSTIES mannanna E a E EEEE a a REE EIU IET ELI RUE Ae 1 15 Ph PI ASSIGNMENtS aiieieo a eva RENTE sias ror DEEE ep be eta lace t Fax de d Ta mie Dd huis 1 16 IL Ec TAG POR MM r 1 17 2 SVME DMV 210 Carrier Card tne ere ceu creen ndaakadaxasusun mnnn 2 1 Gerieral Descripti ni ipo Pr RE UR ee RU iM EH EE E ERE AT UEM E M NUR URN EE 2 1 SUMMALY OF Feat reS Em 2 2 PCl PO Bridge DescriptiOri cu tex etd n ERR RR EORURRRRERUNARERESEREKENTENEMODDIMERUMRN NE NRANN RUDI 2 3 COLI fIQUEBblOD aci chee ass ecangacemca eto ameet untdulit i MEE eese bs ies 2 3 PCI Sigfial ENViIrOniMe nt iii loe cines i e rre Ld wn aw eCard Wi Ek de a d ecu 2 3 PCI System Reset RST ccccccccce cee eee ene eene eese enean enne een nnn nn nn enn nnn 2 3 PCI Tnterr pts ien casae esc teen eet nih Pad ma ade E d re eade A ER EUER RP RR IRR LEUTE 2 3 PCI Nu CREDO I LR E PER 2 4 PMC Bus Mode Sigtials ie veshnin er eto are epe ira dada ait DEEE ante ilies 2 4 Physical Electrical and environmental Characteristics 0 cc cece eee ee eee eee eee ene nme 2 5 DIMENSIONS ccce E E mand usta re E E aac cxtat te eetie E E 2 5 Mating ConnecCtOls excu ERR RI RE ERR EREIEQUUNR E Racdsd salar thas nad PAN D XIX 2 5 Electrical Characteristics cic iecisrsesvaneeth wip exe same nece Dexi
75. m nenne ene 4 7 Primary BAR Conflgutratlon i2 rbeco ebrei FU He rere ener ba gale Fee Uer e peer EA de PERPE Ln ERE 4 8 Translated Base Register Configuration cece cece emen eene nemen nnns 4 9 Address Map for Local PCI and PO Buses sssssssssssssese meses eene nennen 4 11 Tirarisferring Iata eben eter tenuta urpis Rd canne cti Rer clita pss Rse Si REP ix dvd kin 4 11 PCI PO Configuration Space Addressing sssssssssssese memes mememe sene eem ene 4 12 Addressing EXaltmiple ios ener pie Ee a ONAA EOE NEA KU ee tasamca rane 4 12 A Installation INSiIruCiOnS mee A 1 installation OVErVieW wisiciansisiciies vis Pe RR ERRARE EEERERARRA ERR ARERRRMR YEEREERRU FEY RR vada eed RERTRAN RECEN ERR EE NIA VS A 1 Unpack Cards sarsies EEUU A 2 Configure Cards and PCI PO Development Backplane ssssssssseee mme A 2 Install PMC 605 on Basea raosira enn nn NREN EEEN eee nn eese nnn A 3 Insert Cards Ini Chassls uie e deccm ree ree d eto Erei nE E eel pese der Poco pide ele A 3 Attach the PCI PO Development Backplane sssssssssses meme ener A 4 Connect Basecard to Terminali iraniana nann aaaea hee dre EUR E RE R EA RR LAE dar PRIX RR FR ds A 5 AD Ply ROWE Toresen exeuntis uer EEN r E E Dm out ae teem geese dee td led A 5 Display Initial Screen Message 0 ccc niunie oi u aaa KEEN EEA ESEE EENAA eese A 5 Install BS Pescsccsiniaseti aun pe ERR DRE RA
76. nal basecard signal basecard signal basecard signal basecard signal 12 CBEO CBE1 ARBDIS 1 ADO AD1 13 AD2 AD3 AD4 AD5 GND 14 AD7 AD6 AD9 AD8 AD11 15 AD10 AD13 AD12 GND AD14 16 AD15 AD16 AD17 AD18 AD19 17 GND AD21 AD20 AD23 AD22 18 AD25 AD24 AD27 AD26 GND 19 AD28 AD29 AD30 AD31 basecard signal Pins carrying PMC 605 signals are cut short to prevent the PCI PO bus from being over extended when a cable is attached to the development backplane 809524 Revision D FEBRUARY 2009 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com OUTREACH PCI PMC EXPANSION SYSTEM USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING 3 SLOT BACKPLANE CONFIGURATION PINS TABLE 3 7 Line Clock Source Reset Interrupts 5 V Rail Ground Request Line Grant Line 3 10 In a 3 slot backplane each slot has 4 configuration pins that are independent of other slots These control arbiter functions clock source line termination and bus arbitration 3 Slot Backplane Configuration Pins Description The card in System Slot 0 drives a clock out on pins D4 CLKO and C5 CLK1 System Slot pin C5 con nects to Peripheral Slot 1 pin D4 System Slot D4 connects to Peripheral Slot 2 pin D4 The Reset line is common on pin E4 and should only be driven from Slot 0 The interrupt line INTA is common on pin E5 The 5 V rail pin A6 that goes to each P
77. neslons ex bx EE eua E nun n t nates aet ERG 2 6 Environmental Characteristics ener ie S exe RERO MR ER FER KA ERE AREE RUN MORERRIFERI STEM REL 2 6 Connector PINLASSIGHIMENES uie cer etes cerro Ca ER RE sans UR ERDCMDMR FEE RA EK DEREN E ET A EEA 2 7 PMC Site 1 Jin and Jin2 Connectors oci eee ere erre inu P et LESE e n RE RE na dea bn 2 7 PMC Site 1 Jn3 and Jn4 Connectors cece nemen nn 2 8 PMC Site 2 inL and Jin2 Connectors eerte ere e nese d eere Fe aaepe bcn OE ERAT deua e 2 9 PMC Site 2 Jn3 and Jn4 Connectors sssssssesssseseI eee eee s ess 2 10 VME PO Connector Pin Assignments sssssssssssssssememe memes eee EE EEEE E esas 2 11 VME P1 Connector Pin Assignments sssssssssssssseemem me esee messes emen nnne nnns 2 12 VME P2 Connector Pin Assignments ssssssssssssssssemem memes sene eee nena sess 2 13 3 PCI PO Development Backplane eeeeeeeeeeeeeeeeeeeen nennen nnne nans 3 1 General DeScriPtion EEUU 3 1 Backplane J umper Configurations ssssssssssssssssesen e memememe e essem sese e enemies 3 2 Bus Arbiter Jumper Settings ssssssssss ene eremi nene 3 2 PCI Bus Clock J mper Settings eiit err n EE nna E ENE ED ENEE eese Ee ro laus efe ae t eos 3 4 System Slot Termination Jumper Settings cece een ee te eene nens 3 5 809524 Revision D FEBRUARY 2009 Artisan Scientific Quality Instrumentation Guaranteed 8
78. ng the PMC 605 service Pmc605_writeSeeprom Refer to Appendix A of the Foundation Firmware User s Manual document number 808006 for a complete description of the PMC 605 FF W Services Cross Reference SVME DMV 179 GPM MAP COMMAND WITH PMC 605 INSTALLED The following is typical of what you will see when you type map at the GPM prompt of your SVME DMV 179 SBC with a PMC 605 installed 809524 REVISION D FEBRUARY 2009 4 5 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com OUTREACH PCI PMC EXPANSION SYSTEM USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING 40000000 map Hardware map for the SVME DMV 179 Base Addr Size LM Addr A24 0x00400000 0x00080000 0x00000000 A32 0x40000000 0x07FFF000 0x00000000 CFI1 4Mx16 OxFF000000 0x01000000 CFI1 4Mx16 OxFE000000 0x01000000 DRAM 0x00000000 0x08000000 NOVRAM OxF4008000 0x00008000 Vendor Device HDR Config Memory Space Allocation Device name ID ID TYPE Base Addr BAR PCI Base Size Type GT 64130 0x11AB 0x6320 0x00 0x80000000 0 0x00000000 Memory 1 0x01000000 Memory 2 0x1C000000 Memory 3 OxFF000000 Memory 4 OxF0000000 Memory Universe 0x10E3 0x0000 0x00 0x80003000 0 OxD0001000 0x00001000 Memory 1 0xE0001000 0x00001000 I O SYM53C885ET 0x1000 0x0701 0x80 0x80004100 0 0xE0000000 0x00000100 I O 1 0xD0000000 0x00000100 Memory SYM53C885SC 0x1000 0x000D 0x80 0x80004000 0 OxE0000100 0x00000100 I O 1
79. nostics for the PMC 605 The LED on the PMC 605 will initially be illuminated When the PMC 605 is successfully initialized and its diagnostics passed by FF W the LED is extinguished Refer to the Getting Started Manual for your SBC for information about applying power boot sequences internal diagnostic routines LED activity and troubleshooting information Cross Reference DISPLAY INITIAL SCREEN MESSAGE After bootup control is typically transferred to the General Purpose Monitor GPM Pressing any key on the keyboard will inform the GPM that I O data is being received from the serial data port The GPM will then display a sign on message similar to the following SVME 179 PowerPC 750 General Purpose Monitor Version 8 0 c CWCEC Systems Inc Type for help 40000000 The last line is the initial prompt which shows the VMEbus base address of the card In this example the base address is 4000 0000h Type at the prompt to display the help screen for the GPM For more detailed information on using the GPM refer to the V8 Foundation Firmware User s Manual 808006 Cross Reference 809524 Revision D FEBRUARY 2009 A 5 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com OUTREACH PCI PMC EXPANSION SYSTEM USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING INSTALL BSP Once the hardware is correctl
80. on ROM Base 0x00000000 maximum latency 0x00 minimum grant 0x00 interupt pin 0x01 interupt line 0x00 40000000 PRIMARY BAR CONFIGURATION Once the Secondary BARs are configured then the Primary BARs of the PMC 605 must be configured This can be achieved by any device with access to the PCI PO bus configuration space In this example the host SBC in slot 1 will configure the primary BARs of its own PMC 605 via the PMC 605 s Secondary interface configuration space and the Primary BARs of the PMC 605 in slot 2 via the PCI PO configuration space Figure 4 4 shows one option for the address map for the PCI PO bus based on the requirements of the BARs as defined by the Primary Setup registers FIGURE 4 4 Example of Address Map based on BAR Requirements PCI PO Memory map PCI PO I O map Slave PMC605 CSRs 0x0030 1000 Master PMC605 CSRs 0x0030 0000 0x0010 0000 Slave PMC605 CSRs 0x0000 0100 Master 179 RAM Master PMC605 CSRs 0x0000 0000 0x0000 0000 4 8 809524 Revision D FEBRUARY 2009 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING SYSTEM INTEGRATION Configure Master s Primary BARs Configure Slave s Primary BARs To configure the Master s primary BARs use the CSS function PciConfigWrite The parameters to access a PMC 605 on an SBC are as follows busNo 0 deviceNo OxB functionNo 0 RegNo
81. ower Requirements Configuration EEPROM JTAG Support Ruggedization Levels The PMC 605 has the following major features The Intel 21554 PCI to PCI Bridge device supports a clock speed of 33 MHz on the Secondary PCI Bus and 33 MHz on the Primary PCI bus The Primary PCI bus connects to the PCI PO bus and the Secondary PCI bus interface connects to the Host PCI bus The PMC 605 is dynamically configured during power up or reboot to act as the bus arbiter when placed in the PCI PO backplane s System Slot The PMC 605 uses a parallel arbitration scheme The PMC 605 can generate a PCI bus clock for the PCI PO bus or receive it from an external source The PCI bus clock is dynamically enabled when placed in the PCI PO backplane s System Slot and is disabled when placed in a Peripheral Slot The PCI PO bus can be synchronous to the Primary PCI bus or operate completely asynchronously according to the configuration of its PCI bus clock source The PMC 605 is dynamically configured during power up or reboot to terminate signals as necessary for the PCI bus when placed in the PCI PO backplane s System Slot The PCI PO bus is 3 3 V signalling 5 V tolerant The PMC 605 is powered via the basecard s 5 V rail an on board regulator provides 43 3 V A serial EEPROM stores basic configuration information for the 21554 PCI to PCI Bridge device The CPLD supports the IEEE Std 1149 1 boundary scan JTAG and is In System Programmable if so con
82. res a significant amount of insertion force Use extra care when aligning and inserting your SBCs into your chassis to ensure that a secure mechanical and electrical connection is made between the cards and the backplane mating connectors 809524 Revision D FEBRUARY 2009 A 3 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com OUTREACH PCI PMC EXPANSION SYSTEM USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING Choosing Slot Locations Insert the first SBC with PMC 605 card in Slot 1 the left most slot in the VME chassis if you want it to be the VMEbus System Controller SYSCON If you intend to use another card as the SYSCON place the SBC with PMC 605 in the left most unoccupied slot All VME cards should be installed in adjacent slots leaving empty slots may cause problems with interrupts and Bus Grant signals Insert the additional SBC with PMC 605 cards in the immediately adjacent slots If you have a specific SBC with PMC 605 card that you wish to use as the PCI PO System Controller make sure that it is installed to the left of the other cards equipped with PMC 605 cards ATTACH THE PCI PO DEVELOPMENT BACKPLANE A Caution Rear View BPL 605 003 E E14 E E15 El E16 E E17 A E18 A Attach the PCI PO development backplane either the BPL 605 002 or the BPL 605 003 to the back of the VME backplane Depending
83. rimary Min GNT Max LAT C 0x00 D 0x00 Secondary Class code E 0x80 F 0x06 10 0x00 Secondary Min GNT Max LAT 11 0x00 12 0x00 Downstream Mem0 CSRs only set a 4 Kbyte window size for CSRs 13 OxFO 14 OxFF 15 OxFF 16 0x00 Downstream Mem1 or I O set 1 Mbyte memory size window 17 0x00 18 OxFO 19 OxFF 1A 0x00 Downstream Mem 2 not used 1B 0x00 1C 0x00 1D 0x00 1E 0x00 Downstream Mem 3 not used 1F 0x00 20 0x00 21 0x00 22 0x00 Downstream Mem 3 Upper 32 23 0x00 24 0x00 25 0x00 26 0x00 Expansion ROM not used 27 0x00 28 0x01 Upstream Memo or I O Set 1 Kbyte I O window size 29 OxFC 4 4 809524 REVISION D FEBRUARY 2009 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING SYSTEM INTEGRATION TABLE 4 1 Serial EEPROM Factory Default Values Offset Data Description 2A OxFF 2B OxFF 2C 0x00 Upstream Mem1 set 4 Mbyte memory window size 2D 0x00 2E 0xCO 2F OxFF 30 0x00 Chip Control 31 0x00 Clear Primary Lockout bit 32 0x00 Chip Control 1 33 0x00 LUT disable 120 disable 34 0x00 Arbiter Control not used 35 0x00 36 0x00 System error disable 37 0x00 38 0x00 Power management 39 0x00 3A 0x00 3B 0x00 3C 0x00 3D 0x00 3E 0x00 3F 0x00 40 0x00 41 0x00 42 0x00 These default values listed above can be changed usi
84. rs Pn1 Pn2 Pn3 and Pn4 are compliant with IEEE P1386 1 Draft 2 2 April 22 2000 The P1 P2 and PO connectors conform to the ANSI VITA 1 1994 Draft 1 11 10 April 1995 VME64bus Specification 809524 Revision D FEBRUARY 2009 2 5 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com OUTREACH PCI PMC EXPANSION SYSTEM USER S MANUAL ELECTRICAL CHARACTERISTICS The maximum current of the SVME DMV 210 at 5 V is 1000 mA PMC cards not included ENVIRONMENTAL CHARACTERISTICS Table 2 1 shows the complete range of environmental specification limits used to categorize the ruggedization levels of CWCEC products The SVME DMV 210 is available in ruggedization levels 0 and 200 TABLE 2 1 Card Air Cooled Level 0 Air Cooled Level 50 Air Cooled Level 100 Conduction Cooled Level 100 Conduction Cooled Level 200 2 6 CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING Environmental Specification Limits and Ruggedization Levels ts D Oe Ww Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com Operating Storage Temperature Temperature 0 Cto 50 C 40Tt085C inlet 4 cfm air flow note 6 20 Cto 65 C 40 C to 85 C inlet 4 cfm air flow note 6 40 C to 71 C 55 C to 85 C inlet 4 cfm air flow note 6 40 C t071 55 C to 85 C card edge temperature 55 C to 85 C 62 C
85. rs and Technicians on staff in our Remotely inspect equipment before purchasing with our State of the art Full Service In House Service Center Facility Innovative InstraView website at http www instraview com We buy used equipment We also offer credit for Buy Backs and Trade Ins Sell your excess underutilized and idle used equipment Contact one of our Customer Service Representatives today Talk to a live person 888 88 SOURCE 888 887 6872 Contact us by email sales artisan scientific com Visit our website http www artisan scientific com
86. ry PCI Clock 3 PCI PCI Interface i Interface PO PCI Bus PCI PCI Bridge PCI Bus P2 Reset PMC2 IO 64 Interrupt EE PMC Clock Secondary o 2 Mask j Peet PMC2 Clock 3 T4174 PMC1 Reset PMC1 Busmode1 PMC1 Interrupts PLD PMC2 Interrupts A S PMC2 Reset PMC2 Busmode1 The SVME DMV 210 has the following major features Initiator Target PCI Bridge Interface Intel 21154 PCI PCI bridge PO PCI data bus 32 bit 25 MHz minimum 33 MHz typical e PMC PCI data bus 64 bit 25 MHz minimum 33 MHz typical Allows for initiator capable I O cards Connector 1O Routing PMC I O to P2 PO Supports interrupts to the processor card The SVME DMV 210 transfers interrupts from PMC cards to INTA on the PCI PO bus The SVME DMV 210 uses standard VME 6U eurocard dimensions and is compliant with ANSI VITA 1 1994 DRAFT 1 11 0 April 1995 VME64bus Specification The SVME DMV 210 requires a 5V 0 25V input power supply from the backplane An on board regulator provides 3 3V capable of providing up to 12 W or 3 5 A The maximum current used by the SVME DMV 210 not including that used by PMC modules is 1000 mA The 12 V and 12 V power supplies from the VMEbus are routed to the PMC modules The SVME DMV 210 is available in air cooled ruggedization level 0 and conduction cooled level 200 40 C to 85 C card edge versions An Auxiliary Thermal Interface is provided for the conduction cooled version FIGURE 2 2 SVME DMV 210 Block
87. ry Interrupt Request register to assert INTA on the Mechanism host PCI bus This provides an inter card interrupt mechanism directly under software control The PCI PO I NTA to the host PCI bus is enabled and disabled by a software controllable bit in the PMC 605 s Local Control and Status Register LCSR Refer to page 1 10 for information on the LCSR Cross Reference RESET Only a card with TERMDIS grounded can generate a PCI PO Reset It can either follow the Reset signal from the host or it can be initiated from the host through software The PMC 605 does not accept resets from the PCI PO bus regardless of the state of TERMDIS If an external PMC 605 reset is required this must be done via the host basecard s VME interface 809524 REVISION D FEBRUARY 2009 1 9 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com OUTREACH PCI PMC EXPANSION SYSTEM USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING SERIAL EEPROM LED REGISTERS TABLE 1 2 A serial EEPROM provides basic configuration details to the 21554 PCI to PCI Bridge device such as subsystem vendor ID D4D4 and subsystem device ID 0605 The configuration details can be programmed by the host card and read by the 21554 after power up or card reset Refer to Chapter 4 of this manual and Appendix A of the V8 Foundation Firmware User s Manual 808006 for more information The PMC 6
88. t may appear in this document No part of this document may be copied or reproduced without the prior written consent of Curtiss Wright Controls Inc The proprietary information contained in this document must not be disclosed to others for any purpose nor used for manufacturing purposes without written permission of Curtiss Wright Controls Inc The acceptance of this document will be construed as an acceptance of the foregoing condition Copyright 2009 Curtiss Wright Controls I nc All rights reserved TRADEMARKS PowerPC is a trademark of International Business Machines Corporation VxWorks is a registered trademark of Wind River Systems Inc Outreach is a trademark of CWCEC Systems Inc All other brand and product names are trademarks or registered trademarks of their respective owners 809524 VERSION D FEBRUARY 2009 Ul Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com OUTREACH PCI PMC EXPANSION SYSTEM USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING IV 809524 VERSION D FEBRUARY 2009 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com CuRTISS WRIGHT CONTROLS EMBEDDED COMPUTING TABLE OF CONTENTS 1 PMG 605 PCE PO Bridge Module tica nii nia ekle iicnlnedanne iR RA Bd nd 1 1 General DESErIPtiON e OERUMMMTMTMMMSET 1 1 Summary of Feat res icc ee e Exe LEA IRAN Te RUE PR EIN NR MUN INN Var
89. t of brackets File names are set in italics Open the file named es h Directory names show the full directory path The last Go to the c windows temp backup directory directory in the path does not have a trailing slash following it Prompts and other text appearing on monitors is set mpp MC68040gnu gt in bold monospace type Firmware code and any information you need to make f Makefile MC68040gnu type in response to a prompt is set in monospace type Table 2 lists symbols that can follow a signal name For example the asterisk is used with a PCI signal name such as IRDY TABLE 2 Signal Conventions Symbol Description no symbol The signal is active HIGH or The signal is active LOW 809524 REvisioN D FEBRUARY 2009 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING Abbreviations Memory Addresses Icons Cross Reference Warning A Caution gt Table 3 lists the abbreviations used to describe the size of a memory device or a range of addresses TABLE 3 Abbreviations Abbreviation Convention 1 Kbyte 1 024 bytes 1 Mbyte 1 024 Kbytes 1 Gbyte 1 024 Mbytes Unless otherwise stated all memory addresses are shown in hexadecimal notation The following icons are used throughout this document Cross references to other documents are use
90. te and routes this second clock over the PCI PO bus In this configuration the primary and secondary sides can operate at dif ferent clock speeds Peripheral Slot PMC 605 modules in the peripheral slots receive clocking from their host cards for their secondary sides Their primary buses use a clock source on the PCI PO bus Note The on board oscillator is not installed on standard versions of the PMC 605 product Consult the factory if you require a version of the product that includes the oscillator FIGURE 1 5 PCI PO Clock Source Configurations Fully Synchronous Asynchronous Peripheral Slot System Slot System Slot PCI Clock PCI Clock PCI Clock 21554 21554 21554 Secondary PCI Bus e H Secondary PCI Bus H Secondary PCI Bus CLKOJ Primary PCI Bus 0 33 MHz Primary PCI Bus m Primary PCI Bus CLKO CLKO PCI PO Bus PCI PO Bus PCI PO Bus 809524 REVISION D FEBRUARY 2009 1 7 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com CuRTISS WRIGHT CONTROLS EMBEDDED COMPUTING OUTREACH PCI PMC EXPANSION SYSTEM UsER s MANUAL PCI PO SYSTEM SLOT TERMINATION when the TERMDIS signal is connected directly to Vcc The TERMDIS signal referred to above is connected to Ground or Vcc via the 2 or 3 slot PCI PO Development Backplane part number BPL 605 002 or BPL 605 003 The
91. to 125 C card edge temperature Notes 0 to 100 Operating Humidity 0 to 95 non condensing non condensing 0t0100 non condensing 0 to 100 non condensing 0 to 100 non condensing 0to 95 Storage Humidity non condensing 0 to 100 non condensing 0 to 100 non condensing 0 to 100 non condensing 0 to 100 condensing Sine Random Mechanical Vibration Vibration Shock note 1 note 4 note 5 N A N A N A N A 0 02g Hz 30 g peak 20 2000 Hz half sine pulse 11 ms dura tion 10gpeak 0 04g Hz 30g peak 15 2000 Hz 15 2000 Hz half sine note 2 pulse 11 ms dura tion 10g 0 01 g Hz 40g peak 15 2000 Hz 15 2000 Hz half sine note 3 pulse 11 ms dura tion 10g 0 1 g Hz 40 g peak 15 2000 Hz 15 2000 Hz half sine note 3 pulse 11 ms dura tion All levels based on a sweep duration of ten minutes per axis each of three mutually perpendicular axis Displacement limited to 0 10 inches D A from 15 to 44 Hz Displacement limited to 0 436 inches D A from 15 to 21 Hz 60 minutes per axis each of three mutually perpendicular axes Three hits per direction per axis total of 18 hits At sea level 809524 REVISIOND FEBRUARY 2009 CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING CONNECTOR PIN ASSIGNMENTS PMC SiTE 1 JN1 AND JN2 CONNECTORS TABLE 2 2 PMC Site 1 Jn2 32 Bit PCI PMC Site 1 Pin Assignments Jn1 and Jn2 PMC Site 1 Jn1 32 Bit PCI SVM
92. total of 18 hits At sea level 809524 Revision D FEBRUARY 2009 CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING PMC 605 PCI PO BRIDGE MODULE CONNECTOR PIN ASSIGNMENTS CONNECTOR LOCATIONS The locations of the Pn1 Pn2 Pn3 Pn3 and J1 connectors are shown in Figure 1 8 FIGURE 1 8 Connector Locations 8 5 i o c Ca c gt J Ca a O O a ES 0000000000 _ soono E o O ojo Oo Pn1 Pn3 Pn2 Pn4 809524 REVISION D FEBRUARY 2009 1 13 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com OUTREACH PCI PMC EXPANSION SYSTEM USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING PN1 PN2 PIN ASSIGNMENTS TABLE 1 4 Pn1 Pn2 Pin Assignments Pn1 32 bit PCI Pn2 32 bit PCI Pin Signal Name Signal Name Pin Pin Signal Name Signal Name Pin 1 TCK 12V 2 1 12V TRST 2 3 Ground INTA 4 3 TMS TDO 4 5 INTB INTC 6 5 TDI Ground 6 7 BUSMODE1 5V 8 7 Ground PCI RSVD 8 9 INTD PCI RSVD 10 9 PCI RSVD PCI RSVD 10 11 Ground PCI RSVD 12
93. umper Settings 2 Slot Backplane 3 Slot Backplane Recommended Setting Recommended Setting 605 in System Slot 0 terminating bus signals 605 in System Slot 0 terminating bus signals Slot 0 Connect E8 E9 Slot 0 Connect E8 E9 Slot 1 Connect E16 E17 Slot 1 Connect E19 E20 Slot 2 Connect E28 E29 Additional Possible Configurations Additional Possible Configurations 605 in Slot 1 terminating bus signals 605 in Slot 1 terminating bus signals Slot 0 Connect E7 E8 Slot 0 Connect E7 E8 Slot 1 Connect E17 E18 Slot 1 Connect E20 E21 Slot 2 Connect E28 E29 605 in Slot 2 terminating bus signals Slot 0 Connect E7 E8 Slot 1 Connect E19 E20 Slot 2 Connect E29 E30 809524 Revision D FEBRUARY 2009 3 5 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com OUTREACH PCI PMC EXPANSION SYSTEM USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING FIGURE 3 4 Bus Termination Jumper Locations Slot 1 Slot 0 Slot 2 Slot 1 Slot 0 Rear View 2 Slot Backplane Rear View 3 Slot Backplane BPL 605 002 BPL 605 003 The 95 pin conne
94. ut to the arbiter device which does not have a pull up on it Inputs should not be left floating Also note that only one card in the system should be configured as the bus arbiter Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com OUTREACH PCI PMC EXPANSION SYSTEM USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING Cross Reference Refer to Bus Arbiter Jumper Settings on page 3 2 for information on configuring arbiter settings when using the PMC 605 with the PCI PO Development Backplane part number BPL 605 002 or BPL 605 003 PCI PO Bus CLOCK Cross Reference The PMC 605 functions as the PCI PO bus clock source when the CLKDIS signal is connected directly to Ground The PMC 605 provides a 33 MHz clock source on both SCLKO and SCLK1 The PCI PO bus clock source is disabled when the CLKDIS signal is connected directly to Vcc In this mode the PCI PO bus clock needs to be provided from an external source such as from a basecard s 33 MHz clock or another PMC 605 The PCI PO clock source is always received on PCLKO PCLK1 is only used in systems with more than three slots on the PCI PO bus The CLKDIS signal referred to above is connected to Ground or Vcc via the 2 or 3 slot PCI PO Development Backplane part number BPL 605 002 or BPL 605 003 See PCI Bus Clock Jumper Settings on page 3 4 for details The state of
95. y configured and installed in the chassis the next step is to install the host card s board support package software See the BSP Software User s Manual for more information Cross Reference A 6 809524 REVISION D FEBRUARY 2009 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com 2 Slot Backplane configuration pins 3 7 Peripheral Slot 1 pin assignments 3 9 System Slot 0 pin assignments 3 8 21554 Embedded PCI Bridge Controller 1 4 21554 PCI to PCI Bridge Controller 1 3 3 Slot Backplane configuration pins 3 10 Peripheral Slot 1 3 12 Peripheral Slot 2 3 13 System Slot O 3 11 A addressing example 4 12 ARBDIS signal 1 5 arbitration scheme 1 3 1 5 asynchronous operation 1 3 asynchronous System Slot configuration 1 7 B backplane 3 1 backplane pin assignments 3 7 Base Address Registers BARs 4 7 block diagram PMC 605 1 2 SVME DMV 210 2 2 block diagram PMC 605 1 2 boundary scan JTAG 1 3 bus arbiter 1 5 Bus Arbiter jumper settings 3 3 bus arbitration 1 3 bus clock source 1 6 C card insertion force A 3 cautionary note ARBDIS signal 1 5 CLKDIS signal 1 6 CLKDIS signal 1 6 clock 809524 VERSION D FEBRUARY 2009 Index speed 1 3 clock source configurations 1 7 component locations PMC 605 1 11 SVME DMV 210 2 5 configuration register preload 4 3 connector locations PMC 605 1 11 1 13 SVME DMV 210 2 5 D device ID 1 10 dia

Curtiss-Wright / DY4 PMC-605 PMC Module Manual

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