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1. M Figure 6 Jumper Locations top view 14 PHYTEC Messtechnik GmbH 2014 L 800e 0 Jumpers on on O LEG OO OD on OD doom go 09 00
2. fete AS 00000000000090 00000000000000 0000000000 HL 090 P UD CD mery aE on 1 CRO OB DES DES phyCARD i MX 6 Component Placement top view Figure 2 PHYTEC Messtechnik GmbH 2014 L 800e 0 Introduction 0 0 0 OXA HH 600 00 920 940 600 20 BHSSHRBS g 2 8 0000000000600000 an an 88 C 88
3. o Figure 9 JTAG Interface at X2 and X3 top view 40 PHYTEC Messtechnik GmbH 2014 1 800 0 Debug Interfaces HAAR on on on O OD GOOD 0 OF co on of ux ox 00 Of on 0 on 0000000 0000000 0000000 0000000 0000000 D 0000000 el ooooQooo m OOOOO MMMMM OH m Dg dio og e on 032 M gt on M on og on L on on O0000000000000000000000 Lcd OCO 0 m on mf 1 DA Figure 10 Interface at X2 and bottom view Pin 1 of the JTAG connector X3 is on the connector side of the module Pin 2 of the JTAG connector is on the controller side of the module Not
4. 7 8 Physical 1 10 47 PHYTEC Display Interface 74 Descrip sasanak ns aod ura 7 PICU MEER ERR RR 10 11 12 92 18 Power 48 Power 1 19 Power 1 23 Power Management IC 18 Power ux sd ERES SERE ERE MEE ANT RE 6 R 5 232 aaa awanane aan 32 a NANA NG NAN ee eee eee ede 90 5 SD MMC Card Interfaces 29 SDRAM aan 27 Serial Interfaces 31 SMT Connector 7 SPEED LED tee 70 SPI 37 Storage 48 Supply Voltage 2 17 System Configuration 25 System Memory 27 System Power 7 17 96 T Technical Specifications 47 U 28 35 cc Y 27 18 ll 16 46 lu m R U 18 02 09 0 27
5. U13 S 889 C360 ABS 16 10 TP22 AAN PON Figure 3 phyCARD i MX 6 Component Placement bottom view PHYTEC Messtechnik GmbH 2014 L 800e 0 phyCARD i MX 6 PCA A XL3 xxx 1 3 Minimum Requirements to Operate the phyCARD i MX 6 Basic operation of the phyCARD i MX 6 only requires supply of a 3 3 V input voltage with 1 5 A load and the corresponding GND connection These supply pins are located at the phyCARD Connector X1 VDD_3V3 X1 1 2A 1B 2B Connect all 3 3 V VCC input pins to your power supply and at least the matching number of GND pins Corresponding GND 1 4A 13 4B 8B 13B Please refer to section 2 for information on additional GND Pins located at the phyCARD Connector X1 Caution We recommend connecting all available 3 3 V input pins to the power supply system on a custom carrier board housing the phyCARD i MX 6 and at least the matching number of GND pins neighboring the 3 3 V pins In addition proper implementation of the phyCARD i MX 6 module into a target application also requires connecting all GND pins neighboring signals that are being used in the application circuitry Please refer to section
6. 70 USB OTG Interface at Connector X29 222 72 Universal LVDS Interface at Connector X6 eee 73 Audio Interface at Connectors X1 X2 78 Extension Connector X8A 9 83 SD MM Card interface at connector 26 2 85 Boot Mode Selection Jumper JP1 86 System Reset 1 88 Battery 89 Carrier Board Physical DimensionS ssssessssessessessessessessesscssessessessessesesseseesse 92 PHYTEC Messtechnik GmbH 2014 L 800e 0 ii phyCARD i MX 6 PCA A XL3 xxx List of Tables Table 1 Abbreviations and Acronyms used in this Manual eene viii Table 2 BUS EDE EOD DOPO ODER NER DESEE 9 Table 3 Pinout of the phyCARD Connector X1 Row 1 4 4 2 2 0 10 Table 4 Pinout of the phyCARD Connector X1 Row 2 2 2 11 Table 5 Settings a i eva UPS 16 Table 6 Power Management ERE 23 Table 7 Power 23 Table 8 Boot Modes of the phyCARD i MX 6
7. 26 Table 9 Boot Configuration Signals generated by the 26 Table 10 EEPROM write protection states via J3 28 Table 11 Location of SD MMC Card Interface 5 2 29 Table 12 Location of the UART 1 32 Table 13 Location of the USB OTG Signals 4 amp E een 33 Table 14 Location of the USB Host Signals 55 33 Table 15 Location of the Ethernet Signals A oe 34 Table 16 Interface Signal Location 2 2 0 35 Table 17 SPL Interface Signal Location 36 Table 18 551 Interface Signal 37 Table 19 Location of GPIO and IRQ 38 Table 20 JTAG Connector Signal 519 42 Table 21 Debug interface Connector X2 Signal 42 Table 22 Display Interface Signal Location 2 2 2 43 Table 23 Pixel Mapping of 18 bit LVDS Display Interface eese 44 Table24 Pixel Mapping of 24 bit LVDS Display
8. O 9 0x290 a Bl MBH 910 D ololo 0 00 hed emm s nuo 9 080 gag un 000000 00 ao Sooo BB oo IU 888 mp 000 gg HBBH O BH 0000 u OD Gg SSSSSEHBSH 00 9 505 9995 unu 00 Gp 2510888882 2685 8 050 0000 EET 0000 Ss 0000 0000 Un 0010 B 0000 0008 8 pons 0000 ELI 0000 D im fred up nn wem ong 0100 D 8 0000 0000 n5 8 uz ooooceoooo B 0000060000 0000 00 00 n 00000000 00 00 00000000 0000960000 0000090000 a 8900000000 00 BS 00000000 nm ES oo un m nade E 00 665s op aD B 00000000 UD E Eu p pang 00001000000 99 F B 00 aga oO eo ra 88888888 EB Be 0520 a o E 00 gg 00 00 00 om 5 00 00 Bt Bo BEd msip 00 sd wmm gt 8 ooo n E 3 uu 00 m mna 005 00 D 8 5
9. 76 Selection of the Touch Screen 0 77 Selection of the Audio 1 79 NGGEN 80 80 SPI Connector Selection ee 82 SPI and GPIO Connector Selection 49 Mp 84 PHYTEC Extension Connectors X8A b s 84 Boot Options for the phyCARD 1 MX 6 amp 87 phyCARD i MX 6 PCA A XL3 xxx vi PHYTEC Messtechnik GmbH 2014 L 800e 0 Conventions Abbreviations and Acronyms Conventions Abbreviations and Acronyms This hardware manual describes the PCA A XS1 System on Module in the following referred to as phyCARD i MX 6 The manual specifies the phyCARD i MX 6 s design and function Precise specifications for the Freescale Semiconductor 1 6 microcontrollers can found in the enclosed microcontroller Data Sheet User s Manual Conventions The conventions used in this manual are as follows Signals that are preceded by an n or character e g nRD RD or RD or that have a dash on top of the signal name e g RD are designated as active low signals That is their active state is when they are driven low or are driving low A 0 indicates a logic zero or low level signal while a 1 represents a logic on
10. 00 5 000 5 00 8 EL 00 8 00 E 00 gp un bu manens B BD un m oo Bu off aues 000000090 H a eto L SOS m 8 00 00 E gn je 00 i ool 00 8 1 ggg og w UD enh EC E m BE roms un m 00 gg 00 B 863 m 2 a Figure 27 SD MM Card interface at connector X26 The phyCARD Carrier Board provides a standard SDHC card slot at X26 for connection to SD MMC interface cards It allows easy and convenient connection to peripheral devices like SD and MMC cards in 1 bit or 4 bit bus mode Power to the SD interface is supplied by sticking the appropriate card into the SD MMC slot The card slot X26 connects to the phyCARD i MX 6 via a level shifter to ensure the correct voltage for the SD MMC cards PHYTEC Messtechnik GmbH 2014 L 800e 0 85 phyCARD i MX 6 PCA A XL3 xxx 17 3 14 Boot Mode Selection JP1 9 H n 9 5e e 0000 S eO coocoo o D 909 9999 Hg BO nim BE o ORBO ggg 0000 m 2 00 000000 Dig oo 888
11. onon 005008 7 H D gg 0000 L Uoanoanogd8g5 fg oo ggg B BB oo nnnn 0000 8 000000 0095 oS gt 9 99 cea Du 9959 SS poo yoge o000 00 to gg Ia 0000 Soen bann 905 0000 050 9898 Sooo Mee EB 050 eb a Bu 5 1000925 poi 00 B c3 0000 muri Bui iis un nn 00 B 00 vagig 0 00 inn 1 m 87000 DB 28 op zi 00 UD s E 00 un 5 10000000 0000980000 TIS 0000980000 Eh m E E 000004600900 gt 99 0000090000 gg 00000000 a 00 un B gm un Eres 00 jg oF 0045 pa B g y UD m o 88 E aa 5 8 bn sa 0 S otg ad 56 ofa 0 IE 0000 mun gaca a 00 29565666 S UJ ip 52 sAm E 00 S m B 0 ag 00 T E na B D 00 a L9 3 asim Boop Ged OO mum x BE SUN A BDSun 00 on Ql 004 0080 n agu 5 un 00 0000 UD preng omen oo E omo p 5 000 EH 00 m 8 Bwe 9 m 4ga epo B 00 00 00 S E 00 00
12. 0050 9 5086 am 2 BAE oo B 1 ca 00 gs un DU 50 poit 59 Bo 00 Soa 00 Br H a 8 mn D 0 o m 888 00 Figure 17 Powering Scheme Caution Do not use a laboratory adapter to sup ply power to the carrier board Power spikes during power on could destroy the phyCARD module mounted on the carrier board Do not change modules or jumper settings while the carrier board is supplied with power Permissible input voltage at X28 9 V The required current load capacity 2 0 Ais recommended 9 36 Center Hole 2 2000 mA 7 GND Figure 18 No jumper configuration is required in order to supply power to the phyCARD module 66 36 V DC unregulated of the power supply depends on the specific configuration of the phyCARD mounted on the carrier board as well as whether an optional extension board is connected to the carrier board An adapter with a minimum supply of Polarity Y min 5 0 mm Power Connector corresponding to Wall Adapter 28 Messtechnik GmbH 2014 1 800 0 The phyCARD i MX 6 on the phyBASE The phyBASE is assembled with a few power LEDs whose functions are described in the following table LEDs Color Description 037 green VCC5V 5V supply voltage for peripherals on the phyBASE 038 green VCC supply voltage of th
13. Sanggit y puo SINI g 9 O0p Ooo ae 9800 oo Os E anm 5 no oof Un 00000000 COM uem mur ad 0 Y 55 000 cu 00 E age 2 00 00 0000 aacra 90 00 oo aono B pL 00 H S20 960095 fo E M 00 gg 00 ES 0000 j B omg 0000 1 DD oo 500 0518 g Ez BE B 00 EE I p 00 mo 9 00 0 nnn i BH oo ggg UD o BE D mng BL oo nn BH a Boge B lt on m 8 B 000 m Z E oo oo 00 un 8 5 00 00 26 0 eco E 00 unn lt 00 00 019 m of z 006 Usg ca nnns 00000000 si goo on un ES ES a 8 oo mE Ll 09 B 00 n un H a BE H Eo B r3 n 00 Ej ims H cp E a o tf oS I a oo utu m ggg n5 B on BEE oo UD 204 2050 Bo E c EQUUM ENIE DO an n 00 Un 00 552 00 Figure 26 Extension Connector X8A X9A The extension connectors
14. e ng a LU L1 nn 00 9 06 0000 zg 00 un 0 oo 00 00 n 00000000 Ji EE 0000960000 L ao 0000580000 0000060000 gil ou 00000000 Alo m 55 200 ao 800 pp GOO DCO mo Bg Soo Ej mm EEH 00 nun LL a B am 9001000000755 og B 2080 I 20 00 nn uan E o o 3 00000000 000 un mw OG SOS otiso 29 8 58 ooo ee 96 BLON 8 00 00 0000 88888888 m 885 MV 0520 a 00 00 00 2 E Coo D nn odoo Gb Bong 00 0000 00 BE oo Goo 00 EB wmm a ooo oo P 00 UD DD go o n m oo 00 B ou 000000 Bag E E jon 4 00 n CB 5 og 000 E 00 ag P 8 BuU 00 nn un 00 055 oo eT eed ooo 288 BB 00 nn gu E B ilee 2 00000000 oo of F anfon mm on my SS B un 88 100 puna am oe 0 00 i Bag un un oo E Sau 00 i ius Pha m E Jas r3 E a pean maan anana 2 5
15. 88 88882855555 smmm 54 DO go 00 BBBBBBBSBOESEHAS B BEBED 0 85588858888658 Une a 689600 IEN 5 EN fg CO mun ag Gun Pessoa E S3 18 007 on 050 lis a Tama 00000000 00 dn Sooo eng 9 D 9 05 0000 00 00 Ed SO90000 Ses BH A Begg 559 a 5 EB 00 06 008 gB E 00 9 0000 DU 995 Eg 9 00 cls on 050 5 un 00000000 Figure 13 phyBASE Overview of Connectors LEDs and Buttons 56 PHYTEC Messtechnik GmbH 2014 1 800 0 The phyCARD i MX 6 on the phyBASE 17 2 1 Connectors and Pin Header Table 27 lists all available connectors on the phyBASE Figure 13 highlights the location of each connector for easy identification Reference Description 282 Designator Section X1 Stereo Microphone input connector 17 3 8 X2 Stereo Line out connector 17 3 8 X3 Stereo Line In connector 17 3 8 X6 Display data connector 15341 X7 Dual USB Host connector 17 3 X8A Extension connector 0 43 12 X9A Extension connector 1 17 92 X10 Fthernet connector RJ45 with speed and ihi WA link led 26 Secure Digital MultiMedia Card slot 17 3 13 X27 phyCARD Connector for mounting the 17 3 1 phyCARD i MX 6 X28 Wal
16. 80 17 3 10 SPI Connectivity 4 82 17 3 11 User programmable GPI S 82 17 3 12 Extension 7 83 17 3 13 Secure Digital Memory Card MultiMedia Card 26 85 17 3 14 Boot Mode 86 17 3 15 System Buldi0n 5 88 17 3 16 RICat UM M 89 17 53 1417 91 17 3 18 Carrier Board Physical 5 92 18 _ uoa 93 iii eM 95 PHYTEC Messtechnik GmbH 2014 1 800 0 Contents List of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Block Diagram of the phyCARD MX 6 5 5225255 Eh aMEA HER REO ERA uS ER REEF ARR ER RSEN PE PR MAPA 3 phyCARD i MX 6 Component Placement top view 4 phyCARD i MX 6 Component Pla
17. ers 32 05 Interface 32 USB 2 0 9 71 73 USB 33 USB Host 59 32 33 USB 8 99 eee 32 User 4 40 17 19 21 VSTBY JAAN 18 du 19 W NE E 48 censa pem 79 X vo a 73 TANNA 41 PHYTEC Messtechnik GmbH 2014 1 800 0 Suggestions for Improvement Document phyCARD i MX 6 Document number 1 800 0 August 2014 How would you improve this manual Did you find any mistakes in this manual page Submitted by Customer number Name Company Address Return to PHYTEC Messtechnik GmbH Postfach 100403 D 55135 Mainz Germany Fax 49 6131 9221 33 PHYTEC MesstechnikGmbH 2014 L 800e 0 Published Messtechnik GmbH 2014 Ordering No L 800e 0 Printed in Germany
18. uu 000000 nn oi 9 un E Mg Bg 000 6 len up 5 B am 00 00 us 00 B 055 5 i ol mos un Bo t EM oo mu 00000000 gi Fon on 00 00 9 5 B SOS m 98 850 gum I c Bn peng 8 B a 00 1 ms 0000 naon ND 58 00 Lexi 2 eBs n 00 ca m E oo 00 a a OO oo Figure 16 phyCARD i MX 6 SOM Connectivity to the Carrier Board Connector X27 on the carrier board provides the phyCARD System on Module connectivity The connector is keyed for proper insertion of the SOM Figure 16 above shows the location of connector X27 along with the pin numbering scheme as described in section 2 PHYTEC Messtechnik GmbH 2014 1 800 0 65 phyCARD i MX 6 PCA A XL3 xxx 17 3 2 Power Supply X28 OTOOTO 0 0x290 o9 o X amp Uc a MH ooooo D ooo D E 9 O22900 wr Bg o og ssss3 B dB 9000 0023008 V s 888 ooon 0 88 Jg o0 BB BB un nonn 0000 20885658858 5 00 992558558 020 TL Un 0 0 garai suos 1000 588 0000 geste 0000 350056
19. Suspend to RAM Open Collector X1B26 nSUSPEND TO RAM OC 1 00 LOGIC Output port P3 3 of CMIC at 017 Power Off Open Collector Output X1B29 nPOWER OFF OC VDD_3V3_LOGIC port P3 2 of CMIC at U17 Table 6 Power Management Pins With the two output signals X_nPOWER_OFF pin X1B29 and X_nSUSPEND_TO_RAM pin X1B26 three different power states can be defined HOMES Standby Off Signal X nSUSPEND TO RAM High Low X X nPOWER OFF High High Low VDD 3V3 On Off Off VSTBY X On Off X don t care Table 7 Power States Please refer to the chapter Power Management in the phyCARD Design In Guide for more information about the implementation of the power management into your design PHYTEC Messtechnik GmbH 2014 1 800 0 23 phyCARD i MX 6 PCA A XL3 xxx Caution According to the specification for the phyCARD family writing custom software to utilize pins X nSUSPEND TO RAM and X nPOWER OFF requires them to be configured as Open Collector Output The power management features of the phyCARD are implemented with the devices at U29 PMIC and U17 CMIC and allow for a higher granularity in control of the power consumption To implement power management with the PMIC it can be programmed via interface at I C address 0x58 Please refer to the PMIC s User s Guide for more information 24 PHYTEC Messtechnik GmbH 2014 1 800 0
20. ib EG phyCARD 1 6 Hardware Manual Document No L 800e 0 SOM Prod PCA A XL3 xxx SOM PCB No 1371 2 CB Prod No PBA A 03 CB PCB No 1360 2 Edition August 2014 A product ofa PHYTEC Technology Holding company phyCARD i MX 6 PCA A XL3 xxx Copyrighted products are not explicitly indicated in this manual The absence of the trademark TM and copyright O symbols does not imply that a product is not protected Additionally registered patents and trademarks are similarly not expressly indicated in this manual The information in this document has been carefully checked and is considered to be entirely reliable However PHYTEC Messtechnik GmbH assumes no responsibility for any inaccuracies PHYTEC Messtechnik GmbH neither gives any guarantee nor accepts any liability whatsoever for consequential damages resulting from the use of this manual or its associated product PHYTEC Messtechnik GmbH reserves the right to alter the information contained herein without prior notification and accepts no responsibility for any damages that might result Additionally PHYTEC Messtechnik GmbH offers no guarantee nor accepts any liability for damages arising from the improper usage or improper installation of the hardware or software PHYTEC Messtechnik GmbH further reserves the right to alter the layout and or design of the hardware without prior notification and accepts no liability for doing so Copyrigh
21. 10 Caution The current draw at VDD 3V3 LOGIC must not exceed 500 mA PHYTEC Messtechnik GmbH 2014 L 800e 0 Pin Description Pin X1A Pind Signal 1 0 51 Description 31A 5010 00 1 0 VDD LOGIC SD MMC Data line DO both in 1 bit and 4 bit mode 32A X 5010 02 I 0 VDD 3V3 LOGIC SD MMC Data line D 2both in 1 bit and 4 bit mode 33A X SDIO CLK 0 VDD 3V3 LOGIC SD MMC Clock for MMC SD SDIO 34A GND Power Ground 0 V 35A X SPI CSO 0 VDD 3V3 LOGIC SPI3 Chip select 0 36A X_SPI_RDY 0 VDD_3V3_LOGIC SPI3 Data ready in master mode 37A X_SPI_SCLK 0 VDD 3V3 LOGIC SPI3 Clock 38A GND Power Ground 0V 39A X_UART_TXD 0 VDD_3V3_LOGIC Serial transmit signal UART3 40A X_UART_RTS 0 VDD_3V3_LOGIC Request to send UART 3 41A GND Power Ground 0 V 42 X AC97 INT I 0 VDD 3V3 LOGIC T S Selection 1 pull down R67 to configure or target application for TS audio interface 43A X I2S SDATA OUT 0 VDD 3V3 LOGIC 125 Transmit output AUD5 44 X 125 SDATA 1 VDD 3V3 LOGIC 175 Receive input AUD5 45 GND Ground 46A X GPIOO IRQO I O VDD 3V3 LOGIC GPIOO IRQ uC port GPIO2 24 47 X GPIO2 IRQ PWM I O VDD 3V3 LOGIC GPIO2 IRQ PWM uC port 04 29 48 X nWKUP I VDD 3V3 LOGIC Wakeup interrupt input Port
22. 44 Table 25 Camera Interface Signal Location at 1 45 Table 26 LVDS Signal Configuration RU URN RUE 45 Table 27 Connectors and Pin 57 Table 28 phyBASE Push Buttons 5 58 Table 29 phyBASE DIP Switch S3 enne nennen 59 Table 30 phy BASE LEDs Descriptions nana MM 60 Table 315 EE IEEE ERE 63 Table 32 LEDs Assembled on the Carrier Board 67 Table 33 Distribution of the USB Hub s U4 71 iv PHYTEC Messtechnik GmbH 2014 1 800 0 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Table 42 Table 43 Table 44 Table 45 Table 46 PHYTEC Messtechnik GmbH 2014 1 800 0 Contents Universal USB Pin Header X33 Signal Description 71 Display Data Connector X6 Signal 74 Auxiliary Interfaces at Data Connector X12 75 SPI and GPIO Connector Selection sssssssssssesseseessssessessessessessessesessessessessesees 76 LVDS Power Connector X32 Signal 1 30 1 0 00
23. ecce eee e eee e eee eee eee eee 0000000000000000 54 17 1 Concept of the phyBASE RN 55 17 2 Overview of the phyBASE Peripherals ooo paa pan ova eere sey Revo 56 17 2 1 Connectorsand Pin Heddet 57 172 ag a 58 ys asana 60 17 2 4 llc 61 17 3 Functional Components on the phyBASE Board 65 17 3 1 phyCARD i MX 6 SOM Connectivity 27 65 17 3 2 Power Supply X28 66 17 3 3 RS 232 Connectivity P1 eoe NR Nes 68 17 3 4 Ethernet Connectivity X10 sss rib ee 69 17 3 5 USB Host Connectivity X7 X8 X9 3 70 17 3 6 USB Connectivity X29 4 9 7 72 17 3 7 Display Touch Connectivity X6 X32 9 2 73 17 3 7 1 PDI Data Connector 2 2 74 17 3 7 2 Display Power Connector X32 76 17 3 7 3 Touch Screen 77 17 3 8 Audio Interface X1 X2 78 17 3 9 9
24. 00 mi m o 000055 n EBu Bm 00000009 gi foo oo un oo ES ERE B SOS m an an 5 poo om g TE mo g m ang 2 8 El Sm 00 1 gn oi 88 z jos 0000 i B pen 7 g 5 oo gt oo un cB g Bact 80 oo 0096 o H 28 oo i ooo gt ss Von 59 un S m 00 cu T d e D B z 00 un g Ban Figure 28 Boot Mode Selection Jumper JP1 The boot mode jumper JP1 is provided to configure the boot mode of the phyCARD i MX 6 after a reset By default the boot mode jumper is open configuring the phyCARD i MX 6 for booting from the NAND device Table 46 shows the different boot options for the phyCARD i MX 6 Please refer to section 6 as well as the 1 6 Reference Manual for more information about possible configurations 86 PHYTEC Messtechnik GmbH 2014 L 800e 0 The phyCARD i MX 6 on the phyBASE Jumper Setting Description Jumper JP1 selects the boot device of the phyCARD i MX 6 open 1 2 SDO external 3 4 Serial USB OTG USBO 1 2 Bootconfig from eFUSE 3 4 JP1 other settings must not be used with the phyCARD i MX 6 Table 46 Boot Options for the phyCARD i MX 6 please see section 6 for more information on the different boot modes PHYTEC Messtechnik GmbH
25. PHYTEC Messtechnik GmbH 2014 1 800 0 81 phyCARD i MX 6 PCA A XL3 xxx 17 3 10 SPI Connectivity The SPI interface of the X Arc bus is available at the extension connectors X8A and X9A as well as at the display data connector X6 refer to sections 17 3 7 1 and 17 3 12 to see the pinout Due to the X Arc bus specification only two slave select signals are available Because of that the CPLD maps the SPI interface to two of the connectors depending on the configuration of switches 7 and 8 of DIP Switch S3 The table below shows the possible configurations Button Setting Description S3 7 0 0 SSO GPIOO IRQ gt extension 0 X8A 53 8 551 6 101 gt extension 1 X9A 0 1 SSO GPIOO IRQ gt extension 0 X8A 551 6 101 IRQ gt display data connector X6 1 x SSO GPIOO IRQ gt extension 1 X9A SS1 GPIO1 gt display data connector X6 Table 43 SPI Connector Selection 17 3 11 User programmable GPIOs Two GPIOO IRQ and GPIO1 IRQ of the three GPIO Interrupt signals available at the X Arc bus are freely available They are mapped to the extension connectors X8A and X9A pin 16 orto the display data connector X6 pin 5 depending in the configuration at DIP Switch S3 see Table 43 The third GPIO Interrupt signal GPIO2 IRQ is used to connect the interrupt output of the touch screen controller at U28 to the phyCARD i MX 6 GPIOO IRQO GPIO2 24 at J23 and GP
26. Pin Row X1B Ping Signal 1 0 SL Description 20B ETH I 0 ETH 3V3 Receive positive input normal Transmit positive output reversed 21B ETH RX I 0 ETH 3V3 Receive negative input normal Transmit negative output reversed 22B GND Power Ground 0 V 23B nUSB HOST PWR 0 VDD 3V3 LOGIC USB HOST1 Power switch output open drain 24B X nUSB HOST OC I VDD 3V3 LOGIC USB HOST1 over current input signal 25B GND Power Ground 0 V 26B nSUSPEND TO RAM OC VDD_3V3_LOGIC Suspend to RAM open collector output uC port GPIO1 24 278 USB HOST D 1 0 USB USB HOST1 transceiver cable interface D 28B USB HOST 0 1 0 USB USB HOST1 transceiver cable interface D 29B X nPOWER OFF OC VDD_3V3_LOGIC Power Off open collector output uC port GPIO1 25 30B GND Power Ground 0 V 31B X SDIO D1 I O VDD 3V3 LOGIC SD MMC Data line both in 1 bit and 4 bit mode 32B X SDIO D3 I O VDD 3V3 LOGIC SD MMC Data line both in 1 bit and 4 bit mode 33B X SDIO CMD 0 VDD 3V3 LOGIC SD MMC Command for MMC SD SDIO 34B GND Power Ground 0 V 35B X SPI CS1 0 VDD 3V3 LOGIC SPI3 Chip select 1 36B X SPI MOSI I O VDD 3V3 LOGIC SPI3 Master data out slave data in 37B X SPI MISO I O VDD 3V3 LOGIC SPI3 Master data in slave data out 38B GND Power Ground 0 V 39B X UART RXD I VDD 3V3 LOGIC Serial data receive signal UART3 40B X UART CTS I VDD 3V3 LOGIC Clear to send UART3 41B GND Power Ground 0 V 42B X I2S BIT CLK 1 0
27. Please refer to Table for information on alternative settings PHYTEC Messtechnik GmbH 2014 1 800 0 79 phyCARD i MX 6 PCA A XL3 xxx 17 3 9 I C Connectivity The interface of the X Arc bus is available at different connectors on the phyBASE following table provides a list of the connectors and pins with I2C connectivity Connector Location Camera interface X5 pin 4 C SDA pin 5 I C_SCL Display data connector X6 pin 8 IC SDA pin 7 I C_SCL Extension connector 1 X8A pin 7 C SDA pin 8 IC SCL Extension connector 2 X9A pin 7 C SDA pin 8 IC SCL Table41 I C Connectivity To avoid any conflicts when connecting external 1 devices to the phyBASE the addresses of the on board I C devices must be considered Some of the addresses can be configured by jumper Table 42 lists the addresses already in use The table shows only the default address Please refer to section 17 2 4 for alternative address settings Device Address used 7 MSB Jumper LED dimmer U21 0x60 J2 RTC U3 0x51 A D converter U22 0x64 Touch screen controller 0x44 J3 U28 CPLD U25 0x40 S3 3 53 4 Table42 Addresses in Use interface of the 1 6 s third module I2C3 is used for connectivity on the carrier board refer also to section 9 5 80 PHYTEC Messtechnik GmbH 2014 1 800 0 The phyCARD i MX 6 on the phyBASE
28. un 000000 c3 B SB gep Soo 0000 000000 to S008 998 joo BBB cCa48888 A 0000 n oo anno 8B 0000 000000 0005 0000 b CHBHBEBBBBE 99 965 9565 a 5958 02 B 05000 oo nan 0000 mi 4 B ngo Seo un o ee pon 0000 0022 105108 sm g E B8B m xm 00 BB OO 0000 00 0000 gea i Booo 0 un uu 0000 1 E mmm 88m Band 8 5 0000 8 0 un an n 10000000 0000980000 0000060000 B m 0000060000 yn BH 2000600000 gl g 00000000 n2 omP m El H B DD Goo 5959800 gg mg oD on ap B0000 na 0000 Cj E un 00 O 00 oS gun n g 0000000 og Bos 88 gu 0 000 nig a 5888 5 amp LS E Its 00 00 0000 sambi 0 00 BHEBEBHHB m Fee JA pp 10 0528 Sco 8 fo NL S 00 00 r3 og oo B B 0000 BH 25186 S00 55 EB nnm E pow GOD op Bn a e e 00500 unn EU cus B 00 000000 ggg 00 00 B m i B
29. All controller required supplies are generated on board On board power management IC PMIC with integrated RTC Control Management IC CMIC Industrial temperature range 40 C 80 C PHYTEC Messtechnik GmbH 2014 L 800e 0 Introduction 1 1 Block Diagram 32 785 kHz PMIC CLK32 optional 32 786 kHz Control Signals Control Signal VSTBY EEPROM 4 K 1 Wire EEPROM DDR3 RAM 64 Bit BANK1 512 MB to 2 GB NN DDR3 RAM 64 Bit BANK2 m 512 MB to 2 GB LVDS CSIO Camera parallel LVDS SD MMC NAND Flash GPMI 256 MB to 4 GB OT A 25 MHz UART3 with hand shake USB_OTG USB_HOST Card Edge Connector JTAG ETH PHY Card Edge Connector UART 2 10 100 MBit Ethernet Figure 1 Block Diagram of the phyCARD i MX 6 PHYTEC Messtechnik GmbH 2014 L 800e 0 3 phyCARD i MX 6 PCA A XL3 xxx View of the phyCARD i MX 6 1 2 EE aooo 0000 0000 ea gt x do am OOO0O000000000000000000000 OO000000000000000000000000
30. This signal is also available at the display power connector X32 refer to section 17 3 7 2 for more information Provided to supply any logic on the display adapter Max draw 100 mA LEDs D17 and D24 signal use of the USB interface 74 PHYTEC Messtechnik GmbH 2014 1 800 0 The phyCARD i MX 6 on the phyBASE 23 TXOUT1 0 3 3V LVDS data channel 1 positive output 24 GND Ground 25 TXOUT2 0 3 3V LVDS data channel 2 negative output 26 TXOUT2 0 3 3V LVDS data channel 2 positive output 27 GND Ground 28 TXOUT3 0 3 3V LVDS data channel 3 negative output 29 TXOUT3 0 3 3V LVDS data channel 3 positive output 30 GND Ground 31 TXCLKOUT 0 3 3V LVDS clock channel negative output 32 TXCLKOUT 0 3 3V LVDS clock channel positive output 33 GND Ground 34 TP_X 1 0 3 3V Touch 35 TP_X 1 0 3 3V Touch 36 TP_Y 1 0 3 3V Touch 37 TP Y 1 0 3 3V Touch 38 WP I O 3 3V Touch 39 GND Ground 40 15 ANA I 3 3V Light sensor analog input Table 35 Display Data Connector X6 Signal Description continued The table below shows the auxiliary interfaces at display data connector X6 Signal Description USB host interface derived from downstream port 2 of the USB hub at U4 USB2 D Suitable for optional features e g front USB refer to section 17 3 5 for more information about the USB host interfaces interface for
31. SD MMC Card interface the phyCARD i MX 6 the interface signals extend from the controllers third Ultra Secured Digital uSDHC3 Host Controller to the phyCARD Connector Table 11 shows the location of the different interface signals on the phyCARD Connector The MMC SD SDIO Host Controller is fully compatible with the SD Memory Card Specification 3 0 and SD 1 0 Specification Part v1 10 The SDC MMC interface USDHC3 of the 1 6 of the phyCARD i MX 6 supports 4 of the host controller s 8 data channels with a maximum data rate of 104 Mbps refer to the 1 6 Reference Manual for more information The MMC SD SDIO Host Controller is supplied by the VDD 3V3 LOGIC voltage which is derived from the main power supply of the phyCARD i MX 6 3 3 V Because of compatibility reasons a card detect signal X SDIO CD is added to the SD MMC Card Interface The card detect function is implemented by using GPIO5 22 of the 1 6 Pin Signal 1 0 51 Description 1 31 5010 DO I O VDD 3V3 LOGIC SD MMC data bit 0 X1A32 X 5010 02 1 0 VDD LOGIC SD MMC data bit 2 SD MMC clock for X1A33 X SDIO CLK 0 VDD 3V3 LOGIC MMC SD SDIOO X1B31 X SDIO D1 I 0 VDD 3V3 LOGIC SD MMC data bit 1 X1B32 X 5010 03 I O VDD 3V3 LOGIC SD MMC data bit 3 SD MMC command for X1B33 X SDIO CMD I 0 VDD 3V3 LOGIC MMC SD SDIOO SD MMC card insertion and X1B46 X SDIO CD I 00 LOGIC extraction detection GPIO5
32. VDD 3V3 LOGIC I C Clock Output X1B17 I2C SDA I O VDD 3V3 LOGIC Data Table 16 ITC Interface Signal Location PHYTEC Messtechnik GmbH 2014 1 800 0 35 phyCARD i MX 6 PCA A XL3 xxx 9 6 SPI Interface The Serial Peripheral Interface SPI interface is a four wire bidirectional serial bus that provides a simple and efficient method for data exchange among devices 6 pins of the X Arc bus are designated to the SPI interface refer to Table 2 In addition to the four standard signals a second chip select and the SPI ready signal are provided at the X Arc bus The later signal allows to also use SPI devices with 5 wire protocol The Enhanced Configurable SPI ECSPI of the 1 6 has five separate modules ECSPI1 to ECSPI5 The interface signals of the third module ECSPI3 are made available on the phyCARD Connector This module is Master Slave configurable i MX 6 does not provide the SPI ready signal Because of that an additional GPIO GPIO1_9 is attached to pin X1A36 instead The following table lists the SPI signals on the phyCARD Connector Pin Signal 1 0 51 Description X1A35 SPIO 50 VDD 3V3 LOGIC ECSPI3 Chip select 0 X1B35 X SPIO CS1 VDD_3V3_LOGIC ECSPI3 Chip select 1 X1A36 X SPIO RDY 1 00 3V3 LOGIC SPI Ready signal implemented by use of GPIO1 9 1 37 SPIO O 1 00 3V3 LOGIC ECSPI3 clock X1B36 X SPIO MOSI I O VDD 3V3 LOG
33. refer to section 17 3 4 Caution Please see the datasheet of the Ethernet transceiver as well as the phyCARD s Design Guide LAN 051 when designing the Ethernet transformer circuitry The reset input of the Ethernet controller is permanently connected to the reset output signal B of the control management IC U17 on the phyCARD i MX 6 refer to section 4 3 2 9 4 2 MAC Address In a computer network such as a local area network LAN the Media Access Control address is a unique computer hardware number For a connection to the Internet a table is used to convert the assigned IP number to the hardware s MAC address In order to guarantee that the MAC address is unique all addresses are managed in a central location PHYTEC has acquired a pool of MAC addresses The MAC address of the phyCARD i MX 6 is located on the bar code sticker attached to the module This number is a 12 digit HEX value 9 5 12 Interface The Inter Integrated Circuit interface is two wire bidirectional serial bus that provides a simple and efficient method for data exchange among devices The 1 6 contains three identical and independent multimaster Fast mode I C modules The interface of the third module I2C3 extends directly to the phyCARD Connector No other components are connected to this module The following table lists the I C port on the phyCARD Connector Pin Signal I O ISL Description X1A17 I2C SCL O
34. 0 The phyCARD i MX 6 on the phyBASE The following conventions were used in the Jumper column of the jumper table Table 31 J solder jumper removable jumper See Jumper Setting Description Section Jumper JP1 selects the boot device of the phyCARD 1 6 open NAND 1 2 500 external JP1 34 SerialUSB OTG 0580 1 2 Bootconfig from eFUSE 3 4 other settings must not be used with the phyCARD i MX 6 Jumper JP2 connects the input voltage to connector X32 as supply voltage for a backlight JP2 open VCC12V Backlight disabled 17 3 7 2 closed VCC12V Backlight connected to power supply Only 12V DC power supplies allowed Jumper JP3 forces the USB OTG interface of the phyCARD i MX 6 to function either as host master or device slave JP3 open USB OTG ID floating phyCARD i MX 6 in slave mode 17 3 6 or according to the mode configured by software closed USB OTG ID connected to GND phyCARD i MX 6 in host mode Jumper J2 configures the 1 address of the LED dimmer at U21 17 272 closed device address of LED dimmer set to 0x60 17 5 8 open device address of LED dimmer set to 0x61 J2 Jumper 23 configures the address of the touch screen controller at U28 17373 142 device address set to 0x44 17 3 9 243 device address set to 0x41 Table 31 phyBASE Jumper Descriptions J3 please see se
35. 99 9000 og WU BH 05000 0008501 66887 255658 10 05 5 e mp E mmo Sos a wales 0000 0000 oo 80108 0000 HB B 0000 0000 8 5556 0000 85 im gE E mcm un 00 D 8200 un ooo oooco goog 0000 99 Bac 1100 no a nn 00 ooo 00050 zB un 8 UD 00 n E 10000000 0000980000 0000960000 un Om HH FEES 9000080000 m 200006080000 gop 00 QB 10000000 HB 3 Pun m 00 UD B 00 ao O o g 0000 00 gooo 9955500 5 un gt goo 0 oo 995 B a Er B UDponpggp gt ES amp 0000 a E ghs OIE O HE 0 nun 00 2 ES 00000000 O00 onma SNS Q pg B gg 98 Hg 5 a r3 r3 5 00 H anm S 99 88886866 B 0 8 D 152 aH m 2 00 0000 00 oo oo DO BH id EH an 551 B Bnng 00 sed 98 E mmm a E 09500 00 gu T am nog 1060 n B oo 000000 D 00 8 000 EBUscGEw B oo nn a B mes B E 00 B m 00 00 m TED CN INCUN es moo 00 So Ba 8117
36. Camera data X1B15 LVDS CAM RX LVDS VDD 3V3 LOGIC data X1B16 X LVDS CAM nLOCK 0 2 9 c1 CCK output of the Deserializer at U27 Table25 Camera Interface Signal Location at X1 To assists the implementation of a power management the Deserializer s REN input is connected to the 510 DATA EN signal of the i MX 6 Furthermore the nPWRDN signal of the Deserializer is connected to CAM LVDS PRWDN GPIO5 27 5 of the 1 6 Thereby the LVDS Deserializer can be turned off by software 14 1 Signal Configuration 331 J31 selects rising or falling edge strobe for the LVDS Deserializer at U27 used for the camera connectivity of the phyCARD i MX 6 CSIO port Position Description Type 2 3 rising edge strobe used for the LVDS camera OR signals 0402 1 2 falling edge strobe used for the LVDS camera signals Table 26 1 05 Signal Configuration J31 PHYTEC Messtechnik GmbH 2014 1 800 0 45 phyCARD i MX 6 PCA A XL3 xxx 15 Technical Specifications The physical dimensions of the phyCARD i MX 6 are represented in Figure 11 The module s profile is max 11 4 mm thick with a maximum component height of 5 0 mm on the bottom connector side of the PCB and approximately 3 0 mm on the top microcontroller side The board itself is approximately 1 4 mm thick 60mm gt 52mm 02 7 phyCARD XL3 Figure 11
37. GPIO1 6 at T3 of the i MX 6 76 PHYTEC Messtechnik GmbH 2014 L 800e 0 The phyCARD i MX 6 on the phyBASE Caution The backlight voltage VCC12V BL corresponds to the input voltage at power jack X28 There is no protective circuitry for the backlight Close jumper JP2 only if a 12 V power supply is connected to X28 as primary supply for the phyBASE The PWM signal at pin 10 can be used to control the brightness of a display s backlight It is generated by an LED dimmer 021 The LED dimmer is connected to the bus at address 0x60 7 MSB 17 3 7 3 Touch Screen Connectivity As many smaller applications need a touch screen as user interface provisions are made to connect 4 or 5 wire resistive touch screens to the display data connector X6 pins 34 38 refer to Table 35 Two touch screen controllers are available on the phyCARD Carrier Board The audio touch codec at U1 allows connecting 4 and 5 wire touch panels whereas a separate touch panel controller at U28 is suitable for 4 wire touch panels only Because of the dual functionality of the audio touch controller the choice which controller is used to handle the signals from the touch screen is pegged to the audio standard supported by the phyCARD For phyCARDs supporting the AC 97 standard the audio touch controller at U1 processes the touch panel signals For phyCARDs delivering 25 compliant audio signals the dedicated touch panel controller at U28 must be selected
38. PCB 1371 2 with phyBASE Carrier Board PCB 1360 2 PHYTEC Messtechnik GmbH 2014 1 800 0 93 phyCARD i MX 6 PCA A XL3 xxx 94 PHYTEC Messtechnik GmbH 2014 L 800e 0 Index 1 MOG BAS E oe 35 1 e 35 9 E 46 A dio CODEC 79 Audio Interface 37 B Backup 18 Block 1 3 Boot Configuration 26 25 C Camera 1 46 Control Management IC 18 D 0083 SDRAM ies 27 3_1 5 19 DDR3_VREF iIIa 4 19 DDR3 VIT ao adf e 19 Debug Interface 41 Dimensions amp 48 Display 44 27 28 EEPROM Write Protection 28 i E R xi Ethernet 35 gud cq 2 55 G General Purpose I Os 39 GND Connection 53 H tmnt tern 48 PHYTEC Messt
39. Physical Dimensions Note To facilitate the integration of the phyCARD i MX 6 into your design the footprint of the phyCARD i MX 6 is available for download see section 16 1 46 PHYTEC Messtechnik GmbH 2014 L 800e 0 Technical Specifications Additional specifications Dimensions 60 mm x 60 mm Weight approximately 16g with all optional components mounted on the circuit board Storage temperature 40 C to 125 C Operating temperature 0 C to 70 C commercial 40 C to 80 C industrial Humidity 95 r F not condensed Operating voltage VCC 3 3 V Power consumption 2 2 W Supply voltage Condition hardware 3 3V VSTBY OV 256 LP DDR RAM 512 NAND Flash Ethernet 720 MHz Condition software commands frequency at 20 C executed Linux seriell Ethernet communication dd fbtest These specifications describe the standard configuration of the phyCARD i MX 6 as of the printing of this manual PHYTEC Messtechnik GmbH 2014 1 800 0 47 phyCARD i MX 6 PCA A XL3 xxx Connectors on the phyCARD Manufacturer Molex Number of pins per contact rows 100 2 rows of 50 pins each Molex part number lead free 52885 1074 receptacle Matting connectors on the phyBASE Component height 6 mm Manufacturer Molex Number of pins per contact row 100 2 rows of 50 pins each Molex part number lead free 55091 1075 1074 heade
40. TB oo 000000090 8 Boo 00 DD H m BR 0000 B 000 gt 00 cR a mad i 00 pang nn HI oo ca BB 1 260000 ia cab a maan usan anan oes Es a Bese Hoo ca anang Og E Scc EI oo gg an 50 ondt ga B da g 1 m 00 0005 m 5 15 D 00 00 B o 00 ng Figure 23 USB Interface at Connector X29 The USB OTG interface of the phyCARD is accessible at connector X29 USB Mini AB on the carrier board The phyCARD i MX 6 supports the On The Go feature The Universal Serial Bus On The Go is a device capable to initiate the session control the connection and exchange Host Peripheral roles between each other This interface is compliant with USB revision 2 0 Jumper JP3 configures the OTG operating mode By default this jumper is open which leaves the USB OTG ID pin floating and thus configuring the OTG interface as slave Alternatively this jumper can be closed connecting the signal X UID to GND and configuring the OTG interface as host Typically the configuration of a connecting device as host or slave is done automatically via a USB OTG cable However given the limited number of OTG enabled devices in the embedded market this jumper is provided to either simulate an OTG cable or force the OTG interface into host
41. USB 5 below D20 D27 40 pin pins 16 0 USB2 X6 and 17 D D17 D24 20 pin header row pins 19 USB3 X8 D and 20 D D18 D25 20 pin header row pins 19 USB4 X9 D and 20 D D19 D26 USB6 X7A bottom USBA D21 D28 USB7 X7 B top USBA D22 D29 Table 33 Distribution of the USB Hub s U4 Ports Pin Signal name Description 1 USB5 VBUS USB5 Power Supply 3 USB5 D USB5 Data 5 USB5 0 USB5 Data 2 USB1 VBUS USB1 Power Supply 4 USB1 D USB1 Data 6 USB1 0 USB1 Data 7 8 GND Ground 9 10 NC Not connected Table 34 Universal USB Pin Header X33 Signal Description PHYTEC Messtechnik GmbH 2014 1 800 0 71 phyCARD i MX 6 PCA A XL3 xxx 17 3 6 USB OTG Connectivity X29 ce RS o C 99 3 9 T a OD 9 00000 J USBOTG _ 00 m kei al alo o ORRO 1 o Imm a ooo 00090000 0 00 T 00 000000 996 foo sgg BEEE 0000 on ELE x Gang cc 9 ooroo 0000 O0 onono n BRS un 0000 99 E
42. must be first initialized see RTC Data Sheet for more information Use of a coin cell at BAT1 allows to buffer the RTC extending on the phyCARD i MX 6 to the input port PWRON of the PMIC U29 and port P3 2 of the CMIC U13 90 PHYTEC Messtechnik GmbH 2014 1 800 0 The phyCARD i MX 6 on the phyBASE 17 3 17 PLD at U25 The phyBASE is equipped with a Lattice LC4256V PLD at U25 This PLD device provides the following features Power management function section 17 3 2 Signal mapping and configuration of the sound devices at U1 for AC 97 and at U17 for I S section 17 3 8 Signal mapping SPI chip select and interrupt to the extension or display connectors sections 17 3 10 and 17 3 11 Touch Signal mapping to the discrete touch controller at U28 or to the touch controller integrated in the audio codec at U1 section 17 3 7 3 PHYTEC Messtechnik GmbH 2014 1 800 0 91 phyCARD i MX 6 PCA A XL3 xxx 17 3 18 Carrier Board Physical Dimensions UJUJOE D3 2mm CN LO 5 200 f Y NA i 5 Figure 31 Carrier Board Physical Dimensions Please contact us if a more detailed dimensioned drawing is needed to integrate the phyBASE into a customer application 92 PHYTEC Messtechnik GmbH 2014 1 800 0 Revision History 18 Revision History Changes in this manual 21 08 2014 Manual Preliminary edition L 800e 0 Describes the phyCARD i MX 6 SOM
43. 1 MX 6 are supposed to be powered while the phyCARD i MX 6 is in suspend mode or turned off This situation might result in voltages at the IO pins of the phyCARD i MX 6 which are sourced from the supply voltage of the peripheral device and which cause a current flow into the controller To avoid these voltages bus switches powered by VDD 3V3 LOGIC on the phyCARD side should be used Alternatively the bus switches output enable to the SOM be controlled by 3V3 LOGIC Please refer to the phyCARD Design In Guide LAN 051 for more information about using the serial interfaces of the phyCARD i MX 6 in customer applications PHYTEC Messtechnik GmbH 2014 1 800 0 31 phyCARD i MX 6 PCA A XL3 xxx 9 1 Universal Asynchronous Interface The phyCARD i MX 6 provides a high speed universal asynchronous interface with up to 4 MHz and hardware flow control RTS and CTS signals The following table shows the location of the signals on the phyCARD Connector Pin Signal 1 0 51 Description X1A39 UART 00 LOGIC Serial data transmit signal UART 3 X1A40 X UART RTS VDD 3V3 LOGIC Request to send UART 3 X1B39 X UART RXD I VDD 3V3 LOGIC Serial data receive signal UART 3 X1B40 X UART CTS I VDD 3V3 LOGIC Clearto send UART 3 Table 12 Location of the UART Signals The signals extend from UART3 of the 1 6 directly to the phyCARD Connector without conversion to RS 23
44. 22 of the i MX 6 Table 11 Location of SD MMC Card Interface Signals PHYTEC Messtechnik GmbH 2014 1 800 0 29 phyCARD i MX 6 PCA A XL3 xxx Note In order to follow the power up and power down sequencing mandatory for the i MX 6 the SD MMC card interface should be supplied by the 1 0 supply voltage 3V3 LOGIC which is brought out at pins X1A5 and X1B5 of the phyCARD Connector Use of VDD 3V3 LOGIC ensures that the interface is only supplied when the supply voltages of the 1 MX 6 are stable Caution The current draw for VDD_3V3_LOGIC must not exceed 500 mA If devices with a higher power consumption are to be connected to the GPIOs of the phyCARD i MX 6 they should be switched on and off by use of 3V3 LOGIC This way the power up and power down sequencing will be considered even if the devices are not supplied directly by VDD 3V3 LOGIC The 1 6 5 requires strict separation of the supply voltages generated on the phyCARD i MX 6 and the supply voltages used on the carrier board custom application To avoid voltages which are sourced from the supply voltage of the SD MMC card interface bus switches powered by VDD 3V3 LOGIC on the phyCARD side should be used Alternatively the bus switches output enable to the SOM can be controlled by VDD_3V3_LOGIC please refer to section 4 4 for more information Please refer to the chapter SD MMC in the phyCARD Design In Guide for more informa
45. 28 gg pfo 82 0000 00 B 5 E gg 00 0520 pn E 00 00 oo BB 0000 Soo ELE 9516 tg HUS OO on un ma 00600 E Spoon 00 ii B 000000 itg 000 oo 009 Og 6 4 00 000 sms oo oo 02 Wee 4 00 un m IECIT NEN a ad EE bu 000025 cao t oo 00 200 00000009 gll Boo DB nn un Rom EISE g SS m nn B fon 0 m UU c mad 0500 8 E 00 un 00 8 amp F 1 H 00 i pz B 000 co 1 ca ts ed n n BB H 5857 co i Un t tO uL un H B oo TO oo oo un m ooo Boo cag un 259096 ra un oo SER m 00 NE H o 00 gg D D 00 00 Figure 30 RTC with Battery Buffer 00 00 9 For real time or time driven applications the phyBASE is equipped with an 8564 Real Time Clock at U3 This RTC device provides the following features e Serial input output bus address 0x51 7 MSB Power consumption Bus active 400 kHz 1mA Bus inactive CLKOUT inactive 275 e Clock function with four y
46. GPIO Connector Selection Pin Signal Name Description 1 VCC5V 5 V power supply 2 VCC5V 5 V power supply 3 VCC3V3 3 3 V power supply 4 VCC3V3 3 3 V power supply 5 GND Ground 6 GND Ground 7 I2C SDA Data 8 I2C SCL Clock Hardware Introspection Interface 4 For internal 10 GND Ground 11 SPI SS SLOTO X8A SPI chip select extension port 0 SPI SS SLOT1 X9A SPI chip select extension port 1 12 SPI1 MOSI SPI master output slave input 13 SPI1 SCLK SPI clock output 14 SPI1 MISO SPI master input slave output 15 SPI1_RDY SPI data ready input master mode only 16 SLOTO_IRQ X8A Interrupt input extension port 0 SLOT1_IRQ X9A Interrupt input extension port 1 17 GND Ground 18 GND Ground 19 USB3_D X8A USB3 Data D USB4_D X9A USB4 Data 0 20 USB3 0 USB3 Data D USB4_D X9A USB4 Data D Table 45 PHYTEC Extension Connectors X8A X9A T 3 84 GPIOO_IRQO GPIO2 24 at 223 and GPIO1 IRQ1 GPIO1 6 at T3 of the i MX 6 refer to section 10 LEDs D18 and D25 signal use of the USB3 interface X8A LEDs 019 and 026 signal use of the USB4 interface X94 PHYTEC Messtechnik GmbH 2014 L 800e 0 The phyCARD i MX 6 on the phyBASE 17 3 13 Secure Digital Memory Card MultiMedia Card X26 Mol s ol aen 09000 Q j 90 Q 000 E 20900 50 oO LO O22900 RB n dos
47. UART3 of the 1 6 The TTL level signals from the phyCARD i MX 6 are converted to RS 232 level signals As defined in the specification of the X Arc bus the serial interface allows for a 5 wire connection including the signals RTS and CTS for hardware flow control Figure 20 below shows the signal mapping of the RS 232 level signals at connector P1 The RS 232 interface is hard wired and no jumpers must be configured for proper operation vU N a Figure 20 68 2 7 3 8 5 TxD RS232 RTS RS232 RxD RS232 CTS RS232 GND RS 232 Connector P1 Signal Mapping PHYTEC Messtechnik GmbH 2014 L 800e 0 17 3 4 Ethernet Connectivity X10 The phyCARD i MX 6 on the phyBASE o0 LJ 5 eO 00000 o 000000 98000000 un BBB 8 0053006 gg 00 bong 0000 0 up gas aa 08 020255655508 S gas 29 Um g 0090 0000 25200588962 2 666 gt 8 mp g E 0000 0000 050 nn Do Soo Moo o 0000 00 0000 EE m 1009 0000 BOO 0060000 __ m LS BO 014 9 eme D B 0000 mm
48. X8A and X9A provide an easy way to add other functions and features to the phyBASE Standard interfaces such as USB SPI and as well as different supply voltages and one GPIO are available at the pin header rows The pinout of the extension connectors is shown in Table 45 As can be seen in Figure 26 the location of the connectors allows to expand the functionality without expanding the physical dimensions Mounting wholes can be used to screw the additional PCBs to the phyBASE The extension connectors share the SPI interface and the GPIOs of the X Arc bus with the display data connector X6 Therefore switches 7 and 8 of DIP Switch S3 must be configured to map the signals to the desired connector The following table shows the possible configurations 1 PHYTEC offers a variety of extension boards PEBs to add new features such as CAN additional GPIOs or Ethernet etc Please visit our web side or contact our sales team PHYTEC Messtechnik GmbH 2014 L 800e 0 83 phyCARD i MX 6 PCA A XL3 xxx Button Setting Description S3 7 0 0 550 6 00 IRQ gt extension 0 X8A S3 8 SS1 GPIO1 IRQ gt extension 1 X9A 0 1 SSO GPIOO IRQ gt extension 0 X8A SS1 GPIO1 IRQ gt display data connector 1 x SSO GPIOO IRQ gt extension 1 X94 SS1 GPIO1 IRQ gt display data connector Table 44 SPI and
49. an optional EEPROM or other devices additional information on the interfaces can be found in section 17 3 9 for internal use only Power on off signal to allow for an ON OFF switch on a front panel It nPWR KEY connects to the nPWR KEY input of the PLD at U25 parallel to the ON OFF switch S2 Can be used to enable or disable the display or to shutdown the backlight nDISP_ENA is connected to the corresponding input of the PLD at U25 x PWM output to control the brightness of a display s backlight 0 dark 100 bright The signal is derived from the first output LEDO of the LCD dimmer at U21 Analog light sensor input The analog light sensor input at pin 40 extends to an 8 bit A D converter 15 ANA which is connected to the I C bus at address 0x64 To get the maximum adjustment range the output voltage of an applicable light sensor should range from 0 V to VRef 3V3AD Table 36 Auxiliary Interfaces at PDI Data Connector X12 This signal is also available at the display power connector X32 refer to section 17 3 7 2 for more information PHYTEC Messtechnik GmbH 2014 1 800 0 75 phyCARD i MX 6 PCA A XL3 xxx The connection of the SPI interface and the display interrupt input to the X Arc bus is shared with the SPI interfaces and the interrupt inputs on the extension connectors X8A and X9A Because of that these signals have to be mapped to the display data connector by configuring switches 7 and
50. g oo na UD 3 Q na 88 88 5280 5 nago E Tang 3 E B 058 gg 0000 O BE T af un 0 Ss fe E 85 E B 00 0000 0 05 tm BH un 0520 3 9 00 DD gg 00 woo ee anB Bu un Soo a ag BB EB a m g ooo oo oo 4 200 00 E ng go E too uu 0000006 ggg a 00 Q mo 4 000 00 BB n 8 du gp 8 5 000 0 00 B B Es oo oo oo TON NRI INCL NE 900 D on 00000009 gg p 23 un E EE an 8 025 m 00 oo Good m bN 00 1 B J24 5 p moona onn 2 9 aa Baca 85 Meee gs H i 859 un oS open r3 E un nn 0025 un oo un 00 0 DD Owens Oa 00 Figure 24 Universal LVDS Interface at Connector X6 The various performance classes of the phyCARD family allow to attach a large number of different displays varying in resolution signal level type of the backlight pinout etc In order not to limit the range
51. mode when OTG operation is not required LED D49 signals VBUS power supply which is generated via a power distribution switch TPS2042 U29 of the carrier board The power distribution switch is controlled via the signals X USB HS nPSW and X USB HS FAULT which extend directly from the phyCARD connector 72 PHYTEC Messtechnik GmbH 2014 L 800e 0 The phyCARD i MX 6 on the phyBASE 17 3 7 Display Touch Connectivity X6 X32 O 9 D Hx290 o9 o P 0000 0 c c ga 00000 o D ololo 9909 RB ad O O 290 0000 naga Sf Bess 00 000900 w c x 00 HB B8B omo 820000000059 02055506 98 ggg UD 10000 Ens 000 noa gt go 2 0 030 ncc 9 2ununu ma B uu mama 000 65606 ooo B HEB n 008 Dui 0000 au nn oooo 0000 00 B D U HB S 08 B oo pooo pooo i 00 00 omon 00 MAR apu UU um 4 00 S 0509 050 an zB 8 00 00 10000000 0000960000 0000960000 Eh ub 0000060000 yn je Bd 0000090000 Sma glum
52. of the X Arc bus with the functional grouping of the signals while Table 3 and Table 4 provide an overview of the pinout of the phyCARD Connector with signal names and descriptions specific to the phyCARD i MX 6 They also provide the appropriate signal level interface voltages listed in the SL Signal Level column and the signal direction The Freescale Semiconductor 1 6 is a multi voltage operated microcontroller and as such special attention should be paid to the interface voltage levels to avoid unintentional damage to the microcontroller and other on board components Please refer to the Freescale Semiconductor i MX 6 Reference Manual for details on the functions and features of controller signals and port pins 8 PHYTEC Messtechnik GmbH 2014 L 800e 0 Pin Description Signal Pin Pin Signal gt VCC VCC In amp 4 In VCC VCC In FS 42 VCC VCC In lt GND GND Out VCC LOGIC VCC LOGIC Out VSTBY In In nRESET InRESET OUT GND GND Out LVDS LVDS_TX1 Out o Out LVDS TXO ILVDS TX1 Out a amp LVDS_TX2 LVDS_TX3 Out amp 24 Out LVDS_TX2 1 08 _ Out E GND GND 5 Out LVDS_TXCLK In D Out LVDS TXCLK In ra Camera Out Out J 9 C4 Bi CLK 2 DATA Bi Out Out n 9 Out In 2 iu Out In 2 A USB Host 5 n n 5 cri Bi Out e Bi Bi BH 2 Bi Bi US
53. on OH DEJCOEO 0000000 0000000 0000000 0000000 0000000 0000000 o on o oco Lad D U res LI im a L on on IM a M S 1 mp o gu xcd OCU E gt b MU Figure 7 Jumper Locations bottom view PHYTEC Messtechnik GmbH 2014 L 800e 0 15 phyCARD i MX 6 PCA A XL3 xxx The jumpers J solder jumper have the following functions Jumper Description Type Chapter J3 connects the write protect input of the on board EEPROM at U10 with GND If this jumper is not populated the EEPROM is write protected OR feded closed EEPROM is not write protected 0402 open EEPROM is write protected The protection can be changed by the EEPROM WP GPIO3 19 signal J31 selects rising or fallin
54. on chip RTC and different power management functionalities It is connected to the i MX 6 via the bus I2C1 The I2C1 addresses for the PMIC at U29 is 0x58 page 0 and 1 and 0x59 page 2 and 3 Please refer to the dialog SEMICONDUTOR DA9063 datasheet for further information 4 3 2 Control Management IC CMIC U17 The control management IC at U17 is monitoring the supply voltages and generates necessary control signals for the 1 6 processor in respect to the different input signals It also ensures the correct power sequencing during powering up of the module and configures the boot mode of the i MX 6 s section 6 U17 generates a reset if the on board voltage generator senses a voltage drop on the primary supply voltage and generates a reset signal or if a reset is applied at pin X1A7 of the phyCARD Connector 18 PHYTEC Messtechnik GmbH 2014 L 800e 0 Power Requirements 4 3 3 Power Domains The PMIC has two input voltage rails VDD_3V3 and VSTBY IN as can be seen in Figure 8 VDD 3V3 is directly connected to the primary voltage input pins VDD 3V3 of the phyCARD i MX 6 whereas VDD 3V3 LOGIC is attached to the primary voltage input pins 3V3 via switch 017 017 is controlled by the PMIC at U29 Not all devices on the phyCARD i MX 6 are supplied by the internally generated voltages Some devices such as the Ethernet PHY the LVDS FlatLink transmitter etc are powered the primary input voltage VDD_3V3 The follo
55. pairs After a few alternations components can be removed with the solder iron tip Alternatively a hot air gun can be used to heat and loosen the bonds PHYTEC Messtechnik GmbH 2014 1 800 0 61 phyCARD i MX 6 PCA A XL3 xxx ag a IH tf th OE ER 0000 Let B a a NE CAs mmg ahi CNH 008 ti 0000 a ao 00 2 o o 00 Expansion 1 BB 00 gee c UD J gULO re M lt lt 9 quvo ud Hn Bg LO TEE an 00 ORO ORC 0000 JO gt lt Be C 00002 m 000009 un 00000000 3 032 B 00000000 c a 195 U16 020 00 000 un 1000000 0000 g 58 00 m 00000000 g 53 00000000 8 00000000 6 phyCARD XL cooling area SBBBBHB mum ag UAE UD qu 00 a a un 00 Bn H 00000000 OFF m a 00 am D gs A 5 Figure 15 phyBASE Jumper Locations 62 00000000 Messtechnik GmbH 2014 0 1 800
56. s imi om m n 28 a E E B HO 5 BB oe I 0 mna ooo m E 00959 4 m gos 50 poj 50 soos on 5 88 m a ons 9 Dn nn 00 un 9 Figure 22 Components supporting the USB Host Interface The USB host interface of the phyCARD is accessible via the USB hub controller U4 on the carrier board The controller supports control of input USB devices such as keyboard mouse or USB key The USB hub has 7 downstream facing ports Two ports extend to standard USB connectors at X7 dual USB A Two more ports connect to 9 pin header row X33 These interfaces are compliant with USB revision 2 0 The remaining ports are accessible at the display data connector X6 and the extension connectors X8A and X9A These three interfaces provide only the data lines D and D They do not feature a supply line Vbus 70 PHYTEC Messtechnik GmbH 2014 1 800 0 The phyCARD i MX 6 on the phyBASE LEDs 016 to 029 as well as 030 and 050 signal use of the USB host interfaces Table 30 shows the assignment of the LEDs to the different USB ports Table 33 shows the distribution of the seven downstream facing ports to the different connectors whereas Table 34 shows the pinout of USB host connector X33 USB hub Connector Connector Type LEDs port USB1 X33 9 pin header row see table D16 D23
57. the chapter GPIOs in the phyCARD Design In Guide for more information about how to integrate the GPIO pins in your design 38 PHYTEC Messtechnik GmbH 2014 L 800e 0 Debug Interfaces 11 User LEDs The phyFLEX i MX 6 provides two user LEDs on board a red D2 and a green D1 D2 can be controlled by setting GPIO3 20 pad 020 and D1 can by controlled by setting GPIO1 7 pad GPIO_7 to the desired output level A high level turns the LED on a low level turns it off PHYTEC Messtechnik GmbH 2014 1 800 0 39 phyCARD i MX 6 PCA A XL3 xxx 12 Debug Interface X3 The phyCARD i MX 6 is equipped with a JTAG interface for downloading program code into the external flash internal controller RAM or for debugging programs currently executing The JTAG interface extends to a 2 54 mm pitch contact pad row at X3 which allows for attaching a 2x10 pin 2 54 mm pitch pin header on the edge of the module PCB Figure 9 and Figure 10 show the position of the debug interface JTAG connector X3 DEBUG INTERFACE X2 on the phyCARD i MX 6 module Software debugging via DEBUG INTERFACE connector X2 requires special tools hardware software For further information please see the MX 6 Reference Manual _UART2 on 0 gogo 082 000 ud 0 OFF CED CROCI ndn OH
58. the module Please consider that any change of the default BCFG configuration can also influence other boot modes which might result in faulty boot behavior For further information about the different boot modes and the influence of the BCFG pins please see the MX 6 Reference Manual The following table shows to which level the CMIC sets the different configuration signals for the boot modes High Z means that the CMIC sets the signal to high impedance and thus the value of the configuration resistor is used Boot BOOT MODE BCFG1 7 BCFG2 1 Description Mode 1 0 0 0510 1 High Z NAND 1 0b10 0 High Z 500 2 0 01 High Z High Z USB OTG 3 0500 High Z High Z eFUSE Table 9 Boot Configuration Signals generated by the CM Default settings are in bold blue text 26 PHYTEC Messtechnik GmbH 2014 1 800 0 System Memory 7 System Memory The phyCARD i MX 6 provides three types of on board memory e 2 Banks DDR3 RAM 512 MB DDR3 SDRAM up to 4 GB NAND Flash VFBGA 256 MB up to 4 GB 2 4 kB The following sections of this chapter detail each memory type used on the phyCARD i MX 6 7 1 DDR3 SDRAM U2 U9 The RAM memory of the phyCARD i MX 6 is comprised of up to two 64 bit wide banks each of four 16 bit wide DDR3 SDRAM chips Bank 1 U2 U5 Bank 2 U6 U9 The chips are connected to the special DDR interface called Multi Mode DDR Controller
59. web side It provides recommendations as to development of customized carrier board target hardware in which the phyCARD i MX 6 and other phyCARDs can be deployed the link Carrier Board within the category Dimensional Drawing leads to the layout data as shown in Figure 12 It is available in different file formats different support packages are available to support you in all stages of your embedded development Please visit http www phytec de de support support pakete html or http www phytec eu europe support support packages html or contact our sales team for more details PHYTEC Messtechnik GmbH 2014 1 800 0 Hints for Handling xii Ref Des 10 45mm alle mit Toleranz von 0 1mm Figure 12 Footprint of the phyCARD i MX 6 PHYTEC Messtechnik GmbH 2014 1 800 0 51 phyCARD i MX 6 PCA A XL3 xxx 16 2 Handling the phyCARD i MX 6 X Modifications on the phyCARD Module Removal of various components such as the microcontroller and the standard quartz is not advisable given the compact nature of the module Should this nonetheless be necessary please ensure that the board as well as surrounding components and sockets remain undamaged while de soldering Overheating the board can cause the solder pads to loosen rendering the module inoperable Carefully heat neighboring connections in pairs After a few alternations components can be removed with the solder
60. 0000 57 nami an 088899889 S8 SS ooo Um c n nn RB r 0520 Coo oo EB 0000 Bane oo 9 Reset 00 00 151 B apo 00 BB H a B nus 5 op wi HH ann 88 sEu a Bm O 00 050000 ggg 00 S 00 5 2009 Og 000 u P B 6 000 00 Ses imm 00 00 00 m aaa a SS ooo 55 us of on Ej Te 2E g un 000000090 Boo 00 OO OO 10 H 5 00 B 00 E m 00 58 U25 i 5 was O an an i S nn 00 pono 0084 21 8 E E Bs oo Boos m E 28 0000 E sB g 59 pac a o un 5 0 B a BBE on E um oo 00 i EC E 00 00 on hae to 4 po Er nn im 9 8 00 np 00 o nn Figure 29 System Reset Button 51 The phyCARD Carrier Board is equipped with a system reset button at S1 Pressing this button will toggle the X nRESET IN pin X1A7 of the phyCARD SOM low causing the module to reset Additionally a peripheral reset is generated by the PLD U25 on the
61. 2 Ls _ 95956 68 00 ma 7 oO Fi 0 95 b 1 gp DD B Boog m n anc 259505 p i D 00 nnnn ps 9 DU 0 nn o O a 66 Bb 524 21 Ethernet Interface at Connector X10 The Ethernet interface of the phyCARD is accessible at an RJ45 connector X10 on the carrier board Due to its characteristics this interface is hard wired and can not be configured via jumpers The LEDs for LINK green and SPEED yellow indication are integrated in the connector PHYTEC Messtechnik GmbH 2014 L 800e 0 69 phyCARD i MX 6 PCA A XL3 xxx 17 3 5 USB Host Connectivity X6 X7 X8 X9 X33 Front S S Oo Li ooooo D 000 00 5 B a 0000 9 00000000 B E 0 8970 un HB 0900000 108 888833 88 85 888 L 119 oom 00688888586 59 88 88 E 2 om ag 02000 emm 8895 9669600 558 dom 000 8 oc 0000 Mo
62. 2 level External RS 232 transceivers must be attached by the user if RS 232 levels are required 9 2 USB OTG Interface The phyCARD i MX 6 provides a high speed USB OTG interface which uses the 1 6 embedded HS USB OTG PHY Because of the processor is not featuring the USB over current detection GPIO1 20 can be used as USB OTG over current input signal The signalis active low For self powered devices an external USB Standard A for USB host or USB mini AB for USB OTG connector is all that is needed to interface the phyCARD i MX 6 USB OTG functionality To attach devices which require the VBUS supply voltage an external power logic or charge pump capable of sourcing 5 V power must be provided on the carrier board Signal X nUSB OTG X1A23 allows control of the external power logic After reset signal X_nUSB_OTG_PWR is low meaning active Therefore an external power switch is enabled and booting via USB is possible The applicable interface signals can be found on the phyCARD Connector as shown in Table 13 32 PHYTEC Messtechnik GmbH 2014 1 800 0 Serial Interfaces Pin Signal 1 0 51 Description USB power switch output open drain low active USB OTG over current input signal e X1A23 X nUSB OTG PWR VDD 3V3 LOGIC X1A24 X nUSB OC VDD 3V3 LOGIC low active X1A26 X USB VBUS I USB VBUS voltage X1A27 X USB DM I 0 USB transceiver cable interface D X1A28 X U
63. 2014 1 800 0 87 phyCARD i MX 6 PCA A XL3 xxx 17 3 15 System Reset Button S1 m Ped EHO Off c A 5 a ooooo o gt 2000 Q O22900 e B o un 0000 00000000 m gE HE 0600 n Bann 00 000000 SINE 00 dada ae foo BEB co n 0000 n 5 HB og 0000 000000 0096 0000 p 08HBEBEBSB 5 65 59556 Ha 00 Un we ScEmDUHagBES 29 BH B BB 0000 gry 0000 9 9988 00 0000 0200 aun 2m g Gg un 0000 fef 0000 009 am 05 Band aim D OD 20 Cemeg _ gung 1000 0000 2 eA T 00 B un nn 8 nn 0 oo 00 00 n 00000000 00009080000 ESO 0000960000 B un 0000060000 Je BH 2000080000 Sma gm BB 010000000 Bm DE 00 00 ema 8555800 9 82658 g a 2 0000000000899 E 8900 8 m E Ss DD Bn m N BB B ggg 1000000 05100 55 SIME oto hg o gio c 5 a s 75 prn an pes n
64. 4 for more information 6 PHYTEC Messtechnik GmbH 2014 L 800e 0 Pin Description 2 Pin Description Please note that all module connections are not to exceed their expressed maximum voltage or current Maximum signal input values are indicated in the corresponding controller manuals data sheets As damage from improper connections varies according to use and application it is the user s responsibility to take appropriate safety measures to ensure that the module connections are protected from overloading through connected peripherals As Figure 4 indicates all X Arc bus signals extend to one surface mount technology SMT connector 0 635 mm lining on side of the module referred to as phyCARD Connector This allows the phyCARD i MX 6 to be plugged into any target application like a big chip The numbering scheme for the phyCARD Connector is based on a two dimensional matrix in which column positions are identified by a letter and row position by a number Pin 1A for example is always located in the upper left hand corner of the matrix The pin numbering values increase moving down on the board Lettering of the pin connector rows progresses alphabetically from left to right refer to Figure 4 The numbered matrix can be aligned with the phyCARD i MX 6 viewed from above phyCARD Connector pointing down or with the socket of the corresponding phyCARD Carrier Board user target circuitry The upper left hand corner of the numbered m
65. 8 of DIP Switch S3 Table 37 shows the required settings The default setting does not connect the SPI interface and the GPIO Interrupt pin of the X Arc bus to the display data connector Settin Button 4 Description S3 7 0 0 SSO GPIOO IRQ gt extension 0 X8A 53 8 551 6 101 gt extension 1 X9A 0 1 SSO GPIOO IRQ gt extension 0 X8A 551 6 101 IRQ gt display data connector X6 1 SSO GPIOO IRQ gt extension 1 X9A SS1 GPIO1 IRQ gt display data connector X6 Table 37 SPI and GPIO Connector Selection 17 3 7 2 Display Power Connector X32 The display power connector X32 AMP microMatch 8 188275 2 provides all supply voltages needed to supply the display and a backlight as well as one PWM signal for brightness control Pin Signalname 1 0 SL Description 1 GND Ground 2 VCC3V3 0 3 3V 3 3V power supply display 3 GND Ground 4 VCC5V 0 5V 5V power supply display 5 GND Ground 6 VCC5V 0 5V 5 V power supply display 7 GND Ground 8 VCC5V 0 5V 5 V power supply display 9 GND Ground 10 LS_ BRIGHT 0 3 3V PWM brightness output 11 VCC12V BL 0 9 38 Backlight power supply 12 VCC12V BL 0 9 38 Backlight power supply Table 38 LVDS Power Connector X32 Signal Description make 12 BL available at X32 jumper JP2 must be closed GPIOO 1800 6 102 24 at J23 and GPIO1 IRQ1
66. 9 5605 2 030 050 0000 5 2 900 0000 an 0000 ja 00 5 0000 0000 ooon 00 IMBA D 0000 n OBEBD moro 2 Bong 0000 00 5965 20600 5 28 88 BG gg an 0 10000000 0000980000 ils 0000980000 0000040000 HH 2000600000 gili g Sg 10000000 BE on e ds 8 nn aus BB m uid DO pp ES DHA TO 50000 gp 2 008 er um 00000009 1m 58 _ du on 0 BB sms gg B 010 00 gn SA BB uu UL gagonnno a8 LS ON OFF 29200 95 89896568 e LE 11521 S505 oo pong c m 00 gg 00 oo dE 25 SIE I a oo asin B Boo 00 Eod CO B mmm a a DOBD 10 n mao n Sogo i B 00 ggg UD ES 00 2009 82458 mnn mg Cun n 00 00 8 8 c EB 00 n ooo E an 00 gg oo CE SOS B B 00050 oe mm z EBu es He Bm 00000009 foo on ES See B E 26 m 5 i S we 00 poi a Bn nd i i s E o Tod ein 1 B oo cd ug e a 9 Tag
67. B nn a B Or oo sama E 000006890000 Bi IT un E 00 Cio gum 6900 00 BD 00 B na 7 00 H M E S allel BS Bn A n d BB 4 Se s ooo 00 J4 EB p 00 6230 010 EL SN zi B qo co fom un hy pes 58 H p 0005 B n 1 cw os i H H BBEB coc E 48 acr ca pos H o The audio interface provides a method of exploring the i 6 s 125 capabilities Depending on the audio standard supported by the phyCARD the audio interface on the X Arc bus connects either to a Wolfson WM9712L audio touch controller U1 or a TI TLV320AIC3007 U17 Audio CODEC on the carrier board The audio touch controller at U1 processes AC 97 compliant signals while signals according to the IS standard are handled by the Audio CODEC at U17 Switches 1 and 2 of DIP Switch S3 select which codec is used to process the audio signals Table 40 shows the different options 78 PHYTEC Messtechnik GmbH 2014 L 800e 0 The phyCARD i MX 6 on the phyBASE Button Setting Description S3 1 Depending on the audio standard supported by the phyCARD the audio and touch 3 2 panel signals are either processed by the Wolfson audio touch contrl at U1 7 AC 97 or the TI Audio CODEC at U17 125 and dedic
68. B Host In GND GND Bi SDIO DO SDIO 01 Bi Bi SDIO D2 SDIO D3 Bi Out SDIO CLK SDIO CMD Bi GND GND SD MMC Out In Out GND GND Out In UART In Out UART GND GND gt L Bi 125 SEL AC97 INT AC97 I2S Bi gt lt Out AC97 I28 SDATA OUT AC97 I28 SYNC Out S 2 In 97 125 SDATA IN AC97 2S nRESET J jy GND GND 2 Bi 500 In SD MMC Bi Bi J GPIO In for internal use only Bi GND GND Boot Opt In Boot Opt Table 2 X Arc Bus Pinout PHYTEC Messtechnik GmbH 2014 1 800 0 9 phyCARD i MX 6 PCA A XL3 xxx Note SL is short for Signal Level V and is the applicable logic level to interface a given pin Those pins marked as N A have a range of applicable values that constitute proper operation Please refer to the phyCARD Design In Guide LAN 051 for layout recommendations and example circuitry Pin Row X1A Pin Signal 1 0 SL Description 1A VDD 3V3 I Power 3 3 V Primary voltage supply input VDD 3V3 I Power 3 3 V Primary voltage supply input 3A VDD 3V3 I Power 3 3 V Primary voltage supply input 4A GND Ground 0 V 5A VDD 3V3 LOGIC 0 Power VCC Logic output 6A FEEDBACK 0 Power Feedback output to indicate the supply voltage required floating i
69. CB to reset peripherals such as the USB Hub etc 88 PHYTEC Messtechnik GmbH 2014 1 800 0 The phyCARD i MX 6 on the phyBASE 17 3 16 RTC at U3 0 o9 o9 H 5 IO coooo gg Vll El 0 O 00000 o K HB o Q o a Q 9 088980 Bun 0000 00 000000 Bc rp 000000 on S008 00 as BB 888 0000 BBBH 1 uL 800 0 e8660 ABB DD 0000 0000 pn E un nn 3d 00 0 Jagong 0000 558 9 gg cgp omm 5 20508888935 BBBBOO me an Sm aman 0000 ss em 555 Soe mes 8 EBBS i 00 00 uum eu oco Hz End PL 00 00 0900 60000 2 mu HW m un 00 00 n nm 00000000 00000650000 TES 0000980000 B nn py 0000060000 ug 3 0000090000 Sma 91000 g 9610110000 oo UD gg amp Bn n un 5055500 80000 go gu OCU go 995 B Sooo 3 mm ada d lr a ooo n B gm 5 0000000000900 pmm O D O a a 02000 oq oo a 00000000 0 a oto JE BUD
70. D Connector to the PDI Data Connector X6 Along with the display and touch screen interface signals other useful interfaces such as USB etc are available at PDI data connector X6 Table 36 lists all miscellaneous signals and gives detailed explanations The following table shows the pin out of the PDI s display data connectors at X6 Pini Signal name I O SL Description 1 Seli SULA 0 33V SPI1cock 2 SPI MISO I O 3 3V SPI 1 master data in slave data out 3 SPI1 MOSI O I 3 3V SPI 1 master data out slave data in 4 Aa DISP 0 3 3V SPI 1 chip select display 5 DESAKU 1 3 3V Display interrupt input 6 VCC3V3 0 3 3V Power supply display 7 I2C SCL 1 0 3 3V I Cclock signal 8 12C_SDA 1 0 3 3V data signal 9 GND Ground 10 15 BRIGHT 0 3 3V PWM brightness output 11 VCC3V3 0 3 3V Logic supply voltage 12 nPWR KEY I 3 3V Power on off button 13 nDISP ENA 0 3 3V Display enable signal Hardware Introspection Interface 14 PHE 1 0 337 forinternal use only 15 GND Ground 16 USB2_D 1 0 3 3V USB2 data 17 USB2_D 1 0 3 3V USB2 data 18 GND Ground 19 TXOUTO 0 3 3V LVDS data channel 0 negative output 20 TXOUTO 0 3 3V LVDS data channel positive output 21 GND Ground 22 TXOUT1 0 3 3V LVDS data channel 1 negative output Table 35 Display Data Connector X6 Signal Description
71. Ds Their function is listed in the table below See LED Color Description Seton D16 yellow USB1 amber led D17 yellow USB2 amber led D18 yellow USB3 amber led D19 yellow USB4 amber led D20 yellow USB5 amber led D21 yellow USB6 amber led D22 yellow USB7 amber led D23 green USB1 green led D24 green USB2 green led 17 3 5 D25 green USB3 green led D26 green USB4 green led D27 green USB5 green led D28 green USB6 green led D29 green USB7 green led D30 red Active Suspend status LED of the USB hub at U4 Hi Speed indicator LED for USB hub s upstream port connection speed D50 red D49 red Indicates presence of VBUS at the USB OTG interface 17 3 6 037 green 5 Vsupply voltage for peripherals on the phyBASE D38 green supply voltage of the phyCARD D39 green 3 3V supply voltage for peripherals on the phyBASE ILE 040 green 3 3 V standby voltage of the phyBASE 041 green standby voltage of the phyCARD 045 yellow SSI interface compliant with the AC 97 standard 046 green SSI interface compliant with the 125 standard 17 3 6 048 yellow user LED driven by the LED dimmer at 121 Table 30 LEDs Descriptions 60 PHYTEC Messtechnik GmbH 2014 1 800 0 The phyCARD i MX 6 on the phyBASE 17 2 4 Jumpers The phyCARD Carrier Board comes
72. For maximum EMI performance all GND pins should be connected to a solid ground plane PHYTEC Messtechnik GmbH 2014 L 800e 0 17 phyCARD i MX 6 PCA A XL3 xxx 4 2 Backup Voltage VSTBY VSTBY is an additional supply voltage input which has to be connected to a supply voltage of 3 3 V 5 if power management functions will be used This input voltage supplies the control management IC CMIC at U17 which is necessary for all power management functions of the phyCARD module and the RTC of the power management IC at U29 To backup the RTC of the power management IC PMIC on the module it is necessary to attach a secondary voltage source of 3 3 V to the phyCARD i MX 6 at pin X1B6 This voltage source is supplying the internal backup voltage domain VBACKUP of the PMIC which again supplies the RTC and some critical registers if the primary system power VDD 3V3 is removed Applications not requiring a backup mode or power management functions can connect the VSTBY IN pin to the primary system power supply VDD 3 3 V 4 3 Power Management IC 029 Control Management IC 017 The phyCARD i MX 6 provides a Power Management IC PMIC at U29 DA9063 and a Control Management IC CMIC at U17 MSP430G2153 Figure 8 presents a graphical depiction of the powering scheme 4 3 1 Power Management IC PMIC U29 The PMIC at U29 generates the different voltages required by the processor and on board components and provides features such as
73. IC ECSPI3 Master data out slave data in X1B37 X SPIO MISO I O VDD 3V3 LOGIC Master data in slave data out Table17 SPI Interface Signal Location 9 7 125 Audio Interface 551 The Synchronous Serial Interface SSI of the phyCARD i MX 6 is a full duplex serial interface that allows to communicate with a variety of serial devices such as standard codecs digital signal processors DSPs microprocessors peripherals and popular industry audio codecs that implement the inter IC sound bus standard 15 and Intel AC97 standard The i MX6 provides three instances of the SSI module On the phyCARD i MX 6 5515 is brought out to the phyCARD Connector With reference to the X Arc bus specification the main purpose of this interface is to connect to an external codec such as 125 Four signals extend from the i MX 6 SSI module to the phyCARD Connector 125 CLK 125 SYNC 125 SDATA OUT 125 SDATA IN _ AC97 INT and X 125 nRESET are two additional pins assisting the functionality of this interface X 97 INT is used as input and output As output it signals which codec is supported by the phyCARD Use of this pin as an input enables to attach an external interrupt to GPIO GPIO5 14 X 125 nRESET is connected to GPIO7 12 of the 1 6 allowing to perform a software reset for the device attached to the interface 36 PHYTEC Messtechnik GmbH 2014 1 800 0 Serial Interfaces Please al
74. IO1 IRQ1 GPIO1 6 at T3 of the i MX 6 refer to section 10 2 GPIO2 GPIO4 29 R22 of the i MX 6 refer to section 10 82 PHYTEC Messtechnik GmbH 2014 L 800e 0 The phyCARD i MX 6 on the phyBASE 17 3 12 Extension connectors X8A X9A 9 o CY 2 y 0 AlO ooooo Ole 4 O50 d o 2000 EB 50 BH 0000 og ca 000000 doc EET m 8 22 HB HB ENS 0000 000000 n Bau an 888 BEBEBE 1000 0106 E 8 29 cen omom F 552000000060 0000 er 2 BB 0000 B mes m 45 90 9998 gt 030 anga Ss nonno 0000 og B 5 BB 02000 0000 25 200688963 Tana 00002 D g lt U nn 90010 9860 pp 0000 0 gan B 98 5 men pong pooo H oo Boon 0 _ OD 00 VITE 0010 g Baoa 00 S Expansion 09 2 OO Expansion 1 un 11000001 0000 E 00 00 ais X9 X8 5 Tm 2000 0000 ooo oooo Boone un 00000000 a 5 oo na nn 00 DD px
75. MMDC of the 1 6 processor The DDR3 memory is accessed via the second AHB port starting at 0x1000 0000 Typically the DDR3 SDRAM initialization is performed by a boot loader or operating system following a power on reset and must not be changed at a later point by any application code When writing custom code independent of an operating system or boot loader SDRAM must be initialized by accessing the appropriate SDRAM configuration registers on the 1 6 controller Refer to the 7 MX 6 Reference Manual for accessing and configuring these registers 7 2 NAND Flash Memory U13 Use of Flash as non volatile memory on the phyCARD i MX6 provides an easily reprogrammable means of code storage These Flash devices are programmable with 3 3 V No dedicated programming voltage is required As of the printing of this manual these NAND Flash devices generally have a life expectancy of at least 100 000 erase program cycles and a data retention rate of 10 years The NAND Flash memories are connected to the External Interface Module EIM CSO NANDF CSO ofthe EIM interface selects the NAND Flash at U13 Any parts that are footprint TSOP 48 50 C3 and functionally compatible may be used with the phyCARD i MX 6 Please contact PHYTEC for more information about additional module configurations PHYTEC Messtechnik GmbH 2014 L 800e 0 27 phyCARD i MX 6 PCA A XL3 xxx 7 3 12 010 phyCARD i MX 6 is populat
76. P2 1 of CMIC at U17 49A GND Power Ground 0 V 50A X CONFIGO I VSTBY Boot Mode input 0 Table 3 Pinout of the phyCARD Connector X1 Row A continued Pin Row X1B Pin Signal 1 0 SL Description 1B VDD 3V3 Power 3 3 V Primary voltage supply input 2B VDD 3V3 Power 3 3 V Primary voltage supply input 3B VDD 3V3 Power 3 3 V Primary voltage supply input 4B GND Power Ground 0 V 5B VDD 3V3 LOGIC 0 Power VCC Logic output 6B VSTBY IN Power Standby voltage input 7B X nRESET OUT VDD 3V3 LOGIC Active low reset output 8B GND Power Ground 0 V 9B X LVDS TX1 0 LVDS LVDS Chanel 1 positive output 10B X LVDS TX1 0 LVDS LVDS Chanel 1 negative output 11B X LVDS 3 0 LVDS LVDS Chanel 3 positive output 12B X LVDS TX3 0 LVDS LVDS Chanel 3 negative output 13B GND Power Ground 0 V 14B X LVDS CAM I LVDS Camera data positive input 15B X LVDS CAM RX I LVDS Camera data negative input 16B X LVDS CAM nLOCK 0 LVDS Camera lock output active low 17B X I2C SDA I O VDD 3V3 LOGIC 12 2 Data 18B GND Power Ground 0 V 198 ETH LINK 0 VDD ETH 3V3 Ethernet Link Indicator open drain Table 4 Pinout of the phyCARD Connector X1 Row B 1 Caution The current draw at 3V3 LOGIC must not exceed 500 mA PHYTEC Messtechnik GmbH 2014 1 800 0 11 phyCARD i MX 6 PCA A XL3 xxx
77. S Lowest S low M middle L high XL highest In order to receive product specific information on changes and updates in the best way also in the future we recommend to register at http www phytec de de support registrierung html or http www phytec eu europe support registration html For technical support and additional information concerning your product please visit the support section of our web site which provides product specific information such as errata sheets application notes FAQs etc http www phytec de de support faq fag phyCARD i MX 6 html or http www phytec eu europe support faq faq phyCARD i MX 6 html K PHYTEC Messtechnik GmbH 2014 1 800 0 Preface Declaration of Electro Magnetic Conformity of the phyCARD i MX 6 C System on Module henceforth products are designed for installation in electrical appliances or as dedicated Evaluation Boards i e for use as a test and prototype platform for hardware software development in laboratory environments Caution PHYTEC products lacking protective enclosures are subject to damage by ESD and hence may only be unpacked handled or operated in environments in which sufficient precautionary measures have been taken in respect to ESD dangers It is also necessary that only appropriately trained personnel such as electricians technicians and engineers handle and or operate these products Moreover PHYTEC products
78. SB DP I 0 USB transceiver cable interface D USB on the go transceiver cable ID X1A29 X USB UID I resistor connection Table 13 Location of the USB Signals In order to use the phyCARD i MX 6 as USB device an USB Standard B connector and an appropriate configuration of the ID pin on the carrier board is all that is needed 9 3 USB Host Interface The 1 6 provides a high speed USB Host interface which uses the 1 6 embedded HS USB Host PHY Neither VBUS detection nor the ID pin is required Therefore USB VBUS and ID are not brought out to the phyCARD Connector For self powered devices an external USB Standard A for USB Host connector is all that is needed to interface the phyCARD i MX 6 USB Host functionality To attach devices which require the VBUS supply voltage an external power logic or charge pump capable of sourcing 5 V power must be provided on the carrier board Signal X nUSB HOST PWR X1B23 allows control of the external power logic It can be used to switch an external VBUS power supply and is derived from the USB HOST interface of the i MX 6 The applicable interface signals 0 0 PWR OC can be found on the phyCARD Connector as shown in the following table Pin Signal Description X1B23 X nUSB HOST PWR O 3v3 VSB HOST power switch output open drain X1B24 X nUSB HOST OC I 3V3 LOGIC 22 over current input USB HO
79. ST transceiver cable interface D USB HOST transceiver cable interface D X1B27 X USB HOST D I 0 X1B28 X USB HOST 0 1 0 Table 14 Location of the USB Host Signals PHYTEC Messtechnik GmbH 2014 1 800 0 33 phyCARD i MX 6 PCA A XL3 xxx 9 4 Ethernet Interface Connection of the phyCARD i MX 6 to the world wide web or a local area network LAN is possible using the on board PHY at U11 It is connected to the interface of the 1 6 The FEC operates with a data transmission speed of 10 Mbit s or 100 Mbit s 9 4 1 Ethernet PHY U11 With an Ethernet PHY mounted at U11 the phyCARD i MX 6 has been designed for use in 10Base T and 100Base T networks The 10 100Base T interface with its LED signals extends to phyCARD Connector X1 Pind Signal I O ISL Description X1A19 X ETH SPEED 0 3V3 Ethernet Speed Indicator Open Drain Transmit positive output normal Receive positive input reversed Transmit negative output normal Receive negative input reversed X1B19 X ETH LINK 0 VCC Ethernet Link Indicator Open Drain Receive positive input normal Transmit positive output reversed Receive negative input normal Transmit negative output reversed 1 20 X ETH 0 I 3V3 1 21 TX 0 I 3V3 X1B20 X ETH 1 0 3V3 X1B21 X ETH RX I 0 VCC_3V3 Table 15 Location of the Ethe
80. Switches 1 and 2 of DIP Switch S3 select which controller is used to process the touch panel signals The different configurations are shown in Table 39 Button Setting Description S3 1 Depending on the audio standard supported by the phyCARD the audio and touch 3 2 panel signals are either processed by the Wolfson audio touch contrl at U1 AC 97 the TI Audio CODEC at U17 125 and a dedicated touch contrl at 028 Switches 1 and 2 of DIP Switch S3 select which device processes the audio and touch panel signals 0 0 Auto Detection based on the low level of the HDA SEL AC INT signal generated on the phyCARD i MX 6 the dedicated touch contrl at U28 handles the signals from a touch screen 1 0 The dedicated touch contrl at U28 handles the signals from a touch screen regardless of the signal HDA SEL AC INT Table 39 Selection of the Touch Screen Controller As the phyCARD i MX 6 features an 125 compliant audio interface the dedicated touch controller at U28 STMPE811 must be chosen to process the touch screen signals It is connected to the X Arc bus s interface The address can be configured with jumper J3 The default setting is 0x44 7 MSB The touch controller provides an interrupt output which extends directly to the interrupt input pin GPIO2 IRQ X1A47 atthe phyCARD Connector Please refer to Table 31 for information on alternativ I C address configurations PHYTEC Messtec
81. System Configuration and Booting 6 System Configuration and Booting Although most features of the 1 6 microcontroller are configured and or programmed during the initialization routine other features which impact program execution must be configured prior to initialization via pin termination The system start up configuration includes Boot device order configuration During the reset cycle the operational system boot mode of the 1 6 processor is determined by the configuration of two BOOTMODE pins BOOT_MODE 1 0 These pins select the boot type If the boot type is set to Internal boot BOOT_MODE 1 0 10 pins BOOT CFGx 7 0 are used to configure further boot options You can find further information about these boot pins in the 7 MX 6 Reference Manual To allow flexible selection of the booting device not all of the BOOT CFGx 7 0 pins are preconfigured 10 kO pull up or pull down configuration resistors or by jumpers on the phyFLEX i MX 6 Some signals are set by the CMIC at U17 During powering up the boot configuration pins X CONFIG1 and X XONFIG2 of the module are read by the CMIC Depending on the setting of these pins CMIC configures BOOT MODE 1 0 CFG1 7 and BOOT CFG2 1 It also ensures the correct power up sequencing so that the i MX 6 is powered only after the configuration of the boot mode pins Table 8 shows the possible settings of pins X CONFIG1 and X XONFIG2 and the resulting boot configuration
82. VDD 3V3 LOGIC 175 Clock AUD5 43B X 125 SYNC 0 VDD 3V3 LOGIC I S Frame SYNC AUD5 44B X I2S nRESET 0 VDD 3V3 LOGIC Reset for external 125 device connects to GPIO7 12 45B GND Power Ground 0 V 46B X SDIO CD I VDD 3V3 LOGIC SD MMC Card detect for MMC SD SDIO uC port GPIO5 22 47B X GPIO1 IRQ1 I O VDD 3V3 LOGIC GPIO1 IRQ pC port GPIO1 06 48B X HW INTROSPECTION I O VDD LOGIC Hardware introspection interface GPIO5 26 for internal use only 49B GND Power Ground 0 V 50B X CONFIG1 I VSTBY Boot Mode input 1 Table 4 Pinout of the phyCARD Connector X1 Row B continued 12 PHYTEC Messtechnik GmbH 2014 1 800 0 Jumpers 3 Jumpers For configuration purposes the phyCARD i MX 6 has several solder jumpers some of which have been installed prior to delivery Figure 5 illustrates the numbering of the solder jumper pads while Figure 6 and Figure 7 indicate the location of the solder jumpers on the board Table 5 provides a functional summary of the solder jumpers which can be changed to adapt the phyCARD i MX 6 to your needs It shows their default positions and possible alternative positions and functions A detailed description of each solder jumper can be found in the applicable chapter listed in the table Note Jumpers not listed should not be changed as they are installed with regard to the configuration of the phyCARD i MX 6 closed 1 1 IE 1 2 LI 2 IL 2 5 e g J3 e g J3 e g J31 Figure 5 Typic
83. al Jumper Pad Numbering Scheme If manual jumper modification is required please ensure that the board as well as surrounding components and sockets remain undamaged while de soldering Overheating the board can cause the solder pads to loosen rendering the module inoperable Carefully heat neighboring connections in pairs After a few alternations components can be removed with the solder iron tip Alternatively a hot air gun can be used to heat and loosen the bonds PHYTEC Messtechnik GmbH 2014 1 800 0 13 phyCARD i MX 6 PCA A XL3 xxx Please pay special attention to the TYPE column to ensure you are using the correct type of jumper 0 10 etc The jumpers are either 0805 package or 0402 package with a 1 8 W or better power rating OFF 00 Dm OD Of OO OOM On 00 ADO oO on OO OD
84. asy start up and subsequent programming of the phyCARD i MX 6 System on Module The carrier board design allows easy connection of additional extension boards featuring various functions that support fast and convenient prototyping and software evaluation The phyBASE supports the following features for the phyCARD i MX 6 modules e Power supply circuits to supply the modules and the peripheral devices e Support of different power modes of appropriate phyCARD e Full featured 4 line RS 232 transceiver supporting data rates of up to 120 kbps hardware handshake and RS 232 connector Seven USB Host interfaces USB OTG interface 10 100 Mbps Ethernet interface Complete audio and touch screen interface LVDS display interface with separate connectors for data lines and display backlight supply voltage Circuitry to allow dimming of a backlight e Secure Digital Card Multi Media Card Interface e Two extension connectors for PHYTEC Extension Boards PEBs or customer prototyping purposes featuring one USB one 1 and one SPI interface as well as one GPIO IRQ at either connector DIP Switch to configure various interface options e Jumper to configure the boot options for the phyCARD i MX 6 module mounted e RTC with battery supply backup 54 PHYTEC Messtechnik GmbH 2014 1 800 0 The phyCARD i MX 6 on the phyBASE 17 1 Concept of the phyBASE Board The phyCARD Carrier Board provides a flexible development platform enabling quick an
85. ated touch contrl at U28 Switches 1 and 2 of DIP Switch 53 select which device processes the audio and touch panel signals 0 0 Auto Detection based on the low level of the HDA_SEL AC_INT signal generated on the phyCARD i MX 6 the TI audio CODEC U17 is selected to process the 125 compliant audio signals 1 0 The TI audio CODEC U17 is selected to process the 125 compliant audio signals regardless of the signal HDA_SEL AC_INT Table 40 Selection of the Audio Codec As the phyCARD i MX 6 features an 125 compliant audio interface the Audio CODEC at U17 must be chosen to process the audio signals LEDs 045 AC 97 046 15 indicate which audio interface is active For the phyCARD i MX 6 LED D46 should be on To reset the audio ICs at U1 and U17 two different reset sources can be selected with jumper J4 The source of the reset can be either the peripheral reset signal X_nRES_OUT X27B7 or the dedicated audio device reset SSI_RESET X27B44 from the phyCARD i MX 6 The default setting of jumper J4 selects the peripheral reset signal X_nRES_OUT X27B7 from the phyCARD i MX 6 Audio devices can be connected to 3 5 mm audio jacks at X1 X2 and X3 Audio outputs X2 Line output Line OUTL Line OUTR Audio Inputs X1 Microphone Inputs MIC1 MIC2 X3 LineInput Line INL Line INR Please refer to the audio codec s reference manual for additional information regarding the special interface specification
86. atrix pin 1A is thus covered with the corner of the phyCARD i MX 6 marked with 1A The numbering scheme is always in relation to the PCB as viewed from above even if all connector contacts extend to the bottom of the module The numbering scheme is thus consistent for both the module s phyCARD Connector as well as the mating connector on the phyCARD Carrier Board or target hardware thereby considerably reducing the risk of pin identification errors Since the pins are exactly defined according to the numbered matrix previously described the phyCARD Connector is usually assigned a single designator for its position X1 for example In this manner the phyCARD Connector comprises a single logical unit regardless of the fact that it could consist of more than one physical socketed connector The following figure illustrates the numbered matrix system It shows a phyCARD i MX 6 with an SMT phyCARD Connector on its underside defined as dotted lines mounted on a carrier board In order to facilitate understanding of the pin assignment scheme the diagram presents a cross view of the phyCARD i MX 6 module showing the phyCARD Connector mounted on the underside of the module s PCB PHYTEC Messtechnik GmbH 2014 1 800 0 7 phyCARD i MX 6 PCA A XL3 xxx UART JTAG oo M NEA A pa 6 s 4 Pinout of the phyCARD Connector top view with cross section insert Table 2 shows the pinout
87. cement bottom 1 5 Pinout of the phyCARD Connector top view with cross section insert 8 Typical Jumper Pad Numbering Scheme iiio eoa 13 Jumper Locations LON VIEW sasana aaa aaa PLA a a a aaa RUNE RUNE RUNE D ag pM OR Ra PRA aan 14 Jumper Locations 15 Power Supply Diagram 20 JTAG Interface at X2 and top view ee Ng enne 40 JTAG Interface at X2 and bottom 41 Physical Dimensions ooa ooo root B cale 46 Footprint of the phyCARD 1 MX 6 51 phyBASE Overview of Connectors LEDs and 56 Typical Jumper Numbering Scheme 98 99 61 Phy BASE Jumper LOCATIONS Ny eonceervsssssueesrenseossiassaecsesnesnsensene 62 phyCARD i MX 6 SOM Connectivity to the Carrier Board 65 POWering ilo ccce e n a Aa Rd A Ina 66 Power Connector corresponding to Wall Adapter Input 28 66 RS 232 Interface orae rero opea rera eoe rota eoo eeu eere inaa erus 68 RS 232 Connector P1 Signal suas xu 68 Ethernet Interface at Connector X10 69 Components supporting the USB Host
88. ction 6 for more information on the different boot modes PHYTEC Messtechnik GmbH 2014 1 800 0 63 phyCARD i MX 6 PCA A XL3 xxx See Jumper Setting Description Section Jumper J4 selects the reset source of the audio devices at U1 and U17 The source of the reset can be either the peripheral reset signal X 5 OUT X27B7 or the dedicated audio device reset 551 RESET X27B44 from the phyCARD i MX 6 J4 1 2 Dedicated audio device reset SSI_RESET X27B44 from 17 3 7 3 the phyCARD i MX 6 connected to the reset input of the audio devices at U1 and U17 2 3 Peripheral reset signal X_nRES_OUT X27B7 from the phyCARD i MX 6 connected to the reset input of the audio devices at U1 and U17 Table31 phyBASE Jumper Descriptions continued Note Detailed descriptions of the assembled connectors jumpers and switches can be found in the following chapters Default settings are in bold blue text The reset signal at X27 B44 originates from GPIO3 21 of the i MX 6 Default settings are in bold blue text 64 PHYTEC Messtechnik GmbH 2014 L 800e 0 The phyCARD i MX 6 on the phyBASE 17 3 Functional Components on the phyBASE Board This section describes the functional components of the phyCARD Carrier Board supporting the phyCARD i MX 6 Each subsection details a particular connector interface and associated jumpers for configuring that interface 17 3 1 phyCARD i MX 6 SOM Connectivity X27
89. d easy start up and subsequent programming of the phyCARD System on Module The carrier board design allows easy connection of additional extension boards featuring various functions that support fast and convenient prototyping and software evaluation The carrier board is compatible with all phyCARDs This modular development platform concept includes the following components the phyCARD i MX 6 module populated with the 1 6 processor and all applicable SOM circuitry such as DDR SDRAM Flash PHYs and transceivers to name a few the phyBASE which offers all essential components and connectors for start up including a power socket which enables connection to an external power adapter interface connectors such as DB 9 USB and Ethernet allowing for use of the SOM s interfaces with standard cable The following sections contain specific information relevant to the operation of the phyCARD i MX 6 mounted on the phyCARD Carrier Board Note Only features of the phyBASE which are supported by the phyCARD i MX 6 are described Jumper settings and configurations which are not suitable for the phyCARD i MX 6 are not described in the following chapters PHYTEC Messtechnik GmbH 2014 1 800 0 55 phyCARD i MX 6 PCA A XL3 xxx 17 2 Overview of the phyBASE Peripherals aThe phyBASE is depicted in Figure 13 It is equipped with the components and peripherals listed in Table 27 Table 28 Table 29 and Table 30 For a more detailed de
90. e high level signal The hex numbers given for addresses of I C devices always represent the 7 MSB of the address byte The correct value of the LSB which depends on the desired command read 1 or write 0 must be added to get the complete address byte E g given address in this manual 0x41 gt complete address byte 0x83 to read from the device and 0x82 to write to the device Tables which describe jumper settings show the default position in bold blue text Text in blue italic indicates a hyperlink within or external to the document Click these links to quickly jump to the applicable URL part chapter table or figure References made to the phyCARD Connector always refer to the high density molex connector on the undersides of the phyCARD i MX 6 System on Module Abbreviations and Acronyms Many acronyms and abbreviations are used throughout this manual Use the table below to navigate unfamiliar terms used in this document PHYTEC Messtechnik GmbH 2014 1 800 0 vii phyCARD i MX 6 PCA A XL3 xxx Abbreviation Definition BSP Board Support Package Software delivered with the Development Kit including an operating system Windows or Linux preinstalled on the module and Development Tools CB Carrier Board used in reference to the phyBASE Development Kit Carrier Board DFF D flip flop EMB External memory bus EMI Electromagne
91. e The connectors X2 and X3 only populates phyCARD i MX 6 modules with a special order code DEBUG JTAG connectors X2 and X3 are not populated on the standard phyCARD module We recommend integration of a standard 2 54 mm pitch pin header connector in the user target circuitry to allow easy program updates via the JTAG interface PHYTEC Messtechnik GmbH 2014 1 800 0 41 phyCARD i MX 6 PCA A XL3 xxx See the following table for details on the JTAG signal pin assignment Pin Row Signal 5 Signal VSUPPLY 2 1 TREF VDD 3V3 LOGIC VDD_3V3_LOGIC via 00 GND 3 X JTAG TRSTB 10 kO pull up GND 6 5 X JTAG TDI 10 kO pull up GND 8 7 X TMS 10 pull up GND 10 9 X JTAG TCK GND 12 11 Connected to X JTAG TCK via 0 O GND 14 13 X JTAG 100 GND 16 15 X nRESET IN GND 18 17 NC GND 20 19 NC Table20 JTAG Connector Signal Assignment Note Row A is on the controller side of the module and row B is on the connector side of the module The following table shows details on the debug interface pin assignment X2 Pin Row Signal 7 z Signal VDD_3V3 2 1 GND VDD_3V3_LOGIC 4 3 UART2_TX GND 6 5 UART2_RX Table 21 Debug interface Connector X2 Signal Assignment 42 PHYTEC Messtechnik GmbH 2014 L 800e_0 LVDS Camera Interface 13 LVDS Display Interface The LVDS Signals from channel serializer 0 of the 1 6 s o
92. e 1 6 are supposed to be powered while the phyCARD i MX 6 is in suspend mode or turned off The bus switches can either be supplied by VDD 3V3 LOGIC on the phyCARD side or the bus switches output enable to the SOM can be controlled by LOGIC to prevent these voltages from occurring Use of 3V3 LOGIC to supply level shifters allows converting the signals according to the needs on the custom target hardware Alternatively signals can be connected to an open drain circuitry with a pull up resistor attached to LOGIC PHYTEC Messtechnik GmbH 2014 L 800e 0 21 phyCARD i MX 6 PCA A XL3 xxx 22 PHYTEC Messtechnik GmbH 2014 1 800 0 Power Management 5 Power Management The phyCARD i MX 6 was designed to support applications requiring a power management Three pins of the X Arc bus are designated for this purpose X nPOWER OFF and X nSUSPEND RAM are output pins which can be used to indicate the power status of the phyCARD i MX 6 whereas nWKUP is an input pin to apply a wake up signal to the phyCARD i MX 6 The three power management signals are connected to ports of the control management IC CMIC at U17 Thus their functionality can be programmed to your needs refer to section 4 3 2 The following table shows the location of the power management pins on the phyCARD Connector and the corresponding ports of the CMIC Ping Signal 1 0 51 Description Wakeup Interrupt Input
93. e phyCARD D39 green VCC3V3 3V3 supply voltage for peripherals on the phyBASE 040 green VCC3V3STBY 3V3 standby voltage of the phyBASE D41 9 VSTBY standby voltage of the phyCARD Table 32 LEDs Assembled on the Carrier Board Note For powering up the phyCARD the following actions have to be done 1 Plug in the power supply connector All power LEDs should light up and the phyCARD puts serial output to serial line 0 at P1 2 For powering down the phyCARD i MX 6 button S2 should be pressed for a minimum time of 2000 ms 3 Press button S2 for a maximum time of 1000 ms All power LEDs should light up and the phyCARD puts serial output to serial line 0 at P1 Three different power states are possible RUN OFF and SUSPEND e During RUN all supply voltages except VSTBY are This means that the phyCARD 1 6 is supplied PHYCARD e In OFF state all supply voltages are turned off Only the standby voltage VCC3V3STBY of the phyBASE itself is still available to supply the PLD the RTC and to provide a high level voltage for the Reset and Power switch In SUSPEND mode only the standby voltage VSTBY for the phyCARD i MX 6 and the standby voltage VCC3V3STBY of the phyBASE itself are generated This means the phyCARD i MX 6 is supplied only by VSTBY The RUN and OFF state can be entered using the power button S2 as described in the gray box above It is also possible to enter OFF state with
94. ear calendar e Century bit for year 2000 compliance e Universal timer with alarm and overflow indication 24 hour format e Automatic word address incrementing Programmable alarm timer and interrupt functions The Real Time Clock is programmed via the I C bus address 0x51 Since the phyCARD i MX 6 is equipped with an internal 12 controller the I C protocol is processed very effectively without extensive processor action refer also to section 9 5 PHYTEC Messtechnik GmbH 2014 L 800e 0 89 phyCARD i MX 6 PCA A XL3 xxx The Real Time Clock also provides an interrupt output that extends to the Wakeup input of the PLD at U25 and is used within the PLD s state machine Additionally the interrupt is inverted and brought out as low active signal X nWakeUp at pin X27A48 on the phyCARD Connctor An interrupt occurs in the event of a clock alarm timer alarm timer overflow and event counter alarm It has to be cleared by software With the interrupt function the Real Time Clock can be utilized in various applications CLK signal which is also connected to the PLD at U25 be programmed to various frequencies e g 1 Hz Caution As the signal is used for the timing of the PLD s internal processes great care must be taken to ensure that the timing doesn t get corrupted by changing the frequency Note After connection of the supply voltage the Real Time Clock generates no interrupt The RTC
95. echnik GmbH 2014 1 800 0 Index I I2C 28 FC 36 Memory cesses eene 16 sana aaa tanana gana ana ana baa aaa 9 9 00205 37 J CID e 16 28 PI 16 46 JTAG 1 41 L LAN 7 36 SOM 01 EK 2 40 VA 40 144 70 LVDS Camera Signals 16 46 M MAC ccececcscecsceccscecsccceecscescececseeeeces 36 MAC lt 36 N NAND Flash oiov 27 0 Operating 48 Operating 48 P rA DA Cete RR 74 phyBASE lt 58 169 sawanan aa aa aaa 57 Pin 58 sasa aaa aia aa ara alaa naela a aa 59 70 66 bia cc 67 v 73 T 74 71 95 phyCARD i MX 6 PCA A XL3 xxx AG T HO S 71 74 71 JO cessas edd 71 KG sss aaa 71
96. ed with a non volatile 4 12 EEPROM at 010 This memory can be used to store configuration data or other general purpose data This device is accessed through port 1 on the i MX 6 The control registers for port 1 are mapped between addresses 0x021A 0000 and 0x021A 3FFF Please see the 7 MX 6 Reference Manual for detailed information on the registers The three lower address bits are fixed to zero which means that the EEPROM can be accessed at I C address 0x50 Write protection to the device is accomplished via jumper J3 Refer to section 7 3 1 for further details on setting this jumper 7 3 1 EEPROM Write Protection Control 33 Jumper J3 controls write access to the EEPROM U10 device Closing this jumper allows write access to the device while removing this jumper will cause the EEPROM to enter write protect mode thereby disabling write access to the device The following configurations are possible EEPROM Write Protection State J3 Write access allowed closed Write protected open Table 10 EEPROM write protection states 23 Note If the jumper is not set the write protection signal can also be changed by GPIO3 19 of the i MX 6 controller See the manufacturer s data sheet for interfacing and operation Defaults are in bold blue text 28 PHYTEC Messtechnik GmbH 2014 L 800e 0 SD MMC Card Interfaces 8 50 Interfaces The X Arc bus features
97. g edge strobe for the LVDS Deserializer at used for the camera connectivity of the phyCARD i MX 6 rising edge strobe used for the LVDS camera signals falling edge strobe used for the LVDS camera signals Table 5 Jumper Settings 16 PHYTEC Messtechnik GmbH 2014 1 800 0 Power Requirements 4 Power The phyCARD i MX 6 operates off of a single power supply voltage The following sections of this chapter discuss the primary power pins on the phyCARD Connector X1 in detail 4 1 Primary System Power VDD 3V3 The phyCARD i MX 6 operates off of a primary voltage supply with a nominal value of 3 3 V The on board power management IC PMIC at U29 generates the 2 5 V 1 375 V 1 5 V 0 75 V 1 2 V and 3 0 V voltage supplies required by the 1 6 MCU and on board components from the primary 3 3 V VDD 3V3 supplied to the SOM For proper operation the phyCARD i MX 6 must be supplied with a voltage source of 3 3 V 5 with 1 5 A load at the VCC pins on the phyCARD Connector X1 VDD 3V3 X1 1 2 1B 2B 3B Connect all 3 3 V VCC input pins to your power supply and at least the matching number of GND pins Corresponding GND 1 4A 8A 13 4B 8B 13B Please refer to section 2 for information on additional GND Pins located at the phyCARD Connector X1 Caution As a general design rule we recommend connecting all GND pins neighboring signals which are being used in the application circuitry
98. g the module to reset Additionally a peripheral reset is generated by the PLD on the CB to reset peripherals such as the USB Hub etc S2 Issues a power on off event Pressing this button less than 2 seconds will toggle the nPWR KEY pin of the phyBASE CPLD LOW causing the CPLD to turn on the supply voltages Pressing this button for more than 2 seconds causes the CPLD to turn off the supply voltages Additionally a DIP Switch is available at S3 The following table gives an overview of the functions of the DIP switch Note The following table describes only settings suitable for the phyCARD i MX 6 Other settings must not be used with the phyCARD i MX 6 58 PHYTEC Messtechnik GmbH 2014 L 800e 0 The phyCARD i MX 6 on the phyBASE See Switch Setting Description Section Depending on the audio standard supported by the phyCARD the audio and touch panel signals are either processed by the Wolfson audio touch contrl at U1 AC 97 or the TI Audio CODEC at U17 125 and a dedicated touch contrl at U28 Switches 1 and 2 of DIP Switch S3 select which device processes the audio and touch panel signals 53 1 0 0 Auto Detection based on the low level of the SEL AC INT signal 17 3 7 3 53 2 generated on the phyCARD i MX6 the TI audio CODEC 017 is 17 3 8 selected to process 125 compliant audio signals while the dedicated touch contrl at U28 handles the signals from a touch screen 1 0 Regardless of
99. hnik GmbH 2014 1 800 0 77 phyCARD i MX 6 PCA A XL3 xxx 17 3 8 Audio Interface X1 X2 X3 0000 o Q 00000 Q o Ba 2 5 we 6000 gs gas 25558 gauss 028888 un FE O Eug 1 pron Ma w gaen 00010 Wa EB a 8000 5 0600 coo Eg 00000000 0000980000 ils ag 9000690000 i a 58 mmm Bis oon nm nb BD 88 5500 Dn engg Sod E 883558 TH e 10000 007755 ng _ 050 00 B Ed 050 ooo ng on m 0000 a 95 00888858288 ison ag 00 046 oo o0 00 00 OD s 200p E is ooo 00 m 00 00 00 ES DB 00 e cae 09000009 S5 EIQ E 00 on 00 Bowe Bog 00 ji Bog ES 00 EP 00 ooo s 00 2 00 OD 00 Figure 25 Audio Interface at Connectors X1 X2 X3 o o o co 50 n BBB OG c 0998 nooo LL B E 00
100. iron tip Alternatively a hot air gun can be used to heat and loosen the bonds Caution If any modifications to the module are performed regardless of their nature the manufacturer guarantee is voided Integrating phyCARD into a Target Application Successful integration in user target circuitry greatly depends on the adherence to the layout design rules for the GND connections of the phyCARD module As a general design rule we recommend connecting all GND pins neighboring signals which are being used in the application circuitry For maximum EMI performance all GND pins should be connected to a solid ground plane Note Please refer to the phyCARD Design In Guide LAN 051 for additional information layout recommendations and example circuitry 52 PHYTEC Messtechnik GmbH 2014 L 800e 0 Hints for Handling PHYTEC Messtechnik GmbH 2014 1 800 0 53 phyCARD i MX 6 PCA A XL3 xxx 17 The phyCARD i MX 6 on the phyBASE PHYTEC phyBASE Boards are fully equipped with all mechanical and electrical components necessary for the speedy and secure start up and subsequent communication to and programming of applicable PHYTEC System on Module SOM modules phyBASE Boards are designed for evaluation testing and prototyping of PHYTEC System on Module in laboratory environments prior to their use in customer designed applications The phyCARD i MX 6 Carrier Board provides flexible development platform enabling quick and e
101. l adapter input power jack to supply 17 3 2 main board power 9 36 V X29 USB On The Go connector 17 3 6 X32 Display Backlight supply voltage 17 3 7 2 X33 USB Host connector 1535 for X34 CPLD JTAG connector internal use only 1 Serial Interface DB 9F 27 22 Table 27 phyBASE Connectors and Pin Headers Note Ensure that all module connections are not to exceed their expressed maximum voltage or current Maximum signal input values are indicated in the corresponding controller User s Manual Data Sheets As damage from improper connections varies according to use and application it is the user s responsibility to take appropriate safety measures to ensure that the module connections are protected from overloading through connected peripherals PHYTEC Messtechnik GmbH 2014 1 800 0 57 phyCARD i MX 6 PCA A XL3 xxx 17 2 2 Switches The phyBASE is populated with two switches which are essential for the operation of the phyCARD i MX 6 module on the carrier board Figure 13 shows the location of the switches and push buttons See Button Description Section 51 System Reset Button system reset signal TT generation m 52 Power Button powering on and off main 17 3 2 supply voltages of the carrier board Table 28 phyBASE Push Buttons Descriptions S1 Issues a system reset signal Pressing this button will toggle the X nRESET IN pin X2A7 of the phyCARD SOM low causin
102. ly voltage of the phyCARD i MX 6 But in order to follow the power up and power down sequencing mandatory for the i MX 6 VDD 3V3 LOGIC is switched on with a certain delay Because of that use of VDD 3V3 LOGIC ensures that external components are only supplied when the supply voltages of the 1 6 are stable External devices connected to the GPIO pins should supplied by VDD 3V3 LOGIC available at X1A5 and X1B5 refer to section 4 4 Alternatively an open drain circuit with a pull up resistor attached to 3V3 LOGIC can be connected to the GPIOs of the phyCARD 1 MX 6 Caution The current draw for LOGIC must not exceed 500 mA If devices with a higher power consumption are to be connected to the GPIOs of the phyCARD i MX 6 they should be switched on and off by use of 3V3 LOGIC This way the power up and power down sequencing will be considered even if the devices are not supplied directly by VDD 3V3 LOGIC Caution The i MX6 s requires strict separation of the supply voltages generated on the phyCARD i MX 6 and the supply voltages used on the carrier board custom application To avoid voltages which are sourced from the supply voltage of peripheral devices attached to the GPIOs bus switches powered by 3V3 LOGIC on the phyCARD side should be used Alternatively the bus switches output enable to the SOM can be controlled by VDD_3V3_LOGIC please refer to section 4 4 for more information Please refer to
103. m g 00 an J mg ome Ej mm zz s 0000 Thon 2 B 011110001 n B Bn B a 0 0 an oo ero 0 gun zog nn gt o o 3 01000000 050 un e go SOS a B 26 5 000 a on O 8 mi un 00 aac 00 un ao oO gt ic up 00 0520 Soo 8 00 0 0900 a a 5 pg OO 00 UD Bg msim B 00 as CO E p m ERE mg 006 n ae 3 gH 00 000000 ggg UD ES 00 0 ooo 00 m 5 ga mn un an zs le E un UD 00 m E 00 ooog 00 un nun Bm 00000000 oo Boo 0000 5 00 NG m 00 oo foo omi Poono B 00 ag jg Bo gt om m B 00 0000 mes a B oom waana maan 2 9 ca omm B o 6608 BB co g i 00 pjo 0 B a co 996 BESED 1 c EB oo 00 Bea oy 275 0 a oo 22 m d 9 B 00 pq a Un D y UD o BBm OQ nn Figure 19 5 232 Interface Connector P1 Connector P1 is a DB9 sub connector and provides a connection interface to
104. n chip LVDS Display Bridge LDB are brought out at the X Arc Connector X1 Thus an LVDS Display can connect directly to the phyCARD i MX 6 The location of the applicable interface signals X LVDS 0 3 X LVDS 0 3 X LVDS TXCLK and X LVDS TXCLK can be found in the table below Pind Signal 1 0 51 Description X1A9 LVDS 0 LVDS 1050 data0 X1A10 X LVDS TXO 0 LVDS LVDSO data0 X1A11 LVDS 2 0 LVDS LVDSO data2 X1A12 LVDS TX2 0 LVDS LVDSO data2 X1A14 X_LVDS_TXCLK 0 LVDS LVDSO clock X1A15 X_LVDS_TXCLK 0 LVDS LVDSO clock 1 9 X LVDS 1 0 LVDS LVDSO data1 X1B10 LVDS 1 0 LVDS LVDSO data1 X1B11 X_LVDS_TX3 0 LVDS LVDSO data3 X1B12 X LVDS TX3 0 LVDS LVDSO data3 Table 22 Display Interface Signal Location 13 1 LVDS Display Interface pixel mapping The phyCARD specification defines the pixel mapping of the LVDS display interface The pixel mapping equates to the OpenLDI respectively Intel 24 0 standard Thus you can connect 18 bit as well as 24 bit LVDS displays to the phyCARD Table 23 and Table 24 show the recommended pixel mapping of the LVDS display For further information please see the phyCARD Design Guide Note Make sure that the LVDS display you want to use provides the same pin mapping as the phyCARD Normally this is only important for 24 bit LVDS displays because due to the organization of the LVDS
105. n order to configure the CB or target application for 3 3 V 7A X nRESET I VBAT Active low Reset In 8A GND Power Ground 0 V 9A X LVDS TXO 0 LVDS LVDS Chanel 0 positive output 10A X LVDS 0 0 LVDS LVDS Chanel 0 negative output 11A X LVDS TX2 0 LVDS LVDS Chanel 2 positive output 12A X LVDS TX2 0 LVDS LVDS Chanel 2 negative Output 13A GND Power Ground 14A X_LVDS_TXCLK 0 LVDS LVDS Clock positive output 15A X_LVDS_TXCLK 0 LVDS LVDS Clock negative output 16A X_LVDS_CAM_MCLK VDD_3V3_LOGIC Camera master clock output 17A X_I2C_CLK 0 VDD_3V3_LOGIC I2C2 Clock output 18A GND Power Ground 0 V 19A X ETH SPEED 0 VDD ETH 3V3 Ethernet speed indicator open drain 20A X ETH O I VDD ETH 3V3 Transmit positive output normal Receive positive input reversed 21A X ETH TX O I VDD ETH 3V3 Transmit negative output normal Receive negative input reversed 22A GND Power Ground 0 V 23A X nUSB OTG PWR 0 VDD 3V3 LOGIC USB OTG power switch output open drain 24 X nUSB OTG OC I VDD_3V3_LOGIC USB OTG over current input signal 25A GND Power Ground 26A X_USB_OTG_VBUS I Power USB OTG VBUS voltage 5 V optional 27A X_USB_OTG_D 1 0 USB USB OTG transceiver cable interface D 28A X_USB_OTG_D 1 0 USB USB OTG transceiver cable interface D 29A X_USB_OTG_UID I VDD_3V3_LOGIC USB OTG on the go transceiver cable ID resistor connection 30A GND Power Ground 0 V Table 3 Pinout of the phyCARD Connector X1 Row A 1
106. neral philosophy here is We never discontinue a product as long as there is demand for it PHYTEC Messtechnik GmbH 2014 1 800 0 xi phyCARD i MX 6 PCA A XL3 xxx Therefore we have established a set of methods to fulfill our philosophy Avoiding strategies e Avoid changes by evaluating long livety of parts during design in phase e Ensure availability of equivalent second source parts Stay in close contact with part vendors to be aware of roadmap strategies Change management in case of functional changes e Avoid impacts on product functionality by choosing equivalent replacement parts e Avoid impacts on product functionality by compensating changes through HW redesign or backward compatible SW maintenance e Provide early change notifications concerning functional relevant changes of our products Change management in rare event of an obsolete and non replaceable part e Ensure long term availability by stocking parts through last time buy management according to product forecasts e Offer long term frame contract to customers Therefore we refrain from providing detailed part specific information within this manual which can be subject to continuous changes due to part maintenance for our products In order to receive reliable up to date and detailed information concerning parts used for our product please contact our support team through the contact information given within this manual xii PHYTEC Messtech
107. nik GmbH 2014 L 800e 0 Introduction 1 Introduction The phyCARD i MX 6 belongs to PHYTEC s phyCARD System on Module family The phyCARD SOMs represent the continuous development of PHYTEC System on Module technology Like its mini micro and nanoMODUL predecessors the phyCARD boards integrate all core elements of a microcontroller system on a subminiature board and are designed in a manner that ensures their easy expansion and embedding in peripheral hardware developments PHYTEC s phyCARD family introduces the newly developed X Arc embedded bus standard Apart from processor performance a large number of embedded solutions require a corresponding number of standard interfaces Among these process interfaces are for example Ethernet USB UART SPI audio display and camera connectivity The X Arc bus exactly meets this requirement As well the location of the commonly used interfaces as the mechanical specifications are clearly defined ALL interface signals of PHYTEC s new X Arc bus are available on a single 100 pin high density pitch 0 635 mm connector allowing the phyCARDs to be plugged like a big chip into a target application The reduced complexity of the phyCARD SOM as well as the smaller number of interface signals greatly simplifies the SOM carrier board design helping you to reduce your time to market As independent research indicates that approximately 70 of all EMI Electro Magnetic Interference problems stem fr
108. o Blood 805108 9 0000 05000 9 5 8 ooo oo Bog 118m H ooo 0000 un gun un 00 04500 220070 USB Host 2 95 00 00 00 5 gt oO 00000000 HEEERCEREE ES 5350385577 0 00 0000 0000 oooo Em B ansion fo 00 o S n Expansion El a a e Tu Ea 0 Stan 5 g a E a gn 2 ju je m B 110000000 EH pu pis EH 99 gt cB 5 mm gaca 00 00 Fes BO Ak D Sa m UU 52 Soo 9 00 UD ES ES oo 00 00 UU 00 00 00 a BB 291 Boo U4 Gd eea BS E mm ab Se 3 nos an OOD un EE e 9 00800 n i B 00 029 000000 ggg UD ju Bg coc EE a 00 009021 un a 00 00 027 00 DUeD20 m B oo 00 005026710 m eo 190 coop 00 00 0090 E un e Zg 00000009 foo m Eb OD 00018 5 ex 3 SS m mpa LO 5 000907 00
109. of displays connectable to the phyCARD the phyBASE has no special display connector suitable only for a small number of displays The new concept intends the use of an adapter board e g PHYTEC s LCD display adapters LCD 014 and LCD 017 to attach a special display or display family to the phyCARD A new PHYTEC Display Interface PDI was defined to connect the adapter board to the phyBASE Tt consists of two universal connectors which provide the connectivity for the display adapter They allow easy adaption also to any customer display One connector 40 pin FCC connector 0 5 mm pitch at X6 is intend for connecting all data signals to the display adapter It combines various interface signals like LVDS USB etc required to hook up a display The second connector of the PDI AMP microMatch 8 338069 2 at X32 provides all supply voltages needed to supply the display and a backlight and the brightness control The following sections contain specific information on each connector PHYTEC Messtechnik GmbH 2014 1 800 0 73 phyCARD i MX 6 PCA A XL3 xxx 17 3 7 1 PDI Data Connector X6 PDI data connector X6 provides display data which originates from the parallel display interface of the i MX6 1100 The display signals are converted into LVDS on the phyCARD i MX 6 and are available at the X Arc bus phyCARD Connector Hence no additional signal conversion is necessary on the phyBASE The LVDS signals extend directly from the phyCAR
110. of the 1 6 This mechanism provides the possibility to customize the boot behavior by changing the code of the CMIC After the 1 6 is powered up the internal ROM code is the first code executed during the initialization process of the controller The ROM code detects which boot devices the controller has to check by using the previously set MODE 1 0 and particular BOOT CFGx 7 0 pin configuration For serial boot devices the ROM code polls the communication interface selected initiates the download of the code into the internal RAM and triggers its execution from there For memory booting the ROM code finds the bootstrap in permanent memories such as NAND Flash or SD Cards and executes it Please refer to 7 MX 6 Reference Manual for more information PHYTEC Messtechnik GmbH 2014 1 800 0 25 phyCARD i MX 6 PCA A XL3 xxx BootMode X CONFIG1 X CONFIGO Bootsource 0 1 1 NAND 1 1 0 500 external 2 0 1 Serial USB OTG USBO 3 0 0 Bootconfig from eFUSE Table 8 Boot Modes of the phyCARD i MX 61 The X CONFIG 1 0 lines have 10 kO pull up resistors populated on the module Hence leaving the two pins unconnected sets the controller to boot mode 0 NAND boot If boot configurations are needed that require change of other boot configuration pins than BOOT MODE 1 0 BOOT CFG1 7 and BOOT CFG2 1 the specific boot settings can also be changed by modifying the resistors and jumpers on
111. om insufficient supply voltage grounding of electronic components in high frequency environments approximately 2096 of all pin header connectors on the X Arc bus are dedicated to Ground This improves EMI and EMC characteristics and makes it easier to design complex applications meeting EMI and EMC guidelines using phyCARD boards even in high noise environments phyCARD boards achieve their small size through modern SMD technology and multi layer design In accordance with the complexity of the module 0402 packaged SMD components and laser drilled microvias are used on the boards providing phyCARD users with access to this cutting edge miniaturization technology for integration into their own design The phyCARD i MX 6 is a subminiature 60 mm x 60 mm insert ready System on Module populated with the Freescale Semiconductor 1 6 microcontroller Tts universal design enables its insertion in a wide range of embedded applications Precise specifications for the controller populating the board can be found in the applicable controller Reference Manual or datasheet The descriptions in this manual are based on the Freescale Semiconductor i MX6 description of compatible microcontroller derivative functions is included as such functions are not relevant for the basic functioning of the phyCARD i MX 6 PHYTEC Messtechnik GmbH 2014 1 800 0 1 phyCARD i MX 6 PCA A XL3 xxx The phyCARD i MX 6 offers the following features Subminiat
112. opto OD 00 dcm on on on 5 ooo 00 on ng
113. ower With this new SOM concept it is possible to design entire embedded product families around vastly different processor performances while optimizing overall system cost In addition future advances in processor technology are already considered with this new embedded bus standard making product upgrades very easy Another major advantage is the forgone risk of potential system hardware redesign steps caused by processor or other critical component discontinuation Just use one of PHYTEC s other phyCARD SOMs thereby ensuring an extended product life cycle of your embedded application Production ready Board Support Packages BSPs and Design Services for our hardware will further reduce your development time and risk and allow you to focus on your product expertise Take advantage of PHYTEC products to shorten time to market reduce development costs and avoid substantial design issues and risks With this new innovative full system solution you will be able to bring your new ideas to market in the most timely and cost efficient manner For more information go to http www phytec de de leistungen entwicklungsunterstuetzung html or www phytec eu europe oem integration evaluation start up html PHYTEC Messtechnik GmbH 2014 1 800 0 1 phyCARD i MX 6 PCA A XL3 xxx Ordering Information The part numbering of the phyCARD has the following structure PCA A XL3 xxxxxx Generation A First generation Performance class X
114. pIon aii REX EAE RR 7 I n 13 17 4 1 Primary System Power VDD 3 3 Nb eene 17 4 2 Backup Voltage VSTBY sccusssssusssusbxu boss saos cesse nons n oos 18 4 3 Power Management IC 029 Control Management IC U17 18 4 3 1 Power Management IC PMIC 29 2 18 4 3 2 Control Management IC CMIC 017 M 18 45922 Power DOMAINS cuc naun aaa oomen aaa aaa aaa aa 19 4 4 Supply Voltage for external Logic 8 21 5 Power eere NOn up eaae e 23 6 System Configuration and Booting 1 ecce eee e eee eee e eee eee eene eee 25 7 System Memory ooa 27 7 1 DDR3 SDRAM 2 09 27 7 2 NAND Flash Memory 3 27 7 3 T2C EEPROM 010 28 7 3 1 EEPROM Write Protection Control 93 28 8 SD MMCCard Interfa Stip Rp ccccrssccccssscccccs
115. pixel mapping all common 18 bit LVDS displays should work PHYTEC Messtechnik GmbH 2014 1 800 0 43 phyCARD i MX 6 PCA A XL3 xxx 18 bit LVDS Display 1 2 3 4 5 6 7 CLK 1 1 0 0 0 1 1 GO R5 R4 R3 R2 R1 RO Al B1 BO G5 G4 G3 G2 G1 A2 DE VSYNC HSYNC 5 B4 B3 B2 A3 0 0 0 0 0 0 0 Table 23 Pixel Mapping of 18 bit LVDS Display Interface 24 bit LVDS Display 1 2 3 4 5 6 7 CLK 1 1 0 0 0 1 1 G2 R7 R6 R5 R4 R3 R2 Al B3 B2 G7 G6 G5 G4 G3 A2 DE VSYNC HSYNC B7 6 5 4 A3 0 B1 BO G1 GO R1 RO Table 24 Pixel Mapping of 24 bit LVDS Display Interface 44 PHYTEC Messtechnik GmbH 2014 L 800e 0 LVDS Camera Interface 14 LVDS Camera Interface The phyCARD i MX 6 uses one 10 Bit LVDS Random Lock Deserializer U27 to receive LVDS Signals from a LVDS Camera Interface 1 channel The LVDS Deserializer converts the LVDS Signals to a 10 bit wide parallel data bus and separate clock which can be used as inputs for the 1 6 Camera Sensor Interfaces 027 is connected to CSIO The 10 bit wide data bus consists of 8 color information bits and 2 sync bits HSYNC VSYNC The following table shows the location of the applicable interface signals on the phyCARD Connector Pins Signal ST Voltage Domain Description X1A16 LVDS CAM MCLK 0 VDD 3V3 LOGIC Camera master clock X1B14 LVDS CAM RAH 1705 I VDD 3V3 LOGIC
116. ply Diagram 20 PHYTEC Messtechnik GmbH 2014 1 800 0 Power Requirements 4 4 Supply Voltage for external Logic The voltage level of the phyCARDs logic circuitry is 3V3 3 3 V which is derived from the main input voltage VDD_3V3 of the SOM In order to follow the power up and power down sequencing mandatory for the 1 6 external devices have to be supplied by the 1 0 supply voltage VDD 3V3 LOGIC which is brought out at pins X1A5 and X1B5 of the phyCARD Connector Use of VDD LOGIC ensures that external components are only supplied when the supply voltages of the i MX 6 are stable Caution The current draw for VDD_3V3_LOGIC must not exceed 500 mA If devices with a higher power consumption are to be connected to the phyCARD i MX 6 they should be switched on and off by use of VDD_3V3_LOGIC This way the power up and power down sequencing will be considered even if the devices are not supplied directly by VDD_3V3_LOGIC If used to control or supply bus switches the phyCARD side VDD LOGIC also serves to strictly separate the supply voltages generated on the phyCARD i MX 6 and the supply voltages used on the carrier board custom application That way voltages at the IO pins of the phyCARD i MX 6 which are sourced from the supply voltage of peripheral devices attached to the SOM are avoided These voltages can cause a current flow into the controller especially if peripheral devices attached to the interfaces of th
117. pre configured with 2 removable jumpers JP and 3 solder jumpers J The jumpers allow the user flexibility of configuring a limited number of features for development constraint purposes Table 31 ists the jumpers their default positions and their functions in each position Figure 14 depicts the jumper pad numbering scheme for reference when altering jumper settings on the development board Figure 15 provides a detailed view of the phyBase jumpers and their default settings In these diagrams a beveled edge indicates the location of pin 1 Before making connections to peripheral connectors it is advisable to consult the applicable section in this manual for setting the associated jumpers 1 1 Oj 2 2 I 1 5 IO O 4 5 2 0 e g JP1 e g Jl e g JP2 Figure 14 Typical Jumper Numbering Scheme Table 31 provides a comprehensive list of all carrier board jumpers The table only provides a concise summary of jumper descriptions Only jumpers supporting features of the phyCARD i MX 6 are described For a detailed description of each jumper see the applicable chapter listing in the right hand column of the table If manual modification of the solder jumpers is required please ensure that the board as well as surrounding components and sockets remain undamaged while de soldering Overheating the board can cause the solder pads to loosen rendering the board inoperable Carefully heat neighboring connections in
118. r PHYTEC part number lead free VB090 Component height 10 mm Manufacturer Molex Number of pins per contact row 100 2 rows of 50 pins each Molex part number lead free 53553 1079 header Two different heights are offered for the receptacle sockets that correspond to the connectors populating the underside of the phyCARD i MX 6 The given connector height indicates the distance between the two connected PCBs when the module is mounted on the corresponding carrier board In order to get the exact spacing the maximum component height 3 mm on the bottom side of the phyCARD must be subtracted Please refer to the corresponding data sheets and mechanical specifications provided by Molex www molek com 48 PHYTEC Messtechnik GmbH 2014 1 800 0 Technical Specifications PHYTEC Messtechnik GmbH 2014 1 800 0 40 phyCARD i MX 6 PCA A XL3 xxx 16 Hints for Integrating and Handling the phyCARD i MX 6 16 1 Integrating the phyCARD i MX 6 Besides this hardware manual much information is available to facilitate the integration of the phyCARD i MX 6 into customer applications 1 2 50 the design of the standard phyCARD Carrier Board can be used as a reference for any customer application many answers to common questions can be found at http www phytec de de support faq faq phyCARD i MX 6 html or http www phytec eu europe support fag faq phyCARD i MX 6 html a Design In Guide can be downloaded from the same
119. rnet Signals The Ethernet transceiver supports HP Auto MDIX technology eliminating the need for the consideration of a direct connect LAN cable or a cross over patch cable It detects the TX and RX pins of the connected device and automatically configures the PHY TX and RX pins accordingly The Ethernet controller also features an Auto negotiation to automatically determine the best speed and duplex mode The Ethernet transceiver is directly connected to the MII Interface of the i MX 6 Please refer to the 7 MX 6 Reference Manual for more information about this interface In order to connect the module to an existing 10 100Base T network some external circuitry is required The required 49 9 1 termination resistors on the analog signals ETH_TX are already populated on the module Connection to an external Ethernet magnetics should be done using very short signal traces The TPI TPI and signals should be routed as 100 O differential pairs The same applies for the signal lines after the transformer circuit The carrier board layout should avoid any other signal lines crossing the Ethernet signals An example for the external circuitry is shown in the phyCARD s Design Guide 34 PHYTEC Messtechnik GmbH 2014 L 800e 0 Serial Interfaces If you are using the applicable carrier board for the phyCARD i MX 6 part number PBA A 03 the external circuitry mentioned above is already integrated on the board
120. scccccesscccossscoocsssccccsseccccssssoooes 29 9 Serial Interfaces 4 9 31 9 1 Universal Asynchronous Interface 32 0 anane 32 9 3 USB Host Acn MEM 33 Dur ENIM CEN ACE 34 9 4 Wqu nrgrdddl fiku 34 DU SMAC Addres S eied rai E 35 OS E TE EAR 35 aa aa 36 9 7 125 Audio Interface SSI sssccesssscsesscesssccesssccessscesececesssscsssscesssscesasecssseeeses 36 ue cupo riu 38 13 oie ein eco n eco d ou od dv d d 39 12 Debug 40 13 LVDS Display Interface essessesscosecssesscsscoscsscssossosscssossossossosesssosessessessessessesees 43 13 1 LVDS Display Interface pixel mapping sssessssesessesessosessoseseesosessosessoseseesesesseseo 43 14 LVDS C mera 45 14 1 Signal De 45 15 Technical Specifications 46 PHYTEC Messtechnik GmbH 2014 1 800 0 1 phyCARD i MX 6 PCA A XL3 xxx 16 Hints for Integrating and Handling the phyCARD i MX 6 50 15 1 Integrating the phy ARD M 50 16 2 Handling the phyCARD I MX 9 E AAN ENAK 52 17 The phyCARD i MX 6 on the phyBASE
121. scription of each peripheral refer to the appropriate chapter listed in the applicable table Figure 13 highlights the location of each peripheral for easy identification s8 rJ S e Oo O jem 9 oo 90 00 m ae L i I LI 002 NEB 0 0 n mE a HB Bg eI a TOs AL b lt a X lt a J0j2euu 5 9 OS 0308 201990000 B Un 08 un ES 00 09 gun B 232 06 PU pa 9 00 B gt 00 C mom 00 00900 0006 zs aP op ing 5 002760 LO To 202 2 04000 E758 BB 1000 S mor D 8 popp 5 00 amp BT a nn EC o B En 0000 ge B oou Sah m o9 UT 3E 00 80000 5 o gg 00 m SI fee o 83 E 00 En B 00 5 5 1000 np 00 00 wawasan xp n 2 8 00000000 0 888 a o x dip ooo mona 8 lo Q B oo 000000009 gt oo BgsuaBH 5 O N 00 00 N B gt gg 590 o B E o 4 E vu m Bb E 05 U32 658 B gp 5 5 00000000 50 ing on deett 00000000 c A 51 01 125
122. should not be operated without protection circuitry if connections to the product s pin header rows are longer than 3 m PHYTEC products fulfill the norms of the European Union s Directive for Electro Magnetic Conformity only in accordance to the descriptions and rules of usage indicated in this hardware manual particularly in respect to the pin header row connectors power connector and serial interface to a host PC Implementation of PHYTEC products into target devices as well as user modifications and extensions of PHYTEC products is subject to renewed establishment of conformity to and certification of Electro Magnetic Directives Users should ensure conformance following any modifications to the products as well as implementation of the products into target systems Product Change Management and information in this manual on parts populated on the SOM When buying a PHYTEC SOM you will in addition to our HW and SW offerings receive a free obsolescence maintenance service for the HW we provide Our PCM Product Change Management Team of developers is continuously processing all incoming PCN s Product Change Notifications from vendors and distributors concerning parts which are being used in our products Possible impacts to the functionality of our products due to changes of functionality or obsolesce of a certain part are being evaluated in order to take the right masseurs in purchasing or within our HW SW design Our ge
123. so read the phyCARD Design In Guide for more information about how to use the 125 interface Ping Signal 1 0 SL Description X1A42 X AC97 INT 1 0 VDD_3V3_LOGIC 125 Interrupt Input connected to GPIO5 14 X1A43 X 125 SDATA OUT 0 00 3V3 LOGIC 125 Transmit Output X1A44 X I2S SDATA IN I VDD_3V3_LOGIC 125 Receive Input X1B42 125 I VDD 3V3 LOGIC 125 Transmit Clock 0 0 X1B43 125 SYNC VDD_3V3_LOGIC 125 Transmit Frame Sync 1 44 X I2S nRESET VDD 3V3 LOGIC Reset for external 125 device derived from 6 07 12 Table 18 551 Interface Signal Location PHYTEC Messtechnik GmbH 2014 1 800 0 37 phyCARD i MX 6 PCA A XL3 xxx 10 General Purpose I Os The X Arc bus provides 3 GPIO signals Table 19 shows the location of the GPIO IRQ pins on the phyCARD Connector as well as the corresponding ports of the i MX 6 Pind Signal 1 0 SL Description General purpose input output 0 GPIO2 24 of i MX 6 General purpose input output 2 04 29 of i MX 6 General purpose input output 1 GPIO1 6 of i MX 6 X1A46 X GPIOO IRQO VDD 3V3 LOGIC X1A47 X GPIO2 IRQ PWM 1 0 LOGIC X1B47 X GPIO1 IRO1 1 0 VDD 3V3 LOGIC Table 19 Location of GPIO and IRQ pins As can be seen in the table above the voltage level is VDD LOGIC which is 3 3 V In other words 3 3 LOGIC is identical with the supp
124. t 2014 PHYTEC Messtechnik GmbH D 55129 Mainz Rights including those of translation reprint broadcast photomechanical or similar reproduction and storage or processing in computer systems in whole or in part are reserved No reproduction may occur without the express written consent from PHYTEC Messtechnik GmbH EUROPE NORTH AMERICA Address PHYTEC Messtechnik GmbH PHYTEC America LLC Robert Koch Str 39 203 Parfitt Way SW Suite G100 D 55129 Mainz Bainbridge Island WA 98110 GERMANY USA Ordering 49 6131 9221 32 1 800 278 9913 Information sales phytec de sales phytec com Technical 49 6131 9221 31 1 800 278 9913 Support support phytec de support phytec com Fax 49 6131 9221 33 1 206 780 9135 http www phytec de Web Site uff phytec eu http www phytec com Preliminary Edition August 2014 PHYTEC Messtechnik GmbH 2014 1 800 0 Contents List REV EE EE E EE ERE RR iii List of Tables ce T iv Conventions Abbreviations and Acronyms 0000000009000000 0000000000000000000 vii PRET ACE Scu cun ix E BA a a rr tr er rer tr re re etn nn ndn rr rt re 1 3 1 2 View ot tie phyCARD AI MA aaa saa 4 1 3 Minimum Requirements to Operate the phyCARD i MX 6 6 Pin Descri
125. the help of the phyCARD s X nPOWER OFF signal GPIO1 25 of the 1 6 To enter OFF state signal X nPOWER OFF must be active low for at least 100 ms SUSPEND state can be entered using signal X nSUSPEND RAM at pin X27B26 of the phyCARD Connector GPIO1 24 of the i MX 6 X nSUSPEND RAM must be active low for at least 100 ms PHYTEC Messtechnik GmbH 2014 1 800 0 67 phyCARD i MX 6 PCA A XL3 xxx 17 3 3 RS 232 Connectivity P1 O o 9 5 ololo HE 8 000000 9 27 HEB 0000 00 000000 mig oo 858 5988 ome WU oe w open HB of unon 57 0000 00 poopoo as BES 58 BH 00 pana 2 _ 00 5 0 0 00 8 Js pon BB 05000 0000 200299920 9868 505 0 0 030 BB mm 0 0000 0000 oo 30 0000 50 g Mas am 0000 0000 000 0 aj 0000 0 0000 0000 00070 gg End gy E ooo an 8 npn an 00 00 5 10000000 0000980000 0000980000 B un pr 000049490000 SLs 0000000000 B 5010 00 soo B gg 10000000 2 n e a p ET 00 nm
126. the signal SEL AC INT the TI audio CODEC U17 is selected to process the 125 compliant audio signals while the dedicated touch contrl at U28 handles the signals from a touch screen Switches 3 and 4 of DIP Switch S3 configure the address for the 53 3 communication between CPLD and phyCARD S3 4 0 0 CPLD Address 0x40 7 MSB Switch 5 of DIP Switch 53 selects the interface used for the 53 5 communication between CPLD and phyCARD 0 communication selected Switch 6 of DIP Switch S3 turns the SPI Multiplexer on or off 536 0 SPI multiplexer off Switches 7 and 8 of DIP Switch S3 map the two slave select signals of the SPI interface and the two GPIO_IRQ signals 6100 GPIO1 IRQ to two of the three available connectors 14323 s3 7 0 0 SSO GPIOO gt extension O X8A 17 3 10 3 8 SS1 GPIO1 gt extension 1 X9A 17 3 11 i 0 1 550 00 gt extension 0 X8A 17 3 12 SS1 GPIO1 gt display data connector X6 1 x SSO GPIOO0 gt extension 1 9 SS1 GPIO1 gt display data connector X6 Table 29 phyBASE DIP Switch S3 Descriptions Default settings are in bold blue text PHYTEC Messtechnik GmbH 2014 1 800 0 59 phyCARD i MX 6 PCA A XL3 xxx 17 2 3 LEDs The phyBASE is populated with numerous LEDs to indicate the status of the various USB Host interfaces as well as the different supply voltages Figure 13 shows the location of the LE
127. tic Interference GPI General purpose input GPIO General purpose input and output GPO General purpose output IRAM Internal RAM the internal static RAM on the Freescale Semiconductor 1 6 microcontroller J Solder jumper these types of jumpers require solder equipment to remove and place JP Solderless jumper these types of jumpers can be removed and placed by hand with no special tools PCB Printed circuit board PDI PHYTEC Display Interface defined to connect PHYTEC display adapter boards or custom adapters PEB PHYTEC Extension Board PMIC Power management IC PoE Power over Ethernet PoP Package on Package POR Power on reset RTC Real time clock SMT Surface mount technology SOM System on Module used in reference to PCA A XS1 phyCARD 1 6 module Sx User button Sx e g 51 52 used in reference to the available user buttons or DIP Switches on the CB Sx y Switch y of DIP Switch Sx used in reference to the DIP Switch on the carrier board VSTBY SOM standby voltage input Table 1 Abbreviations and Acronyms used in this Manual Note The BSP delivered with the phyCARD i MX 6 usually includes drivers and or software for controlling all components such as interfaces memory etc Therefore programming close to hardware at register level is not necessary in most cases For this reason this manual contains no detailed description of the controller s registers or information relevant for software development Please refer
128. tion about connecting an SD MMC Card slot to the phyCARD i MX 6 30 PHYTEC Messtechnik GmbH 2014 L 800e 0 Serial Interfaces 9 Serial Interfaces The phyCARD i MX 6 provides seven serial interfaces some of which are equipped with a transceiver to allow direct connection to external devices 1 High speed UART TTL derived from UART3 of the 1 6 with up to 4 MHz and hardware flow control RTS and CTS signals 2 High speed USB OTG interface extended directly from the 1 6 USB HS OTG PHY USB PHY 3 High speed USB HOST interface extended directly from the 1 6 USB HOST USB PHY 4 Auto MDIX enabled 10 100 Ethernet interface implemented with an Ethernet PHY attached to the i MX 6 ENET interface 5 derived from second I C port I2C2 ofthe i MX 6 6 Serial Peripheral Interface SPI interface extended from the third SPI module eCSPI3 of the i MX 6 7 15 audio interface Synchronous Serial Interface SSI5 originating from the fifth port of the i MX 6 s Synchronous Serial Interface SSI5 The following sections of this chapter detail each of these serial interfaces and any applicable configuration jumpers Caution The 1 6 s power sequencing requires strict separation of the supply voltages generated on the phyCARD i MX6 and the supply voltages used the carrier board custom application Especially if peripheral devices attached to the interfaces of the
129. to 1 6 Reference Manual if such information is needed to connect customer designed applications viii PHYTEC Messtechnik GmbH 2014 L 800e 0 Preface Preface As a member of PHYTEC s new phyCARD product family the phyCARD i MX 6 is one of a series of PHYTEC System on Modules SOMs that can be populated with different controllers and hence offers various functions and configurations PHYTEC supports a variety of 8 16 and 32 bit controllers in two ways 1 asthe basis for Rapid Development Kits which serve as a reference and evaluation platform 2 as insert ready fully functional phyCARD OEM modules which can be embedded directly into the user s peripheral hardware design Implementation of an OEM able SOM subassembly as the core of your embedded design allows you to focus on hardware peripherals and firmware without expending resources to re invent microcontroller circuitry Furthermore much of the value of the phyCARD module lies in its layout and test PHYTEC s new phyCARD product family consists of a series of extremely compact embedded control engines featuring various processing performance classes while using the newly developed X Arc embedded bus standard The standardized connector footprint and pin assignment of the X Arc bus makes this new SOM generation extremely scalable and flexible This also allows to use the same carrier board to create different applications depending on the required processing p
130. ure System on Module 60mm x 60 mm achieved through modern SMD technology Populated with the Freescale Semiconductor i MX6 microcontroller BGA624 packaging Improved interference safety achieved through multi layer PCB technology and dedicated ground pins X Arc bus including commonly used interfaces such as Ethernet USB UART SPI audio camera and display connectivity LVDS available at one 100 pin high density 0 635 mm Molex connector enabling the phyCARD i MX 6 to be plugged like a big chip into the target application Max 1 GHz core clock frequency Boot from different memory devices NAND Flash standard RAM memory device with 512 MB up to 4 GB DDR3 SDRAM 256 MB up to 4 GB on board NAND Flash VFBGA Up to 32 Kbit I C EEPROM Serial interface with 4 lines TTL allowing simple hardware handshake High Speed USB OTG interface High Speed USB HOST interface Auto HDX FDX 10 100MBit Ethernet interface with HP Auto MDI MDI X support I C interfaces One SPI interfaces 15 SSI audio interface 4 channel LVDS 24 bit LCD interface LVDS camera interface phyCAM S compatible SD MMC card interface with DMA Support of standard 20 pin debug interface through JTAG connector Additional serial interface connector for debugging 3 GPIO IRQ ports 2 Power State outputs to support applications requiring a power management 1 Wake Up input Two user programmable LEDs Single supply voltage of 3 3 V max 1 5 A
131. wing list summarizes the relation between the different voltage rails and the devices on the phyCARD i MX 6 External voltages 3V3 and VSTBY IN Internally generated voltages MX6 ARM 1V4 1 375 V VDD MX6 SOC 1 375 V VDD 3V3 LOGIC 3 3 V VDD MX6 SNVS 3 0 V VDD HIGH 3 0 V VDD DDR3 TERM 1 2V VDD DDR3 1V5 1 5 V DDR3 VIT 0 75 V DDR3 VREF 0 75 V VDD MX6 ARM 1V4 i MX6 core VDDARM IN VDDARM23 IN 1 375 V e MX6 SOC 1 6 SOC VDDSOC IN 1 375 V e VDD HIGH 1 6 internal regulator IN 3 0 V e VDD MX6 SNVS 1 6 backup supply VDD SNVS IN 3 0 V e VDD DDR3 1V5 1 6 DDR NVCC_DRAM RAM devices supply voltage 1 5 V e DDR3 VIF RAM devices termination voltage 0 75 V DDR3 VREF 1 6 DDR3 reference voltage DRAM VREF RAM 0 75 V devices reference voltage e VDD 3V3 LOGIC 1 6 pad supply NVCC_NANDF NVCC JTAG NVCC LCD 3 3 V NVCC CST NVCC NVCC GPIO 12C EEPROM SPI Flash NAND Flash Camera Deserializer Ethernet PHY EMIC USB VBUS USB Host OTG PHY 5V PHYTEC Messtechnik GmbH 2014 1 800 0 19 phyCARD i MX 6 PCA A XL3 xxx VDD 3V3 VSTBY IN VDD 3V3 LOGIC mM 6 ARM 1 4 VDD MX6 SOC S amp F VDD DDR3 1V5 E DDR3 VTT 2 VDD DDR3 TERM DDR3 VREF DA9063 VDD MX6 SNVS e VDD MX6 HIGH USB VBUS USB 5V Chargepump 1 8 Power Sup

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