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Synplicity`s HAPS Development Platform IP Core User`s Manual

1. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 31 30 HapsTrak 1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 31 HapsTrak 31 input unused 30 1 HapsTrak 30 1 input a k a hapstraka 30 1 0 HapsTrak 0 input unused Table 13 Input register 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 63 62 HapsTrak 33 32 JAJAJA A A A A A A A A A A A A A A A A A A A A A A A A AJA A 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37136 35 34 33 32 31 31 HapsTrak 63 input unused 30 1 HapsTrak 62 33 input a k a hapstraka 60 31 0 HapsTrak 32 input unused Table 14 Input register 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 95 94 HapsTrak 65 64 BI IBIB BIB B B BIB B BB B BB BB BI
2. 5 7 Signal descriptions Table 25 shows the interface signals of the core VHDL ports Table 25 Signal descriptions Signal name Field Type Function Active RST N A Input Reset Low CLK N A Input Clock APBI Input APB slave input signals APBO Output APB slave output signals HAPSTRAKO DOUT 127 0 Output Output data OEN 127 0 Output Output enable VAL 127 0 Output Synchronized input data SIG OUT 127 0 Output Asynchronous input data HAPSTRAKI DIN 127 0 Input Input data see GRLIB IP Library User s Manual 5 8 Library dependencies Table 26 shows libraries used when instantiating the core VHDL libraries Table 26 Library dependencies Library Package Imported unit s Description GRLIB AMBA Signals AMBA signal definitions GAISLER HAPS Signals component Component declaration 5 9 Component declaration The core has the following component declaration component hapstrak generic pindex integer 0 paddr integer 0 pmask integer 16 fff port f rst in std logic clk in std logic apbi in apb slv in type apbo out apb slv out type hapstraki in hapstrak in type hapstrako out hapstrak out type end component S 10 Instantiation This example shows how the core can be instantiated library grlib use grlib amba all library gaisler use gaisler haps all entity leon3mp is port hapstraka inout std logic vector 60 dovmto 1 hapstrakb inout std
3. 11 4 3 Ra OSSE Se 12 4 4 REFI p EE 12 4 5 Vendor and device identifier cec RR TERR ee e e I RI eer 13 4 6 Configuration options uscire eO ir RO em oca Renier rad 13 4 7 Signal descriptions aee ed Ree een 13 4 8 Library dependencies epe eet Ce e RUD e SERRE Ne e RU E ceret eed 13 4 9 Component declarations i ete NN E Sd 14 4 10 nstanhation zoe IRR URSI RE RA AR n RU 14 HAPSTRAK HapsTrak controller for HAPS boards eee 15 5 1 ener eir TRE RR E n PER r b 15 5 2 Operati D T y d m UD m m l 15 5 3 GRAL R A DR A R s 16 5 4 16 95 eco reed rte e e dte gn bar PE 19 5 6 Configuration Optlons eee eoe Eee e i eap RE HE Aa ln ER REN 19 5 7 Signal descriptions eie t estote it eee ha ES eee guts 20 5 8 Library dependencies 7 eeu eot e aa E b 20 5 9 Component declaration IRURE a e RU d Us E 20 5 10 Tnstantiat onae HD decime fedet m b 20 BIOI Controller for HAPS Basic I O daughter board BIOI 2222 22 6 1 SYNE 22 6 2 Operation me t NE th OU et intet ad dU de AG ode Ee e DU E O 22 6 3 COTS USAGE P 23 6 4 Registets
4. 0 lt sd0o address sdcke0 lt sd0o sdcke sdwen0 lt sd0o sdwen sdcsn0 lt sd0o sdcsn sdrasn0 sd0o rasn sdcasn0 sd0o casn sddqm0 lt sd0o dqm sal lt sdlo address sdckel lt sdlo sdcke sdvenl lt sdlo sdwen sdcsnl lt sdlo sdcsn sdrasnl lt sdlo rasn sdcasnl lt sdlo casn sddqml sdlo dqm Data pad instantiation with scalar bdrive sd0 pad iopadv generic map width gt 32 port map sd0 31 downto 0 sd0o data sd0o bdrive sd0i data 31 downto 0 sd1 pad iopadv generic map width gt 32 port map sd1 31 downto 0 sdlo data sdlo bdrive sdli data 31 downto 0 Alternative data pad instantiation vith vectored bdrive sd0 pad iopadvv generic map width gt 32 port map sd0 31 downto 0 sd0o data sd0o vbdrive sd0i data 31 downto 0 sd1 pad iopadvv generic map width gt 32 port map sd1 31 downto 0 sdlo data sdlo vbdrive sdli data 31 downto 0 end 29 30 8 1 8 2 8 3 DDR 1X1 DDR266 Controller for HAPSDDR 1x1 Overview The memory controller for the Synplicity HAPS DDR 1x1 daughter boards is a 64 bit DDR266 con troller that interfaces external DDR SDRAM to the AMBA AHB bus The memory controller acts as a slave on the AHB bus and has a configuration register accessible through the AHB I O address space The memory controller is based on the Gaisler Research DDRSPA 16 32 64 bit DDR266 Control ler See corresponding manual for details
5. Runlibusb win32 filter bin 0 1 12 1 exe or later and follow the instructions GRMON Unzip the file grmon eval 1 1 28 tar gz or later and place the folder vvin32 with five files in 1t in the installation directory Add the search path to the file grmon eval exe i e c Maps gaislerwin32N to the environment variable PATH SPARC ELF GCC if compilation is desired Unzip the file sparc elf 3 4 4 1 0 30 mingw zip or later and place the folder sparc elf 3 4 4 in the installation directory Add the search path to the directory bin i e c haps gaisler sparc elf 3 4 4 bin to the envi ronment variable PATH 14 6 59 Hardvvare setup 14 6 1 Setting up the HAPS 51 motherboard This describes the setup for the HAPS 51 motherboard Configure voltage region V1b V2a and V3b to 3 3V Configure voltage region V2b and V3a to 2 5V Connect the BIO1 to GPIO 1 10 Connect the GEPHY 1x1 on connector A5 Optional Jumper J4 int voltage source Jumper JS and J7 2 5V Jumper J6 and J8 125 MHz Connect the SDRAM 1 1 on connector A2 Optional Connect the DDR 1x1 on connector A4 Optional Configure the frequency select switch 1 to 00011 00101 100 MHz Connect a coax cable from OSCI a to GC1 Connect the Xilinx USB cable to JTAG IN iMPACT Configure the board with the design c haps gaisler designs leon3 hardi haps5 1 bitfiles leon3mp bit iMPACT Select Output gt Ca
6. Ee Uie range 1 to 64 range 4 to 128 16400005Ef 1640000004 16 c0a8 16 0035 range 0 to 32 range 0 tol range 0 to 1 0 i 9 6 nsync mdcscaler memtech oepol Scanen 3 port rst clk ahbmi0 ahbmo0 apbi0 apbo0 ethi0 etho0 ahbmil ahbmol apbil apbol ethil ethol end component Instantiation integer integer integer integer integer range range sm Us range range in std ulogic in std ulogic in ahb mst in type out ahb mst out type in slv in type out apb slv out type in eth in type I to 2 2 2 O to 255 25 Otol to 1 out eth out type in ahb mst in type out ahb mst out type in apb slv in type out apb slv out type in eth in type out eth out type This example shovvs hovv the core can be instantiated library ieee use ieee std logic 1164 all library grlib use grlib amba all library gaisler use gaisler haps all entity greth ex is port end clk in std ulogic rstn in std ulogic ethernet s ethi0 in etho0 in ethil in ethol in h architecture rtl AMBA signals signal apbi signal apbo signal ahbmi signal ahbmo begin ignals eth in type eth out type eth in type eth out type of greth ex is apb slv in type apb slv out vector ahb mst in type ahb mst out vector others apb none others ahbm none AMBA Component
7. HAPS the HAPS logo High performance ASIC Prototyping System and HapsTrak HapsTrak I and HapsTrak II are trademarks of Synplicity Inc Vendor and device identifier The core has vendor identifier 0x01 Gaisler Research and device identifier 0x00A For description of vendor and device identifiers see GRLIB IP Library User s Manual Library dependencies Table 2 shows libraries used when instantiating the core VHDL libraries Table 2 Library dependencies Library Package Imported unit s Description GRLIB AMBA Signals AMBA signal definitions GAISLER MEMCTRL Signals Signal declarations GAISLER HAPS Component Component declaration 2 4 2 5 Component declaration The core has the following component declaration component flash 1x1 is generic hindex integer 0 pindex integer 0 romaddr integer 16400048 rommask integer 16 E00 ioaddr integer 16142008 iomask integer 16HE00 ramaddr integer 16144008 rammask integer 16 008 paddr integer 0 pmask integer 16 fff bus16 integer 0 tech integer 0 netlist integer 0 port rst in std ulogic clk in std ulogic ahbsi in ahb slv in type ahbso out ahb slv out type apbi in apb slv in type apbo out apb slv out type sri in memory in type sro out memory out type end component Instantiation This example shovvs hovv the core can be instantiated library g use g
8. abstract abstract abstract abstract abstract abstract abstract abstract 39 40 10 10 1 LEON3 template design for HAPS 31 motherboard Overvievv The LEON3 template design for the HAPS 31 motherboard from Synplicity assumes the presence of the SRAM_1x1 FLASH 1 1 SDRAM_1x1 DDR 1xl and GEPHY 1x1 daughter boards and the BIO1 VO board For more information about HAPS visit vvvvvv synplicity com Figure 9 Synplicity s HAPS 31 motherboard The LEON3 architecture for the HAPS 31 motherboards includes the following modules LEON3 SPARC V8 Integer Unit optional MMU and FPU Debug Support Unit with AMBA trace buffer JTAG Debug Link Timer unit with 32 bit timers Interrupt controller for 15 interrupts in two priority levels UART with FIFO and baud rate generator accessed via the BIO1 board AMBA AHB status register Extra Synchronous SRAM controller for SRAM 1x1 daughter board SRAM 1X1 core Extra PROM controller for FLASH 1x1 daughter board FLASH 1X1 core Extra SDRAM controller for SDRAM 1x1 daughter board SDRAM 1X1 core Extra DDR controller for DDR 1x1 daughter board DDR 1X1 core Extra Ethernet controller for GEPHY 1x1 daughter board GEPHY 1X1 core For more information about the GRLIB IP Library visit www gaisler com 41 3 Port 3 Port Register File File EE LEONS FT SPARC Trace Support FLASH 1x1 DDR ixi HapsTrak Mul Div 32t Integer Unit Butter Unit Interface
9. see GRLIB IP Library User s Manual Library dependencies Table 10 shows libraries used when instantiating the core VHDL libraries Table 10 Library dependencies Library Package Imported unit s Description GRLIB AMBA Signals AMBA signal definitions GAISLER HAPS Signals component Component declaration 14 4 9 Component declaration The core has the following component declaration component test 1x2 generic pindex integer 0 paddr integer 0 pmask integer 16 fff fdiv integer 1000000 port rst in std logic clk in std logic apbi in apb slv in type apbo out apb slv out type test 1x2i in test 1x2 in type test 1x20 out test 1x2 out type end component 4 10 Instantiation This example shows how the core can be instantiated library grlib use grlib amba all library gaisler use gaisler haps all Signal test 1x2i test 1x2 in type Signal test 1x20 test 1x2 out type begin test 1x2 gen if CFG TEST 1X2 0 generate test 1x2 inst test 1x2 generic map pindex 5 paddr gt 5 fdiv gt 1000000 port map rst gt rstn Clk clkm apbi apbi apbo apbo 5 test 1x2i test 1x2i test 1x20 test 1x20 end generate 5 1 5 2 15 HAPSTRAK HapsTrak controller for HAPS boards Overvievv HapsTrak is a connector and module standard developed by Synplicity to be used with their HAPS mot
10. e Xilinx ISE 9 2 031 or later or corresponding web pack version Downloads HAPS GPL GRMON and SPARC ELF GCC can be downloaded from http www gaisler com Downloads gt LEON GRLIB gt grlib haps 1 0 18 tar gz or later Downloads gt GRMON gt grmon eval 1 1 28 tar gz or later Downloads gt Compilers gt BCC binaries for Linux and Windows gt windows gt sparc elf 3 4 4 1 0 30 mingw zip or later Note that only the HAPS GPL distribution with programming files for the LEON3 template designs is required for the demonstration of the LEON3 processor on the HAPS 50 motherboards For those wanting to modify the HAPS template designs the complete GRLIB IP core library also needs to be downloaded in source from http vvvvvv gaisler com After the GRLIB IP core library has been down loaded and extracted the grlib haps tar gz should be extracted into the grlib directory Downloads gt LEON GRLIB gt grlib gpl 1 0 18 tar gz or later Software installation For explanation purposes the installation instruction assumes the installation directory is c haps gaisler and that the design files are located in c haps gaisler designs HAPS GPL bitfiles Unzip the file grlib haps 1 0 18 tar gz or later in the installation directory thereby creating the c Maps gaisler designs directory and also the c haps gaisler lib gaisler haps and c Maps gaisler boards directories not used here LibUsb Win32
11. The DDRSPA IP core is provided in VHDL source code as part of the GRLIB GPL distribution Figure 7 HAPS DDR 1x1 daughter board More information on HAPS can be found at www synplicity com Synplicity the Synplicity logo and Simply Better Results are registered trademarks of Synplicity Inc HAPS the HAPS logo High performance ASIC Prototyping System and HapsTrak HapsTrak I and HapsTrak II are trademarks of Synplicity Inc Vendor and device identifier The core has vendor identifier 0x01 Gaisler Research and device identifier 0x025 For description of vendor and device identifiers see GRLIB IP Library User s Manual Library dependencies Table 36 shows libraries used when instantiating the core VHDL libraries Table 36 Library dependencies Library Package Imported unit s Description GRLIB AMBA Signals AMBA signal definitions GAISLER MEMCTRL Signals Signal declarations GAISLER HAPS Component Component declaration 8 4 8 5 Component declaration The core has the following component declaration component ddr 1x1 generic fabtech integer 0 memtech integer 0 hindex integer 0 haddr integer 0 hmask integer 16 f00 ioaddr integer 1680004 iomask integer 16 fff MHz integer 100 clkmul integer 2 clkdiv integer 2 col integer 9 Mbyte integer 16 rstdel integer 200 pwron integer 0 oepo
12. colon 4 5 4 6 4 7 4 8 Table 7 LED register 13 31 24 23 13 12 11 10 1 0 000 0 L12 L1 L12 L1 Red Red Green Green 23 12 Red LEDs L12 to L1 11 0 Vendor and device identifiers Green LEDs L12 to L1 The core has vendor identifier 0x01 Gaisler Research and device identifier 0x078 For description of vendor and device identifiers see GRLIB IP Library User s Manual Configuration options Table 8 shows the configuration options of the core VHDL generics Table 8 Configuration options Generic Function Allowed range Default pindex Selects which APB select signal PSEL will be used to to NAPBMAX 1 0 access the GPIO unit paddr The 12 bit MSB APB address 0 to 16 FFF 0 pmask The APB address mask 0 to 168FFF 16 FFF fdiv Defines division factor for generating LCD clock Integer 1000000 Signal descriptions Table 9 shows the interface signals of the core VHDL ports Table 9 Signal descriptions Signal name Field Type Function Active RST N A Input Reset Low CLK N A Input Clock APBI Input APB slave input signals APBO Output APB slave output signals TEST_1X20 LCD CLK 1 0 Output LCD clock output LCD SEG 31 0 Output LCD segment output GREEN LED N 11 0 Output Green LEDs output Low RED LED N 11 0 Output Red LEDs output Low TEST 1X21 BUTTON N 11 01 Input Buttons input Low
13. unused 5 5 5 6 Table 20 Output Enable register 0 19 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 31 30 HapsTrak 1 TAAAAAAAAAAAAAAAAAAAAA AAAAAAA AA lA 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13112 11 10 9 8 7 6 5 4 3 2 1 31 HapsTrak 31 output enable unused 30 1 HapsTrak 30 1 output enable a k a hapstraka 30 1 0 HapsTrak 0 output enable unused Table 21 Output Enable register 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 6 5 4 3 2 1 0 63 62 HapsTrak 33 32 TAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A l A 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 31 HapsTrak 63 output enable unused 30 1 HapsTrak 62 33 output enable a k a hapstraka 60 31 0 HapsTrak 32 output enable unused Table 22 Output Enable register 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 95 94 HapsTrak
14. 0x01C SRAM_1X1 32 bit SSRAM PROM Controller for HAPS SRAM_1x1 0x01 0x00A DDR2SPA 16 32 and 64 bit DDR2 Controller 0x01 0x02E AHBSTAT AHB failing address register 0x01 0x052 APBUART 8 bit UART with FIFO 0x01 0x00C GPTIMER Modular timer unit with watchdog 0x01 0x011 GRGPIO General purpose I O port 0x01 0x01A IROMP LEON3 Interrupt controller 0x01 0x00D I2CMST I C master 0x01 0x028 HAPSTRAK HapsTrak controller for HAPS boards 0x01 0x077 SDRAM IXI Dual 32 bit SDRAM Controller for HAPS SDRAM 1x1 0x01 0x009 DDR 1 1 64 bit DDR266 Controller for HAPS DDR 1x1 0x01 0x025 GEPHY 1X1 Dual Ethernet Controller for HAPS GEPHY 1x1 0x01 0x01D BIO1 BIO1 Controller for HAPS BIO1 0x01 0x07A Interrupts All interrupts are handled by the interrupt controller and forwarded to the LEON3 processor See the GRLIB IP Core User s Manual for how and when the interrupts are raised Table 44 Interrupt assignment Core Interrupt Comment AHBSTAT 7 APBUART 0 2 APBUART 1 3 GPTIMER 8 9 GEPHY_1X1 10 12 I2CMST 11 48 11 5 Memory map The memory map shown in table 45 is based on the AMBA AHB address space Access to addresses outside the ranges vvill return an AHB error response Table 45 AMBA AHB address range Core Address range Area SRAM_1X1 0x00000000 0x10000000 Flash PROM area not all used 0x40000000 0x60000000 SSRAM area not all used DDR2SPA 0x600000
15. 65 64 BB BB B BB B B BBB BB B B B BIB BB B BIB B BB BIB B BIB B 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13112 1111019186 71645 72413 2 1 31 HapsTrak 95 output enable unused 30 1 HapsTrak 94 65 output enable a k a hapstrakb 30 1 0 HapsTrak 64 output enable unused Table 23 Output Enable register 3 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 127 126 125 HapsTrak 97 96 BB BB BIB BBB BB B BIB B BIB BB B BIB B B 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45144 43 42 41 40 39 38 37 36 35 34 33 32 31 31 HapsTrak 127 output enable unused 30 HapsTrak 126 output enable unused 29 1 HapsTrak 125 97 output enable a k a hapstrakb 60 31 0 HapsTrak 96 output enable unused Vendor and device identifiers The core has vendor identifier 0x01 Gaisler Research and device identifier 0x077 For description of vendor and device identifiers see GRLIB IP Library User s Manual Configuration options Table 24 shows the configuration options of the core VHDL generics Table 24 Configuration options Generic Function Allowed range Default pindex Selects which APB select signal PSEL will be used to to NAPBMAX 1 0 access the GPIO unit paddr The 12 bit MSB APB address 0 to 16 FFF 0 pmask The APB address mask 0 to 16 FFF 16 FFF 20
16. Controller Controller Controller 5 1x1 Cache D D Cache AMBA SRAM 1x1 7 a ITLB SRMMU DTLB Uc Controller 7 5 AHBCTRL 32 bit AMBA AHB 32 bit AMBA APB inan APBCTRL Figure 10 LEON3 template design for HAPS 31 motherboard 10 2 Configuration The HAPS 31 LEON3 template design can be configured by means of commands described in the GRLIB IP Library User s Manual The Xilinx ucf pin placement file for the motherboard can be generated from the leon3mp pas and leon3mp con files using the HapsMap software from Synplicity After editing the leon3mp pas or leon3mp con file run the following command to generate a new ucf file make hapsmap Ensure that the hapsmap executable is the search path For details please refer to the HAPS manuals from Synplicity The 40 MHz template design assumes an external clock frequency of 100 MHz See HAPS 31 moth erboard documentation for appropriate settings of the external clock generator circuitry The on board 16 MHz oscillator should be used with the settings N 1 and M 25 Please refer to the leon3mp con and leon3mp pas files in the template design directory for the detail configuration of the board 42 10 3 10 4 Cores The LEON3 HAPS 31 template design is based on cores from the GRLIB IP library The vendor and device identifiers for each core can be extracted from the plug amp play information as described in the GRLIB IP Core User s Manual The used IP cores
17. S1 23 16 Buttons S8 to S1 15 8 Buttons S8 to S1 ils 0 Buttons S8 to S1 Table 29 LED digits register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 4 4G 4F 4E 4D 4C 4B 4A 3 3G SF 3E 8D 3C 3B 3A 2 2G 2F 2E 2D 2C 2B 2A 1 1G 1F 1E 1D 1C 1B 1A DP DP DP DP 4A 3A 4F 4B 3F 3B 2F 4E 4C 3E B 3C 2E IF cgo LM Me 40 4 30 3DP 2DP ID IDP 31 4DP fourth decimal point 30 24 Character 4 23 3DP third decimal point 22 16 Character 3 15 2DP second decimal point 14 8 Character 2 IDP first decimal point 0 Character 1 24 6 5 6 6 Table 30 LED register 31 16 15 9 8 7 1 0 000 0 L12 L1 L8 L1 Red Red Green Green 31 16 Unused 15 Red LEDs L1 to L8 7 Green LEDs L1 to L8 Table 31 control register 31 16 15 0 Uodate rate Bit rate 31 16 Update rate 15 0 Bit rate Vendor and device identifiers The core has vendor identifier 0x01 Gaisler Research and device identifier 0x07A For description of vendor and device identifiers see GRLIB IP Library User s Manual Configuration options Table 32 shows the configuration options of the core VHDL generics Table 32 Configuration options Generic Function Allowed range Default sysclk AMBA system clock frequency in
18. any purpose neither implicit nor explicit Synplicity the Synplicity logo and Simply Better Results are registered trademarks of Synplicity Inc HAPS the HAPS logo High performance ASIC Prototyping System and HapsTrak HapsTrak I and HapsTrak II are trademarks of Synplicity Inc
19. are listed in table 39 Table 39 Used IP cores Core Function Vendor Device AHBCTRL AHB Arbiter amp Decoder 0x01 APBCTRL AHB APB Bridge 0x01 0x006 LEON3 LEON3 SPARC V8 32 bit processor 0x01 0x003 DSU3 LEON3 Debug support unit 0x01 0x004 AHBJTAG JTAG AHB debug interface 0x01 0x01C SRAM 1 1 32 bit SSRAM PROM Controller for HAPS SRAM 1x1 0x01 0x00A FLASH 1 1 32 16 bit PROM Controller for HAPS FLASH 1x1 0x01 0x00A AHBSTAT AHB failing address register 0x01 0x052 APBUART 8 bit UART with FIFO 0x01 0x00C GPTIMER Modular timer unit with watchdog 0x01 0x011 IRQMP LEON3 Interrupt controller 0x01 0x00D HAPSTRAK HapsTrak controller for HAPS boards 0x01 0x077 SDRAM 1 1 Dual 32 bit SDRAM Controller for HAPS SDRAM 1x1 0x01 0x009 DDR 1 1 64 bit DDR266 Controller for HAPS DDR 1x1 0x01 0x025 GEPHY 1X1 Dual Ethernet Controller for HAPS GEPHY 1x1 0x01 x01D BIO1 BIO1 Controller for HAPS BIO1 0x01 0x07A Interrupts All interrupts are handled by the interrupt controller and forwarded to the LEON3 processor See the GRLIB IP Core User s Manual for how and when the interrupts are raised Table 40 Interrupt assignment Core Interrupt Comment AHBSTAT 7 APBUART 2 GPTIMER 8 9 GEPHY 1X1 10 12 10 5 10 6 43 Memory map The memory map shown in table 41 is based on the AMBA AHB address space Access to addresses outside the ranges will return an AH
20. daughter board GEPHY_1X1 0x80000B00 0x80000C00 AHBSTAT 0x80000F00 0x80001000 APB plug amp play 0x800FF000 0x80100000 Setup This describes the setup for the HAPS 31 motherboard e Configure voltage region V1 V2 and V3 to 3 3V e Configure voltage region V4 and V5 to 2 5V Configure the frequency select switch to 01011 00101 100 MHz e Connect the SRAM_1x1 on connector Al Voltage select int 2 3 PLL on S1 e Connect the BIO1 to GPIO 1 10 e Connect the FLASH 1x1 on connector A3 Optional Jumper J2 and J4 Word mode 1 2 44 Connect the SDRAM 1 1 on connector A2 Optional Connect the DDR 1x1 on connector AS Optional Connect the GEPHY 1x1 on connector A4 Optional Jumper J4 int voltage source Jumper J5 and J7 2 5V Jumper J6 and J8 125 MHz Connect the Xilinx USB cable to JTAG IN iMPACT Configure the board with the design c haps gaisler designs leon3 hardi haps3 1 bitfiles leon3mp bit iMPACT Select Output gt Cable Disconnect important Use GRMON to connect to the LEON3 processor 11 11 1 45 LEON3 template design for HAPS 51 motherboard Overvievv The LEON3 template design for the HAPS 51 motherboard from Synplicity assumes the presence of the SDRAM 1x1 DDR_1x1 and GEPHY 1xl daughter boards and the BIO1 VO board although not strictly necessary For more information about HAPS visit www synplicity com Figure 11 Synplicity s HAPS 51 motherboard The LEONG architecture
21. designs The full source code is available under the GNU GPL license allowing free and unlimited use for research and education LEON3 is also available under a low cost commercial license allowing it to be used in any commercial application to a fraction of the cost of comparable IP cores Synplicity Hardware Platforms Group www synplicity com is a leading provider of off the shelf ASIC prototyping boards The key product is HAPSTM High performance ASIC Prototyping Sys tem a modular system with multi FPGA motherboards and standard or custom made daughter boards which can be stacked together in a variety of ways Gaisler Research s GRLIB IP library environment includes support for HAPSTM development plat forms providing example designs and board support packages used with Synplicity s synthesis tools and Xilinx place z route tools Gaisler Research s HAPSTM development suite comprises everything needed in order to develop a LEONG based system on a chip design for a HAPSTM platform The suite includes GRLIB VHDL IP library containing LEON3 source code HAPS specific IP cores etc e Synplicity HAPS template designs HAPS 31 HAPS 51 HAPS 52 HAPS 54 etc Bare C Cross compiler system BCC GRMON debug monitor software IP cores for HAPS development suite The IP cores cover the following functions FLASH 1 1 32 16 bit PROM Controller for HAPSTM FLASH 1x1 SRAM IXI 32 bit SSRAM PROM Controller for HAPSTM
22. in the SSRAM and the code executes accesses to from the BIO1 board in order to read buttons and control the LEDs Figure 17 Synplicity s HAPS 51 motherboard and PC used for demonstration This application note is based on the GRLIB IP Core Library and the GRMON debug monitor soft ware from Gaisler Research Although these instructions are written for Windows based PC Laptop usage full Linux support is also provided for the library and the debug monitor software Hardware requirements The following hardware is required e PC Laptop running Windows 2000 XP not Vista e Xilinx Platform USB Cable version 9G or later HAPS 51 with a BIO1 board with optional GEPHY 1x1 SDRAM 1x1 DDR 1x1 or HAPS 52 with a BIO1 board and an SRAM _ 1x1 board with optional FLASH 1xl GEPHY 1x1 SDRAM 1x1 DDR 1x1 or HAPS 54 with a BIO1 board and an SRAM_1x1 board with optional FLASH 1xl GEPHY 1x1 SDRAM_1x1 DDR 1x1 58 14 3 14 4 14 5 Softvvare requirements The following software is required HAPS GPL distribution including bitfiles for template designs from http www gaisler com debug monitor software from http www gaisler com Used to control the LEON3 processor and more specifically load new programs SPARC ELF GCC if compilation is desired from http www gaisler com LibUsb Win32 from http libusb vvin32 sourceforge net A filter driver needed by GRMON to access the Xilinx USB cable
23. kHz Integer 1000000 pindex Selects which APB select signal PSEL will be used to to NAPBMAX 1 0 access the GPIO unit paddr The 12 bit MSB APB address 0 to 16 FFF 0 pmask The APB address mask 0 to 16 FFF 16 FFF 6 7 Signal descriptions Table 33 shovvs the interface signals of the core VHDL ports Table 33 Signal descriptions 25 Signal name Field Type Function Active RST N A Input Reset Low CLK N A Input Clock APBI Input APB slave input signals APBO Output APB slave output signals BI DATA Input Read data TXD Input UART transmit data from BIO1 board RTSN Input UART request to send from BIO1 board Low UO TXD Input UART transmit data form UART controller UO RTSN Input UART request to send from UART controller Low BO CLK Output Shift register clock WRITE Output Write latch enable 3 READ Output Read latch enable DATA Output Write data RXD Output UART receiver data to BIO1 board CTSN Output UART clear to send to BIO1 board Low ULRXD Output UART receiver data to UART controller ULCTSN Output UART clear to send to UART controller Low see GRLIB IP Library User s Manual 6 8 Library dependencies Table 34 shows libraries used when instantiating the core VHDL libraries Table 34 Library dependencies Library Package Imported unit s Description GRLIB AMBA Signals AMBA signal definitions GAISL
24. logic vector 59 downto 1 Signal hapstraki hapstrak in type Signal hapstrako hapstrak out type begin hapstrak gen if CFG HAPSTRAK 0 generate hapstrak i hapstrak generic map pindex 9 paddr gt 9 port map rst rstn Clk clkm apbi apbi apbo apbo 9 hapstraki hapstraki hapstrako hapstrako hapstrakal pads iopadvv generic map tech padtech width 30 port map hapstraka 30 downto 1 hapstrako dout 30 downto 1 hapstrako oen 30 downto 1 hapstraki din 30 downto 1 hapstraka31 pads iopadvv generic map tech padtech width 30 port map hapstraka 60 downto 31 hapstrako dout 62 downto 33 hapstrako oen 62 downto 33 hapstraki din 62 downto 33 hapstrakbl pads iopadvv generic map tech padtech width 30 port map hapstrakb 30 downto 1 hapstrako dout 94 downto 65 hapstrako oen 94 downto 65 hapstraki din 94 downto 65 hapstrakb31 pads iopadvv generic map tech padtech width 29 port map hapstrakb 59 downto 31 hapstrako dout 125 downto 97 hapstrako oen 125 downto 97 hapstraki din 125 downto 97 end generate 21 22 6 1 6 2 BIO1 Controller for HAPS Basic I O daughter board BTO1 Overvievv BIOI is a daughter board developed by Synplicity to be used with their HAPS motherboards BIO1 daughter board can be attached directly to a HAPS motherboard to be used as a simple interac tive I O interface Eigh
25. out std logic vector 14 downto 0 sdi inout std logic vector 63 downto 0 end architecture rtl of mctrl ex is AMBA bus AHB and APB signal apbi apb slv in type signal apbo apb slv out vector others gt apb none signal ahbsi ahb slv in type signal ahbso ahb slv out vector others ahbs none Signal ahbmi ahb mst in type Signal ahbmo ahb mst out vector others ahbm none signal sd0i sdli sdctrl in type signal sd0o sdlo sdctrl out type signal clkm rstn std ulogic signal cgi clkgen in type signal cgo clkgen out type Signal gnd std ulogic begin Clock and reset generators clkgen0 clkgen generic map clk mul gt 2 clk div gt 2 sdramen gt 1 tech virtex2 sdinvclk 0 port map clk gnd clkm open open sdclk open cgi cgo cgi pllctrl 00 cgi pllrst resetn cgi pllref pllref rst0 rstgen port map resetn clkm cgo clklock rstn SDRAM controller Sdc sdram 1x1 generic map hindex0 gt 0 haddr0 gt 161444004 hmask0 gt 164 F004 ioaddrO 1 hindex1 gt 1 haddr1 gt 164566004 hmask1 gt 164 F004 ioaddr1 gt 2 pwron 0 invclk 0 port map rstn clkm ahbsi ahbso 0 ahbsi ahbso 1 sd0i sd0o sdli sdlo input signals sd0i data 31 downto 0 lt sd0 31 downto 0 sdli data 31 downto 0 sd1 31 downto 0 connect SDRAM controller outputs to entity output signals
26. pipelined SRAM and the Flash PROM memory UMS AY A 3 Figure 2 HAPS 5 1 1 daughter board More information on HAPS can be found at www synplicity com Synplicity the Synplicity logo and Simply Better Results are registered trademarks of Synplicity Inc HAPS the HAPS logo High performance ASIC Prototyping System and HapsTrak HapsTrak I and HapsTrak II are trademarks of Synplicity Inc Vendor and device identifier The core has vendor identifier 0x01 Gaisler Research and device identifier 0x00A For description of vendor and device identifiers see GRLIB IP Library User s Manual Library dependencies Table 3 shows libraries used when instantiating the core VHDL libraries Table 3 Library dependencies Library Package Imported unit s Description GRLIB AMBA Signals AMBA signal definitions GAISLER MEMCTRL Signals Signal declarations GAISLER HAPS Component Component declaration 10 3 4 3 5 Component declaration The core has the follovving component declaration component sram 1x1 is generic hindex integer 0 pindex integer 0 romaddr integer 1640004 rommask integer 16 E00 ioaddr integer 16142008 iomask integer 16HE00 ramaddr integer 16144008 rammask integer 16 008 paddr integer 0 pmask integer 16 fff bus16 integer 0 tech integer 0 netlist integer 0 port rst in std ulogi
27. source operating system Eclipse C Developers Tool kit CDT and the GR Eclipse plug in GUI for various tools debug monitor software evaluation version available GrmonRCP GUI for GRMON evaluation version available TSIM LEONG LEON3 instruction simulator with GUI evaluation version available HASP HL drivers for GRMON and TSIM only needed for professional software versions The GRTools installer will set all necessary path variable and create short cuts on the Windows desk top The GRTools installer includes a graphical version of GRMON debug monitor software Based on the Eclipse rich client platform RCP GRMON RCP provides a graphical interface to all GRMON functions For more information see the GRTools Manual at ftp gaisler net tools gr cdt pdf Information furnished by Gaisler Research is believed to be accurate and reliable Hovvever no responsibility is assumed by Gaisler Research for its use nor for any infringements of patents or other rights of third parties vvhich may result from its use No license is granted by implication or otherwise under any patent or patent rights of Gaisler Research Gaisler Research AB tel 46 31 7758650 F rsta L nggatan 19 fax 46 31 421407 Sle 413 27 G teborg sales gaisler com Sweden www gaisler com GAISLER RESEARCH Copyright 2007 Gaisler Research AB All information is provided as is There is no warranty that it is correct or suitable for
28. the board 12 3 12 4 51 Cores The LEON3 HAPS 52 template design is based on cores from the GRLIB IP library The vendor and device identifiers for each core can be extracted from the plug amp play information as described in the GRLIB IP Core User s Manual The used IP cores are listed in table 47 Table 47 Used IP cores Core Function Vendor Device AHBCTRL AHB Arbiter amp Decoder 0x01 APBCTRL AHB APB Bridge 0x01 0x006 LEON3 LEON3 SPARC V8 32 bit processor 0x01 0x003 DSU3 LEON3 Debug support unit 0x01 0x004 AHBJTAG JTAG AHB debug interface 0x01 0x01C SRAM 1 1 32 bit SSRAM PROM Controller for HAPS SRAM 1x1 0x01 0x00A FLASH 1 1 32 16 bit PROM Controller for HAPS FLASH 1x1 0x01 0x00A AHBSTAT AHB failing address register 0x01 0x052 APBUART 8 bit UART with FIFO 0x01 0x00C GPTIMER Modular timer unit with watchdog 0x01 0x011 IRQMP LEON3 Interrupt controller 0x01 0x00D HAPSTRAK HapsTrak controller for HAPS boards 0x01 0x077 SDRAM 1 1 Dual 32 bit SDRAM Controller for HAPS SDRAM 1x1 0x01 0x009 DDR 1 1 64 bit DDR266 Controller for HAPS DDR 1x1 0x01 0x025 GEPHY 1X1 Dual Ethernet Controller for HAPS GEPHY 1x1 0x01 x01D BIO1 BIO1 Controller for HAPS BIO1 0x01 0x07A Interrupts All interrupts are handled by the interrupt controller and forwarded to the LEON3 processor See the GRLIB IP Core User s Manual for how and when the interrupts are raised Table 48 Inter
29. 00 0x80000000 DDR2 area not all used APBCTRL 0x80000000 0x81000000 APB bridge DSU3 0x90000000 0xA0000000 Registers DDR 1 1 0xA0000000 0xB0000000 DDR area SDRAM 1X1 0xB0000000 0xC0000000 SDRAM area SDRAM 1X1 0xC0000000 0xD0000000 DDR2SPA OxFFF00100 OxFFF00200 Registers for DDR2 controller DDR 1X1 OxFFF00200 OxFFF00300 Registers for DDR 1X1 controller SDRAM IXI OxFFF00300 OxFFF00400 Registers for SDRAM 1 1 controller SDRAM 1X1 OxFFF00400 OxFFF00500 AHB plug amp play OxFFFFF000 OXFFFFFFFF Registers The control registers of most on chip peripherals are accessible via the AHB APB bridge which is mapped at address 0x80000000 The memory map shown in table 46 is based on the AMBA AHB address space The detailed register layout is defined in the GRLIB IP Core User s Manual Table 46 APB address range Core Address range Comment SRAM 1X1 0x80000000 0x80000100 APBUART 0 0x80000100 0x80000200 Extra UART not on HAPS 51 motherboard IRQMP 0x80000200 0x80000300 GPTIMER 0x80000300 0x80000400 BIO1 0x80000500 0x80000600 Used with extra BIO1 I O board APBUART 1 0x80000600 0x80000700 Extra UART not on HAPS 51 motherboard GRGPIO 0 0x80000700 0x80000800 Extra 32 bit GPIO not on HAPS 51 motherboard GRGPIO 1 0x80000800 0x80000900 Extra 32 bit GPIO not on HAPS 51 motherboard HAPSTRAK 0x80000900 0x80000A00 GEPHY 1 1 0x80000A00 0x80000B00
30. 000200 0x80000300 GPTIMER 0x80000300 0x80000400 FLASH 1XI 0x80000400 0x80000500 Used with extra FLASH 1x1 daughter board BIO1 0x80000500 0x80000600 Used with extra BIO1 I O board HAPSTRAK 0x80000900 0x80000A00 GEPHY_1X1 0x80000A00 0x80000B00 Used with extra GEPHY 1x1 daughter board GEPHY_1X1 0x80000B00 0x80000C00 AHBSTAT 0x80000F00 0x80001000 APB plug amp play Ox800FF000 0x80100000 13 13 1 53 LEON3 template design for HAPS 54 motherboard Overvievv The LEON3 template design for the HAPS 54 motherboard from Synplicity assumes the presence of the SRAM_1x1 FLASH 1 1 SDRAM_ 1x1 DDR 1x1 and GEPHY 1 1 daughter boards and the BIO1 VO board Note that only one FPGA is used FPGA A For more information about HAPS visit www synplicity com Figure 15 Synplicity s HAPS 54 motherboard The LEONG architecture for the HAPS 54 motherboards includes the following modules LEON3 SPARC V8 Integer Unit optional MMU and FPU Debug Support Unit with AMBA trace buffer JTAG Debug Link Timer unit with 32 bit timers Interrupt controller for 15 interrupts in two priority levels UART with FIFO and baud rate generator accessed via the BIO1 board AMBA AHB status register Extra HapsTrak controller for HAPS boards HAPSTRAK core Extra Synchronous SRAM controller for SRAM 1x1 daughter board SRAM 1X1 core Extra PROM controller for FLASH 1x1 daughter board FLASH 1X1 core Extra SDRAM controller for
31. 1 Press enter to activate the HAPS 52 prompt Use the following command to set the FPGA A reset mask register HAPS 52 gt wsr 31 08 iMPACT Configure the board with the design c haps gaisler designs leon3 hardi haps52 bitfiles leon3mp bit iMPACT Select Output gt Cable Disconnect important Use GRMON to connect to the running LEON3 processor 14 6 3 Setting up the HAPS 54 motherboard This describes the setup for the HAPS 54 motherboard Configure voltage region Vla V1b V3a and V3b to 3 3V Configure voltage region V2b and V2a to 2 5V Configure the SETUP svvitch to 00000 00000 default Configure the frequency select switch 1 to 00011 00101 100 MHz Connect a MMCX coax cable between OSC la and GCLK IN 1 Connect the BIO1 to GPIO 1 10 Connect the SRAM 1x1 on connector A3 Voltage select int 2 3 PLL on S1 Connect the FLASH 1x1 on connector A1 Optional Jumper J2 and J4 Word mode 1 2 Connect the GEPHY 1x1 on connector AS Optional Jumper J4 int voltage source Jumper JS and J7 2 5V Jumper J6 and J8 125 MHz Connect the SDRAM 1x1 on connector A2 Optional Connect the DDR 1x1 on connector Optional Connect the Xilinx USB cable to JTAG IN iMPACT Configure the board with the design c haps gaisler designs leon3 hardi haps54 bitfiles leon3mp bit iMPACT Select Output gt Cable Disconnect important Use GRMON to connect to the LEON3 processor If FPGA A is the only configured device on the H
32. 1 integer 16 000 iomaskl integer 16 fff wprot integer 0 invclk integer 0 fast integer 0 pwron integer 0 Sdbits integer 32 oepol integer 0 pageburst integer 0 y port rst in std ulogic clk in std ulogic ahbsi0 in ahb slv in type ahbso0 out ahb slv out type ahbsil in ahb slv in type ahbsol out ahb slv out type sdoi in sdctrl in type sd0o out sdctrl out type sdli in sdctrl in type sdlo out sdctrl out type yj end component Instantiation This example shows how the core can be instantiated library ieee use ieee std logic 1164 11 library grlib use grlib amba all library techmap use techmap gencomp all library gaisler use gaisler memctrl all use gaisler misc all entity sdram ex is port Clk in std ulogic resetn in std ulogic pllref in std ulogic sdclk out std logic sdcke0 out std logic vector 1 dovnto 0 sdcsn0 out std logic vector 1 dovnto 0 sdven0 out std logic sdrasn0 out std logic sdcasn0 out std logic sddqm0 out std logic vector 7 downto 0 sdclk0 out std logic 0 out std logic vector 14 downto 0 sdo inout std_logic_vector 63 downto 0 sdckel out std_logic_vector 1 downto 0 sdcsnl out std logic vector 1 downto 0 sdvenl out std logic sdrasnl out std logic sdcasnl out std logic sddqm1 out std logic vector 7 downto 0 Sal
33. 45 J1_B46 J1_B47 abstract abstract abstract abstract abstract abstract abstract abstract abstract abstract abstract abstract abstract abstract abstract abstract abstract abstract abstract abstract abstract abstract abstract abstract abstract abstract abstract abstract abstract abstract abstract abstract abstract abstract abstract abstract abstract abstract abstract abstract abstract abstract abstract abstract abstract abstract abstract abstract abstract abstract abstract abstract abstract abstract abstract abstract abstract abstract 102 abstract 103 abstract 104 abstract 105 abstract 106 107 108 109 110 111 112 113 abstract abstract abstract abstract abstract abstract abstract 1 B48 1 B49 1 B50 1 B51 1 B52 1 B53 1 B54 1 B55 1 B56 1 B57 1 B58 1 B59 C4 C4 C4 C4 C4 C4 C4 ua C4 C4 48J1 B60 48J1 H1 Hol H2 Hol H3 48J1 H4 48J1 H5 48J1 H6 48J1 H7 48J1 H8 1 B48 1 B49 J1 B50 J1 B51 J1 B52 J1_B53 J1_B54 J1_B55 J1_B56 J1_B57 J1_B58 J1_B59 J1_B60 J1 J1 Ul J1 J1 J1 J1 J1 0 AU 5 N HF 114 115 116 117 118 119 120 121 122 123 124 125 abstract abstract abstract abstract abstract abstract abstract abstract abstract abstract abstract abstract abstract 126
34. 52sec a e el tek des bo st obec ee on E de e o O 23 10 11 12 13 6 5 Vendor and deviceadentifiers uiuere eti dette el eoi oder eoe ehe Ho 24 6 6 Configuration options eren enne nennen nenne RR enn Inn Ran NOR RR an nan nr an nan nenne ene nennen nennen 24 6 7 Signal descriptions NN 25 6 8 Library dependencies os eee s Eee et oid sil 25 6 9 Component declaration reise oe eie ete OH RO e ERG ERG WEE RE TERR Y 25 6 10 Instant ouem aue eo enis s ets ctis 26 SDRAM 1 1 Dual 32 bit PC1133 SDRAM Controller for HAPS SDRAM 1 1 27 7 1 OVETVIEW cioe et eene rona nti P teni Rn Rb 27 7 2 Vendor and device identifiers ooi toto per p t t re utei nee D e ERR rires 27 7 3 Library dependenci es re S TR e We b TS MR eT iia 27 7 4 Component declaration 335 5 ARR BIRR PR ite itid e lur ei G ns 27 7 5 TInstantiationl e temet 28 DDR 1XI DDR266 Controller for HAPS DDR J1xl eee 30 8 1 OVEIVI Wasi 30 8 2 Vendor and device identifier eerte e ne i e y u 30 8 3 Library dependencies HER pe TR EE TE A RR 30 8 4 Component declara 31 8 5 Instantiationz RN 31 GEPHY 1 1 Ethernet Media Access Controller for HAPS GEPHY 1 1 33 9 1 OVEN EW totus Sm Ic a oa La RA TRI EAT 33 9 2 Vendor and device dentifier i uo A e Rn 33 9 3 Configuration Options cete tiae tette eben tns 34 9 4 Library dependencies as
35. APS 54 motherboard the reset mask for FPGA A needs to be modified Otherwise the design will be held in reset until all the other FPGAs are config ured If this is the case do like this Connect to the RS232 port on the HAPS 54 board using a terminal emulator HyperTerminal set to 38400 8 N 1 Press enter to activate the HAPS 54 prompt 14 7 14 8 61 Use the following command to set the FPGA A reset mask register HAPS 54 gt wsr 31 08 iMPACT Configure the board with the design c haps gaisler designs leon3 hardi haps54 bitfiles leon3mp bit iMPACT Select Output gt Cable Disconnect important Use GRMON to connect to the running LEON3 processor Software setup This describes the software setup for the HAPS 51 motherboard The procedure is the same for the HAPS 52 and HAPS 54 boards only the design folder name is different Start a command prompt in Windows Navigate to the design folder c haps gaisler designs leon3 hardi haps5 1 gt gt cd c haps gaisler designs leon3 hardi haps5 1 Use GRMON to connect to the LEON3 gt gt grmon eval exe xilusb u Unless you selected Cable Disconnect from iMPACT the GRMON debug monitor software will not be able to connect properly Load the software test executable to the SSRAM memory gt gt load test Start the program gt gt run This should start the test program which writes out text and blinks the LEDs By pressing the buttons S1 to S6
36. B error response Table 41 AMBA AHB address range Core Address range Area FLASH 1XI 0x00000000 0x10000000 Flash PROM area not all used SRAM 1 1 0x40000000 0x80000000 SSRAM area not all used APBCTRL 0x80000000 0x81000000 APB bridge DSU3 0x90000000 0xA0000000 Registers DDR 1 1 0xA0000000 0xB0000000 DDR area SDRAM 1 1 0xB0000000 0xC0000000 SDRAM area SDRAM 1 1 0xC0000000 0xD0000000 DDR 1X1 OxFFF00200 OxFFF00300 Registers for DDR 1X1 controller SDRAM 1 1 OxFFF00300 OxFFF00400 Registers for SDRAM 1 1 controller SDRAM 1X1 OxFFF00400 OxFFF00500 AHB plug amp play OxFFFFF000 OXFFFFFFFF Registers The control registers of most on chip peripherals are accessible via the AHB APB bridge which is mapped at address 0x80000000 The memory map shown in table 42 is based on the AMBA AHB address space The detailed register layout is defined in the GRLIB IP Core User s Manual Table 42 APB address range Core Address range Comment SRAM 1X1 0x80000000 0x80000100 Used with extra SRAM 1x1 daughter board APBUART 0x80000100 0x80000200 IRQMP 0x80000200 0x80000300 GPTIMER 0x80000300 0x80000400 FLASH 1XI 0x80000400 0x80000500 Used with extra FLASH 1x1 daughter board BIO1 0x80000500 0x80000600 Used with extra BIO1 I O board HAPSTRAK 0x80000900 0x80000A00 GEPHY 1 1 0x80000A00 0x80000B00 Used with extra GEPHY 1x1
37. BIB BIB B B BIB BBB B B B B 30 29 28 27 26 25 24 23 22 21 20 19 18117 16115 14113 1211100909 8 7 6 5 4 3 2 1 31 HapsTrak 95 input unused 30 1 HapsTrak 94 65 input a k a hapstrakb 30 1 0 HapsTrak 64 input unused Table 15 Input register 3 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 1211 10 9 8 7 6 5 4 3 2 1 0 127 126 125 HapsTrak 97 96 BIBI BIB B B B JB BBB BIB B B BIB B BI BIBIB B 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37136 35 34 33 32 31 31 HapsTrak 127 input unused 30 HapsTrak 126 input unused 29 1 HapsTrak 125 97 input a k a hapstrakb 60 31 0 HapsTrak 96 input unused 18 Table 16 Output register 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 1211 10 9 8 7 6 5 4 3 2 1 31 30 HapsTrak 1 fA AAAAAANVMN AAAAAAAAAAAAAQ ANQ QAAA QAAA ANQA 30 29 28 27 26 25 24 23 22 21 20 19 18117 16115 14 13 1211100909 8 7 6 5 4 3 2 1 31 Hap
38. ER HAPS Signals component Component declaration 6 9 Component declaration The core has the following component declaration component biol generic sysclk integer 100000 pindex integer 0 paddr integer 0 pmask integer 16 fff port rst in std logic clk in std logic apbi in apb slv in type apbo out apb slv out type bi in bio in type bo out bio out type end component 26 6 10 Instantiation This example shows how the core can be instantiated library grlib use grlib amba all library gaisler use gaisler haps all Signal bi bio in type Signal bo bio out type begin biol gen if BIO1 generate biol inst biol generic map sysclk gt 50000 pindex 5 paddr gt 5 port map rst rstn Clk clkm apbi apbi apbo apbo 5 bi bi bo gt bo end generate 7 1 7 2 7 3 7 4 27 SDRAM 1 1 Dual 32 bit PCI133 SDRAM Controller for HAPS SDRAM 1x1 Overvievv The memory controller for the Synplicity HAPS SDRAM_ 1x1 daughter boards is two 32 bit SDRAM controllers that interfaces external SDRAM to the AMBA AHB bus The memory controller acts as two slave on the AHB bus and has a configuration register accessible through the AHB I O address space The tvvo memory controllers can be configured separately and can be connected to the same AMBA AHB bus or to tvvo different AMBA AHB buses The memory contro
39. SDRAM 1x1 daughter board SDRAM 1X1 core Extra DDR controller for DDR 1x1 daughter board DDR 1X1 core Extra Ethernet controller for GEPHY 1x1 daughter board GEPHY 1X1 core For more information about the GRLIB IP Library visit www gaisler com 54 13 2 3 Port 3 Port Register File File IEEE ma LEON3 FT SPARC m Eye Debug FLASH 1x1 DDR 1x1 HapsTrak Mul Div 32 bit Integer Unit Buffer Unit Interface Controller Controller Controller D Cache Cache E SRAM xi SDRAM 1x1 GEPHY_1x1 ITLB SRMMU DTLB Controller Controller Controller 32 bit AMBA AHB 32 bit AMBA APB APBCTRL LEONSMP CLKGEN RSTGEN AHB STA TIMERS Figure 16 LEON3 template design for HAPS 54 motherboard Configuration The HAPS 54 LEONG template design can be configured by means of commands described in the GRLIB IP Library User s Manual The Xilinx ucf pin placement file for the motherboard can be generated from the leon3mp pas and leon3mp con files using the HapsMap software from Synplicity After editing the leon3mp pas or leon3mp con file run the following command to generate a new ucf file make hapsmap Ensure that the hapsmap executable is the search path For details please refer to the HAPS manuals from Synplicity The 70 MHz template design assumes an external clock frequency of 100 MHz See HAPS 54 moth erboard documentation for appropriate settings of the external clock generator circuitry The
40. SRAM 1x1 TEST 1X2 Controller for HAPSTM test daughter board TEST 1x2 HAPSTRAK HapsTrak controller for HAPSTM boards e BIOI Controller for HAPS test daughter board BIO1 e SDRAM 1 1 32 bit SDRAM Controller for HAPSTM SDRAM 1x1 DDR 1 1 DDR266 Controller for HAPS DDR_ 1x1 GEPHY 1 1 Ethernet Controller for HAPSTM GEPHY_ 1x1 Implementation characteristics The cores are portable and can be implemented on most FPGA and ASIC technologies and have been tested for Xilinx Virtex 4 and Virtex 5 FPGA technologies The cores are available in VHDL source code and when applicable use the plug amp play configuration method described in the GRLIB IP LIbrary User s Manual 1 4 1 5 1 6 Licensing The tables below lists the provided IP cores and their AMBA plug amp play device ID The license col umn indicates if a core is available under GNU GPL and or under a commercial license COM The open source version of GRLIB includes only cores marked with GPL or LGPL Table 1 HAPS functions Name Function Vendor Device License FLASH 1X1 32 16 bit PROM Controller for HAPS FLASH 1x1 0x01 0 COM SRAM 1 1 32 bit SSRAM PROM Controller for HAPS SRAM 1x1 0x01 0x00A COM TEST 1X2 Controller for HAPS test daughter board TEST 1x2 0x01 0x078 GPL HAPSTRAK HapsTrak controller for HAPS boards 0x01 0x077 GPL BIO1 Controller for HAPS I O board BIO1 0x01 0x07A GPL SDRAM 1 1 32 bit SDRAM Con
41. Used with extra GEPHY 1x1 daughter board GEPHY 1X1 0x80000B00 0x80000C00 I2CMST 0x80000C00 0x80000D00 Connected to DDR2 memory AHBSTAT 0x80000F00 0x80001000 APB plug amp play 0x800FF000 0x80100000 Registers 12 12 1 49 LEON3 template design for HAPS 52 motherboard Overvievv The LEON3 template design for the HAPS 52 motherboard from Synplicity assumes the presence of the SRAM 1 1 FLASH 1 1 SDRAM 1 1 DDR 1x1 and GEPHY 1 1 daughter boards and the BIO1 VO board Note that only one FPGA is used FPGA A For more information about HAPS visit www synplicity com Figure 13 Synplicity s HAPS 52 motherboard The LEONG architecture for the HAPS 52 motherboards includes the following modules LEON3 SPARC V8 Integer Unit optional MMU and FPU Debug Support Unit with AMBA trace buffer JTAG Debug Link Timer unit with 32 bit timers Interrupt controller for 15 interrupts in two priority levels UART with FIFO and baud rate generator accessed via the BIO1 board AMBA AHB status register Extra HapsTrak controller for HAPS boards HAPSTRAK core Extra Synchronous SRAM controller for SRAM 1x1 daughter board SRAM 1X1 core Extra PROM controller for FLASH 1x1 daughter board FLASH 1X1 core Extra SDRAM controller for SDRAM 1x1 daughter board SDRAM 1X1 core Extra DDR controller for DDR 1x1 daughter board DDR 1X1 core Extra Ethernet controller for GEPHY 1x1 daughter board GEPHY 1X1 core For mor
42. als TEST 1x2 Connector J2B test 1x20 1cd seg 0 31 ctr1 1cd 0 31 test 1x20 1cd clk 0 1 ctrl bp 1 2 test 1x2o green led n 0 11 ctrl green n 1 12 L 1 618SL 1 6 J2B 42 47 amp J2B 36 41 test 1x2o red led n 0 11 ctrl red n 1 12 L 1 6 amp SL 1 6 J2B 54 59 amp J2B 48 53 test 1x2i button n 0 11 ctrl button n 1 12 S 1 6 amp SL 1 6 J2B 24 29 amp J2B 30 35 Registers The core is programmed through registers mapped into APB address space Table 4 TEST 1X2 registers APB address offset Register 0x00 Buttons register 0x04 LCD register 0x08 LED register Table 5 Buttons register 31 12 11 109 8 7 6 5 4 3 2 1 000 0 SL SL SL SL SL SL S6 S5 S4 S3 S2 S1 6 514 312 1 11 6 Buttons SL6 to SL1 2 0 Buttons S6 to S1 Table 6 LCD register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 4A 4B 4C 4D 4E 4F 4G 3A 3B 3C 3D 3E 3F 3G 2A 2B 2C 2D 2E 2F 2G 1A 1B 1C 1D 1E 1F 1G 4 3 2 L DP DP DP 4A 3A 1A IF mi ar mu 3F lso os IL EN Bic 4C 3E 3C 4E 4D 4DP 3D 3DP 31 25 Character 4 24 18 Character 3 17 11 Character 2 10 4 Character 1 4DP fourth decimal point 3DP third decimal point 2DP second decimal point or NW L
43. ange Core Address range Comment SRAM 1X1 0x80000000 0x80000100 Used with extra SRAM 1x1 daughter board APBUART 0x80000100 0x80000200 IRQMP 0x80000200 0x80000300 GPTIMER 0x80000300 0x80000400 FLASH 1XI 0x80000400 0x80000500 Used with extra FLASH 1x1 daughter board BIO1 0x80000500 0x80000600 Used with extra BIO1 I O board HAPSTRAK 0x80000900 0x80000A00 GEPHY_1X1 0x80000A00 0x80000B00 Used with extra GEPHY 1x1 daughter board GEPHY_1X1 0x80000B00 0x80000C00 AHBSTAT 0x80000F00 0x80001000 APB plug amp play Ox800FF000 0x80100000 14 14 1 14 2 57 Application note for HAPS 50 motherboard demonstration Overview This is an instructions for how to run a simple demo on the HAPS 51 HAPS 52 and HAPS 54 boards The design running on the HAPS motherboards includes a LEON3 SPARC V8 processor In reference to the board descriptions in the previous sections the LEON3 processor is connected to a 32 bit AMBA AHB bus Among other things this AHB bus is connected to a SSRAM controller which handles the on board SSRAM and Flash PROM on the HAPS 51 motherboard and SRAM_1x1 and FLASH_1x1 daughter boards on the HAPS 52 and HAPS 54 motherboards Via an AHB to APB bus bridge the LEON3 processor can access controllers implemented to interface to the BIOI board and to a general HapsTrak connector In the running of a simple demo application the LEON3 processor software is placed
44. b out std ulogic ddr write enable ddr rasb out std ulogic ddr ras ddr casb out std ulogic ddr cas ddr dm out std logic vector 7 downto 0 ddr dm ddr dqs inout std logic vector 7 downto 0 ddr dqs ddr ad out std logic vector 13 downto 0 ddr address ddr ba out std logic vector 1 downto 0 ddr bank address ddr dq inout std logic vector 63 downto 0 ddr data end architecture rtl of mctrl ex is AMBA bus Signal ahbsi ahb slv in type signal ahbso ahb slv out vector others gt ahbs none Signal clkml lock std ulogic begin DDR controller ddrc ddr 1x1 generic map fabtech virtex4 ddrbits 64 memtech memtech hindex gt 4 haddr gt 161414004 hmask gt 164 F004 ioaddr gt 1 pwron 1 MHz 100 col 9 Mbyte 32 ahbfreq 50 ddrbits 64 port map rstneg rstn lclk clkm lock clkml clkml ahbsi ahbso 4 ddr clk ddr clkb ddr clk fb out ddr clk fb ddr cke ddr csb ddr web ddr rasb ddr casb ddr dm ddr dqs ddr adl ddr ba ddr dq 9 1 9 2 33 GEPHY 1X1 Ethernet Media Access Controller for HAPS GEPHY 1x1 Overview The Ethernet Media Access Controller for the Synplicity HAPS GEPHY 1x1 daughter boards pro vides an interface between an AMBA AHB bus and an Ethernet network The controller provides two Ethernet cores and supports 10 100 1000 Mbit speed in both full and half duplex The AMBA int
45. ble Disconnect important Use GRMON to connect to the LEON3 processor 14 6 2 Setting up the HAPS 52 motherboard This describes the setup for the HAPS 52 motherboard Configure voltage region Vla V1b V3a and V3b to 3 3V Configure voltage region V2b and V2a to 2 5V Configure the SETUP switch to 00000_00000 default Configure the frequency select switch 1 to 00011 00101 100 MHz Connect a MMCX coax cable between OSC la and GCLK IN 1 Connect the BIO1 to GPIO 1 10 Connect the SRAM 1x1 on connector Voltage select int 2 3 PLL on S1 Connect the FLASH 1x1 on connector A1 Optional Jumper J2 and J4 Word mode 1 2 Connect the GEPHY 1x1 on connector AS Optional Jumper J4 int voltage source Jumper JS and J7 2 5V Jumper J6 and J8 125 MHz Connect the SDRAM 1 1 on connector A2 Optional Connect the DDR 1x1 on connector A6 Optional Connect the Xilinx USB cable to JTAG IN iMPACT Configure the board with the design c haps gaisler designs leon3 hardi haps52 bitfiles leon3mp bit iMPACT Select Output gt Cable Disconnect important Use GRMON to connect to the LEON3 processor 60 If FPGA A is the only configured device on the HAPS 52 board the reset mask for FPGA A needs to be modified Othervvise the design will be held in reset until FPGA B is configured as well If this is the case do like this Connect to the RS232 port on the HAPS 52 board using a terminal emulator HyperTerminal set to 38400 8 N
46. c clk in std ulogic ahbsi in ahb slv in type ahbso out ahb slv out type apbi in apb slv in type apbo out apb slv out type sri in memory in type sro out memory out type end component Instantiation This example shows how the core can be instantiated library grlib use grlib amba all library gaisler use gaisler haps all use gaisler memctrl all Signal memi Signal memo memory in type memory out type begin ssr0 if CFG SRAM 1x1 1 generate sram 1x1 0 sram 1x1 generic map hindex gt 5 pindex gt 4 rommask gt 0 no PROM memory iomask gt 0 no memory mapped IO ramaddr gt 16440048 bus16 CFG SRAM 1x1 PROM16 netlist CFG SRAM 1x1 NETLIST tech virtex5 port map rstn clkm end generate ahbsi ahbso 5 apbi apbo 4 memi memo 4 1 4 2 11 TEST_1X2 Controller for HAPS test daughter board TEST_1x2 Overview TEST_1x2 is a daughter board developed by Synplicity to be used with their HAPS motherboards TEST 1x2 daughter board can be attached directly to a HAPS motherboard to be used as a simple interactive I O interface A number of LEDs push buttons and an LCD are available for this purpose These inputs and outputs are monitored and controlled via one of the two HapsTrak connectors on the board The TEST_1X2 controller supports the following functions e 12 push buttons e 12 two color LEDs LCD with four 7 segment characters LCD cloc
47. different text is written on the LCD To stop the program gt gt Ctrl c Notice that this will not stop the actual design but only stop the execution of the software by the LEON3 processor Compilation optional This describes the software compilation procedure for the HAPS 51 motherboard The procedure is the same for the HAPS 52 and HAPS 54 boards only the design folder name is different Start a command prompt in Windows Navigate to the design folder c haps gaisler designs leon3 hardi haps51 gt gt cd c haps gaisler designs leon3 hardi haps51 62 14 9 Make the required modification to the test c C source file using any available editor e Recompile the code gt gt sparc elf gcc g O2 msoft float test c o test This will recompile the code and create an updated test executable file Use the instructions from the above software setup to download and run the new test Alternative software optional As an alternative to separate GRMON and SPARC ELF GCC downloads the complete GRTools suite can be downloaded from http www gaisler com Downloads gt GRTools installer for windows gt GRTools installer Downloads gt GRTools installer for windows gt GRTools Manual GRTools is a single file installer for Windows It will install the following tools in a uniform way BCC cross compiler SPARC ELF GCC compiler system e cross compiler including RTEMS 4 6 and 4 8 open
48. e information about the GRLIB IP Library visit www gaisler com 50 12 2 3 Port 3 Port Register File File IEEE DN LEON3 FT SPARC H B FLASH 1 1 DDR 1x1 HapsTrak Mujpiy 22 bit Integer Unit Butter Uni Interface Controller Controller GEPHY 1x1 l Cache D D Cache AMBA SRAM 1x1 ITLB SRMMU DTLB Controller Controller Controller 32 bit AMBA AHB 32 bit AMBA APB APBCTRL HEONSMP CLKGEN RSTGEN AHB STA TIMERS Figure 14 LEON3 template design for HAPS 52 motherboard Configuration The HAPS 52 LEONG template design can be configured by means of commands described in the GRLIB IP Library User s Manual The Xilinx ucf pin placement file for the motherboard can be generated from the leon3mp pas and leon3mp con files using the HapsMap software from Synplicity After editing the leon3mp pas or leon3mp con file run the following command to generate a new ucf file make hapsmap Ensure that the hapsmap executable is the search path For details please refer to the HAPS manuals from Synplicity The 70 MHz template design assumes an external clock frequency of 100 MHz See HAPS 52 moth erboard documentation for appropriate settings of the external clock generator circuitry The on board 16 MHz oscillator should be used with the settings N 1 and M 25 Please refer to the leon3mp con and leon3mp pas files in the template design directory for the detail configuration of
49. e rate time between two update accesses to the BIO1 board is set to Bit rate Update rate value 1 The default bit rate and update frequency are set to 10 Mbit respective 1 kHz This is calculated from the sysclk VHDL generic 23 The RS232 UART interface on the BIO1 board is not controlled by this controller The UART inter face is forwarded to be connected to an UART controller GRLIB s APBUART Core usage Note that the mapping between the VHDL ports and the BIO1 daughter board depends on which GPIO connectors on the motherboard it is connected to HapsMap is a pin assignment software from Synplicity that generates Xilinx UCF files describing the mapping from RTL port names VHDL or Verilog to pins for all FPGAs in a HAPS system For details refer to the HAPS manuals from Syn plicity Registers The core is programmed through registers mapped into APB address space Table 27 BIO1 registers APB address offset Register 0x00 Buttons register 0x04 LED digits register 0x08 LED register 0 Control register Table 28 Buttons register 31 30 28 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 1211 10 9 8 7 6 5 4 3 2 1 0 58 S7 S6 S5 S4 S3 S2 S1 S8 S7 S6 S5 S4 S3 S2 S1 S8 S7 S6 S5 S4 S3 S2 S1 S8 S7 S6 S5 S4 S3 S2 S1 31 24 Buttons S8 to
50. ed these are possible to use with HapsMap once files describing the mapping of pins to signals on the specific boards map files have been added to the library More information on HAPS HapsTrak and HapsMap can be found at www synplicity com A HapsMap mapping file has been crated for the HapsTrak controller and is defined hereunder If not already existing in the cardlib directory of the HapsMap installation the text hereunder should be copied and pasted into a file named hapstrak map that should be placed in the aforementioned direc tory i e cardlib hapstrak map The HapsMap software can then be used to map the HapsTrak con troller to any HapsTrak I II connector on any HAPS motherboard Connection vs signal name for HapsTrak II connector Nov 5 2007 Sandi Habinc lt sandi gaisler com gt Revisions 2007 11 05 Sandi Habinc New file Please contact Synplicity if you have any questions top bottom Signal name UL Al J1 Al abstract 1 J1_A2 Ul A2 abstract 2 1 Ul A3 abstract 3 Ul A4 Ul A4 abstract 4 J1_A5 J1_A5 abstract 5 Jl A6 Ul A6 abstract 6 Jl A7 Jl A7 abstract 7 Ul A8 Ul A8 abstract 8 Ul A9 Ul A9 abstract 9 UL A10 UL A10 abstract 10 UL A11 UL A11 abstract 11 Ul A12 UL A12 abstract 12 Ul A13 Jl A13 abstract 13 Ul A14 Jl A14 abstract 14 Ul A15 Jl A15 abstract 15 Ul A16 Ul A16 abstract 16 Ul A17 Jl A17 abstract 17 Ul A18 Ul A18 abstract 18 Ul A19 Jl A19 abstrac
51. er face of each Ethernet core consists of an APB interface for configuration and control and an AHB master interface which handles the dataflow The dataflow is handled through DMA channels The Ethernet Media Access Controller is based on the Gaisler Research GRETH Ethernet Media Access Controller and GRETH GBIT Gigabit Ethernet Media Access Controller See corresponding manual for details The GRETH IP core is provided in VHDL source code as part of the GRLIB GPL distribution The GRETH GBIT IP core is only available in the GRLIB COM distribution Figure 8 HAPS GRPHY 1x1 daughter board More information on HAPS can be found at www synplicity com Synplicity the Synplicity logo and Simply Better Results are registered trademarks of Synplicity Inc HAPS the HAPS logo High performance ASIC Prototyping System and HapsTrak HapsTrak I and HapsTrak II are trademarks of Synplicity Inc Vendor and device identifier The core has vendor identifier 0x01 Gaisler Research and device identifier 0x01D For description of vendor and device identifiers see GRLIB IP Library User s Manual 34 9 3 9 4 9 5 Configuration options Table 37 shovvs additional configuration options of the core VHDL generics not described in the GRETH GRETH GBIT core manual Table 37 Configuration options Generic Function Allowed range Default grethen0 Enables Ethernet interface 0 0 1 1 giga0 Enables the Gigab
52. for the HAPS 51 motherboards includes the following modules LEON3 SPARC V8 Integer Unit optional FPU and MMU Debug Support Unit with AMBA trace buffer JTAG Debug Link 16 32 and 64 bit DDR2 Controller Synchronous SRAM PROM controller SRAM_1X1 core Timer unit with 32 bit timers Interrupt controller for 15 interrupts in two priority levels UART with FIFO and baud rate generator accessed via the BIO1 board AMBA AHB status register Extra HapsTrak controller for HAPS boards HAPSTRAK core Extra SDRAM controller for SDRAM 1x1 daughter board SDRAM 1X1 core Extra DDR controller for DDR_1x1 daughter board DDR_ 1X1 core Extra Ethernet controller for GEPHY 1x1 daughter board GEPHY 1X1 core One extra UARTs with FIFO and baud rate generator Two extra 32 bit general purpose I O port GPIO For more information about the GRLIB IP Library visit www gaisler com 46 11 2 3 Port 3 Port Register File File IEEE LEON3 FT SPARC sVruction ed DDR2 DDR ixi HapsTrak Mul Div 32 bit Integer Unit Buffer Unit Interface Controller Controller Controller l Cache D D Cache SRAM ixi SDRAM txt GEPHY 1x1 ITLB SRMMU DTLB Buffer Controller Controller Controller 32 bit AMBA AHB a LEON3MP CLKGEN RSTGEN AHB STA e 4 ART Figure 12 LEON3 template design for HAPS 51 motherboard Configuration The HAPS 51 LEON3 template design can be configured by means of commands described in
53. her and daughter boards The HapsTrak I connector or simply HapsTrak supports 120 pins with 119 user VO signals The HapsTrak II connector supports 128 pins with 119 user I O signals The HapsTrak II connector is backwards compatible with HapsTrak I HapsTrak I daughter boards will not loose any functionality when mounted on a HapsTrak II connector but they will not be able to benefit from the features of HapsTrak II The HapsTrak controller supports the following functions 0119 inputs read via registers 119 outputs written via registers with individually enabled output drivers via registers GND 3 3V H1 H2 3 3V B1 4 A1 B30 lt A30 Reserved H3 L p4 Reserved for for future use HS FP H future use B31 A31 VCCO B60 A60 VCCO H7 H8 VCCO GND Figure 4 HapsTrak II connector pinout More information on HAPS and HapsTrak can be found at www synplicity com Synplicity the Synplicity logo and Simply Better Results are registered trademarks of Synplicity Inc HAPS the HAPS logo High performance ASIC Prototyping System and HapsTrak HapsTrak I and HapsTrak II are trademarks of Synplicity Inc Operation Each signal on the HapsTrak connector can be read from or written to via registers The output enable of each signal is individually programmable 16 5 3 5 4 Core usage Note that the mapping between the VHDL ports of the HapsTrak contr
54. it MAC for Ethernet interface 0 0 1 0 grethenl Enables Ethernet interface 1 0 1 1 gigal Enables the Gigabit MAC for Ethernet interface 1 0 1 0 Library dependencies Table 38 shows libraries used when instantiating the core VHDL libraries Table 38 Library dependencies Library Package Imported unit s Description GRLIB AMBA Signals AMBA signal definitions GAISLER NET Signals components Signal declarations GAISLER HAPS Component Component declaration Component declaration The core has the following component declaration component gephy 1x1 is generic grethen0 integer hindex0 integer pindex0 integer paddr0 integer pmask0 integer pirq0 integer fifosize0 integer 10 integer edclbufsz0 integer burstlengthO integer macaddrh0 integer macaddr10 integer ipaddrh0 integer ipaddr10 integer phyrstadr0 integer giga0 integer grethenl integer hindexl integer pindexi integer paddr1 integer pmask1 integer pirq integer fifosizel integer edcl1 integer edclbufsz integer burstlength1 integer macaddrh1 integer macaddr11 integer ipaddrh1 integer ipaddr11 integer phyrstadr integer gigal integer sim integer l 16 FFFH smi range 4 to 64 range 0 to range 1 to 64 range 4 to 128 16 00005E 16 000000 16 c0a8 16 0035 range 0 to 32 range to 1 sms Sz 2 0 16 FFFH range range 4 to 64
55. k generation Figure 3 HAPS TEST_1x2 daughter board More information on HAPS can be found at www synplicity com Synplicity the Synplicity logo and Simply Better Results are registered trademarks of Synplicity Inc HAPS the HAPS logo High performance ASIC Prototyping System and HapsTrak HapsTrak 1 and HapsTrak II are trademarks of Synplicity Inc Operation The status of each button can be read out via a register The value of each LED can be controlled via a register The value of each LCD segment can be controlled via a register The register output is modulated with the LCD clock frequency The two LCD clocks are generated by the controller The LCD clock oscillator frequency is generated from the system clock and is configurable through the fdiv VHDL generic that defines the clock divi sion factor 12 4 3 4 4 Core usage Note that the mapping between the VHDL ports and the TEST 1x2 daughter board depends on which connectors on the motherboard it is connected to HapsMap is a pin assignment softvvare from Syn plicity that generates Xilinx UCF files describing the mapping from RTL port names VHDL or Ver ilog to pins for all FPGAs in a HAPS system For details refer to the HAPS manuals from Synplicity The register mapping hereafter assumes the following mapping between the VHDL ports and the names used by HapsMap TEST 1x2 daughter board signal names and connector VHDL signals HapsMap sign
56. l integer 0 ddrbits integer 16 ahbfreq integer 50 port rst ddr in std ulogic rst ahb in std ulogic Clk ddr in std ulogic clk ahb in std ulogic lock out std ulogic DCM locked clkddro out std ulogic DCM locked clkddri in std ulogic ahbsi in ahb slv in type ahbso out ahb slv out type ddr clk out std logic vector 2 downto 0 ddr clkb out std logic vector 2 downto 0 ddr clk fb out out std logic ddr clk fb in std logic ddr cke out std logic vector 1 downto 0 ddr csb out std logic vector 1 downto 0 ddr web out std ulogic ddr rasb out std ulogic ddr casb out std ulogic ddr dm out std logic vector ddrbits 8 1 downto 0 ddr dqs inout std logic vector ddrbits 8 1 downto 0 ddr ad out std logic vector 13 downto 0 ddr ba out std logic vector 1 downto 0 ddr dq inout std logic vector ddrbits 1 downto end component Instantiation This example shows how the core can be instantiated library ieee use ieee std logic 1164 all library grlib use grlib amba all use grlib tech all library gaisler use gaisler memctrl all entity ddr Interface is port ddr clk out std logic vector 2 downto 0 ddr clkb out std logic vector 2 downto 0 ddr clk fb in std logic ddr clk fb out out std logic 31 32 ddr cke out std logic vector 1 downto 0 ddr csb out std logic vector 1 downto 0 ddr we
57. le logic designs The Confirma at speed verification platform comprising software tools and the HAPS family of prototyping systems enables both comprehensive verification of ASIC ASSP and SoC designs and software development prior to chip tapeout For more information about HAPS visit http www synplicity com Synplicity the Synplicity logo and Simply Better Results are registered trademarks of Synplicity Inc HAPS the HAPS logo High performance ASIC Prototyping System and HapsTrak HapsTrak I and HapsTrak II are trademarks of Synplicity Inc 2 1 2 2 2 3 FLASH 1X1 32 16 bit PROM Controller for HAPS FLASH 1 1 Overvievv The memory controller for the Synplicity HAPS FLASH 1x1 daughter boards is a 32 16 bit con troller that interfaces external PROM or Flash PROM to the AMBA AHB bus The memory controller acts as a slave on the AHB bus and has a configuration register accessible through an APB slave inter face The memory controller is based on the Gaisler Research SSRCTRL 32 bit SSRAM PROM Control ler See corresponding manual for details The SSCTRL IP core is provided in VHDL netlist format for the Xilinx Virtex 4 and Virtex 5 technologies as part of the GRLIB GPL distribution Figure 1 HAPS FLASH 1x1 daughter board More information on HAPS can be found at www synplicity com Synplicity the Synplicity logo and Simply Better Results are registered trademarks of Synplicity Inc
58. ller is based on the Gaisler Research SDCTRL 32 64 bit PC133 SDRAM Con troller See corresponding manual for details The SDCTRL IP core is provided in VHDL source code as part of the GRLIB GPL distribution Figure 6 HAPS SDRAM 1 1 daughter board More information on HAPS can be found at www synplicity com Synplicity the Synplicity logo and Simply Better Results are registered trademarks of Synplicity Inc HAPS the HAPS logo High performance ASIC Prototyping System and HapsTrak HapsTrak I and HapsTrak II are trademarks of Synplicity Inc Vendor and device identifier The core has vendor identifier 0x01 Gaisler Research and device identifier 0x009 For description of vendor and device identifiers see GRLIB IP Library User s Manual Library dependencies Table 35 shows libraries used when instantiating the core VHDL libraries Table 35 Library dependencies Library Package Imported unit s Description GRLIB AMBA Signals AMBA signal definitions GAISLER MEMCTRL Signals Signal declarations GAISLER HAPS Component Component declaration Component declaration The core has the following component declaration 28 7 5 component sdram 1x1 is generic hindex0 integer 0 haddrO integer 0 hmask0 integer 16 f 00 loaddr0 integer 16 000 iomaskO integer 16 fff hindexl integer 0 haddrl integer hmask1 integer 16 f 00 ioaddr
59. note for HAPS 50 motherboard demonstration sess 57 14 1 dul 57 14 2 Hardware requirements uo eee vede ut ete bn NR et 57 14 3 Software requirements n ete e ee e R R E eU ene tbe do etae i ege 58 14 4 Downloads a o t ds ld ot cp So dt 58 14 5 Software installation oo pU ERE ARE EE pU AREE A ER e AB tate oes 58 14 6 Hatrdware setup mote A s yin ttem aiite Guo A a we 59 14 6 1 Setting up the HAPS 51 motherboard sess 59 14 6 2 Setting up the HAPS 52 motherboard sss 59 14 6 3 Setting up the HAPS 54 motherboard sss 60 14 7 Software setup cud e AS dida i ete deii i su 61 14 8 Compilation optional 4 rent n op apodo TIGRE 61 14 9 Alternative software optional nie ee er RE DIR de eie e te Un 62 1 1 1 2 1 3 Introduction Overview Gaisler Research provides system on a chip SoC solutions for exceptionally competitive markets such as aerospace military and demanding commercial applications Gaisler Research s products con sist of usercustomizable 32 bit SPARC V8 processor cores peripheral IP cores and associated soft ware and development tools The key product is the LEON3 32 bit SPARC processor core LEON3 LEONG is a synthesisable VHDL model of a 32 bit processor compliant with the SPARC V8 architec ture The model is highly configurable and particularly suitable for system on a chip SOC
60. nu TE HAPS GAISLER RESEARCH High performance ASIC Prototyping System Synplicity s HAPS Development Platform IP Core User s Manual Based on GRLIB Sandi Habinc Nils Johan Wessman Copyright Gaisler Research May 2008 Table of contents InttOQUCOTE sees ceo t see deiecta er a RAR 5 1 1 OVER iio ace is a A 5 1 2 IP cores for HAPS development 80 eren 5 1 3 Implementation character cete segs 5 1 4 A sce ie c REI e ioi etes ta ecole tete ld USES 6 1 5 References uero ore Pa nee 6 1 6 About Sopla odes tates qo mU eredi 6 FLASH 1X1 32 16 bit PROM Controller for HAPS FLASH Ixl 7 2 1 OVerVIeW ioco CUR Te ea OU eia EHE E UR dta NER 7 2 2 Vendor and device 1dentifiet nies rt aret teet av ee a eerie 7 2 3 Library dependencies dee rede ttp tite ertet a tee ulta rebate 7 2 4 Component declaration I Ree i ade io ca te teet 8 2 5 nstantiafiom ded e dir RE RE ROTER R BLR TERRIER aio 8 SRAM 1XI 32 bit SSRAM PROM Controller for HAPS SRAM 41Ixl 9 3 1 uad a 9 3 2 Vendor and device identifier 9 3 3 Library dependencies cete dst eee pe Ee e Cet E I NE RE 9 3 4 Component declaration rs diat died 10 3 5 InstantiatiOT roe dai 10 TEST 1X2 Controller for HAPS test daughter board TEST 1x2 22 11 4 1 OVENI E Wunden dt a o SUE Ef 11 4 2 OperatiOM e
61. o RR ee Pe he SU 34 9 5 Component declaration e S ene sheath a dA tont Atte ade 34 9 6 Instantiationz s r Sub Ame ete eate rotor secret 35 9 7 HapsMap file for HapsTrak controller essen enne 37 LEON3 template design for HAPS 31 motherboard sse 40 10 1 COV ET VIS Wis oc pede o e n Lo 40 10 2 Configuration 4c eee c n eene ee t er e e eed E e ae 41 10 3 COTES oy R Eos 42 10 4 E P 42 10 5 Memory maps E 43 10 6 Setups A eR e uere ee eC EI E 43 LEON3 template design for HAPS 51 motherboard sse 45 11 1 OVervieyy z SEER 45 11 2 Config ratioli O RR Ciao nnt 46 11 3 COLES 0000007 et RE CR ORO 00 0000000 eo pve o ies 47 11 4 Vi I E ERE TENDO a DIDI LU LU o es satis 47 11 5 Memory map E 48 LEON3 template design for HAPS 52 motherboard sse 49 12 1 ONCE Led e o dl e mote R 49 12 2 CO 50 12 3 0300000500 51 12 4 A d E 51 12 5 hg RI 52 LEON3 template design for HAPS 54 motherboard sse 53 13 1 OVerVie ROA MT PR A AA A M EA mE MIA 53 14 13 2 Configuration Nm 54 13 3 COTES c e ode UR UD RF EE e e UR E ENS e ee 55 13 4 TIGHT p P 55 13 5 MEDI Maa b b sl 56 Application
62. oller and the HapsTrak I or HapsTrak II pins depends on which connector on the motherboard it is connected to For details please refer to the HAPS manuals from Synplicity The following is an example of a mapping between the HapsTrak controller ports and registers typ ical signal names for a top level design and the HapsTrak II pin names hapstraki hapstrako 0 unused H2 hapstraki hapstrako 30 downto 1 hapstraka 30 1 A30 downto Al hapstraki hapstrako 31 unused lt gt H4 hapstraki hapstrako 32 unused H6 hapstraki hapstrako 62 downto 33 hapstraka 60 31 A60 downto A31 hapstraki hapstrako 63 unused H8 hapstraki hapstrako 64 unused lt gt H1 hapstraki hapstrako 94 downto 65 hapstrakb 30 1 B30 downto B1 hapstraki hapstrako 95 unused H3 hapstraki hapstrako 96 unused H5 hapstraki hapstrako 125 downto 97 hapstrakb 59 31 B59 downto B31 hapstraki hapstrako 126 unused B60 hapstraki hapstrako 127 unused H7 Registers The core is programmed through registers mapped into APB address space Table 11 HAPSTRAK registers APB address offset Register 0x00 0x0C Input registers 0x10 1 Output registers 0x20 0x2C Output enable registers Table 12 Input register 0 17
63. on board 16 MHz oscillator should be used with the settings N 1 and M 25 Please refer to the leon3mp con and leon3mp pas files in the template design directory for the detail configuration of the board 13 3 13 4 55 Cores The LEON3 HAPS 54 template design is based on cores from the GRLIB IP library The vendor and device identifiers for each core can be extracted from the plug amp play information as described in the GRLIB IP Core User s Manual The used IP cores are listed in table 51 Table 51 Used IP cores Core Function Vendor Device AHBCTRL AHB Arbiter amp Decoder 0x01 APBCTRL AHB APB Bridge 0x01 0x006 LEON3 LEON3 SPARC V8 32 bit processor 0x01 0x003 DSU3 LEON3 Debug support unit 0x01 0x004 AHBJTAG JTAG AHB debug interface 0x01 0x01C SRAM 1 1 32 bit SSRAM PROM Controller for HAPS SRAM 1x1 0x01 0x00A FLASH 1 1 32 16 bit PROM Controller for HAPS FLASH 1x1 0x01 0x00A AHBSTAT AHB failing address register 0x01 0x052 APBUART 8 bit UART with FIFO 0x01 0x00C GPTIMER Modular timer unit with watchdog 0x01 0x011 IRQMP LEON3 Interrupt controller 0x01 0x00D HAPSTRAK HapsTrak controller for HAPS boards 0x01 0x077 SDRAM 1 1 Dual 32 bit SDRAM Controller for HAPS SDRAM 1x1 0x01 0x009 DDR 1 1 64 bit DDR266 Controller for HAPS DDR 1x1 0x01 0x025 GEPHY 1X1 Dual Ethernet Controller for HAPS GEPHY 1x1 0x01 x01D BIO1 BIO1 Controller for HAPS BIO1 0x01 0x07A Interrupt
64. rlib library g use gaisl use gaisl rlib amba all aisler er haps all er memctrl all signal flash memi memory in type signal flash memo memory out type begin flash 1x1 0 if CFG FLASH 1x1 1 generate flash 1x1 00 flash 1 1 generic map por end gen hindex gt 3 pindex gt 0 rommask 1682008 iomask gt 0 no memory mapped IO ramaddr gt 0 rammask s 0 no SSRAM memory paddr gt 4 bus16 s CFG FLASH 1x1 PROM16 netlist gt CFG FLASH 1x1 NETLIST tech gt virtex5 t map rstn clkm erate ahbsi ahbso 3 apbi apbo 0 flash memi flash memo 3 1 32 3 3 SRAM TXI 32 bit SSRAM PROM Controller for HAPS SRAM 1x1 Overview The memory controller for the Synplicity HAPS SRAM 1x1 daughter boards is a 32 bit SSRAM controller that interfaces external synchronous pipelined SRAM to the AMBA AHB bus It can also interface 16 and 32 bit PROM or Flash PROM memory The memory controller acts as a slave on the AHB bus and has a configuration register accessible through an APB slave interface The memory controller is based on the Gaisler Research SSRCTRL 32 bit SSRAM PROM Control ler See corresponding manual for details The SSCTRL IP core is provided in VHDL netlist format for the Xilinx Virtex 4 and Virtex 5 technologies as part of the GRLIB GPL distribution The memory controller can also be used with the Synplicity HAPS 51 motherboard to interface the synchronous
65. rupt assignment Core Interrupt Comment AHBSTAT 7 APBUART 2 GPTIMER 8 9 GEPHY 1X1 10 12 52 12 5 Memory map The memory map shown in table 49 is based on the AMBA AHB address space Access to addresses outside the ranges vvill return an AHB error response Table 49 AMBA AHB address range Core Address range Area FLASH 1X1 0x00000000 0x10000000 Flash PROM area not all used SRAM_1X1 0x40000000 0x80000000 SSRAM area not all used APBCTRL 0x80000000 0x81000000 APB bridge DSU3 0x90000000 0xA0000000 Registers DDR 1 1 0xA0000000 0xB0000000 DDR area SDRAM 1 1 0xB0000000 0xC0000000 SDRAM area SDRAM 1 1 0xC0000000 0xD0000000 DDR 1X1 OxFFF00200 OxFFF00300 Registers for DDR 1X1 controller SDRAM 1 1 OxFFF00300 OxFFF00400 Registers for SDRAM 1 1 controller SDRAM 1X1 OxFFF00400 OxFFF00500 AHB plug amp play OxFFFFF000 OXFFFFFFFF Registers The control registers of most on chip peripherals are accessible via the AHB APB bridge which is mapped at address 0x80000000 The memory map shown in table 50 is based on the AMBA AHB address space The detailed register layout is defined in the GRLIB IP Core User s Manual Table 50 APB address range Core Address range Comment SRAM_1X1 0x80000000 0x80000100 Used with extra SRAM_1x1 daughter board APBUART 0x80000100 0x80000200 IRQMP 0x80
66. s All interrupts are handled by the interrupt controller and forwarded to the LEON3 processor See the GRLIB IP Core User s Manual for how and when the interrupts are raised Table 52 Interrupt assignment Core Interrupt Comment AHBSTAT 7 APBUART 2 GPTIMER 8 9 GEPHY 1X1 10 12 56 13 5 Memory map The memory map shown in table 53 is based on the AMBA AHB address space Access to addresses outside the ranges vvill return an AHB error response Table 53 AMBA AHB address range Core Address range Area FLASH 1X1 0x00000000 0x10000000 Flash PROM area not all used SRAM_1X1 0x40000000 0x80000000 SSRAM area not all used APBCTRL 0x80000000 0x81000000 APB bridge DSU3 0x90000000 0xA0000000 Registers DDR 1 1 0xA0000000 0xB0000000 DDR area SDRAM 1 1 0xB0000000 0xC0000000 SDRAM area SDRAM 1 1 0xC0000000 0xD0000000 DDR 1X1 OxFFF00200 OxFFF00300 Registers for DDR 1X1 controller SDRAM 1 1 OxFFF00300 OxFFF00400 Registers for SDRAM 1 1 controller SDRAM 1X1 OxFFF00400 OxFFF00500 AHB plug amp play OxFFFFF000 OXFFFFFFFF Registers The control registers of most on chip peripherals are accessible via the AHB APB bridge which is mapped at address 0x80000000 The memory map shown in table 54 is based on the AMBA AHB address space The detailed register layout is defined in the GRLIB IP Core User s Manual Table 54 APB address r
67. s are instantiated here GRETH el gephy 1x1 generic map grethenO hindex0 pindex0 paddro pirq0 burstlengtho edc10 22 2 2 x 12 gt 32 35 36 edclbufsz0 macaddrho macaddrlO ipaddrh0 ipaddr10 giga0 grethenl 1 pindexi paddr1 pirq 1 burstlength1i edcli edclbufsz macaddrh macaddrl ipaddrh1 ipaddr11 gigal memtech mdcscaler nsync port map rst clk ahbmi0 ahbmo0 apbi0 apbo0 ethi0 etho0 ahbmil ahbmol apbil apbol ethil ethol gt C r8 gt 16 00005E gt 16 00005D gt 16 c0as gt 16 0035 gt gt 1 gt 1 gt 13 gt 13 I3 m 32 s 1 gt 8 gt 16100005Ef gt 16 00005D gt 16 c0as gt 16 0035 gt gt inferred gt 50 5 T gt rstn lk ahbmi ahbmo 0 apbi apbo 12 ethi etho ahbmi ahbmo 1 apbi apbo 13 ethil ethol 9 7 37 HapsMap file for HapsTrak controller HapsMap is a pin assignment software from Synplicity that generates Xilinx UCF files describing the mapping from RTL port names VHDL or Verilog to pins for all FPGAs in a HAPS system The pro gram consists of a script based engine and a library of text files map describing the different HAPS motherboards and different HAPS daughter boards If additional cards are created or if custom made daughter boards are creat
68. sTrak 31 output unused 30 1 HapsTrak 30 1 output a k a hapstraka 30 1 0 HapsTrak 0 output unused Table 17 Output register 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 63 62 HapsTrak 33 32 fAIAAAAAAN V AAA AAAAAAAAAAAQAQAAAQAAA ANQA 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 31 HapsTrak 63 output unused 30 1 HapsTrak 62 33 output a k a hapstraka 60 31 0 HapsTrak 32 output unused Table 18 Output register 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 95 94 HapsTrak 65 64 B IBIB BIB B B BIB BIBIB BIB B B BIB B BIBIBIB B 30 29 28 27 26 25 24 23 22 21 20 19 18117 16115 14 13 1211110019 87 77161 1514 3121 1 31 HapsTrak 95 output unused 30 1 HapsTrak 94 65 output a k a hapstrakb 30 1 0 HapsTrak 64 output unused Table 19 Output register 3 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 127 126 125 HapsTrak 97 96 B BBB B B B B B B PBB B BB BB BBB B BBB B BIB BBB B B B B 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 31 HapsTrak 127 output unused 30 HapsTrak 126 output unused 29 1 HapsTrak 125 97 output a k a hapstrakb 60 31 0 HapsTrak 96 output
69. t 19 Ul A20 Jl A20 abstract 20 Ul A21 UL A21 abstract 21 Ul A22 Jl A22 abstract 22 Ul A23 Ul A23 abstract 23 Ul A24 Jl A24 abstract 24 Ul A25 Jl A25 abstract 25 Ul A26 Ul A26 abstract 26 Ul A27 Ul A27 abstract 27 Ul A28 Ul A28 abstract 28 Ul A29 Ul A29 abstract 29 Ul A30 Jl A30 abstract 30 Ul A31 Jl A31 abstract 33 Ul A32 Jl A32 abstract 34 Ul A33 Jl A33 abstract 35 Ul A34 Ul A34 abstract 36 Ul A35 Jl A35 abstract 37 Ul A36 Ul A36 abstract 38 Ul A37 Jl A37 abstract 39 Ul A38 Ul A38 abstract 40 38 C4 C4 C4 C4 C4 Cj C4 C4 C4 C4 C4 C4 Cj C4 C4 C4 C4 C4 C4 C4 Cj C4 C4 C4 C4 C4 C4 C4 Cj C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 Cj c Ea Er E E tra E Er O E EE 1 A39 1 A40 1 A41 1 A42 1 A43 1 A44 1 A45 1 A46 1 A47 1 A48 1 A49 1 A50 1 A51 1 A52 1 A53 1 A54 1 A55 1 A56 1 A57 1 A58 1 A59 1 A60 1 A39 1 440 Jl A41 1 A42 1 A43 1 A44 1 A45 1 446 1 447 1 448 1 449 1 A50 Jl A51 1 A52 1 A53 1 A54 1 A55 1 A56 Jl A57 1 A58 1 A59 1 A60 J1 B1 Ul B2 J1 B3 J1 B4 1 B5 1 B6 J1 B7 J1 B8 Ul B9 J1 B10 J1 Bil J1 B12 J1 B13 1 B14 1 B15 J1_B16 J1_B17 J1_B18 J1_B19 J1_B20 J1_B21 J1_B22 J1_B23 J1_B24 J1_B25 J1_B26 J1_B27 J1_B28 J1_B29 J1_B30 J1_B31 J1_B32 J1_B33 J1_B34 J1_B35 J1 B36 J1_B37 J1 B38 J1 B39 1 B40 J1 B41 1 B42 1 B43 J1 B44 J1_B
70. t tvvo colored LEDs eight push buttons and four seven segment LED digits are available for this purpose These inputs and outputs are monitored and controlled via one GPIO con nector on the HAPS motherboard The BIO1 controller supports the follovving functions 8 push buttons 8two colored LEDs 4seven segment LED digits Update rate control Figure 5 HAPS BIOI daughter board More information on HAPS can be found at www synplicity com Synplicity the Synplicity logo and Simply Better Results are registered trademarks of Synplicity Inc HAPS the HAPS logo High performance ASIC Prototyping System and HapsTrak HapsTrak I and HapsTrak II are trademarks of Synplicity Inc Operation The status of each button can be read out via a register The value of each LED and seven segment LED digits can be controlled via registers The bit rate and update frequency of the communication with the BIO1 card can be controlled via a control register All registers are accessed via the APB bus The controller continuously updates the LEDs and LED digits and reads the status of the push buttons The LEDs are updated in the following order LED L1 to L8 LED digit D3 and D4 LED digit D1 and D2 After all LEDs are updated the push buttons are read The bit rate of communication with the BIO1 board is controlled by the bit rate section of the control register The bit rate is set to System clock bit rate value 1 The updat
71. the GRLIB IP Library User s Manual The Xilinx ucf pin placement file for the motherboard can be generated from the leon3mp pas and leon3mp con files using the HapsMap software from Synplicity After editing the leon3mp pas or leon3mp con file run the following command to generate a new ucf file gt make hapsmap Ensure that the hapsmap executable is the search path For details please refer to the HAPS manuals from Synplicity The 70 MHz template design assumes an external clock frequency of 100 MHz See HAPS 51 moth erboard documentation for appropriate settings of the external clock generator circuitry The on board 16 MHz oscillator should be used with the settings N 1 and M 25 Please refer to the leon3mp con and leon3mp pas files in the template design directory for the detail configuration of the board 11 3 11 4 47 Cores The LEON3 HAPS 51 template design is based on cores from the GRLIB IP library The vendor and device identifiers for each core can be extracted from the plug amp play information as described in the GRLIB IP Core User s Manual The used IP cores are listed in table 43 Table 43 Used IP cores Core Function Vendor Device AHBCTRL AHB Arbiter amp Decoder 0x01 APBCTRL AHB APB Bridge 0x01 0x006 LEON3 LEON3 SPARC V8 32 bit processor 0x01 0x003 DSU3 LEON3 Debug support unit 0x01 0x004 AHBJTAG JTAG AHB debug interface 0x01
72. troller for HAPS SDRAM 1x1 0x01 0x009 GPL DDR 1X1 64 bit DDR266 Controller for HAPS DDR 1x1 0x01 0x025 GPL GEPHY 1X1 Ethernet Controller for HAPS GEPHY 1x1 0x01 0x00A GPL Note The underlying SSRAM controller used in the FLASH 1X1 and SRAM 1XI cores is provided in VHDL netlist format in the GRLIB GPL distribution The VHDL source code is only provided under commercial license Note The 10 100 Mbit Media Access Controller MAC is available in the GRLIB GPL distribution The 1000 Mbit MAC is only provided under commercial license References GRLIB GRLIB IP Library User s Manual Gaisler Research http vvvvvv gaisler com products grlib grlib pdf GRIP GRLIB IP Core User s Manual Gaisler Research http www gaisler com products grlib grip pdf GRMON GRMON User s Manual Gaisler Research http vvvvvv gaisler com doc grmon pdf SPARC The SPARC Architecture Manual Version 8 Revision SAV080S19308 SPARC International Inc http www sparc org About Synplicity Synplicity amp Inc is a leading supplier of innovative IC design and verification solutions that serve a wide range of communications military aerospace semiconductor consumer computer and other electronic applications markets Synplicity s FPGA implementation tools provide outstanding perfor mance cost and time to market benefits by simplifying improving and automating logic synthesis physical synthesis analysis and debug for programmab

Synplicity`s HAPS Development Platform IP Core User`s Manual

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