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ModelSim SE Tutorial

1. Browse 1b m Test Dataset Either dataset can be a saved wif file or a dataset that is already opened 1 Create a comparison using the Comparison Wizard Use the Browse buttons to browse for a Select Tools Waveform Compare Comparison Wizard saved dataset or click the down Use Curent Simulation 1 arrow to select file from the dataset selection history b Click the Browse button and select gold wif as the reference dataset IV Update comparison after each run Figure 127 C Specify Dataset Recall that gold wlf is from the first simulation run 2 Leaving the test dataset set Use Current Simulation click Next d Select Compare All Signals in the second dialog and click Next Figure 128 e Inthe next three dialogs click Next Compute Differences Now and lt Previous Next gt Finish respectively ModelSim performs the comparison and displays the compared signals Figure 128 Second dialog of the Comparison Wizard in the Wave window I Comparison wizara With the reference and test datasets selected the next step is to select a ison Method comparison method omparison Metho 1 Compare All Signals compares all signals in the test dataset against the signals in the reference dataset Compare Top Level Ports Compare Top Level Ports compares Specify Comparison by Signal the top level ports of the
2. Append to file ModelSim SE Tutorial T 134 Lesson 11 Simulating with Code Coverage Lesson wrap up This concludes this lesson Before continuing we need to end the current simulation 1 quit sim at the VSIM gt prompt ModelSim SE Tutorial Lesson 12 Debugging with PSL assertions Topics The following topics are covered in this lesson Introduction Design files for this lesson Related reading Compile the example design Load and run without assertions Using assertions to speed debugging Debugging the assertion failure Lesson wrap up T 136 T 136 T 136 T 137 T 138 T 139 T 141 T 143 T 135 ModelSim SE Tutorial T 136 Lesson 12 Debugging with PSL assertions Introduction Using assertions in your HDL code increases visibility into your design and improves verification productivity ModelSim supports Property Specification Language PSL assertions for use in dynamic simulation verification These assertions are simple statements of design intent that declare design or interface assumptions This lesson will familiarize you with the use of PSL assertions in ModelSim You will run a simulation with and without assertions enabled so you can see how much easier it is to debug with assertions After running the simulation with assertions you will use the ModelSim debugging environment to locate a problem with the design Design files for t
3. mem mem 1 ModelSim SE Tutorial T 106 Lesson 9 Viewing and initializing memories Saving memory contents to a file Figure 86 Save Memory dialog box x You can save memory contents to a file that can be loaded at some later point in n xl simulation nstance Name Aram tb spram1 mem 1 Save a memory pattern from the ram_tb spraml mem instance to a file a Make sure ram tb spraml mem is open and selected in the MDI frame Address Range b Select File gt Save to bring up the Save Memory dialog box Figure 86 AI c Forthe Address Radix select Decimal Addresses in decimal d Forthe Data Radix select Binary Start 0 End 4035 e data mem mem into the Filename field f Click OK m File Format You can view the saved file in any editor C Verilog Hex No addresses C DM Memory pattern files can be saved as relocatable files simply by leaving out the nc Compress address information Relocatable memory files can be loaded anywhere in a MTI memory because no addresses are specified M Address Radix Data Radix C r pe 2 Save a relocatable memory pattern file from the ram_tb spram2 mem een ee instance Decimal Binary a Select the mem 1 tab in the MDI pane to see the data for the ram_tb s DE spram2 mem instance 1c 1d Decimal b Right click on the memory contents to open a popup menu and select Unsigned Properties C Hexadecimal
4. Figure 73 Tracing the event set BEIC i lol x File Edit View Navigate Trace Tools Window Ie 3 xig uz oi a NAND 50 test A tout strb ni Kl TS Extended mode enabled Keep 1 Itop p amp ASSIGN amp 251 7 Tracing an X unknown The Dataflow window lets you easily track an unknown value X as it propagates through the design The Dataflow window is linked to the stand alone Wave window so you can view signals in the Wave window and then use the Dataflow window to track the source of a problem As you traverse your design in the Dataflow window appropriate signals are added automatically to the Wave window 1 View t out in the Wave and Dataflow windows a Scroll in the Wave window until you can see top p t_out t_out goes to an unknown state at 2065 ns and continues transitioning between and unknown for the rest of the run Figure 74 The red color of the waveform indicates an unknown value b Double click the last transition of signal t out at 2784 ns This automatically opens the Dataflow window and displays t out its associated process and its waveform You may need to increase the size of the Dataflow window and scroll the panes to see everything c the cursor in the Wave window As previously mentioned the Wave and Dataflow windows are designed to work together As you move the cursor in the Wave the value o
5. tv ModelSim SE Tutorial Lesson wrap up T 143 Lesson wrap up This concludes this lesson Before continuing we need to end the current simulation 1 Select Simulate gt End Simulation Click Yes ModelSim SE Tutorial T 144 Lesson 12 Debugging with PSL assertions ModelSim SE Tutorial Lesson 13 Waveform Compare Topics The following topics are covered in this lesson Introduction Design files for this lesson Related reading Creating the test dataset Verilog VHDL Comparing the simulation runs Viewing comparison data SU e ux Viewing comparison data in the Main window Viewing comparison data in the Wave window Viewing comparison data in the List window Saving and reloading comparison data Lesson wrap up gt Note The functionality described in this tutorial requires a compare license feature in your ModelSim license file Please contact your Mentor Graphics sales representative if you currently do not have such a feature T 146 T 146 T 146 T 148 T 148 T 149 T 150 T 151 T 151 T 151 T 152 T 153 T 155 T 145 ModelSim SE Tutorial T 146 Lesson 13 Waveform Compare Introduction Waveform Compare computes timing differences between test signals and reference signals The general procedure for comparing waveforms has four main steps 1 Select the simulations or datasets to compare 2 Specify the signals or regions to compare
6. Browse a Type vsim tb at the ModelSim prompt Recursive All assertions 2 Execute the lesson DO file a Typedo sim do at the ModelSim gt prompt Failures Passes The DO file does the following m Assertions Assertions Opens the Assertions pane and displays all assertions Enable C Enable e Opens a Source window C Disable Disable e Adds signals to the Wave window Logging You may need to resize and move the panes to better view the data On On 3 Set all assertions to Break on Failures C Off C Off a Make sure the Assertions pane is selected SG Sy Limit Limit b Select Edit gt Advanced gt Change This opens the Change assertions oles Pu dialog Figure 120 Limited Limited c In the Change on section select All assertions if necessary Unlimited Unlimited d In the Failures Assertions section select Enable if necessary e the Failures Action section select Break Action This causes the simulation to break stop on any failed assertion Continue f Click the OK button to accept your selections and close the dialog Break Exit OK Cancel Apply ModelSim SE Tutorial T 140 Lesson 12 Debugging with PSL assertions 4 assertions and cover directives to the Wave window a b Select the Assertions pane if necessary Select Add gt Wave gt Assertio
7. 3 Recompile and simulate a In the Project tab of the Workspace right click tcounter vhd and select Compile Compile Selected In the Library tab double click test counter to load the design The design loads without errors ModelSim SE Tutorial Figure 34 Mapping to the parts lib library fu Create a New Library Create C anew library and a logical mapping to it to an existing library Library Name parts_lib Library Maps to E75 Tutorial resource library parts vi Browse DK Cancel Figure 35 Adding LIBRARY and USE statements to the testbench C modeltech examples testbench tcounter vhd 3 4 All Rights Reserved 5 E 6 THIS WORK CONTAINS TRADE SECRET AND PROPRI 7 MENTOR GRAPHICS CORPORATION OR ITS LICENS 8 9 10 LIBRARY parts lib 11 USE parts lib ALL 12 13 entity test_counter is 14 PORT count BUFFER bit_vector 8 downt c IE eee H tcounter vhd Permanently mapping resource libraries If you reference particular resource libraries in every project or simulation you may want to permanently map the libraries Doing this requires that you edit the master modelsim ini file in the installation directory Though you won t actually practice it in this tutorial here are the steps for editing the file 1 Locate the modelsim ini file in the ModelSim installation directory install dir modeltech modelsim ini
8. J OM in amp 1a ModelSim SE Tutorial Viewing a memory T 105 Edit the address location directly Figure 84 Edit the address directly To quickly move to a particular address do the following ESS OF spram i mem a Double click any address in the address column 30 01000110 31 01000111 32 01001000 33 01001001 34 01001010 The pane scrolls to that address 35 01001011 36 01001100 b Enter any desired address Figure 84 Press Enter on your keyboard 37 01001101 Now let s find a particular data entry 100 Oloollio 01001111 a Right click anywhere in the data column and select Find a 01010000 e i 01010001 The Find in dialog box opens Figure 85 01010010 b 11111010 in the Find data field and click Find Next The data scrolls to the first occurrence of that address Click Find Next a few more times to search through the list c Click Close to close the dialog box Figure 85 Find in searching for data value ram tb spram1 mem Lm xi 92 10000100 al l1000n1n1 E 3 94 ELLE CURE EST 7 95 100 36 100 3 i oe 200i Find data 11111010 Find Next 38 100 lace with ee Replace wi eplace 100 100 Replace al 101 100 102 1000 Find backwards 103 100 Example Find Patterns 122 1001 1224 101 O11 052 hfa38 Cose
9. st Net Lesson wrap up T 29 Lesson wrap up This concludes this lesson Before continuing we need to end the current simulation 1 Select Simulate gt End Simulation 2 Click Yes when prompted to confirm that you wish to quit simulating ModelSim SE Tutorial T 30 Lesson 2 Basic simulation ModelSim SE Tutorial Lesson 3 ModelSim projects Topics The following topics are covered in this lesson Introduction Related reading Creating anew project Adding objects to the project Changing compile order VHDL Compiling and loading a design Organizing projects with folders Adding folders s Moving files to folders Simulation Configurations Lesson wrap up T 32 T 32 T 33 T 34 T 35 T 36 T 37 T 37 T 38 T 39 T 40 T 31 ModelSim SE Tutorial T 32 Lesson 3 ModelSim projects Introduction In this lesson you will practice creating a project At a minimum projects have a work library and a session state that is stored in a mpf file A project may also consist of HDL source files or references to source files e other files such as READMES or other project documentation e local libraries e references to global libraries This lesson uses the Verilog files tcounter v and counter v in the examples If you have a VHDL license use tcounter vhd and counter vhd instead Related reading ModelSim User s Manual Chapter 2 Projects UM 37 ModelSim SE Tutorial
10. wave default d nl File Edit View Insert Format Tools Window QQ ego Edit counter reset 510 m E E gt gt Se Now 0 ns Delta 0 2 Ons to 1522 ns 2 Stretch an edge on signal clk a b Click signal on the transition at 350 ns Select Edit gt Edit Wave gt Stretch Edge from the menu bar If the command is dimmed out the cursor probably isn t on the edge at 350 ns In the Edit Stretch Edge dialog enter 50 for Duration make sure the Time field shows 350 and then click OK Figure 61 The wave edge stretches so it s high until 400 ns Figure 62 Note the difference between stretching and moving an edge the Stretch command moves an edge by moving other edges on the waveform either increasing waveform duration or deleting edges at the beginning of simulation time the Move command moves an edge but does not move other edges on the waveform You should see in the Wave window that the waveform for signal clk now extends to 1050 ns Editing waveforms in the Wave window Figure 61 The Edit Stretch Edge dialog M Edit Stretch Edge x Signal Name Edit counter clk Direction Forward Backward Duration Time Time Unit fo f Figure 62 Stretching an edge on signal clk y wave default File Edit View Insert Format Tools Window Edit counter clk 510 4 Edit counter reset
11. 1 Open a memory instance and change its display characteristics a Double click instance ram_tb dpraml mem in the Memories tab b Right click in the memory contents pane and select Properties c Change the Data Radix to Hexadecimal d Select Words per line and enter 2 e Click OK 2 Initialize a range of memory addresses from a fill pattern a Right click in the data column of ram tb dpram I mem contents pane and select Change to open the Change Memory dialog Figure 92 b Click the Addresses radio button and enter the start address as 0x00000006 and the end address as 0x00000009 The Ox hex notation is optional c Select Random as the Fill Type d Enter 0 as the Fill Data setting the seed for the Random pattern e Click OK The data in the specified range are replaced with a generated random fill pattern Figure 93 Interactive debugging commands T 109 Figure 91 Original memory contents E ram_tb dpram1 mem x 00000000 06 03 00000002 7a 1b 00000004 1c 14 00000006 1e 1f 00000008 20 21 00000002 ZZ Z3 0000000 24 25 0000000e 26 27 7 J gt lt 5ram tb v Figure 92 Changing memory contents for a range of addresses Change Memory xi Instance Name Aram tb dpramt mem EN Address Range Fill 1 C Value m Addresses a Increment C Di it Start 0 00000006 End 0x00000009 d
12. 2 IMPORTANT Make a backup copy of the file 3 Change the file attributes of modelsim ini so it is no longer read only 4 Open the file and enter your library mappings in the Library section For example parts lib C libraries parts lib 5 Save the file 6 Change the file attributes so the file is read only again Permanently mapping resource libraries T 49 ModelSim SE Tutorial T 50 Lesson 4 Working with multiple libraries Lesson wrap up This concludes this lesson Before continuing we need to end the current simulation and close the project 1 Select Simulate gt End Simulation Click Yes 2 Select the Project tab of the Main window Workspace 3 Select File gt Close Click OK ModelSim SE Tutorial Lesson 5 Simulating designs with SystemC Topics The following topics are covered in this lesson Introduction Design files for this lesson Related reading Setting up the environment Preparing an OSCI SystemC design Compiling a SystemC only design Mixed SystemC and HDL example Viewing SystemC objects in the GUI Setting breakpoints and stepping in the Source window Lesson Wrap up Note The functionality described in this tutorial requires a systemc license feature in your ModelSim license file Please contact your Mentor Graphics sales representative if you currently do not have such a feature T 52 T 52 T 52 T 53 T 56 T 56 T 56 T 60 T 61 T 64 T 51 M
13. 266 of the dramcon_sim v module ERROR at tine 26 400 Controller is not working data written 01 dataread 80 VHDL The simulation reports an error at 246800 ns and stops on line 135 of the dramcon_sim vhd entity The ERROR message indicates that the controller is not working because Break at dramcon_sim v line 266 a value read from memory does not match the expected value Figure VSIM 5 vsim tb nopsl 119 To debug the error you might first examine the simulation waveforms and look for all writes to the memory location You might also check the data on the bus and the actual memory contents at the location after each write If that did not identify the problem you might then check all refresh cycles to determine if a refresh corrupted the memory location Quite possibly all of these debugging activities would be required depending on one s skill or luck in determining the most likely cause of the error Any way you look at it it is a tedious exercise 3 the simulation a quit sim at the VSIM gt prompt to end this simulation ModelSim SE Tutorial Using assertions to speed debugging T 139 Figure 120 Change assertions dialog Using assertions to speed debugging M Change assertions E x To show how assertions help with debugging we ll reload the design with assertions r Change on C Specific instance Reload the design Instance Name sim tb
14. D Dataflow window T 89 displaying hierarchy T 96 expanding to drivers readers T 92 options T 96 tracing events T 93 tracing unknowns T 95 dataset close command T 155 design library working type T 16 DO files T 157 documentation T 7 drivers expanding to T 92 E error messages more information T 46 external libraries linking to T 46 F folders in projects T 37 format saving for Wave window T 73 G gcc T 53 ModelSim SE Tutorial T 174 Index hierarchy displaying in Dataflow window T 96 L libraries design library types T 16 linking to external libraries T 46 mapping to permanently T 49 resource libraries T 16 working libraries T 16 working creating T 21 linking to external libraries T 46 M macros T 157 manuals T 7 mapping libraries permanently T 49 memories changing values T 109 initializing T 107 viewing T 99 memory contents saving to a file T 106 Memory window T 99 N notepad command T 153 O options simulation T 39 P Performance Analyzer T 113 ModelSim SE Tutorial filtering data T 120 physical connectivity T 92 Profiler profile details T 119 viewing profile details T 119 projects T 31 adding items to T 34 creating T 33 flow overview T 15 organizing with folders T 37 simulation configurations T 39 Q quit command T 46 R radix command T 102 reference dataset Waveform Compare T 147 reference signals T 146 run all T 26 run command T 25 S
15. b Save the file as basic cpp You can overwrite the existing basic cpp 4 View and edit the basic_orig h header file a Adda ModelSim specific SC_MODULE top see Figure 36 The declarations that were in sc_main are placed here in the header file in SC_MODULE top This creates a top level module above mod_a which allows the tool s automatic name binding feature to properly associate the primitive channels with their names b Save the file as basic h You can overwrite the existing basic h Now you have made all the edits that are required for preparing the design for compilation Preparing an OSCI SystemC design T 55 Figure 36 Basic example excerpts before and after modifications basic_orig cpp original file include basic h int se_main int char sc_clock clk moda a a jj a oclk cik j sc initialize return 0 basic orig h ifndef INCLUDED TEST define INCLUDED TEST include systemc h SC_MODULE mod_a sc_in_clk clk void main action method cout lt lt simcontext gt delta_count lt lt main action method called endl void main action thread while true cout lt lt simcontext gt delta_count lt lt main action thread called endl SC_CTOR mod_a SC_METHOD main_action_method SC_THREAD main_action_thread endif basic cpp modified file Existing contents of bas
16. d Select File New Project Type counter in the Project Name field Click OK If a dialog appears asking about which modelsim ini file to use click Use Default Ini Add the testbench to the project a b c d Click Add Existing File in the Add items to the Project dialog Click the Browse button and select tcounter v Click Open and then OK Click Close to dismiss the Add items to the Project dialog The tcounter v file is listed in the Project tab of the Main window Compile the testbench a Right click tcounter v and select Compile Compile Selected Creating the project T 45 ModelSim SE Tutorial T 46 Lesson 4 Working with multiple libraries Linking to the resource library To wrap up this part of the lesson you will link to the parts_lib library you created earlier But first try simulating the testbench without the link and see what happens ModelSim responds differently for Verilog and VHDL in this situation Verilog 1 Simulate a Verilog design with a missing resource library a VHDL In the Library tab click the icon next to the work library double click test counter The Main window Transcript reports an error Figure 31 When you see a message that contains text like Error vsim 3033 you can view more detail by using the verror command Type verror 3033 at the ModelSim prompt The expanded error message tells you that a design unit could not
17. Creating a new project 1 If you just finished the previous lesson ModelSim should already be running If not start ModelSim a Type vsim at a UNIX shell prompt or use the ModelSim icon in Windows Create a new project a Select Create a Project from the Welcome dialog or File gt New gt Project Main window from the menu bar This opens a dialog where you enter a Project Name Project Location i e directory and Default Library Name Figure 14 The default library is where compiled design units will reside Type test in the Project Name field Click Browse to select a directory where the project file will be stored Leave the Default Library Name set to work Click OK If you see the Select Initial Ini dialog asking which modelsim ini file you would like the project to be created from click the Use Default Ini button Figure 14 The Create Project dialog Create Project B m Project Name test I m Project Location C modeltech examples Browse m Default Library Name work Creating a new project T 33 2b 2c 2d ModelSim SE Tutorial T 34 Lesson 3 ModelSim projects Adding objects to the project Once you click OK to accept the new project settings you will see a blank Project tab in the workspace area of the Main window and the Add items to the Project dialog will appear Figure 15 From this dialog you can create a new design file
18. 3 Runthe comparison 4 View the comparison results In this exercise you will run and save a simulation edit one of the source files run the simulation again and finally compare the two runs Design files for this lesson The sample design for this lesson consists of a finite state machine which controls a behavioral memory The testbench fest sm provides stimulus The ModelSim installation comes with Verilog and VHDL versions of this design The files are located in the following directories Verilog install dir modeltech examples compare verilog VHDL install dir modeltech examples compare vhdl This lesson uses the Verilog version in the examples If you have a VHDL license use the VHDL version instead When necessary we distinguish between the Verilog and VHDL versions of the design Related reading Waveform Compare UM 271 Chapter 8 WLF files datasets and virtuals UM 225 ModelSim SE Tutorial Creating the reference dataset The reference dataset is the wi f file that the test dataset will be compared against It can be a saved dataset the current simulation dataset or any part of the current simulation dataset In this exercise you will use a DO file to create the reference dataset 1 Create a new directory and copy the tutorial files into it Start by creating a new directory for this exercise in case other users will be working with these lessons Create the directory and copy all files
19. Exploring the physical connectivity of your design Viewing and initializing memories Analyzing simulation performance Testing code coverage Comparing waveforms ModelSim SE Tutorial T 18 Lesson 1 ModelSim conceptual overview ModelSim SE Tutorial Lesson 2 Basic simulation Topics The following topics are covered in this lesson Introduction Design files for this lesson Related reading Creating the working design library Compiling the design Loading the design into the simulator Running the simulation Setting breakpoints and stepping in the Source window Lesson wrap up T 20 T 20 T 20 1 21 T 23 T 24 T 25 1 27 T 29 T 19 ModelSim SE Tutorial T 20 Lesson 2 Basic simulation Introduction In this lesson you will go step by step through the basic simulation flow Design files for this lesson The sample design for this lesson is a simple 8 bit binary up counter with an associated testbench The pathnames are as follows Verilog lt install_dir gt modeltech examples counter v and tcounter v VHDL lt install_dir gt modeltech examples counter vhd and tcounter vhd This lesson uses the Verilog files counter v and tcounter v in the examples If you have a VHDL license use counter vhd and tcounter vhd instead Or if you have a mixed license feel free to use the Verilog testbench with the VHDL counter or vice versa Related reading ModelSim User s Manual
20. Fe d Select Tools gt Waveform Compare gt Reload My mde veim wif D t Since you saved the data using default file names the dialog should pen already have the correct files specified Figure 135 Deskt e Click OK The comparison reloads You can drag comparison object to the e Wave or List window to view the differences again My Documents lt My Computer E LT Filename Places x Files of type EEE 3b Figure 135 Reloading saved comparison data Reload and Redisplay Compare Differences OI x Waveform Rules file name compare ru Browse Waveform Difference file name compare di Browse ModelSim SE Tutorial Lesson wrap up This concludes this lesson Before continuing we need to end the current simulation and close the gold wif dataset 1 Type quit sim at the VSIM gt prompt 2 dataset close gold at the ModelSim gt prompt Lesson wrap up T 155 ModelSim SE Tutorial T 156 Lesson 13 Waveform Compare ModelSim SE Tutorial Lesson 14 Automating ModelSim Topics The following topics are covered in this lesson Introduction Related reading Creating a simple DO file Running ModelSim in command line mode Using Tcl with ModelSim Lesson Wrap up T 158 T 158 T 159 T 161 T 164 T 166 T 157 ModelSim SE Tutorial T 158 Lesson 14 Automating ModelSim Introductio
21. HA Creating the working library Compiling your design Running the simulation Debugging your results Project flow Multiple library flow Debugging tools T 12 T 13 T 13 T 13 T 13 T 14 T 15 T 16 T 17 ModelSim SE Tutorial T 12 Lesson 1 ModelSim conceptual overview Introduction ModelSim is a simulation and debugging tool for VHDL Verilog SystemC and mixed language designs This lesson provides a brief conceptual overview of the ModelSim simulation environment It is divided into four topics which you will learn more about in subsequent lessons Topic Additional information and practice Basic simulation flow Lesson 2 Basic simulation Project flow Lesson 3 ModelSim projects Multiple library flow Lesson 4 Working with multiple libraries Debugging tools Remaining lessons ModelSim SE Tutorial Basic simulation flow T 13 Basic simulation flow The following diagram shows the basic steps for simulating a design in ModelSim Creating the working library In ModelSim all designs be they VHDL Verilog SystemC or some combination thereof are compiled into a library You typically start a new simulation in ModelSim by creating a working library called work Work is the library name used by the compiler as the default destination for compiled design units Compiling your design After creating the working library you compile your design units into it The ModelSi
22. Increment f Inthe Fill Data field set the seed value of 0 for the incrementing data C Decrement Skip 0 word s g Click OK Random s h View the data near address 250 by double clicking on any address in the OK pm Address column and entering 250 ES You can see the specified range of addresses overwritten with the new data Also Figure 90 Overwritten values in memory instance you can see the incrementing data beginning at address 251 Figure 90 Now before you leave this section go ahead and clear the instances already being E ram_tb spram3 mem viewed 246 00000000000000000010010000011110 247 00000000000000000010010000011111 248 00000000000000000010010000100000 4 Right click somewhere in the mem 2 pane and select Close All 249 00000000000000000010010000100001 250 00000000000000000010010000100010 251 00000000000000000000000000000000 252 00000000000000000000000000000001 253 00000000000000000000000000000010 254 00000000000000000000000000000011 255 00000000000000000000000000000100 256 00000000000000000000000000000101 257 00000000000000000000000000000110 258 00000000000000000000000000000111 259 00000000000000000000000000001000 nen mnnnnnanmnmnananmnmnmaunnnaununnnamnnnnmnna4nmnmnna4 LL 4 ModelSim SE Tutorial Interactive debugging commands The memory panes can also be used interactively for a variety of debugging purposes The features described in this section are useful for this purpose
23. MDI frame with line 105 displayed Figure 100 VHDL Double click test_sm vhd 203 The Source window opens in the MDI frame with line 203 displayed ModelSim SE Tutorial Figure 99 Expand the hierarchical function call tree Figure 100 The Source window showing a line from the profile data 39 100 16 53 33 80 10 46 100 5 mam Underfraw Infraw Unde inc 4 Tcl Flush 37 0 204 0 096 L Tcl Close 37 36 204 19 9 Tcl DoOneEvent 15 1 8 396 0 6 F Tcl_WaitForEvent 8 8 4 4 4 4 Tcl DeleteTimerHand 5 1 2 896 0 6 L Tcl GetTime 4 4 2 296 2 296 EF smx 73 13 6 7 296 3 3 E Tcl Flush B 0 33 0 0 L Tcl Close B B 3 396 3 396 test sm v 82 7 Fi 3 9 3 9 z Ranked Call Tree Structural 102 always posedge clk 103 outof 5 out wire put output in register 104 105 always outof any change of outof 106 display tine GueGEy een outof 107 108 integer i js 109 110 111 112 tests xj m sm v 4 View Profile Details The Profile Details pane increases visibility into simulation performance Right clicking any function in the Ranked or Call Tree views opens a popup menu that includes a Function Usage selection When you select Function Usage the Profile Details pane opens and displays all instances that use the selected function 1 View the Profile Details of a function in the Call Tree view a Right click the Tc
24. ModelSim Quick Guide command and feature quick reference paper shipped with ModelSim PDF select Help gt Documentation also available from the Support page of our web site www model com ModelSim Tutorial PDF HTML select Help gt Documentation also available from the Support page of our web site www model com ModelSim User s Manual PDF HTML select Help gt Documentation ModelSim Command Reference PDF HTML select Help gt Documentation ModelSim GUI Reference PDF HTML select Help gt Documentation Foreign Language Interface Reference PDF HTML select Help gt Documentation Std_DevelopersKit User s Manual PDF www model com support documentation BOOK sdk_um pdf The Standard Developer s Kit is for use with Mentor Graphics QuickHDL Command Help type help command name at the prompt in the Transcript pane Error message help type verror lt msgNum gt at the Transcript or shell prompt Tcl Man Pages Tcl manual select Help gt Tcl Man Pages or find contents htm in nodeltech docs tcl_help_html Technotes select Technotes dropdown on www model com support ModelSim SE Tutorial T 8 Introduction Technical support and updates Support Model Technology online and email technical support options maintenance renewal and links to international support contacts www model com support default asp
25. Transcript tt Loading work cout Save List view 4 test_counter clk test_counter reset EA test_counter count 0000000000000 TA 4 ih tcounter v gaa wave ModelSim SE Tutorial T 26 Lesson 2 Basic simulation c Click the Run All icon on the Main or Wave window toolbar The simulation continues running until you execute a break command or it hits a statement in your code e g a Verilog stop statement that halts the simulation d Click the Break icon The simulation stops running ModelSim SE Tutorial Setting breakpoints and stepping in the Source window Next you will take a brief look at one interactive debugging feature of the ModelSim environment You will set a breakpoint in the Source window run the simulation and then step through the design under test Breakpoints can be set only on lines with red line numbers 1 Open counter v in the Source window a Select the Files tab in the Main window Workspace b Double click counter v to add it to the Source window 2 Setabreakpoint on line 36 of counter v if you are simulating the VHDL files use line 39 instead a Scroll to line 36 and click on the line number A red ball appears next to the line Figure 10 indicating that a breakpoint has been set 3 Disable enable and delete the breakpoint a Click the red ball to disable the breakpoint It will become a black circle b Click the black circle to re enable the b
26. add an existing file add a folder for organization purposes or create a simulation configuration discussed below 1 Add two existing files a Click Add Existing File This opens the Add file to Project dialog Figure 16 This dialog lets you browse to find files specify the file type specify which folder to add the file to and identify whether to leave the file in its current location or to copy it to the project directory b Click Browse c Open the examples directory in your ModelSim installation tree d Verilog Select counter v hold the Ctrl key down and then select tcounter v VHDL Select counter vhd hold the lt Ctrl gt key down and then select tcounter vhd e Click Open and then OK f Click Close to dismiss the Add items to the Project dialog ModelSim SE Tutorial Figure 15 Adding new items to a project ModelSim File Edit View Format Compile Simulate Add Tools Window Help 0288 22 A8 8 m Ep Add items to the Project Ax m Click on the icon to add items of that type ms Create New File ModelSim gt M Create Simulation Add Existing File Create New Folder Project test lt No Design Loaded gt lt No Context gt Figure 16 The Add file to Project dialog y Add file to Project Fila Nae corsa nec evan Wo NE RI OOO 1b counter vfcounter v B
27. lexpected 151 dataerror write var dataerror newval 152 153 if reset read 0 154 g 155 storage write 0 156 expected write 0 157 actual write 0 EXIIT nu B M ES SSSR a 1 test ringbuf h KE Figure 43 Simulation stopped at the breakpoint test_ringbuf h 139 if var pseudo newval 19 var pseudo 19 140 txda write var pseudo newval 19 145 py 146 On every negedge of the clock compare actual and expe 147 148 inline void test ringbuf compare data 149 1506 bool var dataerror newval actual lexpected 151 dataerror write var dataerror newval 152 153 if reset read 0 r FE RSR H C test rinabuf h ModelSim SE Tutorial T 62 Lesson 5 Simulating designs with SystemC b Click the Step icon on the Source window toolbar This steps the simulation to the next statement Because the next statement is a function call ModelSim steps into the function which is in a separate file Figure 44 c Click the Continue Run icon on the Source window toolbar The breakpoint in test ringbuf h is hit again Examining SystemC objects and variables To examine the value of a SystemC object or variable you can use the examine command or view the value in the Objects window 1 View the value and type of an sc signal a Typeshow at the CDBG prompt to display a list of all the objects in the design includ
28. memories in the current design context ram_tb with the range depth and width of each memory VHDL The radix for enumerated types is Symbolic To change the radix to binary for the purposes of this lesson type the following command at the vsim prompt VSIM gt radix bin Double click the ram_tb spraml mem instance in the memories list to view its contents A mem tab is created in the MDI frame to display the memory contents The data are all X 0 in VHDL since you have not yet simulated the design The first column blue hex characters lists the addresses Figure 79 and the remaining columns show the data values Double click instance ram_tb spram2 mem in the Memories tab of the Workspace This creates a new tab in the MDI frame called mem 1 that contains the addresses and data for the spram2 instance Each time you double click a new memory instance in the Workspace a new tab is created for that instance in the MDI frame ModelSim SE Tutorial Figure 78 Viewing the memories tab in the Main window workspace Workspace M ram_tb sprami mem 4095 M ftam_tb spram2 mem 0 2047 M ram_tb spram3 mem 0 65535 E M ram_tb spramd mem 0 3 M ram_tb dprami mem 0 15 4096 2048 65536 4 16 ES Memories capa Figure 79 The mem tab in the MDI pane shows instance ram tb spram1 mem zi ram tb spram1 mem 00000000 00000006 0000000c 00000012 00000018 0000001e 0000
29. 2 2 2 2 sm vi73 13 6 Tuz 3 3 calltree rpt ModelSim SE Tutorial T 122 Lesson 10 Analyzing performance with the Profiler Lesson wrap up This concludes this lesson Before continuing we need to end the current simulation 1 Select Simulate gt End Simulation Click Yes ModelSim SE Tutorial Lesson 11 Simulating with Code Coverage Topics The following topics are covered in this lesson Introduction Design files for this lesson Related reading Compiling the design Loading and running the design Viewing statistics in the Main window Viewing statistics in the Source window Viewing toggle statistics in the Objects pane Excluding lines and files from coverage statistics Creating Code Coverage reports Lesson wrap up D Note The functionality described in this tutorial requires a coverage license feature in your ModelSim license file Please contact your Mentor Graphics sales representative if you currently do not have such a feature T 124 T 124 T 124 T 125 T 126 T 127 T 129 T 131 T 132 T 132 T 134 T 123 ModelSim SE Tutorial T 124 Lesson 11 Simulating with Code Coverage Introduction ModelSim Code Coverage gives you graphical and report file feedback on which executable statements branches conditions and expressions in your source code have been executed It also measures bits of logic that have been toggled during execution Design fil
30. 510 T 81 Ons to 1522 ns Now Ons Delta 0 y ModelSim SE Tutorial T 82 Lesson 7 Creating stimulus with Waveform Editor 3 Delete an edge Figure 63 Deleting an edge on signal clk a Click signal clk just to the right of the transition at 400 ns M wave default 04 nl xl i File Edit View Insert Format Tools Window The cursor should snap to 400 ns gt Ed Fa Tey ip b Click the Delete Edge icon sue JELLE SATS Ha counter clk 4 Edit counter reset 510 The edge is deleted and c k now stays high until 500 ns Figure 63 4 Undo and redo an edit a Click the Wave Undo icon ll xi Ons to 1522 ns Now Ons Delta 0 The deleted edge reappears b Click the Wave Redo icon The edge is deleted again You can undo and redo any number of editing operations except extending all waves and changing drive types Those two edits cannot be undone ModelSim SE Tutorial Saving and reusing the wave commands You can save the commands that ModelSim used to create the waveforms You can load this format file at a later time to re create the waves In this exercise we will save the commands quit and reload the simulation and then open the format file 1 Save the wave commands to a format file a Select File gt Close in the Wave window and you will be prompted to save the wave commands Click Yes Type waveedit do in the File name field and then cli
31. Chapter 3 Design libraries UM 57 Chapter 5 Verilog simulation UM 111 Chapter 4 VHDL simulation UM 71 ModelSim Command Reference vlib CR 360 vmap CR 374 vlog CR 362 vcom CR 314 right CR 252 vopt CR 375 and view CR 336 commands ModelSim SE Tutorial Creating the working design library Before you can simulate a design you must first create a library and compile the source code into that library 1 Create a new directory and copy the tutorial files into it Start by creating a new directory for this exercise in case other users will be working with these lessons Verilog Copy counter v and tcounter v files from lt install_dir gt examples to the new directory VHDL Copy counter vhd and tcounter vhd files from lt install_dir gt examples to the new directory 2 Start ModelSim if necessary a vsim at a UNIX shell prompt or use the ModelSim icon in Windows Upon opening ModelSim for the first time you will see the Welcome to ModelSim dialog Figure 1 Click Close b Select File gt Change Directory and change to the directory you created in step 1 3 Create the working library a Select File gt New gt Library This opens a dialog where you specify physical and logical names for the library Figure 2 You can create a new library or map to an existing library We ll be doing the former b Type work in the Library Name field if it isn t entered automatically Creat
32. Create Wave 0 b Select Constant for the pattern type and click Next c Enter 0 for the Value and click Finish _ lt Previous Finish Cancel A second generated waveform appears in the Wave window You may want to undock the Wave window Figure 58 The created waveform LT um File Edit View Insert Format Tools Window msi QQ ame ns to 1 us Now ns Delta 0 S ModelSim SE Tutorial T 80 Lesson 7 Creating stimulus with Waveform Editor Editing waveforms in the Wave window Waveform Editor gives you numerous commands for interactively editing waveforms e g invert mirror stretch edge cut paste etc You can access these commands via the menus toolbar buttons or via keyboard and mouse shortcuts You will try out several commands in this part of the exercise 1 Inserta pulse on signal reset a Click the Edit Mode icon on the Wave window toolbar b Click signal reset so it is selected c Inthe waveform pane right click on signal reset and select Edit Wave gt Insert Pulse d Insert Pulse dialog enter 100 for duration and 100 for time Figure 59 and click OK Signal reset now goes high from 100 ns to 200 ns Figure 62 ModelSim SE Tutorial Figure 59 The Insert Pulse dialog M Insert Pulse x Signal Name Edit counter reset Duration Time Time Unit po fa fs wi Figure 60 Signal reset with an inserted pulse
33. Files tab and a green square circle or diamond icon NO Library elsewhere Module Module E Module View Workspace and objects ScModue a Click on the Library tab in the Workspace pane of the Main window Module L ScModule SystemC objects have a green S next to their names Figure 40 i Library Library 2 Observe window linkages im i Library 5 Librar a Click on the sim tab in the Workspace pane of the Main window b Select the clock instance in the sim tab Figure 41 The Objects window updates to show the associated SystemC or HDL objects 3 Add objects to the Wave window a Right click test_ringbuf in the sim pane of the Workspace and select Add gt Add to Wave lest ringbuf ScModule sc_clock ScModule 2 ringbuf Module m_negedge_time test ringbuf ScMethod gt data test_ringbuf ScMethod m_start_time m_duty_cycle 3 test ringbuf ScMethod print error lest ringbuf ScMethod m period print restore test ringbuf ScMethod Active Processes Ready IMPLICIT WIRE outstrobe 28 Ready HIMPLICIT wIRE oeenable t27 Ready IMPLICIT WIRE ramadrs 26 gt Ready HASSIGNHES test ringbuf ring Ready SIMPLICIT wIRE buffer H23 Readu HASSIGNI3S test rinabuf rina ModelSim SE Tutorial Setting breakpoints and stepping in the Source window As with HDL files you can set breakpoints and step
34. ModelSim 2 View statistics in the Missed Coverage pane a Select different files from the Files tab of the Workspace The Missed Coverage pane updates to show statistics for the selected file Figure 110 Select any entry in the Statement tab to display that line in the Source window Viewing statistics in the Main window T 127 Figure 109 Right click a column heading to hide or show columns Stmt Stmt Graph B 21 20 95238 DD 28 25 89 285 ARN 9 8 90000 SEX 81 73 90 123 NE Transcript 998855 outof 000000 998915 outof 000000bb 998975 outof 000000cc 999035 000000 999095 outof 000000ce 999111 illegal op received 999155 outof 000000cf 9994955 NNNNNNaa HHHHHHHH Fullpath Type v Stmt Count w Stmt Hits Stmt w Stmt Graph v Branch Count v Branch Hits v Branch w Branch Graph Condition Count Branch Graph 13 92657 SN 17 85000 SN 67500 NN w Condition Hits v Condition 2 w Condition Graph Expression Count w Expression Hits w Expression w Expression Graph Figure 110 Statement statistics in the Missed Coverage pane ES RER n_state n_state n_state CTRL IDLE IDLE Statement Condition Toggle 45 Branch Condtion Expression Toggle a ModelSim SE Tutorial T 128 Lesson 11 Simulating with Code Coverag
35. _Close function and select Function Usage from the popup menu The Profile Details pane displays all instances using function Tcl_Close Figure 101 The statistical performance data show how much simulation time is used by Tcl Close in each instance When you right click a selected function or instance in the Structural pane the popup menu displays either a Function Usage selection or an Instance Usage selection depending on the object selected 2 View the Profile Details of an instance in the Structural view a b C Select the Structural tab to change to the Structural view Right click test_sm and select Expand All from the popup menu Verilog Right click the sm_0 instance and select Instance Usage from the popup menu The Profile Details shows all instances with the same definition as test_sm sm_seqO sm_0 Figure 102 VHDL Right click the dut instance and select Instance Usage from the popup menu The Profile Details shows all instances with the same definition as test_sm dut View Profile Details T 119 Figure 101 Profile Details of function Tcl Close Profile Details Instances using function Tcl_Close Name Under raw Infraw Under In M test sm 37 36 20 4 19 9 M test sm sm seq sm 7 3 9 3 9 Figure 102 Profile Details of instance sm_0 Profile Details Instances with same definition as test_sm sm_seq0 sm_O Name Underfraw In ravi Under In M tes
36. a directory for the library lists it in the Library tab of the Workspace and modifies the modelsim ini file to record this new library for the future Creating the resource library T 43 Figure 29 Creating the new resource library Create a New Library E bj Create C a map to an existing library a new library and a logical mapping to it Library Name parts lit m Library Physical Name parts_lib OK Cancel ModelSim SE Tutorial T 44 Lesson 4 Working with multiple libraries 5 Compile the counter into the resource library a Click the Compile icon on the Main window toolbar b Selectthe parts lib library from the Library list Figure 30 c Double click counter v to compile it d Click Done You now have a resource library containing a compiled version of the counter design unit 6 Change to the testbench directory a Select File gt Change Directory and change to the testbench directory you created in step 2 ModelSim SE Tutorial Figure 30 Compiling into the resource library 2x Library parts ib 5b Look in CD resource library 6 er ES File name counter v Files of type HDL Files vhd vhdl vho hdl v Y Done Default Options Edit Source Creating the project Now you will create a project that contains fcounter v the counter s testbench 1 Create the project a b c
37. a text file LIM o File Edit Window E compare tst Total signals compared 11 Total primary differences 6 Total secondary differences 6 Number of primary signals with differences 4 Diff number 1 From time 135 ns delta 0 to time 155 ns gold test sm into 00000000000000000000000010101010 sim test sm into 00000000000000000000000010101011 Diff number 2 From time 135 ns delta O to time 155 ns gold test sm into 0 0 sim test sm into 0 1 Diff number 3 From time 171 ns delta 1 to time 191 ns gold test_sm dat 00000000000000000000000010101010 sim test_sm dat 00000000000000000000000010101011 Diff number 4 From time 171 ns delta 1 to time 191 ns gold test sm dat 0 560 sim test sm dat O St1 Diff number 5 From time 409 ns delta 1 to time 411 ns gold test sm dat 00000000000000000000000010101010 sim test sm dat 00000000000000000000000010101011 Diff number 6 From time 409 ns delta 1 to time 411 ns gold test sm dat 0 860 sim test sm dat O St1 Diff number 7 From time 431 ns delta 1 to time 491 ns delta wnli jenne awlane wien nnnnnnnnnnnnnnnnnnnnnnnnsnin304n T 153 ModelSim SE Tutorial T 154 Lesson 13 Waveform Compare 3 Reload the comparison data Figure 134 Displaying log files in the Open dialog a Select File gt Open and open Open File RTE b Change the Files of Type to Log Files wlf Look in C3 veriog e e Double click gold wif to open the dataset
38. be found for instantiation It also tells you that the original error message should list which libraries ModelSim searched In this case the original message says ModelSim searched only work 1 Simulate a VHDL design with a missing resource library a In the Library tab click the icon next to the work library and double click test counter The Main window Transcript reports a warning Figure 32 When you see a message that contains text like Warning vsim 3473 you can view more detail by using the verror command Type verror 3473 at the ModelSim prompt The expanded error message tells you that a component dut in this case has not been explicitly bound and no default binding can be found Type quit sim to quit the simulation ModelSim SE Tutorial Figure 31 Verilog simulation error reported in the Main window Transcript Top level modules H counter cd C 6 0 Tutorial testbench Loading project counter Compile of tcounter v was successful ModelSim gt vsim work test_counter vsim work test counter Loading work test counter Error vsim 3033 C 6 0 Tutorial testbench tcounter v 9 Instantiation of counter failed The design unit was not found Region test_counter Searched libraries work Error loading design ModelSim gt Figure 32 VHDL simulation warning reported in Main window Transcript cd C 6 0 Tutorial testben
39. click anywhere in the Memory Contents pane and select Properties The Properties dialog box opens Figure 81 b Forthe Address Radix select Decimal This changes the radix for the addresses only c Select Words per line and type 1 in the field d Click OK You can see the results of the settings in Figure 82 If the figure doesn t match what you have in your ModelSim session check to make sure you set the Address Radix rather than the Data Radix Data Radix should still be set to Symbolic the default Viewing a memory T 103 Figure 80 Memory display updates with simulation 00000000 00000006 0000000c 00000012 00000018 0000001e 00000024 0000002 00000030 00000036 0000003c 00000042 00000048 manana 4 mem f mem 1 ram m1 mem 00101000 00101110 00110100 00111010 01000000 01000110 01001100 01010010 01011000 01011110 01100100 01101010 01110000 111361310 00101001 00101010 00101111 00110000 00110101 00110110 00111011 00111100 01000001 01000010 01000111 01001000 01001101 01001110 01010011 01010100 01011001 01011010 01011111 01100000 01100101 01100110 01101011 01101100 01110001 01110010 11336335357 Figure 81 Changing the address radix BITTCEREEESNSS Address Radis Hexadecimal Decimal c r r r Data Radix Symbolic Binary Octal Decimal Unsigned Hexadecimal 00101011 00110001 00110111 00111101 01000011 010010
40. e g vsim vlib vlog etc are actually stand alone executables that can be invoked at the system command prompt Additionally you can create a DO file that contains other ModelSim commands and specify that file when you invoke the simulator 1 Create a new directory and copy the tutorial files into it Start by creating a new directory for this exercise Create the directory and copy these files into it lt install_dir gt modeltech examples counter v e lt install_dir gt modeltech examples stim do We have used the Verilog file counter v in this example If you have a VHDL license use counter vhd instead 2 Create a new design library and compile the source file Again enter these commands at a DOS UNIX prompt in the new directory you created in step 1 a Type vlib work at the DOS UNIX prompt b For Verilog type vlog counter v at the DOS UNIX prompt For VHDL type vcom counter vhd Running ModelSim in command line mode T 161 ModelSim SE Tutorial T 162 3 Lesson 14 Automating ModelSim Create a DO file a b Open a text editor Type the following lines into a new file list all signals in decimal format add list decimal read in stimulus do stim do output results write list counter lst quit the simulation quit f Save the file with the name sim do and place it in the current directory 4 Run the batch mode simulation 5 a Type vsim c do sim do counter wlf
41. free to open the DO file and look at its contents Compiling and loading the design T 91 ModelSim SE Tutorial T 92 Lesson 8 Debugging with the Dataflow window Exploring connectivity A primary use of the Dataflow window is exploring the physical connectivity of your design You do this by expanding the view from process to process This allows you to see the drivers receivers of a particular signal net or register 1 Add a signal to the Dataflow window a Make sure instance is selected in the sim tab of the Workspace pane b Drag signal strb from the Objects pane to the Dataflow window Figure 68 2 Explore the design a Double click the net highlighted in red The view expands to display the processes that are connected to strb Figure 69 b Selectsignal test on process NAND 50 labeled line_71 in the VHDL version and click the Expand net to all drivers icon Notice that after the display expands the signal line for strb is highlighted in green This highlighting indicates the path you have traversed in the design Select signal oen on process ALWAYS 55 labeled line 84 in the VHDL version and click the Expand net to all readers 4t icon Continue exploring if you wish When you are done click the Erase All icon F ModelSim SE Tutorial Figure 68 A signal in the Dataflow window ZT Lox File Edit View Navigate Trace Tools Window Silk m 4i X BMD dA Je e 9 Hee 3 9 2 6 am
42. from lt install_dir gt modeltech examples compare verilog to the new directory If you have a VHDL license copy the files in lt install_dir gt modeltech examples compare vhdl instead 2 Start ModelSim and change to the exercise directory If you just finished the previous lesson ModelSim should already be running If not start ModelSim a Type vsim at a UNIX shell prompt or use the ModelSim icon in Windows If the Welcome to ModelSim dialog appears click Close b Select File gt Change Directory and change to the directory you created in step 1 3 Execute the lesson DO file a Typedo gold sim do at the ModelSim prompt The DO file does the following e Creates and maps the work library Compiles the Verilog and VHDL files e Runs the simulation and saves the results to a dataset named gold wif Quits the simulation Feel free to open the DO file and look at its contents Creating the reference dataset T 147 ModelSim SE Tutorial T 148 Lesson 13 Waveform Compare Creating the test dataset The test dataset is the w f file that will be compared against the reference dataset Like the reference dataset the test dataset can be a saved dataset the current simulation dataset or any part of the current simulation dataset To simplify matters you will create the test dataset from the simulation you just ran However you will edit the testbench to create differences between the two runs Verilog 1 Edit t
43. have not toggled Instance Coverage Displays statement branch condition expression and toggle coverage statistics for each instance in a flat non hierarchical view Details Shows details of missed coverage such as truth tables or toggle details Another coverage related pane is the Current Exclusions pane Select View gt Code Coverage gt Current Exclusions to display that pane Current Exclusions Lists all files and lines that are excluded from coverage statistics see Excluding lines and files from coverage statistics T 132 for more information These panes can be re sized rearranged and undocked to make the data more easily viewable To resize a pane click and drag on the top or bottom border To move a pane click and drag on the double line to the right of the pane name To undock a pane you can select it then drag it out of the Main window or you can click the Dock Undock Pane button in the header bar top right To redock the pane click the Dock Undock Pane button again We will look at these panes more closely in the next exercise For complete details on each pane see Code coverage panes GR 121 ModelSim SE Tutorial pensis 107 Coverage columns in the Main window Workspace t ETT 3 92857 28 25 83206 DS 20 17 500 9 90000 DST 8 7 67 500 RN 81 73 90 123 NE X 31 PE Details gd x X 31 into 4 b0001 28 b0 Instance fte
44. line of the property is defined on line 18 The key part of the refresh protocol is that we_n must be held high write enable not active for the entire refresh cycle VHDL The current line arrow points to the failed assertion on line 24 of the dram cntrl psl file The refresh_sequence second line of the property is defined on line 20 2 Check the Wave window to see if we n was held high through both REF and states a Expand assert_check_refresh to reveal all signals referenced by the assertion Zoom and scroll the Wave window so you can see we_n and mem_state Figure 124 It is easy to see that we n is high only during the REF state It is low during REF2 Let s examine we_n further Debugging the assertion failure T 141 Figure 123 Source code for failed assertion Ih modeltech examples psl verilog dram cntrl psl 19 20 property check refresh always rose reft 21 state IDLE 0 14 22 abort fellireset n 23 24 5 assert check_refresh 25 26 declare refresh rate check 27 sequence signal refresh 24 rose refr 28 property refresh rate always rose reset 29 signal r 30 EE PSS dramcon_sim v wave ih dram cntrl psl Figure 124 Examining we_n with respect to mem_state m default Assertions asset test read resp asser test write resp assert check as asser check refresh 4 check refresh refresh mem s
45. modules test_ringbuf Type sccom link at the ModelSim gt prompt to perform the final link on the SystemC objects ModelSim SE Tutorial Figure 37 ringbuf h include systemc h class ringbuf public sc_foreign_module public Sc in bool clock sc in bool reset sc in bool txda Sc out bool rxda Sc out bool txc Sc out bool outstrobe ringbuf sc module name nm const char hdl name int num generics const char generic list Sc foreign module nm hdl name num generics clock clock reset reset txda txda rxda rxda outstrobe ringbuf Figure 38 test_ringbuf cpp file test_ringbuf cpp Copyright Model Technology a Mentor Graphics Corporation company 2004 All rights reserved include test_ringbuf h include lt iostream gt SC_MODULE_EXPORT test_ringbuf generic_list Load the design a Click on the Library tab in the Workspace pane of the Main window b Click the icon next to the work library c Double click the test_ringbuf design unit The equivalent command line entry is vsim test_ringbuf entered at the ModelSim gt prompt If necessary you may close the Locals Profile and Watch panes of the main window Make sure the Objects and Active Processes windows are open as shown in Figure 39 To open or close these windows select View gt Debug Windows Mixed SystemC and HD
46. or disclose such information as necessary to enforce its rights under this Agreement CONTROLLING LAW AND JURISDICTION THIS AGREEMENT SHALL BE GOVERNED BY AND CONSTRUED UNDER THE LAWS OF THE STATE OF OREGON USA IF YOU ARE LOCATED IN NORTH OR SOUTH AMERICA AND THE LAWS OF IRELAND IF YOU ARE LOCATED OUTSIDE OF NORTH AND SOUTH AMERICA All disputes ModelSim SE Tutorial 16 17 arising out of or in relation to this Agreement shall be submitted to the exclusive jurisdiction of Dublin Ireland when the laws of Ireland apply or Wilsonville Oregon when the laws of Oregon apply This section shall not restrict Mentor Graphics right to bring an action against you in the jurisdiction where your place of business is located The United Nations Convention on Contracts for the International Sale of Goods does not apply to this Agreement SEVERABILITY If any provision of this Agreement is held by a court of competent jurisdiction to be void invalid unenforceable or illegal such provision shall be severed from this Agreement and the remaining provisions will remain in full force and effect PAYMENT TERMS AND MISCELLANEOUS You will pay amounts invoiced in the currency specified on the applicable invoice within 30 days from the date of such invoice This Agreement contains the parties entire understanding relating to its subject matter and supersedes all prior or contemporaneous agreements including but not limited to any purchase order term
47. s Resolution navigate within the hierarchy by clicking on any line with a expand Jwork test_counter i or contract icon You will also see a tab named Files that displays ae all files included in the design Deer Enable optimization Optimization Options OK Cancel_ Figure 7 Workspace tab showing a Verilog design x ModelSim File Edit View Format Compile Simulate Add Tools Window Help Workspace rinstance Design unit Design unit type EM test counter test counter Module M dut counter Module IMPLICI test counter Process Top level modules SIMPLICI test counter Process test counter ModelSim gt vsim work test counter INITIAL test counter Process vsim work test counter OSINITIAL test counter Process Loading work test counter HINITIAL test counter Process f Loading work counter Library sim Files VSIM 19 gt Now 0 ns Delta 0 sim test_counter af 6 0 Beta Compiler 2004 06 Jun 4 2004 Compiling module counter Compiling module test_counter ModelSim SE Tutorial Running the simulation Now you will run the simulation 1 Set the graphic user interface to view all debugging windows a Select View gt Debug Windows gt All Windows This opens all ModelSim windows giving you different views of your design data and a variety of debugging tools Most windows will op
48. the Under column You can click the heading of any column to sort data by that column The Tcl_ entries are functions that are part of the internal simulation code They are not directly related to your HDL code Running the simulation T 117 ModelSim SE Tutorial T 118 Lesson 10 Analyzing performance with the Profiler Click the Call Tree tab to view the profile data in a hierarchical function call tree display The results differ between the Verilog and VHDL versions of the design In Verilog line 105 test_sm v 105 is taking the majority of simulation time In VHDL test_sm vhd 203 and sm vhd 93 are taking the majority of the time gt Note Your results may look slightly different as a result of the computer you re using and different system calls that occur during the simulation Also the line number reported may be one or two lines off the actual source file This happens due to how the stacktrace is decoded on different platforms Verilog Right click test_sm v 105 and select Expand All from the popup menu This expands the hierarchy of test_sm v 105 and displays the functions that call it Figure 99 VHDL Right click test_sm vhd 203 and select Expand All from the popup menu This expands the hierarchy of test_sm vhd 203 and displays the functions that call it 4 View the source code of a line that is using a lot of simulation time a Verilog Double click test_sm v 105 The Source window opens in the
49. the Wave window 2 Lock cursor B Figure 54 A locked cursor in the Wave window a Right click cursor B in the cursor pane and select Lock B Tiwave default 1 File Edit View Insert Format Tools Window The cursor color changes to red and you can no longer drag the cursor Figure 54 SUSE seen le Nasal SE GF GG 4 jest counter clk a Right click cursor B and select Delete B 4 RESTE 3 Delete cursor MT EEE EE TEE ee x z y T3 D ns to 420 ns Now 400 ns Delta 2 ModelSim SE Tutorial Saving the window format If you close the Wave window any configurations you made to the window e g signals added cursors set etc are discarded However you can use the Save Format command to capture the current Wave window display and signal preferences to a DO file You open the DO file later to recreate the Wave window as it appeared when the file was created Format files are design specific use them only with the design you were simulating when they were created 1 Save a format file a b In the Wave window select File gt Save gt Format Leave the file name set to wave do and click OK Close the Wave window 2 Load a format file a b In the Main window select View gt Debug Windows gt Wave Undock the window All signals and cursor s that you had set are gone In the Wave window select File gt Lo
50. 00000 999555 outof 000000bb 999615 outof 000000 999675 outof 000000cd 999735 outof 000000 999751 illegal op received HHHHHHHHH Profiling paused VSIM 4 gt Now 1ms Delta 2 Profile Samples 181 Samples 181 Figure 98 The Profile window Profile Under 2 Tcl Close 44 43 24 396 23 896 test sm v 105 94 41 51 996 22 796 Tcl WaitFarEvent 8 8 4 496 4 4 test_sm v 92 rd 3 9 3 9 sm v 73 Ti 6 7 2 3 3 Tcl GetTime 4 2 296 2 296 beh sram v 22 4 4 2 296 2 296 Click here to hide or display columns Column Description Under he ratio as a percentage of the samples collected during the execution of a function and all support routines under that function to the total number of samples collected or the ratio of the samples collected during an instance including all instances beneath it in the structural hierarchy to the total number of samples collected In the ratio as a percentage of the total samples collected during a function or instance Parent not in the Ranked view the ratio as a percentage of the samples collected during the execution of a function or instance to the samples collected in the parent function or instance Data in the Ranked view is sorted by default from highest to lowest percentage in the In column In the Call Tree and Structural views data is sorted by default according to
51. 0000000 00100000000000000000000000000000 0000 0 00100000000000000000000000000000 00100000000000000000000000000000 0000 1 00100000000000000000000000000000 00100000000000000000000000000000 0000 QE Saving and reloading comparison data You can save comparison data for later viewing either in a text file or in files that can be reloaded into ModelSim To save comparison data so it can be reloaded into ModelSim you must save two files First you save the computed differences to one file next you save the comparison configuration rules to a separate file When you reload the data you must have the reference dataset open 1 Save the comparison data to a text file a Inthe Main window select Tools gt Waveform Compare gt Differences gt Write Report b Click Save This saves compare txt to the current directory notepad compare txt at the VSIM gt prompt to display the report Figure 133 d Close Notepad when you are done reviewing the report 2 Save the comparison data in files that can be reloaded into ModelSim a Select Tools Waveform Compare Differences Save b Click Save This saves compare dif to the current directory c Select Tools Waveform Compare Rules Save d Click Save This saves compare rul to the current directory e Select Tools Waveform Compare End Comparison Saving and reloading comparison data Figure 133 Coverage data saved to
52. 0000000110100 El Zu ModelSim SE Tutorial T 108 Lesson 9 Viewing and initializing memories In this next step you will experiment with loading from both a file and a fill Figure 89 Loading a relocatable memory file pattern You will initialize spram3 with the 250 addresses of data you saved previously into the relocatable file You will also initialize 50 Instance Name additional address entries with a fill pattern fram tb spramS mem T Load Type Address Range 3 Loadthe ram tb spram3 mem instance with a relocatable memory pattern gt reloc mem and a fill pattern poe ON Addresses in decimal a Right click in the data column of the mem 2 tab and select Load to Both File and Data Start 0 300 bring up the Load Memory dialog box Figure 89 3d m File Load b For Load Type select Both File and Data File Format c For Address Range select Addresses and enter 0 as the Start address and Verilog Hex 3e 300 as the End address d Binary This means that you will be loading the file from 0 to 300 However the reloc mem file contains only 251 addresses of data Addresses 251 to 300 will be loaded with the fill data you specify next Filename jreloc mem Browse r Data Load d ForFile Load enter reloc mem in the Filename field Fill Type e For Data Load select a Fill Type of Increment Value
53. 0024 0000002 00000030 00000036 0000003c 00000042 00000048 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX NECC OO D DIM Simulate the design a Click the run all icon in the Main window b Click the mem tab of the MDI frame to bring the ram_tb spram1 mem instance to the foreground Figure 80 VHDL In the Transcript pane you will see NUMERIC STD warnings that can be ignored and an assertion failure that is functioning to stop the simulation The simulation itself has not failed Let s change the address radix and the number of words per line for instance ram_tb spraml mem a Right
54. 01 01001111 01010101 01011011 01100001 01100111 01101101 01110011 1111601 Line Wrap C Fit in Window Words per Line 1 OK Cancel 00101100 00101101 00110010 00110011 00111000 00111001 00111110 00111111 01000100 01000101 01001010 01001011 01010000 01010001 01010110 01010111 01011100 01011101 01100010 01100011 01101000 01101001 01101110 01101111 01110100 01110101 1333636 13334131 ModelSim SE Tutorial T 104 Lesson 9 Viewing and initializing memories Navigating within the memory Figure 82 Memory window new address radix and line length You can navigate to specific memory address locations or to locations containing E ram_tb sprami mem particular data patterns First you will go to a specific address 0 00101000 1 00101001 1 Use Goto to find a specific address 2 00101010 3 00101011 a Right click anywhere in address column and select Goto Figure 83 4 00101100 5 00101101 The Goto dialog box opens in the data pane 6 00101110 7 00101111 b Type 30 in the dialog box 8 00110000 00110001 c Click OK 00110010 00110011 00110100 The requested address appears in the top line of the window 4 mem mem 1 ram_tb v Figure 83 The Goto dialog box Z ram tb spram1 mem 00101000 00101001 00101010 00101011 v Goto Memory x 00101101 Goto Address 00101110 00101111 00110000 00110001 00110010 00110011 00110100
55. 1 Design VHDL vea 1f Type Path Library C modeltech examples work 1 Module C modeltech examples counter v Module C modeltech examples tcounter v Library MODEL_TECH vital2000 Library MODEL_TECH ieee Library MODEL_TECH modelsim_lib Library MODEL_TECH std Library MODEL_TECH std_developerskit synopsys Library MODEL_TECH synopsys mo A il NECI SOMONE TEU Aes Design Unit s Resolution work test counter gt vi 1 Te Optimization Enable optimization Design Files tcounter v M counter Folder Folder Verilog 1 Verilog 0 Simul 11 23 04 07 33 31 11 23 04 07 33 30 ModelSim SE Tutorial T 40 Lesson 3 ModelSim projects Lesson wrap up This concludes this lesson Before continuing you need to end the current simulation and close the current project 1 Select Simulate gt End Simulation Click Yes 2 Select the Project tab in the Main window Workspace 3 Right click the test project to open a context popup menu and select Close Project If you do not close the project it will open automatically the next time you start ModelSim ModelSim SE Tutorial Figure 28 Transcript shows options used for Simulation Configuration Transcript Compile of tcounter was successful Compile of counter v was successful 2 compiles 0 failed with no errors vsim hazards t ps work tes
56. CTIVE UNDER APPLICABLE LAW IN NO EVENT SHALL MENTOR GRAPHICS OR ITS LICENSORS BE LIABLE FOR INDIRECT SPECIAL INCIDENTAL OR CONSEQUENTIAL DAMAGES INCLUDING LOST PROFITS OR SAVINGS WHETHER BASED ON CONTRACT TORT OR ANY OTHER LEGAL THEORY EVEN IF MENTOR GRAPHICS OR ITS LICENSORS HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES IN NO EVENT SHALL MENTOR GRAPHICS OR ITS LICENSORS LIABILITY UNDER THIS AGREEMENT EXCEED THE AMOUNT PAID BY YOU FOR THE SOFTWARE OR SERVICE GIVING RISE TO THE CLAIM IN THE CASE WHERE NO AMOUNT WAS PAID MENTOR GRAPHICS AND ITS LICENSORS SHALL HAVE NO LIABILITY FOR ANY DAMAGES WHATSOEVER LIFE ENDANGERING ACTIVITIES NEITHER MENTOR GRAPHICS NOR ITS LICENSORS SHALL BE LIABLE FOR ANY DAMAGES RESULTING FROM OR IN CONNECTION WITH THE USE OF SOFTWARE IN ANY APPLICATION WHERE THE FAILURE OR INACCURACY OF THE SOFTWARE MIGHT RESULT IN DEATH OR PERSONAL INJURY INDEMNIFICATION YOU AGREE TO INDEMNIFY AND HOLD HARMLESS MENTOR GRAPHICS AND ITS LICENSORS FROM ANY CLAIMS LOSS COST DAMAGE EXPENSE OR LIABILITY INCLUDING ATTORNEYS FEES ARISING OUT OF OR IN CONNECTION WITH YOUR USE OF SOFTWARE AS DESCRIBED IN SECTION 7 INFRINGEMENT 9 1 Mentor Graphics will defend or settle at its option and expense any action brought against you alleging that Software infringes a patent or copyright or misappropriates a trade secret in the United States Canada Japan or member state of the European Patent Office Mentor Graphics
57. DL license use the VHDL version instead When necessary we distinguish between the Verilog and VHDL versions of the design Related reading ModelSim User s Manual Tracing signals with the Dataflow window UM 299 ModelSim GUI Reference Dataflow window GR 133 ModelSim SE Tutorial Compiling and loading the design In this exercise you will use a DO file to compile and load the design 1 Create a new directory and copy the tutorial files into it Start by creating a new directory for this exercise in case other users will be working with these lessons Create the directory and copy all files from lt install_dir gt examples dataflow verilog to the new directory If you have a VHDL license copy the files in lt install_dir gt examples dataflow vhdl instead Start ModelSim and change to the exercise directory If you just finished the previous lesson ModelSim should already be running If not start ModelSim a Type vsim at a UNIX shell prompt or use the ModelSim icon in Windows If the Welcome to ModelSim dialog appears click Close b Select File gt Change Directory and change to the directory you created in step 1 Execute the lesson DO file a Type do run do at the ModelSim gt prompt The DO file does the following e Creates the working library e Compiles the design files e Opens the Dataflow window e Adds signals to the Wave window Logs all signals in the design e Runs the simulation Feel
58. L C modeltech examples resource_library parts_lib Add Modify Delete r Search Libraries First Lf _Add OK Cancel ModelSim SE Tutorial T 48 Lesson 4 Working with multiple libraries Linking in VHDL To link to a resource library in VHDL you have to create a logical mapping to the physical library and then add LIBRARY and USE statements to the source file 1 Create a logical mapping to parts lib a b Select File gt New gt Library In the Create a New Library dialog select a map to an existing library Type parts_lib in the Library Name field Click Browse to open the Select Library dialog and browse to parts_lib in the resource_library directory you created earlier in the lesson Click OK to select the library and close the Select Library dialog The Create a New Library dialog should look similar to the one shown in Figure 34 Click OK to close the dialog 2 Add LIBRARY and USE statements to tcounter vhd a In the Library tab of the Main window click the icon next to the work library Right click test_counter in the work library and select Edit This opens the file in the Source window Right click in the Source window and uncheck Read Only Add these two lines to the top of the file LIBRARY parts_lib USE parts_lib ALL The testbench source code should now look similar to that shown in Figure 35 Select File gt Save
59. L example Figure 39 test_ringbuf design in ModelSim Te Modelsim File Edit View Format Compile Simulate Add Tools Window Help ontan A test_ringbuf cModule clock sc clock ScModule mi ring INST ringbuf Module D reset generator test_tingbuf ScMethod Generate data test ScMethod compare data test ringbuf ScMethod print error test_ringbuf ScMethod print restore test ringbuf ScMethod Objects a x lt Ready gt lt Ready gt lt Ready gt lt Ready gt lt Ready gt Ready Active Processes HIMPLICIT WIRE outstrobe tt IMPLICIT WIRE oeenable t HIMPLICIT WIRE ramadrs 2 HASSIGN 6S test rinabuf ri HIMPLICIT wWIRE buffer H23 HASSIGNH3S test rinabuf ri ModelSim sccom ink tt Model Technology ModelSim SE sccom 6 0 Beta 3 compiler 2004 07 Jul 9 2004 ModelSim gt vsim test ringbuf vsim test ringbuf Loading work systemc so Loading work test_ringbuf Loading work ringbuf Loading work control tt Loading work store Loading work retrieve Now Ons Delta 0 sim test ringbuf ModelSim SE Tutorial T 60 Lesson 5 Simulating designs with SystemC Viewing SystemC objects in the G Ul Figure 40 SystemC objects in the work library SystemC objects are denoted in the ModelSim GUI with a green S on the Library tab a green C on the
60. Mentor Graphics support www mentor com supportnet Updates Access to the most current version of ModelSim www model com downloads default asp Latest version email Place your name on our list for email notification of news and updates www model com products informant asp ModelSim SE Tutorial Before you begin T 9 Before you begin Preparation for some of the lessons leaves certain details up to you You will decide the best way to create directories copy files and execute programs within your operating system When you are operating the simulator within ModelSim s GUI the interface is consistent for all platforms Examples show Windows path separators use separators appropriate for your operating system when trying the examples Example designs ModelSim comes with Verilog and VHDL versions of the designs used in these lessons This allows you to do the tutorial regardless of which license type you have Though we have tried to minimize the differences between the Verilog and VHDL versions we could not do so in all cases In cases where the designs differ e g line numbers or syntax you will find language specific instructions Follow the instructions that are appropriate for the language that you are using ModelSim SE Tutorial T 10 Introduction ModelSim SE Tutorial Lesson 1 ModelSim conceptual overview Topics The following topics are covered in this chapter Introduction Basic simulation flow
61. NST bloc 0000100 test_ringbuf ring_INST bloc ringbuf ring INST block Ztest ringbuf ring INST block test rinabufZring INST block 10000100 rinabuf ring INST block 0 ringbuf ring INST block 10000100 ringbuf ring INST block ringbuf ring INST block 010110 0100 test_ringbuf ring_INST block 00000 62300 463000 ns 461988 ns to 463241 ns Now 500 us Delta 2 cursor name cursor value cursor Loading a design For the examples in this lesson we have used the design simulated in Lesson 2 Basic simulation 1 If you just finished the previous lesson ModelSim should already be running If not start ModelSim a vsim at a UNIX shell prompt or use the ModelSim icon in Windows If the Welcome to ModelSim dialog appears click Close 2 Load the design a Select File gt Change Directory and open the directory you created in Lesson 2 The work library should already exist b Click the icon next to the work library and double click test counter ModelSim loads the design and adds sim and Files tabs to the Workspace Loading a design 67 ModelSim SE Tutorial T 68 Lesson 6 Viewing simulations in the Wave window Adding objects to the Wave Wi nd OW Figure 48 A Wave window docked in the Main window m efault ModelSim offers several methods for addi
62. Sim Advanced Verification and Debugging SE Tutorial Version 6 0e Published June 15 2005 AU Pa E a E did 1 2 SN x SO LO Tip IOA diis S 1 F ry Fr j e T I n 1 r E a i d PE 1 Ba A A 7 L b fi ams 0 i P H m Fa 1 n P I A L 7 E Copyright Mentor Graphics Corporation 2005 All rights reserved This document contains information that is proprietary to Mentor Graphics Corporation The original recipient of this document may duplicate this document in whole or in part for internal business purposes only provided that this entire notice appears in all copies In duplicating any part of this document the recipient agrees to make every reasonable effort to prevent the unauthorized use and distribution of the proprietary information This document is for information and instruction purposes Mentor Graphics reserves the right to make changes in specifications and other information contained in this publication without prior notice and the reader should in all cases consult Mentor Graphics to determine whether any changes have been made The terms and conditions governing the sale and licensing of Mentor Graphics products are set forth in written agreements between Mentor Graphics and its customers No representation or other affirmation of fact contained in this publicati
63. This opens the Coverage Report dialog Figure 118 b Make sure Report on all instances and No Filtering are selected and then click OK ModelSim creates a file report txt in the current directory and displays the report in Notepad c Close Notepad when you are done looking at the report 2 Create a summary report on all design files from the Transcript pane a Typecoverage report file cover txt at the VSIM prompt b notepad cover txt at the VSIM gt prompt to view the report c Close Notepad when you are done reviewing the report Creating Code Coverage reports T 133 Figure 118 The Coverage Report dialog ie e C C 2 Coverage Type Coverage Report Report on all files Report on all instances Report on all design units Report on a specific DU 1 x DU Name x Report on a specific instance Instance Name sim top Report on a source file File Report specific package Browse Package Name x Statement Coverage Branch Coverage Condition Coverage Expression Coverage Toggle Coverage Extended Toggle Coverage Filter No Filtering Filter Above Percent Filter Below Percent Percent 75 m Report Pathname report txt Browse Other Options Zero Coverage Only Include Line Details Coverage Totals Only Disable Source Annotation Recursive Write XML Format
64. ad Select wave do and click Open ModelSim restores the window to its previous state Close the Wave window when you are finished by selecting File gt Close Saving the window format 73 ModelSim SE Tutorial T 74 Lesson 6 Viewing simulations in the Wave window Lesson wrap up This concludes this lesson Before continuing we need to end the current simulation 1 Select Simulate gt End Simulation Click Yes ModelSim SE Tutorial Lesson 7 Creating stimulus with Waveform Editor Topics The following topics are covered in this lesson Introduction Related reading Loading a design unit Creating waves with a wizard Editing waveforms in the Wave window Saving and reusing the wave commands Exporting the created waveforms Running the simulation Simulating with the testbench file Importing an EVCD file Lesson wrap up T 76 T 76 T 77 T 78 T 80 T 83 T 84 T 85 T 86 T 87 T 88 T 75 ModelSim SE Tutorial T 76 Lesson 7 Creating stimulus with Waveform Editor Introduction The Waveform Editor creates stimulus for your design via interactive manipulation of waveforms You can then run the simulation with these edited waveforms or export them to a stimulus file for later use In this lesson you will do the following Load the counter design unit without a testbench Create waves via a wizard Edit waves interactively in the Wave window Export the waves to an HDL testbe
65. ample In this next example you have a SystemC testbench that instantiates an HDL module In order for the SystemC testbench to interface properly with the HDL module you must create a stub module a foreign module declaration You will use the scgenmod CR 260 utility to create the foreign module declaration Finally you will link the created C object files using sccom link 1 Create a new directory and copy the tutorial files into it Start by creating a new directory for this exercise in case other users will be working with these lessons Create the directory then copy all files from lt install_dir gt modeltech examples systemc sc_vlog into the new directory If you have a VHDL license copy the files in lt install_dir gt modeltech examples systemc sc_vhdl instead Start ModelSim and change to the exercise directory If you just finished the previous lesson ModelSim should already be running If not start ModelSim a Type vsim at a command shell prompt If the Welcome to ModelSim dialog appears click Close b Select File gt Change Directory and change to the directory you created in step 1 Set the working library a Type vlib work in the ModelSim Transcript window to create the working library Compile the design a Verilog Type vlog v in the ModelSim Transcript window to compile all Verilog source files VHDL Type vcom 93 vhd in the ModelSim Transcript window to compile all VHDL source file
66. and counter v in the examples If you have a VHDL license use tcounter vhd and counter vhd instead Related reading ModelSim User s Manual 3 Design libraries UM 57 ModelSim SE Tutorial Creating the resource library 1 Create a directory for the resource library Create a new directory called resource_library Copy counter v from lt install_dir gt modeltech examples to the new directory Create a directory for the testbench Create a new directory called testbench that will hold the testbench and project files Copy tcounter v from lt install_dir gt modeltech examples to the new directory You are creating two directories in this lesson to mimic the situation where you receive a resource library from a third party As noted earlier we will link to the resource library in the first directory later in the lesson Start ModelSim and change to the exercise directory If you just finished the previous lesson ModelSim should already be running If not start ModelSim a Type vsim at a UNIX shell prompt or use the ModelSim icon in Windows If the Welcome to ModelSim dialog appears click Close b Select File gt Change Directory and change to the resource library directory you created in step 1 Create the resource library a Select File gt New gt Library b Type parts lib in the Library Name field Figure 29 The Library Physical Name field is filled out automatically Once you click OK ModelSim creates
67. by hovering the mouse pointer The icons change to numbers that indicate how many times the statements and branches in that line were executed Figure 115 In this case line 24 was executed 1562 times Ih C modeltech examples coverage verilog test_sm v nop e Select Tools Code Coverage Show coverage numbers 23 task nop The icons are replaced by execution counts on every line An ellipsis E ABOCO op_ is displayed whenever there are multiple statements on the line Hover 26 rn the mouse pointer over a statement to see the count for that statement 27 the ctrl op 28 task ctrl 29 input 7 0 data f Select Tools gt Code Coverage gt Hide coverage numbers to return to icon display 30 begin X 31 5 into 4 b0001 28 b0 c X 32 G posedge clk X 33 5 into data 34 end X 35 endtask SRS oT ree h beh_sram v h sm seq v hi test sm v ModelSim SE Tutorial Viewing toggle statistics in the Objects pane Toggle coverage counts each time a logic node transitions from one state to another Earlier in the lesson you enabled two state toggle coverage 0 gt 1 and 1 gt 0 with the cover t argument Alternatively you can enable six state toggle coverage using the cover x argument See Toggle coverage UM 344 for more information 1 View toggle data in the Objects pane of the Main window Select test sm in the sim tab of the Main wi
68. c Properties dialog set the Address Radix to Decimal and the Data Radix to Binary Click OK to accept the changes and close the dialog File S d Select File gt Save to bring up the Save Memory dialog box vius e Specify a Start address of 0 and End address of 250 E doo mem mem Browse f For Address Radix select Decimal and for Data Radix select Binary ok es g Click No addresses to create a memory pattern that you can use to relocate somewhere else in the memory or in another memory Te h Enter the file name as reloc mem then click OK to save the memory contents and close the dialog ModelSim SE Tutorial You will use this file for initialization in the next section Initializing a memory In ModelSim it is possible to initialize a memory using one of three methods from a saved memory file from a fill pattern or from both First let s initialize a memory from a file only You will use one you saved previously data_mem mem 1 View instance ram tb spram3 mem a Double click the ram tb spram3 mem instance in the Memories tab This will open a new tab mem 2 in MDI frame to display the contents of ram_tb spram3 mem Scan these contents so you can identify changes once the initialization is complete b Right click and select Properties to bring up the Properties dialog c Change the Address Radix to Decimal and Data Radix to Binary and click OK 2 Initialize
69. ch Loading project counter Compile of tcounter vhd was successful ModelSim gt vsim work test_counter vsim work test_counter Loading C Modeltech 6 0 win32 std standard Loading work test_counter only Warning vsim 3473 Component dut is not bound Time Ons Iteration 0 Region test_counter File C 6 0 Tutorial testbench tcounter vhd VSIM 9 gt n The process for linking to a resource library differs between Verilog and VHDL If you are using Verilog follow the steps in Linking in Verilog T 47 If you are using VHDL follow the steps in Linking in VHDL T 48 one page later Linking in Verilog Linking in Verilog requires that you specify a search library when you invoke the simulator 1 Specify a search library during simulation a Click the Simulate icon on the Main window toolbar b Click the icon next to the work library and select PER test counter c Click the Libraries tab d Click the Add button next to the Search Libraries field and browse to parts lib in the first directory you created earlier in the lesson e Click OK The dialog should have parts lib listed in the Search Libraries field Figure 33 f Click OK The design loads without errors Linking to the resource library T 47 Figure 33 Specifying a search library in the Simulate dialog eStart Simulation Design VHDL Verilog Libraries SDF Others Search Libraries
70. ck Save This saves a DO file named waveedit do to the current directory 2 Quit and then reload the simulation a In the Main window select Simulate gt End Simulation and click Yes to confirm you want to quit simulating Double click the counter design unit on the Library tab to reload the simulation 3 Open the format file a b Select View gt Debug Windows gt Wave to open the Wave window Undock the Wave window In the Wave window select File gt Load Double click waveedit do to open the file The waves you created earlier in the lesson reappear If waves do not appear you probably did not load the counter design unit Saving and reusing the wave commands T 83 ModelSim SE Tutorial T 84 Lesson 7 Creating stimulus with Waveform Editor Exporting the created waveforms At this point you can run the simulation or you can export the created waveforms to one of four stimulus file formats You will run the simulation in a minute but first let us export the created waveforms so we can use them later in the lesson 1 Export the created waveforms in an HDL testbench format a b In the Wave window select File gt Export gt Waveform Select Verilog Testbench or VHDL Testbench if you are using the VHDL sample files Enter 1000 Figure 64 for End Time if necessary and click OK ModelSim creates a file named export v or export vhd in the current directory Later in the lesson we will
71. clock pattern a In the Objects pane right click signal clk and select Create Wave Figure 55 This opens the Create Pattern Wizard dialog where you specify the type of pattern Clock Repeater etc and a start and end time b The default pattern is Clock which is what we need so click Next Figure 56 ModelSim SE Tutorial Figure 55 Creating waves from the Objects pane tpd_teset_to 3 Parameter Internal tpd_clk_to_c 2 Parameter Internal count Reg Out clk 5 In Signal Declaration reset Net In View Memory Contents Insert Breakpoint Add to Wave Add to List Log Signal Toggle Coverage Force NoForce Clock sim counter clk Start Time End Time Time Unit fo Mo Ins wi Creating waves with a wizard T 79 c In the second dialog of the wizard enter 0 for Initial Value leave Figure 57 Specifying clock pattern attributes everything else as is and click Finish Figure 57 x sim counter clk Pattern clock gt x A generated waveform appears in the Wave window Figure 58 Notice M x 1 Een PL 1 Clock Attributes the small red dot on the waveform icon and the prefix Edit These Specify the Clock Pattern Wari nbutes Attributes items denote an editable wave o ELSES 1c Clock Period Time Unit 100 Ins 2 Create a second wave using the wizard a Duty Cycle a Right click signal reset in the Objects pane and select
72. compile and simulate the file 2 Export the created waveforms in an extended VCD format Select File gt Export gt Waveform Select EVCD File Enter 1000 for End Time if necessary and click OK ModelSim creates an extended VCD file named export vcd We will import this file later in the lesson ModelSim SE Tutorial Figure 64 The Export Waveform dialog M Export Waveform 3 E xl Save As C Force File EVCD File VHDL Testbench Verilog Testbench Start Time End Time Time Unit Design Unit Name counter File Name E Browse Overwrite Existing Files OK Cancel Running the simulation Once you have finished editing the waveforms you can run the simulation straight away 1 Add a design signal a Inthe Objects pane right click count and select Add to Wave gt Selected Signals The signal is added to the Wave window 2 Run the simulation a Click the Run All icon The simulation runs for 1000 ns and the waveform is drawn for sim counter count Figure 65 Look at the signal transitions for count from 300 ns to 500 ns The transitions occur when clk goes high and you can see that count follows the pattern you created when you edited clk by stretching and deleting edges 3 Quit the simulation a Inthe Main window select Simulate gt End Simulation and click Yes to confirm you want to quit simulating Running the simulation T 85 Fi
73. counter wlf at the DOS UNIX prompt The c argument instructs ModelSim not to invoke the GUI The wlf argument saves the simulation results in a WLF file This allows you to view the simulation results in the GUI for debugging purposes View the list output a Open counter st and view the simulation results ns counter count delta counter clk counter reset 0 0 xz l 0 0 z 50 0 100 0 00 100 41 000 150 0 0 0 151 0 1 Q 200 0 1 0 0 250 0 p ModelSim SE Tutorial This is the output produced by the Verilog version of the design It may appear slightly different if you used the VHDL version View the results in the GUL Since you saved the simulation results in counter wlf you can view them in the GUI by invoking VSIM with the view argument a vsim view counter wlf at the DOS UNIX prompt The GUI opens and a dataset tab named counter is displayed in the Workspace Figure 136 b Right click the counter instance and select Add gt Add to Wave The waveforms display in the Wave window When you finish viewing the results select File gt Quit to close ModelSim Running ModelSim in command line mode T 163 Figure 136 A dataset in the Main window Workspace M counter counter Module ad ed amp counter gt ModelSim SE Tutorial T 164 Lesson 14 Automating ModelSim Using Tcl with ModelSim The DO files used in previous exercises contained only M
74. d with ESD C and C compiler Software that are linked into a composite program as an integral part of your compiled computer program provided that you distribute these files only in conjunction with your compiled computer program Mentor Graphics does NOT grant you any right to duplicate or incorporate copies of Mentor Graphics real time operating systems or other ESD Software except those explicitly granted in this section into your products without first signing a separate agreement with Mentor Graphics for such purpose BETA CODE Portions or all of certain Software may contain code for experimental testing and evaluation Beta Code which may not be used without Mentor Graphics explicit authorization Upon Mentor Graphics authorization Mentor Graphics grants to you a temporary nontransferable nonexclusive license for experimental use to test and evaluate the Beta Code without charge for a limited period of time specified by Mentor Graphics This grant and your use T 167 ModelSim SE Tutorial T 168 License Agreement of the Beta Code shall not be construed as marketing or offering to sell a license to the Beta Code which Mentor Graphics may choose not to release commercially in any form If Mentor Graphics authorizes you to use the Beta Code you agree to evaluate and test the Beta Code under normal conditions as directed by Mentor Graphics You will contact Mentor Graphics periodically during your use of the Beta Code to d
75. dialog Figure 25 which lets you set a variety of options on your design files c Click the Place In Folder drop down arrow and select HDL d Click OK The two files are moved into the HDL folder Click the icons on the folders to see the files The files are now marked with a icon Because you moved the files the project no longer knows if the previous compilation is still valid ModelSim SE Tutorial Figure 24 A folder with a sub folder V ce counter Design Files HDL Folder 2e Figure 25 Changing file location via the project settings dialog fw Project Compiler Settings x General Verilog Coverage General Settings Do Not Compile Compile to library wok vi Place in Folder Top Level File Properties File sm v Location C 6 0 Tutorial examples coverage verilog sm v MS DOS name C 6 0 Tutorial examples coverage werilog sm Type Verilog Change T ype Size 2459 2KB Simulation Configurations A Simulation Configuration associates a design unit s and its simulation options For example say every time you load tcounter v you want to set the simulator resolution to picoseconds ps and enable event order hazard checking Ordinarily you would have to specify those options each time you load the design With a Simulation Configuration you specify options for a design and then save a configuration that associates the design and its op
76. dir gt examples psl vhdl instead Start ModelSim and change to the exercise directory you created If you just finished the previous lesson ModelSim should already be running If not start ModelSim a To start ModelSim type vsim at a UNIX shell prompt or use the ModelSim icon in Windows If the Welcome to ModelSim dialog appears click Close Select File gt Change Directory and change to the directory you created in step 1 Execute the lesson DO file a Type do compile do at the ModelSim gt prompt The DO file does the following e Creates the working library e Compiles the design files assertions and cover directives Feel free to open the DO file and look at its contents Compile the example design T 137 ModelSim SE Tutorial T 138 Lesson 12 Debugging with PSL assertions Loa d an d run wi thou tasse rti ons Figure 119 Transcript after running the simulation without assertions Ti Transcript ixl 1 Load the design without assertions Transcript a Type vsim tb nopsl at the VSIM gt prompt ModelSim gt vsim tb nopsl vsim nopsl tb Loading work tb Loading work dram_control Loading work dram VSIM 4 run all Reset is working The nopsl argument instructs the compiler to ignore PSL assertions 2 the simulation a Type run all at the VSIM gt prompt or click the Run All icon Verilog The simulation reports an error at 267400 ns and stops on line
77. e 3 View statistics in the Details pane Figure 111 Details pane showing toggle coverage statistics a Select the Toggle tab in the Missed Coverage pane If the Toggle tab isn t visible you can do one of two things 1 widen the pestamce Cast sm pane by clicking and dragging on the pane border 2 if your mouse has Signal a middle button click and drag the tabs with the middle mouse button Noda count 32 b Select any object in the Toggle tab to see details in the Details pane gt 0 71870 Figure 111 1 71876 Toggle Coverage 34 35 0 1 Coverage 34 38 Full Coverage 34 35 The Instance Coverage pane displays coverage statistics for each instance in 2 Coverage 34 38 flat non hierarchical view Figure 112 Select any instance in the Instance Coverage pane to see its source code displayed in the Source window 4 View instance coverage statistics Figure 112 The Instance Coverage pane Instance Cov erage METEN Stmt graph Bunch ent penchhis _ Branchnfves_ Buaneh 2 TA ModelSim SE Tutorial Viewing statistics in the Source window In the previous section you saw that the Source window and the Main window Viewing statistics in the Source window T 129 Figure 113 Selecting a line in the Missed Coverage pane M ge Missed Statements coverage panes are linked You can select objects in the Main window panes to view the underlying source code in the Source window Furt
78. e Figure 3 and records the library mapping for future reference in the ModelSim EH wok Library initialization file modelsim ini MEL vital uuu ModelSim gt wm title ModelSim Librar vlib work When you pressed OK in step c above several lines were printed to the Main modek B Ti vmap work work window Transcript pane Copying C Modeltech 6 0 win32 mo PR std Library delsim ini to modelsim ini vlib work std developerskit Library Modifying modelsim ini Wl synopsys Library warning Copied C Modeltech 6 0 w vmap work work k piel Phere in32 modelsim ini to modelsim ini Copying C modeltech win32 modelsim ini to modelsim ini vb ME Updated modelsim ini Modifying modelsim ini Warning Copied C modeltech win32 modelsim ini to Library ModelSim gt modelsim ini bu Updated modelsim ini No Design Loaded The first two lines are the command line equivalent of the menu commands you invoked Many menu driven functions will echo their command line equivalents in this fashion The other lines notify you that the mapping has been recorded in a local ModelSim initialization file ModelSim SE Tutorial Compiling the design With the working library created you are ready to compile your source files You can compile by using the menus and dialogs of the graphic interface as in the Verilog example below or by entering a command at the ModelSim gt p
79. e assertions The Assertions pane also indicates a failure of assert check refresh in the Failure Count column Figure 122 ModelSim SE Tutorial Figure 121 Assertion failure indicated in the Wave window m V default E count E ref count 4 refresh Assertions assert test rea asser test writ asset check asser check asser refresh asset check asset check f Cursor 1 ae in dramcon_sim el wave h h dram_cntrl ps TERNE tions E 1 4 w Name Fite Pass Faiure Count Pass Count tb cnitr t check refresh disabled enabled 0 E Aib cnit assert refresh rate enabled disabled 1 EKA tb entrl assert_check_write enabled disabled D 1 EKA tb cntil assert check read enabled enabled 0 0 Debugging the assertion failure 1 View the source code of the failed assertion Verilog The current line arrow points to the failed assertion on line 24 of dram_cntrl psl file Figure 123 This assertion consists of checking the check_refresh property which is defined on lines 20 22 The property states that when the refresh signal is active then we will wait until the memory controller state goes to IDLE The longest a read or write should take is 14 cycles If the controller is already IDLE then the wait is 0 cycles Once the controller is in IDLE state then the refresh sequence should start in the next cycle The refresh_sequence second
80. e several options for checking values e at the values shown in the Objects window Figure 13 set your mouse pointer over the count variable in the Source window and a balloon will pop up with the value Figure 12 e highlight the count variable in the Source window right click it and select Examine from the pop up menu use the examine command to output the value to the Main window Transcript 1 examine count 5 Try out the step commands a Click the Step icon on the Main window toolbar This single steps the debugger Experiment on your own Set and clear breakpoints and use the Step Step Over and Continue Run commands until you feel comfortable with their operation ModelSim SE Tutorial Figure 12 Resting the mouse pointer on a variable in the Source view 32 33 34 35 E C 6 0 Tutorial examples counte 22 for i 4 bO carry 4 bl 46 i lt 7 i it 23 begin 24 increment i val i carry 25 carry val i amp carry 26 end 27 end 28 endfunction 29 30 always posedge clk or posedge reset if reset colunt tpd reset to count 8 h00 else count renent count ftest counter dut count i JE Figure 13 Values shown the Objects window Objects count clk reset tpd_teset_to_count 3 tpd clk to count 2 Parameter Internal Parameter Internal NKNRKNMM Reg Out 50
81. elSim license file to simulate SystemC designs Please contact your Mentor Graphics sales representatives if you currently do not have such a feature The table below shows the supported operating systems for SystemC and the corresponding required versions of a C compiler Platform Supported compiler versions HP UX 11 0 or later aCC 3 45 with associated patches RedHat Linux 7 2 and 7 3 gcc 3 2 3 RedHat Linux Enterprise version 2 1 SunOS 5 6 or later gcc 3 2 Windows NT and other NT based platforms win2K XP etc Minimalist GNU for Windows MinGW gcc 3 2 3 See SystemC simulation in the ModelSim User s Manual for further details Setting up the environment T 53 ModelSim SE Tutorial T 54 Lesson 5 Simulating designs with SystemC Preparing an OSCI SystemC design For an OpenSystemC Initiative OSCI compliant SystemC design to run on ModelSim you must first e Replace sc main with an SC MODULE potentially adding a process to contain any testbench code Replace sc_start by using the run CR 254 command in the GUI Remove calls to sc initialize Export the top level SystemC design unit s using the SC MODULE EXPORT macro In order to maintain portability between OSCI and ModelSim simulations we recommend that you preserve the original code by using ifdef to add the ModelSim specific information When the design is analyzed sccom CR 256 recognizes the MTI SYSTEMC preprocessi
82. elSim should already be running If not start ModelSim a Type vsim at a UNIX shell prompt or use the ModelSim icon in Windows If the Welcome to ModelSim dialog appears click Close b Select File gt Change Directory and change to the directory you created in step 1 Create the working library a Type vlib work at the ModelSim gt prompt Compile the design files a For Verilog Type vlog cover bct sm v sm seq v beh sram v test sm v at the ModelSim gt prompt For VHDL Type vcom cover bct sm vhd sm seq vhd sm sram vhd test sm vhd at the ModelSim prompt The cover bct argument instructs ModelSim that you want branch condition and toggle coverage statistics statement coverage is included by default See Enabling code coverage UM 339 for more information on the available coverage types Compiling the design T 125 ModelSim SE Tutorial T 126 Lesson 11 Simulating with Code Coverage Loading and running the design 1 Load the design a Type vsim coverage test sm at the ModelSim gt prompt 2 the simulation b Type run 1 ms at the VSIM gt prompt When you load a design with Code Coverage enabled ModelSim adds several columns to the Files and sim tabs in the Workspace Figure 107 ModelSim also displays three Code Coverage panes in the Main window Figure 108 Missed Coverage Displays the selected file s un executed statements branches conditions and expressions and signals that
83. elect Simulate gt End Simulation Click Yes when prompted to confirm that you wish to quit simulating ModelSim SE Tutorial Lesson 6 Viewing simulations in the Wave window Topics The following topics are covered in this lesson Introduction Related reading Loading a design Adding objects to the Wave window Using cursors in the Wave window Working with a single cursor Working with multiple cursors Saving the window format Lesson wrap up T 66 T 66 T 67 T 68 T 70 T 70 T 71 T 73 T 74 T 65 ModelSim SE Tutorial T 66 Lesson 6 Viewing simulations in the Wave window Introduction The Wave window allows you to view the results of your simulation as HDL waveforms and their values The Wave window is divided into a number of window panes Figure 47 All window panes in the Wave window can be resized by clicking and dragging the bar between any two panes Related reading ModelSim GUI Reference Wave window GR 216 ModelSim User s Manual Chapter 8 WLF files datasets and virtuals UM 225 ModelSim SE Tutorial Figure 47 The Wave window and its many panes pathname value waveform Ted wave default File Edit View Insert Format Tools Window amp x meal is wa ee Ex Sut is test_ringbuf ring_INST block test_ringbuf ring_INST block test_ringbuf ring_I
84. en as panes within the Main window The Dataflow and List windows will open as separate windows You may need to move or resize the windows to your liking Panes within the Main window can be undocked to stand alone 2 Add signals to the Wave window a b In the Workspace pane select the sim tab Right click test_counter to open a popup context menu Select Add gt Add to Wave Figure 8 Three signals are added to the Wave window 3 the simulation a Click the Run icon in the Main or Wave window toolbar The simulation runs for 100 ns the default simulation length El and waves are drawn in the Wave window Type run 500 at the VSIM gt prompt in the Main window The simulation advances another 500 ns for a total of 600 ns Figure 9 Running the simulation T 25 Figure 8 Adding signals to the Wave window 77 ModelSim File Edit Yiew Format Compile Simulate Add Tools Window Help Objects A f Name Value ck x e 4 A 5 Add to Wave dg x Add to Dataflow eed Add to List LICIT wIR H gi xi pal wave de M dut IMPLIC Instantiation fe Hum 0 INITIAL EN Ls FINITIAL HINITIAL Copy Find View Declaration Create Wave Expand Selected i xl s Collapse Selected Ili Library amp Exand A h tcounte _ Collapse All
85. er Module ieee Library Beta Compiler 2004 06 Jun 4 2004 modelsim lib Library Compiling module counter std Library Top level modules 4 counter Library ModelSim gt E No Design Loaded No Context ModelSim SE Tutorial T 24 Lesson 2 Basic simulation Loading the desig n into the Si mu ator Figure 6 Loading the design with the Start Simulation dialog fea Start Simulation 1 Load the test counter module into the simulator Design VHDL Verlag Libraries SDF Others a Double click test counter in the Main window Workspace to load the desi gn Library C 6 0 Tutorial examples work T Module C 6 0 Tutorial examples counter v You can also load the design by selecting Simulate gt Start Simulation Module Tutorial examples tcounter v in the menu bar This opens the Start Simulation dialog With the Design NODE FER Library MODEL_TECH ieee Library MODEL TECH modelsim lib Library MODEL_TECH std std_developerskit Library MODEL_TECH std_developerskit mA Libram NDEI TECH Jomoanene tab selected click the sign next to the work library to see the counter and test counter modules Select the test counter module and click OK Figure 6 When the design is loaded you will see a new tab named sim that displays the hierarchical structure of the design Figure 7 You can m Design Unit
86. ere ene le Random 2c Fill Data Skip 0 word s 2 OK Cancel Apply Figure 93 Random contents of a range of addresses E ram_tb dpram1 mem 00000000 06 03 00000002 7a 1b 00000004 1c 1d 00000006 92 40 00000008 04 31 00000002 0000000 24 25 0000000e 26 27 i TUE Rp cute ieee ETD um Sram 35 gimem ModelSim SE Tutorial T 110 Lesson 9 Viewing and initializing memories 3 Change contents by highlighting Figure 94 Changing contents by highlighting You can also change data by highlighting them in the Address Data pane amp ram_tb dpram1 mem 00000000 a Highlight the data for the addresses 0x0000000c 0x0000000e as shown 00000002 00000004 in Figure 94 00000006 00000008 b Right click the highlighted data and select Change 0000000a o000000 0000000e This brings up the Change dialog box Figure 95 Note that the Addresses field is already populated with the range you highlighted Select Value as the Fill Type d Enter the data values into the Fill Data field as follow 34 35 36 e Click OK EI The data in the address locations change to the values you entered Figure 96 Figure 95 Entering data to change 4 Edit data in place Viglen tb dpram1 mem To edit only one value at a time do the following Address Range Fill Type p Doub
87. es for this lesson The sample design for this lesson consists of a finite state machine which controls a behavioral memory The testbench fest sm provides stimulus The ModelSim installation comes with Verilog and VHDL versions of this design The files are located in the following directories Verilog install dir modeltech examples coverage verilog VHDL install dir modeltech examples coverage vhdl This lesson uses the Verilog version in the examples If you have a VHDL license use the VHDL version instead When necessary we distinguish between the Verilog and VHDL versions of the design Related reading ModelSim User s Manual Chapter 13 Measuring code coverage UM 335 ModelSim SE Tutorial Compiling the design Enabling Code Coverage is a two step process first you compile the files and identify which coverage statistics you want second you load the design and tell ModelSim to produce those statistics 1 Create a new directory and copy the tutorial files into it Start by creating a new directory for this exercise in case other users will be working with these lessons Create the directory and copy all files from lt install_dir gt modeltech examples coverage verilog to the new directory If you have a VHDL license copy the files in lt install_dir gt modeltech examples coverage vhdl instead Start ModelSim and change to the exercise directory If you just finished the previous lesson Mod
88. ew directory for this exercise in case other users will be working with these lessons Create the directory and copy all files from lt install_dir gt examples memory verilog to the new directory If you have a VHDL license copy the files in lt install_dir gt examples memory vhdl instead Start ModelSim and change to the exercise directory If you just finished the previous lesson ModelSim should already be running If not start ModelSim a Type vsim at a UNIX shell prompt or use the ModelSim icon in Windows If the Welcome to ModelSim dialog appears click Close b Select File gt Change Directory and change to the directory you created in step 1 Create the working library and compile the design a Type vlib work at the ModelSim gt prompt b Verilog Type vlog sp syn ram v dp syn ram v ram tb v at the ModelSim gt prompt VHDL Type vcom 93 sp syn ram vhd dp syn ram vhd ram tb vhd at the ModelSim gt prompt Load the design a On the Library tab of the Main window Workspace click the icon next to the work library b Double click the ram tb design unit to load the design Compiling and loading the design T 101 ModelSim SE Tutorial T 102 Lesson 9 Viewing and initializing memories Viewing a memory Memories can be viewed via the ModelSim GUI 1 Open a Memory instance a Select View gt Debug Windows gt Memory The Memories tab opens in the Workspace pane Figure 78 and lists the
89. f t out changes in the Dataflow window d Move the cursor to a time when f out is unknown e g 2724 ns 2 Tracethe unknown a Dataflow window make sure t out is selected and then select Trace gt ChaseX The design expands to show the source of the unknown Figure 75 In this case there is a HiZ U in the VHDL version on input signal test in and a 0 on input signal rw bar rw in the VHDL version so output signal test2 resolves to an unknown Scroll to the bottom of the Wave window and you will see that all of the signals contributing to the unknown value have been added 3 Clearthe Dataflow window before continuing Tracing an X unknown Figure 74 A signal with unknown values default top p tdy top p addr ftop p rw Atop p stib top p data 4top p addr_r Atop p data Atop p rw top p stib top p verbose top p t_out top p t set Atop p rw out sim top p t out 2784 ns top p test 521 IB xi File Edit View Navigate Trace Tools Window amp x adi X OS Aie e HILL DBA Bo mj 1 AND 23 rw NOR 49 E E SGT test2 bl test in mE val mU yl pas 8 amp 4 amp BA hx 4 top p t_out 2785 ns af n af Extended mode enabled Keep 1 hop pitest2 z T 95 ModelSim SE Tutorial T 96 Lesson 8 Debugging with the Dataflow window Displaying hie
90. fference find next difference find next annotated difference find last difference Use these icons to move the selected cursor The compare icons cycle through differences on all signals To view differences for just the selected signal use lt tab gt and lt shift gt lt tab gt Figure 129 Comparison information in the Main window Viewing comparison data T 151 Instance Design unit test_sm 711 illegal op received dataset open C modeltech examples co mpare verilog gold wlf gold 3 C modeltech examples compare verilo g gold wlf opened as dataset gold compare start gold sim compare options track compare add recursive all wave Created 11 comparisons compare run Computing waveform differences from ti me Ops to 750 ns Found 12 differences IVSIM 14 gt No Data No Dat o Dat No Data default sim test_sm rd_ sim test_sm wr_ compare test_sm compare sm compare sm compare test compare test sm compare test sm r compare test sm compare compare sm r compare test sm l compare sm i No Data No Data No Data No Data No Data No Data No Data No Data No Data Figure 131 The compare icons ie le le ModelSim SE Tutorial T 152 Lesson 13 Wave
91. form Compare Viewing comparison data in the List window You can also view the results of your waveform comparison in the List window 1 Add comparison data to the List window a Select View gt Debug Windows gt List from the Main window menu bar b Drag the test sm comparison object from the compare tab of the Main window to the List window Scroll down the window Differences are noted with yellow highlighting Figure 132 Differences that have been annotated have red highlighting ModelSim SE Tutorial Figure 132 Compare differences in the List window File Edit View Tools Window Psy deltay 30000 35000 100000 110000 115000 120000 130000 135000 140000 150000 151000 155000 160000 170000 171000 compare test_su into lt into El 0 00000000000000000000000000000000 00000000000000000000000000000000 0 00100000000000000000000000000000 00100000000000000000000000000000 0 00100000000000000000000000000000 00100000000000000000000000000000 0000 0 00100000000000000000000000000000 00100000000000000000000000000000 0 00000000000000000000000000010000 00000000000000000000000000010000 0000 0 00000000000000000000000000010000 00000000000000000000000000010000 0000 0 00000000000000000000000000010000 00000000000000000000000000010000 0 0 0 L 0 00100000000000000000000000000000 00100000000000000000000000000000 0000 0 0010000000000000000000000
92. gnalksc dt sc uint 20 gt storage sc signal bool expected sc signalcbool dataerror sc signak bool actual EDI counter ringbuf ring INST test ringbuf amp operator test_ringbuf const amp test ringbuf test ringbuf const amp void reset generator void generate data void compare data void print error void print restore Viewing SystemC objects in the GUI T 63 Removing a breakpoint Figure 46 SystemC primitive channels in the Wave window sr 1 Right click the red sphere in the Source window and select Remove Breakpoint test ringbuf counter test ringbuf reset ringbuf t da 2 Click the Continue Run button again test ringbul nda The simulation runs for 500 ns and waves are drawn in the Wave window ringbuf t c Figure 46 test ringbuf outstrobe false test_tingbuf pseudo 00000000000000000 If you are using the VHDL version you might see warnings in the Main test_tingbuf storage 000000000000000010 window transcript These warnings are related to VHDL value test_tingbuf expected conversion routines and can be ignored ftest_ringbuf dataerror true test_ringbuf actual ModelSim SE Tutorial T 64 Lesson 5 Simulating designs with SystemC Lesson Wrap up This concludes the lesson Before continuing we need to quit the C debugger and end the current simulation 1 Select Tools gt C Debug gt Quit C Debug 2 S
93. gt End Simulation Click Yes ModelSim SE Tutorial Lesson 8 Debugging with the Dataflow window Topics The following topics are covered in this lesson Introduction Related reading Compiling and loading the design Exploring connectivity Tracing events Tracing an X unknown Displaying hierarchy in the Dataflow window Lesson Wrap up gt Note The functionality described in this tutorial requires a dataflow license feature in your ModelSim license file Please contact your Mentor Graphics sales representative if you currently do not have such a feature T 90 T 90 T 91 T 92 T 93 T 95 T 96 T 97 T 89 ModelSim SE Tutorial T 90 Lesson 8 Debugging with the Dataflow window Introduction The Dataflow window allows you to explore the physical connectivity of your design to trace events that propagate through the design and to identify the cause of unexpected outputs The window displays processes signals nets and registers and interconnect Design files for this lesson The sample design for this lesson is a testbench that verifies a cache module and how it works with primary memory A processor design unit provides read and write requests The pathnames to the files are as follows Verilog lt install_dir gt modeltech examples dataflow verilog VHDL lt install_dir gt modeltech examples dataflow vhdl This lesson uses the Verilog version in the examples If you have a VH
94. gure 65 The counter waveform reacts to the created stimulus patterns Im default File Edit View Insert Format Tools Window x amp amp A hx i 4 Edit counter clk 4 Edit counter reset St0 Cursor 1 ni E sim counter count 000001 o ns to 1518 ns Now 1us Delta 1 ModelSim SE Tutorial T 86 Lesson 7 Creating stimulus with Waveform Editor Simulating with the testbench file Earlier in the lesson you exported the created waveforms to a testbench file In this exercise you will compile and load the testbench and then run the simulation 1 Compile and load the testbench a Atthe ModelSim prompt enter vlog export v or vcom export vhd if you are working with VHDL files You should see a design unit named export appear in the Library tab Figure 66 b Double click export on the Library tab to load the design 2 Add waves and run the design a Atthe VSIM prompt type add wave b Next type run 1000 The waveforms in the Wave window match those you saw in the last exercise Figure 67 3 Quitthe simulation a Inthe Main window select Simulate gt End Simulation and click Yes to confirm you want to quit simulating ModelSim SE Tutorial Figure 66 The export testbench compiled into the work library Library work Module C modeltech export Module Uri test_counter Module vital2000 Library ieee Library Il modelsi
95. he right of a transition Figure 51 The cursor doesn t snap to a transition if you drag in the cursor pane ModelSim SE Tutorial Using cursors in the Wave window 71 2 Rename the cursor Figure 52 Renaming a cursor a Right click Cursor 1 in the cursor name pane and select and delete the LC O text Figure 5 2 File Edit View Insert Format Tools Window b Type A and press Enter The cursor name changes to A 4 test_counter clk 4 test_counter reset cox o c7 A A 3 Jump the cursor to the next or previous transition a Click signal count in the pathname pane a Click the Find Next Transition icon on the Wave window toolbar The cursor jumps to the next transition on the currently selected signal b Click the Find Previous Transition icon on the Wave window toolbar The cursor jumps to the previous transition on the currently selected x wave default E loj x si gnal File Edit View Insert Format Tools Window Working with multiple cursors amp amp S amp A hJX 4 test_counter clk 1 Adda second cursor 4 counter reset a Click the Add Cursor icon on the Wave window toolbar b Right click the name of the new cursor and delete the text Type B and press Enter d Drag cursor B and watch the interval measurement change dynamically Figure 53 ni ModelSim SE Tutorial T 72 Lesson 6 Viewing simulations in
96. he testbench a Select File gt Open and open fest sm v b Scroll to line 122 which looks like this posedge clk wt wd hl0 haa c Change the data pattern to ab posedge clk wt wd h10 hab d Select File Save to save the file 2 Compile the revised file and rerun the simulation a Type do sec sim do at the ModelSim gt prompt The DO file does the following e Re compiles the testbench Adds waves to the Wave window e Runs the simulation ModelSim SE Tutorial VHDL 1 Edit the testbench a b d Select File gt Open and open test sm vhd Scroll to line 151 which looks like this wt wd 16 10 16 aa clk into Change the data pattern aa to ab wt_wd 16 10 16 ab clk into Select File gt Save to save the file 2 Compile the revised file and rerun the simulation a Type do sec_sim do at the ModelSim gt prompt The DO file does the following e Re compiles the testbench e Adds waves to the Wave window e Runs the simulation Creating the test dataset T 149 ModelSim SE Tutorial T 150 Lesson 13 Waveform Compare Com pari ng the simulation runs Figure 127 First dialog of the Comparison Wizard ModelSim includes a Comparison Wizard that walks you through the process quee ie ox You can also configure the comparison manually with menu or command line Hs lat la reference Reference Dataset commands and test datasets wlf files
97. hermore the Source window contains statistics of its own 1 View coverage statistics for test_sm in the Source window a sure fest sm is selected in the sim tab of the Workspace b Inthe Statement tab of the Missed Coverage pane expand fest sm v if necessary and select any line Figure 113 The Source window opens in the MDI frame with the line you selected highlighted Figure 114 c Switch to the Source window The table below describes the various icons Icon Description wi test sm v into data endtask stop a Statement Condition Toggle 4 Branch Condition Expression Toggle green checkmark indicates a statement that has been executed red X indicates that a statement in that line has not been executed zero hits Figure 114 Coverage statistics in the Source window green E indicates a line that has been excluded from code coverage statistics red or indicates that a true or false branch respectively of a conditional statement has not been executed In C modeltech examples coverage verlog test sm v 30 begin X 31 5 into 4 b0001 28 b0 c X 32 G posedge clk X 33 5 into data 34 end al h beh sram v h sm seqv h test sm v ModelSim SE Tutorial T 130 Lesson 11 Simulating with Code Coverage d Hover your mouse pointer over a line of code with a green checkmark Figure 115 Coverage numbers shown
98. his lesson The sample design for this lesson uses a DRAM behavioral model and a self checking testbench The DRAM controller interfaces between the system processor and the DRAM and must be periodically refreshed in order to provide read write and refresh memory operations Refresh operations have priority over other operations but a refresh will not preempt an in process operation The ModelSim installation comes with Verilog and VHDL versions of this design The files are located in the following directories Verilog lt install_dir gt modeltech examples psl verilog VHDL lt install_dir gt modeltech examples psl vhdl This lesson uses the Verilog version for the exercises If you have a VHDL license use the VHDL version instead You can embed assertions within your code or supply them in a separate file This example design uses an external file Related reading ModelSim User s Manual Chapter 14 PSL Assertions Chapter 15 Functional coverage with PSL and ModelSim ModelSim SE Tutorial Compile the example design In this exercise you will use a DO file to compile the design 1 Create a new directory and copy the lesson files into it Start by creating a new directory for this exercise in case other users will be working with these lessons Create the directory and copy all files from lt install_dir gt examples psl verilog to the new directory If you have a VHDL license copy the files in lt install_
99. ic_orig cpp and adds include basic h ifdef MTI_SYSTEMC SC_MODULE_EXPORT top else OSCI sc_main code here endif basic h Includes everything in basic_orig h and adds the following OSCI SC_MODULE code here ifdef MTI_SYSTEMC SC_MODULE top sc_clock clk mod_a a SC_CTOR Lop tela eclk elk endif endif ModelSim SE Tutorial T 56 Lesson 5 Simulating designs with SystemC Compiling a SystemC only design With the edits complete you are ready to compile the design Designs that contain only SystemC code are compiled with sccom CR 256 1 Set the working library a Type vlib work in the ModelSim Transcript window to create the working library 2 Compile and link all SystemC files a sccom g basic cpp at the ModelSim gt prompt The g argument compiles the design for debug Upon successfully compiling the design the following message is issued to the screen Model Technology ModelSim sccom compiler 2003 05 May 25 2004 Exported modules top b sccom link at the ModelSim gt prompt to perform the final link on the SystemC objects You have successfully compile and linked the design The successful compilation verifies that all the necessary file modifications have been entered correctly In the next exercise you will compile and load a design that includes both SystemC and HDL code ModelSim SE Tutorial Mixed SystemC and HDL ex
100. ied in the DO file ModelSim SE Tutorial T 166 Lesson 14 Automating ModelSim Lesson Wrap up This concludes this lesson 1 Select File gt Quit to close ModelSim ModelSim SE Tutorial End User License Agreement IMPORTANT USE OF THIS SOFTWARE IS SUBJECT TO LICENSE RESTRICTIONS CAREFULLY READ THIS LICENSE AGREEMENT BEFORE USING THE SOFTWARE This license is a legal Agreement concerning the use of Software between you the end user either individually or as an authorized representative of the company acquiring the license and Mentor Graphics Corporation and Mentor Graphics Ireland Limited acting directly or through their subsidiaries or authorized distributors collectively Mentor Graphics USE OF SOFTWARE INDICATES YOUR COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH IN THIS AGREEMENT If you do not agree to these terms and conditions promptly return or if received electronically certify destruction of Software and all accompanying items within five days after receipt of Software and receive a full refund of any license fee paid END USER LICENSE AGREEMENT GRANT OF LICENSE The software programs you are installing downloading or have acquired with this Agreement including any updates modifications revisions copies documentation and design data Software are copyrighted trade secret and confidential information of Mentor Graphics or its licensors who maintain exclusive
101. ile Edit View Format Compile Simulate Add Tools Window Help counter v P Verilog 1 11 29 04 07 33 30 tcounter v Verilog 11229204 07 33 30 move up down buttons ModelSim SE Tutorial T 36 Lesson 3 ModelSim projects Compiling and loading a design Figure 19 The Library tab with an expanded library 1 Compile the files a Right click anywhere in the Project tab and select Compile gt Compile Library C modeltech examples wo All from the pop up menu N Module C modeltech examples co Module C modeltech examples tccl ModelSim compiles both files and changes the symbol in the Status Library MODEL_TECH vital200 column to a check mark A check mark means the compile succeeded If Libraty MODEL_TECH ieee the compile had failed the symbol would be a red X and you would r Librar M CH Pm see an error message in the Transcript pane mi std MODEL_TECH std 1 00 2 View the design units a Click the Library tab in the workspace b Click the icon next to the work library You should see two compiled design units their types modules in this case and the path to the underlying source files Figure 19 3 Load the test counter design unit a Double click the fest counter design unit You should see a new tab named sim that displays the structure of the test counter design unit Figure 20 A fourth tab named Files contains information about the under
102. im adds all objects from the current region b Run simulation for awhile so you can see waveforms ModelSim SE Tutorial Zooming the waveform display T 69 Zooming the wavefo rm d isplay Figure 49 Zooming in with the mouse pointer wave default 101 x Zooming lets you change the display range in the waveform pane There are File Edit View Insert Format Tools Window numerous methods for zooming the display 1 Zoom the display using various techniques test_counter clk dtest_counter reset counter count EL b In the waveform pane click and drag down and to the right a Click the Zoom Mode icon on the Wave window toolbar You should see blue vertical lines and numbers defining an area to zoom in Figure 49 c Select View gt Zoom gt Zoom Last The waveform pane returns to the previous display range mi d Click the Zoom In 2x icon a few times e In the waveform pane click and drag up and to the right You should see a blue line and numbers defining an area to zoom out Figure 50 4 counter clk 4 test_counter teset fe fest counter count O0 100000110 00000111 f Select View gt Zoom gt Zoom Full E 102 ns to 240 ns Now 400 ns Delta 2 ModelSim SE Tutorial T 70 Lesson 6 Viewing simulations in the Wave window Usi ng cursors in the Wave windo
103. ing the working design library T 21 Figure 1 The Welcome to ModelSim dialog IMPORTANT Information Ol x Model gt Welcome to ModelSim 6 0 eo IMPORTANT Information Key Information ModelSim platform changes Product Changes Changes in ModelSim functionality New Features The latest ModelSim features ModelSim 6 0 Application Notes Performance Guidelines Taking Advantage of SystemVerilog The ModelSim Debug GUI SystemC Verification Comparing PSL and OVL Verilog 2001 Ready For Use E Select J tart t AZ Jumpstart M Ciose Figure 2 The Create a New Library dialog Create a New Library EE x Create Ca Don t show this dialog again C to an existing library Library Name work 3b Library Physical Name work d Cancel ModelSim SE Tutorial T 22 Lesson 2 Basic simulation c Click OK Figure 3 The newly created work library v ModelSim File Edit View Format Compile Simulate Add Tools Window Help ModelSim creates a directory called work and writes a specially formatted file named info into that directory The _info file must remain in the directory to distinguish it as a ModelSim library Do not edit the folder contents from your operating system all changes should be made from within ModelSim ModelSim also adds the library to the list in the Workspac
104. ing their types Inspect the list to discover that the type for dataerror is boolean sc logic for VHDL and counter is integer Figure 45 b examine dataerror at the CDBG gt prompt The value returned is true 2 View the value of a SystemC variable a Typeexamine counter at the CDBG prompt to view the value of this variable The value returned is 1 ModelSim SE Tutorial Figure 44 ModelSim steps into a function in a separate file 556 get the negative edge event 557 virtual const sc event amp negedge_event const 558 return m negedge event 559 560 561 read the current value 562 virtual const bool amp read const 563 return m cur val 564 565 get a reference to the current value for tracing 566 virtual const bool amp get data const 567 return m cur val 568 569 570 was there a value changed event E 3 bus m 1 baal Arrant 8 n RE SSSR nj al wave C C test_ringbufh C sc_signalh Figure 45 Output of show command CDBG 22 gt show ptype this type class test_ringbuf public sc module HHHHHHHHHHHHHHHHHHHHHH public struct sc clock clock sc event reset deactivation event sc signal bool reset sc_signal lt bool gt t da sc_signal lt bool gt r da sc_signal lt bool gt t c sc signal bool outstrobe sc signaksc dt sc uint 20 gt pseudo sc si
105. iscuss any malfunctions or suggested improvements Upon completion of your evaluation and testing you will send to Mentor Graphics a written evaluation of the Beta Code including its strengths weaknesses and recommended improvements You agree that any written evaluations and all inventions product improvements modifications or developments that Mentor Graphics conceived or made during or subsequent to this Agreement including those based partly or wholly on your feedback will be the exclusive property of Mentor Graphics Mentor Graphics will have exclusive rights title and interest in all such property The provisions of this subsection shall survive termination or expiration of this Agreement 4 RESTRICTIONS ON USE You may copy Software only as reasonably necessary to support the authorized use Each copy must include all notices and legends embedded in Software and affixed to its medium and container as received from Mentor Graphics All copies shall remain the property of Mentor Graphics or its licensors You shall maintain a record of the number and primary location of all copies of Software including copies merged with other software and shall make those records available to Mentor Graphics upon request You shall not make Software available in any form to any person other than employees and contractors excluding Mentor Graphics competitors whose job performance requires access You shall take appropriate action to protect the confidentialit
106. l with ModelSim T 165 These commands do the following Figure 137 Buttons added to the Main window toolbar T sce ME e Use a when statement to identify when clk transitions to 1 File Edit View Format Compile Simulate Add Tools Window Help Examine the value of count at those transitions and add a bookmark if itis a certain value script with the name add_bkmrk do EMM test_counter test_counter Module 2 2 M dut counter Module Save it into the directory you created in Lesson 2 Basic simulation IMPLICIT WIRE tes test counter Process HIMPLICIT WIRE cIk test counter Process SINITIALHT lest counter Process 2 Load the fest counter design unit D sNITIALN23 ipu Piocess HINITIALH3O test_counter Process a Start ModelSim b Select File gt Change Directory and change to the directory you saved the DO file to in step 1c above c In the Library tab of the Main window expand the work library and double click the test_counter design unit 3c 3 Execute the DO file and run the design Type do add bkmrk do at the VSIM gt prompt b Type run 1500 ns at the VSIM gt prompt The simulation runs and the DO file creates two bookmarks It also creates buttons labeled 1 and 2 on the Main window toolbar that jump to the bookmarks Figure 137 c Click the buttons and watch the Wave window zoom on and scroll to the time when count is the value specif
107. lation 1 Load the fest counter design unit a b If necessary start ModelSim Change to the directory you created in Lesson 2 Basic simulation In the Library tab of the Workspace pane double click the test_counter design unit to load it 2 Enter commands to add signals to the Wave window force signals and run the simulation a a Select File gt New gt Source gt Do to create a new DO file Enter the following commands into the source window add wave count add wave clk add wave reset force freeze clk 0 0 1 50 ns r 100 force reset 1 run 100 force reset 0 run 300 force reset 1 run 400 force reset 0 run 200 3 Save the file a b Select File gt Save As Type sim do in the File name field and save it to the current directory Creating a simple DO file T 159 ModelSim SE Tutorial T 160 Lesson 14 Automating ModelSim 4 Load the simulation again and use the DO file a quit sim at the VSIM gt prompt b Type vsim test counter at the ModelSim gt prompt c do sim do at the VSIM gt prompt ModelSim executes the saved commands and draws the waves in the Wave window 5 When you are done with this exercise select File gt Quit to quit ModelSim ModelSim SE Tutorial Running ModelSim in command line mode We use the term command line mode to refer to simulations that are run from a DOS UNIX prompt without invoking the GUI Several ModelSim commands
108. le click any value in the Data column A t b Enter the desired value and press lt Enter gt AA Start p000000c End 0000000 re c When you are finished editing all values press the lt Enter gt key on your SEN keyboard to exit the editing mode Fil Data Skip 8d If you needed to cancel the edit function press the Esc key on your o word s keyboard Cancel Apply Figure 96 Changed contents for specified addresses ES ram_tb dpram1 mem 00000000 00000002 00000004 00000006 00000008 00000002 0000000c 0000000e 27 Tcl eset tn ee e RISUS SES SRN I nn ModelSim SE Tutorial Lesson Wrap up T 111 Lesson Wrap up This concludes this lesson Before continuing we need to end the current simulation 1 Select Simulate gt End Simulation Click Yes ModelSim SE Tutorial T 112 Lesson 9 Viewing and initializing memories ModelSim SE Tutorial Lesson 10 Analyzing performance with the Profiler Topics The following topics are covered in this lesson Introduction ids lx Design files for this lesson Related reading Compiling and loading the design Running the simulation View Profile Details Filtering and saving the data Lesson wrap up gt Note The functionality described in this tutorial requires a profile license feature in your ModelSim license file Please contact your Mentor Gra
109. lying source files L Module counter Module jd IMPLICIT WIRE res test counter Process HIMPLICIT WIRE clk test counter Process HINITIALHI7 test_counter Process INITIALH23 test_counter Process HINITISLH30 test_counter Process At this point you would generally run the simulation and analyze or debug your design like you did in the previous lesson For now you ll continue working with the project However first you need to end the simulation that started when you loaded fest counter 4 Endthe simulation a Select Simulate End Simulation b Click Yes ModelSim SE Tutorial Organizing projects with folders If you have a lot of files to add to a project you may want to organize them in folders You can create folders either before or after adding your files If you create a folder before adding files you can specify in which folder you want a file placed at the time you add the file see Folder field in Figure 16 If you create a folder after adding files you edit the file properties to move it to that folder Adding folders As shown previously in Figure 15 the Add items to the Project dialog has an option for adding folders If you have already closed that dialog you can use a menu command to add a folder 1 Add a new folder a Select File gt Add to Project gt Folder b Design Files in the Folder Name field Figure 21 c Click OK You ll now see a folder in the Projec
110. m lib Library MODEL TEC m nn lihre ANDEI rer 7 ad a Ji pi Figure 67 Waves from the newly created testbench Im default File Edit View Insert Format Tools Window E4 expoit count 0 10 a yoo 00 4 Jjewpott clk 4 export reset Ons 1518 ns Now 1 us Delta 1 Z Importing an EVCD file Earlier in the lesson you exported the created waveforms to an extended VCD file In this exercise you will use that file to stimulate the counter design unit 1 Load the counter design unit and add waves a Double click counter on the Library tab b Inthe Objects pane right click count and select Add to Wave gt Selected Signals 2 Import the VCD file a Inthe Wave window select File gt Import EVCD b Double click export vcd The created waveforms draw in the Wave window c Click the Run All icon The simulation runs for 1000 ns and the waveform is drawn for sim counter count When you import an EVCD file signal mapping happens automatically if signal names and widths match If they do not you have to manually map the signals See Signal mapping and importing EVCD files GR 295 for more information Importing an EVCD file T 87 ModelSim SE Tutorial T 88 Lesson 7 Creating stimulus with Waveform Editor Lesson wrap up This concludes this lesson Before continuing we need to end the current simulation 1 In the Main window select Simulate
111. m library format is compatible across all supported platforms You can simulate your design on any platform without having to recompile your design Running the simulation With the design compiled you invoke the simulator on a top level module Verilog or a configuration or entity architecture pair VHDL Assuming the design loads successfully the simulation time is set to zero and you enter a run command to begin simulation ModelSim SE Tutorial T 14 Lesson 1 ModelSim conceptual overview Debugging your results If you don t get the results you expect you can use ModelSim s robust debugging environment to track down the cause of the problem ModelSim SE Tutorial Project flow T 15 Project flow A project is a collection mechanism for an HDL design under specification or test Even though you don t have to use projects in ModelSim they may ease interaction with the tool and are useful for organizing files and specifying simulation settings The following diagram shows the basic steps for simulating a design within a ModelSim project As you can see the flow is similar to the basic simulation flow However there are two important differences You do not have to create a working library in the project flow it is done for you automatically Projects are persistent In other words they will open every time you invoke ModelSim unless you specifically close them ModelSim SE Tutorial T 16 Lesson 1 ModelSim co
112. n Aside from executing a couple of pre existing DO files the previous lessons focused on using ModelSim in interactive mode executing single commands one after another via the GUI menus or Main window command line In situations where you have repetitive tasks to complete you can increase your productivity with DO files DO files are scripts that allow you to execute many commands at once The scripts can be as simple as a series of ModelSim commands with associated arguments or they can be full blown Tcl programs with variables conditional execution and so forth You can execute DO files from within the GUI or you can run them from the system command prompt without ever invoking the GUI A Important This lesson assumes that you have added the install dir modeltech platform directory to your PATH If you did not you will need to specify full paths to the tools i e vlib vmap vlog vcom and vsim that are used in the lesson Related reading ModelSim User s Manual 20 Tcl and macros DO files UM 225 Practical Programming in Tcl and Tk Brent B Welch Copyright 1997 ModelSim SE Tutorial Creating a simple DO file Creating DO files is as simple as typing the commands ina text file Alternatively you can save the Main window transcript as a DO file In this exercise you will use the transcript to create a DO file that adds signals to the Wave window provides stimulus to those signals and then advances the simu
113. n 11 Simulating with Code Coverage T 123 Lesson 12 Debugging with PSL assertions T 135 Lesson 13 Waveform Compare T 145 T 3 ModelSim SE Tutorial T 4 ModelSim SE Tutorial Introduction Topics The following topics are covered in this chapter Assumptions Where to find our documentation Technical support and updates Before you begin Example designs T 6 T 8 T 9 T 9 ModelSim SE Tutorial T 6 Introduction Assumptions We assume that you are familiar with the use of your operating system You should be familiar with the window management functions of your graphic interface either OpenWindows OSF Motif CDE KDE GNOME or Microsoft Windows 98 Me NT 2000 XP We also assume that you have a working knowledge of VHDL Verilog and or SystemC Although ModelSim is an excellent tool to use while learning HDL concepts and practices this document is not written to support that goal ModelSim SE Tutorial Where to find our documentation T 7 Where to find our documentation ModelSim documentation is available from our website at www model com support or in the following formats and locations Document Format How to get it ModelSim Installation amp Licensing Guide paper shipped with ModelSim PDF select Help gt Documentation also available from the Support page of our web site www model com
114. nceptual overview Multiple library flow ModelSim uses libraries in two ways 1 as a local working library that contains the compiled version of your design 2 as a resource library The contents of your working library will change as you update your design and recompile A resource library is typically static and serves as a parts source for your design You can create your own resource libraries or they may be supplied by another design team or a third party e g a silicon vendor You specify which resource libraries will be used when the design is compiled and there are rules to specify in which order they are searched A common example of using both a working library and a resource library is one where your gate level design and testbench are compiled into the working library and the design references gate level models in a separate resource library The diagram below shows the basic steps for simulating with multiple libraries You can also link to resource libraries from within a project If you are using a project you would replace the first step above with these two steps create the project and add the testbench to the project ModelSim SE Tutorial Debugging tools T 17 Debugging tools ModelSim offers numerous tools for debugging and analyzing your design Several of these tools are covered in subsequent lessons including Setting breakpoints and stepping through the source code Viewing waveforms and measuring time
115. nch and extended VCD file Run the simulation Re simulate using the exported testbench and VCD file Related reading ModelSim User s Manual 10 Generating stimulus with Waveform Editor UM 225 ModelSim GUI Reference Wave window GR 216 ModelSim SE Tutorial Loading a design unit For the examples in this lesson we will use part of the design simulated in Lesson 2 Basic simulation gt Note You can also use Waveform Editor prior to loading a design See Using Waveform Editor prior to loading a design GR 287 in the ModelSim GUI Reference for more information 1 Ifyou just finished the previous lesson ModelSim should already be running If not start ModelSim a Type vsim at a UNIX shell prompt or use the ModelSim icon in Windows If the Welcome to ModelSim dialog appears click Close 2 Load the counter design unit a Select File gt Change Directory and open the directory you created in Lesson 2 The work library should already exist b Click the icon next to the work library and double click counter ModelSim loads the counter design unit and adds sim and Files tabs to the Workspace Loading a design unit T 77 ModelSim SE Tutorial T 78 Lesson 7 Creating stimulus with Waveform Editor Creating waves with a wizard Waveform Editor includes a Create Pattern wizard that walks you through the process of creating editable waveforms 1 Use the Create Pattern wizard to create a
116. ndow b Ifthe Objects pane isn t open already select View gt Debug Windows gt Objects Scroll to the right and you will see the various toggle coverage columns Figure 116 The blank columns would show data if you had enabled extended toggle coverage Viewing toggle statistics in the Objects pane T 131 Figure 116 Toggle coverage columns in the Source window HToggled Toggled 01 Full Z D 3 s 71870 12493 2 50000 12493 395271 15621 0 12499 1 50000 39 t M MD 11 18 5 100 100 100 100 ModelSim SE Tutorial T 132 Lesson 11 Simulating with Code Coverage Excluding lines and files from coverage statistics ModelSim allows you to exclude lines and files from code coverage statistics You can set exclusions with the GUI with a text file called an exclusion filter file or with pragmas in your source code Pragmas are statements that instruct ModelSim to not collect statistics for the bracketed code See Excluding objects from coverage UM 348 for more details on exclusion filter files and pragmas 1 Display the Current Exclusions pane if necessary a Select View Code Coverage Current Exclusions 2 Exclude a line via the Missed Coverage pane a Right click a line in the Missed Coverage pane and select Exclude Selection You can also exclude the selection for the current instance only by selecting Exclude Selection For Instance lt ins
117. ng directive and handles the code appropriately For more information on these modifications see Modifying SystemC source code UM 164 in the ModelSim User s Manual 1 Create a new directory and copy the tutorial files into it Start by creating a new directory for this exercise in case other users will be working with these lessons Create the directory then copy all files from install dir modeltech examples systemc sc basic into the new directory 2 Start ModelSim and change to the exercise directory If you just finished the previous lesson ModelSim should already be running If not start ModelSim a Type vsim at a UNIX shell prompt or use the ModelSim icon in Windows If the Welcome to ModelSim dialog appears click Close b Select File gt Change Directory and change to the directory you created in step 1 ModelSim SE Tutorial 3 Use a text editor to view and edit the basic_orig cpp file To use ModelSim s editor from the Main Menu select File gt Open Change the files of type to C C files then double click basic_orig cpp The red highlighted code in the _orig files Figure 36 indicates the section of the code that needs modification a Using the ifdef MTI_SYSTEMC preprocessor directive add the SC_MODULE_EXPORT top to the design see Figure 36 Close the preprocessing directive with else The original code in the cpp file follows directly after else End that section of the file with endif
118. ng objects to the Wave window In this itest counter ck x 4 test_counter reset EA test counter count exercise you will try different methods 1 Add objects from the Objects pane a Selectan item in the Objects pane of the Main window right click and then select Add to Wave Signals in Region ModelSim adds several signals to the Wave window 2 Undock the Wave window By default ModelSim opens Wave windows as a tab in the MDI frame of the Cursor 1 Main window You can change the default via the Preferences dialog Tools gt Edit Preferences See ModelSim GUI preferences GR 272 in the ModelSim GUI amp Interface Reference for more information a Click the undock icon on the Wave pane Figure 48 The Wave pane becomes a standalone un docked window You will probably need to resize the window 3 Add objects using drag and drop You can drag an object to the Wave window from many other windows and panes e g Workspace Objects and Locals a Inthe Wave window select Edit gt Select All and then Edit gt Delete b Drag an instance from the sim tab of the Main window to the Wave window ModelSim adds the objects for that instance to the Wave window c Drag a signal from the Objects pane to the Wave window d Inthe Wave window select Edit gt Select All and then Edit gt Delete 4 Add objects using a command a Type add wave at the VSIM gt prompt ModelS
119. ngement by you that is deemed willful In the case of h you shall reimburse Mentor Graphics for its attorney fees and other costs related to the action upon a final judgment 9 4 THIS SECTION 9 STATES THE ENTIRE LIABILITY OF MENTOR GRAPHICS AND ITS LICENSORS AND YOUR SOLE AND EXCLUSIVE REMEDY WITH RESPECT TO ANY ALLEGED PATENT OR COPYRIGHT INFRINGEMENT OR TRADE SECRET MISAPPROPRIATION BY ANY SOFTWARE LICENSED UNDER THIS AGREEMENT TERM This Agreement remains effective until expiration or termination This Agreement will immediately terminate upon notice if you exceed the scope of license granted or otherwise fail to comply with the provisions of Sections 1 2 or 4 For any other material breach under this Agreement Mentor Graphics may terminate this Agreement upon 30 days written notice if you are in material breach and fail to cure such breach within the 30 day notice period If Software was provided for limited term use this Agreement will automatically expire at the end of the authorized term Upon any termination or expiration you agree to cease all use of Software and return it to Mentor Graphics or certify deletion and destruction of Software including all copies to Mentor Graphics reasonable satisfaction EXPORT Software is subject to regulation by local laws and United States government agencies which prohibit export or diversion of certain products information about the products and direct products of the products to certain coun
120. ns in Design Scroll to the bottom of the Wave window and you will see the assertions denoted by magenta triangles Select View gt Debug Windows gt Functional Coverage Main window to see cover directives in the Functional Coverage window Select the Functional Coverage pane Select Add gt Wave gt Functional Coverages in Design Scroll to the bottom of the Wave window and you will see the cover directives denoted by magenta triangles 5 Run the simulation a Type run all at the VSIM gt prompt Verilog The Main window transcript shows that the assert check refresh assertion in the dram_cntrl psl file failed at 3100 ns The simulation is stopped at that time Note that with no assertions the testbench did not report a failure until 267 400 ns over 80x the simulation time required for a failure to be reported with assertions VHDL The Main window transcript shows that the assert check refresh assertion in the dram cntrl psl file failed at 3800 ns The simulation is stopped at that time Note that with no assertions the testbench did not report a failure until 246 800 ns over 60x the simulation time required for a failure to be reported with assertions The Wave window displays a red triangle at the point of the simulation break and shows FAIL in the values column of the assert check refresh assertion Figure 121 The blue sections of the assertion waveforms indicate inactive assertions green indicates activ
121. odelSim SE Tutorial T 52 Lesson 5 Simulating designs with SystemC Introduction ModelSim treats SystemC as just another design language With only a few exceptions in the current release you can simulate and debug your SystemC designs the same way you do HDL designs Design files for this lesson There are two sample designs for this lesson The first is a very basic design called basic containing only SystemC code The second design is a ring buffer where the testbench and top level chip are implemented in SystemC and the lower level modules are written in HDL The pathnames to the files are as follows SystemC lt install_dir gt modeltech examples systemc sc_basic SystemC Verilog lt install_dir gt modeltech examples systemc sc_vlog SystemC VHDL lt install_dir gt modeltech examples systemc sc_vhdl This lesson uses the SystemC Verilog version of the ringbuf design in the examples If you have a VHDL license use the VHDL version instead There is also a mixed version of the design but the instructions here do not account for the slight differences in that version Related reading ModelSim User s Manual Chapter 6 SystemC simulation UM 159 Chapter 7 Mixed language simulation UM 187 Chapter 16 C Debug UM 401 ModelSim Command Reference sccom command CR 256 ModelSim SE Tutorial Setting up the environment SystemC is a licensed feature You need the systemc license feature in your Mod
122. odelSim commands However DO files are really just Tcl scripts This means you can include a whole variety of Tcl constructs such as procedures conditional operators math and trig functions regular expressions and so forth In this exercise you will create a simple Tcl script that tests for certain values on a signal and then adds bookmarks that zoom the Wave window when that value exists Bookmarks allow you to save a particular zoom range and scroll position in the Wave window The Tcl script also creates buttons in the Main window that call these bookmarks 1 Create the script a Ina text editor open a new file and enter the following lines proc add_wave_zoom stime num echo Bookmarking wave num bookmark add wave bk num expr stime 50 expr stime 100 0 add button num list bookmark goto wave bk num These commands do the following e Create a new procedure called add wave zoom that has two arguments stime and num e Create a bookmark with a zoom range from the current simulation time minus 50 time units to the current simulation time plus 100 time units e a button to the Main window that calls the bookmark b Now add these lines to the bottom of the script add wave r when clk event and clk 1 echo Count is exa count if exa count 00100111 add_wave_zoom Snow 1 elseif exa count 01000111 add_wave_zoom Snow 2 ModelSim SE Tutorial Using Tc
123. ompiling and loading the design 1 Create a new directory and copy the tutorial files into it Start by creating a new directory for this exercise in case other users will be working with these lessons Create the directory and copy all files from lt install_dir gt examples profiler verilog to the new directory If you have a VHDL license copy the files in lt install_dir gt examples profiler vhdl instead Start ModelSim and change to the exercise directory If you just finished the previous lesson ModelSim should already be running If not start ModelSim a Type vsim at a UNIX shell prompt or use the ModelSim icon in Windows If the Welcome to ModelSim dialog appears click Close b Select File gt Change Directory and change to the directory you created in step 1 Create the work library a Type vlib work at the ModelSim gt prompt Compile the design files a Verilog Type vlog test sm v sm seq v sm v beh sram v at the ModelSim gt prompt VHDL Type vcom 93 sm vhd sm seq vhd sm sram vhd test sm vhd at the ModelSim prompt Load the top level design unit a Type vsim test sm at the ModelSim gt prompt Compiling and loading the design T 115 ModelSim SE Tutorial T 116 Lesson 10 Analyzing performance with the Profiler Running the simulation You will now run the simulation and view the profiling data 1 Enable the statistical sampling profiler a Select Tools gt Profile gt Pe
124. on shall be deemed to be a warranty or give rise to any liability of Mentor Graphics whatsoever MENTOR GRAPHICS MAKES NO WARRANTY OF ANY KIND WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OR MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE MENTOR GRAPHICS SHALL NOT BE LIABLE FOR ANY INCIDENTAL INDIRECT SPECIAL OR CONSEQUENTIAL DAMAGES WHATSOEVER INCLUDING BUT NOT LIMITED TO LOST PROFITS ARISING OUT OF OR RELATED TO THIS PUBLICATION OR THE INFORMATION CONTAINED INIT EVEN IF MENTOR GRAPHICS CORPORATION HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES RESTRICTED RIGHTS LEGEND 03 97 U S Government Restricted Rights The SOFTWARE and documentation have been developed entirely at private expense and are commercial computer software provided with restricted rights Use duplication or disclosure by the U S Government or a U S Government subcontractor is subject to the restrictions set forth in the license agreement provided with the software pursuant to DFARS 227 7202 3 a or as set forth in subparagraph c 1 and 2 of the Commercial Computer Software Restricted Rights clause at FAR 52 227 19 as applicable Contractor manufacturer is Mentor Graphics Corporation 8005 S W Boeckman Road Wilsonville Oregon 97070 7777 This is an unpublished work of Mentor Graphics Corporation Contacting ModelSim Support Telephone 503 685 0820 Toll Free Telephone 877 744 6699 Website www model com Suppor
125. or that operation of Software will be uninterrupted or error free The warranty period is 90 days starting on the 15th day after delivery or upon installation whichever first occurs You must notify Mentor Graphics in writing of any nonconformity within the warranty period This warranty shall not be valid if Software has been subject to misuse unauthorized modification or installation MENTOR GRAPHICS ENTIRE LIABILITY AND YOUR EXCLUSIVE REMEDY SHALL BE AT MENTOR GRAPHICS OPTION EITHER A REFUND OF THE PRICE PAID UPON RETURN OF SOFTWARE TO MENTOR GRAPHICS OR B MODIFICATION OR REPLACEMENT OF SOFTWARE THAT DOES NOT MEET THIS LIMITED WARRANTY PROVIDED YOU HAVE OTHERWISE COMPLIED WITH THIS AGREEMENT MENTOR GRAPHICS MAKES NO WARRANTIES WITH RESPECT TO A SERVICES B SOFTWARE WHICH IS LICENSED TO YOU FOR A LIMITED TERM OR LICENSED AT NO COST OR C EXPERIMENTAL BETA CODE ALL OF WHICH ARE PROVIDED AS IS ModelSim SE Tutorial 5 2 THE WARRANTIES SET FORTH IN THIS SECTION 5 ARE EXCLUSIVE NEITHER MENTOR GRAPHICS NOR ITS LICENSORS MAKE ANY OTHER WARRANTIES EXPRESS IMPLIED OR STATUTORY WITH RESPECT TO SOFTWARE OR OTHER MATERIAL PROVIDED UNDER THIS AGREEMENT MENTOR GRAPHICS AND ITS LICENSORS SPECIFICALLY DISCLAIM ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE AND NON INFRINGEMENT OF INTELLECTUAL PROPERTY LIMITATION OF LIABILITY EXCEPT WHERE THIS EXCLUSION OR RESTRICTION OF LIABILITY WOULD BE VOID OR INEFFE
126. p B m Figure 69 Expanding the view to display connected processes En E File Edit View Navigate Trace Tools Window amp x od X DAAA nj ASSIGN 25 1 est NAND 50 pu Tracing events Another useful debugging feature is tracing events that contribute to an unexpected output value Using the Dataflow window s embedded wave viewer you can trace backward from a transition to see which process or signal caused the unexpected output 1 Add an object to the Dataflow window Make sure instance p is selected in the sim tab of the Main window b Drag signal t out from the Objects pane into the Dataflow window c Select View Show Wave in the Dataflow window to open the wave viewer Figure 70 You may need to increase the size of the Dataflow window and scroll the panes to see everything 2 Trace the inputs of the nand gate a Select process NAND 50 labeled line 71 in VHDL version in the dataflow pane All input and output signals of the process are displayed automatically in the wave viewer b Inthe wave view scroll to time 2785 ns the last transition of signal t out c Click on the last transition of signal t out to set a cursor Figure 71 Tracing events Figure 70 The embedded wave viewer pane SR GSH amp B OO A ke 3e EXE TZ E2918 dataflow E nl x File Edit View Navigate Trace Tools Window amp Bb m NAND 50 te
127. phics sales representative if you currently do not have such a feature T 114 T 114 T 114 T 115 T 116 T 119 T 120 T 122 T 113 ModelSim SE Tutorial T 114 Lesson 10 Analyzing performance with the Profiler Introduction The Profiler identifies the percentage of simulation time spent in each section of your code as well as the amount of memory allocated to each function and instance With this information you can identify bottlenecks and reduce simulation time by optimizing your code Users have reported up to 75 reductions in simulation time after using the Profiler This lesson introduces the Profiler and shows you how to use the main Profiler commands to identify performance bottlenecks Design files for this lesson The example design for this lesson consists of a finite state machine which controls a behavioral memory The testbench test_sm provides stimulus The ModelSim installation comes with Verilog and VHDL versions of this design The files are located in the following directories Verilog install dir modeltech examples profiler verilog VHDL install dir modeltech examples profiler vhdl This lesson uses the Verilog version for the exercises If you have a VHDL license use the VHDL version instead Related reading ModelSim User s Manual Chapter 12 Profiling performance and memory use UM 317 Chapter 20 Tcl and macros DO files UM 473 ModelSim SE Tutorial C
128. rarchy in the Dataflow win dow You can display connectivity in the Dataflow window using hierarchical instances You enable this by modifying the options prior to adding objects to the window 1 Change options to display hierarchy a Select Tools gt Options from the Dataflow window menu bar b Check Show Hierarchy and then click OK Figure 76 2 Add signal t_out to the Dataflow window a Type add dataflow top p t out at the VSIM gt prompt The Dataflow window will display t_out and all hierarchical instances Figure 77 ModelSim SE Tutorial Figure 76 The Dataflow options dialog xi General options Warning options Hide cells Keep Dataflow Beep dai Show Hierarchy Hus side i Bottom inout pins Disable Sprout Select equivalent nets Lognets Select Environment Automatic Add to Wave Figure 77 Dataflow window displaying with hierarchy dataflow 1512 File Edit View Navigate Trace Tools Window Si Bt BBQ dA Ke Kc 3C 9 AWA X 1 Bo mi BAAUAND SO out Lesson Wrap up T 97 Lesson Wrap up This concludes this lesson Before continuing we need to end the current simulation 1 Type quit sim at the VSIM gt prompt ModelSim SE Tutorial T 98 Lesson 8 Debugging with the Dataflow window ModelSim SE Tutorial Lesson 9 Viewing and initializing memories Topics The following topics are co
129. reakpoint It will become a red ball c Click the red ball with your right mouse button and select Remove Breakpoint 36 d Click on line number 36 again to re create the breakpoint 4 Restart the simulation a Click the Restart icon to reload the design elements and reset the simulation time to zero The Restart dialog that appears gives you options on what to retain during the restart Figure 11 b Click Restart in the Restart dialog Setting breakpoints and stepping in the Source window T 27 Figure 10 A breakpoint in the Source window C modeltech examples counter v 30 carry val i amp carry 3l end 32 end 33 endfunction 34 3 always 8 posedge clk or posedge reset 369 if reset 37 count tpd reset to count 8 h00 38 else Ft 4 Ve 17 d 4 o de f Fr Figure 11 The Restart dialog v List Format v Wave Format v Breakpoints v Logged Signals v Virtual Definitions v Assertions and Functional Coverage Restart Cancel ModelSim SE Tutorial T 28 Lesson 2 Basic simulation Click the Run All icon The simulation runs until the breakpoint is hit When the simulation hits the breakpoint it stops running highlights the line with a blue arrow in the Source view Figure 12 and issues a Break message in the Transcript pane When a breakpoint is reached typically you want to know one or more signal values You hav
130. rformance or click the Performance P Profiling icon in the toolbar a This must be done prior to running the simulation ModelSim is now ready to collect performance data when the simulation is run Run the simulation a Type run 1 ms at the VSIM gt prompt Notice that the number of samples taken is displayed both in the Transcript and the Main window status bar Figure 97 Also ModelSim reports the percentage of samples that were taken in your design code versus in internal simulator code Display the statistical performance data in the Profile pane a Select View gt Profile gt View The Profile pane you may need to increase its size displays three tab selectable views of the data Ranked Call Tree and Structural Figure 98 The table below gives a description of the columns in each tab For more details on each pane see Profile panes GR 197 in the ModelSim GUI Reference Column Description Under raw the raw number of Profiler samples collected during the execution of a function including all support routines under that function or the number of samples collected for an instance including all instances beneath it in the structural hierarchy In raw the raw number of Profiler samples collected during a function or instance ModelSim SE Tutorial Figure 97 Sampling reported in the Transcript Transcript 333111 illegal op received 333155 outof 000000cf 999495 outof 0
131. rompt 1 Compile counter v and tcounter v a Select Compile gt Compile This opens the Compile Source Files dialog Figure 4 If the Compile menu option is not available you probably have a project open If so close the project by selecting File gt Close when the Workspace pane is selected b Select counter v hold the lt Ctrl gt key down and then select tcounter v c With the two files selected click Compile The files are compiled into the work library d Click Done 2 View the compiled design units a the Library tab click the icon next to the work library and you will see two design units Figure 5 You can also see their types Modules Entities etc and the path to the underlying source files scroll to the right if necessary Compiling the design T 23 Figure 4 The Compile HDL Source Files dialog Library wk x Look in tutorial et E3 counter v Ecounter v File name counter v counter Files of ype HDL Files v v vhd vhdl vho v v Done Default Options Edit Source Figure 5 Verilog modules compiled into the work library 7 ModelSim File Edit View Format Compile Simulate Add Tools Window Help Top level modules test_counter vlog reportprogress 300 work work C 6 0 Tutorial examples counter v Model Technology ModelSim SE vlog 6 0 UW work Library thi counter Module test_count
132. rowse Add file as type Folder dest Verilog ties vi Reference from current location C Copy to project directory You should now see two files listed in the Project tab of the Workspace pane Figure 17 Question mark icons in the Status column mean the file hasn t been compiled or the source file has changed since the last successful compile The other columns identify file type e g Verilog or VHDL compilation order and modified date Changing compile order VHDL Compilation order is important in VHDL designs Follow these steps to change compilation order within a project 1 Change the compile order a Select Compile gt Compile Order This opens the Compile Order dialog box Figure 18 b Click the Auto Generate button ModelSim determines the compile order by making multiple passes over the files It starts compiling from the top if a file fails to compile due to dependencies it moves that file to the bottom and then recompiles it after compiling the rest of the files It continues in this manner until all files compile successfully or until a file s can t be compiled for reasons other than dependency Alternatively you can select a file and use the Move Up and Move Down buttons to put the files in the correct order c Click OK to close the Compile Order dialog Creating a new project T 35 Figure 17 Newly added project files display a for status v ModelSim F
133. ry only collected Include function call hierarchy Performance and memory Specify structure level d Specify the Cutoff percent as 2 pos 5 1 Cutoff percent e Select Write to file and type calltree rpt in the file name field C Function to instance 2d f View file is selected by default when you select Write to file Leave it Function C Default 0 selected C Instances using same definition Specity 25 Instance g Click OK Output Wiite to transcript 2e write to file calltres rpt Browse View file OK Cancel 2f ModelSim SE Tutorial The calltree rpt report file will open automatically in Notepad Figure 106 You can also output this report from the command line using the profile report command See the ModelSim Command Reference for details Filtering and saving the data T 121 Figure 106 The calltree rpt report Notepad File Edit Window zi calltree rpt Model Technology ModelSim SE PLUS vsim 6 0b Simulator 2004 12 Dec 12 Platform win32 Calltree profile generated Wed Dec 15 09 10 33 2004 Number of samples 151 Number of samples in user code 133 735 Cutoff percentage 2 Name Under raw In raw Under In 5 test sm v 105 94 41 51 9 22 7 Tcl Flush 37 20 4 0 0 Tcl Close 37 36 20 4 19 9 1 Tcl DoOneEvent 15 1 8 3 0 6 Tcl WaitForEvent 8 8 4 4 4 4 Tcl DeleteTimerHandler 5 1 2 8 0 6 Tcl GetTime 4 4
134. s Mixed SystemC and HDL example T 57 ModelSim SE Tutorial T 58 Lesson 5 Simulating designs with SystemC Upon successful compilation the following message Verilog version shown appears in the Transcript window Model Technology ModelSim vlog compiler Compiling module control Compiling module retrieve Compiling module ringbuf Compiling module store Top level modules ringbuf 5 Create the foreign module declaration SystemC stub for the Verilog module ringbuf a Verilog Type scgenmod bool ringbuf gt ringbuf h at the ModelSim gt prompt The bool argument is used to generate boolean scalar port types inside the foreign module declaration See scgenmod CR 260 for more information VHDL Type scgenmod ringbuf gt ringbuf h at the ModelSim gt prompt The output is redirected to the file ringbuf h Figure 37 This file is included in test_ringbuf h which is included in file test_ringbuf cpp Figure 38 6 Compile and link all SystemC files including the generated ringbuf h a Type sccom g test_ringbuf cpp at the ModelSim gt prompt The test_ringbuf cpp file contains an include statement for test ringbuf h and a required SC_MODULE_EXPORT top statement which informs ModelSim that the top level module is SystemC Upon successfully compiling the design following message appears in the Transcript window Model Technology ModelSim sccom compiler 2003 05 May 25 2004 Exported
135. s and conditions except valid license agreements related to the subject matter of this Agreement which are physically signed by you and an authorized agent of Mentor Graphics either referenced in the purchase order or otherwise governing this subject matter This Agreement may only be modified in writing by authorized representatives of the parties Waiver of terms or excuse of breach must be in writing and shall not constitute subsequent consent waiver or excuse The prevailing party in any legal action regarding the subject matter of this Agreement shall be entitled to recover in addition to other relief reasonable attorneys fees and expenses Rev 040401 Part Number 221417 T 171 ModelSim SE Tutorial T 172 License Agreement ModelSim SE Tutorial Index A aCC T 53 add dataflow command T 96 add wave command T 68 Assertions add to dataflow T 142 debugging failures T 141 ignore assertions during simulation T 138 nopsl argument to vsim T 138 speeding debugging T 139 using assertions for debugging T 135 B break icon T 26 breakpoints in SystemC modules T 61 setting T 27 stepping T 28 C C Debug T 61 Code Coverage excluding lines and files T 132 reports T 133 Source window T 129 command line mode T 161 comparisons Waveform Compare T 145 compile order changing T 35 compiling your design T 13 T 23 cover argument T 125 coverage argument T 126 coverage report command T 133 cursors Wave window T 70 T 85
136. saving simulation options T 39 simulation basic flow overview T 13 comparing runs T 145 restarting T 27 running T 25 simulation configurations T 39 Standard Developer s Kit User Manual T 7 stepping after a breakpoint T 28 Support T 8 SystemC T 51 setting up the environment T 53 supported platforms T 53 viewing in the GUI T 60 T Tcl using in ModelSim T 164 Technical support and updates T 8 test dataset Waveform Compare T 148 test signals T 146 time measuring in Wave window T 70 T 85 toggle statistics Signals window T 131 tracing events T 93 tracing unknowns T 95 U unknowns tracing T 95 V vcom command T 101 verror command T 46 vlib command T 101 vlog command T 101 vsim command T 21 W Wave window T 65 T 75 adding items to T 68 T 78 cursors T 70 T 85 measuring time with cursors T 70 T 85 saving format T 73 zooming T 69 T 80 Waveform Compare T 145 reference signals T 146 saving and reloading T 153 test signals T 146 working library creating T 13 T 21 X X values tracing T 95 Z zooming Wave window T 69 T 80 T 175 ModelSim SE Tutorial T 176 Introduction ModelSim SE Tutorial
137. selected datasets Specify Comparison by Region Specify Comparison by Signal opens the structure browser to allow you to select specific signals for comparison Specify Comparison by Region opens the Add Comparison by Region dialog to allow selection of a specific reference region lt Previous Next gt Cancel ModelSim SE Tutorial Viewing comparison data Comparison data displays in three places within the ModelSim GUI the Workspace pane of the Main window the Wave window and the List window Viewing comparison data in the Main window Comparison information displays in three places in the Main window the Compare tab in the Workspace pane shows the region that was compared the Transcript shows the number of differences found between the reference and test datasets and the Objects pane shows comparison differences if you select the object on the Compare tab Figure 129 Viewing comparison data in the Wave window In the pathnames pane of the Wave window a timing difference is denoted by a red X Figure 130 Red areas in the waveform pane show the location of the timing differences as do the red lines in the scrollbars Annotated differences are highlighted in blue The Wave window includes six compare icons that let you quickly jump between differences Figure 131 From left to right the icons do the following find first difference find previous annotated difference find previous di
138. spram3 from a file a Right click anywhere in the data column and select Load to bring up the Load Memory dialog box Figure 87 The default Load Type is File Only b Typedata mem mem in the Filename field c Click OK The addresses in instance ram_tb spram3 mem are updated with the data from data mem mem Figure 88 Figure 87 Load Memory dialog box jj Load Memory I Figure 88 Initialized memory from file and fill pattern nstanc Initializing a memory T 107 Xl e Name ram tb spram3 mem m Load Type Address Range File Only AI C Data Only Addresses in decimal C Both File and Data Start 0 End 65535 Fil Filename data mem mem File Load Format C Verilog Hex C Verilog Binary MTI Browse Data Load Fill Type Fil Data Value C Increment C Decrement Skip C Random o word s 2b Caneel spram3 mem Min amp NH mem mem 1 ram 16 mem 2 J 00000000000000000000000000101000 00000000000000000000000000101001 00000000000000000000000000101010 00000000000000000000000000101011 00000000000000000000000000101100 00000000000000000000000000101101 00000000000000000000000000101110 00000000000000000000000000101111 00000000000000000000000000110000 00000000000000000000000000110001 00000000000000000000000000110010 00000000000000000000000000110011 0000000000000000000
139. st out str Kl Extended mode enabled Keep 0 4 Figure 71 Signals added to the wave viewer automatically 1 dataflow E 05 xl File Edit View Navigate Trace Tools Window SiR n dji X O A he L 2 1 Bo mi 4 Inputs 4 top p test 2820 ns 2785 ns 2 x a HRI Extended mode enabled Keep 1 Ttop p NAND 50 I 2c T 93 ModelSim SE Tutorial T 94 Lesson 8 Debugging with the Dataflow window d Select Trace gt Trace next event to trace the first contributing event ModelSim adds a cursor marking the last event the transition of the strobe to 0 at 2745 ns which caused the output of 1 on t out Figure 72 e Select Trace gt Trace next event two more times f Select Trace Trace event set The dataflow pane sprouts to the preceding process and shows the input driver of signal strb Figure 73 Notice too that the wave viewer now shows the input and output signals of the newly selected process You can continue tracing events through the design in this manner select Trace next event until you get to a transition of interest in the wave viewer and then select Trace event set to update the dataflow pane 3 Select File Close to close the Dataflow window ModelSim SE Tutorial Figure 72 Cursor in wave viewer marking last event
140. st sm Signal dat X e a orage eno Node count 32 X 33 s X 33 into data 1H gt 0L 16817 X 35 dtask OL gt 1H 20560 OL gt Z 452245 X T TE 456015 X 134 stop Current Exclusions 85963 sm v entire file Z gt 1H 82225 test_sm v Toggle Coverage 15 75 Statement arch Condon eee on I RIA pragma z Coverage 60 94 E Lines 25 23 Line 25 Line 26 Line 27 Line 28 Instance Coverage re DES Desunt Struts Suriname M test sm sram 0 beh sram Module 3 1 71 9 20 test sm sm seq sm 0 sm Module 28 x 833 M est sm sm seq sm seq Module 21 20 95 B r Module 8 73 test_sm Viewing statistics in the Main window Let s take a look at the data in these various panes 1 View statistics in the Workspace pane a Select the sim tab in the Workspace and scroll to the right Coverage statistics are shown for each object in the design Select the Files tab in the Workspace and scroll to the right Each file in the design shows summary statistics for statements branches conditions and expressions Click the right mouse button on any column name and select an object from the list Figure 109 Whichever column you selected is hidden To redisplay the column right click again and select that column name The status of which columns are displayed or hidden is persistent between invocations of
141. t www model com support Contact technical writer www mentor com supportnet documentation reply_form cfm TRADEMARKS The trademarks logos and servicemarks Marks used herein are the property of Mentor Graphics Corporation or other third parties No one is permitted to use these Marks without the prior written consent of Mentor Graphics or the respective third party owner The use herein of a third party Mark is not an attempt to indicate Mentor Graphics as a source of a product but is intended to indicate a product from or associated with a particular third party A current list of Mentor Graphics trademarks may be viewed at www mentor com terms_conditions trademarks cfm ModelSim SE Tutorial Table of Contents E nm T 5 Lesson 1 ModelSim conceptual overview T 11 Lesson 2 Basic simulation T 19 Lesson 3 ModelSim projects T 31 Lesson 4 Working with multiple libraries T 41 Lesson 5 Simulating designs with SystemC T 51 Lesson 6 Viewing simulations in the Wave window T 65 Lesson 7 Creating stimulus with Waveform Editor T 75 Lesson 8 Debugging with the Dataflow window T 89 Lesson 9 Viewing and initializing memories T 99 Lesson 10 Analyzing performance with the Profiler T 113 Lesso
142. t sm sm seq sm 0 15 15 8 3 8 3 ModelSim SE Tutorial T 120 Lesson 10 Analyzing performance with the Profiler Fi Itering and savi ng the data Figure 103 The Profiler toolbar As a last step you will filter out lines that take less than 296 of the simulation time A Under 2 E O i ll x using the Profiler toolbar and then save the report data to a text file 1c id 2a 1 Filter lines that take less than 2 of the simulation time Figure 104 The filtered profile data Ee d E MM LN b Right click somewhere in the pane and select Collapse All Nane Undedraw Infraw Unded inf xPaem c Change the Under field to 2 Figure 103 NU TS es NEN T smx 73 13 6 72 33 10 If you do not see these toolbar buttons right click in a blank area of the eat anil 7 7 3 9 3 9 5 toolbar and select Profile du an v22 4 4 229 22 3 d Click the Refresh Profile Data button ModelSim filters the list to show only those lines that take 2 or more Figure 105 The Profile Report dialog of the simulation time Figure 104 Profile Report x 2 Save the report r Performance Memory data a Click the save icon in the Profiler toolbar f Call Tree 2b C Ranked 2c Default data collected b Inthe Profile Report dialog Figure 105 select the Call Tree Type Grae Performance only c Inthe Performance Memory data section select Default data Root opt C Memo
143. t tab Figure 22 2 Adda sub folder a Right click anywhere in the Project tab and select Add to Project gt Folder b HDL in the Folder Name field Figure 23 c Click the Folder Location drop down arrow and select Design Files d Click OK Organizing projects with folders T 37 Figure 21 Adding a new folder to the project 7 Add Folder Folder z Files 1b Folder Location E Level vij DK Cancel Figure 22 A folder in a project Workspace Name Status Type rder Modfed countery vy Verilog 1 06 03 04 07 36 00 PM tcounter Verilog 0 06 03 04 07 36 26 Design Files Folder Project Library Figure 23 Creating a subfolder y Add Folder xj m Folder Name HDL Folder Location Design Files a Top Level incel 2c ModelSim SE Tutorial T 38 Lesson 3 ModelSim projects You ll now see a icon next to the Design Files folder in the Project tab Figure 24 e Click the icon to see the HDL sub folder Moving files to folders If you don t place files into a folder when you first add the files to the project you can move them into a folder using the properties dialog 1 Move tcounter v and counter v to the HDL folder a Select counter v hold the lt Ctrl gt key down and then select tcounter v b Right click either file and select Properties This opens the Project Compiler Settings
144. t_counter vsim hazards t ps work test_counter d Lau L VIDIT JL Project test Now Ops Delta 0 command line switches Lesson 4 Working with multiple libraries Topics The following topics are covered in this lesson Introduction Related reading Creating the resource library Creating the project Linking to the resource library Permanently mapping resource libraries Lesson wrap up T 42 T 42 T 43 T 45 T 46 T 49 T 50 T 41 ModelSim SE Tutorial T 42 Lesson 4 Working with multiple libraries Introduction In this lesson you will practice working with multiple libraries As discussed in Lesson I ModelSim conceptual overview you might have multiple libraries to organize your design to access IP from a third party source or to share common parts between simulations You will start the lesson by creating a resource library that contains the counter design unit Next you will create a project and compile the testbench into it Finally you will link to the library containing the counter and then run the simulation Design files for this lesson The sample design for this lesson is a simple 8 bit binary up counter with an associated testbench The pathnames are as follows Verilog lt install_dir gt modeltech examples counter v and tcounter v VHDL lt install_dir gt modeltech examples counter vhd and tcounter vhd This lesson uses the Verilog files tcounter v
145. t_name gt 3 Exclude an entire file a In the Files tab of the Workspace locate sm v or sm vhd if you are using the VHDL example b Right click the file name and select Code Coverage gt Exclude Selected File Figure 117 The file is added to the Current Exclusions pane 4 Cancel the exclusion of sm v a Right click sm v in the Current Exclusions pane and select Cancel Selected Exclusions ModelSim SE Tutorial Figure 117 Excluding an entire file via the GUI View Source beh file Save List test sm v file Code Code Coverage Reports Copy Properties Filename Fulpath Type Stmt Count StmtHis Stmt _ Stmt Graph seq sm seqv v file 21 20 35 230 IBN Creating Code Coverage reports You can create reports on the coverage statistics using either the menus or by entering commands in the Transcript pane The reports are output to a text file regardless of which method you use To create coverage reports via the menus do one of the following select Tools gt Code Coverage gt Reports from the Main window menu right click any object in the sim or Files tab of the Workspace and select Code Coverage gt Code Coverage Reports right click any object in the Instance Coverage pane and select Code coverage reports from the context menu 1 Create a report on all instances a Select Tools gt Code Coverage gt Reports from the Main window toolbar
146. tatesmem s newe n as neras n cas necas n reset n reset n rafrech rata TER IDLE TREF1 X REF2 Cursor 1 IET ge wave as dram_cntrl ps ModelSim SE Tutorial T 142 Lesson 12 Debugging with PSL assertions 3 Examine we_n in the Dataflow and Source windows Figure 125 Viewing we_n in the Dataflow window zi File Edit View Navigate Trace Tools Window Dataflow Main window b Drag from the Wave window to the Dataflow window i IE i Ba i i Verilog The Dataflow window shows that we_n is driven by the al Ze je n Ne 3e 3c 4 ASSIGN 106 process with inputs rw and mem state Figure 125 The RD ARR m values shown in yellow are the values for each signal at the point at which the simulation stopped 3100 ns We see that we n is 510 when mem_state is REF2 As noted above we_n should be St1 This is the reason for the assertion failure 2 SSIGN 104 VHDL The Dataflow window shows that we_n is driven by the process at line 61 which has inputs rw and mem_state The values shown in yellow the values for each signal at point at which the simulation stopped 3800 ns We see that we_n is St0 when mem_state is REF2 As noted above we_n should be St1 This is the reason for the assertion EI failure Extended mode enabled Keep 1 ftb entrlAve_n Select the process that drives in order to displa
147. through SystemC files in the Source window In the case of SystemC ModelSim uses C Debug an interface to the open source gdb debugger See C Debug UM 401 in the ModelSim User s Manual for complete details 1 Seta breakpoint a Double click test_ringbuf in the sim pane of the Workspace to open the source file b Inthe Source window scroll to near line 150 of test ringbuf h c Click on the red line number next to the line shown in Figure 42 containing Verilog bool var_dataerror_newval actual read VHDL sc_logic var dataerror newval acutal read ModelSim recognizes that the file contains SystemC code so it automatically launches C Debug Once the debugger is running ModelSim places a solid red sphere next to the line number Figure 42 2 Run and step through the code a Type run 500 at the VSIM gt prompt When the simulation hits the breakpoint it stops running highlights the line with an arrow in the Source window Figure 43 and issues a message like this in the Transcript C breakpoint c 1 test_ringbuf compare_data this 0x842f658 at test_ringbuf h lt line_number gt Viewing SystemC objects in the GUI T 61 Figure 42 An active breakpoint in a SystemC file Ki test_tingbuf h ln 143 144 145 4 146 On every negedge of the clock compare actual and expe 147 148 inline void test ringbuf compare data 149 1500 bool var dataerror newval actual read
148. tions The configuration is then listed in the Project tab and you can double click it to load tcounter v along with its options 1 Create a new Simulation Configuration a Select File gt Add to Project gt Simulation Configuration This opens the Simulate dialog Figure 26 The tabs in this dialog present a myriad of simulation options You may want to explore the tabs to see what s available You can consult the ModelSim User s Manual to get a description of each option b counter in the Simulation Configuration Name field c Select HDL from the Place in Folder drop down d Click the icon next to the work library and select test counter e Click the Resolution drop down and select ps f For Verilog click the Verilog tab and check Enable Hazard Checking g Click OK The Project tab now shows a Simulation Configuration named counter Figure 27 2 Load the Simulation Configuration a Double click the counter Simulation Configuration in the Project tab In the Transcript pane of the Main window the vsim the ModelSim simulator invocation shows the hazards and t ps switches Figure 28 These are the command line equivalents of the options you specified in the Simulate dialog Simulation Configurations T 39 Figure 26 The Simulation Configuration dialog y Add Simulation Configuration gt Simulation Configuration Name Place in Folder n
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151. vered in this lesson Introduction Related reading Compiling and loading the design Viewing memory Navigating within the memory Saving memory contents to a file Initializing a memory Interactive debugging commands Lesson Wrap up T 100 T 100 T 101 T 102 T 104 T 106 T 107 T 109 T 111 T 99 ModelSim SE Tutorial T 100 Lesson 9 Viewing and initializing memories Introduction In this lesson you will learn how to view and initialize memories in ModelSim ModelSim defines and lists as memories any of the following e wire and std logic arrays nteger arrays e Single dimensional arrays of VHDL enumerated types other than std logic Design files for this lesson The ModelSim installation comes with Verilog and VHDL versions of the example design The files are located in the following directories Verilog install dir modeltech examples memory verilog VHDL install dir modeltech examples memory vhdl This lesson uses the Verilog version for the exercises If you have a VHDL license use the VHDL version instead Related reading ModelSim GUI Reference Memory windows GR 174 ModelSim Command Reference mem display CR 198 mem load CR 201 mem save CR 204 radix CR 243 commands ModelSim SE Tutorial Compiling and loading the design 1 Create a new directory and copy the tutorial files into it Start by creating a n
152. w Figure 51 Working with a single cursor in the Wave window y wave default E 101 File Edit View Insert Format Tools Window Cursors mark simulation time in the Wave window When ModelSim first draws the Wave window it places one cursor at time zero Clicking anywhere in the waveform pane brings that cursor to the mouse location You can also add additional cursors name lock and delete cursors use cursors to measure time intervals and use cursors to find transitions 4 test_counter clk 4 test_counter reset Working with a single cursor E Aest_counter count 1 Position the cursor by clicking and dragging a Click the Select Mode icon on the Wave window toolbar b Click anywhere in the waveform pane x D ns to 420 ns Now 400 ns Delta 2 A cursor is inserted at the time where you clicked Figure 51 c Drag the cursor and observe the value pane The signal values change as you move the cursor This is perhaps the easiest way to examine the value of a signal at a particular time d Inthe waveform pane drag the cursor to the right of a transition with the mouse positioned over a waveform The cursor snaps to the transition Cursors snap to a waveform edge if you click or drag a cursor to within ten pixels of a waveform edge You can set the snap distance in the Window Preferences dialog select Tools Window Preferences e Inthe cursor pane drag the cursor to t
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154. y its source code in the Source window Figure 126 Finding the bug in the source code Verilog Looking at the Source window you will see that the current line arrow points to line 104 of the dramcon_rtl sv file Figure 126 In this C modeltech examples psl verilog dramcon_ttl sv line you can see that the logic assigning we_n is wrong it does not account for the REF2 state assign mem_state 1 100 assign ack mem state 0 The code shows that the incorrect assignment is used for the example 101 with the correct assignment immediately below lines 106 107 that will 102 Deassert we n high during refresh hold we n high through both states of the refresh cycle 103 ifdef BUG 7 104 1 DEL tate REF1 VHDL Looking at the Source window you can see that the current line 105 we T arrow points to line 61 of the dramcon rtl vhd file In this line you can 106 assign DEL we n rw mem state REF1 see that the logic assigning we n is wrong it does not account for the 107 mem state REF2 REF state 108 endif 109 The code shows that the incorrect assignment is used for the example 110 jf mius the row nddraxe or col nn address to d with the correct assignment immediately below line 65 that will hold ete we n high through both states of the refresh cycle Mo gu c T H dam ensi hi
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