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1. Figure 2 3 Block Diagram of PCA card IijasiC Terasic PCA User Manual www terasic com www terasic com Chapter 3 Board Component This chapter describes the specifications of the on board components 3 1 PCle Edge Connector This Edge connector is used to connect the PCA with PC motherboard PCIe slot as show Figure 3 1 and Figure 3 2 Figure 3 1 PCA Edge Connector EFS Hu uin Ax tu tun Fa Figure 3 2 plug the PCA into motherboard PCle slot Kadasic Terasic PCA User Manual www terasic com www rasic com The pins are numbered as shown with side A on the top of the centerline on the solder side of the board and side B on the bottom of the centerline on the component side of the board The PCle interface pins PETpx PETnx PERpx and PERnx are named with the following convention PE stands for PCIe high speed T for Transmitter R for Receiver p positive and n for negative Note that adjacent differential pairs are separated by two ground pins to manage the connector crosstalk Table 3 1 gives the wiring information of the PCIe Edge connector 66 99 Table 3 1 Pin assignments and descriptions on PCIe Edge connector Pin Numbers 1 O ON D0 RON ke mah k 12 13 14 15 16 17 18 19 20 21 22 Terasic PCA User Manual www terasic com Side B ame NC NC NC GND NC NC GND VCC3P3 NC 3 3VAUX WAK
2. User Manual Terasic PCle Cable Adapter Daughter Card 10101010100010101010101010101010010101011101010010101001 10101010100010101010101010101010010101011101010010101001 un o 101010101000101010101010101010100101010111010100101010010010101010101001010101010 101010101000101010101010101010100101010111010100101010010010101010101001010101010101010101010010110101011011000101111010011010 aaa 10101010100010101010101010101010010101011101010010101001 0110 ar HUI Ta CINES TC 10101010100010101010101010101010010101011101010010101001001010101010100101010101010101 www terasic com Copyright O 2003 2012 Terasic Technologies Inc All Rights Reserved CONTENTS CHAPTER 1 INTRODUCTION OF THE PCA CARD i nvnnnnnnnnnnnnvnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnenunnunnunnnnen 2 INNO Ui T 2 PADOU EE AM ET 3 IS penus c 4 CHAPTER 2 PLACARDARCHITECTURE iiit sam mmm mmm 5 MT MT 5 2 2 Bloek Diagram Or the PCA Board anccssccsessossarenssasaancanetaausesececncdsesanagssadanaasnadanasatecesuedcosaaunseatanaassananenocacosaesse 6 CHAPTER 3 BOARD COMPONENT cecooeiisaninvaniwinesiniu an vans e euise Lapis oou MUN Cou Es annanannn Kanaan Kab Ona man Nana dalan 8 PCE base d ONC COLON ER aa 8 SWAT Cale Con CIO 0 JE EE voce denuen nsanueectcoepee obs eetce censors piers tecieeecee ss 10 DN ena a
3. 1 PCA switches setting B Demonstration Setup e Make sure TR4 and PC are both powered off e Plug the PCA card into PCIe slot on the PC motherboard e Use the PCIe cable to connect to the TRA PCIEO connector and PCIe adapter card as shown in Figure 4 2 Kias c Terasic PCA User Manual www terasic com www i Straux IV 3 0 md diu ia A ue 1 xL p 1 HE gt IN 01 Haa t i LER E zono J l En E N Z Yg s 4 m mm i J isa ij Figure 4 2 PCle Fundamental Communication Demonstration Setup e Power on your PC e Download the tr4 pcie0 fundamental sof into the TRA using the Quartus II Programmer And all seven LEDs on PCA card will be lighted on if work rightly while the PC automatic start e Install PCIe driver if necessary The driver is located in the folder PCIe SDK Driver e Launch the demo program PCIe Fundamental Demo exe shown in Figure 4 3 20 Terasic PCA User Manual www terasic com www terasic com Register ReadAwrite Button Register 0x04 LED Register Gx04 Custom Registers BUTTON 0 LEDO Register Address Register Value BUTTON 1 Le BUTTON 2 mj ED BUTTON 3 I LEDS Read Status Set LEG DMA Memory Mapped Write and Read FIFO Write and Read ter www terasib nacm PCIE Board Connected Figure 4 3 PCle Fundamental Demo GUI e Make sure Select FPGA Board appears as VID 1172 DID E001 e Press BUTTONO BUTTON3 on the TRA and c
4. Po BBB Po 0 1 3S8dB TAB 1 7 1 0 S0dB 90dB 1 1 1 2 177 dB Default Setting 12 3 dB Default Setting 15 Kias c Terasic PCA User Manual www terasic com Table 3 5 SW2 Settings Input Equalizer Configuration for Channel B Pin4 SELO B Pin5 SEL1 B Pin6 SEL2 B 1 25GHz 2 5GHz 0 0 0 0 5dB 1 2 dB 0 0 1 0 6dB 1 5 dB 0 1 0 1 0 dB 2 6 dB 0 1 1 1 9 dB 4 3 dB 1 0 0 2 8 dB 5 8 dB 1 0 1 3 6 dB 7 1 dB 1 1 0 5 0 dB 9 0 dB 1 1 1 7 7 dB Default Setting 12 3 dB Default Setting Receiver Detect Enable input for CH A Pin 7 amp B Pin 8 with 100kohm pull up resistors RXD A amp B High indicates that the Receiver Detect Function Enable Table 3 6 SW2 Settings Receiver Detect Function Enable for CH A amp CH B Pin7 RXD A Pin8 RXD B Receiver Detect Function Enable 1 1 CH A amp CH B Receiver Detect Enable Default Setting 1 0 CH A Receiver Detect Enable CH B Receiver Detect Disable 0 1 CH A Receiver Detect Disable CH B Receiver Detect Enable 0 0 CH A amp CH B Receiver Detect Disable Please refer the datasheet of PI2EQX5904 to more settings 3 4 LEDs The PCA includes status LEDs Please refer Table 3 7 for the status of the LED indicator Board ud LED name Description Reference D1 CBL Cable PRSNT1n D2 EDGE Edge PRSNT1n 16 www terasic com Terasic PCA User Manual www terasic com D3 POWER Power LED DN1 SIG A Signal detect output for CH A DN2 SIG B Signal detect output
5. for CH B DN3 RX50 A Receiver Detect Output for CH A0 DNA RX50 B Receiver Detect Output for CH BO 17 TTlasiC Terasic PCA User Manual www terasic com www terasic com Chapter 4 Set up on PCA This chapter illustrates the set up for the PCA card base on the TR4 Board To purchase the TR4 board please visit www tr4 terasic com 4 1 Introduction The application reference design shows how to implement fundamental control and data transfer by using PCIEO port on the TR4 In the design basic I O is used to read or write the buttons and LEDs on the TR4 High speed data transfer is performed by DMA Both Memory Mapped and FIFO memory types are demonstrated in the reference design The demonstration also makes use of the associated PCIe cable adapter card PCA 4 2 System Requirements The following items are required for the PCA demonstration e TR4 board xl e PCA card xl e PCIe X4 Cable xl e PC x2 B Demonstration Files Location The demo file is located in the folder on the TRA CD TRA PCIeO FundamentaNdemo batch The folder includes following files e PC Application Software PCle Fundamental Demo exe e FPGA Configuration File tr4 pcieO fundamental sof e PCIe Library TERASIC PCIE DLL e Demo Batch File tr4 pcieO fundamental bat 18 TTlasiC Terasic PCA User Manual www terasic com rasic com ADEN B PCA Setup e SWI set to X4 mode SW2 all pin set to 1 as shown in Figure 4 1 Figure 4
6. the PCA kit content E S PCA board Figure 1 2 PCA kit package contents 3 TjasIc Terasic PCA User Manual www terasic com www terasic com 1 3 Getting Help Here is information of how to get help if you encounter any problem Terasic Technologies e Tel 886 3 550 8800 e Email support terasic com Sadasic Terasic PCA User Manual www terasic com www terasic co m Chapter 2 PCA Card Architecture This chapter provides information about architecture and block diagram of the PCA board 2 1 Layout and Components The picture of the PCA card is shown in Figure 2 1 and Figure 2 2 It depicts the layout of the board and indicates the locations of the connectors and key components PCle X4 X1 Mode Select Config Switch PCle Connector Redriver IC Figure 2 1 The PCA Card PCB and component diagram top view TTlasiC Terasic PCA User Manual www terasic com www terasic com Figure 2 2 The PCA Card PCB and component diagram bottom view 2 2 Block Diagram of the PCA Board Figure 2 3 shows the block diagram of the PCA card TTlasiC Terasic PCA User Manual www terasic com www terasic com Clock PI2E0X5904 i X4 PCle Tx PCle Signal X4 PCle Tx Redriver l i i X4 PCle Rx PCIe Signa X4 PCle Rx Redriver 4 Millen apr mp rrr prm msan gl 5 CPRSNT n j VCC3P3 LED CPERST mE 0 ohm WAKE n 0 ohm
7. E RSVD GND PETpO PETnO GND PRSNT2n GND PETp1 PETn1 GND GND Description NC NC NC Ground NC NC Ground 3 3V Power NC 3 3 V Auxiliary Power NC Mechanical Key Reserved Ground Transmitter differential pair Lane 0 Ground Hot Plug presence detect Ground Transmitter differential pair Lane 1 Ground Ground Side A Name PRSNT1n NC NC GND NC NC NC NC VCC3P3 VCC3P3 PERSTn GND REFCLK REFCLK GND PERpO PERnO GND GND PERp1 PERn1 Description Hot Plug presence detect NC NC Ground NC NC NC NC 3 3V Power 3 3V Power Fundamental Reset Ground Reference clock differential pair Ground Receiver differential pair Lane 0 Ground Ground Receiver differential pair www terasic com differential pair Lane 3 Reserved Hot Plug presence detect 3 2 PCIe Cable Connector PCIe cable connector is used to connect the PCIe X4 Cable and PCA cable connector Connect the PCA by using a PCIe X4 Cable as show Figure 3 3 Figure 3 3 PCle X4 Cable and PCA To purchase the PCIe X4 Cable please refer Terasic website PCIe Cable terasic com Figure 3 4 as show the PCIe Cable connects PCA connector 10 Terasic PCA User Manual www terasic com www terasic com Feed mani IU os 2 z ee TO es Figure 3 4 PCle Cable connects PCA connector Table 3 2 gives the wiring information of the PCIe Cable connector MT Eves ronente
8. a aan ene m asa eumd ade RM NEN MEMINI HUNE 13 LED asem E aan aa stan sn se an aa nan Boa nan 16 CHAPTER 4 IN 18 Ea 0 Io EE Na 5909000098001 8000 PN Ma Dn 18 Z2 SUC TU AR CE aa naa EE scoot Sao EE Yu Yel sn Oa Ana an PAR 18 CHAPTER 5 MENN mc eee 25 Sal Revisi on ER 25 EA Co pa ie ee an NE 25 1 TTlasiC Terasic PCA User Manual www terasic com www terasic com Chapter 1 Introduction of the PCA Card PCA PCIe Cable Adapter which is used to connect PCIe upstream slot with downstream target board by a PCIe X4 cable supports the PCIe X4 amp X1 mode PCA card can provide programmable equalization amplification and de emphasis for PCIe transceiver signal by using 8 select bits It is also available to optimize performance over a variety of physical mediums by reducing Inter symbol interference 1 1 Features Figure 1 1 shows a photograph of the PCA Card Figure 1 1 Layout of the PCA card TTlasiC Terasic PCA User Manual www terasic com www teresic com The key features of the card are listed below e Up to 5 0Gbps PCIe 2 0 Serial Re Driver e PCle X4 Gen 2 e Adjustable receiver equalization e Adjustable transmitter amplitude and de emphasis 1 2 About the KIT The PCA kit will come with the following contents e PCAcard Please visit PCIe Cable terasic com download the PCA user manual Figure 1 2 shows the photograph of
9. defines some constants based on FPGA design shown below 22 Terasic PCA User Manual www terasic com www terasic co m define PCIE VID HEILT VE define PCIE DID Us ELE T define DEMO PCIE USER BAR PCIE BARI define DEMO PCIE IO ADDR 0x04 define DEMO PCIE FIFO ID 0x00 The vendor ID is defined as 0x1172 and the device ID is defined as OxEO01 The BUTTON LED register address is 0x04 based on PCIE BARI A C class PCIE is designed to encapsulate the DLL dynamic loading for TERASIC PCIE DLL A PCIE instance is created with the name m hPCIE To enumerate all PCIe cards in system call the function m hPCIE ScanCardiwVendorID wDewiceID amp dwDewiceHum m szPcieIntfao where wVendorID and wDeviceID are zeros The return value dwDeviceNum represents the number of PCIe cards found in the system The m szPcielnfo array contains detailed information for each PCIe card To connect the selected PCIe card the functions are called int noel ComhbobBoxBoard Itemlndex WORD VID m szPcieInfo n5e1 VendorID WORD DID m szPcieInfo n5el DeviceID h uccess m hPCIE Open VID DID 01 O first matched board where nSel is selected index in the Selected FPGA Board poll down menu Based on the return m szPcielnfo we can find the associated PID and DID which can br used to specifiy the target PCIe card To read the BUTTON status the function is called m hPCIE Read32 DEMO PCIE USER BAR DEMO PCIE IO ADDR amp d
10. lick Read Status in the application software e Check Uncheck the LEDO 3 in this application software and click Set LED The LEDs on the TR4 should light and unlight accordingly e Click Memory Mapped Write and Read to test the memory mapped DMA A report dialog will appear when the DMA process is completed e Click FIFO Write and Read to test the FIFO DMA A report dialog box will appear when the DMA process is completed e The Custom Registers Group is used to test custom design registers on the FPGA side Users can use this function to verify custom register design B Demonstration Setup e Quartus II 11 1 21 Sadasic Terasic PCA User Manual www terasic com www teresic com B Demonstration Source Code Location e Quartus Project TRA PCIeO Fundamental e Borland C Project TRA PCIeQ Fundamental pc B FPGA Application Design The PCI Express demonstration uses the basic I O interface and DMA channel on the Terasic PCIe IP to control I O Button LED and access two internal memories RAM FIFO through the MUX block FPGA Le Basic LI BE I O Button Interface Terasic PCIe IP F Internal RAM an MUX Channel Address Decoder 1 FIFO 5 Figure 4 4 Hardware Block Diagram of the PCle Reference Design B PC Application Design The application shows how to call the TERASIC_PCIE DLL exported to API To enumerate all PCIe cards in system call the software design
11. press transmitter Lanes Differential PCI Express receiver Lane 1 Differential PCI Express receiver Lane 1 Ground reference for PCI Express transmitter Lanes Differential PCI Express receiver Lane 2 Differential PCI Express receiver Lane 2 Ground reference for PCI Express transmitter Lanes Differential PCI Express receiver Lane 3 Differential PCI Express receiver Lane 3 Ground reference for PCI Express transmitter Lanes 12 www terasic com B14 PWR B15 PWR 3 3VCablepower B16 PWRATN B19 CWAKEn Power management signal for wakeup events optional CPERSTn Cable PERSTn 3 3 Switches The PCA contains x2 and x8 switches that allow configuration of the PCA PCIe mode SW1 equalization and de emphasis SW2 The two switches SW1 and SW2 are located on top of the front side of the PCA card Figure 3 5 show the location of the board POI EXPRESS Figure 3 5 Switches 13 TilasiC Terasic PCA User Manual www terasic com www terasic com Figure 3 6 show the SW1 settings Table 3 3 SWI Settings Figure 3 7 Show the SW2 Settings 14 Tjasic Terasic PCA User Manual www terasic com www terasic co The PI2EQX5904 has two channels A and B has separate egualization control Figure 3 8 show the channel A and B inside on the block diagram Figure 3 8 CH A and CH B within PI2EQX5904 Table 3 4 SW2 Settings Input Equalizer Configuration for Channel A oO es 0 BB 0 19843
12. r anes Express transmitter Lanes ee transmitter Lane 0 KAN Had er nd transmitter Lane 0 2 ET Pe Express transmitter Lanes KAN GAN emettawi transmitter Lane 1 PETn1 Differential PCI Express Po TU aeneae NN T Prem rane anes Express transmitter Lanes om ENS transmitter Lane 2 cm ENDS transmitter Lane 2 m Ground reference for PCI Express transmitter Lanes 11 Tjasic Terasic PCA User Manual www terasic com www terasic com A11 A12 A13 A14 A15 A16 A17 A18 A19 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 PETp3 PETn3 GND CREFCLK CREFCLK GND SB RTN CPRSNTn CPWRON GND PERpO PERnO GND PERp1 PERn1 GND PERp2 PERn2 GND PERp3 PERn3 GND YadasiC Terasic PCA User Manual rasic com Differential PCI Express transmitter Lane 3 Differential PCI Express transmitter Lane 3 Ground reference for PCI Express transmitter Lanes Differential 100MHz cable reference clock Differential 100MHz cable reference clock Ground reference for PCI Express transmitter Lanes Signal return for single ended sideband signals Used for detection of whether a cable is installed and the downstream subsystem is powered Turns power on off to slavetype downstream subsystems Ground reference for PCI Express transmitter Lanes Differential PCI Express receiver Lane 0 Differential PCI Express receiver Lane 0 Ground reference for PCI Ex
13. wData To set LED status the function is called m hPCIE Write32 DEMO PCIE USER BAR DEMO PCIE IO ADDE dwData To write and read memory mapped memory call the functions 23 TijasiC Terasic PCA User Manual www terasic com www terasic com ff Write bouccess m hPCIE DmaWriteiLocal ddr pWrite nTestSizel if ib2uccezss i ff read bouccess m hPCIE DmaEead Local ddr pEead nTestsizel To write and read FIFO memory call the functions 24 Terasic PCA User Manual www terasic com www terasic com Chapter 5 Appendix 5 1 Revision History Change Log Initial Version Preliminary 5 2 Copyright Statement Copyright 2012 Terasic Technologies All rights reserved 25 Kadasic Terasic PCA User Manual www terasic com www terasic com

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