FastATLAS An Ultra-Fast Physical MESFET and HEMT
Contents
1. especially at the drain edge of the gate In addition the solution sequence has been automated In FastATLAS it is not necessary to specify solution techniques since the simulation procedure automatically and robustly solves for all biases Combining these features produce a flexible simulation tool able to rapidly characterize ar bitrary FET structures F I in lt ons Pin Tes Dn Fe ari E Figure 5 Current driven DC IV simulation illustrating the efficient ex traction algorithm where samples are only taken in regions of change November 1997 S FastNOISE is capable of extracting FAT ATLAN noise parameters for a simulated device anaimwm biy sia Bavio hanapan cra olathe This simulation incorporates a variety of EENT noise mechanisms and uses the imped FTD ance field method to obtain the terminal iia characteristics Again several post pro anon cessing options are available allowing FastNOISE to output the conventional noise parameters Finin Rn and Iopt 2 m E E FastMixedMode embeds any of the mod ules listed above within a circuit enabling the user to perform TCAD on complex systems of devices and passive elements This feature leads to large signal analysis which will include both time domain and harmonic balance techniques Features One method of the optimizations has been to modify the ATLAS code from a voltage driven format where the terminal biases are applied to a mixed anam e2. and shows the potential gradient along its length The channel conduction particularly the parasitic conduction in the AlGaAs is consistent with the gate potential profile is clearly varying under the dynamic bias ing as the gate is forced more negative on The TCAD Driven CAD Journal Page 12 November 1997 Calendar of Events November December Bulletin Board MRS Meeting Boston MRS Meeting Boston CO MRS Meeting Boston Visit Silvaco at IEDM 97 MRS Meeting Boston Silvaco will be demonstrating the latest advances in our Virtual Wafer Fab TCAD simulation MRS Meeting Boston products at the conference which will be held at the Washington D C Hilton on December 7 10 1997 Silvaco s demo suite will be located in Suite C325 on the Lobby floor All conference participants i are welcome to come and see the exciting new EDM 9 Washington D C tools available from Silvaco including FastAtlas 9 9 IEDM 97 Washington D C an extremely fast FET device simulator f Blaze3D a 3D device simulator for compound 10 ICCAD 97 Santa Clara 10 IEDM 97 Washington D C materials and CLEVER highly accurate cell 11 ICCAD 97 Santa Clara 11 level LPE based on Silvaco s advanced 3D process simulation capabilities All participants are 12 _ICCAD 97 Santa Clara 12 encouraged to take advantage of this opportunity 13 13 to come and see how the only significant remaining commercial TCAD vendor can help meet your 14 14 tec
3. feature available in FastATLAS is the transport parameter database A new set of models have been de veloped using three valley ensemble Monte Carlo simu lation to derive the carrier mobility velocity effective mass and both the energy and momentum relaxation times as functions of electric field doping and ambient lattice temperature Figure 6 illustrates the variation of carrier velocity as a function of field and doping in GaAs where velocity overshoot and saturation are clearly vis ible Further due to the new automated solution process the simulation convergence is relatively independent of transport models FastATLAS works within the VWF framework and is interfaced to all SILVACO input and graphical analysis tools Figure 7 displays the conduc tion band energy of a recessed GaAs MESFET biased at 2 volts Drain Source and volts on the gate Conclusion FastATLAS is a new and highly efficient TCAD tool for arbitrary non planar MESFET and HEMT device simulation New techniques allow automated mesh generation bias step control and very high frequency analysis Device optimization can be done using the most advanced physical model with almost no speed penalty A 1000x to 10000x speed up over conventional device simulation allows results to be obtained in seconds 3D Numerical Simulation of the Pseudo MOS Transistor for SOI Film Characterization Dz Munteanul S Cristoloveanu and E Guichard2 ILPCS ENSERG 23 rue des Martyrs
4. geometries correctly Although ATLAS Device3D can perform simula tions of 3D Flash memory structures it is often more convienient to find a solution using 2D simulation By default in 2D simulations the coupling capacitances between the floating gate and the control gate and other elec trodes is determined only by the layer thicknesses and other 2D geometries How ever ATLAS enables the user to specify an extra capacitance between a floating electrode and any other electrode in the device structure Most commonly this is an extra capacitance between the float ing gate and the control gate This would old simulation be defined using the syntax CONTACT NAME FGATE FLOATING EL1 CAP CGATE FG1 CAP lt value gt Users should note this capacitance is applied between electrode nodes This differs from the usual lumped capacitance definition on the CONTACT statement which applies between the specified electrode and ground The effect of the extra capacitance is to give the correct coupling ratio seen in simple EEPROM simulations such as the threshold voltage evalution shown in Figure 1 Gen erally the value of the external capacitor should be tuned to the threshold behavior before more complex simula tions of programming erasing or breakdown are done Capacitive coupling between the floating gate and other electrodes can also be modeled by additional syntax The syntax ELx CAP and FGx CAP where x 1 to 4 can be used to defin
5. polysilicon S GAZE EID zj imu imation or aes a Bre Sardown Coe CEEOL CE A fOY PLOTS megia TORTALOTSD af Figure 3 lsosurfaces of impact ionization rate reveal that the most intense with an appropriate resistivity and avalanche multiplication is along the centre of the emitter stripe and in the electron affinity November 1997 n doped SiGe collector region Page 11 The TCAD Driven CAD Journal Fint Tekira Miate raminti ee the right side The contours in the GaAs fay P ence Hage iiA aie mh show the local electron channel current in Mi aaant i Fenr Lec i the 2DEG and AlGaAs is consistent with the gate potential being lower on the right hand side where the gate potential is more negative b Conclusion Blaze3D extends ATLAS simulation ca pability to include arbitrary three dimen sional heterostructure devices Combined with DevEdit3D and TonyPlot3D accurate structure definition and results analysis are possible for 3D device technology develop ment These features are demonstrated for typical examples of HBT and HEMT n iF I pay pee i ta Reference 1 A Pruijboom et al IEDM 95 747 __ SAV mieniem 1995 Figure 4 a cut plane through 3D HBT structure at onset of avalanche breakdown Note the concentration of impact ionization in the centre of the n SiGe collector extension region b HBT collector breakdown characteristic c cut line through 2D sec NOTE Fu
6. the result ing distortion of the field distribution Figure 8 is responsible for an apparent degradation of the transconductance Figure 9 and hence extracted mobil ity On the other hand when the probe in terdistance becomes comparable with the contact area Figure 10 the short channel large contact effect causes an over estimation of the carrier mobility In order for the SOI material quality not to be underestimated or over estimated it is therefore necessary to respect cer tain rules in term of probe inter dis tance on sample size Conclusion The 3D simulator Device3D has reliably modeled the W MOSFET structure The simulations have uncovered a number of non obvious features of Y MOS tran sistor behavior This work makes clear the conditions required for reliable opera tion of the W MOSFET for SOI substrate characterization References 1 S Cristoloveanu S S Li Electrical Characterization of Hier Vere Piet Torri FAET Prooeties HeT Elation of lg sewer jna Inallicon TADO ledernutoral Figure 8 Border proximity effect shown by distortion of iso current distribution SOI Materials and Devices Kluwer 1995 2 Atlas User s Manual 1997 n i Hrab cerrzal 4 a 1 nin hins VY GS TETTEL TETE TT SSE caey CARTET imi ia Trema ae keg cel a Bair kina Yy Th Figure 9 Simulated Y MOSFET curves for different sample areas 1 2
7. 00x200 2 120x120 3 80x80yum2 November 1997 Figure 10 Influence of the 2 probe interdistance 200x200 um2 sample constant carrier mobility Page 7 The TCAD Driven CAD Journal ATLAS Simulation of SiC Devices Using Anisotropic Mobility Models Introduction There has recently been a great deal of interest and research into using wide band gap mate rials such as silicon carbide in high power high temperature applications The operation of these devices has been found to be signifi cantly different from the similar devices made using silicon These differences are not fully explained by changing the material properties to those of SiC Recent work has shown that the Hall mobilities in SiC are different depending on the crystalline axis where conduction is taking place 1 This anisotropic mobility could dramatically affect device simulation results particularly in power devices where current flow may be fully two dimensional ATLAS has been modified so that this aniso tropic mobility behavior may be modeled accurately as part of the device simulation All of the existing mobility models imple mented in ATLAS support this feature and only require the user to specify the mobil ity parameters in the two crystallographic planes used within the simulation ATLAS then automatically accounts for the change in mobility as the vector of current flow moves through 360 degrees Simulated UMOS Device Figure 1 Struc
8. BP 257 F 38016 Grenoble Cedex 1 France 2Silvaco Data System Sarl 8 av de Vignate 38610 Gi res France Introduction The electrical characterization of SOI wafers is a difficult task due to the thin ness of the film and complexity of the stacked structure This is why the elec trical properties are in general inferred from the analysis of test MOS device or integrated circuits Described below is a simple technique that takes advantage of the specific configuration of SOI and has the potential of being nondestructive The pseudo MOS transistor also called the point contact transistor or Y MOSFET is the first transistor that does not require any lithography or technology at all The W MOSFET is based on the inverted MOS structure that is inherent in all SOI materials Figure 1 shows that the bulk Si drain D source S L Vg 0V VD Si substrate gate substrate contact G substrate can act as a gate terminal and Figure 1 3D structure used for simulation of Y MOSFET can be biased to induce a conduction channel at the upper interface of the bur ied oxide The TCAD Driven CAD Journal Page 4 November 1997 Figure 2 IdVd curve simulation of Y MOSFET The buried oxide plays the role of a gate oxide and the Si film represents the transistor body To operate the W MOSFET in situ without lithography and metallization low pressure probes are placed on the silicon film and form source and drain point cont
9. TCAD Driven CAD A Journal for Process and Device Engineers FastATLAS An Ultra Fast Physical MESFET and HEMT Simulator Introduction By designing specifically for MESFETs and HEMTs Silvaco has optimized device simulation al gorithms to produce a new and highly efficient simulation framework to be released as FastAT LAS Simulations with FastATLAS are typically 1000 to 10000 times faster than ATLAS allowing truly interactive TCAD FastATLAS includes all the relevant physical models currently available with in the ATLAS framework maintaining simulation accuracy while delivering unprecedented speed FastATLAS and ATLAS were both used to simu late a 0 5 micron gate length recessed GaAs MES FET structure The ATLAS structure contained 2700 nodes and averaged around 55 seconds per bias point on a SUN Sparc ULTRA workstation The same structure was simulated with FastAT LAS which automatically generated a mesh using over 15000 nodes yet reduced the simulation time 1 iF ma rt E Caii Liik hii Laii bee ee A Bai ee ee FastAtLAS Simulation Timings EEr Ere Type of Analysis CPU Time on Figure 2 Small signal RF simulaton of a GaAs AlGaAs GaAs HEMT SUAREN biased at 0 volts Vgs 2 volts Vps Frequency sweeps from 1 Ghz to 25 Charge Control analysis 24 seconds GHz in 1GHz intervals DC Id Vds family 2 6 seconds drift diffusion 119 points DC Id Vds family 1 4 seconds ee g 7 ance 99 points to 7 5 milliseconds per bias p
10. Vol 43 No 10 1996 pp 1717 1731 8 M Ruff H Mitlehner and R Helbig SiC Devices Physics and Numerical Simulation IEEE Trans Elect Dev Vol 41 No 6 1994 pp 1040 1054 W J Schaffer G H Negley K G Irvine and J W Palmour Conduc tivityanisotropy in epitaxial 6H and 4H SiC Mat Res Soc Sym Vol 339 1994 pp 595 600 3D Simulation of Heterostructure Devices Introduction De pm eh The three dimensional silicon and GaAs device S24 so F simulator Device3D has now been extended to allow simulation of heterostructure devices within the AT LAS framework The new product Blaze3D includes the modeling of graded and abrupt heterojunction barriers which is critical to the simulation of impor tant classes of devices such as HBTs and HEMTs Two typical examples of the application of Blaze3D are presented here Firstly the collector avalanche breakdown of a SiGe base HBT is simulated Sec ondly a conventional GaAs AlGaAs HEMT with a resistive T gate is simulated in transient mode The progression of a negative gate voltage pulse along the length of the gate is accompanied by the progressive turn off of the channel conduction through the 2DEG in the GaAs Creation of Virtual Device Structures The TCAD Driven CAD Journal al ml fw aa Figure 1 3D super self aligned SiGe HBT structure created and meshed 3 dimensional structures may be created using using DevEdit3D Emitter and base contacts are polysilico
11. acts Despite the device simplicity and nonparallelism of cur rent lines very pure MOSFET like characteristics are produced As shown in Figure 2 the simulated output IV is very similar to a classical MOSFET curve Positive or negative biases can be applied to the gate to form accumulation or inversion channels at the interface Total Current Density Ajon Figure 3 IdVg curve simulation of P MOSFET For example a log Ip Vq characteristic is shown for n channel accumulation in Figure 3 For all the reasons described above the Y MOSFET stands as a unique method permitting a quick and complete evaluation of the electrical properties of SOI wafers prior to any device processing 1 This article describes the use of 3 D numerical simulations which validate the method and show the optimum conditions for application and parameter extraction Structure Definition The structure can be built either the internal syntax of ATLAS or DevEdit3D which allows interactive structure editing structure specification and grid generation for 3D devices The visualization of the structure is made with TonyPlot3D Figure 4 ATLAS is perfectly suited to this kind of simulation although it was developed for the simulation of fully processed devices However special attention has to be paid the contact specification and especially to the determination of the work function for the Schottky contact between the metal probe and the silicon film Si
12. ai CUrrent voltage driven form where the Figure 6 Carrier velocity as a function of electric field V m 1 and doping density m 3 input source current and gate bias are Generated using a 3 valley ensemble Monte Carlo model specified and used to calculate the cor responding drain bias and gate current This new approach allows FastATLAS to reduce simulation times by an order Module Description i of magnitude Unfortunately if a solu FASTBlaze is the simulator that solves DC single point and swept IV simula tion and the small signal time domain RF single point and swept bias simula tions One of the benefits of an extremely fast simulation is that one can perform time domain simulations This is done ek gate Oke aa ere BT omer ew ey within FastATLAS and forms the basis eb jj of the RF simulator In the small signal rey Source simulation sinusoid input signals are ap plied to the terminals and their effects monitored The user can then select from time domain or a variety of two port output options FastGiga incorporates the lattice heat FELT paz flow equations into FastBlaze account Ss j ing for thermal effects particularly hrg important in power applications One u new development is to include a com Lb prehensive transport parameter data base derived from an ensemble Monte Carlo simulation The transport models implicitly include the effects of field doping and importantly for FastGiga l
13. at tice temperature ees Figure 7 Conduction band profile generated by FastATLAS for a 1 2 micron gate MES FET biased at 2 volts Vps November 1997 Page 3 The TCAD Driven CAD Journal tion at a specified drain bias is desired this must be found using ireation on the drain current somewhat reducing the gains in efficiency However importantly if a DC IV sweep is performed the simulator can be left in current driven mode and no iteration is necessary In fact an automatic DC IV generation algorithm has been written that increases the efficiency of the whole simulation since it is able take large steps in the linear regions of device operation and only refines the output in areas of change in particular around the knee of the IV curve and at breakdown The results can then be interpolated onto in dividual drain bias positions with accuracy guaranteed by the tolerance entered into the generation algorithm Typical results are displayed in Figure 5 illustrating the clustering around the knee and larger steps in the ohmic region of de vice operation and as the device goes into saturation The interpolated results taken from this curve have less than 0 003 error compared with the full voltage driven results and were completed in less than 4 of the time Transport options include conventional drift diffusion and hydrodynamic energy balance with a range of different mobility and energy relaxation models An ad ditional
14. cation Engineers Software Developers fax your resume to 408 496 6 080 or Opportunities worldwide for apps engineers Santa Clara Phoenix Austin Boston e mail to Tokyo Guildford Munich Grenoble Seoul Hsinchu Opportunities for developers personnel silvaco com at our California headquarters SIVAC International 4701 Patrick Henry Drive Building 2 Santa Clara CA 95054 Telephone 408 567 1000 Fax 408 496 6080 URL http www silvaco com
15. cted gate technique to deal with this situation defined by current and floating gate charge is only possible if the time scale is known Thus transient simulation should be used in ATLAS The length of the transient This quasistatic method adjusts the error control within needs to be matched to the one shot programming ATLAS to avoid excessively short timesteps It is relevant measurement setup for all other types of quasistatic transient simulations METHOD QUASISTATIC Although the simulation is run as a transient mode the final results are displayed as an Ip Vps curve Figure 3 The curve clearly shows the on set of programming and the i er ee ee ep i ATLAS f DE O LATHE PH CERI Peer final punchthough See i i wpe tiple PE Fpi pe a e U e er e Call for Questions If you have hints tips solutions or questions to contribute please contact our Applications and Support Department Phone 408 567 1000 Fax 408 496 6080 e mail support silvaco com Hints Tips and Solutions Archive E eiai Figure 3 One shot programming characteristic of a Flash Memory Check our our Web Page to see more details of this example plus an device is simulated by using quasi static transient simulation in archeo pio ous inisee and oons ATLAS http www silvaco com November 1997 Page 15 The TCAD Driven CAD Journal Join the Winning Team Silvaco Wants You SPICE Application Engineers Process and Device Appli
16. d a floating gate in ATLAS ATLA Flet REP Py eg a PHA Programming and Erasing simulations in a circuit envi ronment can be performed using ATLAS MixedMode Figure 2 shows a Flash programming simulation where j i oe i ey eT a the EEPROM device is in series with a MOS transistor 1 F simulated in SPICE To highlight MixedMode usage the comparison shows the effect of variations in the series MOSFET on the programming curve 4 z i ar my Ff j Q How can one shot EEPROM programming be i modeled with ATLAS y u a i a a r a rme r aee ee A ATLAS can model the one shot programming by mirroring the test conditions used in measurements In as this test the control gate of Flash memory device is held Carat earned at a high voltage Then the drain is ramped up from zero Figure 2 EEPROM programming simulated in MixedMode Varia to a voltage around breakdown tion in parameters of the series MOSFET is used to illustrate the effect of circuit variation During the Vps ramp at around 2 3V hot electron gate current programs the floating gate causing a Vy shift This causes the drain current to drop and hot electron current to fall off However since the timescale of the drain voltage ramp is typically slow the device is in equilibrium at each If a DC solution was used in ATLAS the results would time step ATLAS includes a special numerical be incorrect since the connection between inje
17. e up to four different electrode names and capacitors The TCAD Driven CAD Journal MTH CLs APT AHY Pike frapeti lle ATLAS EFFECT OF CAPACTING COUPLING ON EEPAOU THRESHOLD Lgl go 3 OGATE wi Aii Ce D ALVADI literaniara Figure 1 Correct setting of the coupling ratio is required for accurate EEPROM thresh Q How can EEPROM devices be simulated in a cir cuit environment using ATLAS MixedMode A Any type of EEPROM or non volatile memory from ATLAS can be embedded in a SPICE circuit and simulated using MixedMode The ATLAS device should be de fined in the circuit netlist using syntax such as AEPR 1 FGATE 1 CGATE 2 DRAIN 0 SUBSTRATE 0 SOURCE WIDTH lt value gt INFILE lt filename gt Note that the floating gate is assigned a negative node number This allows ATLAS to store the change on the floating gate during MixedMode simulations In the numerical device parameter definition of the MixedMode input file the floating gate should still be defined as a floating electrode using the CONTACT statement The coupling capacitances described above should also be defined using the CONTACT statement and the syntax refered to in the previous question Users should not make any connection to the floating gate node in the SPICE circuit This especially includes November 1997 capacitors between the floating gate and any node This HD MEMS is due to the difference in definition of a floating node in SPICE an
18. g profiles to be in corporated into device structures drawn on the screen and provides optimal 3D prismatic mesh generation based on user defined constraints The ability to automati cally generate a conformal non uniform mesh allows arbitrary device geometries to be studied Concentration of mesh in active device re Hie wee fe HEMT FLDMOB and CONMOB mobility models were in voked and single carrier mode was selected to reduce run time The band offsets were set by defining the electron affinity of each layer A 0 6V 2pS gate voltage transient was applied to one end of the gate and the 2DEG channel observed to progressively turn off with time gions with relaxed mesh density elsewhere l wj a wi E Ejdi aja me Xj helps minimize simulation times A wide range of compound semiconductors are supported and layer composition fractions are easily defined Figure 1 shows a TonyPlot3D image of a 3D Si SiGe HBT created using DevEdit3D and based on a device structure reported in 1 The active device region is revealed by selectively removing a region of isolation oxide from the view Concentration of the mesh in the confined SiGe base region may be noted A 3D HEMT structure Figure 2 has the 10um gate stripe extending along the z axis with the channel conduction along the x axis between source and drain Because met als are treated as perfect conductors in ATLAS the resistive gate is modeled by representing the gate metal as
19. he mobility coefficients for the plane lt 0001 gt and secondly with the mobility coefficients for the plane lt 1100 gt As shown in the results the anisotropic mobility November 1997 Simulated DIMOS Structure pinch off region in the channel which lies in icrana the lt 1100 gt plane As a result the anisotropic model gives a higher on resistance than the lt 1100 gt mobility but the saturation current will be close to that obtained for the lt 1100 gt plane but at a much higher drain voltage The anisotropic model also results in a slightly different current flow path for the DIMOS device Figures 5 and 6 show the simulated current flowlines for the isotropic and anisotropic mobility models The anisotropic model is shown to have a different current flow path Firstly the current spreads out more in the n region but is more dense around the corner of the p region This will affect both the series resistance and the self heating in the device Figure 3 Structure of the double implanted MOS DIMOS device for simulation in ATLAS model has given a similar characteristic to the isotropic model with mobility parameters of the lt 0001 gt plane This result can be understood intuitively from Figure 1 as the current path is almost entirely in the lt 0001 gt plane Also the MOS channel to the left of the gate it self lies in the lt 0001 gt plane The only current flow along lt 1100 gt will be in the n so
20. hnology development needs 15 15 16 16 17 17 18 18 CO 1 O UMS E oe Silvaco at MRS Fall Meeting 20 20 Dr Misha Temkin will present a paper showing 21 TCAD W S Tokyo 21 the latest enhancements to ATHENA entitled Computationally Efficient Model for 2D Ion 22 22 Implantation Simulation at the Semiconductor 23 23 Process and Device Performance Modeling Symposium during Material Research Society 24 24 1997 Fall Meeting December 1st 5th in Boston Ma 25 25 Christmas Day 26 ATHENA W S Taiwan 26 27 UTMOST WIS Taiwan 27 28 28 O 29 28 Taiwan Workshops 30 30 Our new Hsinchu office is now open and will 31 start providing regular workshops for Taiwan customers The first two workshops are titled Advanced diffusion models in ATHENA for TCAD users and SmartSpice BSIM3v3 Capacitance Modeling and AC Parameters Extraction using UTMOST for UTMOST users COIN D O JAJU JNJ CIN Io JAJA JO JNJ For more information on any of our workshops please check our web site at http www silvaco com v The TCAD Driven CAD Journal circulation 16 500 Vol 8 No 11 November 1997 is copyrighted by Silvaco International If you or someone you know wants a subscription to this free publication please call 408 567 1000 USA 44 1483 401 800 UK 81 45 341 7220 Japan or your nearest Silvaco distributor Simulation S
21. hown to correctly match the isotropic model In the second example the DIMOS device the Id Vd Characteristics of DIMOS Device sed cep seb Gi ty isotropic cook lity THS ee T puu __ a al E a At T nes Sy ar a se a 3 1 15 a 5 a Lain Veltege iY Figure 4 Simulation results showing the Id Vd characteristics of the DIMOS device using both isotropic and anisotropic mobility models The anisotropic results cannot be matched with just one set of isotropic mobility coefficients The TCAD Driven CAD Journal Carimi Flew Figure 5 Two dimensional plot of the current flowlines in the DIMOS device simulated with the isotropic mobility model complex two dimensional current flow pattern can not be accurately modeled with the isotropic mobility model and only ananisotropic mobility model will yield the correct I V characteristics References 1 M Schadt and G Pensl Anisotropy of the electron Hall mobility in4H 6H and 15R silicon carbide Appl Phys Lett Vol 65 1994 pp 3120 3122 Carem Flowliees in DIMOS Device Anloireple Wiobility Woe mait pele Figure 6 Two dimensional plot of the current flowlines in the DIMOS device simulated with the anisotropic mobility model The current spreading and current concentration with this model are different to those found with the isotropic mobility model 2 B Jayant Baliga Trends in power semiconductor devices IEEET rans Elect Dev
22. ll color graphics of the 3D hetro tion showing graph of impact ionization rate with depth under poly emitter stripe structures may be viewed at www silvaco com Simulation Results Results of device simulation are gener ally in the form of terminal current voltage characteristics and 3D structure files The latter may be viewed and analyzed using lala ra Eabh naei TonyPlot3D which provides advanced im good cote hereto M A on aging and dissection capabilities Taking the example of the HBT breakdown the region of avalanche multiplication may be imaged as isosurfaces of impact generation rate Figure 3 A 2D cut plane exported to Tonyplot Figure 4a gives a different perspective and a 1D cut line allows a graph to be drawn Figure 4c Figure 4b shows the breakdown characteristic It may be observed in these plots that the avalanche breakdown in this HBT occurs primarily in the n SiGe collector extension region The purpose of this layer is to avoid a potential barrier at the SiGe base Si collector interface 1 The response of the T gated HEMT to a gate bias transient can be observed in Figure 5 which shows a 2D cut plane taken along the principal axis of the T gate The contours in G ALAT Iara re the gate region represent the voltage which Figure 5 2D cut plane taken from a Blaze3D solution for the 3D HEMT during a negative gate bias transient The section is along the major axis of the resistive T gate
23. mulation ATLAS simulation calculates Ig and IpVp charac teristics for both inversion and accumulation channels in either n or p doped films Figure 5 In addition the simulations offer the distribution of the charge potential Figure 7 and electric field The accuracy Figure 4 Current density lines border effect free structure from Device3D simulation November 1997 Page 5 The TCAD Driven CAD Journal g 114 bed L 3yr accua El ilen vouinom r ELI ESTEE TE EE a mde hos Va TH Figure 5 Simulated Ip Vge and gm Vo of the simulations has been validated by comparison with systematic experimental data example in Figure 6 and by a self consistent procedure standard param eter extraction from the simulated curves and coherence of the output parameters with those initially fed into the simulator carrier mobility doping oxide charges These simulations deliver illuminating information on the influence of several key parameters film and substrate doping film and buried oxide thickness Schottky contact depth series resistances interface roughness Eyaprierial Jait unken in Sean 0 SACO RT Figure 7 Equipotential line distribution in a 240x240pm2 sample The TCAD Driven CAD Journal Page 6 bd t Dain porcine G pA Mansom g m i ie i flake Flay Yu jY Figure 6 Experimental MOSFET curves in a p type UNIBOND More complex experimental situations have also been reprod
24. n A section of ATLAS command syntax or more easily by using oxide isolation is removed from the view to reveal the confined SiGe base DevEdit3D the 3D extension to the powerful De egion with denser mesh November 1997 Selection of Models All the mobility models available in Blaze are incorporated in Blaze3D concentra tion transverse field and parallel field de pendence negative differential mobility or simple velocity saturation Blaze3D also supports multiple recombination mecha nisms Auger radiative and concentration dependent Schockley Read Hall and band gap narrowing for simulation of bipolar transistors Single event upset may be modeled as in Device3D and impact ion ization may also be modeled to investigate breakdown limitations Blaze3D carries the same comprehensive materials library as Blaze This includes parameter defaults for more than 40 compound semiconduc tors Arbitrary user defined materials and properties are also supported The SiGe HEMT with fore C rea ec Coe ECCECEDOL c FOWHFLOT C Enam HBT was simulated using the AUGER TOMVALOTID RAZA atiras CONSRH FLDMOB CONMOB BGN and Figure 2 3D AlGaAs GaAs HEMT structure with resistive T gate and end gate IMPACT models and biased into avalanche contact from DevEdit3D breakdown in the collector region under zero gate bias For the simulation of the 3D vedit device design and meshing package DevEdit3D allows simulated or analytic dopin
25. oint a speed increase by a P I 2 5 seconds factor of 7000 FastATLAS timings for typical analyses ance oOInts i are given in Figure 1 Rf rapid 1 3 seconds energy balance 33 points Rf full period 2 5 seconds energy balance 128 points Rf swept full period 59 seconds Continued on page SATA energy balance 7552 points Figure 1 All simulations were on a 0 5um gate length INSIDE recessed MESFET The DC IV simulations were taken over the range 2 lt Vgs lt 0 0 5 volt increments i 0 lt Vds lt 5 0 1 volt increments The Id Vgs sweep was ATLAS Simulation of SiC Devices Using taken over the range 2 lt Vgs lt 0 0 1 volt increment Vds ison oie MODNYM 0 1 volts The RF simulations were taken at the bias 3 Dimensional Simulation of Heterostructure Devices point Vgs 0 Vds 2 volts freq 20 GHz and the RF Calendar of Events swept simulation was taken at Vgs 0 Vds 2 volts Hints Tips and Solutions 1 lt freq lt 30 GHz 0 5 Ghz increment 3D Numerical Simulation of the Pseudo MOS Transistor Volume 8 Number 11 November 1997 Comprehensive material and transport parameters database Core Simulation automatic mesh generator automatic solution section wide selection of C Interpreter physical models Figure 3 Architecture of FastATLAS framework FastATLAS Architecture The complete suite of FastATLAS modules is illustrated in Figure 3 The core simulator incorporates the phy
26. si cal models present in ATLAS including complex effects such as energy balance and velocity overshoot These features are coupled with a comprehensive material pa rameter database input parser c interpreter and several post processing options including various two port and equivalent circuit extraction algorithms FastATLAS has been designed to be user friendly and includes several features to enable ease of use One important de velopment has been the inclusion of an automatic mesh generation algorithm relieving the user from this ardu ous and time consuming task The speed of the simu lation process enables FastATLAS to perform trial ag eee Figure 4 Mesh layout around the gate automatically generated with in FastATLAS Typical mesh size at drain edge of gate 2 8 x 0 6nm The TCAD Driven CAD Journal FastBlaze DC IV extraction Small Signal RF extraction latice heat flow equation independence connec equivalent circuit local noise extraction AE noise parameter extraction Post Processing two port extractio FastMixedMode circuit embedded device simulation large signal solutions using an exceptionally dense mesh typically with only two Angstrom node spacing The solutions are then analyzed and a non uniform mesh generated that maintains solution accuracy and enables high simu lation speed A typical mesh generated by FastATLAS is shown in Figure 4 illustrating the clustering of nodes
27. tandard TCAD Driven CAD Virtual Wafer Fab Analog Alliance Legacy ATHENA ATLAS FAST ATLAS ODIN VYPER TSUNAMI RESILIENCE TEMPEST CELEBRITY Manufacturing Tools Automation Tools Interactive Tools TonyPlot DeckBuild DevEdit Interpreter ATHENA Interpreter ATLAS Interpreter Circuit Optimizer MaskViews PSTATS SSuprem3 SSuprem4 Elite Optolith Flash Silicides SPDB CMP MC Deposit MC Implant Process Adaptive Meshing S Pisces Blaze Device 3D Thermal 3D Interconnect 3D TFT Luminous Giga MixedMode ESD Laser FastBlaze FastMixedMode FastGiga FastNoise UTMOST UTMOST II UTMOST III UTMOST IV PROMOST SPAYN SmartSpice MixSim Twister FastSpice SmartLib SDDL EXACT CLEVER STELLAR HIPEX Scholar SIREN ESCORT STARLET Expert Savage Scout Guardian and Envoy are trademarks of Silvaco International November 1997 Page 13 The TCAD Driven CAD Journal Hints Tips and Solutions Andy Strachan Applications and Support Manager Q How is the coupling ratio between Tis i Are the floating gate and control gate of a Flash EEPROM modeled in ATLAS A In EEPROM devices the floating gate is capacitively coupled to the control gate and the substrate The exact ratio of the cou pling is determined by the relative shape of the floating and control gate electrodes as well as the inter gate layer thicknesses For most structures full3Dsimulationswould be required to model the control and float ing gate
28. ture of the trench gated MOS device UMOS for simulation in ATLAS Simulated id Vd Characteristics for UMOS Device a a aincropec miley mobility lt ih lent E ltrepit mobility lt H gt tit titiotbinibes i HH 0 l r tt o 7 w a In Drain Vebtage F Figure 2 Simulation results of the Id Vd characteristics of the UMOS device using isotropic and anisotropic mobility models The anisotropic mobility results can be matched with one set of appropriate isotropic mobility coefficients The TCAD Driven CAD Journal Page 8 To illustrate the effects that this model has on numerical simulation we have performed simulations on two 6H SiC transistor struc tures the trench gated MOS UMOS and the double implanted MOS DIMOS transis tor 2 with the standard physical material parameters suggested in 3 The mobilities were defined for the planes lt 0001 gt and lt 1100 gt which resulted in a perpendicular to parallel mobility ratio of 5 as suggested by 4 The plane lt 1100 gt contains the greater mobility values for both electrons and holes Simulation Results Figure 1 shows the first structure to be simu lated the UMOS device The Id Vd character istics of this device were simulated with both the standard isotropic and the anisotropic mobility models The results of these simula tions are shown in Figure 2 Two simulations were performed using the standard mobility model firstly with t
29. uced successfully In a narrow range of gate voltages a depletion region forms underneath the buried oxide The depletion capacitance apparently modifies the oxide capaci tance and gives rise to a hump in the drain current and tranconductance dotted circle in Figure 5 This hump can be used to evaluate the substrate doping In accumulation the current flows not only at the interface but also in the film volume The simulations allow to make distinction between these two components as a function of film doping and thickness A practical concern with the YMOSFET technique is the geometrical factor f which replaces the transistor aspect ratio W L and is not known a priori This factor is estimated experimentally by the comparison between the MOS FET and 4 point probe data 1 Any uncertainty directly impacts on the ex traction accuracy of the carrier mobility and threshold voltage 3 D simulations do show the non parallel current flow lines across the sample Figure 4 We verified that in samples large enough when compared to the probe interdistance the geometri cal factor is roughly f 0 7 in full agree ment with the experiment A typical problem which can be sloved using 3 D simulations is the influence of the sample size and the proximity of the borders The investigation was con ducted by either shrinking the sample size or by placing the contacts closer November 1997 to the edges In both cases
30. urce region where there is only minimal resistance As a result the mobility chang es little along the current flow path and can be simulated using an isotropic mobility model Figure 3 shows the second device under analysis the DIMOS device The Id Vd characteristics of this device were once again obtained with both the standard isotropic and the anisotropic mobil ity models and are shown in Figure 4 In this device three different curves are obtained The two curves obtained from the isotropic mobility model for planes lt 0001 gt and lt 1100 gt are both different to that obtained using the anisotropic mobil ity model This difference is a result of the current flowing partly in the lt 0001 gt plane and partly in the lt 1100 gt plane The MOS channel lies in the plane lt 1100 gt which is the high mobility plane whilst the major ity of the distance over which the current flows is in the lt 0001 gt plane Therefore the on resistance which is controlled by the lt 0001 gt plane will be quite high Howev er current saturation is controlled by the November 1997 Page 9 Conclusions A new implementation of the mobility model into the semiconductor equations allows either isotropic or anisotropic mobility behavior tobe modeled The imple mentation fully supports all the mobility models that are currently included in ATLAS Two examples have been demonstrated For a UMOS device the anisotopic mobil ity model was s
Download Pdf Manuals
Related Search