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8-Bit XC82x

1. V1 0 2010 02 23 12 Figure 23 2 SET_LDLINE_CMP Function SFR Settings User s Manual ROM Library V0 5 Cinfineon XC82x ROM Library 23 2 1 1 Inputs for SET_LDLINE_CMP Function LED only If only LED module is enabled the inputs overview is shown in Table 23 8 Examples of input parameters for 2 4 6 or 8 LEDs enabled are also shown in Figure 23 3 Table 23 8 Specifications of Setting LDLINE amp COMPARE LED only Subroutine SET LDLINE CMP Address DFCF Input R7 of current Register Bank Start IRAM address of LDLINE parameters R5 of current Register Bank Start IRAM address of COMPARE parameters LDLINE parameters programmed into IRAM R7 R7 1 etc R7 LDLINE parameter for COLA R7 1 LDLINE parameter for COLO R7 y 1 LDLINE parameter for COL y 2 COMPARE parameters programmed into IRAM R5 R5 1 etc 5 COMPARE parameter for 5 1 COMPARE parameter for COLO R5 y 1 COMPARE parameter for COL y 2 Output Sfr LTS LDLINE is programmed Sfr LTS COMPARE is programmed Stack size required 2 Resource used destroyed A RO R1 R2 R3 R4 1 Depending how many LED s is are enabled y no of LED s enabled User s Manual ROM Library V0 5 23 13 V1 0 2010 02 Infineon XC82x ROM Library
2. Table 3 9 CCU6 Register Overview cont d Addr Register Name Bit 7 6 5 4 3 2 1 0 CCU6_TCTR4H Reset 004 Bit Fie T13 T13 0 T13 T13R TISR Timer Control Register 4 High STD STR RES S R Type w w f w w w CCU6 MCMOUTSL Reset 00y Bit Field STRM 0 MCMPS Multi Channel Mode Output Shadow CM Register Low Type w r CCU6 MCMOUTSH Reset 00 Bit Fiel STRH 0 CURHS EXPHS Multi Channel Mode Output Shadow Register High Type w r rw rw 4 CCU6_ISRL Reset 004 Bit Fie RT12 RT12 RCC6 RCC6 RCC6 RCC6 RCC6 RCC6 Capture Compare Interrupt Status PM OM 2F 2R 1 1R OF OR Reset Register Low Type w w w w w w w w ASH CCU6_ISRH Reset 004 Bit Fie RSTR RIDLE RWH RCHE 0 RTRP RT13 RT13 Capture Compare Interrupt Status CM Reset Register High Type w w w w r w w w A6H CCU6 CMPMODIFL Reset 00 Bit Fiel 0 MCC6 0 MCC6 MCC6 MCC6 Compare State Modification Register 3S 25 15 05 Low Type r w r w w w CCU6 CMPMODIFH 00 Bit Fiel 0 MCC6 0 MCC6 MCC6 MCC6 Compare State Modification Register 3R 2R 1R OR High Type w r w w w FAH CCU6_CC60SRL Reset 004 Bit Fie CC60SL Capture Compare Shadow Register for Channel CC60 Low Type rwh CCU6_CC60SRH Reset 00 Bit Fie CC60SH Capture Compare Shadow Register for Channel CC60 High Type rwh FCH CCU6_CC61SRL Reset 00 Bit Fie CC61SL Capture Compare Shadow Registe
3. Value of Status STAT register 00 Bus error 08 START condition transmitted 10 Repeated START condition transmitted 184 Address and write bit transmitted ACK received 204 Address and write bit transmitted ACK not received 284 Data byte transmitted in master mode ACK received 30 Data byte transmitted in master mode ACK not received 38 Arbitration lost in address or data byte 40 Address and read bit transmitted ACK received 48 Address and read bit transmitted ACK not received 50 Data byte received in master mode ACK transmitted 58 Data byte received in master mode ACK not transmitted 60 Slave address and write bit received ACK transmitted 68 Arbitration lost in address as master slave address and write bit received ACK transmitted 70 General call address received ACK transmitted 78 Arbitration lost in address as master general call address received ACK transmitted 80 Data byte received after slave address received ACK transmitted 88 Data byte received after slave address received ACK not transmitted 90 Data byte received after general call address received ACK transmitted 98 Data byte received after general call address received ACK not transmitted User s Manual 17 4 V1 0 2010 02 V1 1 Cinfineon Inter IC Bus Table 17 4 Status Code Value of Status STAT register AOp ST
4. 1 2 l P1 P2 1 2 1 2 I P1 P2 NEM TE 2 1 Interrupt request 1 4 I Interrupt I polled LCALL 1 instruction at request i last cycle of interrupt vector active sampled current I instruction gt Interrupt response time 3 x machine cycle Figure 9 9 Minimum Interrupt Response Time A longer response time would be obtained if the request is blocked by one of the three previously listed conditions 1 If an interrupt of equal or higher priority is already in progress the additional wait time will depend on the nature of the other interrupt s service routine 2 If the instruction in progress is not in its final cycle the additional wait time cannot be more than three machine cycles since the longest instructions MUL and DIV are only four machine cycles long See Figure 9 10 3 If the instruction in progress is RETI or a write access to registers IENO IEN1 or IP H IP1 H the additional wait time cannot be more than five cycles a maximum of one more machine cycle to complete the instruction in progress plus four machine cycles to complete the next instruction if the instruction is MUL or DIV See Figure 9 11 User s Manual 9 14 V1 0 2010 02 Interrupt System V 2 3 3 Infineon Interrupt System
5. Table 7 5 SFR Address List for SCU Pages 0 7 Address Page 0 Page 1 Page 2 Page 3 F24 IRCONO PASSWD XADDRH F3 IRCON1 PMCONO MODPISEL F4 EXICON1 OSC CON MODPISEL1 F5 IRCON2 ID MODPISEL2 F6 IRCON3 WDTCON MODSUSP F74 NMISR RSTCON MODIEN EE NMICON SDCON MODPISEL3 EF EXICONO 1 Address Page 4 Page 5 Page 6 Page 7 F24 BCON F3 WDTREL BGL WDTWINB BGH F5 WDTL LINST F6 WDTH FEAL F74 FEAH User s Manual 7 26 V1 0 2010 02 Cinfineon Watchdog Timer 8 Watchdog Timer 8 1 Overview The Watchdog Timer WDT provides a highly reliable and secure way to detect and recover from software or hardware failures The WDT is reset at a regular interval that is predefined by the user The CPU must service the WDT within this interval to prevent the WDT from causing an XC82x system reset Hence routine service of the WDT confirms that the system is functioning properly This ensures that an accidental malfunction of the XC82x will be aborted in a user specified time period The WDT is by default disabled In debug mode the WDT is default suspended and stops counting its debug suspend bit is default set i e MODSUSP WDTSUSP 1 Therefore during debugging there is no need to refresh the WDT Features e 16 bit Watchdog Timer Programmable reload value for upper 8 bits of timer Programmable window boundary Input frequency from a secondary clock sourc
6. ejdues 1 E E RA oT Receive E 49019 J yesel E TTITITTTTTTIT Figure 16 2 Serial Interface Modes 2 and 3 Timing Diagram 16 7 V1 0 2010 02 User s Manual UART V 1 6 Cinfineon UART 16 4 Multiprocessor Communication Modes 2 and 3 have a special provision for multiprocessor communication using a system of address bytes with bit 9 1 and data bytes with bit 9 0 In these modes 9 data bits are received The 9th data bit goes into RB8 The communication always ends with one stop bit The port can be programmed such that when the stop bit is received the serial port interrupt will be activated only if RB8 1 This feature is enabled by setting bit SM2 in SCON One of the ways to use this feature in multiprocessor systems is described in the following paragraph When the master processor wants to transmit a block of data to one of several slaves it first sends out an address byte that identifies the target slave An address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte With SM2 1 no slave will be interrupted by a data byte An address byte however will interrupt all slaves so that each slave can examine the received byte and see if it is being addre
7. Table 20 9 Multi Input Capture Modes Overview MSEL6x Mode Signal Active Edge T12 Stored in 1010 5 CC6xIN Rising CC6xR CCPOSx Falling CC6xSR 1011 6 CC6xIN Falling CC6xR CCPOSx Rising CC6xSR 1100 7 CC6xIN Rising CC6xR CCPOSx Rising CC6xSR 1101 8 CC6xIN Falling CC6xR CCPOSx Falling CC6xSR 1110 9 CC6xIN Any CC6xR CCPOSx Any CC6xSR 1111 reserved capture compare action User s Manual CCU6 V4 0 20 40 V1 0 2010 02 Cinfineon Capture Compare Unit 6 CCU6 20 3 6 12 Shadow Register Transfer A special shadow transfer signal T12_ST can be generated to facilitate updating the period and compare values of the compare channels CC60 CC61 and CC62 synchronously to the operation of T12 Providing a shadow register for values defining one PWM period facilitates a concurrent update by software for all relevant parameters The next PWM period can run with a new set of parameters The generation of this signal is requested by software via bit TCTROL STE12 set by writing 1 to the write only bit TCTR4L T12STR cleared by writing 1 to the write only bit TCTR4L T12STD Figure 20 22 shows the shadow register structure and the shadow transfer signals as well as on the read write accessibility of the various registers Read Read Read Read li CC6xPS COUT6xPS Shadow Shadow Write Write Write Write Read hd e T12 ST Other Modes Hall
8. 7 6 5 1 0 0 EXINT6 5 4 rw rw rw Field Bits Type Description EXINT4 1 0 rw External Interrupt 4 Trigger Select 00 Interrupt on falling edge 01 Interrupt on rising edge 10 Interrupt on both rising and falling edge 11 External interrupt 4 is disabled EXINT5 3 2 rw External Interrupt 5 Trigger Select 00 Interrupt on falling edge 01 Interrupt on rising edge 10 Interrupt on both rising and falling edge 11 External interrupt 5 is disabled EXINT6 5 4 rw External Interrupt 6 Trigger Select 00 Interrupt on falling edge 01 Interrupt on rising edge 10 Interrupt on both rising and falling edge 11 External interrupt 6 is disabled 0 7 6 r Reserved Returns 0 if read should be written with 0 MODPISEL1 Peripheral Input Select Register 1 F4 Reset Value 00 RMAP 0 PAGE 3 7 6 5 1 0 0 EXINT1IS 0 EXINTOIS URRIS r rw rw TW User s Manual 9 22 V1 0 2010 02 Interrupt System V 2 3 3 Cinfineon Interrupt System Field Bits Description EXINTOIS 4 3 rw External Interrupt 0 Input Selection 00 External Interrupt Input EXINTO 0 is selected 01 External Interrupt Input EXINTO 1 is selected 10 External Interrupt Input EXINTO 2 is selected 11 X External Interrupt Input EXINTO 3 is selected EXINT1IS 6 rw External Interrupt 1 Input Select 0 External Interrupt Input EXINT1 0 is selected 1 External Interrupt Input EXINT1 1 is selected
9. delayed T12DTCH Dead Time Control Register for Timer T12 High A54 Reset Value 00 RMAP 0 PAGE 1 7 6 5 4 3 2 1 0 0 DTR2 DTR1 DTRO 0 DTE2 DTE1 DTEO r rh rh rh r rw rw rw User s Manual 20 49 V1 0 2010 02 CCUG V4 0 Cinfineon XC82x Capture Compare Unit 6 CCU6 Field Type Description DTE2 DTE1 DTEO Dead Time Enable Bits Bits DTEO DTE2 enable and disable the dead time generation for each compare channel 0 1 2 of timer T12 Oy Dead Time Counter x is disabled The corresponding outputs switch from the passive state to the active state according to the actual compare status without any delay 1g Dead Time Counter x is enabled corresponding outputs switch from the passive state to the active state according to the compare status with the delay programmed in bit field DTM DTR2 DTR1 DTRO Dead Time Run Indication Bits Bits DTRO DTR2 indicate the status of the dead time generation for each compare channel 0 1 2 of timer T12 Dead Time Counter x is currently in the passive state 13 Dead Time Counter x is currently in the active state m reserved returns 0 if read should be written with 0 User s Manual CCU6 V4 0 20 50 V1 0 2010 02 Cinfineon Capture Compare Unit 6 CCU6 20 3 9 Control Registers 20 3 9 1 Channel State Bits The Co
10. BPSEL Register Selected BPSEL Register Selected Oxxx reserved no selection 1000 HWBPOL 1001 HWBPOH 1010 HWBP1L 1011 HWBP1H 1100 HWBP2L 1101 HWBP2H 1110 HWBP3L 1111 HWBP3H User s Manual 10 14 V1 0 2010 02 OCDS V 2 7 1 Cinfineon XC82x 10 8 1 Control and Status Registers MMICR Monitor Mode Interrupt Control Register F4 RMAP 1 PAGE X Debug System Reset value 00 7 6 5 4 3 2 1 0 FNMIRW FNMIRR NMIRWE NMIRRE rwh rwh rw rw Field Bits Type Description NMIRRE 0 rw NMI upon IRAM read refer to Section 10 6 1 0 Disabled 1 Enabled NMIRWE 1 rw NMI upon IRAM write refer to Section 10 6 1 0 Disabled 1 Enabled FNMIRR 2 rwh Read NMI Flag FNMIRW 3 rwh Write NMI Flag FNMIRR FNMIRW bits set by hardware in case of NMI request from OCDS activated upon read write access to the Internal RAM refer to Section 10 5 1 and Section 10 6 1 the software can only reset these bits User s Manual 10 15 OCDS V 2 7 1 V1 0 2010 02 Cinfineon Debug System 10 8 2 Hardware Breakpoint Registers All of the Hardware Breakpoint Registers HWBPOL HWBP3H within OCDS can be set to the desired compare values indirectly by writing only to one software accessible register HWBPDR after BPSEL bitfield within the select register HWBPSR has been properly programmed refer to Table 10
11. LED and Touch Sense N RARR Flash Controller VA T bit Digital VO T On Chip Boot ROM Capture Compare Unit Debug Port 1 6 bit Digital VO 8K Bytes 16 bit Support XC800 Core ADC XRAM Compare Unit SE 256 Bytes 16 bit 10 bit Port2 4 bit Digital Analog Input 4 channel RAM Timer 0 Timer 1 Timer 2 Real Time Watchdog MDU 256 Bytes 16 bit 16 bit 16 bit Clock Timer Figure 1 1 XC82x Functional Units User s Manual 1 1 V1 0 2010 02 System Architecture V1 0 Cinfineon 1 1 Introduction XC82x Feature List The following list summarizes the main features of the XC82x High performance XC800 Core compatible to standard 8051 Core two clocks per machine cycle architecture for memory access without wait state two data pointers On chip Memory 8 KByte Boot ROM for startup firmware Flash and User routines and ROM library 256 byte RAM plus 64 byte Monitor RAM 256 byte XRAM 4 KByte Flash for program code and data includes memory protection strategy I O port supply at 2 5 5 5V and core logic supply at 2 5V generated by embedded voltage regulator Power on reset generation Brown out detection for IO supply and core logic supply On chip OSC for clock generation Loss of clock detection Power saving modes idle mode power down mode with wake up capability via real time clock interrupt clock gating control to each peripheral Watchdog Timer WDT with p
12. 19 18 1 Inizio 19 19 1 Registers 19 20 1 Global Control and Status 19 21 1 Function Control Registers 19 24 1 Capture Compare Unit 6 CCU6 20 1 1 ie eed 20 1 1 Feature Set Overview 20 2 1 Block Diagram 2 02 2 re per ede ees 20 3 1 Register Overview 20 4 1 System Information 20 8 1 PINNING 20 8 1 Clocking 20 12 1 Interrupt Events and Assignment 20 13 1 IP Interconnection 20 15 1 Module Suspend Control 20 17 1 Operating Timer T12 20 17 1 TIZ OVEIVIGW iis az ee E E EE 20 19 1 T12 Counting Scheme 20 21 1 Clock Selection 22252045000 ERE ER 20 21 1 Edge Aligned Center Aligned Mode 20 21 1 Single Shot Mode 20 24 1 T12 Compare 20 25 1 Compare Ch
13. A Vasmi Vauemz Y vaes CC6x 2 2 CC6x 1 CC6x 1 a CC6x 1 CC6x 0 CC6x 0 CC6x 0 b _ CC6x 3 3 CC6x 3 CC6x 3 4 4 CC6x 4 CC6x 4 a CC6x 5 CC6x 5 CC6x 5 CC6x 5 CC6x 3 CC6x 6 CC6x 6 CC6x 6 f CCU6_MCT05517 Figure 20 13 Compare Waveform Examples Example b illustrates the transition to a duty cycle of 100 First a compare value of 0001 is used then changed to 0000 Please note that a low pulse with the length of one T12 clock is still produced in the cycle where the new value 0000 is in effect this pulse originates from the previous value 0001 In the following timer cycles the State Bit CC6xST remains at 1 producing a 10096 duty cycle signal In this case the compare rule zero match AND compare match is in effect Example f shows the transition to a duty cycle of 0 The new compare value is set to lt Period Value gt 1 and the State Bit CC6ST remains cleared Figure 20 14 illustrates an example for the waveforms of all three channels With the appropriate dead time control and output modulation a very efficient 3 phase PWM signal can be generated User s Manual 20 29 V1 0 2010 02 CCU6 V4 0 Cinfineon Capture Compare Unit 6 CCU6 Period Value CC61R CC62R T12 Count CC60R Zero Down CDI
14. Field Bits Description WDTRS 1 rwh_ WDT Refresh Start Active high Set to start refresh operation on the watchdog timer Cleared automatically by hardware after it is set by software WDTEN 2 rw WDT Enable 0 WDT is disabled 1 WDT is enabled WDTEN is a protected bit If the Protection Scheme is activated then this bit cannot be written directly See protection Scheme for more details Note Clearing WDTEN bit to 0 during Prewarning Mode WDTPR 1 has no effect WDTPR 4 rh Watchdog Prewarning Mode Flag 0 Normal mode default after reset 1 The Watchdog is operating in Prewarning Mode This bit is set to 1 when a Watchdog error is detected The Watchdog Timer has issued an NMI trap and is in Prewarning Mode A reset of the chip occurs after the prewarning period has expired WINBEN 5 rw Watchdog Window Boundary Enable 0 Watchdog Window Boundary feature is disabled default 1 Watchdog Window Boundary feature is enabled 0 0 3 r Reserved 7 6 Returns 0 if read should be written with 0 User s Manual 8 8 V1 0 2010 02 WDT V1 0 Cinfineon Watchdog Timer WDTL Watchdog Timer Low Byte F5 Reset Value 00 RMAP 0 PAGE 4 7 6 5 4 3 2 1 0 WDT th Field Bits Type Description WDT 7 0 rh Watchdog Timer Current Value WDTH Watchdog Timer High Byte F6 Reset Value 00
15. Field Bits Type Description RI 0 rwh Serial Interface Receiver Interrupt Flag Set by hardware if a serial data byte has been received Must be cleared by software TI 1 rwh Serial Interface Transmitter Interrupt Flag Set by hardware at the end of a serial data transmission Must be cleared by software NMISR NMI Status Register 7 Reset Value 00 RMAP 0 PAGE 0 7 6 5 4 3 2 1 0 FNMI FNMI FNMI FNMI FNMI 0 VDDP VDDC OCDS FLASH OSCCLK FNMIWDT r rwh rwh rwh rwh rwh rwh rwh Field Bits Type Description FNMIWDT 0 rwh Watchdog Timer NMI Flag 0 No watchdog NMI has occurred 1 WDT prewarning has occurred FNMIOSCCLK 1 rwh 48 MHz or 75 KHz Oscillator Clock NMI Flag 0 No 48 MHz or 75 KHz Oscillator NMI has occurred 1 48 MHz or 75 KHz loss of clock has occurred FNMIFLASH 2 rwh Flash Operation Complete NMI Flag 0 No Flash NMI has occurred 1 Flash operation complete event has occurred FNMIOCDS 3 rwh_ OCDS NMI Flag 0 No OCDS NMI has occurred 1 JTAG receiving or user interrupt request in Monitor Mode has occurred FNMIVDDC 4 rwh VDDC Prewarning NMI Flag 0 No Vppc NMI has occurred 1 Vppc Prewarning drop below 2 3V has occurred User s Manual 9 28 V1 0 2010 02 Interrupt System V 2 3 3 Cinfineon XC82x Interrupt System Field Bits Type Description FNMIVDDP 5 rwh VDDP Prewarning NMI Flag 0 No NMI has occurred 1 Vppp prewarning drop below 4 0V f
16. il ir i ECTRC RTCCR2 RTCCR3 Bit 0 Bts Bt 16 17 Bit 23 24 Bt 31 Real Time Clock Registers These bits are unreadable Figure 15 1 Real time Clock Mode 1 While the real time clock is in operation the contents of RTCCR register will be compared to the real time clock counter CNT An interrupt will be generated in active mode when the contents are equal if ECRTC is set to 1 bit CFRTC in register RTCON User s Manual 15 3 V1 0 2010 02 RTC V1 0 Cinfineon Real Time Clock will be set This will generate a wake up from the software power down when the device is in power down mode 2 The CFRTC flag can be monitored for the real time clock wake up request but the flag has to be cleared by user software In such situation the real time clock is reset and count from zero again The handling of the wake up is similiar to the wake up from power down mode through EXINTO pin Note No wake up interrupt is generated after wake up from power down mode without reset It is irregardless of the status of ECRTC bit However the CFRTC flag is set to 1 after wake up in such situation With RTC mode 1 in power down mode 2 it is able to wake up at a fixed time by programming the number of count value that is equivalent to the length of time to wake up in the RTCCR register The real time clo
17. Eg 2 LED No TS enabled Eg 4 LED No TS enabled Eg 6 LED No TS enabled Eg 8 LED No TS enabled LDLINE A R7 LDLINE A R7 LDLINE A R7 LDLINE A R7 LDLINE 0 R7 1 LDLINE 0 R7 1 LDLINE 0 R7 1 LDLINE 0 R7 1 LDLINE 1 R7 2 LDLINE 1 R7 2 LDLINE 1 R7 2 COMPARE A R5 LDLINE 2 R7 3 LDLINE 2 R7 3 LDLINE 2 R7 3 COMPARE 0 5 1 LDLINE 3 R7 4 LDLINE 3 R7 4 COMPARE A R5 LDLINE 4 R7 5 LDLINE 4 R7 5 COMPARE 0 R5 1 LDLINE 5 R7 6 COMPARE 1 R5 2 COMPARE A R5 LDLINE 6 R7 7 COMPARE 2 R5 3 COMPARE 0 R5 1 COMPARE 1 R5 2 COMPARE A R5 COMPARE 2 R5 3 COMPARE 0 R5 1 COMPARE 3 R5 4 COMPARE 1 R5 2 COMPARE 4 R5 5 COMPARE 2 R5 3 COMPARE 3 R5 4 COMPARE 4 R5 5 For LED COMPARE 5 R5 6 For Touch Sense COMPARE 6 R5 7 Figure 23 3 Input Parameters Example LED enabled only User s Manual 23 14 V1 0 2010 02 ROM Library V0 5 Cinfineon ROM Library 23 2 1 2 Inputs for SET_LDLINE_CMP Function Touch sense only If only Touch sense module is enabled the inputs overview is shown in Table 23 9 Table 23 10 for common and different compare parameters setting for oscillation window respectively Examples of input parameters are also shown in Figure 23 4
18. 16 3 UART Modes The UART can be used in four different modes In mode 0 it operates as an 8 bit shift register In mode 1 it operates as an 8 bit serial port In modes 2 and 3 it operates as a 9 bit serial port The only difference between mode 2 and mode 3 is the baud rate which is fixed in mode 2 but variable in mode 3 The variable baud rate is set by either the underflow rate on the dedicated baud rate generator or by the overflow rate on Timer 1 The different modes are selected by setting bits SMO and SM1 to their corresponding values as shown in Table 16 4 Table 16 4 UART Modes SMO SM1 Operating Mode Baud Rate 0 0 Mode 0 8 bit shift register 2 0 1 Mode 1 8 bit shift UART Variable 1 0 Mode 2 9 bit shift UART 64 or fog 432 1 1 Mode 3 9 bit shift UART Variable 16 3 1 Mode 0 8 Bit Shift Register Fixed Baud Rate In mode 0 the serial port behaves as an 8 bit shift register Data is shifted in through RXD and out through RXDO while the TXD line is used to provide a shift clock which can be used by external devices to clock data in and out User s Manual 16 3 V1 0 2010 02 UART V 1 6 Cinfineon UART The transmission cycle is activated by a write to SBUF One machine cycle later the data has been written to the transmit shift register with a 1 at the 9th bit position For the next seven machine cycles the contents of the transmit shift register are
19. 2 This bit has a shadow bit and is updated in parallel to the compare and period registers of T13 A read action targets the actually used values whereas a write action targets the shadow bit User s Manual 20 52 V1 0 2010 02 CCU6 V4 0 Cinfineon Capture Compare Unit 6 CCU6 The Compare Status Modification Register CMPMODIFL H provides software control independent set and clear conditions for the channel state bits CC6xST This feature enables the user to individually change the status of the output lines by software for example when the corresponding compare timer is stopped CMPMODIFL Compare State Modification Register Low Reset Value 00 RMAP 0 PAGE 0 7 6 5 4 3 2 1 0 0 MCC63S 0 MCC62S MCC61S MCC60S r w r w w Ww Field Bits Type Description MCC60S 0 Capture Compare Status Modification Bits MCC61S 1 These bits are used to bits to set MCC6xS or to 625 2 clear MCC6xR the corresponding bits CC6xST by MCC63S 6 SW This feature allows the user to individually change the status of the output lines by SW e g when the corresponding compare timer is stopped This allows a bit manipulation of CC6xST bits by a single data write action The following functionality of a write access to bits concerning the same capture compare state bit is provided MCC6xR MCC6xS 00 Bit CC6xST is not changed 01 Bit CC6xST is set 10 Bit CC6xST is
20. 0 2 5 r Reserved 7 Returns 0 if read should be written with O TCON Timer and Counter Control Status Register 88 Reset Value 00 RMAP X PAGE X 7 6 5 4 3 2 1 0 TF1 TR1 TFO TRO IE1 IT1 IEO ITO rwh rw rwh rw rwh rw rwh rw Field Bits Type Description ITO 0 rw External Interrupt 0 Level Edge Trigger Control 0 Low level triggered external interrupt 0 is selected 1 Falling edge triggered external interrupt 0 is selected IT1 2 rw External Interrupt 1 Level Edge Trigger Control 0 Low level triggered external interrupt 1 is selected 1 Falling edge triggered external interrupt 1 is selected 9 5 3 Interrupt Flag Registers The interrupt flags for the different interrupt sources are located in several Special Function Registers In case of software and hardware access to a flag bit at the same User s Manual 9 23 V1 0 2010 02 Interrupt System V 2 3 3 Cinfineon Interrupt System time hardware will have higher priority The bit field PAGE of SCU_PAGE register must be programmed before accessing IRCONx and NMISR register IRCONO Interrupt Request Register 0 F2 Reset Value 00 RMAP 0 PAGE 0 7 6 5 4 3 2 1 0 0 EXINT6 5 4 2 0 r rwh rwh rwh rwh rwh Field Bits Type Description EXINTx 6 2 rwh Interrupt Flag for External Interrupt x x22 6 This bit is set by hardware an
21. AIN CH3 7 ADC_single_ended_measurement2 vsd In differential like ADC conversion with internal 1 2V voltage reference and ground reference taken from CHO CHO cannot be used for ADC measurement CHO is used as ground reference for ADC which may be connected externally to increase measurement accuracy See Figure 21 13 The digital features of CHO maybe reused for other channels with the alias function See Section 21 8 4 Please note that a minimum time of 50usec is needed between conversions when this mode is used 2 ADC kernel va_altref va_altgnd Um V42vGND result AD AIN CHO handling converter AIN CH1 request conversion AIN CH3 7 control 3 control Interrupt generation ADC_differential_like_1 2Vref_chOgnd_measurement2 vsd Figure 21 13 Differential like measurement with internal 1 2V voltage reference and CHO gnd In single ended ADC conversion with 1 2V voltage reference and Vssp CHO can be used for ADC measurement See Figure 21 14 User s Manual 21 46 V1 0 2010 02 ADC V2 1 Cinfineon Analog to Digital Converter VauzvREF ADC kernel va altref va altgnd V sp result lt gt AD AIN CHO handling converter AIN CH1 request conversion AIN CH3 7 control control m Interrupt generation ADC single ended
22. LTS fn COLA pad turn O pad turn 1 pad turn 2 M pad _turn_3 o COL2 gt COL1 8 coro p i LED function LED first column active SW With time slice interrupt write next column line pattem and compare value to shadow registers SW Analyze amp actions on pad oscilat ion count HW On compare match LED column is de activated HW On counter 8LSB overflow shadow transfer line pattern amp compare value for next column LED function LED last column active SW With time slice interrupt write touch sense compare value to shadow register HW On compare match LED column is de activated HW On counter8LSB overflow shadow transfer line pattern amp compare value for touchsense function Touch sense function Pad oscilator active on pad with active turn SW With time slice interrupt write LED 1 column line pattern and compare value to shadow registers HW LED columns atinactive level HW On compare match enable pad oscillation Oscillations are counted HW On counter 8LSB overflow shadow transfer line amp compare value for f column Disable pad oscilation amp update bit PADT for next pad tum Figure 19 1 Time Multiplexed LEDTSCU Functions on Pin Example User s Manual 19 7 LEDTSCU V 1 2 1 V1 0 2010 02 Cinfineon
23. 17 2 1 Clocking 17 2 1 Interrupt Events and Assignment 17 3 1 StatUS COUE cs acceded de pa a dade s 17 4 1 Baud Rate Generation 17 5 1 Clock Synchronization 17 6 1 Bus Arbitration 2 2 susc eeu esan EE e Ro E 17 6 1 User s Manual 1 7 V1 0 2010 02 Cinfineon 17 7 17 8 17 8 1 17 8 2 17 8 3 17 8 4 17 9 17 9 1 17 9 2 17 9 3 17 9 4 17 9 5 17 9 6 18 18 1 18 2 18 2 1 18 2 2 18 2 3 18 3 18 3 1 18 3 2 18 3 3 18 3 4 18 3 5 18 3 6 18 4 18 5 18 5 1 18 5 2 18 5 3 18 5 4 19 19 1 19 2 19 2 1 19 2 2 19 2 3 19 2 4 19 2 5 19 3 19 4 Software Res t secui e eh Rx eth 17 7 1 Operating Modes 2 2 2 2 17 7 1 Master 17 7 1 Master Receive 2222 0 liess ee nr RR ERES 17 10 1 Slave Transmit s clesie Ee Rb eee 17 12 1 Slave a s ace nea nae 17 13 1 Registers 17 15 1 Slave Address Registers 17 16 1 Data 17 17 1 Control 5
24. Port Pin Input Output Select Connected Signal s From to Module P0 6 Input GPI PO_DATAIN P6 ALT1 RXD_1 UART ALT2 SDA 0 ALT3 MTSR_1 SSC ALT4 MRST 0 SSC ALT5 EXINTO 1 SCU ALT6 T2bX 0 Timer 2 TSING LEDTSCU OTHERS SPD_0 SPD Output GPO PO DATAOUT P6 ALT1 LINEG TSING LEDTSCU ALT2 MRST 0 SSC ALT3 TXD 0 UART ALTA SDA 0 ALT5 COL2_1 LEDTSCU ALT6 COLA_1 LEDTSCU OTHERS SPD_0 SPD User s Manual 11 16 V1 0 2010 02 Cinfineon XC82x Parallel Ports 11 2 2 Registers Description PO DATAIN Port 0 Data In Register 86 Reset Value XX RMAP 0 PAGE 0 7 6 5 4 3 2 1 0 0 P6 P5 P4 P3 P2 P1 PO r rh rh rh rh rh rh rh Field Bits Description Pn n rh Port 0 Pin n Data Value n20 6 0 Port 0 pin n data value 0 1 Port 0 pin n data value 1 0 7 r Reserved Returns 0 if read should be written with O PO DATAOUT Port 0 Data Output Register 80 Reset Value 7F RMAP 0 PAGE 0 7 6 5 4 3 2 1 0 0 6 5 P4 P3 P2 1 r rw rw rw rw rw rw rw Field Bits Type Description Pn n rw Port 0 Pin n Data Value 0 6 0 Port 0 pin n data value 0 1 Port 0 pin n data value 1 0 7 r Reserved Returns 0 if read should be written with 0 User s Manual 11 17 V1 0 2010 02 Cinfineon Parallel Ports PO OD Port 0 Open Dra
25. Reserved Returns 0 if read should be written with 0 1 A minimum of 50usec is needed between conversions when using this mode User s Manual ADC V2 1 21 50 V1 0 2010 02 Cinfineon Analog to Digital Converter An input class defines the length of the sample phase and the resolution of the conversion The default settings select the minimum sample phase length of 2 fapc cycles The Input Class Registers select the sample time and the resolution for each input class ADC_INPCRO Input Class 0 Register Reset Value 00 RMAP 0 PAGE 0 7 6 5 4 3 2 1 0 0 STC r rw Field Bits Type Description STC 3 0 rw Sample Time Control This bit field defines the additional length of the sample time given in terms of f4pc clock cycles A sample time of 2 analog clock cycles is extended by the programmed value 0 7 4 r Reserved Returns 0 if read should be written with 0 User s Manual 21 51 V1 0 2010 02 ADC V2 1 Cinfineon Analog to Digital Converter 21 8 3 Limit Checking The limit checking mechanism automatically compares each conversion result to two boundary values boundary A and boundary B For each channel the user can select these boundaries from a set of 2 programmable values ADC_LCBRO to ADC_LCBR1 A channel event is then generated depending on the two comparisons The conditions are selected via bitfield LCC in the respective cha
26. 19 1 1 QvervigW irc elk oboe bee er cR 19 1 1 System Information 19 2 1 Pinnilg ES RR EE Du pee EP d P ed 19 2 1 Clocking 19 3 1 Interrupt Events and Assignment 19 4 1 IP Interconnection 19 4 1 Debug Suspend Control 19 5 1 Time Multiplexed LED amp Touch Sense Functions On Pin 19 5 1 LED DAVIN xg eoe eser Raed aoe ale MERE 19 8 1 User s Manual 1 8 V1 0 2010 02 Cinfineon 19 4 1 19 5 19 5 1 19 6 19 7 19 8 19 9 19 10 19 11 19 11 1 19 11 2 20 20 1 20 1 1 20 1 2 20 1 3 20 2 20 2 1 20 2 2 20 2 3 20 2 4 20 2 5 20 3 20 3 1 20 3 2 20 3 2 1 20 3 2 2 20 3 2 3 20 3 3 20 3 3 1 20 3 3 2 20 3 3 3 20 3 4 20 3 4 1 20 3 4 2 20 3 4 3 20 3 5 20 3 6 20 3 7 20 3 8 20 3 8 1 20 3 8 2 LED Pin Assignment and Current Capability 19 10 1 Touchpad 5 2 4 19 11 1 Finger SENSING 19 13 1 Time Multiplexed LED and Touch Sense Function on Pin 19 14 1 Function Enabling and Control Hints 19 15 1 LEDTSCU Timing Calculations 19 16 1 LEDTSCU Pin
27. 1 2 1 2 1 2 1 2 1 2 i P1 P2 P1 P2 1 2 A l It Interrupt 4 cycle current instruction 1 I request MUL or DIV 1 sampled active l 1 k 1 Interrupt bla 1 1 Interrupt request LCALL 1 instruction at request polled interrupt vector sampled last cycle of curent 1 instruction gt Interrupt response time 6 x machine cycle Figure 9 10 Interrupt Response Time for Condition 2 P1 P2 P1 P2 P1 P2 i P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 LLL ULL IU 4 l t l l l l l Interrupt 2 cycle currgnt instruction o request l sampled active 1 4 cycle next instruction Interrupt l interrupt request MUL or DIV request polled sampled RETI or write l iccess to interrupt k rl pl registers interrupt request Interrupt polled LCALL request last cycle of interrupt vector sampled curent 1 instruction 1 Interrupt response time 8 x machine cycle Figure 9 11 Interrupt Response Time for Condition Thus in a single interrupt system the
28. User s Manual 12 8 V1 0 2010 02 MDU V2 9 Cinfineon XC82x Multiplication Division Unit Table 12 5 MDx Registers cont d Register Roles of Registers in Operations 16 bit 32 16 bit 16 16 bit Normalize and Multiplication Division Division Shift MD3 MD4 M orL D orL D orL Control MD5 M orH D orH D orH Table 12 6 MRx Registers Register Roles of Registers in Operations 16 bit 32 16 bit 16 16 bit Normalize and Multiplication Division Division Shift MRO PrL QuoL QuoL ResultL MR1 Pr Quo QuoH Result MR2 Pr Quo PrH QuoH ResultH MR4 M orL RemL RemL Control MR5 M orH RemH RemH Abbreviations D end Dividend 1 operand of division Divisor 214 operand of division Multiplicand 1 operand of multiplication Mor Multiplicator 274 operand of multiplication Pr Product result of multiplication Rem Remainder Quo Quotient result of division L means that this byte is the least significant of the 16 bit or 32 bit operand H means that this byte is the most significant of the 16 bit or 32 bit operand The MDx registers are built with shadow registers which are latched with data from the actual registers at the start of a calculation This frees up the MDx registers to be written with the next set of operands while the current calculatio
29. OA eel ode Pade de ces 10 2 1 Clocking 10 2 1 Interrupt Events and 10 2 1 Debug Suspend Control 10 3 1 JTAG ID Lieu we den me We peel 10 4 1 Functional Overview of the Debug System 10 5 1 Recognizing Debug events 10 5 1 Activating the Monitor Program 10 6 1 Debug Suspend Control 10 7 1 Running the Monitor 10 7 1 Returning to the User Program 10 7 1 Single Step Execution 10 7 1 Breakpoint Generation Module 10 8 1 Generating Hardware Breakpoints 10 8 1 Breakpoints on Instruction Address 10 8 1 Breakpoints on Internal RAM Address 10 9 1 Tracing changes in Break Address 10 10 1 Processing External 10 10 1 Processing Software Breakpoints 10 10 1 Reactions on Breakpoints without Monitor Entry 10 11 1 Triggering NMI request 10 11 1 NMI Request and Control by OCDS 10
30. 17 18 1 Status Register 17 20 1 Baud Rate Control 17 21 1 Software Reset Register 17 21 1 High Speed Synchronous Serial Interface 18 1 1 OVEINIEW ed be hd be eh oner 18 1 1 System Information 18 2 1 PINNING 18 2 1 Clocking 18 6 1 Interrupt Events and 18 7 1 General Operation 18 8 1 Operating Mode Selection 18 8 1 Full Duplex Operation 18 10 1 Half Duplex Operation 18 13 1 Continuous Transfers 18 14 1 Baud Rate Generation 18 15 1 Error Detection Mechanisms 18 16 1 18 19 1 Register Description 18 20 1 Configuration Register 18 21 1 Baud Rate Timer Reload 18 26 1 Transmitter Buffer Register 18 26 1 Receiver Buffer Register 18 27 1 LED and Touch Sense Controller
31. Interrupt Request Reg CC6x 1IC Interrupt Request Reg CC6x_2IC Interrupt Request Reg Interrupt Set Register ISS Interrupt Status Register IS Interrupt Reset Register ISR Interrupt Enable Register IEN Node Pointer Register INP Q c 9 5 gt o a a Figure 20 42 Interrupt Sources and Events User s Manual CCU6 V4 0 20 111 V1 0 2010 02 Cinfineon Capture Compare Unit 6 CCU6 20 9 2 Interrupt Registers 20 9 2 1 Interrupt Status Register Register ISL H contains the individual interrupt request bits This register can only be read write actions have no impact on the contents of this register The SW can set or clear the bits individually by writing to the registers ISSL H to set the bits or to register ISRL H to clear the bits The interrupt generation is independent from the value of the bits in register ISL H e g the interrupt will be generated if enabled even if the corresponding bit is already set The trigger for an interrupt generation is the detection of a set condition HW or SW for the corresponding bit in register ISL H In compare mode and hall mode the timer related interrupts are only generated while the timer is running T1xR 1 In capture mode the capture interrupts are also generated while the timer T12 is stopped Note Not all bits in register ISL H can generate an interrupt Other status bits have been added th
32. Mode T12 counts down after detecting a period match and counts up after detecting a one match 1 A concurrent set clear action on T12R from T12SSC T12RR or T12RS will have no effect The bit T12R will remain unchanged User s Manual CCU6 V4 0 20 58 V1 0 2010 02 Cinfineon Capture Compare Unit 6 CCU6 TCTROH Timer Control Register 0 High 7 Reset Value 00 RMAP 0 PAGE 1 7 6 5 4 3 2 1 0 0 STE13 T13R T13PRE T13CLK T rh rh rw rw Field Bits Type Description T13CLK 2 0 rw Timer T13 Input Clock Select Selects the input clock for timer T13 that is derived from the peripheral clock according to the equation fus fece 25 13 1 gt 000g fece 001g fr45 fece 2 010g fece 4 011 frig fece 8 100g fece 16 1015 fece 32 110g fece 64 111g fece 128 T13PRE 3 rw Timer T13 Prescaler Bit In order to support higher clock frequencies an additional prescaler factor of 1 256 can be enabled for the prescaler for T13 Os additional prescaler for T13 is disabled 1g additional prescaler for T13 is enabled T13R 4 rh Timer T13 Run Bit T13R starts and stops timer T13 It is set cleared by SW by setting bits TT3RR orT13RS orit is set cleared by HW according to the function defined by bit fields T138SC T13TEC and T13TED Og Timer T13 is stopped 13 Timer T13 is running U
33. 2 ALT 3 4 ALT 5 2 SCU ALT 6 OTHERS SPD_1 SPD Output GPO P1 DATAOUT PO ALT 1 COLO 0 LEDTSCU ALT2 COUT60 0 CCU6 ALT 3 TXD_1 UART OTHERS SPD_1 SPD 1 17 Input GPI P1 DATAIN P1 ALT 1 ALT 2 ALT 3 ALT 4 ALT 5 ALT 6 CC60_0 CCU6 Output GPO P1 DATAOUT P1 ALT 1 COL1 0 LEDTSCU ALT2 CC60 0 CCUG ALT 3 TXD 2 UART User s Manual 11 23 V1 0 2010 02 Cinfineon XC82x Parallel Ports Table 11 7 Port 1 Input Output Functions cont d Port Pin Input Output Select Connected Signal s From to Module P1 2 Input P1_DATAIN P2 ALT 1 ALT 2 ALT 3 ALT 4 ALT 5 EXINT4 SCU ALT 6 Output GPO P1_DATAOUT P2 ALT 1 COL2_0 LEDTSCU ALT 2 COUT61_0 CCU6 ALT 3 COUT63_0 CCU6 P1 3 Input P1_DATAIN P3 ALT 1 ALT 2 ALT 3 ALT 4 ALT 5 ALT 6 CC61_0 CCU6 Output GPO P1_DATAOUT P3 ALT1 COL3_0 LEDTSCU ALT2 CC61_0 CCU6 ALT3 EXF2_1 Timer 2 User s Manual 11 24 V1 0 2010 02 Cinfineon XC82x Parallel Ports Table 11 7 Port 1 Input Output Functions cont d Port Pin Input Output Select Connected Signal s From to Module P1 4 Input P1_DATAIN P4 ALT 1 ALT 2 ALT 3 ALT 4 ALT 5 EXINT5 SCU ALT 6 Output GPO P1_DATAOUT P4 ALT1 COL4 LEDTSCU ALT2 COUT62_0 CCU6 ALT3 COUT63_1 CCU6 P1 5 Input GPI P1_DATAIN P5 A
34. Sector 9 128 byte Sector 8 128 byte Sector 7 128 byte Sector 6 128 byte Sector 5 256 byte Sector 4 256 byte Sector 3 512 byte Sector 2 512 byte Sector 1 1 Kbyte Sector 0 1 Kbyte 1x Flash Bank Figure 4 2 Flash Bank Sectorization Sector Partitioning in each 4 Kbyte Flash bank Two 1 Kbyte sectors Two 512 byte sectors Two 256 byte sectors Four 128 byte sectors The internal structure of each Flash bank represents a sector architecture for flexible erase capability The minimum erase width is always a complete sector and sectors can be erased separately or in parallel Contrary to standard EEPROMs erased Flash memory cells contain Os The Flash bank is divided into more physical sectors for extended erasing and reprogramming capability even numbers for each sector size are provided to allow greater flexibility and the ability to adapt to a wide range of application requirements For example the user s program can implement a buffer mechanism for each sector Double copies of each data set can be stored in separate sectors of similar size to ensure that a backup copy ofthe data set is available in the event the actual data set is corrupted or erased Alternatively the user can implement an algorithm for EEPROM emulation which uses the Flash bank like a circular stack memory the latest data updates are always programmed on top of the actual region
35. User s Manual 1 16 V1 0 2010 02 System Architecture V1 0 Cinfineon 800 2 800 This chapter describes the XC800 Core 2 1 Overview The XC800 Core is a complete high performance CPU core that is functionally upward compatible to the 8051 While the standard 8051 core is designed around a 12 clock machine cycle the XC800 Core uses a two clock period machine cycle The instruction set consists of 45 one byte 41 two byte and 14 three byte instructions Each instruction takes 1 2 or 4 machine cycles to execute In case of access to slower memory the access time may be extended by wait cycles one wait cycle lasts one machine cycle which is equivalent to two wait states The XC800 Core support a range of debugging features including basic stop start single step execution breakpoint support and read write access to the data memory program memory and special function registers Features The key features of the XC800 Core implemented are listed below Two clocks per machine cycle On chip XRAM in external data space 256 bytes IRAM in internal data space Up to 64 kByte of code space not fully assigned to implemented memory Support for synchronous or asynchronous program and data memory Wait state support for slow memory e 15 source 4 level interrupt controller 2 data pointers Power saving modes Dedicated debug mode Two 16 bit timers Timer 0 and Tim
36. Wait for start mode the current conversion is completed the conversion of the arbitration winner is started after that This mode provides maximum throughput but can produce a jitter for the higher priority conversion Example in Figure 21 11 Conversion A is requested t1 and started t2 Conversion B is then requested t3 but started only after completion of conversion A t4 Cancel inject repeat mode the current conversion is aborted the conversion of the arbitration winner is started after the abortion 1 3 fanc cycles The aborted conversion request is restored in the corresponding request source and takes part again in the next arbitration round This mode provides minimum jitter for the higher priority conversions but reduces the overall throughput Example in Figure 21 11 Conversion is requested t6 and started t7 Conversion B is then requested t8 and started t9 while conversion A is aborted but requested again When conversion B is complete t10 conversion A is restarted Exception If both requests target the same result register with wait for read mode active see Section 21 10 the current conversion cannot be aborted User s Manual 21 43 V1 0 2010 02 ADC V2 1 Cinfineon Analog to Digital Converter request channel B request channel conversions t2 t4 t5 19 t10 t11 X waitfor start mode canceLinjectrepeat mode conv starts
37. 11 26 1 2 byt E ERES 11 30 1 Functions e Re ae dE 11 31 1 Registers 5 11 33 1 Multiplication Division 12 1 1 OvervieW siec net he eee eee 12 1 1 System Information 12 2 1 Clocking 12 2 1 Interrupt Events and 12 3 1 Functional Description 12 3 1 DIVISION ep 12 4 1 NortiallZe zm eke RERO RE RU EIE RR RI d 12 5 1 pare P ETE 12 5 1 Multiplication with Single Left Shift 12 5 1 Division with Single Right Shift 12 6 1 BUSY bad ossi etna i E colos 12 6 1 Error 2 2 242 2 5 lt 12 6 1 Interrupt 12 7 1 Registers lt 12 8 1 Operand and Result Registers 12 10 1 Control Register 2 12 12 1 Status Register 12 14 1 Timer 0 and 1 13 1 1 ou P 13 1 1 User s Manual 1 5 V1 0 2010 02
38. 20 3 8 3 Capture Compare Registers In compare mode the registers CC6xRL H x 0 2 are the actual compare registers for T12 The values stored in CC6xR are compared all three channels in parallel to the counter value of T12 In capture mode the current value of the T12 counter register is captured by registers CC6xRL H if the corresponding capture event is detected CC6xRL x 0 2 Capture Compare Register for Channel CC6x Low FA x 2 Reset Value 00 RMAP 0 PAGE 1 7 6 5 4 3 2 1 0 CCVL rh Field Bits Type Description CCVL 7 0 rh Capture Compare Value In compare mode the bit fields CCV contain the values that are compared to the T12 counter value In capture mode the captured value of T12 can be read from these registers CC6xRH x 0 2 Capture Compare Register for Channel CC6x High FB x 2 Reset Value 00 RMAP 0 PAGE 1 7 6 5 4 3 2 1 0 CCVH th Field Bits Type Description CCVH 7 0 rh Capture Compare Value In compare mode the bit fields CCV contain the values that are compared to the T12 counter value In capture mode the captured value of T12 can be read from these registers User s Manual 20 46 V1 0 2010 02 CCU6 V4 0 Cinfineon Capture Compare Unit 6 CCU6 20 3 8 4 Capture Compare Shadow Registers The registers CC6xRL H can only be read by SW the modification of the value is done by a shadow registe
39. Bit Field P2 Pi PO P2 Data In Register Type rh rh rh rh RMAP 0 PAGE 1 80H P0_PUDSEL Reset 6 Bit Field 0 P6 P5 P4 P2 P1 PO Pull Up Pull Down Select Register Type r rw rw rw rw rw rw TW B6y PUDEN Reset C44 Bit Field P7 P6 4 P2 P1 PO Pull Up Pull Down Enable Register Type TW rw rw rw TW rw rw rw 90y P1_PUDSEL Reset 3Fj Bit Field 0 5 4 P3 P2 P1 PO P1 Pull Up Pull Down Select Register Type r rw rw rw rw rw TW 91H P1_PUDEN Reset 004 Bit Field 0 4 P2 1 P1 Pull Up Pull Down Enable Register Type r rw rw rw rw rw rw 93H P2_PUDSEL Reset OF Bit Field P3 P2 P1 PO P2 Pull Up Pull Down Select Register Type Ww dad IW dud 4 P2_PUDEN Reset 004 Bit Field P2 1 PO P2 Pull Up Pull Down Enable Register Type PN nw Ww IRMAP 0 PAGE 2 User s Manual 3 18 V1 0 2010 02 Memory Organization V 0 1 Infineon XC82x Memory Organization Table 3 4 Port Register Overview cont d Addr Register Name Bit 7 6 5 4 3 2 1 0 PO_ALTSELO Reset 004 Bit Field P6 P5 P4 P2 P1 PO Alternate Select 0 Register Type r rw rw rw rw rw rw TW 5 PO_ALTSEL2 Reset 004 Bit Field 0 6 5 4 0 PO Alternate Select 2 Register Type rw rw rw r g6u PO ALTSEL1 Reset 004 Bit Field 0 P6 5 4 2 P1 PO Alternate Select 1
40. Not Used Option Checksum Block 1 byte 4 bytes 1 byte Mode Data Description User s Manual 6 14 V1 0 2010 02 Cinfineon Boot Loader Option This byte will determine the 4 bytes data to be sent to the host Only option 00 02 are valid options 00 Chip Identification Number MSB byte 1 LSB byte 4 01 USER ID MSB byte 1 LSB byte 4 In Mode A the header block is the only transfer block to be sent by the host The microcontroller will return an acknowledgement followed by 4 bytes of data to the host if the header block is received successfully If an invalid option is received the microcontroller will return 4 bytes of 00 USER is the user identification number and the order of the 4 bytes of USER_ID_INFO are as followed USER_ID_4 USER_ID_3 USER_ID_2 and USER_ID_1 User s Manual 6 15 V1 0 2010 02 Cinfineon System Control Unit 7 System Control Unit The System Control Unit SCU of the XC82x handles all system control tasks besides the debug related tasks which are controlled by the OCDS Cerberus All functions described in this chapter are tightly coupled thus they are conveniently handled by one unit the SCU The SCU contains the following functional sub blocks Embedded Voltage Regulator EVR see Section 7 1 on Page 7 1 Reset Control see Section 7 2 on Page 7 6 e Clock System and Control see Section 7 3 Page 7 11 Po
41. 1 AF024 01 AFOO 2 1 2 1 0 382 ge i ack 55 874 87 9 0E82 0 81 0E80 AEOFH cet oes 82 81 AE804 0662 0 61 0E60 2 AE624 AE614 AEG0 9 oF d 5 Bed 2 Be i ENDE d 0E02 0 01 0E00 METER eee eee ee 2 AEO1 AE004 ODERI estis ODE2 ODEtn ODEO inert egt ADE2u 1 ADEOn S or BOUE Si i 15 Dian o OD1F 0002 0001 0D004 gt 1 AD024 01 00 OCFF 2 1 2 1 HE 5 8 B 5 lt 58 E Te 0 1 0 02 0 01 0 00 E 1 AC024 1 2 OBE1 8 2 ABE 14 o8e o8 8 2 258 c 58 0A224 0 21 0420 o 8 22 21 20 0 02 0401 0 00 AA024 1 00 09 2 09E 14 09 0 hr 2 9 1 2 ato ak a 854 8 0822 0821 0820 9 2 I A822
42. Delays induced by cancelled conversions that must be repeated The configured arbitration cycle time The frequency of external trigger signals if enabled Example1 When N 10bit STC 0000g fapc 48Mhz CTC 01 48Mhz 1 3 12Mhz 83 33ns 21 1 trample 2 0 x 83 33ns 166 67ns 21 2 User s Manual 21 61 V1 0 2010 02 ADC V2 1 Cinfineon XC82x Analog to Digital Converter Table 21 6 Sample Time Sample Time ADC_INPCRO STC bin 0000 0001 17 x fanol 11116 1 x 1 1 3 3 10 0 1 104us User s Manual ADC V2 1 21 62 21 3 V1 0 2010 02 Cinfineon Analog to Digital Converter 21 8 7 Channel Events and Interrupts A channel event interrupt can be generated based on a channel event according to the structure shown in Figure 21 20 If a channel event is detected it sets the corresponding indication flag in register ADC_CHINFR The indication flags can be cleared by SW by writing a 1 to the corresponding bit position in register CHINCR channel to SRO event channel event flags CHINFR ADC 0 ADC chev1 ADC chev2 channel number Note ADC 0 2 are internally connected signals to other modules and is not triggered by CHINSR set channel interrupt register ADC channel events routing Figure 21 20 Channel Event Interrupt Generation User s Ma
43. For flexibility users can choose common compare parameter for all PADTx or choose different compare parameters for individual PADTx This is also provided to give better sensitivity for respective pads If CMP OPTION at address R5 is programmed as OxFF it means that different compare value is selected Then the different compare parameters are read at IRAM address R5 1 onwards for individual pads If CMP_OPTION is not programmed as OxFF then common compare parameter for all pads is selected and this value is programmed at address R5 itself In preparing compare value for Touch sense quantization effect is taken into consideration in the function The respective compare value will be XRL with 2 4 8 16 etc and finally updating the final value to sfr LTS COMPARE Quantization effect gives better sensitivity and is transparent to users as all are achieved by the function Table 23 9 Specifications of Setting LDLINE amp Common COMPARE TS only Subroutine SET LDLINE CMP Address DFCF Input R7 of current Register Bank Start IRAM address of LDLINE parameter R5 of current Register Bank Start IRAM address of CMP_OPTION amp COMPARE parameters LDLINE parameters programmed into IRAM address R7 LDLINE parameter for COLA TS COMPARE parameters programmed into IRAM address R5 R5 Common COMPARE parameter for all PADTx Output Sfr LTS LDLINE is programmed Sfr LTS COMPARE is programmed Stack size requir
44. Programmable shift direction Least Significant Bit LSB or Most Significant Bit MSB shift first Programmable clock polarity idle low or high state for the shift clock Programmable clock data phase data shift with leading or trailing edge of the shift clock Variable baud rate Compatible with Serial Peripheral Interface SPI Interrupt generation On a transmitter empty condition On areceiver full condition error condition receive phase baud rate transmit error Figure 18 1 shows the block diagram of the SSC User s Manual 18 1 V1 0 2010 02 SSC V1 4 Cinfineon XC82x High Speed Synchronous Serial Interface PCLK Baudrate Generator Clock Control Shift Clock SSC Control Block Register CON Status Control gt id Pin 16 Bit Shift Control Register Transmit Buffer Receive Buffer Register TB Register RB w Internal Bus SS CLK MS CLK Receive Int Request Transmit Int Request gt Error Int Request gt TXD Master RXD Slave TXD Slave RXD Master Figure 18 1 SSC Block Diagram 18 2 This section provides system information relevant to the SSC 18 2 1 User s Manual SSC V1 4 Pinning The SSC pin assignment for XC82x is shown in Table 18 1 System Info
45. wrong hall event is detected 1g Thebit DLE is automatically set when a wrong hall event is detected ENSTR 7 rw Enable Multi Channel Mode Shadow Transfer Interrupt No interrupt will be generated if the set condition for bit STR in register IS occurs 1 An interrupt will be generated if the set condition for bit STR in register IS occurs The service request output that will be activated is selected by bit field INPCHE User s Manual CCU6 V4 0 20 122 V1 0 2010 02 Cinfineon XC82x Capture Compare Unit 6 CCU6 Field Bits Type Description reserved returns 0 if read should be written with 0 User s Manual CCU6 V4 0 20 123 V1 0 2010 02 Cinfineon Capture Compare Unit 6 CCU6 20 9 2 5 Interrupt Node Pointer Register Register INPL H contains the interrupt node pointers allowing a flexible interrupt handling These bit fields define which service request output will be activated if the corresponding interrupt event occurs and the interrupt generation for this event is enabled INPL Interrupt Node Pointer Register Low 9E Reset Value 40 RMAP 0 PAGE 2 7 6 5 4 3 2 1 0 INPCHE INPCC62 INPCC61 INPCC60 rw rw rw rw Field Bits Type Description INPCC60 1 0 rw Interrupt Node Pointer for Channel CC6x INPCC61 3 2 Interrupts INPCC62 5 4 This bit field defines the service request output activated due to a set condition for bit C
46. All Timer 2 register names described in the following sections are referenced in other chapters of this document with the module name prefix T2_ e g T2_T2CON The Timer 2 SFRs are located in the standard non mapped SFR area Table 14 5 lists these addresses Table 14 5 Register Map Address Register 2 C1 T2MOD C2 RC2L C3 RC2H C4 T2L C5 T2H C6 T2CON1 User s Manual 14 11 V1 0 2010 02 Timer 2 V 1 2 Cinfineon XBox Timer 2 14 8 1 Mode Register The T2MOD is used to configure Timer 2 for various modes of operation T2 T2MOD Timer 2 Mode Register C1 Reset Value 00 RMAP 0 PAGE X 7 6 5 4 3 2 1 0 T2REGS T2RHEN EDGESEL T2PRE DCEN rw rw rw rw rw rw Field Bit Type Description DCEN 0 rw Up Down Counter Enable Og Up Down Counter function is disabled 1 3 Up Down Counter function is enabled and controlled by pin T2EX Up 1 Down 0 T2PRE 3 1 rw Timer 2 Prescaler Bit Selects the input clock for Timer 2 which is derived from the peripheral clock 000 fr fpcik 0015 fr feci 2 010g fr 4 011g fr foci 8 1006 fr fpa 16 101 fr 32 110g fog 64 1115 fr fpa 128 PREN 4 rw Prescaler Enable Og disabled and the 2 or 12 divider takes effect 1g Prescaler is enabled see T2PRE bit and the 2 or 12 divider is bypassed E
47. Hall Compare Logic CM_WHE CCU6_MCA05540 Figure 20 38 Hall Mode Flags User s Manual 20 95 V1 0 2010 02 CCU6 V4 0 Cinfineon Capture Compare Unit 6 CCU6 20 7 4 Mode for Brushless DC Motor Control The CCU6 provides a mode for the Timer T12 Block especially targeted for convenient control of block commutation patterns for Brushless DC Motors This mode is selected by setting all TT2MSELL T12MSELH MSEL amp 6x bit fields of the three T12 Channels to 10005 In this mode illustrated in Figure 20 39 channel CC60 is placed in capture mode to measure the time elapsed between the last two correct Hall events channel CC61 in compare mode to provide a programmable phase delay between the Hall event and the application of a new PWM output pattern and channel CC62 also in compare mode as first time out criterion A second time out criterion can be built by the T12 period match event f Counter Register Clear Hall Compare 2 T12 Logic CHE gt CM 61 Capture Register Compare Register Compare Register CC61R CC62R Compare Shadow Compare Shadow Register CC61SR Register CC62SR 06 05538 Figure 20 39 12 Block Hall Sensor Mode The signal CM_CHE from the Hall compare logic is used to transfer the new compare values from the shadow registers CC6xSR into the actual compare registers CC6xR performs the sh
48. Ny T2 baud Combining Equation 6 1 and Equation 6 2 together with N 8 fr Jec k 4 T2PRE 010 PRE 1 6 3 IPCLK g e 16 PREx BRVALUE 2 User s Manual 6 3 V1 0 2010 02 Cinfineon Boot Loader Simplifying Equation 6 3 we get 6 4 BRVALUE a I 3 32 The capturing of the timing for 8 bits makes the formula easy for realization in assembly language The division with 32 can be simply achieved by a 5 bit right shift operation In previous Acropolis family the shift operation causes a loss in the decimal digits thus reducing the baud rate accuracy Therefore in XC82x the concept SFRs BGL and BGH is implemented in such a way that the actual shift division is not necessary by firmware as it will be executed by hardware In this way we keep the decimal digits after division and giving a better accuracy of the baud rate detection Thus after capturing the 8 bits timing in R2CH and R2CL the values are programmed directly to BGH and BGL respectively After setting BG and PRE the Baud Rate Generator will then be enabled and the subsequent frames will follow this baud rate After receiving UART INIT ID to determine single or dual pins for UART BSL the UART BSL routine sends an Acknowledge byte 554 to the host If this byte is received correctly it will be guaranteed that both serial interfaces are working with the same baud rate 6 2 Phase II Serial Communication Protoco
49. On chip Peripheral Memo OSC logic Figure 7 1 82 Power Supply System Vopp 2 5V 5 5V Vssp EVR Features Input voltage Vppp 3 0 V to 5 5 V full operation condition Input voltage down to 2 5 V in active mode or power down mode with a reduction in the load conditions reduced voltage condition Output Voltage Vppc 2 5 V 7 5 Low power voltage regulator provided in power down mode Vypc and prewarning detection brownout detection The EVR consists of a main voltage regulator and a low power voltage regulator In active mode both voltage regulators are enabled In power down mode the main voltage regulator is switched off while the low power voltage regulator continues to function and provide power supply to the system with low power consumption The EVR works within an input voltage range of 3 0 V to 5 5V under full operation condition and within an input range down to 2 5 V under reduced voltage condition XC82x will only work in power down mode or in active mode with limited load available in the reduced voltage condition The EVR has the Vppc and detectors There are two threshold voltage levels for Vppc detection prewarning 2 4 V and brownout 2 3 V When is below a nominal voltage of 2 4 V the NMI flag NMISR FNMIVDDC is set and an NMI request to the User s Manual 7 2 V1 0 2010 02 Cinf
50. RO of current Register Bank Value2 Bits 31 24 Output R7 of current Register Bank Result of Value1 x Value2 Bits 7 0 R6 of current Register Bank Result of Value1 x Value2 Bits 15 8 R5 of current Register Bank Result of Value1 x Value2 Bits 23 16 R4 of current Register Bank Result of Value1 x Value2 Bits 31 24 Stack size required 2 Resource used destroyed A MDO MD1 MD4 MD5 MR1 MR2 MDUCON MDUSTAT User s Manual ROM Library V0 5 23 40 V1 0 2010 02 T6 XC82x Infineon ROM Library 23 3 3 Integer Division 23 19 Outputs are Result and Remainder of Value P Value2 Table 23 17 Specifications of 16 16 bit Division Subroutine Subroutine C UIDIV XC Address DFC6 Input R7 of current Register Bank Value1 Low Byte R6 of current Register Bank Value1 High Byte R5 of current Register Bank Value2 Low Byte R4 of current Register Bank Value2 High Byte Output R7 of current Register Bank Result of Value1 Value2 Low Byte R6 of current Register Bank Result of Value1 Value2 High Byte R5 of current Register Bank Remainder of Value1 Value2 Low Byte R4 of current Register Bank Remainder of Value1 Value2 High Byte Stack size required 2 Resource A MDO MD1 MD4 MD5 MRO MR1 MR4 MR5 MDUCON used destroyed MDUSTAT User s Manual 23 41 V1 0 2010 02 ROM Library V0 5
51. Setting this bit clears the T12R bit T12Ris not influenced 1g T12Ris cleared T12 stops counting T12RS 1 w Timer T12 Run Set Setting this bit sets the T12R bit T12Ris not influenced 1g T12R is set T12 starts counting T12RES 2 w Timer T12 Reset No effect on T12 1g T12 counter register is cleared to zero The switching of the output signals is according to the switching rules Setting of T12RES has no impact on bit T12R DTRES 3 w Dead Time Counter Reset 0s No effect on the dead time counters 1g three dead time counter channels are cleared to zero T12STR 6 Timer T12 Shadow Transfer Request 0s No action 1g STE12 is set enabling the shadow transfer T12STD 7 w Timer T12 Shadow Transfer Disable 0s No action 1g STE12 is cleared without triggering the shadow transfer User s Manual 20 64 V1 0 2010 02 CCU6 V4 0 Cinfineon Capture Compare Unit 6 CCU6 Field Bits Type Description 0 5 4 reserved returns 0 if read should be written with 0 Note A simultaneous write of a 1 to bits that set and clear the same bit will trigger no action The corresponding bit will remain unchanged TCTR4H Timer Control Register 4 High 90 Reset Value 00 RMAP 0 PAGE 0 7 6 5 4 3 2 1 0 T13STD T13STR 0 T13RES T13RS T13RR Ww r i Ww Field Bits Type Description T13RR
52. Before this interrupt is serviced the DATA register must be loaded with either a 7 bit slave address or the first part of a 10 bit slave address with the LSB cleared to 0 i e with an added Write bit to specify transmit mode The IFLG bit should now be cleared to 0 to prompt the transfer to continue After the 7 bit slave address or the first part of a 10 bit address plus the Write bit have been transmitted IFLG will be set again A number of status codes are possible in the STAT register User s Manual 17 7 V1 0 2010 02 V1 1 Cinfineon XC82x Inter IC Bus Table 17 6 Status Code after Address is Transmitted in Master Transmit Mode Code 1 State CPU Response Next Action 184 Addr W For 7 bit address ACK received Write byte to DATA clear Transmit data byte IFLG receives ACK Or Set STA clear IFLG Transmit repeated START Or Set STP clear IFLG Transmit STOP Or Set STA and STP clear Transmit STOP then IFLG START For 10 bit address Write extended address Transmit extended data byte to DATA clear IFLG byte 204 Addr W Same as for code 184 Same as for code 184 ACK not received 384 Arbitration lost Clear IFLG Return to idle state Or set STA clear IFLG Transmit START when bus is free 68 Arbitration lost Clear IFLG 0 Receive data byte transmit SLA W received not ACK ACK transmitted Or clear IFLG 1 Receive data byte transmit ACK 784 Arbitratio
53. Cinfineon Multiplication Division Unit single left shift on this product gives a Q31 value and the product in Q15 format can be obtained by taking only the upper 16 bit of the 32 bit value 12 3 5 Division with Single Right Shift The division with single right shift is similar to a signed 32 bit by 16 bit division except that the MDU performs a single right shift first before the division This operation can be used to facilitate signed 16 bit by 16 bit fixed point number divisions in Q15 format Normally to divide a Q15 fixed number by another and obtain a Q15 quotient the dividend has to be scaled up first by a factor of 215 before performing a 32 bit by 16 bit division User software can write the 16 bit dividend to the upper half word of the 32 bit operand data register and select the division with single right shift to have the same effect 12 3 6 Busy Flag A busy flag is provided to indicate the MDU is still performing a calculation The flag MDUSTAT BSY is set at the start of a calculation and cleared after the calculation is completed at the end of phase two It is also cleared when the error flag is set If a second operation needs to be executed the status of the busy flag will be polled first and only when it is not set can the start bit be written and the second operation begin Any unauthorized write to the start bit while the busy flag is still set will be ignored 12 3 7 Error Detection The error flag MDUS
54. RMAP 0 PAGE X 7 6 5 4 3 2 1 0 EN MS 0 AREN BEN PEN REN TEN rw rw r rw rw rw rw rw Field Bit Type Description TEN 0 rw Transmit Error Enable Og Ignore transmit errors 1g Check transmit errors REN 1 nw Receive Error Enable Og Ignore receive errors 1g Check receive errors PEN 2 nw Phase Error Enable Og Ignore phase errors 1g Check phase errors BEN 3 rw Baud Rate Error Enable Og Ignore baud rate errors 1g Check baud rate errors AREN 4 rw Automatic Reset Enable Og additional action upon a baud rate error 1g SSC is automatically reset upon a baud rate error MS 6 rw Master Select Og Slave Mode Operate on shift clock received via SCLK 1g Master Mode Generate shift clock and output it via SCLK User s Manual 18 22 V1 0 2010 02 SSC V1 4 Cinfineon XC82x High Speed Synchronous Serial Interface Field Bit Type Description EN 7 rw Enable Bit 0 Transmission and reception disabled Access to control bits 0 5 r Reserved Returns 0 if read should be written with 0 User s Manual SSC V1 4 18 23 V1 0 2010 02 Cinfineon CON EN 1 Operating Mode XC82x High Speed Synchronous Serial Interface SSC_CONL Control Register Low Operating Mode Reset Value 00 RMAP 0 PAGE X 7 6 5 4 3 2 1 0 0 BC r rh Field Bit Type Descr
55. This avoids an unintentional additional dead time if a State Bit CC6xST changes too early A disabled dead time counter is always considered as passive and does not delay any edge of CC6xST Based on the State Bits CC6xST the Dead Time Generation Block outputs a direct signal CC6xST and an inverted signal CC6xST for each compare channel each masked with the effect of the related Dead Time Counters waveforms illustrated in Figure 20 17 User s Manual 20 33 V1 0 2010 02 CCU6 V4 0 Cinfineon Capture Compare Unit 6 CCU6 T12 Counter Value Compare Value active State Bit 1 CC6xST passive active active Dead Time CC6xST with Dead passive Time CC6xST with Dead Time active CCU6_MCT05521 Figure 20 17 Dead Time Generation Waveforms 20 3 4 2 State Selection To support a wide range of power switches and drivers the state selection offers the flexibility to define when a an output can be active and can be modulated especially useful for complementary or multi phase PWM signals The state selection is based on the signals CC6xST and CC6xST delivered by the dead time generator see Figure 20 15 Both signals are never active at the same time but can be passive at the same time This happens during the dead time of each compare channel after a change of the corresponding State Bit CC6xST The user can select independently for each output signal CC6xO
56. WDTTO WDTRST ENWDT_P If the WDT is not serviced before the timer overflows a system malfunction is assumed and normal mode is terminated A WDT NMI request FNMIWDT is then asserted and prewarning is entered The prewarning lasts for 30 count During the prewarning period refreshing of the WDT is ignored and the WDT cannot be disabled A reset WDTRST of the XC82x is imminent and can no longer be avoided The occurrence of a WDT reset is indicated by the bit WDTRST in RSTCON register If refresh happens at the same time an overflow occurs WDT will not go into prewarning period The WDT must be serviced periodically so that its count value will not overflow Servicing the WDT clears the low byte and reloads the high byte with the preset value in bit field WDTREL Servicing the WDT also clears the bit WDTRS The WDT has a programmable window boundary which disallows any refresh during the WDT s count up A refresh during this window boundary constitutes an invalid access to the WDT and causes the WDT to activate WDTRST although no NMI request User s Manual 8 4 V1 0 2010 02 WDT V1 0 Cinfineon Watchdog Timer is generated in this instance The window boundary is from 0000 to the value obtained from the concatenation of WDTWINB and 00 This feature can be enabled by WINBEN After being serviced the Watchdog Timer continues counting up from the value lt WDTREL gt 2 The time period for an o
57. repeated interrupt requests 18 16 V1 0 2010 02 Cinfineon neers High Speed Synchronous Serial Interface Bits in Register CON Transmit Error Interrupt EIR Figure 18 6 SSC Error Interrupt Control A Receive Error Master or Slave Mode is detected when a new data frame is completely received but the previous data was not read out of the receive buffer register RB This condition sets the error flag CON RE and the error interrupt request line EIR when enabled via CON REN The old data in the receive buffer RB will be overwritten with the new value and is irretrievably lost A Phase Error Master or Slave Mode is detected when the incoming data at pin MRST Master Mode or MTSR Slave Mode sampled with the same frequency as the module clock changes between one cycle before and two cycles after the latching edge of the shift clock signal SCLK This condition sets the error flag CON PE and when enabled via CON PEN the error interrupt request line EIR Note When receiving and transmitting data in parallel phase errors occur if the baud rate is configured to fiw ox 2 A Baud Rate Error Slave Mode is detected when the incoming clock signal deviates from the programmed baud rate by more than 100 i e it is either more than double or less than half the expected baud rate This condition sets the error flag CON BE and when enabled via CON BEN the error interrupt request line EIR Using this error det
58. 0 5 3 Reserved Returns 0 if read should be written with 0 18 3 General Operation The SSC supports full duplex and half duplex synchronous communication up to 12 MBaud 24 MHz module clock The serial clock signal can be generated by the SSC itself Master Mode or can be received from an external master Slave Mode Data width shift direction clock polarity and phase are programmable This allows communication with SPl compatible devices Transmission and reception of data is double buffered A 16 bit baud rate generator provides the SSC with a separate serial clock signal The SSC can be configured in a very flexible way so it can be used with other synchronous serial interfaces can serve for master slave or multimaster interconnections or can operate compatible with the popular SPI interface Thus the SSC can be used to communicate with shift registers I O expansion peripherals e g EEPROMs etc or other controllers networking The SSC supports half duplex and full duplex communication Data is transmitted or received on lines TXD and RXD normally connected with pins MTSR Master Transmit Slave Receive and MRST Master Receive Slave Transmit The clock signal is output via line MS_CLK Master Serial Shift Clock or input via line SS_CLK Slave Serial Shift Clock Both lines are normally connected to pin SCLK 18 3 1 Operating Mode Selection The operating mode of the serial channel SSC is contr
59. 00 RMAP 1 PAGE X 7 6 5 4 3 2 1 0 MMWR2 rw User s Manual 10 19 V1 0 2010 02 OCDS V 2 7 1 T6 XC82x Infineon Debug System Field Bits Type Description MMWR2 7 0 rw Work location 2 for the Monitor Program User s Manual 10 20 V1 0 2010 02 OCDS V 2 7 1 Cinfineon Parallel Ports 11 Parallel Ports XC822 has 13 port pins and XC824 has 17 port pins Both of them are organized into three parallel ports Port 0 PO to Port 2 P2 Each pin has a pair of internal pull up and pull down devices that can be individually enabled or disabled Ports PO and P1 are bidirectional and can be used as general purpose input output GPIO or to perform alternate input output functions for the on chip peripherals When configured as an output the open drain mode can be selected Port P2 is an input only port providing general purpose input functions alternate input functions for the on chip peripherals and also analog inputs for the Analog to Digital Converter ADC Standard Bidirectional Port Features e Configurable pin direction Configurable pull up pull down devices Configurable open drain mode Transfer data through digital inputs and outputs general purpose 1 0 Alternate input output for on chip peripherals Input and output drivers are disabled during power save mode Input Port Features e Configurable input driver e Configurable pull up pull down devices Receive data th
60. 00 Analog to digital conversion is done with reference to Vssp See Figure 21 12 01 Analog to digital conversion is done with internal 1 2V and CHO as the ground reference See Figure 21 13 10 Analog to digital conversion is dones with internal 1 2V and Vssp See Figure 21 14 11 Reserved do not use this combination User s Manual 21 48 V1 0 2010 02 ADC V2 1 Cinfineon Analog to Digital Converter Field Bits Type Description LCC 6 4 rw Limit Check Control This bit field defines the behavior of the limit checking mechanism See Section 21 8 3 000 Never 001 Result outside area 010 Result outside area II 011 Result outside area III 100 Always boundaries disregarded 101 Result within area 110 Result within area Il 111 Result within area 111 BFEN 7 rw Boundary Flags Enable This bit is the gating control for the boundary flags ADC lt 2 0 gt signal Og X Boundary flag signal is disabled for the corresponding channel 1g Boundary flag signal is enabled for the corresponding channel 1 A minimum of 50usec is needed between conversions when using this mode CHCTRx x 3 5 Channel x Control Register CA x 1 Reset Value 00 ADC CHCTRx x 6 7 Channel x Control Register CC x 1 Reset Value 00 RMAP 0 PAGE 1 7 6 5 4 3 2 1 0 0 LCC REFSEL RESRSEL r mo rw rw Note ADC_CHCTR 4
61. 100 8MHz gt 6 bit 0018 6004 011 4004 1015 2004 1115 0004 CLK PS Sbitcompare Ye On compare On 8 bit 0 No dock match overflow Ta gt amp gt Enable pad oscillator oc 111 e Oj 63 63 110 amp gt COLA Di B amp COLO wo BP coL1 d az gt E COL2 m gt amp gt gt COL3 or gt cos m gt s gt gt COL5 8 pth coLe C5 C2 CO If touchsense function is enabled this time slice is reserved for pad osc enabling and Shadow transfer 8 bit compare LED column control is not available 7 0 value amp LED line pattern For touch sense function pin COLA may be configured to enable external pull up not shown here Time slice Interrupt Time frame gt Interrupt Figure 19 2 LED Function Control Circuit also provides pad oscillator enable In Section 19 8 the time slice duration and formulations for LEDTSCU related timings are provided User s Manual 19 9 V1 0 2010 02 LEDTSCU V 1 2 1 Cinfineon LED Touch Sense Controller 19 4 1 LED Pin Assignment and Current Capability One LED column pin is enabled at a time within each configured time slice duration to control up to eight LEDs The assignment of COL x to pins is configurable to suit various use cases Refer to product data sheet for the current capability of assigned pin s For example a column
62. 1B Pad ERROR Pad Line7 7 rw Pad Line 7 of PadError OB Pad OK 1B PadERROR 23 2 2 2 Implementation Details of Function The important formulas used in the function are how the Total TSCTRL H obtained how Average is calculated how LowTrip Trip point is derived and finally how a comparison is made for a touch or no touch of a pad SFR LTS TSCTR value is used for this calculation Total number of samples accumulated is defined in AccumulatorCounter input Total value of all samples is TOTAL TSCTRL H n is user defined input for FINDTOUCHEDPAD function AccumulatorCounter 23 7 AccumulatorCounter TOTAL TSCTRL H x gt LTS_TSCTR i i l where is the user defined input AccumulatorCounter number of samples required supporting value 1 to 255 The Average is calculated as follows 23 8 AVERAGEL H x AVERAGEL H x 1 TOTAL_TSCTRL H x AVERAGEL HGc1 n 2 where n is the user defined input Divisor n supporting value 1 to 8 User s Manual 23 30 V1 0 2010 02 ROM Library V0 5 Cinfineon ROM Library The LowTrip Trip point value is calculated by subtracting user defined input subtraction m from the Average 23 9 LOWTRIPL H x AVERAGEL H x SUBTRACTION m With the LowTrip value calculated from the Average value the comparison is done with the current accumulated LTS_TSCTR values in TOTAL TSCTRL H 2 where is the user defined input Divisor n A padtouch is identified w
63. 21 30 V1 0 2010 02 Cinfineon XC82x Analog to Digital Converter The Queue Status Register indicates the current status of the queued source The filling level and the empty information refer to the queue intermediate stages if available and to the queue register 0 An aborted conversion stored in the backup stage is not indicated by these bits therefore see QBURx V ADC_QSRO Queue Status Register RMAP 0 PAGE 6 7 Reset Value 20 EMPTY EV 0 FILL ERES rh A 2 rh Field Bits Type Description FILL 1 0 Filling Level This bit field indicates how many entries are valid in the sequential sourced queue It is incremented each time a new entry is written to QINRO decremented each time a requested conversion has been finished A new entry is ignored if the filling level has reached its maximum value If EMPTY bit 1 there are no valid entries in the queue 00 If EMPTY bit 0 there is 1 valid entry the queue 01g IfEMPTY bit O there are 2 valid entries in the queue 10 If EMPTY bit there is valid entry in the queue 11g If EMPTY bit 0 there 4 valid entries in the queue EV rh Event Detected This bit indicates that an event has been detected while V 1 Once set this bit is reset automatically when the requested conversion is started Og An event has not been detected 13 An event has
64. 6 2 2 5 Mode3 Execute customer code in FLASH Mode 3 is used to execute a customer program in the Flash of the uC at 0000 The Header Block for this working mode has the following structure The Header Block Data Area 00 034 Header Mode 3 Not Used n Block 1 byte Mode Data Description Not used The five bytes are not used and will be ignored in Mode 3 In working Mode 3 the Header Block is the only transfer block to be sent by the host no further serial communication is necessary The uC will exit the UART BSL Mode and jump to the Flash address at 0000 6 2 2 6 4 Erase customer code in FLASH sector s Mode 4 is used to erase different sector in the Flash Bank 0 The Header Block for Flash Sector erase Data Area 00 04 Header Mode 4 Flash_BO_ Flash BO Checksum Block SectorL SectorH 1 byte 1 byte 1 byte 3 bytes Mode Data Description Flash BO SectorL In this byte the sectors 0 to 7 of Flash Bank 0 are represented by bits 0 to 7 When the bit contains a 1 the corresponding sector is selected E g byte of 0x12 selects sectors 1 and 4 of Flash Bank 0 for erase Flash BO SectorH In this byte the sectors 8 to 9 of Flash Bank 0 are represented by bits to 1 When the bit contains a 1 the corresponding sector is selected E g byte of 0x01 selects sectors 8 of Flash Bank 0 for erase Note Unwanted unselected bits s
65. 6 PISELOH ISPOSO 11 CCPOSO ADC BFO CCU6 input i ADC boundary event 1 CCU6 PISELOH ISPOS1 11 CCPOS1 ADC BF1 CCU6 input i ADC boundary event 2 CCU6 PISELOH ISPOS2 11 CCPOS2 ADC BF2 User s Manual 20 16 V1 0 2010 02 CCUG V4 0 Cinfineon Capture Compare Unit 6 CCU6 20 2 5 Module Suspend Control When the On Chip Debug Support OCDS is in Monitor Mode MMCR2 MMODE 1 and the Debug Suspend signal is active MMCR2 DSUSP 1 Timer T12 and Timer T13 of CCU6 module in XC82x can be suspended based on the settings of their corresponding module suspend bits in register MODSUSP The definition of this register is described in Chapter 10 2 4 When suspended only the timer stops counting as the counter input clock is gated off The module is still clocked so that module registers are accessible 20 3 Operating Timer T12 The timer T12 block is the main unit to generate the 3 phase PWM signals A 16 bit counter is connected to 3 channel registers via comparators that generate a signal when the counter contents match one of the channel register contents A variety of control functions facilitate the adaptation of the T12 structure to different application needs Besides the 3 phase PWM generation the T12 block offers options for individual compare and capture functions as well as dead time control and hysteresis like compare mode This section provides information about e 712 overview see Section 2
66. 821 A820 2222 0802 0801 0800 ABER A802 A8014 A8004 7 07E24 07 1 07 0 nouum 2 ATE1 2o 8 ERTA Ba ag 8 secure 04424 04414 04404 2 4 eem A424 441 M40 Tm 0422 04214 0420 coste A 4224 A4214 A420 DL 0402 0401 0400 A402 A4014 A4004 03E2 03E 1 03 0 2 1 one o5 58 B 0042 00414 00404 2 4 ADSER EEUU TUTTO A042 A041 A040 82 c EU 00224 00214 00201 ADJEH A0224 021 A0204 ERR GE 0002 00014 0000 DIEN A0024 001 A000 WL WL Address Address Figure 4 3 User s Manual Flash Memory V 0 1 4 5 Flash Bank 0 Wordline Addresses V1 0 2010 02 Cinfineon nears Flash Memory A WL address can be calculated as follow 0000 A000 20 x n with O x n lt 127 for Flash Bank 0 4 1 Only one out of all the wordlines in the Flash banks can be programmed each time The maximum minimum program width of each WL is 32 bytes Before programming can be done the user must first write the number of bytes of data that is equivalent to the program width into the IRAM using MOV instructions Then the Boot loader BSL routine see Section 4 6 or Flash program subroutine see Section 4 7 1 will transfer
67. 9 Bit UART Fixed Baud Rate 16 6 1 Mode 9 Bit UART Variable Baud Rate 16 6 1 Multiprocessor Communication 16 8 1 Baud Rate Generation 16 9 1 Fixed Clock eost pia pd x D ron 16 9 1 UART Baud rate 16 9 1 Bin ee eae MIA ae dM LE 16 12 1 LIN Support 16 13 1 LINCPrOIOCOL 45 tie so ba eee 16 13 1 LIN Header Transmission 16 15 1 Automatic Synchronization to the Host 16 15 1 Initialization of Break Synch Field Detection Logic 16 16 1 Baud Rate Range Selection 16 16 1 LIN Baud Rate Detection 16 18 1 Registers 16 19 1 UART 16 20 1 Baud rate Generator Control and Status Registers 16 22 1 Baud rate Generator Timer Reload Registers 16 24 1 Inter IG Bus 2 2 eae rr emere eere 17 1 1 onu PTT 17 1 1 System Information 17 1 1 ex 5 4 ya d 17 1 1 Output Pin Configuration
68. DPSEL1 DPSELO r rw r rw rw rw Field Bits Description DPSELO 0 rw Data Pointer Select DPSEL1 1 These bits are used to select the current data DPSEL2 2 pointer 000 selected 001 DPTR1 selected others Reserved TRAP_EN 4 rw TRAP Enable Og Select MOVC DPTR A 1g Select software TRAP instruction 0 7 5 r Reserved Returns 0 if read should be written with 0 User s Manual 2 5 V1 0 2010 02 XC800 Core V 1 0 2 Cinfineon XC800 Core 2 3 7 Power Control Register PCON 87 The PCON register provides control for entering idle mode baud rate control for UART in mode 2 as well as two general purpose flags The XC800 Core has two power saving modes idle mode and power down mode The idle mode can be entered via the PCON register In idle mode the clock to the core is disabled while the timers serial port and interrupt controller continue to run In power down mode 1 the clock to the entire core is stopped PCON Power Control Register 87 Reset Value 00 RMAP X PAGE X 7 6 5 4 3 2 1 0 SMOD 0 GF1 GFO 0 IDLE rw r rw rw r rw Field Bits Type Description IDLE 0 rw Idle Mode Enable 0s not enter idle mode 1g Enter idle mode GFO rw General Purpose Flag Bit 0 GF1 rw General Purpose Flag Bit 1 SMOD rw Double Baud Rate Enable This bit controls the baud rate generation for UART in mode 2 Os not double
69. Digital Converter 21 6 1 Channel Scan Request Source Handling Each analog input channel can be included in or excluded from the scan sequence see bits in register ADC_CRCR1 The programmed register value remains unchanged by an ongoing scan sequence The scan sequence starts with the highest enabled channel number and continues towards lower channel numbers Upon a load event the request pattern is transferred to the pending bits see register ADC_CRCR1 The pending conversion requests indicate which input channels are to be converted in an ongoing scan sequence Each conversion start that was triggered by the scan request source automatically clears the corresponding pending bit If the last conversion triggered by the scan source is finished and all pending bits are cleared the current scan sequence is considered finished and a request source event is generated A conversion request is only issued to the request source arbiter if at least one pending bit is set If the arbiter aborts a conversion triggered by the scan request source due to higher priority requests the corresponding pending bit is automatically set This ensures that an aborted conversion is not lost but takes part in the next arbitration round The trigger unit generates load events from the selected external outside the ADC trigger signals For example a timer unit can issue a request signal to synchronize conversions to PWM events Load events start a scan seq
70. Each pin can also be programmed to activate an internal weak pull up or pull down device Register P2 PUDSEL selects whether a pull up or the pull down device is activated while register P2 PUDEN enables or disables the pull device The analog input Analogin bypasses the digital circuitry and Schmitt Trigger device for direct feed through to the ADC input channel Internal Bus PUDSEL Pull up Pull down Select Register PUDEN Pull up Pull down Enable Register Pull up Pull down Control Logic Pull Device Input Data In Driver Pin Data Register Senmi rigger Pad AltDataln Analogln Figure 11 2 General Structure of Input Port User s Manual 11 4 V1 0 2010 02 Cinfineon Parallel Ports 11 1 1 General Register Description This section describes the SFR registers available on the XC82x module 11 1 1 1 Register Map The Port SFRs are located in the standard memory area RMAP 0 and are organized into 4 pages The PORT PAGE register is located at address 8E It contains the page value and page control information The addresses of the Port SFRs are listed in Table 11 1 Table 11 1 SFR Address List for Pages 0 3 Address Page 0 Page 1 Page 2 Page 3 80 PO DATAOUT PUDSEL PO ALTSELO PO OD 86 PO DATAIN PO PUDEN PO ALTSEL1 85 PO ALTSEL2 90 P1 DATAOUT PUDSEL P1 ALTSELO
71. Figure 21 11 Conversion Start Modes The conversion start mode can be individually programmed for each request source by bits in register ADC_PRAR and is applied to all channels requested by the source In this example channel A is issued by a request source with a lower priority than the request source requesting the conversion of channel B User s Manual 21 44 V1 0 2010 02 ADC V2 1 Cinfineon Analog to Digital Converter 21 8 Analog Input Channel Configuration For each analog input channel a number of parameters can be configured that control the conversion of this channel After a channel has won the arbitration its parameters are applied to the converter The channel control registers CHCTRx on Page 21 48 define the following parameters Conversion parameters The input class defines sample time and data width All channels is using the same input class Reference selection Three types of internal reference are available for selection ranging from internal 1 2V and Vddp 3 3 5V The reference selection determines the conversion conversion mode of the ADC i e single ended or differential mode See Section 21 8 1 Please note that low reference voltages lead to small granularity As a consequence the resulting TUE increases due to noise effects Resulttarget The conversion result can be stored in one of 4 result registers Channel event handling Channel events can be restricted to results inside or outside a def
72. For Output PO ALTSELO P1 0 PO ALTSEL1 P1 1 PO 0 MRST 3 SSC Master Receive Input For Input MODPISEL MIS 11 The SSC uses three lines to communicate with the external world Pin SCK serves as the clock line while pins MRST Master Receive Slave Transmit and MTSR Master Transmit Slave Receive serve as the serial data input output lines Each of the input lines can be selected from one of several different sources The selection is done in the MODPISEL register Similarly each of the output lines can be also selected from several different sources However the selection is done at the respective Ports ALTSELx registers The bit field PAGE of SCU_PAGE register must be programmed before accessing the MODPISEL register MODPISEL Peripheral Input Select Register Reset Value 00 RMAP 0 PAGE 3 7 6 5 4 3 2 1 0 0 CIS 515 0 MIS r rw rw r rw Field Bits Description MIS 1 0 rw Master Mode Receive Input Select 00 SSC Master Receiver Input 0 is selected 01 SSC Master Receiver Input 1 is selected 10 SSC Master Receiver Input 2 is selected 11 SSC Master Receiver Input is selected User s Manual 18 4 V1 0 2010 02 SSC V1 4 Cinfineon XC82x High Speed Synchronous Serial Interface Field Bits Type Description SIS 5 3 Slave Mode Receive Input Select 000 SSC Slave Receiver Input 0 is selected 001 SSC Slave
73. Kp Proportional gain e X Error Reference value Actual value k Time or instantaneous time Table 23 2 Specifications of P Controller Routine Subroutine P controller G16 P controller 5256 Routine Address OxD655 P controller 616 OxD65B P controller G256 C Prototype int P controller G16 int Ref val int Actual val char idata Kp int P controller G256 int Ref val int Actual val char idata Kp Input R7 R6 MSB Ref val 16 bit Reference value R5 R4 MSB Acutal val 16 bit Actual value idata pointer to Kp H Output R7 R6 MSB 16 bit Y k value Execution Cycle P controller G16 138 cclks P controller G256 112 cclks Resource PSW A MDU used destroyed Ro R4 R5 of current Register Bank User s Manual 23 3 V1 0 2010 02 ROM Library V0 5 Cinfineon ROM Library Code Example global variables data int Speed data int Speed ref data int Speed kp data int P Speed program Speed 16288 Speed ref 4000 Speed kp 4096 P Speed P controller 616 5 ref Speed char idata amp Speed kp P speed 0 7 40 23 1 2 Controller Routine The PI controller routine is the implementation of a proportional integral control algorithm defined as 23 2 Y k Gx Kp x X k Y k 1 Ki x X k where Y k Pl controller output Y k 1 Previous PI controller output G Gain factor of16 or 256 Kp Proportional gain Ki Integral gain
74. PadFlag bit is O for future analysis PadResult Status If bitis 1 function will be exited for that Touch sense Pad Turn No analysis will be done Users should clear this status when PadFlag bit is O for future analysis Output IRAM address Ox2D Output Parameters at IRAM address PadError Status Bit O indicates the error status of PADTO Bit 1 indicates the error status of PADT1 Bit 7 indicates the error status of PADT7 This byte bit s indicate s that the pad s is are touched for too long This byte bit s is are not cleared by function and must be cleared by user Access this status only when PadFlag status is 0 User s Manual ROM Library V0 5 23 24 V1 0 2010 02 Cinfineon ROM Library Table 23 13 Specifications of Find Touched Pad Subroutine cont d IRAM address 0x2E PadResult Status Bit O indicates the result status of PADTO Bit 1 indicates the result status of PADT1 Bit 7 indicates the result flag of PADT7 This byte bit s indicate s that the pad s is are touched within valid range This byte bit s is are not cleared by function and must be cleared by user Access this status only when PadFlag status is O IRAM address Ox2F PadFlag Status Bit 0 indicates the flag status of PADTO Bit 1 indicates the flag status of PADT1 Bit 7 indicates the flag status of PADT7 When this byte bit s is are 1 it indicate s that the pad s is are identify as being touched and a
75. R5 1 etc QR5 Common COMPARE parameter for PADTx 5 1 COMPARE parameter for COLO 5 7 COMPARE parameter for COL6 Output Sfr LTS LDLINE is programmed Sfr LTS COMPARE is programmed Stack size required 2 Resource A RO R1 R2 R4 used destroyed User s Manual 23 17 V1 0 2010 02 ROM Library V0 5 Cinfineon XC82x ROM Library 1 Depending how many LED s is are enabled y no of LED s enabled Maximum LEDs enabled are 7 when TS is enabled 2 This common Compare parameter cannot be OxFF value Table 23 12 Specifications of Setting LDLINE amp Different COMPARE LEDTS Subroutine SET_LDLINE_CMP Address DFCF Input R7 of current Register Bank Start IRAM address of LDLINE parameter R5 of current Register Bank Start IRAM address of CMP_OPTION amp COMPARE parameters LDLINE parameters programmed into IRAM address R7 R7 LDLINE parameter for COLA for Touch sense R7 1 LDLINE parameter for COLO R7 y LDLINE parameter for COL y 1 COMPARE parameters programmed into IRAM R5 R5 1 etc R5 OPTION OxFF value R5 1 COMPARE parameter for COLO R5 2 COMPARE parameter for COL 1 R5 y COMPARE parameter for COL y 1 R5 y 1 COMPARE parameter for PADTO R5 y 2 COMPARE parameter for PADT 1 R5 y z COMPARE parameter for PADT z 1 Output Sfr LTS_LDLINE is programmed Sfr LTS_COMPARE
76. RMAP 0 PAGE 4 7 6 5 4 3 2 1 0 WDT rh Field Bits Description WDT 7 0 rh Watchdog Timer Current Value WDTWINB Watchdog Window Boundary Count F4 Reset Value 00 RMAP 0 PAGE 4 7 6 5 4 3 2 1 0 WDTWINB rw User s Manual 8 9 V1 0 2010 02 WDT V1 0 Cinfineon Watchdog Timer Field Bits Description WDTWINB 7 0 rw Watchdog Window Boundary Count Value This value is programmable Within this Window Boundary range from 0000 to WDTWINB 00 the WDT cannot do a Refresh else it will cause a WDTRST to be asserted WDTWINB is matched to WDTH User s Manual 8 10 V1 0 2010 02 WDT V1 0 Cinfineon Interrupt System 9 Interrupt System The XC800 Core supports one non maskable interrupt NMI and 14 maskable interrupt requests In addition to the standard interrupt functions supported by the core e g configurable interrupt priority and interrupt masking the XC82x interrupt system provides extended interrupt support capabilities such as the mapping of each interrupt vector to several interrupt sources to increase the number of interrupt sources supported and additional status registers for detecting and identifying the interrupt Source 9 1 Interrupt Sources The XC82x supports 14 interrupt vectors with four priority levels Ten of these interrupt vectors are assigned to the on chip peripherals Timer 0 Timer 1 UART and SSC are each assigned one dedicate
77. T12RSEL 1 0 rw Timer T12 External Run Selection Bit field T12RSEL defines the event of signal T12HR that can set the run bit T12R by HW 00 The external setting of T12R is disabled 01 Bit T12R is set if a rising edge of signal T12HR is detected 10 Bit T12R is setifa falling edge of signal T12HR is detected 11g Bit T12R is set if an edge of signal T12HR is detected T13RSEL 3 2 rw Timer T13 External Run Selection Bit field T13RSEL defines the event of signal T13HR that can set the run bit T13R by HW 00 external setting of T13R is disabled 01 Bit T13R is set if a rising edge of signal TT3HR is detected 10 Bit T13R is setifa falling edge of signal T13HR is detected 11 Bit T13R is set if an edge of signal T13HR is detected 0 7 4 r reserved returns 0 if read should be written with 0 User s Manual 20 63 V1 0 2010 02 CCU6 V4 0 Cinfineon Capture Compare Unit 6 CCU6 Register TCTR4L H provides software control independent set and clear conditions for the run bits T12R and T13R Furthermore the timers can be reset while running and bits STE12 and STE13 can be controlled by software Reading these bits always returns 0 TCTR4L Timer Control Register 4 Low 9 Reset Value 00 RMAP 0 PAGE 0 7 6 5 4 3 2 1 0 T12STD T12STR 0 DTRES T12RES T12RS T12RR w w T w w Ww w Field Bits Type Description T12RR 0 w Timer T12 Run Reset
78. User s Manual 9 26 V1 0 2010 02 Interrupt System V 2 3 3 Cinfineon XC82x Interrupt System TCON Timer and Counter Control Status Register 88 Reset Value 00 RMAP X PAGE X 7 6 5 4 3 2 1 0 TF1 TR1 TFO TRO IE1 IT1 IEO ITO rwh rw rwh rw rwh rw rwh rw Field Bits Type Description IEO 1 rwh External Interrupt 0 Flag Set by hardware when external interrupt 0 event is detected Cleared by hardware when the processor vectors to interrupt routine Can also be cleared by software IE1 3 rwh External Interrupt 1 Flag Set by hardware when external interrupt 1 event is detected Cleared by hardware when the processor vectors to interrupt routine Can also be cleared by software TFO 5 rwh Timer 0 Overflow Flag Set by hardware on Timer Counter 0 overflow Cleared by hardware when processor vectors to interrupt routine Can also be cleared by software TF1 7 rwh Timer 1 Overflow Flag Set by hardware on Timer Counter 1 overflow Cleared by hardware when processor vectors to interrupt routine Can also be cleared by software SCON UART Control Status Register 98 Reset Value 00 RMAP X PAGE X 7 6 5 4 3 2 1 0 SMO SM1 SM2 REN TB8 RB8 TI RI rw rw rw rw rw rwh rwh rwh User s Manual 9 27 V1 0 2010 02 Interrupt System V 2 3 3 Cinfineon XC82x Interrupt System
79. byte Valid logical address Mode 0 31 data 1 status WL 0 Mode 1 62 data 2 status WL 0 amp WL 1 Mode 2 93 data 3 status WL 0 WL 1 amp WL 2 Mode 3 124 data 4 status WL 0 WL 1 WL 2 amp WL 3 Table 23 20 Relationship between logical address and data bytes Logical address Data bytes WL 0 0 to 30 WL 1 31 to 61 WL 2 62 to 92 WL 3 93 to 124 Additionally the initialisation function can perform some basic error detection It can detect if an abort occur during a flash erase operation or emulated EEPROM is used for first time The initialisation function assumes that flash area used for EEPROM emulation is already erased when its used for the first time User application will access the emulated EEPROM using logical address via the read and write function Each read operation will read out 31 user data bytes and 1 status byte The 32 bytes of data will be stored in IRAM location provided by the calling function Similarly each write operation can only program 31 bytes and 1 status byte The data to be written should be stored in IRAM location provided by the calling function The status byte value would be automatically be updated by the write function Once the active sector is completely filled with data subsequent write operation will be in the next logical sector The next sector is set as the active sector and the previous active sector is reclaimed The reclaim operation involves programmi
80. field is set to 1 User s Manual 21 68 V1 0 2010 02 ADC V2 1 Cinfineon Analog to Digital Converter Field Bits Type Description VF 4 rh Valid Flag for Result Register x This bit indicates that the contents of the result register x are valid Os result register x does not contain valid data 1g result register x contains valid data 0 7 5 r Reserved Returns 0 if read should be written with 0 ADC_RESRxH x 0 2 Result Register x High View Std 8 bit or Acc 8 bit 1st conv CB x 2 Reset Value 00 ADC_RESR3H Result Register 3 High View Std 8 bit or Acc 8 bit 1st conv D3 Reset Value 00 RMAP 0 PAGE 2 7 6 5 4 3 2 1 0 RESULT 7 0 rh Field Bits Type Description RESULT 7 0 7 0 rh Conversion Result This bit field contains the conversion result or the result of the data reduction filter RESRxL x 0 2 Result Register x Low View Std 10 bit CA x 2 Reset Value 00 ADC RESR3L Result Register 3 Low View Std 10 bit D2 Reset Value 00 RMAP 0 PAGE 2 7 6 5 4 3 2 1 0 RESULT 2 0 VF DRC CHNR rh rh rh rh User s Manual 21 69 V1 0 2010 02 ADC V2 1 Cinfineon XC82x Analog to Digital Converter Field Bits Type Description CHNR 2 0 rh Channel Number This bit field contains the channel number of the latest register updat
81. is polled When this flag is set Timer 2 is stopped T2 Reload Capture register RC2H L is the time taken for 8 bits Then the auto baud routine calculates the actual baud rate sets the PRE and BG values and activates Baud Rate Generator Once all are done UART INIT ID value is read to determine the setting of the UART BSL Mode to be single or dual pins before ACK bytes 0x55 are sent out The baud rate detection is shown in Figure 6 1 User s Manual 6 2 V1 0 2010 02 Cinfineon Boot Loader 1st negative transition 2 automatically Last captured value of T2 EOFSYN bit is set set T2RHEN bit starts upon negative transition T2 is stopped SYN BREAK SYN CHAR 554 tarl m UART INIT ID Captured Value 8 bits 0x55 Dual pins UART OxAA Single pin UART Figure 6 1 Auto Baud Rate Detection 6 1 2 Calculation of BG and PRE values To set up auto baud rate detection the BG and PRE must be preload As there are two unknown values two formulas are therefore needed Firstly the correlation between the baud rate baud and the reload value BG depends on the internal peripheral frequency 6 1 f 16 PREx BRVALUE z Second the relation between the baud rate baud and the recording value of Timer 2 T2 depends on the T2 peripheral frequency the number of received bits 6 2
82. modes being selected User s Manual 21 67 V1 0 2010 02 ADC V2 1 Cinfineon Analog to Digital Converter The standard read views of the result registers consists of ADC RESRxL and ADC RESRXxH which delivers the conversion result and the related channel number The corresponding valid flag is cleared when register RESRx is read application view ADC RESRXxL x 0 2 Result Register x Low View Std 8 bit or Acc 8 bit 1st conv CA x 2 Reset Value 00 RESR3L Result Register 3 Low View Std 8 bit or Acc 8 bit 1st conv D2 Reset Value 00 RMAP 0 PAGE 2 7 6 5 4 3 2 1 0 0 VF DRC CHNR r rh rh rh Field Bits Type Description CHNR 2 0 rh Channel Number This bit field contains the channel number of the latest register update Note Bit 2 is only applicable for devices that have 8 ADC channels For channels not implemented these bits should be treated as Reserved bits of type f which returns 0 if read and should be written with DRC 3 rh Data Reduction Counter This bit field indicates how many conversion results have still to be accumulated to generate the final result for data reduction Og The final result is available in the result register The valid flag is automatically set when this bit field is set to 0 1g 1 more conversion result must be added to obtain the final result in the result register The valid flag is automatically reset when this bit
83. received It subsequently transmits the response character 55 acknowledge code if initialization is completed successfully Stack size required 11 Resource Port related SFRs A SBUF SCON MODPISEL1 used destroyed MODPISEL2 TCON TMOD THO TLO TRO BCON LINST T2 T2CON T2 RC2H L T2 T2MOD T2 T2H L IRAM address Ox7F 22 5 UART BSL Routine This routine allows application software to jump back to UART BSL Mode for various modes like programming erasing of XRAM FLASH etc Auto baud detection will be done in this routine User has to take care of the clock frequency used and program the BCON BGSEL SFR field bit according to their desired auto baud rate For details of the feature of UART_BSL Mode refer to Boot loader chapter Note Clock Frequency and BGSEL SFR field bit are not modified in this routine These field bits can be modified by user first before jumping back to this user routine for desired baud rate and clock frequency Note This routine will NOT return as it will be always be waiting for any uart bsl header therefore an LJMP to this routine should be used instead of LCALL Note SPD setting is disabled upon entering this user routine And once SPD is disabled it cannot be enabled again unless via reset User s Manual 22 6 V1 0 2010 02 BootROM User Routines V1 1 Cinfineon Boot ROM User Routines Table 22 8 Specifications of BR UART BSL subroutine Subroutine BR
84. 0 Cinfineon Capture Compare Unit 6 CCU6 1 These bits are set and cleared according to the T12 T13 switching rules CMPSTATH Compare State Register High FF Reset Value 00 RMAP 0 PAGE 3 7 6 5 4 3 2 1 0 1 CC62PS oo CC61PS PE CC60PS rwh rwh rwh rwh rwh rwh rwh rwh Field Bits Type Description CC60PS 0 rwh_s Passive State Select for Compare Outputs CC61PS 2 Bits CC6xPS COUT6xPS select the state of the CC62PS 4 corresponding compare channel that is considered COUT60PS 1 to be the passive state During the passive state the COUT61PS 3 passive level defined in register PSLR is driven by COUT62PS 5 the output pin Bits CC6xPS COUT6xPS x 0 1 2 COUT63PS 6 are related to T12 bit CC63PS is related to T13 1 Og corresponding compare signal is in passive state while CC6xST is 0 1g The corresponding compare signal is in passive state while CC6xST is 1 In capture mode these bits are not used T13IM 15 rwh 13 Inverted Modulation Bit 1 inverts the T13 signal for the modulation of the CC6x and COUT6x x 0 1 2 signals Og 113 output CC63 is equal to CC63ST 1g 113 output CC63 is equal to CC63ST 1 These bits have shadow bits and are updated in parallel to the capture compare registers of T12 T13 respectively A read action targets the actually used values whereas a write action targets the shadow bits
85. 0 00 2400 Baud 8 011 78 4E 4 04 09C4 0 00 1 The value of the 16 bit BG register is obtained by concantenating the 11 bit BRVALUE and 5 bit FD_NUM into a 16 bit value User s Manual UART V 1 6 16 11 V1 0 2010 02 Cinfineon UART 16 5 3 Timer 1 In modes 1 and 3 of UART Timer 1 can also be used for generating the variable baud rates In theory this timer could be used in any of its modes But in practice it should be set into auto reload mode Timer 1 mode 2 with its high byte set to the appropriate value for the required baud rate The baud rate is determined by the Timer 1 overflow rate and the value of SMOD bit in the PCON register as follows 16 3 SMOD 2 x CLK Mode 1 3 baud rate 32x2x 256 THI Alternatively for a given baud rate the value of Timer 1 high byte can be derived 16 4 SMOD 2 x fFPCLK 26 32 x 2 x Mode 1 3 baud rate Note Timer 1 can neither indicate an overflow nor generate an interrupt if Timer 0 is in mode 3 Timer 1 is halted while Timer 0 takes over the use of its control bits and overflow flag Hence the baud rate supplied to the UART is defined by Timer 0 and not Timer 1 User should avoid using Timer 0 and Timer 1 in mode 3 for baud rate generation User s Manual 16 12 V1 0 2010 02 UART V 1 6 Cinfineon UART 16 6 LIN Support in UART The UART module can be used to support the L
86. 0 and Timer 1 They can be accessed from both the standard non mapped and mapped SFR area Table 13 4 lists the addresses of these SFRs Table 13 4 Register Map Address Register 88 TCON 89 TMOD TLO 8B TL1 8C THO 8D TH1 A84 IENO 13 5 1 Timer 0 and Timer 1 Registers The low bytes TLO TL1 and high bytes THO TH1 of both Timer 0 and Timer 1 can be combined to a one timer configuration depending on the mode used Register TCON controls the operations of Timer 0 and Timer 1 The operating modes of both timers are selected using register TMOD Register IENO contains bits that enable interrupt operations in Timer 0 and Timer 1 TLx x 2 0 1 Timer x Low Byte 8A x Reset Value 00 RMAP X PAGE X 7 6 5 4 3 2 1 0 VAL rwh User s Manual 13 9 V1 0 2010 02 Timer 0 and 1 V1 0 Cinfineon XC82x Timer 0 and Timer 1 Field Bits Type Description VAL 7 0 rwh_ Timer 0 1 Low Register 00 TLx holds the 5 bit prescaler value 01 TLx holds the lower 8 bit part of the 16 bit timer value 10 TLx holds the 8 bit timer value 11 TLO holds the 8 bit timer value TL1 is not used THx x 2 0 1 Timer x High Byte 8C x Reset Value 00 RMAP X PAGE X 6 5 4 3 2 1 0 VAL rwh Field Bits Type Description VAL 7 0 rwh Timer 0 1 High Register 00 holds the 8
87. 00 Page 20 49 T12 Low T12DTCH Dead Time Control Register for Timer A5 00 Page 20 49 T12 High CC60RL Capture Compare Register Channel FA 00 Page 20 46 CC60 Low CC60RH Capture Compare Register Channel FB 00 Page 20 46 CC60 High CC61RL Capture Compare Register Channel FC 00 Page 20 46 CC61 Low CC61RH Capture Compare Register Channel FD 00 Page 20 46 CC61 High CC62RL Capture Compare Register Channel FE 00 20 46 CC62 Low CC62RH Capture Compare Register Channel FF 00 Page 20 46 CC62 High CC60SRL Capture Compare Shadow Register FA 00 Page 20 47 Channel CC60 Low CC60SRH Capture Compare Shadow Register FB 00 Page 20 47 Channel CC60 High User s Manual 20 5 V1 0 2010 02 CCUG V4 0 Cinfineon XC82x Capture Compare Unit 6 CCU6 Table 20 1 CCU6 Module Register Summary cont d Short Name Description Offset Reset See Value Page CC61SRL_ Capture Compare Shadow Register FC 00 Page 20 47 Channel CC61 Low CC61SRH Shadow Register FD 00 20 47 Channel CC61 High CC62SRL Capture Compare Shadow Register FE 00 20 47 Channel CC62 Low CC62SRH Shadow Register FF 00 20 47 Channel 62 High Capture Compare Control Registers CMPSTATL Compare State Register Low FE 00 20 51 CMPSTATH Compare State Regi
88. 1 IP interconnection 14 4 1 Module Suspend Control 14 4 1 Basic Timer Operations 14 5 1 Auto Reload 22 22 14 5 1 Up Down Count Disabled 14 5 1 Up Down Count Enabled 14 6 1 Capture Mode e poi aa ots x os xa d B 14 8 1 Count x enar a dee UE 14 9 1 External Interrupt Function 14 10 1 Registers 14 11 1 Mode Register 14 12 1 Control 2 2 2 2 2 2 22 14 13 1 Timer 2 Reload Capture Register 14 14 1 Timer 2 Count Register 14 15 1 Real Time 15 1 1 OvervieW in heed 15 1 1 System Information 15 1 1 Pinnilig Ra Eier rte RP eh 15 1 1 Interrupt Events and 15 1 1 Module Suspend 15 2 1 Oscillators o berane re gre yos prs a meten 15 2 1
89. 1 1 1 TW 1 User s Manual 16 24 V1 0 2010 02 UART V 1 6 Cinfineon XC82x UART Field Bits Description FD_SEL 4 0 rw Fractional Divider Selection Selects the fractional divider to be n 32 where n is the value of FD SEL and is in the range of 0 to 31 For example writing 0001 to FD SEL selects the fractional divider to be 1 32 Note Fractional divider has no effect if BR VALUE 000 BR VALUE 7 5 rwh_ Baud Rate Timer Reload Value The lower three bits of the 11 bit Baud Rate Timer Reload value See also description in BGH register BGH Baud Rate Timer Reload Register High Byte F44 Reset Value 00 RMAP 0 PAGE 5 7 6 5 4 3 2 1 0 BR VALUE rwh Field Bits Description BR_VALUE 7 0 rwh_ Baud Rate Timer Reload Value The upper 8 bits of the 11 bit Baud Rate Timer Reload value When the 11 bit BR_VALUE is 000 baud rate timer is bypassed User s Manual UART V 1 6 16 25 V1 0 2010 02 Cinfineon Inter IC Bus 17 Inter IC Bus 17 1 Overview The IIC provides an interface between the microcontroller and an IIC bus that conforms to the IIC Bus Protocol The IIC can operate in either master or slave mode It performs arbitration in master mode to allow it to operate in multi master systems The IIC provides communication at data rates of up to 400 KBaud and features 7 bit addressing as well as 10 bit addressi
90. 14 2 lists the interrupt event sources from the Timer 2 and the corresponding event interrupt enable bit and flag bit User s Manual 14 3 V1 0 2010 02 Timer 2 V 1 2 Cinfineon 2 Table 14 2 Timer 2 Interrupt Events Event Event Interrupt Enable Bit Event Flag Bit Timer 2 Overflow T2_T2CON1 TF2EN T2_T2CON TF2 Timer 2 External T2_T2CON1 EXF2EN T2_T2CON EXF2 Table 14 3 shows the interrupt node assignment for each Timer 2 interrupt source Table 14 3 Timer 2 Events Interrupt Node Control Event Interrupt Node Interrupt Node Flag Vector Enable Bit Bit Address Timer 2 Overflow IENO ET2 2B Timer 2 External 14 2 4 IP interconnection In XC82x T2EX 4 input and T2EX 5 input can be triggered by Out of Range 0 ORCO event and Out of Range 1 ORC1 event from the ADC module respectively as shown in Table 14 4 ORCx will generate a rising edge signal to the T2EX input when there is an out of range event To detect a rising edge signal in T2EX input either bit EDGESEL or T2REGS of T2 T2MODE register must be set to 1 depending on the usage of the pin In addition T2EX 4 or T2EX 5 input needs to be setup via MODPISEL2 register as shown in Table 14 1 Table 14 4 Timer 2 Interconnections Connected Other Module Function Signal Timer 2 Function Signal Out of Range 0 ORCO Timer 2 External Trigger i T2EX 4 Out of Range 1 0 ORC1 Timer 2 External Trigger i T
91. 14 registers 12 registers for data manipulation one register to control the operation of MDU and one register for storing the status flags These registers are memory mapped as special function registers like any other registers for peripheral control The MDU operates concurrently with and independent of the CPU Features e Fast signed unsigned 16 bit multiplication Fast signed unsigned 32 bit divide by 16 bit and 16 bit divide by 16 bit operations Signed 16 bit multiplication with single left shift to support fixed point number calculations in Q15 format Signed 32 bit divide by 16 bit with single right shift to support fixed point number calculations in Q15 format e 32 bit unsigned normalize operation e 32 bit arithmetic logical shift operations User s Manual 12 1 V1 0 2010 02 MDU V2 9 Cinfineon XC82x Multiplication Division Unit Table 12 1 specifies the number of clock cycles used for calculation in various operations Table 12 1 MDU Operation Characteristics Operation Result Reminder No of Clock Cycles Used for Calculation Signed 32 bit 16 bit 32 bit 16 bit 33 Signed 32 bit 16 bit with 32 bit 16 bit 33 Single Right Shift Signed 16 bit 16bit 16 bit 16 bit 17 Signed 16 bit x 16 bit 32 bit 16 Signed 16 bit x 16 bit with 32 bit 16 Single Left Shift Unsigned 32 bit 16 bit 32 bit 16 bit 32 Unsigned 16 bit 16 bit 16 bit 16 bit 16 Unsigned
92. 16 bit reload of the timer count upon overflow or a capture of current timer count depending on the mode selected User s Manual 14 14 V1 0 2010 02 Timer 2 V 1 2 Cinfineon XBox Timer 2 T2 RC2L Timer 2 Reload Capture Register Low Byte C2 Reset Value 00 RMAP 0 PAGE X 7 6 5 4 3 2 1 0 RC2 rwh Field Bit Type Description RC2 7 0 rwh Reload Capture Value 7 0 If CP RL2 0 these contents are loaded into the timer register upon an overflow condition If CP RL2 1 this register is loaded with the current timer count upon a negative positive transition at pin T2EX when EXEN2 1 T2_RC2H Timer 2 Reload Capture Register Low Byte C3 Reset Value 00 RMAP 0 PAGE X 7 6 5 4 3 2 1 0 RC2 rwh Field Bit Type Description RC2 7 0 rwh Reload Capture Value 15 8 If CP RL2 0 these contents are loaded into the timer register upon an overflow condition If CP RL2 1 this register is loaded with the current timer count upon a negative positive transition at pin T2EX when EXEN2 1 14 8 4 Timer 2 Count Register Register T2L and T2L hold the current 16 bit value of the Timer 2 count User s Manual 14 15 V1 0 2010 02 Timer 2 V 1 2 rm XC82x Infineon Timer 2 T2 T2L Timer 2 Low Byte C44 Reset Value 00 RMAP 0 PAGE X 7 6 5 4 3 2 1 0 THL2 rwh Field Bit Type Description THL2 7 0 rwh
93. 16 bit x 16 bit 32 bit 16 32 bit normalize No of shifts 1 32 32 bit shift L R No of shifts 1 32 12 2 System Information This section provides system information relevant to the MDU 12 2 1 Clocking Configuration The MDU runs on the FPCLK at a fixed frequency of 48 MHz If the MDU functionality is not required at all it can be completely disabled by gating off its clock input for maximal power reduction This is done by setting bit MDU_DIS in register PMCON1 as described below The bit field PAGE of SCU PAGE register must be programmed before accessing the PMCON register User s Manual MDU V2 9 12 2 V1 0 2010 02 Cinfineon Multiplication Division Unit PMCON1 Peripheral Management Control Register 1 EF Reset Value DF RMAP 0 PAGE 1 7 6 5 4 3 2 1 0 DIS LTS DIS 0 DIS T2 DIS DIS SSC DIS DIS rw rw r rw rw rw rw rw Field Bits Type Description MDU DIS 4 rw MDU Disable Request Active high 0 MDU is in normal operation 1 Request to disable the MDU default 0 5 r Reserved Returns 0 if read should be written with O 12 2 2 Interrupt Events and Assignment Table 12 2 lists the interrupt event sources from the MDU and the corresponding event interrupt enable bit and flag bit Table 12 2 MDU Interrupt Events Event Event Interrupt Enable Bit Event Flag Bit End of
94. 2010 02 ADC V2 1 Cinfineon Analog to Digital Converter The Limit Check Boundary Registers define compare values boundaries for the limit checking unit ADC_LCBRO Limit Check Boundary Register 0 CD Reset Value 70 ADC_LCBR1 Limit Check Boundary Register 1 Reset Value B0 RMAP 0 PAGE 0 7 6 5 4 3 2 1 0 BOUNDARY rw Field Bits Type Description BOUNDARY 7 0 rw Boundary for Limit Checking This value is compared to the actual conversion result 21 8 4 Alias Feature The alias feature re directs conversion requests for channels CHO to other channel numbers This means that CHO are converted with the channel parameters of the referenced channel instead of with their own The re direction feature serves several purposes The same signal can be measured twice and the two results original and re directed can be stored in separate result registers This allows triggering both conversions quickly one after the other while data loss is avoided independent from the CPU interrupt latency The sensor signal is connected to only one input instead of two This can save input pins in low cost applications and reduces the input leakage to be considered in the error calculation Even if the analog input CHO is used as alternate gnd see Figure 21 18 the internal trigger and data handling features for channel CHO can be used The channel settings for both conversions of the
95. 2010 02 CCU6 V4 0 Cinfineon Capture Compare Unit 6 CCU6 contains a programmable Dead Time Generation Block that delays the passive to active edge of the switching signals by a programmable time the active to passive edge is not delayed The Dead Time Generation Block illustrated in Figure 20 16 is built in a similar way for all three channels of T12 It is controlled by bits in register T12DTCL T12DTCH Any change of a CC6xST State Bit activates the corresponding Dead Time Counter that is clocked with the same input clock as T12 2 The length of the dead time can be programmed by bit field DTM This value is identical for all three channels Writing TCTR4L DTRES 1 sets all dead times to passive Dead Time Value DTM DTRES Dead Time Counter 0 Dead Time Dead Time Counter 1 Counter 2 Dead Time 2 active passive Dead Time 0 Dead Time 1 active passive active passive M Y v 605 605 615 615 625 625 CCU6_MCB05520 Figure 20 16 Dead Time Generation Block Diagram Each of the three dead time counters has its individual dead time enable bit DTEx An enabled dead time counter generates a dead time delaying the passive to active edge of the channel output signal The change in a State Bit CC6xST is not taken into account while the dead time generation of this channel is currently in progress active
96. 3 polling of polling of check for conversion request request Notused synchronized can be source 0 source 1 start request started ADC arbiter round Figure 21 10 Arbitration Round User s Manual 21 38 V1 0 2010 02 ADC V2 1 Cinfineon Analog to Digital Converter User s Manual 21 39 V1 0 2010 02 ADC V2 1 Cinfineon Analog to Digital Converter 21 7 1 Arbiter Timing The timing of the arbiter i e of an arbitration round is determined by the number of arbitration slots within an arbitration round and by the duration of an arbitration slot An arbitration round consist of 4arbitration slots The duration of an arbitration slot is configurable fg fapc The duration of an arbitration round therefore is tars N x tsio N number of slots The period of the arbitration round introduces a timing granularity to detect an incoming conversion request signal and the earliest point to start the related conversion This granularity can introduce a jitter of maximum one arbitration round The jitter can be reduced by minimizing the period of an arbitration round To achieve a reproducible reaction time constant delay without jitter between the trigger event of a conversion request e g by a timer unit or due to an external event and the start of the related conversion mainly the following two options exist For both options the converter has to be idle and other conversion requests must not be pending for
97. 3 26 1 CCUG REISES o i oua ri hes Etre 3 26 1 SOC Registers 4c ex ERREUR REED Eu Ra PUR DEC 3 31 1 IC Redlsters woes tae he bcr ROS RUP sc cb Rus 3 31 1 OCDS Registers cucckuwukcu 3 32 1 Flash Memory use ze eb eg eme epar kad eni E 4 1 1 Flash Memory Address Mapping 4 2 1 Flash Bank Sectorization 4 2 1 Wordline Address 4 5 1 Operating Modes 2 eee eo eee e See 4 8 1 Error Detection and Correction 4 9 1 Flash Error Address Register 4 10 1 In System Programming 4 11 1 In Application Programming 4 12 1 Flash Programming 4 13 1 Non background Flash Program Subroutine 4 13 1 Background Flash Program Subroutine 4 13 1 Flash Erasing cag 2 ee RR 4 13 1 Non background Flash Erase Subroutine 4 14 1 Background Flash Erase Subroutine 4 14 1 Aborting Background Flash Erase 4 14 1 Flash Read Mode Status 4 16 1 Boot and Startup 5 1 1 User Identification Nu
98. 3 Clock System and Control Figure 7 2 shows the block diagram of the clock system in XC82x It consists of a 48 MHz oscillator and a clock control unit CCU The system clock is generated by the 48 MHz internal oscillator In addition is also the input clock to the Clock Control Unit CCU The CCU generates all clock signals required within the microcontroller from the system clock It consists of Clock mode selection in active mode Centralized enable disable circuit for clock control LEDTSCU CCU6 MDU ADC v SSC UART TO T1 CLKMODE 1 T2 IIC WDT CLKMODE 0 FLASH Interface Clock Control Unit CCU 1 CLKMODE is an input to a Boot ROM user routine that is used to select the core frequency 2 Refer to the respective module chapter for the clock source to the counter in WDT and RTC Figure 7 2 Clock System Block Diagram In normal running mode the typical frequencies of different modules are as follows e CPU clock CCLK SCLK 24 MHz Flash Interface clock CCLKn 48 MHz Fast peripherial clock FPCLK 48 MHz Slow peripherial clock SPCLK 8 MHz Peripheral clock PCLK 24 MHz same as CPU clock User s Manual 7 11 V1 0 2010 02 Cinfineon System Control Unit Peripherals that are running in FPCLK frequency are CCU6 MDU ADC LED and Touch sense controller Oth
99. 6 224 Mode2 Program customer code to FLASH Mode 2 is used to transfer a customer program from the host to the Flash of the uC via serial interface The header block for this working mode has the following structure The Header Block Data Area 00 024 Header Mode 2 StartAddr StartAddr Block NotUsed Checksum Block High Low Length 1 byte 1 byte 1 byte 1 byte 2 bytes Mode Data Description Start Addr High Low 16 bit Start Address which determines where to copy the received program codes in the Flash This address must be valid and aligned to the page address Block_Length The length of the following Data Bocks or EOT Block At each time PC Host can sent minimum 1WL 32 bytes and maximum 3 WLs 96 bytes If data blocks are to be sent the maximum block_length has to be 98 96 2 bytes If only EOT block is sent the maximum block_length has to be 99 96 3 bytes Not used 2 bytes these bytes are not used and will be ignored in Mode 2 User s Manual 6 11 V1 0 2010 02 Cinfineon Boot Loader Note If the data starts non page address PC Host must fill up the beginning vacancies with 00 and provide the start address of that page address For e g if data starts in OF82 the PC Host will fill up the addresses OF 80 and OF 81 with 00 and provide the Start Address OF80 to microcontroller And if data is only 8 bytes the PC Host will also
100. 7 are only for devices that have 8 ADC channels For channels not implemented these bits should be treated as Reserved bits of type r which returns 0 if read and should be written with 0 User s Manual 21 49 V1 0 2010 02 ADC V2 1 Cinfineon XC82x Analog to Digital Converter Field Bits Type Description RESRSEL 1 0 Result Register Selection This bit field defines which result register will be the target of a conversion of this channel 00 The result register 0 is selected 01g The result register 1 is selected 10 result register 2 is selected 11 result register 3 is selected REFSEL 3 2 Reference Input Selection This bit field defines the reference source for this channel 00 Analog to digital conversion is done with reference to Vssp See Figure 21 12 01 Analog to digital conversion is done with internal 1 2V and CHO as the ground reference See Figure 21 13 10 Analog to digital conversion is dones with internal 1 2V and Vssp See Figure 21 14 11 Reserved do not use this combination LCC 6 4 Limit Check Control This bit field defines the behavior of the limit checking mechanism See Section 21 8 3 000g Never 001g Result outside area I 010 Result outside area Il 011 Result outside area III 100 Always boundaries disregarded 101 Result within area 110 Result within area II 111 Result within area III
101. 8 auto reload timer 11 Timer 0 is split into two halves TLO is an 8 bit timer controlled by the standard Timer 0 control bits and THO is the other 8 bit timer controlled by the standard Timer 1 control bits TH1 and TL1 of Timer 1 are held Timer 1 is stopped TOS 2 rw Timer 0 Selector Og Inputis from internal system clock 1g Inputis from TO GATEO 3 rw Timer 0 Gate Flag Og Timer 0 will only run if TCON TRO 1 software control 1g 0 will only run if EXINTO pin 1 hardware control and TCON TRO is set T1M 5 4 rw Mode Select Bits 00 13 bit timer M8048 compatible mode 01 16 bit timer 10g 8 bit auto reload timer 11 Timer 0 is split into two halves TLO is an 8 bit timer controlled by the standard Timer 0 control bits and THO is the other 8 bit timer controlled by the standard Timer 1 control bits TH1 and TL1 of Timer 1 are held Timer 1 is stopped T1S 6 rw Timer 1 Selector Og Inputis from internal system clock 1g Inputis from T1 pin GATE1 7 rw Timer 1 Gate Flag Og Timer 1 will only run if TCON TR1 1 software control 1g Timer 1 will only run if EXINTO pin 7 1 hardware control and TCON TR1 is set User s Manual Timer 0 and 1 V1 0 13 12 V1 0 2010 02 Cinfineon XC82x Timer 0 and Timer 1 IENO Interrupt Enable Register 8 Reset Value 00 RMAP X PAGE X 7 6 5 4 3 2 1 0 EA 0 ET2 ES ET1 EX1 rw r rw rw rw rw r
102. 8 1 Mode0 Program customer code to XRAM 6 9 1 Mode Execute customer code in XRAM 6 11 1 Mode2 Program customer code to FLASH 6 11 1 Mode3 Execute customer code in FLASH 6 13 1 Mode4 Erase customer code in FLASH sector s 6 13 1 Mode6 Program 4 bytes of USERID 6 14 1 ModeA Get 4 bytes Information 6 14 1 System Control Unit 7 1 1 Power Supply System with Embedded Voltage Regulator 7 1 1 Reduced Voltage Condition 7 3 1 EVR Register Description 7 4 1 Reset Control i c ace Rice ID REOR een oe Ron ROS RU OR 7 6 1 Types of 7 6 1 Power On Reset 7 6 1 Watchdog Timer Reset 7 1 1 DOM ROSE cut us der dun Eder 7 1 1 Power Down Wake Up Reset 7 7 1 Brownout Reset 7 1 1 Module Reset Behavior 7 8 1 Reset Control Register Description 7 9 1 Clock System and 7 11 1 Oscillator 0 7 12 1 Loss of Clock Detecti
103. 98 1 20 8 1 Modulation 20 98 1 20 8 2 Trap Control Register scisco e Res 20 100 1 20 8 3 Passive State Level Register 20 103 1 20 8 4 Multi Channel Mode Registers 20 104 1 20 9 Interrupt Handling 20 110 1 20 9 1 Interrupt Structure 20 110 1 20 9 2 Interrupt Registers 20 112 1 20 9 2 1 Interrupt Status Register 20 112 1 20 9 2 2 Interrupt Status Set Register 20 116 1 20 9 2 3 Status Reset Register 20 118 1 20 9 2 4 Interrupt Enable Register 20 120 1 20 9 2 5 Interrupt Node Pointer Register 20 124 1 20 10 General Module Operation 20 126 1 20 10 1 Inp t Selection essere ex pr 20 126 1 User s Manual 1 10 V1 0 2010 02 Cinfineon 20 10 2 20 10 2 1 20 11 21 21 1 21 1 1 21 1 2 21 1 3 21 1 4 21 2 21 3 21 4 21 5 21 5 1 21 6 21 6 1 21 6 2 21 6 3 21 7 21 7 1 21 7 2 21 8 21 8 1 21 8 2 21 8 3 21 8 4 21 8 5 21 8 6 21 8 7 21 9 21 9 1 21 10 21 10 1 21 10 2 21 11 21 12 22 22 1 22 2 22 3 22 4 22 5 General Registers 20 127
104. Basic Timer Operation 15 2 1 Real Time Clock Modes 15 2 1 Mode 1 Periodic Wake up Mode with 75 KHz Oscillator Clock 15 3 1 User s Manual 1 6 V1 0 2010 02 Cinfineon 15 5 2 15 6 15 7 15 7 1 16 16 1 16 2 16 2 1 16 2 2 16 2 3 16 3 16 3 1 16 3 2 16 3 3 16 3 4 16 4 16 5 16 5 1 16 5 2 16 5 3 16 6 16 6 1 16 6 2 16 6 2 1 16 6 2 2 16 6 2 3 16 6 2 4 16 7 16 7 1 16 7 2 16 7 3 17 17 1 17 2 17 2 1 17 2 1 1 17 2 2 17 2 3 17 3 17 4 17 5 17 6 Mode 3 Timer Mode with External Clock 15 4 1 Power Saving Mode Option 15 5 1 Registers 15 6 1 Real Time Clock Registers 15 7 1 UART ra e uec eS 16 1 1 OVerVIBW ee Sele dee x ded que 16 1 1 System Information 16 1 1 PINNING seme e poi betes ERI RR oidi pede bao ee 16 1 1 Clocking 16 2 1 Interrupt Events and 16 3 1 UART MOd6S 2x cei cheney eee ees 16 3 1 Mode 0 8 Bit Shift Register Fixed Baud Rate 16 3 1 Mode 1 8 Bit UART Variable Baud Rate 16 4 1 Mode 2
105. CC63SRH CC63RH T12MSELH MCMOUTH 9CH TCTR4L T12PRL IENL ISL 9DH TCTR4H T12PRH IENH ISH 9EH MCMOUTSL T13PRL INPL PISELOL 9FH MCMOUTSH T13PRH INPH PISELOH A4H ISRL T12DTCL ISSL PISEL2 A5H ISRH T12DTCH ISSH A6H CMPMODIFL TCTROL PSLR ATH CMPMODIFH TCTROH MCMCTR FAH CC60SRL CC60RL TCTR2L T12L FBH CC60SRH CC60RH TCTR2H T12H FCH CC61SRL CC61RL MODCTRL T13L FDH CC61SRH CC61RH MODCTRH T13H FEH CC62SRL CC62RL TRPCTRL CMPSTATL FFH CC62SRH CC62RH TRPCTRH CMPSTATH User s Manual 20 131 V1 0 2010 02 CCUG V4 0 82 Cinfineon 21 Analog to Digital Converter The Analog to Digital Converter module ADC of the XC82x uses the successive approximation method to convert analog input values voltages to discrete digital values Analog to Digital Converter One ADC kernel ADCO operate on a user selectable number of input channels The input channels can be selected and arbitrated flexibly ADC kernel 0 conversion control analog AD data result bus inputs converter handling inter face request control ADC_1_kernels Figure 21 1 ADC Module Block Diagram This section gives an overview about the feature of the ADC module and introduces the general structure which is described in the below fromat Introduction and Basic Structure on Page 21 7 Configuration of General Functions on Page 21 13 Conversion Request Generation on Page 21 17 Request Sourc
106. CCU6 20 1 1 Feature Set Overview This section gives an overview over the different building blocks and their main features Timer 12 Block Features Three capture compare channels each channel can be used either as capture or as compare channel Generation of a three phase PWM supported six outputs individual signals for high side and low side switches 16 bit resolution maximum count frequency peripheral clock Dead time control for each channel to avoid short circuits in the power stage Concurrent update of T12 registers Center aligned and edge aligned PWM can be generated Single shot mode supported Start can be controlled by external events Capability of counting external events Many interrupt request sources Hysteresis like control mode Timer 13 Block Features One independent compare channel with one output 16 bit resolution maximum count frequency peripheral clock Concurrent update of T13 registers Can be synchronized to T12 Interrupt generation at period match and compare match Single shot mode supported Start can be controlled by external events Capability of counting external events Additional Specific Functions Block commutation for Brushless DC drives implemented Position detection via Hall sensor pattern Noise filter supported for position input signals Automatic rotational speed measurement and commutation control for block commutation Integrated error handling Fast emergency stop without
107. CPU load via external signal CTRAP Control modes for multi channel AC drives Output levels can be selected and adapted to the power stage User s Manual 20 2 V1 0 2010 02 CCU6 V4 0 Cinfineon Capture Compare Unit 6 CCU6 20 1 2 Block Diagram The Timer T12 can operate in capture and or compare mode for its three channels The modes can also be combined e g a channel operates in compare mode whereas another channel operates in capture mode The Timer T13 can operate in compare mode only The multi channel control unit generates output patterns which can be modulated by T12 and or T13 The modulation sources can be selected and combined for the signal modulation CCU6 Module Kernel Compare CC60 Multi T12 CC61 Trap channel Control Control CC62 Clock Control Output Select Hall Input Output Select Trap Input Compare Interrupt Control Input Output Control TI 2HRIH A T13HR H A COUT63 COUT60 CC60 CC60IN D A COUT61 CC61 CC61IN D A COUT62 CC62 CC62IN D A CCPOSO D A CCPOS1 D A CCPOS2 D A CTRAPID A Port Control Do O80 CCU6_MCB05506 Figure 20 1 CCU6 Block Diagram User s Manual 20 3 V1 0 2010 02 CCU6 V4 0 Cinfineon Capture Compare Unit 6 CCU6 20 1 3 Register Overview For the generation of the overall register table t
108. Calculation MDUCON IE MDUSTAT IRDY Occurrence of Error MDUSTAT IERR Table 12 3 shows the interrupt node assignment for each MDU interrupt source Table 12 3 MDU Events Interrupt Node Control Event Interrupt Node Interrupt Node Flag Vector Enable Bit Bit Address End of Calculation IEN1 EX2 43 Occurrence of Error 12 3 Functional Description The MDU can be regarded as a special coprocessor for multiplication division normalization and shift Its operation can be divided into three phases see Figure 12 1 User s Manual 12 3 V1 0 2010 02 MDU V2 9 Cinfineon Multiplication Division Unit Phase One Load MDx Registers In this phase the operands are loaded into the MDU Operand MDx registers by the CPU The type of calculation the MDU must perform is selected by writing a 4 bit opcode that represents the required operation into the bit field MDUCON OPCODE Phase Two Execute Calculation This phase commences only when the start bit MDUCON START is set which in turn sets the busy flag The start bit is automatically cleared in the next cycle During this phase the MDU works on its own in parallel with the CPU The result of the calculation is made available in the MDU Result MRx registers at the end of this phase Phase Three Read Result from the MRx Registers In this final phase the result is fetched from the MRx registers by the CPU The MRx registers will be overwrit
109. Capture etc Compare Shadow Register CC6xSR Write Read CCU6_MCA05546 Figure 20 22 T12 Shadow Register Overview User s Manual 20 41 V1 0 2010 02 CCU6 V4 0 Cinfineon Capture Compare Unit 6 CCU6 T12 shadow register transfer takes place T12_ST active while timer T12 is not running T12R 0 or e STE12 1 and a Period Match is detected while counting up or e STE12 1 and a One Match is detected while counting down When signal T12 ST is active a shadow register transfer is triggered with the next cycle of the T12 clock Bit STE12 is automatically cleared with the shadow register transfer 20 3 7 Timer T12 Operating Mode Selection The operating mode for the T12 channels are defined by the bit fields TCTRAL MSEL6x T12MSELL MSEL6x Table 20 10 T12 Capture Compare Modes Overview MSEL6x Selected Operating Mode 00005 Capture Compare modes switched off 1111 00015 Compare mode see Section 20 3 3 0010s same behavior for all three codings 0011 01XXg Double Register Capture modes see Section 20 3 5 1000 Hall Sensor Mode see Section 20 7 In order to properly enable this mode all three MSEL6x fields have to be programmed to Hall Sensor mode 10015 Hysteresis like compare mode see Section 20 3 3 3 1010 Multi Input Capture modes see Section 20 3 5 10115 1100 1101 1110 The clocking and counting scheme of the timers are controlled by the
110. Cinfineon ROM Library 23 3 4 Long Division 23 20 Valuel Outputs are Result and Remainder of Value2 Table 23 18 Specifications of 32 32 bit Division Subroutine Subroutine C ULDIV XC Address DFC9 Input R7 of current Register Bank Value Bits 7 0 R6 of current Register Bank Value1 Bits 15 8 R5 of current Register Bank Value1 Bits 23 16 R4 of current Register Bank Value1 Bits 31 24 R3 of current Register Bank Value2 Bits 7 0 R2 of current Register Bank Value2 Bits 15 8 R1 of current Register Bank Value2 Bits 23 16 RO of current Register Bank Value2 Bits 31 24 User s Manual 23 42 V1 0 2010 02 ROM Library V0 5 Cinfineon XC82x ROM Library Table 23 18 Specifications of 32 32 bit Division Subroutine cont d Output R7 of current Register Bank Result of Value1 Value2 Bits 7 0 R6 of current Register Bank Result of Value1 Value2 Bits 15 8 R5 of current Register Bank Result of Value1 Value2 Bits 23 16 R4 of current Register Bank Result of Value1 Value2 Bits 31 24 R3 of current Register Bank Remainder of Value1 Value2 Bits 7 0 R2 of current Register Bank Remainder of Value1 Value2 Bits 15 8 R1 of current Register Bank Remainder of Value1 Value2 Bits 23 16 RO of current Register Bank Remainder of Value1 Value2 Bits 31 24 Stack
111. Clock Compare Capture Register 1 Type d rwh Modes 0 and 2 E94 RTC_RTCCR1 Reset 004 Bit Fie CC_VAL Real Time Clock Compare Capture Register 1 Type rwh Modes 1 and 3 RTCCR2 Reset 004 Bit Fie 0 CC_MINUTES Real Time Clock Compare Capture Register 2 Type r rwh Modes 0 and 2 RTCCR2 Reset 00 Bit Fie CC_VAL Real Time Clock Compare Capture Register 2 Type rwh Modes 1 and 3 EBH RTC_RTCCR3 Reset 004 Bit Fie 0 CC_HOURS Real Time Clock Compare Capture Register 3 Type rwh Modes 0 and 2 EBH RTCCR3 Reset 004 Bit Fie CC_VAL Real Time Clock Compare Capture Register 3 Type rwh Modes 1 and 3 ECH RTC_RTCCR4 Reset 00 Bit Fie CC_DAYS Real Time Clock Compare Capture Register 4 Type rwh Modes 0 and 2 EDH RTCCRS Reset 00 Bit Fie 0 CC D Real Time Clock AYS Compare Capture Register 5 Modes 0 and 2 Type r DN User s Manual 3 25 V1 0 2010 02 Memory Organization V 0 1 Infineon 3 4 5 XC82x 8 Timer 2 Registers Memory Organization The Timer 2 SFRs can be accessed in the standard memory area RMAP 0 Table 3 8 T2 Register Overview Addr Register Name Bit 7 6 5 4 3 2 1 0 IRMAP 0 2_ 2 Reset 004 Bit Field TF2 EXF2 0 TR2 C_T2 CP_RL Timer 2 Control Re
112. Description Data Block 01 This block length depends on the special information given in the previous header block This block is used in working mode 0 and 2 to transfer a portion of program code The program code is in the data area of the block EOT Block 02 This block length depends the special information given in the previous header block This block is the last block in data transmission in working mode 0 and 2 The last program code to be transferred are in the data area of the block 6 2 1 3 Response codes to the host The uC would let the host know whether a block has been successfully received by sending out a response code If a block is received correctly an Acknowledge Code 55 is sent In case of failure there are two kinds of errors The error might be a wrong block type and the UART BSL would send back a block type error OFF to the host This kind of error is caused by two conditions One is the uC receives a block type other than the implemented ones The other is the uC receives the transfer blocks in wrong sequences For example in working mode 0 immediately after the header block is received if another header block instead of a data block is received the uC would consider this case be a wrong block type error Besides wrong block type error the other error is checksum error If the checksum comparison fails the UART BSL routine is rejecting the transfer block by sending back a checksum error c
113. ECCIP1 IRCON2 CCU6SR1 5B SR2 IEN1 ECCIP2 IRCONS3 CCUGSR2 63 MODIEN CCU6SR2EN SR3 IEN1 ECCIP3 65 6B MODIEN CCU6SR3EN Beside the event interrupt enable bit as shown in Table 20 3 bit MODIEN CCU6SR2EN and MODIEN CCU6SR3EN must be set to 1 to enable the SR2 and SR3 interrupt service request The bit field PAGE of register SCU_PAGE must be programmed before accessing the MODIEN register Note SR2 and SR3 event of CCU6 module are used as interconnection output signals to trigger CC6x inputs T12HR input and T13HR input If no interrupt service is required during this type of trigger mode control bits in register MODIEN can be disabled However for SR2 and SR3 events to be used as interconnection output signal the event interrupt enable bit in register IENL and IENH must be enabled User s Manual 20 13 V1 0 2010 02 CCU6 V4 0 Cinfineon Capture Compare Unit 6 CCU6 MODIEN Peripheral Interrupt Enable Register F7 Reset Value 07 RMAP 0 PAGE 3 7 6 5 4 3 2 1 0 CCU6SR3 CCU6SR2 EN EN 0 RIREN TIREN EIREN rw rw r rw rw rw Field Bits Type Description CCU6SR2EN 6 rw CCU6 SR2 Enable 0 CCU6 SR2 interrupt service request is disabled 1 CCU6 SR2 interrupt service request is enabled CCU6SR3EN 7 rw CCU6 SR3 Enable 0 CCU6 SR3 interrupt service request is disabled 1 CCU6 SR3 interrupt service request is enabled 0 5 3 r Reserved Returns 0 if
114. EXINTO 3 SCU ANALOG ADC P2 1 Input P2 DATAIN P1 ALT 1 CCPOS1 1 CCU6 ALT 2 RXD_3 UART ALT 3 MTSR_4 SSC ALT 4 ALT 5 TO 1 Timer 0 ALT 6 EXINT1 1 SCU ANALOG 1 ADC P2 2 Input P2_DATAIN P1 ALT 1 CCPOS2_1 CCU6 ALT 2 T12HR_3 CCU6 ALT 3 T13HR_3 CCU6 ALT 4 SCK_1 SSC ALT 5 T1 1 Timer 1 ALT 6 EXINT2 SCU ANALOG 2 ADC User s Manual 11 31 V1 0 2010 02 Cinfineon XC82x Table 11 10 Port 2 Input Functions cont d Parallel Ports Port Pin Input Output Select Connected Signal s From to Module P2 3 Input GPI P2 DATAIN P3 ALT 1 CCPOSO 2 CCU6 ALT 2 CTRAP _2 CCU6 ALT 3 ALT 4 ALT 5 2_2 2 ALT 6 EXINT3 SCU ANALOG ADC User s Manual 11 32 V1 0 2010 02 Cinfineon XC82x 11 4 2 Registers Description Parallel Ports P2_DATAIN Port 2 Data Register 94 Reset Value 0X RMAP 0 PAGE 0 7 6 5 4 3 2 1 0 0 P3 P2 P1 PO rh rh rh rh Field Bits Type Description Pn n rh Port 2 Pin n Data Value 0 3 0 Port 2 pin n data value 0 1 Port 2 pin n data value 1 0 7 4 r Reserved Returns 0 if read should be written with 0 P2_EN Port 2 Enable Register 94 Reset Value 00 RMAP 0 PAGE 3 7 6 5 4 3 2 1 0 0 P3 P2 P1 PO T rw rw rw rw Field Bits Type Description Pn n rw Port 2 Pin n Input Driver Control n 0 3 0 Input d
115. Flag RCC61R 2 No action RCC62R 4 1g CC6xR will be cleared RCC60F 1 Ww Reset Capture Compare Match Falling Edge RCC61F 3 Flag RCC62F 5 Og action 1g Bit CC6xF will be cleared RT120M 6 Reset Timer T12 One Match Flag Og action 1g Bit 12 will be cleared RT12PM 7 w Reset Timer T12 Period Match Flag Og action 1g Bit T12PM IS will be cleared Status Reset Register High 5 Reset Value 00 RMAP 0 PAGE 0 7 6 5 4 3 2 1 0 RSTR RIDLE RWHE RCHE 0 RTRPF RT13PM RT13CM w w Ww Ww r w w User s Manual 20 118 V1 0 2010 02 CCUG V4 0 Cinfineon XC82x Capture Compare Unit 6 CCU6 Field Bits Type Description RT13CM 0 Ww Reset Timer T13 Compare Match Flag Og action 1g Bit T13CM will be cleared RT13PM 1 Ww Reset Timer T13 Period Match Flag Og No action 1g Bit T13PM will be cleared RTRPF 2 Ww Reset Trap Flag Og action 1g Bit TRPF will be cleared not taken into account while input CTRAP 0 and TRPPEN 1 RCHE 4 WwW Reset Correct Hall Event Flag Og action 1g will be cleared RWHE 5 Ww Reset Wrong Hall Event Flag 1g No action 0 Bit WHE will be cleared RIDLE 6 w Reset IDLE Flag Og No action 1g Bit IDLE will be cleared RSTR 7 w Reset STR Flag Og No action 1 Bit STR will be cleared 0 3 r reserved returns 0 if read should be written with 0 User s
116. Functions cont d Parallel Ports Port Pin Input Output Select Connected Signal s From to Module P0 3 Input GPI PO DATAIN P3 ALT1 ALT2 CC60_1 CCU6 ALT3 SDA_1 ALT4 ALT5 ALT6 CTRAP _0 CCU6 ALT7 TSIN3 LEDTSCU Output GPO DATAOUT P3 ALT1 LINE3 TSIN3 SSC ALT2 SDA_1 ALT3 CC60_1 CCU6 P0 4 Input GPI PO_DATAIN P4 ALT1 2 _1 2 ALT2 SCL 0 ALT3 SCK 0 SSC ALT4 ALT5 EXINT1_0 SCU ALT6 CTRAP _1 CCU6 ALT7 TSIN4 LEDTSCU Output GPO DATAOUT P4 ALT1 LINE4 TSIN4 LEDTSCU ALT2 SCK 0 SSC ALT3 EXF2_0 Timer 2 ALT4 SCL 0 ALT5 COLO 1 LEDTSCU ALT6 1 LEDTSCU ALT7 COLA_2 LEDTSCU User s Manual 11 14 V1 0 2010 02 Cinfineon XC82x Parallel Ports Table 11 4 Port 0 Input Output Functions cont d Port Pin Input Output Select Connected Signal s From to Module 5 Input GPI PO DATAIN P5 ALT1 RXD 0 UART ALT2 RTCCLK RTC ALT3 MTSR 0 SSC ALTA MRST 1 SSC ALT5 EXINTO 0 SCU ALT6 ALT7 TSIN5 LEDTSCU Output GPO PO DATAOUT P5 ALT1 LINES TSIN5 LEDTSCU ALT2 MTSR 0 SSC ALT3 COUT62_1 CCU6 ALT4 TXD_3 UART ALT5 COL1_1 LEDTSCU ALT6 EXF2_2 Timer 2 User s Manual 11 15 V1 0 2010 02 Cinfineon XC82x Table 11 4 Port 0 Input Output Functions cont d Parallel Ports
117. IEN1 EADC IRCON1 ADCSRO 33 SR1 IRCON1 ADCSR1 21 1 4 IP Interconnection The ADC has interconnection to other peripherals enabling higher level of automation without requiring software Table 21 4 describes the interconnection from ADC outputs channel events and out of range comparator events to CCU6 and Timer 2 inputs Table 21 5 describes the interconnection from CCU6 and LEDTSCU outputs to the external request trigger input of ADC User s Manual 21 4 V1 0 2010 02 ADC V2 1 Cinfineon XC82x Table 21 4 ADC Output Interconnections Analog to Digital Converter ADC Function Signal Connected Other Module Inputs Selected By Channel Events ADC channel event ADC_CHEV CCUS input i TI2HR CCU6_PISELOH IST12HR 115 CCUS input i T13HR CCU6_PISEL2 IST13HR 11 ADC channel event 0 CCU6 input i CTRAP CCU6_PISELOL ISTRP 11 ADC_CHEVO ADC channel event 1 0 No connection ADC_CHEV1 ADC channel event 2 No connection ADC_CHEV2 ADC boundary event 0 CCU6 input i CC60 CCU6_PISELOL ISCC60 11 ADC BFO CCU6 input i CCPOSO CCU6 PISELOH ISPOSO 11 ADC boundary event 1 CCU6 input i CC61 CCU6_PISELOL ISCC61 11 ADC BF1 CCU6 input i CCPOS1 CCU6_PISELOH ISPOS1 11 ADC boundary event2 CCU6 input i CC62 CCU6_PISELOL ISCC62 11 ADC_BF2 CCU6 input i 52 CCU6_PISEL
118. Introduction Table 1 1 Pin Definitions and Functions for XC82x Symbol Pin Type Reset Function Number State DSO20 TSSOP16 P0 2 17 14 Hi Z T10 Timer 1 Input CC62 1 Input Output of Capture Compare channel 1 SCL 1 Clock Line CCPOS2 0 CCU6 Hall Input 2 TSIN2 Touch sense Input 2 LINE2 LED Line 2 P0 3 18 15 Hi Z 60 1 Input Output of Capture Compare channel 1 SDA 1 Data Line CTRAP 0 CCU6 Trap Input TSIN3 Touch sense Input 3 LINE3 LED Line 3 P0 4 19 16 PD T2EX_1 Timer 2 External Trigger Input SCK 0 SSC Clock Input Output SCL 0 Clock Line CTRAP 1 CCU6 Trap Input EXINT1 O External Interrupt Input 1 TSIN4 Touch sense Input 4 LINE4 LED Line 4 EXF2_0 Timer 2 Overflow Flag COLO 1 LED Column 0 1 LED Column 3 COLA 2 LED Column A User s Manual System Architecture V1 0 1 7 V1 0 2010 02 Cinfineon XC82x Introduction Table 1 1 Pin Definitions and Functions for XC82x Symbol Pin Type Reset Function Number State DSO20 TSSOP16 P0 5 20 1 Hi Z RXD 0 UART Receive Input RTCCLK RTC External Clock Input MTSR 0 SSC Master Transmit Output Slave Receive Input MRST 1 SSC Master Receive Input EXINTO 0 External Interrupt Input 0 TSIN5 Touch sense Input 5 LINE5 LED Line 5 COUT62 1 Output of Capture Compare Channel 2 TXD 3 UART Transmit Output 2 wire UART BSL Transmit Output COL 1 LED Column 1 EXF2 2 Timer 2 Overflow Flag P0 6 1 2 PU SPD_0 SPD Input Output R
119. LDLINE 3 COMPARE 0 COMPARE 1 COMPARE 2 COMPARE 3 TS PADTx has common compare value R7 R7 1 R7 2 R7 3 R7 4 R5 1 R5 2 R5 3 R5 4 TS PADTx has different compare value LDLINE 0 LDLINE 1 LDLINE 2 LDLINE 3 LDLINE 4 LDLINE 5 LDLINE 6 COMPARE 0 COMPARE 1 COMPARE 2 COMPARE 3 COMPARE 4 COMPARE 5 COMPARE 6 R7 R7 1 R7 2 R7 3 R7 4 R7 5 R7 6 R7 7 R5 R5 1 R5 2 R5 3 R5 4 R5 5 R5 6 R5 7 R5 8 R5 9 R5 10 R5 11 R5 12 R5 13 R5 14 R5 15 TS PADTx has compare value LDLINE 0 LDLINE 1 LDLINE 2 LDLINE 3 LDLINE 4 LDLINE 5 LDLINE 6 R7 R7 1 R7 2 R7 3 R7 4 R7 5 R7 6 R7 7 COMPARE 0 R5 1 COMPARE 1 R5 2 COMPARE 2 R5 3 COMPARE 3 R5 4 COMPARE 4 R5 5 COMPARE 5 R5 6 6 R5 7 For LED Figure 23 5 User s Manual Input Parameters Examples 2 LED amp TS enabled ROM Library V0 5 23 20 V1 0 2010 02 Cinfineon ROM Library 23 22 FINDTOUCHEDPAD Function TS The touch sense concept is based on a pad being a capacitor between the padline
120. LEDCOL Refer Section 19 4 for details When this bit is clear to O from other value the LEDTS counter stops running and resets TS 6 rw Touch Sense Function Enable Set to enable the kernel for touch sense function control when CLK_PS is set from 0 LD EN 7 rw LED Function Enable Set to enable the kernel for LED function control when CLK PS is set from 0 1 This bit can only be modified when bit CLK PS 0 User s Manual LEDTSCU V 1 2 1 19 21 V1 0 2010 02 Cinfineon LED and Touch Sense Controller LTS_GLOBCTL1 Global Control Register 1 D8 Reset Value 00 RMAP 0 PAGE X 7 6 5 4 3 2 1 0 TSF ITS_EN TFF ITF EN CLKSEL FNCOL rwh rw rwh rw rw rh Field Bits Type Description FNCOL 2 0 rh Previous Active Function LED Column Status Shows the active function LED column in the previous time slice Updated on start of new time slice when LEDTS counter 8LSB over flows Controlled by latched value of the internal DE MUX see Figure 19 2 CLKSEL 3 rw LEDTS Counter Clock Input Select 0s 48 MHZ is selected 1g 8 MHz is selected ITF_EN 4 rw Enable Time Frame Interrupt Og Disabled 1g Enabled TFF 5 rwh Time Frame Interrupt Flag Set on activation of each new time frame including when bit CLK_PS is set from 0 To be cleared by software ITS_EN 6 rw Enable Time Slice Interrupt Og Disabled 1g Enabled TSF 7 rwh Time Slice Interrupt
121. MDU Result Register 0 Type B3y MD1 Reset 004 Bit Fie DATA MDU Operand Register 1 Type User s Manual 3 14 V1 0 2010 02 Memory Organization V 0 1 Infineon XC82x Memory Organization Table 3 2 MDU Register Overview cont d Addr Register Name Bit 7 6 5 4 3 2 1 0 B3y MR1 Reset 004 Bit Field DATA MDU Result Register 1 Type rh B4y MD2 Reset 004 Bit Field DATA MDU Operand Register 2 Type rw B4y MR2 Reset 004 Bit Field DATA MDU Result Register 2 Type rh B5H MD3 Reset 004 Bit Field DATA MDU Operand Register 3 Type rw B5H MR3 Reset 004 Bit Field DATA MDU Result Register 3 Type rh MD4 Reset 004 Bit Field DATA MDU Operand Register 4 Type rw MR4 Reset 004 Bit Field DATA MDU Result Register 4 Type rh B7y MD5 Reset 004 Bit Field DATA MDU Operand Register 5 Type rw B7y MR5 Reset 004 Bit Field DATA MDU Result Register 5 Type rh 3 4 5 3 System Control Registers The system control SFRs can be accessed in the standard memory area RMAP 0 Table 3 3 SCU Register Overview Addr Register Name Bit 7 6 5 4 3 2 1 0 RMAP 0 or 1 BFH SYSCONO Reset 044 Bit Field 0 IMOD 0 1 0 RMAP System Control Register 0 E Type r rw r r r rw RMAP 0 Fin SCU PAGE Reset 004 Bit Field STNR 0
122. Manual CCU6 V4 0 20 119 V1 0 2010 02 Cinfineon Capture Compare Unit 6 CCU6 20 9 2 4 Interrupt Enable Register Register IENL H contains the interrupt enable bits and a control bit to enable the automatic idle function in the case of a wrong hall pattern IENL Interrupt Enable Register Low 9 Reset Value 00 RMAP 0 PAGE 2 7 6 5 4 3 2 1 0 ENT12PM ENT12OM ENCC62F ENCC62R ENCC61F ENCC61R ENCC60F ENCC60R rw rw rw rw rw rw rw rw Field Bits Type Description ENCC60R 0 rw Capture Compare Match Rising Edge Interrupt ENCC61R 2 Enable for Channel CC6x ENCC62R 4 interrupt will be generated if the set condition for bit CC6xR in register IS occurs 1g An interrupt will be generated if the set condition for bit CC6xR in register IS occurs The service request output that will be activated is selected by bit field INPCC6x ENCCOOF 1 rw Capture Compare Match Falling Edge Interrupt ENCC6 1F 3 Enable for Channel CC6x ENCC62F 5 No interrupt will be generated if the set condition for bit CC6xF in register IS occurs 1g An interrupt will be generated if the set condition for bit CC6xF in register IS occurs The service request output that will be activated is selected by bit field INPCC6x ENT120M 6 rw Enable Interrupt for T12 One Match No interrupt will be generated if the set condition for bit T12OM in register IS occurs 1g An interr
123. Manual 3 19 V1 0 2010 02 Memory Organization V 0 1 Infineon XC82x Memory Organization Table 3 5 ADC Register Overview cont d Addr Register Name Bit 7 6 5 4 3 2 1 0 ADC_INPCRO Reset 004 Bit Field 0 STC Input Class 0 Register Type rw CFH ADC_LCBR1 Reset BO Bit Field BOUND1 Limit Check Boundary Register 1 Type D2u ADC LORE Reset 004 Bit Field 0 LORE LORE LORE LORE Latched Out of Range Event 3 2 1 0 Register Type rwh rwh rwh rwh ADC_ENORC Reset 004 Bit Field 0 ENOR ENOR ENOR ENOR Enable Out of Range C3 C2 C1 Comparator Register Type r TW rw rw TW RMAP 0 PAGE 1 ADC CHCTRO Reset 00 Bit Field BFEN LCC REFSEL RESRSEL Channel Control Register 0 Type rw TW TW TW CBH ADC CHCTR1 Reset 00 Bit Field BFEN LCC REFSEL RESRSEL Channel Control Register 1 Type rw rw rw rw CCH ADC CHCTR2 Reset 00 Bit Field BFEN LCC REFSEL RESRSEL Channel Control Register 2 Type rw rw rw rw CDH ADC CHCTR3 Reset 00 Bit Field 0 LCC REFSEL RESRSEL Channel Control Register 3 Type r rw rw TW RMAP 0 PAGE 2 ADC RESROL Reset 00 Bit Field RESULT VF DRC 0 CHNR Result Register 0 Low Type rh rh rh r rh CBH ADC RESROH Reset 00 Bit Field RESULT R
124. Memory and this routine User s Manual 10 12 V1 0 2010 02 OCDS V 2 7 1 Cinfineon Debug System identify OCDS as NMl requesting source and the type of IRAM access causing the request by evaluating NMISR FNMIOCDS in SCU and MMICR FNMIRR FNMIRW in OCDS b must clear FNMIRR FNMIRW flags before its end to allow a proper reaction on next NMIs 5 any attempt to configure activate a Breakpoint for debugging by writing into MMBPCR will reset the internal nmi_r e nmi_r e_ flags and therefore disable the generation of NMI request upon IRAM access Attention all the software handling of OCDS NMI servicing routine is to be supported by user code 10 6 2 X General NMI control by OCDS The controls are aimed to support a correct NMI related behavior allthe pending NMI requests raised before Monitor Mode entry and as long as the system is in Monitor Mode will be not affected i e these requests are safely kept and sent to the core when the system returns to User Mode 10 7 NMI mode priority over Debug mode While the core is in NMI mode after an NMI request has been accepted and before the RETI instruction is executed i e the time during a NMI servicing routine certain debug functions are blocked restricted 1 No external break refer to Section 10 4 2 is possible while the core is servicing a NMI External break requested inside a NMI servicing routine will be taken only after RETI is executed 2 A
125. Mode Stop When the STP bit is set to 1 the IIC will transmit a STOP condition If the STP bit is set while the IIC is in slave mode no STOP condition will be transmitted on the IIC bus but the IIC behaves as if a STOP condition has been received If both STA and STP bits are set the IIC will first transmit a STOP condition if in master mode before transmitting a START condition Og The IIC does not transmit any STOP condition 1g IIC transmits a STOP condition on the bus Note The STP bit is cleared automatically after the STOP condition has been sent writing O to this bit has no effect STA rwh Master Mode Start When the STA bit is set to 1 the IIC will enter master mode and transmit a START condition once the IIC bus is free If the is already in master mode and one or more bytes have been transmitted a repeated START condition will be transmitted If the IIC is still being accessed in slave mode the IIC will complete the data transfer in slave mode and enter master mode once the IIC bus has been released Og The IIC does not enter master mode 1g IIC enters master mode and transmits START condition on the IIC bus Note The STA bit is cleared automatically after the START condition has been sent writing O to this bit has no effect ENAB Enable Og ThellC is disabled 1g IIC is enabled IEN Interrupt Enable Og The interrupt
126. Out of range comparator When a voltage out of range event occurs the event is latched into ADC_LORC LOREx sets an interrupt request through ADC_SR1and triggers other modules through internal connections with ORCEVENTO 4 Triggering of other modules is only made availble on ADC_CHO 4 User s Manual 21 57 V1 0 2010 02 ADC V2 1 Cinfineon Analog to Digital Converter The bit fields in these registers enables the out of range comparator in the ADC channel ADC_ENORC Enable Out Of Range Comparator Register D3 Reset Value 00 RMAP 0 PAGE 0 7 6 5 4 3 2 1 0 ENORC7 ENORC6 5 4 ENORC3 ENORC2 ENORC1 ENORCO rw rw rw rw rw rw rw rw Field Bits Type Description ENORCx x rw Enable Out of Range Comparator x x 0 7 This bit defines if the out of range comparator is enabled in the corresponding analog input channel Os Out of range comparator disabled 1 Out of range comparator enabled Note Bit 4 7 are only applicable for devices that have 8 ADC channels For channels not implemented these bits should be treated as Reserved bits of type r which returns 0 if read and should be written with 0 User s Manual 21 58 V1 0 2010 02 ADC V2 1 Cinfineon Analog to Digital Converter The bit fields in this register selects for detection of voltages higher or lower than Vddp at each input ADC channels that triggers the
127. P1 OD 91 P1 DATAIN P1 PUDEN P1 ALTSEL1 92 93 P2 PUDSEL 94 P2 DATAIN P2 PUDEN P2 EN PORT PAGE Page Register for PORT 8E Reset Value 00 RMAP 0 PAGE X 7 6 5 4 3 2 1 0 OP STNR 0 PAGE w w r rwh Field Bits Type Description PAGE 2 0 rwh Page Bits When written the value indicates the new page address When read the value indicates the currently active page addr 1 User s Manual 11 5 V1 0 2010 02 Cinfineon Parallel Ports Field Bits Type Description STNR 5 4 Storage Number This number indicates which storage bit field is the target of the operation defined by bit OP If OP 10g the contents of PAGE are saved in STx before being overwritten with the new value If OP 115 the contents of PAGE are overwritten by the contents of STx The value written to the bit positions of PAGE is ignored 00 STOis selected 01 ST1 is selected 10 ST2is selected 11 ST3is selected OP 7 6 Operation OX Manual page mode The value of STNR is ignored and PAGE is directly written 10 New page programming with automatic page saving The value written to the bit positions of PAGE is stored In parallel the former contents of PAGE are saved in the storage bit field STx indicated by STNR 11 A Automatic restore page action The value written to the bit positions PAGE is ignored and instead PAGE is overwritten by the contents of the storage bit field STx
128. PO 0 P1_ALTSEL1 P0 1 User s Manual CCU6 V4 0 20 9 V1 0 2010 02 Cinfineon XC82x Capture Compare Unit 6 CCU6 Table 20 2 CCU6 Pin Functions and Selection Pin Function Desciption Selected By P1 3 CC61 O Compare outputs for channel P1 ALTSELO P3 0 CC61 P1 ALTSEL1 P3 1 PO 1 CC61 1 PO ALTSELO P1 7 1g PO ALTSEL1 P1 1g P1 2 COUT61 0 P1 ALTSELO P2 0g P1 ALTSEL1 P2 7 1g PO 0 COUT61 1 PO ALTSELO PO 1 PO ALTSEL1 PO 1g P1 5 CC62 0 Compare outputs for channel P1 ALTSELO P5 0 CC62 P1 ALTSEL1 P5 1 0 2 CC62 1 PO ALTSELO P2 7 1g PO ALTSEL1 P2 7 1g P1 4 COUT62 0 P1 ALTSELO P4 0g P1 ALTSEL1 P4 1 P0 5 COUT6O2 1 PO ALTSELO P5 1 PO ALTSEL1 P5 1g PO ALTSEL2 P5 0g P1 2 COUT63 0 Compare outputs for channel P1 ALTSELO P2 1 CC63 P1 ALTSEL1 P2 1 P1 4 COUT63 1 P1 ALTSELO P4 1g P1 ALTSEL1 P4 1 The bit field PAGE of SCU PAGE register must be programmed before accessing the MODPISELS register MODPISEL3 Peripheral Input Select Register 3 EE Reset Value 00 RMAP 0 PAGE 3 7 6 5 4 3 2 1 0 IST13HR1 IST12HR1 CTRAPIS rw rw TW User s Manual 20 10 V1 0 2010 02 CCUG V4 0 Cinfineon XC82x Capture Compare Unit 6 CCU6 Field Bits Description CTRAPIS 1 0 rw CCU6 CTRAP Input Selection 00 CCU6 CTRAP Input Pin CTRAP 0 is selected 01 6 CT
129. Page Register Type w w r rw RMAP 0 PAGE 0 NMICON Reset 004 Bit Field 0 NMI NMI NMI NMI NMI NMI NMI NMI Control Register ECC VDDP OCDS FLASH OSC WDT CLK Type rw rw rw rw rw rw TW EXICONO Reset Bit Field EXINT3 EXINT2 EXINT1 EXINTO External Interrupt Control Register 0 Type iw Iw Iw Kw User s Manual 3 15 V1 0 2010 02 Memory Organization V 0 1 Infineon XC82x Memory Organization Table 3 3 SCU Register Overview cont d Addr Register Name Bit 7 6 5 4 3 2 1 0 F2y IRCONO Reset 004 Bit Fie 0 EXINT EXINT EXINT EXINT EXINT 0 Interrupt Request Register 0 6 5 4 3 2 Type rwh rwh rwh rwh rwh r F3y IRCON1 Reset 004 Bit Fie 0 ADCS ADCS RIR TIR EIR Interrupt Request Register 1 R1 RO Type r rwh rwh rwh rwh rwh Fay EXICON1 Reset Bit Fie 0 EXINT6 5 EXINT4 External Interrupt Control Register 1 Type r DN NN IRCON2 Reset 004 Bit Fie 0 CCU6 0 CCU6 Interrupt Request Register 2 SR1 SRO Type r rwh r rwh Fey Reset 004 Bit Fie 0 CCU6 0 CCU6 Interrupt Request Register 3 SR3 SR2 Type r rwh r rwh NMISR Reset 004 Bit Fie 0 FNMI FNMI FNMI FNMI FNMI FNMI FNMI NMI Status Register ECC VDDP VDDC OCDS FLASH OSC WDT CLK
130. RCR2 ADC CHINSR ADC_CRMR1 CDH RCR3 ADC QMRO CEH ADC VFCR ADC EVINFR ADC_QSRO CFH ADC ALRO ADC EVINCR ADC_QORO D2H ADC CORC ADC EVINSR ADC_QBUR0 ADC QINRO D3H ADC ETRCR User s Manual 21 90 V1 0 2010 02 ADC V2 1 Cinfineon 22 XC82x Boot ROM User Routines Boot ROM User Routines The Boot ROM User Routines provides a set of useful routines that can be called by user application These routines have been developed as part of the Boot ROM functionality and are provided to the user via a Boot ROM User Routine table User application would be able to call these routines provided in Table 22 1 Table 22 1 ROM User Routine table Address Name Description OxDFDE BR_FLASH_READ_MODE_ Check the Read Mode status of the STATUS selected Flash Bank OxDFE1 BR_GET_4 BYTES INFO Read the 4 bytes of Chip Identification Number and User Identification Number USER 4 BR PROG USER ID Program 4 bytes of USER ID Option 0 of BR FEATURE SETTING OxDFE4 BR CLKMODE SETTING Initialize CLKMODE Option 1 of BR FEATURE SETTING OxDFE7 BR AUTO BAUD Automatically detect UART Baud rate OxDFEA BR_UART_BSL Re enter UART BSL Mode OxDFED BR FLASH BACKGROUND Program code data in the background PROGRAM OxDFFO BR FLASH BACKGROUND Erase flash the background ERASE OxDFF3 BR FLASH BACKGROUND Abort Flash Erase background ERASE ABORT OxDFF6 BR FLASH PROGRAM Program code d
131. Request Pending Register 1 Type rwh rwh rwh rwh User s Manual 3 21 V1 0 2010 02 Memory Organization V 0 1 Infineon XC82x Memory Organization Table 3 5 ADC Register Overview cont d Addr Register Name Bit 7 6 5 4 3 2 1 0 CCu ADC CRMR1 Reset 004 Bit Field 0 LDEV CLRP SCAN ENSI ENTR 0 ENGT Conversion Request Mode ND Register 1 Type f w w rw rw rw r TW CDH ADC_QMRO Reset 004 BitField CEV TREV FLUS CLRV 0 ENTR 0 ENGT Queue Mode Register 0 H Type w w w w r rw r rw ADC_QSRO Reset 204 Bit Field 0 EV FILL Queue Status Register 0 rh rh rh ADC_QORO Reset 004 BitField EXTR ENSI RF V REQCHNR Queue 0 Register 0 Type rh rh rh rh rh D2u ADC QBURO Reset 004 BitField EXTR ENSI RF V REQCHNR Queue Backup Register 0 Type rh rh rh rh rh D2u ADC QINRO Reset 004 BitField EXTR ENSI RF 0 REQCHNR Queue Input Register 0 Type w w w r rh User s Manual 3 22 V1 0 2010 02 Memory Organization V 0 1 Infineon 3 4 5 XC82x 6 LEDSCU Registers Memory Organization The LEDSCU SFRs can be accessed in the standard memory area RMAP 0 Table 3 6 LEDSCU Register Overview Addr Register Name Bit 7 6 5 4 3 2 1 0 IRMAP 0 07 LTS_GLOBCTLO Reset 00 Bit Fie L
132. SSC EIR IRCON1 0 EIREN MODIEN O SSC_TIR TIR IRCON1 1 TIREN MODIEN 1 SSC_RIR 4 RIR IRCON1 2 RIREN MODIEN 2 EXINT2 EINT e 07 X a IRCONO 2 EXINT2 EXICONO 4 5 4 MDUSTATO IE MDUCON 7 MDU_1 ERR MDUSTAT 1 is MDUCON 7 See FLG eo CNTR3 Request flag is cleared by hardware IENO 7 S e q Figure 9 3 Interrupt Request Sources Part 3 User s Manual Interrupt System V 2 3 3 V1 0 2010 02 Cinfineon Interrupt System EINT3 x EXINT3 o IRCONO 3 EXINT3 EXICONO 6 7 Pages EINT4 oo EN IRCONO 4 EXINT3 EXICON1 0 1 arx 5 oot K Oe EN IRCONO 5 EXINTS EXICON1 2 3 SEES EINT6 oo X m 2 a IRCONO 6 EXINT6 EXICON1 4 5 RTC Compare CFRTC H Wakeup RTCON 6 ECRTC RTCON RTC SEC TIME SFRTC H e o RTCON 7 ESRTC RTCON 5 Y Bit addressable Request flag is cleared by hardware Figure 9 4 Interrupt Request Sources Part 4 User s Manual 9 5 V1 0 2010 02 I
133. Shadow Register for Timer 13 9B 00 Page 20 84 Low Modulation Control Registers MODCTRL Modulation Control Register Low FC 00 Page 20 98 MODCTRH Modulation Control Register High FD 00 Page 20 99 TRPCTRL Trap Control Register Low FE 00 20 100 TRPCTRH Trap Control Register High FF 00 Page 20 101 PSLR Passive State Level Register A64 00 Page 20 103 MCMOUTS Multi Channel Mode Output Shadow 9E 00 Page 20 106 L Register Low MCMOUTS Multi Channel Mode Output Shadow OF 00 Page 20 106 H Register High MCMOUTL Multi Channel Mode Output Register 9A 00 Page 20 107 Low MCMOUTH Multi Channel Mode Output Register 9B 00 Page 20 109 High MCMCTR _ Multi Channel Mode Control Register A7 00 Page 20 104 Interrupt Status and Node Registers ISL Interrupt Status Register Low 9C 00 Page 20 112 ISH Interrupt Status Register High 9D 00 20 113 ISSL Interrupt Status Set Register Low A4y 00 Page 20 116 ISSH Interrupt Status Set Register High A5 00 Page 20 116 ISRL Interrupt Status Reset Register Low 4 00 Page 20 118 ISRH Interrupt Status Reset Register High A5 00 Page 20 118 INPL Interrupt Node Pointer Register Low 9E 40 Page 20 124 INPH Interrupt Node Pointer Register High OF 39 Page 20 125 User s Manual 20 7 V1 0 2010 02 CCUG V4 0 82 Cinfineon Capture Compare Unit 6 CCU6 Table 20 1 CCU6 Module Register Summary cont d Short Name Description Offs
134. Source Handling A queued request source supports short conversion sequences of arbitrary channels contrary to a scan request source with a fixed conversion order for the enabled channels The programmed sequence is stored in a queue buffer based on a FIFO mechanism The requested channel numbers are entered via the queue input while queue stage 0 defines the channel to be converted next A conversion request is only issued to the request source arbiter if a valid entry is stored in queue stage 0 If the arbiter aborts a conversion triggered by a queued request source due to higher priority requests the corresponding conversion parameters are automatically saved in the backup stage This ensures that an aborted conversion is not lost but takes part in the next arbitration round before stage 0 The trigger and gating unit generates trigger events from the selected external outside the ADC trigger For example a timer unit can issue a request signal to synchronize conversions to PWM events Trigger events start a queued sequence and can be generated either via software or via the selected hardware triggers The occurrence of a trigger event is indicated by bit QSRx EV This flag is cleared when the corresponding conversion is started or by writing to bit QMRx CEV User s Manual 21 25 V1 0 2010 02 ADC V2 1 Cinfineon Analog to Digital Converter refill intermediate queue stages queue stage 0 request
135. Stop Timer 2 1g Start Timer 2 EXEN2 3 rw Timer 2 External Enable Control Og External events are disabled 1g X External events are enabled in Capture Reload Mode User s Manual Timer 2 V 1 2 14 13 V1 0 2010 02 Cinfineon XBox Timer 2 Field Bit Type Description EXF2 6 rwh Timer 2 External Flag In Capture Reload Mode this bit is set by hardware when a negative positive transition occurs at pin T2EX if bit EXEN2 1 This bit must be cleared by software Note When bit DCEN 1 in auto reload mode no interrupt request to the core is generated TF2 7 rwh Timer 2 Overflow Underflow Flag Set by a Timer 2 overflow underflow Must be cleared by software 0 5 4 r Reserved Returns 0 if read must be written with Register T2CONlis used to enable the external interrupt and the overflow interrupt T2 T2CON1 Timer 2 Control Register 1 6 Reset Value 03 RMAP 0 PAGE X 7 6 5 4 3 2 1 0 0 TF2EN EXF2EN r i rw rw Field Bit Type Description EXF2EN 0 rw External Interrupt Enable Og X External interrupt is disabled 1g X External interrupt is enabled TF2EN 1 rw Overflow Underflow Interrupt Enable Og X Overflow underflow interrupt is disabled 1g Overflow underflow interrupt is enabled 0 7 2 r Reserved Returns 0 if read should be written with 0 14 8 3 Timer 2 Reload Capture Register The RC2 register is used for a
136. Timer 2 Value 7 0 These bits indicate the current 16 bit timer value T2 T2H Timer 2 High Byte C54 Reset Value 00 RMAP 0 PAGE X 7 6 5 4 3 2 1 0 THL2 rwh Field Bit Type Description THL2 7 0 rwh Timer 2 Value 15 8 These bits indicate the current 16 bit timer value User s Manual Timer 2 V 1 2 14 16 V1 0 2010 02 Cinfineon Real Time Clock 15 Real Time Clock 15 1 Overview One of the XC82x s perpherials is the Real Time Clock RTC that once started can work independently of the state of the rest of the microcontroller There are two possible clock sources for this real time clock mainly the 75 KHz internal oscillator and an external clock input via RTCCLK pin Features Periodic Wake up Mode with 75 KHz internal oscillator e Wake up source during power down mode 15 2 System Information This section provides system information relevant to the Real Time Clock 15 2 1 Pinning RTC clock source can be either from on chip or an external source via a pin RTCCLK The RTCCLK pin assignment for XC82x is shown in Table 15 1 Table 15 1 RTC Pin Functions in XC82x Pin Function Desciption Selected By 5 RTCCLK RTC External Clock Input 15 2 2 Interrupt Events and Assignment Table 15 2 lists the interrupt event sources from the RTC and the corresponding event interrupt enable bit and flag bit Table 15 2 RTC Interrupt Events Event Event Interrupt
137. Type r rwh rwh rwh rwh rwh rwh rwh RMAP 0 PAGE 1 SDCON Reset 4 Bit Fie 0 VDDP VDDC VDDP VDDP VDDP VDDC Supply Detection Control TH TH BOBP BOA PW PW Regist easter Type r rh rh TW rw rw TW EFy PMCON1 Reset 004 Bit Fie LTS_ 0 MDU T2 CCU SSC ADC_ Power Mode Control Register 1 DIS DIS DIS DIS DIS DIS DIS Type TW rw r rw rw rw rw rw F2u PASSWD Reset 074 Bit Fie PASS PROT MODE Password Register ECT_S Type wh rh rw F34 Reset 01 Bit Fie 0 WK 0 PD PD EWS Power Mode Control Register 0 SEL MODE Type r rw r rw rwh TW OSC_CON Reset 004 Bit Fie 0 INT 0 75 48 RC OSC Control Register OSC_ OSC OSC OWD ST 2L 2L RST Type r rh ln rh rh rwh 1 Reset Bit Fie PRODID VERID Identity Regist entity Register Type r Fey WDTCON Reset 004 Bit Fie 0 WINB WDT 0 WDT WDT 0 Watchdog Timer Control EN PR EN RS Regist rw rh r rw rwh r F7y RSTCON Reset 00 Bit Fie SWRQ 0 SOFT WDT WKRS Reset Control Register RS RST Type rwh rwh rwh rwh RMAP 0 PAGE 3 User s Manual 3 16 V1 0 2010 02 Memory Organization V 0 1 Infineon XC82x Memory Organization Table 3 3 SCU Register Overview cont d Addr Register Name Bit 7 6 5 4 3 2 1 0 MODPI
138. V 2 7 1 Cinfineon Debug System HWBP1H Hardware Breakpoint 1 High Register written via HWBPDR Reset value 00 7 6 5 4 3 2 1 0 HWBP1H Field Bits Type Description HWBP1H 7 0 The High Byte from Compare Address HWBP1 HWBP2L Hardware Breakpoint 2 Low Register written via HWBPDR Reset value 00 7 6 5 4 3 2 1 0 HWBP2L Field Bits Type Description HWBP2L 7 0 The Low Byte from Compare Address HWBP2 HWBP2H Hardware Breakpoint 2 High Register written via HWBPDR Reset value 00 7 6 5 4 3 2 1 0 HWBP2H Field Bits Type Description HWBP2H 7 0 The High Byte from Compare Address HWBP2 User s Manual 10 18 V1 0 2010 02 OCDS V 2 7 1 Cinfineon Debug System HWBP3L Hardware Breakpoint 3 Low Register written via HWBPDR Reset value 00 7 6 5 4 3 2 1 0 HWBP3L Field Bits Type Description HWBP3L 7 0 The Low Byte from Compare Address HWBP3 HWBP3H Hardware Breakpoint 3 High Register written via HWBPDR Reset value 00 7 6 5 4 3 2 1 0 HWBP3H Field Bits Type Description HWBP3H 7 0 The High Byte from Compare Address HWBP3 10 8 3 Monitor Work Register MMWR2 be used for general pusposes when no debug session is possible if the device is not started in OCDS mode and no external device is connected MMWR2 Monitor Work Register 1 EC Reset value
139. Value 00 7 6 5 4 3 2 1 0 Pad Line7 Pad Line6 Pad Line5 Pad Line4 Pad Line3 Pad Line2 Pad Line1 Pad LineO rw rw rw rw rw rw rw rw Field Bits Description Pad Lined 0 rw Pad Line 0 of PadFlag OB Pad not touched 1B Pad touched Pad Line1 1 rw Pad Line 1 of PadFlag OB Pad not touched 1B Pad touched Pad Line2 2 rw Pad Line 2 of PadFlag OB Pad not touched 1B Pad touched User s Manual 23 27 V1 0 2010 02 ROM Library V0 5 Cinfineon ROM Library Field Bits Type Description Pad Line3 3 rw Pad Line 3 of PadFlag OB Pad not touched 1B Pad touched Pad Line4 4 rw Pad Line 4 of PadFlag OB Pad not touched 1B Pad touched Pad Line5 5 rw Pad Line 5 of PadFlag OB Pad not touched 1B Pad touched Pad Line6 6 rw Pad Line 6 of PadFlag OB Pad not touched 1B Pad touched Pad Line7 7 rw Pad Line 7 of PadFlag OB Pad not touched 1B Pad touched PadResult R PadResult Status IRAM address 0 2 Reset Value 00 7 6 5 4 3 2 1 0 Pad Line7 Pad Line6 Pad Line5 Pad Line4 Pad Line3 Pad Line2 Pad Line1 Pad LineO rw rw rw rw rw rw rw rw Field Bits Type Description Pad LineO 0 rw Pad Line 0 of PadResult OB Pad not valid 1B Pad valid Pad Line1 1 rw Pad Line 1 of PadResult OB Pad not valid 1B Pad valid Pad Line2 2 rw Pad
140. XC MDU ROM Library OxDFC9 C ULDIV XC MDU ROM Library OxDFCC FINDTOUCHEDPAD LEDTS ROM Library OxDFCF SET LDLINE CMP LEDTS ROM Library OxDFD2 INITEEPROM EEPROM Emulation ROM Library User s Manual ROM Library V0 5 23 1 V1 0 2010 02 T6 XC82x Infineon ROM Library Table 23 1 XC82x ROM Library function and its Address cont d Addr Name Description OxDFD5 FIXEEPROM EEPROM Emulation ROM Library OxDFD8 READEEPROM EEPROM Emulation ROM Library OxDFDB WRITEEEPROM EEPROM Emulation ROM Library 1 These functions are useful for space vector modulation as these functions can used as move accelerator i e executing without User s Manual ROM Library V0 5 waitstate 23 2 V1 0 2010 02 Cinfineon ROM Library 23 1 Fixed Point ROM Library The Fixed Point Library contains a list of routines that recite in ROM that are accessible to users The definitions and specifications of the library routines are explained in the following sections Execution Cycles in the tables does not include the calling instruction LCALL which requires 10 clock cycles if it is executed from FLASH or 8 clock cycles if it is executed from XRAM 23 1 1 P Controller Routine The P controller routine is the implementation of a proportional control algorithm defined as 23 1 Y k G x Kp x X k where Y k P controller output G Gain factor of16 or 256
141. a result is less important than its range As long as the measured values are within their defined valid range no CPU action is required A channel event should be generated only if the conversion result is outside the valid range to indicate a critical condition over temperature loss of pressure etc The CPU load is minimized if the conversions of the analog input signals to be monitored are part of an auto scan sequence autonomously triggered on a regular time base Under normal conditions the CPU load here is zero Note In the case of an over current protection the channel event can be used to disable PWM generation to reduce the current in the XC82x an interrupt output line of the ADC module is connected to a corresponding input of the CCU6x units to allow fast reactions without CPU intervention Boundary Flag Control The limit checking mechanism can be configured to automatically control the boundary flags A boundary flag will be set when the conversions result is within area IIl and will be cleared when the conversion result is within area I Boundary 1 BoundaryO Flag BFx MC BFLAG Figure 21 17 Boundary Flag Control The difference between the two boundary values defines a hysterisis for setting clearing the boundary flags Using this feature on three channels that onitor linear hall elements can produce signals to feed the three hall position inputs of a CCU6x unit User s Manual 21 53 V1 0
142. and ground A finger approaching this pad will alter the capacitance To measure this change the arrangement is such that together with a resistor and the I O pad we have an RC oscillator The oscillations are counted in an 8 bit counter over a pre determined period essentially forming a frequency counter This frequency counting LTS_TSCTR happens for each pad line User can determine the number of samples to accumulate to form a total frequency counter TOTAL TSCTRL H The function FINDTOUCHEDPAD needed for successfully detecting if a pad has been touched consists the following features Find Average Find LowTrip Find which pad s is are touched if any Generate status flag s Figure 23 6 gives an overview of this function while Figure 23 7 shows the respective SFR settings used for this function P PadFlag0 b P PadFlagl Averagel gt total TSCTR Ed Lp Average p gt PadFlag3 H gt Average3 Lowlrip gt PadFlag4 E subtraction Lp PadFlags gt Averaged L gt Averages Y X Subtraction ml I PadFlag6 b P PadFlag7 P Average gt increment PADT Dm rrr gy accumulate low pass filter m 0 Y K T Y 1 Mc TSCTRVAL Figure 23 6 FINDTOUCHEDPAD Function Overview User s Manual 23 21 V1 0 2010 0
143. and the IFLG bit must be cleared to allow the transfer to continue When the STOP condition or a repeated START condition is detected after the acknowledge bit then the IFLG bit is set and the STAT register will contain status code 0 User s Manual 17 13 V1 0 2010 02 V1 1 Cinfineon Inter IC Bus If the bit is cleared to 0 during a transfer the IIC will transmit a not acknowledge bit high level on SDA after the next byte is received and set the IFLG bit The STAT register will contain status code 88 or 98 if slave receive mode was entered with the general call address When the IFLG bit has been cleared to 0 the IIC will return to idle state status code F8 User s Manual 17 14 V1 0 2010 02 V1 1 Cinfineon Inter IC Bus 17 9 Registers Description The IIC Special Function Registers are accessed from the standard non mapped SFR area Table 17 11 lists the IIC registers with their addresses Table 17 11 Register Map Address Register Description DA ADDR Slave Address Register DB DATA Data Byte Register DC IIC_CNTR Control Register DD STAT Status Register read only DD BRCR Clock Control Register write only DE ADDRX Extended Slave Address Register DF IIC_SRST Software Reset Register User s Manual 17 15 V1 0 2010 02 IIC V1 1 Cinfineon Inter IC Bus 17 9 1 Slave Address Registers T
144. be cleared by software The auto reload mode is further classified into two categories depending upon the DCEN control bit in register 2 14 4 1 Up Down Count Disabled If DCEN 0 the up down count selection is disabled The timer therefore functions as a pure up counting timer only The operational block diagram is shown in Figure 14 1 If the T2CON register bit EXEN2 0 the timer starts to count up to a maximum of FFFF once the timer is started by setting the bit TR2 in register T2CON to 1 Upon overflow bit TF2 is set and the timer register is reloaded with the 16 bit reload value of the RC2 register This reload value is chosen by software prior to the occurrence of an overflow condition A fresh count sequence is started and the timer counts up from this reload value as in the previous count sequence If EXEN2 1 the timer counts up to a maximum of FFFF once TR2 is set A 16 bit reload of the timer registers from register RC2 is triggered either by an overflow condition or by a negative positive edge chosen by the bit EDGESEL in register T2MOD at input pin T2EX If an overflow caused the reload the overflow flag TF2 is set If a negative positive transition at pin T2EX caused the reload bit EXF2 in register T2CON is set In either case an interrupt is generated to the core if the related interrupt enable bit EXF2EN TF2EN in register T2CON1 is enabled and the timer proceeds to its next count sequence The EXF2 flag
145. bit cannot be written directly For more information on Protection Scheme see Section 3 4 4 PDMODE 2 rw Power Down Mode Select 0 Power down mode 1 is selected 1 Power down mode 2 is selected WKSEL 4 rw Wake up Reset Select Bit 0 Wake up without reset 1 Wake up with reset 0 3 r Reserved 7 5 Returns 0 if read should be written with 0 User s Manual 7 23 V1 0 2010 02 Cinfineon XC82x PCON Note This register is located within XC800 core Power Control Register Not bitaddressable 87 RMAP 0 PAGE X System Control Unit Reset Value 00 7 6 5 4 3 2 1 0 SMOD 0 GF1 GFO 0 IDLE rw r rw rw r rw Field Bits Description IDLE 0 rw Idle Mode Enable 0 Do not enter Idle Mode 1 Enter Idle Mode User s Manual 7 24 V1 0 2010 02 Cinfineon System Control Unit 7 5 SCU Register Mapping The system control SFRs are used to control the overall system functionalities such as interrupts variable baud rate generation clock management bit protection scheme and oscillator The SFRs are located in the standard memory area RMAP 0 and are organized into 8 pages The SCU PAGE register is located at F14 It contains the page value and page control information SCU PAGE Page Register for SCU F1 Reset Value 00 RMAP 0 PAGE X 7 6 5 4 3 2 1 0 OP STNR 0 PAGE w w r rwh Field Bits Type Descri
146. boot mode Default mode is the UART BSL Mode BMI is introduced to detect if the BMI value is valid Thus BMI value is valid when BMI BMI 1 0 Table 5 1 shows the BMI value required for each mode Table 5 1 Boot Mode Index Boot Mode BMI BMI UART BSL Mode 00 FF UART BSL Mode 00 00 User Mode Productive 10 EF User Mode Diagnostic with SPD pin SPD 0 50 AF User Mode Diagnostic with SPD pin SPD 1 524 AD OCDS Mode with SPD pin SPD 0 60 OCDS Mode with SPD SPD_1 62 9D Reserved Others Others 1 SPD Single Pin DAP 2 UART BSL Mode can be entered when BMI is 00 and is either 00 or FF The BMI and BMI are part of the User Identification USER_ID USER_ID is a 4 byte data that contains user s specific information see Section 5 1 Beside the BMI the user can also select either the 8 MHz active mode or 24 MHz active mode by programming the USER_ID The mode selection is performed in the startup firmware before the start of the user code Once the device is in user mode productive changing of the BMI value to enter another boot mode could be done by a specific code embedded in the user code This code should only be executed under a defined user condition In this specific code user can use one of the following instructions to change the BMI value LJMP to user routine BR_UART_BSL to enter BSL mode using BSL mode 6 LCALL the user routine BR PROG USER
147. breakpoint into NMI servicing routine is taken but single stepping is not possible afterwards If a step is requested the servicing routine will run continuously and monitor mode will be invoked again only after a RETI is executed Hardware breakpoints and software breakpoints proceed as normal while CPU is in NMI mode 10 8 Registers Description The OCDS Special Function Registers are accessed from the mapped SFR area Table 10 5 lists the direct addressable SFRs and corresponding address User s Manual 10 13 V1 0 2010 02 OCDS V 2 7 1 Cinfineon Debug System Table 10 5 Register Map Direct Addressable Address Register MMICR F6 HWBPSR F7 HWBPDR EC MMWR2 Additionally there are Hardware Breakpoint Registers which are indirect accessible via HWBPSR register select and HWBPDR data refer to Table 10 6 and Table 10 7 for more information look at Section 10 8 Table 10 6 Hardware Breakpoint Registers Indirect Accessed Register Description HWBPOL Hardware Breakpoint O Low Register HWBPOH Hardware Breakpoint O High Register HWBP1L Hardware Breakpoint 1 Low Register HWBP1H Hardware Breakpoint 1 High Register HWBP2L Hardware Breakpoint 2 Low Register HWBP2H Hardware Breakpoint 2 High Register HWBP3L Hardware Breakpoint 3 Low Register HWBP3H Hardware Breakpoint 3 High Register Table 10 7 HWBPSR 3 0 Selecting Hardware Breakpoint Registers
148. by the T13 state selection with an individual enable bit T13MODENy per output signal y 0 2 4 for outputs CC6x and y 1 3 5 for outputs COUT6x A multi channel output signal MCMPy y 0 2 4 for outputs CC6x 1 3 5 for outputs COUT6x with a common enable bit MCMEN The trap state TRPS with an individual enable bit TRPENy per output signal y 0 2 4 for outputs CC6x and y 1 3 5 for outputs COUT6x If one of the modulation input signals CC6x O COUT6x O CC63 O or MCMPy of an output modulation block is enabled and is at passive state the modulated is also in passive state regardless of the state of the other signals that are enabled Only if all enabled signals are in active state the modulated output shows an active state If no modulation input is enabled the output is in passive state If the Trap State is active TRPS 1 then the outputs that are enabled for the trap signal by TRPENy 1 are set to the passive state The output of each of the modulation control blocks is connected to a level select block that is configured by register PSLR It offers the option to determine the actual output level of a pin depending on the state of the output line decoupling of active passive state and output polarity as specified by the Passive State Select bit PSLy If the modulated output signal is in the passive state the level specified directly by PSLy is output If itis in the active state the inverted level of PS
149. channel to be converted in the case of concurrent requests from multiple sources according to the application requirements A disabled or unused arbitration slot is considered empty and does not take part in the arbitration After reset all slots are disabled and must be enabled register ADC_PRAR to take part in the arbitration process Figure 21 10 summarizes the arbitration sequence An arbitration round consists of one arbitration slot for each available request source The synchronization source is always evaluated in the last slot and has a higher priority than all other sources Additional arbitration slots can be inserted to adjust the timing to other products not required for the XC82x At the end of each arbitration round the arbiter has determined the highest priority conversion request If a conversion is started in an arbitration round this arbitration round does not deliver an arbitration winner In the XC82x the following request sources are available Arbitration slot 0 4 stage sequential source 4 stage sequences in arbitrary order Arbitration slot 1 4 8 channel scan source sequences in defined order Last arbitration slot Synchronization source synchronized conversion requests another ADC kernel always handled with the highest priority in a synchronization slave kernel arbitration round arbitration winner arbitration arbitration arbitration arbitration found slot 0 slot 1 slot 2 slot
150. cleared 116 reserved 0 5 3 r reserved 7 returns 0 if read should be written with 0 1 This bit field is contained in the Compare State Modification Register High User s Manual 20 53 V1 0 2010 02 CCU6 V4 0 Cinfineon Capture Compare Unit 6 CCU6 CMPMODIFH Compare State Modification Register High 7 Reset Value 00 RMAP 0 PAGE 0 7 6 5 4 3 2 1 0 0 MCC63R 0 MCC62R MCC61R MCC60R r w 0 rw w w Field Bits Type Description MCC60R 0 Capture Compare Status Modification Bits MCC61R 1 These bits are used to bits to set 6 5 or to MCC62R 2 clear MCC6xR the corresponding bits CC6xST by MCC63R 6 SW This feature allows the user to individually change the status of the output lines by SW e g when the corresponding compare timer is stopped This allows a bit manipulation of CC6xST bits by a single data write action The following functionality of a write access to bits concerning the same capture compare state bit is provided MCC6xR MCC6xS 00 Bit CC6xST is not changed 01 Bit CC6xST is set 10 Bit CC6xST is cleared 11 reserved 0 5 3 r reserved 7 returns 0 if read should be written with 0 1 This bit field is contained in the Compare State Modification Register Low User s Manual 20 54 V1 0 2010 02 CCU6 V4 0 Cinfineon Capture Compare Unit 6 CCU6 20 3 9 2 T12 Mode Control Register Register T12
151. compare parameters setting for oscillation window respectively Examples of input parameters are also shown in Figure 23 4 and Figure 23 5 For flexibility users can choose common compare parameter for all PADTx or choose different compare parameters for individual PADTx This is also provided to give better sensitivity for respective pads If CMP_OPTION at address R5 is programmed as OxFF it means that common compare value is selected Then the common compare parameter is read at IRAM address R5 1 If CMP_OPTION is not programmed as OxFF then different compare parameters for individual pads are selected In preparing compare value for Touch sense quantization effect is taken into consideration in the function The respective compare value will be XRL with 2 4 8 16 etc and finally updating the final value to sfr LTS COMPARE Quantization effect gives better sensitivity and is transparent to users as all are achieved by the function Table 23 11 Specifications of Setting LDLINE amp Common COMPARE LEDTS Subroutine SET_LDLINE_CMP Address DFCF Input R7 of current Register Bank Start IRAM address of LDLINE parameters R5 of current Register Bank Start IRAM address of COMPARE parameters LDLINE parameters programmed into IRAM R7 R7 1 etc LDLINE parameter for COLA for Touch sense R7 1 LDLINE parameter for COLO R7 y LDLINE parameter for COL y 1 COMPARE parameters programmed into IRAM R5
152. counter automatic reset 1g Enable TS counter automatic reset to 00 on new pad turn Triggered on compare match in time slice TSCTROVF 7 rwh TS Counter Overflow Indication This bit indicates whether a TS counter overflow has occurred This bit is cleared on new pad turn triggered on compare match overflow has occurred 1g TS counter has overflowed at least once 1 This bit can only be modified when bit CLK PS 0 LTS TSVAL Touch Sense Counter Value D9 Reset Value 00 RMAP 0 PAGE X 7 6 5 4 3 2 1 0 TSCTRVAL rwh Field Bits Type Description TSCTRVAL 7 0 rwh TS Counter Value This shows the actual TS counter value It can only be written when no pad turn is active This counter may be enabled for automatic reset on the start of a new pad turn User s Manual 19 27 V1 0 2010 02 LEDTSCU V 1 2 1 Cinfineon Capture Compare Unit 6 CCU6 20 Capture Compare Unit 6 CCU6 The CCU6 is a high resolution 16 bit capture and compare unit with application specific modes mainly for AC drive control Special operating modes support the control of Brushless DC motors using Hall sensors or Back EMF detection Furthermore block commutation and control mechanisms for multi phase machines are supported It also supports inputs to start several timers synchronously an important feature in devices with several CCU6 modules This chapter is structured as
153. follows Introduction see Section 20 1 including the register overview see Section 20 1 3 System information see Section 20 2 Operating T12 see Section 20 3 including T12 related registers see Section 20 3 8 and capture compare control registers see Section 20 3 9 Operating T13 see Section 20 4 including T13 related registers see Section 20 4 6 Trap handling see Section 20 5 Multi Channel mode see Section 20 6 Hall sensor mode see Section 20 7 Modulation control registers see Section 20 8 Interrupt handling see Section 20 9 including interrupt registers see Section 20 9 2 General module operation see Section 20 10 including general registers see Section 20 10 2 20 1 Introduction The CCUG unit is made up of a Timer T12 Block with three capture compare channels and a Timer T13 Block with one compare channel The T12 channels can independently generate PWM signals or accept capture triggers or they can jointly generate control signal patterns to drive AC motors or inverters A rich set of status bits synchronized updating of parameter values via shadow registers and flexible generation of interrupt request signals provide means for efficient software control Note The capture compare module itself is named CCU6 capture compare unit 6 A capture compare channel inside this module is named CC6x User s Manual 20 1 V1 0 2010 02 CCU6 V4 0 Cinfineon Capture Compare Unit 6
154. g SCON O gt 21 Lleol UART w S Transmit SCON q of ed ox d L 1 0 c EINTO e se oH XH a TCON O EXINTO EXICONO 0 1 Lb ox e IE1 EINT1 on kt CONS oH A Tay TCON 2 EXINT1 2 3 Bit addressable 4 Request flag is cleared by hardware Figure 9 1 Interrupt Request Sources Part 1 User s Manual 9 2 V1 0 2010 02 Interrupt System V 2 3 3 Infineon XC82x Interrupt System Timer 2 _ TF2 6 Overflow T2 T2CON7 E Xx T2 T2CON1 MEX 2 8 2 EN x EXEN2 72 2 6 expen T2 T2CON 3 T2 T2CON1 0 EL T2 T2MOD 5 End f lgorsyy Synch Byte LINST 4 gt 1 Synch Byte ERRSYN SYNEN Error LINST 5 LINST 6 ADC Service Request 0 ADCSRO IRCONI 3 ADC Service Request 1 ADCSR1 TRCONT4 Y Bit addressable 4 Request flag is cleared by hardware 5 oc Figure 9 2 Interrupt Request Sources Part 2 User s Manual 9 3 Interrupt System V 2 3 3 V1 0 2010 02 Cinfineon XC82x Interrupt System Bit addressable
155. gt Core Block Diagram Figure 2 1 800 Core Block Diagram The arithmetic section of the processor performs extensive data manipulation and consists of the arithmetic logic unit ALU A register B register and PSW register The ALU accepts 8 bit data words from one or two sources and generates an 8 bit result under the control of the instruction decoder The ALU performs both arithmetic and logic operations Arithmetic operations include add substract multiply divide increment decrement BCD decimal add adjust and compare Logic operations include AND OR Exclusive OR complement and rotate right left or swap nibble left four Also included is a Boolean unit performing the bit operations as set clear complement jump if set jump if not set jump if set and clear and move to from carry The ALU can perform the bit operations of logical AND or logical OR between any addressable bit or its complement and the carry flag and place the new result in the carry flag The program control section controls the sequence in which the instructions stored in program memory are executed The 16 bit program counter PC holds the address of the next instruction to be executed The conditional branch logic enables internal and external events to the processor to cause a change in the program execution sequence User s Manual 2 2 V1 0 2010 02 XC800 Core V 1 0 2 Cinfineon XC800 Core The access control unit is responsib
156. have 8 ADC channels For channels not implemented these bits should be treated as Reserved bits of type f which returns 0 if read and should be written with DRC rh Data Reduction Counter This bit field indicates how many conversion results have still to be accumulated to generate the final result for data reduction Og final result is available in the result register The valid flag is automatically set when this bit field is set to 0 1g 1 more conversion result must be added to obtain the final result in the result register The valid flag is automatically reset when this bit field is set to 1 VF rh Valid Flag for Result Register x This bit indicates that the contents of the result register x are valid Og result register x does not contain valid data 1g result register x contains valid data RESULT 2 0 7 5 rh Conversion Result This bit field contains the conversion result or the result of the data reduction filter RESRxH x 0 2 Result Register x High View Acc 10 bit ist conv CB x 2 Reset Value 00 ADC RESR3H Result Register 3 High View Acc 10 bit 1st conv D3 Reset Value 00 RMAP 0 PAGE 2 7 6 5 4 3 2 1 0 0 RESULT 9 3 r rh User s Manual 21 73 V1 0 2010 02 ADC V2 1 Cinfineon XBox Analog to Digital Converter Field Bits Type Description RESULT 9 3 6 0 rh Conversion Resu
157. in the following steps STEP 1 Initialize serial interface for reception and timer for baud rate measurement STEP 2 Wait for SYN Break 13 bits low and SYN Byte 0x55 from host STEP 3 Synchronize the baud rate to the host STEP 4 Acquire UART INIT ID or 0x55 to determine single pin or dual pins UART and initialize pins STEP 5 Send Acknowledge byte 55H to the host STEP 6 Enter Phase ll 6 1 1 General Description The baud rate detection feature provides the capability to detect the baud rate using Timer 2 Initialization consists of Serial port of the microcontroller set to Mode 1 8 bit UART variable baud rate for communication Baudrate selection for detection BCON BGSEL is defined as 00 left as default Capture Timer 2 data register contents on negative transition at pin T2EX Timer 2 external events are enabled EXF2 flag is set when a negative transition occurs at pin T2EX 4 T2PRE 010 The auto baud for UART BSL consists of the SYN Break 13 Bit time low SYN byte 55 e UART INIT ID The Break is used to signal the beginning of a new frame and must be at least 13 bits of dominant value When negative transition is detected at pin T2EX at the beginning of Break the Timer 2 External Start Enable bit T2MOD T2RHEN is set This will then automatically start Timer 2 at the next negative transition of pin T2EX Finally the End of SYN Byte Flag FDCON EOFSYN
158. indicated by STNR 0 3 r Reserved Returns 0 if read should be written with 0 11 1 1 2 Register Overview The individual control and data bits of each parallel port are implemented in a number of 8 bit registers Bits with the same meaning and function are assembled together in the same register The registers configure and use the port as general purpose I O or alternate function input output For port P1 and P2 not all the registers in Table 11 2 are implemented The availability and definition of registers specific to each port is defined in Section 11 2 to Section 11 4 This section provides only an overview of the different port registers User s Manual 11 6 V1 0 2010 02 82 Cinfineon Parallel Ports Table 11 2 Port Registers Register Short Name Register Long Name Description Px_DATAOUT Port x Data Out Register Page 11 7 Px_DATAIN Port x Data In Register Page 11 8 Px_OD Port x Open Drain Control Register Page 11 8 Px_PUDSEL Port x Pull Up Pull Down Select Register Page 11 9 Px_PUDEN Port x Pull Up Pull Down Enable Register Page 11 9 Px_ALTSELO Port x Alternate Select Register 0 Page 11 10 Px_ALTSEL1 Port x Alternate Select Register 1 Page 11 10 Px_ALTSEL2 Port x Alternate Select Register 2 Page 11 10 Px_EN Port x Input Control Register Page 11 10 Note Not all the registers are implemented for each port Port Data Out Register If a port pin is use
159. is disabled 1g interrupt is enabled User s Manual V1 1 17 19 V1 0 2010 02 Cinfineon Inter IC Bus Field Bits Type Description 0 1 0 Reserved Returns 0 if read should be written with 0 17 9 4 Status Register The read only STAT register stores the 5 bit status code of the IIC 5 Status Register Read Mode Reset Value F8 RMAP 0 PAGE X 7 6 5 4 3 2 1 0 STAT 0 r r Field Bits Type Description STAT 7 3 r Status Code 5 bit status code see Table 17 4 0 2 0 r Reserved Returns 0 if read should be written with 0 User s Manual 17 20 V1 0 2010 02 V1 1 Cinfineon neers Inter IC Bus 17 9 5 Baud Rate Control Register The write only BRCR register controls the sampling frequency of the IIC and the baud rate of the IIC in master mode BRCR Baud Rate Control Register Write Mode DD Reset Value 00 RMAP 0 PAGE X 7 6 5 4 3 2 1 0 0 BRP PREDIV w w w Field Bits Type Description PREDIV 2 0 w Predivider for Baud Rate Generation 000 Predivider factor of 1 is used 001 Predivider factor of 2 is used 010 Predivider factor of 4 is used 011 Predivider factor of 8 is used 100 Predivider factor of 16 is used 101 Predivider factor of 32 is used 110 Predivider factor of 64 is used 111 Predivider factor of 128 is used BRP 6 3 w Baud Rat
160. is programmed Stack size required 2 Resource used destroyed A RO R1 R2 R3 R4 1 Depending how many LED s and Touch sense pad turn s is are enabled y no of LED s enabled z no of PADTx enabled User s Manual ROM Library V0 5 23 18 V1 0 2010 02 Cinfineon ROM Library Eg No LED 8 TS PAD enabled Eg No LED 8 TS PAD enabled Eg 2 LED 2 TS PAD enabled Eg 2 LED 2 TS PAD enabled TS PADTx has different compare TS PADTx has common TS PADTx has different TS PADTx has common value compare value compare value compare value LDLINE O R7 1 LDLINEQ R7 1 LDLINE 1 R7 2 LDLINE R7 2 R5 3 COMPARE 0 R5 1 COMPARE R5 1 Bea R5 4 COMPARE 1 R5 2 COMPARE 1 R5 2 Figure 23 4 Input Parameters Examples 1 LED amp TS enabled User s Manual 23 19 V1 0 2010 02 ROM Library V0 5 Infineon XC82x ROM Library Eg 4 LED 5 TS PAD enabled Eg 4 LED 5 TS PAD enabled Eg 7 LED 8 TS PAD enabled 7 LED 8 TS PAD enabled TS PADTx has different compare value R7 LDLINE 0 R7 1 LDLINE 1 R7 2 LDLINE 2 R7 3 LDLINE 3 R7 4 R5 COMPARE 0 R541 COMPARE 1 R5 2 COMPARE 2 R5 3 COMPARE 3 R5 4 R5 5 R5 6 R5 7 R5 8 R5 9 LDLINE 0 LDLINE 1 LDLINE 2
161. is provided for the hardware reset Bit fields and bits in registers are generally referenced as Register name Bit field or Register name Bit Most of the register names contain a module name prefix separated by an underscore character from the actual register name In the example of SSC_CON SSC is the module name prefix and is the actual register name Variables that are used to represent sets of processing units or registers appear in mixed case type For example the register name CC6xR refers to multiple CC6xR registers with the variable x x 0 1 2 The bounds of the variables are always specified where the register expression is first used e g x 0 2 and is repeated as needed The default radix is decimal Hexadecimal constants have a suffix with the subscript letter e g CO Binary constants have a suffix with the subscript letter B e g 118 When the extents of register fields groups of signals or groups of pins are collectively named in the body of the document they are represented as NAME A B which defines a range from B to A for the named group Individual bits signals or pins are represented as NAME C with the range of the variable provided in the text e g CFG 2 0 and TOS 0 Units are abbreviated as follows MHz Megahertz ps Microseconds kBaud kbit 1000 characters bits per second MB
162. it is not allowed to enter the other boot modes without an erase of the BMI by the user code Therefore boot options that load and execute external code will be blocked and only user code starting from address 0000 can be executed 3 4 Special Function Registers The Special Function Registers SFRs occupy direct internal data memory space in the range 80 to FF All registers except the program counter reside in the SFR area The SFRs include pointers and registers that provide an interface between the CPU and the on chip peripherals As the 128 SFR range is less than the total number of registers required address extension mechanisms are required to increase the number of addressable SFRs The address extension mechanisms include Mapping Paging 3 4 1 Address Extension by Mapping Address extension is performed at the system level by mapping The SFR area is extended into two portions the standard non mapped SFR area and the mapped SFR area Each portion supports the same address range 80 to FF bringing the number of addressable SFRs to 256 The extended address range is not directly controlled by the CPU instruction itself but is derived from bit RMAP in the system control register SYSCONO at address 8F To access SFRs in the mapped area bit RMAP in SFR SYSCONO must be set However the SFRs in the standard area can be accessed by clearing bit RMAP Figure 3 2 shows how the SFR area can be selected As long as bit R
163. kHz to 13 9 kHz Each BGSEL setting supports a range of baud rate for detection If the baud rate used is outside the defined range the baud rate may not be detected correctly When fok 24 MHz the baud rate range between 1 4 kHz to 333 3 kHz can be detected The following examples serve as a guide to select BGSEL value Ifthe baud rate falls in the range of 1 4 kHz to 2 8 kHz selected BGSEL value is 11g If the baud rate falls in the range of 2 8 kHz to 5 5 kHz selected BGSEL value is 10g Ifthe baud rate falls in the range of 5 5 kHz to 11 kHz selected BGSEL value is 015 Ifthe baud rate falls in the range of 11 kHz to 333 3 kHz selected BGSEL value is 00g If the baud rate is 20 kHz the possible values of BGSEL that can be selected are 00g 015 10 and 115 However it is advisable to select 00g for better detection accuracy The baud rate can also be detected when f 8 MHz for which the baud rate range that can be detected is between 0 46 kHz to 111 1 kHz User s Manual 16 17 V1 0 2010 02 UART V 1 6 Cinfineon UART 16 6 2 4 LIN Baud Rate Detection The baud rate detection for LIN is shown in Figure 16 8 the Header LIN frame consists of the SYN Break 13 bit times low SYN byte 55 Protected ID field 1st negative transition T2 automatically Last captured value of T2 EOFSYN btt is set set T2
164. mode Note In XC82x there are only Mode 1 and 3 Mode 0 and Mode 2 are not available 15 5 1 Mode 1 Periodic Wake up Mode with 75 KHz Oscillator Clock Figure 15 1 shows Mode 1 of the real time clock It is the default mode upon power on reset In this mode the real time clock consists of a 41 bit general purposes timer The 75 kHz oscillator is the input clock to the timer Before the real time clock starts to run CNT register of the real time clock can be written with any values The value written is used as an initial value for the real time clock timer when it is started by setting bit RTCC in the RTCON register to 1 This bit also enables the input clock into the real time clock timer CNT register is protected by the bit protection scheme as described in the SCU chapter The initial count value can only be updated when the protection scheme is being disabled in the stop mode RTCC 0 The real time clock s lower 9 bits which serve as a prescaler into the 32 bit counters CNT are set to an initial value of 0000000005 when the RTC starts to run Real Time Clock Counter Y v Y Y 5 CNO gt 1 H CNT2 Y CNT3 Reset Timer Bit 0 Bt 7 8 Bt 15 Bi 16 Bt23 Bit 24 Bt 31 RTCC atcct Vj wrecr ee 32 bits Comparator Interrupt TY TY TY TY Request
165. mode 3 the Timer 1 control bits TR1 TF1 and ET1 are reserved for THO see Section 13 4 4 External Control In addition to pure software control the timers can also be enabled or disabled through external port control When external port control is used SFR EXICONO must first be configured to bypass the edge detection circuitry for EXINTx to allow direct feed through When the timer is enabled TCON TRx 1 and TMOD GATEx is set the respective timer will only run if the core external interrupt EXINTx 1 This facilitates pulse width measurements However this is not applicable for Timer 1 in mode 3 If TMOD GATEx is cleared the timer reverts to pure software control User s Manual 13 3 V1 0 2010 02 Timer 0 and 1 V1 0 Cinfineon 0 1 13 4 Timers 0 and 1 are fully compatible can be configured in four different operating modes as shown in Table 13 3 The bit field TxM in register TMOD selects the operating mode to be used for each timer In modes 0 1 and 2 the two timers operate independently but in mode 3 their functions are specialized Table 13 3 Timer 0 and Timer 1 Modes Mode Operation 0 13 bit timer counter The timer is essentially an 8 bit counter with a divide by 32 prescaler This mode is included solely for compatibility with Intel 8048 devices 1 16 bit timer counter The timer registers TLx and THx are concatenated to form a 16
166. modulation of the corresponding output signal by a T12 PWM pattern is disabled 1g modulation of the corresponding output signal by a T12 PWM pattern is enabled MCMEN 7 rw Multi Channel Mode Enable Og modulation of the corresponding output signal by a multi channel pattern according to bit field MCMOUT is disabled 1g modulation of the corresponding output signal by a multi channel pattern according to bit field MCMOUT is enabled 0 6 r reserved returns 0 if read should be written with 0 User s Manual 20 98 V1 0 2010 02 CCU6 V4 0 Cinfineon Capture Compare Unit 6 CCU6 MODCTRH Modulation Control Register High FD Reset Value 00 RMAP 0 PAGE 2 7 6 5 4 3 2 1 0 ECT130 0 T13MODEN rw r rw Field Bits Type Description T13MODEN 5 0 rw T13 Modulation Enable These bits enable the modulation of the corresponding output signal by the PWM pattern CC63 O generated by timer T13 T13MODENO MODCTR 8 for output CC60 T13MODEN1 MODCTR 9 for output COUT60 T13MODEN 2 MODCTR 10 for output CC61 T13MODEN3 MODCTR 11 for output COUT61 T13MODEN4 MODCTR 12 for output CC62 T13MODEN5 MODCTR 13 for output COUT62 Og modulation of the corresponding output signal by a T13 PWM pattern is disabled 1g modulation of the corresponding output signal by a T13 PWM pattern is enabled ECT130 7 rw Enable Compare Timer T13 Output Og outp
167. of shifts to be performed during a shift operation SLR 5 rw Shift Direction Os Selects shift left operation 1g X Selects shift right operation 0 7 6 rw Reserved Should be written with 0 Returns undefined data if read MDU_MR4 Shift Output Control Register B6 Reset Value 00 RMAP 0 PAGE X 7 6 5 4 3 2 1 0 0 SCTR rh rh Field Bits Type Description SCTR 4 0 rw Shift Counter After a normalize operation SCTR contains the number of normalizing shifts performed 0 7 5 rh Reserved Returns undefined data if read User s Manual MDU V2 9 12 11 V1 0 2010 02 Cinfineon Multiplication Division Unit 12 5 2 Control Register Register MDUCON contains control bits that select and start the type of operation to be performed MDU_MDUCON MDU Control Register B1 Reset Value 00 RMAP 0 PAGE X 7 6 5 4 3 2 1 0 IE IR RSEL START OPCODE rw rw rw rwh rw Field Bits Type Description OPCODE 3 0 rw Operation Code 0000 Unsigned 16 bit Multiplication 0001 Unsigned 16 bit 16 bit Division 0010 Unsigned 32 bit 16 bit Division 0011 32 bit Logical Shift L R 0100 Signed 16 bit Multiplication 0101 Signed 16 bit 16 bit Division 0110 Signed 32 bit 16 bit Division 0111 32 bit Arithmetic Shift L R 1000 32 bit Normalize 1001 Signed 16 bit Multiplication with Single Left Shift 1010 Signed 32 bit 16 bit Division with Single Right Shift Others Reser
168. of LEDTS counter which indicates the start of a new time slice Figure 19 2 shows the LED function control circuit which also provides the pad oscillator enable control The clock source for the control circuit is selectable from the constant FPCLK of 48 MHz or SPCLK of 8 MHz A 6 bit divider provides pre scale possibilities to flexibly configure the internal LEDTS counter count rate which overflows in one time frame In the duration of one time frame comprising of configurable number of time slices the configured number of LED columns are activated in sequence In the last time slice of the time frame touch sense function is activated if enabled The time frame is divided into equal time slices of duration ranging from 5 3 us to 2 01 ms configurable The LEDTS counter is started when bit CLK_PS is set to any other value from 0 and at least one of the LED function or the touch sense function is are enabled It does not run when both functions are disabled To avoid over write of function enable which disturbs the hardware control during LEDTS counter running the TS_EN and LD_EN bits can only be modified when bit CLK_PS 0 It is nonetheless possible to set the bits TS_EN and LD_EN in one single write to SFR GLOBCTLO when setting CLK_PS from 0 to 1 or from 1 to 0 When started the counter starts running from a reset reload value based on enabled function s 1 the number of columns bit field NR LEDCOL when LED function is enabled 2 add o
169. operating mode and on the shadow transfer enable bit STE12 Providing a shadow register for the period value as well as for other values related to the generation of the PWM signal allows a concurrent update by software for all relevant parameters Two further signals indicate whether the counter contents are equal to 0000 T12 ZM zero match or 0001 T12 OM one match These signals control the counting and switching behavior of T12 The basic operating mode of T12 either Edge Aligned mode Figure 20 5 or Center Aligned mode Figure 20 6 is selected via bit CTM A Single Shot control bit T12SSC enables an automatic stop of the timer when the current counting period is finished see Figure 20 7 and Figure 20 8 The start or stop of T12 is controlled by the Run bit T12R that can be modified by bits in register TCTRAL TCTR4H The run bit can be set cleared by software via the associated set clear bits T12RS or T12RR it can be set by a selectable edge of the input signal T12HR TCTR2H T12RSEL or it is cleared by hardware according to preselected conditions The timer T12 run bit T12R must not be set while the applied T12 period value is zero Timer T12 can be cleared via control bit T12RES Setting this write only bit does only clear the timer contents but has no further effects for example it does not stop the timer The generation of the T12 shadow transfer control signal T12 ST is enabled via bit STE12 This bit can be set
170. or reset by software indirectly through its associated set clear control bits T1289 TR and T12STD While Timer T12 is running write accesses to the count register T12 are not taken into account If T12 is stopped and the Dead Time counters are 0 write actions to register T12 are immediately taken into account User s Manual 20 20 V1 0 2010 02 CCU6 V4 0 Cinfineon 20 3 2 12 Scheme This section describes the clocking and counting capabilities of T12 Capture Compare Unit 6 CCU6 20 3 2 1 Clock Selection The input clock 74 of Timer T12 is derived from the internal module clock fece through a programmable prescaler and an optional 1 256 divider The resulting prescaler factors are listed in Table 20 7 The prescaler of T12 is cleared while T12 is not running TCTROL T12R 0 to ensure reproducible timings and delays Table 20 7 Timer T12 Input Frequency Options T12CLK Resulting Input Clock 42 Resulting Input Clock 42 Prescaler Off T12PRE 0 Prescaler On T12PRE 1 000g Joce 256 0015 Teal 512 010g Joce 4 foce 1024 011 218 Joce 2048 100 16 Joce 4096 101 32 foce 8192 1105 foce 64 Joce 16384 1115 fece 128 foce 32768 20 3 2 2 Edge Aligned Center Aligned Mode In Edge Aligned Mode CTM 0 timer T12 is always counting upwards CDIR 0 When reaching the value given by the period register pe
171. out data from its shift register There are two ways to avoid collisions on the receive line due to different slave data Only one slave drives the line i e enables the driver of its MRST pin All the other slaves must have their MRST pins programmed as input so only one slave can put its data onto the master s receive line Only receiving data from the master is possible The master selects the slave device from which it expects data either by separate select lines or by sending a special command to this slave The selected slave then switches its MRST line to output until it gets a de selection signal or command This option is applicable only if pin has output driver disabling capability The slaves use open drain output on MRST This forms a wired AND connection The receive line needs an external pull up in this case Corruption of the data on the receive line sent by the selected slave is avoided when all slaves not selected for transmission to the master only send ones 1s Because this high level is not actively driven onto the line but only held through the pull up device the selected slave can pull this line actively to a low level when transmitting a zero bit The master selects User s Manual 18 11 V1 0 2010 02 SSC V1 4 Cinfineon neers High Speed Synchronous Serial Interface the slave device from which it expects data either by separate select lines or by sending a special command to this slave After performing the ne
172. range 0 125 MHz to 0 25 MHz As described in above section some flexibility is provided to adjust the oscillation in the user system 1 Configurable pin low level active extension 2 Alternative enabling of external pull up with resistance selectable by user With a time slice duration configurable ranging from 5 3 us 0 18 MHz to 2 01 ms 496 Hz the software can configure the duration of the pad turn adjustable within time slice using compare function and set a count threshold for oscillations to detect if finger control is available User s Manual 19 13 V1 0 2010 02 LEDTSCU V 1 2 1 Cinfineon LED and Touch Sense Controller 19 6 Time Multiplexed LED and Touch Sense Function on Pin Some hints are provided regarding the time multiplexed usage of a pin for LED and touch sense function The maximum number of LED columns 7 when touch sense function is also enabled If enabled by pin COLA outputs HIGH to enable external R resistor as pull up for touch sense function During touch sense time slice recommend to set LED lines to output HIGH During LED time slice COLA outputs LOW and will sink current if connected lines output HIGH The effective capacitance for each TSIN line depends largely on what is connected to the line and the application board layout All touch pads for the application should be calibrated for robust touch detection User s Manual 19 14 V1 0 2010 02 LEDTSCU V 1 2 1 Cinfineon LED an
173. rate of the serial communication partner host is automatically synchronized in the following steps that are to be included in user software STEP 1 Initialize interface for reception and timer for baud rate measurement STEP 2 Wait for an incoming LIN frame from host STEP 3 Synchronize the baud rate to the host STEP 4 Enter for Master Request Frame or for Slave Response Frame The next section Section 16 6 2 2 provides some hints on setting up the microcontroller for baud rate detection of LIN Note Re synchronization and setup of baud rate are always done for every Master Request Header or Slave Response Header LIN frame User s Manual 16 15 V1 0 2010 02 UART V 1 6 Cinfineon UART 16 6 2 2 Initialization of Break Synch Field Detection Logic The LIN baud rate detection feature provides the capability to detect the baud rate within the LIN protocol using Timer 2 Initialization consists of Serial port of the microcontroller set to Mode 1 8 bit UART variable baud rate for communication Provide the baud rate range via bit field BCON BGSEL Toggle BCON BRDIS bit set the bit to 1 before clearing it back to O to initialize the Break Synch detection logic Clear all status flags LINST BRK LINST EOFSYN and LINST ERRSYN to 0 Timer 2 is set to capture mode with falling edge trigger at pin T2EX Bit T2MOD EDGESEL is set to 0 by default and bit T2CON CP RL2 is set to 1 Timer 2 external events are enab
174. rates together with the required dividers setting User s Manual 17 5 V1 0 2010 02 V1 1 XC82x Cinfineon Inter IC Bus Table 17 5 Baud Rate Selection Baud Rate 100 KBaud Baud Rate 400 KBaud PREDIV BRP 1 PREDIV BRP 1 8 MHz 1 14 4 44 1 14 1 14 24 MHz 1 14 12 1 14 3 34 The frequency at which the IIC bus is sampled is calculated by the formulae 17 2 f _ SAMP jPREDIV To ensure correct detection of START and STOP conditions on the bus the IIC must sample the IIC bus at least ten times faster than the bus clock speed of the fastest master on the bus The sampling frequency should therefore be at least 1 MHz in standard mode or 4 MHz in fast mode to guarantee correct operation with other bus masters 17 5 Clock Synchronization If another device on the IIC bus drives the clock line when the IIC is in master mode the will synchronize its clock to the IIC bus clock The high period of the clock will be determined by the device that generates the shortest high clock period The low period ofthe clock will be determined by the device that generates the longest low clock period When the IIC is in master mode and is communicating with a slow slave the slave may stretch each bit period by holding the SCL line low until it is ready for the next bit The will automatically re synchronize as described above When the IIC is in slave mode it will ho
175. read should be written with 0 User s Manual 20 14 V1 0 2010 02 CCU6 V4 0 Cinfineon XC82x 20 2 4 IP Interconnection Capture Compare Unit 6 CCU6 The CCUG has interconnection to other peripherals enabling higher level of automation without requiring software Table 20 5 CCU6 Outputs Interconnection CCU6 Function Signal Connected Other Module Function Signal Timer 12 output signals T12 period match 0 T12PM ADC Request Source 0 1 Trigger 2 Inputs i REQTROC REQTR1C Timer 13 output signals T13 compare match T13CM ADC Request Source 0 1 Trigger 4 Inputs i REQTROE REQTR1E T13 period match T13PM ADC Request Source 0 1 Trigger 3 Inputs i REQTROD REQTR1D CCU6 service request output signa Is Service request output SR2 0 CCU6_SR2 ADC Request Source 0 1 Trigger 0 Input i REQTROA REQTR1A Service request output SR3 CCU6_SR3 ADC Request Source 0 1 Trigger 1 Input i REQTROB REQTR1B Miscellaneous signals MCM shadow transfer MCM_ST ADC Request Source 0 1Trigger 5 Inputs i REQTROF REQTR1F Table 20 6 CCU6 Inputs Interconnection CCU6 Connected Other Module Selected By Function Signal Function Signal Capture Inputs CCU6 input i CC60 CCU6 SR2 output CCU6_PISELOL ISCC60 10 CCU6_SR2 ADC boundary event 0 CCU6_PISELOL ISCC60 11 ADC_BFO C
176. reduced rate if data reduction or digital low pass filteris active Outofrange comparator events indicate that a voltage higher or lower than Vddp is detected at the analog input channels Each ADC event is indicated by a dedicated flag that can be cleared by software If an interrupt is enabled for a certain event the interrupt is generated for each event independent of the status of the corresponding event indication flag This ensures efficient handling of ADC events the ADC event can generate an interrupt without the need to clear the indication flag The Request source event Channel event and Result events share a common service request output ADC SRO while the the Out of range comparator events uses the ADC SR service request output Note A conversion can lead to three interrupts one of each type if all are enabled In this case the ADC module first triggers the request source event interrupt then the channel event interrupt followed by the result event interrupt all within a few clock cycles User s Manual 21 83 V1 0 2010 02 ADC V2 1 Cinfineon XC82x Analog to Digital Converter The Event indication Flag Register ADC_EVINFR monitors both the detected request source events flags EVINFO EVINF 1 and the result events flags EVINF4 EVINF7 ADC EVINFR Event Interrupt Flag Register Reset Value 00 RMAP 0 PAGE 5 7 6 5 4 3 2 1 0 EVINF7 EVINF6 EV
177. request source event of a scan source occurs if the last conversion of a scan sequence is finished all pending bits 0 A request source event interrupt can be generated based on a request source event according to the structure shown in Figure 21 7 If a request source event is detected it sets the corresponding indication flag in register ADC_EVINFR The indication flags can be cleared by SW by writing a1 to the corresponding bit position in register ADC_EVINCR The service request output SRx becomes activated each time the related request source event is detected and enabled by CRMRx ENSI The request source events and the result events share the same registers The request source event is located at the bit position in register ADC_EVINFR Event 1 Request source event of the channel scan source 1 in arbitration slot 1 requestsource request source event event indication flag interrupt enable EVINFR EVINF 1 set scan sequence finished request source event to SRO ADC_scan_source_int Figure 21 7 Interrupt Generation of a Scan Request Source The conversion request mode registers contains bits used to set the request source in the desired mode ADC_CRMR1 Conversion Request Mode Register 1 CC Reset Value 00 RMAP 0 PAGE 6 7 6 5 4 3 2 1 0 0 LDEV CLRPND SCAN ENSI ENTR 0 r rw rw rw User s Manual 21 21 V1 0 2010 02 ADC V2 1 Cinfineon XC82
178. rw Input Control Register Input control register controls the input driver of each port pin This register is use in port P2 User s Manual 11 10 V1 0 2010 02 Cinfineon XC82x Parallel Ports Field Bits Type Description Pn n rw Pin Output Functions 0 7 Configuration of Px_ALTSELO Pn Px_ALTSEL1 Pn and Px_ALTSEL2 Pn for GPIO or alternate settings 000 Normal GPIO 001 Alternate Select 1 010 Alternate Select 2 011 Alternate Select 3 100 Alternate Select 4 101 Alternate Select 5 110 Alternate Select 6 111 Alternate Select 7 Px_EN Port x Input Control Register 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 1 PO rw rw rw rw rw rw rw rw Field Bits Type Description Pn n rw Input Driver Control at Port x Bit n 0 7 0 Input driver is enabled 1 Input driver is disabled User s Manual 11 11 V1 0 2010 02 Cinfineon XC82x 11 2 Port 0 Parallel Ports Port 0 is a 7 bit general purpose bidirectional port It uses the standard bidirectional pad for each pin The registers of Port 0 are summarized in Table 11 3 Table 11 3 Port 0 Registers Register Short Name Register Long Name PO DATAIN Port 0 Data In Register PO DATAOUT Port 0 Data Out Register PO OD Port 0 Open Drain Control Register PO PUDSEL Port 0 Pull Up Pull Down Select Register PO PUDEN Port 0 Pull Up Pull Down Enable Register PO ALTSELO Port 0
179. rw rw rw rw rw Field Bits Type Description NMIWDT 0 rw Watchdog Timer NMI Enable 0 WDT NMI is disabled 1 WDT NMI is enabled NMIOSCCLK 1 rw Loss of 48 MHz or 75 KHz Oscillator Clock NMI Enable 0 Loss of 48 MHz or 75 KHz Oscillator Clock NMI is disabled 1 Loss of 48 MHz or 75 KHz Oscillator Clock NMI is enabled NMIFLASH 2 rw Flash NMI Enable 0 Flash Timer NMI is disabled 1 Flash Timer NMI is enabled NMIOCDS 3 rw OCDS NMI Enable 0 OCDS NMI is disabled 1 OCDS NMI is enabled NMIVDDC 4 rw VDDC Prewarning NMI Enable 0 VDDC prewarning NMI is disabled 1 VDDC prewarning NMI is enabled User s Manual 9 19 V1 0 2010 02 Interrupt System V 2 3 3 Cinfineon XBox Interrupt System Field Bits Type Description NMIVDDP 5 rw VDDP Prewarning NMI Enable 0 VDDP prewarning NMI is disabled 1 VDDP prewarning NMI is enabled NMIECC 6 rw ECC Error NMI Enable 0 ECC Error NMI is disabled 1 ECC Error NMI is enabled 0 7 r Reserved Returns 0 if read should be written with 0 Note When the external power supply is 3 3 V the user must disable NMIVDDP 9 5 2 External Interrupt Control Registers The seven external interrupts EXT_INT 6 0 are driven into the XC82x from the ports External interrupts can be positive negative or double edge triggered Registers EXICONO and 1 specify the active edge for the external interrupt Among the external interrupts ext
180. serial port behaves as shift register data is shifted in through RXD and out through RXDO while the TXD line is used to provide a shift clock which can be used by external devices to clock data in and out In modes 1 2 and 3 the port behaves as an UART Data is transmitted on TXD and received on RXD Note XC82x does not support mode 0 operation and therefore RXDO line is not connected to any general purpose I O port The UART I O pins are generally assigned as alternate functions to general purpose I O ports Bit URRIS in register MODPISEL 1 is used to select one of the RXD input function The UART pin assignment for XC82x is shown in Table 16 1 Table 16 1 Pin Functions in XC82x Pin Function Desciption Selected By P0 5 RXD 0 Receive Data Input 0 MODPISEL1 URRIS 00 P0 6 RXD 1 UART Receive Data Input 1 MODPISEL1 URRIS 01g P1 0 RXD 2 UART Receive Data Input 2 MODPISEL1 URRIS 10 User s Manual 16 1 V1 0 2010 02 UART V 1 6 Cinfineon UART Table 16 1 UART Pin Functions in XC82x Pin Function Desciption Selected By P2 1 RXD 3 UART Receive Data Input 3 MODPISEL1 URRIS 11 P0 6 TXD_O UART Transmit Data Output 0 PO_ALTSELO P5 1 PO_ALTSEL1 P5 1 PO_ALTSEL2 P5 0 P1 0 TXD_1 UART Transmit Data Output 1 P1 ALTSELO PO 1g P1 ALTSEL1 PO 1g P1 1 TXD 2 UART Transmit Data Output 2 P1 ALTSELO P1 1 P1 ALTSEL1 P1 1g P0 5 TXD 3 UART Transmit Dat
181. shifted right one position and a zero shifted in from the left so that when the MSB of the data byte is at the output position it has a 1 and a sequence of zeros to its left The control block then executes one last shift beforesetting the TI bit Reception is started by the condition REN 1 and RI 0 At the start of the reception cycle 11111110 is written to the receive shift register In each machine cycle that follows the contents of the shift register are shifted left one position and the value sampled on the RXD line in the same machine cycle is shifted in from the right When the 0 of the initial byte reaches the leftmost position the control block executes one last shift loads SBUF and sets the RI bit The baud rate for the transfer is fixed at foc 2 where fpc is the input clock frequency i e one bit per machine cycle 16 3 2 1 8 Bit UART Variable Baud Rate In mode 1 the UART behaves as an 8 bit serial port A start bit 0 8 data bits anda stop bit 1 are transmitted on TXD or received on RXD at a variable baud rate The transmission cycle is activated by a write to SBUF The data is transferred to the transmit register and a 1 is loaded to the 9th bit position as in mode 0 At phase 1 of the machine cycle after the next rollover in the divide by 16 counter the start bit is copied to TXD and data is activated one bit time later One bit time after the data is activated the data starts getting shifted
182. signals CCPOSx and the CURH and EXPH bit fields are arranged in the following order CCPOSO corresponds to CURH 0 LSB and 0 LSB 51 corresponds to CURH 1 and EXPH 1 CCPOS2 corresponds to CURH 2 MSB and EXPH 2 MSB User s Manual 20 90 V1 0 2010 02 CCU6 V4 0 Cinfineon Capture Compare Unit 6 CCU6 20 7 1 Hall Pattern Evaluation The Hall sensor inputs CCPOSx can be permanently monitored via an edge detection block with the module clock fcc In order to suppress spikes on the Hall inputs due to noise in rugged inverter environment two optional noise filtering methods are supported by the Hall logic both methods can be combined Noise filtering with delay For this function the mode control bit fields MSEL6x for all T12 compare channels must be programmed to 1000 and DBYP 0 The selected event triggers Dead Time Counter 0 to generate a programmable delay defined by bit field DTM When the delay has elapsed the evaluation signal HCRDY becomes activated Output modulation with T12 PWM signals is not possible in this mode Noise filtering by synchronization to PWM The Hall inputs are not permanently monitored by the edge detection block but samples are taken only at defined points in time during a PWM period This can be used to sample the Hall inputs when the switching noise due to PWM does not disturb the Hall input signals If neither the delay function of Dead Time Counter 0 is not used fo
183. similar to the TF2 must be cleared by software If bit T2RHEN is set Timer 2 is started by first falling edge rising edge at pin T2EX which is defined by bit T2REGS If bit EXEN2 is set bit EXF2 is also set at the same point when Timer 2 is started with the same falling edge rising edge at pin T2EX which is defined by bit EDGESEL The reload will happen with the following negative positive transitions at pin T2EX which is defined by bit EDGESEL User s Manual 14 5 V1 0 2010 02 Timer 2 V 1 2 Cinfineon Timer 2 Note In counter mode if the reload via T2EX and the count clock T2 are detected simultaneously the reload takes precedence over the count The counter increments its value with the following T2 count clock PREN Overflow Timer 2 Interrupt T2EX Figure 14 1 Auto Reload Mode 0 14 4 2 Up Down Count Enabled If 1 the up down count selection is enabled The direction of count is determined by the level at input pin T2EX The operational block diagram is shown in Figure 14 2 A logic 1 at pin T2EX sets the Timer 2 to up counting mode The timer therefore counts up to a maximum of FFFF Upon overflow bit TF2 is set and the timer register is reloaded with a 16 bit reload value of the RC2 register A fresh count sequence is started and the timer counts up from this reload value as in the previous count sequence This reload value is chosen by software prior
184. size required 2 Resource used destroyed A MDO MD1 MD2 MD4 MD5 MRO MR1 MR2 MR4 MR5 MDUCON MDUSTAT DPL DPH RO R7 of current Register Bank User s Manual ROM Library V0 5 23 43 V1 0 2010 02 Cinfineon ROM Library 23 4 EEPROM Emulation ROM Library The XC82x provide EEPROM emulation functionality via the ROM library The EEPROM is emulated using the on chip flash memory The ROM library provide a framework to access the emulated EEPROM The ROM library used the following application note as a reference 0805710 XC866 XC886 XC888 EEPROM EMULATION 23 4 1 Feature The EEPROM emulation ROM library has the following feature Provide functions to initialize fix read and write to emulated EEPROM Support EEPROM emulation size of 31 62 93 or 124 bytes Upto 1 6 millions endurance cycles for a data retention time of 2 years 23 4 2 System requirement The ROM library has several requirement e Use 512 bytes of flash memory from address AE00 to AFFF for EEPROM emulation Only support KEIL C51 toolchain small memory model big endian register calling convention Only support polling based flash operation No support for detection of aborted programming operation 23 4 3 Concept EEPROM emulation is implemented using 512 bytes of flash that is divided into 2 logical sectors At any one time only one of the logical sectors is the active sectors i e
185. that a conversion is currently active Og analog part is idle 1g conversion is currently active SAMPLE rh Sample Phase This bit indicates that an analog input signal is currently sampled Og analog part is not in the sampling phase 1g analog part is in the sampling phase CHNR 5 3 rh Channel Number This bit field indicates which analog input channel is currently converted This information is updated when a new conversion is started Note Bit 5 is only applicable for devices that have 8 ADC channels For channels not implemented these bits should be treated as Reserved bits of type r which returns 0 if read and should be written with 2 7 6 Reserved Returns 0 if read should be written with 0 User s Manual ADC V2 1 21 16 V1 0 2010 02 Cinfineon Analog to Digital Converter 21 6 Conversion Request Generation The conversion request unit of each ADC kernel autonomously handles the generation of conversion requests Two request sources can generate requests for the conversion of an analog channel The arbiter resolves concurrent requests and selects the channel to be converted next Upon a trigger event the request source requests the conversion of a certain analog input channel or a sequence of channels Software triggers directly activate the respective request source External triggers synchronize the request source activa
186. the sector containing the latest dataset User application needs to initialise the emulated EEPROM before it can be used This can be done by calling the initialisation function and specifying the desired emulation scheme The initialisation function will update the information in EEPROMInfo data structure on Page 23 46 that is used by the ROM library functions The ROM library supports 4 emulation scheme i e Mode 0 Mode 1 Mode 2 amp Mode 3 Basically each mode represent the size of the emulated EEPROM User application will access the emulated EEPROM using logical address The number of valid logical address is dependent on the size of the emulated EEPROM Each logical address represent 32 bytes of data where 31 bytes are user data and one status byte This represent the required size for each flash write operation i e flash word line WL size 1 For 4K device EEPROM is emulated using address 0E00 to OFFF User s Manual 23 44 V1 0 2010 02 ROM Library V0 5 Cinfineon ROM Library The logical address provides a convenient abstraction so that user application don t need to deal with the actual physical flash address that is used for emulation The status byte is used by the ROM library to manage the EEPROM emulation It is written at the end of each flash wordline The user application can safely ignore this status byte Table 23 19 EEPROM emulation scheme Emulation Scheme Emulated EEPROM size
187. the functions of the microcontroller are stopped while the contents of the Flash on chip RAM XRAM and the SFRs are maintained Table 7 3 shows the behaviour of several modules during power down mode In power down mode 2 RTC is running in the periodic wake up mode It allows the device to exit power down mode at a specfic period of time The function is useful in low power application Modules running in power down mode remain functioning at the reduced voltage condition where the main power supply could be as low as 2 5 V However it may shows a reduced performance The rest of the modules are powered down in all power down modes Table 7 4 shows the available wake up source for each power down mode One of the available source is to receives an external wake up signal via EXINTO pin by setting bit EWS to 1 The edge that trigger the wake up signal will depends on bit EXINTO in EXICONO register User s Manual 7 17 V1 0 2010 02 Cinfineon XC82x System Control Unit Note EXICONO EXINTO 11 cannot be used to wake up from power down mode Table 7 3 Modules Behavior in Power Down Modules Power Down Mode 1 Power Down Mode 2 RTC N Y 75 KHz OSC N Y 75 KHz OWD N N 1 indicates that the module is shut down and Y indicates that it can run if enabled in power down mode 2 RTC Mode 3 is not supported in power down mode The RTCCLK pin will be shut down once power down mode is entered Table 7
188. this IRAM data to the corresponding write buffers of the targeted Flash bank Once the data are assembled in the write buffers the charge pump voltages are ramped up by a built in program and erase state machine Once the voltage ramping is completed the volatile data content in the write buffers would have been stored into the non volatile Flash cells along the selected WL The WL is selected via the WL addresses shown in Figure 4 3 It is necessary to fill the IRAM with the number of bytes of data as defined by the program width otherwise the previous values stored in the write buffers will remain and be programmed into the WL The same WL can be programmed twice before erasing is required as the Flash cells are able to withstand two gate disturbs This means if the number of data bytes that need to be written is smaller than the 32 bytes minimum programming width the user can opt to program this number of data bytes x where x can be any integer from 1 to 31 first and program the remaining bytes 32 x later However since the minimum programming width of Flash is always 32 bytes the bytes that are unused in each programming cycle must be written with all zeros Figure 4 4 shows an example of programming the same wordline twice with 16 bytes of data In the first program cycle the lower 16 bytes are written with valid data while the upper 16 bytes that do not contain meaningful data are written with all zeros In the second program cycle it
189. to the occurrence of an overflow condition A logic 0 at pin T2EX sets the Timer 2 to down counting mode The timer counts down and underflows when the THL2 value reaches the value stored at register RC2 The User s Manual 14 6 V1 0 2010 02 Timer 2 V 1 2 Cinfineon 2 underflow condition sets the TF2 flag and causes to be reloaded into the 2 register A fresh down counting sequence is started and the timer counts down as in the previous counting sequence If bit T2RHEN is set Timer 2 can only be started either by rising edge T2REGS 1 at pin T2EX and then proceed with the up counting or be started by falling edge T2REGS 0 at pin T2EX and then proceed with the down counting In this mode bit EXF2 toggles whenever an overflow or an underflow condition is detected This flag however does not generate an interrupt request Timer 2 TF2 Interrupt Overflow Figure 14 2 Auto Reload Mode 1 User s Manual 14 7 V1 0 2010 02 Timer 2 V 1 2 Cinfineon Timer 2 14 5 Capture Mode In order to enter the 16 bit capture mode bits CP RL2 and EXEN2 in register T2CON must be set In this mode the down count function must remain disabled The timer functions as a 16 bit timer and always counts up to FFFF after which an overflow condition occurs Upon overflow bit TF2 is set and the timer reloads its registers with 00003 The setting of TF2 generates
190. w User s Manual 20 116 V1 0 2010 02 CCUG V4 0 Cinfineon XC82x Capture Compare Unit 6 CCU6 Field Bits Type Description ST13CM 0 w Set Timer T13 Compare Match Flag Og action 1g Bit T13CM will be set ST13PM 1 w Set Timer T13 Period Match Flag 0s action 1g Bit T13PM will be set STRPF 2 Ww Set Trap Flag Og No action 1g Bits TRPF and TRPS will be set SWHC 3 w Software Hall Compare Og No action 1g The Hall compare action is triggered SCHE 4 w Set Correct Hall Event Flag Og action 1g will be set SWHE 5 WwW Set Wrong Hall Event Flag Og action 1g Bit WHE will be set SIDLE 6 w Set IDLE Flag Og No action 1g Bit IDLE will be set SSTR 7 w Set STR Flag Og action 1g Bit STR will be set User s Manual CCU6 V4 0 20 117 V1 0 2010 02 Cinfineon Capture Compare Unit 6 CCU6 20 9 2 3 Status Reset Register Register ISRL H contains bits to individually clear the interrupt event flags by software Writing a 1 clears the bit s in register IS at the corresponding bit position s All bit positions read as 0 ISRL Interrupt Status Reset Register Low 4 Reset Value 00 RMAP 0 PAGE 0 7 6 5 4 3 2 1 0 RT12PM 12 RCC62F RCC62R RCC61F RCC61R RCC60F RCC60R Ww Ww w w w w w w Field Bits Type Description RCC60R 0 w Reset Capture Compare Match Rising Edge
191. will be opposite as now only the upper 16 bytes can be written with valid data and the lower 16 bytes which already contain meaningful data must be written with all zeros User s Manual 4 6 V1 0 2010 02 Flash Memory V 0 1 Infineon XC82x Flash Memory 32 bytes 1 WL 0000 0000 0000 0000 0000 0000 1111 0000 m 111 0 Flash memory cells Program 1 16 bytes 0000 0000 16 bytes SAAN sns 1111 Note A Flash memory cell be programmed from 0 to 1 but not from 1 to 0 32 byte write buffers Figure 4 4 Flash Program User s Manual Flash Memory V 0 1 4 7 V1 0 2010 02 Cinfineon nears Flash Memory 4 4 Operating Modes The Flash operating modes for each bank are shown in Figure 4 5 5 i of Call of Flash erase routine Flash program routine or by BSL or by BSL p Power Down System Power Down Figure 4 5 Flash Operating Modes In general the Flash operating modes are controlled by the BSL and Flash program erase subroutines see Section 4 7 Each Flash bank must be in ready to read mode before the program mode or sector s erase mode is entered In the ready to read mode the 32 byte write buffers for each Flash bank can be written and the memory cell
192. working modes User s Manual 5 4 V1 0 2010 02 Cinfineon XBox Boot and Startup 5 2 4 OCDS Mode If the OCDS mode is selected the debug mode will be entered for debugging program code The OCDS hardware is initialized and a jump to program memory address 0000 is performed next The user code in the Flash memory is executed and the debugging process may be started During the OCDS mode the lowest 64 bytes 00 in the internal data memory address range may be alternatively mapped to the 64 byte monitor RAM or the internal data RAM User s Manual 5 5 V1 0 2010 02 Cinfineon Boot Loader 6 UART Boot Loader The XC82x includes a UART Boot Loader BSL Mode that can be entered with the BMI settings as described in Boot and Startup chapter The main purpose of BSL Mode is to allow easy and quick programming erasing of the Flash and XRAM via UART The UART BSL mode consists of two functional parts that presents two phases as described below Phase I Establish a serial connection and automatically synchronize to the transfer speed bau d rate of the serial communication partner host Phase Perform the serial communication with the host The host controls the communication by sending special header information which selects one of the working modes These modes are 1 Mode2 Mode3 4 ModeA Program customer
193. 0 LINE3 TSIN3 P0 2 T1 0 CC62 1 SCL 1 CCPOS2 0 LINE2 TSIN2 P0 1 T0_0 CC61_1 MTSR_3 MRST_2 T13HR O CCPOS1 O LINE1 TSIN1 P0 0 T2_0 T13HR_4 MTSR_2 MRST_3 T12HR_0 CCPOSO_O LINEO TSINO COUT61_1 Vssp Vopr P4 3 CC61 0 COL3 0 CC61 O EXF2 1 Figure 1 3 XC824 050 20 package Pin Configuration Top View User s Manual 1 4 V1 0 2010 02 System Architecture V1 0 Cinfineon Introduction 11 002 0 2 _1 5 1_0 5 _0 1_0 EXINTO_O LINES TSINS sod ge aS 16 CTRAP_T LINEA TSIN4 EXF2_0 COLO_4 COL3 1 COLA 2 PO 6ISPD_OIRXD_1 SDA_OIMTSR_1 MRST_0 15 0 1 SDA CTRAP 9j EXINTO 1 T2EX O LINEG TSING TXD 0 LINES TSINS COL2 1 COLA 1 P0 2 T1 0 CC62 1 SCL 1 CCPOS2 0 P2 3 CCPOS0_2 CTRAP_2 T2_2 EXINT3 AN3 3 MT P2 2 CCPOS2 1 T12HR 3 T13HR 3 4 43 P0 1 T0_0 CC61_1 MTSR_3 MRST_2 SCK 1 T1 1 EXINT2 AN2 T13HR O CCPOS1 O LINE1 TSIN1 XC822 P2 4 CCPOS1 1 RXD 3 MTSR 4 70 1 P0 0 T2 0 T13HR 1 MTSR 2 1 AN1 5 12 MRST_3 T12HR_O CCPOSO_O LINEO TSINO COUT61 1 P2 0ICCPOSO 1 TI2HR 2IT13HR 2 72 3 amp aliy T2_1 EXINTO_3 ANO 006 P4 0 SPD 1 RXD 2 T2EX 2 0 2 wiy COLO 0 COUT60 O TXD 1 Ser P1 2IEXINTA COL2_O COUT61_0 mu COUT63 0 DDP Figure 1 4 XC822 TSSOP 16 package Pin Configuration To
194. 0 2010 02 IIC V1 1 Cinfineon Inter IC Bus Field Bits Description 5 7 rw Disable Request Active high 0 is in normal operation 1 Request to disable the IIC default 0 5 r Reserved Returns 0 if read should be written with 0 17 2 3 Interrupt Events and Assignment Table 17 2 lists the interrupt event source from the IIC and the corresponding event interrupt enable bit and flag bit Table 17 2 IIC Interrupt Events Event Event Interrupt Enable Bit Event Flag Bit interrupt CNTR IEN CNTR IFLG Table 17 3 shows the interrupt node assignment for the IIC interrupt source Table 17 3 IIC Events Interrupt Node Control Event Interrupt Node Interrupt Node Flag Vector Enable Bit Bit Address interrupt IEN1 EX2 43 User s Manual 17 3 V1 0 2010 02 IIC V1 1 Cinfineon Inter IC Bus 17 3 Status Code The state of the IIC is defined by the 5 bit status code in STAT register When STAT contains the status code F8 no relevant status information is available no interrupt is generated and the IFLG bit in the CNTR register is not set All other status codes correspond to a defined state of the IIC When any of these states is entered the corresponding status code appears in this register and the IFLG bit in the CNTR register is set When the IFLG bit is cleared the status code returns to F84 Table 17 4 Status Code
195. 0 R8 R7 R6 R5 R4 R3 R2 R1 RO 0 O VF CHNR msb rh Isb rh adc_result_register_view_he_8bit_drctr 1_dlpf 0 vsd Figure 21 24 8bit RCRx DRCTR 1 RCRx DLPF 0 Result Register View Result Read View SFR Page 2 10 bit conversion with accumulation 15 conversion RESRxH RESRxL 7 6 5 4 3 2 1 0 7 6 5 43 2 1 0 0 Ra R7 5 4 RB R2 R1 RO VF CHNR msb rh Isb rh 10 bit conversion accumulated 11 bit 274 conversion onwards RESRxH RESRxL 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 RO VF CHNR msb rh Isb rh adc_result_register_view_he_10bit_drct 1_dipf 0 vsd Figure 21 25 10bit RCRx DRCTR 1 RCRx DLPF 0 Result Register View Result Read View SFR Page 2 10 bit conversion accumulated 13 bit filter with DLPF 1 RESRxH RESRxL 7 6 5 4 3 2 1 0 7 6 5 43 2 1 0 R12 R11 R10 R9 Ra R7 R6 R5 R4 R3 R2 R1 RO CHNR msb rh Isb rh adc_result_register_view_he_10bit_drct 0_dipf 1 vsd Figure 21 26 10bit RCRx DRCTR 0 RCRx DLPF 1 Result Register View All conversion results are stored in the result registers the content of the result register is available at a single page address and data are aligned according to the different
196. 0 3 1 Counting scheme see Section 20 3 2 Compare modes see Section 20 3 3 Compare mode output path see Section 20 3 4 Capture modes see Section 20 3 5 Shadow transfer see Section 20 3 6 T12 operating mode selection see Section 20 3 7 T12 counter register description see Section 20 3 8 User s Manual 20 17 V1 0 2010 02 CCU6 V4 0 Cinfineon Capture Compare Unit 6 CCU6 State Bits Capture Compare Channel CC60 Hen Dead Time Timer T12 Capture Compare Control Logic Channel CC61 poster and Output Capture Compare Modulation Channel CC62 CC62ST Input and Control Status Logic T12HR CCPOSx CCU6_MCA05507 Figure 20 3 Overview Diagram of the Timer T12 Block User s Manual 20 18 V1 0 2010 02 CCU6 V4 0 Cinfineon Capture Compare Unit 6 CCU6 20 3 1 T12 Overview Figure 20 4 shows a detailed block diagram of Timer T12 The functions of the timer T12 block are controlled by bits in registers TCTROL TCTROH TCTR2L TCTR2H TCTRAL PISELOL and PISELOH Timer T12 receives its input clock 742 from the module clock focs via a programmable prescaler and an optional 1 256 divider or from an input signal T12HR These options are controlled via bit fields T12CLK and T12PRE see Table 20 7 T12 can count up or down depending on the selected operation mode A direction flag CDIR indicates the current counting direction T12RS T12RS
197. 0 7 0 Pull down device is selected 1 Pull up device is selected Px_PUDEN Port x Pull Up Pull Down Enable Register 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 1 rw rw rw rw rw rw rw rw User s Manual 11 9 V1 0 2010 02 Cinfineon Parallel Ports Field Bits Type Description Pn n rw Pull Up Pull Down Enable at Port x Bit n 0 7 0 Pull up or Pull down device is disabled 1 Pull up or Pull down device is enabled Alternate Input Functions The number of alternate functions that uses a pin for input is not limited Each port control logic of an I O pin provides several input paths of digital input value via register These port input selection registers are described in each peripheral chapter Alternate Output Functions Alternate functions are selected via an output multiplexer which can select up to eight output lines This multiplexer can be controlled by the following signals Register Px ALTSELO Register Px ALTSEL1 Register Px ALTSEL2 Selection of alternate functions is defined in registers ALTSELO Px ALTSEL1 and Px ALTSEL2 Px ALTSEL2 is optional for ports that does not required more than 4 alternate functions Note Set Px ALTSELO Pn Px ALTSEL1 Pn and Px ALTSEL2 Pn to select only implemented alternate output functions Px ALTSEL n n 7 0 1 2 Port x Alternate Select Register 7 6 5 4 3 2 1 0 7 6 5 P4 P3 P2 1 rw rw rw rw rw rw rw
198. 0 Normal Mode output is actively driven for 0 1 state 1 Open Drain Mode output is actively driven only for 0 state default 0 7 6 r Reserved Returns 0 if read should be written with 0 P1_PUDSEL Port 1 Pull Up Pull Down Select Register 90 RMAP 0 PAGE 1 Reset Value 3F 7 6 5 4 3 2 1 0 0 5 P4 P3 P2 1 T rw rw rw rw rw rw Field Bits Type Description Pn n rw Pull Up Pull Down Select Port 1 Bit n n 0 5 0 Pull down device is selected 1 Pull up device is selected default 0 7 6 r Reserved Returns 0 if read should be written with 0 User s Manual 11 27 V1 0 2010 02 Cinfineon XC82x P1_PUDEN Port 1 Pull Up Pull Down Enable Register 91 RMAP 0 PAGE 1 Parallel Ports Reset Value 00 7 6 5 4 3 2 1 0 0 P5 P4 P3 P2 P1 PO T rw rw rw rw rw rw Field Bits Type Description Pn n rw Pull Up Pull Down Enable at Port 1 Bit n n 0 5 0 Pull up or Pull down device is disabled default 1 Pull up or Pull down device is enabled 0 7 6 r Reserved Returns 0 if read should be written with 0 P1_ALTSELx x 0 1 Port 1 Alternate Select Register 90 x RMAP 0 PAGE 2 Reset Value 00 7 6 5 4 3 2 1 0 0 P5 P4 P3 P2 P1 r nw nw nw nw rw rw Field Bits Type Description Pn n rw See Table 11 8 0 5 0 7 6 r
199. 0 w Timer T13 Run Reset Setting this bit clears the T13R bit T13Ris not influenced 1g T13Ris cleared T13 stops counting T13RS 1 w Timer T13 Run Set Setting this bit sets the T13R bit T13Ris not influenced 1g T13R is set T13 starts counting T13RES 2 w Timer T13 Reset No effect T13 1g T13 counter register is cleared to zero The switching of the output signals is according to the switching rules Setting of T13RES has no impact on bit T13R T13STR 6 Timer T13 Shadow Transfer Request Og No action 1g STE13 is set enabling the shadow transfer T13STD 7 w Timer T13 Shadow Transfer Disable Og action 1g STE13 is cleared without triggering the shadow transfer User s Manual 20 65 V1 0 2010 02 CCU6 V4 0 Cinfineon XC82x Capture Compare Unit 6 CCU6 Field Bits Type Description 5 3 reserved returns 0 if read should be written with 0 Note A simultaneous write of a 1 to bits that set and clear the same bit will trigger no action The corresponding bit will remain unchanged User s Manual CCU6 V4 0 20 66 V1 0 2010 02 Cinfineon Capture Compare Unit 6 CCU6 20 4 Operating Timer T13 Timer T13 is implemented similarly to Timer T12 but only with one channel in compare mode A 16 bit up counter is connected to a channel register via a comparator that generates a signal when the counte
200. 00 Bit Fie T13RSEL T12RSEL Timer Control Register 2 High Type rw rw FCH CCU6_MODCTRL Reset 004 Bit Fie MCM 0 T12MODEN Modulation Control Register Low EN Type rw r TW FDH CCU6_MODCTRH Reset 004 Bit Fie ECT1 0 T13MODEN Modulation Control Register High 30 Type rw r rw FEH CCU6_TRPCTRL Reset 004 Bit Fie 0 TRPM TRPM TRPM Trap Control Register Low 2 1 0 Type rw rw rw FFH CCU6_TRPCTRH Reset 004 Bit Fie TRPP TRPE TRPEN Trap Control Register High EN N13 Type TW rw TW RMAP 0 PAGE 3 CCU6_MCMOUTL Reset 004 Bit Field 0 R MCMP Multi Channel Mode Output Register Low Type r rh rh CCU6_MCMOUTH Reset 00 Bit Field 0 CURH EXPH Multi Channel Mode Output Register Type r rh rh High User s Manual 3 29 V1 0 2010 02 Memory Organization V 0 1 Infineon XC82x Memory Organization Table 3 9 CCU6 Register Overview cont d Addr Register Name Bit 7 6 5 4 3 2 1 0 PCy CCU6_ISL Reset 004 Bit Fie T12 T12 ICC62 ICC62 ICC61 ICC61 ICC60 ICC60 Capture Compare Interrupt Status PM OM R F R F R Register L iad Type rh rh rh rh rh rh rh rh CCU6_ISH Reset 004 Bit Fie STR IDLE WHE CHE TRPS TRPF 113 T13 Capture Compare Interrupt Status PM CM Register High Sd Type rh rh rh rh rh rh rh rh CCU6_PISELOL Reset 004 Bit Fie ISTRP ISCC62
201. 011 Timer 2 Input T2EX 3 is selected 100 Timer 2 Input T2EX 4 is selected 101 Timer 2 Input T2EX 5 is selected 110 Reserved 111 Reserved Note T2EX 4 and T2bX 5 are triggered by Out of Range 0 event and Out of Range 1 event respectively User s Manual 14 2 V1 0 2010 02 Timer 2 V 1 2 Cinfineon XBox Timer 2 Field Bits Type Description 215 4 3 rw Timer 2 Input Select 00 Timer 2 Input T2_0 is selected 01 Timer2 Input T2 1 is selected 10 Timer 2 Input T2 2 is selected 11 Reserved 0 7 r Reserved Returns 0 if read should be written with 0 14 2 2 Clocking Configuration The Timer 2 runs on the PCLK at a frequency of either 8 MHz or 24 MHz If the Timer 2 functionality is not required at all it can be completely disabled by gating off its clock input for maximal power reduction This is done by setting bit T2_DIS in register PMCON 1 as described below PMCON1 Peripheral Management Control Register 1 EF Reset Value RMAP 0 PAGE 1 7 6 5 4 3 2 1 0 DIS LTS DIS 0 MDU DIS T2 DIS DIS SSC DIS DIS rw rw fF rw rw rw rw rw Field Bits Description T2_DIS 3 rw T2 Disable Request Active high 0 T2 is in normal operation 1 Request to disable the T2 default 0 5 r Reserved Returns 0 if read should be written with 0 14 2 3 Interrupt Events and Assignment Table
202. 1 mle E RR OR AMS RAS E 1 14 1 800 Core bane ae eae eae e Ea pu RR Roe EG 2 1 1 Quad APP 2 1 1 XC800 Core Functional Blocks 2 1 1 SERS Of the CPI uses ses se kei Ronde CRT OR dor Rs 2 3 1 Stack Pointer SP 81 2 3 1 Data Pointer DPTR 82 3 2 3 1 Accumulator ACC 0 2 3 1 B Register FO e Glee AR AE 2 3 1 Program Status Word PSW 2 3 1 Extended Operation Register EO A24 2 5 1 Power Control Register PCON 87 2 6 1 Interrupt Registers 2 2 2 2 6 1 SFRs of The Core Peripherals 2 7 1 Timer Registers a eR 2 7 1 VART Registers scum bed e 2 7 1 Instr ctlon TIMING 5 ina eo Reg el aah hee dr egt 2 8 1 Memory Organization 3 1 1 Program Memoby ordern tarder 3 2 1 Data Memo eui oes ex bo ados ox Ree dos eR s 3 2 1 Internal Data Memory 3 2 1 External D
203. 1 Port Input Select Registers 20 127 1 Register 0 2 2 20 131 1 Analog to Digital Converter 21 1 1 System Information 21 3 1 Pinning deep 21 3 1 Clocking 21 3 1 Interrupt Events and 21 4 1 IP Interconnection i oes Rhee nne enel 21 4 1 Introduction and Basic Structure 21 7 1 Electncal Models ER 21 10 1 Transfer Characteristics and Error Definitions 21 12 1 Configuration of General Functions 21 13 1 General Clocking Scheme and 21 13 1 Conversion Request Generation 21 17 1 Channel Scan Request Source Handling 21 19 1 Queued Request Source Handling 21 25 1 Hardware Trigger Selection 21 37 1 Request Source Arbitration 21 38 1 Arbiter Timing 21 40 1 Request Source Priority and Conversion Start Mode 21 41 1 Analog Input Channel Configuration 21 45 1 Reference Selection
204. 1 23 2 2 2 23 2 3 23 3 23 3 1 23 3 2 23 3 3 23 3 4 23 4 23 4 1 23 4 2 23 4 3 23 4 4 23 4 4 1 23 4 4 2 23 4 4 3 23 4 4 4 Flash Program Subroutine 22 7 1 Flash Erase Subroutine 22 9 1 Abort Flash Erase Subroutine 22 11 1 ROM Library 23 1 1 Fixed Point ROM Library 23 3 1 P Controller Routine 23 3 1 PI Controller Routine 23 4 1 PT1 24 Controller Routine 23 6 1 PT1 32 Controller Routine 23 7 1 Clarke Transform Routine 23 8 1 LED and Touch Sense Controller ROM Library 23 10 1 SET LDLINE CMP Function LED and TS 23 11 1 Inputs for SET LDLINE CMP Function LED only 23 13 1 Inputs for SET LDLINE CMP Function Touch sense only 23 15 1 Inputs for SET LDLINE CMP Function LED and TS 23 17 1 FINDTOUCHEDPAD Function TS 23 21 1 Outputs of Function 23 27 1 Implementation Details of Function 23 30 1 Use of the functions in Interrupts 23 37 1 MDU ROM Library MATH 23 39 1 In
205. 1 2Vref vssp measurement2 vsd Figure 21 14 Single ended measurement with internal 1 2V voltage reference and Vssp The reference selection for each input channel is selected by programming ADC CHCTRx REFSEL bits Please note that a minimum time of 50 usec is needed between conversions when this mode is used User s Manual 21 47 V1 0 2010 02 ADC V2 1 Cinfineon Analog to Digital Converter 21 8 2 Channel Parameters Each analog input channel is configured by its associated channel control register The sample time and the result width are selected via an input class The Channel Control Registers select the control parameters for each input channel it contain bits to select the targetted result register selection of internal reference voltages controls the limit check mechanism and boundary flags ADC CHCTRx x 0 2 Channel x Control Register CA x 1 Reset Value 00 RMAP 0 PAGE 1 7 6 5 4 3 2 1 0 BFEN LCC REFSEL RESRSEL rw mo rw rw Field Bits Type Description RESRSEL 1 0 rw Result Register Selection This bit field defines which result register will be the target of a conversion of this channel 00 The result register 0 is selected 01 result register 1 is selected 10 result register 2 is selected 11 result register 3 is selected REFSEL 3 2 rw Reference Input Selection This bit field defines the reference source for this channel
206. 1 Receive data byte transmit ACK 784 Arbitration lost Same as for code 68 Same as for code 684 general call address received ACK transmitted BO Arbitration lost Write byte to DATA clear Transmit last byte receive SLA received IFLG 0 ACK transmitted Or write byte to DATA Transmit data byte receive clear IFLG AAK 1 ACK If 10 bit addressing is being used the slave is first addressed using the full 10 bit address plus the Write bit The master then issues a restart followed the first part of the 10 bit address again but plus the Read bit after which the status code will be 40 or 48 It is the responsibility of the slave to remember that it had been selected prior to the restart If a repeated START condition has been transmitted the status code will be 10 instead of 08 User s Manual 17 11 V1 0 2010 02 IIC V1 1 Cinfineon Inter IC Bus After each data byte has been received IFLG will be set and one of three status codes will be in the STAT register Table 17 10 Status Code after Data is Received in Master Receive Mode Code IIC State CPU Response Next IIC Action 50 Data byte received Read DATA clear IFLG Receive data byte transmit ACK transmitted 0 not ACK Or read DATA clear IFLG Receive data byte transmit 1 58 Data byte received Read DATA set STA clear Transmit repeated START not ACK transmitted IFLG
207. 10 Unused 113 ADC channel 2 boundary limit check event IST12HR 7 6 Input Select for T12HR This bit field defines the input signal used as T12HR input 00 of the input pin for T12HR 7 0 01 CCU6 SR2 output 10 CCU6 SR3 output 11 ADC channel event 1 The selection of T12HR 7 0 can be done by bit IST12HR1 in MODIPISEL3 register from SCU module PISEL2 Port Input Select Register 2 A44 Reset Value 00 RMAP 0 PAGE 3 7 6 5 4 3 2 1 0 0 IST13HR rw User s Manual 20 129 V1 0 2010 02 CCUG V4 0 Cinfineon XC82x Capture Compare Unit 6 CCU6 Field Bits Type Description IST13HR 1 0 rw Input Select for T13HR This bit field defines the input signal used as T13HR input 00 Any of the input pin for T13HR 7 0 01 CCU6 SR2 output 10 CCU6 SR3 output 11 ADC channel event 0 7 2 reserved returns 0 if read should be written with 0 1 The selection of T13HR 7 0 be done by bit ISTT3HR1 in MODIPISEL3 register from SCU module User s Manual CCU6 V4 0 20 130 V1 0 2010 02 Cinfineon XC82x Capture Compare Unit 6 CCU6 20 11 Register Mapping The addresses of the kernel SFRs are listed in Table 20 16 Table 20 16 SFR Address List for Pages 0 3 Address Page 0 Page 1 Page 2 Page 3 9AH CC63SRL CC63RL T12MSELL MCMOUTL 9BH
208. 10 3 5 10 3 6 10 4 10 4 1 10 4 1 1 10 4 1 2 10 4 1 3 10 4 2 10 4 3 10 5 10 5 1 10 6 Watchdog Timer Registers 8 7 1 Interrupt System 9 1 1 Interrupt Sources 1 9 1 1 Interrupt Source and 9 8 1 Interrupt Source and Priority 9 9 1 Interrupt Structure 2 soe eee eee E ERR ER 9 10 1 Interrupt Structure 1 9 11 1 Interrupt Structure 2 9 11 1 Interrupt Handling 9 12 1 Interrupt Response Time 9 13 1 Registers 2 9 16 1 Interrupt Node Enable Registers 9 17 1 External Interrupt Control Registers 9 20 1 Interrupt Flag Registers 9 23 1 Interrupt Priority Registers 9 30 1 Interrupt Flag Overview 9 32 1 Debug System oss Pa ek eee Ped de 10 1 1 OVerVIBW os cus trs xe Ai ee enced Ae ae UR Ua 10 1 1 Components of the Debug System 10 1 1 Product Specific Information 10 2 1 PINNING
209. 12 1 User s Manual 1 4 V1 0 2010 02 Cinfineon 10 6 1 10 6 2 10 7 10 8 10 8 1 10 8 2 10 8 3 11 11 1 11 1 1 11 1 1 1 11 1 1 2 11 2 11 2 1 11 2 2 11 3 11 3 1 11 3 2 11 4 11 4 1 11 4 2 12 12 1 12 2 12 2 1 12 2 2 12 3 12 3 1 12 3 2 12 3 3 12 3 4 12 3 5 12 3 6 12 3 7 12 4 12 5 12 5 1 12 5 2 12 5 3 13 13 1 NMI request from OCDS 10 12 1 General NMI control byOCDS 10 13 1 NMI mode priority over Debug mode 10 13 1 Registers 10 13 1 Control and Status Registers 10 15 1 Hardware Breakpoint Registers 10 16 1 Monitor Work Register 10 19 1 Parallel Ports 11 1 1 General Port Operation 11 1 1 General Register Description 11 5 1 Register Map thee Sami ext be Pa ek son RUE 11 5 1 Register Overview 11 6 1 11 12 1 FUNCIONS PD 11 12 1 Registers Description 11 17 1 11 22 1 FUNCIONS hese ah apu eem EY ees 11 23 1 Registers Description
210. 2 ROM Library V0 5 82 ROM Library L i X AIA A ssed Mo 280 925 24y 4 Bi ene Hs Eror 4 5 4 Eray 4 POPLIP 3 E C 250 047 did Loana Bopa Infineon dreind V1 0 2010 02 23 22 Figure 23 7 FINDTOUCHEDPAD Function SFR Settings User s Manual ROM Library V0 5 Cinfineon ROM Library This function calculates a running average for each Pad Turn to eliminate any spurious peaks and troughs in the pad frequencies and to create a stable value from which the trip points can be calculated The average is derived from the total values from number of samples input AccumulatorCounter and included low pass filter gain input divisor n It then takes the stored average and calculates a trip point by subtracting a value input subtraction m from the average This low trip value will be the determining factor if the key has been touched Status Flags output PadResult PadFlag PadError will be the indication key factors of what is are detected in the function Finding average and low trip values are skipped when at least one of the pad flags is set PADFLAG Status 0x00 Common or di
211. 2 MODPISEL3 CTRAPIS 10 CCU6_PISELOL ISTRP 00 Hall Input Signals User s Manual 20 8 V1 0 2010 02 CCU6 V4 0 Cinfineon XC82x Capture Compare Unit 6 CCU6 Table 20 2 CCU6 Pin Functions and Selection Pin Function Desciption Selected By P0 0 CCPOSO 0 Input signals for CCPOSO CCU6_PISELOH ISPOSO 00 P2 0 CCPOSO 1 CCU6_PISELOH ISPOSO 01 P2 3 50 2 CCU6_PISELOH ISPOSO 10 P0 1 CCPOS1_0 Input signals for CCPOS1 CCU6_PISELOH ISPOS1 00 P2 1 CCPOS1 1 CCUG PISELOH ISPOS1 01 P0 2 CCPOS2 0 Input signals for CCPOS2 CCUG PISELOH ISPOS2 00 P2 2 CCPOS2 1 CCUG PISELOH ISPOS2 01 Timer Input Signals PO 0 T12HR 0 Input signals for T12HR MODPISEL3 IST12HR1 000 CCU6_PISELOH IST12HR 00 P2 0 T12HR 2 MODPISEL3 IST12HR1 010 CCU6_PISELOH IST12HR 00 P2 2 T12HR 3 MODPISEL3 IST12HR1 011 CCU6_PISELOH IST12HR 00 PO 1 T13HR_O Input signals for T13HR MODPISEL3 IST13HR1 000 CCU6_PISEL2 IST13HR 00g PO 0 T13HR_1 MODPISEL3 IST13HR1 000 CCU6_PISEL2 IST13HR 00 P2 0 T13HR_2 MODPISEL3 IST13HR1 000 CCU6_PISEL2 IST13HR 00 P2 2 T13HR 3 MODPISEL3 IST13HR1 000 CCU6_PISEL2 IST13HR 00 Compare Output Signals P1 1 CC60 0 Compare outputs for channel P1 ALTSELO P1 0g CC60 P1 ALTSEL1 P1 1 P0 3 CC60 1 PO ALTSELO P3 1 PO ALTSEL1 P3 1g P1 0 COUT60 0 P1 ALTSELO
212. 2 Output Modulation T12 T13 STE12U Shadow STE12D 600001010 T13 ST ontrol Outputs CC6x COUT6x T12 ST STE13U CCU6 05535 Figure 20 35 Multi Channel Mode Block Diagram Figure 20 35 shows the functional blocks for the Multi Channel operation controlled by bit fields in register MCMCTR The event that triggers the update of bit field MCMP is chosen by SWSEL In order to synchronize the update of MCMP to a PWM generated by T12 or T13 bit field SWSYN allows the selection of the synchronization event leading to the transfer from MCMPS to MCMP Due to this structure an update takes place with a new PWM period A reminder flag R is set when the selected switching event occurs User s Manual 20 87 V1 0 2010 02 CCU6 V4 0 Cinfineon Capture Compare Unit 6 CCU6 the event is not necessarily synchronous to the modulating PWM and is cleared when the transfer takes place This flag can be monitored by software to check for the status of this logic block If the shadow transfer from MCMPS to MCMP takes place bit ISH STR becomes set and an interrupt can be generated In addition to the Multi Channel shadow transfer event MCM_ST the shadow transfers for T12 T12 ST and T13 T13_ST can be generated to allow concurrent updates of applied duty cycles for T12 and or T13 modulation and Multi Channel patterns If it is explicitly desired the update takes place immediately with the occurrence of the selecte
213. 2 PCCIP1 PCCIPO PXM PFTO PSSC PADC rw rw rw rw rw rw rw rw Field Bits Type Description PADC 0 rw Priority Level Low Bit for Interrupt Node XINTR6 PSSC 1 rw Priority Level Low Bit for Interrupt Node XINTR7 PFTO 2 rw Priority Level Low Bit for Interrupt Node XINTR8 PXM 3 rw Priority Level Low Bit for Interrupt Node XINTR9 PCCIPO 4 rw Priority Level Low Bit for Interrupt Node XINTR10 PCCIP1 5 rw Priority Level Low Bit for Interrupt Node XINTR11 User s Manual 9 31 V1 0 2010 02 Interrupt System V 2 3 3 Cinfineon Interrupt System Field Bits Type Description PCCIP2 6 rw Priority Level Low Bit for Interrupt Node XINTR12 PCCIP3 7 rw Priority Level Low Bit for Interrupt Node XINTR13 IPH1 Interrupt Priority 1 High Register 9 Reset Value 04 RMAP X PAGE X 7 6 5 4 3 2 1 0 PCCIP3H PCCIP2H PCCIP1H PCCIPOH PXMH PFTOH PSSCH PADCH rw rw rw rw rw rw rw rw Field Bits Type Description PADCH 0 rw Priority Level High Bit for Interrupt Node XINTR6 PSSCH 1 rw Priority Level High Bit for Interrupt Node XINTR7 PFTOH 2 rw Priority Level High Bit for Interrupt Node XINTR8 PXMH 3 rw Priority Level High Bit for Interrupt Node XINTR9 PCCIPOH 4 rw Priority Level High Bit for Interrupt Node XINTR10 PCCIP1H 5 rw Priority Level High Bit for Interrupt Node XINTR11 PCCIP2H 6 rw Priority Level High Bit for Interrupt Node XINTR12 PCCIP3
214. 2010 02 CCU6 V4 0 Cinfineon 20 8 4 XC82x Capture Compare Unit 6 CCU6 Multi Channel Mode Registers Register MCMCTR contains control bits for the multi channel functionality MCMCTR Multi Channel Mode Control Register A7 RMAP 0 PAGE 2 Reset Value 00 7 6 5 4 3 2 1 0 0 SWSYN 0 SWSEL T rw r rw Field Bits Type Description SWSEL 2 0 rw Switching Selection Bit field SWSEL selects one of the following trigger request sources next multi channel event for the shadow transfer MCM_ST from MCMPS to MCMP The trigger request is stored in the reminder flag R until the shadow transfer is done and flag R is cleared automatically with the shadow transfer The shadow transfer takes place synchronously with an event selected in bit field SWSYN 000 No trigger request will be generated 001 Correct Hall pattern detected CM_CHE 010g T13 period match detected while counting up 011 T12 one match while counting down 100 T12 channel 1 compare match detected phase delay function 101 T12 period match detected while counting up 110g reserved no trigger request will be generated 111g reserved no trigger request will be generated User s Manual CCUG V4 0 20 104 V1 0 2010 02 Cinfineon Capture Compare Unit 6 CCU6 Field Bits Type Description SWSYN 5 4 rw Switching Synchronization Bit field SWSYN defines the synchronization
215. 21 45 1 Channel Parameters 21 48 1 Limit Checking 55 nies x Reese nee ee ee Rn 21 52 1 254 ep 21 54 1 Out of Range Comparator 21 57 1 Conversion 0 21 61 1 Channel Events and Interrupts 21 63 1 Conversion Result Handling 21 64 1 Storage of Conversion Results 21 64 1 Wait for Read Mode 21 79 1 Result Events and Interrupts 21 80 1 Data Reduction and Filtering 21 80 1 Interrupt Request Handling 21 83 1 Register 21 89 1 Boot ROM User Routines 22 1 1 Flash Bank Read Mode Status Subroutine 22 2 1 Get 4 Bytes Information 22 3 1 Feature Setting Subroutine 22 4 1 UART Auto Baud Subroutine 22 5 1 VART BSL Routine ke mk RR eee ee sinis 22 6 1 User s Manual 1 11 V1 0 2010 02 Cinfineon 22 6 22 7 22 8 23 23 1 23 1 1 23 1 2 23 1 3 23 1 4 23 1 5 23 2 23 2 1 23 2 1 1 23 2 1 2 23 2 1 3 23 2 2 23 2 2
216. 2EX 5 14 2 5 Module Suspend Control When the On Chip Debug Support OCDS is in Monitor Mode MMCR2 MMODE 1 and the Debug Suspend signal is active MMCR2 DSUSP 1 the timer counter in Timer 2 module in XC82x can be suspended based on the settings of their corresponding module suspend bits in register MODSUSP When suspended only the timer stops counting as the counter input clock is gated off The module is still clocked so that module registers are accessible Refer to Chapter 10 2 4 for the definition of register MODSUSP User s Manual 14 4 V1 0 2010 02 Timer 2 V 1 2 Cinfineon 2 14 3 Basic Timer Operations Timer 2 can be started by using TR2 bit by hardware or software Timer 2 can be started by setting TR2 bit by software If bit T2RHEN is set Timer 2 can be started by hardware Bit T2REGS defines the event on pin T2EX falling edge or rising edge that can set the run bit TR2 by hardware Timer 2 can only be stopped by resetting TR2 bit by software 14 4 Auto Reload Mode The auto reload mode is selected when the bit CP RL2 in register T2CON is zero In this mode Timer 2 counts to an overflow value and then reloads its register contents with a 16 bit start value for a fresh counting sequence The overflow condition is indicated by setting bit TF2 in the T2CON register At the same time an interrupt request to the core will be generated if interrupt is enabled The overflow flag TF2 must
217. 3 15 4 Oscillator 15 2 Registers Description 15 6 RTC registers 15 7 S Schmitt trigger 11 2 Sectorization 4 2 Soft reset 7 7 Special Function Register area 3 1 SSC 18 1 18 27 Baudrate generation 18 15 User s Manual Keyword Index Continous transfer operation 18 14 Data width 18 9 Error detection 18 16 Baud rate error 18 17 Phase error 18 17 Receive error 18 17 Transmit error 18 18 Full duplex operation 18 10 Half duplex operation 18 13 Interrupts 18 16 Operating mode selection 18 8 Register description 18 20 Register map 18 20 Synchronous Serial Interface 18 1 T TCON 13 10 THx 13 10 Timer 0 and Timer 1 Counter 13 1 External control 13 3 Mode 0 13 bit timer 13 5 Mode 1 16 bit timer 13 6 Mode 2 8 bit automatic reload timer 13 7 Mode 3 two 8 bit timers 13 8 Register Description 13 9 Register map 13 9 Timer operations 13 3 Timer overflow 13 3 Timer 2 14 1 Auto Reload mode 14 5 Up Down Count Disabled 14 5 Up Down Count Enabled 14 6 Capture mode 14 8 External interrupt function 14 10 Registers description 14 11 Timer operations 14 5 Timers 0 and 1 Registers IENO 13 13 TCON 13 10 THx 13 10 L 5 V1 0 2010 02 Cinfineon XC82x TLx 13 9 TMOD 13 11 TLx 13 9 TMOD 13 11 Touch Sense Controller 19 1 U 16 1 16 25 Baud rate 16 9 Baud rate generator 16 9 Interrupt requests 16 6 Mode 0 8 bit shift register 16 3 Mode 1 8 bit UART 16 4 Mode 2 9 bit UART 16 6 Mode 3 9 bit UART 16 6 Modes 1
218. 4 Available Wake up Source for Power Down Mode Modules Power Down Mode 1 Power Down Mode 2 RTC wake up Not available Available Clock Failure Not available Not available EXINTO Available Available 1 EXINTO wake up source is selected using bit PMCONO EWS Power Down Mode 1 All peripherial blocks and CPU including the real time clock that operates with the 75 KHz oscillator is stopped 75 KHz oscillator watchdog is also stopped With the clock being turned off the system cannot be awakened by an interrupt or the Watchdog Timer It will be awakened only when it receives an external wake up signal via EXINTO pin by setting bit EWS to 1 The wake up source and wake up type must be selected before the system enters the power down mode The sequence to enter power down mode 1 is Select power down mode 1 by setting bit PMCONO PDMODE to 0g Power down all modules including the 48 MHz and 75 KHz oscillator by setting bit PMCONO PD to 1 Three NOP instructions must be inserted after the bit PMCONO PD is set to 1 This ensures the first instruction after two NOP instructions is executed correctly after wake up from power down mode Power Down Mode 2 In this mode all the modules except those that are described in Table 7 3 are powered down The real time clock that operates with the 75 KHz oscillators is running in the periodic wake up mode and the real time count is maintained However no monitoring User s
219. 6 3 Multiprocessor communication 16 8 Register description 16 19 Register map 16 19 User Identification 5 2 USER 5 1 6 15 Watchdog timer 8 1 8 2 Module suspend control 8 3 Register description 8 7 Servicing 8 4 Watchdog timer reset 7 7 Window boundary 8 4 Wordline address 4 5 Write buffers 4 6 X XRAM 3 1 User s Manual L 6 Keyword Index V1 0 2010 02 Cinfineon XC82x Register Index B BCON 16 22 BGH 16 25 BGL 16 24 CCU6_CC60RH 20 46 CCU6_CC60RL 20 46 CCU6_CC60SRH 20 47 CCU6_CC60SRL 20 47 CCU6_CC61RH 20 46 CCU6_CC61RL 20 46 CCU6_CC61SRH 20 47 CCU6_CC61SRL 20 47 CCU6_CC62RH 20 46 CCU6_CC62RL 20 46 CCU6_CC62SRH 20 47 CCU6_CC62SRL 20 47 CCU6_CC63RH 20 83 CCU6_CC63RL 20 83 CCU6_CC63SRH 20 84 CCU6_CC63SRL 20 84 CCU6_CMPMODIFH 20 54 CCU6_CMPMODIFL 20 53 CCU6_CMPSTATH 20 52 CCU6_CMPSTATL 20 51 CCU6_IENH 20 121 CCU6_IENL 20 120 CCU6_INPH 20 125 CCU6_INPL 20 124 CCU6_ISH 20 113 CCU6_ISL 20 112 CCU6_ISRH 20 118 CCU6_ISRL 20 118 CCU6_ISSH 20 116 CCU6_ISSL 20 116 CCU6_MCMCTR 20 104 CCU6_MCMOUTH 20 109 CCU6_MCMOUTL 20 107 CCU6_MCMOUTSHH 20 106 User s Manual Register Index CCU6_MCMOUTSL 20 106 CCU6_MODCTRH 20 99 CCU6_MODCTRL 20 98 CCU6_PISELOH 20 128 CCU6_PISELOL 20 127 CCU6_PISEL2 20 129 CCU6_PSLR 20 103 CCU6_T12DTCH 20 49 CCU6_T12DTCL 20 49 CCU6_T12H 20 43 CCU6_T12L 20 43 CCU6_T12MSELH 20 55 CCU6_T12MSELL 20 55 CCU6_T12PRH 20 44 CCU6_T12PRL 20 44 CCU6_T13H 20
220. 7 HWBPSR Hardware Breakpoints Select Register 6 Reset value 00 RMAP 1 PAGE X 7 6 5 4 3 2 1 0 0 0 0 BPSEL P BPSEL r r r TW Field Bits Type Description BPSEL 3 0 rw BreakPoint register Select refer to Table 10 7 BPSEL_P 4 w Bit protection 0 BPSEL unchangeable 1 BPSEL can be changed 0 7 5 r Reserved HWBPDR Hardware Breakpoints Data Register F7 Reset value 00 RMAP 1 PAGE X 7 6 5 4 3 2 1 0 HWBPxx rw Field Bits Type Description HWBPxx 7 0 rw Data to be written into read from a HWBPxx register as currently selected by HWBPSR User s Manual 10 16 V1 0 2010 02 OCDS V 2 7 1 Cinfineon Debug System HWBPOL Hardware Breakpoint 0 Low Register written via HWBPDR Reset value 00 7 6 5 4 3 2 1 0 HWBPOL Field Bits Type Description HWBPOL 7 0 The Low Byte from Compare Address HWBPO Hardware Breakpoint 0 High Register written via HWBPDR Reset value 00 7 6 5 4 3 2 1 0 Field Bits Type Description HWBPOH 7 0 The High Byte from Compare Address HWBPO HWBP1L Hardware Breakpoint 1 Low Register written via HWBPDR Reset value 00 7 6 5 4 3 2 1 0 HWBP1L Field Bits Type Description HWBP1L 7 0 The Low Byte from Compare Address HWBP1 User s Manual 10 17 V1 0 2010 02 OCDS
221. 79 CCU6_T13L 20 79 CCU6_T13PRH 20 81 CCU6_T13PRL 20 81 CCU6_TCTROH 20 59 CCU6_TCTROL 20 57 CCU6_TCTR2H 20 63 CCU6_TCTR2L 20 61 CCU6_TCTR4H 20 65 CCU6_TCTR4L 20 64 CCU6_TRPCTRH 20 101 CCU6_TRPCTRL 20 100 CHINCR 21 89 CHINFR 21 87 CHINSR 21 88 CPU Registers EO 2 5 CRCR1 21 23 1 21 21 CRPR1 21 24 E EO 2 5 ETRCR 21 37 EVINCR 21 86 L 8 V1 0 2010 02 Cinfineon EVINFR 21 84 EVINPR 21 58 EVINSR 21 85 EXICONO 9 21 9 22 F FEAH 4 10 FEAL 4 10 G GLOBCTR 21 14 GLOBSTR 21 15 H HWBPOH 10 17 HWBPOL 10 17 HWBP1H 10 18 HWBP1L 10 17 HWBP2H 10 18 HWBP2L 10 18 HWBP3H 10 19 HWBP3L 10 19 HWBPDR 10 16 HWBPSR 10 16 IENO 9 17 IEN1 9 18 17 16 ADDRX 17 17 17 21 17 18 17 17 SRST 17 21 STAT 17 20 INPCRO 21 51 IP 9 30 IP1 9 31 IPH 9 31 IPH1 9 32 IRCONO 9 24 IRCON1 9 24 IRCON2 9 25 User s Manual XC82x L 9 Register Index IRCONS 9 26 L LCBR 21 54 LINST 16 23 LTS COMPARE 19 23 LTS GLOBCTLO 19 21 LTS GLOBCTL1 19 22 LTS LDLINE 19 25 LTS LDTSCTL 19 24 LTS TSCTL 19 26 LTS TSVAL 19 27 M MDU MD4A 12 11 MDU MDUCON 12 12 MDU MDUSTAT 12 14 MDU MDx 12 10 MDU MRA 12 11 MDU MRx 12 10 MMICR 10 15 MMWR2 10 19 RTC CNTO 15 8 RTC_CNT1 15 8 RTC CNT2 15 9 RTC_CNT3 15 9 RTC RTCCRO 15 10 RTC RTCCR1 15 10 RTC RTCCR2 15 11 RTC 15 11 MODPISEL1 9 22 16 2 MODPISEL2 13 2 14 2 N NMIC
222. 8 Bits gt gt TOS 1 l TO Control TRO GATEO L L EXINTO 90 Figure 13 1 Timer 0 Mode 0 13 Bit Timer Counter User s Manual 13 5 V1 0 2010 02 Timer 0 and 1 V1 0 Cinfineon 0 1 13 42 Mode 1 Mode 1 operation is similar to that of mode 0 except that the timer register runs with all 16 bits Mode 1 operation for Timer 0 is shown in Figure 13 2 fta 708 0 THO um e 8Bits gt interrupt TOS 1 I TO Control TRO amp 1 GATEO 5i EXINTO Figure 13 2 Timer 0 Mode 1 16 Bit Timer Counter User s Manual 13 6 V1 0 2010 02 Timer 0 and 1 V1 0 Cinfineon 0 1 1343 Mode 2 In Mode 2 operation the timer is configured as 8 bit counter TLx with automatic reload as shown in Figure 13 3 for Timer An overflow from TLx not only sets TFx but also reloads TLx with the contents of THx that has been preset by software The reload leaves THx unchanged Interrupt uo GATEO EXINTO Treo Mose Figure 13 3 Timer 0 Mode 2 8 Bit Timer Counter with Auto Reload User s Ma
223. A Acknowledge Block Type Error Checksum Error E Acknowledge Block Type Error Checksum Error The responses are defined in Table 6 5 which lists the possible reasons and or implications for error and suggests the possible corrective actions that the host can take upon notification of the error User s Manual 6 7 V1 0 2010 02 Cinfineon Boot Loader 6 5 Definitions of Responses Response Value Description Block BSL Reasons Implications Corrective Type Mode Action Acknow 55 Head 1 3 The requested operation will ledge er be performed once the response is sent 6 A The requested operation has EOT 024 been performed and is successful All others Reception of the Block is successful Transmission of IDs follow in Mode A Ready to receive the next Block Block FF All others Either the Block Type is Retransmit a valid Error undefined or option is invalid Block or the flow is invalid Checksum FE There is a mismatch between Retransmit a valid Error the calculated and the Block received Checksum 6 2 2 The Selection of Working Modes When the UART BSL routine enters Phase ll it first waits for an eight byte long header block from the host The header block contains the information for the selection of the working modes Depending on this information the UART BSL routine selects and activates the desired w
224. Alternate Select Register 0 PO ALTSEL1 Port 0 Alternate Select Register 1 PO ALTSEL2 Port 0 Alternate Select Register 2 11 2 1 Functions Port 0 input and output functions are shown in Table 11 4 Table 11 4 Port 0 Input Output Functions Port Pin Input Output Select Connected Signal s From to Module P0 0 Input GPI PO DATAIN PO ALT1 T2 0 Timer 2 ALT2 T13HR 1 CCUG ALT3 MTSR 2 SSC ALTA MRST 3 SSC ALT5 T12HR 0 CCUG ALT6 CCPOSO 0 CCUG TSINO LEDTSCU Output GPO PO DATAOUT PO ALT1 LINEO TSINO LEDTSCU ALT2 MTSR 2 SSC ALT3 COUT61 1 CCUG User s Manual 11 12 V1 0 2010 02 Cinfineon XC82x Table 11 4 Port 0 Input Output Functions cont d Parallel Ports Port Pin Input Output Select Connected Signal s From to Module PO 1 Input PO DATAIN P1 ALT1 TO 0 Timer 0 ALT2 CC61 1 CCUG ALT3 MTSR 3 SSC ALTA MRST 2 SSC ALT5 T13HR 0 CCUG ALT6 CCPOS1 0 CCUG TSIN1 LEDTSCU Output GPO PO DATAOUT P1 ALT1 LINE1 TSIN1 LEDTSCU ALT2 MRST_2 SSC ALT3 CC61 1 CCUG P0 2 Input GPI PO DATAIN P2 ALT1 T1 0 Timer 1 ALT2 CC62 1 CCUG ALT3 SCL 1 ALT4 ALT5 ALT6 CCPOS2_0 CCU6 TSIN2 LEDTSCU Output GPO PO DATAOUT P2 ALT1 LINE2 TSIN2 LEDTSCU ALT2 SCL_1 ALT3 CC62_1 CCU6 User s Manual 11 13 V1 0 2010 02 Cinfineon XC82x Table 11 4 Port 0 Input Output
225. BR 0000 or 6 MBaud in Slave Mode with lt BR gt 0001 Table 18 3 lists some possible baud rates together with the required reload values and the resulting bit times assuming a module clock of 24 MHz User s Manual 18 15 V1 0 2010 02 SSC V1 4 Cinfineon XC82x High Speed Synchronous Serial Interface Table 18 3 Typical Baud Rates of the SSC fiw 24 MHz Reload Value Baud Rate fus cikiss_cLk Deviation 0000 12 MBaud only Master Mode 0 0 0001 6 MBaud 0 0 0005 2 MBaud 0 096 000B 1 MBaud 0 096 0017 500 kBaud 0 0 0077 100 kBaud 0 0 FFFF 183 11 Baud 0 0 18 3 6 Error Detection Mechanisms The SSC is able to detect four different error conditions Receive Error and Phase Error are detected in all modes Transmit Error and Baud Rate Error apply only to Slave Mode When an error is detected the respective error flag is can be set and an error interrupt request will be generated by activating the EIR line see Figure 18 6 if enabled The error interrupt handler may then check the error flags to determine the cause of the error interrupt The error flags are not reset automatically but rather must be cleared by software after servicing This allows servicing of some error conditions via interrupt while the others may be polled by software Note The error interrupt handler must clear the associated enabled error flag s to prevent User s Manual SSC V1 4
226. BSY minimum two clock cycles after transmit data is written into TB Therefore it is not recommended to poll CON BSY to indicate the start and end of a single transmission Instead interrupt service routine should be used if interrupts are enabled or the interrupt flags IRCONT1 TIR and IRCONT RIR should be polled if interrupts are disabled Note Only one SSC etc can be master at a given time The transfer of serial data bits can be programmed in many respects The data width can be specified from 2 bits to 8 bits Atransfer may start with either the LSB or the MSB The shift clock may be idle low or idle high The data bits may be shifted with the leading edge or the trailing edge of the shift clock signal The baud rate may be set from 183 11 Baud up to 12 MBaud 24 MHz module clock The shift clock can be generated MS CLK or can be received 55 CLK These features allow the adaptation of the SSC to a wide range of applications requiring serial data transfer The Data Width Selection supports the transfer of frames of any data length from 2 bit characters up to 8 bit characters Starting with the LSB CON HB 0 allows communication with SSC devices in Synchronous Mode or with 8051 like serial interfaces for example Starting with the MSB CON HB 1 allows operation compatible with the SPI interface Regardless of the data width selected and whether the MSB or the LSB is transmitted first the transfer data i
227. C T2 0 a count clock of 712 if prescaler is disabled is used for the count operation If C T2 1 Timer 2 behaves as a counter that counts 1 to 0 transitions of input pin T2 The counter samples pin T2 over 2 PCLK clock cycles If a 1 was detected during the first clock and a 0 was detected in the following clock then the counter increments by one Therefore the input levels should be stable for at least 1 clock If bit T2RHEN is set Timer 2 can be started by the falling edge rising edge on pin 2 which is defined by bit T2REGS Note The C501 compatible feature requires a count resolution of at least 24 clocks User s Manual 14 9 V1 0 2010 02 Timer 2 V 1 2 Cinfineon Timer 2 14 7 External Interrupt Function While the timer counter function is disabled TR2 0 it is still possible to generate a Timer 2 interrupt to the core via an external event at T2EX as long as Timer 2 remains enabled 1 2 DIS 0 To achieve this bit EXEN2 in register T2CON must be set As a result any transition on T2EX will cause either a dummy reload or a dummy capture depending on the CP RL2 bit selection By disabling the timer counter function T2EX can be alternatively used to provide an edge triggered rising or falling external interrupt function with bit EXF2 serving as the external interrupt flag User s Manual 14 10 V1 0 2010 02 Timer 2 V 1 2 Cinfineon Timer 2 14 8 Registers Description
228. C6xR if enabled by bit ENCC6xR or for bit CC6xF if enabled by bit ENCC6xF 00 Service request output SRO is selected 01 Service request output SR1 is selected 10g Service request output SR2 is selected 11g Service request output SR3 is selected INPCHE 7 6 rw Interrupt Node Pointer for the CHE Interrupt This bit field defines the service request output activated due to a set condition for bit CHE if enabled by bit ENCHE of for bit STR if enabled by bit ENSTR Coding see User s Manual 20 124 V1 0 2010 02 CCUG V4 0 Cinfineon Capture Compare Unit 6 CCU6 INPH Interrupt Node Pointer Register High 9F Reset Value 39 RMAP 0 PAGE 2 7 6 5 4 3 2 1 0 0 INPT13 INPT12 INPERR r rw rw rw Field Bits Type Description INPERR 1 0 rw Interrupt Node Pointer for Error Interrupts This bit field defines the service request output activated due to a set condition for bit TRPF if enabled by bit ENTRPF or for bit WHE if enabled by bit ENWHE Coding see INPCC6x INPT12 3 2 rw Interrupt Node Pointer for Timer12 Interrupts This bit field defines the service request output activated due to a set condition for bit T12OM if enabled by bit ENT12OM or for bit T12PM if enabled by bit ENT12PM Coding see INPCC6x INPT13 5 4 rw Interrupt Node Pointer for Timer13 Interrupt This bit field defines the service request output activated due to a set cond
229. C6xSR that is preloaded by software and transferred into the compare register when signal T12 shadow transfer T12_ST gets active Providing a shadow register for the compare value as well as for other values related to the generation of the PWM signal facilitates a concurrent update by software for all relevant parameters of a three phase PWM User s Manual 20 25 V1 0 2010 02 CCU6 V4 0 82 Cinfineon 20 3 3 2 Channel State Bits Associated with each compare channel is a State Bit CMPSTATL CC6xST holding the status of the compare or capture operation see Figure 20 10 In compare mode the State Bits are modified according to a set of switching rules depending on the current Capture Compare Unit 6 CCU6 status of timer T12 T12 Counter TEM CCce0 R 1 To Interrupt CCPOSO Switching e Control Rule rd Logic State Bit To Dead_Time CC60 CC60ST Counter 0 CC61 CCPOS1 Q To Interrupt Switching CLR Control Rule Compare cw 61 Logic State Bit To Dead Time Channel CC61ST a CC61 Counter 1 MSEL61 MCC61S R CC62 ccPos2 d To Interrupt Switching ee Control Rule Compare 62 Logic State Bit To Dead_Time Channel oa CC62ST Counter 2 CCU6_MCB05514 Figure 20 10 Compare State Bits for Compare Mode The inputs to the switching rule logic for the CC6xST bits are the timer direction CDIR the timer run bit T12R the timer T12 zer
230. CONDS Clock Count Register 0 Mode 0 Type rwh 1 RTC_CNTO Reset 004 Bit Fie CNT_VAL Clock Count Register 0 Modes 1 and 3 Type rwh E2u RTC CNT1 Reset 004 Bit Fie 0 SECONDS Clock Count Register 1 Modes 0 and 2 Type r rwh E2u RTC CNT1 Reset 004 Bit Fie CNT_VAL Clock Count Register 1 Modes 1 and 3 Type rwh E3H RTC_CNT2 Reset 004 Bit Fie 0 MINUTES Clock Count Register 2 Modes 0 and 2 Type rwh 2 Reset 004 Bit Fie CNT_VAL Clock Count Register 2 Modes 1 and 3 Type rwh E44 RTC_CNT3 Reset 004 Bit Fie 0 HOURS Clock Count Register 3 Modes 0 and 2 Type r rwh E44 RTC_CNT3 Reset 004 Bit Fie CNT VAL Clock Count Register 3 Modes 1 and 3 Type rwh E5y RTC_CNT4 Reset 004 Bit Fie DAYS Clock Count Register 4 Modes 0 and 2 Type rwh E6y RTC CNT5 Reset 004 Bit Fie 0 DAYS Clock Count Register 5 Modes 0 and 2 Type r IW E7u RTCCRO Reset 00 Bit Fie 0 CC MSECS Real Time Clock Compare Capture Register 0 Type r rwh Mode 0 E7y RTCCRO Reset 004 Bit Fie CC_VAL Real Time Clock Compare Capture Register 0 Type rwh Modes 1 and 3 User s Manual 3 24 V1 0 2010 02 Memory Organization V 0 1 Infineon XC82x Memory Organization Table 3 7 RTC Register Overview cont d Addr Register Name Bit 7 6 4 3 2 1 0 E94 RTC_RTCCR1 Reset 004 Bit Fie 0 CC_SECONDS Real Time
231. CU6 input i CC61 6 SR2 output CCU6_PISELOL ISCC61 10 CCU6_SR2 ADC_BF1 ADC boundary event 1 CCU6_PISELOL ISCC61 11 User s Manual CCU6 V4 0 20 15 V1 0 2010 02 Cinfineon XC82x Table 20 6 CCU6 Inputs Interconnection Capture Compare Unit 6 CCU6 CCU6 Function Signal Connected Other Module Function Signal Selected By CCU6 input i CC62 CCU6 SR2 output CCU6_PISELOL ISCC62 10 CCU6_SR2 ADC Boundary event 2 CCU6_PISELOL ISCC62 11 ADC_BF2 CCU6 input i T12HR CCU6 SR2 output CCUG PISELOH IST12HR 01 CCU6_SR2 CCU6 SR3 output CCU6_PISELOH IST12HR 10 CCU6_SR3 ADC Channel event CCU6_PISELOH IST12HR 11 ADC_CHEV ORC event 0 0 MODPISEL3 IST12HR1 001 ORCEVENTO CCU6_PISELOH IST12HR 00 ORC event 2 0 MODPISEL3 IST12HR1 100 ORCEVENT2 CCU6_PISELOH IST12HR 00 CCU6 input i TI3HR CCU6 SR2 output CCUG PISEL2 IST13HR 01 CCU6_SR2 CCU6 SR3 output CCU6_PISEL2 IST13HR 10g CCU6_SR3 ADC Channel event CCU6_PISEL2 IST13HR 11 ADC_CHEV ORC event 2 0 MODPISEL3 IST13HR1 100 ORCEVENT2 CCUG PISEL2 IST13HR 00g CCU6 input i CTRAP ORC event MODPISEL3 CTRAPIS 11 CCU6_PISELOL ISTRP 00 ADC Channel event 0 CCU6_PISELOL ISTRP 11 ADC CHEVO CCU6 input i ADC boundary event 0
232. C_VFCR Reset 004 Bit Field VFC3 VFC2 VFC1 VFCO Valid Flag Clear Register Type w w w w CFH ADC_ALRO Reset 004 Bit Field 0 0 ALIASO Alias Register 0 Type r r TW D2u ADC CNF Reset 004 Bit Field CNF3 CNF2 CNF1 CNFO Configure Out of Range Comparator Register Type UM DN FW dod D3H ADC_ETRCR Reset 004 Bit Field 0 ETRSEL1 ETRSELO External Trigger Control Register Type i dud id RMAP 0 PAGE 5 ADC_CHINFR Reset 004 Bit Field CHINF CHINF CHINF CHINF Channel Interrupt Flag Register 3 2 1 0 rh rh rh rh CBH ADC CHINCR Reset 004 Bit Field CHINC CHINC CHINC CHINC Channel Interrupt Clear Register 3 2 1 0 w w w w CCH ADC_CHINSR Reset 004 Bit Field CHINS CHINS CHINS CHINS Channel Interrupt Set Register 3 2 1 0 w w w w ADC_EVINFR Reset 004 Bit Field EVINF EVINF EVINF EVINF 0 EVINF EVINF Event Interrupt Flag Register 7 6 5 4 1 0 Type rh rh rh rh r rh rh ADC_EVINCR Reset 004 Bit Field EVINC EVINC EVINC EVINC 0 EVINC EVINC Event Interrupt Clear Flag 7 6 5 4 1 0 Register Type w w w w r w w D2u ADC EVINSR Reset 004 Bit Field EVINS EVINS EVINS EVINS 0 EVINS EVINS Event Interrupt Set Flag Register 7 6 5 4 1 0 Type w w w w r w w RMAP 0 PAGE 6 ADC_CRCR1 Reset 00 Bit Field CH3 CH2 CH1 CHO Conversion Request Control Register 1 Type rwh rwh rwh rwh CBH ADC_CRPR1 Reset 00 Field CHP3 CHP2 CHP1 CHPO Conversion
233. Cinfineon 13 2 13 2 1 13 2 2 13 2 3 13 3 13 4 13 4 1 13 4 2 13 4 3 13 4 4 13 5 13 5 1 14 14 1 14 2 14 2 1 14 2 2 14 2 3 14 2 4 14 2 5 14 3 14 4 14 4 1 14 4 2 14 5 14 6 14 7 14 8 14 8 1 14 8 2 14 8 3 14 8 4 15 15 1 15 2 15 2 1 15 2 2 15 2 3 15 3 15 4 15 5 15 5 1 System Information 13 1 1 PINNING 22555550005 s XE RU TUUS afe s 13 1 1 Clocking 13 2 1 Interrupt Events and Assignment 13 2 1 Basic Timer Operations 13 3 1 Timer MOSS 13 4 1 elu m CC 13 5 1 oL erent gos nee Mentan eee ee em are 13 6 1 Secs Shh we Shee qid dau er 13 7 1 Mod Sr sucus eee are eth ee ae eee eee 13 8 1 Registers 13 9 1 Timer 0 and Timer 1 Registers 13 9 1 Timer2 50 idR bn ESSE ae er Rene Reed 14 1 1 OM os cop dete as c 14 1 1 System Information 14 1 1 PINNING 212225 vica RE ak adeat ados RR Rua TR UR E 14 1 1 Clocking 14 3 1 Interrupt Events and 14 3
234. Cinfineon Never stop thinking 8 Bit XC82x 8 Bit Single Chip Microcontroller User s Manual V1 0 2010 02 Microcontrollers Edition 2010 02 Published by Infineon Technologies AG 81726 Munich Germany 2010 Infineon Technologies AG All Rights Reserved Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics With respect to any examples or hints given herein any typical values stated herein and or any information regarding the application of the device Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind including without limitation warranties of non infringement of intellectual property rights of any third party Information For further information on technology delivery terms and conditions and prices please contact the nearest Infineon Technologies Office www infineon com Warnings Due to technical requirements components may contain dangerous substances For information on the types in question please contact the nearest Infineon Technologies Office Infineon Technologies components may be used in life support devices or systems only with the express written approval of Infineon Technologies if a failure of such components can reasonably be expected to cause the failure of that life support device or system or to affect the safety or effectiveness of that device or system Life support d
235. DGESEL 5 rw Edge Select in Capture Mode Reload Mode Og falling edge at Pin T2EX is selected 1g rising edge at Pin T2EX is selected T2RHEN 6 rw Timer 2 External Start Enable Og Timer 2 External Start is disabled 1g 2 External Start is enabled User s Manual 14 12 V1 0 2010 02 Timer 2 V 1 2 XC82x Cinfineon Timer 2 Field Bit Type Description T2REGS 7 rw Edge Select for Timer 2 External Start Og falling edge at Pin T2EX is selected 1 rising edge at Pin T2EX is selected 14 8 2 Control Register Control register T2CON is used to control the operating modes and interrupt of Timer 2 In addition it contains the status flags for interrupt generation T2 T2CON Timer 2 Control Register Reset Value 00 RMAP 0 PAGE X 7 6 5 4 3 2 1 0 TF2 EXF2 0 0 EXEN2 TR2 C T2 CP RL2 rwh rwh r r rw rwh rw rw Field Bit Type Description CP_RL2 0 rw Capture Reload Select Og Reload upon overflow or upon negative positive transition at pin 2 when 2 1 1g Capture Timer 2 data register contents on the negative positive transition at pin T2EX provided EXEN2 1 The negative or positive transition at Pin T2EX is selected by bit EDGESEL C_T2 1 rw Timer or Counter Select Og Timer function selected 1g Count upon negative edge at pin T2 TR2 2 rwh 2 Start Stop Control
236. DTS counter by clearing prescaler MOV LTS GLOBCTLO 0b01XXXXXX User s Manual 19 15 V1 0 2010 02 LEDTSCU V 1 2 1 Cinfineon LED Touch Sense Controller Interpretation of Bit Field FNCOL The handling by software in each time slice includes to update the line value and compare value to be activated shadow transferred in the next time slice The FNCOL bit field provides information on the function column active in the previous time slice With this information software can determine the active function column in current time slice and prepare the necessary values to be shadow transferred valid for the next time slice Following is an example where six time slices are enabled per time frame with five LED columns and touch sensing enabled Table 19 5 Interpretation of FNCOL Bit Field FNCOL Active Function Column in SW Prepare via Shadow Registers for Current Time Slice Function Column of Next Time Slice 111 LED COL 4 LED COL 3 010 LED COL 3 LED COL 2 011 LED COL 2 LED COL 1 100 LED LED 101 LED COL 0 Touch sense TSIN PADT 110 Touch sense TSIN PADT LED COL 4 19 8 LEDTSCU Timing Calculations LEDTSCU main timing or duration formulation are provided in following Count Rate CR 19 1 CR fCLK PREscaler Time slice duration TSD 19 2 TSD 28 CR Time frame duration 19 3 TimeFrameDuration Number of time
237. D_EN TS_EN CLK_PS H H Global Control Register 0 Type TW rw rw D4u LTS COMPARE Reset 00 Bit Fie SHD CMP Time Slice Compare Shadow Register Type TW D5H LTS_LDLINE Reset 004 Bit Fie SHD LINE LED Line Pattern Shadow Register Type tw LTS_LDTSCTL Reset 00 Bit Fie NR_LEDCOL COL NR_PADT TSO LED and Touch sense Control LEV EXT Register Type rw rw rw TW D7y LTS_TSCTL Reset 004 Bit Fie TS TS TS PADT PADT Touch sense Control Register CTR CTRR CTR PULL SW OVL SAT Type TW rw rw rw rw rwh D8y LTS GLOBCTL1 Reset 004 Bit Fie TSF ITS TFF ITF CLK FNCOL Global Control Register 1 BEN EN SEL Type rwh rw rwh rw rw rh D9H LTS_TSVAL Reset 004 Bit Fie TSCTRVAL Touch sense Counter Value Register Type rwh User s Manual 3 23 V1 0 2010 02 Memory Organization V 0 1 Infineon XC82x 3 4 5 7 RTC Registers Memory Organization The RTC SFRs can be accessed in the standard memory area RMAP 0 Table 3 7 RTC Register Overview Addr Register Name Bit 7 6 5 4 3 2 1 0 IRMAP 0 95H RTC_RTCON Reset 008 Bit Fie SFRT CRFT ESRT CRT RTCC RTM RTCC Real Time Clock Control u Regist rwh rwh rw rw rwh rw rw 96H RTC_RTCON1 Reset 024 Bit Fie 0 RTYR Real Time Clock Control Register 1 Type r b 1 RTC_CNTO Reset 004 Bit Fie 0 MILLISE
238. E2 DTE1 DTEO Dead Time Control Register for Timer T12 High Type r rh rh rh r TW rw rw A6H CCU6_TCTROL Reset 004 Bit Fie CTM CDIR STE1 T12R T12 T12CLK Timer Control Register 0 Low 2 PRE Type rw rh rh rh rw TW CCU6_TCTROH Reset 004 Bit Fie 0 STE1 T13R T13 T13CLK Timer Control Register 0 High 9 f rh rh rw rw FAH CCU6_CC60RL Reset 004 Bit Fie CC60VL Capture Compare Register for Channel CC60 Low Type rh CCU6_CC60RH Reset 00 Bit Fie CC60VH Capture Compare Register for Channel CC60 High Type rh FCH CCU6_CC61RL Reset 00 Bit Fie CC61VL Capture Compare Register for Channel CC61 Low Type m FDH CCU6_CC61RH Reset 004 Bit Fie CC61VH Capture Compare Register for Channel CC61 High Type rh FEH CCU6_CC62RL Reset 004 Bit Fie CC62VL Capture Compare Register for Channel CC62 Low Type rh CCU6_CC62RH Reset 00 Bit Fie CC62VH Capture Compare Register for Channel CC62 High Type rh RMAP 0 PAGE 2 DAY CCU6_T12MSELL Reset 00 Bit Fie MSEL61 MSEL60 T12 Capture Compare Mode Select Register Low Type TW bd CCU6_T12MSELH Reset 004 Bit Fie DBYP HSYNC MSEL62 T12 Capture Compare Mode Select Register High Type rw wW 9CH CCU6_IENL Reset 004 Bit Fie ENT1 ENT1 ENCC ENCC ENCC ENCC ENCC ENCC Capture Compare Interrupt Enable 2 2 62 62R 61F 61R 60F 60R Register Low PM OM Type TW rw rw rw rw TW rw rw User s Manual 3 28 V1 0 2010 02 Memory Organization V 0 1
239. EL edge detection T12 Control 71255 amp Status T12RES detection Clock Selection T12 ZM 712 gt 712 PM Read from A T12PR Period Register T12_ST Write to Period Shadow T12PR Register 8 BIT_8BIT_CCU6_MCA05508 Figure 20 4 Timer T12 Logic and Period Comparators Via a comparator the T12 counter register T12L T12H is connected to a Period Register T12PRL T12PRH This register determines the maximum count value for T12 In Edge Aligned mode T12 is cleared to 0000 after it has reached the period value User s Manual 20 19 V1 0 2010 02 CCU6 V4 0 Cinfineon Capture Compare Unit 6 CCU6 defined by T12PR In Center Aligned mode the count direction of T12 is set from up to down after it has reached the period value please note that in this mode T12 exceeds the period value by one before counting down In both cases signal T12 PM T12 Period Match is generated The Period Register receives a new period value from its Shadow Period Register A read access to T12PR delivers the current period value at the comparator whereas a write access targets the Shadow Period Register to prepare another period value The transfer of a new period value from the Shadow Period Register into the Period Register see Section 20 3 6 is controlled via the T12 Shadow Transfer control signal T12 ST The generation of this signal depends on the
240. EN Enable TSIN x for Hardware over rule on sense Touch oscillation pad turn x for active sense All other TSIN pins duration output LINE value Enable pull up this over rule can be disabled by bit Passive level on EPULL COL the rest except Enable open drain 1 1 For the other pad inputs not on turn there is no HW over rule which means the GPIO SFR setting is active User s Manual 19 18 V1 0 2010 02 LEDTSCU V 1 2 1 Cinfineon XC82x LED and Touch Sense Controller Definition GP 0 function by SFR control LEDTS outputsignal Its fn amp amp pad turn x ts extended x Touch sense enable over rule amp amp pad turn x Touch sense disable pull over rule Touch sense pull up only PUDENSSEL Pull Control Touch sense open drain enable Open Drain Control ALTSELx v Alternate Select Pull id line x T Device AltDataOut LED amp T S Output AltDataOut N Driver gt lt Input Driver Schmitt Trigger Pad LED line Touchsense pad x Figure 19 5 Over rule Control on Pad Input Pin for Touch Sense Function 19 10 Interrupt There are two interrupts triggered by LEDTSCU kernel 1 time slice event 2 time frame event The flags are set on event or when CLK PS is set from 0 regardless of whether the correspond
241. ENO and IEN1 Register IENO also contains the global interrupt masking bit EA which can be cleared to block all pending interrupt requests at once The NMI interrupt vector is shared by a number of sources each of which can be enabled or disabled individually via register NMICON After reset the enable bits in IENO IEN1 and NMICON are cleared to 0 This implies that all interrupt nodes are disabled by default IENO Interrupt Enable Register 0 8 Reset Value 00 RMAP X PAGE X 7 6 5 4 3 2 1 0 EA 0 ET2 ES ET1 EX1 ETO rw r rw rw rw rw rw rw Field Bits Type Description EX0 0 rw Interrupt Node XINTRO Enable 0 XINTRO is disabled 1 XINTRO is enabled 1 rw Interrupt Node XINTR1 Enable 0 XINTR1 is disabled 1 XINTR1 is enabled EX1 2 rw Interrupt Node XINTR2 Enable 0 XINTR2 is disabled 1 XINTR2 is enabled ET1 3 rw Interrupt Node XINTR3 Enable 0 XINTR3 is disabled 1 XINTR3 is enabled ES 4 rw Interrupt Node XINTR4 Enable 0 XINTR4 is disabled 1 XINTR4 is enabled ET2 5 rw Interrupt Node XINTR5 Enable 0 XINTR5 is disabled 1 XINTRS is enabled User s Manual 9 17 V1 0 2010 02 Interrupt System V 2 3 3 Cinfineon XC82x Interrupt System Field Bits Type Description EA 7 rw Global Interrupt Mask 0 All pending interrupt requests except NMI are blocked from the
242. Enable Bit Event Flag Bit RTC compare wake up RTCON ECRTC RTC_RTCON CFRTC RTC second time RTC_RTCON ESRTC RTC_RTCON SFRTC Table 15 3 shows the interrupt node assignment for each RTC interrupt source User s Manual 15 1 V1 0 2010 02 RTC V1 0 Cinfineon Real Time Clock Table 15 3 RTC Events Interrupt Node Control Event Interrupt Node Interrupt Node Flag Vector Enable Bit Bit Address RTC compare wake up IEN1 EXM 4B RTC second time 15 2 3 Module Suspend Control When the On Chip Debug Support OCDS is in Monitor Mode MMCR2 MMODE 1 and the Debug Suspend signal is active MMCR2 DSUSP 1 the timer counter in RTC module in XC82x can be suspended based on the settings of their corresponding module suspend bits in register MODSUSP The definition of this register is described in Chapter 10 2 4 When suspended only the timer stops counting as the counter input clock is gated off The module is still clocked so that module registers are accessible 15 3 Oscillators The 75 KHz internal oscillator can be used to clock the RTC It is also used to clock an oscillation watchdog to monitor the 48 MHz oscillation which is the source of the system frequency Once power up the oscillator can operate irrespective of the state of the microcontroller That is it keeps running even when the device has entered idle or power down mode 2 The oscillator as well as the whole real time clo
243. FO 0 IDLE Power Control Register Type TW r rw rw r TW 881 TCON Reset 004 Bit Field TF1 TR1 TFO TRO IE1 IT1 IEO ITO Ti Control Regist rwh rw rwh rw rwh rw rwh TW B94 TMOD Reset 00 Bit Field GATE T1S T1M GATE TOS TOM Timer Mode Register 1 0 Type TW rw TW TW rw TW TLO Reset 0 Bit Field VAL Timer 0 Register Low Type rwh BBH TL1 Reset 004 Bit Field VAL Timer 1 Register Low Type rwh BCH THO Reset 004 Bit Field VAL Timer 0 Register High Type rwh BDH TH1 Reset 004 Bit Field VAL Timer 1 Register High Type rwh 98H SCON Reset 004 Bit Field SMO SM1 SM2 REN TB8 RB8 TI RI Serial Channel Control Register Type rw rw rw rw rw rwh rwh rwh 994 SBUF Reset 004 Bit Field VAL Serial Data Buffer Register Type rwh A2y EO Reset 004 Bit Field 0 TRAP_ 0 DPSE DPSE DPSE Extended Operation Register EN L2 1 LO Type rw r rw rw rw User s Manual 3 13 V1 0 2010 02 Memory Organization V 0 1 Infineon XC82x Memory Organization Table 3 1 CPU Register Overview cont d Addr Register Name Bit 7 6 5 4 3 2 1 0 A8y IENO Reset 004 Bit Fie EA 0 ET2 ES ET1 1 Interrupt Enable Register 0 Type rw r rw rw rw rw rw TW IP Reset 004 Bit Fie PT2 PS PT1 1 Inte
244. Field Bits Type Description CCVL 7 0 rh Channel CC63 Compare Value The bit field CCV contains the lower 8 bits value that is compared to the T13 counter value CC63RH Compare Register for T13 High 9B Reset Value 00 RMAP 0 PAGE 1 7 6 5 4 3 2 1 0 CCVH rh Field Bits Type Description CCVH 7 0 rh Channel CC63 Compare Value The bit field CCV contains the upper 8 bits value that is compared to the T13 counter value 20 4 6 4 Compare Shadow Register The register CC63RL H can only be read by SW the modification of the value is done by a shadow register transfer from register CC63SRL H The corresponding shadow register CC63SRL H can be read and written by SW User s Manual 20 83 V1 0 2010 02 CCU6 V4 0 Cinfineon Capture Compare Unit 6 CCU6 CC63SRL Compare Shadow Register for T13 Low 9 Reset Value 00 RMAP 0 PAGE 0 7 6 5 4 3 2 1 0 CCSL rw Field Bits Type Description CCSL 7 0 rw Shadow Register for Channel CC63 Compare Value The bit field contents of CCSL is transferred to the lower 8 bits of bit field CCV during a shadow transfer CC63SRH Compare Shadow Register for T13 High 9 Reset Value 00 RMAP 0 PAGE 0 7 6 5 4 3 2 1 0 CCSH rw Field Bits Type Description CCSH 7 0 rw Shadow Register for Channel CC63 Compare Value The bit field contents of CCSH is transferred to the up
245. Flag Set on activation of each new time slice including when bit CLK_PS is set from 0 To be cleared by software 1 This bit can only be modified when bit CLK PS 0 User s Manual 19 22 V1 0 2010 02 LEDTSCU V 1 2 1 Cinfineon LTS_COMPARE XC82x LED and Touch Sense Controller Time Slice Compare Shadow Register D4 Reset Value 00 RMAP 0 PAGE X 7 6 5 4 3 2 1 0 SHD_CMP rw Field Bits Type Description SHD_CMP 7 0 rw Compare Value for Time Slice to Shadow Transfer This value is shadow transferred to the time slice compare register on start of each new time slice A shadow transfer is effected on CLK_PS set from 0 User s Manual LEDTSCU V 1 2 1 19 23 V1 0 2010 02 Cinfineon LED and Touch Sense Controller 19 11 2 Function Control Registers These registers provide controls for the LED drive and touch sense functions LTS_LDTSCTL LED and Touch Sense Control Register D6 Reset Value 00 RMAP 0 PAGE X 7 6 5 4 3 2 1 0 NR_LEDCOL COLLEV NR_PADT TSOEXT rw rw rw rw Field Bits Type Description TSOEXT 0 rw Extension for Touch Sense Output for Pin Low Level Og Extend by 1 FPCLK 1g Extend by 4 FPCLK NR PADT 3 1 rw Number of Touch Sense Pad Turns Defines the number of touch sense inputs which is equal to number of pad turns Used for the hardware control of pad turn enabling Op 1 np n COLLEV 4
246. H 7 rw Priority Level High Bit for Interrupt Node XINTR13 9 6 Interrupt Flag Overview The interrupt events have interrupt flags that are located in different SFRs Table 9 5 shows the corresponding SFR to which each interrupt flag belongs Detailed information on the interrupt flags is provided in the respective peripheral chapters Table 9 5 Location of the Interrupt Flags Interrupt Event Interrupt Flag SFR Timer 0 Overflow TFO TCON Timer 1 Overflow TF1 TCON User s Manual 9 32 V1 0 2010 02 Interrupt System V 2 3 3 Cinfineon XC82x Table 9 5 Location of the Interrupt Flags cont d Interrupt System Interrupt Event Interrupt Flag SFR Timer2 Overflow TF2 T2_T2CON Timer2 External Event EXF2 T2_T2CON UART Receive RI SCON UART Transmit TI SCON LIN End of Synch Byte EOFSYN LINST LIN Synch Byte Error ERRSYN LINST External Interrupt 0 IEO TCON External Interrupt 1 IE1 TCON External Interrupt 2 EXINT2 IRCONO External Interrupt 3 EXINT3 IRCONO External Interrupt 4 EXINT4 IRCONO External Interrupt 5 EXINT5 IRCONO External Interrupt 6 EXINT6 IRCONO RTC compare wakeup interrupt CFRTC RTCON RTC second time interrupt SFRTC RTCON A D Converter Service Request 0 ADCSRO IRCON1 A D Converter Service Request 1 ADCSR1 IRCON1 MDU Result Ready IRDY MDUSTAT MDU Error IERR MDUSTAT SSC Error EIR IRCON1 SSC Transm
247. ID to program USER to enter other boot mode User s Manual 5 1 V1 0 2010 02 Cinfineon XBox Boot and Startup For code protection user may want to erase all flash contents before executing this code Detailed description of these user routines are found in the Boot ROM User Routines Chapter Note A soft reset will be performed after the BMI has been updated Switching off the supply voltage before the soft reset happened may cause the BMI to be updated wrongly No additional reset is necessary for the system to use the new BMI value Note It is advisable to disable the Watchdog Timer WDT during the changing of BMI value A WDT reset during the programming of BMI may cause the BMI to update wrongly Beside that a stable power supply is also mandatory A wrong BMI could cause the device to enter a deadlock situation Note Unintentional execution of the BR PROG USER user routine will affect the BMI value Device may not be able to boot up properly because of an invalid BMI A user defined condition must be included to prevent an unintentional jump to this routine In OCDS mode startup firmware will based on the BMI and BMI values to enable the debug interface of the single pin DAP SPD In User mode Diagnostic the SPD interface is handled similiarly as debug mode which is also based on BMI and BMI values 5 1 User Identification Number The USER is a 4 byte data that contains user s specific information inc
248. INF5 EVINF4 0 EVINF1 EVINFO rh rh rh rh rh rh Field Bits Type Description EVINFO 0 rh Interrupt Flag for Event x EVINF1 1 This bit monitors the status of the event interrupt x EVINF4 4 Aneventinterruptfor event x has not occurred EVINF5 5 Writing a 0 clears this register EVINF6 6 1g X An event interrupt for event x has occurred EVINF7 7 Writing a 1 sets this register and generates an interrupt pulse if interrupt is enabled 0 3 2 r Reserved Returns 0 if read should be written with 0 User s Manual ADC V2 1 21 84 V1 0 2010 02 Cinfineon XC82x Analog to Digital Converter The Event Interrupt Set Flag Register ADC_EVINSR sets the corresponding bit at ADC_EVINFR and generates an interrupt request when the associated bit is written ADC_EVINSR Event Interrupt Set Flag Register D2 Reset Value 00 RMAP 0 PAGE 5 7 6 5 4 3 2 1 0 EVINS7 EVINS6 EVINS5 EVINS4 0 EVINS1 EVINSO WwW Ww Ww WwW Field Bits Type Description EVINSO 0 w Set Interrupt Flag for Event x EVINS1 1 No action EVINS4 4 1g Bit EVINFR xis set EVINSS 5 EVINS6 6 EVINS7 7 0 3 2 r Reserved Returns 0 if read should be written with 0 Note Writing 1 to a bit of the Event Interrupt Set Flag Register EVINSR sets the corresponding bit at EVINFR and generates the associated interrupt request Writing a 0 has not e
249. ISCC61 ISCC60 Port Input Select Register 0 Low rw rw rw rw CCU6_PISELOH Reset 004 Bit Fie IST12HR ISPOS2 ISPOS1 ISPOSO Port Input Select Register 0 High T ype rw rw rw rw 4 CCU6_PISEL2 Reset 004 Bit Fie 0 IST13HR Port Input Select Register 2 rw FAH CCU6_T12L Reset 00 Bit Fie T12CVL Timer T12 Counter Register Low Type CCU6_T12H Reset 00 Bit Fie T12CVH Timer T12 Counter Register High rwh FCH CCU6_T13L Reset 00 Bit Fie T13CVL Timer T13 Counter Register Low rwh FDH CCU6_T13H Reset 004 Bit Fie T13CVH Timer T13 Counter Register High T ype rwh FEH CCU6_CMPSTATL Reset 004 Bit Fie 0 CC63 cc cc 62 61 60 Compare State Register Low ST POS2 POS1 POSO ST ST ST Type r rh rh rh rh rh rh rh FFH CCU6_CMPSTATH Reset 004 Bit Field T13IM COUT COUT CC62 COUT CC61 COUT CC60 Compare State Register High 63PS 62PS PS 61PS PS 60PS PS Type rwh rwh rwh rwh rwh rwh rwh rwh User s Manual 3 30 V1 0 2010 02 Memory Organization V 0 1 Infineon Memory Organization 3 4 5 10 SSC Registers The SSC SFRs can be accessed in the standard memory area RMAP 0 Table 3 10 SSC Register Overview Addr Register Name Bit 7 6 5 4 3 2 1 0 IRMAP 0 AAH SSC_CONL Reset 004 Bit Field LB PO PH HB BM Control Register Low P
250. In this case do not write to the queue input while the queued source is running Write operations to a completely filled queue are ignored Stop or abort an ongoing queued sequence by executing the following actions Disable the corresponding arbitration slot 0 in the arbiter This does not modify the queue entries but only prevents the arbiter from accepting requests from the request handling block Disable the queued source by clearing bitfield ENGT Og Invalidate the next pending queue entry by setting bit QMRX CLRV 1 If the backup stage contains a valid entry this one is invalidated otherwise stage 0 is invalidated Remove all entries from the queue by setting bit QMRx FLUSH 1 User s Manual 21 27 V1 0 2010 02 ADC V2 1 Cinfineon Analog to Digital Converter Queue Request Source Events and Interrupts A request source event of a queued source occurs when a conversion is finished A request source event interrupt can be generated based on a request source event according to the structure shown in Figure 21 9 If a request source event is detected it sets the corresponding indication flag in register ADC_EVINFR The indication flags can be cleared by SW by writing a 1 to the corresponding bit position in register ADC EVINCR The interrupt enable bit is taken from stage 0 for a normal sequential conversion or from the backup stage for a repeated conversion after an abort The service request output l
251. Infineon XC82x Memory Organization Table 3 9 CCU6 Register Overview cont d Addr Register Name Bit 7 6 5 4 3 2 1 0 CCU6_IENH Reset 004 Bit Fie EN EN EN EN EN ENT1 ENT1 Capture Compare Interrupt Enable STR IDLE WHE CHE TRPF 3PM 3CM Register High Type TW rw TW TW r rw rw rw BEY CCU6_INPL Reset 404 Bit Fie INPCHE INPCC62 INPCC61 INPCC60 Capture Compare Interrupt Node Pointer Register Low Type FE CCU6_INPH Reset 39 Bit Fie 0 INPT13 INPT12 INPERR Capture Compare Interrupt Node Pointer Register High Type r TW Iw TW Mu CCU6_ISSL Reset 00 Bit Fie ST12 ST12 SCC6 SCC6 SCC6 SCC6 SCC6 SCC6 Capture Compare Interrupt Status PM OM 2F 2R 1R OF OR Set Register Low Type w w w w w w w w ASH CCU6_ISSH Reset 00 Bit Fie SSTR SIDLE SWHE SCHE SWH STRP ST13 ST13 Capture Compare Interrupt Status Ir PM CM Set Register High Type w w w w w w w w CCU6_PSLR Reset 00 Bit Field PSL63 0 PSL Passive State Level Register Type rwh r rwh CCU6_MCMCTR Reset 00 Bit Fie 0 SWSYN 0 SWSEL Multi Channel Mode Control Register Type r rw rw FAH CCU6_TCTR2L Reset 00 Bit Fie 0 T13TED T13TEC T13 T12 Timer Control Register 2 Low SSC SSC Type r rw rw rw TW CCU6_TCTR2H Reset
252. LED and Touch Sense Controller 19 4 LED Driving The control provided for LED driving is mainly for LED column selection where one column is enabled at a time It is required for interrupt based software handling to control LED enabling per selected column Up to eight LED columns are supported and up to eight LEDs can be enabled per column With direct LED drive it is supported for adjust of luminence for different types of LEDs with different forward voltages A compare register for LEDTS counter is provided so that the duty cycle for column enabling per time slice can be adjusted The LED column is enabled from the beginning of the time slice until compare match event For 100 duty cycle for LED column enable in time slice the compare value should be set to If the compare value is set to 00 the LED column will stay at passive level during the time slice Update of the compare register for each time slice is by shadow transfer which takes place automatically at the beginning of each time slice A shadow transfer mechanism for update of LED enabling LED line pattern per column time slice is also provided This shadow transfer takes place automatically at the beginning of each new time slice When the LEDTS counter is first started enable input clock by CLK_PS a shadow transfer of line pattern and compare value is activated for the first column A time slice interrupt can be enabled which occurs on overflow of the 8LSB
253. LT 1 ALT 2 ALT 3 ALT 4 ALT 5 ALT 6 CC62_0 CCU6 Output GPO P1_DATAOUT P5 ALT1 COL5 LEDTSCU ALT2 CC62 0 CCUG ALT3 COLA 0 LEDTSCU 17 1 1 1 3 P1 4 and P1 5 is only available in XC824 User s Manual 11 25 V1 0 2010 02 Cinfineon Parallel Ports 11 3 2 Registers Description P1_DATAIN Port 1 Data In Register 914 Reset Value RMAP 0 PAGE 0 7 6 5 4 3 2 1 0 0 P5 P4 P3 P2 P1 PO T rh rh rh rh rh rh Field Bits Description Pn n rh Port 1 Pin n Data Value 0 5 0 Port 1 data value 0 1 Port 1 data value 1 0 7 6 r Reserved Returns 0 if read should be written with 0 P1_DATAOUT Port 1 Data Out Register 90 Reset Value 3F RMAP 0 PAGE 0 7 6 5 4 3 2 1 0 0 P5 P4 P3 P2 P1 PO r rw rw rw rw rw rw Field Bits Type Description Pn n rw Port 1 Pin n Data Value 0 5 0 Port 1 data value 0 1 Port 1 data value 1 0 7 6 r Reserved Returns 0 if read should be written with 0 User s Manual 11 26 V1 0 2010 02 Cinfineon XC82x P1_OD Port 1 Open Drain Control Register 90 RMAP 0 PAGE 3 Parallel Ports Reset Value 3F 7 6 5 4 3 2 1 0 0 P5 P4 P3 P2 P1 PO T rw rw rw rw rw rw Field Bits Type Description Pn n rw Port 1 Pin n Open Drain Mode n 0 5
254. Line 2 of PadResult OB Pad not valid 1B Pad valid User s Manual 23 28 V1 0 2010 02 ROM Library V0 5 Cinfineon ROM Library Field Bits Description Pad Line3 3 rw Pad Line 3 of PadResult OB Pad not valid 1B Pad valid Pad Line4 4 rw Pad Line 4 of PadResult OB Pad not valid 1B Pad valid Pad Line5 5 rw Pad Line 5 of PadResult OB Pad not valid 1B Pad valid Pad Line6 6 rw Pad Line 6 of PadResult OB Pad not valid 1B Pad valid Pad Line7 7 rw Pad Line7 of PadResult OB Pad not valid 1B Pad valid PadError E PadError Status IRAM address 0x2D Reset Value 00 7 6 5 4 3 2 1 0 Pad Line7 Pad Line6 Pad Line5 Pad Line4 Pad Line3 Pad Line2 Pad Line1 Pad Lined rw rw rw rw rw rw rw rw Field Bits Type Description Pad LineO 0 rw Pad Line 0 of PadError OB Pad OK 1B Pad ERROR Pad Line1 1 rw Pad Line 1 of PadError OB PadOK 1B Pad ERROR Pad Line2 2 rw Pad Line 2 of PadError OB Pad OK 1B Pad ERROR User s Manual 23 29 V1 0 2010 02 ROM Library V0 5 Cinfineon ROM Library Field Bits Description Pad Line3 3 rw Pad Line 3 of PadError OB Pad OK 1B Pad ERROR Pad Line4 4 rw Pad Line 4 of PadError OB Pad OK 1B Pad ERROR Pad Line5 5 rw Pad Line 5 of PadError OB Pad OK 1B PadERROR Pad Line6 6 rw Pad Line 6 of PadError OB Pad OK
255. Ly is output This allows the user to adapt the polarity of an active output signal to the connected circuitry The PSLy bits have shadow registers to allow for updates without undesired pulses on the output lines The bits related to CC6x and COUT6x x 7 0 1 2 are updated with the T12 shadow transfer signal T12 ST A read action returns the actually used values whereas a write action targets the shadow bits Providing a shadow register for the PSL value as well as for other values related to the generation of the PWM signal facilitates a concurrent update by software for all relevant parameters Figure 20 18 shows the output modulation structure for compare channel CC60 output signals CC60 and COUT60 A similar structure is implemented for the other two compare channels CC61 and CC62 User s Manual 20 35 V1 0 2010 02 CCU6 V4 0 Cinfineon XC82x Capture Compare Unit 6 CCU6 Trap Handling Block T12 Block Dead Time Multi Channel Mode TRPS E T13 Block CC60 O T13MODENO Output Modulation CC60 active COUT60 O MCMPO T12MODENO du lt 1 active T13MODEN1 Modulation Passive Output COUT60 T12MODEN1 CCU6_MCA05543 Figure 20 18 Output Modulation for Compare Channel CC60 User s Manual CCU6 V4 0 20 36 V1 0 2010 02 Cinfineon Capture Com
256. MAP is set the mapped SFR area can be accessed This bit is not cleared automatically by hardware Thus before standard mapped registers are accessed bit RMAP must be cleared set respectively by software User s Manual 3 4 V1 0 2010 02 Memory Organization V 0 1 Infineon XC82x Memory Organization Standard Area RMAP 0 SYSCONO RMAP TW SFR Data to from CPU FF Module 1 SFRs Module 2 SFRs Module n SFRs 80 Mapped Area RMAP 1 FF Module n 1 SFRs Module n 2 SFRs Module m SFRs 80 Direct Internal Data Memory Address Figure 3 2 Address Extension by Mapping User s Manual Memory Organization V 0 1 V1 0 2010 02 Cinfineon XC82x Memory Organization 3 4 1 1 System Control Register 0 The SYSCONO register contains the bit to select the SFR mapping SYSCONO System control Register 0 8 Reset Value 00 RMAP X PAGE X 7 6 5 4 3 2 1 0 0 RMAP 1 1 TW Field Bits Type Description RMAP 0 rw Special Function Register Map Control 0 Accessed to non mapped standard special function register area 1 Accessed to mapped special function register area 0 7 1 r Reserved Returns 0 if read should be written with 0 User s Manual Memory Organization V 0 1 3 6 V1 0 2010 02 Cinfineon Memory Organization 3 4 2 Addr
257. MI service routine At this point the Flash bank is in ready to read mode i e programming is done Table 22 10 Specifications of FLASH BACKGROUND PROGRAM subroutine Subroutine BR FLASH BACKGROUND PROGRAM User s Manual 22 8 V1 0 2010 02 BootROM User Routines V1 1 Cinfineon Boot ROM User Routines Table 22 10 Specifications of FLASH_BACKGROUND_PROGRAM subroutine Input Flash WL aligned address to be programmed R6 of current Register Bank DPH R7 of current Register Bank DPL R5 of current Register Bank IRAM start address for 32 byte Flash data 32 byte Flash data Flash NMI NMICON NMIFLASH is enabled 1 or disabled 0 SFR NMISR 00 Output PSW CY 0 Flash programming is in progress 1 Flash programming is not successful DPTR is incremented by 20H Stack size required 8 Resource DPTR A used destroyed RO R2 R6 and R7 of current Register Bank 4 bytes 1 The last 5 LSB of the DPL is 0 for an aligned WL address for e g 00H 20H 40H 60H 80H AOH COH and EOH 2 DPTR is only incremented by 20 when PSW CY is 0 22 7 Flash Erase Subroutine Each call of the Flash erase subroutine allows sector s erase of the selected Flash Bank At any one time more than one Flash Sectors can be selected for erase Before calling this subroutine the user must ensure that inputs are set accordingly Two types of Flash erasing routines will be offered to users T
258. MIOCDS 73 IRAM write event 10 2 4 Debug Suspend Control It is enabled for selected modules to suspend operation when Monitor Mode becomes active The module functions that can be enabled for debug suspend are Watchdog timer Timer 12 of CCU6 Timer 13 of CCU6 Timer 2 RTC timer LEDTSCU counters By debug suspend these module functions are frozen during the duration of the device in Monitor Mode e g timers stop counting Register MODSUSP is used to control the debug suspend function The bit field of SCU_PAGE register must be programmed before accessing the MODSUSP register MODSUSP Module Suspend Control Register F6 Reset Value 01 RMAP 0 PAGE 3 7 6 5 4 3 2 1 0 0 LTSSUSP RTCSUSP T2SUSP T13SUSP T12SUSP WDTSUSP T rw rw rw rw rw rw Field Bits Type Description WDTSUSP 0 rw SCU Watchdog Timer Debug Suspend Bit 0 WDT will not be suspended 1 WDT will be suspended User s Manual 10 3 V1 0 2010 02 OCDS V 2 7 1 Cinfineon XC82x Debug System Field Bits Type Description T12SUSP Timer 12 Debug Suspend Bit 0 Timer 12 in Capture Compare Unit will not be suspended 1 Timer 12 in Capture Compare Unit will be suspended In addition the T12 PWM outputs are set to the inactive level and capture inputs are disabled when suspended T13SUSP Timer 13 Debug Suspend Bit 0 Timer 13 in Capture Compare Unit will not be s
259. MSELL H contains control bits to select the capture compare functionality of the three channels of Timer T12 T12MSELL T12 Mode Select Register Low 9 Reset Value 00 RMAP 0 PAGE 2 7 6 5 4 3 2 1 0 MSEL61 MSEL60 rw i rw Field Bits Type Description MSEL60 3 0 rw Capture Compare Mode Selection MSEL61 7 4 These bit fields select the operating mode of the three T12 capture compare channels Each channel x 0 1 2 can be programmed individually for one of these modes except for Hall Sensor Mode Coding see Table 20 10 T12MSELH T12 Mode Select Register High 9 Reset Value 00 RMAP 0 PAGE 2 7 6 5 4 3 2 1 0 DBYP HSYNC MSEL62 rw rw IW Field Bits Type Description MSEL62 3 0 rw Capture Compare Mode Selection These bit fields select the operating mode of the three T12 capture compare channels Each channel x 0 1 2 be programmed individually for one of these modes except for Hall Sensor Mode Coding see Table 20 10 User s Manual 20 55 V1 0 2010 02 CCU6 V4 0 Cinfineon XC82x Capture Compare Unit 6 CCU6 Field Bits Type Description HSYNC 6 4 rw Hall Synchronization Bit field HSYNC defines the source for the sampling of the Hall input pattern and the comparison to the current and the expected Hall pattern bit fields Coding see Table 20 15 DBYP Delay Bypass DBYP c
260. Manual Keyword Index Address extension by mapping 3 4 Mapped 3 4 Standard 3 4 Address extension by paging 3 7 Local address extension 3 7 Save and restore 3 8 Memory protection 3 4 Minimum erase width 4 3 Minimum program width 4 6 Multifold replications 4 4 Multiplication Division Unit 12 1 OCDS 10 1 Breakpoint 10 8 External Break 10 10 Hardware 10 8 On Instruction Address 10 8 On IRAM Address 10 9 Software 10 10 Breakpoint Reaction 10 11 NMI 10 12 NMI Priority 10 13 OD 14 12 PO register description 11 17 P1 register description 11 26 P2 register description 11 33 Parallel ports 11 1 General bidirectional port structure 11 3 Input mode 11 2 Kernel registers 11 7 Alternate input functions 11 10 Alternate output functions 11 10 Input control register 11 10 Open drain control register 11 8 Port data in register 11 8 L 4 V1 0 2010 02 Cinfineon XC82x Port data out register 11 7 Pull Up Pull Down device register 11 9 Px_ALTSELn 11 10 Px_OD 11 8 Px_PUDEN 11 9 Px_PUDSEL 11 9 Register addresses 11 5 Normal mode 11 1 Open drain mode 11 1 PO 11 12 P1 11 22 P2 11 30 PCON 7 24 Peripheral clock management 7 21 Personal computer host 4 11 Power down mode 7 12 Power down wake up reset 7 7 Power on reset 7 2 7 6 Prewarning period 8 4 Program memory 3 2 R Read access time 4 1 Register Overview 3 13 Reset Module behavior 7 8 RS 232 4 11 RTC 15 1 Basic Timer Operation 15 2 Mode 1 15 3 Mode
261. Manual 18 13 V1 0 2010 02 SSC V1 4 Cinfineon neers High Speed Synchronous Serial Interface The Half Duplex Mode port configuration using three pins is shown in Figure 18 4 Master Device 1 Device 2 Slave Shift Register Transmit Common Transmit Receive Device 3 Figure 18 4 SSC Half Duplex Configuration 18 3 4 Continuous Transfers When the transmit interrupt request flag is set it indicates that the transmit buffer TB is empty and ready to be loaded with the next transmit data If TB has been reloaded by the time the current transmission is finished the data is immediately transferred to the shift register and the next transmission will start without any additional delay On the data line there is no gap between the two successive frames For example two byte transfers would look the same as one word transfer This feature can be used to interface with devices that can operate with or require more than 8 data bits per transfer It is just a matter of software how long a total data frame length can be This option can also be used to interface to byte wide and word wide devices on the same serial bus for instance Note Of course this can happen only in multiples of the selected basic data width because it would require disabling enabling of the SSC to reprogram the basic data width on the fly User s Manual 18 14 V1 0 2010 02 SSC V1 4 Cinfineon neers High Speed Synchr
262. Manual 7 18 V1 0 2010 02 Cinfineon System Control Unit of the status of the 75 KHz oscillation is possible This is because the 75 KHz oscillator watchdog is powered down To exit power down mode 2 the real time clock wake up event can be used Besides this wake up source it can also be awakened when it receives an external wake up signal via EXINTO pin by setting bit PMCONO EWS to 1 The sequence to enter power down mode 2 is Ensure that real time clock is enabled by setting bit RTCON RTCC set to 1 Disable the WDT module by setting bit WDTCON WDTEN to 0 Select power down mode 2 by setting PMCONO PDMODE to 1g Enter power down mode by setting bit PMCONO PD to 1 Three NOP instructions must be inserted after the bit PMCONO PD is set to 1 This ensures the first instruction after two NOP instructions is executed correctly after wake up from power down mode For all types of power down mode the port pins hold the logicial state they had when the power down mode was activated For digital ports the input and output driver of all port pins that are not used as wake up source are disabled once the chip enters power down mode This can reduce the leakage current in the power down mode Exiting Power Down Mode Power down mode can be exited in various ways The EXINTO pin detects a edge based on the setting in bit EXICONO EXINTO The wake up event request from the real time clock The RTC clock source failure N
263. NST ERRSYN are not set User s Manual 16 18 V1 0 2010 02 UART V 1 6 Cinfineon UART 16 7 Registers Description Besides the SCON and SBUF registers which can be accessed from both the standard non mapped and mapped SFR area the rest of the UART s SFRs are located in SCU page 5 of the standard area The bit field PAGE of SCU_PAGE register must be programmed before accessing these registers Table 16 8 lists the addresses of these SFRs Table 16 8 Register Map Address Register 98 SCON 99 SBUF F24 BCON BGL F4 BGH F5 LINST User s Manual 16 19 V1 0 2010 02 UART V 1 6 Cinfineon UART 16 7 1 UART Registers UART contains the two Special Function Registers SFRs SCON and SBUF SCON is the control register and SBUF is the data register On reset both SCON and SBUF return 00 The serial port control and status register is the SFR SCON This register contains not only the mode selection bits but also the 9th data bit for transmit and receive TB8 and RB8 and the serial port interrupt bits and RI SBUF is the receive and transmit buffer of the serial interface Writing to SBUF loads the transmit register and initiates transmission This register is used for both transmit and receive data Transmit data is written to this location and receive data is read from this location but the two paths are independent Reading out SBUF accesses a physically separa
264. OH ISPOS2 11 Out of Range Comparator ORC ORC event 0 0 ORCEVENTO CCU6 input i T12HR MODPISEL3 IST12HR1 001 CCU6_PISELOH IST12HR 00 Timer 2 input i 2 MODPISEL2 T2EXIS 100 ORC event 1 0 Timer 2 input i 2 MODPISEL2 T2EXIS 101 ORCEVENT 1 ORC event 2 0 CCU6 input i TI2HR MODPISEL3 IST12HR1 100g ORCEVENT2 CCU6_PISELOH IST12HR 00 CCU6 input i T13HR MODPISEL3 IST13HR1 100 CCU6_PISEL2 IST13HR 00 ORC event 3 0 ORCEVENT3 CCU6 input i CTRAP MODPISEL3 CTRAPIS 11 CCU6_PISELOL ISTRP 00 User s Manual ADC V2 1 21 5 V1 0 2010 02 Cinfineon XC82x Analog to Digital Converter Table 21 5 ADC Input Interconnection ADC Function Signal Connected Other Module Function Signal Request Source x x 0 1 Request Source x Trigger 0 Input i REQTRxA CCU6 service request output SR2 CCU6_SR2 Request Source x Trigger 1 Input i REQTRxB CCU6 service request output SR3 0 CCU6_SR3 Request Source x Trigger 2 Input i REQTRxC CCU6 T12 period match 0 T12PM Request Source x Trigger 3 Input i REQTRxD CCU6 T13 period match 0 T13PM Request Source x Trigger 4 Input i REQTRxE CCU6 T13 compare match o T13CM Request Source x Trigger 5 Input i REQTRxF CCU6 MCM shadow transfer 0 MCM ST Request Source x Trigger 6 Input i RE
265. ON 9 19 P PO ALTSELO 11 19 PO ALTSEL1 11 20 PO ALTSEL2 11 20 PO DATAIN 11 17 PO DATAOUT 11 17 PO OD 11 18 V1 0 2010 02 Cinfineon XC82x PO PUDEN 11 19 PO PUDSEL 11 18 P1 ALTSELO 11 28 P1 ALTSEL41 11 28 P1 DATAIN 11 26 P1 DATAOUT 11 26 P1 OD 11 27 P1 PUDEN 11 28 P1 PUDSEL 11 27 P2 DATAIN 11 33 P2 EN 11 33 P2 PUDEN 11 34 P2 PUDSEL 11 34 PASSWD 3 11 PCON 2 6 16 22 1 14 3 19 4 20 12 21 3 PORT PAGE 11 5 PRAR 21 41 PSW 2 4 Px ALTSELn 11 10 Px DATAIN 11 8 Px DATAOUT 11 7 Px EN 11 11 Px OD 11 8 11 9 Px PUDEN 11 9 Q QORO 21 34 QBURO 21 36 QINRO 21 33 QMRO 21 29 QSRO 21 31 R RCRx x 0 3 21 77 RESRxH x 0 3 21 72 RESRxL x 0 3 21 69 21 72 21 75 RTC RTCON 15 7 S SBUF 16 20 SCON 16 20 SCU PAGE 7 25 User s Manual Register Index SDCON 7 4 SSC BRH 18 26 SSC BRL 18 26 SSC CONH 18 22 18 24 SSC CONL 18 21 18 24 SSC RBL 18 27 SSC TBL 18 27 SYSCONO 3 6 T T2 RC2H 14 15 T2 21 14 15 2 2 14 13 2 2 1 14 14 T2_T2H 14 16 2 21 14 16 T2 T2MOD 14 12 TCON 9 23 9 27 V VFCR 21 79 WDTCON 8 8 23 27 23 28 23 29 WDTH 8 9 WDTL 8 9 WDTREL 8 7 WDTWINB 8 9 X XADDRH 3 3 L 10 V1 0 2010 02
266. OP or repeated START mode received in slave mode A8 Slave address and read bit received ACK transmitted BO Arbitration lost in address as master slave address and read bit received ACK transmitted B8 Data byte transmitted in slave mode ACK received Data byte transmitted in slave mode ACK not received C8 Last byte transmitted in slave mode ACK received DO Second address byte and write bit transmitted ACK received D8 Second address byte and write bit transmitted ACK not received EO Unused E84 Unused F0 Unused F8 No relevant status information IFLG 0 If an illegal condition occurs on the IIC bus the bus error state is entered status code 00 To recover from this state the STP bit in the CNTR register must be set and the IFLG bit cleared The will then return to idle state status code F8 no STOP condition will be transmitted on the IIC bus To request resumption of transmission set the STA bit to 1 at the same time as the STP bit is set The IIC will then send a START on recovery from the bus error 17 4 Baud Rate Generation To support a wide range of input clock frequencies fiic two dividers are implemented to generate the required baud rate on the IIC bus in master mode The two dividers are defined by the PREDIV and BRP bits in BRCR register The baud rate is calculated by the formulae 17 1 fpcLK f OK __ OSCL jPREDIY x BRP 1 x 10 Table 17 5 shows various commonly used baud
267. Or read DATA set STP Transmit STOP clear IFLG Or read DATA set STA Transmit STOP then and STP clear IFLG START 38 Arbitration lost in not Clear IFLG Return to idle state ACK bit Or set STA clear IFLG Transmit START when bus is free When all bytes have been received a not ACK should be transmitted then the STP bit should be set by writing a 1 to this bit in the CNTR register The IIC will transmit a STOP condition clear the STP bit and return to idle state status code 8 17 8 3 Slave Transmit In the slave transmit mode a number of bytes are transmitted to a master receiver For the IIC to respond the bit in the CNTR register needs to be set The IIC will enter slave transmit mode when it receives its own slave address and a Read bit after a START condition The IIC will then transmit an acknowledge bit and set the IFLG bit in the CNTR register The STAT register will contain the status code 8 Note Where the IIC has an extended slave address signified by 11110 in ADDR 7 3 it will first be selected then there will be a restart followed by another address byte If this address byte matches the value stored in ADDR the IIC will transmit an acknowledge after this address byte is received An interrupt will be generated IFLG will be set and the status will be A8 No second address byte will be sent by the master it is up to the slave to remember that it had been selected prior to the r
268. PAGE 0 02 OV PO ALTSE 0 0x00 Select Alternate function as GPIO OV PO A TSEL1 0 00 Px ALTSELx in PORT PAGE 0x02 OV ALTSEL2 40x00 User s Manual 11 2 V1 0 2010 02 Infineon XC82x Parallel Ports Internal Bus AltDataOut 7 PUDSEL Pull up Pull down Select Register Pull up Pull down Control Logic PUDEN Pull up Pull down Enable Register OD Open Drain Control Register ALTSELO Alternate Select Register 0 ALTSEL1 Alternate Select Register 1 ALTSEL2 Alternate Select Register 2 AltDataOut 1 AltDataln Data OUT Data Register Y Drive Data IN Port Output Driver Control Registers Schmitt Trigger Pull Device Output Input Driver Pad Figure 11 1 General Structure of Standard Bidirectional Port User s Manual V1 0 2010 02 Cinfineon XC82x Parallel Ports Figure 11 2 shows the structure of an input only port pin Each P2 pin can only function in input mode Register P2_EN is provided to enable or disable the input driver When the input driver is enabled the actual voltage level present at the port pin is translated into a logic 0 or 1 via a Schmitt Trigger device and can be read via the register P2_DATAIN
269. QTRxG LEDTSCU Compare match 0 LEDTS CM Request Source x Trigger 7 Input i REQTRxH LEDTSCU Time slice interrupt o LEDTS TSI User s Manual ADC V2 1 21 6 V1 0 2010 02 Cinfineon Analog to Digital Converter 21 2 Introduction and Basic Structure A set of functional units can be configured according to the requirements of a given application These units build a path from the input signals to the digital results Vddp V12vR F va altref va ref ADC kernel interrupt generation result handling V sp analog input channel CHO analog input converter channel CH3 7 request control conversion control kernel overv3 Figure 21 2 ADC Kernel Block Diagram Request Source Control Concurrent conversion requests can be generated by up to 2 request sources A linear sequence source requests auto scan conversions of a configurable sequence of up to 8 channels An arbitrary sequence source requests queued conversions of up to 4 arbitrarily selectable channels Each source can requests its selected conversion sequence once or repeatedly Each Source can be enabled separately and can be triggered by external events such as edges of PWM or timer signals or pin transitions An arbiter resolves concurrent conversion requests from different sources Requests with higher priority can either cancel a running l
270. R Shadow Transfer CC60ST CC61ST CC62ST o un Lh T 8 Figure 20 14 Three Channel Compare Waveforms User s Manual 20 30 V1 0 2010 02 CCU6 V4 0 Cinfineon Capture Compare Unit 6 CCU6 20 3 3 3 Hysteresis Like Control Mode The hysteresis like control mode T12MSELL MSEL6x 1001 offers the possibility to switch off the PWM output if the input CCPOSx becomes 0 by clearing the State Bit CC6xST This can be used as a simple motor control feature by using a comparator indicating e g overcurrent While CCPOSx 0 the PWM outputs of the corresponding channel are driving their passive levels because the setting of bit CC6xST is only possible while CCPOSx 1 As long as input CCPOSx is 0 the corresponding State Bit is held 0 When CCPOSx is at high level the outputs can be in active state and are determined by bit CC6xST see Figure 20 10 for the state bit logic and Figure 20 15 for the output paths The CCPOSx inputs are evaluated with fece This mode can be used to introduce a timing related behavior to a hysteresis controller A standard hysteresis controller detects if a value exceeds a limit and switches its output according to the compare result Depending on the operating conditions the switching frequency and the duty cycle are not fixed but change permanently If outer time related control loops based on a hysteresis controller in an inner loop should be implemented t
271. RAP Input Pin CTRAP 1 is selected 10 CCU6 CTRAP Input Pin CTRAP 2 is selected 11 Out of Range Channel event on Input Pin CTRAP 3 is selected Note To select the port pin ORC event to trigger CTRAP CCUG PISELOL ISTRP must be set to 00g IST12HR1 4 2 rw CCU6 T12HR Port Pin Input Select 000 001 010 011 100 101 110 111 Note T12HR Input Pin T12HR O is selected Out of Range Channel 0 event on Input T12HR 1 is selected T12HR Input Pin T12HR 2 is selected T12HR Input Pin T12HR 3 is selected Out of Range Channel 2 event on Input T12HR 4 is selected Reserved Reserved Reserved To select the port pin ORC event to trigger T12HR CCUG6 PISELOH IST12HR must be set to 00g User s Manual CCU6 V4 0 20 11 V1 0 2010 02 Cinfineon Capture Compare Unit 6 CCU6 Field Bits Description IST13HR1 7 5 rw CCU6 T13HR Port Pin Input Select 000 T13HR Input Pin 13 0 is selected 001 T13HR Input Pin T13HR_1 is selected 010 T13HR Input Pin 13 2 is selected 011 Input Pin TT3HR 3 is selected 100 Out of Range Channel 2 event on Input T13HR 4 is selected 101 Reserved 110 Reserved 111 Reserved Note To select the port pin ORC event to trigger T13HR CCU6_PISEL2 IST13HR must be set to 00g 20 2 2 Clocking Configuration The CCU6 kernel runs on the FPCLK at a fixed frequency of 48 MHz If the CCU6 functionality is not required
272. RESULT 9 3 6 0 rh Conversion Result This bit field contains the conversion result or the result of the data reduction filter 0 7 r Reserved Returns 0 if read should be written with 0 ADC RESRxL x 0 2 Result Register x Low View Acc 8 bit 2nd conv CA x 2 Reset Value 00 ADC RESR3L Result Register 3 Low View Acc 8 bit 2nd conv D2 Reset Value 00 RMAP 0 PAGE 2 7 6 5 4 3 2 1 0 RO 0 VF DRC CHNR rh r rh rh rh Field Bits Type Description CHNR 2 0 rh Channel Number This bit field contains the channel number of the latest register update Note Bit 2is only applicable for devices that have 8 ADC channels For channels not implemented these bits should be treated as Reserved bits of type f which returns 0 if read and should be written with 0 DRC 3 rh Data Reduction Counter This bit field indicates how many conversion results have still to be accumulated to generate the final result for data reduction Og The final result is available in the result register The valid flag is automatically set when this bit field is set to 0 1g 1 more conversion result must be added to obtain the final result in the result register The valid flag is automatically reset when this bit field is set to 1 User s Manual 21 71 V1 0 2010 02 ADC V2 1 Cinfineon Analog to Digital Converter Field Bits Type Description VF 4 rh Va
273. RHEN bit starts upon negative transition T2 is stopped SYN BREAK SYN CHAR 55 tar toi P Bit Y Y Bit d Check the break field flag bit BRK is set or not Captured Value 8 bits gt Figure 16 8 LIN Auto Baud Rate Detection With the first falling edge The Timer 2 External Start Enable bit T2MOD T2RHEN is set The falling edge at pin T2EX is selected by default for Timer 2 External Start bit T2MOD T2REGS is 0 With the second falling edge Start Timer 2 by the hardware With the third falling edge Timer 2 captures the timing of 2 bits of SYN byte Checkthe Break Field Flag bit LINST BRK If the Break Field Flag LINST BRK is set software may continue to capture 4 6 8 bits of SYN byte Finally the End of SYN Byte Flag LINST EOFSYN is set Timer 2 is stopped T2 Reload Capture register RC2H L is the time taken for 2 4 6 8 bits according to the implementation Then the LIN routine calculates the actual baud rate sets the PRE and BG values if the UART module uses the baud rate generator for baud rate generation After the third falling edge the software may discard the current operation and continue to detect the next header LIN frame if the following conditions were detected The Break Field Flag LINST BRK is not set or The SYN Byte Error Flag LINST ERRSYN is set or The Break Field Flag LINST BRK is set but the End of SYN Byte Flag LINST EOFSYN and the SYN Byte Error Flag LI
274. RPEN3 TRPCTR 11 for output COUT61 TRPEN4 TRPCTR 12 for output CC62 TRPENS 13 for output COUT62 Og trap functionality of the corresponding output signal is disabled The output state is independent from bit IS TRPS 1g The trap functionality of the corresponding output signal is enabled The output state is set to the passive while IS TRPS 1 TRPEN13 Trap Enable Control for Timer T13 Og trap functionality for output COUT63 is disabled The output state is independent from bit IS TRPS 1g The trap functionality for output COUT63 is enabled The output state is set to the passive while IS TRPS 1 TRPPEN Trap Pin Enable This bit enables the input pin function for the trap generation An interrupt can only be generated if a falling edge is detected at pin CTRAP while TRPPEN 1 Os TheCCUGtrap functionality based on the input CTRAP is disabled A CCU6 trap can only be generated by SW by setting bit TRPF 1g CCU6 trap functionality based on the input CTRAP is enabled A CCU6 trap can be generated by SW by setting bit TRPF or by CTRAP 0 User s Manual CCU6 V4 0 20 102 V1 0 2010 02 Cinfineon Capture Compare Unit 6 CCU6 20 8 3 Passive State Level Register Register PSLR defines the passive state level of the PWM outputs of the module The passive state level is the value that is driven during the passive state of the output During t
275. RTC Vssc 4 Kbyte 1 N Flash v LN 2 d WDT CCU6 5 P2 0 P2 3 Clock Generator 1 Timer 2 OCDS b 48 MHz j ADC On chip OSC a N 75 2 evr 800 On chip OSC LED and Touch Sense Controller v 1 Includes 1 Kbyte monitor ROM Figure 1 2 XC82x Block Diagram 1 2 Pin Configuration Figure 1 3 shows the pin configuration of XC824 in DSO 20 package and Figure 1 4 shows the pin configuration of XC822 in TSSOP 16 package User s Manual System Architecture V1 0 V1 0 2010 02 Infineon XC82x Introduction P0 6 SPD_0 RXD_1 SDA_0 MTSR_4 MRST_O EXINTO_1 T2EX_0 LINE6 TSING TXD 0 COL2 1 COLA 1 P1 4 EXINT5 COL4 COUT62_0 COUT63 1 P1 5 CC62 0 COLS COLA 0 P2 3 CCPOS0_2 CTRAP_2 T2_2 EXINT3 AN3 P2 2 CCPOS2_1 T12HR_3 T13HR_3 SCK_1 T1_4 EXINT2 AN2 P2 1 CCPOS1_1 RXD_3 MTSR_4 T0_4 EXINT1_1 AN1 P2 0 CCPOS0_1 T12HR_2 T13HR_2 T2EX_3 T2_4 EXINTO_3 ANO P4 0 SPD 1 RXD 2 T2EX 2 EXINTO 2 COLO 0 COUT60 O TXD 1 P4 1 CC60 0 COL1 0 TXD 2 P1 2 EXINT4 COL2_0 COUT61_0 COUT63 0 10 XC824 10 20 19 18 17 16 15 14 13 12 11 P0 5 RXD_O RTCCLK MTSR_O MRST_1 EXINTO_O LINES TSIN5 COUT62_1 TXD_3 COL1_1 EXF2_2 P0 4 T2EX_1 SCL_0 SCK_0 EXINT1_0 CTRAP_1 LINE4 TSIN4 EXF2_0 COLO_1 COL3 1 COLA 2 P0 3 CC60_1 SDA_1 CTRAP_
276. Read next opoode one wait cyde one wait cycle Nm 1 1 WAIT WAIT 1 2 WAIT WAIT next instruction b 2 byte 1 cyde instruction e g ADD A data Read next opcode without weit state 1 1 OPI C2P2 nex instruction Read next opcode Ec es 1 1 1 2 2 2 WAIT next instruction 1 byte 2 cyde instruction e g Figure 2 2 CPU Instruction Timing The time taken for each instruction includes decoding executing the fetched opcode e fetching the operand s for instructions gt 1 byte fetching the first byte opcode of the next instruction due to CPU pipeline Note The XC800 Core fetches the opcode of the next instruction while executing the current instruction User s Manual 2 9 V1 0 2010 02 XC800 Core V 1 0 2 Cinfineon XC800 Core Table 2 1 lists all the instructions supported by the XC800 Core Instructions are 1 2 or 3 bytes long as indicted in the Bytes column Each instruction takes 1 2 or 4 machine cycles to execute with no wait cycle The table gives two values for the number of machine cycles required by each instruction The first value applies to fetching operand s and opcode from fast memory e g Boot ROM and XRAM without wait state The second value applies to fetching operand s and opcode and in some cases accessing data from slow memory e g Flash with wait cycles inserted due to memory re
277. Real Time Clock Count Value 7 0 These bits represent counter value 7 0 of the current real time clock timer RTC CNT1 Mode 1 and Mode 3 Count Clock Register 1 E24 Reset Value 00 RMAP 0 PAGE X 7 6 5 4 3 2 1 0 CNT VAL rwh User s Manual 15 8 V1 0 2010 02 RTC V1 0 Cinfineon Real Time Clock Field Bits Type Description CNT_VAL 7 0 rwh Real Time Clock Count Value 15 8 These bits represent counter value 15 8 of the current real time clock timer RTC_CNT2 Mode 1 and Mode 3 Count Clock Register 2 Reset Value 00 RMAP 0 PAGE X 7 6 5 4 3 2 1 0 CNT_VAL TWh Field Bits Type Description CNT_VAL 7 0 rwh Real Time Clock Count Value 23 16 These bits represent counter value 23 16 of the current real time clock timer RTC_CNT3 Mode 1 and Mode 3 Count Clock Register 3 E4 Reset Value 00 RMAP 0 PAGE X 7 6 5 4 3 2 1 0 CNT_VAL rwh Field Bits Type Description CNT VAL 7 0 rwh Real Time Clock Count Value 31 23 These bits represent counter value 31 23 of the current real time clock timer In Mode 1 and Mode 3 4 compare and capture registers RTCCRO RTCCR3 are used to represent 32 bits of compare values that will generate a compare event when it matches the counter values as specified in CNT register When a capture event is triggered by setting RTCCT bit t
278. Receiver Input 1 is selected 010 SSC Slave Receiver Input 2 is selected 011 SSC Slave Receiver Input 3 is selected 100 SSC Slave Receiver Input 4 is selected 101 Reserved 110 Reserved 111 Reserved CIS Slave Mode Clock Input Select 0 SSC Slave Clock Input 0 is selected 1 SSC Slave Clock Input 1 is selected 2 7 Reserved Returns 0 if read should be written with 0 User s Manual SSC V1 4 18 5 V1 0 2010 02 Cinfineon neers High Speed Synchronous Serial Interface 18 2 2 Clocking Configuration The SSC runs on the PCLK at a frequency of either 8 MHz or 24 MHz If the SSC functionality is not required at all it can be completely disabled by gating off its clock input for maximal power reduction The bit field PAGE of register SCU_PAGE must be programmed before accessing the PMCON register PMCON1 Peripheral Management Control Register 1 EF Reset Value DF RMAP 0 PAGE 1 7 6 5 4 3 2 1 0 DIS LTS DIS 0 DIS T2 DIS DIS SSC DIS DIS rw rw r rw rw rw rw rw Field Bits Type Description SSC DIS 1 rw SSC Disable Request Active high 0 SSC is in normal operation 1 Request to disable the SSC default 0 5 r Reserved Returns 0 if read should be written with 0 User s Manual 18 6 V1 0 2010 02 SSC V1 4 Cinfineon neers High Speed Synchronous Serial Interface 18 2 3 Interrupt Events an
279. Register High Byte Type rwh F5H LINST Reset 004 Bit Fie BGS SYNE ERRS EOFS BRK 0 LIN Status Register N YN YN Type TW rw rwh rwh rwh r Fey FEAL Reset 004 Bit Fie ECCERRADDR Flash Error Address Register Low Type rh User s Manual 3 17 V1 0 2010 02 Memory Organization V 0 1 Infineon XC82x Memory Organization Table 3 3 SCU Register Overview cont d Addr Register Name Bit 7 6 5 4 3 2 1 0 FEAH Reset 004 Bit Field ECCERRADDR Flash Error Address Register High Type th 3 4 5 4 Port Registers The Port SFRs can be accessed in the standard memory area RMAP 0 Table 3 4 Port Register Overview Addr Register Name Bit 7 6 5 4 3 2 1 0 IRMAP 0 PORT PAGE Reset 004 Bit Field OP STNR 0 PAGE Page Register Type w w r rw RMAP 0 PAGE 0 PO_DATAOUT Reset 7 Bit Field 0 P6 P5 P4 P3 P2 1 PO PO Data Output Register Type rw rw rw rw rw rw rw PO DATAIN Reset Bit Field 0 6 P5 P4 P3 P2 P1 PO PO Data In Register Type r rh rh rh rh rh rh rh 901 P1 DATA Reset Bit Field 0 P5 P4 2 P1 PO P1 Data Register Type r rw rw rw rw rw TW 91H P1_DATAIN Reset Bit Field 0 5 4 P2 P1 PO P1 Data In Register Type r rh rh rh rh rh rh 94H P2_DATAIN Reset 0
280. Register Type r rw rw rw rw rw rw rw P1_ALTSELO Reset 004 Bit Field 0 P5 P4 P3 P2 1 PO P1 Alternate Select 0 Register Type r rw rw rw rw rw rw 91H P1_ALTSEL1 Reset 00 Bit Field 0 BS P4 P3 P2 P1 PO P1 Alternate Select 1 Register Type r rw TW rw rw rw TW RMAP 0 PAGE 3 OD Reset Bit Field 0 P6 DS P4 P3 P2 P1 PO Open Drain Control Register Type r rw rw rw rw rw rw TW 90H P1_OD Reset Bit Field 0 PS P4 2 1 P1 Open Drain Control Register Type r rw rw rw rw rw rw 94H P2_EN Reset 004 Bit Field 0 P3 P2 Pi P2 Enable Register Type r rw rw rw rw 3 4 5 5 ADC Registers The ADC SFRs be accessed in the standard memory area RMAP 0 Table 3 5 ADC Register Overview Addr Register Name Bit 7 6 5 4 3 2 1 0 IRMAP 0 Diy ADC_PAGE Reset 004 Bit Field OP STNR 0 PAGE Page Register Type w w r rw RMAP 0 PAGE 0 ADC_GLOBCTR Reset 304 Bit Field ANON DW CTC ORCIE CLCIE 0 Global Control Register N N Type rw rw rw rw TW r CBH ADC GLOBSTR Reset 004 Bit Field 0 0 BUSY Global Status Register LE Type r rh rh CCH ADC_PRAR Reset 004 Bit Field ASEN ASEN 0 ARBM CSM1 PRIO1 CSMO PRIOO Priority and Arbitration Register 1 0 Type rw TW r rw rw rw rw TW CDH ADC_LCBRO Reset 704 Bit Field BOUNDO Limit Check Boundary Register 0 Type User s
281. Reserved Returns 0 if read should be written with 0 Table 11 8 Function of Bits P1 ALTSELO Pn and P1_ALTSEL1 Pn P1 ALTSEL1 Pn P1 ALTSELO Pn Function 0 0 Normal GPIO default 0 1 Alternate Select 1 User s Manual 11 28 V1 0 2010 02 Cinfineon XC82x Parallel Ports Table 11 8 Function of Bits P1 ALTSELO Pn and P1_ALTSEL1 Pn cont d P1_ALTSEL1 Pn P1 ALTSELO Pn Function 1 0 Alternate Select 2 1 1 Alternate Select 3 User s Manual 11 29 V1 0 2010 02 Cinfineon Parallel Ports 11 4 Port 2 Port 2 is a general purpose input only port In XC82x Port 2 has 4 pins P2 0 P2 3 The registers of Port 2 are summarized in Table 11 9 Table 11 9 Port 2 Registers Register Short Name Register Long Name P2_DATAIN Port 2 Data Register P2_EN Port 2 Enable Register P2_PUDSEL Port 2 Pull Up Pull Down Select Register P2_PUDEN Port 2 Pull Up Pull Down Enable Register User s Manual 11 30 V1 0 2010 02 Cinfineon XC82x 11 4 1 Functions Port 2 input and output functions are shown in Table 11 10 Table 11 10 Port 2 Input Functions Parallel Ports Port Pin Input Output Select Connected Signal s From to Module P2 0 Input GPI P2 DATAIN PO ALT 1 CCPOSO 1 CCUG ALT 2 T12HR 2 CCUG ALT 3 T13HR 2 CCUG ALT 4 T2EX 3 Timer 2 ALT 5 T2 1 Timer 2 ALT 6
282. Returns 0 if read should be written with 0 IRCON2 Interrupt Request Register 2 5 Reset Value 00 RMAP 0 PAGE 0 7 6 5 4 3 2 1 0 0 CCU6SR1 0 CCU6SRO r rwh r rwh Field Bits Type Description CCU6SRO 0 rwh Interrupt Flag 0 for CCU6 This bit is set by hardware and can only be cleared by software 0 Interrupt event has not occurred 1 Interrupt event has occurred User s Manual 9 25 V1 0 2010 02 Interrupt System V 2 3 3 Cinfineon Interrupt System Field Bits Type Description CCU6SR1 4 rwh Interrupt Flag 1 for CCU6 This bit is set by hardware and can only be cleared by software 0 Interrupt event has not occurred 1 Interrupt event has occurred 0 3 1 r Reserved 7 5 Returns 0 if read should be written with 0 IRCON3 Interrupt Request Register 3 F6 Reset Value 00 RMAP 0 PAGE 0 7 6 5 4 3 2 1 0 0 CCU6SR3 0 CCU6SR2 r rwh r rwh Field Bits Type Description CCU6SR3 4 rwh Interrupt Flag 3 for CCU6 This bit is set by hardware and can only be cleared by software 0 Interrupt event has not occurred 1 Interrupt event has occurred CCU6SR2 0 rwh Interrupt Flag 2 for CCU6 This bit is set by hardware and can only be cleared by software 0 Interrupt event has not occurred 1 Interrupt event has occurred 0 3 1 r Reserved 7 5 Returns 0 if read should be written with 0
283. Ri 66 67 1 1 2 XRL A data 64 2 1 3 XRL dir A 62 2 1 3 XRL dir data 63 3 2 5 CLRA E4 1 1 2 CPLA F4 1 1 2 SWAP A C4 1 1 2 RLA 23 1 1 2 RLC A 33 1 1 2 RRA 03 1 1 2 RRC A 13 1 1 2 User s Manual 2 11 V1 0 2010 02 XC800 Core V 1 0 2 on Cinfineon 800 Table 2 1 Instruction Table cont d Mnemonic Hex Code Bytes Machine Machine Cycles Cycles one wait state no wait state DATA TRANSFER MOV A Rn E8 EF 1 1 2 MOV Air E5 2 1 3 MOV A Ri E6 E7 1 1 2 MOV A data 74 2 1 3 MOV Rn A F8 FF 1 1 2 MOV A8 AF 2 2 4 MOV Rn data 78 2 1 3 MOV dir A F5 2 1 3 MOV dir Rn 88 8F 2 2 4 MOV dir dir 85 3 2 5 MOV dir Ri 86 87 2 2 4 MOV dir data 75 3 2 5 MOV Ri A F6 F7 1 1 2 MOV Ri dir A6 A7 2 2 4 MOV Ri data 76 77 2 1 3 MOV DPTR data 90 3 2 5 MOVC A A DPTR 93 1 2 3 or 4 MOVC A A PC 83 1 2 3 or 4 MOVX A Ri E2 E3 1 2 3 MOVX A DPTR EO 1 2 3 MOVX Ri A F2 F3 1 2 3 MOVX QDPTR A FO 1 2 3 PUSH dir CO 2 2 4 POP dir DO 2 2 4 XCH C8 CF 1 1 2 A dir C5 2 1 3 XCH A QRi C6 C7 1 1 2 XCHD A Ri D6 D7 1 1 2 User s Manual XC800 Core V 1 0 2 N V1 0 2010 02 on Cinfineon 800 Table 2 1 Instruction Table cont d Mnemonic Hex Code By
284. SCTR contains the number of shift left operations that were done This number may be used later as an exponent The maximum number of shifts in a normalize operation is 31 25 1 12 3 3 Shift The MDU implements both logical and arithmetic shifts to support up to 32 bit unsigned and signed shift operations During logical shift zeros are shifted in from the left end of register MD3 or right end of register MDO An arithmetic left shift is identical to a logical left shift but during arithmetic right shifts signed bits are shifted in from the left end of register MD3 For example if the data 0101B and 1010B are to undergo an arithmetic shift right the results obtained will be 0010B and 1101B respectively For any shift operation register bit MD4 SLR specifies the shift direction and MD4 SCTR the shift count Note The MDU does not detect overflows due to an arithmetic shift left operation User must always ensure that the result of an arithmetic shift left is within the boundaries of MDU 12 3 4 Multiplication with Single Left Shift The multiplication with single left shift is similar to a signed 16 bit multiplication except that after the multiplication the MDU performs a single left shift on the product This operation can be used to facilitate signed fixed point number multiplications in 0151 format Multiplication of two Q15 numbers will result in a Q1 30 fixed point product A User s Manual 12 5 V1 0 2010 02 MDU V2 9
285. SEL3 Reset 004 Bit Fie IST13HR1 IST12HR1 CTRAPIS Peripheral Input Select Register 3 Type rw rw rw F24 XADDRH Reset Bit Fie ADDRH On chip XRAM Address Higher Order Type o F3 MODPISEL Reset 00 Bit Fie 0 CIS SIS 0 MIS Peripheral Input Select Register Type r rw rw r TW MODPISEL1 Reset 004 Bit Fie 0 EXINT 0 EXINTOIS 0 URRIS Peripheral Input Select Register 115 1 rw r TW r TW MODPISEL2 Reset 004 Bit Fie 0 TOIS T1IS 215 2 5 Peripheral Input Select Register 2 Type rw rw rw rw MODSUSP Reset 014 Bit Fie 0 LTS RTC T2SUS T13SU T12SU WDTS Module Suspend Control SUSP SUSP 5 SP USP Register Type rw TW rw rw rw TW MODIEN Reset 074 Bit Fie CCU6 CCU6 0 RIREN TIREN EIREN Peripheral Interrupt Enable SR3 SR2 Register EN EN Type TW rw r rw rw TW RMAP 0 PAGE 4 F3y WDTREL Reset 004 Bit Fie WDTREL Watchdog Timer Reload Register Type ny WDTWINB Reset 004 Bit Fie WDTWINB Watchdog Window Boundary Count Register Type dud WDTL Reset 004 Bit Fie WDT Watchdog Timer Register Low Type rh WDTH Reset 004 Bit Fie WDT Watchdog Timer Register High Type rh IRMAP 0 PAGE 5 F2y BCON Reset 004 Bit Fie BGSEL 0 BRDIS BRPRE R Baud Rate Control Register Type TW r TW rw TW F3y BGL Reset 004 Bit Fie BR_VALUE FDSEL Baud Rate Timer Reload Register Low Byte Type rwh TW BGH Reset 004 Bit Fie BR_VALUE Baud Rate Timer Reload
286. Sense Pad Turns are enabled 1 Time Slice PADTO PADT1 PADT2 PADTO 65 4 3 2 1 0 756 5 4 3 2 1 0 T5 6 5 4 32 1 0 19 6 5 4 3 2 1 O TS6 1 gt 8 Period hardware controlled scheme For example 7 LEDs and 3 Touch Sense Pad Turns are enabled AccumulatorCounter 7 0x04 1 Time Slice PADTO PADTO PADTO PADTO PADTO PADT1 PADT1 PADT1 Bless 0 TS 6 0 TS 8 0 T8 lt 6 0 TS 6 O TS 6 1 Time Frame 1Period 4 software controlled ROM library scheme _____ Single Pad Accumulated Count Period 4 PADTO gt lt PADT1 gt lt PADT2 gt lt PADTO gt 1Period 14 Single Pad Accumulated Count Period 1Period software controlled ROM library scheme ______________ All Enabled Pads Accumulated Count Period PDC decrements once each time in 1 period All Enabled PADTx Accumulated Count Period where a pad is touched in the case of a combination pad 2 pads touched the PDC decrements once also in 1 Period All Enabled PADTx Accumulated Count Period Figure 23 11 Period Relationship for Software Controlled ROM Library Scheme User s Manual 23 36 V1 0 2010 02 ROM Library V0 5 Infineon ROM Library 23 2 3 Use of the functions in Interrupts With correct inputs prepared for the functions the functions can be called from Time Slice interrupt or Time Frame int
287. Synch Byte Slave snoops for ID According to ID slave determines whether to receive or transmit data or do nothing When transmitting the slave sends 2 4 or 8 data bytes followed by check byte 16 6 2 LIN Header Transmission LIN header transmission is only applicable in master mode In the LIN communication a master task decides when and which frame is to be transferred on the bus It also identifies a slave task to provide the data transported by each frame The information needed for the handshaking between the master and slave tasks is provided by the master task through the header portion of the frame The header consists of a break and synch pattern followed by an identifier Among these three fields only the break pattern cannot be transmitted as a normal 8 bit UART data The break must contain a dominant value of 13 bits or more to ensure proper synchronization of slave nodes In the LIN communication a slave task is required to be synchronized at the beginning of the protected identifier field of frame For this purpose every frame starts with a sequence consisting of a break field followed by a synch byte field This sequence is unique and provides enough information for any slave task to detect the beginning of a new frame and be synchronized at the start of the identifier field 16 6 2 1 Automatic Synchronization to the Host Upon entering LIN communication a connection is established and the transfer speed baud
288. TAT IERR is provided to indicate that an error has occurred while performing a calculation The flag is set by hardware when one of these occurs Division by zero Writing of reserved opcodes to MDUCON register The setting of the error flag causes the current operation to be aborted and triggers an interrupt see Section 12 4 below A division by zero error does not set the error flag immediately but rather at the end of calculation phase for a division operation An opcode error is detected upon setting MDUCON START to 1 Errors due to division by zero lead to the loading of a saturated value into the MRx registers Note The accuracy of any result obtained when the error flag is set is not guaranteed by MDU and hence the result should not be used 1 The Q number is a fixed point number representation that takes the form Qx y where x is the number of bits in the integer portion of the number default is 0 while y is the number of bits in the fractional portion The signed bit is always excluded from the Qx y notation User s Manual 12 6 V1 0 2010 02 MDU V2 9 Cinfineon Multiplication Division Unit 12 4 Interrupt Generation The interrupt structure of the MDU is shown in Figure 12 2 There are two possible interrupt events in the MDU and each event sets one of the two interrupt flags The interrupt flags is reset by software by writing 0 to it At the end of phase two the interrupt flag MDUSTAT IRDY is set by hardware t
289. TCON register It can be triggered by application software where necessary 7 2 1 4 Power Down Wake Up Reset Power is still applied to the XC82x during power down mode as the low power voltage regulator is still operating If power down mode is entered appropriately all important system states will have been preserved in the Flash by software If the XC82x is in power down mode three options are available to awaken it through RTC wake up event depending on the type of power down mode through EXINTO pin through the failure of the RTC clock source Selection of option through EXINTO pin is made via the control bit PMCONO EWS The RTC wake up event and RTC clock failure could be used as the wake up sources depending on the type of power down mode The wake up from power down can be with reset or without reset this is chosen by the PMCONO WKSEL bit The wake up status with or without reset is indicated by the RSTCON WKRS bit The time needed for the device to be out of reset is faster as compared to the power on reset as the EVR takes a shorter time period to become stable 7 2 1 5 Brownout Reset In active mode detector in EVR detects brownout when the core supply voltage Vppc dips below the threshold voltage approximately 2 3 V or the threshold voltage Vppp approximately 2 9 V if the detector is enabled or e the threshold voltage Vopp approximately 2 4 V if the detector is disable
290. TR DW 0 RCRx DRCTR 1 RCRx DLPF 0 When this mode is chosen the targetted result register in ADC_RESRxL x 0 3 x 0 3 would be shown as Figure 21 25 After the 1st conversion in ADC_RESRxL x 0 3 result register bits 2 0 indicate the channel number whose conversion triggered the result event bits 7 5 returns bits 2 0 of the conversion results ADC_RESRxH x 0 3 bits 6 0 returns bits 9 3 of the conversion result Reading the result automatically clears the valid flag At the 2nd conversion onwards in ADC_RESRxL x 0 3 result register bits 2 0 User s Manual 21 65 V1 0 2010 02 ADC V2 1 Cinfineon XC82x Analog to Digital Converter indicate the channel number whose conversion triggered the result event bit 7 5 returns bits 2 0 of the accumulated result In ADC_RESRxH x 0 3 bits 7 0 returns bit 10 3 of the accumulated result Digital low pass filtered application read view RESRxL H 10bit conversion mode with Data Reduction Disabled and Digital Low Pass Filter enabled i e ADC_GLOBCTR DW 0 RCRx DRCTR 0 RCRx DLPF 1 This mode is only available for 10bit conversions and the Data Reduction Feature cannot be turned on when the Digital Low Pass Filter is being used since there is only one adder When this mode is chosen the targetted result register in ADC_RESRxL x 0 3 and ADC RESRxH x 0 3 would be shown as Figure 21 26 In ADC_RESRxL 0 3 bits 2 0 indicate the channel numb
291. The hardware triggers can be derived from several module signals or port inputs The external trigger control register contains bits to select the external trigger input signal source ADC_ETRCR External Trigger Control Register D3 Reset Value 00 RMAP 0 PAGE 4 7 6 5 4 3 2 1 0 0 ETRSEL1 ETRSELO T rw rw Field Bits Type Description ETRSELO 2 0 rw External Trigger Selection for Request Source x ETRSEL1 5 3 This bit field defines which external trigger input signal is selected 000g The trigger input is selected 001g The trigger input is selected 010g The trigger input REQTRxC is selected 011 The trigger input is selected 100 The trigger input is selected 101g The trigger input is selected 110g The trigger input REQTRxG is selected 111g The trigger input REQTRXH is selected 0 7 6 r Reserved Returns 0 if read should be written with 0 User s Manual 21 37 V1 0 2010 02 ADC V2 1 Cinfineon Analog to Digital Converter 21 7 Request Source Arbitration The request source arbiter regularly polls the request sources one after the other for pending conversion requests Each request source is assigned to a certain time slot within an arbitration round called arbitration slot The priority of each request source is user configurable via register ADC_PRAR so the arbiter can select the next
292. U_MDUSTAT B0 MDU Status Register MDU MDO MRO B2 MDU Data Result Register 0 MDU MD1 MR1 B3 MDU Data Result Register 1 MDU MD2 MR2 BA MDU Data Result Register 2 MDU MD3 MR3 B5 MDU Data Result Register 3 MDU MD4 MR4 B6 MDU Data Result Register 4 MDU MD5 MR5 B7 MDU Data Result Register 5 The MDx and MRx registers share the same address However since MRx registers should never be written to any write operation to one of these addresses will be interpreted as a write to an MDx register In the event of a read operation an additional bit MDUCON RSEL is needed to select which set of registers MDx or MRx the read operation must be directed to By default the MRx registers are read The 14 SFRs of the MDU consist of a control register MDUCON a status register MDUSTAT and 2 sets of data registers MDO to MD5 which contain the operands and MRO to MR5 which contain the results Depending on the type of operation the individual MDx and MRx registers assume specific roles as summarized in Table 12 5 and Table 12 6 For example in a multiplication operation the low byte of the 16 bit multiplicator must be written to register MD4 and the high byte to MD5 Table 12 5 MDx Registers Register Roles of Registers in Operations 16 bit 32 16 bit 16 16 bit Normalize and Multiplication Division Division Shift MDO M andL D endL D endL OperandL MD1 M andH D end D endH Operand MD2
293. User s Manual 23 25 V1 0 2010 02 ROM Library V0 5 Cinfineon ROM Library cannot enable PADTx and defined them as PADTO PADT4 and PADT6 for example it has to be PADTO PADT1 and PADT2 PADTx will remains for AccumulatorCounter 1 time and the function will increment the PADTx when TSCTR_COUNTER 2 is 0x00 and will repeat back to PADTO once the highest enabled PADTx is set For example if AccumulatorCounter is defined as Ox04 and 2 Touch sense Pad Turns are enabled the sequences for PADTx will be PADT1 PADT1 PADT1 PADT1 PADT1 PADTO PADTO PADTO PADTO PADTO PADT1 etc The cycle continues This function is normally called in a Time Frame interrupt But user can also call this function in a Time Slice interrupt A check whether LTS_GLOBCTL1 FNCOL 0x07 is implemented in this function therefore users can safely call this function in Time Slice interrupt after SET LDLINE CMP function without extra code check in between The function will check if this Time Slice is for Touch sense before executing the rest of the function If LTS GLOBCTL1 FNCOL is not 0x07 function will exit See Figure 23 13 1 Extra one count is for calculation of Average value 2 TSCTR COUNTER is a parameter in XRAM that holds the user defined input AccumulatorCounter and will decrement every time FINDTOUCHEDPAD function is entered when LTS GLOBCTL1 FNCOL 0x07 for Touch sense User s Manual 23 26 V1 0 2010 02 ROM Library V0 5 C
294. When the top of the sector is reached all actual User s Manual 4 3 V1 0 2010 02 Flash Memory V 0 1 Cinfineon Flash Memory data representing the EEPROM data is copied to the bottom area of the next sector and the last sector is then erased This round robin procedure using multifold replications of the emulated EEPROM size significantly increases the Flash endurance To speed up data search the RAM can be used to contain the pointer to the valid data set User s Manual 4 4 V1 0 2010 02 Flash Memory V 0 1 Infineon 4 3 The wordline WL addresses of Flash Bank 0 are given in Figure 4 3 XC82x Wordline Address Flash Memory Flash Bank 0 Byte 31 Byte 2 Byte 1 Byte 0 Byte 31 Byte 2 Byte 1 Byte 0 OFFFu OFE2u OFE1n amp AFFFi 2 1 0 amp oS g 5 5 Sx SRI 28 i SQ 29 9 85 II OF82 81 OF80 DI AF824 AF814 AF804 E re 62 OF61u 0 60 5 Eee AF624 1 Q ore oS ese i 82 i i gig d E Gus 81 OF 1F 4 2 0 01 OFOO
295. XC82x memory protection strategy features read out protection of user intellectual property IP Other key features include a Capture Compare Unit 6 CCU6 for the generation of pulse width modulated signal with special modes for motor control a 10 bit Analog to Digital Converter ADC with out of range comparator that has differential input channels and extended functionalities such as autoscan and result accumulation for anti aliasing filtering or for averaging a Multiplication Division Unit MDU to support the XC800 Core in math intensive computations in advanced motor control like Field Oriented Control a LED and Touch sense Controller LEDTSCU for driving 7 segment displays in a LED matrix and supporting touch sense function concurrently a Real Time Clock RTC to support periodic wake up in low power application and an On Chip Debug Support OCDS unit for software development and debugging of XC800 based systems Local Interconnect Network LIN applications are also supported through extended UART features and the provision of LIN low level drivers for most devices For low power applications various power saving modes are available for selection by the user Control of the numerous on chip peripheral functionalities is achieved by extending the Special Function Register SFR address range with an intelligent paging mechanism optimized for interrupt handling Figure 1 1 shows the functional units of the XC82x
296. XD_1 UART Receive Input UART BSL Receive Input SDA 0 Data Line MTSR 1 SSC Slave Receive Input MRST 0 SSC Master Receive Input Slave Transmit Output EXINTO 1 External Interrupt Input 0 T2EX 0 Timer 2 External Trigger Input TSING Touch sense Input 6 LINE6 LED Line 6 TXD 0 UART Transmit Output 1 wire UART BSL Transmit Output COL2 1 LED Column 2 COLA 1 LED Column A User s Manual System Architecture V1 0 1 8 V1 0 2010 02 Cinfineon XC82x Introduction Table 1 1 Pin Definitions and Functions for XC82x Symbol Pin Type Reset Function Number State DSO20 TSSOP16 P1 I O Port 1 Port 1 is a bidirectional general purpose I O port It can be used as alternate functions for CCU6 LEDTSCU SPD UART and Timer 2 P1 0 8 7 Hi Z SPD 1 SPD Input Output RXD 2 UART Receive Input T2EX 2 Timer 2 External Trigger Input EXINTO 2 External Interrupt Input 0 COLO 0 LED Column 0 COUT60 0 Output of Capture Compare Channel 0 TXD 1 UART Transmit Output P1 1 9 Hi Z CC60 0 Input Output of Capture Compare channel 0 COL1 0 LED Column 1 TXD 2 UART Transmit Output P1 2 10 8 Hi Z EXINT4 External Interrupt Input 4 COL2_0 LED Column 2 COUT61_0 Output of Capture Compare channel 1 COUT63_0 Output of Capture Compare channel 3 P1 3 11 Hi Z CC61 0 Input Output of Capture Compare channel 1 COL3 0 LED Column 3 EXF2 1 Timer 2 Overflow Flag User s Manual 1 9 V1 0 2010 02 System Archit
297. _UART_BSL Input IENO EA 0 NMICON 0x00 BCON BGSEL SFR field bit to be set accordingly Stack Pointer SP Setting 0x07 lt SP lt 0x60 or SP OxEO Output Stack size required Resource used destroyed 22 6 Flash Program Subroutine Each call of the Flash program subroutine allows the programming of e 32 of data bytes WL aligned into selected Flash wordline Before calling this subroutine the user must ensure that the Flash content to be programmed should be buffered in an identically sized IRAM buffer Two types of Flash programing routines will be offered to users The calling of the erase and program user routines can be called from XRAM or Flash Table 22 2 shows the description of how to use and call these routines The first type of routine supports non background programming BR FLASH PROGRAM will wait until programming is done before allowing user program to continue with its execution This type of routine is necessary for users who need to program the Flash bank where the user code is in execution especially when there will be only one flash bank The Flash cannot be in both program mode and read mode at the same time It is also useful for users who wish to program the Flash Bank where the interrupt vectors are defined as interrupts cannot be handled when the Flash Bank is in program mode as the interrupt handler cannot be fetched For Type 1 program routine Boot ROM will control the c
298. a Output 4 PO ALTSELO P5 0 PO ALTSEL1 P5 0 PO ALTSEL2 P5 1g The bit field PAGE of SCU PAGE register must be programmed before accessing the MODPISEL1 register MODPISEL1 Peripheral Input Select Register 1 4 Reset Value 00 RMAP 0 PAGE 3 7 6 5 4 3 2 1 0 0 EXINT1IS 0 EXINTOIS 0 URRIS r rw r TW r TW Field Bits Type Description URRIS 1 0 rw UART Receive Input Select 00 UART Receiver Input 0 is selected 01 UART Receiver Input RXD 1 is selected 10 UART Receiver Input RXD 2 is selected 11 UART Receiver Input RXD 3 is selected 0 2 5 r Reserved 7 Returns 0 if read should be written with O 16 2 2 Clocking Configuration The UART runs on the PCLK at a frequency of either 8 MHz or 24 MHz User s Manual 16 2 V1 0 2010 02 UART V 1 6 Cinfineon UART 16 2 3 Interrupt Events and Assignment Table 16 2 lists the interrupt event sources from the UART and the corresponding event interrupt enable bit and flag bit Table 16 2 UART Interrupt Events Event Event Interrupt Enable Bit Event Flag Bit Data Received SCON RI Data Transmitted SCON TI Table 16 3 shows the interrupt node assignment for each UART interrupt source Table 16 3 UART Events Interrupt Node Control Event Interrupt Node Interrupt Node Flag Vector Enable Bit Bit Address Data Received IENO ES 234 Data Transmitted
299. a bit RB8 is 0 In mode 1 if SM2 is set to 1 RI will not be activated if a valid stop bit RB8 was not received In mode 0 SM2 should be 0 SM1 6 rw Serial Port Operating Mode Selection See definition for SMO SMO 7 rw Serial Port Operating Mode Selection SMO SM1 00 Mode 0 8 bit shift register fixed baud rate 2 01 Mode 1 8 bit UART variable baud rate 10 Mode 2 9 bit UART fixed baud rate 64 or foc 32 11 Mode 3 9 bit variable baud rate User s Manual UART V 1 6 16 21 V1 0 2010 02 Cinfineon 16 7 2 Baud rate Generator Control and Status Registers PCON Power Control Register 87 4 Reset Value 00 RMAP X PAGE X 7 6 5 4 3 2 1 0 SMOD 0 GF1 GFO 0 IDLE rw r rw rw r rw Field Bits Type Description SMOD 7 rw Double Baud Rate Enable Og not double the baud rate of serial interface in modes 1 2 and 3 1g Double the baud rate of serial interface in mode 2 and in modes 1 and 3 only if Timer 1 is used as variable baud rate source 0 1 6 4 r Reserved Returns 0 if read should be written with 0 BCON Baud Rate Control Register 2 Reset Value 00 RMAP 0 PAGE 5 7 6 5 4 3 2 1 0 BGSEL 0 BRDIS BRPRE R TW r rw rw rw Field Bits Type Description R 0 rw Baud Rate Generator Run Control Bit 0s generator disabled 1g Baud rate generato
300. a valid start bit the controller goes back to looking for a high to low transition on RXD When the start bit reaches the leftmost position the control block executes one last shift then loads SBUF with the 8 data bits loads RB8 SCON 2 with the 9th data bit and sets the RI bit provided RI 0 and either SM2 0 see Section 16 4 or the 9th bit 1 If none of these conditions is met the received byte is lost The baud rate for the transfer is either 64 or fc 32 depending on the setting of the top bit SMOD of the PCON Power Control register which acts as a Double Baud Rate selector 16 3 4 3 9 Bit UART Variable Baud Rate Mode 3 is the same as mode 2 in all respects except that the baud rate is variable In all modes transmission is initiated by any instruction that uses SBUF as a destination register Reception is initiated in the modes by the incoming start bit if REN 1 The serial interface also provides interrupt requests when transmission or reception of the frames has been completed The corresponding interrupt request flags are TI or RI respectively If the serial interrupt is not used i e serial interrupt not enabled TI and RI can also be used for polling the serial interface The associated timings for transmit receive in modes 2 and 3 are illustrated in Figure 16 2 User s Manual 16 6 V1 0 2010 02 UART V 1 6 82 UART HUS
301. able for devices that have 8 ADC channels For channels not implemented these bits should be treated as Reserved bits of type f which returns 0 if read and should be written with V 4 rh Request Channel Number Valid This bit indicates if the data in REQCHNR RF ENSI and EXTR is valid Bit V is set if a running conversion is aborted It is reset when the conversion is started Og The backup register does not contain valid data because the conversion described by this data has not been aborted 1g The data is valid The aborted conversion is requested before taking into account what is requested by QORO RF 5 rh Refill This bit is updated by bit QORO RF when the conversion requested by QORO is started ENSI 6 rh Enable Source Interrupt This bit is updated by bit QORO ENSI when the conversion requested by QORO is started EXTR 7 rh External Trigger This bit is updated by bit QORO EXTR when the conversion requested by QORO is started 0 3 r Reserved Returns 0 if read should be written with 0 User s Manual 21 36 V1 0 2010 02 ADC V2 1 Cinfineon Analog to Digital Converter Note Registers QBURx share addresses with registers QINRx Read operations return the status bits from register QBURx Write operations target the control bits in register QINRx 21 6 3 Hardware Trigger Selection Each request source can be activated either by software or by a hardware trigger signal
302. achieved by this feature depends on the number of peripherals running Peripherals that are not required for a particular functionality can be disabled by gating off the clock inputs For example in idle mode if all timers are stopped and ADC CCU6 MDU and the serial interfaces are not running maximum power reduction can be achieved However the user must take care when determining which peripherals should continue running and which must be stopped during active and idle modes The ADC SSC CCU6 MDU LEDTSCU IIC Timer 2 can be disabled clock is gated off by setting the corresponding bit in the PMCON1 register Furthermore the analog part of the ADC module may be disabled by resetting the GLOBCTR ANON bit This feature causes the generation of the ADC analog clock to be stopped and allows a reduction in power consumption when no conversion is needed PMCON1 Peripheral Management Control Register 1 EF Reset Value DF RMAP 0 PAGE 1 7 6 5 4 3 2 1 0 DIS LTS DIS 0 MDU DIS T2 DIS DIS SSC DIS DIS rw rw r rw rw rw rw rw Field Bits Type Description ADC DIS 0 rw ADC Disable Request Active high 0 ADC is in normal operation 1 Request to disable the ADC default SSC DIS 1 rw SSC Disable Request Active high 0 SSC is in normal operation 1 Request to disable the SSC default CCU DIS 2 rw CCU Disable Request Active high 0 CCU is in normal operation 1 Reque
303. ad event If a hardware trigger is selected and enabled generate the configured transition at the selected input signal e g from a timer or an input pin Generate a software load event by setting ADC_CRMR1 LDEV 1 Generate a load event by writing the scan pattern directly to the pending bits in CRPR1 The pattern is copied to ADC_CRCR1 and a load event is generated automatically In this case a scan sequence can be defined and started with a single data write action Note If autoscan is enabled a load event is generated automatically each time a request source event occurs when the scan sequence has finished This permanently repeats the defined scan sequence autoscan Stop or abort an ongoing scan sequence by executing the following actions If external gating is enabled switch the gating signal to the defined inactive level This does not modify the conversion pending bits but only prevents issuing conversion requests to the arbiter Disable the corresponding arbitration slot 1 in the arbiter This does not modify the contents of the conversion pending bits but only prevents the arbiter from accepting requests from the request handling block Disable the channel scan source by clearing bitfield ENGT Og Clear the pending request bits by setting bit ADC_CRMR1 CLRPND 1 User s Manual 21 20 V1 0 2010 02 ADC V2 1 Cinfineon Analog to Digital Converter Scan Request Source Events and Interrupts A
304. adow transfer for the T12 period register to capture the current T12 contents into register CC60R and to clear T12 Note In this mode the shadow transfer signal T12 ST is not generated Not all shadow bits such as the PSLy bits will be transferred to their main registers To program the main registers SW needs to write to these registers while Timer T12 is stopped In this case a SW write actualizes both registers User s Manual 20 96 V1 0 2010 02 CCU6 V4 0 Cinfineon Capture Compare Unit 6 CCU6 CC62 Compare Hall Event captures for Time Out and resets T12 CC62 Comp T12 Count CC61 Compare CC61 Comp for Phase Delay 0000 CCPOSO 1 1 1 0 0 CCPOS1 0 0 1 1 1 CCPOS2 1 0 0 0 1 CURH EXPH MCMP Phase Delay COUT6y CCUG MCTO5539 Figure 20 40 Brushless DC Motor Control Example all MSEL6x 10005 After the detection of an expected Hall pattern CM CHE active the T12 count value is captured into channel CC60 representing the actual rotor speed by measuring the elapsed time between the last two correct Hall events and T12 is reset When the timer reaches the compare value in channel CC61 the next multi channel state is switched by triggering the shadow transfer of bit field MCMP This trigger event can be combined with the synchronization of the next multi channel state to the PWM source to avoid spikes on the output lines see Section 20 6 This co
305. age thresholds must be reached before the system starts operation with the release of the system reset The CPU then starts to execute from the Boot ROM firmware The Watchdog Timer WDT module is also capable of resetting the device if it detects a malfunction in the system Another type of reset that needs to be detected is the reset while the device is in power down mode i e wake up reset While the contents of the static RAM are undefined after a power on reset they are well defined after a wake up reset from power down mode A brownout reset is triggered if the Vbpc supply voltage dips below 2 3 V or Vbpp supply voltage dips below 2 9 V provided the detector is enabled As for soft reset it can be triggered by application software where applicable 7 2 1 Types of Reset 7 2 1 1 Power On Reset The supply voltage Vppp is used to power up the chip The EVR is the first module in the chip to be reset which includes 1 Startup of the main voltage regulator and the low power voltage regulator 2 When Vppp and Vppc reach the threshold of the Vppp and detectors the reset of EVR becomes inactive When the system starts up the device is running in active 8 MHz mode using internal 48 MHz oscillator clock as the system frequency Once the 48 MHz oscillator is stable which is 480 oscillations after EVR is stable Flash has to be in the ready to read mode before the deassertion of the system reset In user mode the system cloc
306. al CC6xIN and signal CCPOSx Counter Register T12 fri CC6xIN om bt ib Selection Detect Shadow Register CC6xSR Register CC6xR CC6x_R CC6x F gt To Interrupt Logic Joce Set State Bit CC6xST Set Capture Edge XD ae MSEL6x Figure 20 21 Multi Input Capture Modes Block Diagram CCPOSx CCU6_MCB05524 In each of these modes the current T12 contents are captured in register CC6xR in response to a selected event at signal CC6xIN and in register CC6xSR in response to a selected event at signal CCPOSx The possible events can be opposite input transitions or the same transitions or any transition at the two inputs The different options are detailed in Table 20 9 In each of the various capture modes the Channel State Bit CC6xST is set to 1 when the selected capture trigger event at signal CC6xIN or CCPOSx has occurred The State Bit is not cleared by hardware but can be cleared by software In addition appropriate signal lines to the interrupt logic are activated that can generate an interrupt request to the CPU Regardless of the selected active edge all edges detected at signal CC6xIN can lead to the activation of the appropriate interrupt request line see also Section 20 9 User s Manual 20 39 V1 0 2010 02 CCU6 V4 0 Cinfineon XC82x Capture Compare Unit 6 CCU6
307. an be ignored 6 The CPU operation is resumed The core will return to execute the next instruction after the instruction which sets the PD bit Note For this case no interrupt will be generated by the EXINTO wake up source even if EXINTO is enabled before entering power down mode It is the same for the rest of the wake up sources An interrupt will be generated only if EXINTO fulfils the interrupt generation conditions after CPU resumes operation As for exiting power down mode to active mode in reduced voltage condition the active current must be below the limits as specified in the Data Sheet A brownout reset may occurred immediately after wakeup if the condition is not met After wake up from power down mode without reset the status flag of the wake up event can be used to indicate the source of wake up In addition the oscillator watchdog needs to be re enabled if necessary by setting bit RCOWDRST in OSC CON register But before the oscillator watchdog can be enabled it is required to ensure that the 48 MHz and 75 KHz oscillators are stable by checking the status of 5 CON INTOSC ST status flag See Section 7 3 1 for more detail descriptions In power down mode 1 real time clock is stopped and user is required to enabled it once the chip exit power down mode User s Manual 7 20 V1 0 2010 02 Cinfineon System Control Unit 7 4 1 3 Peripheral Clock Management The amount of reduction in power consumption that can be
308. an interrupt request to the core Additionally with a falling rising edge chosen by T2MOD EDGESEL on pin T2EX the contents of the timer register THL2 are captured into the RC2 register The external input is sampled in every PCLK clock cycle When a sampled input shows a low high level in one PCLK clock cycle and a high low in the next PCLK clock cycle a transition is recognized If the capture signal is detected while the counter is being incremented the counter is first incremented before the capture operation is performed This ensures that the latest value of the timer register is always captured If bit TZRHEN is set Timer 2 is started by first falling edge rising edge at pin T2EX which is defined by bit T2REGS If bit EXEN2 is set bit EXF2 is also set at the same point when Timer 2 is started with the same falling edge rising edge at pin T2EX which is defined by bit EDGESEL The capture will happen with the following negative positive transitions at pin T2EX which is defined by bit EDGESEL When the capture operation is completed bit EXF2 is set and can be used to generate an interrupt request Figure 14 3 describes the capture function of Timer 2 User s Manual 14 8 V1 0 2010 02 Timer 2 V 1 2 Cinfineon XBox Timer 2 PREN Overflow Timer 2 Interrupt Figure 14 3 Capture Mode 14 6 Count Clock The count clock for the auto reload mode is chosen by the bit C T2 in register T2CON If
309. and COUT6xO if it should be active before or after the compare value has been reached see register CMPSTATL CMPSTATH With this selection the active conducting phases of complementary power switches in a power inverter bridge leg can be positioned with respect to the compare value e g signal CC6xO can be active before whereas COUT6xO can be active after the compare value is reached Like this the output modulation the trap logic and the output level selection can be programmed independently for each output signal although two output signals are referring to the same compare channel User s Manual 20 34 V1 0 2010 02 CCU6 V4 0 Cinfineon Capture Compare Unit 6 CCU6 20 3 4 3 Output Modulation and Level Selection The last block of the data path is the Output Modulation block Here all the modulation sources and the trap functionality are combined and control the actual level of the output pins controlled by the modulation enable bits T1xMODENy and MCMEN in register MODCTRL MODCTRH The following signal sources can be combined here for each T12 output signal see Figure 20 18 for compare channel CC60 A T12 related compare signal CC6x O for outputs CC6x or COUT6x for outputs COUT6x delivered by the T12 block state selection with dead time with an individual enable bit T12MODENy per output signal y 0 2 4 for outputs CC6x and y 1 3 5 for outputs COUT6x The 13 related compare signal CC63 O delivered
310. annels 20 25 1 Channel State Bits 20 26 1 Hysteresis Like Control Mode 20 31 1 Compare Mode Output Path 20 32 1 Dead Time Generation 20 32 1 State Selection 20 34 1 Output Modulation and Level Selection 20 35 1 T12 Capture Modes 2 2 20 37 1 T12 Shadow Register Transfer 20 41 1 Timer T12 Operating Mode Selection 20 42 1 T12 related Registers 20 43 1 T12 Counter Register 20 43 1 Period Register 20 44 1 User s Manual 1 9 V1 0 2010 02 Cinfineon 20 3 8 3 Capture Compare Registers 20 46 1 20 3 8 4 Capture Compare Shadow Registers 20 47 1 20 3 8 5 Dead time Control Register 20 49 1 20 3 9 Capture Compare Control Registers 20 51 1 20 3 9 1 Channel State Bits 20 51 1 20 3 9 2 T12 Mode Control Register 20 55 1 20 3 9 3 Timer Control Registers 20 57 1 20 4 Operating 13 22 2 2 2 2 20 67 1 20 4 1 T13 Overview crm
311. ant to the Timer 0 and 1 13 2 1 Pinning Timer 0 and 1 can be used as an event counter which count 1 to 0 transitions at their external input pins TO and T1 These pins are selected from two different sources TO 0 and TO 1 for Timer 0 and T1 O and T1 1 for Timer 1 Timer 0 and 1 pin assignment for XC82x is shown in Table 13 1 This selection is performed by the SFR bits MODPISEL2 TOIS and MODPISEL2 T1IS Table 13 1 Timer 0 and 1 Pin Functions in XC82x Pin Function Desciption Selected By PO 1 TO 0 Timer 0 Input MODPISEL2 TOIS 0g P2 1 TO 1 MODPISEL2 TOIS 1 PO 2 T1 0 Timer 1 Input MODPISEL2 T1IS 0g P2 2 T1_0 MODPISEL2 T1IS 0g User s Manual 13 1 V1 0 2010 02 Timer 0 and 1 V1 0 Cinfineon 0 1 The bit field of SCU_PAGE register must be programmed before accessing the MODPISEL2 register MODPISEL2 Peripheral Input Select Register 2 F5 Reset Value 00 RMAP 0 PAGE 3 7 6 5 4 3 2 1 0 0 TOIS T1IS 215 2 r rw rw rw rw Field Bits Description 115 5 rw Timer 1 Input Select 0 Timer 1 Input T1_0 is selected 1 Timer 1 Input T1_1 is selected TOIS 6 rw Timer 0 Input Select 0 Timer 0 Input _0 is selected 1 Timer 0 Input TO 1 is selected 0 7 r Reserved Returns 0 if read should be written with 0 13 2 2 Clocking Configuration The Timer 0 and 1 runs on th
312. arallel Ports Table 11 5 Function of Bits ALTSEL2 Pn PO_ALTSEL1 Pn cont d and PO ALTSELO Pn PO ALTSEL2 Pn PO ALTSEL1 Pn PO ALTSELO Pn Function 0 1 1 Alternate Select 3 Alternate Select 4 Alternate Select 5 Alternate Select 6 1 1 1 1 o o O O Alternate Select 7 User s Manual 11 21 V1 0 2010 02 Cinfineon XC82x 11 3 Port 1 Parallel Ports Port 1 is a general purpose bidirectional port In XC82x P1 uses the standard bidirectional pad for each pin The registers of Port 1 are summarized in Table 11 6 Table 11 6 Port 1 Registers Register Short Name Register Long Name P1_DATAOUT Port 1 Data Out Register P1_DATAIN Port 1 Data In Register P1 OD Port 1 Open Drain Control Register P1 PUDSEL Port 1 Pull Up Pull Down Select Register P1 PUDEN Port 1 Pull Up Pull Down Enable Register P1 ALTSELO Port 1 Alternate Select Register 0 P1 ALTSEL1 Port 1 Alternate Select Register 1 User s Manual 11 22 V1 0 2010 02 Cinfineon 11 3 1 XC82x Functions Port 1 input and output functions are shown in Table 11 7 Parallel Ports Table 11 7 Port 1 Input Output Functions Port Pin Input Output Select Connected Signal s From to Module P1 0 Input P1 DATAIN PO ALT 1 RXD 2 UART ALT 2 2 2
313. at all it can be completely disabled by gating off its clock input for maximal power reduction This is done by setting bit CCU_DIS in register PMCON 1 as described below The bit field PAGE of SCU PAGE register must be programmed before accessing the PMCON1 register PMCON1 Peripheral Management Control Register 1 EF Reset Value DF RMAP 0 PAGE 1 7 6 5 4 3 2 1 0 DIS LTS DIS 0 MDU DIS T2 DIS CCU DIS SSC DIS ADC DIS rw rw r rw rw rw rw rw Field Bits Type Description CCU_DIS 2 rw CCU6 Disable Request Active high 0 CCU6 is in normal operation 1 Request to disable the CCU6 default 0 5 r Reserved Returns 0 if read should be written with 0 User s Manual 20 12 V1 0 2010 02 CCU6 V4 0 Cinfineon Capture Compare Unit 6 CCU6 20 2 3 Interrupt Events and Assignment Table 20 3 lists the interrupt event sources from the CCU6 and the corresponding event interrupt enable bit and flag bit Table 20 3 CCU6 Interrupt Events Event Event Interrupt Enable Bit Event Flag Bit Service Request Output See See IENL IENH See ISL ISH SRO SR1 Section 20 9 SR2 SR3 Table 20 4 shows the interrupt node assignment for each CCU6 interrupt source Table 20 4 CCU6 Events Interrupt Node Control Event Interrupt Node Enable Bit Interrupt Node Flag Vector Bit Address SRO IEN1 ECCIPO IRCON2 CCUGSRO 53 SR1 IEN1
314. at have a similar structure for their set and clear actions It is recommended that SW checks the interrupt bits bit wisely instead of common OR over the bits ISL Interrupt Status Register Low 9 Reset Value 00 RMAP 0 PAGE 3 7 6 5 4 3 2 1 0 12 T120M ICC62F ICC62R ICC61F ICC61R ICC60F ICC60R rh rh rh rh rh rh rh rh Field Bits Type Description ICC60R 0 rh Capture Compare Match Rising Edge Flag ICC61R 2 This bit indicates that event CC6x R has been ICC62R 4 detected This event occurs in compare mode when a compare match is detected while T12 is counting up CM 6x and CDIR 0 and in capture mode when a rising edge is detected at the related input CC6xIN Og event has not yet been detected 1g event has been detected User s Manual 20 112 V1 0 2010 02 CCUG V4 0 Cinfineon XC82x Capture Compare Unit 6 CCU6 Field Bits Type Description ICC60F 1 rh Capture Compare Match Falling Edge Flag ICC61F 3 This bit indicates that event CC6x_F has been ICC62F 5 detected This event occurs in compare mode when a compare match is detected while T12 is counting down CM_6x and CDIR 1 and in capture mode when a falling edge is detected at the related input CC6XxIN Og The event has not yet been detected 1g event has been detected T120M 6 rh Timer T12 One Match Flag T
315. at least one arbiter round before the trigger event occurs If bit ADC PRAR ARBM 0 the arbiter runs permanently The trigger for the conversion triggers has to be generated synchronously to the arbiter timing Incoming triggers should have exactly n times the granularity of the arbiter n 1 2 3 In order to allow some flexibility the duration of an arbitration slot can be programmed in cycles of If bit PRAR ARBM 1 the arbiter stops after an arbitration round when no conversion request have been found pending any more The arbiter is started again if at least one enabled request source indicates a pending conversion request The trigger of a conversion request does need not to be synchronous to the arbiter timing User s Manual 21 40 V1 0 2010 02 ADC V2 1 Cinfineon Analog to Digital Converter 21 7 2 Request Source Priority and Conversion Start Mode Each request source has a configurable priority so the arbiter can resolve concurrent conversion requests from different sources The request with the highest priority is selected for conversion These priorities can be adapted to the requirements of a given application see register ADC_PRAR The Conversion Start Mode determines the handling of the conversion request that has won the arbitration The Priority and Arbitration Register defines the request source priority the conversion start mode for each request source and enables disables the ar
316. ata 3 2 1 Memory Protection Strategy 3 4 1 Special Function Registers 3 4 1 Address Extension by Mapping 3 4 1 System Control 0 3 6 1 Address Extension by Paging 3 7 1 Page Register 3 9 1 Bit Addressing ce eee Re dia didt 3 10 1 Bit Protection Scheme 3 11 1 XC82x Register Overview 3 13 1 CPU Reglsters ede rr Bae LR RS Rd 3 13 1 MDW Registers 22 55 2 cee GG Sve wees Dee Rc es 3 14 1 System Control Registers 3 15 1 Port eglsters us sse atri 3 18 1 User s Manual 1 1 V1 0 2010 02 Cinfineon 3 4 5 5 3 4 5 6 3 4 5 7 3 4 5 8 3 4 5 9 3 4 5 10 3 4 5 11 3 4 5 12 4 4 1 4 2 4 3 44 4 5 4 51 4 6 4 7 4 7 1 4 7 1 1 4 7 1 2 4 7 2 4 7 2 1 4 7 2 2 4 7 3 4 7 4 5 5 1 5 2 5 2 1 5 2 2 5 2 3 5 2 4 6 6 1 6 1 1 6 1 2 6 2 6 2 1 6 2 1 1 6 2 1 2 6 2 1 3 ADC Registers 3 19 1 LEDSCU Registers usos eee bee eee eens 3 23 1 RTC Registers 2 nu RR eed eee 3 24 1 Timer 2 Registers e Role ox eor Rn
317. ata into flash OxDFF9 BR FLASH ERASE Erase flash The erase and program user routines can be called from XRAM or Flash Table 22 2 shows the description of how to use and call these routines User s Manual BootROM User Routines V1 1 22 1 V1 0 2010 02 Cinfineon Boot ROM User Routines Table 22 2 Calling Flash User Routines Name Called from Target BR_FLASH_PROGRAM Flash Bank 0 Flash Bank 0 XRAM Flash Bank 0 BR_FLASH_ERASE BR_FLASH_BACKGROUND_PROGRAM XRAM Flash Bank 0 BR_FLASH_BACKGROUND_ERASE BR FLASH BACKGROUND ERASE ABORT 22 1 Flash Bank Read Mode Status Subroutine The Read Mode status subroutine allows the checking of ready to read Mode status of the Flash Bank This routine is especially useful when user uses BR FLASH BACKGROUND ERASE ABORT user routine After calling the erase abort routine user can call this Read Mode Status user routine to check if erase has been successfully aborted and the Flash is in Read Mode already Before calling this subroutine the user must ensure that the input R7 is configured to the selected Flash Bank The carry flag is clear when Flash is in Read Mode otherwise it is set For wrong input the carry flag is set Table 22 3 Specifications of Flash Bank Read Mode Status subroutine Subroutine BR FLASH READ MODE STATUS Input R7 of current Register Bank Selected Flash Bank 00 Flash Bank 0 Others Reserved Invalid options Output C O Se
318. ata valid flags Figure 21 21 Conversion Result Storage Conversion result handling comprises the following functions Storage of conversion results to user configurable registers Wait for read mode to avoid loss of data if several channels share one result register see Section 21 10 Result event interrupts see Section 21 10 1 Data reduction or anti aliasing filtering and Digital low pass fitlering see Section 21 10 2 User s Manual 21 64 V1 0 2010 02 ADC V2 1 Cinfineon Analog to Digital Converter Up to 4 result values can be added in each result register This reduces the frequency of interrupts generated by the ADC Standard application read view RESRxL H 8bit conversion mode with Data Reduction and Digital Low Pass Filter disabled ADC_GLOBCTR DW 1 RCRx DRCTR 0 RCRx DLPF 0 When this mode is chosen the targetted result register in ADC_RESRxL x 0 3 and x 0 3 would be shown as Figure 21 22 In ADC_RESRxL x 0 3 bits 2 0 indicate the channel number whose conversion triggered the result event and in x 0 3 bits 7 0 returns the conversion result Reading the result automatically clears the valid flag This view is useful only without data reduction 10bit conversion mode with Data Reduction and Digital Low Pass Filter disabled ADC_GLOBCTR DW 0 RCRx DRCTR 0 RCRx DLPF 0 When this mode is chosen the targetted result registe
319. atch of T12 110 set T13R upon a zero match of T12 while counting up 111 set T13R on any edge of inputs CCPOSx T13TED 6 5 rw Timer T13 Trigger Event Direction Bit field T13TED delivers additional information to control the automatic set of bit T13R in the case that the trigger action defined by T13TEC is detected 00 reserved no action 01 while T12 is counting up 10 while T12 is counting down 11 independent on the count direction of T12 0 7 r reserved returns 0 if read should be written with 0 1 Example If the timer T13 is intended to start at any compare event on T12 T13TEC 100 the trigger event direction can be programmed to counting up gt gt a T12 channel 0 1 2 compare match triggers T13R only while T12 is counting up counting down gt gt a T12 channel 0 1 2 compare match triggers T13R only while T12 is counting down independent from bit CDIR gt gt each T12 channel 0 1 2 compare match triggers T13R The timer count direction is taken from the value of bit CDIR As a result if T12 is running in edge aligned mode counting up only T13 can only be started automatically if bit field T13TED 01 or 11 User s Manual 20 62 V1 0 2010 02 CCU6 V4 0 Cinfineon Capture Compare Unit 6 CCU6 TCTR2H Timer Control Register 2 High Reset Value 00 RMAP 0 PAGE 2 7 6 5 4 3 2 1 0 0 T13RSEL T12RSEL r rw rw Field Bits Type Description
320. aud Mbit 1 000 000 characters bits per second Kbyte 1024 bytes of memory Mbyte 1 048 576 bytes of memory In general the k prefix scales a unit by 1000 whereas the K prefix scales a unit by 1024 Hence the Kbyte unit scales the expression preceding it by 1024 The kBaud unit scales the expression preceding it by 1000 The M prefix scales by 1 000 000 or 1048576 and scales by 0 000001 For example 1 Kbyte is 1024 bytes 1 Mbyte is 1024 x 1024 bytes 1 kBaud kbit are 1000 characters bits per second 1 MBaud Mbit are 1 000 000 characters bits per second and 1 MHz is 1 000 000 Hz Data format quantities are defined as follows Byte 8 bit quantity User s Manual 1 13 V1 0 2010 02 System Architecture V1 0 Cinfineon Introduction 1 6 Reserved Undefined and Unimplemented Terminology In tables where register bit fields are defined the following conventions are used to indicate undefined and unimplemented function Further types of bits and bit fields are defined using the abbreviations shown in Table 1 2 Table 1 2 Bit Function Terminology Function of Bits Description Unimplemented Register bit fields named 0 indicate unimplemented functions with the following behavior Reading these bit fields returns 0 Writing to these bit fields has no effect These bit fields are reserved When writing software should always set such bit fields to 0 in order to preserve compatibility with futur
321. been detected User s Manual ADC V2 1 21 31 V1 0 2010 02 Cinfineon XC82x Analog to Digital Converter Field Bits Type Description EMPTY 5 rh Queue Empty This bit indicates if the sequential source contains valid entries A new entry is ignored if the queue is filled EMPTY 0 Os The queue is filled with FILL 1 valid entries in the queue 1g queue is empty no valid entries present in the queue 0 3 2 r Reserved 7 6 Returns 0 if read should be written with 0 User s Manual ADC V2 1 21 32 V1 0 2010 02 Cinfineon Analog to Digital Converter The Queue Input Register is the entry point for conversion requests of a queued request source ADC_QINRO Queue Input Register 0 D2 Reset Value 00 RMAP 0 PAGE 6 7 6 5 4 3 2 1 0 EXTR ENSI RF 0 REQCHNR w w w Field Bits Type Description REQCHNR 2 0 w Request Channel Number This bit field defines the requested channel number Note Bit 2is only applicable for devices that have 8 ADC channels For channels not implemented these bits should be treated as Reserved bits of type r which returns 0 if read and should be written with RF 5 w Refill This bit defines the refill functionality ENSI 6 w Enable Source Interrupt This bit defines the source interrupt functionality EXTR 7 w External Trigger This bit defines the external trigger
322. been read So a conversion or a conversion sequence can be requested by a hardware or software trigger while each conversion is only started after the previous one has been read This automatically aligns the conversion sequence with the CPU capability to read the formerly converted result interrupt latency If wait for read mode is enabled for a result register bit WFR 1 in the corresponding result control register a request source does not generate a conversion request while the targeted result register contains valid data indicated by the valid flag VFx 1 or if a currently running conversion targets the same result register 1 Repeated conversions of a single channel that use a sepearate result register will not destroy other results but rather update their own previous result value This way always the actual signal data is available in the result register User s Manual 21 79 V1 0 2010 02 ADC V2 1 Cinfineon Analog to Digital Converter If two request sources target the same result register with wait for read mode selected a higher priority source cannot interrupt a lower priority conversion request started before the higher priority source has requested its conversion Cancel inject repeat mode does not work in this case If the higher priority request targets a different result register the lower priority conversion can be cancelled and repeated afterwards 21 10 1 Result Events and Interrupts A result event i
323. bit timer counter 2 8 bit timer counter with auto reload The timer register TLx is reloaded with a user defined 8 bit value in THx upon overflow 3 Timer 0 operates as two 8 bit timers counters The timer registers TLO and THO operate as two separate 8 bit counters Timer 1 is halted and retains its count even if enabled User s Manual 13 4 V1 0 2010 02 Timer 0 and 1 V1 0 Cinfineon 0 1 13 4 1 0 Putting either Timer 0 or Timer 1 into mode 0 configures it as an 8 bit timer counter with a divide by 32 prescaler Figure 13 1 shows the mode 0 operation In this mode the timer register is configured as a 13 bit register As the count rolls over from all 15 to all Os it sets the timer overflow flag TFx The overflow flag TFx can then be used to request an interrupt The counted input is enabled for the timer when TRx 1 and either GATEx 0 or EXINTx 1 setting GATEx 1 allows the timer to be controlled by external input EXINTx to facilitate pulse width measurements TRx is a control bit in the register TCON bit GATEx is in register TMOD The 13 bit register consists of all the 8 bits of THx and the lower 5 bits of TLx The upper 3 bits of TLx are indeterminate and should be ignored Setting the run flag TRx does not clear the registers Mode 0 operation is the same for Timer 0 and Timer 1 y T0870 gt on a Ree TO l 5Bits
324. bit timer value 01 THx holds the higher 8 bit part of the 16 bit timer value 10 THx holds the 8 bit reload value 11 THO holds the 8 bit timer value TH1 is not used TCON Timer 0 1 Control Registers 88 Reset Value 00 RMAP X PAGE X 7 6 5 4 3 2 1 0 TF1 TR1 TFO TRO IE1 IT1 IEO ITO rwh rw rwh rw rwh w rwh rw User s Manual 13 10 V1 0 2010 02 Timer 0 and 1 V1 0 Cinfineon XC82x Timer 0 and Timer 1 Field Bits Type Description TRO 4 Timer 0 Run Control Og Timeris halted 1g runs TFO 5 rwh Timer 0 Overflow Flag Set by hardware when Timer 0 overflows Cleared by hardware when the processor calls the interrupt service routine TR1 6 Timer 1 Run Control Og Timeris halted 1g runs Note Timer 1 Run Control affects THO also if Timer 0 operates in Mode 3 TF1 7 rwh Timer 1 Overflow Flag Set by hardware when Timer 1 overflows Cleared by hardware when the processor calls the interrupt service routine 1 TF1 is set by THO instead if Timer 0 operates in Mode 3 TMOD Timer Mode Register 89 Reset Value 00 RMAP X PAGE X 7 6 4 3 2 1 0 GATE1 T1S T1M GATEO TOS TOM User s Manual 13 11 V1 0 2010 02 Timer 0 and 1 V1 0 Cinfineon XC82x Timer 0 and Timer 1 Field Bits Type Description TOM 1 0 rw Mode Select Bits 00 13 bit timer M8048 compatible mode 01 16 bit timer 10g
325. bitrary result registers User s Manual 21 80 V1 0 2010 02 ADC V2 1 Cinfineon Analog to Digital Converter The digital low pass filter pre processes the result values by averaging the previous and current results to remove any transient noise voltages that is measured Standard Data Reduction Mode The data reduction mode can be used as digital filter for anti aliasing or decimation purposes It accumulates a maximum of 2 conversion results to generate a final result Each result register can be individually enabled for data reduction controlled by bitfield DRCTR in registers ADC_RCRx x 0 3 The data reduction counter DRC indicates the actual status of the accumulation Note Conversions for other result registers can be inserted between conversions to be accumulated Lf ff running conversion delivered result DRC 0 mt 4 6 M8 r2 3 r4 5 6 7 content of result register x valid flag for result register x VF a o bl f DRCTR 1 Figure 21 28 Standard Data Reduction Filter This example shows a data reduction sequence of 2 accumulated conversion results Eight conversion results rO r7 are accumulated and produce 4 final results When a conversion is complete and stores data to a result register that has data reduction mode enabled the data handling is controlled by the data reduction count
326. bitration slots to control whether or not conversion requests are considered Note Only change priority and conversion start mode settings of a request source while this request source is disabled and a currently running conversion requested by this source is finished ADC_PRAR Priority and Arbitration Register CC Reset Value 00 RMAP 0 PAGE 0 7 6 5 4 3 2 1 0 ASEN1 ASENO 0 ARBM CSM1 PRIO1 CSMO PRIOO rw rw r rw rw rw rw rw Field Bits Type Description PRIOO 0 rw Priority of Request Source 0 This bit defines the priority of the sequential request source 0 Og Low priority 1g High priority CSMO 1 rw Conversion Start Mode of Request Source 0 This bit defines the conversion start mode of the sequential request source 0 Oz wait for start mode is selected 1g cancel inject repeat mode is selected PRIO1 2 rw Priority of Request Source 1 This bit defines the priority of the parallel request source 1 Og Low priority 1g High priority User s Manual 21 41 V1 0 2010 02 ADC V2 1 Cinfineon XC82x Analog to Digital Converter Field Bits Type Description CSM1 Conversion Start Mode of Request Source 1 This bit defines the conversion start mode of the parallel request source 1 0s wait for start mode is selected 1g mode is selected ARBM Arbitration Mode This b
327. by the value of MCMPS When read this bit always delivers 0 Og No action 1g field MCMP is updated 0 6 r reserved returns 0 if read should be written with 0 MCMOUTSH Multi Channel Mode Output Shadow Register High Reset Value 00 RMAP 0 PAGE 0 7 6 5 4 3 2 1 0 STRHP 0 CURHS EXPHS rw r rw rw User s Manual 20 106 V1 0 2010 02 CCUG V4 0 Cinfineon XC82x Capture Compare Unit 6 CCU6 Field Bits Type Description EXPHS 2 0 rw Expected Hall Pattern Shadow Bit field EXPHS is the shadow bit field for bit field EXPH The shadow transfer takes place when a correct Hall event is detected CM_CHE CURHS 5 3 rw Current Hall Pattern Shadow Bit field CURHS is the shadow bit field for bit field CURH The shadow transfer takes place when a correct Hall event is detected CM CHE STRHP 7 w Shadow Transfer Request for the Hall Pattern Writing STRHP 1 leads to an immediate activation of HP_ST to update bit fields EXPH and CURH by EXPHS and CURHS When read this bit always delivers 0 0s No action 1g fields EXPH CURH are updated 0 6 r reserved returns 0 if read should be written with 0 MCMOUTL Multi Channel Mode Output Register Low 9A Reset Value 00 RMAP 0 PAGE 3 7 6 5 4 3 2 1 0 0 R MCMP r rh rw User s Manual 20 107 V1 0 2010 02 CCUG V4 0 Cinfineon XC82x Capture C
328. by enabling each LED column one at a time As only one time slice per time frame is used for touch sense function depending on the number of touchpad sense inputs pad turns configured by default the hardware automatically enables each pad oscillator pad turn x and sense the respective pins in round robin fashion Otherwise it is possible to enable for software control where the active pad turn is fully under user control If touch sense function is disabled no pad turn is active in the last time slice of time frame A time frame comprises of several time slices whose duration and number is configurable When touch sense function is enabled for automatic hardware pad turn control several time frames make up one time period where all pad turns are completed The time slice duration is configured centrally for the LED and or touch sense functions using the LEDTS counter Refer to the description in Section 19 4 Section 19 8 and Figure 19 2 If enabled a time slice interrupt is triggered on overflow of LEDTS counter 8LSB for each new time slice started A time frame interrupt may also be enabled which is triggered on overflow of the whole LEDTS counter User s Manual 19 5 V1 0 2010 02 LEDTSCU V 1 2 1 Cinfineon LED and Touch Sense Controller To allow flexible duration of activation of LED columns and or touch sense oscillation counting the duty cycle of column enable and pad oscillation enable can be adjusted for each tim
329. cations of FLASH BACKGROUND ERASE subroutine Subroutine BR_FLASH_BACKGROUND_ERASE Input R7 of Current Register Bank Select sector s to be erased for the Flash Bank 0 LSB represents sector 0 MSB represents sector 7 R6 of Current Register Bank Select sector s to be erased for the Flash Bank 0 LSB represents sector 8 and bit 1 represents sector 9 SFR NMISR 00 Flash NMI NMICON NMIFLASH is enabled 1 or disabled 0 Output PSW CY 0 Flash erasing is in progress 1 Flash erasing is not successful 1 Invalid No input s is given Stack size required 8 Resource DPTR A used destroyed R2 of current Register Bank 1 bytes 1 The inputs should be set as 0 if the sector s of the bank is are not to be selected for erasing 22 8 Abort Flash Erase Subroutine Each complete erase operation on a Flash bank requires approximately 100 ms during which read and program operations on the Flash bank cannot be performed For the XC82x provision has been made to allow an on going erase operation type 2 BR_FLASH_BACKGROUND_ERASE to be interrupted so that higher priority tasks such as reading programming of critical data from to the Flash bank can be performed Hence erase operations on selected Flash bank sector s may be aborted to allow data in other sectors to be read or programmed To minimize the effect of aborted erase on the Flash data retention cycling and to guarantee data reliabil
330. cessary initialization of the SSC the serial interfaces can be enabled For a master device the alternate clock line will now go to its programmed polarity The alternate data line will go to either 0 or 1 until the first transfer starts After a transfer the alternate data line will always remain at the logic level of the last transmitted data bit When the serial interfaces are enabled the master device can initiate the first data transfer by writing the transmit data into register TB This value is copied into the shift register assumed to be empty at this time and the selected first bit of the transmit data will be placed onto the TXD line on the next clock from the baud rate generator transmission starts only if CON EN 1 Depending on the selected clock phase clock pulse will also be generated on the MS_CLK line At the same time with the opposite clock edge the master latches and shifts in the data detected at its input line RXD This exchanges the transmit data with the receive data Because the clock line is connected to all slaves their shift registers will be shifted synchronously with the master s shift register shifting out the data contained in the registers and shifting in the data detected at the input line After the preprogrammed number of clock pulses via the data width selection the data transmitted by the master is contained in all the slaves shift registers while the master s shift register holds
331. ck remains in operation during certain power down modes with a power supply of 2 5V 5 5 V 15 4 Basic Timer Operation The real time clock consists of a 41 bit timer which count up It contains a set of 4 to 6 count registers collectively know at CNT register that shows the current count value or the current time of the real time clock Before starting the real time clock CNT register can be written with any value The value written is used as an initial value for the real time clock when it is started Another set of registers RTCCR register that consists of 4 to 6 registers can be used for interrupt generation It can also be used to wake up device from power down mode The RTCCR register is also used to store the capture value when a capture event is triggered The real time clock is started by setting bit RTCC in the RTCON register to 1 This enables the input clock into the real time clock timer 15 5 Real Time Clock Modes In XC82x the real time clock operates in two modes Mode 1 is the periodic wake up mode that uses a 41 bit counter In this mode an internal oscillator of 75 KHz is used as User s Manual 15 2 V1 0 2010 02 RTC V1 0 Cinfineon Real Time Clock the clock input Mode 3 which has similiar functions as Mode 1 uses an external clock input to a 32 bit counter In XC82x Mode 1 is selected by default upon power up User need to ensure that the switching of mode is performed when the Real time clock is in stop
332. ck can generate a wake up request to the XC82x during power down mode provided all the following conditions are fulfilled e XC82xis in power down mode 2 bit PDMODE 1 in PMCONO register The power down mode is enabled bit PD 1 in PMCONO register The type of wake up mode is selected bit WKSEL in PMCONO register Operating power supply levels including reduced voltage conditions are maintained A capture event could be triggered by setting RTCCT bit in RTCON register to 1 The previous content in the RTCCR register will be overwritten with the captured CNT values after 2 CPU clock cycles An update of the actual compared value is necessary once a captured event is triggered In XC82x it is recommended to trigger a capture event to read the value of the RTC counter CNT There is a potential of reading a wrong 32 bits real time value while the RTC is in running mode as only 8 bit of data could be fetch at one time The real time clock stops counting and CNT register holds the last value when the RTCC bit is set to 0 Setting this bit subsequently will start a new counting sequence which begin with the stop count Note A compare match event could happen concurrently with the capture event when both events happen within the same clock cycle 15 5 2 Mode 3 Timer Mode with External Clock Figure 15 2 shows Mode 3 of the real time clock In this mode the real time clock consists of a 32 bit general purposes timer It has th
333. cknowledge from core Event interrupt request pending clear interrupt IL gt request 4 FF Event AND set clear occurrence interrupt node Corresponding enable bit rr AND Implemented as latch cannot set by software p Figure 9 8 Interrupt Structure 2 An event generated by its corresponding interrupt source will set the status flag and in parallel if the event is enabled for interrupt activate the pending interrupt request Consider the case where interrupt event occurred while its interrupt node was disabled assume global interrupt enable EA is set When the interrupt node is enabled later previously activated pending interrupt request will now cause an active interrupt request to the core Note for the special case of NMI node that it is essentially non maskable An active pending interrupt request interrupts the core and is automatically cleared by hardware the core once the interrupt node is serviced interrupt acknowledged the status flag remains set and must be cleared by software A pending interrupt request can also be cleared by software only on clearing all interrupt enabled status flags of the node will indirectly clear its pending interrupt request Note that this is not exactly like interrupt structure 1 where the pending interrupt request is cleared directly by resetting the node s interrupt status flags In summary the following lists in descending order the
334. code to XRAM Execute customer code in XRAM Program customer code to FLASH Execute customer code in FLASH Erase customer code in FLASH sector s Program 4 bytes of USER ID Get 4 bytes Information Except Mode 1 Mode 3 and Mode 6 the uC would return to the beginning of Phase II and wait for the next command from the host after executing all other Modes The serial communication which is activated in Phase ll is based a byte received in Phase after baud rate 0x0055 to select single pin OxAA or dual pins 0x55 UART of XC82x UART auto baud routine uses the LIN baud rate detection to calculate the baud rate The port settings for BSL Mode are listed in Table 6 1 Table 6 1 Port Settings for UART BSL Mode Device UART INIT ID Single Dual Pin s Pin s used XC82x OxAA Single pin P 0 6 as RXD P 0 6 as TXD XC82x 0x55 Dual pins P 0 6 as RXD P 0 5 as TXD The serial transfer is working in asynchronous mode with the serial parameters 8N1 eight data bits no parity and one stop bit The host can vary the baud rate in a wide range because the uC does an automatic synchronization with the host in Phase User s Manual 6 1 V1 0 2010 02 Cinfineon Boot Loader 6 1 Phase 1 Automatic Serial Synchronization to the Host Upon entering UART BSL Mode a serial connection is established and the transfer speed baud rate of the serial communication partner host is automatically synchronized
335. contents read via CPU access In the program mode data in the 32 byte write buffers is programmed into the Flash memory cells of the targeted wordline The operating modes for each Flash bank are enforced by its dedicated state machine to ensure the correct sequence of Flash mode transition This avoids inadvertent destruction of the Flash contents with a reasonably low software overhead The state machine also ensures that a Flash bank is blocked no read access possible while it is being programmed or erased At any time a Flash bank can only be in ready to read program or sector s erase mode However it is possible to program erase one Flash bank while reading from another When the user sets bit PMCONO PD 1 to enter the system power down mode the Flash banks are automatically brought to its power down state by hardware Upon wake up from system power down the Flash banks are brought to ready to read mode to allow access by the CPU User s Manual 4 8 V1 0 2010 02 Flash Memory V 0 1 Cinfineon nears Flash Memory 4 5 Error Detection and Correction The 8 bit data from the CPU is encoded with an Error Correction Code ECC before being stored in the Flash memory During a read access data is retrieved from the Flash memory and decoded for dynamic error detection and correction The correction algorithm hamming code has the capability to Detect and correct all 1 bit errors Detect all 2 bit errors but cannot correc
336. conversion start User s Manual ADC V2 1 21 34 V1 0 2010 02 Cinfineon XC82x Analog to Digital Converter Field Bits Type Description ENSI rh Enable Source Interrupt This bit indicates if a source interrupt will be generated when the conversion is completed The interrupt trigger becomes activated if the conversion requested by the source has been completed and ENSI 1 Og The source interrupt generation is disabled 1g source interrupt generation is enabled EXTR rh External Trigger This bit defines if the conversion request is sensitive to an external trigger event The event flag bit EV indicates if an external event has taken place and a conversion can be requested Og Bit EV is not used to start conversion request 1g Bit EV is used to start conversion request Reserved Returns 0 if read should be written with 0 User s Manual ADC V2 1 21 35 V1 0 2010 02 Cinfineon Analog to Digital Converter The Queue Backup Registers monitor the status of an aborted queued request ADC_QBURO Queue Backup Register 0 02 Reset Value 00 RMAP 0 PAGE 6 7 6 5 4 3 2 1 0 EXTR ENSI RF 0 REQCHNR rh rh rh rh r rh Field Bits Type Description REQCHNR 2 0 rh Request Channel Number This bit field is updated by bit field QORO REQCHNR when the conversion requested by QORO is started Note Bit 2 is only applic
337. core 1 Pending interrupt requests are not blocked from the core 0 6 r Reserved Returns 0 if read should be written with 0 IEN1 Interrupt Enable Register 1 E8 Reset Value 00 RMAP X PAGE X 7 6 5 4 3 2 1 0 ECCIP3 ECCIP2 ECCIP1 ECCIPO EXM EFTO ESSC EADC rw rw rw rw rw rw rw rw Field Bits Type Description EADC 0 rw Interrupt Node XINTR6 Enable 0 XINTR6 is disabled 1 XINTR6 is enabled ESSC 1 rw Interrupt Node XINTR7 Enable 0 XINTR7 is disabled 1 XINTR7 is enabled EFTO 2 rw Interrupt Node XINTR8 Enable 0 XINTR8 is disabled 1 XINTR8 is enabled EXM 3 rw Interrupt Node XINTR9 Enable 0 XINTRO is disabled 1 is enabled ECCIPO 4 rw Interrupt Node XINTR10 Enable 0 XINTR10 is disabled 1 XINTR10 is enabled ECCIP1 5 rw Interrupt Node XINTR11 Enable 0 XINTR11 is disabled 1 XINTR11 is enabled User s Manual Interrupt System V 2 3 3 9 18 V1 0 2010 02 Cinfineon XBox Interrupt System Field Bits Type Description ECCIP2 6 rw Interrupt Node XINTR12 Enable 0 XINTR12 is disabled 1 XINTR12 is enabled ECCIP3 7 rw Interrupt Node XINTR13 Enable 0 XINTR13 is disabled 1 XINTR13 is enabled The bit field PAGE of SCU_PAGE register must be programmed before accessing the NMICON register NMICON NMI Control Register EE Reset Value 00 RMAP 0 PAGE 0 7 6 5 4 3 2 1 0 NMI NMI 0 NMIECC NMIVDDP NMIVDDC NMIOCDS FLASH OSCCLK NMIWDT r rw rw
338. counter counts up while CDIR 0 and it counts down while CDIR 1 User s Manual 20 22 V1 0 2010 02 CCU6 V4 0 Cinfineon Capture Compare Unit 6 CCU6 lt Period Value gt 1 Period i i Value Zero Period Period T12 Count uH Match Match Zero Down Up Up Down CDIR CC6x Valuen X Value n 1 Value n 1 2 Shadow Transfer Shadow Transfer CCU6_MCT05510 Figure 20 6 T12 Operation in Center Aligned Mode Note Bit CDIR changes with the next timer clock event after the one match or the period match Therefore the timer continues counting in the previous direction for one cycle before actually changing its direction see Figure 20 6 User s Manual 20 23 V1 0 2010 02 CCU6 V4 0 Cinfineon Capture Compare Unit 6 CCU6 20 3 2 3 Single Shot Mode In Single Shot Mode the timer run bit T12R is cleared by hardware If bit T12SSC 1 the timer T12 will stop when the current timer period is finished In Edge Aligned mode T12R is cleared when the timer becomes zero after having reached the period value see Figure 20 7 Period Value T12 Count Compare Value 0 T12R CC6xST IIIT cous meross11 Figure 20 7 Single Shot Operation in Edge Aligned Mode In Center Aligned mode the period is finished when the timer has counted down to zero one clock cycle after the one match while counting down see Figure 20 8 Peri
339. ct the 8 type of sources to trigger CTRAP 00 One of the input pin for CTRAP 0 CTRAP 1 CTRAP 2 CTRAP 3 is selected Bit CTRAPIS bit in MODPISEL3 register are used for the indicidual selection 01g P1 overcurrent detection output is selected 10 Any input source from above option 00 or 01 is selected to trigger a CTRAP 11g ADC channel event is selected 1 Applicable for XC83x only Unused for XC82x PISELOH Port Input Select Register 0 High Reset Value 00 RMAP 0 PAGE 3 7 6 5 4 3 2 1 0 IST12HR ISPOS2 ISPOS1 ISPOSO rw rw rw rw Field Bits Type Description ISPOSO 1 0 rw Input Select for CCPOSO This bit field defines the input signal used as CCPOSO input 00 Input pin for CCPOSO 0 01 Input pin for CCPOSO 1 10g Input pin for CCPOSO 2 116 ADC channel 0 boundary limit check event User s Manual 20 128 V1 0 2010 02 CCUG V4 0 Cinfineon XC82x Capture Compare Unit 6 CCU6 Field Bits Type Description ISPOS1 3 2 Input Select for CCPOS1 This bit field defines the input signal used as CCPOS1 input 00 Input pin for CCPOS1_0 01 Input pin for CCPOS1 1 10 Unused 11 ADC channel 1 boundary limit check event ISPOS2 5 4 Input Select for CCPOS2 This bit field defines the the port pin that is used for the CCPOS2 input signal 005 Input pin for CCPOS2 0 01 Input pin for CCPOS2 1
340. d User s Manual 7 7 V1 0 2010 02 Cinfineon XC82x System Control Unit The brownout will cause the device to be reset In power down mode the Vpp is monitored by the POR in EVR and a reset is generated when drops below 1 5 V Once the brownout reset takes place the reset sequence is the same as the power on reset sequence 7 2 2 Module Reset Behavior Table 7 1 lists the functions of the XC82x and the various reset types that affect these functions The symbol I signifies that the particular function is reset to its default state Table 7 1 Effect of Reset on Modules Functions Module Power On Brown Out Wake up Soft Watchdog Function Reset Reset Reset Reset Reset Core BH SCU Bl except except except indication bits indication bits indication bits Peripherals Debug E E E System Port a a Control FW Startup Executesall Executes all Executes Executes all Executes all Execution INIT INIT INIT INIT INIT On Chip Affected Affected Not affected Not affected Not affected Static RAM unreliable unreliable reliable reliable reliable Flash g L Clock L El System User s Manual 7 8 V1 0 2010 02 Cinfineon System Control Unit 7 2 3 Reset Control Register Description RSTCON register consist of the indication bits of a wake up
341. d When Time Slice and Time Frame interrupts are enabled Time Slice Interrupt TimeSliceFlag LED Column Data for Called every time slice display COMPARE SET LDLINE regardless of touch sense value for brightness or or LED column slice oscillation window Interrupt TimeFrameFlag Calculate Average Called every time Frame LowTrip which pad FINDTOUCHEDPAD esp for touch sense touched Y 2 When LED TS are enabled When only Time Slice interrupt is enabled Time Slice Interrupt TimeSliceF lag v Calculate Average aK If FNCOL is 0x07 LowTrip which pad p FINDTOUCHEDPAD 5 i 5 touched routine will be exited LED Column Data for v display COMPARE SET LDLINE CMP value for brightness or oscillation window Y C RETI 2 Figure 23 13 Calling of Functions in Interrupt Routine ii User s Manual 23 38 V1 0 2010 02 ROM Library V0 5 Cinfineon ROM Library 23 3 MDU ROM Library MATH Function The MDU ROM Library MATH Function contains 4 routines that reside in ROM that are accessible to users The call functions for MDU ROM Library is listed in Table 23 14 Table 23 14 MDU ROM Library MATH Function Routine Table Address Name Description OxDFCO C IMUL XC 16 bit Multip
342. d Assignment Table 18 2 lists the interrupt event sources from the SSC and the interrupt node assignment for each SSC interrupt source Note All SSC interrupt enable bits and flags are located at the node level Table 18 2 SSC Events Interrupt Node Control Event Interrupt Node Interrupt Node Flag Vector Enable Bit Bit Address Start of Transmission MODIEN TIREN IRCON1 TIR 3BH IEN1 ESSC End of Transmission MODIEN RIREN IRCON1 RIR 3BH IEN1 ESSC Occurrence of Error MODIEN EIREN IRCON1 EIR 3BH IEN1 ESSC The three interrupt events of SSC module are of interrupt structure 2 and register MODIEN is used to enable the interrupt The bit field PAGE of register SCU_PAGE must be programmed before accessing the MODIEN register MODIEN Peripheral Interrupt Enable Register Reset Value 07 RMAP 0 PAGE 3 7 6 5 4 3 2 1 0 CCU6SR3 CCU6SR2 EN EN 0 RIREN TIREN EIREN rw rw r rw rw rw Field Bits Type Description EIREN 0 rw SSC Error Interrupt Enable 0 Error interrupt is disabled 1 Error interrupt is enabled TIREN 1 rw SSC Transmit Interrupt Enable 0 Transmit interrupt is disabled 1 Transmit interrupt is enabled RIREN 2 rw SSC Receive Interrupt Enable 0 Receive interrupt is disabled 1 Receive interrupt is enabled User s Manual 18 7 V1 0 2010 02 SSC V1 4 Cinfineon High Speed Synchronous Serial Interface Field Bits Type Description
343. d Program Memory IP address the break is set just at one instruction from the user software code is fetched from a defined Program Memory IP address range the break is set over a number of consecutive instructions from the user software Read or Write selectable is performed at a defined Internal RAM address the break is caused by moving data from to a memory location For setting of breakpoint on instruction address HWBPx defines the 16 bit address For setting of breakpoint on IRAM address HWBP2 3L and HWBP2 3H define the 8 bit IRAM address range The configurations supported are Breakpoint 0 Breakpoint 1 Two equal breakpoints on Instruction Address HWBPO and Instruction Address HWBP1 or One range breakpoint on HWBPO lt Instruction Address lt HWBP1 Breakpoint 2 One equal breakpoint on Instruction Address HWBP2 or range breakpoint on HWBP2L lt IRAM Read Address lt HWBP2H Breakpoint 3 One equal breakpoint on Instruction Address HWBP3 or One range breakpoint on HWBP3L lt IRAM Write Address lt HWBP3H Setting both values for a range breakpoint to the same address leads to generation of an equal breakpoint User s Manual 10 5 V1 0 2010 02 OCDS V 2 7 1 Cinfineon Debug System Software Breakpoints These are implemented by storing into the code XC800 specific TRAP instruction not 8051 standard while at the same time TRAP_EN bit within the E
344. d Touch Sense Controller 19 7 Function Enabling and Control Hints It is recommended to set up all configuration for the LEDTSCU in all SFRs before write LTS_GLOBCTLO SFR to enable and start LED and or touch sense function s Note SFR bits especially affecting the LEDTS counter configuration for LED touch sense function can only be written when the counter is not running i e CLK_PS 0 Refer to SFR bit description Section 19 11 Enable LED Function Only To enable LED function only set LD_EN clear TS_EN Initialization after reset MOV LTS GLOBCTLO 0b10XXXXXxX set LD EN and start LEDTS counter on prescaled clock CLK PS 0 Re configuration during run time MOV LTS GLOBCTLO 0x00 stop LEDTS counter by clearing prescaler MOV LTS GLOBCTLO 0b10XXXXXxX Enable Touch Sense Function Only To enable touch sense function only clear LD EN set TS EN Initialization after reset MOV LTS GLOBCTLO 0501 set TS EN and start LEDTS counter on prescaled clock PS 0 Re configuration during run time MOV LTS GLOBCTLO 0x00 stop LEDTS counter by clearing prescaler MOV LTS GLOBCTLO 0b01XXXXXX Enable Both LED and Touch Sense Function To enable both functions set LD_EN set TS_EN Initialization after reset MOV LTS GLOBCTLO 0511 set TS EN and start LEDTS counter on prescaled clock PS 0 Re configuration during run time MOV LTS GLOBCTLO 0x00 stop LE
345. d as general purpose output output data is written into register Px_DATAOUT of port x A read operation of Px_DATAOUT returns the register value and not the state of the Px_DATAOUT pins Px_DATAOUT Port x Data Out Register 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 1 rw rw rw rw rw rw rw rw Field Bits Type Description Pn n rw Port x Pin n Data Value 0 7 0 Port x data value 0 1 Port x pin n data value 1 default User s Manual 11 7 V1 0 2010 02 Cinfineon Parallel Ports Port Data In Register If a port pin is used as general purpose input the value at a port pin can be read through the register Px_DATAIN The data register Px_DATAIN always contains a latched value of the assigned port pin even if the port pin is assigned as output Px_DATAIN Port x Data In Register 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 1 PO rh rh rh rh rh rh rh rh Field Bits Type Description Pn n rh Port x Pin n Data Value 0 7 0 Port x data value 0 1 Port x pin n data value 1 Open Drain Control Register Each pin in output mode can be switched to open drain mode If driven with 1 no driver will be activated and the pin output state depends on the internal pull up pull down device setting if driven with 0 the driver s pull down transistor will be activated The open drain mode is controlled by the r
346. d can only be cleared by software 0 Interrupt event has not occurred 1 Interrupt event has occurred 0 1 0 7 r Reserved Returns 0 if read Should be written with O IRCON1 Interrupt Request Register 1 Reset Value 00 RMAP 0 PAGE 0 7 6 5 4 3 2 1 0 0 ADCSR1 ADCSRO RIR TIR EIR r rwh rwh rwh rwh rwh Field Bits Type Description EIR 0 rwh Error Interrupt Flag for SSC This bit is set by hardware and can only be cleared by software 0 Interrupt event has not occurred 1 Interrupt event has occurred User s Manual 9 24 V1 0 2010 02 Interrupt System V 2 3 3 Cinfineon Interrupt System Field Bits Type Description TIR 1 rwh Transmit Interrupt Flag for SSC This bit is set by hardware and can only be cleared by software 0 Interrupt event has not occurred 1 Interrupt event has occurred RIR 2 rwh Receive Interrupt Flag for SSC This bit is set by hardware and can only be cleared by software 0 Interrupt event has not occurred 1 Interrupt event has occurred ADCSRO 3 rwh Interrupt Flag 0 for ADC This bit is set by hardware and can only be cleared by software 0 Interrupt event has not occurred 1 Interrupt event has occurred ADCSR1 4 rwh Interrupt Flag 1 for ADC This bit is set by hardware and can only be cleared by software 0 Interrupt event has not occurred 1 Interrupt event has occurred 0 7 5 r Reserved
347. d event when the direct synchronization mode is selected The update can also be requested by software by writing to bit field MCMPS with the shadow transfer request bit STRMCM 1 The option to trigger an update by SW is possible for all settings of SWSEL By using the direct mode and bit STRMCM 1 the update takes place completely under software control The event selection and synchronization options are summarized in Table 20 13 and Table 20 14 Table 20 13 Multi Channel Mode Switching Event Selection SWSEL Selected Event see register MCMCTR 000 No automatic event detection 001 Correct Hall Event CM_CHE detected at input signals CCPOSx without additional delay 010 T13 Period Match T13_PM 011 T12 One Match while counting down T12_OM and CDIR 1 100 T12 Compare Channel 1 Event while counting up CM_61 and CDIR 0 to support the phase delay function by CC61 for block commutation mode 101 T12 Period Match while counting up T12_PM and CDIR 0 110 111 Reserved no action Table 20 14 Multi Channel Mode Switching Synchronization SWSYN Synchronization Event see register MCMCTR 00 Direct Mode the trigger event directly causes the shadow transfer 01g T13 Zero Match T13 ZM the MCM shadow transfer is synchronized to a T13 PWM User s Manual 20 88 V1 0 2010 02 CCU6 V4 0 Cinfineon Capture Compare Unit 6 CCU6 Table 20 14 Multi Channel Mode Switchi
348. d interrupt vector while Timer 2 A D Converter LIN LEDTSCU and the Capture Compare Unit share six interrupt vectors In addition four interrupt vectors are assigned to the external interrupts MDU RTC and IIC External interrupts 0 to 1 are each assigned one dedicated interrupt vector External interrupt 2 is shared with MDU and IIC RTC and External interrupt 6 3 share the same interrupt vector A non maskable interrupt NMI with the highest priority is shared by the following Watchdog Timer warning before overflow 48 MHz and 75 KHz Oscillators loss of oscillator clock Flash Timer on operation complete e g erase OCDS on user IRAM event Flash ECC error Vbpp prewarning prewarning Figure 9 1 Figure 9 2 Figure 9 3 Figure 9 4 and Figure 9 5 give a general overview of the interrupt sources and nodes and their corresponding control and status flags Figure 9 6 gives the corresponding overview for the NMI sources User s Manual 9 1 V1 0 2010 02 Interrupt System V 2 3 3 Cinfineon Interrupt System Timer 0 Overflow sj 5 1 Overflow TEI TCON 7 P o l i UART n Receive RI
349. d the stop bit is encoded as a bit with value one recessive User s Manual 16 13 V1 0 2010 02 UART V 1 6 Cinfineon UART Byte field i wet bh bh b Lh Jem Figure 16 5 The Structure of Byte Field The break is used to signal the beginning of a new frame It is the only field that does not comply with Figure 16 5 A break is always generated by the master task in the master mode and it must be at least 13 bits of dominant value including the start bit followed by a break delimiter as shown in Figure 16 6 The break delimiter will be at least one nominal bit time long A slave node will use a break detection threshold of 11 nominal bit times Break delimit Figure 16 6 The Break Field Synch Byte is a specific pattern for determination of time base The byte field is with the data value 55 as shown in Figure 16 7 A slave task is always able to detect the Break Synch sequence even if it expects a byte field assuming the byte fields are separated from each other If this happens detection of the Break Synch sequence will abort the transfer in progress and processing of the new frame will commence Figure 16 7 The Synch Byte Field User s Manual 16 14 V1 0 2010 02 UART V 1 6 Cinfineon UART The slave task will receive and transmit data when an appropriate ID is sent by the master Slave waits for Synch Break Slave synchronizes on
350. d via bit VDDPBOA and VDDPBOPD 7 1 1 Reduced Voltage Condition In the reduced voltage conditon of 2 5 V lt Vbpp lt 3 0 V the active current must be below a sets of values based on the EVR driving capability These limits can be found in the Data Sheet The active current consumption needs to be below the specified values as according to the Vppp voltage If the conditions are not met a brownout reset may be triggered A guideline of the current consumption for some of the modules is also available in the datasheet Note The full operation of XC82x is specified for 3 V lt Vppp lt 5 5 V User s Manual 7 3 V1 0 2010 02 Cinfineon System Control Unit 7 1 2 EVR Register Description The SDCON is used to enable or disable the various detectors The status of Vppp and Vppc threshold levels are also indicated in this register The bit field PAGE of SCU PAGE register must be programmed before accessing these registers SDCON Supply Detection Control Register Reset Value 34 RMAP 0 PAGE 1 7 6 5 4 3 2 1 0 0 VDDPTH VDDCTH 5 VDDPBOA VDDPPW VDDCPW rh rh rw rw rw rw Field Bits Description VDDCPW 0 rw Vppc Prewarning Detection Enable 0 Vppc prewarning detection is disabled 1 Vppc prewarning detection is enabled Note VDDC prewarning flag and NMI will only be triggered when this bit is set to 1 VDDPPW 1 rw Vppp Prewarning Detection Enable 0 Vopp prewar
351. de is used to reduce power consumption by stopping the core s clock In idle mode the oscillator continues to run but the core is stopped with its clock disabled Peripherals whose input clocks are not disabled are still functional The user should disable the Watchdog Timer WDT before the system enters the idle mode otherwise it will generate an internal reset when an overflow occurs and thus will disrupt the idle mode The CPU status is preserved in its entirety the stack pointer program counter program status word accumulator and all other registers maintain their data during idle mode The port pins hold the logical state they had at the time the idle mode was activated Software requests idle mode by setting the bit PCON IDLE to 1 The idle mode can be terminated and the system will returned to active mode by activating any enabled interrupt The CPU operation is resumed and the interrupt will be serviced Upon RETI instruction the core will return to execute the next instruction after the instruction that sets the IDLE bit to 1 7 4 1 2 Power Down Mode In order to achieve different levels of power saving the XC82x has two types of power down modes Power Down mode 1 and 2 Generally the 48 MHz oscillator and the Flash memory are put into power down state in all the modes In addition the main voltage regulator is switched off with only low power voltage regulator still operating in these power down modes Therefore most of
352. decrement the PDC check if PDC 0 check if Total TSCTRL H LowTripL H point for this pad turn On Exit depending on the results of the checks set relevant pad error flag set relevant pad result flag Pad Released On Enter check if PDC gt short count check PDC short count On Exit clear all flags if gt short count clear pad flag if short count Pad Result User s Manual 23 32 V1 0 2010 02 ROM Library V0 5 Cinfineon ROM Library On Enter check if pad result is cleared by the user if not exit On Exit IDLE Pad Error On Enter check if pad error is cleared by the user if not exit On Exit IDLE Pad Down Counter PDC When function detects an initial padtouch it will initialize the PDC value to OxFF Every time function is called as long as pad is still being touched function will decrement PDC value In case of dual pads PDC will only be decrement once during both pads analysis time able to detect that PDC is already decremented before The diagram below shows how the Pad Down Counter PDC works this is a count down software counter Time Slice Frame interrupt is its clock Short count thrshold Counter preset value Too long pad error r Time slices N Figure 23 9 Pad Down Counter PDC User s Manual 23 33 V1 0 2010 02 ROM Library V0 5 Cinfineon ROM Library TSCTRVAL Time slices the ap
353. ded to half the previous register value The valid flag is activated after the addition User s Manual 21 82 V1 0 2010 02 ADC V2 1 Cinfineon Analog to Digital Converter 21 11 Interrupt Request Handling Interrupts can be generated by several types of events Each ADC kernel provides 2 service request output signals ADCx_SR 1 0 connected to interrupt nodes Four types of events can generate interrupt requests Request source events indicate that a request source completed the requested conversion sequence For a scan source the event is generated when the complete defined set of channels has been arbitrated For a sequential source the user can define where inside a conversion sequence a request source event is generated Request source events indicate that a conversion sequence has reached a defined state and software can access the related set of results Channel events indicate that a conversion is finished Optionally channel events can be generated only for conversion result within a programmable value range Channel events preferably indicate analog input values inside or outside a nominal operating range This offloads the CPU load from background tasks i e an interrupt is only required if the specified conversion result range is met or exceeded Result events indicate a new valid result in a result register Usually this triggers a read action by the CPU Optionally result events can be generated only at a
354. e HUS eq 49019 V1 0 2010 02 16 5 Figure 16 1 Serial Interface Mode 1 Timing Diagram User s Manual UART V 1 6 Cinfineon UART 16 3 3 Mode 2 9 Bit UART Fixed Baud Rate In mode 2 the UART behaves as a 9 bit serial port A start bit 0 8 data bits plus a programmable 9th bit and a stop bit 1 are transmitted on TXD or received on RXD The 9th bit for transmission is taken from TB8 SCON 3 while for reception the 9th bit received is placed in RB8 SCON 2 The transmission cycle is activated by a write to SBUF The data is transferred to the transmit register and TB8 is copied into the 9th bit position At phase 1 of the machine cycle following the next rollover in the divide by 16 counter the start bit is copied to TXD and data is activated one bit time later One bit time after the data is activated the data starts shifting right For the first shift a stop bit 1 is shifted in from the left and for subsequent shifts zeros are shifted in When the TB8 bit gets to the output position the control block executes one last shift and sets the TI bit Reception is started by a high to low transition on RXD sampled at 16 times the baud rate The divide by 16 counter is then reset and 1111 1111 is written to the receive register If a valid start bit 0 is then detected based on two out of three samples it is shifted into the register followed by 8 data bits If the transition is not followed by
355. e Note Bit 2is only applicable for devices that have 8 ADC channels For channels not implemented these bits should be treated as Reserved bits of type f which returns 0 if read and should be written with DRC rh Data Reduction Counter This bit field indicates how many conversion results have still to be accumulated to generate the final result for data reduction final result is available the result register The valid flag is automatically set when this bit field is set to 0 1g 1 more conversion result must be added to obtain the final result in the result register The valid flag is automatically reset when this bit field is set to 1 VF rh Valid Flag for Result Register x This bit indicates that the contents of the result register x are valid Theresult register x does not contain valid data 1g result register x contains valid data RESULT 2 0 7 5 rh Conversion Result This bit field contains the conversion result or the result of the data reduction filter RESRxH x 0 2 Result Register x High View Std 10 bit CB x 2 Reset Value 00 ADC_RESR3H Result Register 3 High View Std 10 bit D3 Reset Value 00 RMAP 0 PAGE 2 7 6 5 4 3 2 1 0 0 RESULT 9 3 r rh User s Manual 21 70 V1 0 2010 02 ADC V2 1 Cinfineon Analog to Digital Converter Field Bits Type Description
356. e The functions of the Monitor include Communication with an external Debugger via the debug interface Read write access to arbitrary memory locations and Special Function Registers SFRs including the Instruction Pointer and password protected bits Configuring OCDS and setting removing breakpoints e Executing a single instruction step mode Note Details of the Monitor program functionality is not covered in this documentation User s Manual 10 6 V1 0 2010 02 OCDS V 2 7 1 Cinfineon Debug System 10 3 3 Debug Suspend Control Next to the basic debug functionality setting breakpoints and halting the execution of user software OCDS supports also for module suspend during debugging As long as the device is in monitor mode i e while the user software is not running but in break and if debug suspend functionality is generally enabled by on chip software modules or functions can be suspended in this duration This feature could be quite useful especially regarding the Watchdog Timer it prevents unintentional WDT resets during the debug session Usually debug suspend is provided for other timer modules Stopping counters provide for a complete freeze of the device status during a break Generally the debug suspend control bits global enable in OCDS and individual selections in SCU are disabled after reset i e by default no module will be suspended upon a break Normally for debugging the device wi
357. e 00 RMAP X PAGE X 7 6 5 4 3 2 1 0 0 PT2 PS PT1 PX1 PTO PX0 r rw rw rw rw rw rw Field Bits Type Description PX0 0 rw Priority Level Low Bit for Interrupt Node XINTRO PTO 1 rw Priority Level Low Bit for Interrupt Node XINTR1 PX1 2 rw Priority Level Low Bit for Interrupt Node XINTR2 PT1 3 rw Priority Level Low Bit for Interrupt Node XINTR3 PS 4 rw Priority Level Low Bit for Interrupt Node XINTR4 PT2 5 rw Priority Level Low Bit for Interrupt Node XINTR5 0 7 6 r Reserved Returns 0 if read should be written with 0 User s Manual 9 30 V1 0 2010 02 Interrupt System V 2 3 3 Cinfineon Interrupt System IPH Interrupt Priority High Register B9 Reset Value 00 RMAP X PAGE X 7 6 5 4 3 2 1 0 0 PT2H PSH PT1H PX1H PTOH T rw rw rw rw rw rw Field Bits Type Description 0 rw Priority Level High Bit for Interrupt Node XINTRO PTOH 1 rw Priority Level High Bit for Interrupt Node XINTR1 PX1H 2 rw Priority Level High Bit for Interrupt Node XINTR2 PT1H 3 rw Priority Level High Bit for Interrupt Node XINTR3 PSH 4 rw Priority Level High Bit for Interrupt Node XINTR4 PT2H 5 rw Priority Level High Bit for Interrupt Node XINTR5 0 7 6 r Reserved Returns 0 if read should be written with 0 IP1 Interrupt Priority 1 Register F8 Reset Value 04 RMAP X PAGE X 7 6 5 4 3 2 1 0 PCCIP3 PCCIP
358. e At the end of the startup code it is re enabled before the user code start to execute PO ALTSELO Port 0 Alternate Select Register 0 80 RMAP 0 PAGE 2 Reset Value 00 7 6 4 3 2 1 0 0 6 5 P4 P3 P2 1 r rw rw rw rw rw rw rw Field Bits Type Description Pn n rw See Table 11 5 0 6 0 7 r Reserved Returns 0 if read should be written with 0 User s Manual 11 19 V1 0 2010 02 Cinfineon XC82x Parallel Ports PO ALTSEL1 Port 0 Alternate Select Register 1 86 Reset Value 00 RMAP 0 PAGE 2 7 6 5 4 3 2 1 0 0 6 5 P4 P3 P2 1 r rw rw rw rw rw rw rw Field Bits Type Description Pn n rw See Table 11 5 0 6 0 7 r Reserved Returns 0 if read should be written with PO ALTSEL2 Port 0 Alternate Select Register 2 85 Reset Value 00 RMAP 0 PAGE 2 7 6 5 4 3 2 1 0 0 P6 P5 P4 0 r nw nw nw T Field Bits Type Description Pn n rw See Table 11 5 0 6 0 3 0 7 r Reserved Returns 0 if read should be written with 0 Table 11 5 Function of Bits PO_ALTSEL2 Pn PO_ALTSEL1 Pn and PO ALTSELO Pn PO ALTSEL2 Pn PO_ALTSEL1 Pn PO_ALTSELO Pn Function 0 0 0 Normal GPIO default 0 0 1 Alternate Select 1 0 1 0 Alternate Select 2 User s Manual 11 20 V1 0 2010 02 Cinfineon XC82x P
359. e Arbitration on Page 21 38 Analog Input Channel Configuration on Page 21 45 Conversion Result Handling on Page 21 64 Interrupt Request Handling on Page 21 83 Register Mapping on Page 21 89 User s Manual V1 0 2010 02 V2 1 Cinfineon Analog to Digital Converter The following features describe the functionality of an ADC kernel Input voltage range from 0 V up to analog supply voltage Vppp 3 0 V to 5 5 V Three internal reference voltage source selectable for each channel to support ratiometric measurements and different signal scales which are Internal and Vssp Internal 1 2 used as ADC voltage reference ground Internal 1 2V and Vaso Up to 4 analog input channels Conversion speed and sample time adjustable to adapt to sensors and reference Conversion time below 1 us depending on result width and sample time Flexible source selection and arbitration Single channel conversion single or repeated Configurable auto scan conversions single or repeated Programmable arbitrary conversion sequence single or repeated Conversions triggered by software timer events or external events Wait for start mode for maximum throughput or Cancel inject restart mode for reduced conversion delay Powerful result handling Selectable result width of 8 to 10 bits 4 independent result registers Configurable limit checking against programmable borde
360. e PCLK at a frequency of either 8 MHz or 24 MHz 13 2 3 Interrupt Events and Assignment Table 13 2 lists the interrupt event sources from the Timer 0 and 1 and the interrupt node assignment for each Timer 0 and 1 interrupt source Table 13 2 Timer 0 and 1 Events Interrupt Node Control Event Interrupt Node Enable Interrupt Node Flag Vector Bit Bit Address Timer 0 Overflow IENO ETO TCON TFO 0B Timer 1 Overflow IENO ET1 TCON TF1 1B User s Manual 13 2 V1 0 2010 02 Timer 0 and 1 V1 0 Cinfineon 0 1 13 3 Basic Timer Operations The operations of the two timers are controlled using the Special Function Registers SFRs TCON and TMOD To enable a timer i e allow the timer to run its control bit TCON TRx is set To select the timer input to be either from internal system clock or external pin the input selector bit TMOD is used Note The x e g TCON TRx in this chapter denotes either 0 or 1 Each timer consists of two 8 bit registers TLx low byte and THx high byte which defaults to 00 on reset Setting or clearing TCON TRx does not affect the timer registers Timer Overflow When a timer overflow occurs the timer overflow flag TCON TFx is set and an interrupt may be raised if the interrupt enable control bit IENO ETx is set The overflow flag is automatically cleared when the interrupt service routine is entered When Timer 0 operates in
361. e Prescaler Determines the baud rate for the IIC in master mode 0 7 w Reserved Should be written with 0 17 9 6 Software Reset Register The SRST register provides for a software reset on the IIC SRST Software Reset Register DF Reset Value XX RMAP 0 PAGE X 7 6 5 4 3 2 1 0 SRST i w User s Manual 17 21 V1 0 2010 02 IIC V1 1 Cinfineon Inter IC Bus Field Bits Type Description SRST 7 0 Software Reset Writing any value to the SRST bit field triggers a soft reset on the IIC User s Manual 17 22 V1 0 2010 02 IIC V1 1 Cinfineon neers High Speed Synchronous Serial Interface 18 High Speed Synchronous Serial Interface 18 1 Overview The High Speed Synchronous Serial Interface SSC supports both full duplex and half duplex serial synchronous communication The serial clock signal can be generated by the SSC itself Master Mode through its own 16 bit baud rate generator or can be received from an external master Slave Mode Data width shift direction clock polarity and phase are programmable This allows communication with SPl compatible devices using other synchronous serial interfaces Transmission and reception of data is double buffered Features Master and Slave Mode operation Full duplex or half duplex operation Transmit and receive buffered Flexible data format Programmable number of data bits 2 to 8 bits
362. e Trap State This offers SW the option to select the best operation for the application Exiting the Trap State can be done either immediately when the trap condition is removed CTRAP 1 or TRPPEN 0 or under software control or synchronously to the PWM generated by either Timer T12 or Timer T13 CTRAP Entry Exit Control TRPPEN T12 ZM T13 ZM Trap Exit To T12 Synchro T13 Output TRMO 1 nization Modulation CCU6_MCB05541 Figure 20 33 Trap Logic Block Diagram User s Manual 20 85 V1 0 2010 02 CCU6 V4 0 Cinfineon Capture Compare Unit 6 CCU6 Clearing of TRPF is controlled by the mode control bit TRPM2 If TRPM2 0 TRPF is automatically cleared by HW when CTRAP returns to the inactive level CTRAP 1 or if the trap input is disabled TRPPEN 0 When TRPM2 1 TRPF must be reset by SW after CTRAP has become inactive Clearing of TRPS is controlled by the mode control bits TRPM1 and TRPMO located in the Trap Control Register TRPCTRL H A reset of TRPS terminates the Trap State and returns to normal operation There are three options selected by TRPM1 and TRPMO One is that the Trap State is left immediately when the Trap Flag TRPF is cleared without any synchronization to timers T12 or T13 The other two options facilitate the synchronization of the termination of the Trap State to the count periods of either Timer T12 or Timer T13 Figure 20 34 gives an ove
363. e X Error Reference value Actual value k Time or instantaneous time Table 23 3 Specifications of PI Controller Routine Subroutine PI controller G16 controller 6256 Routine Address 0 0649 controller G16 OxD64F controller G256 C Prototype int Pl controller G16 int Ref val int Actual val Pl param int Pl controller G256 int Ref val int Actual val Pl param User s Manual 23 4 V1 0 2010 02 ROM Library V0 5 Cinfineon XC82x ROM Library Table 23 3 Specifications of PI Controller Routine cont d Input R7 R6 MSB Ref_val 16 bit Reference value R5 R4 MSB Acutal_val 16 bit Actual value R3 idata pointer to Y k 1 _H Remark Required structure Struct Y k 1 HLh Kp HL Ki HL PI SAT HH high byte of 24 bit saturation value OXHHFFFF Output R7 R6 MSB 16 bit Y k value Execution Cycle PI controller G16 248 cclks PI controller G256 226 cclks Resource used destroyed PSW A MDU RO R2 R4 R5 of current Register Bank Code Example define structure typedef struct pi char int int yn 3 kp ki unsigned char SAT HH param global variables data int Speed data int Speed ref data int PI Speed idataPI param Speed control program Speed 2048 Speed ref 4000 Speed control yn 0 0x01 Speed control yn 1 0x4C Speed control
364. e and transferred into the compare register when signal T13 shadow transfer T13_ST gets active Providing a shadow register for the compare value as well as for other values related to the generation of the PWM signal facilitates a concurrent update by software for all relevant parameters Associated with the channel is a State Bit CMPSTATL CC63ST holding the status of the compare operation Figure 20 28 gives an overview on the logic for the State Bit Counter Register T13 fri To State State Bit Selection and tes CC63ST Output ogic Modulation Compare Register MCC63S R CC63R A T13 ST Compare Shadow Register CC63SR CCU6 05532 Figure 20 28 T13 State Bit Block Diagram gt To Interrupt Control A compare interrupt event CM_63 is signaled when a compare match is detected The actual setting of a State Bit has no influence on the interrupt generation The inputs to the switching rule logic for the CC63ST bit are the timer run bit T13R the timer zero match signal T13 ZM and the actual individual compare match signal User s Manual 20 74 V1 0 2010 02 CCU6 V4 0 Cinfineon Capture Compare Unit 6 CCU6 CM 63 In addition the state bit can be set or cleared by software via bits MCC63S and MCC63R in register CMPMODIFL CMPMODIFH A modification of the State Bit CC63ST by hardware is only possible while Timer T13 is running T13R 1 I
365. e of 75 KHz internal oscillator User s Manual 8 1 V1 0 2010 02 WDT V1 0 Cinfineon Watchdog Timer 8 2 System Information This section consist of the system information required to use the WDT 8 2 1 Reset effects The Watchdog Timer maintains a counter which must be refreshed or cleared periodically Otherwise the counter will overflow and the watchdog reset will be asserted The occurrence of a WDT reset is indicated by the bit WDTRST in RSTCON register The bit field of The bit field PAGE of SCU PAGE register must be programmed before accessing the RSTCON register RSTCON Reset Control Register F7 Reset Value 00 RMAP 0 PAGE 1 7 6 5 4 3 2 1 0 SWRQ 0 SOFTRS WDTRST WKRS rwh rwh rwh rwh 1 The reset value for watchdog timer reset is 02 Field Bits Description WDTRST 1 rwh Watchdog Timer Reset Indication Bit 0 No watchdog reset occurred 1 Watchdog reset has occurred This bit can only be set by hadware and clear by software 0 6 3 r Reserved Returns 0 if read should be written with 0 8 2 2 Clocking Configuration The WDT runs on the 75 KHz Oscillator 8 2 3 Interrupt Events and Assignment Table 8 1 shows the non maskable interrupt node assignment of the WDT interrupt source User s Manual 8 2 V1 0 2010 02 WDT V1 0 T6 XC82x Infineon Watchdog Timer Table 8 1 WDT Events Non maskable Interrupt Node Contr
366. e phase system into a two phase orthogonal system It s implementation is defined as 23 5 I alpha I phaseA 2 23 6 Theta assa 2 2 where Y k PT1 24 controller output Y k 1 Previous PT1 24 controller output e Z Division factor of 1 22 X k 16 bit input k Time or instantaneous time Table 23 6 Specifications of Clarke Transform Routine Subroutine Clarke Routine Address OxD7CE Clarke User s Manual 23 8 V1 0 2010 02 ROM Library V0 5 Cinfineon Table 23 6 XC82x ROM Library Specifications of Clarke Transform Routine C Prototype void Clarke int idata phaseAB int idata _alphabeta Input R7 idata pointer to phaseA R5 idata pointer to alpha H Remark char idata phaseAB Expected addreass arrangement in IRAM phaseA H MSB _phaseA_L _phaseB_H _phaseB_L char idata alphabeta Expected addreass arrangement in IRAM alpha alpha beta beta L Output Result of alpha beta saved in address location of 274 input parameter Execution Cycle 84 cclk Resource PSW A MDU used destroyed RO R1 of current Register Bank Code Example declare variables data int phaseA 0x36 data int phaseB 0x38 data int I alpha at 0x4A data int I beta at 0x4C program I phaseA 2048 I phaseB 8192 Clarke amp I phaseA amp I alpha alpha O
367. e products Setting the bit fields to 1 may lead to unpredictable results Undefined Certain bit combinations in a bit field can be labeled Reserved indicating that the behavior of the XC82x is undefined for that combination of bits Setting the register to undefined bit combinations may lead to unpredictable results Such bit combinations are reserved When writing software must always set such bit fields to legal values as provided in the bit field description tables rw The bit or bit field can be read and written The bit or bit field can only be read read only w The bit or bit field can only be written write only Reading always return 0 h The bit or bit field can also be modified by hardware such as a status bit This attribute can be combined with rw or r bits to rwh and rh bits respectively 1 7 Acronyms Table 1 3 lists the acronyms used in this document Table 1 3 Acronyms Acronym Description ADC Analog to Digital Converter ALU Arithmetic Logic Unit BSL Boot Loader User s Manual 1 14 V1 0 2010 02 System Architecture V1 0 Cinfineon Introduction Table 1 3 Acronyms cont d Acronym Description CAN Controller Area Network CCU6 Capture Compare Unit 6 CGU Clock Generation Unit CORDIC Cordinate Rotation Digital Computer CPU Central Pr
368. e same function of Mode 1 except that the 9 bits prescaler is bypassed The external clock via RTCCLK pin is the input clock to the timer User need to select the RTCCLK pin to input mode and connect to a external clock before the counter can start to run In XC82x RTC Mode 3 cannot be used to wake up from power down mode User s Manual 15 4 V1 0 2010 02 RTC V1 0 Cinfineon Real Time Clock Real Time Clock Counter y y y RTCCLK CNTO CNT1 CNT2 CNT3 External Clock 4 4 7 Bis Bt15 Bt16 Bt23 Bt 24 31 Timer RTCC y vj Rrccr vi Rrccr a Interrupt 32 bits Comparator CFRTC Request rey 2 lt P q ECTRC X X RTCCRI RTCCR2 RTCCR3 Bit 0 Bt8 Bt16 BL17 Bt 23 Bit 24 Bit 31 Real Time Clock CompardCapture Registers Figure 15 2 Real time Clock Mode 15 6 Power Saving Mode Option Once started the real time clock continues counting until the bit RTCON RTCC is cleared The real time clock is not affected by the idle mode of the XC82x and continues counting in power down mode except in power down mode 1 In addition the real time clock will not stopped automatically if the bit OSC_CON 75KOSC2L status is set to 1 In power down modes 2 the real time clock continues to run provided the clock so
369. e service request output that will be activated is selected by bit field INPT13 User s Manual CCU6 V4 0 20 121 V1 0 2010 02 Cinfineon XC82x Capture Compare Unit 6 CCU6 Field Bits Type Description ENTRPF 2 rw Enable Interrupt for Trap Flag Og No interrupt will be generated if the set condition for bit TRPF in register IS occurs 1g An interrupt will be generated if the set condition for bit TRPF in register IS occurs The service request output that will be activated is selected by bit field INPERR ENCHE 4 rw Enable Interrupt for Correct Hall Event No interrupt will be generated if the set condition for bit CHE in register IS occurs 1g An interrupt will be generated if the set condition for bit CHE in register IS occurs The service request output that will be activated is selected by bit field INPCHE ENWHE 5 rw Enable Interrupt for Wrong Hall Event Og No interrupt will be generated if the set condition for bit WHE in register IS occurs 1g An interrupt will be generated if the set condition for bit WHE in register IS occurs The service request output that will be activated is selected by bit field INPERR ENIDLE 6 rw Enable Idle This bit enables the automatic entering of the idle state bit IDLE will be set after a wrong hall event has been detected bit WHE is set During the idle state the bit field MCMP is automatically cleared The bit IDLE is not automatically set when
370. e set by software via the associated set clear bits T13RS or T13RR in register TCTRAL TCTRAH or it is cleared by hardware according to preselected conditions single shot mode The timer T13 run bit T13R must not be set while the applied T13 period value is zero Bit T13R can be set automatically if an event of T12 is detected to synchronize T13 User s Manual 20 68 V1 0 2010 02 CCU6 V4 0 Cinfineon Capture Compare Unit 6 CCU6 timings to T12 events e g to generate a programmable delay via T13 after an edge of a T12 compare channel before triggering an AD conversion T13 can trigger ADC conversions Timer T13 can be cleared to 0000 via control bit T13RES Setting this write only bit only clears the timer contents but has no further effects e g it does not stop the timer The generation of the T13 shadow transfer control signal T13_ST is enabled via bit STE13 This bit can be set or cleared by software indirectly through its associated set reset control bits T13STR and T13STD Two bit fields T13TEC and T13TED control the synchronization of T13 to Timer T12 events T13TEC selects the trigger event while T13TED determines for which T12 count direction the trigger should be active While Timer T13 is running write accesses to the count register T13 are not taken into account If T13 is stopped write actions to register T13 are immediately taken into account Note The T13 Period Register and its associated shadow
371. e slice Figure 19 1 shows an example for a LED matrix configuration with touch pads The configuration in this example is 8 X 4 LED matrix with 4 touch pad turns here 6 touch pads enabled in sequence by hardware Here four time frames complete a time period In the time slice interrupt software can setup line value for next time slice setup compare value for next time slice Refer to Section 19 7 for Interpretation of Bit Field FNCOL to determine the currently active time slice A time frame interrupt indicates one touch input line has been sensed application level software can for example Start touch sense analysis routines and update status enable LED display update User s Manual 19 6 V1 0 2010 02 LEDTSCU V 1 2 1 Infineon XC82x LED and Touch Sense Controller One complete period m Frame 0 Frame 1 Frame 2 Frame 3 Y mp E d 5 3 5 us 201 5 ms C3 C2 C1 O0 TS ca C2 C2 C CO TS C2 1 TS XD nO OO a T Ta E E 4 aS E W a ssa tat
372. e state of the port pin If an on chip peripheral uses the pin for output signals alternate output lines AltDataOut can be switched via the multiplexer to the output driver circuitry Selection of the alternate function is defined registers PO ALTSELO PO ALTSEL1 PO ALTSEL2 P1 ALTSELO and P1 ALTSEL1 To configure the pin to input mode default after reset the output driver must be Switched to high impedance using the following steps Enable the the open drain function via register Px OD Set output driver to high impedance by writting 1 to the port pin via register Px DATAOUT Select normal GPIO as alternate output function via register Px ALTSELx Setting to normal GPIO alternate function is not necessary if the alternate output line is ensured to held at high during input mode The actual voltage level present at the port pin is translated into a logic 0 or 1 via a Schmitt Trigger device and can be read via the register Px DATAIN Each pin can also be programmed to activate an internal weak pull up or pull down device Register Px PUDSEL selects whether a pull up or the pull down device is activated while register Px PUDEN enables or disables the pull device A following code shows the configuration of all Port 0 pins to input mode ANL SYSCONO 0 OV PORT PAGE 0x03 OV PO OD 0xFF Enable open drain OV PORT PAGE 40x00 OV PO DATAOUT SOxFF PO DATAOUT PORT PAGE 0x00 OV PORT
373. e to write to any protected bits PASS 7 3 wh Password bits The Bit Protection Scheme only recognizes three patterns 11000gEnables writing of the bit field MODE 10011gO0pens access to writing of all protected bits 10101 Closes access to writing of all protected bits User s Manual Memory Organization V 0 1 3 12 V1 0 2010 02 Infineon near Memory Organization 3 4 5 XC82x Register Overview The SFRs of the XC82x are organized into groups according to their functional units The contents bits of the SFRs are summarized in Section 3 4 5 1 to Section 3 4 5 12 Note The addresses of the bit addressable SFRs appear in bold typeface 3 4 5 1 CPU Registers The CPU SFRs can be accessed in both the standard and mapped memory areas RMAP 0 or 1 Table 3 1 CPU Register Overview Addr Register Name Bit 7 6 5 4 3 2 1 0 IRMAP 0 or 1 gu SP Reset 07 4 Bit Field SP Stack Pointer Register Type TW 82u DPL Reset 004 Bit Field DPL7 DPL6 DPL5 DPL4 DPL3 DPL2 DPL1 DPLO Data Pointer Register Low Type TW rw rw rw rw rw rw rw 83u DPH Reset 004 Bit Field DPH7 DPH6 DPH5 DPH4 DPH3 DPH2 DPH1 Data Pointer Register High Type TW rw rw rw rw rw rw rw 87H PCON Reset 004 Bit Field SMOD 0 1 G
374. eal transfer curve can exhibit certain deviations from the ideal transfer curve The offset error is the deviation of the real transfer line from the ideal transfer line at the lowest code This refers to best fit lines through all possible codes for both cases The gain error is the deviation of the slope of the real transfer line from the slope of the ideal transfer line This refers to best fit lines through all possible codes for both cases The differential non linearity error DNL is the deviation of the real code width variation of the analog input voltage between two adjacent digital conversion results from the ideal code width A DNL value of 1 LSB indicates a missing code The integral non linearity error INL is the deviation of the real transfer curve from an adjusted ideal transfer curve same offset and gain error as the real curve but equal code widths The total unadjusted error TUE describes the maximum deviation between a real conversion result and the ideal transfer characteristics over a given measurement range Since some of these errors noted above can compensate each other the TUE value generally is much less than the sum of the individual errors The TUE also covers production process variations and internal noise effects if switching noise is generated by the system this generally leads to an increased TUE value User s Manual 21 12 V1 0 2010 02 ADC V2 1 Cinfineon Analog to Digital Conv
375. echniques including Stopping the CPU clock Stopping the clocks of individual system components Reducing clock speed of some peripheral components Power down of the entire system with fast restart capability After a reset the active mode normal operating mode is selected by default see Figure 7 3 and the system runs in the main system clock frequency In active mode the system clock could be running in 24 MHz or 8 MHz From active mode different power saving modes can be selected by software They are Idle mode e Power down mode 1 Power down mode 2 POWER DOWN MODE 1 Set bits PDMODE 0s set IDLE bit active any interrupt EXINTORTC Set bits wake up event PDMODE 1s POWER DOWN MODE 2 Figure 7 3 Transition between Power Saving Modes without reset EXINTO pin In XC82x all functions must be operational in the active mode and idle mode when the normal Vppp supply range of 3 0 V to 5 5 V is applied to the system For reduced voltage condition in active mode and idle mode required functions as needed by user will be available as long as the active current is kept under the limits As for power down mode User s Manual 7 16 V1 0 2010 02 Cinfineon System Control Unit specified modules as described in Section 7 4 1 2 must continue to function when the Vppp is as low as 2 5 V but maybe performance could be reduced 7 4 1 Functional Description 7 4 1 1 Idle Mode The idle mo
376. ected when the corresponding bit position is written with a 1 flag CHINFx is cleared ADC CHINCR Channel Interrupt Clear Register Reset Value 00 RMAP 0 PAGE 5 7 6 5 4 3 2 1 0 CHINC7 6 CHINC5 4 CHINC2 CHINC1 CHINCO w w w w w w Ww w Field Bits Type Description CHINCx x w Clear Interrupt Flag for Channel x x 0 7 Og No action 1g Bit CHINFR x is reset Note Bit 4 7 are only applicable for devices that have 8 ADC channels For channels not implemented these bits should be treated as Reserved bits of type f which returns 0 if read and should be written with 0 21 12 Register Mapping The addresses of the kernel SFRs are listed in Table 21 7 and Table 21 8 Table 21 7 SFR Address List for Pages 0 3 Address Page 0 Page 1 Page 2 Page 3 CAH ADC_GLOBCTR CHCTRO RESROL CBH ADC GLOBSTR CHCTR1 RESROH CCH ADC PRAR CHCTR2 RESR1L CDH ADC LCBRO CHCTR3 RESR1H CEH ADC_INPCRO CHCTR4 RESR2L CFH ADC LCBR1 CHCTR5 RESR2H D2H ADC LORC CHCTR6 RESR3L D3H ADC ENORC CHCTR7 RESR3H User s Manual 21 89 V1 0 2010 02 ADC V2 1 Cinfineon Table 21 8 SFR Address Listing for Pages 4 7 XC82x Analog to Digital Converter Address Page 4 Page 5 Page 6 Page 7 CAH RCRO ADC CHINFR CRCR1 CBH RCR1 ADC CHINCR ADC_CRPR1 CCH
377. ection capability requires that the slave s baud rate generator is programmed to the User s Manual 18 17 V1 0 2010 02 SSC V1 4 Cinfineon neers High Speed Synchronous Serial Interface same baud rate as the master device This feature detects false additional or missing pulses on the clock line within a certain frame Note If this error condition occurs and bit CON AREN 1 an automatic reset of the SSC will be performed in case of this error This is done to re initialize the SSC if too few or too many clock pulses have been detected Note This error can occur after any transfer if the communication is stopped This is the case due to the fact that the SSC module supports back to back transfers for multiple transfers In order to handle this the baud rate detector expects after a finished transfer immediately a next clock cycle for a new transfer A Transmit Error Slave Mode is detected when a transfer was initiated by the master SS_CLK gets active but the transmit buffer TB of the slave was not updated since the last transfer This condition sets the error flag CON TE and the error interrupt request line EIR when enabled via CON TEN If a transfer starts while the transmit buffer is not updated the slave will shift out the old contents of the shift register which normally is the data received during the last transfer This may lead to corruption of the data on the transmit receive line in half duplex mode open drai
378. ecture V1 0 Cinfineon XC82x Introduction Table 1 1 Pin Definitions and Functions for XC82x Symbol Pin Type Reset Function Number State DSO20 TSSOP16 P1 4 2 Hi Z EXINT5 External Interrupt Input 5 COL4 LED Column 4 COUT62_0 Output of Capture Compare channel 2 COUT63_1 Output of Capture Compare channel 3 P1 5 3 Hi Z CC62 0 Input Output of Capture Compare channel 2 COL5 LED Column 5 COLA 0 LED Column A P2 2 Port 2 is a general purpose input only port It be used as inputs for A D Converter and out of range comparator CCU6 Timer 2 SSC and UART P2 0 7 6 Hi Z 501 CCU6 Hall Input 0 T12HR_2 CCU6 Timer 12 Hardware Run Input T13HR_2 CCU6 Timer 13 Hardware Run Input T2EX_3 Timer 2 External Trigger Input T2 1 Timer 2 Input EXINTO 3 External Interrupt Input O ANO Analog Input 0 Out of range comparator channel 0 User s Manual System Architecture V1 0 V1 0 2010 02 Cinfineon XC82x Introduction Table 1 1 Pin Definitions and Functions for XC82x Symbol Pin Type Reset Function Number State DSO20 TSSOP16 P2 1 6 5 Hi Z CCPOS1 1 CCU6 Hall Input 1 RXD 3 UART Receive Input MTSR 4 Slave Receive Input TO 1 Timer 0 Input EXINT1 1 External Interrupt Input 1 AN1 Analog Input 1 Out of range comparator channel 1 P2 2 5 4 Hi Z CCPOS2 1 CCU6 Hall Input 2 T12HR 3 CCU6 Timer 12 Hardware Run Input T13HR 3 CCU6 Timer 13 Hard
379. ed 1g trap condition is has been detected TRPS rh Trap State This bit indicates the actual trap state It is set if 1 and becomes cleared according to the mode selected in register TRPCTR Og trap state is not active 1g The trap state is active CHE rh Correct Hall Event This bit indicates that a correct Hall event CM CHE has been detected Og The event has not yet been detected 1g event has been detected WHE rh Wrong Hall Event This bit indicates that a wrong Hall event CM WHE has been detected event has not yet been detected 1g event has been detected IDLE rh IDLE State If enabled by ENIDLE 1 this bitis set together with bit WHE and it has to be cleared by SW Og action 1p Bit field MCMP is cleared the selected outputs are set to passive state User s Manual CCU6 V4 0 20 114 V1 0 2010 02 Cinfineon XC82x Capture Compare Unit 6 CCU6 Field Bits Type Description STR rh Multi Channel Mode Shadow Transfer Request This bit indicates that a shadow transfer from MCMPS to MCMP MCM_ST has taken place Og event has not yet been detected 1g event has been detected 1 During the trap state the selected outputs are set to the passive state The logic level driven during the passive state is defined by the corresponding bit in regis
380. ed 2 Resource A RO R1 R2 R3 RA used destroyed 1 This common Compare parameter cannot be OxFF value Table 23 10 Specifications of Setting LDLINE amp Different COMPARE TS only Subroutine SET_LDLINE_CMP Address DFCF User s Manual 23 15 V1 0 2010 02 ROM Library V0 5 Cinfineon XC82x ROM Library Table 23 10 Specifications of Setting LDLINE amp Different COMPARE TS only Input R7 of current Register Bank Start IRAM address of LDLINE parameter R5 of current Register Bank Start IRAM address of CMP OPTION amp COMPARE parameters LDLINE parameters programmed into IRAM address R7 LDLINE parameter for COLA TS COMPARE parameters programmed into IRAM R5 R5 1 etc 5 CMP OPTION OxFF value R5 1 COMPARE parameter for PADTO 5 2 COMPARE parameter for PADT1 R5 z COMPARE parameter for PADT z 1 Output Sfr LTS LDLINE is programmed Sfr LTS COMPARE is programmed Stack size required 2 Resource used destroyed A RO R1 R2 R3 R4 1 Depending how many Touch sense pad turn s is are enabled z no of PADTx enabled User s Manual ROM Library V0 5 23 16 V1 0 2010 02 Cinfineon ROM Library 23 2 1 3 Inputs for SET_LDLINE_CMP Function LED and TS If both LED and Touch sense modules are enabled the inputs overview is shown in Table 23 11 and Table 23 12 for common and different
381. ed Invalid options R5 of current Register Bank 00 8MHz 80 24MHz Others Reserved Output C 0 Correct option is selected CLK Mode is set accordingly C 1 Invalid option is selected Stack size required 9 Resource A used destroyed User s Manual 22 4 V1 0 2010 02 BootROM User Routines V1 1 Cinfineon Boot ROM User Routines Table 22 6 Specifications of Program USER ID subroutine Subroutine BR_PROG_USER_ID BR_FEATURE_SETTING Option 1 Input R7 of current Register Bank Option 01 Option 1 BR_PROG_USER_ID Others Reserved Invalid options R5 of current Register Bank IRAM start address for 4 byte User Identification Number R5 USER ID 3 R5 1 USER ID 2 R5 2 USER ID 1 R5 3 USER ID 0 4 byte User ID Information in IRAM SFR NMISR 7 00 Stack Pointer SP Setting 0x07 lt SP lt 0x60 or 0 lt SP lt OxEO Output C 1 Programming of User ID has failed C 1 Routine is exited as NMISR is not 00 error Stack size required 10 Resource DPTR A used destroyed RO R1 R3 R5 R6 and R7 of current Register Bank 6 bytes IRAM Address 0x80 OxBF 64 bytes 1 Routine is exited and output is observed only when programming of USER ID has failed When successful programming of USER a soft reset will be triggered and it will boot up in the programmed Boot up Mode depending on BMI 22 4 UART Auto Baud Subr
382. ed The RETI instruction informs the processor that the interrupt routine is no longer in progress then pops the two top bytes from the stack and reloads the PC Execution of the interrupted program continues from the point where it was stopped Note that the RETI instruction is important because it informs the processor that the program has left the current interrupt priority level A simple RET instruction would also have returned execution to the interrupted program but it would have left the interrupt control system on the assumption that an interrupt was still in progress In this case no interrupt of the same or lower priority level would be acknowledged 9 4 Interrupt Response Time Due to an interrupt event of the various sources of an interrupt node its corresponding request signal will be sampled active at phase 2 in every machine cycle The value is not polled by the circuitry until the next machine cycle If the request is active and conditions User s Manual 9 13 V1 0 2010 02 Interrupt System V 2 3 3 Cinfineon Interrupt System are right for it to be acknowledged a hardware subroutine call to the requested service routine will be the next instruction to be executed The call itself takes two machine cycles Thus a minimum of three complete machine cycles will elapse from activation of the interrupt request to the beginning of execution of the first instruction of the service routine as shown in Figure 9 9
383. ediately On set this bit is held for two PCLK clock cycle then cleared by hardware Reading this bit always return O ECRTC 4 Real Time Clock Compare Interrupt Enable Og Disable real time clock compare interrupt 1g X Enable real time clock compare interrupt ESRTC 5 Real Time Clock Second Timing Interrupt Enable Og Disable real time clock interrupt at every second in Mode 0 1g Enable real time clock interrupt at every second in Mode 0 Note The interrupt function at every second is only available in Mode 0 and Mode 2 User s Manual RTC V1 0 15 7 V1 0 2010 02 Cinfineon Real Time Clock Field Bits Type Description CFRTC 6 rwh Real Time Clock Compare Flag This bit is set by hardware when there is a compare match and can only be cleared by software A wake up request is generated only if the XC82x is either in power down mode 2 3 or 4 SFRTC 7 rwh Real Time Clock Second Timing Flag This bit is set by hardware at every second and can only be cleared by software It is only available in Mode 0 and Mode 2 4 count registers CNTO CNT3 are used to represent the most significant 32 bits of the 41 bits real time clock timer in Mode 1 and 32 bits timer in Mode 3 RTC CNTO Mode 1 and Mode 3 Count Clock Register 0 E1 Reset Value 00 RMAP 0 PAGE X 7 6 5 4 3 2 1 0 VAL rwh Field Bits Type Description CNT VAL 7 0 rwh
384. egister Px_OD Px_OD Port x Open Drain Control Register 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 1 PO rw rw rw rw rw rw rw rw Field Bits Type Description Pn n rw Port x Pin n Open Drain Mode 0 7 0 Normal Mode output is actively driven for 0 and 1 state 1 Open Drain Mode output is actively driven only for 0 state default User s Manual 11 8 V1 0 2010 02 Cinfineon Parallel Ports Pull Up Pull Down Device Register Internal pull up pull down devices can be optionally applied to a port pin This offers the possibility to configure the following input characteristics Tristate High impedance with a weak pull up device High impedance with a weak pull down device and the following output characteristics e Push pull optional pull up pull down Open drain with internal pull up Open drain with external pull up The pull up pull down device can be fixed or controlled via the registers Px PUDSEL and Px_PUDEN Register Px_PUDSEL selects the type of pull up pull down device while register Px_PUDEN enables or disables it The pull up pull down device can be selected pinwise Px_PUDSEL Port x Pull Up Pull Down Select Register 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 rw rw rw rw rw rw rw rw Field Bits Type Description Pn n rw Pull Up Pull Down Select Port x Bit n
385. egister x This bit indicates that the contents of the result register x are valid Os result register x does not contain valid data 1g result register x contains valid data RESULT 2 0 7 5 rh Conversion Result This bit field contains the conversion result or the result of the data reduction filter ADC RESRxH x 0 2 Result Register x High View 10bit 2nd conv CB x 2 Reset Value 00 ADC RESR3H Result Register High View Acc 10bit 2nd conv D3 Reset Value 00 RMAP 0 PAGE 2 7 6 5 4 3 2 1 0 RESULT 10 3 rh Field Bits Type Description RESULT 10 3 7 0 rh Conversion Result This bit field contains the conversion result or the result of the data reduction filter ADC RESRxL x 0 2 Result Register x Low View LPF 10 bit CA x 2 Reset Value 00 ADC RESR3L Result Register 3 Low View LPF 10 bit D2 Reset Value 00 RMAP 0 PAGE 2 7 6 5 4 3 2 1 0 RESULT 4 0 CHNR rh rh User s Manual 21 75 V1 0 2010 02 ADC V2 1 Cinfineon Analog to Digital Converter Field Bits Type Description CHNR 2 0 rh Channel Number This bit field contains the channel number of the latest register update Note Bit 2is only applicable for devices that have 8 ADC channels For channels not implemented these bits should be treated as Reserved bits of type f which returns 0 if read and should be wr
386. egisters Capture Compare Unit 6 CCU6 20 10 2 1 Port Input Select Registers Registers PISELOL and PISELOH contain bit fields selecting the actual input signal for the module inputs PISELOL Port Input Select Register Low RMAP 0 PAGE 3 9E Reset Value 00 7 6 ISTRP ISCC62 ISCC61 ISCC60 rw rw rw Field Bits Type Description ISCC60 1 0 rw Input Select for CC60 This bit field defines the port pin or that is used for the CC60 capture input 00 Input pin 60 0 01 Input pin 60 1 10 CCU6 SR2 event 116 ADC channel 0 boundary limit check event ISCC61 3 2 rw Input Select for CC61 This bit field defines the port pin that is used for the CC61 capture input signal 005 Input pin 61 0 015 Input pin CC61 1 10 CCU6 SR2 event 11 ADC channel 1 boundary limit check event ISCC62 5 4 rw Input Select for CC62 This bit field defines the port pin that is used for the CC62 capture input signal 00 Input pin CC62 O 01g Input pin CC62 1 10 CCU6 SR2 event 116 ADC channel 2 boundary limit check event User s Manual CCU6 V4 0 20 127 V1 0 2010 02 Cinfineon Capture Compare Unit 6 CCU6 Field Bits Type Description ISTRP 7 6 rw Input Select for CTRAP This bit field defines the options that is used for the CTRAP input signal MODPISEL3 CPTRAPIS is concurrently to sele
387. el x has not occurred 1g Achannel interrupt for channel x has occurred Note Bit 4 7 are only applicable for devices that have 8 ADC channels For channels not implemented these bits should be treated as Reserved bits of type f which returns 0 if read and should be written with 0 User s Manual 21 87 V1 0 2010 02 ADC V2 1 Cinfineon Analog to Digital Converter Writing 1 to a bit of the CHINSR register sets the corresponding bit and generates the associated interrupt request Writing a 0 has no effect ADC_CHINSR Channel Interrupt Set Register CC Reset Value 00 RMAP 0 PAGE 5 7 6 5 4 3 2 1 0 CHINS7 CHINS6 CHINSS CHINS4 CHINS3 CHINS2 CHINS1 CHINSO w w Ww w w Field Bits Type Description CHINSx x w Set Interrupt Flag for Channel x x 0 7 Og No action 1g Bit CHINFR x is set and an interrupt pulse is generated Note Bit 4 7 are only applicable for devices that have 8 ADC channels For channels not implemented these bits should be treated as Reserved bits of type r which returns 0 if read and should be written with O User s Manual 21 88 V1 0 2010 02 ADC V2 1 Cinfineon Analog to Digital Converter Writing a 1 to a bit position in the channel indication clear register CHINCR clears the corresponding channel event indication flag CHINFx in register ADC_CHINFR If a channel event is det
388. emory with zero or one two wait state 3 For branch instructions the instruction time may vary depending on jump destina User s Manual 2 14 XC800 Core V 1 0 2 ion V1 0 2010 02 3 Infineon Memory Organization Memory Organization The XC82x CPU operates in the following five address spaces 8 Kbytes of Boot ROM program memory 256 bytes of internal RAM data memory 256 bytes of XRAM memory XRAM can be read written as program memory or external data memory a 128 byte Special Function Register area 4 Kbytes of Flash program memory Figure 3 1 illustrates the memory address spaces of the XC82x FFFF FFFF4 F1004 F100 XRAM XRAM 256 Bytes F000 256 Bytes F000 E000 Boot ROM 8 KBytes C000 B000 Flash Bank 0 4 KBytes A000 Indirect Direct Address Address Internal RAM Special Function Registers 80H 10004 TF Flash Bank 0 han AM Lo 4 KBytes In Debug Mode this 64 byte address area 0000 0000 00 is replaced by a 64 byte Monitor RAM Code Space External Data Space Internal Data Space 1 Physically one 4 Kbyte Flash bank mapped to both address range C lemory Map User Mode Figure 3 1 Memory Map of XC82x User s Manual 3 1 V1 0 2010 02 Memory Organization V 0 1 Cinfineon Memory Organization 3 1 Program Memory The code space is theorectically 64 KBytes Howev
389. er DRC If DRC 0 t3 t5 t7 t9in the example the conversion result is stored to the register DRC is loaded with the contents of bitfield RCRx DRCTR i e the accumulation begins IfDRC gt 0 t2 t4 t6 t8in the example the conversion result is added to the value in the result register DRC is decremented by 1 User s Manual 21 81 V1 0 2010 02 ADC V2 1 Cinfineon Analog Digital Converter becomes 0 either decremented from 1 t2 t4 t6 t8 in the example or loaded from DRCTR the valid bit for the respective result register is set and a result register event occurs The final result must be read before the next data reduction sequence starts before t3 t5 t7 or t9in the example This automatically clears the valid flag Digital Low Pass Filter Mode Alternatively the data reduction logic can build a digital low pass filter by adding the amplified result factor 4 to the attenuated current value factor 0 5 Each result register can be individually enabled for low pass filtering controlled by bitfield LPFEN in registers ADC_RCRx x 0 3 The data reduction counter DRC is not used in this case Note For low pass filtering the result data must come from one dedicated channel conversion results for RESRAx contents of RESRAx VFR VFx t1 t2 t3 t4 t4 MC_ADC_LPFILTER Figure 21 29 Low Pass Filter Operation Each result is multiplied by 4 and ad
390. er only access to defined program memory as shown in memory map figure is supported For XC82x defined code space is occupied by on chip memories 3 2 Data Memory The data space consists of an internal and external data space Access to internal and external data space are distinguished by different sets of instruction opcodes In XC82x on chip XRAM is located in external data space and accessed by MOVX instructions XC82x does not support access to external off chip memory Internal data space is occupied by Internal RAM IRAM and Special Function Registers SFRs distinguished by direct or indirect addressing 3 2 1 Internal Data Memory The internal data memory is divided into two physically separate and distinct blocks the 256 byte RAM and the 128 byte Special Function Register SFR area While the upper 128 bytes of RAM and the SFR area share the same address locations they are accessed through different addressing modes The lower 128 bytes of RAM can be accessed through either direct or register indirect addressing while the upper 128 bytes of RAM can be accessed through register indirect addressing only The SFRs are accessible through direct addressing The 16 bytes of RAM that occupy addresses from 20 to 2F are bitaddressable RAM occupying direct addresses from 304 to 7F can be used as scratch pad registers or used for the stack 3 2 2 External Data Memory The 256 byte XRAM is mapped to both the external data me
391. er 1 Full duplex serial port UART 2 2 XC800 Core Functional Blocks Figure 2 1 shows the functional blocks of the XC800 Core The XC800 Core consists mainly of the instruction decoder the arithmetic section the program control section the access control section and the interrupt controller The instruction decoder decodes each instruction and accordingly generates the internal signals required to control the functions of the individual units within the core These internal signals have an effect on the source and destination of data transfers and control the ALU processing User s Manual 2 1 V1 0 2010 02 XC800 Core V 1 0 2 Cinfineon 800 Internal Data pun Memory N A N N Core SFRs 7 Register Interface t External Data External SFRs Memory AN 16 bit Registers amp N ALU Memory Interface EC Program Memory Opcode amp Immediate Multiplier Divider Registers Opcode Decoder Timer 0 Timer 1 y Clocks gt S ine amp Memory Wait LA tate Machine IAN IN UART Power Saving Nem Reset 4 Legacy External Interrupts IENO IEN1 _ gt External Interrupts j gt Interrupt Controller Non Maskable Interrupt j
392. er peripherials are clocked by PCLK which is the same as CPU clock In normal running mode PCLK CCLK In active mode there are 2 clocking frequencies 8 MHz and 24 MHz for the CPU clock CCLK SCLk and the peripherials clock PCLK A user routine called BR_CLKMODE_SETTING in the Boot ROM is used to switch between these 2 clock frequencies If the CLKMODE input of the user routine is set to 0 8 MHz frequency is selected 24 MHz is selected when CLKMODE is set to 1 While changing the frequency of CPU clock and PCLK clock it is recommended to disable all interrupts to prevent any access to flash that may results in an unsuccessful flash operation In idle mode only the CPU clock CCLK is disabled In power down mode CCLK SCLK FPCLK SPCLK CCLKn and PCLK are all disabled 7 3 1 Oscillator Watchdog There are 2 oscillator watchdogs in XC82x namely the 48 MHz oscillator watchdog 48 MHz OWD and 75 KHz oscillator watchdog 75 KHz OWD The 48 MHz OWD monitors the 48 MHz clock source Only incoming frequencies that are below 40 MHz are detected The 75 KHz OWD monitors the 75 KHz clock source By setting bit OSC_CON RCOWDRST the detection for 48 MHz oscillator and 75 KHz oscillator can be restarted The detection status output is only valid after 13 cycles of the 75 KHz frequency approximately 180 us After reset both the 48 MHz and 75 KHz OWD are default disabled User need to check the status of OSC_CON INTOSC_ST status flag before bo
393. er whose conversion triggered the result event bits 7 3 returns bits 4 0 of the filtered result In RESRxH x 0 3 bits 7 0 returns bits 12 5 of the filtered result Result Read View SFR Page 2 8 bit conversion without accumulation RESRxH RESRxL 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 R7 R6 R5 R4 R3 R2 R1 RO 0 0 0 VF DRC CHNR msb rh Isb rh adc_result_register_view_he_8bit_drctr_dipf 0 vsd Figure 21 22 8bit RCRx DRCTR 0 RCRx DLPF 0 Result Register View Result Read View SFR Page 2 10 bit conversion without accumulation RESRxH RESRxL 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 Re Re R7 Re Ra R2 R1 Ro vr rd CHNR th Isb rh adc_result_register_view_he_10bit_drct 0_dipf 0 vsd Figure 21 23 10bit RCRx DRCTR 0 RCRx DLPF 0 Result Register View User s Manual ADC V2 1 21 66 V1 0 2010 02 Infineon Analog Digital Converter Result Read View SFR Page 2 8 bit conversion with accumulation 1 conversion RESRxH RESRxL 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 R7 R6 R5 R4 R3 R2 R1 RO 0 0 VF DRC CHNR msb rh Isb rh 8 bit conversion accumulated 9 bit 274 conversion onwards RESRxH RESRxL 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1
394. erated and T13 is cleared to 0000 with the next T13 clock edge The Period Register receives a new period value from its Shadow Period Register T13PS that is loaded via software The transfer of a new period value from the shadow register into T13PR is controlled via the T13 Shadow Transfer control signal T13 ST The generation of this signal depends User s Manual 20 67 V1 0 2010 02 CCU6 V4 0 Cinfineon Capture Compare Unit 6 CCU6 on the associated control bit STE13 Providing a shadow register for the period value as well as for other values related to the generation of the PWM signal facilitates a concurrent update by software for all relevant parameters refer to Table 20 4 5 Another signal indicates whether the counter contents are equal to 0000 T13 ZM A Single Shot control bit T13SSC enables an automatic stop of the timer when the current counting period is finished see Figure 20 24 T13RSEL Sync to T12 edge detection edge amp Status detection T13 T13HR Control T1388C Counter Register T13 T13RES Clock Selection lt gt gt T13 PM T13CLK T13PRE Read from T13PR T13 ZM Period Register T43 ST Write to Period Shadow T13PR Register 8BIT 8BIT CCU6 05527 Figure 20 24 T13 Counter Logic and Period Comparators The start or stop of T13 is controlled by the Run bit T13R This control bit can b
395. eration In a Half Duplex Mode only one data line is necessary for both receiving and transmitting of data There are two port configuration options for Half Duplex Mode The first option uses all the three pins but with the data exchange line connected to both the MTSR and MRST pins of each device the shift clock line is connected to the SCLK pin The second option uses two pins and requires the MTSR and MRST lines to be selected for the same GPIO pin thus establishing also only a single data exchange line The shift clock line is connected to the SCLK pin as before The master device controls the data transfer by generating the shift clock while the slave devices receive it Due to the fact that all transmit and receive pins are connected to the one data exchange line serial data may be moved between arbitrary stations Similar to Full Duplex Mode there are two ways to avoid collisions on the data exchange line Only the transmitting device may enable its transmit pin driver This option is applicable only if pin has output driver disabling capability The non transmitting devices use open drain output and send only ones Because the data inputs and outputs are connected together a transmitting device will clock in its own data at the input pin MRST for a master device MTSR for a slave By this method any corruptions on the common data exchange line are detected if the received data is not equal to the transmitted data User s
396. eration EO register Breakpoints can be classified into three types Break Before Make The break happens just before the break instruction i e the instruction causing the break is executed Therefore the break instruction itself will be the next instruction from the user program flow but executed only after the relevant debug action has been taken Break After Make The break happens immediately after the instruction causing it has been executed Therefore the break instruction itself has already been executed when the relevant debug action is taken Break Now The events of this type are asynchronous to the code execution inside the XC82x and there is no instruction causing the debug event in this case The debug action is performed by OCDS as soon as possible once the debug event is raised 10 4 1 Generating Hardware Breakpoints This block is built around a set of comparators dedicated to recognize two types of hardware breakpoints 10 4 1 1 Breakpoints on Instruction Address These IP breakpoints are generated only when the BP address is matched for the first byte of an instruction i e just for the opcode In case of 2 and 3 byte instructions the break will not be generated at all for addresses of the second and third instruction bytes The IP breakpoints are of Break Before Make type therefore the instruction at the breakpoint is executed only after the proper debug action is taken Address Comparators Co
397. ernal interrupt 0 and external interrupt 1 can be selected to bypass edge detection in the SCU for direct feed through to the core This signal to the core can be further programmed to either low level or negative transition activated by the bits ITO and IT1 in the TCON register However for edge detection in SCU TCON ITO 1 must be set to falling edge triggered An active edge event detected in SCU will generate internally two CCLK cycle low pulse for detection by core If the external interrupt is positive negative edge triggered the external source must hold the request pin low high for at least one CCLK cycle and then hold it high low for at least one CCLK cycle to ensure that the transition is recognized If edge detection is bypassed for external interrupt 0 and external interrupt 1 the external source must hold the request pin high or low for at least two CCLK cycles External interrupts 2 to 6 share their interrupt node with other interrupt sources Therefore in addition to the corresponding interrupt node enable each external interrupt 2 to 6 may be disabled individually and are disabled by default after reset The bit field PAGE of SCU PAGE register must be programmed before accessing EXICONO EXICON1 and MODPISEL 1 registers Note Several external interrupts support alternative input pin When switching inputs the active edge level trigger select and the level on the associated pins should be considered to prevent un
398. ero match AND a parallel compare match when T12 is counting up A State Bit CC6xST is cleared to 0 e with the next T12 clock f 42 after a compare match when T12 is counting down i e when the counter is decremented below the compare value in center aligned mode e with the next T12 clock 742 after a zero match AND NO parallel compare match when T12 is counting up Period Value T12 Count Compare Value Zero CC6xST CCU6_MCT05515 Figure 20 11 Compare Operation Edge Aligned Mode Figure 20 13 illustrates some more examples for compare waveforms It is important to note that in these examples it is assumed that some of the compare values are changed User s Manual 20 27 V1 0 2010 02 CCU6 V4 0 Cinfineon Capture Compare Unit 6 CCU6 while the timer is running This change is performed via a software preload of the Shadow Register CC6xSR The value is transferred to the actual Compare Register CC6xR with the T12 Shadow Transfer signal T12 ST that is assumed to be enabled Compare Match 5x Compare Match p Period Value T12 Count Compare Value Zero CC6xST Ae Figure 20 12 Compare Operation Center Aligned Mode User s Manual 20 28 V1 0 2010 02 CCU6 V4 0 Cinfineon Capture Compare Unit 6 CCU6 Period Value 5 T12 Count Zero Down Up Down Up CDIR
399. errupt depending on whether LED or and TS is enabled Figure 23 12 and Figure 23 13 illustrate how users can use and call the functions in respective situations When only LED is enabled function in ROM When only Time Slice interrupt is enabled Time Slice m TimeSliceFlag LED Column Data for display p COMPARE value for PELE brightness Y When only TS is enabled When only Time Frame Slice interrupt is enabled Time FrameSlice Interrupt TimeFrame SliceF Sf _ Y Calculate Average LowTrip which pad gt FINDTOUCHEDPAD touched 1 Set COMPARE value for respective pad s oscillation window p SET LDLINE When only TS are enabled When Time Slice amp Time Frame interrupts are enabled Time Slice Interrupt Set COMPARE value for respective pad s oscillation SET_LDLINE_CMP window NENNEN MN a C RETI Time Frame Interrupt has higher priority default ar Frame in TimeFrameFlag Calculate Average LowTrip which pad gt FINDTOUCHEDPAD touched Y C RETI gt Figure 23 12 Calling of Functions in Interrupt Routine i User s Manual 23 37 V1 0 2010 02 ROM Library V0 5 Infineon ROM Library function in ROM When LED and TS are enable
400. errupt occurs if a new data frame is completely Error received and the last data in the receive buffer was not read Phase Error EIR This interrupt is generated if the incoming data changes between one cycle before and two cycles after the latching edge of the shift clock signal SCLK Baud Rate EIR This interrupt is generated when the incoming clock signal Error Slave deviates from the programmed baud rate by more than Mode only 100 Transmit EIR This interrupt is generated when TB was not updated since Error Slave the last transfer if a transfer is initiated by a master Mode only User s Manual SSC V1 4 18 19 V1 0 2010 02 Cinfineon neers High Speed Synchronous Serial Interface 18 5 Register Description The SSC Special Function Registers are accessed from the standard non mapped SFR area The addresses of the SFRs are listed in Table 18 5 Table 18 5 Register Map Address Register AA CONL AB CONH ACh TBL AD RBL AE BRL AF BRH User s Manual 18 20 V1 0 2010 02 SSC V1 4 Cinfineon XC82x High Speed Synchronous Serial Interface 18 5 1 Configuration Register The operating mode of the serial channel SSC is controlled by the control register CON This register contains control bits for mode and error check selection and status flags for error identification Depending on bit EN either control functions or status flags and master slave control a
401. erter 21 5 Configuration of General Functions While many parameters can be selected individually for each channel source etc some adjustments are valid for the whole ADC kernel 21 5 1 General Clocking Scheme and Control The different parts of an ADC kernel are driven by clock signals that are based on the clock fanc of the bus that is used to access the ADC module The ADC in the XC82x device are connected to the system clock so fanc Jays e The analog clock is used as internal clock for the converter and defines the conversion length and the sample time See Section 21 8 6 e The digital clock fapcp is used for the arbiter and defines the duration of an arbiter round All other digital structures such as interrupts etc are directly driven by the module clock fpc Timing parameters are programmed in register GLOBCTR clock generation unit in SCU fsvs ADC kernel module clock divider for fapci analog clock digital clock fADCI fADCD converter arbiter ADC8_clocking2 interrupts etc Figure 21 4 Clocking Scheme User s Manual 21 13 V1 0 2010 02 ADC V2 1 Cinfineon Analog to Digital Converter Note If the clock generation for the converter of the ADC falls below a minimum value or is stopped during a running conversion the conversion result can be corrupted For correct ADC results the frequency of f must
402. eset Value 004 RMAP 0 PAGE 3 7 6 5 4 3 2 1 0 0 CURH EXPH T rw rw Field Bits Type Description EXPH 10 8 rh Expected Hall Pattern Bit field EXPH is updated by a shadow transfer HP_ST from bit field EXPHS If HCRDY 1 EXPH is compared to the sampled CCPOSx inputs in order to detect the occurrence of the next desired expected hall pattern or a wrong pattern If the sampled hall pattern at the hall input pins is equal to bit field EXPH a correct Hall event has been detected CM CHE CURH 13 11 rh Current Hall Pattern Bit field CURH is updated by a shadow transfer HP_ST from bit field CURHS If HCRDY 1 CURH is compared to the sampled CCPOSx inputs in order to detect a spike If the sampled Hall pattern at the Hall input pins is equal to bit field CURH no Hall event has been detected If the sampled Hall input pattern is neither equal to CURH nor equal to EXPH the Hall event was not the desired one and may be due to a fatal error e g blocked rotor etc In this case a wrong Hall event has been detected CM WHE 0 7 6 r reserved returns 0 if read should be written with 0 User s Manual CCU6 V4 0 20 109 V1 0 2010 02 Cinfineon Capture Compare Unit 6 CCU6 20 9 Interrupt Handling This section describes the interrupt handling of the CCU6 module 20 9 1 Interrupt Structure The HW interrupt event or the SW setting of the corresponding interrupt set bit in register ISS sets
403. ess Extension by Paging Address extension is further performed at the module level by paging With the address extension by mapping the XC82x has a 256 SFR address range However this is still less than the total number of SFRs needed by the on chip peripherals To meet this requirement some peripherals have a built in local address extension mechanism for increasing the number of addressable SFRs The extended address range is not directly controlled by the CPU instruction itself but is derived from bit field PAGE in the module page register MOD_PAGE Hence the bit field PAGE must be programmed before accessing the SFRs of the target module Each module may contain a different number of pages and a different number of SFRs per page depending on the specific requirement Besides setting the correct RMAP bit value to select the SFR area the user must also ensure that a valid PAGE is selected to target the desired SFRs Figure 3 3 shows how a page inside the extended address range can be selected SFR Address from CPU y PAGED MOD_PAGE PAGE SFR SFRO L 8 T sFRx PAGE 1 lt 7 SFRO SFR Data to from CPU gt i __SFRy i __SFRO SFR1 sFRz Module Figure 3 3 Address Extension by Paging User s Manual 3 7 V1 0 2010 02 Memory Organization V 0 1 Cinfineon Memory Organization In orde
404. estart User s Manual 17 12 V1 0 2010 02 V1 1 Cinfineon Inter IC Bus Slave transmit mode can also be entered directly from a master mode if arbitration is lost in master mode during the transmission of an address and the slave address and Read bit are received The status code in the STAT register will then be BO The data byte to be transmitted should then be loaded into the DATA register and IFLG cleared When the IIC has transmitted the byte and received an acknowledge IFLG will be set and the STAT register will contain B8 Once the last byte to be transmitted has been loaded into the DATA register the AAK bit should be cleared when IFLG is cleared After the last byte has been transmitted IFLG will be set and the STAT register will contain C8 The IIC will then return to idle state status code F84 The bit must be set to 1 before slave mode can be entered again If no acknowledge is received after transmitting a byte IFLG will be set and the STAT register will contain CO4 The IIC will then return to idle state If the STOP condition is detected after an acknowledge bit the IIC will return to idle state 17 8 4 Slave Receive In the slave receive mode a number of data bytes are received from a master transmitter The IIC will enter slave receive mode when it receives its own slave address and a Write bit LSB 0 after a START condition The IIC will then transmit an acknowledge bit and set the IFLG b
405. esult Register 0 High Type CCH ADC_RESRiL Reset 00 Bit Field RESULT VF DRC 0 CHNR Result Register 1 Low Type CDH ADC_RESR1H Reset 00 Bit Field RESULT Result Register 1 High Type ADC RESR2L Reset 00 Bit Field RESULT VF DRC 0 CHNR Result Register 2 Low Type rh rh rh r rh ADC_RESR2H_ Reset 004 Bit Field RESULT Result Register 2 High Type D2u ADC RESR3L Reset 004 Bit Field RESULT VF DRC 0 CHNR Result Register 3 Low Type rh rh rh r rh ADC_RESR3H_ Reset 00 Bit Field RESULT Result Register 3 High Type IRMAP 0 PAGE 4 ADC_RCRO Reset 004 BitField WFR 0 IEN 0 DLPF 0 DRCT Result Control Register 0 R R Type rw TW r rw TW r TW User s Manual 3 20 V1 0 2010 02 Memory Organization V 0 1 Infineon XC82x Memory Organization Table 3 5 ADC Register Overview cont d Addr Register Name Bit 7 6 5 4 3 2 1 0 CBH ADC_RCR1 Reset 004 Bit Field WFR IEN DLPF 0 DRCT Result Control Register 1 R R Type rw TW r rw TW r TW CCH ADC_RCR2 Reset 004 Bit Field WFR 0 IEN 0 DLPF 0 DRCT Result Control Register 2 R R Type rw rw r rw r rw r TW CDH ADC_RCR3 Reset 004 Bit Field WFR 0 IEN 0 DLPF 0 DRCT Result Control Register 3 R R Type rw TW r rw r TW r TW AD
406. et Reset See Value Page IENL Interrupt Node Pointer Register Low 9C 0000 Page 20 120 IENH Interrupt Node Pointer Register High 9D 0000 Page 20 121 Note In the case of a write access to addresses inside the address range that is 20 2 covered by the same chip select signal but that are not the addresses explicitly mentioned for the module the write access is not taken into account for the module The same principle is valid for read accesses In case of a read access to another address the module does not react System Information This section provides system information relevant to the CCU6 20 2 1 Pinning The CCU6 pin assignment for XC82x is shown in Table 20 2 Table 20 2 CCU6 Pin Functions and Selection Pin Function Desciption Selected By Capture Input Signals P1 1 CC60 0 Input signals for capture event CCU6_PISELOL ISCC60 00 P0 3 CC60 1 on channel CC60 CCU6 PISELOL ISCC60 01 P1 3 CC61 O Input signals for capture event CCU6 PISELOL ISCC61 00 PO 1 CC61_1 10n channel CC61 CCU6 PISELOL ISCC61 01 P1 5 CC62 0 Input signals for capture event CCU6_PISELOL ISCC62 00 P0 2 62 1 on channel CC62 CCU6 PISELOL ISCC62 01 Trap Input Signals P0 3 CTRAP O Input signals for MODPISEL3 CTRAPIS 00 CCU6_PISELOL ISTRP 00 P0 4 CTRAP 1 MODPISEL3 CTRAPIS 01 CCU6_PISELOL ISTRP 00 P2 3 CTRAP
407. event WDT reset and soft reset Table 7 2 shows the reset value of RSTCON register after these events RSTCON Reset Control Register 7 Reset Value 00 RMAP 0 PAGE 1 7 6 5 4 3 2 1 0 SWRQ 0 SOFTRS WDTRST WKRS rwh r rwh rwh rwh Field Bits Type Description WKRS 0 rwh Wake up Indication Bit 0 No Wake up occurred 1 Wake up has occurred This bit can only be set by hadware and clear by software WDTRST 1 rwh Watchdog Timer Reset Indication Bit 0 No watchdog reset occurred 1 Watchdog reset has occurred This bit can only be set by hadware and clear by software SOFTRS 2 rwh Soft Reset Indication Bit 0 No soft reset occurred 1 Soft reset has occurred This bit can only be set by hadware and clear by software SWRQ 7 rwh Soft Reset Request 0 No action 1 On set soft reset is requested This bit is automatically cleared by hardware The SWRQ bit is a protected bit When the Protection Scheme is activated this bit cannot be written directly 0 6 3 r Reserved Returns 0 if read should be written with 0 User s Manual 7 9 V1 0 2010 02 Cinfineon System Control Unit Table 7 2 Reset Value of Register RSTCON Reset Source Reset Value Power down Wake up Reset 0000 0001 WDT Reset 0000 0010 Soft Reset 0000 0100 Power On Reset Brown out Reset 0000 0000 User s Manual 7 10 V1 0 2010 02 Cinfineon System Control Unit 7
408. evices or systems are intended to be implanted in the human body or to support and or maintain and sustain and or protect human life If they fail it is reasonable to assume that the health of the user or other persons may be endangered Cinfineon Never stop thinking 8 Bit XC82x 8 Bit Single Chip Microcontroller User s Manual V1 0 2010 02 Microcontrollers Cinfineon XC82x User s Manual Revision History V1 0 2010 02 Previous Versions Page Subjects major changes since last revision We Listen to Your Comments Is there any information in this document that you feel is wrong unclear or missing Your feedback will help us to continuously improve the quality of this document Please send your proposal including a reference to this document to mcdocu comments infineon com gt lt User s Manual V1 0 2010 02 Cinfineon 3 4 2 1 3 4 3 3 4 4 3 4 5 3 4 5 1 3 4 5 2 3 4 5 3 3 4 5 4 Introduction 1 1 1 ACS amp 2x Feature List 2 22 2 22 XR ES 1 2 1 Pin Configuration hee done ede eee ee bed 1 3 1 Pin Definitions and Functions 1 5 1 Chip Identification Number 1 12 1 Text Conventions ig Bx Rm ROSEO ROS P 1 13 1 Reserved Undefined and Unimplemented Terminology 1 14
409. f this is the case the following switching rules apply for setting and resetting the State Bit in Compare Mode State Bit CC63ST is set to 1 e with the next T13 clock 1 after a compare match T13 is always counting up i e when the counter is incremented above the compare value e with the next T13 clock f 43 after a zero match AND a parallel compare match State Bit CC63ST is cleared to 0 e with the next T13 clock 143 after a zero match AND NO parallel compare match Compare Match Compare Match Period Value T13 Count Compare Value Zero CC63ST CCU6 05533 Figure 20 29 T13 Compare Operation User s Manual 20 75 V1 0 2010 02 CCU6 V4 0 Cinfineon Capture Compare Unit 6 CCU6 20 44 Compare Mode Output Path Figure 20 30 gives an overview on the signal path from the channel State Bit CC63ST to its output pin COUT63 As illustrated a user can determine the desired output behavior in relation to the current state of CC63ST Please refer to Section 20 3 4 3 for detailed information on the output modulation for T12 signals T13 Output Output Level State Selection Modulation Selection T12 Output Modulation State Bit CC63ST T13 Output Modulation COUT63 O COUT63PS ECT130 COUT63 CCU6_MCA05534 Figure 20 30 Channel 63 Output Path The output line COUT63 O can generate a T13 PWM at the output pin COUT63 T
410. ffect User s Manual ADC V2 1 21 85 V1 0 2010 02 Cinfineon Analog to Digital Converter Writing a 1 to a bit position in the Event Indication Clear Register ADC_EVINCR clears the corresponding event indication flag EVINFx in register ADC_EVINFR If a request source or result event is detected when the corresponding bit position is written with a 1 flag EVINFx is cleared ADC EVINCR Event Interrupt Clear Flag Register CF Reset Value 00 RMAP 0 PAGE 5 7 6 5 4 3 2 1 0 EVINC7 EVINC6 EVINC5 EVINC4 0 EVINC1 EVINCO w w w w Field Bits Type Description EVINCO 0 w Clear Interrupt Flag for Event x EVINC1 1 Og No action EVINC4 4 1 Bit EVINFR x is reset EVINC5 5 EVINC6 6 EVINC7 7 0 3 2 r Reserved Returns 0 if read should be written with 0 User s Manual 21 86 V1 0 2010 02 ADC V2 1 Cinfineon Analog Digital Converter The Channel Event Indication Flag Register CHINFR monitors the detected channel events for channels 0 7 ADC_CHINFR Channel Interrupt Flag Register Reset Value 00 RMAP 0 PAGE 5 7 6 5 4 3 2 1 0 CHINF7 CHINF6 CHINFS CHINF4 CHINF3 CHINF2 CHINF1 CHINFO rh rh rh rh rh rh rh rh Field Bits Type Description CHINFx x rh Interrupt Flag for Channel x x 0 7 This bit monitors the status of the channel interrupt x Os A channel interrupt for chann
411. fferent Trip point for each PADT can be chosen and is determined by the Subtraction Option at IRAM address 0x32 If Subtraction Option is 0x00 common subtraction m value is initialized at IRAM address 0x34 If different subtraction m values are selected Subtraction Option is programmed as the start IRAM address of these subtraction m values Common or different Oscillation window period LTS_COMPARE can be determined by users as well refer to Section 23 2 1 The details of the subroutine are listed in Table 23 13 The parameters for the function are shown also Section 23 2 2 1 Implementation details is shown Section 23 2 2 2 Table 23 13 Specifications of Find Touched Pad Subroutine Subroutine FINDTOUCHEDPAD Address DFCC Input Input Parameters at IRAM address or SFR input setting LTS GLOBCTLO TS EN 1 Enable Touch Sense function control and its respective settings LTS TSCTL PADTSW 0 User needs to disable the hardware control to use this function IRAM address 0x30 Accumulator Counter The number of samples to be accumulated to calculate the average value Values supported are 1 to 255 IRAM address 0x31 ShortCount The value to be compared with a counter value named PadDownCounter PDC to indicate a valid range to set the Result flag PDC lt ShortCount indicates valid range PDC is initialized to be OxFF at start of a detected padtouch and is decremented once at each period U
412. fill up the remaining addresses with 00 and transfer 32n data bytes Note The Block Length refers to the whole length block type data area and checksum of the following transfer block Data Block or EOT Block Since the data area is multiples of 32 bytes thus by adding block type and checksum bytes the Block Length is 32n 2 bytes After successfully receiving the Header Block the uC enters Mode 2 during which the program codes are transmitted from the host to the uC by Data Block and EOT Block which are describe as below Note No empty Data Block is allowed The Data Block 014 Data Program Codes Checksum Block Block Length 2 bytes 1 byte 1 byte Description Program Codes The program codes have a length of Block Length 2 byte where the Block Length is provided in the previous Header Block The EOT Block 02 Last_Code EOT Lenath Program Code Not Used Checksum Block 979 1 byte 1 byte 1 byte Description Last_Codelength This byte indicates the length of the program codes in this EOT Block Note If Data blocks are sent this byte should be zero If this byte is not zero additional undesired bytes will be programmed Program Codes The last program codes to be sent to the uC User s Manual 6 12 V1 0 2010 02 Cinfineon Boot Loader Not used The length is Block_Length 3 Last_Codelength and should be filled with zeros
413. fore accessing the register User s Manual 19 3 V1 0 2010 02 LEDTSCU V 1 2 1 Cinfineon LED Touch Sense Controller PMCON1 Peripheral Management Control Register 1 EF Reset Value DF RMAP 0 PAGE 1 7 6 5 4 3 2 1 0 DIS LTS DIS 0 MDU DIS T2 DIS DIS SSC DIS DIS rw rw r rw rw rw rw rw Field Bits Type Description LTS DIS 6 rw LEDTSCU Disable Request Active high 0 LEDTSCU is in normal operation 1 Request to disable the LEDTSCU default 0 5 r Reserved Returns 0 if read should be written with 0 19 2 3 Interrupt Events and Assignment Table 19 2 lists the interrupt event sources from the LEDTSCU and the corresponding event interrupt enable bit and flag bit Table 19 2 LEDTSCU Interrupt Events Event Event Interrupt Enable Bit Event Flag Bit Start of Time Slice GLOBCTL1 ITS_EN GLOBCTL1 TSF Start of Time Frame GLOBCTL1 ITF_EN GLOBCTL1 TFF Table 19 3 shows the interrupt node assignment for each LEDTSCU interrupt source Table 19 3 LEDTSCU Events Interrupt Node Control Event Interrupt Node Interrupt Node Flag Vector Enable Bit Bit Address Start of Time Slice IEN1 ECCIP3 6By Start of Time Frame IEN1 ECCIP1 5B 19 2 4 IP Interconnection The LEDTSCU has interconnection to other peripherals enabling higher level of automation without requiring software User s Ma
414. fter TRPF has become 0 again when a zero match of T13 is detected synchronization to T13 10 reserved 11g The trap state is left return to normal operation immediately after TRPF has become 0 again without any synchronization to T12 or T13 User s Manual 20 100 V1 0 2010 02 CCUG V4 0 Cinfineon XC82x Capture Compare Unit 6 CCU6 Field Bits Type Description TRPM2 2 rw Trap Mode Control Bit 2 This bit defines how the trap flag TRPF can be cleared after the trap input condition CTRAP 0 and TRPPEN 1 is no longer valid either by CTRAP 1 or by TRPPEN 0 Og Automatic Mode Bit TRPF is cleared by HW if the trap input condition is no longer valid 13 Manual Mode Bit TRPF stays 0 after the trap input condition is no longer valid It has to be cleared by SW by writing ISR RTRPF 1 0 7 3 r reserved returns 0 if read should be written with 0 TRPCTRH Trap Control Register High Reset Value 00 RMAP 0 PAGE 2 7 6 5 4 3 2 1 0 TRPPEN TRPEN13 TRPEN rw rw rw User s Manual 20 101 V1 0 2010 02 CCUG V4 0 Cinfineon XC82x Capture Compare Unit 6 CCU6 Field Bits Type Description TRPEN 5 0 Trap Enable Control Setting a bit enables the trap functionality for the following corresponding output signals TRPENO TRPCTR 8 for output CC60 TRPEN1 TRPCTR 9 for output COUT60 TRPEN2 TRPCTR 10 for output CC61 T
415. functionality 0 4 3 r Reserved Returns 0 if read should be written with 0 User s Manual 21 33 V1 0 2010 02 ADC V2 1 Cinfineon XC82x Analog to Digital Converter The queue registers 0 monitor the status of the pending request queue stage 0 ADC_QORO Queue 0 Register 0 RMAP 0 PAGE 6 7 6 Reset Value 00 4 3 2 1 0 EXTR ENSI RF V 0 REQCHNR rh rh rh rh r rh Field Bits Type Description REQCHNR 2 0 rh Request Channel Number This bit field indicates the channel number that will be or is currently requested Note Bit 2is only applicable for devices that have 8 ADC channels For channels not implemented these bits should be treated as Reserved bits of type f which returns 0 if read and should be written with rh Request Channel Number Valid This bit indicates if the data in REQCHNR RF ENSI and EXTR is valid Bit V is set when a valid entry is written to the queue input register QINRO or by an update by intermediate queue registers Og data is not valid 1g data is valid RF 5 rh Refill This bit indicates if the pending request is discarded after being executed conversion start or if it is automatically refilled in the top position of the request queue The request is discarded after conversion start 1g request is refilled in the queue after
416. g Scheme 20 70 Shadow Register Transfer 20 77 Synchronization to T12 20 72 Trap Handling 20 85 Chip identification number 1 12 Circular stack memory 4 3 Correction algorithm 4 9 Count Clock 14 9 Counter 13 1 CPU 2 1 Functional Blocks 2 1 Instruction Table 2 10 Instruction Timing 2 8 L 2 V1 0 2010 02 Cinfineon XC82x Registers 2 3 ACC 2 3 B Register 2 3 Data Pointer 2 3 PCON 2 6 PSW 2 3 Stack Pointer 2 3 D Data memory 3 2 Debug System 10 1 Functional Overview 10 5 Breakpoints 10 5 Debug Suspend Control 10 7 Monitor Program 10 6 Monitor Running 10 7 Return to User Program 10 7 Single Step 10 7 Document Acronyms 1 14 Terminology 1 14 Textual conventions 1 13 Dynamic error detection 4 9 E EEPROM emulation 4 3 Embedded voltage regulator 7 1 Low power voltage regulator 7 2 Main voltage regulator 7 2 Threshold voltage levels 7 2 Error Correction Code 4 9 External data memory 3 2 F Flash 4 1 Endurance 4 4 Erase mode 4 8 Memory address mapping 4 2 Non volatile 4 1 Operating modes 4 8 Power down mode 4 8 Program mode 4 8 Ready to read mode 4 8 User s Manual L 3 Keyword Index Sector 4 3 Flash program memory 3 1 G Gate disturb 4 6 GPIO 11 1 H Hamming code 4 9 High impedance 11 2 Idle mode 7 12 7 17 IENO 13 13 17 1 17 22 Baud rate generation 17 5 Bus arbitration 17 6 Clock synchronization 17 6 Master receive 17 10 Master transmit 17 7 Operating modes 17 7 Regis
417. gger input REQTR when at least one V bit is set in register QORO or QBURO Og external trigger is disabled 1g external trigger is enabled CLRV 4 w Clear V Bits 0s No action 1g The bit V in register or QBURO is reset If QBURO V 1 then QBURO V is reset If QBURO V 0 then QORO V is reset FLUSH 5 w Flush Queue Og No action 1g All bits V in the queue registers and bit EV are reset The queue contains no more valid entry TREV 6 w Trigger Event Og No action 1g Atrigger event is generated by software If the source waits for a trigger event a conversion request is started User s Manual 21 29 V1 0 2010 02 ADC V2 1 Cinfineon XC82x Analog to Digital Converter Field Bits Type Description CEV 7 w Clear Event Bit Og action 1g Bit EV is cleared 0 1 3 r Reserved Returns 0 if read should be written with 0 Note Before SW modifies the queue content by QMR CLRV or QMR FLUSH all HW actions related to this queue have to be finished Therefore the arbitration slot has to be disabled and SW has to wait for at least two arbitration rounds to be sure that this request source can no longer be an arbitration winner Then it has to check ADC_GLOBCTR BUSY to be sure that a conversion triggered by this request source is no longer running Then SW can read QBURx and QORx and can start modification of the queue content User s Manual ADC V2 1
418. gister 2 2 Type rwh rwh r TW rwh rw rw Ciy T2_T2MOD Reset 004 Field 2 T2RH EDGE T2PRE DCEN Timer 2 Mode Register GS EN SEL Type TW rw rw rw rw rw rw rw C2u T2 RC2L Reset 004 Bit Field RC2 Timer 2 Reload Capture Register Low Type own C3y T2_RC2H Reset 004 Bit Field RC2 Timer 2 Reload Capture Register High Type TY C4y T2 T2L Reset 004 Bit Field THL2 Timer 2 Register Low Type rwh C5u T2 T2H Reset 004 Bit Field THL2 Timer 2 Register High Type rwh 2 2 1 Reset 034 Bit Field 0 2 2 Timer 2 Control Register 1 N Type r rw rw 3 4 5 9 CCU6 Registers The CCU6 SFRs can be accessed in the standard memory area RMAP 0 Table 3 9 CCUG Register Overview Addr Register Name Bit 7 6 5 4 3 2 1 0 IRMAP 0 CCU6_PAGE Reset 004 Bit Field OP STNR 0 Page Register Type w w r rw RMAP 0 PAGE 0 DAY CCU6_CC63SRL Reset 004 Bit Field CC63SL Capture Compare Shadow Register for Channel CC63 Low Type mw CCU6_CC63SRH Reset 004 Bit Field CC63SH Capture Compare Shadow Register for Channel CC63 High Type rw PCy CCU6_TCTR4L Reset 004 BitField T12 T12 0 DT T12 T12R T12R Timer Control Register 4 Low STD STR RES RES S R Type w w r w w w w User s Manual 3 26 V1 0 2010 02 Memory Organization V 0 1 Infineon XC82x Memory Organization
419. gnal activated provided the respective suspend bit WDTSUSP in SFR MODSUSP are set See Module Suspend Control section User s Manual WDT V1 0 8 6 V1 0 2010 02 Cinfineon 2 Watchdog Timer 8 4 Registers Description Five SFRs control the operations of the WDT They can be accessed from the mapped SFR area Table 8 3 lists the addresses of these SFRs Table 8 3 Register Map Address Page Register F6 1 WDTCON F3 4 WDTREL 4 WDTWINB F5 4 WDTL F6 4 WDTH 8 4 1 Watchdog Timer Registers The Watchdog Timer Current Count Value is contained in the Watchdog Timer Register WDTH and WDTL which are non bitaddressable read only register The operation of the WDT is controlled by its bitaddressable WDT Control Register WDTCON This register also selects the input clock prescaling factor The register WDTREL specifies the reload value for the high byte of the timer WDTWINB specifies Watchdog Window Boundary count value WDTREL Watchdog Timer Reload Register Reset Value 00 RMAP 0 PAGE 4 7 6 5 4 3 2 1 0 WDTREL rw Field Bits Description WDTREL 7 0 rw Watchdog Timer Reload Value for the high byte of WDT User s Manual 8 7 V1 0 2010 02 WDT V1 0 Cinfineon Watchdog Timer WDTCON Watchdog Timer Control Register F6 Reset Value 00 RMAP 0 PAGE 1 7 6 5 4 3 2 1 0 0 WINBEN WDTPR 0 WDTEN WDTRS 0 rw rh r rw rwh r
420. gram The output path is based on signals that are defined as active or passive The terms active and passive are not related to output levels but to internal actions This mainly applies for the modulation where T12 and T13 signals are combined with the multi channel signals and the trap function The Output level Selection allows the user to define the output level at the output pin for the passive state inverted level for the active state It is recommended to configure this block in a way that an external power switch is switched off while the CCU6 delivers an output signal in the passive state 20 3 4 1 Dead Time Generation The generation of complementary signals for the high side and the low side switches of one power inverter phase is based on the same compare channel For example if the high side switch should be active while the T12 counter value is above the compare value State Bit 1 then the low side switch should be active while the counter value is below the compare value State Bit 0 In most cases the switching behavior of the connected power switches is not symmetrical concerning the switch on and switch off times A general problem arises if the time for switch on is smaller than the time for switch off of the power device In this case a short circuit can occur in the inverter bridge leg which may damage the complete system In order to solve this problem by HW this capture compare unit User s Manual 20 32 V1 0
421. ground program and erase operations for CPU load minimization e Support for aborting erase operation e 32 byte minimum program width e sector minimum erase width e 1 byte read access e 1or3x 1 period read access time depending on zero or one wait state Flash is delivered in erased state read all zeros User s Manual 4 1 V1 0 2010 02 Flash Memory V 0 1 Cinfineon nears Flash Memory 4 1 Flash Memory Address Mapping The program memory map for the two Flash sizes is shown in Figure 4 1 B000 Flash Bank 0 4 Kbytes A000 10004 Flash Bank 0 4 Kbytes 00004 4 Kbytes Figure 4 1 Flash Memory For the XC82x only a single 4 Kbyte Flash bank Bank 0 is available The Flash bank is mapped to two program memory address spaces 0000 OFFF and A000 AFFF The double mapping of the Flash banks is intended to facilitate software coding As a general guideline the lower address spaces 0000 OFFF should be used for Flash contents that are intended to be used as program code Whereas the higher address space A0004 AFFF should be used for Flash contents that are intended to be used as data 4 2 Flash Bank Sectorization The XC82x Flash devices consist of one 4 Kbyte Flash bank with the sectorization shown in Figure 4 2 Each Flash bank can be used for code and data storage User s Manual 4 2 V1 0 2010 02 Flash Memory V 0 1 Cinfineon nears Flash Memory
422. h of compare channel CC61 while counting down CM_61 and CDIR 1 User s Manual CCU6 V4 0 20 92 V1 0 2010 02 Cinfineon Capture Compare Unit 6 CCU6 20 7 2 Hall Pattern Compare Logic Figure 20 37 gives an overview on the double register structure and the pattern compare logic Software writes the next modulation pattern MCMPS and the corresponding current CURHS and expected EXPHS Hall patterns into the shadow register MCMOUTS Register MCMOUT holds the actually used values CURH and EXPH The modulation pattern MCMP is provided to the T12 Output Modulation block The current CURH and expected EXPH Hall patterns are compared to the sampled Hall sensor inputs visible in register CMPSTATL CMPSTATH Sampling of the inputs and the evaluation of the comparator outputs is triggered by the evaluation signal HCRDY Hall Compare Ready that is detailed in the next section Multi Channel Mode Logic SW Write SW Write SW Write Hall Pattem clear Evaluation T12 Output Modulation CM CHE CM WHE Pattern Compare Hall Compare Logic CCU6 05536 Figure 20 37 Hall Pattern Compare Logic If the sampled Hall pattern matches the value programmed in CURH the detected transition was a spike no Hall event and no further actions are necessary If the sampled Hall pattern matches the value programmed in EXPH the detected t
423. handling trigger inputs RECT REQTRx 7 0 trigger amp gating unit wait for request trigger source event request requ est source arbiter status sequential backup stage request source ADC_seq_reqsrc Figure 21 8 Queued Request Source A sequence is defined by entering conversion requests into the queue input register ADC_QINRO Each entry selects the channel to be converted and can enable an external trigger generation of an interrupt and an automatic refill i e keep this entry in the queue after conversion The entries are stored in the queue buffer stages The content of stage 0 ADC QORO selects the channel to be converted next When the requested conversion is started the contents of this queue stage is invalidated and copied to the backup stage Then the next queue entry can be handled if available Note The contents of the queue stages cannot be modified directly but only by writing to the queue input or by flushing the queue If all queue entries have automatic refill selected the defined conversion sequence can be repeated without re programming Properties of the Queued Request Source The ADC kernels of the XC82x provide one queued request source with buffer size Queued request source 0 provides 4 buffer stages and can handle sequences of up to 4 input channel entries It supports short application specific conversion sequences especially for
424. harge during the sample phase This structure allows significantly shorter sample phase than without a blocking capacitor because the low pass time constant defining the sample time is mainly given by the values of Ran and Can Additionally the capacitor C a is automatically precharged to a voltage of approximately the half of the standard reference voltage Varer to minimize the average difference between Vain and at the beginning of a sample phase Due to varying parameters and parasitic effects the precharge voltage of is typically smaller than Varer 2 On the other hand the charge redistribution between Cry and Can leads to a voltage change of V anx during the sample phase In order to keep this voltage change lower than 1 LSB it is recommended to use an external blocking capacitor in the range of at least 2 x Cain The resulting low pass filter of Rexr and Cex should be dimensioned a way to allow Vainx to follow Vs between two sample phases of the same analog input channel Please note that especially at high temperatures the analog input structure of an ADC can lead to a leakage current and introduces an error due to a voltage drop over Reyr The ADC input leakage current increases if the input voltage level is close to the analog supply ground Vss or to the analog power supply Vppp It is recommended to use operating range for the input voltage between approximately 3 and 97 of Vppp to reduce the inpu
425. he signal CC63 can be used to modulate T12 related output signals with a T13 PWM In order to decouple COUT63 from the internal modulation the compare state leading to an active signal can be selected independently by bits T13IM and COUT63PS The last block of the data path is the Output Modulation block Here the modulation source T13 and the trap functionality are combined and control the actual level of the output pin COUT63 see Figure 20 31 The T13 related compare signal COUT63 O delivered by the T13 state selection with the enable bit MODCTRH ECT13O The trap state TRPS with an individual enable bit TRPCTRH TRPEN13 If the modulation input signal COUT63 is enabled ECT130 1 and is at passive state the modulated is also in passive state If the modulation input is not enabled the output is in passive state If the Trap State is active TRPS 1 then the output enabled for the trap signal by 13 1 is set to the passive state The output of the modulation control block is connected to a level select block It offers the option to determine the actual output level of a pin depending on the state of the output line decoupling of active passive state and output polarity as specified by the Passive State Select bit PSLR PSL63 If the modulated output signal is in the passive User s Manual 20 76 V1 0 2010 02 CCU6 V4 0 Cinfineon Capture Compare Unit 6 CCU6 state the level specified directl
426. he ADDR register contains the bit to enable the general call address option and the device address of the IIC in 7 bit addressing mode For 10 bit addressing part of the address bits is located in ADDRX register ADDR Slave Address Register DA Reset Value 00 RMAP 0 PAGE X 7 6 5 4 3 2 1 0 SLA GCE rw rw Field Bits Type Description GCE 0 rw General Call Address Enable Og General call address option is disabled 1g General call address option is enabled SLA 7 1 rw Slave Address For 7 bit addressing SLA contains the 7 bit address of the IIC when in slave mode For 10 bit addressing the uppermost five bits SLA 6 2 are fixed at 11110 while SLA 1 0 contains the uppermost two bits of the 10 bit slave address The remaining lower 8 bits are located in ADDRX register User s Manual 17 16 V1 0 2010 02 V1 1 Cinfineon Inter IC Bus The ADDRX register contains the lower 8 bit slave address of the device in 10 bit addressing mode ADDRX Extended Slave Address Register DE Reset Value 00 RMAP 0 PAGE X 7 6 5 4 3 2 1 0 SLAX rw Field Bits Type Description SLAX 7 0 rw Extended Slave Address For 10 bit addressing SLAX contains the lower 8 bit address of the IIC when in slave mode 17 9 2 Data Register The DATA register contains the data byte or slave address to be transmitted or the data byte that has ju
427. he active state the corresponding output pin drives the active state level that is the inverted passive state level The passive state level permits to adapt the driven output levels to the driver polarity inverted not inverted of the connected power stage The bits in this register have shadow bit fields to permit a concurrent update of all PWM related parameters bit field PSL is updated with T12_ST whereas PSL63 is updated with T13 ST The actually used values can be read attribute rh whereas the shadow bits can only be written attribute w PSLR Passive State Level Register Reset Value 00 RMAP 0 PAGE 2 7 6 5 4 3 2 1 0 PSL63 0 PSL rwh r rwh Field Bits Type Description PSL 5 0 rwh Compare Outputs Passive State Level These bits define the passive level driven by the module outputs during the passive state PSLO PSLR O for output CC60 PSL1 PSLR 1 for output COUT60 PSL2 PSLR 2 for output CC61 PSL3 PSLR 3 for output COUT61 PSL4 PSLR 4 for output CC62 PSL5 PSLR 5 for output COUT62 Og passive level is 0 1g The passive level is 1 PSL63 7 rwh Passive State Level of Output COUT63 This bit defines the passive level driven by the module output COUT63 during the passive state Oz passive level is 0 1g passive level is 1 0 6 r reserved returns 0 if read should be written with 0 User s Manual 20 103 V1 0
428. he calling of the erase and program user routines can be called from XRAM or Flash Table 22 2 shows the description of how to use and call these routines The first type of routine supports non background erasing BR FLASH ERASE will wait until erasing is done before allowing user program to continue with its execution This routine will be aborted if the FNMIVDDP FNMIVDD or FNMIPLL flag is set while they are being polled for error This type of routine is necessary for users who need to erase the Flash bank where the user code is in execution especially when there is only one Flash Bank The Flash cannot be in both erase mode and read mode at the same time It is also useful for users who wish to erase the Flash Bank where the interrupt vectors are defined as interrupts cannot be handled when the Flash is in erase mode as the interrupt handler cannot be fetched For Type 1 erase routine Boot ROM will control the code the FNMIFLASH flag is cleared automatically and therefore need not be handled by users User s Manual 22 9 V1 0 2010 02 BootROM User Routines V1 1 Cinfineon Boot ROM User Routines Note As program will return to user code after erasing is completed customer should take care that they do not erase their user program code as well Note When invalid No input s is provided for this routine C flag will be set and routine will be exited Nothing else will be done Table 22 11 Specifications of FLASH_ERASE subrou
429. he load event occurs Note Writes to register CRPR1 also update CRCR 1 and generate a load event ADC CRCR1 Conversion Request Control Register 1 CA Reset Value 00 RMAP 0 PAGE 6 7 6 5 4 3 2 1 0 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CHO rwh rwh rwh rwh rwh rwh rwh rwh Field Bits Type Description CHx X rwh Channel Bit x x 0 7 Each bit corresponds to one analog channel the channel number x is defined by the bit position in the register The corresponding bit x in the conversion request pending register will be overwritten by this bit when the load event occurs Og The analog channel x will not be requested for conversion by the parallel request source 1g analog channel x will be requested for conversion by the parallel request source Note Bits 4 7 are only applicable for devices that have 8 ADC channels For channels not implemented these bits should be treated as Reserved bits of type r which returns 0 if read and should be written with O User s Manual 21 23 V1 0 2010 02 ADC V2 1 Cinfineon Analog to Digital Converter The Conversion Request Pending Register indicates which channels of request source 1 channel scan source are requesting a conversion Its bits are updated from pending register CRCR1 when the load event occurs Note Writes to register CRPR1 also update CRCR 1 and generate a load event ADC_CRPR1 Conversion Request Pending Reg
430. he outer loops show a better behavior if they are synchronized to the inner loops Therefore the hysteresis like mode can be used that combines timer related switching with a hysteresis controller behavior For example in this mode an output can be switched on according to a fixed time base but it is switched off as soon as a falling edge is detected at input CCPOSx This mode can also be used for standard PWM with overcurrent protection As long as there is no low level signal at pin CCPOSx the output signals are generated in the normal manner as described in the previous sections Only if input CCPOSx shows a low level e g due to the detection of overcurrent the outputs are shut off to avoid harmful stress to the system User s Manual 20 31 V1 0 2010 02 CCU6 V4 0 Cinfineon Capture Compare Unit 6 CCU6 20 3 4 Compare Mode Output Path Figure 20 15 gives an overview on the signal path from a channel State Bit to its output pin in its simplest form As illustrated a user has a variety of controls to determine the desired output signal switching behavior in relation to the current state of the State Bit CC6xST Please refer to Section 20 3 4 3 for details on the output modulation T12 Dead Time T12 Output Level State Bits Generation State Selection Selection CC6x O CC6x CC61ST Dead Time CC62ST CC6xST COUT6x_O CCU6_MCA05519 Figure 20 15 Compare Mode Simplified Output Path Dia
431. he prefix CCU6x_ has to be added to the register names in this table to identify the registers of different CCU6 modules that are implemented In this naming convention x indicates the module number Table 20 1 shows all registers required for programming of a CCU6 module It summarizes the CCU6 kernel registers and defines the offset and the reset values 8 bit short addresses are not available for this module T12 related Cap Com Interrupt Status General Registers Control Registers Control Registers Registers Modulation Control Registers T13 related Registers CC63RL CC63RH CC63SRL CC63SRH 8 Bit_CCU6_regs Figure 20 2 CCU6 Registers User s Manual 20 4 V1 0 2010 02 CCU6 V4 0 Cinfineon XC82x Capture Compare Unit 6 CCU6 Table 20 1 CCU6 Module Register Summary Short Name Description Offset Reset See Value General Registers PISELOL Port Input Select Register Low 9E 00 Page 20 127 PISELOH Port Input Select Register High OF 00 Page 20 128 PISEL2 Port Input Select Register 2 A4y 00 Page 20 129 Timer T12 related Registers T12L Timer 12 Counter Register Low FA 00 Page 20 43 T12H Timer 12 Counter Register High FB 00 Page 20 43 T12PRL Timer 12 Period Register Low 9C 00 Page 20 44 T12PRH Timer 12 Period Register High 9D 00 Page 20 44 T12DTCL Dead Time Control Register for Timer A44
432. he source of the Break and relevant information is to be forwarded to the Debugger concerning the Break Event source IRAM read write 10 4 2 Processing External Breaks Possible external break requests are generated and processed as follows 1 arequest comes from one of the possible source s a Debugger request via SPD a dedicated command has been sent with MMODE_r 1 RRF_r 0 and data Byte A5 while at the same time MMCR2 MMODE 0 and MMCR2 ALTDI 0 2 the core ends executing current instruction the core enters Debug Mode Note External Breaks are not possible inside a NMI servicing routine For more information refer to Section 10 7 10 4 3 Processing Software Breakpoints Software breakpoints are of Break Before Make type therefore the instruction at the breakpoint is executed only after the proper debug action is taken Upon fetching a TRAP instruction Software Breakpoint is effected Due to this it goes to Debug Mode Attention The user software must not clear the TRAP_EN bit in EO register The OCDS reacts in two ways Break eventis recognized for Entering Monitor Mode the Software Break is ignored This happens when the above condition is not satisfied i e basically when the Software Breakpoints are disabled User s Manual 10 10 V1 0 2010 02 OCDS V 2 7 1 Cinfineon Debug System Upon matching a not enabled Software Breakpoint the user software execution is suppressed for 4 clock cycles afte
433. hen 23 10 TOTAL_TSCTRL H x x 2 lt LOWTRIPL H x A pad not touched or a padtouch being removed lifted are identified when 23 11 TOTAL_TSCTRL H x x 2 gt LOWTRIPL H x When padtouch is identified a counter PDC is initialized to OxFF and will start decrementing till the padtouch is being removed lifted At this instant the PDC is compared with ShortCount input to determine is the padtouch is a valid or invalid touch Internal states Because of the time multiplexed nature of the touch sense functionality the function can be in a number of states when entered and the states can be modified inside this function and outside by the user application Here is a state diagram that shows the various states and how to transit from one state to the other There are 5 states in total Idle State Pad Touched State Pad Released State Error State and Result State User s Manual 23 31 V1 0 2010 02 ROM Library V0 5 Cinfineon ROM Library total TSCTR lt LowTrip touched FoR error flag cleared byuser total TSCTR gt LowTrip PAD released FRE PDC lt SC result flag cleared by user PDC gt SC Figure 23 8 State diagram Actions on entering a state IDLE On Enter check if Total TSCTRL H lt LowTripL H point for this pad turn On Exit If yes set the corresponding pad flag start the counter PDC OxFF Pad Touched On Enter
434. his bit indicates that a timer T12 one match while counting down T12 OM and CDIR 1 has been detected Og event has not yet been detected 1g event has been detected T12PM 7 rh Timer T12 Period Match Flag This bit indicates that a timer T12 period match while counting up T12 PM and CDIR 0 has been detected Og The event has not yet been detected 1g event has been detected ISH Interrupt Status Register High 9D Reset Value 00 RMAP 0 PAGE 3 7 6 5 4 3 2 1 0 STR IDLE WHE CHE TRPS TRPF T13PM T13CM rh rh rh rh rh rh rh rh Field Bits Type Description T13CM 0 rh Timer T13 Compare Match Flag This bit indicates that a timer T13 compare match CM 63 has been detected Og event has not yet been detected 1g event has been detected User s Manual CCU6 V4 0 20 113 V1 0 2010 02 Cinfineon XC82x Capture Compare Unit 6 CCU6 Field Bits Type Description T13PM rh Timer T13 Period Match Flag This bit indicates that a timer T13 period match T13 PM has been detected Og event has not yet been detected 1g event has been detected TRPF rh Trap Flag This bit indicates if a trap condition input 0 or by SW is has been detected If TRM2 0 it becomes cleared automatically if CTRAP 1 or TRPPEN 0 whereas if TRM2 1 it has to be cleared by writing RTRPF 1 Og trap condition has not been detect
435. hould be cleared to 0 User s Manual 6 13 V1 0 2010 02 Cinfineon Boot Loader 6 2 2 7 Mode6 Program 4 bytes of USER ID Mode 6 is used to program User indentification USER_ID 4 bytes The Header block for this working mode has the following structure The Header Block Data Area 00 06 Header Mode 6 USER ID USER ID USER ID USER ID NotUsed Checksum Block 3 2 1 0 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte Mode Data Description User ID These 4 bytes is given by user as USER for BMI values and initialization of settings Not used This byte is not used and will be ignored in Mode 6 After programming the USER ID and sending back the acknowledge response to the Host to indicate successful operation has executed a software reset will be triggered and the programmed boot up mode will be entered Note This Mode should be handled and executed with care It should be executed last User should program their Flash code first program XRAM code if needed and finally program USER Note There is no erasing option for USER ID To erase the USER ID simply write 0x00 to the 4 bytes USER 6 228 ModeA Get 4 bytes Information Mode A is used to get 4 bytes data determined by the Option byte in the header block The header block for this working mode has the following structure The Header Block Data Area 00 0 Header
436. ibes how to enable select the particular LED or touch sense pin function for XC82x Table 19 1 82 Pin Functions and Selection Pin Function Desciption Selected By PO 0 TSINO LINEO Touch sense input 0 LED line 0 PO ALTSELO PO 1 PO_ALTSEL1 P0 0 PO 1 TSIN1 LINE1 Touch sense input 1 LED line 1 PO ALTSELO P1 18 PO ALTSEL1 P1 0 P0 2 TSIN2 LINE2 Touch sense input 2 LED line 2 PO ALTSELO P2 1 PO ALTSEL1 P2 0 P0 3 TSIN3 LINE3 Touch sense input 3 LED line 3 PO_ALTSELO P3 1 PO ALTSEL1 P3 0g P0 4 TSIN4 LINE4 Touch sense input 4 LED line 4 PO_ALTSELO P4 1 PO_ALTSEL1 P4 0 PO_ALTSEL2 P4 0 P0 5 TSINS LINES Touch sense input 5 LED line 5 PO_ALTSELO P5 1 PO_ALTSEL1 P5 0 PO_ALTSEL2 P5 0 P0 6 TSIN6 LINE6 Touch sense input 6 LED line 6 PO_ALTSELO P6 1 PO_ALTSEL1 P6 0 PO_ALTSEL2 P6 0 P1 0 COLO O LED column 0 P1 ALTSELO PO 1g P1 ALTSEL1 PO 0g P0 4 1 LED column 0 PO ALTSELO PA 1g PO ALTSEL1 P4 0 PO ALTSEL2 PA 1g P1 1 COL1 O LED column 1 P1 ALTSELO P1 7 1g P1 ALTSEL1 P1 0g P0 5 COL1 1 LED column 1 PO ALTSELO P5 1 PO ALTSEL1 P5 0 PO ALTSEL2 P5 1g User s Manual LEDTSCU V 1 2 1 19 2 V1 0 2010 02 Cinfineon LED Touch Sense Controller Table 19 1 82 Pin Functions and Selection Pin Function Descipti
437. in Control Register 80 Reset Value 7F RMAP 0 PAGE 3 7 6 5 4 3 2 1 0 0 P6 P5 P4 P3 P2 P1 r rw rw rw rw rw rw rw Field Bits Type Description Pn n rw Port 0 Pin n Open Drain Mode 0 6 0 Normal Mode output is actively driven for 0 and 1 state 1 Open Drain Mode output is actively driven only for 0 state default 0 7 r Reserved Returns 0 if read should be written with 0 PO PUDSEL Port 0 Pull Up Pull Down Select Register 80 Reset Value 6F RMAP 0 PAGE 1 7 6 5 4 3 2 1 0 0 P6 P5 P4 P3 P2 P1 r rw rw rw rw rw rw rw Field Bits Type Description Pn n rw Pull Up Pull Down Select Port 0 Bit n 0 6 0 Pull down device is selected 1 Pull up device is selected default 0 7 r Reserved Returns 0 if read should be written with 0 User s Manual 11 18 V1 0 2010 02 Cinfineon XC82x PO PUDEN Port 0 Pull Up Pull Down Enable Register 86 RMAP 0 PAGE 1 Parallel Ports Reset Value 50 7 6 5 4 3 2 1 0 0 P6 P5 P4 P3 P2 P1 r rw rw rw rw rw rw rw Field Bits Type Description Pn n rw Pull Up Pull Down Enable at Port 0 Bit n n20 6 0 Pull up or Pull down device is disabled 1 Pull up or Pull down device is enabled 0 7 r Reserved Returns 0 if read should be written with O Note 0 4 has a default pull down device enabled which will be disabled by firmware in the startup cod
438. in a valid Flash WL address and all NMI flags in SFR NMISR must be 0 Otherwise PSW CY bit will be set and no programming will occur Two types of Flash program subroutines are provided in the Boot ROM to program the Flash e Non background Flash Program subroutine see Section 4 7 1 1 Background Flash Program subroutine see Section 4 7 1 2 4 7 1 1 Non background Flash Program Subroutine The first type of subroutine Non background Flash Program waits until Flash programming is completed before allowing the user code to continue with its execution This type of routine can be used to program the Flash bank where the user code is in execution The Flash cannot be in both program mode and read mode at the same time It can also be used for programming the Flash bank where the interrupt vectors are defined as interrupts cannot be handled when the Flash is in program mode For this subroutine the FNMIFLASH flag in SFR NMISR is cleared automatically and therefore need not be handled by the user 4 7 1 2 Background Flash Program Subroutine The second type of subroutine Background Flash Program allows the user program code to continue execution from where it last stopped until the Flash NMI event is generated The FNMIFLASH flag is set and if enabled via bit NMIFLASH in SFR NMICON an NMI to the CPU will be triggered to enter the Flash NMI service routine At this point the Flash bank is in ready to read mode i e programming is d
439. ine SRx becomes activated each time the related request Source event is detected and enabled by QORx ENSI or QBURx ENSI respectively The request source events and the result events share the same registers The request source event is located at the bit position in register ADC_EVINFR Event 0 Request source event of queued source 0 in arbitration slot 0 requestsource request source event event indication flag interrupt enable EVINFR QORO EVINFO ENSI conversion finished triggered by request source request source event to SRO ADC seq source int Figure 21 9 Interrupt Generation of a Queued Request Source User s Manual 21 28 V1 0 2010 02 ADC V2 1 Cinfineon Analog to Digital Converter The Queue Mode Register configures the operating mode of a queued request source ADC QMRO Queue Mode Register CD Reset Value 00 RMAP 0 PAGE 6 7 6 5 4 3 2 1 0 CEV TREV FLUSH CLRV 0 ENTR 0 ENGT fi rw r rw Field Bits Type Description ENGT 0 rw Enable Gate This bit enables the gating functionality for the request source Og The gating line is permanently 0 The source is Switched off 1g The gating line is permanently 1 The source is Switched on ENTR 2 rw Enable External Trigger This bit enables the external trigger possibility If enabled bit EV is set if a rising edge is detected at the external tri
440. ined area of values limit checking In addition to the general channel control the ADC kernel supports a mechanism named alias feature see Section 21 8 4 to redirect a conversion request to another channel number 21 8 1 Reference Selection The conversion result of the ADC is always reference to a reference voltage The maximum digital result value full scale is obtained if the analog input voltage equals the reference voltage In order to support more than one measurement range with full scale digital representation the user can select between three conversion modes which are Single ended measurement with ADC reference connected internally to Vppp and Vssp See Figure 21 12 Differential like measurement wth ADC reference connected to internal 1 2V voltage reference and ground reference taken from CHO See Figure 21 13 Single ended measurement with ADC reference connected to internal 1 2V voltage reference and Vggp See Figure 21 14 In single ended ADC conversion with reference to Vddp and Vssp voltage the ADC reference voltage is internally connected to Vddp and Vssp voltage See Figure 21 12 User s Manual 21 45 V1 0 2010 02 ADC V2 1 Cinfineon Analog to Digital Converter ADC kernel Vdd va_ref va_gnd Vssp result AD handling converter request conversion control control Interrupt generation Figure 21 12 Single ended measurement with Vddp Vssp AIN CHO AIN CH1
441. ineon System Control Unit CPU is activated provided NMI is enabled NMICON NMIVDDC The prewarning detection is disabled by default via bit VDDCPW in SDCON register This is necessary especially in the reduced voltage condition This bit has to be set to 1 to enable the prewarning detection If Vppc is below a nominal voltage of 2 3 V the brownout reset will be activated putting the microcontroller into a reset state In power down mode brownout reset happens when is below 1 5 V For Vppp there is a nominal prewarning level of 3 6 V and a nominal brownout reset threshold of 2 9 V When Vppp is below a nominal voltage of 3 6 V the Vppp NMI flag NMISR FNMIVDDP is set and an NMI request to the CPU is activated provided Vppp NMI is enabled NMICON NMIVDDP If Vppp is below a nominal voltage of 2 9 V the brownout reset will be activated putting the microcontroller into a reset state The detection of these 2 levels could be disabled via bits VDDPPW and VDDPBOA in SDCON register in active mode especially in the reduced voltage condition These 2 detections are automatically shut down in power down mode In power down mode brownout reset happens when Vppp is below 3 6 V if bit VDDPBOPD is set to 1 Besides the various brownout threshold levels for and EVR enters into the reset mode when is below 2 4 V It could happened if the Vppp brownout detection in active mode or power down mode is disable
442. ineon neers High Speed Synchronous Serial Interface SSC TBL Transmitter Buffer Register Low Reset Value 00 RMAP 0 PAGE X 7 6 5 4 3 2 1 0 TB_VALUE rw Field Bit Type Description TB_VALUE 7 0 rw Transmit Data Register Value TB_VALUE is the data value to be transmitted Unselected bits of TB are ignored during transmission 18 5 4 Receiver Buffer Register The SSC receiver buffer register RB contains the receive data value SSC_RBL Receiver Buffer Register Low AD Reset Value 00 RMAP 0 PAGE X 7 6 5 4 3 2 1 0 RB_VALUE rh Field Bit Type Description RB_VALUE 7 0 rh Receive Data Register Value RB contains the received data value RB_VALUE Unselected bits of RB will be not valid and should be ignored User s Manual 18 27 V1 0 2010 02 SSC V1 4 Cinfineon LED and Touch Sense Controller 19 LED and Touch Sense Controller This chapter describes the LEDTSCU 19 1 Overview The LED and Touch sense control unit LEDTSCU provides for up to eight line pins and up to eight column pins time multiplexed control for LED driving and touchpad sensing on single pin LEDTSCU provides optimized HW control for column enabling and function selection Software handling is required for line enabling per column time slice Features For the LED driving function LEDTSCU provides features Selection of up to 8 LED columns Up to 7 LED c
443. infineon ROM Library 23 2 2 1 Outputs of Function This function checks if the current counter value is below the trip point and sets a flag in a variable called PadFlag Status Once a PadFlag Status has been set a software implemented Pad Down Counter PDC starts to decrement each time the function is called provided the PadFlag is set When PadFlag Status is set it means the particular pad is being assessed and result is either valid touch short touch invalid or long touch error Once the pad down counter value reaches above the trip point the PDC is checked and compared with a pre determined threshold value ShortCount If above this threshold the PadFlag is simply cleared and no further action takes place This is regarded as a invalid key press If the PDC is below the threshold but gt 0 the PadFlag Status if cleared and the corresponding bit in a variable called PadResult Status is set This means that the padtouch is being recognized But once the PDC reaches 0 the PadFlag Status is cleared and the corresponding bit in a variable called PadError Status is set This means that there is an error in detection as the press of the pad is too long Because all this happens over a series of Time Slices the application needs to check that PadFlags is 0 before any PadError or PadResult is valid A non zero PadFlag variable indicates that pads are still being processed PadFlag F Pad Flag Status IRAM address 0x2F Reset
444. ing interrupt is enabled or not When enabled the event including setting of CLK PS from 0 activates the corresponding interrupt request from the kernel User s Manual LEDTSCU V 1 2 1 19 19 V1 0 2010 02 Cinfineon LED Touch Sense Controller 19 11 Registers Description The LEDTSCU Special Function Registers are accessed from the standard non mapped SFR area Table 19 7 lists the SFRs and corresponding address Table 19 7 Register Map Address Register 97 LTS GLOBCTLO D4 LTS_COMPARE D5 LTS_LDLINE D64 LTS_LDTSCTL D74 LTS_TSCTL D84 LTS_GLOBCTL1 D9 LTS_TSVAL User s Manual 19 20 V1 0 2010 02 LEDTSCU V 1 2 1 Cinfineon 19 11 1 XC82x LED and Touch Sense Controller Global Control and Status There are three registers for global control and status LTS_GLOBCTLO Global Control Register 0 974 Reset Value 00 RMAP 0 PAGE X 7 6 5 4 3 2 1 0 LD_EN TS_EN CLK_PS rw rw rw Field Bits Type Description CLK_PS 5 0 rw LEDTS Counter Clock Pre Scale Factor The input clock FPCLK or SPCLK is prescaled according to setting 05 1 Divide by 1 np Divide by n 63p Divide by 63 This bit can only be set to any other value from 0 provided at least one of touch sense or LED function is enabled The LEDTS counter starts running on the input clock from reset reload value based on enabled function s and NR
445. intentional interrupt generation User s Manual 9 20 V1 0 2010 02 Interrupt System V 2 3 3 Cinfineon XC82x EXICONO External Interrupt Control Register 0 RMAP 0 PAGE 0 Interrupt System Reset Value F0 7 6 5 3 2 1 0 EXINT3 EXINT2 EXINT1 EXINTO rw rw rw rw Field Bits Type Description EXINTO 1 0 rw External Interrupt 0 Trigger Select 00 Interrupt on falling edge 01 Interrupt on rising edge 10 Interrupt on both rising and falling edge 11 Bypass the edge detection in SCU The input signal directly feeds to the core EXINT1 3 2 rw External Interrupt 1 Trigger Select 00 Interrupt on falling edge 01 Interrupt on rising edge 10 Interrupt on both rising and falling edge 11 Bypass the edge detection in SCU The input signal directly feeds to the core EXINT2 5 4 rw External Interrupt 2 Trigger Select 00 Interrupt on falling edge 01 Interrupt on rising edge 10 Interrupt on both rising and falling edge 11 External interrupt 2 is disabled EXINT3 7 6 rw External Interrupt 3 Trigger Select 00 Interrupt on falling edge 01 Interrupt on rising edge 10 Interrupt on both rising and falling edge 11 External interrupt 3 is disabled User s Manual Interrupt System V 2 3 3 9 21 V1 0 2010 02 Cinfineon EXICON1 XC82x External Interrupt Control Register 1 F4 RMAP 0 PAGE 0 Interrupt System Reset Value 3F
446. interrupt sources Timer 0 Timer 1 external interrupt 0 and external interrupt 1 each have a dedicated interrupt node will have their respective interrupt status flags TFO TF1 IEO and IE1 in register TCON cleared by the core once their corresponding pending interrupt request is serviced In the case that an interrupt node is disabled e g software polling is used its interrupt status flag must be cleared by software since the core will not be interrupted and therefore the interrupt acknowledge is not generated For the UART which has its dedicated interrupt node interrupt status flags RI and TI in register SCON will not be cleared by the core even when its pending interrupt request is serviced The UART interrupt status flags and hence the pending interrupt request can only be cleared by software 9 2 2 Interrupt Structure 2 This structure applies to the Timer 2 LIN external interrupts 2 to 6 ADC SSC IIC RTC LEDTSCU CCU6 and MDU interrupt sources For interrupt structure 2 see Figure 9 8 the interrupt status flag does not directly drive the pending interrupt request User s Manual 9 11 V1 0 2010 02 Interrupt System V 2 3 3 Cinfineon Interrupt System All qualified flags of the oo Corresponding 2 interrupt node m event status NOR gt OR amp e interrup flag a
447. ion T13TEC Selected Event 000 None 001 T12 Compare Event on Channel 0 CM CC60 010g T12 Compare Event on Channel 1 CM CC61 011 T12 Compare Event on Channel 2 CM_CC62 100 T12 Compare Event on any Channel 0 1 2 101 T12 Period Match T12_PM 110 T12 Zero Match while counting up T12_ZM and CDIR 0 111 Any Hall State Change Table 20 12 112 Trigger Event Additional Specifier T13TED Selected Event Specifier 00g Reserved no action 015 Selected event is active while T12 is counting up CDIR 0 10g Selected event is active while T12 is counting down CDIR 7 1 11g Selected event is active independently of the count direction of T12 User s Manual CCU6 V4 0 20 73 V1 0 2010 02 Cinfineon Capture Compare Unit 6 CCU6 20 4 3 T13 Compare Mode Associated with Timer T13 is one compare channel that can perform compare operations with regard to the contents of the T13 counter Figure 20 23 gives an overview on the T13 channel in Compare Mode The channel is connected to the T13 counter register via an equal to comparator generating a compare match signal when the contents of the counter matches the contents of the compare register The channel consists of the comparator and a double register structure the actual compare register CC63RL CC63RH feeding the comparator and an associated shadow register CC63SRL CC63SRH that is preloaded by softwar
448. iption BC 3 0 rh Bit Count Field Shift counter is updated with every shift bit Note This bit field is not to be written to 0 7 4 r Reserved Returns 0 if read should be written with 0 SSC_CONH Control Register High Operating Mode AB Reset Value 00 RMAP 0 PAGE X 7 6 5 4 3 2 1 0 EN MS 0 BSY BE PE RE TE rw rw r rh rwh rwh rwh rwh Field Bit Type Description TE 0 rwh Transmit Error Flag No error 1g Transfer starts with the slave s transmit buffer not being updated RE 1 rwh_ Receive Error Flag 0s No error 1g Reception completed before the receive buffer was read User s Manual SSC V1 4 18 24 V1 0 2010 02 Cinfineon XC82x High Speed Synchronous Serial Interface Field Bit Type Description PE rwh Phase Error Flag No error 1 Received data changes around sampling clock edge BE rwh Baud Rate Error Flag 0s No error 1g than factor 2 or 0 5 between slave s actual and expected baud rate BSY rh Busy Flag Set while a transfer is in progress Note This bit is not to be written to MS Master Select Bit Og X Slave Mode Operate on shift clock received via SCLK 1g Master Mode Generate shift clock and output it via SCLK EN Enable Bit 1 Transmission and reception enabled Access to status flags and M S control Reserved Returns 0 if read should be written with O Note The
449. is section provides product specific information relevant to the OCDS 10 2 1 Pinning Figure 10 1 describes the debug pin function in XC82x Table 10 1 XC82x Pin Functions and Selection Pin Function Desciption Selected By P0 6 SPD 0 Single pin debug access port Selectable via BMI value Refer data to Chapter 5 for more details P1 0 SPD 1 Single pin debug access port data 10 2 2 Clocking Configuration The OCDS runs at the CPU operating frequency of either 8 MHz or 24 MHz 10 2 3 Interrupt Events and Assignment Instead of entering Monitor Mode on a break event it can be configured such that OCDS NMI is vectored to In this configuration the action on OCDS NMI is fully under user software control Details of this usage is described in later sections Table 10 2 lists the interrupt event sources from the OCDS and the corresponding event interrupt enable bit and flag bit Table 10 2 OCDS Interrupt Events Event Event Interrupt Enable Bit Event Flag Bit IRAM read event MMICR NMIRRE MMICR FNMIRR IRAM write event MMICR NMIRWE MMICR FNMIRW Table 10 3 shows the interrupt node assignment for each OCDS interrupt source User s Manual 10 2 V1 0 2010 02 OCDS V 2 7 1 Cinfineon Debug System Table 10 3 OCDS Events Interrupt Node Control Event Interrupt Node Interrupt Node Flag Vector Enable Bit Bit Address IRAM read event NMICON NMIOCDS NMISR FN
450. ister 1 CB Reset Value 00 RMAP 0 PAGE 6 7 6 5 4 3 2 1 0 CHP7 CHP6 CHP5 CHP4 CHP3 CHP2 CHP1 CHPO rwh rwh rwh rwh rwh rwh rwh rwh Field Bits Type Description CHPx x rwh Channel Pending Bit x x20 7 Write view A write to this address targets the bits in register CRCR1 Read view Each bit corresponds to one analog channel the channel number x is defined by the bit position in the register The arbiter automatically resets at start of conversion or sets it again at abort of conversion for the corresponding analog channel Og analog channel x is not requested for conversion by the parallel request source 1g analog channel x is requested for conversion by the parallel request source Note Bits 4 7 are only applicable for devices that have 8 ADC channels For channels not implemented these bits should be treated as Reserved bits of type r which returns 0 if read and should be written with 0 0 7 4 r Reserved Returns 0 if read should be written with O Note The bits that can be read from this register location are generally rh They cannot be modified directly by a write operation A write operation modifies the bits in User s Manual 21 24 V1 0 2010 02 ADC V2 1 Cinfineon Analog to Digital Converter CRCR1 that is why they are marked rwh and leads to a load event one clock cycle later 21 6 2 Queued Request
451. ister containing the currently assumed Hall pattern CURH the next expected Hall pattern EXPH and the corresponding output pattern MCMP A new Modulation pattern is output when the sampled Hall inputs match the expected ones EXPH To detect the next rotation phase segment for block commutation the CCU6 monitors the Hall inputs for changes When the next expected Hall pattern is detected the next corresponding Modulation pattern is output To increase for noise immunity to a certain extend the CCU6 offers the possibility to introduce a sampling delay for the Hall inputs Some changes of the Hall inputs are not leading to the expected Hall pattern because they are only short spikes due to noise The Hall pattern compare logic compares the Hall inputs to the next expected pattern and also to the currently assumed pattern to filter out spikes For the Hall and Modulation output patterns a double register structure is implemented While register MCMOUTL MCMOUTH holds the actually used values its shadow register MCMOUTSL MCMOUTSH can be loaded by software from a pre defined table holding the appropriate Hall and Modulation patterns for the given motor control A transfer from the shadow register into register MCMOUT can take place when a correct Hall pattern change is detected Software can then load the next values into register MCMOUTS It is also possible by software to force a transfer from MCMOUTS into MCMOUT Note The Hall input
452. it TIR IRCON1 SSC Receive RIR IRCON1 IIC Interrupt IFLG CNTR CCU6 Node 0 Interrupt CCU6SRO IRCON2 CCU6 Node 1 Interrupt CCU6SR1 IRCON2 CCU6 Node 2 Interrupt CCU6SR2 CCU6 Node 3 Interrupt CCU6SR3 LEDTSCU Time Slice Interrupt TSF GLOBCTL1 LEDTSCU Time Frame Interrupt TFF GLOBCTL1 Watchdog Timer NMI FNMIWDT NMISR User s Manual 9 33 V1 0 2010 02 Interrupt System V 2 3 3 Cinfineon Interrupt System Table 9 5 Location of the Interrupt Flags cont d Interrupt Event Interrupt Flag SFR 48 MHz and 75 KHz Oscillator NMI FNMIOSCCLK NMISR 32 768 KHz XTAL Oscillator NMI FNMIXTALCLK NMISR Flash Operation Complete NMI FNMIFLASH NMISR OCDS NMI FNMIOCDS NMISR VDDC Prewarning NMI FNMIVDDC NMISR VDDP Prewarning NMI FNMIVDDP NMISR Flash ECC NMI FNMIECC NMISR 1 Each CCU6 interrupt can be assigned to any of the CCU6 interrupt nodes 3 0 via CCU6 registers INPL INPH User s Manual 9 34 V1 0 2010 02 Interrupt System V 2 3 3 Cinfineon Debug System 10 Debug System This chapter describes the XC800 debug system in particular focus on the OCDS unit which provides the hardware to support debug functionality 10 1 Overview The debug system comprises of the On Chip Debug Support OCDS unit and Debug Monitor in ROM which provides basic debug functionality for XC800 based systems controlled directly by an external tool via debug interface pin s Fea
453. it defines which arbitration mode is selected Og Permanent arbitration default 1g Arbitration started by pending conversion request ASENO ASEN1 Arbitration Slot x Enable Each bit enables an arbitration slot of the arbiter round ASENO enables arbitration slot 0 ASEN1 enables slot 1 If an arbitration slot is disabled a pending conversion request of a request source connected to this slot is not taken into account for arbitration Og corresponding arbitration slot is disabled 1g corresponding arbitration slot is enabled Reserved Returns 0 if read should be written with 0 Note If the arbiter shall not be running continuously ARBM 1 no conversion request of the request source for arbitration slot x must be active Clear conversion requests of the related request source before disabling an arbitration slot User s Manual ADC V2 1 21 42 V1 0 2010 02 Cinfineon Analog to Digital Converter Conversion Start Mode When the arbiter has selected the request to be converted next the handling of this channel depends on the current activity of the converter Converter is currently idle the conversion of the arbitration winner is started immediately Current conversion has same or higher priority the current conversion is completed the conversion of the arbitration winner is started after that Current conversion has lower priority the action is user configurable
454. it in the CNTR register the STAT register will then contain status code 60 The IIC will also enter slave receive mode when it receives the general call address 00 if the GCE bit in the ADDR register is set status code will then be 70 Note Where the IIC has an extended slave address signified by 11110 in ADDR 7 3 it will transmit an acknowledge after the first address byte is received but no interrupt will be generated IFLG will not be set and the status will not change Only after the second address byte has been received will the IIC generate an interrupt set the IFLG bit and the status code as described above Slave receive mode can also be entered directly from a master mode if arbitration is lost in master mode during the transmission of an address and the slave address and Write bit or the general call address if bit GCE in the ADDR register is set to 1 are received The status code the STAT register will then be 68 if the slave address was received or 78 if the general call address was received The IFLG bit must be cleared to 0 to allow the data transfer to continue If the AAK bit in the CNTR register is set to 1 then after each byte is received an acknowledge bit low level on SDA is transmitted and the IFLG bit is set the STAT register will then contain status code 80 or 90 if slave receive mode was entered with the general call address The received data byte can be read from the DATA register
455. itialize the EEPROMInfo data structure based on the selected emulation mode It should be called at least once before using the other API functions InitEEPROM assume that flash area used for EEPROM emulation is in erased condition when InitEEPROM is called for the first time It will update the EEPROM configuration to indicate the current active sector and the flash address that is to be written to on subsequent call to WriteEEPROM User s Manual 23 47 V1 0 2010 02 ROM Library V0 5 Cinfineon ROM Library The active sector is selected based on the sector containing a valid status byte If both logical sector contains valid status byte the one containing the least amount of valid status byte is selected as the active sector Additionally InitEEPROM will return an error status requesting the sector with the most valid status byte to be erased However there s a scenario where this might not be desired e g if there was a sudden power off during a WriteEEPROM reclaim operation For example a 124 bytes configured EEPROM is powered off suddenly during the WriteEEPROM reclaim operation Thus not all the 124 bytes of valid information is copied to the new sector Once the active sector has been determined the flash address to be written is determined as the first flash WL without a valid status byte in the active sector InitEEPROM will also check for situation where erase operation has been unexpected
456. ition for bit T13CM if enabled by bit ENT13CM or for bit T13PM if enabled by bit ENT13PM Coding see 0 7 6 r reserved returns 0 if read should be written with 0 User s Manual 20 125 V1 0 2010 02 CCUG V4 0 Cinfineon Capture Compare Unit 6 CCU6 20 10 General Module Operation This section provides information about the Input selection see Section 20 10 1 General register description see Section 20 10 2 20 10 1 Input Selection Each CCU6 input signal can be selected from a vector of four or eight possible inputs by programming the port input select registers PISELOL PISELOH and PISEL2 This permits to adapt the pin functionality of the device to the application requirements The output pins for the module output signals are chosen in the ports Naming convention The input vector CC60IN D A for input signal CC60IN is composed of the signals CC60INA to CC60IND Note All functional inputs of the CCU6 are synchronized to before they affect the module internal logic The resulting delay of 2 and for asynchronous signals an additional uncertainty of 1 have to be taken into account for precise timing calculation An edge of an input signal can only be correctly detected if the high phase and the low phase of the input signal are both longer than 1 fo g User s Manual 20 126 V1 0 2010 02 CCUG V4 0 82 Cinfineon 20 10 2 General R
457. itten with RESULT 4 0 7 3 rh Conversion Result This bit field contains the result of the digital low pass filter ADC RESRxH x 0 2 Result Register x High View LPF 10 bit CB x 2 Reset Value 00 ADC RESR3H Result Register 3 High View LPF 10 bit D3 Reset Value 00 RMAP 0 PAGE 2 7 6 5 4 3 2 1 0 RESULT 12 5 rh Field Bits Type Description RESULT 12 5 7 0 rh Conversion Result This bit field contains the result of the digital low pass filter User s Manual 21 76 V1 0 2010 02 ADC V2 1 Cinfineon XC82x Analog to Digital Converter The Result Control Registers control the behavior of the result registers and monitor their status ADC_RCRx x 0 3 Result Control Register x RMAP 0 PAGE 4 7 6 CA x 1 Reset Value 00 VFCTR WFR IEN 0 DLPF 0 DRCTR Field Bits Type Description Data Reduction Control This bit defines how many conversion results are accumulated for data reduction It defines the reload value for bit DRC data reduction filter is disabled The reload value for DRC is 0 so the accumulation is done over 1 conversion 13 The data reduction filter is enabled The reload value for DRC is 1 so the accumulation is done over 2 conversions DLPF Digital Low Pass Filter Control This bit defines if the conversion resu
458. ity the following points must be noted for each Flash bank erase operation cannot be aborted earlier than 5 ms after it starts Maximum of two consecutive aborted erase without complete erase in between are allowed on each sector Complete erase operation approximately 100 ms is required and initiated by user program after a single or two consecutive aborted erase as data in relevant sector s is corrupted For the specified cycling time each aborted erase constitutes one program erase cycling User s Manual 22 11 V1 0 2010 02 BootROM User Routines V1 1 Cinfineon Boot ROM User Routines Maximum allowable number of aborted erase for each D Flash sector during lifetime is 2500 The Flash erase abort subroutine call cannot be performed anytime within 5 ms after the erase operation has started This is a strict requirement that must be ensured by the user Otherwise the erase operation cannot be aborted Once exited from this routine user can call BR FLASH READ MODE STATUS user routine to check if the abort erase operation has been completed When the selected bank is already in Read Mode it indicates that the abort erase operation has been completed Table 22 13 Specifications of Flash Erase Abort subroutine Subroutine BR FLASH BACKGROUND ERASE ABORT Input Flash Bank is in erase mode Output C 0 Flash erase abort is in progress C 1 Flash erase abort is not started Stack size req
459. k which are describe as below Note No empty Data Block is allowed The Data Block 014 Data Program Codes Checksum Block Block Length 2 bytes 1 byte 1 byte Description Program Codes The program codes have a length of Block Length 2 byte where the Block Length is provided in the previous Header Block The EOT Block 02 Last_Code Program Code Not Used Checksum _Length Block 1 byte 1 byte 1 byte Description Last_Codelength This byte indicates the length of the program codes in this EOT Block Program Codes The last program codes to be sent to the uC Not used The length is Block_Length 3 Last_Codelength These bytes are not used and they can be set to any value User s Manual 6 10 V1 0 2010 02 Cinfineon Boot Loader 6 2 2 3 Mode1 Execute customer code Mode 1 is used to execute a customer program in the XRAM of the uC at OF000 The Header Block for this working mode has the following structure The Header Block Data Area 00 014 Header Mode1 Not Used m Block 1 byte Mode Data Description Not used The five bytes are not used and will be ignored in Mode 1 Under working Mode 1 the Header Block is the only transfer block to be sent by the host no further serial communication is necessary The uC will exit the UART BSL Mode and jump to the XRAM address at OF000
460. k can be switched by the startup firmware in Boot ROM to the user selectable mode active 8 MHz mode or 24 MHz mode 0 4 pin serves as a reset indication to the external world to indicate that the device has executed a reset The startup firmware starts to run after the system is out of reset The user specified settings in USER ID such as the boot mode User Mode BSL Mode OCDS Mode to enter and the system clock speed will be decoded in the startup firmware Based on the value decoded the startup firmware will performed the necessary setup before entering the selected boot mode User s Manual 7 6 V1 0 2010 02 Cinfineon System Control Unit Note When Vppp is not powered on the current over any GPIO pin must not source Vppp higher than 0 3 0 5 V 7 2 1 2 Watchdog Timer Reset The watchdog timer reset is an internal reset The Watchdog Timer WDT maintains a counter that must be refreshed or cleared periodically If the WDT is not serviced correctly and in time it will generate an NMI request to the CPU and then reset the device after a predefined time out period Bit PMCONO WDTRST is used to indicate the watchdog timer reset status For watchdog timer reset as the EVR and 48 MHz oscillator is already stable the timing for watchdog timer reset is shorter compared to the other types of resets 7 2 1 3 Soft Reset Soft reset is an internal reset that is caused by a software set of the soft reset request bit SWRQ in RS
461. l 21 17 V1 0 2010 02 ADC V2 1 Cinfineon Analog to Digital Converter Two types of requests sources are available A channel scan source can issue conversion requests for a coherent sequence of input channels This sequence begins with the highest enabled channel number and continues towards lower channel numbers Up to channels can be enabled for the scan sequence Each channel is converted once per sequence A scan source converts a series of input channels permanently or on a regular time base For example if programmed with low priority some input channels can be scanned in a background task to update information that is not time critical Request source 1 is a channel scan source A queued source can issue conversion requests for an arbitrary sequence of input channels The channel numbers for this sequence can be freely programmed This supports application specific conversion sequences that cannot be covered by a channel scan source Also multiple conversions of the same channel within a sequence are supported A queued source converts a series of input channels permanently or on a regular time base For example if programmed with medium priority some input channels can be converted upon a specified event e g synchronized to a PWM Conversions of lower priority sources are suspended in the meantime Request source 0 is a 4 stage queued source User s Manual 21 18 V1 0 2010 02 ADC V2 1 Cinfineon Analog
462. l and the Modes After the successful synchronization to the host the UART BSL routine enters Phase II during which it communicates with the host to select the desired working modes The detailed communication protocol is explained as follows 6 2 1 Serial Communication Protocol The communication between the host and the UART BSL routine is done by a simple transfer protocol The information is sent from the host to the uC in blocks All the blocks follow the specified block structure The communication is nearly unidirectional that is that the host is sending several transfer blocks and the UART BSL routine is just confirming them by sending back single acknowledge or error bytes The uC itself does not send any transfer blocks However the above regulation does not apply to some modes where the uC might need to send the required data to the host besides the acknowledge or error byte 6 2 1 1 Transfer Block Structure A transfer block consists of three parts User s Manual 6 4 V1 0 2010 02 Cinfineon Boot Loader Block Data Area Checksum 1 byte X bytes 1 byte Block Type the type of block which determines how the data in the data area is interpreted Implemented block types are 00 type HEADER O1 type DATA 02 type END OF TRANSMISSION EOT Data Area A list of bytes which represents the data of the block The length of data area cannot exceed 96 97 byte
463. l interrupt request is assigned to two interrupt nodes Additional Features Detect and trigger mechanisms are supported with two mechanisms to ensure a fast response without CPU intervention Out of Range Comparator ORC is build into every ADC channel which will trigger other modules or an interrupt when voltage out of range condition occurs This happens when voltage at the input channel rises to above Vddp level or when the input channel falls to a voltage below level The out of range comparator is connected to other modules e g CCU6 timer such that it is able to trigger the start or stop of other modules All out of range comparator events is assigned to one interrupt node Configurable Limit Checker checks the conversion results against programmed values which will trigger other modules or an interrupt when the trigger condition is fulfilled The configurable limit checker is conected to other module i e CCU6 such that is is able to trigger the start or stop of the other module User s Manual 21 9 V1 0 2010 02 ADC V2 1 Cinfineon Analog to Digital Converter 21 3 Electrical Models Each conversion of an analog input voltage to a digital value consists of two consecutive phases During the sample phase the input voltage is sampled and stored The input signal path is a simplified model for this During the conversion phase the stored voltage is converted to a digital result The reference voltage path i
464. ld the SCL line low after each byte has been transferred until IFLG has been cleared in the CNTR register 17 6 Bus Arbitration In master mode the IIC will check that each transmitted logic 1 appears on the IIC bus as a logic 1 If another device on the bus over rules and pulls the SDA line low arbitration is lost If arbitration is lost during the transmission of a data byte or a Not Acknowledge bit the IIC will return to idle state If arbitration is lost during the transmission of an address the will switch to slave mode so that it can recognize its own slave address or the general call address User s Manual 17 6 V1 1 V1 0 2010 02 Cinfineon Inter IC Bus 17 7 Software Reset A software reset may be applied to the IIC module by writing any value to register SRST address This sets the IIC back to idle STAT set to F8 and sets the STP STA and IFLG bits of the CNTR register to 0 17 8 Operating Modes All operating modes of the IIC module require the ENAB bit of register CNTR to be set to 1 17 8 1 Master Transmit In the master transmit mode the IIC transmits a number of bytes to a slave receiver The master transmit mode is entered by setting the STA bit in register CNTR to 1 The IIC will then test the IIC bus and will transmit a START condition when the bus is free When a START condition has been transmitted the IFLG bit will be set and the status code in the STAT register will be 08
465. le for the selection of the on chip memory resources The interrupt requests from the peripheral units are handled by the interrupt controller unit 2 3 SFRs of the CPU The XC800 Core registers occupy direct Internal Data Memory space locations in the range 80 to FF 2 3 1 Stack Pointer SP 81 The SP register contains the Stack Pointer The Stack Pointer is used to load the program counter into internal data memory during LCALL and ACALL instructions and to retrieve the program counter from memory during RET and RETI instructions Data may also be saved on or retrieved from the stack using PUSH and POP instructions Instructions that use the stack automatically pre increment or post decrement the stack pointer so that the stack pointer always points to the last byte written to the stack i e the top of the stack On reset the Stack Pointer is reset to 07 This causes the stack to begin at a location 08 above register bank zero The SP can be read or written under Software control The programmer must ensure that the location and size of the stack in internal data memory do not overlap with other application data 2 3 2 Data Pointer DPTR 82 3 The Data Pointer DPTR is stored in registers DPL Data Pointer Low byte and DPH Data Pointer High byte to form 16 bit addresses for External Data Memory accesses MOVX A DPTR and MOVX DPTR A for program byte moves MOVC A A DPTR and for indirect program jumps JMP A DPTR T
466. lected Flash Bank is in Read Mode C 1 Selected Flash Bank is not in Read Mode C 1 Invalid option is selected Stack size required 6 Resource A used destroyed User s Manual 22 2 V1 0 2010 02 BootROM User Routines V1 1 Cinfineon Boot ROM User Routines 22 2 Get 4 Bytes Information This routine allow the tool chain software or even user code to read out the Chip Identification Number see Chapter 1 4 or User Identification Number USER_ID see Chapter 5 1 for device Table 22 4 Specifications of BR GET 4 BYTES INFO subroutine Subroutine BR GET 4 BYTES INFO Input R7 of current Register Bank Option 00 Option 0 Chip Idenitification Number 01 Option 1 User Identification Number USER ID Others Reserved Invalid options R5 of current Register Bank Pointer for the 4 byte IRAM buffer Output The IRAM buffer is filled with the following for Option 0 R5 Chip Identification Number MSB R5 1 Chip Identification Number R5 2 Chip Identification Number R5 3 Chip Identification Number LSB The IRAM buffer is filled with the following for Option 1 R5 USER ID MSB R5 1 USER_ID R5 2 USER_ID R5 3 USER_ID LSB The IRAM buffer is filled with the following for invalid option R5 0x00 R5 1 0x00 R5 2 0x00 R5 3 0x00 C 0 Fetch is successful 1 Fetch is not successful Option is invalid Stack size required 8 Reso
467. led T2CON EXEN2 is set to 1 EXF2 flag is set when a negative transition occurs at pin T2EX be configured by bit field T2MOD T2PRE Note It is also recommended to toggle the BCON BRDIS bit after the reception of each complete LIN frame to avoid a wrong Break field detection in noisy environments i e spikes on the LIN bus 16 6 2 3 Baud Rate Range Selection The Break Synch Field detection logic supports a maximum number of bits in the Break field as defined by Equation 16 5 16 5 Maximum number of bits Baud Rate x EN CEN Sample Frequency The sample frequency is given by Equation 16 6 16 6 _ PCLK Sample Frequency eae 8x2 If the maximum number of bits in the Break field is exceeded the internal counter will overflow which results in a baudrate detection error Therefore an appropriate BGSEL value has to be selected for the required baudrate detection range User s Manual 16 16 V1 0 2010 02 UART V 1 6 Cinfineon UART The baud rate range defined by different BGSEL settings is shown in Table 16 7 Table 16 7 BGSEL Bit Field Definition for Different Input Frequencies BGSEL Baud Rate Select for Detection foa 2184 2 BGSEL to f 72 2 BGSEL 24 MHz 00 11 kHz to 333 3 kHz 015 5 5 kHz to 166 7 kHz 10g 2 8 kHz to 83 3 kHz 11 1 4 kHz to 41 7 kHz 8 MHz 00 3 7 kHz to 111 1 kHz 01 1 8 kHz to 55 6 kHz 105 0 92 2 27 8 2 11 0 46
468. lication OxDFC3 C LMUL XC 32 bit Multiplication OxDFC6 C UIDIV XC 16 16 bit Division OxDFC9 C ULDIV XC 32 32 bit Division 23 3 1 Integer Multiplication 23 17 Output is Result of Valuel x Value2 Table 23 15 Specifications of 16 bit Multiplication Subroutine Subroutine C IMUL XC Address DFCO Input R7 of current Register Bank Value1 Low Byte R6 of current Register Bank Value1 High Byte R5 of current Register Bank Value2 Low Byte R4 of current Register Bank Value2 High Byte Output R7 of current Register Bank Result of Value1 x Value2 Low Byte R6 of current Register Bank Result of Value1 x Value2 High Byte Stack size required 2 Resource A MDO MD1 MD4 MD5 MRO MR1 MR2 MR3 MDUCON used destroyed User s Manual 23 39 V1 0 2010 02 ROM Library V0 5 Cinfineon XC82x ROM Library 23 3 2 Long Multiplication 23 18 Output is Result of Valuel x Value2 Table 23 16 Specifications of 32 bit Multiplication Subroutine Subroutine C LMUL XC Address DFC3 Input R7 of current Register Bank Value Bits 7 0 R6 of current Register Bank Value1 Bits 15 8 R5 of current Register Bank Value1 Bits 23 16 R4 of current Register Bank Value1 Bits 31 24 R3 of current Register Bank Value2 Bits 7 0 R2 of current Register Bank Value2 Bits 15 8 R1 of current Register Bank Value2 Bits 23 16
469. lid Flag for Result Register x This bit indicates that the contents of the result register x are valid Os result register x does not contain valid data 1g result register x contains valid data 0 6 5 r Reserved Returns 0 if read should be written with 0 RESULT 0 7 rh Conversion Result This bit field contains the conversion result or the result of the data reduction filter ADC_RESRxH x 0 2 Result Register x High View Acc 8 bit 2nd conv CB x 2 Reset Value 00 ADC RESR3H Result Register High View Acc 8 bit 2nd conv D3 Reset Value 00 RMAP 0 PAGE 2 7 6 5 4 3 2 1 0 RESULT 8 1 rh Field Bits Type Description RESULT 8 1 7 0 rh Conversion Result This bit field contains the conversion result or the result of the data reduction filter ADC RESRXxL x 0 2 Result Register x Low View Acc 10 bit 1st conv CA x 2 Reset Value 00 ADC RESR3L Result Register 3 Low View Acc 10 bit 1st conv D2 Reset Value 00 RMAP 0 PAGE 2 7 6 5 4 3 2 1 0 RESULT 2 0 VF DRC CHNR rh rh rh rh User s Manual 21 72 V1 0 2010 02 ADC V2 1 Cinfineon XC82x Analog to Digital Converter Field Bits Type Description CHNR 2 0 rh Channel Number This bit field contains the channel number of the latest register update Note Bit 2is only applicable for devices that
470. ll be generated if it is enabled by NMICON NMIOSCCLK For both cases of oscillator failure emergency routines can be executed using either 48 MHz or 75 KHz clock source The XC82x remains in this loss of clock state until the next power on reset or after a successful clock recovery has been performed A clock recovery could be carried out by restarting the detection Upon detecting a stable oscillator frequency of more than 40 MHz 48MOSC2L will be set to 0 and the system clock will switched automatically to the 48 MHz clock source Note With 75 KHz as the system frequency in loss of clock state read from flash is possible However Flash program and erase is not allowed Note NMICON NMIOSCCLK is used to enable the NMI interrupt for loss of clock failure in 48 MHz or 75 KHz oscillators User s Manual 7 13 V1 0 2010 02 Cinfineon System Control Unit 7 3 3 CCU Register Description The registers of the clock control unit are reset to the default value after any type of reset Register OSC_CON controls the 48 MHz oscillator watchdog and 75 KHz oscillattor watchdog OSC_CON OSC Control Register F4 Reset Value 00 RMAP 0 PAGE 1 7 6 5 4 3 2 1 0 0 INTOSC 0 75KOSC 48MOSC RCOWD _ST 21 21 RST r rh r rh rh rwh Field Bits Type Description RCOWDRST 0 rwh 48 MHz and 75 KHz Oscillators Watchdog Reset Setting this bit will restart the oscillator detection This bit will be auto
471. ll be started in OCDS mode and then the monitor will be invoked before to start any user code The debugger should provide for user configuration of suspend controls 10 3 4 Running the Monitor The Monitor runs with its own stack and data work space therefore the complete status of the core is saved and later restored before returning to the user code Once the Monitor is running it can access for read and write all of the system resources and data can be communicated with the Debugger 10 3 5 Returning to the User Program When a return to User Program is requested the Monitor sets core registers including the Instruction Pointer IP as required This can be either the same status as at the Breakpoint or including some changes done during the Break by a host debugger Then a jump to the location pointed by IP is performed and the target system returns to User Mode 10 3 6 Single Step Execution For this functionality OCDS operates at first as when Returning to the User Program but also a dedicated flag is set into a control register MMCR MSTEP This way just one user instruction is executed before re entering the Monitor again User s Manual 10 7 V1 0 2010 02 OCDS V 2 7 1 Cinfineon Debug System 10 4 Breakpoint Generation Module Breakpoint generation is only possible in Monitor Mode Attention To be able to debug via Monitor Mode the application software should not change the TRAP_EN bit within Extended Op
472. lt This bit field contains the conversion result or the result of the data reduction filter 0 7 r Reserved Returns 0 if read should be written with 0 ADC_RESRxL x 0 2 Result Register x Low View Acc 10 bit 2nd conv CA x 2 Reset Value 00 ADC RESR3L Result Register 3 Low View Acc 10 bit 2nd conv D2 Reset Value 00 RMAP 0 PAGE 2 7 6 5 4 3 2 1 0 RESULT 2 0 VF DRC CHNR rh rh rh rh Field Bits Type Description CHNR 2 0 rh Channel Number This bit field contains the channel number of the latest register update Note Bit 2is only applicable for devices that have 8 ADC channels For channels not implemented these bits should be treated as Reserved bits of type f which returns 0 if read and should be written with DRC 3 rh Data Reduction Counter This bit field indicates how many conversion results have still to be accumulated to generate the final result for data reduction final result is available in the result register The valid flag is automatically set when this bit field is set to 0 1g 1 conversion result must be added to obtain the final result in the result register The valid flag is automatically reset when this bit field is set to 1 User s Manual 21 74 V1 0 2010 02 ADC V2 1 Cinfineon Analog to Digital Converter Field Bits Type Description VF 4 rh Valid Flag for Result R
473. lts is processed through the Digital low pass filter Og digital low pass filter is disabled 1g digital low pass filter is enabled and previous result register is cleared for the first time when the bit is changed from 0 gt 1 See Page 21 82 IEN Interrupt Enable This bit enables the event interrupt related to the result register x An event interrupt can be generated when DRC is set to 0 after decrementing or by reload event interrupt is disabled 1g event interrupt is enabled User s Manual ADC V2 1 21 77 V1 0 2010 02 Cinfineon XC82x Analog to Digital Converter Field Bits Type Description WFR 6 rw Wait for Read Mode This bit enables the wait for read mode for result register x Og wait for read mode is disabled 1g The wait for read mode is enabled VFCTR 7 rw Valid Flag Control This bit enables the reset of valid flag by read access to high byte for result register x 0g unchanged by read access to RESRxH RESRAxH default 1g reset by read access to RESRxH RESRAXH 0 1 3 5 r Reserved Returns 0 if read should be written with 0 1 For 10bit conversion either Data Reduction Filter OR Digital Low Pass Filter can be used However since there is only one adder both filter cannot be turned on at the same time Thus when both filter is turned on at the same time DRCTR 1 and DLPF 1 the results would be the sa
474. luding the boot up options BMI It can be accessed by user using BR GET 4 BYTES INFO user routine or via BSL Mode A USER can be programmed via BR FEATURE SETTING user routine or via BSL Mode 6 Detailed description of these BSL Modes can be found in UART Boot loader chapter USER ID Byte 0 7 6 5 4 3 2 1 0 BMI Field Bits Description BMI 7 0 Boot Mode Index The boot option to enter User Mode UART BSL Mode and OCDS Mode as described in Table 5 1 User s Manual 5 2 V1 0 2010 02 Cinfineon XUNAR Boot and Startup USER_ID Byte 1 15 14 13 12 11 10 9 8 BMI Field Bits Description BMI 15 8 Inverse of Boot Mode Index mE The inverse of BMI BMI is checked for validity with BMI BMI is valid when BMI BMI 1 0 USER_ID Byte 2 23 22 21 20 19 18 17 16 0 Field Bits Description 0 23 16 Reserved USER_ID Byte 3 31 30 29 28 27 26 25 24 CLKMOD PERIPHER E E SEL ALS EN Field Bits Description 0 29 24 Reserved User s Manual 5 3 V1 0 2010 02 Cinfineon XUNAR Boot and Startup Field Bits Description PERIPHERALS_EN 30 Peripherals Enable Bit 0 Disable all peripherals defined in register 1 1 Enable all peripherals defined in register 1 CLKMODE_SEL 31 Clock Mode Selection 0 8 MHz active mode 1 24 MHz active mode 5 2 Boot ROM Operating Mode Afte
475. lue 00 RMAP 0 PAGE 2 7 6 5 4 3 2 1 0 0 T13TED T13TEC T13SSC T12SSC r TW rw rw rw Field Bits Type Description T12SSC 0 rw Timer T12 Single Shot Control This bit controls the single shot mode of T12 Og single shot mode is disabled no HW action on T12R 1p The single shot mode is enabled the bit T12R is cleared by HW if T12 reaches its period value in edge aligned mode T12 reaches the value 1 while down counting in center aligned mode In parallel to the clear action of bit T12R the bits CC6xST x 0 1 2 are cleared T13SSC 1 rw Timer T13 Single Shot Control This bit controls the single shot mode of T13 0s No HW action T13R 1g The single shot mode is enabled the bit T13R is cleared by HW if T13 reaches its period value In parallel to the clear action of bit T13R the bit CC63ST is cleared User s Manual 20 61 V1 0 2010 02 CCU6 V4 0 Cinfineon Capture Compare Unit 6 CCU6 Field Bits Type Description T13TEC 4 2 rw T13 Trigger Event Control bit field T13TEC selects the trigger event to start T13 automatic set of T13R for synchronization to T12 compare signals according to following combinations 000g no action 001 set T13R on a T12 compare event on channel 0 010g set T13R on a T12 compare event on channel 1 011 set T13R on a T12 compare event on channel 2 100 set 1 on any T12 compare event ch 0 1 2 101g set T13R upon a period m
476. ly aborted and return a status byte indicating sectors that needs to be re initialised FixEEPROM Table 23 22 FixEEPROM Function name FixEEPROM Function prototype void FixEEPROM unsigned char sector status unsigned char idata buffer Input sector status status returned by InitEEPROM buffer Pointer to 32 bytes buffer in IRAM location Return None Max stack size 4 bytes 12 bytes Boot ROM User Routines FixEEPROM will take the status byte returned by InitEEPROM and fix the invalid sectors It will erase the flash sectors and write a status byte to indicate that the sector has been erased A pointer to a buffer of 32 bytes in IRAM is needed to enable flash write operation For save operation ensure that flags in NMISR SFR are cleared before calling this function User s Manual 23 48 V1 0 2010 02 ROM Library V0 5 Cinfineon ROM Library WriteEEPROM Table 23 23 WriteEEPROM Function name WriteEEPROM Function prototype void WriteEEPROM unsigned char address char idata src EEPROMInfo config Input address Logical address of emulated EEPROM to write to src Pointer to 32 bytes of data in IRAM that is to be written config Pointer to EEPROMInfo data structures Return None Max stack size 6 bytes 12 bytes Boot ROM User Routines WriteEEPROM will perform the write operation based on EEPROM configuration It will p
477. ly be written while the timer T13 is stopped Write actions while T13 is running are not taken into account Register T13 can always be read by SW Timer T13 only supports edge aligned mode counting up T13PRL Timer T13 Period Register Low 9E Reset Value 00 RMAP 0 PAGE 1 7 6 5 4 3 2 1 0 T13PVL rwh Field Bits Type Description T13PVL 7 0 rwh T13 Period Value The value T13PV defines the lower 8 bits of counter value for T13 leading to a period match When reaching this value the timer T13 is set to zero T13PRH Timer T13 Period Register High Reset Value 00 RMAP 0 PAGE 1 7 6 5 4 3 2 1 0 T13PVH rwh User s Manual 20 81 V1 0 2010 02 CCUG V4 0 Cinfineon Capture Compare Unit 6 CCU6 Field Bits Type Description T13PVH 7 0 rwh 13 Period Value The value T13PV defines the upper 8 bits of counter value for T13 leading to a period match When reaching this value the timer T13 is set to zero User s Manual 20 82 V1 0 2010 02 CCU6 V4 0 Cinfineon Capture Compare Unit 6 CCU6 20 4 6 3 Compare Register Registers CC63RL H is the actual compare register for T13 The values stored in CC63RL H is compared to the counter value of T13 The State Bit CC63ST is located in register CMPSTATL CC63RL Compare Register for T13 Low 9 Reset Value 00 RMAP 0 PAGE 1 7 6 5 4 3 2 1 0 CCVL th
478. matically reset to 0 and thus always be read back as 0 0 No effect 1 Restart the oscillator watchdog for 48 MHz and 75 KHz oscillation 48MOSC2L and 75KOSC2L flag will be held in the last value until it is updated after 180 usec 48MOSC2L 1 rh 48 MHz Oscillator Too Low Flag The Oscillator Watchdog monitors the same as fosc System frequency could be generated from the internal 48 MHz oscillator or an external 48 MHz clock source 0 _fgyg is above threshold 1 fays is below threshold 75KOSC2L 2 rh 75 KHz Oscillator Too Low Flag The Oscillator Watchdog monitors the 75 KHz oscillation 0 75 KHz oscillates above threshold 1 75 KHz oscillates below threshold INTOSC_ST 6 rh Internal Oscillator Stable Indication 0 48MHz and 75 KHz oscillators are not stable 1 48MHz and 75 KHz oscillators are stable User s Manual 7 14 V1 0 2010 02 Cinfineon XC82x System Control Unit Field Bits Description 0 5 3 r Reserved 7 Returns 0 if read should be written with 0 Note The reset value of OSC_CON register is 0000 0110 One clock after reset bits 48MOSC2L and 75KOSC2L will be set to 0 if both oscillators are running then the value 0000 0000g will be observed User s Manual 7 15 V1 0 2010 02 Cinfineon System Control Unit 7 4 Power Management The power saving modes in the XC82x provide flexible power consumption through a combination of t
479. mber 5 2 1 Boot ROM Operating Mode 5 4 1 User Mode 5 4 1 User Mode 5 4 1 Boot Loader 5 4 1 OCDS MOd6 Sees Oh en eere rae en 5 5 1 UART Boot Loader 6 1 1 Phase Automatic Serial Synchronization to the Host 6 2 1 General Description eee RR Rm RE 6 2 1 Calculation of BG and PRE values 6 3 1 Phase II Serial Communication Protocol and the Modes 6 4 1 Serial Communication Protocol 6 4 1 Transfer Block Structure 6 4 1 Transfer Block 6 5 1 Response codes to the host 6 6 1 User s Manual 1 2 V1 0 2010 02 Cinfineon 6 2 2 6 2 2 1 6 2 2 2 6 2 2 3 6 2 2 4 6 2 2 5 6 2 2 6 6 2 2 7 6 2 2 8 7 7 1 7 1 1 7 1 2 7 2 7 2 1 7 2 1 1 7 2 1 2 7 2 1 3 7 2 1 4 7 2 1 5 7 2 2 7 2 3 7 3 7 3 1 7 3 2 7 3 3 7 4 7 4 1 7 4 1 1 7 4 1 2 7 4 1 3 7 4 2 7 5 8 8 1 8 2 8 2 1 8 2 2 8 2 3 8 2 4 8 3 8 4 The Selection of Working Modes 6 8 1 Receiving the Header Block 6
480. me slice when the count value saturates i e does not overflow amp stops at FF In this case the TS counter starts running again only on a new pad turn A configurable pin low level active extension is provided for adjustment of oscillation per user system The extension is active during the discharge phase of oscillation and is configurable to extend by one or four FPCLK Figure 19 4 illustrates this function The pad configuration of the active touch sense pin TSIN x is over ruled by hardware in the active duration to enable oscillations reference Section 19 9 In particular the weak internal pull up can be optionally disabled GPIO pin SFR setting for pull applies instead such as when the user system utilize external resistor for pull up instead In the whole duration of the touch sense time slice COLA is activated high This activates a pull up via an external resistor connected to pin COLA This configuration provides some flexibility to adjust the pad oscillation rate for adaptation to user system The touch sense function is time multiplexed with the LED function on enabled LINE x TSIN x pins During the touch sense time slice for the other TSIN pins which are not on active pad turn the corresponding LINE output remains active Software should take care to set the line bits to 1 to avoid current sink from pin COLA User s Manual 19 11 V1 0 2010 02 LEDTSCU V 1 2 1 Cinfineon LED Touch Sense Controller The t
481. me as DRCTR 0 and DLPF 1 digital low pass filter enabled For 8 bit conversion only Data Reduction Filter can be used When 8bit resolution mode is chosen and digital low pass filter is enabled DLPF 1 the results will be the same as DLPF 0 digital low pass filter disabled User s Manual ADC V2 1 21 78 V1 0 2010 02 Cinfineon Analog to Digital Converter The Valid Flag Register summarizes the flags indicating that the corresponding result register contents are valid ADC_VFCR Valid Flag Clear Register Reset Value 00 RMAP 0 PAGE 4 7 6 5 4 3 2 1 0 0 VFC3 VFC2 1 T w w w w Field Bits Type Description VFCx x 0 3 w Clear Valid Flag for Result Register x 0s No action 1g Bit VF in result register RESRXL is reset 0 7 4 r Reserved Returns 0 if read should be written with 0 21 10 Wait for Read Mode The wait for read mode is a feature to prevent data loss due to overwriting a result register with a new conversion result before the CPU has read the previous data For example auto scan conversion sequences or other sequences with relaxed timing requirements are likely to use the same result register However the results come from different input channels so an overwrite would destroy the result from the previous conversion Wait for read mode automatically suspends the start of a conversion for this channel until the current result has
482. mechanism of the shadow transfer event MCM_ST if it has been requested before flag R set by an event selected by SWSEL and if MCMEN 1 This feature permits the synchronization of the outputs to the PWM source that is used for modulation T12 or T13 00 Direct the trigger event immediately leads to the shadow transfer 01 A T13 zero match triggers the shadow transfer 10 A T12 zero match while counting up triggers the shadow transfer 11g reserved no action 0 7 6 r reserved 3 returns 0 if read should be written with 0 User s Manual 20 105 V1 0 2010 02 CCUG V4 0 Cinfineon Capture Compare Unit 6 CCU6 Register MCMOUTSL H contains bits used as pattern input for the multi channel mode and the Hall mode This register is a shadow register that can be read and written for register MCMOUT indicating the currently active signals MCMOUTSL Multi Channel Mode Output Shadow Register Low 9E Reset Value 00 RMAP 0 PAGE 0 7 6 5 4 3 2 1 0 STRMCM 0 MCMPS w r rw Field Bits Type Description MCMPS 5 0 rw Multi Channel PWM Pattern Shadow Bit field MCMPS is the shadow bit field for bit field MCMP The multi channel shadow transfer is triggered by MCM_ST according to the transfer conditions defined by register MCMCTR STRMCM 7 w Shadow Transfer Request for MCMPS Writing STRMCM 1 leads to an immediate activation of MCM_ST to update bit field MCMP
483. mory area and the program memory area It can be accessed using both MOVX and MOVC instructions The MOVX instructions for XRAM access use either 8 bit or 16 bit indirect addresses While the DPTR register is used for 16 bit addressing either register RO or R1 is used to form the 8 bit address The upper byte of the XRAM address during execution of the 8 bit accesses is defined by the value stored in register XADDRH Hence the write instruction for setting the higher order XRAM address in register XADDRH must precede the MOVX instruction The bit field PAGE of SCU PAGE register must be programmed before accessing the XADDRH register User s Manual 3 2 V1 0 2010 02 Memory Organization V 0 1 Cinfineon XC82x Memory Organization XADDRH On Chip XRAM Address Higher Order F2 Reset Value F0 RMAP 0 PAGE 3 7 6 5 4 3 2 1 0 ADDRH rw Field Bits Type Description ADDRH 7 0 rw Higher Order of On chip XRAM Address The value for XC82x is FO User s Manual Memory Organization V 0 1 3 3 V1 0 2010 02 Cinfineon Memory Organization 3 3 Memory Protection Strategy The memory protection strategy in XC82x prevents unauthorized read out of critical data and user IP from Flash memory by blocking all external access to the device This is achieved by using the Boot Mode Index BMI to control the boot options such that once the BMI is programmed to enter user mode productive
484. mpare State Register CMPSTATL H contains status bits monitoring the current capture and compare state and control bits defining the active passive state of the compare channels CMPSTATL Compare State Register Low Reset Value 00 RMAP 0 PAGE 3 7 6 5 4 3 2 1 0 0 CC63ST CCPOS2 CCPOS1 CCPOSO CC62ST CC61ST CC60ST r rh rh rh rh rh rh rh Field Bits Type Description CC60ST 0 rh Capture Compare State Bits CC61ST 1 Bits CC6xST monitor the state of the CC62ST 2 capture compare channels Bits CC6xST x 0 1 CC63ST 6 2 are related to T12 bit CC63ST is related to T13 1 In compare mode the timer count is less than the compare value In capture mode the selected edge has not yet been detected since the bit has been cleared by SW the last time 1g X In compare mode the counter value is greater than or equal to the compare value In capture mode the selected edge has been detected CCPOS60 3 rh Sampled Hall Pattern Bits CCPOS61 4 Bits CCPOS6x x 0 1 2 are indicating the value CCPOS62 5 of the input Hall pattern that has been compared to the current and expected value The value is sampled when the event HCRDY Hall Compare Ready occurs Os input CCPOS6x has been sampled as 0 13 input CCPOS6x has been sampled as 1 0 7 r reserved returns 0 if read should be written with 0 User s Manual 20 51 V1 0 2010 02 CCU6 V4
485. mpare function of channel CC61 can be used as a phase delay from the position sensor input signals to the switching of the output signals that is necessary if a sensorless back EMF technique or Hall sensors are used The compare value in channel CC62 can be used as a time out trigger interrupt indicating that the actual motor speed is far below the desired destination value An abnormal load change can be detected with this feature and PWM generation can be disabled User s Manual 20 97 V1 0 2010 02 CCU6 V4 0 Cinfineon Capture Compare Unit 6 CCU6 20 8 Modulation Control Registers 20 8 1 Modulation Control This register contains bits enabling the modulation of the corresponding output signal by PWM pattern generated by the timers T12 and T13 Furthermore the multi channel mode can be enabled as additional modulation source for the output signals MODCTRL Modulation Control Register Low FC Reset Value 00 RMAP 0 PAGE 2 7 6 5 4 3 2 1 0 MCMEN 0 T12MODEN rw r rw Field Bits Type Description T12MODEN 5 0 rw T12 Modulation Enable These bits enable the modulation of the corresponding output signal by a PWM pattern generated by timer T12 T12MODENO MODCTR 0 for output CC60 T12MODEN 1 MODCTR 1 for output COUT60 T12MODEN2 MODCTR 2 for output CC61 T12MODEN3 MODCTR 3 for output COUT61 T12MODEN4 MODCTR 4 for output CC62 T12MODEN5 MODCTR 5 for output COUT62 Og
486. n also be used for erasing the Flash Bank where the interrupt vectors are defined as interrupts cannot be handled when the Flash is in erase mode as the interrupt handler cannot be fetched For this subroutine the FNMIFLASH flag is cleared automatically and therefore need not be handled by the user Note As program will return to user code after erasing is completed customer should take care that they do not erase their user program code as well 4 7 2 2 Background Flash Erase Subroutine The second type of subroutine background Flash erase allows the user program code to continue execution from where it last stopped until the Flash NMI event is generated The FNMIFLASH flag is set and if enabled via bit NMIFLASH an NMI to the CPU will be triggered to enter the Flash NMI service routine At this point the Flash bank is in ready to read mode i e erasing is done This subroutine can be used in either of the following two cases The Flash bank where the code execution is taking place is not the same as the Flash bank that is targeted for erasing The subroutine is called from XRAM 4 7 3 Aborting Background Flash Erase Each complete erase operation on a Flash bank requires approximately 100 ms during which read and program operations on the Flash bank cannot be performed For the XC82x provision has been made to allow an on going background Flash erase operation to be interrupted so that higher priority tasks such as reading
487. n configuration if this slave is not selected for transmission This mode requires that slaves not selected for transmission only shift out ones that is their transmit buffers must be loaded with FFFF prior to any transfer Note In order to avoid possible conflicts or misinterpretations it is recommended to always load the slave s transmit buffer prior to any transfer The cause of an error interrupt request receive phase baud rate transmit error can be identified by the error status flags in control register CON Note In contrast to the error interrupt request line EIR the error status flags CON TE CON RE CON PE and CON BE are not reset automatically upon entry into the error interrupt service routine but must be cleared by software User s Manual 18 18 V1 0 2010 02 SSC V1 4 Cinfineon 18 4 XC82x Interrupts High Speed Synchronous Serial Interface The three SSC interrupts can be separately enabled or disabled by setting or clearing their corresponding enable bits in SFR SCU_MODIEN For a detailed description of the various interrupts see Section 18 3 An overview is given in Table 18 4 Table 18 4 SSC Interrupt Sources Interrupt Signal Description Transmission TIR Indicates that the transmit buffer can be reloaded with new starts data Transmission RIR The configured number of bits have been transmitted and ends shifted to the receive buffer Receive EIR This int
488. n is ongoing MDx and MRx registers not used in an operation are undefined to the user For normalize and shift operations the registers MD4 and MR4 are used as shift input and output control registers to specify the shift direction and store the number of shifts performed User s Manual 12 9 MDU V2 9 V1 0 2010 02 Cinfineon XC82x 12 5 1 Operand and Result Registers Multiplication Division Unit The MDx and MRx registers are used to store the operands and results of a calculation MD4 and MR4 are also used as input and output control registers for shift and normalize operations MDU_MDx x 0 5 MDU Data Register x Operand B2 x 1 RMAP 0 PAGE X Reset Value 00 7 6 5 4 3 1 0 DATA rw Field Bits Type Description DATA 7 0 rw Operand Value See Table 12 5 MDU_MRx x 0 5 MDU Data Register x Result B2 x 1 RMAP 0 PAGE X Reset Value 00 7 6 5 4 3 1 0 DATA rh Field Bits Type Description DATA 7 0 rh Result Value See Table 12 6 User s Manual 12 10 V1 0 2010 02 MDU V2 9 Cinfineon XC82x Multiplication Division Unit MDU_MD4 Shift Input Control Register B6 Reset Value 00 RMAP 0 PAGE X 7 6 5 4 3 2 1 0 0 SLR SCTR TW rw rw Field Bits Type Description SCTR 4 0 rw Shift Counter The count written to SCTR determines the number
489. n lost Same as for code 684 Same as for code 684 general call address received ACK transmitted Arbitration lost Write byte to DATA clear Transmit last byte receive SLA R received ACK transmitted IFLG AAK 0 Or write byte to DATA clear IFLG AAK 1 ACK Transmit data byte receive ACK User s Manual IIC V1 1 17 8 V1 0 2010 02 Cinfineon Inter IC Bus If 10 bit addressing is being used then after the first part of a 10 bit address plus the Write bit have been successfully transmitted the status code will be 18 or 20 After this interrupt has been serviced and the second part of the address transmitted the STAT register will contain one of the following codes Table 17 7 Status Code after Second Address Byte for 10 bit Addressing is Transmitted in Master Transmit Mode Code State CPU Response Next IIC Action 38 Arbitration lost Clear IFLG Return to idle state Or set STA clear IFLG Transmit START when bus is free 68 Arbitration lost Clear IFLG 0 Receive data byte transmit SLA W received not ACK ACK transmitted Or clear IFLG 1 Receive data byte transmit ACK BO Arbitration lost Write byte to DATA clear Transmit last byte receive SLA received IFLG 0 ACK ACK transmitted Or write byte to DATA Transmit data byte receive clear IFLG 1 ACK DO Second address Write byte to DATA clear Transmi
490. n total Figure 2 2 c shows two timing diagrams of a 1 byte 2 cycle 2 x machine cycle instruction The first diagram shows the instruction being executed over two machine cycles with the opcode C2P2 fetched from a memory without wait state The second diagram shows the corresponding states of the same instruction being executed over three machine cycles instruction time extended with one wait cycle inserted for opcode fetching from the slow memory requiring one two wait state s Note For instructions that are executed over two or more machine cycles execution cycle may or may not be extended in case of access to slow memory with one two wait states The execution cycle is nonetheless guaranteed consistent for each instruction when accessed from slow memory with defined wait state s Reference Table 2 1 User s Manual 2 8 V1 0 2010 02 XC800 Core V 1 0 2 Cinfineon 800 Instruction Timing Examples foak Read next opcode without wait state y 1 1 1 2 next instruction Read next opcode one wait cyde ES 1 1 1 2 WAIT WAIT next instruction 1 byte 1 cyde instruction e g INCA Read 29 byte Read next opcode without weit state without wait state 2 next instruction Read 29 byte
491. nalysis is in progress When analysis is completed this byte bit s will be clear by the function This byte bit s will be set and cleared by function users must not tamper with this Users can read the respective PadError and PadResult bit status when respective PadFlag bit status is 0 Stack size required 2 Resource A RO R1 R4 R5 R6 R7 used destroyed IRAM address 0x2D Ox2F 3 byte XRAM address OxFOEC OxFOFF max 20 bytes To enable Touch sense control as well as number of Touch Sense pad turns and the interrupt flag s Time Frame Time Slice The function will control the padt and configure it in LTS TSCTL PADT SFR field Users can programmed this value as 0x34 for example And at IRAM address 0x34 the subtraction m value for PADTO at 0x35 subtraction m value for PADT1 at 0x36 the subtraction m value for PADT2 etc To use common subtraction m value for all touch pads program subtraction option as 0x00 in iram address 0x32 Subtraction m address is defined in iram address 0x32 Notes This function uses fixed IRAM address Ox2D to 0x34 and XRAM address OxFOEC OxFOFF These addressees are not to be destroyed by users at all time In the event of error detection users can clear these addressees to start afresh the calculation The number of Touch Sense Pad Turns enabled must be sequential e g PADTO PADT1 etc for the software round robin of the function to work properly Users
492. nd 0 75 MBaud respectively Table 16 5 and Table 16 6 list various commonly used baud rates together with their corresponding parameter settings and the deviation errors compared to the intended baud rate Table 16 5 Typical Baud Rates of UART 8 MHz Baud rate PRE Reload Value Numeratorof BG Deviation VALUE Fractional Register Error 8 MHz Value 1 FD_NUM 115 2 kBaud 1 BRPRE 000 4 44 11 By 008B 0 08 20 kBaud 1 BRPRE 000 25 193 0 0 0320 0 0096 19 2 1 000 26 1A 1 14 0341 0 04 9600 Baud 2 BRPRE 001 26 1 14 0341 0 04 4800 Baud 4 BRPRE 010 26 1A 1 14 0341 0 04 2400 Baud 8 011 26 1A 1 14 0341 0 0496 1 The value of the 16 bit BG register is obtained by concantenating the 11 bit BRVALUE and 5 bit FD NUM into a 16 bit value Table 16 6 Typical Baud Rates of UART fpc 24 MHz Baud rate PRE Reload Value Numerator of BG Deviation VALUE Fractional Register Error 24 MHz Value 1 FD_NUM 115 2 kBaud 1 BRPRE 000 13 1 01 01A1 0 08 20 kBaud 1 BRPRE 000 75 4B 0 00 0960 0 00 19 2 kBaud 1 000 78 4 4 04 09C4 0 00 9600 Baud 2 001 78 4E 4 041 09C4 0 00 4800 Baud 4 010 78 4E 4 041 09C4
493. nding channel during a shadow transfer In capture mode the captured value of T12 can be read from these registers Note The shadow registers can also be written by SW in capture mode In this case the HW capture event wins over the SW write if both happen in the same cycle the SW write is discarded User s Manual CCU6 V4 0 20 48 V1 0 2010 02 Cinfineon Capture Compare Unit 6 CCU6 20 3 8 5 Dead time Control Register Register T12DTCL H controls the dead time generation for the timer T12 compare channels Each channel can be independently enabled disabled for dead time generation If enabled the transition from passive state to active state is delayed by the value defined by bit field DTM The dead time counters are clocked with the same frequency as T12 This structure allows symmetrical dead time generation in center aligned and in edge aligned PWM mode A duty cycle of 50 leads to CC6x COUT6x switched on for 0 5 period dead time Note The dead time counters are not reset by bit T12RES but by bit DTRES T12DTCL Dead Time Control Register for Timer T12 Low A44 Reset Value 00 RMAP 0 PAGE 1 7 6 5 4 3 2 1 0 DTM rw Field Bits Type Description DTM 7 0 rw Dead Time Bit field DTM determines the programmable delay between switching from the passive state to the active state of the selected outputs The switching from the active state to the passive state is not
494. ne time slice at end of time frame when touch sense function is enabled The counter always counts up and overflows from 7FFH to the reload value User s Manual 19 8 V1 0 2010 02 LEDTSCU V 1 2 1 Infineon LED and Touch Sense Controller which is equal to the reset value Within each time frame the sequence of LED column enabling always start from the most significant enabled column column with higher numbering Example in case of four LED columns enabled in ordered sequence Start with COL3 followed by COL2 followed by COL1 then COLO If the touch sense function is not enabled COLA is always available for LED function as the last LED column time slice of a time frame Example in case of four LED columns enabled in ordered sequence Start with COL2 followed by COL1 followed by COLO then COLA FPCLK No time slice per time frame 48 MHZ No LED Column amp amp LD EN 1 Touchsense amp amp TS EN 48 MHz NR LEDCOL LEDTS counter resetreload value incaseofTS EN 0 rescaler ounter H B H B H SPCLK LEDTS Count la 0005 7004 010 5004 100s 3004 110
495. nea uk EE Rex d ee Rer FR nos 20 67 1 20 4 2 T13 Counting Scheme 20 70 1 20 4 2 1 T13Counting 20 70 1 20 4 2 2 Single Shot Mode 20 71 1 20 4 2 3 Synchronization to T12 20 72 1 20 4 3 T13 Compare Mode 20 74 1 20 4 4 Compare Mode Output Path 20 76 1 20 4 5 T13 Shadow Register Transfer 20 77 1 20 4 6 T13 related Registers 20 79 1 20 4 6 1 T13 Counter Register sl ases 20 79 1 20 4 6 2 Period Register eria acu eR ew hg ER ed 20 81 1 20 4 6 3 Compare Register 2 2 20 83 1 20 4 6 4 Compare Shadow Register 20 83 1 20 5 Trap Handling 20 85 1 20 6 Multi Channel 20 87 1 20 7 Hall Sensor Mode 2 2 22 2 pe a Ee 20 90 1 20 7 1 Hall Pattern Evaluation 20 91 1 20 7 2 Hall Pattern Compare 20 93 1 20 7 3 Hall Mode Flags si Phew EE RR Rex 20 94 1 20 7 4 Hall Mode for Brushless DC Motor Control 20 96 1 20 8 Modulation Control Registers 20
496. ng Features Operates in Master or slave mode Supports multi master systems Performs arbitration and clock synchronization Supports 7 bit and10 bit addressing modes Selectable baud rate generation of up to 400 KBaud fast mode Flexible control via interrupt service routines or polling 17 2 System Information This section provides system information relevant to the IIC 17 2 1 Pinning The IIC pin assignment for XC82x is shown in Table 17 1 Table 17 1 IIC Pin Functions in XC82x Pin Function Desciption Selected By P0 4 SCL 0 Clock Input Output PO_ALTSELO P4 0 PO_ALTSEL1 P4 0 PO_ALTSEL2 P4 1 P0 2 SCL 1 Clock Input Output PO_ALTSELO P2 0 PO_ALTSEL1 P2 1 P0 6 SDA 0 Data Input Output PO_ALTSELO P6 0 PO_ALTSEL1 P6 0 PO_ALTSEL2 P6 1 P0 3 SDA 1 Data Input Output PO ALTSELO P3 0 PO ALTSEL1 P3 1g User s Manual 17 1 V1 0 2010 02 V1 1 Cinfineon Inter IC Bus Since SCL and SDA have input and output functions within the same set of pin selected the input and output signal selection is done using just the Px_ALTSELn signals from the GPIO module No separate input selection control PISEL is required If more than 1 set of input output are selected via Px_ALTSELn register the set with the lower set number has the highest priority For example if output signal SDA_O and SDA_1 are selected at the same time the input
497. ng Synchronization cont d SWSYN Synchronization Event see register MCMCTR 10 T12 Zero Match T12 ZM the MCM shadow transfer is synchronized to a T12 PWM 11g Reserved no action User s Manual CCU6 V4 0 20 89 V1 0 2010 02 Cinfineon Capture Compare Unit 6 CCU6 20 7 Hall Sensor Mode For Brushless DC Motors in block commutation mode the Multi Channel Mode has been introduced to provide efficient means for switching pattern generation These patterns need to be output in relation to the angular position of the motor For this usually Hall sensors or Back EMF sensing are used to determine the angular rotor position The CCU6 provides three inputs CCPOSO CCPOS1 and CCPOS2 that can be used as inputs for the Hall sensors or the Back EMF detection signals There is a strong correlation between the motor position and the output modulation pattern When a certain position of the motor has been reached indicated by the sampled Hall sensor inputs the Hall pattern the next pre determined Multi Channel Modulation pattern has to be output Because of different machine types the modulation pattern for driving the motor can vary Therefore it is wishful to have a wide flexibility in defining the correlation between the Hall pattern and the corresponding Modulation pattern Furthermore a hardware mechanism significantly reduces the CPU for block commutation The CCU6 offers the flexibility by having a reg
498. ng all valid data from the previous active sector to the current active sector before erasing the previous active sector To update less than 31 data bytes in the emulated EEPROM user application needs to perform a read to the logical address where the data resides Once the read data are User s Manual 23 45 V1 0 2010 02 ROM Library V0 5 Cinfineon ROM Library stored in the IRAM user application will then need to update the relevant data in IRAM with the desired data This is then followed by a call to write function to program the data into the emulated EEPROM 23 4 4 description The EEPROM emulation operation is controlled via one data structure and 4 functions Additionally some definition is provided for ease of use 23 4 4 1 Constant definition Several constant definition was added to give meaningful name and promote code readability EEPROM Emulation scheme define MODE 032 define MODE 164 define MODE 2 96 define MODE 3 128 Logical Address define WL 00 define WL 11 define WL_2 2 define WL_3 3 23 4 4 2 EEPROMInfo data structure The EEPROM emulation API use a data structure called EEPROMInfo to manage the EEPROM emulation operation typedef struct EEPROMInfo unsigned int ActiveSector unsigned int WriteAddress unsigned char DataSize Jidata EEPROMInfo EEPROMinfo is a structure containing 3 variables ActiveSector WriteAddress and DataSize The structu
499. ng counter actions depend on the defined counting rules This register has a shadow register and the shadow transfer is controlled by bit STE12 A read action by SW delivers the value that is currently used for the compare action whereas the write action targets a shadow register The shadow register structure allows a concurrent update of all T12 related values T12PRL Timer T12 Period Register Low 9 Reset Value 00 RMAP 0 PAGE 1 7 6 5 4 3 2 1 0 T12PVL rwh Field Bits Type Description T12PVL 7 0 rwh Timer T12 Period Value The value T12PVL defines lower 8 bits of the counter value for T12 leading to a period match When reaching this value the timerT12 is setto zero edge aligned mode or changes its count direction to down counting center aligned mode T12PRH Timer T12 Period Register High 9D Reset Value 00 RMAP 0 PAGE 1 7 6 5 4 3 2 1 0 T12PVH rwh User s Manual 20 44 V1 0 2010 02 CCUG V4 0 Cinfineon Capture Compare Unit 6 CCU6 Field Bits Type Description T12PVH 7 0 rwh Timer T12 Period Value The value T12PVL defines the upper 8 bits of counter value for T12 leading to a period match When reaching this value the timerT12 is set to zero edge aligned mode or changes its count direction to down counting center aligned mode User s Manual 20 45 V1 0 2010 02 CCU6 V4 0 Cinfineon Capture Compare Unit 6 CCU6
500. ning detection is disabled 1 Vppp prewarning detection is enabled Note VDDP prewarning flag and NMI will only be triggered when this bit is set to 1 VDDPBOA 2 rw Vppp Brownout Detection Enable in active mode 0 Vppp brownout detection in active mode is disabled 1 Vppp brownout detection in active mode is enabled VDDPBOPD 3 rw Vppp Brownout Detection Enable in power down mode 0 Vbpp brownout detection in power down mode is disabled 1 Vbpp brownout detection in power down mode is enabled User s Manual 7 4 V1 0 2010 02 Cinfineon XC82x System Control Unit Field Bits Type Description VDDCTH rh Vppc Threshold Indication 0 Below prewarning threshold level 1 Above prewarning threshold level Note It is not affected by the bit VDDCPW VDDPTH rh Vppp Threshold Indication 0 Below Vppp prewarning threshold level 1 Above Vppp prewarning threshold level Note It is not affected by the bit VDDPPW 7 6 Reserved Returns 0 if read should be written with 0 User s Manual 7 5 V1 0 2010 02 Cinfineon System Control Unit 7 2 Reset Control The XC82x has five types of resets power on reset watchdog timer reset soft reset power down wake up reset and brownout reset When the XC82x is first powered up or with brownout condition triggered by supply voltage input s going below the threshold proper volt
501. nnel control register boundaries GLOBCTR channel number limit channel checking event analog part conversion finished conversion result ADC8_channel events overv Figure 21 15 Channel Event Generation The two selectable boundaries split the conversion result range into three areas Area 1 Conversion result below or equal to both boundaries Area Conversion result above one boundary and below equal to other boundary Area Ill Conversion result above both boundaries n 27 1 conversion results with 9 area III channel events e e 5 boundary 5 2 9 9lo 5 area II O conversion results without ale channel events B d 2 oundary zje o conversion results with Q i area channel events 0 ADC_limit_check Figure 21 16 Limit Checking The shown example for limit checking generates channel events only if the conversion results are outside the normal operating range defined by area 11 LCC 0108 User s Manual 21 52 V1 0 2010 02 ADC V2 1 Cinfineon Analog to Digital Converter If only two areas are required use the same boundary register for boundary A and boundary In this case area Il is empty and two result ranges are available Avoid LCC x10 in this case Typical applications for limit checking are monitoring tasks temperature pressure current etc where the real value of
502. not exceed the defined range Please refer to the range indicated in the respective Data Sheet The Global Control Register defines the basic timing parameters and the basic operating mode of the converter unit it contains bits for Enabling Disabling of the analog converter Defining the result bits resolution 8 10bits wide Defining the divider ratio CTC for fang internal clock frequency for the analog part Enabling Disabling of the Out of range comparator interrupt Enabling Disabling of the Channel limit checking interrupt ADC GLOBCTR Global Control Register Reset Value 30 RMAP 0 PAGE 0 7 6 5 4 3 2 1 0 ANON DW CTC ORCIEN CLCIEN 0 Field Bits Type Description CLCIEN 2 rw Channel Limit Checking Interrupt Enable This bit enables the channel event interrupt related to the limit checking see Figure 21 15 A channel event interrupt is generated when this interrupt enable is set to 1 there is new result in buffer and result triggers the limit check unit Og event interrupt is disabled 1g event interrupt is enabled ORCIEN 3 rw Out of Range Comparator Interrupt Enable Og Out of range comparator interrupt disabled 1g of range comparator interrupt enabled User s Manual 21 14 V1 0 2010 02 ADC V2 1 Cinfineon XC82x Analog to Digital Converter Field Bits Type Description CTC 5 4 Conversion Time C
503. nput Pin This is the next or currently active pad turn touch sense input pin When PADTSW 0 the value is updated by hardware at the end of touch sense time slice Software write is always possible Op np TSIN n PADTSW 3 rw Software Control for Touch Sense Pad Turn Og hardware automatically enables the touch sense inputs round robin starting from TSINO 1g Disable hardware control for software control only The active touch sense input is configured in bit PADT EPULL 4 rw Enable External Pull up Configuration on Pin COLA When set the internal pull up over rule on active touch sense input pin is disabled 0s HW over rule to enable internal pull up is active on TSIN x for set duration in touch sense time slice With this setting it is not specified to assign the COLA to any pin 1g Enable external pull up Output 10n COLA for whole duration of touch sense time slice Note Independent of this setting COLA always outputs 1 for whole duration of touch sense time slice User s Manual 19 26 V1 0 2010 02 LEDTSCU V 1 2 1 Cinfineon LED Touch Sense Controller Field Bits Type Description TSCTRSAT 5 rw Saturation of TS Counter Og Disable 1g X Enable TS counter stops counting in the current time slice when it reaches Counter starts to count again on new pad turn triggered on compare match TSCTRR 6 rw TS Counter Auto Reset Og Disable TS
504. nterrupt System V 2 3 3 Infineon XC82x Interrupt System CCU6 Node0 CCU6SRO IRCON2 0 CCU6SR1 IRCON2 4 LeD TS Lt eo Time frame GLOBCTL1 5 EM CCU6 Node 1 GLOBCTL1 4 IEN1 4 ECCIP1 IEN1 5 CCU6 Node 2 CCU6SR2 leo leo IRCON3 0 CCUG SR2EN MODIEN 6 CCU6 Node 3 CCU6SR3 L eo IRCON3 4 CCUG SR3EN LED TS TsF Time slice GLOBCTL1 7 irs EN GLOBCTL1 6 Y Bit addressable MODIEN 7 ECCIP2 IEN1 6 LION ECCIP3 IEN1 7 4 Request flag is cleared by hardware Figure 9 5 Interrupt Request Sources Part 5 User s Manual Interrupt System V 2 3 3 9 6 V1 0 2010 02 Infineon Interrupt System WDT Overflow L o NMISRO NMIWDT 0 48 2 75KHz Loss of clock 0 NMISR 1 NMIOSCCLK NMICON 1 Flash 9 JFNMIFLASH NMISR2 NMIFLASH NMICON 2 IRAM read rnin e o even
505. nterrupt can be generated based on a result event according to the structure shown in Figure 21 27 If a result event is detected it sets the corresponding indication flag in register ADC_EVINFR These flags can also be set by writing a 1 to the corresponding bit position at ADC_EVINSR whereas writing 0 has no effect The indication flags can be cleared by SW by writing a 1 to the corresponding bit position in register ADC_EVINCR result event result event indication flag interrupt enable EVINFR RCRO 3 EVINF4 7 IEN set new data available to SRO result event ADC result event int Figure 21 27 Result Event Interrupt Generation The Request Source Event Interrrupt Channel Event Interupt and Result Event Interrupt all share the same service request output line SRO The result events and the request source events share the same registers The result events are located at the following bit positions in register Event 4 Result event of result register 0 Event 5 Result event of result register 1 Event 7 Result event of result register 3 21 10 2 Data Reduction and Filtering Data reduction automatically accumulates a series of conversion results before generating a result interrupt This can remove some noise from the input signal and reduces the CPU load required to unload the conversion data from the ADC The standard data reduction mode accumulates result values within ar
506. ntrol bits and Flags Below the comparators used for IP Breakpoints are described CMPO A 16 bit comparator between the two HWBPO registers A side and the 16 bit Program Memory Address Bus B side Two output signals are generated break on HWBPO A B see below User s Manual 10 8 V1 0 2010 02 OCDS V 2 7 1 Cinfineon Debug System CMP1 A 16 bit comparator between the two HWBP1 registers A side and the 16 bit Program Memory Address Bus B side Two output signals are generated A B break on IP HWBP1 A gt B when activated together with A lt B from CMPO break HWBPO lt lt HWBP1 e 2 A 16 bit comparator between the two HWBP2 registers A side and the 16 bit Program Memory Address Bus B side One output signal is generated break IP HWBP2 CMPIP3 A 16 bit comparator between the two HWBP3 registers A side and the 16 bit Program Memory Address Bus B side One output signal is generated A B break on IP HWBP3 10 4 1 2 Breakpoints on Internal RAM Address These Internal RAM IRAM Breakpoints are recognized primary by observing the Internal Data Memory Address Buses respectively for Breakpoints on Read and Write addresses respectively The IRAM breakpoints are of Break After Make type therefore the proper debug action is taken immediately after the operation to the breakpoint address is performed The OCDS support
507. nual 13 7 V1 0 2010 02 Timer 0 and 1 V1 0 Cinfineon 0 1 13 4 4 Mode 3 In mode 3 Timer 0 and Timer 1 behave differently Timer 0 in mode 3 establishes TLO and THO as two separate counters Timer 1 in mode 3 simply holds its count The effect is the same as setting TR1 0 The logic for mode 3 operation for Timer 0 is shown in Figure 13 4 TLO uses the Timer 0 control bits GATEO TRO and TFO while THO is locked into a timer function counting machine cycles and takes over the use of TR1 and TF1 from Timer 1 Thus THO now sets TF1 upon overflow and generates an interrupt if is set Mode 3 is provided for applications requiring an extra 8 bit timer When Timer O is in mode 3 and TR1 is set Timer 1 can be turned on by switching it to any of the other modes and turned off by switching it into mode 3 fax Timer Clock TOS 0 Y m eT Bis gt gt interrupt TOS 1 TO Control RO 1 GATEO THO EXINTO V eT 8 Bits gt 1 yintenupt N TR1 Timer0_Mode3 Figure 13 4 Timer 0 Mode 3 Two 8 Bit Timers Counters User s Manual 13 8 V1 0 2010 02 Timer 0 and 1 V1 0 Cinfineon 0 1 13 5 Registers Description Seven SFRs control the operations of Timer
508. nual 19 4 V1 0 2010 02 LEDTSCU V 1 2 1 Cinfineon LED and Touch Sense Controller Table 19 4 LEDTSCU Interconnections LEDTSCU Function Signal Connected Other Module Function Signal Compare match 0 LEDTS CM ADC external trigger i REQTROG REQTR1G Time slice interrupt LEDTS TSI ADC external trigger i REQTROH REQTR1H 19 2 5 Debug Suspend Control The LEDTSCU timers counters LEDTS counter and TS counter can be enabled together for suspend operation when debug Monitor Mode becomes active The debug suspend control is configurable using register MODSUSP Chapter 10 2 4 contain the detailed description of the this register By debug suspend these counters stop counting retains the last value during the duration of the device in Monitor Mode 19 3 Time Multiplexed LED amp Touch Sense Functions On Pin A single pin supports LED amp touch sense functions in time multiplexed mode The hardware provides the enabling for LED mode or touch sense mode for respective function control In each time frame there are maximum eight time slices configurable up to one for touch sense function up to eight for LED function Provided touch sense function is enabled the last time slice is reserved for touch sense function where the pad oscillator circuit will be enabled for pin with active pad turn Provided LED function is enabled the rest of the time slices within the time frame are used for LED function
509. nual 21 63 V1 0 2010 02 ADC V2 1 Cinfineon Analog to Digital Converter 21 9 Conversion Result Handling The conversion results of each analog input channel can be stored in one of 4 conversion result registers selected by bitfield RESRSEL in the associated channel control register CHCTRx This structure provides different locations for the conversion results of different groups of channels Depending on the application needs data reduction auto scan alias feature etc the user can distribute the conversion results to minimize CPU load or to be more tolerant against interrupt latency 21 9 1 Storage of Conversion Results Each result register has an individual data valid flag VFx associated with it This flag indicates when new valid data has been stored in the corresponding result register and can be read out Depending of the result register read view see below the corresponding valid flag is automatically cleared when the result is read or remains set Automatically clearing the valid flag provides an easy handshake between result generation and retrieval This also supports wait for read mode Leaving the valid flag set supports debugging by delivering the result value without disturbing the handshake with the application result registers 0 3 data reduction result events unit digital low pass filter result handling set condition AD conversion stage Pointer to d
510. nversion until the previous result has been read Data reduction e g for digital anti aliasing filtering can automatically add up to 2 conversion results before interrupting the CPU Also result registers can be concatenated to build FIFO structures that store a number of conversion results without overwriting previous data This increases the allowed CPU latency for retrieving conversion data from the ADC A digital first order low pass filter is implemented that can continously filter the conversion results before it is written to the result register Interrupt Generation Several ADC events can issue interrupt requests to the CPU Source events indicate the completion of a conversion sequence in the corresponding request source This event can be used to trigger the setup of a new sequence Channel events indicate the completion of a conversion for a certain channel This can be combined with limit checking so interrupt are generated only if the result is within a defined range of values User s Manual 21 8 V1 0 2010 02 ADC V2 1 Cinfineon Analog to Digital Converter Result events indicate the availability of new result data in the corresponding result register If data reduction or digital low pass filter mode is active events are generated only after a complete accumulation sequence Out of range comparator events indicate that a voltage higher or lower than Vddp is detected at the ADC input channels Al
511. o 1 the content in the RTCCR register will be overwritten User s Manual 15 9 V1 0 2010 02 RTC V1 0 Cinfineon Real Time Clock with the captured CNT values after 2 CPU clock cycles An update of the actual compared value is necessary once a captured event is triggered RTC RTCCRO Mode 1 and Mode 3 Real Time Clock Compare Capture Register 0 E7 Reset Value 00 RMAP 0 PAGE X 7 6 5 4 3 2 1 0 CC VAL TWA Field Bits Type Description CC_VAL 7 0 rwh_ Compare Capture Value 7 0 These bits represent the compare capture value 7 0 of the 32 bits value that could generate a compare interrupt when it matches with the current counter values RTC_RTCCR1 Mode 1 and Mode 3 Real Time Clock Compare Capture Register 1 E9 Reset Value 00 RMAP 0 PAGE X 7 6 5 4 3 2 1 0 CC_VAL rwh Field Bits Type Description CC VAL 7 0 rwh Compare Capture Value 15 8 These bits represent compare capture value 15 8 of the 32 bits value that could generate a compare interrupt when it matches with the current counter values User s Manual 15 10 V1 0 2010 02 RTC V1 0 Cinfineon Real Time Clock RTC_RTCCR2 Mode 1 and Mode 3 Real Time Clock Compare Capture Register 2 EA Reset Value 00 RMAP 0 PAGE X 7 6 5 4 3 2 1 0 CC_VAL rwh Field Bits Type Description CC VAL 7 0 rwh Compare Capture Value 23 16 These bit
512. o indicate the successful completion of a calculation The results can then be obtained from the MRx registers The interrupt line INT OO is mapped directly to this interrupt source An interrupt can also be triggered when an error occurs during calculation This is indicated by the setting of the interrupt flag MDUSTAT IERR In the event of a division by zero error MDUSTAT IERR is set only at the end of the calculation phase Once the MDUSTAT IERR is set any ongoing calculation will be aborted For division by zero a saturated value is then loaded into the MRx registers The bit MDUCON IR determines the interrupt line to be mapped to this interrupt source An interrupt is only generated when interrupt enable bit MDUCON IE is 1 and the corresponding interrupt event occurs An interrupt request signal is always asserted positively for 2 CCLK clocks int reset SW JL reset Completion of Calculation to INT_OO toINT O1 Occurrence JL 4 of Error sd int reset SW TERR Figure 12 2 Interrupt Generation User s Manual 12 7 V1 0 2010 02 MDU V2 9 Cinfineon Multiplication Division Unit 12 5 Registers Description The MDU Special Function Registers are accessed from the standard non mapped SFR area Table 12 4 lists the MDU registers with their addresses Table 12 4 Register SFR Address Name MDU_MDUCON MDU Control Register MD
513. o match signal T12 ZM and the actual individual compare match signals CM 6x as well as the mode control bits T12MSELL MSEL6x User s Manual 20 26 V1 0 2010 02 CCUG V4 0 Cinfineon Capture Compare Unit 6 CCU6 In addition each state bit can be set or cleared by software via the appropriate set and reset bits in register CMPMODIFL CMPMODIFH MCC6xS and MCC6xR The input signals CCPOSx are used in hysteresis like compare mode whereas in normal compare mode these inputs are ignored Note In Hall Sensor single shot or capture modes additional different rules are taken into account see related sections A compare interrupt event CC6x R is signaled when a compare match is detected while counting upwards whereas the compare interrupt event CC6x F is signaled when a compare match is detected while counting down The actual setting of a State Bit has no influence on the interrupt generation in compare mode A modification of a State Bit CC6xST by the switching rule logic due to a compare action is only possible while Timer T12 is running T12R 1 If this is the case the following Switching rules apply for setting and clearing the State Bits in Compare Mode illustrated in Figure 20 11 and Figure 20 12 A State Bit CC6xST is set to 1 e with the next T12 clock 14 after a compare match when T12 is counting up i e when the counter is incremented above the compare value e with the next T12 clock after a z
514. ocal Interconnect Network LIN protocol for both master and slave operations The LIN baud rate detection feature which consists of the hardware logic for Break and Synch Field detection provides the capability to detect the baud rate within LIN protocol using Timer 2 This allows the UART module to be synchronized to the LIN baud rate for data transmission and reception 16 6 1 LIN Protocol LIN is a holistic communication concept for local interconnected networks in vehicles The communication is based on the SCI UART data format a single master multiple slave concept a clock synchronization for nodes without stabilized time base An attractive feature of LIN is self synchronization of the slave nodes without a crystal or ceramic resonator which significantly reduces the cost of hardware platform Hence the baud rate must be calculated and returned with every message frame The structure of a LIN frame is shown in Figure 16 4 The frame consists of the header which comprises a Break 13 bit time low Synch Byte 554 and ID field response time data bytes according to UART protocol e checksum Frame slot Response Synch Protected Data1 Data2 DataN Checksum identifier Figure 16 4 The Structure of LIN Frame Each byte field is transmitted as a serial byte as shown in Figure 16 5 The LSB of the data is sent first and the MSB is sent last The start bit is encoded as a bit with value zero dominant an
515. ocessing Unit DAP Device Access Port DNL Differential Non Linearity error ECC Error Correction Code EVR Embedded Voltage Regulator FDR Fractional Divider FIFO First In First Out data buffer mechanism GPIO General Purpose I O IAP In Application Programming Inter IC Bus Input Output INL Integral Non Linearity error ISP In System Programming JTAG Joint Test Action Group LEDTSCU LED and Touch Sense Controller Unit LIN Local Interconnect Network LSB Least Significant Bit finest granularity of the analog value in digital format represented by one least significant bit of the conversion result with n bits resolution measurement range divided in 2 equally distributed steps MDU Multiplication Division Unit NMI Non Maskable Interrupt OCDS On Chip Debug Support ORC Out of Range Comparator PC Program Counter POR Power On Reset PLL Phase Locked Loop User s Manual 1 15 V1 0 2010 02 System Architecture V1 0 Cinfineon Introduction Table 1 3 Acronyms cont d Acronym Description PSW Program Status Word PWM Pulse Width Modulation RAM Random Access Memory ROM Read Only Memory RTC Real Time Clock SCU System Control Unit of the device SFR Special Function Register SPD Single Pin DAP SPI Serial Peripheral Interface SSC Synchronous Serial Channel TUE Total Unadjusted Error UART Universal Asynchronous Receiver Transmitter WDT Watchdog Timer
516. od Value Compare Value T12 Count 0 T12R CC6xST CCU6_MCT05512 Figure 20 8 Single Shot Operation in Center Aligned Mode User s Manual 20 24 V1 0 2010 02 CCU6 V4 0 Cinfineon Capture Compare Unit 6 CCU6 20 3 3 12 Compare Mode Associated with Timer T12 are three individual capture compare channels that can perform compare or capture operations with regard to the contents of the T12 counter The capture functions are explained in Section 20 3 5 20 3 3 1 Compare Channels In Compare Mode see Figure 20 9 the three individual compare channels CC60 CC61 and CC62 can generate a three phase PWM pattern Counter Register Jna T12 1 gt Match 60 Match 61 Match 62 Compare Register Compare Register Compare Register CC60R CC61R CC62R Compare Shadow Compare Shadow Compare Shadow Register CC60SR Register CC61SR Register CC62SR CCU6_MCA05513 Figure 20 9 T12 Channel Comparators Each compare channel is connected to the T12 counter register via its individual equal to comparator generating a match signal when the contents of the counter matches the contents of the associated compare register Each channel consists of the comparator and a double register structure the actual compare register CC6xR feeding the comparator and an associated shadow register C
517. ode OFE to the host In both error cases the UART BSL routine awaits the actual block from the host again There is no flash protection thus the flash protection type error is removed for XC82x UART BSL does not check for validity of address of XRAM Flash it is to the user s responsibility to ensure that the DPTR of Flash XRAM is valid Table 6 3 gives a summary of the response codes to be sent back to the host by the uC after it receives each transfer block Table 6 3 Type of Response Codes Communication Status Response Code to the Host Successful 55 Block Type Error OFF Checksum Error OFE Table 6 4 shows a tabulated summary of the possible responses the device may transmit following the reception of a Header Data or EOT Block User s Manual 6 6 V1 0 2010 02 Cinfineon XC82x UART Boot Loader Table 6 4 Possible Responses for Various Block Types Mode Header Block Data Block EOT Block 0 Acknowledge Block Type Acknowledge Block Acknowledge Block Error Checksum Error Type Error Checksum Type Error Error Checksum Error 1 Acknowledge Block Type Error Checksum Error 2 Acknowledge Block Type Acknowledge Block Acknowledge Block Error Checksum Error Type Error Checksum Type Error Error Checksum Error 3 Acknowledge Block Type Error Checksum Error 4 Acknowledge Block Type Error Checksum Error 6 Acknowledge Block Type Error Checksum Error
518. ode the FNMIFLASH flag is cleared automatically and therefore need not be handled by users Table 22 9 Specifications of FLASH PROGRAM subroutine Subroutine BR FLASH PROGRAM User s Manual 22 7 V1 0 2010 02 BootROM User Routines V1 1 Cinfineon Boot ROM User Routines Table 22 9 Specifications of FLASH PROGRAM subroutine Input Flash WL aligned address to be programmed R6 of current Register Bank DPH R7 of current Register Bank R5 of current Register Bank IRAM start address for 32 byte Flash data 32 byte Flash data All interrupts including NMI must be disabled IENO EA 0 NMICON 00 SFR NMISR 00 Output PSW CY 0 Flash programming is successful 1 Flash programming is not successful DPTR is incremented by 20 2 Stack size required 12 Resource DPTR A used destroyed RO R2 R6 and R7 of current Register Bank 4 bytes 1 The last 5 LSB of the DPL is 0 for an aligned WL address for e g OOH 20H 40H 60H 80H AOH and EOH 2 DPTR is only incremented by 20 when PSW CY is 0 The second type of routine supports background programming BR FLASH BACKGROUND PROGRAM allows the user program code to continue execution after the programming routine is called User will wait until the Flash NMI event is generated bit FNMIFLASH in register NMISR is set and if enabled via NMIFLASH an NMI to the CPU is triggered to enter the Flash N
519. ode 0 is used to transfer a customer program from the host to the XRAM of the uC via serial interface The header block for this working mode has the following structure The Header Block Data Area 00 00 Header Mode 0 StartAddr StartAddr Block NotUsed Checksum Block High Low Length 1 byte 1 byte 1 byte 1byte 2 bytes Mode Data Description Start Addr High Low 16 bit Start Address which determines where to copy the received program codes in the XRAM Block_Length The length of the following Data Blocks or EOT Block at each transmission Not used 2 bytes these bytes are not used and will be ignored in Mode 0 User s Manual 6 9 V1 0 2010 02 Cinfineon Boot Loader Note The Block Length refers the whole length block type data area and checksum of the following transfer block Data Block or EOT Block For each transmission length of Data Block s and EOT Block should be the same Note Maximum length for Data Blocks when sending Header Block followed by 1 255 Data Blocks and finally end transmission with one EOT Block is 96 2 98 bytes Note Maximum length for EOT Blocks when sending one Header Block followed by one EOT Block each time only is 96 3 99 bytes After successfully receiving the Header Block the uC enters Mode 0 during which the program codes are transmitted from the host to the uC by Data Block s and EOT Bloc
520. odes 0 and 2 are fixed However while the baud rate in mode 0 can only be 2 the baud rate in mode 2 can be selected as either 64 or foc 432 depending on bit SMOD in the PCON register Bit SMOD acts as a double baud rate selector as shown in Equation 16 1 If SMOD 0 value after reset the baud rate is 1 64 of the input clock frequency fpc x If SMOD 1 the baud rate is 1 32 of foc 16 1 SMOD Mode 2 baud rate TX x fPCLK 16 5 2 UART Baud rate Generator The UART baud rate generator is used to generate the variable baud rate for the UART in modes 1 and 3 It has programmable 11 bit reload value 3 bit prescaler and 5 bit fractional divider The baud rate generator is clocked derived via a prescaler fp y from the input clock baud rate timer counts downwards and can be started or stopped through the baud rate control run bit BCON R Each underflow of the timer provides one clock pulse to the serial channel The timer is reloaded with the 11 bit BR VALUE stored in its reload User s Manual 16 9 V1 0 2010 02 UART V 1 6 Cinfineon UART register BG each time it underflows The duration between underflows depends on the n value in the fractional divider which can be selected by the bits BGL FD_SEL n times out of 32 the timer counts one cycle more than specified by BR_VALUE The prescaler is selected by the bits BCON BRPRE Register BG is the dual function Baud ra
521. ogramming ISP of the Flash memory is supported via the Boot ROM based Boot loader BSL allowing a blank microcontroller device mounted onto an application board to be programmed with the user code and also a previously programmed device to be erased then reprogrammed without removal from the board This feature offers ease of use and versatility for the embedded design ISP is supported through the microcontrollers serial interface UART which is connected to the personal computer host via the commonly available RS 232 serial cable The BSL mode is selected if the programmed BMI and BMI values match the corresponding values defined for the BSL mode after power on or hardware reset The BSL routine will first perform an automatic synchronization with the transfer speed baud rate of the serial communication partner personal computer host Communication between the BSL routine and the host is done via a transfer protocol information is sent from the host to the microcontroller in blocks with specified block structure and the BSL routine acknowledges the received data by returning a single acknowledge or error byte User can program erase or execute the Flash bank s The available working modes include Transfer user program from host to Flash Execute user program in Flash Erase Flash sector s Mass Erase of all Flash sectors User s Manual 4 11 V1 0 2010 02 Flash Memory V 0 1 Cinfineon nears Flash Memory 4 7 In Ap
522. ol Event Interrupt Node Interrupt Node Flag Vector Enable Bit Bit Address WDT Overflow NMICON NMIWDT NMISR FNMIWDT 73 8 2 4 Module Suspend Control The timer in WDT is by default suspended on entering debug mode The WDT can be allowed to run in debug mode by clearing the bit WDTSUSP in SFR MODSUSP to 0 Refer to Chapter 10 2 4 for the definition of register MODSUSP User s Manual WDT V1 0 8 3 V1 0 2010 02 Cinfineon Watchdog Timer 8 3 Functional Description The Watchdog Timer WDT is a 16 bit timer which is incremented by a count rate of 75 KHz clock This 16 bit timer is realized as two concatenated 8 bit timers The upper 8 bits of the WDT can be preset to a user programmable value via a watchdog service access in order to vary the watchdog expire time The lower 8 bits are reset on each service access Figure 8 1 shows the block diagram of the WDT unit WDT WDTREL Control Clear wor Low Low Byte TEMO cT Hian High Byte Overflow Time out Control amp ENWDT Window boundary control Figure 8 1 WDT Block Diagram If the WDT is enabled by setting WDTEN to 1 the timer is set to a user defined start value and begins counting up It must be serviced before the counter overflows Servicing is performed through refresh operation setting bit WDTRS to 1 This reloads the timer with the start value and normal operation continues r 75 KHz Oscillator 1
523. olled by its control register CON This register serves two purposes During programming SSC disabled by CON EN 0 it provides access to a set of control bits During operation SSC enabled by CON EN 1 it provides access to a set of status flags The shift register of the SSC is connected to both the transmit lines and the receive lines via the pin control logic Transmission and reception of serial data are synchronized and take place at the same time i e the same number of transmitted bits is also received Transmit data is written into the Transmit Buffer TB and is moved to the shift register as soon as this is empty An SSC master CON MS 1 immediately begins transmitting while an SSC slave CON MS 0 will wait for an active shift clock When the transfer starts the busy flag CON BSY is set and the Transmit Interrupt Request line TIR will be activated to indicate that register TB may be reloaded again When the programmed number of bits 2 8 has been transferred the contents of the shift register are moved to the Receive Buffer RB and the Receive Interrupt Request line RIR User s Manual 18 8 V1 0 2010 02 SSC V1 4 Cinfineon neers High Speed Synchronous Serial Interface will be activated If no further transfer is to take place TB is empty CON BSY will be cleared at the same time Software should not modify CON BSY as this flag is hardware controlled Note The SSC starts transmission and sets CON
524. olumns in case touch sense function is enabled also Time slice and active duration within time slice configurable for LED column Possibility to drive up to 8 LEDs per time slice column common cathode or common anode Shadow transfer of line pattern for LED column time slice Interrupt for each time slice Line and column pins controlled by SFR setting For the touchpad sensing function LEDTSCU provides features Upto 8 touchpad input turns Input pad turn controllable by software or fully by hardware round robin Pad oscillation control circuit with flexible configuration such as oscillation frequency and duration control e 8 bit counter For counting oscillations at pin Share configuration of time slice duration with LED function with configurable active duration within time slice Interrupt for each time slice time frame Pin overrule control for active touch sense function Note This chapter in several instances refer to the LED or touch sense pins e g pin pin TSIN x In all instances it refers to the user configured pin s where the alternate function bit field ALTSEL selects the LED touch sense function Refer to Section 19 7 for more elaboration User s Manual 19 1 V1 0 2010 02 LEDTSCU V 1 2 1 Cinfineon XC82x 19 2 System Information LED and Touch Sense Controller This section provides system information relevant to the LEDTSCU 19 2 1 Pinning Table 19 1 descr
525. ompare Unit 6 CCU6 Field Bits Type Description MCMP 5 0 rh Multi Channel PWM Pattern Bit field MCMP defines the output pattern for the multi channel mode If this mode is enabled by MODCTR MCMEN 1 the output state of all T12 related PWM outputs can be modified This bit field is O while IS IDLE 1 0 for output CC60 MCMP1 MCMOUT 1 for output COUT60 MCMP2 MCMOUT 2 for output CC61 MCMP3 MCMOUT 3 for output COUT61 MCMP4 MCMOUT 4 for output CC62 MCMP5 MCMOUT 5 for output COUT62 Og The output is set to the passive state A PWM generated by T12 or T13 are not taken into account 1g The output can be in the active state depending on the enabled PWM modulation signals generated by T12 T13 and the trap state rh Reminder Flag This flag indicates that the shadow transfer from MCMPS to MCMP has been requested by the selected trigger source It is cleared when the shadow transfer takes place or while MCMEN 0 Og A shadow transfer ST is not requested 1g A shadow transfer ST is requested but has not yet been executed because the selected synchronization condition has not yet occurred reserved returns 0 if read should be written with 0 User s Manual CCU6 V4 0 20 108 V1 0 2010 02 Cinfineon XC82x Capture Compare Unit 6 CCU6 MCMOUTH Multi Channel Mode Output Register High 9 R
526. on The XC800 Core supports access to slow memory by using wait cycle s Each wait cycle lasts one machine cycle i e two clock periods For example in case of a memory requiring one two wait state s the access time is increased by one machine cycle for every byte of opcode operand fetched Figure 2 2 shows the fetch execute timing related to the internal states and phases Execution of an instruction occurs at C1P1 For a 2 byte instruction the second reading starts at C1P1 Figure 2 2 a shows two timing diagrams for a 1 byte 1 cycle 1 x machine cycle instruction The first diagram shows the instruction being executed within one machine cycle since the opcode C1P2 is fetched from a memory without wait state The second diagram shows the corresponding states of the same instruction being executed over two machine cycles instruction time extended with one wait cycle inserted for opcode fetching from the flash memory Figure 2 2 b shows two timing diagrams for a 2 byte 1 cycle 1 x machine cycle instruction The first diagram shows the instruction being executed within one machine cycle since the second byte C1P1 and the opcode C1P2 are fetched from a memory without wait state The second diagram shows the corresponding states of the same instruction being executed over three machine cycles instruction time extended with one wait cycle inserted for each access to the flash memory In this case two wait cycles are inserted i
527. on Selected By P1 2 COL2 0 LED column 2 P1 ALTSELO P2 1g P1 ALTSEL1 P2 0g PO 6 COL2 1 LED column 2 PO ALTSELO P6 1g PO ALTSEL1 P6 0g PO ALTSEL2 P6 1 P1 3 COL3 0 LED column 3 P1 ALTSELO P3 1g P1 ALTSEL1 P3 0g P0 4 COL3 1 LED column 3 PO ALTSELO PA4 0 PO ALTSEL1 P4 1 PO ALTSEL2 PA 1g P1 4 COL4 LED column 4 P1 ALTSELO P4 1g P1 ALTSEL1 P4 0g P1 5 COL5 LED column 5 P1 ALTSELO P5 1 P1 ALTSEL1 P5 0 P1 5 COLA 0 Touch sense external pull up P1 ALTSELO P5 1g LED column A P1 ALTSEL1 P5 1 P0 6 COLA 1 Touch sense external pull up PO ALTSELO P6 0g LED column A PO ALTSEL1 P6 1g PO ALTSEL2 P6 1g PO 4 COLA 2 Touch sense external pull up PO ALTSELO P4 1g LED column A PO ALTSEL1 P4 1g PO ALTSEL2 PA 1 19 2 2 Clocking Configuration There are two constant clocks provided to the LED amp TSCU kernel FPCLK 48 MHz and SPCLK 8 MHz The kernel is mainly running on FPCLK 48 MHz The LEDTS counter can be configured to run on pre scaled clock generated from FPCLK or SPCLK The touch sense counter and corresponding logic is counting and processing pad oscillations on FPCLK If the LEDTSCU functionality is not required at all it can be completely disabled by gating off its clock input for maximal power reduction This is done by setting bit LTS_DIS in register PMCON 1 as described below The bit field PAGE of SCU PAGE register must be programmed be
528. on and Recovery 7 12 1 CCU Register Description 7 14 1 Power 7 16 1 Functional Description 7 17 1 Idle 7 17 1 Power Down Mode 7 17 1 Peripheral Clock Management 7 21 1 Power Management Register Description 7 23 1 SCU Register Mapping 7 25 1 Watchdog 8 1 1 4a societe ba d Rr gena 8 1 1 System Information 8 2 1 Reset effects 8 2 1 Clocking 8 2 1 Interrupt Events and Assignment 8 2 1 Module Suspend Control 8 3 1 Functional Description zie oer ad baad 8 4 1 Registers 8 7 1 User s Manual 1 3 V1 0 2010 02 Cinfineon 8 4 1 9 9 1 9 1 1 9 1 2 9 2 9 2 1 9 2 2 9 3 9 4 9 5 9 5 1 9 5 2 9 5 3 9 5 4 9 6 10 10 1 10 1 1 10 2 10 2 1 10 2 2 10 2 3 10 2 4 10 2 5 10 3 10 3 1 10 3 2 10 3 3 10 3 4
529. one This subroutine can be used in either of the following two cases The Flash bank where the code execution is taking place is not the same as the Flash bank that is targeted for programming The subroutine is called from XRAM 4 7 2 Flash Erasing Each call of the Flash erase subroutine allows the user to select for erase sector or acombination of sectors User s Manual 4 13 V1 0 2010 02 Flash Memory V 0 1 Cinfineon nears Flash Memory Before calling the Flash erase subroutine the user must ensure that R4 to R7 of the current register bank are set accordingly To select a sector for erase the bit corresponding to the sector in R4 to R7 must be set to 1 Sectors not to be erased must have their corresponding bits cleared to 0 If no or invalid inputs are provided PSW CY bit will be set and no programming will occur Two types of Flash erase subroutines are provided in the Boot ROM to erase the Flash Non background Flash erase subroutine see Section 4 7 2 1 Background Flash erase subroutine see Section 4 7 2 2 4 7 2 1 Non background Flash Erase Subroutine The first type of subroutine non background Flash erase waits until erasing is completed before allowing the user code to continue with its execution This type of routine is necessary for users who need to erase the Flash bank where the user code is in execution The Flash cannot be in both erase mode and read mode at the same time It ca
530. onous Serial Interface 18 3 5 Baud Rate Generation The serial channel SSC has its own dedicated 16 bit baud rate generator with 16 bit reload capability allowing baud rate generation independent of the timers Figure 18 5 shows the baud rate generator 16 Bit Reload Register f fus PEK Y 2 16 f MS_cLk max Ih Master Modes 6 2 f ss max N Slave Mode lt foo 4 Figure 18 5 SSC Baud rate Generator The baud rate generator is clocked with the module clock fiw The timer counts downwards Register BR is the dual function Baud rate Generator Reload register Reading BR while the SSC is enabled returns the contents of the timer Reading BR while the SSC is disabled returns the programmed reload value In this mode the desired reload value can be written to BR Note Never write to BR while the SSC is enabled The formulas below calculate either the resulting baud rate for a given reload value or the required reload value for a given baud rate Baud rate BR 1 CEGSBRS 1 9 Baud rate 18 1 lt BR gt represents the contents of the reload register taken as an unsigned 16 bit integer while baud rate is equal to fus cikjss 88 shown in Figure 18 5 The maximum baud rate that can be achieved when using a module clock of 24 MHz is 12 MBaud in Master Mode with
531. ontrol This bit field defines the divider ratio for the divider stage of the internal analog clock fang This clock provides the internal time base for the conversion and sample time calculations 003 1 3 Ols 1 4 x fapcA 106 1 5 X fapca 11g anci 1 6 x fapca default DW Data Width This bitfield defines how many bits are converted for the result Og The result is 10 bits wide default 1g result is 8 bits wide ANON Analog Part Switched On This bit enables the analog part of the ADC module and defines its operation mode Og analog part is switched off and conversions are not possible To achieve minimal power consumption the internal analog circuitry is in its power down state and the generation of fang is stopped 1g The analog part of the ADC module is Switched on and conversions are possible The automatic power down capability of the analog part is disabled 1 0 Reserved Returns 0 if read should be written with 0 The Global Status Register indicates the current status of a conversion ADC GLOBSTR Global Status Register Reset Value 00 RMAP 0 PAGE 0 7 6 5 4 3 2 1 0 0 CHNR 0 SAMPLE BUSY r rh r rh rh User s Manual 21 15 V1 0 2010 02 ADC V2 1 Cinfineon XC82x Analog to Digital Converter Field Bits Type Description BUSY rh Analog Part Busy This bit indicates
532. ontrols whether the source signal for the sampling of the Hall input pattern selected by HSYNC is delayed by the Dead Time Counter 0 0s bypass is not active Dead Time Counter 0 is generating a delay after the source signal becomes active 1g bypass is active Dead Time Counter 0 is not used for a delay User s Manual CCU6 V4 0 20 56 V1 0 2010 02 Cinfineon Capture Compare Unit 6 CCU6 20 3 9 3 Timer Control Registers Register TCTROL H controls the basic functionality of both timers T12 and T13 Note A write action to the bit fields T12CLK or T12PRE is only taken into account while the timer T12 is not running T12R 0 A write action to the bit fields T13CLK or T13PRE is only taken into account while the timer T13 is not running T13R 0 TCTROL Timer Control Register 0 Low Reset Value 00 RMAP 0 PAGE 1 7 6 5 4 3 2 1 0 CTM CDIR STE12 T12R T12PRE T12CLK rw rh rh rh rw rw Field Bits Type Description T12CLK 2 0 rw Timer T12 Input Clock Select Selects the input clock for timer T12 that is derived from the peripheral clock according to the equation T12CLK fro fece 12 000g fr12 fece 0016 fece 2 010g fro fece 4 011g 8 100 5 fece 16 101g fy fece 32 110 frio fece 64 111g 2 fece 128 T12PRE 3 rw Timer T12 Prescaler Bit In order to support higher clock frequencies an additional prescale
533. or external power supply of 5 0V has occurred FNMIECC 6 rwh ECC NMI Flag 0 No ECC error has occurred 1 ECC error has occurred 0 7 r Reserved Returns 0 if read should be written with 0 Note NMISR register can only be cleared by software or reset to the default value after the Power On Reset Its value is retained on any other resets This allows the cause of the previous NMI to be checked User s Manual Interrupt System V 2 3 3 9 29 V1 0 2010 02 Cinfineon Interrupt System 9 5 4 Interrupt Priority Registers Each interrupt node can be individually programmed to one of the four priority levels available Two pairs of Interrupt Priority Registers are available to program the priority level of the each interrupt vector The first pair of Interrupt Priority Registers are SFRs IP and IPH The second pair of Interrupt Priority Registers are SFRs IP1 and IPH1 The corresponding bits in each pair of Interrupt Priority Registers select one of the four priority levels as shown in Table 9 4 Table 9 4 Interrupt Priority Level Selection IPH x IPH1 x IP x IP1 x Priority Level 0 0 Level 0 lowest 0 1 Level 1 1 0 Level 2 1 1 Level 3 highest Note NMI always has the highest priority above Level 3 it does not use the priority level selection shown in Table 9 4 IP Interrupt Priority Register B8 Reset Valu
534. orking mode If the uC receives an incorrect header block the UART BSL routine sends instead of an Acknowledge code a checksum or block error code to the host and awaits the header block again In this case the host may react by re sending the header block or by releasing a message to the customer 6 2 2 1 Receiving the Header Block The header block is always the first transfer block to be sent by the host during one data communication process It contains the working mode number and special information on the related mode referred to as mode data The general structure of a Header Block is shown below User s Manual 6 8 V1 0 2010 02 Cinfineon Boot Loader Block Type Data Area 00 Mode Mode Data 1 byte Header Block 1 byte 5 bytes Description 00 The block type which marks the block as a Header Block Mode The working mode The implemented working modes are 00 Mode0 Program customer code to XRAM 01 Mode1 Execute customer code in XRAM 02 Mode2 Program customer code to FLASH 03 Mode3 Execute customer code in FLASH 04 Mode4 Erase customer code in FLASH sector s 06 Mode6 Program 4 bytes of USER ID ModeA Get 4 bytes Information Mode Data Five bytes of special information which are necessary to activate corresponding working mode e Checksum The checksum of the header block 6 2 2 2 ModeO0 Program customer code to XRAM M
535. ot ROM 3 1 21 25 Boot ROM operating mode 5 4 Queued Source 21 18 Boot Loader Mode 5 4 Reference Selection 21 45 OCDS mode 5 5 User mode diagnostic 5 4 User s Manual L 1 V1 0 2010 02 Cinfineon XC82x User mode productive 5 4 Boot loader 4 6 4 11 5 4 Brownout reset 7 7 Buffer mechanism 4 3 CCU6 Block Diagram 20 3 Hall Sensor Mode 20 90 Interrupt Handling 20 110 Multi Channel Mode 20 87 Registers Keyword Index T12DTCL 20 49 T12H 20 43 T12L 20 43 T12MSELH 20 55 T12MSELL 20 55 T12PRH 20 44 T12PRL 20 44 T13H 20 79 T13L 20 79 T13PRH 20 81 T13PRL 20 81 TCTROH 20 59 CC63RH 20 83 CC63RL 20 83 CC63SRH 20 84 CC63SRL 20 84 CC6xRH 20 46 CC6xRL 20 46 CC6xSRH 20 47 CC6xSRL 20 47 CMPMODIFH 20 54 CMPMODIFL 20 53 CMPSTATL 20 51 20 52 IENL 20 120 20 121 INPH 20 125 INPL 20 124 ISL 20 112 20 113 ISRL 20 118 ISSL 20 116 MCMCTR 20 104 MCMOUTH 20 109 MCMOUTL 20 107 MCMOUTSH 20 106 MCMOUTSL 20 106 MODCTRH 20 99 MODCTRL 20 98 Offset addresses 20 5 Overview 20 4 PISELOH 20 128 PISELOL 20 127 PISEL2 20 129 PSLR 20 103 T12DTCH 20 49 User s Manual TCTROL 20 57 TCTR2H 20 63 TCTR2L 20 61 TCTR4H 20 65 TCTR4L 20 64 TRPCTRH 20 101 TRPCTRL 20 100 T12 20 17 Capture Modes 20 37 Compare Mode 20 25 Counting Scheme 20 21 Dead Time Generation 20 32 Hysteresis like Control Mode 20 31 Output Modulation and Level Se lection 20 35 Shadow Register Transfer 20 41 T13 20 67 Compare Mode 20 74 Countin
536. ote EXICONO EXINTO 11 cannot be used to wake up from power down mode The EXINTO wake up source is enabled by PMCONO EWS Bit MODPISEL1 EXINTOIS can be used for the EXINTO input pin selection The wake up with reset or without reset is selected by bit PMCONO WKSEL If bit WKSEL was set to 1 before entering power down mode the system will execute a reset sequence similar to the power on reset sequence Therefore all port pins are put into their reset state and will remain in this state until they are affected by program execution If bit WKSEL was cleared to 0 before entering power down mode a fast wake up sequence is used The port pins continue to hold their state which was valid during power down mode until they are affected by program execution The wake up from power down without reset using EXINTO wake up source undergoes the following procedure 1 In power down mode EXINTO pin must be held at the inactive level 2 Power down mode is exited when EXINTO pin goes active for at least 100 ns 3 The main voltage regulator is switched on and takes approximately 150 us to become stable User s Manual 7 19 V1 0 2010 02 Cinfineon System Control Unit 4 The on chip oscillator is started Typically the on chip oscillator takes approximately 10 us to stabilize 5 Subsequently the FLASH will enter ready to read mode This does not require the typical 160 us as is the case for the normal reset The timing for this part c
537. ouch sense function is active in the last time slice of a time frame Refer to Section 19 3 and Section 19 4 for more details on time slice allocation and configuration TS counter input Input high threshold ts extended l Input high threshold l pin oscillation Input high threshold Input low threshold Figure 19 4 Pin Low Level Extension Function The pad oscillation is enabled on pad with valid turn for configurable duration A compare value provides to adjust the duty cycle within the time slice when the pad oscillation is enabled TS counter is counting The pad oscillation is enabled only on compare match till the end of the time slice For 10096 duty cycle pad oscillation enable in time slice the compare value shall be set to 00 Setting the compare value to FF results in no pad oscillation in time slice The time slice interrupt and or time frame interrupt may be enabled as required for touch sense control User s Manual 19 12 V1 0 2010 02 LEDTSCU V 1 2 1 Cinfineon LED Touch Sense Controller 19 5 1 Finger Sensing When a finger is placed on the sensor pad it increases the pad capacitance and frequency of oscillation on pad is reduced The pad oscillation frequency without finger is typically expected in the approximate range 0 25 MHz to 0 5 MHz With finger on the sensor the pad oscillation frequency is typically expected in the approximate
538. out of range comparator ADC_CORC Configure Out Of Range Comparator Register D2 Reset Value 00 RMAP 0 PAGE 4 7 6 5 4 3 2 1 0 CNF7 CNF6 CNF5 CNF4 CNF3 CNF2 CNF1 CNFO rw rw rw rw rw rw rw rw Field Bits Type Description CNFx x rw Out of Range Comparator Flag x x 0 7 Og Detect voltage lower than Vddp at analog input pin 1 Detect voltage higher than at analog input pin Note Bit 4 7 are only applicable for devices that have 8 ADC channels For channels not implemented these bits should be treated as Reserved bits of type f which returns 0 if read and should be written with 0 User s Manual 21 59 V1 0 2010 02 ADC V2 1 Cinfineon Analog to Digital Converter The bit fields in these registers indicates if a voltage out of range have occured for the corresponding analog input channels If a voltage out of range have occured it will be latched to 1 in this register The event flag can be cleared by writing a 0 to this register ADC_LORC Latched Out Of Range Event Register D2 Reset Value 00 RMAP 0 PAGE 0 7 6 5 4 3 2 1 0 LORE7 LORE6 LORE5 LORE4 LORE3 LORE2 LORE1 LOREO rwh rwh rwh rwh rwh rwh rwh rwh Field Bits Type Description LOREx x rwh Latched Out of Range Event x x 0 7 This bit defines which analog input channel voltage out of range event have occured The LORE bit is
539. outine This routine allows application software to configure UART settings upon reception of a synchronization byte from the host User application would block once this subroutine is called throughout reception of synchronization byte baudrate calculation and transmission of response byte The protocol of the auto baud is described in Figure 6 1 while the port pins used in the auto baud are defined in Table 6 1 User has to take care of the clock frequency used and program the BCON BGSEL SFR field bit according to their desired auto baud rate User s Manual 22 5 V1 0 2010 02 BootROM User Routines V1 1 Cinfineon Boot ROM User Routines Note Clock Frequency and BGSEL SFR field bit are not modified in this routine These field bits can be modified by user first before calling this user routine for desired baud rate and clock frequency Note SPD setting is not disabled upon entering this user routine User must ensure that there are no conflicts in the port pins used by SPD and auto baud Note It is highly recommended that all interrupts should be disabled before calling this routine as not to interfere with the auto baud detection and calculation Table 22 7 Specifications of BR AUTO BAUD subroutine Subroutine BR AUTO BAUD Input BCON BGSEL SFR field bit to be set accordingly Output This subroutine configures port pins to input output RXD TXD and baud rate for UART based on autobaud value of 005555 or 0055AA
540. ower priority conversion cancel inject repeat mode or be converted immediately after the currently running conversion wait for start mode If the target result register has not been read a conversion can be deferred wait for read mode User s Manual 21 7 V1 0 2010 02 ADC V2 1 Cinfineon Analog to Digital Converter Input Channel Selection The analog input multiplexer selects one of up to 8 analog inputs CHO CH7 to be converted Two sources can select a linear sequence or an arbitrary sequence The priorities of these sources can be configured Note Not all analog input channels are necessarily available in all packages due to pin limitations Please refer to the implementation description in Section 21 1 Conversion Control Conversion parameters such as sample phase duration can be configured in the input classes The input channels can thus be adjusted to the type of sensor or other analog sources connected to the ADC Analog Digital Converter The selected input channel is converted to a digital value by first sampling the voltage on the selected input and then generating the selected number of result bits Result Handling The conversion results of each analog input channel can be directed to one of 4 result registers to be stored there A result register can be used by a group of channels or by a single channel The wait for read mode avoids data loss due to result overwrite by blocking a co
541. p View 1 3 Pin Definitions and Functions After reset all pins are configured as input with one of the following e Pull up device enabled only PU Pull down device enabled only PD High impedance with both pull up and pull down devices disabled Hi Z The functions and default states of the XC82x external pins are provided in Table 1 1 User s Manual 1 5 V1 0 2010 02 System Architecture V1 0 Cinfineon XC82x Introduction Table 1 1 Pin Definitions and Functions for XC82x Symbol Pin Type Reset Function Number State DSO20 TSSOP16 PO Port 0 Port 0 is a bidirectional general purpose I O port It can be used as alternate functions for LEDTSCU Timer 0 1 and 2 SSC CCU6 IIC SPD and UART P0 0 15 12 Hi Z T20 Timer 2 Input T13HR_1 CCU6 Timer 13 Hardware Input MTSR_2 SSC Master Transmit Output Slave Receive Input MRST_3 SSC Master Receive Input T12HR 0 CCU6 Timer 12 Hardware Run Input CCPOSO 0 CCU6 Hall Input 0 TSINO Touch sense Input 0 LINEO LED Line 0 COUT61 1 Output of Capture Compare Channel 1 1 16 13 Hi Z 1700 Timer 0 Input CC61 1 Input Output of Capture Compare channel 1 MTSR 3 SSC Slave Receive Input MRST 2 SSC Master Receive Input Slave Transmit Output T13HR 0 CCU6 Timer 13 Hardware Run Input CCPOS1 0 CCU6 Hall Input 1 TSIN1 Touch sense Input 1 LINE1 LED Line 1 User s Manual 1 6 V1 0 2010 02 System Architecture V1 0 Cinfineon XC82x
542. pare Value 0 Figure 20 26 Single Shot Operation of Timer T13 User s Manual CCU6 V4 0 20 71 V1 0 2010 02 Cinfineon Capture Compare Unit 6 CCU6 20 4 2 3 Synchronization to T12 Timer T13 can be synchronized to a T12 event Bit fields T13TEC and T13TED select the event that is used to start Timer T13 The selected event sets bit T13R via HW and T13 starts counting Combined with the Single Shot mode this feature can be used to generate a programmable delay after a T12 event Figure 20 27 shows an example for the synchronization of T13 to a T12 event Here the selected event is a compare match compare value 2 while counting up The clocks of T12 and T13 can be different other prescaler factor the figure shows an example in which T13 is clocked with half the frequency of T12 Compare Match Period Value T12 Count Compare Value Zero T13R T13 Count CCU6_MCT05530 Figure 20 27 Synchronization of T13 to T12 Compare Match Bit field T13TEC selects the trigger event to start T13 automatic set of T13R for synchronization to T12 compare signals according to the combinations shown in Table 20 11 Bit field T13TED additionally specifies for which count direction of T12 the selected trigger event should be regarded see Table 20 12 User s Manual 20 72 V1 0 2010 02 CCU6 V4 0 Cinfineon Capture Compare Unit 6 CCU6 Table 20 11 112 Trigger Event Select
543. pare Unit 6 CCU6 20 3 5 T12 Capture Modes Each of the three channels of the T12 Block can also be used to capture T12 time information in response to an external signal CC6xIN In capture mode the interrupt event CC6x R is detected when a rising edge is detected at the input CC6xIN whereas the interrupt event CC6x F is detected when a falling edge is detected There are a number of different modes for capture operation In all modes both of the registers of a channel are used The selection of the capture modes is done via the T12MSELL MSEL6x bit fields and can be selected individually for each of the channels Table 20 8 Capture Modes Overview MSEL6x Signal Active Edge CC6nSR Stored in 12 Stored in 0100 1 CC6XIN Rising CC6xR CC6xIN Falling CC6xSR 0101 2 CC6XIN Rising CC6xR CC6xSR 0110 3 CC6XIN Falling CC6xR CC6xSR 0111 4 CC6xIN Any CC6xR CC6xSR Figure 20 19 illustrates Capture Mode 1 When a rising edge 0 to 1 transition is detected at the corresponding input signal CC6xIN the current contents of Timer T12 are captured into register CC6xR When a falling edge 1 to 0 transition is detected at the input signal CC6xIN the contents of Timer T12 are captured into register CC6xSR Edge Kis Counter Register Rising Capture Mode CC6xIN Doo Selection Set State Bit Shadow Register CC6
544. per 8 bits of bit field CCV during a shadow transfer User s Manual 20 84 V1 0 2010 02 CCU6 V4 0 Cinfineon Capture Compare Unit 6 CCU6 20 5 Trap Handling The trap functionality permits the PWM outputs to react on the state of the input signal This functionality can be used to switch off the power devices if the trap input becomes active e g to perform an emergency stop The trap handling and the effect on the output modulation are controlled by the bits in the trap control register TRPCTRL TRPCTRH The trap flags TRPF and TRPS are located in register ISH and can be set cleared by SW by writing to registers ISSH and ISRH Figure 20 33 gives an overview on the trap function The Trap Flag TRPF monitors the trap input and initiates the entry into the Trap State The Trap State Bit TRPS determines the effect on the outputs and controls the exit of the Trap State When a trap condition is detected CTRAP 0 and the input is enabled TRPPEN 1 both the Trap Flag TRPF and the Trap State Bit TRPS are set to 1 trap state active The output of the Trap State Bit TRPS leads to the Output Modulation Blocks for T12 and for T13 and can there deactivate the outputs set them to the passive state Individual enable control bits for each of the six T12 related outputs and the T13 related output facilitate a flexible adaptation to the application needs There are a number of different ways to exit th
545. pin can source sink 20 mA nominal This means per LED drive capability is limited to 2 5 mA when direct drive eight LEDs by column In all usage the total current to direct drive source or sink all eight LEDs at one time must not exceed the specified maximum current for all pins Xl For stronger LED drive capability use of external transistors will be required User s Manual 19 10 V1 0 2010 02 LEDTSCU V 1 2 1 Cinfineon LED and Touch Sense Controller 19 5 Touchpad Sensing Figure 19 3 shows the pin oscillation control unit which is actually integrated with the standard GPIO pad An active pad turn pad_turn_x is defined for the touch sense input pin TSIN x as the duration within the touch sense time slice where the TS counter is counting COLA Xk enable extemal pulup enable pad oscilator 7127 ma Pa tum num pad tum x b t t E Y counter rese l 1 8 bit TS counter Sensor Pad d Is exended standard IO pad e ae Figure 19 3 Touch Sense Oscillator Control Circuit The 8 bit TS counter counts the number of oscillations It can only be written when there is no active pad turn The counter may be enabled for automatic reset to 00 on each start of a new pad turn Bit TSCTROVF indicates that the counter has overflowed Alternatively it can be configured such that the TS counter stops counting in current ti
546. pler and faster Consequently this mechanism significantly improves the performance of short interrupt routines The XC82x supports local address extension for Parallel Ports Analog to Digital Converter ADC e Capture Compare Unit 6 CCU6 System Control Registers User s Manual 3 8 V1 0 2010 02 Memory Organization V 0 1 Cinfineon Memory Organization 3 4 2 1 Page Register The page register has the following definition MOD_PAGE Page Register for module MOD Reset Value 00 7 6 5 4 3 2 1 0 OP STNR 0 PAGE w w mo Field Bits Type Description PAGE 2 0 rw Page Bits When written the value indicates the new page When read the value indicates the currently active page STNR 5 4 Storage Number This number indicates which storage bit field is the target of the operation defined by bit field OP If OP 10g the contents of PAGE are saved in STx before being overwritten with the new value If OP 115 the contents of PAGE are overwritten by the contents of STx The value written to the bit positions of PAGE is ignored 00 STO is selected 01 ST1is selected 10 ST2is selected 11 ST3is selected User s Manual 3 9 V1 0 2010 02 Memory Organization V 0 1 Cinfineon Memory Organization Field Bits Type Description OP 7 6 w Operation OX Manual page mode The value of STNR is ignored and PAGE is directly written 10 New page
547. plication Figure 23 10 Timing Diagram Padline 0 used for the example above to show the interaction between PadFlags PadResult PadError and PDC The trip point LowTrip can be fixed or as in this illustration hysteresis can be added whenever a padflag is set by changing the user input subtraction m The PDC gets pre loaded with its time out value on the first PadFlag being set In any subsequent PadTurn this counter decrements until either it reached O or until all PadFlags are cleared where it is then set to 0 If during a PadTurn the last remaining set PadFlag gets cleared the PDC gets set to 0 on exit of the function This can happen either when a pad is touched too briefly short count or when the last pad is released before PDC times out A corner case can arise when the user does not clear the error or result before another pad is touched In such a situation it is possible that more than two bits in the result can show up if for example the first valid result was a combination pad being touched and the next one touched was a single pad whose padline was not part of the previous combination pad PDC is decremented once every 1 period All Enabled Pads Accumulated Count Period even if dual padflags maybe set User s Manual 23 34 V1 0 2010 02 ROM Library V0 5 Cinfineon ROM Library Time Slice Time Frame and Period Definition There is a Time Slice Time Frame and Periods naming convention There is ha
548. plication Programming In some applications the Flash contents may need to be modified during program execution In Application Programming IAP is supported so that users can program or erase the Flash memory from their Flash user program by calling some subroutines in the Boot ROM see Figure 4 6 and Chapter 22 The Flash subroutines will first perform some checks and an initialization sequence before starting the program or erase operation A manual check on the Flash data is necessary to determine if the programming or erasing was successful by using the MOVC instruction to read out the Flash contents Other special subroutines include aborting the Flash erase operation and checking the Flash bank ready to read status Boot ROM special Flash program erase subroutines user program Flash NMI service routine RETI instruction Flash NMI Figure 4 6 Flash Program Erase Flow User s Manual 4 12 V1 0 2010 02 Flash Memory V 0 1 Cinfineon nears Flash Memory 4 7 1 Flash Programming Each call of the Flash program subroutine allows the programming of 32 bytes of data into the selected wordline WL of the Flash bank Before calling this subroutine the user must ensure that the 32 byte WL contents are stored incrementally in the IRAM starting from the address specified in R5 of the current register bank In addition the input DPTR must conta
549. priority handling of pending interrupt request for interrupt nodes of structure 2 1 CPU acknowledge of interrupt on vectoring to the service routine will clear the pending interrupt request 2 Any event occurring and enabled for interrupt will set the pending interrupt request 3 on clearing of all interrupt enabled status flags will clear the pending interrupt request 9 3 Interrupt Handling The interrupt request signals are sampled at phase 2 in each machine cycle The sampled requests are then polled during the following machine cycle If one interrupt node request was active at phase 2 of the preceding cycle the polling cycle will find it User s Manual 9 12 V1 0 2010 02 Interrupt System V 2 3 3 Cinfineon Interrupt System and the interrupt system will generate a LCALL to the node s service routine provided this hardware generated LCALL is not blocked by any of the following conditions 1 An interrupt of equal or higher priority is already in progress 2 The current polling cycle is not in the final cycle of the instruction in progress 3 The instruction in progress is or any write access to registers IENO IEN1 or IP IPH or IP1 IPH1 Any of these three conditions will block the generation of the LCALL to the interrupt service routine Condition 2 ensures that the instruction in progress is completed before vectoring to any service routine Condition 3 ensures that if the instruction in progress is RETI o
550. programming of critical data from to the Flash bank can be performed Hence erase operations on User s Manual 4 14 V1 0 2010 02 Flash Memory V 0 1 Cinfineon nears Flash Memory selected Flash bank sector s may be aborted to allow data in other sectors to be read or programmed To minimize the effect of aborted erase on the Flash data retention cycling and to guarantee data reliability the following points must be noted for each Flash bank An erase operation cannot be aborted earlier than 5 ms after it starts Maximum of two consecutive aborted erase without complete erase in between are allowed on each sector Complete erase operation approximately 100 ms is required and initiated by user program after a single or two consecutive aborted erase as data in relevant sector s is corrupted For the specified cycling time each aborted erase constitutes one program erase cycling Maximum allowable number of aborted erase for each Flash sector during lifetime is 2500 The Flash erase abort subroutine call cannot be performed anytime within 5 ms after the erase operation has started This is a strict requirement that must be ensured by the user Otherwise the erase operation cannot be aborted Once exited from this subroutine user can call the Flash Read Mode Status subroutine to check if the abort erase operation has been completed When the selected bank is already in Read Mode it indicates that the abort erase operation ha
551. programming with automatic page saving The value written to the bit positions of PAGE is stored In parallel the previous contents of PAGE are saved in the storage bit field STx indicated by STNR 11 Automatic restore page action The value written to the bit positions PAGE is ignored and instead PAGE is overwritten by the contents of the storage bit field STx indicated by STNR 0 3 r Reserved Returns 0 if read should be written with 0 3 4 3 Bit Addressing SFRs that have addresses the form of 1XXXX000 e g 80 88 90 8 are bitaddressable User s Manual 3 10 V1 0 2010 02 Memory Organization V 0 1 Cinfineon Memory Organization 3 4 4 Bit Protection Scheme The bit protection scheme prevents direct software writing of selected bits i e protected bits using the PASSWD register When the bit field MODE is 11g writing 10011 to the bit field PASS opens access to writing of all protected bits and writing 10101 to the bit field PASS closes access to writing of all protected bits In both cases the value of the bit field MODE is not changed even if PASSWD register is written with 98 or It can only be changed when bit field PASS is written with 11000 for example writing DO to PASSWD register disables the bit protection scheme Note that access is opened for maximum 32 CCLKs if the close access password is not written If open access password is wri
552. ption PAGE 3 0 rwh_ Page Bits When written the value indicates the new page address When read the value indicates the currently active page addr y x 1 STNR 5 4 w Storage Number This number indicates which storage bit field is the target of the operation defined by bit OP If OP 10g the contents of PAGE are saved in STx before being overwritten with the new value If OP 115 the contents of PAGE are overwritten by the contents of STx The value written to the bit positions of PAGE is ignored 00 STOis selected 01 ST1 is selected 10 ST2is selected 11 ST3 is selected User s Manual 7 25 V1 0 2010 02 Cinfineon XC82x System Control Unit Field Bits Description OP 7 6 w Operation OX Manual page mode The value of STNR is ignored and PAGE is directly written 10 New page programming with automatic page saving The value written to the bit positions of PAGE is stored In parallel the former contents of PAGE are saved in the storage bit field STx indicated by STNR 11 Automatic restore page action The value written to the bit positions PAGE is ignored and instead PAGE is overwritten by the contents of the storage bit field STx indicated by STNR The addresses of the system control SFRs are listed in Table 7 5 Not listed in the tables is the register SYSCONO which can be accessed in both standard non mapped and mapped address of 8F
553. quiring one two wait state s One machine cycle comprises two CCLK clock cycles Table 2 1 Instruction Table Mnemonic Hex Code Bytes Machine Machine Cycles Cycles one wait state no wait state ARITHMETIC ADD A Rn 28 2F 1 1 2 ADD 25 2 1 3 ADD A Ri 26 27 1 1 2 ADD A data 24 2 1 3 ADDC A Rn 38 3F 1 1 2 ADDC A dir 35 2 1 3 ADDC A Ri 36 37 1 1 2 ADDC A data 34 2 1 3 SUBB A Rn 98 9F 1 1 2 SUBB A dir 95 2 1 3 SUBB A Ri 96 97 1 1 2 SUBB A data 94 2 1 3 INCA 04 1 1 2 INC Rn 08 0F 1 1 2 INC dir 05 2 1 3 INC Ri 06 07 1 1 2 DECA 14 1 1 2 DEC Rn 18 1F 1 1 2 DEC dir 15 2 1 3 DEC Ri 16 17 1 1 2 INC DPTR A3 1 2 2 User s Manual 2 10 V1 0 2010 02 XC800 Core V 1 0 2 Cinfineon 800 2 1 Instruction Table cont d Mnemonic Hex Code Bytes Machine Machine Cycles Cycles one wait state no wait state MUL AB A4 1 4 4 DIV AB 84 1 4 4 DAA D4 1 1 2 LOGICAL ANL A Rn 58 5F 1 1 2 ANL A dir 55 2 1 3 ANL A Ri 56 57 1 1 2 ANL A data 54 2 1 3 ANL dir A 52 2 1 3 ANL dir data 53 3 2 5 ORL A Rn 48 4F 1 1 2 ORL A dir 45 2 1 3 ORL A Ri 46 47 1 1 2 ORL A data 44 2 1 3 ORL dir A 42 2 1 3 ORL dir data 43 3 2 5 XRL A Rn 68 6F 1 1 2 XRL A dir 65 2 1 3 XRL A
554. r for Channel CC61 Low Type mh FDH CCU6_CC61SRH Reset 004 Bit Fie CC61SH Capture Compare Shadow Register for Channel CC61 High Type rwh FEH CCU6_CC62SRL Reset 004 Bit Fie CC62SL Capture Compare Shadow Register for Channel CC62 Low Type CCU6_CC62SRH Reset 00 Bit Fie CC62SH Capture Compare Shadow Register for Channel CC62 High Type rwh RMAP 0 PAGE 1 DAY CCU6_CC63RL Reset 00 Bit Fie CC63VL Capture Compare Register for Channel CC63 Low Type rh By CCU6_CC63RH Reset 004 Bit Fie CC63VH Capture Compare Register for Channel CC63 High Type rh PCy CCU6_T12PRL Reset 004 Bit Fie T12PVL Timer T12 Period Register Low Type rwh User s Manual 3 27 V1 0 2010 02 Memory Organization V 0 1 Infineon XC82x Memory Organization Table 3 9 CCU6 Register Overview cont d Addr Register Name Bit 7 6 5 4 3 2 1 0 9DH CCU6_T12PRH Reset 004 Bit Fie T12PVH Timer T12 Period Register High Type rwh CCU6_T13PRL Reset 004 Bit Fie T13PVL Timer T13 Period Register Low Type rwh Fy CCU6_T13PRH Reset 004 Bit Fie T13PVH Timer T13 Period Register High Type rwh Mu CCU6 T12DTCL Reset 00 Bit Fie DTM Dead Time Control Register for Timer T12 Low Type ASH CCU6_T12DTCH Reset 004 Bit Fie 0 DTR2 DTR1 0 DT
555. r 1 ET1 XINTR4 00234 UART ES XINTR5 002B Timer2 ET2 LIN User s Manual 9 8 V1 0 2010 02 Interrupt System V 2 3 3 Cinfineon XC82x Interrupt System Table 9 1 Interrupt Vector Address cont d Interrupt Vector Assignment for XC82x Enable Bit SFR Node Address XINTR6 0033 ADC EADC IEN1 XINTR7 003B SSC ESSC XINTR8 0043 External Interrupt 2 EX2 MDU XINTR9 004B External Interrupt 3 EXM External Interrupt 4 External Interrupt 5 External Interrupt 6 RTC Interrupt XINTR10 0053 CCU6 SRO ECCIPO XINTR1 1 005B CCU6 SR1 ECCIP1 LEDTSCU Time Frame XINTR12 0063 CCU6 SR2 ECCIP2 XINTR13 006B CCU6 SR3 ECCIP3 LEDTSCU Time Slice 9 1 2 Interrupt Source and Priority An interrupt that is currently being serviced can only be interrupted by a higher priority interrupt but not by another interrupt of the same or lower priority Hence an interrupt of the highest priority cannot be interrupted by any other interrupt request If two or more requests of different priority levels are received simultaneously the request with the highest priority is serviced first If requests of the same priority are received simultaneously an internal polling sequence determines which request is serviced first Thus within each priority level there is a second priority structure determined by the polling sequence as shown in Table 9 2 Table 9 2 Priority Structure
556. r SS_CLK Only the device selected for master operation generates and outputs the shift clock on line MS_CLK Since all slaves receive this clock their pin SCLK must be switched to input mode The output of the master s shift register is connected to the external transmit line which in turn is connected to the slaves shift register input The output of the slaves shift register is connected to the external receive line in order to enable the master to receive the data shifted out of the slave The external connections are hard wired the function and direction of these pins is determined by the master or slave operation of the individual device Note The shift direction shown in the figure applies for MSB first operation as well as for LSB first operation When initializing the devices in this configuration one device must be selected for master operation while all other devices must be programmed for slave operation Initialization includes the operating mode of the device s SSC and also the function of the respective port lines User s Manual 18 10 V1 0 2010 02 SSC V1 4 Cinfineon neers High Speed Synchronous Serial Interface Master Device 1 Device 2 Slave Shift Register Shift Register Figure 18 3 SSC Full Duplex Configuration The data output pins MRST of all slave devices are connected together onto the one receive line in the configuration shown in Figure 18 3 During a transfer each slave shifts
557. r a reset the CPU will always start by executing the Boot ROM code which occupies the program memory address space 0000 1FFF The Boot ROM start up procedure will first switch the address space for the Boot ROM to C000 DFFF Then remaining Boot ROM start up procedure will be executed from COOX This includes checking the programmed BMI value to enter the selected Boot ROM operating modes The memory organization of the XC82x shown in this document is after the Boot ROM address switch where the different operating modes are executed 5 2 1 User Mode Productive If the User mode productive is selected the Boot ROM will jump to program memory address 0000 to execute the user code in the Flash memory In this mode the content in the Flash memory are protected from external access This is the normal operating mode of the XC82x 5 2 2 User Mode Diagnostic If the User mode diagnostic is selected the Boot ROM will jump to program memory address 0000 to execute the user code in the Flash memory This is similar to the user mode productive described in Section 5 2 1 with the addition that the specified SPD port is automatically configured to allow hot attach 5 2 3 Boot Loader Mode If the Boot loader BSL mode is selected the software routines of the BSL located in the Boot ROM will be executed allowing the XRAM and Flash memory to be programmed erased and executed Refer to the UART BSL chapter for the different BSL
558. r any write access to registers IENO IEN1 or IP IPH or IP1 IPH1 then at least one more instruction will be executed before any interrupt is vectored to this delay guarantees that changes of the interrupt status can be observed by the CPU The polling cycle is repeated with each machine cycle and the values polled are the values that were present at phase 2 of the previous machine cycle Note that if any interrupt flag is active but its node interrupt request was not responded to for one of the conditions already mentioned and if the flag is no longer active at a later time when servicing the interrupt node the corresponding interrupt source will not be serviced In other words the fact that the interrupt flag was once active but not serviced is not remembered Every polling cycle interrogates only the pending interrupt requests The processor acknowledges an interrupt request by executing a hardware generated LCALL to the corresponding service routine In some cases hardware also clears the flag that generated the interrupt while in other cases the flag must be cleared by the user s software The hardware generated LCALL pushes the contents of the Program Counter PC onto the stack but it does not save the PSW and reloads the PC with an address that depends on the interrupt node being vectored to as shown in the Table 9 1 Program execution returns to the next instruction after calling the interrupt when the RETI instruction is encounter
559. r contents match the contents of the channel register A variety of control functions facilitate the adaptation of the T13 structure to different application needs In addition T13 can be started synchronously to timer T12 events This section provides information about 113 overview see Section 20 4 1 Counting scheme see Section 20 4 2 Compare mode see Section 20 4 3 Compare output path see Section 20 4 4 Shadow register transfer see Section 20 4 5 T13 counter register description see Section 20 4 6 State Bit Timer T13 Capture Compare To Output Logic Channel CC63 CCG3ST Modulation Input and Control Status Logic T13HR Synchronization to T12 CCU6 05526 Figure 20 23 Overview Diagram of the Timer T13 Block 20 4 1 T13 Overview Figure 20 24 shows a detailed block diagram of Timer T13 The functions of the timer T12 block are controlled by bits in registers TCTROL TCTROH TCTR2L TCTR2H TCTR4L and PISEL2 Timer T13 receives its input clock from the module clock fece via a programmable prescaler and an optional 1 256 divider or from an input signal TT3HR T13 can only count up similar to the Edge Aligned mode of T12 Via a comparator the timer T13 Counter Register T13L T13His connected to the Period Register T13PRL T13PRH This register determines the maximum count value for T13 When T13 reaches the period value signal T13 PM T13 Period Match is gen
560. r enabled Note BR VALUE should only be written if R 0 User s Manual 16 22 V1 0 2010 02 UART V 1 6 XC82x Infineon UART Field Bits Description BRPRE 3 1 rw Prescaler Bit Selects the input clock for foy which is derived from the peripheral clock 0008 for fecik 0016 fecu 2 0106 fpy 4 011g Sow 8 100 Jo 16 1016 Jow fecix 32 Others reserved BRDIS 4 rw Baud Rate Detection Disable Break Synch detection is enabled 1g Break Synch detection is disabled BGSEL 7 6 rw Baud Rate Select for Detection For different values of BGSEL the baud rate range for detection is defined by the following formula Joar 2184 2 BGSEL lt baud rate range lt Joo 72 2 BGSEL where BGSEL 00g 015 105 115 See Table 16 6 for bit field BGSEL definition for different input frequencies LINST LIN Status Register 5 Reset Value 00 RMAP 0 PAGE 5 7 6 5 4 3 2 1 0 BGS SYNEN ERRSYN EOFSYN BRK 0 rw rw rwh rwh rwh r Field Bits Type Description BRK 3 rwh Break Field Flag This bit is set by hardware and can only be cleared by software OQ Break Field is not detected 1g Break Field is detected User s Manual UART V 1 6 16 23 V1 0 2010 02 Cinfineon UART Field Bits Description EOFSYN 4 rwh End of SYN Byte Interrupt Flag This bit i
561. r factor of 1 256 can be enabled for the prescaler for T12 Os additional prescaler for T12 is disabled 1g additional prescaler for T12 is enabled User s Manual 20 57 V1 0 2010 02 CCU6 V4 0 Cinfineon XC82x Capture Compare Unit 6 CCU6 Field Bits Type Description T12R rh Timer T12 Run Bit T12R starts and stops timer T12 It is set cleared by SW by setting bits T12RR or T12RS or it is cleared by HW according to the function defined by bit field T12SSC Og Timer T12 is stopped 1g Timer T12 is running STE12 rh Timer T12 Shadow Transfer Enable Bit STE12 enables or disables the shadow transfer of the T12 period value the compare values and passive state select bits and levels from their shadow registers to the actual registers if a T12 shadow transfer event is detected Bit STE12 is cleared by hardware after the shadow transfer A T12 shadow transfer event is a period match while counting up or a one match while counting down Og shadow register transfer is disabled 1g shadow register transfer is enabled CDIR rh Count Direction of Timer T12 This bit is set cleared according to the counting rules of T12 T12counts up 1g 12 counts down CTM T12 Operating Mode Og Mode T12 always counts up and continues counting from zero after reaching the period value 1g
562. r in ADC_RESRxL x 0 3 and x 0 3 would be shown as Figure 21 23 In ADC_RESRxL x 0 3 bits 2 0 indicate the channel number whose conversion triggered the result event bits 7 5 return the last 3bits of the conversion result In ADC_RESRxH x 0 3 bits 6 0 returns bit 9 3 of the conversion result Reading the result automatically clears the valid flag This view is useful only without data reduction e Accumulated application read view RESRXL H 8bit conversion mode with Data Reduction Enabled and Digital Low Pass Filter disabled i e ADC_GLOBCTR DW 1 RCRx DRCTR 1 RCRx DLPF 0 When this mode is chosen the targetted result register in ADC_RESRxL x 0 3 and 0 3 would be shown as Figure 21 24 After the 1st conversion in ADC_RESRxL x 0 3 result register bits 2 0 indicate the channel number whose conversion triggered the result event In ADC_RESRxH x 0 3 bits 7 0 returns the conversion result This allows the result to be read in a single read Reading the result automatically clears the valid flag At the 2nd conversion onwards in ADC_RESRxL x 0 3 result register bits 2 0 indicate the channel number whose conversion triggered the result event bit 7 indicate the last bit of the accumulated result In x 0 3 bits 7 0 returns bit 8 10f the accumulated result 10bit conversion mode with Data Reduction Enabled and Digital Low Pass Filter disabled ADC_GLOBC
563. r the Hall pattern evaluation nor the Hall mode for Brushless DC Drive control is enabled the timer T12 block is available for PWM generation and output modulation e S Hall g Compare B T Logic de Hall idis HCRDY Hall Pattern Evaluation Edge Dead Time Counter 0 Delay Bypass Event Selection CCU6_MCB05553 Figure 20 36 Hall Pattern Evaluation If the evaluation signal HCRDY Hall Compare Ready see Figure 20 37 becomes activated the Hall inputs are sampled and the Hall compare logic starts the evaluation of the Hall inputs User s Manual 20 91 V1 0 2010 02 CCU6 V4 0 Cinfineon Capture Compare Unit 6 CCU6 Figure 20 36 illustrates the events for Hall pattern evaluation and the noise filter logic Table 20 15 summarizes the selectable trigger input signals Table 20 15 Hall Sensor Mode Trigger Event Selection HSYNC Selected Event see register T12MSELL T12MSELH 000 Any edge at any of the inputs CCPOSx independent from any PWM signal permanent check 001 A T13 Compare Match CM 63 010g A T13 Period Match T13 PM 011 Hall sampling triggered by HW sources is switched off 100 A T12 Period Match while counting up T12 PM and CDIR 0 101 T12 One Match while counting down T12 OM and CDIR 1 110g A T12 Compare Match of compare channel CC61 while counting up CM 61 and CDIR 0 111 12 Compare Matc
564. r the TRAP instruction 10 5 Reactions on Breakpoints without Monitor Entry In case a Break event happens while Monitor Mode is disabled the Monitor program is not started MM_no_entry but another action is triggered by OCDS system 10 5 1 Triggering a NMI request Instead of starting the Monitor program OCDS NMI is requested refer Section 10 6 1 The flags FNMIRR FNMIRW here set can be cleared only per software this must be done by the user NMl servicing routine User s Manual 10 11 V1 0 2010 02 OCDS V 2 7 1 Cinfineon Debug System 10 6 NMI Request and Control by OCDS The OCDS module provides hardware allowing to generate a NMI request itself as well as to control the general NMI processing within the XC800 system 10 6 1 NMI request from OCDS The OCDS generates one interrupt request at the output ocds_nmi_o This signal goes to the Interrupt Management Module into XC800 SCU System Control Unit where it sets a flag within NMI Status Register NMISR In case OCDS is an enabled source in NMI Control Register NMICON a non maskable interrupt request will be activated to the core The NMI request can be activated by OCDS upon memory access performed to defined address areas separately configurable for read write operations in XC800 Internal RAM This is an advanced and fully controllable by application code feature allowing to utilize parts of OCDS not for debugging but to support a general user accessible func
565. r to access a register located in a page other than the current one the current page must be exited This is done by reprogramming the bit field PAGE in the page register Only then can the desired access be performed If an interrupt routine is initiated between the page register access and the module register access and the interrupt needs to access a register located in another page the current page setting can be saved the new one programmed and the old page setting restored This is possible with the storage fields STx x 0 3 for the save and restore action of the current page setting By indicating which storage bit field should be used in parallel with the new page value a single write operation can Save the contents of PAGE in STx before overwriting with the new value this is done at the beginning of the interrupt routine to save the current page setting and program the new page number or e Overwrite the contents of PAGE with the contents of STx ignoring the value written to the bit positions of PAGE this is done at the end of the interrupt routine to restore the previous page setting before the interrupt occurred STNR value update from CPU Figure 3 4 Storage Elements for Paging With this mechanism a certain number of interrupt routines or other routines can perform page changes without reading and storing the previously used page information The use of only write operations makes the system sim
566. r transfer from register CC6xSRL H The corresponding shadow registers CC6xSRL H can be read and written by SW In capture mode the value of the T12 counter register can also be captured by registers CC6xSRL H if the selected capture event is detected depending on the selected capture mode CC6xSRL x 0 2 Capture Compare Shadow Register for Channel CC6x Low FA x 2 Reset Value 00 RMAP 0 PAGE 0 7 6 5 4 3 2 1 0 CCSL rwh Field Bits Type Description CCSL 7 0 rh Shadow Register for Channel x Capture Compare Value In compare mode the bit fields contents of CCS are transferred to the bit fields CCV for the corresponding channel during a shadow transfer In capture mode the captured value of T12 can be read from these registers Note The shadow registers can also be written by SW in capture mode In this case the HW capture event wins over the SW write if both happen in the same cycle the SW write is discarded CC6xSRH x 0 2 Capture Compare Shadow Register for Channel CC6x High FB x 2 Reset Value 00 RMAP 0 PAGE 0 7 6 5 4 3 2 1 0 CCSH th User s Manual 20 47 V1 0 2010 02 CCUG V4 0 Cinfineon XC82x Capture Compare Unit 6 CCU6 Field Bits Type Description CCSH 7 0 Shadow Register for Channel x Capture Compare Value In compare mode the bit fields contents of CCS are transferred to the bit fields CCV for the correspo
567. r values Data rate reduction through adding a selectable number of conversion results First order digital low pass filter through averaging of the conversion results Flexible interrupt generation based on selectable events Support of power saving modes Additional features Out of range ORC voltage comparator detection for each input channel that is able to trigger other modules Configurable limit checker able to trigger other modules 1 A minimum of 50 usec is needed between conversions when using this mode User s Manual 21 2 V1 0 2010 02 ADC V2 1 Cinfineon Analog to Digital Converter 21 1 System Information This section provides system information relevant to the ADC 21 1 1 Pinning The ADC pin assignment for XC82x is shown in Table 21 1 Table 24 1 ADC Pin Functions and Selection Pin Function Desciption Selected By P2 0 CHO Analog input channel 0 P2 EN PO 1g P2 1 CH1 Analog input channel 1 P2 EN P1 1g P2 2 2 Analog input channel 2 P2 EN P2 7 1 P2 3 CH3 Analog input channel 3 P2 EN P3 1g 21 1 2 Clocking Configuration The ADC kernel runs on the FPCLK at a fixed frequency of 48 MHz See Section 21 5 1 If the ADC functionality is not required at all it can be completely disabled by gating off its clock input for maximal power reduction This is done by setting bit ADC DIS in register PMCON 1 as described below The bit field PAGE of SCU PAGE register m
568. ransition was the expected event correct Hall event CM CHE and the MCMP value has to change Ifthe sampled Hall pattern matches neither CURH nor EXPH the transition was due to a major error wrong Hall event CWE and can lead to an emergency shut down IDLE User s Manual 20 93 V1 0 2010 02 CCU6 V4 0 Cinfineon Capture Compare Unit 6 CCU6 At every correct Hall event CM_CHE the next Hall patterns are transferred from the shadow register MCMOUTS into MCMOUT Hall pattern shadow transfer HP_ST and a new Hall pattern with its corresponding output pattern can be loaded e g from a predefined table in memory by software into MCMOUTS For the Modulation patterns signal MCM_ST is used to trigger the transfer Loading this shadow register can also be done by writing MCMOUTS STRHP 1 for EXPH and CURH or MCMOUTS STRMCMP 1 for MCMP 20 7 3 Mode Flags Depending on the Hall pattern compare operation a number of flags are set in order to indicate the status of the module and to trigger further actions and interrupt requests Flag ISH CHE Correct Hall Event is set by signal CM CHE when the sampled Hall pattern matches the expected one EXPH This flag can also be set by SW by setting bit ISSH SCHE 1 If enabled by bit IENH ENCHE 1 the set signal for CHE can also generate an interrupt request to the CPU Bit field INPL INPCHE defines which service request output becomes activated in case of an interrupt
569. rary V0 5 EEPROM V1 0 2010 02 Cinfineon Keyword Index Keyword Index A Registers ADC CHINCR 21 89 Accumulated Application Read View CHINFR 21 87 21 65 CHINSR 21 88 Alias Feature 21 54 CRCR1 21 23 Boundary Flag 21 53 CRMR1 21 21 Channel Scan Request Source Han CRPR1 21 24 dling 21 19 ENORC 21 58 Channel Scan Source 21 18 ETRCR 21 37 Clocking Scheme 21 13 EVINCR 21 86 Conversion Timing 21 61 EVINFR 21 84 Data Reduction and Filtering 21 80 EVINSR 21 85 Digital Low Pass Filter Mode 21 82 GLOBCTR 21 14 Standard Data Reduction Mode GLOBSTR 21 15 21 81 INPCRO 21 51 Differential Like Measurement 21 46 LCBRO 21 54 Digital Low Pass Filtered Application LCBR1 21 54 Read View 21 66 LORC 21 60 Error Definitions 21 12 PRAR 21 41 Differential non linearity error DNL QORO 21 34 21 12 QBURO 21 36 Gain Error 21 12 QINRO 21 33 Integral non linearity error INL QMRO 21 29 21 12 QSRO 21 31 Offset Error 21 12 RCRx x 0 3 21 77 Total unadjusted error TUE 21 12 RESRxH x 0 3 21 72 Interrupt Request Handling 21 83 RESRXL x 0 3 21 69 21 72 Channel Events 21 83 21 75 Out of Range Comparator Events VFCR 21 79 21 83 Request Source Arbitration 21 38 Request Source Events 21 83 Standard Application Read View 21 65 Result Events 21 83 Limit Checking 21 52 B Out of Range Comparator ORC Bitaddressable 3 10 21 57 BMI 5 1 Out of range comparator ORC 21 9 Boot and Startup 5 1 Queued Request Source Handling Bo
570. rdware controlled scheme period and software controlled ROM Library scheme period Single Pad Accumulated Count Period and All Enabled Pads Accumulated Count Period The timing definitions when Touch sense is enabled are shown in the equations below while an example of their relationships are portrayed in Figure 23 11 for a clearer picture A Time Slice is calculated as follows 23 12 Time Slice Prescaler x 256 where prescaler is the LEDTS Counter Clock Pre Scale Factor LTS GLOBCLO CLK PS and the input clock fc will be either 8 MHz 24 MHz depending on the USER setting A Time Frame is defined as follows 23 13 Time Frame Time Slice x No of LED enabled 1 A Period Hardware controlled scheme is defined as follows 23 14 Periode aware Controlled scheme Time Frame x No of PADTx enabled For software controlled ROM Library Scheme the Single Pad Accumulated Count Period is defined as follows 23 15 Period gingte Pad Accumulated Count Time Frame AccumulatorCount 1 where AccumulatorCount is the user defined input for FINDTOUCHEDPAD function For software controlled ROM Library Scheme the All Enabled Pads Accumulated Count Period is defined as follows 23 16 Period an Enabled Pads Period x No of PADTx enabled Single Pad Accumulated Count User s Manual 23 35 V1 0 2010 02 ROM Library V0 5 Infineon ROM Library For example 7 LEDs and 3 Touch
571. re enabled CON EN 0 Programming Mode SSC_CONL Control Register Low Programming Mode Reset Value 00 RMAP 0 PAGE X 7 6 5 4 3 1 0 LB PO PH HB BM rw rw rw rw TW Field Bit Type Description BM 3 0 rw Data Width Selection 0001 0000 Reserved Do not use this combination 0111 Transfer Data Width is 2 8 bits lt BM gt 1 Note The most significant bit of BM field is always fixed at 0 Thus the transfer and receive data width is restricted at maximum 8 bits Transfer Data Width is 2 8 bits lt BM gt 1 HB 4 rw Heading Control Og Transmit Receive LSB First 1g Transmit Receive MSB First PH 5 rw Clock Phase Control on trailing edge Shift transmit data on the leading clock edge latch on trailing edge 1 Latch receive data on leading clock edge shift PO 6 rw Clock Polarity Control to high transition to low transition Og Idle clock line is low leading clock edge is low 1g Idle clock line is high leading clock edge is high User s Manual 18 21 SSC V1 4 V1 0 2010 02 Cinfineon nee High Speed Synchronous Serial Interface Field Bit Type Description LB 7 rw Loop Back Control Og Normal output 1g Receive input is connected with transmit output half duplex mode SSC CONH Control Register High Programming Mode Reset Value 00
572. re must be declared by user application and must reside in indirect IRAM address ActiveSector store the current active sector address It is used by ReadEEPROM to find the current emulated dataset WriteAddress store the start address to write new data set when user application calls WriteEEPROM Both variable is updated by call to User s Manual 23 46 V1 0 2010 02 ROM Library V0 5 Cinfineon ROM Library InitEEPROM and WriteEEPROM DataSize store the EEPROM emulation dataset size EEPROMInfo should not be modified directly by user It only should be modified by functions provided by EEPROM emulation API 23 4 4 3 Functions The EEPROM emulation API provide 4 functions InitEEPROM FixEEPROM WriteEEPROM e ReadEEPROM These functions need to be used when accessing the emulated EEPROM InitEEPROM Table 23 21 InitEEPROM Function name InitEEPROM Function prototype unsigned char InitEEPROM unsigned char mode EEPROMInfo config Input mode Emulation scheme i e size of emulated EEPROM Valid value is 32 64 96 and 128 config Pointer to EEPROMInfo data structure Return status Status of emulated EEPROM Input to FiXEEPROM 0 0 Status of emulated EEPROM is OK 0 1 Sector 8 amp 9 needs to be erased Ox2 Sector 6 amp 7 needs to be erased 0 3 Sector 6 to 9 needs to be erased Max stack size 4 bytes InitEEPROM will in
573. register are located at the same physical address A write access to this address targets the Shadow Register while a read access reads from the actual period register User s Manual 20 69 V1 0 2010 02 CCU6 V4 0 Cinfineon Capture Compare Unit 6 CCU6 20 4 2 T13 Counting Scheme This section describes the clocking and the counting capabilities of T13 20 4 2 1 T13 Counting The period of the timer is determined by the value in the period Register T13PR according to the following formula T13pgr lt Period Value gt 1 in T13 clocks 20 3 Timer T13 can only count up comparable to the Edge Aligned mode of T12 This leads to very simple counting rule for the T13 counter The counter is cleared with the next T13 clock edge if a Period Match is detected The counting direction is always upwards The behavior of T13 is illustrated in Figure 20 25 tras Period Value Period Zero T13 Count Match Match Zero CC63 Value n 1 Value n 2 Shadow Transfer CCU6_MCT05528 Figure 20 25 T13 Counting Sequence User s Manual 20 70 V1 0 2010 02 CCUG V4 0 Cinfineon XC82x 20 4 2 2 Single Shot Mode Capture Compare Unit 6 CCU6 In Single Shot Mode the timer run bit T13R is cleared by hardware If bit T13SSC 1 the timer T13 will stop when the current timer period is finished T13 Count T13R CC63ST TI cue usos Period Value Com
574. request To clear flag CHE SW needs to write ISRH RCHE 1 Flag IS WHE indicates a Wrong Hall Event Its handling for flag setting and resetting as well as interrupt request generation are similar to the mechanism for flag CHE The implementation of flag STR is done in the same way as for CHE and WHE This flag is set by HW by the shadow transfer signal MCM ST see also Figure 20 35 Please note that for flags CHE WHE and STR the interrupt request generation is triggered by the set signal for the flag That means a request can be generated even if the flag is already set There is no need to clear the flag in order to enable further interrupt requests The implementation for the IDLE flag is different It is set by HW through signal CM WHE if enabled by bit ENIDLE Software can also set the flag via bit SIDLE As long as bit IDLE is set the modulation pattern field MCMP is cleared to force the outputs to the passive state Flag IDLE must be cleared by software by writing RIDLE 1 in order to return to normal operation To fully restart from IDLE mode the transfer requests for the bit fields in register MCMOUTS to register MCMOUT have to be initiated by software via bits STRMCM and STRHP in register MCMOUTS In this way the release from IDLE mode is under software control but can be performed synchronously to the PWM signal User s Manual 20 94 V1 0 2010 02 CCU6 V4 0 Cinfineon Capture Compare Unit 6 CCU6 CM_CHE
575. response time is always more than three machine cycles and less than nine machine cycles wait states are not considered When considering wait states the interrupt response time will be extended depending on the user instructions also the hardware generated LCALL being executed during the interrupt response time shaded region in Figure 9 10 and Figure 9 11 User s Manual 9 15 V1 0 2010 02 Interrupt System V 2 3 3 Cinfineon XC82x 9 5 Registers Description Interrupt System Interrupt Special Function Registers or bits are used for interrupt configuration such as node enable external interrupt control interrupt flags and interrupt priority setting Table 9 3 lists the SFRs and corresponding address Table 9 3 Register Map Address Register RMAP 0 or 1 A8 IENO E84 IEN1 B8 IP B9 IPH F8 IP1 F9 IPH1 88 TCON 98 SCON RMAP 0 EE SCU page 0 NMICON EF SCU page 0 EXICONO SCU page 0 EXICON1 F4 SCU page 3 MODPISEL1 F2 SCU page 0 IRCONO SCU page 0 IRCON1 F5 SCU page 0 IRCON2 F6 SCU page 0 F7 SCU page 0 NMISR User s Manual 9 16 V1 0 2010 02 Interrupt System V 2 3 3 Cinfineon Interrupt System 9 5 1 Interrupt Node Enable Registers Each interrupt node can be individually enabled or disabled by setting or clearing the corresponding bit in the interrupt enable registers I
576. right with zeros shifted in from the left When the MSB gets to the output position the control block executes one last shift and sets the TI bit Reception is started by a high to low transition on RXD sampled at 16 times the baud rate The divide by 16 counter is then reset and 1111 1111 is written to the receive register If a valid start bit 0 is then detected based on two out of three samples it is shifted into the register followed by 8 data bits If the transition is not followed by a valid start bit the controller goes back to looking for a high to low transition on RXD When the start bit reaches the leftmost position the control block executes one last shift then loads SBUF with the 8 data bits loads RB8 SCON 2 with the stop bit and sets the RI bit provided RI 0 and either SM2 0 see Section 16 4 or the received stop bit 1 If none of these conditions is met the received byte is lost The associated timings for transmit receive in mode 1 are illustrated in Figure 16 1 User s Manual 16 4 V1 0 2010 02 UART V 1 6 82 UART E QC E ES Transmit Infineon gt 1 5 1 dois od ves m gt lt re a _ a Lo e a Se e a _ gt a gt Receiv
577. riod match T12_PM the value of T12 is cleared with the next counting step saw tooth shape User s Manual 20 21 V1 0 2010 02 CCUG V4 0 Cinfineon Capture Compare Unit 6 CCU6 Jrz Period Value Period Zero T12 Count Match Match Zero CDIR CC6x Value n 1 Value n 2 Shadow Transfer CCU6_MCT05509 Figure 20 5 112 Operation in Edge Aligned Mode As a result in Edge Aligned mode the timer period is given by T12pgr lt Period Value gt 1 in T12 clocks fr42 20 1 In Center Aligned Mode CTM 1 timer T12 is counting upwards or downwards triangular shape When reaching the value given by the period register period match T12_PM while counting upwards CDIR 0 the counting direction control bit CDIR is changed to downwards CDIR 1 with the next counting step When reaching the value 0001 one match T12_OM while counting downwards the counting direction control bit CDIR is changed to upwards with the next counting step As a result in Center Aligned mode the timer period is given by T12pgg lt Period Value gt 1 x 2 in T12 clocks 412 20 2 e With the next clock event of f 42 the count direction is set to counting up CDIR 0 when the counter reaches 0001 while counting down e With the next clock event of fr the count direction is set to counting down CDIR 1 when the Period Match is detected while counting up e With the next clock event of the
578. river is enabled default 1 Input driver is disabled 0 7 4 r Reserved Returns 0 if read should be written with 0 User s Manual 11 33 V1 0 2010 02 Cinfineon XC82x Parallel Ports P2_PUDSEL Port 2 Pull Up Pull Down Select Register 93 Reset Value RMAP 0 PAGE 1 7 6 5 4 3 2 1 0 0 P3 P2 P1 PO T rw rw rw rw Field Bits Type Description Pn n rw Pull Up Pull Down Select Port 2 Bit n n 0 3 0 Pull down device is selected 1 Pull up device is selected default 0 7 4 r Reserved Returns 0 if read should be written with 0 P2_PUDEN Port 2 Pull Up Pull Down Enable Register 94 Reset Value 00 RMAP 0 PAGE 1 7 6 5 4 3 2 1 0 0 P3 P2 P1 PO T rw rw rw rw Field Bits Type Description Pn n rw Pull Up Pull Down Enable at Port 2 Bit n n20 3 0 Pull up or Pull down device is disabled default 1 Pull up or Pull down device is enabled 0 7 4 r Reserved Returns 0 if read should be written with User s Manual 11 34 V1 0 2010 02 Cinfineon Multiplication Division Unit 12 Multiplication Division Unit 12 1 Overview The Multiplication Division Unit MDU provides fast 16 bit multiplication 16 bit and 32 bit division as well as shift and normalize features It has been integrated to support the XC82x Core in real time control applications which require fast mathematical computations The MDU uses a total of
579. rmation 18 2 V1 0 2010 02 Cinfineon XC82x High Speed Synchronous Serial Interface Table 18 1 SSC Pin Functions in XC82x Pin Function Desciption Selected By P0 4 SCK 0 SSC Clock Input Output For Input MODPISEL CIS 0g For Output PO_ALTSELO P4 0 PO ALTSEL1 P4 1 PO ALTSEL2 P4 0g P2 2 SCK 1 SSC Clock Input For Input MODPISEL CIS 1g P0 5 MTSR_O 55 Master Transmit Output For Input Slave Receive Input MODPISEL SIS 000 For Output PO ALTSELO P5 0 PO ALTSEL1 P5 1 PO ALTSEL2 P5 0 P0 6 MTSR 1 SSC Slave Receive Input For Input MODPISEL SIS 001 P0 0 2 SSC Master Transmit Output For Input Slave Receive Input MODPISEL SIS 010 For Output PO ALTSELO PO 0 PO ALTSEL1 PO 1 P0 1 MTSR 3 SSC Slave Receive Input For Input MODPISEL SIS 011 P2 1 MTSR_4 Slave Receive Input For Input MODPISEL SIS 100 P0 6 MRST 0 SSC Master Receive Input For Input Slave Transmit Output MODPISEL MIS 00 For Output PO ALTSELO P6 0 PO ALTSEL1 P6 1g PO ALTSEL2 P6 0g P0 5 MRST 1 SSC Master Receive Input For Input MODPISEL MIS 01 User s Manual SSC V1 4 18 3 V1 0 2010 02 Cinfineon neers High Speed Synchronous Serial Interface Table 18 1 SSC Pin Functions in XC82x Pin Function Desciption Selected By P0 1 MRST_2 SSC Master Receive Input For Input Slave Transmit Output MODPISEL MIS 10
580. rogram to the valid flash address and update the EEPROM configuration Each write operation is 32 bytes 31 data bytes 1 status byte Additionally it will reclaim the previous active sector when its filled with data For save operation ensure that all NMISR SFR flags are cleared before calling this function ReadEEPROM Table 23 24 ReadEEPROM Function name ReadEEPROM Function prototype unsigned char ReadEEPROM unsigned char address char idata dst EEPROMInfo config Input address Logical address of emulated EEPROM to read from dst Pointer to 32 bytes IRAM buffer to store read data config Pointer to EEPROMInfo data structure Output status Read operation result 0x00 Read operation successful OxFF Read operation fail Max stack size 2 bytes User s Manual 23 49 V1 0 2010 02 ROM Library V0 5 Cinfineon ROM Library ReadEEPROM will search the current active sector for the most current data based on the given address It will always return 32 bytes of data i e 31 data byte 1 status bytes The address takes the form of a number from 0 to 3 For dataset size of 32bytes only address 0 is valid For dataset size of 128 address 0 to 3 is valid Address 2 will return byte 64 to byte 95 where byte 95 is the status bytes Function will return an error code if the address can t be found 23 4 4 4 Example of API usage Here s an e
581. rogrammable window feature for refresh operation and warning prior to overflow Three general purpose ports Up to 17 pins as digital I O 4 pin as digital analog input Multiplication Division Unit MDU for arithmetic calculation Up to 4 channels 10 bit A D Converter support up to 3 differential input channel Up to 4 channels Out of range comparator Three 16 bit timers Timer 0 Timer 1 Timer2 Periodic wake up timer Capture compare unit for PWM signal generation CCU6 Full duplex serial interface UART Synchronous serial channel SSC Inter IC IIC serial interface LED and Touch sense Controller LEDTSCU On chip Debug Support via single pin DAP interface SPD 1 KByte monitor ROM part of the Boot ROM 64 byte monitor RAM PG TSSOP 16 and PG DSO 20 pin packages The block diagram of the XC82x is shown in Figure 1 2 User s Manual 1 2 V1 0 2010 02 System Architecture V1 0 Cinfineon XC82x Introduction XC82x Internal Bus 8 Kbyte A 4 Boot ROM 2 800 256 byte A Li 5 C Ke P0 0 P06 64 byte monitor v men UART RAM 1 VAN Vopp AN pur ias EN 5 1 0 1 5 256 byte XRAM Vssp
582. rogramming Mode Type TW Tw IW b IW SSC_CONL Reset 004 Bit Field 0 BC Control Register Low Operating Mode Type 5 rh ABH SSC_CONH Reset 004 Bit Field EN MS 0 AREN BEN PEN REN TEN Control Register High Programming Mode Type id TW ew id TW ME ABH SSC_CONH Reset 004 Bit Field EN MS 0 BSY BE PE RE TE Control Register High Operating Mode Type TW rw r rh rwh rwh rwh rwh ACY SSC_TBL Reset 004 Bit Field TB_VALUE Transmitter Buffer Register Low Type rw ADH SSC_RBL Reset 004 Bit Field RB_VALUE Receiver Buffer Register Low Type rh AEH SSC_BRL Reset 004 Bit Field BR_VALUE Baud Rate Timer Reload Register Low Type 55 Reset 004 Bit Field BR_VALUE Baud Rate Timer Reload Register High Type 3 4 5 11 Registers The IIC SFRs be accessed the standard memory area RMAP 0 Table 3 11 IIC Register Overview Addr Register Name Bit 7 6 5 4 3 2 1 0 IRMAP 0 DAW ADDR Reset 004 Bit Field SLA GCE Slave Address Register Type rw rw DATA Reset 004 Bit Field DATA Data Byte Register Type TW DCH IIC_CNTR Reset 004 Bit Field IEN ENAB STA STP IFLG AAK 0 Control Register Type TW rw rwh rwh rwh rw DDH 5 Reset F84 Bit Field STAT 0 Status Register Type rh r User s Manual 3 31 V1 0 2010 02 Memory Organization V 0 1 Infineon Memor
583. rough digital input general purpose input Alternate input for on chip peripherals Analog input for ADC module Input driver is disabled during power save mode 11 1 General Port Operation Description Figure 11 1 shows the block diagram of an XC82x bidirectional port pin Each port pin is equipped with a number of control and data bits thus enabling very flexible usage of the pin By defining the contents of the control register each individual pin can be configured as an input or an output The user can also configure each pin as an open drain pin with or without internal pull up pull down device The input and output drivers of the standard bidirectional port are always enabled during normal operation except in power down mode However port pin s required as a wake up source during power down mode will not be disabled In output mode the output driver drives the value supplied through the multiplexer to the port pin Each pin in output mode can be switched to open drain mode or normal mode push pull mode via the register Px OD x 0 1 The output multiplexer in front of the output driver enables the port output function to be used for different purposes If the pin is used for general purpose output the multiplexer User s Manual 11 1 V1 0 2010 02 Cinfineon Parallel Ports is switched by software to the data register Px_DATAOUT Software can set or clear the bit in Px_DATAOUT and therefore directly influence th
584. rrupt Priority Register Type rw rw rw rw rw TW B94 IPH Reset 004 Bit Fie PT2H PSH PT1H PX1H PTOH PXOH Interrupt Priority High Register Type rw rw rw rw rw TW PSW Reset 004 Bit Fie CY AC FO RS1 RSO F1 Program Status Word Register Type rwli n m Em rwh W ih E04 ACC Reset 004 Bit Fie ACC7 ACC6 ACC5 ACC4 ACC3 ACC2 ACC1 ACCO Accumulator Register Type rw rw rw rw rw rw rw rw E84 IEN1 Reset 004 Bit Fie ECCIP ECCIP ECCIP ECCIP EXM EX2 ESSC EADC Interrupt Enable Register 1 3 2 1 0 rw rw rw rw TW rw rw rw B Reset 004 Bit Fie B7 B6 B5 B4 B3 B2 B1 BO B Register Type TW rw rw rw TW rw rw rw Fey IP1 Reset 004 Bit Fie PCCIP PCCIP PCCIP PCCIP PXM PX2 PSSC PADC Interrupt Priority 1 Register 3 2 1 0 Type TW rw rw rw rw rw rw rw IPH1 Reset 004 Bit Fie PCCIP PCCIP PCCIP PCCIP PXMH PX2H PSSC PADC Interrupt Priority 1 High Register 3H 2H 1H OH H H Type TW rw rw rw TW rw rw rw 3 4 5 2 Registers MDU SFRs be accessed the standard memory area RMAP 0 Table 3 2 MDU Register Overview Addr Register Name Bit 7 6 5 4 3 2 1 0 IRMAP 0 Boy MDUSTAT Reset 004 Bit Fie 0 BSY IERR IRDY MDU Status Register Type r rh rwh rwh B1H MDUCON Reset 004 Bit Fie IE IR RSEL STAR OPCODE MDU Control Register T Type TW rw rw rwh B2y MDO Reset 004 Bit Fie DATA MDU Operand Register 0 Type B2y MRO Reset 00 Bit Fie DATA
585. rrupt vector node going directly to the core is generated due to the events and cleared Common among these two interrupt structures is the interrupt masking bit EA which is used to globally enable or disable all interrupt requests except NMI to the core Resetting bit EA to 0 only masks the pending interrupt requests from the core but does not block the capture of incoming interrupt requests Note The NMI node is similar to the other interrupt nodes except for the exclusion of EA bit Effectively NMI node is non maskable User s Manual 9 10 V1 0 2010 02 Interrupt System V 2 3 3 Cinfineon Interrupt System 9 2 1 Interrupt Structure 1 For interrupt structure 1 see Figure 9 7 the interrupt event will set the interrupt status flag which doubles as a pending interrupt request to the core An active pending interrupt request will interrupt the core only if its corresponding interrupt node is enabled Once an interrupt node is serviced interrupt acknowledged its pending interrupt request represented by the interrupt status flag may be automatically cleared by hardware the core software interrupt acknowledge pending from core interrupt interrupt set interrupt status request evet 0 flag interrupt node enable bit gt AND to core EA bit Figure 9 7 Interrupt Structure 1 For the XC82x
586. rview on the associated operation T12 Count T13 Count TRPF CTRAP active TRPS Sync to 12 TRPS Sync to T13 TRPS CCU6_MCT05542 Figure 20 34 Trap State Synchronization with TRM2 0 User s Manual 20 86 V1 0 2010 02 CCU6 V4 0 Cinfineon Capture Compare Unit 6 CCU6 20 6 Multi Channel Mode The Multi Channel mode offers the possibility to modulate all six T12 related output signals with one instruction The bits in bit field MCMOUTL MCMP are used to specify the outputs that may become active If Multi Channel mode is enabled bit MODCTRL MCMEN 1 only those outputs may become active that have a 1 at the corresponding bit position in bit field MCMP This bit field has its own shadow bit field MCMOUTSL MCMPS that can be written by software The transfer of the new value in MCMPS to the bit field MCMP can be triggered by and synchronized to T12 or T13 events This structure permits the software to write the new value that is then taken into account by the hardware at a well defined moment and synchronized to a PWM signal This avoids unintended pulses due to unsynchronized modulation sources SWSEL SWSYN Shadow Register EL STRMCM E Shadow Transfer T12 ZM Switching MCM ST CM CHE Synchro T13 ZM nization CM 61 Switching T12 PM Event Detection T12 T13 PM e STR set CDIR MCMOUT MCMP To Interrupt Control T1
587. rw Active Level of LED Column Og Active low 1g Active high User s Manual 19 24 V1 0 2010 02 LEDTSCU V 1 2 1 Cinfineon LED and Touch Sense Controller Field Bits Type Description NR_LEDCOL 7 5 rw Number of LED Columns Defines the number of LED columns 000 1 LED column 001 2 LED columns 010 3 LED columns 011 4 LED columns 100g 5 LED columns 101 6 LED columns 110 7 LED columns 111 8 LED columns max LED columns 7 if bit TS_EN 1 Note LED column is enabled in sequence starting from highest column number If touch sense function is not enabled COLA is activated in last time slice 1 This bit can only be modified when bit CLK PS 0 LTS LDLINE LED Line Pattern Shadow Register D5 Reset Value 00 RMAP 0 PAGE X 7 6 5 4 3 2 1 0 SHD LINE rw Field Bits Type Description SHD_LINE 7 0 rw LED Line Value to Shadow Transfer This value is shadow transferred to the LED lines on start of each new time slice A shadow transfer is effected on CLK_PS set from 0 User s Manual 19 25 V1 0 2010 02 LEDTSCU V 1 2 1 Cinfineon LED and Touch Sense Controller LTS_TSCTL Touch Sense Control Register D744 Reset Value 00 RMAP 0 PAGE X 7 6 5 4 3 2 1 0 TSCTRR IE EPULL PADTSW PADT rwh rw rw rw rw rwh Field Bits Type Description PADT 2 0 rwh_ Touch Sense Pad Turn I
588. s 10 174 11 Bank selected data address 184 1F FO rw General Purpose Flag AC rwh Auxiliary Carry Flag Used by instructions which execute BCD operations CY 7 rwh Carry Flag Used by arithmetic instructions User s Manual XC800 Core V 1 0 2 2 4 V1 0 2010 02 Cinfineon XC800 Core 2 3 6 Extended Operation Register EO A2 The instruction set includes an additional instruction MOVC DPTR A which writes to program memory implemented as RAM This instruction may be used both to download code into the program memory when the CPU is initialized and subsequently to provide software updates The instruction copies the contents of the accumulator to the code memory at the location pointed to by the current data pointer then increments the data pointer The instruction uses the opcode A5 which is the same as the software break instruction TRAP see Table 2 1 Bit TRAP EN in the Extended Operation EO register is used to select the instruction executed by the opcode A5 When bit TRAP EN is 0 default the A5 opcode executes the MOVC instruction When bit TRAP EN is 1 the A5 opcode executes the software break instruction TRAP which switches the CPU to debug mode for breakpoint processing Register EO is also used to select the current data pointer EO Extended Operation Register A24 Reset Value 00 RMAP X PAGE X 7 6 5 4 3 2 1 0 0 TRAP_EN 0 DPSEL2
589. s a simplified model for this Input Signal Path The ADC of the XC82x uses a switched capacitor field represented by Cai small parasitic capacitances are present at each input pin During the sample phase the capacitor field Cay is connected to the selected analog input CHx via the input multiplexer modeled by ideal switches and series resistors Ran The switch to CHx is closed during the sample phase and connects the capacitor field to the input voltage Vw T 2 ADC kernel ADC_signal_path_model3 Figure 21 3 Signal Path Model A simplified model for the analog input signal path is given in Figure 21 3 An analog voltage source value Vs with an internal impedance of Rg 4 delivers the analog input that should be converted During the sample phase the corresponding switch is closed and the capacitor field Cain is charged Due to the low pass behavior of the resulting RC combination the voltage User s Manual 21 10 V1 0 2010 02 ADC V2 1 Cinfineon Analog Digital Converter Vc to be actually converted does not immediately follow Vs The value Rex of the analog voltage source and the desired precision of the conversion strongly define the required length of the sample phase To reduce the influence of Rex and to filter input noise it is recommended to introduce a fast external blocking capacitor at the analog input of the ADC Like this mainly Cry delivers the c
590. s always right aligned in registers TB and RB with the LSB of the transfer data in bit O of these registers The data bits are rearranged for transfer by the internal shift register logic The unselected bits of TB are ignored the unselected bits of RB will not be valid and should be ignored by the receiver service routine The Clock Control allows the adaptation of transmit and receive behavior of the SSC to a variety of serial interfaces A specific shift clock edge rising or falling is used to shift out transmit data while the other shift clock edge is used to latch in receive data Bit CON PH selects the leading edge or the trailing edge for each function Bit CON PO selects the level of the shift clock line in the idle state Thus for an idle high clock the leading edge is a falling one a 1 to 0 transition see Figure 18 2 User s Manual 18 9 V1 0 2010 02 SSC V1 4 Cinfineon neers High Speed Synchronous Serial Interface Shift Clock MS_CLK SS_CLK Pins 222 MTSR MRST i First Transmit Data Last Bit 1 Bit Latch Data Shift Data Figure 18 2 Serial Clock Phase and Polarity Options 18 3 2 Full Duplex Operation The various devices are connected through three lines The definition of these lines is always determined by the master the line connected to the master s data output line TXD is the transmit line the receive line is connected to its data input line RXD the shift clock line is either MS_CLK o
591. s been completed 1 Refer to XC82x Data Sheet for Flash data profile User s Manual 4 15 V1 0 2010 02 Flash Memory V 0 1 Cinfineon nears Flash Memory 4 7 4 Flash Read Mode Status Besides the Flash program and erase subroutines a subroutine to check the ready to read mode status of the Flash Bank is additionally provided Before calling this subroutine the user must ensure that the input R7 is configured to the selected Flash Bank The carry flag is cleared when Flash is in ready to read mode otherwise it is set The carry flag is also set if the input to the subroutine is invalid This routine is especially useful when the abort background Flash erase subroutine is used After calling the erase abort routine the user can call this Flash Read Mode Status subroutine to check if the erase operation has been successfully aborted and that the Flash is already in ready to read mode User s Manual 4 16 V1 0 2010 02 Flash Memory V 0 1 Cinfineon XBox Boot and Startup 5 Boot and Startup Entry to various boot modes such as User mode Boot loader mode BSL and On chip Debug OCDS mode are done by the startup firmware in the Boot ROM The startup firmware will depend on the Boot Mode Index BMI value to enter each boot mode Section 5 2 describes the behaviors of each boot modes The BMI BMI value is programmable via BSL mode 6 user routine BR PROG USER User need to program the BMI and BMI to enter each
592. s for Mode 0 and 2 depending on whether it is a Data Block or EOT Block Checksum the checksum of the block type and data area The host will decide the number of transfer blocks and their respective lengths during one serial communication process For safety purpose the last byte of each transfer block is a simple checksum of the block type and data area The host generates the checksum by XOR ING all the bytes of the block type and data area Every time the UART BSL routine receives a transfer block it recalculates the checksum of the received bytes block type and data area and compares it with the attached checksum Note If there is less than 1WL to be programmed to Flash the PC Host will have to fill up the vacancies with 00 and transfer data in the length of 32n bytes n 1 3 6 2 1 2 Transfer Block There are three types of transfer blocks depending on the value of the block type Table 6 2 provides the general information on these block types More details will be described in the corresponding sections later Table 6 2 Type of Transfer Block Block Name Block Type Description Header Block 00 This block has a fixed length of 8 bytes Special information is contained in the data area of the block which is used to select different working modes User s Manual 6 5 V1 0 2010 02 Cinfineon Boot Loader 6 2 Type of Transfer Block Block Name Block Type
593. s only range breakpoints on IRAM address The OCDS differentiates between a breakpoint on read and a breakpoint on write operation to the IRAM The exact processing is different in case of Read and Write Breakpoints Address Comparators Control bits and Flags Below the comparators used for Memory Access Breakpoints are described CMPRL2 CMPRH2 Two 8 bit comparators CMPRL2 between HWBP2L register A side and the 8 bit IRAM Source Address Bus B side generating A lt B CMPRH2 between HWBP2H register A side and the 8 bit IRAM Source Address Bus B side generating A gt B Then break on HWBP2L lt IRAM Read Address lt HWBP2H User s Manual 10 9 V1 0 2010 02 OCDS V 2 7 1 Cinfineon Debug System CMPWL3 CMPWH3 Two 8 bit comparators CMPWLS between HWBP3L register A side and the 8 bit IRAM Destination Address Bus B side generating A lt B CMPWH3 between HWBP3H register A side and the 8 bit IRAM Destination Address Bus B side generating A gt B Then break on HWBP3L lt IRAM Write Address lt HWBP3H 10 4 1 3 Tracing changes in Break Address The mechanism to generate Hardware Breakpoints assures that immediately upon a break condition match the XC800 core is forced to Debug Mode The Program Counter freezes then at a value related to the address of instruction that would have been fetched had the core not been in Debug Mode When entered the Monitor will determine t
594. s represent compare capture value 23 16 of the 32 bits value that could generate a compare interrupt when it matches with the current counter value RTC RTCCR3 Mode 1 and Mode 3 Real Time Clock Compare Capture Register 3 EB Reset Value 00 RMAP 0 PAGE X 7 6 5 4 3 2 1 0 CC VAL rw Field Bits Type Description CC_VAL 7 0 rwh Compare Capture Value 31 23 These bits represent compare capture value 31 23 of the 32 bits value that could generate a compare interrupt when it matches with the current counter value User s Manual 15 11 V1 0 2010 02 RTC V1 0 Cinfineon UART 16 UART 16 1 Overview The UART provides a full duplex asynchronous receiver transmitter i e it can transmit and receive simultaneously It is also receive buffered i e it can commence reception of a second byte before a previously received byte has been read from the receive register However if the first byte still has not been read by the time reception of the second byte is complete one of the bytes will be lost UART Feature Full duplex asynchronous modes 8 bit or 9 bit data frames LSB first fixed or variable baud rate Receive buffered Multiprocessor communication Interrupt generation on the completion of a data transmission or reception 16 2 System Information This section provides system information relevant to the UART 16 2 1 Pinning In mode 0 the
595. s set by hardware and can only be cleared by software Og of SYN Byte is not detected 13 of SYN Byte is detected ERRSYN 5 rwh SYN Byte Error Interrupt Flag This bit is set by hardware and can only be cleared by software Og Error is not detected in SYN Byte 1g X Error is detected in SYN Byte SYNEN 6 rw End of SYN Byte and SYN Byte Error Interrupts Enable Og of SYN Byte and SYN Byte Error Interrupts are not enabled 1g of SYN Byte and SYN Byte Error Interrupts are enabled BGS 7 rw Baud Rate Generator Select 0s generator is selected 1g X Timer 1 is selected as baud rate generator 16 7 3 Baud rate Generator Timer Reload Registers The low and high bytes of the baud rate timer reload register BG contains the 11 bit reload value for the baud rate timer and the 5 bit fractional divider selection Reading the low byte of register BG returns the content of the lower three bits of the baud rate timer and the FD SEL setting while reading the high byte returns the content of the upper 8 bits of the baud rate timer Writing to register BG loads the baud rate timer with the reload and fractional divider values from the BG register the first instruction cycle after BCON R is set BG should only be written if R 0 BGL Baud Rate Timer Reload Register Low Byte Reset Value 00 RMAP 0 PAGE 5 7 6 5 4 3 2 1 0 BR_VALUE FD_SEL 1 rwh
596. same signal can be different in terms of boundary values interrupts etc f a queued conversion request source has been set up a conversion request for channels CHO can be easily re directed to other input channels without flushing the queue Figure 21 18 shows an example where the sensor signal is connected to one input channel CHx but two conversions are triggered for CHx and CHO The alias feature User s Manual 21 54 V1 0 2010 02 ADC V2 1 Cinfineon Analog Digital Converter re directs the conversion request for CHO to CHx but taking into account the settings for CHO Although the same analog input CHx has been measured the conversion results can be stored and retrieved from result registers RESRx conversion triggered for CHx and RESRO conversion triggered for CHO Additionally different interrupts or limit boundaries can be selected enabled or disabled reference PWM timer trigger CHx ADC_alias Figure 21 18 Alias Feature In typical low cost AC drive applications only one common current sensor is used to determine the phase currents Depending on the applied PWM pattern the measured value has different meanings and the sample points have to be precisely located in the PWM period User s Manual 21 55 V1 0 2010 02 ADC V2 1 Cinfineon XC82x Analog to Digital Converter The Alias Register specifies replacement channel numbers for CHO i e CHO will use the respec
597. ser s Manual 23 23 V1 0 2010 02 ROM Library V0 5 Cinfineon XC82x ROM Library Table 23 13 Specifications of Find Touched Pad Subroutine cont d IRAM address 0x32 IRAM address 0x33 IRAM address 0x34 or user defined IRAM address in 0x32 IRAM address 0x2D IRAM address 0x2E Subtraction Option or Subtraction m Address The option to choose between common subtraction value or different respective subtraction values for all touch pads If option is 0x00 it means common subtraction is chosen for all touch pads The common subtraction m value is at Iram address 0x34 If not 0 00 it means different subtraction values are chosen for respective touch pads In this case the Iram start address for the subtraction m is given here Divisor n Low pass filter gain 2 for calculating the average value where n is 1 2 3 4 5 6 7 8 for low pass filter gain of 2 4 8 256 Subtraction m value Value used to minus from Average to get the LowTrip Trip point value Common subtraction m value or e Subtraction m Address Subtraction m value of PADTO Subtraction m Address 1 Subtraction m value of PADT1 Subtraction m Address 2 Subtraction m value of PADT2 Subtraction m Address z Subtraction m value of PADTz where z is no of PADTx enabled PadError Status If bitis 1 function will be exited for that Touch sense Pad Turn No analysis will be done Users should clear this status when
598. ser s Manual 20 59 V1 0 2010 02 CCU6 V4 0 Cinfineon XC82x Capture Compare Unit 6 CCU6 Field Bits Type Description STE13 rh Timer T13 Shadow Transfer Enable Bit STE13 enables or disables the shadow transfer of the T13 period value the compare value and passive state select bit and level from their shadow registers to the actual registers if a T13 shadow transfer event is detected Bit STE13 is cleared by hardware after the shadow transfer T13 shadow transfer event is a period match shadow register transfer is disabled 13 shadow register transfer is enabled 7 6 reserved returns 0 if read should be written with 0 1 Aconcurrent set cleared action on T13R from T13SSC T13TEC T13RR or T13RS will have no effect The bit T12R will remain unchanged User s Manual CCU6 V4 0 20 60 V1 0 2010 02 Cinfineon Capture Compare Unit 6 CCU6 Register TCTR2L H controls the single shot and the synchronization functionality of both timers T12 and T13 Both timers can run in single shot mode In this mode they stop their counting sequence automatically after one counting period with a count value of zero The single shot mode and the synchronization feature of T13 to T12 allow the generation of events with a programmable delay after well defined PWM actions of T12 TCTR2L Timer Control Register 2 Low FA Reset Va
599. set by hardware and can only be cleared by software Og No voltage out of range event for channel x has not occured Writing a 0 clears this register 1g Avoltage out of range event for channel x has occured Note Bit 4 7 are only applicable for devices that have 8 ADC channels For channels not implemented these bits should be treated as Reserved bits of type r which returns 0 if read and should be written with O User s Manual 21 60 V1 0 2010 02 ADC V2 1 Cinfineon Analog to Digital Converter 21 8 6 Conversion Timing The total time required for a conversion depends on several user definable factors ADC conversion clock frequency where fanc fapc CTC 3 The selected sample time where fg 2 STC x taney STC aditional sample time see also Section 21 5 1 The selected result width N 8 10 bits Synchronization steps done at module clock speed The conversion time is the sum of sample time conversion steps and synchronization It can be computed with the following formula ton tape X 1 rx 3 n STC 3 CTC Conversion Time Control ADC_GLOBCTR CTC STC Sample Time Control ADC_INPCRO STC n 8 or 10 for 8 bit and 10bit conversion respectively tanc 1 fapc The frequency at which conversions are triggered also depends on several configurable factors The selected conversion time according to the input class definitions
600. slice x TSD User s Manual 19 16 V1 0 2010 02 LEDTSCU V 1 2 1 Cinfineon LED and Touch Sense Controller LED drive active duration 19 4 LED Drive Active Duration TSD x Compare VALUE 28 Touch sense drive active duration 19 5 Touch sense Drive Active Duration TSD x 28 Compare VALUE 28 User s Manual 19 17 V1 0 2010 02 LEDTSCU V 1 2 1 Cinfineon LED and Touch Sense Controller 19 9 LEDTSCU Pin Control The user may flexibly assign pins as provided by GPIO SFR ALTSEL for the LEDTSCU functions e COL x for LED column control LINE x TSIN x for LED line control or touch sensing Refer also to Section 19 4 for more considerations with regards to which COL x and or LINE x TSIN Xx will be active based on user configuration User code must configure the ALTSEL assigned LED pin GPIO SFR setting for the LED function For the touch sense function it is also required to configure the ALTSEL to select the TSIN and COLA function even as LEDTSCU provides some pin over rule controls to the assigned touch sense pin with active pad turn see Table 19 6 and Figure 19 5 Table 19 6 LEDTSCU Pin Control Signals Function LD TS e LTS fn Pin Control of Assigned Pin n LED LD 0 LED Enable COL x GPIO SFR setting column 1 Passive level on COL the rest If TS EN 1 0 LED line LD EN 0 LED LINE x shadow GPIO SFR setting transferred from LDLINE Touch TS_
601. ssed The addressed slave will clear its SM2 bit and prepare to receive the data bytes that will be coming The slaves that were not being addressed retain their SM2s as set and ignore the incoming data bytes Bit SM2 has no effect in mode 0 SM2 can be used in mode 1 to check the validity of the stop bit In a mode 1 reception if SM2 1 the receive interrupt will not be activated unless a valid stop bit is received User s Manual 16 8 V1 0 2010 02 UART V 1 6 Cinfineon UART 16 5 Baud Rate Generation There are several ways to generate the baud rate clock for the serial ports depending on the mode in which they are operating The baud rates in modes 0 and 2 are fixed so they use the Fixed clock see Section 16 5 1 In modes 1 and 3 the variable baud rate is generated using either the e UART baud rate generator see Section 16 5 2 or Timer 1 see Section 16 5 3 This selection between the different variable baud rate sources is performed by bit BGS in LINST register Baud rate clock and baud rate must be distinguished from each other The serial interface requires a clock rate that is 16 times the baud rate for internal synchronization Therefore the UART baud rate generator and Timer 1 must provide a baud rate clock to the serial interface where it is divided by 16 to obtain the actual baud rate The abbreviation refers to the input clock frequency 16 5 1 Fixed Clock The baud rates in m
602. st been received DATA Data Register Reset Value 00 RMAP 0 PAGE X 7 6 5 4 3 2 1 0 DATA rw Field Bits Type Description DATA 7 0 rw Data Byte Data to be sent or received User s Manual 17 17 V1 0 2010 02 V1 1 Cinfineon XC82x 17 9 3 Control Register The CNTR register is used to configure the IIC and generate START and STOP conditions It also contains the interrupt status flag Inter IC Bus CNTR Control Register DC Reset Value 00 RMAP 0 PAGE X 7 6 5 4 3 2 1 0 IEN ENAB STA STP IFLG AAK 0 rw rw rwh rwh rwh rw r Field Bits Type Description AAK 2 rw Assert Acknowledge A NACK is sent when a data byte is received in master or slave mode 1 X An ACK is sent if one of the following has been received 1 a matching 7 bit or either byte of the 10 bit slave address 2 general call address 3 a data byte in master or slave mode Note If the bit is cleared to in slave transmitter mode the byte in the DATA register is assumed to be the last byte IFLG 3 rwh Interrupt Flag The IFLG bit is set by hardware and can only be cleared by software interrupt event has occurred 1g An interrupt event has occurred User s Manual V1 1 17 18 V1 0 2010 02 Cinfineon XC82x Inter IC Bus Field Bits Type Description STP rwh Master
603. st to disable the CCU default T2 DIS 3 rw T2 Disable Request Active high 0 T2 is in normal operation 1 Request to disable the T2 default MDU DIS 4 rw MDU Disable Request Active high 0 MDU is in normal operation 1 Request to disable the MDU default User s Manual 7 21 V1 0 2010 02 Cinfineon XC82x System Control Unit Field Bits Description LTS_DIS 6 rw LEDTSCU Disable Request Active high 0 LEDTSCU is in normal operation 1 Request to disable the LEDTSCU default liC_DIS 7 rw Disable Request Active high 0 is in normal operation 1 Request to disable the IIC default 0 5 r Reserved Returns 0 if read should be written with 0 User s Manual 7 22 V1 0 2010 02 Cinfineon System Control Unit 7 4 2 Power Management Register Description PMCONO Power Mode Control Register 0 Reset Value 01 RMAP 0 PAGE 1 7 6 5 4 3 2 1 0 0 WKSEL 0 PDMODE PD EWS r rw r rw rwh rw Field Bits Description EWS 0 rw External interrupt 0 Wake up Source Selected 0 External interrupt 0 wake up is not selected 1 External interrupt 0 wake up is selected PD 1 rwh Power Down Mode Enable Active High Setting this bit will cause the chip to go into a power down mode as indicated by bit PDMODE Reset by wake up circuit The PD bit is a protected bit When the Protection Scheme is activated this
604. ster High FF 00 Page 20 52 CMPMODIF Compare State Modification Register 00 Page 20 53 L Low CMPMODIF Compare State Modification Register AT 00 Page 20 54 H High T12MSELL 12 Capture Compare Mode Select 9A 00 Page 20 55 Register Low T12MSELH 12 Capture Compare Mode Select 9B 00 Page 20 55 Register High TCTROL Timer Control Register 0 Low 00 Page 20 57 TCTROH Timer Control Register 0 High AT 00 20 59 TCTR2L Timer Control Register 2 Low FA 00 Page 20 61 TCTR2H Timer Control Register 2 High FB 00 20 63 TCTR4L Timer Control Register 4 Low 9C 00 Page 20 64 TCTR4H Timer Control Register 4 High 9D 00 Page 20 65 Timer T13 related Registers T13L Timer 13 Counter Register Low FC 00 Page 20 79 T13H Timer 13 Counter Register High FD 00 20 79 T13PRL Timer 13 Period Register Low 9E 00 Page 20 81 T13PRH Timer 13 Period Register High OF 00 Page 20 81 User s Manual 20 6 V1 0 2010 02 CCU6 V4 0 Cinfineon XC82x Capture Compare Unit 6 CCU6 Table 20 1 CCU6 Module Register Summary cont d Short Name Description Offset Reset See Value Page CC63RL Compare Register for Timer 13 Low 9A 00 Page 20 83 CC63RH Compare Register for Timer 13 High 9B 00 20 83 CC63SRL Shadow Register for Timer 13 00 20 84 Low CC63SRH Compare
605. ster Low FC Reset Value 00 RMAP 0 PAGE 3 7 6 5 4 3 2 1 0 T13CVL rwh Field Bits Type Description T13CVL 7 0 rwh Timer 13 Counter Value This register represents the lower 8 bits of 16 bit counter value of Timer13 Note While timer T13 is stopped the internal clock divider is reset in order to ensure reproducible timings and delays T13 Counter Register High FD Reset Value 00 RMAP 0 PAGE 3 7 6 5 4 3 2 1 0 T13CVH rwh User s Manual 20 79 V1 0 2010 02 CCUG V4 0 Cinfineon XC82x Capture Compare Unit 6 CCU6 Field Bits Type Description T13CVH 7 0 rwh Timer 13 Counter Value This register represents the upper 8 bits of 16 bit counter value of Timer13 Note While timer T13 is stopped the internal clock divider is reset in order to ensure reproducible timings and delays User s Manual CCU6 V4 0 20 80 V1 0 2010 02 Cinfineon Capture Compare Unit 6 CCU6 20 4 6 2 Period Register The generation of the patterns for a single channel pulse width modulation PWM is based on timer T13 The registers related to timer T13 can be concurrently updated with well defined conditions in order to ensure consistency of the PWM signal T13 can be synchronized to several timer T12 events Timer T13 only supports compare mode on its compare channel CC63 Register T13 represents the counting value of timer T13 It can on
606. ster Receive In the master receive mode the IIC will receive a number of bytes from a slave transmitter After the START condition has been transmitted the IFLG bit will be set and status code 08 will be in the STAT register The DATA register should now be loaded with the slave address or the first part of a 10 bit slave address with the LSB set to 1 to signify Read The IFLG bit should now be cleared to 0 to prompt the transfer to continue When the 7 bit slave address or the first part of a 10 bit address and the Read bit have been transmitted the IFLG bit will be set again A number of status codes are possible in the STAT register User s Manual 17 10 V1 0 2010 02 V1 1 Cinfineon Inter IC Bus Table 17 9 Status Code after Address is Transmitted in Master Receive Mode Code IIC State CPU Response Next Action 40 Addr R Clear IFLG AAK 0 Receive data byte transmit transmitted ACK not ACK received Or clear IFLG AAK 1 Receive data byte transmit ACK 484 Addr R Set STA clear IFLG Transmit repeated START transmitted ACK not received Or set STP clear IFLG Transmit STOP Or set STA and STP clear Transmit STOP then IFLG START 384 Arbitration lost Clear IFLG Return to idle state Or set STA clear IFLG Transmit START when bus is free 68 Arbitration lost Clear IFLG 0 Receive data byte transmit SLA W received not ACK ACK transmitted Or clear IFLG
607. t No distinction is made between a corrected 1 bit error result is valid and an uncorrected 2 bit error result is invalid In both cases an ECC non maskable interrupt NMI event is generated bit FNMIECC in register NMISR is set and if enabled via NMICON NMIECC an NMI to the CPU is triggered The 16 bit Flash address at which the ECC error occurs is stored in the system control SFRs FEAL and FEAH and can be accessed by the interrupt service routine to determine the Flash bank sector in which the error occurred User s Manual 4 9 V1 0 2010 02 Flash Memory V 0 1 Cinfineon nears Flash Memory 4 5 1 Flash Error Address Register The FEAL and FEAH registers together store the 16 bit Flash address at which the ECC error occurs The bit field PAGE of SCU_PAGE register must be programmed before accessing these registers FEAL Flash Error Address Register Low byte F6 Reset Value 00 RMAP 0 PAGE 5 7 6 5 4 3 2 1 0 ECCERRADDR 7 0 rh Field Bits Description ECCERRADDR 7 0 rh ECC Error Address Value 7 0 FEAH Flash Error Address Register High byte F7 Reset Value 00 RMAP 0 PAGE 5 7 6 5 4 3 2 1 0 ECCERRADDR 15 8 rh Field Bits Type Description ECCERRADDR 7 0 rh ECC Error Address Value 15 8 User s Manual 4 10 V1 0 2010 02 Flash Memory V 0 1 Cinfineon nears Flash Memory 4 6 In System Programming In System Pr
608. t MMICR 2 NMIRRE MMICRO FNMIOCDS Heo IRAM write FuMRw Le o MS NMIOCDS event NMICON 3 MMICR1 Maskable Interrupt VDDC Prewaming ENMIVDDC LM o NMISRA NMIVDD NMICON 4 VDDP Prewaming FNMIVDDP L gt NMISRS NMIVDDP NMICON 5 Flash ECC Error n FNMIECC e oL NMISR NMIECC NMICON 6 Figure 9 6 Non Maskable Interrupt Request Source User s Manual 9 7 V1 0 2010 02 Interrupt System V 2 3 3 Cinfineon Interrupt System 9 1 1 Interrupt Source and Vector Each interrupt event source has an associated interrupt vector address for the interrupt node it belongs to This vector is accessed to service the corresponding interrupt node request The interrupt service of each interrupt node can be individually enabled or disabled via an enable bit The assignment of the XC82x interrupt sources to the interrupt vector address and the corresponding interrupt node enable bits are summarized in Table 9 1 Table 9 1 Interrupt Vector Address Interrupt Vector Assignment for XC82x Enable Bit SFR Node Address NMI 0073 Watchdog Timer NMI NMIWDT NMICON 48 MHz and 75 KHz clock NMI NMIOSCCLK Flash Operation Complete NMIFLASH NMI OCDS NMI NMIOCDS ECC Error NMI NMIECC VDDP Prewarning NMI NMIVDDP VDDC Prewarning NMI NMIVDDC XINTRO 0003 External Interrupt 0 IENO XINTR1 000B Timer 0 ETO XINTR2 0013 External Interrupt 1 1 XINTR3 001B Time
609. t data byte byte W IFLG receives ACK transmitted ACK received Or set STA clear IFLG Transmit repeated START Or set STP clear IFLG Transmit STOP Or set STA and STP clear Transmit STOP then IFLG START Second address Same as for code DO Same as for code DO byte W transmitted ACK not received If a repeated START condition has been transmitted the status code will be 10 instead of 084 After each data byte has been transmitted IFLG will be set and one of three status codes will be in the STAT register User s Manual V1 1 17 9 V1 0 2010 02 Cinfineon Inter IC Bus Table 17 8 Status Code after Data is Transmited in Master Transmit Mode Code 1 State CPU Response Next Action 28 Data byte Write byte to DATA clear Transmit data byte transmitted IFLG receives ACK ACK received Or set STA clear IFLG Transmit repeated START Or set STP clear IFLG Transmit STOP Or set STA and STP clear Transmit STOP then IFLG START 30 Data byte Same as for code 28 Same as for code 284 transmitted ACK not received 38 Arbitration lost Clear IFLG Return to idle state Or set STA clear IFLG Transmit START when bus is free When all bytes have been transmitted the STP bit should be set by writing a 1 to this bit in the CNTR register The IIC will then transmit a STOP condition clear the STP bit and return to idle state status code F8 17 8 2 Ma
610. t leakage current of the respective ADC channel Furthermore the leakage is influenced by an overload condition at adjacent analog inputs During an overload condition an input voltage exceeding the supply range is applied at an input and the built in protection circuit limits the resulting input voltage This leads to an overload current through the protection circuit that is translated by a coupling factor into an additional leakage at adjacent inputs User s Manual 21 11 V1 0 2010 02 ADC V2 1 Cinfineon Analog to Digital Converter 21 4 Transfer Characteristics and Error Definitions The transfer characteristic of the ADC describes the association of analog input voltages to the 2 discrete digital result values n bits resolution Each digital result value in the range of 0 to 2 1 represents an input voltage range defined by the reference voltage range divided by 2 This range called quantization step or code width represents the granularity called LSB of the ADC The discrete character of the digital result generates a system inherent quantization uncertainty of 0 5 LSB for each conversion result The ideal transfer curve has the first digital transition between 0 and 1 when the analog input reaches 0 5 LSB The quantization steps are equally distributed over the input voltage range Analog input voltages below or above the reference voltage limits lead to a saturation of the digital result at 0 or 27 1 The r
611. target of an access to CON control bits or flags is determined by the state of CON EN prior to the access that is writing C057 to CON in programming mode CON EN 0 will initialize the SSC CON EN was 0 and then turn it on CON EN 1 When writing to CON ensure that reserved locations receive Zeros User s Manual SSC V1 4 18 25 V1 0 2010 02 Cinfineon neers High Speed Synchronous Serial Interface 18 5 2 Baud Rate Timer Reload Register The SSC baud rate timer reload register BR contains the 16 bit reload value for the baud rate timer SSC_BRL Baud Rate Timer Reload Register Low Reset Value 00 RMAP 0 PAGE X 7 6 5 4 3 2 1 0 BR_VALUE rw Field Bit Type Description BR_VALUE 7 0 rw Baud Rate Timer Reload Register Value Reading BR returns the 16 bit contents of the baud rate timer Writing BR loads the baud rate timer reload register with BR_VALUE SSC_BRH Baud Rate Timer Reload Register High AF Reset Value 00 RMAP 0 PAGE X 7 6 5 4 3 2 1 0 BR_VALUE rw Field Bit Type Description BR_VALUE 7 0 rw Baud Rate Timer Reload Register Value Reading BR returns the 16 bit contents of the baud rate timer Writing BR loads the baud rate timer reload register with BR_VALUE 18 5 3 Transmitter Buffer Register The SSC transmitter buffer register TB contains the transmit data value User s Manual 18 26 V1 0 2010 02 SSC V1 4 Cinf
612. te Generator Reload register Reading BG returns the contents of the timer while writing to BG low byte always updates the reload register The BG should be written only when BCON R is 0 An auto reload of the timer with the contents of the reload register is performed one instruction cycle after the next time BCON R is set Any write to BG while BCON R is set will be ignored The baud rate of the baud rate generator depends on the following bits and register values e Input clock feci Value of bit field BCON BRPRE Value of bit field BG FD SEL Value of the 11 bit reload value BG BR VALUE Figure 16 3 shows a simplified block diagram of the baud rate generator fpi Baud rate timer far fPcLk Prescaler with 7 Fractional Divider R Figure 16 3 Simplifed Baud Rate Generator Block Diagram The following formula calculate the final baud rate 16 2 fPCLK 16 x PRE x BR vALUE i Baud rate The value of PRE prescaler is chosen by the bit field BCON BRPRE BR VALUE represents the contents of the reload value taken as unsigned 11 bit integer from the bit User s Manual 16 10 V1 0 2010 02 UART V 1 6 Cinfineon XC82x UART field BG BR_VALUE n 32 is defined by the fractional divider selection in bit field BG FDSEL The maximum baud rate that can be generated is limited to 32 Hence for module clocks of 8 MHz and 24 MHz the maximum achievable baud rate is 0 25 MBaud a
613. te receive register SBUF Serial Data Buffer 99 Reset Value 00 RMAP X PAGE X 7 6 5 4 3 2 1 0 VAL rwh Field Bits Type Description VAL 7 0 rwh_ Serial Interface Buffer Register SCON Serial Channel Control Register 98 Reset Value 00 RMAP X PAGE X 7 6 5 4 3 2 1 0 SMO SM1 SM2 REN TB8 RB8 TI RI rw rw rw rw rw rwh rwh rwh Field Bits Type Description RI 0 rwh Receive Interrupt Flag This is set by hardware at the end of the 8th bit on mode 0 or at the half point of the stop bit in modes 1 2 and 3 Must be cleared by software User s Manual 16 20 V1 0 2010 02 UART V 1 6 XC82x Infineon UART Field Bits Description Tl 1 rwh_s Transmit Interrupt Flag This is set by hardware at the end of the 8th bit in mode 0 or at the beginning of the stop bit in modes 1 2 and 3 Must be cleared by software RB8 2 rwh Serial Port Receiver Bit 9 In modes 2 and 3 this is the 9th data bit received In mode 1 this is the stop bit received In mode this bit is not used TB8 3 rw Serial Port Transmitter Bit 9 In modes 2 and 3 this is the 9th data bit sent REN 4 rw Enable Receiver of Serial Port Og Serial reception is disabled 1g Serial reception is enabled SM2 5 rw Enable Serial Port Multiprocessor Communication in Modes 2 and 3 In mode 2 or 3 if SM2 is set to 1 RI will not be activated if the received 9th dat
614. ted by MODPISEL2 T2EXIS Among these sources 4 of them are available as external pin 2 of them are triggered internally by Out of Range 0 ORCO event and Out of Range 1 ORC1 event from the ADC module The Timer 2 pin assignment for XC82x is shown in Table 14 1 Table 14 1 Timer 2 Pin Functions in XC82x Pin Sources Function Desciption Selected By P0 0 T2_0 Timer 2 Input MODPISEL2 T2IS 00 P2 0 T2_1 MODPISEL2 T2IS 01g P2 3 T2 2 MODPISEL2 T2IS 10g User s Manual 14 1 V1 0 2010 02 Timer 2 V 1 2 Cinfineon Timer 2 Table 14 1 Timer 2 Pin Functions in XC82x Pin Sources Function Desciption Selected By P0 6 T2EX 0 Timer 2 External Trigger MODPISEL2 T2EXIS 000 P0 4 T2EX_1 Input MODPISEL2 T2EXIS 001 P1 0 T2EX_2 MODPISEL2 T2EXIS 010 P2 0 T2EX_3 MODPISEL2 T2EXIS 011 event T2EX 4 MODPISEL2 T2EXIS 100 ORC1 event T2EX 5 MODPISEL2 T2EXIS 101 The bit field PAGE of SCU_PAGE register must be programmed before accessing the MODPISEL2 register MODPISEL2 Peripheral Input Select Register 2 F5 Reset Value 00 RMAP 0 PAGE 3 7 6 5 4 3 2 1 0 0 TOIS 115 215 T2bXIS r rw rw rw rw Field Bits Description T2bEXIS 2 0 rw Timer 2 External Input Select 000 Timer 2 Input T2EX 0 is selected 001 Timer 2 Input T2EX 1 is selected 010 Timer 2 Input T2EX 2 is selected
615. teger Multiplication 23 39 1 Long Multiplication rrr ER reor 23 40 1 Integer DIVISION 2222 222 22 424 1 2 23 41 1 LONG DIVISION 23 42 1 EEPROM Emulation ROM Library 23 44 1 E edo Sanna Pa bee 23 44 1 System 23 44 1 Concept lk enda Seta a eee hb NEP eke 23 44 1 23 46 1 Constant definition 23 46 1 EEPROMInfo data structure 23 46 1 Functions ims dcs re pionie e ed og etus 23 47 1 Example of API usage 23 50 1 User s Manual 1 12 V1 0 2010 02 Cinfineon Introduction 1 Introduction The XC82x is a member of the high performance XC800 family of 8 bit microcontrollers It is based on the XC800 Core that is compatible with the industry standard 8051 processor The XC82x features a great number of enhancements to enable new application technologies through its highly integrated on chip components such as on chip oscillator or an integrated voltage regulator allowing a range of voltage supply of 2 5 V to 5 5 V In addition the XC82x is equipped with embedded Flash memory to offer high flexibility in development and ramp up The
616. ten at the start of the next calculation phase First Write Start bit is set First Read Last Read Phase 1 Phase 2 Phase 3 Load Registers Calculate Read Registers Time Figure 12 1 Operating Phases of the MDU 12 3 1 Division The MDU supports the truncated division operation which is also the ISO C99 standard and the popular choice among modern processors The division and modulus functions of the truncated division are related in the following way User s Manual 12 4 V1 0 2010 02 MDU V2 9 Cinfineon Multiplication Division Unit If q D div d and r D mod d then D q d r and lt where is the dividend is the divisor is the quotient is the remainder The truncated division rounds the quotient towards zero and the sign of its remainder is always the same as that of its dividend i e sign r sign D 12 3 2 Normalize The MDU supports up to 32 bit unsigned normalize Normalizing is done on an unsigned 32 bit variable stored in MDO least significant byte to MD3 most significant byte This feature is mainly meant to support applications where floating point arithmetic is used During normalization all leading zeros of an unsigned 32 bit variable in registers MDO to MD3 are removed by shift left operations The whole operation is completed when the MSB most significant bit contains a 1 After normalizing bit field MR4
617. ter Type rwh rwh rwh rh rwh rwh rw rw F5H MMDR Reset 004 Bit Field MMRR Monitor Mode Data Transfer Register Type Receive MMDR Reset 004 Bit Field MMTR Monitor Mode Data Transfer Register Type Transmit Fey HWBPSR Reset 004 Bit Field 0 BPSEL BPSEL Hardware Breakpoints Select de Register Type r w rw HWBPDR Reset 004 Bit Field HWBPxx Hardware Breakpoints Data Register Type M User s Manual 3 32 V1 0 2010 02 Memory Organization V 0 1 Cinfineon XC82x Memory Organization Table 3 12 OCDS Register Overview cont d Addr Register Name Bit 7 6 4 3 1 0 EB MMWR1 Reset 004 Bit Field MMWR1 Monitor Work Register 1 Type rw MMWR2 Reset 004 Bit Field MMWR2 Monitor Work Register 2 Type TW User s Manual 3 33 V1 0 2010 02 Memory Organization V 0 1 Cinfineon nears Flash Memory 4 Flash Memory The XC82x has an embedded user programmable non volatile Flash memory that allows for fast and reliable storage of user code and data It is operated with a single 2 5 supply from the Embedded Voltage Regulator EVR and does not require additional programming or erasing voltage The sectorization of the Flash memory allows each sector to be erased independently Features In System Programming ISP via UART In Application Programming IAP Error Correction Code ECC for dynamic correction of single bit errors e Back
618. ter PSLR Bits TRPS 1 and TRPF 0 can occur if the trap condition is no longer active but the selected synchronization has not yet taken place User s Manual CCU6 V4 0 20 115 V1 0 2010 02 Cinfineon Capture Compare Unit 6 CCU6 20 9 2 2 Interrupt Status Set Register Register ISSL H contains individual interrupt request set bits to generate a CCU6 interrupt request by software Writing a 1 sets the bit s in register ISL H at the corresponding bit position s and can generate an interrupt event if available and enabled All bit positions read as 0 ISSL Interrupt Status Set Register Low A44 Reset Value 00 RMAP 0 PAGE 2 7 6 5 4 3 2 1 0 ST12PM ST120M SCC62F SCC62R SCC61F SCC61R SCC60F SCC60R w w w w w Ww w w Field Bits Type Description SCC60R 0 w Set Capture Compare Match Rising Edge Flag SCC61R 2 No action SCC62R 4 1g Bit CC6xR will be set SCC60F 1 w Set Capture Compare Match Falling Edge Flag SCC61F 3 No action SCC62F 5 1g Bit CC6XF will be set ST120M 6 w Set Timer T12 One Match Flag Og action 1g Bit T12OM will be set ST12PM 7 w Set Timer T12 Period Match Flag Og action 1g Bit T12PM will be set ISSH Interrupt Status Set Register High 5 Reset Value 00 RMAP 0 PAGE 2 7 6 5 4 3 2 1 0 SSTR SIDLE SWHE SCHE SWHC STRPF ST13PM ST13CM w Ww w w w w w
619. ter description 17 15 Register map 17 15 Slave receive 17 13 Slave transmit 17 12 Software reset 17 7 Status code 17 4 In Application Programming 4 11 4 12 Aborting background Flash erase 4 14 Background Flash erase 4 14 Background Flash program 4 13 Flash read mode status 4 16 Non background Flash erase 4 14 Non background Flash program 4 13 In System Programming 4 11 Inter IC Bus 17 1 Internal data memory 3 2 Internal RAM 3 1 Interrupt 9 1 Flags 9 32 Handling 9 12 Priority 9 30 Registers 9 16 V1 0 2010 02 Cinfineon XC82x Structure 9 10 Type 1 9 11 Type 2 9 11 Interrupt Response Time 9 13 L LED and Touch Sense Controller 19 1 LED Controller 19 1 LEDTSCU 19 1 FNCOL Interpretation 19 16 Function 19 5 Function Enable amp Control 19 15 Interrupt 19 19 LED Driving 19 8 Pin Control 19 18 Pin Current Capability 19 10 Registers 19 20 Time Multiplexed Function 19 14 Timing Calculations 19 16 Touch Sensing 19 11 LIN 16 13 Baud rate detection 16 18 Baud rate range selection 16 16 Break field 16 14 Break synch field detection 16 16 Header transmission 16 15 LIN frame 16 13 LIN protocol 16 13 Synch byte 16 14 M MDU 12 1 12 14 Division 12 4 Division with single right shift 12 6 Error detection 12 6 Interrupt generation 12 7 Multiplication with single left shift 12 5 Normalize 12 5 Register description 12 8 Register map 12 8 Shift 12 5 Memory organization 3 1 Special Function Registers 3 4 User s
620. tes Machine Machine Cycles Cycles one wait state no wait state BOOLEAN CLR C C3 1 1 2 CLR bit C2 2 1 3 SETBC D3 1 1 2 SETB bit D2 2 1 3 CPL C B3 1 1 2 CPL bit B2 2 1 3 ANL C bit 82 2 2 4 ANL C bit BO 2 2 4 ORL C bit 72 2 2 4 ORL C bit 2 2 4 MOV C bit A2 2 1 3 MOV bit C 92 2 2 4 BRANCHING ACALL addr11 11 gt F1 2 2 4 LCALL addr16 12 3 2 5 RET 22 1 2 2 or 3 RETI 32 1 2 2 or 3 AJMP addr 11 01 gt E1 2 2 4 LJMP addr 16 02 3 2 5 SJMP rel 80 2 2 4 JC rel 40 2 2 4 JNC rel 50 2 2 4 JB bit rel 20 3 2 5 JNB bit rel 30 3 2 5 JBC bit rel 10 3 2 5 JMP A DPTR 73 1 2 2 or 3 JZ rel 60 2 2 4 JNZ rel 70 2 2 4 User s Manual 2 13 V1 0 2010 02 XC800 Core V 1 0 2 on Cinfineon 800 Table 2 1 Instruction Table cont d Mnemonic Hex Code Bytes Machine Machine Cycles Cycles one wait state no wait state CJNE A dir rel B5 3 2 5 CJNE A Zd rel B4 3 2 5 CJNE Rn Zd rel B8 BF 3 2 5 CJNE Ri d rel B6 B7 3 2 5 DJNZ D8 DF 2 2 4 DJNZ D5 3 2 5 MISCELLANEOUS NOP 00 1 1 2 ADDITIONAL INSTRUCTIONS MOVC DPTR A A5 1 2 2 or 3 TRAP A5 1 1 1 In case of fetch from slow memory requiring only 1 wait state no cycle may be fetched normally for opcodes that do not require fetch in the next cycle required per the instruction 2 Depending on whether the operation is accessing m
621. th OWDs can be enabled When a 1 is detected in bit INTOSC_ST the 75 KHz oscillator should be running in a stable trimmed frequency Next the OWD function could be enabled by setting bit RCOWDRST in OSC_CON register User code is recommended to continue when 48MOSC2L and 75KOSC2L is both 0 User can also choose to continue with other operations while waiting for a stable 48MOSC2L 75KOSC2L The loss of oscillator clock NMI would be based on these 2 signals to trigger a NMI if it is enabled via bit NMICON NMIOSCCLK 7 3 2 Loss of Clock Detection and Recovery Loss of clock happens when the 48 MHz oscillator watchdog detects a frequency that is less than 40 MHz during normal operation In this case an NMI interrupt will be generated if it is enabled by NMICON NMIOSCCLK Concurrently the oscillator status 48MOSC2L is set to 1 and the system clock will be provided by a stable 75 KHz oscillator Emergency routines can be executed with the XC82x clocked with this oscillator In case of a malunction 75 KHz oscillator there will be no switching and the system clock source remains to be the 48 MHz oscillator However the 48 MHz oscillator watchdog will not be functioning No monitoring of this master clock is possible User s Manual 7 12 V1 0 2010 02 Cinfineon System Control Unit When the 75 KHz oscillator is detected to be malfunction the 75 KHz oscillator watchdog status flag 75 gt KOSC2L is set to 1 An NMI interrupt wi
622. the baud rate 1g Double the baud rate 0 1 r Reserved 0 6 4 Returns 0 if read should be written with 0 2 3 8 Interrupt Registers One non maskable and fourteen maskable interrupt nodes are available Refer to Interrupt chapter for details of the interrupt registers User s Manual 2 6 V1 0 2010 02 XC800 Core V 1 0 2 Cinfineon 800 2 4 SFRs of The Core Peripherals 2 4 1 Timer Registers Two 16 bit timers are provided Timer 0 TO and Timer 1 T1 Refer to Timer 0 and Timer 1 chapter for details of the timer registers 2 4 2 UART Registers The UART uses three SFRs PCON SCON and SBUF Refer to Section 2 3 7 and UART chapter for details of the UART registers User s Manual 2 7 V1 0 2010 02 XC800 Core V 1 0 2 Cinfineon XC800 Core 2 5 Instruction Timing A CPU machine cycle comprises two input clock periods referred to as Phase 1 P1 and Phase 2 P2 that correspond to two different CPU states A CPU state within an instruction is referenced by the machine cycle and state number e g C2P1 means the first clock period within machine cycle 2 Memory access takes place during one or both phases of the machine cycle SFR writes occur only at the end of P2 Instructions are 1 2 or 3 bytes long and can take 1 2 or 4 machine cycles to execute Registers are generally updated and the next opcode pre fetched at the end of P2 of the last machine cycle for the current instructi
623. the data of the selected slave In the master and all slaves the contents of the shift register are copied into the receive buffer RB and the receive interrupt line RIR is activated A slave device will immediately output the selected first bit MSB or LSB of the transfer data at line RXD when the contents of the transmit buffer are copied into the slave s shift register Bit CON BSY is not set until the first clock edge at SS_CLK appears The slave device will not wait for the next clock from the baud rate generator as the master does The reason for this is that depending on the selected clock phase the first clock edge generated by the master may already be used to clock in the first data bit Thus the slave s first data bit must already be valid at this time Note On the SSC a transmission and a reception takes place at the same time regardless of whether valid data has been transmitted or received Note The initialization of the CLK pin on the master requires some attention in order to avoid undesired clock transitions which may disturb the other devices Before the clock pin is switched to output mode the clock output level will be selected in the control register CON and the alternate output be prepared via the related ALTSEL register or the output latch must be loaded with the clock idle level User s Manual 18 12 V1 0 2010 02 SSC V1 4 Cinfineon neers High Speed Synchronous Serial Interface 18 3 3 Half Duplex Op
624. the event indication flags in register IS and can trigger the interrupt generation The interrupt pulse is generated independently from the interrupt status flag in register IS it is not necessary to clear the related status bit to be able to generate another interrupt The interrupt flag can be cleared by SW by writing to the corresponding bit in register ISR If enabled by the related interrupt enable bit in register IEN an interrupt pulse can be generated on one of the four service request outputs SRO to SR3 of the module If more than one interrupt source is connected to the same interrupt node pointer in register INP the requests are logically OR combined to one common service request output see Figure 20 41 SW Requests Clear Interrupt Interrupt Interrupt Status Node Pointer Interrupt Enable Set Interrupt gt 1 HW Interrupt Event CCU6_MCA05549 Figure 20 41 General Interrupt Structure The available interrupt events in the CCU6 are shown in Figure 20 42 User s Manual 20 110 V1 0 2010 02 CCU6 V4 0 Cinfineon XC82x Capture Compare Unit 6 CCU6 T12 Counter T12 Capture Compare Channels CC6x T13 Counter T13 Compare Channel CC63 Multi Channel Mode Logic Hall Compare Logic Trap Handling T12 PM T12 OM CC6x CC6x T13 PM Interrupt Control Logic CM 63 STR CM CHE CM WHE TRPF TRPS Interrupt Request Reg CC6x
625. timer control registers TCTROL TCTROH and TCTR2L TCTR2H Specific actions are triggered by write operations to register TCTR4L TCTR4H User s Manual 20 42 V1 0 2010 02 CCU6 V4 0 Cinfineon Capture Compare Unit 6 CCU6 20 3 8 112 related Registers 20 3 8 1 T12 Counter Register Register T12 represents the counting value of timer T12 It can only be written while the timer T12 is stopped Write actions while T12 is running are not taken into account Register T12 can always be read by SW In edge aligned mode T12 only counts up whereas in center aligned mode T12 can count up and down T12L Timer T12 Counter Register Low FA Reset Value 00 RMAP 0 PAGE 3 7 6 5 4 3 2 1 0 T12CVL rwh Field Bits Type Description T12CVL 7 0 rwh T12 Counter Value This register represents lower 8 bits of the 16 bit counter value of T12 T12H Timer T12 Counter Register High Reset Value 00 RMAP 0 PAGE 3 7 6 5 4 3 2 1 0 T12CVH TWA Field Bits Type Description T12CVH 7 0 rwh Timer T12 Counter Value This register represents upper 8 bits of the 16 bit counter value of T12 User s Manual 20 43 V1 0 2010 02 CCU6 V4 0 Cinfineon Capture Compare Unit 6 CCU6 20 3 8 2 Period Register Register T12PRL H contains the period value for timer T12 The period value is compared to the actual counter value of T12 and the resulti
626. timing critical sequences containing also multiple conversions of the same channel User s Manual 21 26 V1 0 2010 02 ADC V2 1 Cinfineon Analog to Digital Converter Queued Source Operation Configure the queued request source by executing the following actions Define the sequence by writing the entries to the queue input ADC_QINRbO Initialize the complete sequence before enabling the request source because with enabled refill feature software writes to QINRx are not allowed If hardware trigger is desired select the appropriate trigger inputs by programming ADC ETRCR Enable the trigger by programming bitfield ENGT in register ADC QMRO Enable the corresponding arbitration slot 0 to accept conversion requests from the queued source see register ADC_PRAR Start a queued sequence by generating a trigger event Ifa hardware trigger is selected and enabled generate the configured transition at the selected input signal e g from a timer or an input pin Generate a software trigger event by setting QMRx TREV 1 Write a new entry to the queue input of an empty queue This leads to a new valid queue entry that is forwarded to queue stage 0 and starts a conversion request if enabled by QMRx ENGT and without waiting for an external trigger Note If the refill mechanism is activated a processed entry is automatically reloaded into the queue This permanently repeats the respective sequence autoscan
627. tine Subroutine BR_FLASH_ERASE Input R7 of Current Register Bank Select sector s to be erased for the Flash Bank 0 LSB represents sector 0 MSB represents sector 7 R6 of Current Register Bank Select sector s to be erased for the Flash Bank 0 LSB represents sector 8 and bit 1 represents sector 9 SFR NMISR 00 All interrupts including NMI must be disabled IENO EA 0 NMICON 00 Output PSW CY 0 Flash erasing is successful 1 Flash erasing is not successful 1 Invalid No input s is given Stack size required 12 Resource DPTR A used destroyed R2 and R7 of current Register Bank 2 bytes 1 The inputs should be set as 0 if the sector s of the bank is are not to be selected for erasing The second type of routine supports background erasing BR_FLASH_BACKGROUND_ERASE allows the user program code to continue execution after the erasing routine is called User will wait until the Flash NMI event is generated bit FNMIFLASH in register NMISR is set and if enabled via NMIFLASH an NMI to the CPU is triggered to enter the Flash NMI service routine At this point the Flash bank is in ready to read mode i e erasing is done Note When invalid No input s is provided for this routine C flag will be set and routine will be exited Nothing else will be done User s Manual 22 10 V1 0 2010 02 BootROM User Routines V1 1 Cinfineon Boot ROM User Routines Table 22 12 Specifi
628. tion with external events such as a trigger pulse from a timer generating a PWM signal or from a port pin Application software selects the trigger the channel s to be converted and the request source priority A request source can also be activated directly by software without requiring an external trigger The arbiter regularly scans the request sources for pending conversion requests and selects the conversion request with the highest priority This conversion request is then forwarded to the converter to start the conversion of the requested channel Each request source can operate in single shot or in continuous mode n single shot mode the programmed conversion sequence is requested once after being triggered A subsequent conversion sequence must be triggered again n continuous mode the programmed conversion sequence is automatically requested repeatedly after being triggered once For each request source external triggers are generated from one of 8 selectable trigger inputs REQTRX H A request control ADC kernel request p source 0 4 stage queue request Ly request source 1 source analog part 4 8 ch scan 4 arbiter external request s Note 1 8 channel scan are for devices with 8 ADC channels and 4 channel scan are for devices with 4 ADC channels ADC request handling 2 Figure 21 5 Conversion Request Unit User s Manua
629. tionality The basics for implementation of this feature are the Breakpoint Generation module is able to recognize read write accesses to IRAM address ranges refer to Section 10 4 1 2 upon a breakpoint match but while MMCR2 MBCON 1 the Monitor firmware is not started and therefore in fact no debug session takes place To configure trigger and handle an OCDS NMI request upon IRAM access refer also to Section 10 5 1 1 is possible only as long as MMCR2 MBCON 1 2 user software must execute the following sequence a set the NMl enable bit s NMIRRE NMIRWE in MMICR respectively for request upon IRAM read write b write the low address es of the observed area into HWBP2L HBWBPS3L respectively for NMI request upon IRAM read write C write the high address es of the observed area into HWBP2H HBWBP3H respectively for NMI request upon IRAM read write 3 after the settings according to point 2 are done and as long as MBCON 1 a NMI request will be triggered by the OCDS upon an access to the respectively configured for read write IRAM area s 4 in case a NMl request has been raised by the OCDS respective flag FNMIRR FNMIRW is set in MMICR refer to the register description Section 10 8 1 and functional definition in Section 10 5 1 If the request is sent to the core in case enabled by NMICON NMIOCDS 1 in SCU then a NMl servicing routine will be invoked by a jump to its standard location in XC800 Program
630. tive channel numbers when requested The programmed alias channel number controls the analog input multiplexer of the converter The original channel number controls all other internal actions and the synchronization request ADC_ALRO Alias Register 0 Reset Value 00 RMAP 0 PAGE 4 7 6 5 4 3 2 1 0 0 ALIASO 1 Field Bits Type Description ALIASO 2 0 rw Alias Value for CHO Conversion Requests The channel indicated in this bit field is converted instead of channel CHO The conversion is done with the settings defined for channel CHO The default for this is CHO Note Bit 2 is only applicable for devices that have 8 ADC channels For channels not implemented these bits should be treated as Reserved bits of type r which returns 0 if read and should be written with O 0 7 3 r Reserved Returns 0 if read should be written with 0 User s Manual ADC V2 1 21 56 V1 0 2010 02 Cinfineon Analog to Digital Converter 21 8 5 Out of Range Comparator The out of range comparator mechanism is build into every ADC channels and detects voltages higher or lower than Vddp Before using the out of range comparator it has to be enabled by setting the bits at ADC_ENORC ENORCx and configuring it to detect voltage higher or lower than Vddp by setting bits ADC_CORC CNFx See Figure 21 19 SR1 ORCEVENTO 4 ADC out of range comparator vsd Figure 21 19
631. triggered with the next cycle of the T13 clock Bit STE13 is automatically cleared with the shadow register transfer A T13 shadow register transfer takes place T13_ST active while timer T13 is not running T13R 0 or e STE13 1 and a Period Match is detected while T13R 1 User s Manual 20 77 V1 0 2010 02 CCU6 V4 0 Cinfineon Capture Compare Unit 6 CCU6 Read Read Read Read T13lM Shadow Write Write Write Write Read e T13 ST Compare Shadow Register CC63SR Write Read CCU6_MCA05547 Figure 20 32 T13 Shadow Register Overview User s Manual 20 78 V1 0 2010 02 CCU6 V4 0 Cinfineon Capture Compare Unit 6 CCU6 20 46 113 related Registers 20 4 6 1 T13 Counter Register The generation of the patterns for a single channel pulse width modulation PWM is based on timer T13 The registers related to timer T13 can be concurrently updated with well defined conditions in order to ensure consistency of the PWM signal T13 can be synchronized to several timer T12 events Timer T13 only supports compare mode on its compare channel CC63 Register T13 represents the counting value of timer T13 It can only be written while the timer T13 is stopped Write actions while T13 is running are not taken into account Register T13 can always be read by SW Timer T13 only supports edge aligned mode counting up T13L Timer T13 Counter Regi
632. tten again before the end of 32 CCLK cycles there will be a recount of 32 CCLK cycles The protected bits are include the soft reset request bit SWRQ the Watchdog Timer enable bit WDTEN the RTC clock count registers CNTO 5 and the power down enable bit PD e RSTCON SWRQ soft reset request bit PMCONO PD power down enable bit WDTCON WDTEN WDT enable bit CNTx x 0 5 all bits of RTC clock count registers The bit field PAGE of SCU PAGE register must be programmed before accessing the PASSWD register PASSWD Password Register Reset Value 074 RMAP 0 PAGE 1 7 6 5 4 3 2 1 0 PASS in ud MODE wh rh rw User s Manual 3 11 V1 0 2010 02 Memory Organization V 0 1 Cinfineon XC82x Memory Organization Field Bits Type Description MODE 1 0 rw Bit Protection Scheme Control bits 00 Scheme disabled direct access to the protected bits is allowed 11 Scheme enabled the bit field PASS has to be written with the passwords to open and close the access to protected bits default Others Scheme enabled These two bits cannot be written directly To change the value between 11g and 00g the bit field PASS must be written with 11000 only then will the MODE 1 0 be registered PROTECT_S 2 rh Bit Protection Signal Status bit This bit shows the status of the protection 0 Software is able to write to all protected bits 1 Software is unabl
633. tures The main debug functionality supported are e Set breakpoints on instruction address and on address range within the Program Memory Set breakpoints on Internal RAM address range Support unlimited software breakpoints in Flash RAM code region Process external breaks via debug interface Step through the program code Userhandling of OCDS NMI in case of IRAM read write breakpoint 10 1 1 Components of the Debug System The components of the debug system are briefly described here Debug Interface The debug interface allows to access the device such as for data read or write The debug interface supported Single pin DAP SPD e 1 or2 pin UART The SPD interface refers to the single pin Device Access Port standardized for the Infineon microcontrollers It utilizes only one pin DAP1 for serial data in out The UART is a standard interface however OCDS hardware commands are not supported Monitor Program Part of the Boot ROM is occupied by the OCDS Monitor program or OCDS firmware On the command from the debugger the Monitor program executes the actual instructions for accessing the addressable locations such as memories sfrs of the device User s Manual 10 1 V1 0 2010 02 OCDS V 2 7 1 Cinfineon Debug System On Chip Debug System Unit OCDS The OCDS hardware is the core of the debug system controlling the debugging with interfaces to the XC800 CPU 10 2 Product Specific Information Th
634. uccessful operation IERR 1 rwh Interrupt on Error The bit IERR is set by hardware and reset by software Og No interrupt is triggered with the occurrence of an error 1g An interrupt is triggered with the occurrence of an error BSY 2 rh Busy Bit Og MDU is not running any calculation 1g MDU is still running a calculation 0 7 3 r Reserved Returns 0 if read should be written with 0 User s Manual 12 14 V1 0 2010 02 MDU V2 9 Cinfineon 0 1 13 0 1 13 1 Overview Timer 0 and Timer 1 can function as both timers or counters When functioning as a timer Timer 0 and Timer 1 are incremented every machine cycle i e every 2 input clocks or 2 PCLKs When functioning as a counter Timer 0 and Timer 1 are incremented in response to a 1 to 0 transition falling edge at their respective external input pins TO or T1 They are useful in many timing applications such as measuring the time interval between events counting events and generating signals at regular intervals In particular Timer 1 can be used as the baud rate generator for the on chip serial port Features Four operational modes Mode 13 bit timer counter Mode 1 16 bit timer counter Mode 2 8 bit timer counter with auto reload Mode 3 Two 8 bit timers counters 13 2 System Information This section provides system information relev
635. uence and can be generated either via software or via the selected hardware triggers REQTRx conversion request control trigger amp gating unit trigger inputs REQTRx 7 0 load event conversion requests pending request source scan req uest source x scan reqsrc request request source event Figure 21 6 Scan Request Source User s Manual 21 19 V1 0 2010 02 ADC V2 1 Cinfineon Analog to Digital Converter Scan Source Operation Configure the scan request source by executing the following actions Select the input channels for the sequence by programming ADC_CRCR1 If hardware trigger is desired select the appropriate trigger inputs by programming ADC_ETRCR Enable the trigger by programming ADC_CRMR1 Define the load event operation handling of pending bits autoscan mode by programming ADC_CRMR1 A load event with bit LDM 0 copies the content of ADC_CRCR1 to ADC_CRPR1 overwrite mode This starts a new scan sequence and aborts any pending conversions from a previous scan sequence A load event with bit LDM 1 OR combines the content of ADC_CRCR1 to ADC_CRPR1 combine mode This starts a scan sequence that includes pending conversions from a previous scan sequence Enable the corresponding arbitration slot 1 to accept conversion requests from the channel scan source see register ADC_PRAR Start a channel scan sequence by generating a lo
636. uired 3 Resource A used destroyed User s Manual 22 12 V1 0 2010 02 BootROM User Routines V1 1 Cinfineon ROM Library 23 ROM Library On top of the User routines a set of useful ROM library routines is also provided to user to be used in user application The ROM Library provided are Fixed Point ROM Library LED and Touch Sense Controller ROM Library e MDU ROM Library MATH Function e EEPROM Emulation ROM Library User application would be able to call these routines by calling the functions provided in Table 23 1 for XC82x device Details of the ROM library are covered in its respective section Table 23 1 XC82x ROM Library function and its Address Addr Name Description 0xD649 CONTROLLER G16 FIXEDPOINT ROM Library OxD64F PI CONTROLLER G256 FIXEDPOINT ROM Library 0 0655 _P_CONTROLLER_G16 FIXEDPOINT ROM Library 0xD65B _P_CONTROLLER_G256 FIXEDPOINT ROM Library 0xD75B _PT1_24 FIXEDPOINT ROM Library 0xD78A _PT1_32 FIXEDPOINT ROM Library OxD7CE _CLARKE FIXEDPOINT ROM Library 0xD802 SET_CCU6_SECA FIXEDPOINT ROM Library 0 0812 SET_CCU6_SECB 7 FIXEDPOINT ROM Library 0 0822 SET_CCU6_SECC FIXEDPOINT ROM Library 0xD832 SET_CCU6_SECD FIXEDPOINT ROM Library 0 0842 SET_CCU6_SECE 7 FIXEDPOINT ROM Library 0 0852 SET_CCU6_SECF FIXEDPOINT ROM Library OxDFCO C IMUL XC MDU ROM Library OxDFC3 C LMUL XC MDU ROM Library OxDFC6 C UIDIV
637. upt will be generated if the set condition for bit T12OM in register IS occurs The service request output that will be activated is selected by bit field INPT12 User s Manual 20 120 V1 0 2010 02 CCUG V4 0 Cinfineon XC82x Capture Compare Unit 6 CCU6 Field Bits Type Description ENT12PM 7 rw Enable Interrupt for T12 Period Match interrupt will be generated if the set condition for bit T12PM in register IS occurs 1g An interrupt will be generated if the set condition for bit T12PM in register IS occurs The service request output that will be activated is selected by bit field INPT12 IENH Interrupt Enable Register High 9D Reset Value 00 RMAP 0 PAGE 2 7 6 5 4 3 2 1 0 ENSTR ENIDLE ENWHE ENCHE 0 ENTRPF ENT13PM ENT13CM rw rw rw rw rw rw rw Field Bits Type Description ENT13CM 0 rw Enable Interrupt for T13 Compare Match Og No interrupt will be generated if the set condition for bit T13CM in register IS occurs 1g An interrupt will be generated if the set condition for bit T13CM in register IS occurs The service request output that will be activated is selected by bit field INPT13 ENT13PM 1 rw Enable Interrupt for T13 Period Match No interrupt will be generated if the set condition for bit T13PM in register IS occurs 1g An interrupt will be generated if the set condition for bit T13PM in register IS occurs Th
638. urce A used destroyed R1 and R7 of current Register Bank 2 bytes User s Manual 22 3 V1 0 2010 02 BootROM User Routines V1 1 Cinfineon Boot ROM User Routines 22 3 Feature Setting Subroutine Feature Setting subroutine is provided in the Boot ROM to initialize some settings Currently only 2 options provided CLKMODE setting BR_CLKMODE_SETTING and programming of USER_ID BR_PROG_USER_ID See The CLKMODE setting sets the frequency to 8MHz or 24MHz while USER_ID programming programs the 4 bytes user identification USER ID information into device These 4 bytes of User Identification Number will consists of BMI BMI to determine entry of Mode and some initialization like clock frequency setting and enabling peripherals This BR_PROG_USER_ID routine will issue a soft reset once programming is completed Thus there is no successful indication except a reset will occur and device will bootup in the programmed boot mode This BR PROG USER ID routine will also check if NMISR is 0x00 If yes it will clear NMICON and EA and continue programming USER 10 User should take care of their watchdog service routine and to disable the wdt before calling this routine as there is no return back after calling this routine Table 22 5 Specifications of CLKMODE Setting subroutine Subroutine BR_CLKMODE_SETTING BR_FEATURE_SETTING Option 0 Input R7 of current Register Bank Option 00 Option 0 BR CLKMODE SETTING Others Reserv
639. urce for the real time clock is available Vppp 2 5 V The real time clock stops operation in software power down mode 1 User s Manual 15 5 V1 0 2010 02 RTC V1 0 Cinfineon Real Time Clock 15 7 Registers Description 14 SFRs are used to control the operation of real time clock They can be accessed from the standard non mapped SFR area The registers are described as follows Table 15 4 lists the addresses of these SFRs Table 15 4 Register Map Address Register 95 RTCON E14 CNTO E24 CNT1 E34 CNT2 EA CNT3 E74 RTCCRO EQ RTCCR1 EA RTCCR2 EB RTCCR3 User s Manual 15 6 V1 0 2010 02 RTC V1 0 Cinfineon XC82x Real Time Clock 15 7 1 Real Time Clock Registers RTC_RTCON Real Time Clock Control Register 95 Reset Value 02 RMAP 0 PAGE X 7 6 SFRTC CFRTC ESRTC ECRTC RTCCT RTM RTCC rwh rwh Field Bits Type Description RTCC 0 Real Time Clock Start Stop Control Stop real time clock Operation 1g Start real time clock Operation RTM 2 1 Real Time Clock Mode OX Mode 1 Periodic wake up mode with 75 KHz oscillator is selected 1Xg Mode 3 Timer mode with direct external clock via RTCCLK is selected Note Mode switching will caused the clock source to be switched at the same time RTCCT 3 rwh Real Time Clock Capture Event Trigger Og No action 1g Capture event is triggered imm
640. uspended 1 Timer 13 in Capture Compare Unit will be suspended In addition the T13 PWM outputs are set to the inactive level and capture inputs are disabled when suspended T2SUSP Timer2 Debug Suspend Bit 0 Timer2 will not be suspended 1 Timer2 will be suspended RTCSUSP Real time Clock Debug Suspend Bit 0 Real time clock will not be suspended 1 Real time clock will be suspended LTSSUSP LED and Touch sense Counters Debug Suspend Bit 0 LED and Touch sense Counters will not be suspended 1 LED and Touch sense Counters will be suspended 7 6 Reserved Returns 0 if read should be written with 0 10 2 5 JTAG ID The JTAG ID for the XC82x devices is given in Table 10 4 Table 10 4 JTAG ID Number Device Type Device Name JTAG ID Flash XC82x 101BC083 User s Manual 10 4 V1 0 2010 02 OCDS V 2 7 1 Cinfineon Debug System 10 3 Functional Overview of the Debug System XC800 debug operation is based on close interaction between the OCDS hardware and the Monitor program in ROM These operations are elaborated in the following 10 3 1 Recognizing Debug events The OCDS hardware takes care to startup properly the Monitor in case some Debug event happens The debug events breakpoints supported are described in following Hardware Breakpoints Up to 4 hardware breakpoints can be set causing a break in case of code is fetched from a define
641. ust be programmed before accessing the PMCON1 register PMCON1 Peripheral Management Control Register 1 EF Reset Value DF RMAP 0 PAGE 1 7 6 5 4 3 2 1 0 DIS LTS DIS 0 MDU DIS T2 DIS CCU DIS SSC DIS ADC DIS rw rw r rw rw rw rw rw Field Bits Description ADC_DIS 0 rw ADC Disable Request Active high 0 ADC is in normal operation 1 Request to disable the ADC default 0 5 r Reserved Returns 0 if read should be written with 0 User s Manual 21 3 V1 0 2010 02 ADC V2 1 Cinfineon Analog to Digital Converter 21 1 3 Interrupt Events and Assignment Table 21 2 lists the interrupt event sources from the ADC and the corresponding event interrupt enable bit and flag bit Table 21 2 ADC Interrupt Events Event Event Interrupt Enable Bit Event Flag Bit Service Request Output Request Source ADC_QORO ENSI ADC_EVINFR EVINFx SRO Event Interrupts ADC QBURO ENSI Channel Event ADC_GLOBCTR CLCIEN ADC_CHINFR CHINFx SRO Interrupts Result Event ADC_RCRx x 0 3 ADC EVINFR EVINFx SRO Interrupts Out of Range ADC GLOBCTR ORCIEN ADC_LORC LOREx SR1 Comparator Event Interrupts Table 21 3 shows the interrupt node assignment for each ADC interrupt source Table 24 3 ADC Events Interrupt Node Control Event Interrupt Node Interrupt Node Flag Vector Enable Bit Bit Address SRO
642. ut COUT63 is in the passive state 1g output COUT63 is enabled for the PWM signal generated by T13 0 6 r reserved returns 0 if read should be written with 0 User s Manual 20 99 V1 0 2010 02 CCU6 V4 0 Cinfineon Capture Compare Unit 6 CCU6 20 8 2 Trap Control Register The register TRPCTRL H controls the trap functionality It contains independent enable bits for each output signal and control bits to select the behavior in case of a trap condition The trap condition is a low level on the CTRAP input pin that is monitored inverted level by bit ISH TRPF While TRPF 1 trap input active the trap state bit IS TRPS is set to 1 TRPCTRL Trap Control Register Low Reset Value 00 RMAP 0 PAGE 2 7 6 5 4 3 2 1 0 0 TRPM2 TRPM1 TRPMO r rw rw rw Field Bits Type Description TRPM1 1 rw Trap Mode Control Bits 1 0 TRPMO 0 These two bits define the behavior of the selected outputs when leaving the trap state after the trap condition has become inactive again A synchronization to the timer driving the PWM pattern avoids unintended pulses when leaving the trap state The combination TRPM1 leads to 00 The trap state is left return to normal operation after has become 0 again when a zero match of T12 while counting up is detected synchronization to T12 01 The trap state is left return to normal operation a
643. ved START 4 rwh Start Bit The bit START is set by software and reset by hardware Og Operation is not started 1g Operation is started RSEL 5 rw Read Select Read the MRx registers 1g Read the MDx registers User s Manual 12 12 V1 0 2010 02 MDU V2 9 Cinfineon XC82x Multiplication Division Unit Field Bits Type Description IR 6 rw Interrupt Routing Og two interrupt sources have their own dedicated interrupt lines 1g two interrupt sources share one interrupt line INT OO IE 7 rw Interrupt Enable Og interrupt is disabled 1g interrupt is enabled Note Write access to MDUCON is not allowed when the busy flag MDUSTAT BSY is set during the calculation phase Note Writing reserved opcode values to MDUCON results in an error condition when MDUCON START bit is set to 1 User s Manual MDU V2 9 12 13 V1 0 2010 02 Cinfineon Multiplication Division Unit 12 5 3 Status Register Register MDUSTAT contains the status flags of the MDU MDU_MDUSTAT MDU Status Register BO Reset Value 00 RMAP 0 PAGE X 7 6 5 4 3 2 1 0 0 BSY IERR IRDY r rh rwh rwh Field Bits Type Description IRDY 0 rwh Interrupt on Result Ready The bit IRDY is set by hardware and reset by software Og No interrupt is triggered at the end of a successful operation 1g An interrupt is triggered at the end of a s
644. verflow of the Watchdog Timer is programmable by the reload value WDTREL It is the high byte of WDT and can be programmed in register WDTREL The period Pwpr between servicing the WDT and the next overflow be determined by the following formula 16 8 2 6 WDTREL x 28 8 1 Pwpr Secik If the Window Boundary Refresh feature of the WDT is enabled the period between servicing the WDT and the next overflow is shortened if WDTWINB is greater than WDTREL See also Figure 8 2 This period can be calculated by the same formula by replacing WDTREL with WDTWINB In order for this feature to be useful WDTWINB cannot be smaller than WDTREL Count WDTWINB WDTREL L time Refresh allowed l 1 1 1 1 1 1 1 1 l l No refresh allowed Figure 8 2 WDT Timing Diagram Table 8 2 lists the possible ranges for the watchdog time which can be achieved using a certain module clock Some numbers are rounded to 3 significant digits User s Manual 8 5 V1 0 2010 02 WDT V1 0 Cinfineon XC82x Watchdog Timer Table 8 2 Watchdog Time Ranges Reload Value in WDTREL 75 KHz Input frequency FF 3 4 ms TF 440 ms 00 874 ms Note For safety reasons the user is advised to rewrite WDTCON each time before the WDT is serviced Note The Watchdog Timer can be suspended when OCDS enters Monitor Mode and has the Debug Suspend si
645. w rw Field Bits Type Description ETO 1 rw Timer 0 Overflow Interrupt Enable Og 0 interrupt is disabled 1g Timer 0 interrupt is enabled ET1 3 rw Timer 1 Overflow Interrupt Enable Og Timer 1 interrupt is disabled 1g 1 interrupt is enabled Note When Timer operates in Mode 3 this interrupt indicates an overflow in the Timer 0 register THO User s Manual Timer 0 and 1 V1 0 13 13 V1 0 2010 02 Cinfineon XBox Timer 2 14 Timer 2 14 1 Overview Timer 2 is a 16 bit general purpose timer which is functionally compatible with the Timer 2 in the C501 product family Timer 2 can function as a timer or counter in each of its modes As a timer it counts with an input clock of PCLK 12 if prescaler is disabled As a counter Timer 2 counts 1 to O transitions on pin T2 In the counter mode the maximum resolution for the count is PCLK 24 if prescaler is disabled Features 16 bit auto reload mode selectable up or down counting Onechannel 16 bit capture mode 14 2 System Information This section provides system information relevant to the Timer 2 14 2 1 Pinning Timer 2 can be used as an event counter which count 1 to 0 transitions at the external input pin T2 These pins are selected from four different sources T2 0 T2 1 T2 2and T2 3 This selection is performed by the SFR bits MODPISEL2 T2IS In addition there are eight sources of T2EX pin for Timer2 They can be selec
646. ware Run Input SCK 1 SSC Clock Input Output T1 1 Timer 1 Input EXINT2 External Interrupt Input 2 AN2 Analog Input 2 Out of range comparator channel 2 P2 3 4 3 Hi Z CCPOSO 2 CCU6 Hall Input 0 CTRAP 2 CCU6 Trap Input T2_2 Timer 2 Input EXINT3 External Interrupt Input 3 AN3 Analog Input 3 Out of range comparator channel 3 Vbpp 12 9 Port Supply 2 5 V 5 5 V 14 11 Core Supply Output 2 5 V Vssp 13 10 I O Port Ground Vasc Core Supply Ground User s Manual System Architecture V1 0 V1 0 2010 02 Cinfineon near Introduction 1 4 Chip Identification Number Each device variant of XC82x is assigned an unique chip identification number to allow easy identification of one device variant from the others The differentiation is based on the product variant type and device step information Two methods are provided to read a device variant s chip identification number In application subroutine see Chapter 22 2 Boot loader BSL mode A see Chapter 6 2 2 8 User s Manual 1 12 V1 0 2010 02 System Architecture V1 0 Cinfineon 1 5 Introduction Text Conventions This document uses the following text conventions for named components of the XC82x Functional units of the XC82x are shown in upper case For example The SSC can be used to communicate with shift registers Pins using negative logic are indicated by an overbar For example A reset input pin RESET
647. wer Management see Section 7 4 on Page 7 16 The XC82x provides a range of utility features for secure system performance under critical conditions e g brownout At the center of the XC82x clock system is the Clock Control Unit CCU which generates a master clock frequency using the 48 MHz oscillator In phase synchronized clock signals are derived from the master clock and distributed throughout the system 7 1 Power Supply System with Embedded Voltage Regulator The power supply to the core memories and the peripherals is regulated by the Embedded Voltage Regulator EVR that comes with detection circuitries to ensure that the supplied voltages are within the specified operating range The main voltage and low power voltage regulators in the EVR may be independently switched off to reduce power consumption for the different power saving modes The XC82x microcontroller requires two different levels of power supply e 2 5Vto5 5V for the Embedded Voltage Regulator EVR and Ports e 2 5 V for the core memory on chip oscillator and peripherals Figure 7 1 shows the XC82x power supply system A power supply of 2 5 V to 5 5 V must be provided from the external power supply pin The 2 5 V power supply for the logic is generated by the EVR The EVR helps reduce the power consumption of the whole chip and the complexity of the application board design User s Manual 7 1 V1 0 2010 02 Cinfineon System Control Unit CPU amp
648. will only come from SDA O 17 2 1 1 Output Pin Configuration The pin drivers that are assigned to the IIC lines provide open drain outputs This ensures that the IIC does not put any load on the IIC bus lines while the IIC is not powered Therefore it is necessary to have external pull up resistors approximately 10 for operation at 100 KBaud 2 for operation at 400 KBaud on the IIC bus lines All pins of the IIC that are to be used for IIC bus communication must be switched to output and their alternate function must be enabled before any communication can be established If not driven by the IIC module the pins will switch off their drivers i e driving 1 to an open drain output Due to the external pull up devices the respective bus levels will then be 1 which is idle 17 2 2 Clocking Configuration The IIC runs on the PCLK at a frequency of either 8 MHz or 24 MHz If the IIC functionality is not required at all it can be completely disabled by gating off its clock input for maximal power reduction This is done by setting bit IIC_DIS in register 1 as described below The bit field PAGE of SCU_PAGE register must be programmed before accessing the PMCON register PMCON1 Peripheral Management Control Register 1 EF Reset Value DF RMAP 0 PAGE 1 7 6 5 4 3 2 1 0 DIS LTS DIS 0 MDU DIS T2 DIS CCU DIS SSC DIS ADC DIS rw rw r rw rw rw rw rw User s Manual 17 2 V1
649. within Interrupt Level Source Level Non maskable Interrupt NMI highest External Interrupt 0 1 Timer 0 2 User s Manual Interrupt System V 2 3 3 9 9 V1 0 2010 02 Cinfineon Interrupt System Table 9 2 Priority Structure within Interrupt Level cont d Source Level External Interrupt 1 3 Timer 1 4 UART 5 Timer 2 LIN 6 A D Converter and ORC 7 SSC 8 External Interrupt 2 MDU IIC 9 EXINT 6 3 RTC 10 CCU6 Interrupt Node Pointer 0 11 CCU6 Interrupt Node Pointer 1 LED and Touch sense 12 CCU6 Interrupt Node Pointer 2 13 CCU6 Interrupt Node Pointer 3 LED and Touch sense 14 9 2 Interrupt Structure An interrupt event source may be generated from the on chip peripherals or from external Detection of interrupt events is controlled by the respective on chip peripherals Interrupt status flags are available for determining which interrupt event has occurred especially useful for an interrupt node which is shared by several event sources Each interrupt node except NMI has a global enable disable bit In most cases additional enable bits are provided for enabling disabling particular interrupt events provided for NMI events No interrupt will be requested for any occurred event that has its interrupt enable bit disabled The XC82x has in general two interrupt structures distinguished mainly by the manner in which the pending interrupt request one per inte
650. wo true 16 bit operations are allowed on the Data Pointer load immediate MOV DPTR data and increment INC DPTR 2 3 3 Accumulator ACC E0 This register provides one of the operands for most ALU operations ACC is the symbol for the accumulator register The mnemonics for accumulator specific instructions however refer to the accumulator simply as 2 3 4 B Register 0 The B register is used during multiply and divide operations to provide the second operand For other instructions it can be treated as another scratch pad register 2 3 5 Program Status Word PSW The PSW contains several status bits that reflect the current state of the core User s Manual 2 3 V1 0 2010 02 XC800 Core V 1 0 2 T6 XC82x Infineon XC800 Core PSW Program Status Word Register D0 Reset Value 00 RMAP X PAGE X 7 6 5 4 3 2 1 0 CY AC F0 RS1 RSO Ov F1 P rwh rwh rw rw rw rwh rw rh Field Bits Description P 0 rh Parity Flag Set cleared by hardware after each instruction to indicate an odd even number of one bits in the accumulator i e even parity F1 1 rw General Purpose Flag OV 2 rwh Overflow Flag Used by arithmetic instructions RSO 3 rw Register Bank Select RS1 4 These bits are used to select one of the four register banks 00 Bank 0 selected data address 00 07 01 Bank 1 selected data address 08 10 Bank 2 selected data addres
651. x Analog to Digital Converter Field Bits Type Description ENTR Enable External Trigger This bit enables the external trigger possibility If enabled the load event takes place if a rising edge is detected at the external trigger input REQTR Og external trigger is disabled 1g external trigger is disabled ENSI Enable Source Interrupt This bit enables the request source interrupt This interrupt can be generated when the last pending conversion is completed for this source while PND 0 source interrupt is disabled 1g The source interrupt is enabled SCAN Autoscan Enable This bit enables the autoscan functionality If enabled the load event is automatically generated when a conversion requested by this source is completed and PND 0 Og autoscan functionality is disabled 1g autoscan functionality is enabled CLRPND Clear Pending Bits Og No action 1g The bits in register CRPR1 are reset LDEV Generate Load Event Og No action 1g load event is generated 7 1 0 Reserved Returns 0 if read should be written with 0 User s Manual V2 1 21 22 V1 0 2010 02 Cinfineon Analog to Digital Converter The Conversion Request 1 Control Register selects the channels to be converted by request source 1 channel scan source Its bits are used to update the pending register CRPR1 when t
652. x1800 angle old 0x0800 result PT1 24 angle new angle old 5 amp speed xesult OxF9AC 23 1 4 1 32 Controller Routine The PT1 32 controller routine is an integrator defined as 23 4 Y k Y k 1 Zl x X k Z2 x Y k 1 where Y k PT1 24 controller output Y k 1 Previous PT1 24 controller output e 7 Division factor of 1 22 X k 16 bit input k Time or instantaneous time Table 23 5 Specifications of PT1 32 Controller Routine Subroutine _PT1_32 Routine Address 0xD78A PT1 32 C Prototype int PT1_32 int X int Z2 int idata pY Input R7 R6 MSB 16 bit X value R5 R4 MSB 16bit Z2 value R3 idata pointer to Y k 1 H MDU MD4 Z1 L MDU MD5 Z1 H Remark Y k 1 32 bits HL hl Z1must be within 0x0000 to Ox3FFF or X must be within OxCO00 to Ox3FFF Output R7 R6 MSB 16 bit Y k value Execution Cycle 118 cclk User s Manual 23 7 V1 0 2010 02 ROM Library V0 5 Cinfineon ROM Library Table 23 5 Specifications of PT1 32 Controller Routine cont d Resource PSW A MDU used destroyed Ro of current Register Bank Code Example global variables data int result data int Integrator 2 program Integrator 0 OxFF12 Integrator 1 0xE828 MD4 Ox1F Low byte Z1 MDU MD5 0x00 High byte Z1 result PT1 32 X 0x109 amp Integrator result OxFF15 23 1 5 Clarke Transform Routine This routine is used for the transformation of a thre
653. xFC00 I beta 0 102 User s Manual 23 9 V1 0 2010 02 ROM Library V0 5 Cinfineon ROM Library 23 2 LED and Touch Sense Controller ROM Library The LEDTS ROM Library contains two routines that recite in ROM that are accessible to users The definitions and specifications of the library routines are organized into the following major sections SET LDLINE CMP Function LED and TS FINDTOUCHEDPAD Function TS Use of the functions in Interrupts The call functions for LEDTS are listed in Table 23 7 Table 23 7 LEDTS ROM Library Routine Table Address Name Description OxDFCF SET LDLINE CMP Program SFRs LTS LDLINE and LTS COMPARE LED enabled only OxDFCF SET LDLINE CMP Program SFRs LTS LDLINE and LTS COMPARE TS enabled only OxDFCF SET LDLINE CMP Program SFRs LTS LDLINE and LTS COMPARE LED and TS are enabled OxDFCC FINDTOUCHEDPAD Get Average calculate LowTrip and assess whether pad s is being touched or not These routines are called from Time Slice or Time Frame Interrupts This is illustrated in Section 23 2 3 User s Manual 23 10 V1 0 2010 02 ROM Library V0 5 Cinfineon ROM Library 23 2 1 SET_LDLINE_CMP Function LED and TS This function programs sfrs LTS_LDLINE and LTS_COMPARE brightness oscillation window for LED and or Touch sense based on the users input parameters The function takes sfr bit FNCOL value direct from the sfr 75 GLOBCTL1 to s
654. xST Register CCGxR CCExSR CC6x_R Ccex F To Interrupt Logic EEG CCU6 05522 Figure 20 19 Capture Mode 1 Block Diagram User s Manual 20 37 V1 0 2010 02 CCU6 V4 0 Cinfineon Capture Compare Unit 6 CCU6 Capture Modes 2 3 and 4 are shown in Figure 20 20 They differ only in the active edge causing the capture operation In each of the three modes when the selected edge is detected at the corresponding input signal CC6xIN the current contents of the shadow register CC6xSR are transferred into register CC6xR and the current Timer T12 contents are captured in register CC6xSR simultaneous transfer The active edge is a rising edge of CC6xIN for Capture Mode 2 a falling edge for Mode 3 and both a rising or a falling edge for Capture Mode 4 as shown in Table 20 8 These capture modes are very useful in cases where there is little time between two consecutive edges of the input signal fs Counter Register CC6xIN Shadow Register CC6xSR Mode Selection State Bit CC6xST E Register CC6xR CC6x_R gt CC x F Interrupt Logic gt CCU6_MCB05523 Figure 20 20 Capture Modes 2 3 and 4 Block Diagram User s Manual 20 38 V1 0 2010 02 CCU6 V4 0 Cinfineon Capture Compare Unit 6 CCU6 Five further capture modes are called Multi Input Capture Modes as they use two different external inputs sign
655. xample in C that use the EEPROM emulation API The example shows how to initialise the flash area for use and some error handling mechanism include EEPROM h void main void EEPROM emulation required data structure char idata buffer 32 EEPROMInfo config unsigned char eeprom_status nitialised and check emulated EEPROM integrity eeprom_status InitEEPROM MODE_3 amp config if 0 eeprom status 0x0 config ActiveSector Erase abort detected or first time using EEPROM Initialise invalid sectors FixEEPROM eeprom status buffer Jelse Programming or erasing aborted suddenly during reclaiming operation Depending on user application additional action can be taken l Initialise invalid sectors Data would be erased FixEEPROM eeprom status buffer User s Manual 23 50 V1 0 2010 02 ROM Library V0 5 Cinfineon XC82x ROM Library Check that EEPROM sectors are in valid condition eeprom_status InitEEPROM MODE_3 amp config if 0 eeprom_status Fatal failure in EEPROM while 1 User application code Example of reading and writing to emulated Get current data ReadEEPROM WL 1 amp buffer amp config Update data to store and write to EEPROM buffer 20 1 Write back updated data WriteEEPROM WL 1 amp buffer amp config while 1 Wait for power off User s Manual 23 51 ROM Lib
656. xtended Operation EO register is also set to 1 Upon fetching a TRAP instruction a breakpoint is generated and the relevant Break Action is taken The software breakpoints are in fact similar in behavior to the equal breakpoints on Instruction address except that they are raised by a program code instead of specialized compare logic An unlimited number of software breakpoints can be set by replacing the original instruction codes into the user program Of course this is possible only at addresses where RAM Flash is implemented External Breaks External breaks could be Requested via the debug interface by OCDS command An external Debugger can activate the Monitor and interrupt a user program running on the target XC800 10 3 2 Activating the Monitor Program Once a Debug event is identified and the OCDS registers are properly programmed the Monitor program in ROM is started as a primary reaction The OCDS hardware ensures that the Monitor is always safely started and fully independent of the current system status at the moment when the debug action is taken Also interrupt requests optionally raised during Monitor entry will not disturb the Monitor firmware functioning Once started the Monitor runs with its own stack and data memory which guarantees that all of the core and memory resources will be found untouched when returning control back to the user program Therefore the OCDS debugging is fully non destructiv
657. y Organization Table 3 11 IIC Register Overview cont d Addr Register Name Bit 7 6 5 4 3 2 1 0 DDH IIC_BRCR Reset 004 Bit Field 0 PREDIV Baud Rate Control Register Type w w w DEH IIC_ADDRX Reset 004 Bit Field SLAX Extended Slave Address Register Type Iw SRST Reset UU Bit Field SRST Software Reset Register Type w 3 4 5 12 OCDS Registers The OCDS SFRs can be accessed in the mapped memory area RMAP 1 Table 3 12 OCDS Register Overview Addr Register Name Bit 7 6 5 4 3 2 1 0 IRMAP 1 E94 MMCR2 Reset 10 Bit Field STMO 0 DSUS MBCO ALTDI MMEP MMOD JENA Monitor Mode Control 2 DE P N Register Type TW rw rw rwh rw rwh rh rh MMCR Reset 004 Bit Field MEXIT MEXIT MSTE MRAM MRAM TRF RRF Monitor Mode Control Register de IE SP S Type w rwh rw rw w rwh rh rh F2y MMSR Reset 004 Bit Field 0 EXBF SWBF HWB3 HWB2 HWB1 HWBO Monitor Mode Status Register F TW rwh rwh rwh rwh rwh rwh F3H MMBPCR Reset 004 Bit Field SWBC HWB3C HWB2C HWB1 HWBOC Breakpoints Control Register TW rw TW rw TW MMICR Reset 004 Bit Field DVEC DRET COMR MSTS FMIR NMIR Monitor Mode Interrupt Control T R ST EL Ww R WE RE Regis
658. y by PSL63 is output If it is in the active state the inverted level of PSL63 is output This allows the user to adapt the polarity of an active output signal to the connected circuitry The PSL63 bit has a shadow register to allow for updates with the T13 shadow transfer signal T13_ST without undesired pulses on the output lines A read action returns the actually used value whereas a write action targets the shadow bit Providing a shadow register for the PSL value as well as for other values related to the generation of the PWM signal facilitates a concurrent update by software for all relevant parameters Trap Handling TRPS Block Output active Level a COUT63 O pon Selection hd T13 Block Cotes ECT130 CCU6_MCA05545 Figure 20 31 T13 Output Modulation 20 4 5 113 Shadow Register Transfer A special shadow transfer signal T13_ST can be generated to facilitate updating the period and compare values of the compare channel CC63 synchronously to the operation of T13 Providing a shadow register for values defining one PWM period facilitates a concurrent update by software for all relevant parameters The next PWM period can run with a new set of parameters The generation of this signal is requested by software via bit TCTROH STE13 set by writing 1 to the write only bit TCTR4H T13STR cleared by writing 1 to the write only bit TCTR4H T13STD When signal T13_ST is active a shadow register transfer is
659. yn 2 0x97 Speed control kp 4096 Speed control ki 32 User s Manual ROM Library V0 5 23 5 V1 0 2010 02 Cinfineon XC82x Speed control PI SAT HH 0 1 PI Speed PI controller Gl6 Speed ref Speed amp Sp PI Speed 0x108E 23 1 3 PT1 24 Controller Routine The PT1 24 controller routine is a digital lowpass filter defined as ROM Library d control 23 3 Y k Y k D 272 x X k Y k 1 where Y k PT1 24 controller output Y k 1 Previous PT1 24 controller output e 7 Division factor of 1 22 X k 16 bit input k Time or instantaneous time Table 23 4 Specifications of PT1 24 Controller Routine Subroutine _PT1_24 Routine Address 0 075 PT1 24 C Prototype int PT1_24 int X char Z char idata pY Input R7 R6 MSB 16 bit X value R5 8 bit Z value number of right shifts 1 27 R3 idata pointer to Y k 1 _H Remark Y k 1 24 bits HLh X must be within 0 000 to Ox3FFF Output R7 R6 MSB 16 bit Y k value Execution Cycle 76 cclk Resource PSW A MDU used destroyed of current Register Bank Code Example declare variables data char Speed 3 data int result data int angle new User s Manual 23 6 V1 0 2010 02 ROM Library V0 5 Cinfineon ROM Library data int angle old program 0 OxF8 Speed 1 OxF3 Speed 2 OxCB angle new 0
660. ynchronize which data is to be programmed into the sfr LTS LDLINE for implementing an LED display Likewise the function also updates the sfr LTS COMPARE for individual LED or Touch sense PADTurn number Figure 23 1 gives an overview of the usage of this function while Figure 23 2 shows the respective SFR settings used for this function call ROMLIB 101 T T ROM Library LEDLINE 7 LEDLINEI6 LEDLINE 5 LEDLINE 4 LEDLINE 3 LEDLINE 2 T T T T Pep o 1 T LEDLINE lI LEDLINE 0 LEDCMP 0 Sh d S 90 5 rw CK Figure 23 1 SET LDLINE CMP Function Overview This function can be called at every Time Slice or Time Frame interrupt depending on whether Touch sense or and LED is are enabled Details of how this functions can be called are shown in Section 23 2 3 The inputs are shown in Section 23 2 1 1 Section 23 2 1 2 and Section 23 2 1 3 for LED enabled only TS enabled only and both LED and TS enabled respectively 1 For Touch sense LTS LDLINE parameter can be written as OxFF User s Manual 23 11 V1 0 2010 02 ROM Library V0 5 82 ROM Library Infineon em 0 WATT 0

8-Bit XC82x

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