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User Manual DN-DualV6-PCIe-4

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1. 111 8 2 1 External Power 112 8 3 Voltage Monitors and Reset 113 8 3 1 Voltage Monitor 113 8 3 2 Voltage Monitor Circuit 8 3 3 Power Sequencing ito REC ERE EVE RH RUBRO 8 3 4 ReS tOptiOns IM 9 DAUGHTER CARD HEADER 9 1 Daughter Gard EORR RR OO ER OE ERE REESE 9 2 Daughter Card Header Pin Assignments ceo n en ERE EGET EE ELE ERE HEADER 115 9 3 Special Pins on the Daughter Card Header 9 3 1 CEK DN 2 5p n and UP 25 p ett ERE 117 9 3 2 Power Supply 9 4 Power and sss 9 5 FPGA to Daughter Card Header IO Connections 9 6 Insertion Removal of Daughter Card 124 9 7 MEG Array Specifications ie tp eO ERE ENSE UR ERE RT D ee 126 10 litre ue PEAT AI 10 1 Board Dimensions 10 2 Standard Daughter Card Size itasse EEA 126 10 3 Daughter Card Spacing eosti ep uie pelle e e e a desea ERO ER HD 128 APPENDIX 130 11 APPENDIX A 130 12 ORDERING INFORMATION
2. Figure 29 GTP Clock Oscillator and Buffer 4 5 2 Connection between GTP Clock Buffers and the FPGAs The connections between the GTP Clock Buffers and the FPGAs ate shown in Table 34 These signals are routed as differential pairs LVDS and are AC coupled Table 34 Connection between GTP Clock Buffers and FPGAs Signal Name Clock Buffer FPGA A B CFV6 23 16 17 AF4 CLK_GTP_CFV6_0N 23 15 17 AF3 CLK_GTP_CFV6_1P 23 14 17 AL5 CLK_GTP_CFV6_1N 23 13 17 AL4 CLK_GTP_CFV6_2P 23 12 22 H6 CLK_GTP_CFV6_2N 23 11 22 H5 24 AK6 24 AK5 CLK_GTP_CFV6_3P 23 10 CLK_GTP_CFV6_3N 23 9 Signal Name Clock Buffer CPU CF FPGA GTX AB 59 16 AB 59 15 AB 1P 59 14 GTX AB 1 59 13 C LC PCS The oscillator power supply 060 15 filtered to reduce power supply noise and jitter Please see the 51534 datasheet for more information 4 5 3 GTP Clock Oscillator FPGA A and FPGA B The 5854104 059 is a low skew high performance 1 to 4 Differential to LVDS Clock Fanout Buffer that is driven by the 51534 Quad Frequency Crystal Oscillator X11 see Figure 30 DN DualV6 PCle 4 User Manual www dinigroup com 97 HARDWARE DESCRIPTION P2 5VF OSC CFVG
3. 38 TSP Ethernet sorei M 39 PECES VIT P 40 1 9 UART RS232 Interface 41 1 10 Real Time Clock 41 1 11 Temperature Monitor 41 1 12 JTAG Boundary Scan STAG Interfaces vest tonic e SR TTE D e doo eade 42 CONFIGURATION HPGrA VIRTEX25 PIERDE EEUU EYE n 43 2 1 Overview 4 22 lt 5 of FPGA Features eet a CRM FORERO ERAI 44 2 3 FPGA Configuration euin ee rU ner DE e P EGER TOR EET ODHEG EUM RE E 2 3 1 Configuration FPGA M 2 0 Select Resistors 2 32 SelectMAP via Maryel CPU 2 3 3 SPP Serial IECUR 2 3 4 JTAG 2 4 Interconnect Configuration FPGA to FPGA 2 4 1 Not Bus NMB T 2 4 2 Past B s Optional R 2 4 3 High Speed Interconnect 4 60 FPGA VIRTEX 6 3 1 ONTA AT A EE A E E 32 xSu mmaryof Virtex 6 F eatut eserin t p E a eL o d ANTENA 62 3 3 FPGA Configuration Virtex 6 3 3 1 FPGA M 2 0 Select Resistors 3 3 2 SelectMAP via Configuration
4. 17 4 2 Powerit Up the Board CUMBRE EROR LO ERE AG 18 4 3 Configuring the FPGA a 5 UPDATING THE MARVELL MV78200 5 19 5 1 Setup Updating the Marvell MV78200 Software 19 5 2 Powering Up the Board ss 5 3 Open Serial Terminal Session x ice eet eee eee 20 5 4 Verify Linux Kernel UP m 20 5 5 Update the Linux Kernel 5221 2 65 dnstalling the Root FileSystem RES Update eitis iieri e PI He RE EE ER AREE CEU UTR Feed Een 23 HARDWARE e d UO 24 1 DESCRIPTION DD 24 1 1 Overview 1 79200 26 14 Overview eese 26 1 2 Reset Strapping Options 27 1 3 Boot 32 1 3 1 Booting from SPL Flashi asiaa aaro rna ANEETA NEIRO A 33 1 3 2 Booting NANDXEl ash eiecti aee oe o e eee este io tee e e e e ius 34 1 4 CPU Memory DDR2 1 5 PCI Express Interface 1 5 1 PCLEXpreSs UD e RUP EL o EU OH 37 1 5 2 PCI Express Port 1 2 37 1 5 3 CLOCKING n dues tret a e ne 38 1 6 IBI Dn I
5. R476 475R PEXIREF 10 nen 15 PEX CLK pn VDDODA T T 16 74 C70 9 GNDODA 1 0 01uF 100 BLM18AG102SN1D 100 50V 6 3V 400mA BS ICS557 05A TSSOP20 1095 209 2096 ICS557G 05ALF CER CER CER 68 6 3v Figure 28 PCI Express Reference Clock Circuit 4 4 2 Connection between CPU CF FPGA and the PCle Reference Clock Buffer The connection between the Marvell MV78200 Configuration FPGA and the PCIe Reference Clock Buffer U13 are shown in Table 32 These signals are routed as differential pairs LVDS and are AC coupled Table 32 Connection between CPU Configuration FPGA and PCI Express Reference Clock Buffer Signal Name PCI Express Edge Connector PEXO P1 A13 4 W1 PEXO P1 A14 4 Y1 Signal Name Clock Buffer CPU CF FPGA PEXA U13 20 4 1 n U13 19 4 AB1 CFPGA U13 18 17 H4 PEXB CFPGA n 013 17 17 H3 4 5 GTP Clock LVDS Oscillators and Buffers x4 The differential oscillators X9 X11 X10 and X12 is powered from 2 5V and provides a differential reference clock to the GTP Transceivers see Figure 29 The GTP Clock Oscillators are assigned as follows X9 High speed SERDES links between Configuration FPGA and FPGA A B DN DualV6 PCle 4 User Manual www dinigroup com 95 HARDWARE DESCRIPTION e X1
6. e GND 5 4 SA x gt 9 67800 5005 67800 5005 0 1uF 1 TxP c 3 C488 c T SATAT RxP gt un 67800 5005 67800 5005 Figure 10 SATA Interface The two SATA II ports connects directly to the Marvell MV78200 see Table 8 8 SATA II CPU Interconnect Signal Name 5 0 TXP SA0 5 0 RXP 5 0 RXN 5 1 TXP SA1 TXN 5 1 RXP 5 1 RXN DN DualV6 PCle 4 User Manual www dinigroup com 40 HARDWARE DESCRIPTION 1 9 UART RS232 Interface See RS232 Pott section in this user manual 1 10 Real Time Clock The DS1338 036 serial real time clock RTC is low power full binary coded decimal BCD clock calendar plus 56 bytes of NV SRAM Address and data are transferred serially through an interface The clock calendar provides seconds minutes hours day date month and year information The RTC is connected to the Two Wire Serial Interface TWSI port 1 see Figure 11 and mapped to address 0x68h P1 8VD Y2 FC 135 32 7680KA A3 R11 32 768 2 4 7 U36 RTC_INTn R287 A oR MPP22 DS1338Z S08 2 2uF DS1338Z 33 6 3V Address 0110 1000 0x68 Figure 11 Real Time Clock RTC The TWSI master starts a transaction by driving a start condition followed by a 7 bit slave address and a read write bit i
7. sess 99 4 6 2 Connection between Daughter Card Header Global Clocks and FPGA 100 4 6 3 Source Synchronous Daughter Card DC Header 5 100 4 6 4 Connection between FPGAs and the Secondary DC Header 101 4 7 lt Not Main Bus Clock NMB 103 4 7 1 Bus NMB Clock 103 4 8 External Clock Test Pointers enire in aA 103 4 8 1 Multiplexed Global Clock Circuit see 103 4 8 2 Connection between External Clock Header and the Clock Multiplexer 104 5 R 232 PORT ctt tte e eh Petre ee rere toe 5 1 1 RS232 Circuit Diagram 5 1 2 Connections between RS232 Port and the Configuration 105 6 TEMPERATURE SENSORS 6 1 1 T mperat te Sensor 1 ec err e e pea e iD E FCU DECRE OSEE TCU BO EX C D Y E GT 106 6 1 2 Connection between FPGA and Temperature 5 5 5 107 7 LED INDICATORS ZA FPGA Status EEDs e IRR RERO EROS EMANUELE DURER Edere 107 7 2 Configuration DONE 00 cm DD 108 7 3 Ethernet 109 7 4 Power Supply Status LEDs 109 7 5 USB Fault LED 46 Miscellaneous secet ine I RU 110 8 POWER DISTRIBUTION eI 110 8 1 In System Operation 111 9 25 e Stand Alne Operat On asns
8. 8133 muss n me UPS URS rs Hrs Nac See ux om cnm 1883 Osc ak CON UIS m GU Gm erven 607 EN crus LOREEN Lorum HELL gp HI EESESRER eo om B e PR5vF 080 paso Gin T i CiK GTP OTP 2p pri L Our Rus Rees aa 47K CIKBUF CFV6 ENO 1 opo CVE ar 2 534FB000184DG 16 63V R670 7 A 1 2 ad 2n 10 20 R669 4 7K ENZ 10 GTP CFV6 3p Tum m zi SE 8 ap UR 2m E REG 092 op P EHS BYE SE om ene sp rar zi 2 4 1 Burr 814 CSSSTTDVTSSOPTS cue 5 n 509 sumeacioaswio sa 7 oom TN 250 00MHz 20 FS 11 312 50MHz CER CER Figure 30 GTP Clock Oscillator and Buffer 4 54 Connection between GTP Clock Buffer and FPGA The connections between the GTP Clock Buffers and FPGA A B are shown in Table 35 These signals are routed as differential pairs LVDS and are AC coupled Table 35 Connection between GTP Clock Buffers and FPGA A B Signal Name Clock Buffer FPGA A B GTX AB U59 16 U22 P6 U59
9. 11 XERT x P3 3VD 9 x R288 47K TEMP A0 C 10 NC R316 2 7 6 ADDO NC 16 X ADD1 NC X P3 3VD 7 GND P3 3VF TEMP C jec ML R317 200R MAXIG17A QSOP16 2 2uF 1617 6 3V Address 0100 1100 0 40 Figure 12 CPU Temperature Sensor The connection between the Marvell MV78200 and the Temperature Sensor are shown in Table 9 Table 9 Connection between MV78200 and Temperature Sensor Signal Name Temp Sensor CPU TEMP P U37 3 CPU TEMP N U37 4 1 12 JTAG Boundary Scan JTAG Interface The Marvell MV78200 JTAG interface 1s used for chip boundary scan as well as for CPU cores debugger The two CPU core TAP controllers ate chained CPUO TDO is connected to CPU1 TDI CPU1 is driven pin Figure 13 shows 23 the JTAG connector used to debug the Marvell MV78200 P3 3VD P3 3VD o C118 C117 R637 lt R638 lt R636 lt gt R612 10uF 4 7K 47K 47K DNI 4 7K esv T 1 205 VSUPPLWTREF JT RSTn R628 A TMS CORE CER ONDI TESTS 1 JT TDI R634 OR JI TMS CPUO GND2 TET JT TMS R629 JI TMS GND3 TMS JT CLK VS GND4 T GND5 RTCK GND6 TD GND7 SRST SRSTn GND8 GND9 DBGACK JTAG 20Pin 10 88 1201 R626 DNI 0R R615 R608 4 7K DNI 4 7K Figure 13 CPU
10. ABNM On 02442 FPGA A 22 D20 22 D19 22 18 22 B22 22 A19 22 H22 224120 22 20 22 23 22 A23 22 F21 22 H19 22 F19 22 21 22 20 22 22 22 20 22 621 20 22 22 021 22 20 22 E19 22 B18 22 21 22 18 24 14 24 13 24 AL10 24 AL13 24 AK11 24 12 24 14 FPGA B e Bend Den ege e 24 22 24 21 24 AL20 24 AN22 24 AL18 24 AC20 24 AC19 24 AP19 24 AN19 24 AP22 24 AE21 24 AG20 24 AJ20 24 AF19 24 AF20 24 AK19 24 AP20 24 22 24 23 24 21 24 22 24 21 24 AM20 24 AM22 24 18 22 14 22 14 22 10 22 11 22 13 22 114 22 13 www dinigroup com 83 HARDWARE DESCRIPTION Signal Name AB2N15 AB2N16 AB2N17 AB2N18 AB2N2 AB2N3 AB2N4 AB2N5 AB2N6 AB2N7 AB2N8 AB2N9 AB2P0 AB2P1 AB2P10 AB2P11 AB2P12 AB2P13 AB2P14 AB2P15 AB2P16 AB2P17 AB2P18 AB2P2 AB2P3 AB2P4 AB2P5 AB2P6 AB2P7 AB2P8 AB2P9 AB3NO DN DualV6 PCle 4 User Manual FPGA A 24 14 24 AP12 24 10 24 AD11 24 AF14 24 AG13 24 AG10 24 12 24 11 24 12 24 12 24 11 24 14 24 13 24 10 24 13 24 AJ11 24 12 24 AD14 24 13 24 11 24 AJ10 24 AD12 24 14 24 13 24 11 24 AE13 24 AF11 24 12 24 12 24 AL11 22 F
11. IO SMGN 13 Hacs OMP IO 5 2 13 OAN IO L7N SM2N 13 OMP 10 SMIP 13 AES OAONTE 10 LEN CC SMIN 13 OMPI IG L9P CC SMOP 13 ag34 QAONT7 10 SMON 13 Hanss OOP 10 CC 13 10 L3N A12 D28 34 L4P A11 027 34 ps Onna 10 LAN VREF 026 34 a9 QGAOPS A09 D25 34 as GAONS 10 15 A08 D24 34 Eg GAOP3 L6P A07 D23 34 HE5 10 LEN A06 D22 34 Hga IO L7P A05 D21 34 10 L7N A04 D20 34 SRCC 34 34 Hio GADPT7 10 L9P MRCC 34 Mo ONTT 10 L9N 34 Hacio GADPiB 10 34 GAUNTE Bank 34 Bank 13 XC5VLX130T 195T 240T 365T M EB o 5 Uu E 10 LION CC 13 73535 AUPTE LION MRCC e un IO LHP SRCC omne ER 13 acas oaos En IO LIN SROC Anto GA0PE VRN 13 Onna o 112 A03 D19 34 Acs E 13 A34 i 1O L12N A02 D18 34
12. 1368398 2 RJ45 1368398 2 R280 4 7K Figure 9 10 100 1000 Ethernet RGMIT DN DualV6 PCle 4 User Manual www dinigroup com 131 12 NO E Bla P SU c 26 PT 4 mee 1 C1972 C204 C199 C205 T 25 MDIO NT 5 6 T O 1uF o tuF O iuF 0 1uF P24 gimis 18074 23 2 808 2 3 8 TRD3 g TRD4 gt mE TRD4 P 6 PO LedO 14 13 R243 49 9R PO 1 0 8 Ledi YEL Led2 ZA 15 R251 49 9R PO Ledi ORN Led2 i7 GC R252 49 9R PO SH1 MTH1 SH1 Ge0 TDI 8 m St 39 HARDWARE DESCRIPTION The 1368398 2 J3 is a Gigabit Ethernet single port jack 45 with integrated magnetics and LEDs see Figure 9 1 8 SATA Interface Serial ATA 1s a high speed serial link replacement for the parallel ATA attachment of mass storage devices The serial link employed is a high speed differential layer that utilizes gigabit technology and 8b 10b encoding The Marvell MV78200 includes two SATA II compliant ports The device employs the latest SATA II PHY technology with 3 0Gbps Gen2i and backwards compatible with 1 5 Gbps 11 SATA I see Figure 10 Both TX RX signal pairs are differentially routed and AC coupled with 0 1uF capacitors J11 1 E GND C585 0 1uF SATA0 TxP c o TX L3 0575
13. 93 LVDS unidirectional pairs clocks or 186 single ended 650 MHz on all signals with soutce synchronous LVDS Signal voltage set by daughter card 1 2V to 2 5V 12V 24W max and 3 3V 10W max Supplied power rails fused e User LEDs e Onboard Distributed Power Supplies e Full support for Embedded Logic Analyzers ChipScope Logic Analyzer e Shared RS232 Port 10 pin Header Stand Alone operation requires an external 12V ATX power supply with a PCIe power connector DN DualV6 PCle 4 User Manual www dinigroup com 4 INTRODUCTION 3 Package Contents Before using the kit or installing the software be sure to check the contents of the kit and inspect the board to verify that you received all of the items If any of these items are missing contact Dini Group before you proceed The DN DualV6 PCle 4 Logic Emulation Board kit includes the following USB Flash Drive 2GB USB 2 0 Cable RS232 DB9 F to IDC Header Cable 12 RS232 Serial Cable DB9 6ft F F Ethernet Cable RJ45 6ft P N CC5E B25B 6 Pin PSU Adaptor for PCI Express Video Cards PSU Enable Connector Daughter Card Mounting Hardware Screw Machine M3x5mm 4 o Nut HEX x4 O Spacer M3x14mm x4 Lithium Coin Battery CR1220 Customer Support Package USB Flash Drive o Host Software EMU o Virtex 6 Reference Designs Verilog o User Manual pdf format Schematic pdf format o Component Datasheets pdf format Op
14. PROGRAMMING CONFIGURING THE HARDWARE 1 Attach an ATX Power Supply to the PCIE PWR header J5 on the DN DUALV6 PCIE 4 Logic Emulation Board 2 Connect the Xilinx Platform Cable USB to the JTAG V6 header J13 4 2 Powering Up the Board 3 Power up the board by turning ON the ATX power supply and verify the 12V LED 0544 is ON indicating the presence of 12V located at the right side of the PCB 4 3 Configuring the FPGA To configure the Xilinx FPGA perform the following steps 1 Open iMPACT and create a new default project Select Configure devices using Boundary Scan TAG from the iMPACT welcome menu e Welcome to iMPACT Please select an action from the list below Configure devices using Boundary Scan JTAG Automatically connect to a cable and identify Boundary Scan chain v Prepare a PROM File Prepare a System ACE File Prepare a Boundary Scan File Configure devices using Slave Serial mode Cancel 2 iMPACT will identify FPGA and FPGA B XC6VSX475T depends on the build option in the JTAG chain A pop up window will display Device Programming Properties Device 1 Programming Properties Click to select default options 3 Right click on FPGA and select Assign New Configuration File Specify the location for the FPGA bit file based on the type of FPGA populated e g XC6VSX475T DN DualV6 PCle 4 User Manual www dinigroup
15. 2 A26 lt C47 0 iuF T n2 p3 GND mv PETp3 GND n3 A28 PAS Tp3 c C49 OjuF PEXO T p3 P3 A30 T nic Tn PEX_PRSNTn4 BSVD PERn3 7331 PRSNT2 GND 335 1 ND Rsvp EXPRESS X4 Figure 39 PCI Express Edge Connector 8 2 Stand Alone Operation An external ATX power supply is used to supply power to the DN DualV6 PCle 4 Logic Emulation Board in stand alone mode see Figure 41 The external power supply connects to a Mini Fit PCI Express header J5 Molex P N 45558 0002 The user should connect the matching male power connector on the ATX power supply to this header 6 Pin PSU Adaptor for PCIe Video Cards supplied as part of this kit The DN DualV6 PCle 4 Logic Emulation Board has the following shared power supplies they are generated from the 12V supply on the external power connector 15 DN DualV6 PCle 4 User Manual www dinigroup com 111 HARDWARE DESCRIPTION e 508 5 0 5 0V e PSUS P25VD 425V e PSU4 P18VD 1 8V e PSU2 P33VD 433V Any type power supply is adequate Group recommends a power supply rated for 450W see Ultra LSP450 P N ULT LSP450 Note that only 6 pin PCI Express graphics cable should be used This connector easily confused with the now defunct AUX POWER connector also 6 pin and the 4 and 6 pin EPS motherboard connections The connector is keye
16. 23 UP OUT Eck UP 2 5 P Gi Beso Esc En p923 UP OUT NC amp CLK UP 2 5 gt RSVD_PWR ENTE aay LB P3 3VFUSED_DCA 43 2 1 32 54 100 R215 10K K20 33 TOLERANT H2 DCA RSTn C167 e 2r 7 6 3V MEG_400_Plug_Stratix3_30 84520102LF Figure 32 Daughter Card Global Clock Input Output FPGA B has a signal DDCA_CLK_FB_P N that is looped back from an output of the FPGA to a clock input on the same FPGA IO Bank 24 see Figure 33 DN DualV6 PCle 4 User Manual www dinigroup com 99 HARDWARE DESCRIPTION Meg Array Connector Daughter Card DNV6FEPCIES four Board Base Board Short Length Device DC FEEDBACK flip flop yo Input flip flop Figure 33 Daughter Card Header Feedback Clock The routing length of this feedback clock is equal to the routing length of the signals to the Daughter Card header This allows the option to have a clock inside the FPGA that is phase aligned with the arrival of the clock at the Daughter Card header 4 6 2 Connection between Daughter Card Header Global Clocks and FPGA The connection between the daughter card header global clocks and FPGA B are shown in Table 37 Table 37 Connections between Daughter Card and B Signal Name Daughter Card FPGA Header DCA CLK DN IN P 2 1 1024
17. D7 17 M5 U22 R24 FPGAA CCLK 17 M6 U22 K8 FPGAA PROGN 17 L5 U22 L8 FPGAA BUSY 17 P7 U22 AA8 FPGAA_RD WRN 17 P6 U22 G8 FPGAA INITN 17 K7 U22 P8 FPGAA CSN 17 K6 U22 F8 FPGAA DONE 17 R6 U22 R8 FPGAA 17 5 022 08 _ 1 17 6 U22 W8 FPGAA M2 17 T6 U22 V8 FPGAB DO 17 L29 U24 AF24 FPGAB_D1 17 E31 U24 AF25 FPGAB_D2 17 F31 24 W24 FPGAB D3 17 29 24 V24 FPGAB D4 17 H29 24 H24 D5 17 F30 24 H25 FPGAB D6 17 G30 24 P24 FPGAB D7 17 F29 U U U U U U 24 R24 FPGAB CCLK 17 E29 U24 K8 FPGAB_PROGN 17 K29 U24 L8 FPGAB_BUSY 17 H30 U24 AA8 FPGAB_RD WRN 17 G31 U24 G8 FPGAB_INITN 17 J30 U24 P8 FPGAB_CSN 17 J31 U24 F8 FPGAB_DONE 17 L30 U24 R8 17 29 U24 U8 FPGAB_M1 17 N29 U24 W8 FPGAB_M2 3 3 3 JTAG Al al al ay al ali al ay 17 M30 U24 V8 Virtex 6 devices support IEEE standards 1149 1 and 1532 IEEE 1532 is a standard for In System Configuration ISC based on the IEEE 1149 1 standard JTAG 15 an acronym for the Joint Test Action Group the technical subcommittee initially DN DualV6 PCle 4 User Manual www dinigro
18. HARDWARE DESCRIPTION 1 3 1 Booting from SPI Flash Device Bus AD 24 23 0 1 selects the Boot from SPI on the Marvell 78200 CPU general purpose SPI interface is provided The M25P64 041 is a 64 Mbit 8M x 8 Serial Flash Memory with advanced write protection mechanisms accessed by a high speed SPI compatible bus instructions allowing clock frequency up to 50 MHz 4 see Figure 5 The memory can be programmed 1 to 256 bytes at a time using the Page Program instruction An enhanced Fast Program Erase mode is available to speed up operations in factory environment The device enters this mode whenever the VPPH voltage is applied to the Write Protect Enhanced Program Supply Voltage pin W VPP The memory is organized as 128 sectors each containing 256 pages Each page is 256 bytes wide Thus the whole memory can be viewed as consisting of 32768 pages or 8388608 bytes The whole memory can be erased using the Bulk Erase instruction or a sector at a time using the Sector Erase instruction P3 3VD P3 3VD P3 3VD R421 R420 R480 4 7K 4 7K 4 7K SPI DO 8 SPI DI PI SPLO 3 DU DU 5 P3 3VD DU 5 E DU 2 X S DU X W HS HOLD DU 14 P3 3VD vec 2 BAR M25P128 SO16 2 2uF M25P128 VMF6P 6 3V Figure 5 SPI Flash Boot The SPI Flash can be programmed by an In System Programming programmer e g DediProg SE100 A programming header is pr
19. 130 List of Figures Eigure 1 DNsDualV6 PGIe 4 Losie Emulation Board ose IRSE tte ad eee tiep eer aene ue uetus 2 Figure 2 USB Flash Drive Directory Structure Figure 3 EMU Graphical User Interface Figure 4 DN DualV6 PCle 4 Logic Emulation Board Block Diagram Figure 5 SPI Flash Boot Figure 6 NAND Flash 2Gbit CE Don t Care Figure 7 CPU Memory DDR2 SDRAM 128M x 64 Figure 8 USB2 0 Port 0 Host Type Figure 9 10 100 1000 Ethernet RGMIT Figure 10 SATA Interface Figure 11 Real Time Clock RTC Figure 12 CPU Temperature Senso Figure 13 CPU JTAG Connector Figure 14 Configuration FPGA M 2 0 Select Resistors default Slave Select MAP Figure 15 SPI Variant Select Resistors Figure 16 Configuration JTAG Interface Figure 17 Not Main Bus to FPGA Figure 18 FPGA A B M 2 0 Select Resistors default Slave SelectMAP Figure 19 FPGA A B JTAG Interf Figure 20 VDD Switching Power Su Figure 21 VTT Linear Power Supply Figure 22 SATA Interface on Figure 23 Backup Battery Supply Figure 24 VCCINT Switching Supp Figure 25 Clocking Block Diagram Figure 26 Clock Multiplier Circuit GO Figure 27 Multiplexed Global Clocks from FPGA A B Figure 28 PCI Express Reference Clock Circuit Figure 29 GTP Clock Oscillator and Buffer Figure 30 GTP Clock Oscillator and Buffer Figure 31 SATA II Clock Oscillat
20. 6 17 AJ6 17 AG7 17 AEG 17 AD7 17 Y6 17 17 AF5 17 V7 17 Y9 17 V9 17 W11 17 U8 17 AB5 17 AB7 17 AC5 17 AD5 17 AG6 17 AAG 17 10 17 7 17 AJ7 17 7 17 ADG 17 7 17 W6 17 AE7 17 5 CL e e cual ere Ge FPGA A U U U U U U U U U U 22 AE31 22 L26 22 127 22 F34 U22 G30 U22 H32 U22 H33 22 H30 U U22 J29 22 C34 22 K29 22 B32 22 L25 U 022 126 22 E34 22 K28 22 D34 U22 F31 www dinigroup com 55 HARDWARE DESCRIPTION Signal Name QA2P18 QA2P19 QA2P2 QA2P3 QA2P4 QA2P5 QA2P6 QA2P7 QA2P8 QA2P9 QA3NO QA3N1 QA3N10 QA3N11 12 13 QA3N14 QA3N15 QA3NI16 QA3N17 QA3N18 QA3N19 QA3N2 QA3N3 QA3N4 QA3N5 6 QA3N7 QA3N8 QA3N9 QA3P0 DN DualV6 PCle 4 User Manual Configuration FPGA 17 W7 17 Y8 17 V10 17 8 17 5 17 6 17 4 17 AD4 17 5 17 24 17 26 17 AG26 17 AE26 17 AD27 17 AJ27 17 AK27 17 AJ29 17 AJ26 17 AA28 17 AA26 17 AA24 17 AC27 17 AD25 17 AE24 17 AF28 17 AG25 17 AH25 17 AF26 17 AH28 17 AC25 cH G Gigga FPGA A U U U U U U U U U U U U U U U 22 K26 22 F33 22 31 22 K33 U22 30 U22 C32 U22 C33 22 A33 22 031 22 E32 22 V25 22 834 22 134 22 V27 22 125 22 V29 22 Y29 22 34 022 128 www dinigroup com 56 HARDWARE DESCRIPTION
21. CLK MUX 14 J8 18 CLK2p 1 CLK Ten 121 VT 2 CLK2n P2 5VD CLK MUX CLK3 3 R347 A A 47K MUX CLK3p te T LK3n 90120 0123 GND 9346 AJ 47K CLK CLK3n KARN FPGA CLKO 6 923 FPGA CLKO 55 MUX FPGA 5 SELO pg23 FPGA CLK1 SEL1 10 1 GND VDD T T 11 20 1 56 52 GND VDD 2 2uF 2 2uF 1 5854057 550 20 amp 3V 6 3V ICS854057AGLF gt Figute 27 Multiplexed Global Clocks from 4 3 2 Connection between FPGA and the Clock Multiplexer The connection between FPGA A B and the Clock Multiplexer U6 are shown in Table 31 Table 31 Connection between FPGA and Clock Multiplexer Signal Name FPGA A B Clock MUX 4 1 FPGAA OUTp U22 M23 U6 2 OUTn U22 L24 U6 4 FPGAB OUTp U27 F24 U6 7 FPGAB OUTn U27 F23 U6 9 J8 1 U6 14 TPn 18 2 06 12 CLKO U17 T10 U6 6 CLK1 U17 T11 U6 5 4 4 PCI Express Reference Clocks In system the PCI Express clock from the PCI Express Edge connector drives the Marvell MV78200 pott directly The 1 5557 05 18 provided as a clock source for the backend to drive the PEX1 port and the Configuration FPGA GTP Transcetvers The ICS5507 05A provides the HCSL clocks for the backend The ICS557 05A is a spread spectrum clock
22. H15 N14 15 P15 5 816 N15 Eig 16 7 G18 N16 G20 BO P17 BO N17 g 1111 eo ooo oO S o 9 A us EIE gt SIS 11111 gt Ud ud d 1111 us 03 03 ud 04 03 03 03 3 03 03 03 03 03 03 04 03 03 stots ts ts tettast ttt PVCCO DC BO o AG E B0 VCCO LN 2 2uF _ 6 3V MEG 400 Plug Stratix3 30 84520102LF Figure 34 Secondary Daughter Card DC Header Clock 4 6 4 Connection between FPGAs and the Secondary DC Header Clocks The connection between the Virtex 6 FPGA and the secondary Daughter Card header clocks are shown in Table 38 These signals may be used as inter connect or clocks Table 38 Connections between FPGA B and y Daughter Card Header Clocks Signal Name DC Header FPGA DC Bank 0 DCA OUT P2 A3 24 AH23 NO OUT P2 B4 24 AH24 CC P2 H11 24 AK27 N13 CC P2 G12 24 27 P2 A11 24 AH25 CC P2 B12 24 25 DN DualV6 PCle 4 User Manual www dinigroup com 101 HARDWARE DESCRIPTION Signal Name DC Header FPGA P8 P2 E5 24 AN27 N8 2 5 24 AM27 DC Bank 1 DCA B1 P13 CC P2 K11 24 AD30 N13 P212 24 AC30 DCA P1
23. UG 198 Virtex 5 RocketlO GTX Transceiver User Guide GTP transceivers are placed as dual transceiver DUAL tiles in Virtex 5 LXT and SXT Platform devices This configuration allows two transceivers to share a single PLL with the TX and RX functions of both reducing size and power consumption Table 18 shows the connection between the Configuration FPGA and FPGA A B In line AC Coupling capacitors are provided for DC isolation from the Transmitter DN DualV6 PCle 4 User Manual www dinigroup com 86 HARDWARE DESCRIPTION Table 28 High Speed Serial connection between the Configuration and FPGA A B Signal Name Configuration FPGA A B FPGA 17 AK2 17 AL2 17 ALA 17 1 17 4 17 AN3 17 AP3 17 2 17 AD2 17 AE2 17 AE1 17 AF1 17 AJ2 17 AH2 17 AH1 17 AG1 HS CF A TXPO HS A HS HS CF A HS CF A HS CF A HS CF A RXP1 HS RXN1 HS B TXPO HS CF B TXNO HS CF B RXPO HS CF B RXNO HS CF B 1 HS CF B HS B RXP1 HS 22 G3 22 G4 22 D1 22 D2 22 E3 22 E4 22 C3 22 24 5 24 AP6 24 AP1 24 AP2 24 AM5 24 AM6 24 AN3 24 4 GGG Ga Gla ae 3 7 Backup Battery The encryption key memory cells are volatile and must receive continuo
24. 2 2uF 6 3V EN 6 3V VBATT 1 2 VBATT 20 2 4 20 P3 3VAUX gt 21 GND GND CER 02 55752257501255 BAS40 05 SOT23 TPS78225DDCR BT1 3 90120 0122 Figure 23 Backup Battery Supply 3 7 2 Backup Battery Loads The backup battery supplies the following loads see Table 29 Table 29 Backup Battery Loads Signal Name Description P2 5V_VBATT FPGA A P2 5V_VBATT FPGA U17 L23 Configuration FPGA U36 3 Real Time Clock RTC 3 8 VCCINT Switching Power Supply FPGA The PTHO8T250W 15 a high performance 50 A rated non isolated power module operating from an input voltage range of 4 5 V to 14 V The PTHO8T250W requires single resistor R183 to set the output voltage to 1 0V FPGA A B share a single PTHO08T250W supply between both FPGAs see Figure 24 TTP1 0VD Ri82 1 87K 1 Pi2V Ol P1 0V_VCCINT_V6 1 PSUS Es Pi2y 7 1 0 6 E 35A PI2VEUSED VCCJNT V6 fyn vour H 4 4 4 Ci55 0451015 MRL 1084 1105 cross VIN c1087 1104 47u0F L 150uF 2h 150uF 2h 1500 1504 47uF 15 2 2uF 47uF 2k 680 2K 680uF 680uF 680uF 16V 16V 1 16V 16V 16V 63V 6 3V av 1 20 20 20 20 20 0 10 184 RANG
25. 8608 7HWO0Z 250 Jagram Figure 25 Clocking Block D 90 Inigroup com www d DN DualV6 PCle 4 User Manual HARDWARE DESCRIPTION e FPGA Clock Multipliers 515326 x3 o General Clock Multiplier U10 GO o DDR2 Clock Multiplier 016 G1 o LVDS Clock Multiplier U20 G2 e Multiplexed Global clocks from FPGA e PCI Express Reference Clock e Oscillators for GTP Transceivers x4 e Daughter Card Header Clocks o DCA CLK DN IN P N o DCA CLK UP OUT P N Not Main Bus Clock Source Synchronous e External Clock Input not shown in block diagram The individual clock resources will be further explained in the following paragraphs 4 2 Clock Multipliers x3 The 515326 15 a jitter attenuating precision clock multiplier for applications requiring sub 1 ps jitter performance The 515326 accepts dual clock inputs ranging from 2 kHz to 710 MHz and generates two clock outputs ranging from 2 kHz to 945 MHz and select frequencies to 1 4 GHz The two outputs are divided down separately from a common source The device provides virtually any frequency translation combination across this operating tange The 15326 input clock frequency and clock multiplication ratio are programmable through an or SPI interface configured for The 515326 is based on Silicon Laboratories 3td generation DSPLL technology which provides any rate frequency synth
26. VIT A 9 U54 T 10114 vo 3 75 VIT A 2 5 A R620 cess 0652 0651 380uF 47uF 2 2uF t VTT REFIN R639 4 7K t JA 1 REFIN REFOUT 6 6 3V 6 3V 6 3V 20 20 20 R645 4 7K VTENA 7 VREF DIMM A TANT CER C650 R643 C662 C668 EN C669 47uF 4 7K 2 2uF 2 2uF 8 2 2uF 3V 6 3V 6 6 3V _ 20 20 20 Ti 9 2096 L ER PWRPAD PGOOD 2 CER S51 200 SONTO TPS51200DRCT Figure 21 VIT Linear Power Supply 5 VTT A 3 4 5 Serial Presence Detect EEPROM Operation DDR3 SDRAM modules incorporate serial presence detect The SPD data is stored in a 256 byte EEPROM The first 128 bytes are programmed by Micron to comply with JEDEC Standard JC 45 Appendix X Serial Presence Detect SPD for DDR3 SDRAM Modules These bytes identify module specific timing parameters configuration information and physical attributes User specific information can be written into the remaining 128 bytes of storage READ WRITE operations between the master system logic and the slave EEPROM device occur via a standard I2C bus using the DIMM s SCL clock and SDA data signals together with SA 1 0 which provide four unique DIMM EEPROM addresses Write protect WP is connected to Vss internal to the Temp Sensor EEPROM permanently disabling hard
27. 1 bom Figure 1 DN DualV6 PCle 4 Logic Emulation Board DN DualV6 PCle 4 Virtex 6 Board features the following e Hosted in a 4 lane PCI Express Slot GENT1 or Stand alone e Xilinx Virtex 6 FPGAs FF1156 3 2 1 1L Speed Grade populated with any of the following options for FPGA A B o XC6VSX475T o XC6VSX315T o XC6VLX365T XC6VLX240T o XC6VLX195T o XC6VLX130T e FPGA to FPGA interconnect Single ended and LVDS 500MHz LVDS Chip to Chip 1 0Gb s Source Synchronous Clocking for LVDS LVDS pairs be used as two single ended signals at reduced frequency 225MHz Reference designs for integrated I O pad ISERDES OSERDES 10x pin multiplexing per LVDS pair e Not Main Bus NMB connects both Virtex 6 FPGAs via dedicated busses to the Configuration FPGA DN DualV6 PCle 4 User Manual www dinigroup com 2 INTRODUCTION o 40 Signals LVDS RocketlO GTX Transceivers 6 5 Gb s with 3 2 speed grade 5 0 Gb s with 1 o 4 Lanes connected between FPGA A and FPGA B o Lanes connected from Configuration FPGA to FPGA A o Lanes connected from Configuration FPGA to FPGA B o Data examples provided using Aurora protocol e FPGA Configuration Virtex 6 o Configuration Options USB PCIe Ethernet JTAG Stand alone configuration with USB stick o Encryption Readback and Partial Reconfiguration e Flexible Clock Resources o FPGA Clock Multipliers 515326 x3 General Clock Net
28. 13 1 14 1 15 1 16 1 17 1 18 1 19 AB1N2 AB1N3 DN DualV6 PCle 4 User Manual CIGI ege c ere GIG Gc Ci FPGA B uc csl c GIG c 24 AL31 24 AL34 24 AM33 24 AN32 24 AP32 24 AF26 24 AN33 24 AF30 24 AG27 24 28 24 29 24 34 24 AK33 24 AE27 24 AE28 24 31 24 29 24 AD20 24 AD19 24 AN18 24 AN20 24 AN23 24 AD21 24 AG21 24 AH20 24 AE19 24 AP21 24 AL19 24 AP21 24 AH22 24 AL23 24 AL21 www dinigroup com 82 HARDWARE DESCRIPTION Signal Name 1 5 1 6 1 7 1 8 1 9 AB1P0 AB1P10 AB1P11 AB1P12 AB1P13 AB1P14 AB1P15 AB1P16 AB1P17 AB1P18 AB1P19 ABIP2 AB1P3 AB1P4 1 5 AB1P6 AB1P7 AB1P8 AB1P9 2 0 2 1 AB2N10 AB2N11 AB2N12 AB2N13 AB2N14 DN DualV6 PCle 4 User Manual Signal Name ABINS 2 ABING __ 02090001 02080000 ABINS 02820000 ABIND ft AI appo 2 9240 ABPO 02880000 qUZ MS ABIPIS 02810000 02890000 0289 ABIPIT ABs 1002802 ABIPIO 100280 AB 02020000 19220 ABS 10089 pP 02880000 UBL UA ABN ABN
29. NC 18 NC 19 NC 20 NC 21 NC 22 NC 23 NC 24 NC 25 NC 26 NC 27 DEV OEn N n ELIT o j OND eV t2 OD NO 00 4 1 4 P1 8VD I VDDIO C59 C446 VDDI1 2 2uF 2 2uF NANDO2GR3B2CZAGE VFBGA63 6 3V 6 3V NANDO2GR3B2CZA6E gt Figure 6 NAND Flash 2Gbit CE Don t Cate Each block can be programmed and erased over 100 000 cycles To extend the lifetime of NAND Flash devices it is strongly recommended to implement an Error Correction Code ECC The device feature a Write Protect pin pulled high by R66 that allows performing hardware protection against program and erase operations The device feature an open drain Ready Busy output that can be used to identify if the Program Erase Read P E R Controller is currently active The use of an open drain DN DualV6 PCle 4 User Manual www dinigroup com 34 HARDWARE DESCRIPTION output allows the Ready Busy pins from several memories to be connected to a single pull up resistor The device has a Chip Enable Don t Care feature which allows code to be directly downloaded by the CPU as Chip Enable transitions during the latency time do not stop the read operation The NAND Flash is connected to the Device Bus on the Marvell CPU see Table 4 The NAND Flash is also connected the Configuration FPGA see the schematic for further details This allows the NAND Flash to be programmed via the Configu
30. 125 DN IN 2 1 024 124 DCA GLK HP OUT P P2 E3 U24 F24 DCA CLK UP OUT N P2 F3 U24 F23 4 6 3 Source Synchronous Daughter Card DC Header Clocks Each Daughter Card IO Bank contains a number of clock capable LVDS pairs CC nets connect to SRCC and MRCC pins on the FPGA while pins connect to global clock inputs on the and is capable of clocking all signals on the daughter card using synchronous zero hold time timing Note on Virtex 6 this means a GCC pin a SRCC or MRCC pin on banks 13 14 15 16 and 23 see Figure 34 These clocks DN DualV6 PCle 4 User Manual www dinigroup com 100 HARDWARE DESCRIPTION need to comply with the IO requirements of the 6 FPGA IO bank they are connected too 00 0 GCC OUT DN NO GUC OUT 5 um Be N1 VREF 88 P2 B8 VREF 3 0_ 3 810 4 N3 811 Bo RIE 9999998 g gt giu us 04 03 03 04 03 03 0103 0 gt 1251 P5 814 NS 6 15 A15 BIS N6 812 P7 X 0 BUS 2 0200 1451 GCC BUS 3 H3 5 G4 Bo G6 Bo N10 Gg H9 BO N11 G10 P12 H11 N12 E CC ur 8124 N13
31. 15 U22 P5 GTX AB 1 U59 14 U24 AD6 AB 1n U59 13 U24 AD5 The oscillator power supply 060 15 filtered to reduce power supply noise and jitter Please see the 51534 datasheet for more information 4 5 5 SATA II Clock Oscillators Circuit 150MHz fixed frequency oscillator X10 X12 P N LV7745DW 150 0M is populated to provide a clock source for the SATA II GTP Transceivers see Figure 31 P2 BIESOSDUSATAUA R143 lt gt R140 lt gt R139 R144 4 7K lt 4 7K 47K 4 7K OSC SATA A 51 SATA pg23 OSC SATA A 1 H Fs1 Fe pg26 pg23 OSC_SATA_A FSO MA 4 FSO CLK CLK SATA An pg26 OSC SATAAEN 2 1 5 SATAA NC 2 5 OSC SATA NC L5 a 3 6 P2 5VF_OSC_SATA_A PSP GND VDD eee cse RS SI534 SMT 8 O tuF 10uF R673 LV7745DW 150 0M 16V 6 3V 10 20 CER CER 2 2R Note Frequency 150MHz Figure 31 SATA II Clock Oscillator 4 5 6 Connection between SATA II Clock Oscillators and the FPGAs The connections between the SATA Clock Oscillators and FPGA A B are shown in Table 36 These signals are routed as differential pairs LVDS and are AC coupled Table 36 Connection between SATA II Clock Oscillators and FPGA A B DN DualV6 PCle 4 User Manual www dinigroup com 98 HARDWARE DESCRIPTION Signal Name SATA II Clock FPGA A B Oscill
32. 20 20 20 0 10 0 CER TANT TANT TANT TANT CER CER 1 0 20 TAO FOER S TANT TANT TANT TANT 2 17 P1 0V_SENSEp V6 R700 oR SHARE SENSE d COUP SENSE P1 0V SENSEn V6 R701 OR CLKIO INH UVLO SmartSYNCH ONFIG 18 VOADJ V6 VOUT ADJ E GND 88 85 22m 1 e GND P1 0VD AGND 170 GND AGND E THOETZSOW DIP2Z RSET al PTHOBT250WAZ SEQ ENin 855138 pgi2 19 SEQ Figure 24 VCCINT Switching Supply for FPGA DN DualV6 PCle 4 User Manual www dinigroup com 88 HARDWARE DESCRIPTION Note In order to comply with the PCI Express Mechanical requirements the VCCINT power supply was designed to meet the nominal power requirements of FPGA Power and heat sinking on was compromised and the user design may exceed the requirements under worst case conditions 4 Clock Generation 4 1 Clock Methodology The DN DualV6 PCle 4 has a flexible and configurable clocking scheme Figure 25 is block diagram showing the clocking resources and connections All of the Global Clock Networks on the DN DualV6 PCle 4 are routed point to point using dedicated LVDS routes Since LVDS is a low voltage swing differential signal using a single ended input buffer in the FPGA will not work An example Verilog implementation of a differential clock input i
33. 22 P34 22 L31 22 L34 22 K31 22 29 22 828 22 133 22 128 22 N25 22 R26 22 R31 22 P31 22 N32 22 N33 22 L29 22 N28 22 P25 22 N27 22 M26 22 M30 22 N34 22 M31 22 K34 22 AD27 22 AE29 22 30 22 2 www dinigroup com 58 HARDWARE DESCRIPTION Signal Name 5 12 QA5N13 QA5N14 QA5N15 QA5N16 QA5N17 QA5N18 QA5N19 QASN2 QA5N3 QA5N4 QA5N5 QA5N6 QA5N7 QA5N8 QA5N9 5 1 5 10 5 11 12 13 4 15 16 17 18 19 2 QA5P4 DN DualV6 PCle 4 User Manual Configuration FPGA 17 26 17 H27 17 F28 17 G28 17 E27 17 G26 17 L24 17 25 17 L26 17 N25 17 T24 17 F26 017 128 17 M27 17 N28 17 H24 U17 N24 17 M25 U17 K27 U17 P26 17 27 17 G27 17 E28 17 H28 17 E26 17 G25 U17 K24 17 24 17 125 17 P25 17 R24 Sg ee ec ege Ci 22 AP33 22 2 22 AH34 22 AF29 22 34 22 30 22 28 22 AE26 22 AD26 22 AH30 22 AM31 22 AK34 22 AL33 22 AJ32 22 1 22 2 22 AE27 22 AE28 22 29 22 AN32 22 AP32 22 AH33 22 34 22 28 22 AN33 22 AF30 22 AG27 22 AF26 22 AD25 22 AH29 22 AL30 www dinigroup com 59 HARDWARE DESCRIPTION Configuration FPGA A FPGA U17
34. 33 GTP Oscillator Frequency Select Signals e 34 Connection between GTP Clock Buffers and FPGAs e 35 Connection between GTP Clock Buffers and FPGA A B 36 Connection between SATA II Clock Oscillators and FPGA A B e 37 Connections between Daughter Card and B e 38 Connections between FPGA B and y Daughter Card Header Clocks e 39 Connection between External Clock Header and Clock Multiplexer e 40 Connections between RS232 Port and the Configuration FPGA CPU e 41 Connection between FPGA A B and Temperature Sensors e 42 FPGA Status LEDSs e 43 FPGA DONE LEDS 44 Gigabit Ethernet LEDs e 45 Power Supply Status LEDs e 46 USB Fault LED e 47 Miscellaneous LEDs e 48 Daughter VCCO Reset Signal e 49 FPGA to Daughter Card Header IO Connections 1 INTRODUCTION Chapter Introduction This User Manual accompames the DN DualV6 PCle4 Xilinx Virtes 6 Logic Emulation Board For information regarding the Virtex 6 parts Please reference the datasheet on the Xilinx website 1 DN DualV6 PCle 4 LOGIC Emulation Kit The DN DualV6 PCle 4 is hosted in 4 lane PCI Express GENI system but can be used stand alone and is configured via USB or Ethernet The FPGA configuration and other miscellaneous board functions are controlled by the Marvell MV78200 CPU single DN DualV6 PClIe 4 configured with two Xilinx Virtex 6 SX47
35. 4 Not Main Bus Clock Circuit In Source Synchronous mode QAO P N 18 19 can be used as the clock signal Table 15 shows the connection between the Configuration FPGA and FPGA A the same applies to FPGA B 4 8 External Clock Test Point A three terminal header is provided to allow for an external differential clock CLK_MUX_TPp n input that drives the ICS854057 LVDS Clock Multiplexer The 1 5854057 is a 4 1 LVDS Clock Multiplexer which can operate up to 2GHz and is a member of the HiPerClockS family of High Performance Clock Solutions from ICS The CLKp CLKn pairs can accept most standard differential input levels Internal termination is provided on each differential input pair The ICS854057 operates using a 2 5V supply voltage The fully differential architecture and low propagation delay make it ideal for use in high speed multiplexing applications The select pins have internal pull down resistors 4 8 1 Multiplexed Global Clock Circuit Header J8 allows a LVDS clock input that is multiplexed by ICS854057 U6 and drives the GO clock network see Figure 27 DN DualV6 PCle 4 User Manual www dinigroup com 103 HARDWARE DESCRIPTION FPGA OUT pg23 FPGAA CLE EPGAA 2 gi 18 CIR FPCA OUT 4 CLK_FPGAA_OUTn X Qon VTO pg23 FPGAA OUTn CLKOn FPGAB OUTp 7 pg23 FPGAB OUTp CLK OUTI T
36. 5VD x U10 SYNTH XA G0 XTAL A S8YNTH 800 6 xa ckouTi GND ekout 2 100R 114 285000 100ppm 7 ckoure 35 CLK Gop GO cee OuF 16 34 Gon C61 O iuF GOn 17 PANI 2 R31 100R gt R392 C64 0 1uF FPGA 12 100R 1 C63 FPGA took eee R425 47K 4 P2 5VD R424 47K SYNTH RATE GO 15 3 R426 47K SYNTH RATEO G0 11 RATEI INT_C1B x R432 47K caola CLK_FPGA_OUTp R437 47K SYNTH INC GO 20 CFPGA OUTR 431 47K SYNTH DEC GO 19 NC LoL 8 SYNTH 101 Go AA SYNTH LOL SCL SYNTH ALL 22 DS7 R387 SCL SYNTH ALL 47K SYNTH SDI GO 27 SOL LED RED 4538 SDA SYNTH ALL 28 P923 SDA SYNTH ALL R69 47K SYNTH CMODE GO 38 0 500 R451 4 7K SYNTH A0 24 R67 47K SYNTH Ai 25 2 R458 4 7K SYNTH G0 Com NE S x R55 47K SYNTH CS 21 2 SSn 14 X CS CA NC Em NC 05 T UM P2 5VD 8 5 0 P2 5VF SYNTH GO RST SYNTH gt gt R466 GND VOD T om E tos T Gi 4 7K OND cis VOD 2 2uF 2 2uF 2 2uF MPZ1608S601A 2 2uF amp av 6 3v 1000 gt 1532570235 96326 6 Figure 26 Clock Multiplier Circuit 4 2 2 Connections between the FPGAs and Clock Multipliers All of the Global Clock Networks on the DN DualV6 PCle 4 are rout
37. AC12 24 AC13 U U U U U U U U U U Note The maximum clock frequency with the ICS854104 differential to LVDS clock buffers are 00M Hz see datasheet 4 3 Multiplexed Global Clocks from FPGA A B The 1CS854057 is a 4 1 LVDS Clock Multiplexer which can operate up to 2GHz and is a member of the HiPerClockS family of High Performance Clock Solutions from IDT The CLKp CLKn pairs can accept most standard differential input levels Internal termination is provided on each differential input pair The ICS854057 operates using a 2 5V supply voltage The fully differential architecture and low propagation delay make it ideal for use in high speed multiplexing applications The select pins have internal pull down resistors 4 3 4 Multiplexed Global Clock Circuit CLK_FPGAA_OUTp n CLK_FPGAB_OUTp n are LVDS clock outputs from FPGA A B that are multiplexed by the ICS854057 U6 and allow the GO clock network to be driven by either FPGA A or FPGA B see Figure 27 DN DualV6 PCle 4 User Manual www dinigroup com 93 HARDWARE DESCRIPTION U6 pg23 CLK FPGAA lt lt CLK FPGAA OUTp 2 CLKOp 16 CIK FPGA OUT 4 CLK_FPGAA_OUTn X Qon VTO CLKOn pg23 FPGAA OUTn FPGAB OUTp 7 pg23 FPGAB OUTp CLK OUTI x H vri pg23 FPGAB OUTn FPGAB OUTh 9
38. Aks nw LISP 13 Ak33 OANT lO L13P A0 017 34 als OANT om 10 L13N 13 aG32 GAO0PS L13N A00 016 34 aps OAPs Md L14P_13 GAONS 10 14 A25 34 Ed 10 VREF 13 1 2 58 OPT VREF A24 34 89 10 L15P 13 Hakas IO L15P A23 34 Ais 2 ALS 19 fu 10 L15N 13 IO L15N 22 34 ONPG x1 IO LI6P 13 IO 116 A21 34 QAUNTS L16N 13 L16N A20 34 Fang E AN9 L17P 13 IO L17P A19 34 apo OAN o 2 10 117 13 OPTS L17N A18 34 Fagg Ox IO LIBP 13 AN33 14 lO L18P A17 34 Fang ONTO 10 13 ANS2 IO LIN 16 94 ANTO_GAUPTS IO 13 2 10 34 OAN 13 2 nm S IO L19N VRP 34 B2 UB w28 F AE10 m 2 13 C558 C569 570 T cens ces ce cars 0807 0822 AA32 2 2uF 2 2uF 2 2uF AM9 2 2uF 2 2uF 2 2uF 2 2uF 2 2u0F 2 2uF 0 18 amp av eav 6 3v 84 amp
39. Configuration Schemes e 12 SeleccMAP Bus between Marvell 78200 CPU and Configuration FPGA e 13 Connection between SPI Flash and the Configuration e 14 Connection between JTAG Header and Configuration FPGA e 15 Connections between the Configuration FPGA and FPGA e e 6 Connections between the Configuration and FPGA 7 Fast Bus connections between the Configuration and 8 High Speed Serial connection between the Configuration and e 19 FPGA Configuration Schemes e 20 SeleccMAP Bus between Configuration FPGA and FPGA A B e 21 Connection between JTAG Header and e 22 Serial Presence Detect EEPROM Connections e 23 Clocking Connections between FPGA and the DDR3 SDRAM SODIMMs e 24 Connections between the SODIMMs and FPGA le 25 DDR3 PCB Trace Lengths e 26 SATA II Ports on FPGA and FPGA e 27 High speed LVDS IO Bus between FPGA A and FPGA e 28 High Speed Serial connection between the Configuration FPGA and FPGA e 29 Backup Battery Loads sse e 30 Connections between FPGAs and Clock Multipliers e 31 Connection between FPGA A B and Clock Multiplexer e 32 Connection between CPU Configuration FPGA and PCI Express Reference Clock Buffer e
40. FPGA 3 3 3 Uca 3 4 aiea eee ret eee 3 4 1 DDR3 SDRAM Memory Interface Solution 342 DDR3 Tetimination s o ove aoctor REPEATED te eH Ha 3 4 3 Vp switching Power Supply P DIMM X 3 44 VTT Linear Power Supply 75 VTT x eee 3 4 5 Serial Presence Detect EEPROM 3 4 6 Clocking Connections between FPGA and DDR3 SDRAM SODIMMS 71 3 4 7 SODIMM connections to the FPGA et 3 4 8 DDR3 PCB Trace Lengths 2219 3 5 SATA Interface FPGA FPGA B 80 9 6 rrr teet eee 81 3 6 1 High speed LVDS IO cie 81 3 6 2 High Speed Interconnect GTP Configuration FPGA to FPGA A B 3 7 Backup Battery e 3 7 1 Backup Battery Circuits oet be eee tea E E E AE SEE E E A EE E PCT 3 7 2 Backup Battery Loads 3 8 VCCINT Switching Power Supply FPGA A D CL
41. FPGAA LED2 DN DualV6 PCle 4 User Manual U22 AE23 LED2 DS23 www dinigroup com HARDWARE DESCRIPTION Signal Name FPGA LED LED3 22 22 LED3 0521 FPGAA_LED4 22 AC23 LED4 0520 FPGAA_LED5 22 AC24 LED5 DS19 FPGAA_LED6 22 AC22 LED6 0518 22 AD22 LED7 15517 FPGA B U24 FPGAB LEDO FPGAB_LED1 FPGAB LED2 FPGAB LED3 FPGAB LED4 FPGAB LED5 FPGAB LED6 LED7 Configuration FPGA U17 LEDO 17 AE13 LEDO DS12 CFPGA_LED1 17 AE12 LED1 DS13 CFPGA_LED2 17 AF23 LED2 DS14 CFPGA_LED3 17 AG23 LED3 DS15 CFPGA_LED4 17 AF13 LED4 0516 24 AA23 LEDO DS34 24 AB23 LED1 DS33 24 23 LED2 0532 24 22 LED3 0531 24 AC23 LED4 0530 24 24 LEDS 0520 24 AC22 LED6 DS28 24 AD22 LED 0527 7 2 Configuration DONE LEDs After the FPGAs have received all the configuration data successfully it releases the DONE pin which is pulled high by a pull up resistor A low to high transition on the DONE indicates configuration is complete and initialization of the device can begin DONE pin drives an N MOSFET and turns ON a blue LED when the DONE pin goes high Table 43 describes the DONE LED and its associated pin assignment on the FPGAs Table 43 FPGA DONE LEDS Signal Name FPGA FPGAA_DONE U26 Y31 FPGAB_DONE U22 R8 CFPGA_DONE 017 15
42. JTAG Connector Table 10 shows the connection between the CPU JTAG connector and the Marvell MV78200 Table 10 CPU TAG connection to the Marvell MV 78200 DN DualV6 PCle 4 User Manual www dinigroup com 42 HARDWARE DESCRIPTION Signal Name Connector Jr J23 9 JI TDI 23 5 Jr 23 13 JI 5 CORE 23 7 JI TMS 123 7 JI TMS 01 123 7 JI RSTn 123 3 JT 885 123 15 2 Configuration FPGA Virtex 5 2 1 Overview The Virtex 5 family provides the newest most powerful features in the market Using the second generation ASMBL Advanced Silicon Modular Block column based architecture the Virtex 5 family contains five distinct platforms sub families the most choice offered by any FPGA family Each platform contains a different ratio of features to address the needs of a wide vatiety of advanced logic designs In addition to the most advanced high performance logic fabric Virtex 5 FPGAs contain many hard IP system level blocks including powerful 36 Kbit block RAM FIFOs second generation 25 x 18 DSP slices SelectIO technology with built in digitally controlled impedance ChipSync M source synchronous interface blocks system monitor functionality enhanced clock management tiles with integrated DCM Digital Clock Managers and phase locked loop PLL clock generators and advanced configuration options Additional platform dependant
43. Mode Configuration Resistots Installed Not Installed NOTE Internally pulled to Ox1 D 20 CPU1 Enable R486 0 Disable 1 Enable NOTE Internally pulled down to 0 0 DEV D 22 21 DEV BootCEn Device Width R491 R39 R492 R40 00 8 bits 01 16 bits 10 32 bits 11 Reserved NOTE Internally pulled down to 0x0 D 24 23 Boot From NAND Flash R498 RA87 R497 R488 Defines the default value of bit lt NFBoot gt in the NAND Flash Control Register 0 0 Boot from device bus NOR Flash ROM 0x1 Boot from SPI 0x2 Boot from CE don t care NAND Flash 0x3 Boot from CE care NAND Flash NOTE Internally pulled down to 0x0 DEV_D 26 25 NAND Flash Initialization Sequence R500 R501 R499 R502 0x0 No initialization Ox1 Init sequence enabled 3 address cycles 0 2 Init sequence enabled 4 address cycles 0 3 Init sequence enabled 5 address cycles NOTE Internally pulled down to 0x0 D 27 Big Endian initialization Little Endian 1 Big Endian NOTE Internally pulled down to 0 0 DEV_D 28 CLK25 Select 0 Both CLK25 PT and CLK25 SSC are used 1 Only CLK25 PT is used NOTE Internally pulled up to Ox1 D29 DRAM Interface Width 0 64b 72b DN DualV6 PCle 4 User Manual www dinigroup com 30 HARDWARE DESCRIPTION Configuration Mode Configuration Resistors Installed Not Installed 1 32b 40b NOTE Internally
44. READs and by the memory controller during WRITEs DOS is edge aligned with data for READs and center aligned with data for WRITEs The x16 offering has two data strobes one for the lower 1 005 112058 and one for the upper byte 1205 12058 gt C315 2 2uF ol lelrloleoi ir l 63V U3 lt u gt 0309 0 0 5 M 2 VREF OOOGOOGGCGOG A M8 G8 M DQO 0 988899 8888888888 G2 M DOT M M7 1 001 H7 M 002 2 a Dd 003 8 jv 5 3 Hi 04 N3 H9 065 N7 5 5 F1 006 V A7 2 Q6 Fo 007 P8 e C8 M 008 MLAS A 098 c2 ATO M2 Q9 57 590 Pre 53 M 11 Dati E R2 Di M 00912 R8 12 0912 D9 M 0013 A13 0013 M Dai4 M BAO DQ14 24 LE BAO pais 89 M 2915 L1 BAI F7 MDOS BA2 LDOS Es M 05 CLK M J8 LDQS NU K8 T upos 87 0 x _ DQS 18 A M_WEn K3 NO 4 o M RASR K7 NCIS M_CASn 17 BAS R3 CAS RFU 1 M F3 RFU 2 V DM B3 UDM M ODTO A GSOGGGGGGGG 00000 020200020 02 0020202 02 COD 92 000090 0 ip SS Se SS e S gt M147H 128M
45. SATA A T 5 GND gt MGTRXPO 112 apg SATA c C831 0 1uF 6 1 SATA BH MGTRXNO 112 T RX OIR SATA An 6 AKS MGTREFCLKOP 112 H o UL MGTREFCLKON_112 ANS 8 MGTTXP1_112 MTH Se 112 1 9 MTH 5 EM 67800 5005 MGTRANT 12 AME 67800 5005 J16 o n 14 gt AM1 SATA_A_TxP1_cC842 Q iuF SATA A TxP1 2 Eun 2 112 SATA A TXNT 60843 O uF SATA A EN ow MGTTXN2_112 1 24 Gnd 1 mua SATA A RxN1 c C859 SATA A RxN1 5 MGTRXP2 112 C858 O iuF 6 RX ANG X fi MGTRXN2 112 7 RX m MGTREFCLKIP 112 1 and x22 MGTREFCLKIN 112 8 5 112 MTH 9 2 3 112 8 xm EIE 67800 5005 MGTRXPS 112 67800 5005 VGTRXN3 112 C6VLX130T 1951 2401 365T 1156 Figure 22 SATA Interface on The two SATA II ports connects directly to the FPGA A and FPGA B see Table 26 Table 26 SATA II Ports on FPGA and FPGA B Signal Name SATA A TxPO SATA TxNO SATA A RxPO SATA RxNO SATA SATA TxN1 SATA RxP1 SATA A RxN1 SATA B TxPO SATA B TxNO SATA B RxPO SATA B RxNO SATA B TxP1 SATA B TxN1 CH EEG Gra raya a ara ae DN DualV6 PCle 4 User Manu
46. Signal Name QA3P1 QA3P10 QA3P11 QA3P12 QA3P13 QA3P14 15 16 17 18 19 QA3P2 QA3P3 QA3P4 QA3P5 QA3P6 QA3P7 QA3P8 QA3P9 QA4NO QA4N1 QA4N10 QA4N11 4 12 QA4N13 QA4N14 QA4N15 QA4N16 QA4N17 QA4N18 QA4N19 DN DualV6 PCle 4 User Manual Configuration FPGA 17 AB25 17 AG27 17 AE27 17 AC28 U17 AK26 U17 AK28 17 AK29 17 AH27 17 AB28 17 AA25 U17 Y24 U17 AB27 17 AD26 17 AD24 17 AE28 17 AF24 17 AJ25 17 AF25 17 AG28 17 ACO 17 AA10 17 AJ10 17 8 17 AF10 17 AD11 U17 AL10 17 AJ11 17 AE11 17 AE9 17 AD9 17 AB8 c c FPGA A www dinigroup com 57 HARDWARE DESCRIPTION Signal Name 4 2 QA4N3 QA4N4 QA4N5 4 6 QA4N7 QA4N8 QA4N9 QA4PO QA4P10 QA4P11 QA4P12 QA4P13 QA4P14 QA4P15 QA4P16 QA4P17 QA4P18 QA4P19 QA4P2 QA4P3 QA4P4 QA4P5 QA4P6 QA4P7 QA4P8 QASNO QASNI QA5N10 QASNI1 DN DualV6 PCle 4 User Manual Configuration FPGA 17 AA9 17 AP14 17 AG11 17 13 17 12 17 11 17 10 17 AK9 17 10 17 10 17 9 17 AG8 17 AF9 17 AD10 17 AL11 17 AK11 17 11 17 AF8 17 8 17 8 17 8 17 AN14 17 AG10 17 AN13 17 AP12 17 AM12 17 AH9 17 P24 17 M26 17 K26 17 P27 eL erre cia FPGA A uic C pc Ci Cig C 22 P26 22 P27 22 M27 22 N30
47. Two SATA 2 0 ports with integrated PHYs e Security engine e Pin compatible with single core MV78100 version The innovative on chip crossbar architecture with any to any connectivity enables concurrent transactions among multiple units that results in high system throughput allowing system designers to create high performance scalable systems Sheeva CPU Core Buel Issue W FRU Sheeva CPU Core 32KB I 32KB D 800MHz 1GHz Dual Issue w FPU 32 64 bit 32KB I 32KB D DDR2 800 512KB 12 800MHz 1GHz with ECC 512KB L2 x4or quad x 1 System Crossbar 4 p Da 32b 1 2 Reset Strapping Options Internal pull up down resistors set the default mode of operation of the Marvell MV87200 CPU External pull up down resistors are required to change the default mode of operation These signals must remain pulled up or down until SYSRSTn de DN DualV6 PCle 4 User Manual www dinigroup com 27 HARDWARE DESCRIPTION assertion zero hold time in respect to SYSRSTn de assertion See Table 2 for the default board configuration Table 2 Reset Strapping Options Configuration Mode Configuration Resistots Installed Not Installed DEV_D 0 Reserved R515 R81 NOTE Internally pulled down to 0x0 DEV_D 1 Reserved R38 R28 NOTE Internally pulled down to 0x0 DEV_D 2 PCI Express port0 mode select 0 Endpoint 1 Root Complex NOTE Internally pulled up to Ox1 DEV D 3 PCI Express portO configuration
48. VCCO see table default jumper 1 3 1 5V TP32 wo PQDIMM A 8 PI2VFUSED DIMM A 1 D DIMM A P DIMM 3 P DIMM A TRACK 2 C545 C544 C87 C607 C105 C104 K 5 VOUT ADJ 47uF 6 3V 2 2uF 6 3 20 R581 33R 250mW 150uF 150 16V 16V 330uF INHIBIT 63 1 20 20 20 20 20 TANT TANT CER p97 12 13 25 SEQ EN2n Note The GND pins of the VOUT ADJ trim resistors must be connected directly to the converter GND pin with a trace The jumper opti Adjust VOUT OPEN DDR3 3 1 DDR3 3 4 DDR2 3 5 DORI DN DualV6 PCle 4 User Manual GND TANT PTH12050W DIP6 PTH12050WAZ TANT CER CER CER e Silkscreen Volt JMPR 855138 SEQ EN2n 1 JP2 1 3 5 1 5 A PZ5V 2 4 6 TSM 103 01 T DV P1 8V A x VO R84 514K R83 4 7K R85 47K R86 14 7K on may degrade performance ADJ Trim Resistors 1 35V 1 5V 41 89 2 5V Figure 20 VDD Switching Power Supply P DIMM A www dinigroup com 69 HARDWARE DESCRIPTION 3 4 4 VTT Linear Power Supply 75 VTT x The Texas Instruments TPS51200 is a sink source double data rate DDR termination regulator for termination of DDR3 SDRAM SODIMMs see Figure 21 TP34 1 P DIMM P2 5VD g 75
49. av esv 5VDSOT SST TT0T SXS0T SX85T veces VCCO 34 SVLXT301 1951 2401 365T 1156 Figure 17 Not Main Bus to A In Source Synchronous mode QAO P N 18 19 can be used as the clock signal Table 15 shows the connection between the Configuration FPGA and FPGA A Table 15 Connections between the Configuration FPGA and FPGA A DN DualV6 PCle 4 User Manual www dinigroup com 50 HARDWARE DESCRIPTION Signal Name QAONO QAON1 QAON10 QAON11 QAON12 QAON13 QAON14 15 16 QAON17 QAON18 QAON19 QAON2 QAON3 QAON4 QAON5 6 QAON7 QAON8 QAON9 QAOPO QAOP10 QAOP11 QAOP12 QAOP14 QAOP15 QAOP16 QAOP17 QAOP18 DN DualV6 PCle 4 User Manual Configuration FPGA 17 V33 17 V34 17 AK32 17 AK33 U17 AL33 17 32 17 AN33 17 AP32 17 2 17 AE34 17 AE33 17 AJ34 17 33 17 W32 17 AB33 17 AB32 17 Y34 17 AD34 17 AH33 17 AH32 17 V32 17 734 17 AJ32 U17 AK34 U17 AL34 17 AM33 17 AN34 17 AN32 17 AD32 17 AF34 U17 AF33 c e eL eC e FPGA A U U U U U U U U U U U U U U 22 B10 22 C8 22 8 22 8 U22 Ap9 U22 AP10 U22 AL9 22 AF10 U U22 AJ9 22 M10 22 D10 22 A8 22 F10 22 H9 U22 AC9 U22 AE9 U22 A10 22 B8 22 AG8 22 AK8 22 AH9 22 L10 022 10 www dinigroup com 51 HARDWARE DESCRIPTION Signal Name Con
50. can safely operate to a maximum of 125 C but timing is not guaranteed Use the temperature setting in the ISE place and route tool to make timing allowances DN DualV6 PCle 4 User Manual www dinigroup com 106 HARDWARE DESCRIPTION for operating the out of range The temperature limit can be disabled by a menu option in the configuration interface 6 1 2 Connection between FPGA A B and Temperature Sensors The connection between FPGA A B and the Temperature Sensors are shown in Table 41 Table 41 Connection between FPGA and Temperature Sensors Signal Name Sensor TEMP 55 14 SDA TEMP 55 12 FPGAA DXP FPGAA DXN FPGAB DXP FPGAB DXN 7 LED Indicators The DN DualV6 PCle 4 Logic Emulation board provides various LEDs to indicate that status of the board The LEDs are turned ON by driving the GATE of the N MOSFET HIGH see Figure 38 49 9R LEDA A0 LED GRN LEDA CO DS25 If nom 9mA FPGAA LEDO Figure 38 LED Indicator 7 1 FPGA Status LEDs Numerous LEDs Green are provided to the user as a design aid during debugging The LEDs can be turned ON by driving the corresponding pin HIGH Table 42 describes the Status LEDs and their associated pin assignments on the Virtex 6 FPGAs Table 42 FPGA Status LEDs Signal Name FPGA LED FPGA A U22 FPGAA LEDO U22 AA23 LEDO DS25 FPGAA_LED1 U22 AB23 LED1 DS24
51. com 18 PROGRAMMING CONFIGURING THE HARDWARE 4 Right click on the FPGA and select the Program option A Progress Dialog box will appear indicating programming progress ISE iMPACT Boundary Scan File Edit view Operations Output Debug Window stk BIST IMPACT Flows 0000 ensx 28 Boundary Scan 38 SlaveSerial 3 Direct SPI E SystemACE Create PROM File PROM File Formatter xcBvsx475t 4751 fpga bypass IMPACT Processes Available Operations are mb Program mb Get Device ID Get Device Signature Usercode Read Device Status One Step SVF One Step XSVF Program Succeeded Boundary Scan Console 1 Programmed successfully PROGRESS END End Operation Elapsed time 43 sec lt Console Errors Warnings Configuration Platform Cable USB 6 MHz usb hs 5 Verify that the DONE blue LED 0522 for FPGA A is enabled indicating successful configuration of the 5 Updating the Marvell MV78200 Software This section lists detailed instructions for updating programming the Marvell MV78200 softwate Note Minor changes to this procedure may occur over the life of the product please contact Dini Group for the latest procedures at support dinigroup com 5 1 Setup Updating the Marvell MV78200 Software Before updating programming the Marvell MV78200 softw
52. connectivity o Virtex 5 TXT High performance systems with double density advanced serial connectivity o Virtex 5 FXT High performance embedded systems with advanced serial connectivity e Cross platform compatibility o LXT SXT and EXT devices are footprint compatible in the same package using adjustable voltage regulators Most advanced high performance optimal utilization e FPGA fabric o Real 6 input look up table LUT technology Dual 5 LUT option o Improved reduced hop routing 64 bit distributed RAM option o SRL32 Dual SRL16 option e Powerful clock management tile CMT clocking o Digital Clock Manager DCM blocks for zero delay buffering frequency synthesis and clock phase shifting o PLL blocks for input jitter filtering zero delay buffering frequency synthesis and phase matched clock division e 36 Kbit block RAM FIFOs True dual port RAM blocks Enhanced optional programmable FIFO logic Programmable True dual port widths up to x36 Simple dual port widths up to x72 O Built in optional errot correction circuitry o Optionally program each block as two independent 18 Kbit blocks e High performance parallel SelectIO technology 1 2 to 3 3V I O Operation Source synchronous interfacing using ChipSync technology DN DualV6 PCle 4 User Manual www dinigroup com 44 HARDWARE DESCRIPTION o Digitally controlled impedance DCI active termination o Flexible fine grained I O bankin
53. download section of the web page may contain a document called DN DualV6 PCIe 4 Frequently Asked Questions FAQ This document is periodically updated with information that may not be in the User s Manual DN DualV6 PCle 4 User Manual www dinigroup com 6 GETTING STARTED Chapter Getting Started Congratulations on your purchase of the DN DudV6 PCle4 Xilinx Vintes 6 Logic Boardi The remainder of this chapter describes how to start using the DIN DualV 6 PCle4 Xilinx Virtes 6 Logic Emulation Board 1 Before You Begin 1 1 Configuring the Programmable Components The DN DUALV6 PCIE 4 has been factory tested and pre programmed to ensure correct operation The user does not need to alter any jumpers or program anything to see the board work 1 2 Warnings e Daughter Card Test Headers Over Voltage The 400 pin daughter card test headers are NOT 5V tolerant These signals connect directly with the FPGA IO Take care when handling the board to avoid touching the components and daughter card connections due to ESD e Mechanical Stress Board stiffeners are provided to reduce mechanical stress however inserting and removing Daughter Cards may add additional stress that may cause board failures e ESD Warning The board is sensitive to static electricity so treat the PCB accordingly The target markets for this product are engineers that are familiar with FPGAs and circuit boards However if needed the followin
54. generator that supports PCI Express requirements It is used in PC or embedded systems to substantially reduce electro magnetic interference EMI The device provides four differential HCSL LVDS high frequency outputs with spread spectrum capability The output frequency and spread type are selectable using external pins DN DualV6 PCle 4 User Manual www dinigroup com 94 HARDWARE DESCRIPTION 4 41 PCI Express Reference Clock Circuit The PCI Express clock buffer U13 is provided to distribute the clock network to the Marvell MV78200 PEX1 port and the Configuration FPGA GTP Transceivers see Figure 28 ABM8 25 000MHZ B2 T U13 cya 15 Xt 5 20 MV R63 33R PEXA MV1 p 1 m ETAS 19 CLK PEXA R62 PEXA MVI n Lb 2 18 PEXB CFPGA p R61 338 PEXB CFPGA 1 ik 1 PEX X2 6 CLKBp 17 PEXB CFPGA n R60 38H CFPGA n CLK PEXB CFPGA p 16 CLKBn CFPGA n 16 R453 4 7K PEX 50 2 14 pr R462 CLK p R460 4 7K PEX 51 3 50 CLKCp 43 CIK PEX R470 PEXC RA61 47K PEX S2 52 12 PEXD pr R71 33R PEXD R471 4 7K PEX_OE 8 CLKDp 711 PEXD nr R73 338 CLK n 469 4 7K PEX 7
55. of the daughter and DN DualV6 PCIe 4 face in opposite directions DN DualV6 PCle 4 User Manual www dinigroup com 129 APPENDIX Chapter Appendix 11 Appendix A UCF File See the Customer Support Package USB Flash Drive for the Xilinx User Constraint Files UCH for FPGA 12 Ordering Information Request quotes by emailing sales dinigroup com For technical questions email support dinigroup com DN DualV6 PCle 4 User Manual www dinigroup com 130
56. remote sensor and its own package The remote sensor is a diode connected transistor typically a low cost easily mounted 2N3904 NPN type that replaces conventional thermistors or thermocouples Remote accuracy is 3 C for multiple transistor manufacturers with no calibration needed The remote channel can also measure the die temperature of other ICs such as microprocessors that contain an on chip diode connected transistor 6 1 14 Temperature Sensor Circuit Each FPGA is connected to a temperature sensor This sensor measutes the temperature of the FPGA silicon die see Figure 37 The maximum recommended operating temperature of the FPGA is 85 degrees When the configuration circuitry measures the temperature of any FPGA above 80 degrees it will immediately un configure the FPGA and prevent it from re configuring P2 5VD P2 5VD P3 3VD P2 SND R131 R128 4 7K 4 7K R130 R129 4 7K 0 001uF TEMP STBY A FPGAA DXN STBY DXP CLK TEMP 14 SDA TEMP 12 SMBDATA FPGAA TEMP INTn 11 R642 4 7K TEMP AO 10 ALERT NC ADDO R127 VA 47K TEMP AL A 6 ADD 1 P3 3VD GND VCC TEMP A ae TUE EMP A R652 208 MAX1617A QSOP16 2 2uF MAX1617AMEE 6 3V Address 0011 0001 0x31 Figure 37 Temperature Sensor FPGA A When the temperature drops below 80 the configuration circuitry will again allow the FPGA to configure The FPGA
57. x4 1 Quad x1 NOTE Internally pulled down to 0x0 PCI Express configuration x4 1 Quad x1 NOTE Internally pulled up to Ox1 D 7 5 HCLK Frequency select R45 R526 0x0 167 MHz R531 0x0 Reserved 0x1 200 MHz 0x2 267 MHz 0x3 333 MHz 0x4 400 MHz 0x5 250 MHz 0x6 300 MHz 0x7 Reserved NOTE Internally pulled to 0x2 DEV D 11 8 PCLKO to HCLK ratio R505 R494 R506 R493 0 0 1 R435 504 R53 R503 0 1 1 5 0 2 2 DN DualV6 PCle 4 User Manual www dinigroup com 28 HARDWARE DESCRIPTION Configuration Mode Configuration Resistors Installed Not Installed 0x3 2 5 0 4 3 0 5 3 5 0 4 0 7 4 5 0 8 5 0 9 5 5 6 OxB OxF Reserved NOTE Internally pulled to 0 4 DEV D 13 12 0 L2 to PCLKO ratio 0 0 1 0 1 2 0 2 3 0 3 Reserved NOTE Internally pulled to Ox1 D 17 14 PCLK1 to HCLK ratio 0 0 1 0 1 1 5 0 2 2 0x3 2 5 0 4 3 0 5 3 5 0 6 4 0 7 4 5 0 8 5 0 9 5 5 OxA 6 OxB OxF Reserved NOTE Internally pulled to 0 4 R54 R57 R75 R74 R496 R52 R436 R437 R479 R478 R495 R433 D 19 18 CPU1 L2 to PCLK1 ratio 0 0 1 0x1 2 0 2 3 0 3 Reserved DN DualV6 PCle 4 User Manual R459 R490 www dinigroup com R64 R489 29 HARDWARE DESCRIPTION Configuration
58. 00 in user region D VIVT write back cache I cache 32768 bytes associativity 4 32 byte lines 256 sets D cache 32768 bytes associativity 4 32 byte lines 256 sets Built 1 zonelists Total pages 260096 50 14 SORows 99 Cols VT100 5 5 Update the Linux Kernel 6 Power cycle the DN DUALV6 PCIE 4 Logic Emulation Board and monitor the power up events in the CRT window Note Press ENTER when the Hit any key to stop autoboot appeats in the CRT window DN DualV6 PCle 4 User Manual www dinigroup com 21 PROGRAMMING CONFIGURING THE HARDWARE iS Serial COM1 File Edit View Options Transfer Script Tools 4333 0030 aaa TRO Seria COM1 Bar 1 15 003f0000 Bar 2 is 00370000 skipping setting bar size here Current Bar sizes Bar 0 is 00000000 Bar 1 is 003 0000 Bar 2 is O03f0000 skipping setting bar size here Current Bar Sizes Bar 0 is 00000000 Bar 1 is 003 0001 Bar 2 is 003f0000 skipping setting bar size here board Error calling mvPciifinit for 0 Current Bar 51265 Bar 0 15 00000000 Bar 1 is 00380001 Bar 2 is 003470001 Current Bar Sizes Bar 0 15 00000000 Bar 1 15 00380001 Bar 2 is 003f0001 Current Bar Sizes Bar 0 is 00000000 Bar 1 15 003f0001 Bar 2 is 003 0001 mvPexHalInit is runnin PEX 4 interface detected no Link Copying Environment from OxFFFOO000 CPU 0 926 Rev 0 streaming enabled wr
59. 1 High speed SERDES links between FPGA FPGA B e 10 5 II Oscillator for FPGA e 12 5 II Oscillator for FPGA B The Silicon Laboratories 51534 Quad Frequency Crystal Oscillator is recommended for this application and is available in frequencies from 10MHz to 945MHz The default factory installed oscillator is running at 312 5MHz They are available from Nu Horizons P N 534FB000184DG The oscillator is pre programmed to four fixed frequencies and the output is selected based on the value of OSC_CFV6_FS1 0 signals see Table 33 Reference the schematic for more information Table 33 GTP Oscillator Frequency Select Signals Frequency Select Frequency MHz OSC_CFV6_FS 1 0 OSC FS 1 OSC_CFV6_FS 1 OSC_CFV6_FS n OSC AB FS 1 0 OSC 5 1 OSC 5 OSC AB FS 1 0 OSC SATA A FS OSC SATA A FS OSC SATA A FS OSC SATA A FS OSC SATA B FS OSC SATA B FS OSC SATA B FS OSC SATA B FS Note Fixed frequency 150MHz oscillators provided for X10 and X12 P N LV7745DW 150 0M 4 51 GTP Clock Oscillator Configuration FPGA and FPGA The 1 5854104 023 is a low skew high performance 1 to 4 Differential to LVDS Clock Fanout Buffer that is driven by the 1534 Quad Frequency Crystal Oscillator X9 see Figure 29 DN DualV6 PCle 4 User Manual www dinigroup com 96 HARDWARE DESCRIPTION
60. 1 6HG FBGA84 MT47H128M16HG 37E Figure 7 CPU Memory DDR2 SDRAM 128M x 64 The DDR2 SDRAM operates from a differential clock CK and the crossing of CK going HIGH and going LOW will be referred to as the positive edge of CK Commands address and control signals are registered at every positive edge of CK Input data is registered on both edges of DOS and output data is referenced to both edges of DOS as well as to both edges of CK 1 5 PCI Express Interface The Marvell MV78200 has two PCI Express interfaces Port 0 and Port 1 PCI Express Port 0 is configured as an Endpoint DEV AD 2 0 while PCI Express Port 1 is always a Root Complex The PCI Express ports are PCI Express Base 1 1 compliant and runs at 2 5GHz allowing for 2Gb s of bandwidth in each direction The PCI Express port uses 64 bit addressing as a master or target It supports extended PCI Express configuration space advanced etror reporting power management 105 and DN DualV6 PCle 4 User Manual www dinigroup com 36 HARDWARE DESCRIPTION softwate L1 interrupt emulation message and error messages The device also support P2P bridging non transparent bridge between PEXO and PEXI ports see MV S800598 00C Functional Specifications for more information 1 5 1 PCI Express Port 0 Port 0 is configured as an Endpoint AD 2 0 0 3 is routed as differential LVDS traces AC coupled and co
61. 15 C cx ee ege T GIG Ci www dinigroup com FPGA B Cic c ce GIG c ege cala c 22 M11 22 C12 22 H14 22 K12 22 E14 22 F13 22 10 22 12 22 L11 22 11 22 13 22 E12 22 A13 22 D14 22 H10 22 G11 22 G12 22 K14 22 L13 22 M12 22 C13 22 G13 22 K13 22 F14 22 E13 2211 22 H12 22 K11 22 A11 22 B12 22 D12 24 AH19 84 HARDWARE DESCRIPTION Signal Name AB3N1 AB3N10 AB3N11 AB3N12 AB3N13 AB3N14 AB3N15 AB3N16 AB3N17 AB3N18 AB3N19 AB3N2 AB3N3 AB3N4 AB3N5 AB3N6 AB3N7 AB3N8 AB3N9 AB3P0 AB3P1 AB3P10 AB3P11 AB3P12 AB3P13 AB3P14 AB3P15 AB3P16 AB3P17 AB3P18 AB3P19 AB3P2 DN DualV6 PCle 4 User Manual FPGA A 22 116 22 17 22 G16 2215 22 K17 22 B16 22 116 22 H18 22 114 22 15 22 M17 22 119 22118 22 E17 221317 22 D16 22 B17 22 B15 22 C15 22 G15 22411 22 17 22 F16 22 H15 22 K18 22 A16 22 K16 22 G18 22 115 22 M16 22 M18 22 K19 Ci GIG GG end ae Ci FPGA B CEG erc c GIG C OVE GIO c 24 AF15 24 AK16 24 AJ14 24 15 24 AJ16 24 AF18 24 AF16 24 AG17 24 AD16 24 AD15 24 17 24 18 24 17 24 17 24 17 24 15 24 16 24 15 24 AL14 24 19 24 15 24 AL16 24 14 24 AJ15 24 17 24 AE18 2
62. 4 AG16 24 AH17 24 AE16 24 15 24 18 24 18 www dinigroup com 85 HARDWARE DESCRIPTION FPGA A FPGA B 22 L19 24 AD17 22 F18 24 AK18 22 E18 24 AN17 22 E16 24 AP16 22 C17 24 17 22 15 24 15 22 D15 24 AL15 3 6 2 High Speed Interconnect GTP Configuration FPGA to FPGA A B Two high speed serial channels are provided between the Configuration FPGA and FPGA This could be used for pin multiplexing 10x pin per LVDS pair The GTP transceiver is highly configurable and tightly integrated with the programmable logic resources of the FPGA It provides the following features to support a wide variety of applications Current Mode Logic CML serial drivers buffers with configurable termination voltage swing and coupling e Programmable TX pre emphasis and RX equalization for optimized signal integrity e Line rates from 100 Mb s to 3 75 Gb s with optional 5x digital oversampling requited for rates between 100 Mb s and 500 Mb s e Optional built in PCS features such as 8B 10B encoding comma alignment channel bonding and clock correction e Fixed latency modes for minimized deterministic datapath latency e Beacon signaling for PCI Express designs and Out of Band signaling including e COM signal support for SATA designs The Xilinx CORE Generator tool includes a Wizard to automatically configure GTP transceivers to support one of various protocols or perform custom configuration see
63. 45 HARDWARE DESCRIPTION 65 nm copper CMOS process technology 1 0V core voltage e High signal integrity flip chip packaging available in standard or Pb free package options 2 3 FPGA Configuration Virtex 5 The Virtex 5 FPGA 18 configured by loading application specific configuration data the bitstream into internal memory Because the Xilinx FPGA configuration memory is volatile it must be configured each time it is powered up The bitstream is loaded into the device through special configuration pins These configuration pins serve as the interface for a number of different configuration modes The following configuration modes ate supported e Slave SelectMAP parallel configuration mode x8 e Master Serial Peripheral Interface SPI Flash configuration mode e JTAG Boundaty Scan configuration mode The configuration modes are explained in detail in Chapter 2 Configuration Interfaces of the UG191 Virtex 5 FPGA Configuration User Guide The specific configuration mode is selected by setting the appropriate level on the dedicated Mode input pins M 2 0 The M2 and MO mode pins should be set at a constant DC voltage level either through pull up or pull down resistors or tied directly to ground CONFIG see Figure 14 The mode pins should not be toggled during and after configuration The configuration mode pins can also be driven by the Marvell MV78200 CPU in Slave SeleccMAP mode 2 3 4 Configuration F
64. 5 MPP8 17 AD21 MPP9 17 22 CFPGA M2 MPP10 17 AD22 BUSY MPP11 17 AD15 CFPGA_DONE MPP16 17 M15 CFPGA_INITn MPP17 17 N14 CFPGA_CCLK_18 18 17 N15 CFPGA_RD WRn MPP19 17 N23 CFPGA_CSn MPP20 17 N22 CFPGA_PROGn_CPU MPP21 17 M22 CE CPC Ce e DN DualV6 PCle 4 User Manual www dinigroup com 47 HARDWARE DESCRIPTION 2 3 8 SPI Serial Flash In SPI serial Flash mode 2 0 001 the Virtex 5 FPGA configures itself from an attached industry standard SPI serial Flash 25 128 Voltage translators are used to interface PROM to the Configuration Bank VCCO 1 8V Although SPI is a standard four wire interface various available SPI Flash memories use different read commands and protocol Besides M 2 0 FS 2 0 pins are sampled by the INIT_B rising edge to determine the type of read commands used by SPI Flash see Figure 15 P1 8VD O MPP1 R109 DNI 4 7K R601 47 R110 4 7K R602 DNI 4 7K Figure 15 SPI Variant Select Resistors For Virtex 5 FPGA configurations the default address always starts from 0 Table 13 shows the SPI related configuration pins and the standard connection between the Configuration FPGA and the SPI Flash Table 13 Connection between SPI Flash and the Configuration FPGA Signal Name SPI Fl
65. 5T FPGAs can emulate up to 10 million gates of logic as measuted by a reasonable ASIC gate counting standard This gate count estimate number does not include embedded memories and multipliers resident in each FPGA The DN DualV6 PClIe 4 provides dual Xilinx Virtex 6 FPGAs in the 1156 pin package The architecture of the board maximizes interconnect by providing a number of dedicated busses between the FPGAs The Marvell MV78200 CPU in conjunction with the Configuration FPGA Virtex 5 is used to configure the Virtex 6 FPGAs using the SelectMAP configuration mode The Marvell MV78200 provides a number of high speed interfaces that is available to the user after configuration The PCI Express interface between the Marvell MV78200 and the Configuration FPGA provides a high speed data path to the system interface whether that is USB Ethernet or PCI Express A Linux kernel provides the basic services and device drivers used by all other programs running on the Marvell CPU Numerous clocking options exist to allow for a flexible clocking scheme External memory to the Virtex 6 FPGAs is realized using a 64 bit 204 pin SODIMM that accepts PC3 8500 DDR3 SODIMMs One 400 pin MEG Array connector on the bottom of the printed circuit board assembly PCBA is used to interface to other Dini Group products e g DNMEG_Obs Daughter Card DN DualV6 PCle 4 User Manual www dinigroup com 1 INTRODUCTION 2 DN DualV6 PCle 4 Logic Emulation Board Features
66. 7 HARDWARE DESCRIPTION example part number for a 4GB 512Meg x 64 204 pin SODIMM SDRAM module is MTI16 SE51264HZ7 1G1 3 4 4 DDR3 SDRAM Memory Interface Solution The Virtex 6 FPGA memory interface solutions core is pre engineered controller and physical layer PHY for interfacing Virtex 6 FPGA user designs to DDR2 and DDR3 SDRAM devices The Memory Interface Generator MIG is a self explanatoty wizard tool that can be invoked under the CORE Generator software This section is intended to help in understanding the various steps involved in using the MIG tool Xilinx published a memory application note please refer to UG 406 Virtex 6 FPGA Memory Interface Solutions User Guide 3 4 2 DDR3 Termination These rules apply to termination for DDR3 SDRAM e Unidirectional signals are to be terminated with the memory device s internal termination or a pull up of 5002 to VTT at the load A split 1006 termination to and a 10002 termination to GND can be used but takes more power For bidirectional signals the termination is needed at both ends of the signal DCI ODT external termination VTT 4 gt 500 2 20 TM gt EJ 222 2x 20 gt 1000 Source 28 Load 2 20 1000 77 UG406_ci_58_061 600 e Differential signals should be terminated with the memory device s internal termination or a 10002 differential termination at the load For bidirectional signals termi
67. 78 HARDWARE DESCRIPTION 3 4 8 DDR3 PCB Trace Lengths The DDR3 traces on the DN DualV6 PCle 4 Logic Emulation Board are routed to the following lengths refer to Table 25 Signal Name Table 25 DDR3 PCB Trace Lengths Routed Length mm Description DIMMA_CKON 60 11 Clock group DIMMA_AO 60 05 Control group DIMMA_DQO 70 06 Data byte group DIMMB_CKON 76 03 Clock group DIMMB_AO 76 91 Control group DIMMB_DQO DN DualV6 PCle 4 User Manual 76 00 Data byte group www dinigroup com 79 HARDWARE DESCRIPTION 3 5 SATA Interface on FPGA A and FPGA B Serial ATA 15 a high speed serial link replacement for the parallel ATA attachment of mass storage devices The serial link employed is a high speed differential layer that utilizes gigabit technology and 8b 10b encoding Two SATA II compliant ports one configuted as a HOST and the other as a Device is provided on A and B see Figure 22 Both TX RX signal pairs are differentially routed and AC coupled with 0 1uF capacitors FPGA A GTX 112 J17 022 17 1 mM 112 ABL SATA c C861 O luF SATA A 2 SND gt A SATA SATA NO t APZ CA c C860 CA TY 8116 SATA A C844 0 10
68. 8 CC P2 C21 24 AE34 DCA_B1_N18_CC P2 D22 24 AF34 DCA_B1_P4_CC P2 C11 24 AD29 DCA B1 CC P2 D12 24 AC29 B1 P8 CC P2 C19 24 AE33 N8 CC P2 D20 24 AF33 DC Bank 2 DCA_B2_P12_CC P2 H29 DCA_B2_N12_CC P2 G30 DCA_B2_P18_CC P2 H21 DCA_B2_N18_CC P2 G22 DCA_B2_P3_CC P2 A29 DCA_B2_N3_CC P2 B30 DCA_B2_P8_CC P2 A39 DCA_B2_N8_CC P2 B40 DC Bank 3 DCA_B3_P12_CC P2 K29 24 F31 DCA_B3_N12_CC P2 J30 24 E31 DCA P17 CC P2 K39 24 D34 B3 N17 2 140 24 34 B3 2 29 24 26 B3 N3 CC P2 D30 24 K27 DCA B3 P8 CC 2 39 24 F33 B3 N8 CC P2 D40 24 G33 DC Bank 3 DCA P18 CC P2 E37 24 V28 DCA N18 P2 F37 24 V27 24 N33 24 M33 24 N28 24 N29 24 N32 24 P32 24 L29 24 L30 Ge DN DualV6 PCle 4 User Manual www dinigroup com 102 HARDWARE DESCRIPTION Signal Name DC Header DCA B4 P6 CC P2 E19 DCA B4 N6 CC P2 F19 P7 CC P2 E21 DCA N7 P2 F21 DCA_B4_P8_CC P2 E23 DCA_B4_N8_CC P2 F23 4 7 Not Main Bus Clock dedicated point to point high speed LVDS Not Bus bus is provided between the Configuration FPGA and FPGA A FPGA B respectively A source synchronous clock can be instantiated from any of the signals that connects to a clock capable input 4 7
69. 9 4 Power and Reset The 12V and 3 3V power rails can be supplied by the Daughter Card Headers if the fuses are installed refer to Figure 47 Each pin on the MEG Array connector is rated to tolerate 1 of cutrent without thermal overload DN DualV6 PCle 4 User Manual www dinigroup com 117 HARDWARE DESCRIPTION F8 12V 5A P ZPN FUSE 0429 E1 Al Pi2VFUSED DCA pg23 DCA CLK DN IN P _ 2 5 P 12V 923 DN IN CLK DN 2 5 N 12V E3 peep Ci P RSVD R210 F9 2 5 i DNI pg23 BOA CLK UP QUT PSS CLK_UP_2 5 RSVD_PWR pg23 DCA CLK UP OUT N d CLK UP 2 5 RSVD PWR id RESG1608N FUSE 0429 B2 P3 3VFUSED DCA 3 3V 3 3 G5 42 5V 100 R215 10K PVCCO CAP RSTI RSTn 3 3 TOLERANT JE C167 7 MEG 400 Plug Stratix3 30 84520102LF Figure 47 Daughter Card Header Power amp RESET The RSTn signal is routed from the under voltage reset monitor U77 The signal is used to hold the Veco power supplies inactive until the 2 5V supply is stable in order to meet the Virtex 6 power sequencing requirements see Table 48 Table 48 Daughter VCCO Reset Signal OD Buffer Daughter Card Header U25 5 026 5 U27 5 U28 5 and U66 5 Signal Name RSTn 077 6 9 5 FPGA to Daughter Card Header IO Connections Table 49 lists the input output inte
70. D P1 0V VCCINT V6 R204 10K 8 R203 F 100K V6 OKn P1 0V SNS V6 FAULTn LT6700 2 TSOT23 6 LT6700CS6 24 TRMPBF Figure 42 Low Voltage Comparator Circuit 8 3 3 Power Sequencing Both the Marvell MV78200 CPU and the Virtex 6 FPGAs have power up requirements Please refer to the datasheet for the requirements 8 3 4 Reset Options Refer to Figure 43 for a block diagram of the reset topology FPGA can be reset by the Configuration FPGA as well as the Power On Reset POR circuitry 5 CPUn RST CPU MPP13n RST CFPGA OUTn PERSTn mm RST PORI gt Stn e ST PORn b CPUn xj EA Power On Reset 23 m PWR_FAULTn N RST_CFPGA_PROGn JT_SRSTn ye _ FPGAB_PROGn_RSTn Push Button FPGAA_PROGn_RSTn Reset sm N FPGAA gt FPGAB PROGn 2 Figure 43 Reset Block Diagram DN DualV6 PCle 4 User Manual www dinigroup com 114 HARDWARE DESCRIPTION Reset inputs from various sources drive the TPS3808 07 The 53808 microprocessor supervisory circuit monitors system voltages asserting an open drain RST PORn signal when the SENSE voltage drops below a preset threshold or when the manual reset MRn pin drops to a logic LOW The reset delay time can be set by connecting the CT pin
71. DEV is set to 0 DEV A 1 1 functions as TCLK De skew PLL Tune Setting recommendation will be released after chip tape out NOTE Internally pulled to Ox1 TXDJ 0 TCLK De skewer PLL Frequency Band Functions as TCLK De Skewer PLL Frequency band Select Relevant for De skew mode only A 0 is set to 0 0 166 MHz 1 200MHz NOTE Internally pulled down to 0x0 GEO TXD 1 Reserved R32 NOTE Internally pulled down to 0 1 TXD 3 2 DEV ALE Mode Select 388 R393 0 0 Address 2 ALE 1 TCLK cycle 0 1 Address 3 ALE 2 cycle 0 2 Address 4 ALE 3 TCLK cycle 0 3 Reserved NOTE Internally pulled down to 0x0 1 3 Boot Options The Marvell MV78200 dual CPU implementation assumes that the CPUO boots first completes the proper chip and system configuration settings and then enables CPU1 boot Upon reset de assertion CPUO starts its boot from the DEV_CSn As part of its boot code CPUO sets all the MV78200 configuration registers initializes the DRAM wakes up the PCI Express link and sets the different chip interface address map It also sets the CPU address decoding windows enabling CPU1 to boot from a different boot device CPUO then clears CPU1 s lt CPUReset gt field in the CPU Control and Status Register thereby enabling to start booting Two boot options are provided on the DN DualV6 PCle 4 DN DualV6 PCle 4 User Manual www dinigroup com 32
72. DINI GROUP LOGIC Emulation Source User Manual DN DualV6 PCle 4 LOGIC EMULATION SOURCE DN DualV6 PCle 4 User Manual Version 2 0 Date of Print October 5 2010 O Dini Group 7469 Draper Ave La Jolla CA92037 Phone 858 454 3419 Fax 858 454 1728 support dinigroup com www dinigroup com Copyright Notice and Proprietary Information Copyright 2010 Dini Group rights reserved No part of this copyrighted work may be reproduced modified or distributed in any form or by any means without the prior written permission of the Dini Group Right to Copy Documentation Dini Group permits licensee to make copies of the documentation for its internal use only Each copy shall include all copyrights trademarks disclaimers and proprietary rights notices Disclaimer Dini Group has made reasonable efforts to ensure that the information in this document is accurate and complete However the Dini Group assumes no liability for errors or for any incidental consequential indirect or special damages including without limitation loss of use loss or alteration of data delays or lost profits or savings arising from the use of this document or the product which it accompanies Table of Contents 1150 81109180 o 1 1 DN DUALV6 PCIE 4 LOGIC EMULATION KIT 41 2 DN DUALV6 PCIE 4 LOGIC
73. DN DualV6 PCle 4 User Manual www dinigroup com 108 HARDWARE DESCRIPTION 7 3 Ethernet LEDs The Gigabit Ethernet Single Port MagJacks J3 from Tyco contains two LEDs that are controlled by the Ethernet PHY Table 44 describes the Ethernet LEDs See Marvell 88E1116R Alaska Gigabit Ethernet Transceiver datasheet for more information on driving the LEDs Table 44 Gigabit Ethernet LEDs Signal Name Ethernet PHY PO_LEDO 01 6 13 13 YEL 01 8 13 15 ORN P0 LED2 01 9 13 17 GRN 7 4 Power Supply Status LEDs The LT6700 1 is configured as a simple window comparator to monitor the power supplies Power FAULT will be indicated by the PORn signal going active LOW and turning on the Reset LED 156 The RST_PORn signal can also be activated by enabling the Reset Switch S1 Table 45 describes the power supply status LEDs and their associated voltage source Table 45 Power Supply Status LEDs Signal Name Source Pin P12V J5 1 2 3 DS44 P1 8VD PSU4 2 3 DS41 P2 5VD PSU5 5 DS37 P3 3VD PSU2 2 3 DS38 P5 0V PSU8 2 3 Not Monitored P1 0VD CPU CORE PSU1 2 3 15536 P1 1VD CPU PSU3 2 3 0535 P1 0V VCCINT V5 PSU9 5 9 DS43 P1 0V_VCCINT_V6 PSU7 5 9 DS42 P_DIMM_A PSU11 5 9 DS39 P DIMM B PSU5 5 9 DS40 USBO OCn U29 5 DS1 DN DualV6 PCle 4 User Manual www dinigroup com 109 HARDWARE DESCRIPTION 7 5 USB Fault LED The AP2171 is an integrated
74. EE CER TC2804 1 880P16 C206 C200 LTC2804CGN 1 PBF 1uF 16V 16 10 10 CER CER Figure 36 MCU Configuration FPGA Serial Port There are two signals attached to the Configuration FPGA Transmit Data 5232 TX e Receive Data RS232 CFPGA TX and RX provide bi directional transmission of transmit and receive data No hardware handshaking is supported Note Signals from the unused LVDS Bus QA 1 4 P N 0 19 between the Configuration FPGA and FPGA may be used to implement a RS232 port on 5 1 2 Connections between RS232 Port and the Configuration FPGA CPU The connections between the Configuration FPGA CPU and the RS232 Port are shown in Table 40 Table 40 Connections between RS232 Port and the Configuration FPGA CPU RS232 Port U30 14 U30 16 U30 3 U30 1 CPU Header U4 AC24 U4 AD24 112 723 Signal Name 5232 MCU TX 5232 MCU RS232 TXD1 RS232 RXD1 Signal Name RS232 Port Configuration RS232 CFPGA TX 30 13 U17 K23 RS232 CFPGA RX 30 15 U17 K22 RS232 TXD2 DN DualV6 PCle 4 User Manual 30 4 www dinigroup com 16 2 105 HARDWARE DESCRIPTION Signal Name RS232 Port CPU Header RS232_RXD2 U30 2 16 3 Signal Name Configuration FPGA A FPGA U17 W24 U17 V24 6 Temperature Sensors The MAX1617A is a precise digital thermometer that reports the temperature of both a
75. EMULATION BOARD FEATURES 22 3 PACKAGE CONTENTS 3 5 4 INSPECT THE BOARD 5 risen SERES 6 5 ADDITIONAL INFORMATION 6 GETTING STARTED X X 7 1 BEFORE YOU 7 1 1 Configuring the Programmable Components 27 1 2 sentido 7 2 INSTALLING THE SOFTWARE 2 1 Exploring the Customer Support Package 3 IO PIDE mE 3 1 Before Powering Up the Board 3 2 Powering Up the Board 4 RUNNING THE FIELD TEST PROGRAMMING CONFIGURING THE HARDWARE eeeeeee eese tatnen sata sata snos essais tatnen enn 12 1 EET e EU EUN RPM 12 EMU GRAPHICAT USER INTERFACE 13 3 CONFIGURING THE VIRTEX 6 FPGAS USING 14 3 1 Before Powering Up the Board sss 5215 3 2 Powering Up the us zu 4 CONFIGURING THE VIRTEX 6 FPGAS USING JTAG 4 1 Setup Configuring the Virtex 6 FPGAS Usine JTAG
76. F25 U22 AL34 U17 K28 U22 AM33 U17 N27 U22 AJ31 U17 M28 U22 AL31 U17 H25 U22 AK33 2 4 3 High Speed Interconnect GTP to FPGA A B Two high speed serial channels are provided between the Configuration FPGA and FPGA A B This could be used for pin multiplexing 10x pin per LVDS pair The GTP transceiver is highly configurable and tightly integrated with the programmable logic resources of the FPGA It provides the following features to support a wide variety of applications Current Mode Logic CML serial drivers buffers with configurable termination voltage swing and coupling e Programmable TX pre emphasis and RX equalization for optimized signal integrity e Line rates from 100 Mb s to 3 75 Gb s with optional 5x digital oversampling required for rates between 100 Mb s and 500 Mb s e Optional built in PCS features such as 8B 10B encoding comma alignment channel bonding and clock correction e Fixed latency modes for minimized deterministic datapath latency e Beacon signaling for PCI Express designs and Out of Band signaling including e COM signal support for SATA designs The Xilinx CORE Generator tool includes a Wizard to automatically configure GTP transceivers to support one of various protocols or perform custom configuration see UG 198 Virtex 5 RocketlO GTX Transceiver User Guide GTP transceivers are placed as dual transceiver DUAL tiles in Virtex 5 LXT and SXT Platform devices This configur
77. GAs using JTAG using the Xilinx Platform Cable USB and JTAG e Updating the Marvell MV78200 Software lists the procedure to update the Marvell MV78200 software Virtex 6 FPGAs are configured by loading application specific configuration data the bitstream into internal memory Because the Xilinx FPGA configuration memory is volatile it must be configured each time it is powered up The bitstream is loaded into the device through special configuration pins These configuration pins serve as the interface for a number of different configuration modes The following configuration modes are supported e Slave SelectMAP parallel configuration mode x8 e JTAG Boundaty Scan configuration mode DN DualV6 PCle 4 User Manual www dinigroup com 12 PROGRAMMING CONFIGURING THE HARDWARE The configuration modes are explained in detail in Chapter 2 Configuration Interfaces of the UG360 Virtex 6 FPGA Configuration User Guide The specific configuration mode is selected by setting the appropriate level on the dedicated Mode input pins M 2 0 In Slave Selecc MAP mode FPGA and FPGA B are independently configured from the Configuration 2 EMU Graphical User Interface GUI 18 both an end user application for interacting with Dini Group hardware as well as a development kit for extending EMU s capabilities or writing custom applications EMU is designed to interface with any Dini Group board that comes with the Ma
78. INT H33SNVHI ONAS 310019 BAN 5 V1 VG ONAS 5 9190581 50758591 z x XAN Et 9911 1896 10 2 1461 10 1 9 114502 85r WWIGOS WWIGOS 8 49 NNO INI 244 MN yer NNOO LNI vivs hi9 WII v NNOO 1NI hte ez Fab god 10 19 ee 22 vilia NNOO1NI 1 ie bpe RE wi aasnuon Lyann hre NNOO INI aasnion 19 se sz 51 aoa SV NNOO INI awna 02 jorj 196 92 1 LOL NNOO INI 99t WWIGOS V ININIGOS duno vedo SELLJJ LS8X 14 SOX 15 1 8 3 LZE NNO INI 1 hio SEN anw ved vamas hr pt ptt We osw 6 aavnas 08 vouNnoo 61 NNOO ud 950 9IJNOO
79. LVDS Not Bus NMB bus is provided between the Configuration FPGA and FPGA A and FPGA B respectively DN DualV6 PCle 4 User Manual www dinigroup com 49 HARDWARE DESCRIPTION NMBO configFPGA User FEAT NMB1 User NMBx User FPGA X 15 a 10 bit bus 9 data 1 source synchronous clock in each direction with a maximum operating speed of 1 Gbps per signal for a total of 9 Gbps in each direction full duplex See Figure 17 for the between the Configuration and A 01740 U22 14 2 QAOPO J9 QAOP7 lO LOP 5 13 y33 QAON lO LOP GC 34 Hg QAON7 IO LON SMBN 13 10 GC 34 aig GAOPO lO LIP SM P 13 OANT lO GC 34 Big lO LIN SM N 13 5y33 QA0P2 10 LIN GC 34 Fg QAOP6 IO L2P SM6P 13 IO L2P A15 D31 34 bets GR NE IO L2N SMeN 13 A334 OPE L2N A14 D30 34 10 L3P SMSP 13 Onne IO L3P A3 D29 34 Hpo IO L3N 8 13 2 GA0P3 10 48 13 10 LAN VREF 18 Hacs OMP 5 13 ap34 IO 8 13 acas GAOPS L6P 5 13 OAUNS
80. O OCn UA R262 475R wi If TMA LED RED Silkscreen USB FAULT J2 P5 0V_VBUSO 1 USB D USB DT R259 USB DH no 2 VBU USB D p USB DT po R258 OR 3 p 4 GND SHIO 05 SH 1 P5 0V_VBUSO 676433910 2 vN HB 084 vcn H 1 NUP2201MR6TIG TSOP6 NUP2201MR6T1G Figure 8 USB2 0 Port 0 Host Type A The AP2171 offer current 1 5 and thermal limiting and short circuit protection as well as controlled rise time and under voltage lockout functionality 1 7 Gigabit Ethernet Interface The Gigabit Ethernet Port GbE includes an IEEE802 3 compliant 10 100 1000Mb MAC The Alaska 88E1116R U1 Gigabit Ethernet Transceiver is a physical layer device PHY between the Marvell MV78200 and the Ethernet connector J3 The 88E111R device supports the Reduced pin count for RGMII for direct connection to the Matvell 78200 Ge0 Rxdo e0 Rx P1 8VF PHY AVDD wed RST_CPU IKS E 10 PRESET TRST4 Ge0 Pel 4 STOMA 4 7K Ge0_XTAL_IN 38 RSET XTAL IN TL 60 7 9 XTAL_OUT HSDACP P HSDACN P ca 18 GeO NCT 28 NCIO 15 15 NG 1 TSTP P 8811 16R OFNG4 R273 R264 88E1116RA0 NNC1C000 4 7K OR P1 8VF_PHY_AVDD Ge0 TRSTh R267 4 99K
81. OCK GENERATION een E 4 1 Clock Methodology site oec 4 2 Clock Multipliers eu pred a areae ep t EC e peu n Op a n pee o Tee OR 4 2 1 General Clock Multiplier U10 GO ET 4 2 2 Connections between the FPGAs and Clock Multipliers 92 43 Global Clocks from 93 4 3 1 Multiplexed Global Clock Circuit E 4 3 2 Connection between FPGA and the Clock Multiplexer 94 PGLExpress Reference CIOCKS storre aie eere 94 4 4 1 PCI Express Reference Clock Circuit esse 495 4 4 2 Connection between CPU CF FPGA and the PCIe Reference Clock Buffer 54 95 4 5 GTP Clock LVDS Oscillators and Buffers 95 4 5 1 GTP Clock Oscillator Configuration FPGA and FPGA 96 4 5 2 Connection between GTP Clock Buffers and the 97 4 5 3 GTP Clock Oscillator FPGA and FPGA B P 4 5 4 Connection between GTP Clock Buffer and FPGA 98 4 5 5 Clock Oscillators pp e deti teet e vU D ertet 98 4 5 6 Connection between SATA II Clock Oscillators and the FPGAs 98 4 6 Daughter Card DC Header Clocks 99 4 6 1 Daughter Card Global Clock Input Output
82. PGA M 2 0 Select Resistors The specific configuration mode is selected setting the appropriate level on the dedicated Mode input pins M 2 0 configuration pins P1 8VD R596 4 7K 18597 0 277 Figure 14 Configuration FPGA M 2 0 Select Resistors default Slave Select MAP Select the configuration scheme by driving the Configuration FPGA M 2 0 pins either HIGH or LOW as shown in Table 11 Table 11 Configuration FPGA Configuration Schemes DN DualV6 PCle 4 User Manual www dinigroup com 46 HARDWARE DESCRIPTION Configuration Mode Configuration Resistors Slave Select MAP R579 R604 R597 Installed Master SPI R582 R605 R579 Installed JTAG R579 R606 R596 Installed 2 3 2 SelectMAP via Marvell CPU The Marvell MPP bus is connected to the SelectMAP interface on the Configuration FPGA The SelectMAP configuration interface provides an 8 bit bidirectional data bus interface to the Virtex 5 configuration logic that can be used for both configuration and readback CCLK is an input to the Configuration FPGA in Slave SelectMAP mode Table 12 shows the MPP bus connection between the Marvel CPU and the Configuration FPGA Table 12 SelectMAP Bus between Marvell 78200 CPU and Configuration FPGA Signal Name Configuration FPGA DO 17 AD19 D1 MPP1 17 AE19 D2 MPP2 17 AE17 D3 MPP3 17 16 D4 4 17 AD20 D5 MPP5 17 AE21 D6 MPP6 17 AE16 D7 MPP7 17 AF1
83. RIPTION P2 5VD R705 4 7K R706 DNI 4 7K 719 4 7 FPGAB 2 8716 DNEATK Figure 18 FPGA M 2 0 Select Resistors default Slave Select MAP Select the configuration scheme by driving the Configuration FPGA M 2 0 pins either HIGH or LOW as shown in Table 19 Table 19 FPGA Configuration Schemes Configuration Mode Configuration Resistors FPGA A Slave SelectMAP R690 R693 R688 Installed JTAG R690 R692 R689 Installed FPGA B Slave SelectMAP R719 R705 R707 Installed JTAG R719 R706 R708 Installed 3 3 2 SelectMAP via Configuration FPGA The Configuration FPGA U17 is connected to the SelectMAP interface on FPGA A U22 and FPGA B U24 with a dedicated 8 bit bidirectional data bus This allows for faster data transfer and independent FPGA configuration during configuration or readback CCLK is an input in Slave SelectMAP mode Table 20 shows the SelectMAP bus connection between the Configuration FPGA and FPGA A B Table 20 SelectMAP Bus between Configuration FPGA and FPGA A B Signal Name Configuration FPGA FPGA A B FPGAA DO U17 L4 22 AF24 FPGAA_D1 U17 P5 22 AF25 FPGAA_D2 U17 N5 22 W24 FPGAA D3 U17 L6 22 24 U U U FPGAA D4 17 M7 22 H24 FPGAA D5 17 N7 17 N8 FPGAA_D6 DN DualV6 PCle 4 User Manual www dinigroup com 65 HARDWARE DESCRIPTION Signal Name Configuration FPGA A B
84. Test Custom Auto Update Board Interface DNO199_DNOUALVEPCIE4 1004030 Ethernet CLOCKS 500 002 Synthesizer Gl 400 012 Synthesizer G2 200 007 Synthesizer Clear Save Text FullScreen Auto Scroll ONESHOT FIELD TEST COMPLETE temperature_test PASS clock_field_test PASS cpu_eeprom_test PASS nnb blockram test PASS dram test 1 PASS single intercon test 55 rocketio field test PASS single intercon fast 55 urn pull test PASS 1945 intercon test PASS HHH HHH FIELD TEST REP 1 1 PASSED DN8199 DNDURLUGPCIE 1664636 12 18 12 6 15 2018 JEJE DN DualV6 PCle 4 User Manual www dinigroup com 11 PROGRAMMING CONFIGURING THE HARDWARE Chapter Programming Configuring the Hardware This chapter details the programming and configuration instructions for the DIN DudlV6 PCle4 Xilinx Virtes 6 Logi Emulation Board 1 Introduction This section of the User Manual presents different methods to configure the Xilinx Virtex 6 FPGAs Configuring the Virtex 6 FPGAs using EMU using the Graphical User Interface GUI e Configuring the Virtex 6 FP
85. acle Bottom FPGA REST 24 02 DN DualV6 PCle 4 User Manual www dinigroup com 121 HARDWARE DESCRIPTION RECEN 4 SIGNAL Receptacle Bottom FPGA noi ugs I nga IT ngo M 22 am DN DualV6 PCle 4 User Manual www dinigroup com 122 HARDWARE DESCRIPTION 2 8 SIGNAL Receptacle Bottom FPGA DCA B3 P2 DCA B3 P3 CC DCA B3 P4 P5 B3 P6 DCA B3 P7 B3 P8 CC DCA B3 p9 DCA B4 DCA B4 N10 DCA B4 N11 VREF N13 B4 N14 DCA N15 DCA N16 N17 B4 N18 CC DCA B4 N2 DCA B4 N4 DCA B4 N5 N6 CC DCA B4 N12 DN DualV6 PCle 4 User Manual www dinigroup com 24 32 24 K26 24 131 24 G32 24 33 24 32 24 F33 24 30 24 26 24 V25 24 T31 24 Y34 24 834 24 29 24 25 24 U32 24 U27 24 V29 24 V27 24 Y29 24 Y31 24 32 24 27 24 N 30 123 HARDWARE DESCRIPTION Daughter Card SIGNAL Receptacle Bottom FPGA 9 6 Insertion Removal of Daughter Card 24 W34 24 U30 24 T34 24 W27 24 W25 24 T30 24 Y33 24 R33 24 T28 24 U25 24 U33 24 U26 24 U28 24 V28 24 N 29 24 Y32 24 331 24 Y28 24 V30 24 V34 24 U31 24 133 24 J24 24 125 24 V23 24 U23 24 F23 24 F24 Due to the high density MEG Array connectors the pins on the plug and receptacle of the MEG Array connectors are delicate W
86. al Pins on the Daughter Card Header 9 3 1 DN 2 5p n UP 2 5p n The daughter pin out defines two bidirectional differential clock pins These clock signals are intended to be used as differential clock signals These signals are routed to clock capable inputs on the 6 and can be used for global clocking 9 3 2 Vccio Power Supply On the Virtex 6 FPGA each IO bank has its own pins is determined by the IO standatd for that particular IO bank Since a daughter card will not always be present on a daughter card connector a Veco bias generator is used on the motherboard for each daughter card bank to keep the Veco pin on the FPGA within its recommended operating range The Daughter Card drives to the required level for the particular IO standard The Veco impressed by the Daughter Card needs to satisfy the Vis the FPGA on the host board There are five Adjustable Linear Power Supplies U25 1726 028 U66 and 027 on the board one per daughter card header IO bank refer to Figure 46 Refer to the datasheet for the LT1963A from Linear Technology on how to adjust the output voltages R782 allows the user to remove the powers supply if a Veco of 2 5V is required since that voltage can be supplied by the system LT1963AES8 SO8 LT1963AES8 5 pg20 21 RSTn Figure 46 Vcco Adjustable Linear Power Supply x5
87. al clock connections for global clocks power connections bank Veco power and a reset signal 9 1 Daughter Card clocking Refer to Daughter Card DC Header Clocks par 4 6 in this User Manual 9 2 Daughter Card Header Pin Assignments The pin assignments of the daughter card header are designed to reduce cross talk to manageable levels while operating at full speed of the Virtex 6 LVDS standards The daughter card header is divided into five banks refer to Figure 45 The Virtex 6 devices support source synchronous interfacing with LVDS signaling at up to 1 6Gbps The ground to signal ratio of the connector is 1 1 refer to Figure 45 General purpose IO is arranged in a GSGS pattern to allow high speed single ended or differential use These signals are routed as loosely coupled differential signals meaning when used differentially they benefit from the noise resistant properties of a differential pair but when used in a single ended configuration they do not interfere with each other excessively DN DualV6 PCle 4 User Manual www dinigroup com 115 HARDWARE DESCRIPTION ABCODEF GH J K 1 1 2 2 B 4 4 5 B B 5 Clock outputs 6 6 Power 720 8 8 9 9 vrer BM Clock 5 Figure 45 Daughter Card Header Bank Pin Assignments DN DualV6 PCle 4 User Manual www dinigroup com 116 HARDWARE DESCRIPTION 9 3 Speci
88. al www dinigroup com 80 HARDWARE DESCRIPTION Signal Name SATA B RxP1 SATA B RxN1 3 6 3 6 1 Interconnect FPGA A High speed LVDS IO Bus to FPGA B Four high speed LVDS IO Banks connected between the A and FPGA B Table 27 shows the connection between the FPGA A and FPGA B Table 27 High speed LVDS IO Bus between FPGA A and FPGA B FPGA B Signal Name ABONO ABON1 ABON10 ABON11 ABON12 ABON13 ABON14 ABON15 ABON16 ABON17 ABON18 ABON19 ABON2 ABON3 ABON4 5 ABONG ABON7 8 9 ABOP1 ABOP10 DN DualV6 PCle 4 User Manual FPGA A 22 A31 22 D30 22 F26 22 D26 22 C25 22 G25 22 E24 22 B28 22 D29 22 A25 22 E28 22 H29 22 29 22 29 22 C27 22 A26 22 B30 22 E27 22 G28 22 G27 22 B31 22 C30 22 E26 Ge se Ci pcc www dinigroup com cia c eL Eg c 24 AH32 24 AD26 24 31 24 AK31 24 4 24 133 24 AM32 24 AP33 24 AE26 24 AN34 24 AG30 24 AG28 24 AF29 24 AH30 24 2 24 AD27 24 AE29 24 AJ32 24 AJ30 24 AH33 24 AD25 24 AL30 81 HARDWARE DESCRIPTION Signal Name ABOP11 12 13 14 15 16 17 18 19 2 ABOP3 5 ABOP6 ABOP7 8 ABOP9 AB1NO 1 1 1 10 1 11 1 12 1
89. are ensure the following steps have been completed 1 Attach an ATX Power Supply to the PCIE PWR header J5 on the DN DUALV6 PCIE 4 Logic Emulation Board DN DualV6 PCle 4 User Manual www dinigroup com 19 PROGRAMMING CONFIGURING THE HARDWARE 2 Connect the Ethernet Cable to the ETHERNET header J3 on the DN DUALV6 PCIE 4 Logic Emulation Board Note In order to be able to access the board over the network the network must support DHCP 5 2 Powering Up the Board 3 Power up the board by turning ON the ATX power supply and verify the 12V LED 0544 is ON indicating the presence of 12V located at the right side of the PCB 5 3 Open Serial Terminal Session Access to the board is allowed via a Serial Terminal Session 4 Connect the RS232 Serial Cable to the RS232 CPU header J1 on the DN DUALV6 PCIE 4 Logic Emulation Board Configure the session as follows Session Options Serial COM1 Category Connection Serial Options EM Port COMI m Flow Control 4 Terminal Baud rate 19200 918 258 Emulation RTS CTS Modes Data bits 8 Emacs Mapped Keys Advanced Stop bits v Appearance Window NUT EET Log File Serialbreaklength 100 milliseconds Printing i Advanced Parity v 5 4 Verify Linux Kernel Version 5 Power DN DUALV6 PCIE 4 Lo
90. ash Configuration SPI FLASH 18 U48 15 U17 AF14 SPI FLASH 18 U48 7 U17 AF14 18 U48 16 U17 N15 D IN 18 U48 8 U17 P15 2 3 4 JTAG Virtex 5 devices support IEEE standards 1149 1 and 1532 IEEE 1532 is a standard for In System Configuration ISC based on the IEEE 1149 1 standard JTAG 15 an acronym for the Joint Test Action Group the technical subcommittee initially responsible for developing the standard This standard provides a means to ensure the board level integrity of individual components and the interconnections between them The IEEE 1149 1 Test Access Port and Boundary Scan Architecture is commonly referred to as JTAG JTAG connector J12 used to download the configuration files to the Configuration FPGA see Figure 16 DN DualV6 PCle 4 User Manual www dinigroup com 48 HARDWARE DESCRIPTION R627 1K JTAG Figure 16 Configuration FPGA JTAG Interface Table 14 shows the connection between the header and the Configuration JTAG Table 14 Connection between JTAG Header and Configuration FPGA Signal Name Configuration Connector FPGA JTAG_CFPGA_TCK U17 AB5 12 6 JTAG CFPGA TDI U17 AC15 12 10 JTAG_CFPGA_TDO_F U17 AD14 7128 JTAG TMS U17 AC14 J124 2 4 Interconnect Configuration FPGA to FPGA 2 4 1 Not Main dedicated point to point high speed
91. ation allows two transceivers to share a single PLL with the TX and RX functions of both reducing size and power consumption Table 18 shows the connection between the Configuration FPGA and FPGA A B In line AC Coupling capacitors are provided for DC isolation from the Transmitter Table 18 High Speed Serial connection between the Configuration FPGA and FPGA A B DN DualV6 PCle 4 User Manual www dinigroup com 60 HARDWARE DESCRIPTION Signal Name Configuration FPGA A B FPGA 17 AK2 17 AL2 17 AL1 17 AM1 17 AN4 17 AN3 17 AP3 17 AP2 HS CF A TXPO HS A HS A HS CF A HS CF A HS A HS CF _ 1 HS RXN1 HS CF B TXPO HS CF B TXNO HS CF B RXPO HS CF B RXNO HS B HS CF B HS B RXP1 HS B 22 63 22 04 22 D1 22 D2 22 E3 22 E4 22 C3 22 aq ae el aeiac al e area ea lay Ge aya 1 3 FPGA AB Virtex 6 3 1 Overview The Virtex 6 family provides the newest most advanced features in the market Virtex 6 FPGAs are the programmable silicon foundation for Targeted Design Platforms that deliver integrated software and hardware components to enable designers to focus on innovation as soon as their development cycle begins Using the third generation ASMBL Advanced Silicon Modular Bloc
92. ators SATA X10 4 U22 AK6 CLK SATA AN X10 5 U22 AK5 SATA SATA BN The oscillator power supply U57 U62 is filtered to reduce power supply noise and jitter Please see the LV7745DW 150 0M datasheet for more information 4 6 Daughter Card DC Header Clocks A single daughter card header is provided on the DN DualV6 PCle 4 Logic Emulation Board The 400 pin MEG Array connector P2 on the bottom of the PCBA is used to interface to Dini Group products e g DNMEG_AD DA The daughter card header provides a dedicated global LVDS input clock from daughter card connected capable pins on FPGA B and a dedicated global LVDS output clock input to daughter card In addition each IO bank provides a source synchronous LVDS clock that connects to FPGA B 4 6 1 Daughter Card Global Clock Input Output DN IN P N is a global LVDS input clock to FPGA B IO Bank 24 and UP OUT P N is a global LVDS output clock from the FPGA IO Bank 24 see Figure 32 Note These signals are routed as differential pairs LVDS and are NOT AC coupled Refer to the Virtex 6 Data Sheet for IO levels and provide DC isolation on the daughter card if required 5A Pi2V PLUG N FUSE 0429 PI2VFUSED DCA 1 23 DCA CLK DN IN P E CLK_DN_2 5 P E 923 ININ CLK DN 2 5 N lt tev PT P_RSVD
93. ble with voltages in the range of 3V to 15V for logical 1 and 3V to 15 for logical 0 This ensures data bits ate read correctly even at maximum cable lengths between DTE and DCE specified as 50 feet The RS 232 standard has two primary modes of operation Data Terminal Equipment DTE and Data Communication Equipment DCE These can be thought of as host or PC for DTE and as peripheral for DCE The DN DualV6 PCle 4 operates in the DCE mode only DN DualV6 PCle 4 User Manual www dinigroup com 104 HARDWARE DESCRIPTION 5 1 1 RS232 Circuit Diagram Figure 36 shows the implementation of the serial port on the DN DualV6 PCle 4 Logic Emulation Board CPU Ji 1 2 x i 4 x 5 6 7 8 2 8 30x RS232 MCU TX 14 3 RS232 TXD1 136 01 0 CFPGA HE232 DD pg4 RS232 CFPGA TX 2 13 T2IN TeouT 4 16 1 RS232 RXD1 1 8232 CFPGA AX 15 3 Rs232 2 9 Ri Configuration FPGA pg4 RS232 CFPGA 2222 Se 2 R20UT R2IN DNI OR 6 5 12 LCD 1 2 P1 8VD wee CE P1 8VD 3 4 8 12 cage 5 8 3 R263 47K 5232 ON RSes2 SW 45V 7 8 3 10 5232 C207 _0 22 10uH C198 DNI OR e CAP PM1812 100J RC 5 136 01 0 6 RS232 VDD 16V 8 von Tg 5232 VEE 0 GND V
94. d so the wrong connectors will have difficulty fitting propetly into the boatd Figure 40 ATX Power Supply 8 2 1 External Power Connector Figure 41 indicates the connections to the external power connector This header is fully polarized to prevent reverse connection and is rated for 600V AC at 6A per contact An overvoltage crowbar circuit utilizing a Diode D1 is provided to protect the 12V supply DN DualV6 PCle 4 User Manual www dinigroup com 112 HARDWARE DESCRIPTION 45558 0002 D1 45558 0002 PDS1040 13 Note Reverse polarity protection 47uF 0 1uF 16V 16V 2096 1096 Figure 41 External Power Connection Note Header J5 is not hot plug able Do not attach power while power supply is ON 8 3 Voltage Monitors and Reset 8 3 1 Voltage Monitor The LT6700 1 is configured as a simple window comparator to monitor the power supplies A power fault will be indicated by the PWR_FAULTn signal going active LOW See 7 4 Power Supply Status LEDs for a description of the power supplies being monitored 8 3 2 Voltage Monitor Circuit The comparators have a built in 400mV reference and each one have one input available externally see Figure 42 The comparators ate configured as a simple window comparator to detect high low voltage thresholds DN DualV6 PCle 4 User Manual www dinigroup com 113 HARDWARE DESCRIPTION P12V R240 P1 0V LED V6 0542 X LED RE
95. ed by a brief description of each section DN DualV6 PCle 4 User Manual www dinigroup com 24 HARDWARE DESCRIPTION 18 2 weibeig 420 9 Burd jojo4d DISV 9 KouenbeJ peonpei e pepue ejBuis pesn mm OE inq paed 50 1 9 HSV14 1008 9199 vs fet x2 PRPS ozasn 45 O028ZAMW II9 18IN Tm 0001 00101 V1VS v5d4 108 1 LS XOMA 951144 10 1X1 1961 X1 951144 10 1X1 1S61X1 10v2X1 1s95X1 1098 1 189 1 o V9d4 veda fo 1 isiexs 1szexs et 191 6 1829 5 25 9 XoUlA 949 9 XLD 94 V V9dd av ZHN 586 01 95 899 WWIGOS 1 005 Figure 4 DN DualV6 PCle 4 Logic Emulation Board Block Diagram The DN DualV6 PCle 4 is hosted in 4 lane PCI Express GENI system but can used stand alone and is configured via USB or Ethernet The FPGA configuration and other miscellaneous board functions are controlled by the Marvell MV78200 CPU single DN DualV6 PClIe 4 configured with two Xilinx Virtex 6 5 475 FPGAs can emulate up to 10 million gates of logic as measured by a reasonable ASIC gate counting 25 www dinigroup com DN DualV6 PCle 4 User Manual HARDWARE DESCRIPTION standard This gate count estimate number does not
96. ed point to point using dedicated differential LVDS traces The arrival times of the clock edges at each FPGA are phase aligned length matched on the PCB within about 100ps These clocks are all suitable for synchronous communication among FPGAs The connections between the FPGAs and the Clock Multipliers are shown in Table 30 Table 30 Connections between FPGAs and Clock Multipliers Signal Name Clock Buffer FPGA General Clock Multiplier CLK G0 AN AP BN BP G0 CFPGAN CLK CFPGAP TN TP DDR2 Clock Multiplier CLK_G1_AN 9 13 9 14 9 11 9 12 9 9 9 10 9 15 9 16 22 M22 22 L23 24 M22 24 L23 17 AG13 17 AH12 TP19 2 TP19 1 U U U U U U CH Ce EC GIC U22 K23 DN DualV6 PCle 4 User Manual www dinigroup com 92 HARDWARE DESCRIPTION Signal Name Clock Buffer FPGA G1 AP U15 14 U22 K24 G1 BN U15 11 U24 K23 G1 BP U15 12 U24 K24 U U CLK G1 CFPGAN U15 9 17 AH19 CLK G1 CFPGAP U15 10 17 AH20 CLK G1 TN U15 15 25 2 CLK G1 TP U15 16 25 1 LVDS Clock Multiplier G2 G2 AN CLK G2 AP G2 BN 19 11 CLK G2 BP 19 12 CLK G2 CFPGAN U19 9 17 AH13 G2 U19 10 17 AH14 CLK G2 TN U19 15 29 2 G2 TP U19 16 TP29 1 19 13 19 14 22 11 22 D11 24
97. eration The primary source of power for the DN DualV6 PCle 4 is the PCI Express graphics power connector J5 All other voltages on the board are generated from this supply During In System operation the DN DualV6 PCle 4 can be powered from the PCI Express Edge Connector however the board will exceed the available power from the system fuse F12 needs to be installed for this option to be available see Figure 39 P12V P12V_PEX0 P12V F12 DNI 7A TLLA PEX PRSNTn R22 PEX PRSNTh4 PRSNTI 819 DNEOR Mie ae P3 3VD GND ND PEXO_LED_A sce ero P3 3V GND LED RED 22 3 3 TMS a8 13 P3 SVAUX VAUX TSSVAUX 2534 i I 33 33 WAKE PERST Au 8200 AA RST CPUN lt C RST CPUn pgi2 N 2 Ai2 RSVD GND CLK PEXD eruit n REFCLK m REFCLK m PEND LATE TpOc C44 Q iuF T PEX PRSNTn1 T PERRO Ai7 A18 GND GND 218 4 PEOR PET aX 21 PEND Lagi PEXO T pt GND PERCH A22 rT nic C45 PER RS GND AN 8 PONO 2825 T p2c C48 0 142 T p2 8
98. esis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components The DSPLL loop bandwidth is digitally programmable providing jitter performance optimization at the application level Please refer to the Any rate Precision Clocks 515316 512322 512323 525325 515326 515365 512366 515367 512368 Family Reference Manual from Silicon Laboratories for the 515326 for programming information 4 2 1 General Clock Multiplier U10 CLK GO One of the outputs of the Clock Multiplier U10 is buffered U9 and distributed as general reference clock for the FPGAs while the other output is connected to the CKIN2 input on the DDR3 CLK Multiplier 016 The clock multiplier 010 can use either oscillator X1 or clock output signals multiplexed as a reference input The clock multiplier U10 must be programmed via the interface Signal Note Three clock multipliers 010 U16 and U20 are on the chain driven from the Configuration FPGA U17 DN DualV6 PCle 4 User Manual www dinigroup com 91 HARDWARE DESCRIPTION SYNTH G0 1 2n are provided to reset the clock multiplier Figure 26 shows one of the clock multiplier circuits LED 057 is used to indicate f k PLL Loss of Lock P2
99. ess Add in Card Form factor One bus bar MP1 is installed to prevent flexing of the PWB The mounting holes are connected to the ground plane and can be used to ground test equipment The user must not short any powet rails or signals to these metal they can conduct a lot of current Mounting holes are provided to allow the PCB to be mounted in a case 2 TR 1 7 imkis in Ehl d K 2 e 1 312mm T WE ME DN DualV6 PCle 4 User Manual www dinigroup com 127 HARDWARE DESCRIPTION 10 2 Standard Daughter Card Size The DN DualV6 PCle 4 Logic Emulation Board provides mounting hole locations for a Daughter Card with the dimensions given below The DNMEG Obs Daughter Card product conforms to these dimensions View Top Side 400 Pin Receptacle on Back 74390 101 1 4 10 3 Daughter Card Spacing With this host plate daughter card arrangement there is a limited Z dimension clearance for backside components on the daughter card This dimension is determined by the daughter card designer s part selection for the receptacle DN DualV6 PCle 4 User Manual www dinigroup com 128 HARDWARE DESCRIPTION MOTHERBOARD Note that the components on the topside
100. features include power optimized high speed serial transceiver blocks for enhanced serial connectivity PCI Express compliant integrated Endpoint blocks tri mode Ethernet MACs Media Access Controllers and high performance PowerPC 440 microprocessor embedded blocks These features allow advanced logic designers to build the highest levels of performance and functionality into their FPGA based systems Built on a 65 nm state of the art copper process technology Virtex 5 FPGAs are a programmable alternative to custom ASIC technology Most advanced system designs require the programmable strength of FPGAs Virtex 5 FPGAs offer the best solution for addressing the needs of high performance logic designers high performance DSP designers and high performance embedded systems designers with unprecedented logic DSP hard soft microprocessor and connectivity capabilities The Virtex 5 LXT SXT TXT and FXT platforms include advanced high speed serial connectivity and link transaction layer capability For more information please reference the Xilinx Virtex 5 literature DN DualV6 PCle 4 User Manual www dinigroup com 43 HARDWARE DESCRIPTION 2 2 Summary of Virtex 5 FPGA Features Five platforms LX LXT SXT TXT and FXT o Virtex 5 LX High performance general logic applications o 5 LXT High performance logic with advanced serial connectivity o Virtex 5 SXT High performance signal processing applications with advanced serial
101. figuration FPGAA FPGA QAOP19 2 5 7 U17 AC34 22 9 QAOP8 U17 AG33 U22 AD10 QAOP9 U17 AG32 U22 AD9 Table 16 shows the connection between the Configuration FPGA and FPGA B Table 16 Connections between the Configuration FPGA and FPGA B Configuration FPGA B FPGA 17 T34 24 AP9 17 R34 24 AL8 17 D32 24 B10 17 D34 24 D10 17 A33 24 D9 17 H32 24 AE9 17 H33 24 AL9 17 J34 24 F10 17 N32 24 K9 17 031 24 AB10 17 K34 24 M10 1792 17 R32 24 8 17 N34 24 AF10 17 C33 24 AP10 17 M33 24 AC9 17 M32 24 H9 c c Ci ili TT Ci Ci DN DualV6 PCle 4 User Manual www dinigroup com 52 HARDWARE DESCRIPTION Signal Name Configuration FPGA B FPGA QBON7 17 E33 24 E9 24 A8 24 C8 24 AN9 ARS AADS U17 U17 U QBONS U17 F34 9 U17 E34 QBOPO U17 U33 U CELO erc GIG 17 DAD 17 1 18 U17 L34 24 L10 19 U17 K33 24 AH9 2 4 2 Fast Bus Optional The unused IO Banks on the Configuration FPGA labeled as Fast Bus LVDS is connected between the Configuration FPGA and FPGA A This interface is available to the User although the Dini Group has no specific purpose for this bus Table 17 shows the connection between the Configuration FPGA and FPGA A Ci Table 17 Fast Bus connections between the Configura
102. g o High speed memory interface support Advanced DSP48E slices 25 18 two s complement multiplication o Optional adder subtracter and accumulator Optional pipelining o Optional bitwise logical functionality o Dedicated cascade connections e Flexible configuration options o SPI and Parallel FLASH interface o Multi bitstream support with dedicated fallback reconfiguration logic Auto bus width detection capability e System Monitoring capability on all devices o On chip Off chip thermal monitoring On chip Off chip power supply monitoring JTAG access to all monitored quantities e Integrated Endpoint blocks for PCI Express Designs LXT SXT TXT and FXT Platforms o Compliant with the PCI Express Base Specification 1 1 o xl x4 or x8 lane support per block o Works in conjunction with RocketIO transceivers e Tri mode 10 100 1000 Mb s Ethernet MACs LXT SXT TXT and FXT Platforms RocketIO transceivers can be used as PHY or connect to external PHY using many soft MII Media Independent Interface options RocketIO GTP transceivers 100 Mb s to 3 75 Gb s LXT and SXT Platforms RocketIO GTX transceivers 150 Mb s to 6 5 Gb s e TXT and FXT Platforms e PowerPC 440 Microprocessors o EXT Platform only RISC architecture 7 stage pipeline 32 Kbyte instruction and data caches included Optimized interface structure crossbar DN DualV6 PCle 4 User Manual www dinigroup com
103. g web page has an excellent tutorial on the Fundamentals of ESD for those of you who are new to ESD sensitive products http www esda org basics part1 DN DualV6 PCle 4 User Manual www dinigroup com 7 GETTING STARTED e Operating Temperature Avoid touching the PTH012050WAZ power supply modules PSU6 and PSU10 as they operate at high temperatures and may cause skin burns 2 Installing the Software For complete information regarding the Host Software GUI and installation instructions see the EMU Software Manual available on the Customer Support Package USB Flash Drive 2 1 Exploring the Customer Support Package The USB Flash Drive contains the following items see Figure 2 Daughtercards Documentation FPGA Reference Designs Host Software Figure 2 USB Flash Drive Directory Structure A description of the USB Flash Drive directory contents is listed in Table 1 Please visit the Dini Group website for the most recent revision of these documents Table 1 USB Flash Drive Directory Contents USB Flash Drive Directory Contents Directory Name Description of Contents Daughtercatds Complete documentation on the DNMEG Intercon and the DNMEG Obs Daughter Cards Documentation Contains the Datasheets Schematics and User Manual for the boatd FPGA Reference Designs Contains the source and compiled programmi
104. gic Emulation Board and monitor the power up events in the CRT window Note Shortly after power up check the Linux Kernel version as shown in the Created date DN DualV6 PCle 4 User Manual www dinigroup com 20 PROGRAMMING CONFIGURING THE HARDWARE Serial COM1 not connected CRT le Edit Options Transfer Script Tools n545353523 9 Seria COM1 DPALMER Current Bar Sizes DPALMER Bar 0 15 00000000 DPALMER Bar 1 is 00380001 DPALMER Bar 2 15 00380001 DPALMER mvPexHalInit is runnin PEX 4 interface detected no Link Copying Environment from 000 CPU 0 ARM926 Rev 0 Streaming enabled write allocate disabled FPU initialized to Run Fast Mode UsB 0 host mode USB 1 host mode UsB 2 device mode dpalmer save val 00020104 egigad PRIME egigal egiga2 egiga3 Hit an ey to stop autoboo 0 Starting kernel Uncompressing Linux boo g the kernel Linux version 2 6 22 18 root amp golden boot dinigroup com gcc version 4 2 1 269 Thu Jun 3 11 45 1 2 PDT 2010 CPU 926 2 5 41159260 revision 0 5 cr 00053977 Machine 78 0 Using UBoot passing parameters structure Memory policy ECC disabled Data cache writeback BUG not creating mapping for 0 00000000 at 0 00000000 in user region not creating mapping for 0 00000000 at 0 00000000 in user region not creating mapping for 0 00000000 at 0 000000
105. group com 16 PROGRAMMING CONFIGURING THE HARDWARE File Board FPGA Clocks Temps Data Test Custom Auto Update Board Interface Refresh DNO199_DNDUALV6PCIE4 1004030 Ethernet CLOCKS 00 500 014 Clear Save Text Full Screen Auto Scroll Running Sanity Check Sanity Check passed Sending File FPGA A CONFIGURED WITH D dncus FPGA bitfiles dn6199_dndualu _pcie4 user_fpga MAINTEST SX475T fpga_A bit 10 Verify that the FPPGAA DONE blue LED 0522 for FPGA A is enabled indicating successful configuration of the 4 Configuring the Virtex 6 FPGAs using JTAG This section lists detailed instructions for programming the Xilinx Virtex 6 FPGAs using iMPACT Version 11 1 tools Before configuring the FPGA ensure that the Xilinx software and the Xilinx Platform Cable USB driver software ate installed on the host computer The JIAG Boundaty Scan configuration interface is always available regardless of the Mode pin settings The JTAG Boundaty Scan configuration mode disables all other configuration modes to prevent conflicts between configuration interfaces Note This User Manual will not be updated for every revision of the Xilinx ISE tools so please be aware of minor differences 4 1 Setup Configuring the Virtex 6 FPGAs using JTAG Before configuring the FPGA ensure the following steps have been completed DN DualV6 PCle 4 User Manual www dinigroup com 17
106. hen plugging in a daughter catd make DN DualV6 PCle 4 User Manual www dinigroup com 124 HARDWARE DESCRIPTION sure to align the daughter card first before pressing on the connector Be absolutely certain that both the small and the large keys at the narrow ends of the MEG Array headers line up BEFORE applying pressure to mate the connectors DN DualV6 PCle 4 User Manual www dinigroup com 125 HARDWARE DESCRIPTION 9 7 MEG Array Specifications Manufacturer Part Number RoHS Compatible Total Number Of Positions Lead Free Contact Area Plating Mating Force Unmating Force Insulation Resistance Withstanding Voltage Current Rating Contact Resistance Temperature Range Trademark Approvals and Certification Product Specification Pick up Cap Housing Material Contact Matertal Durability Mating Cycles DN DualV6 PCle 4 User Manual FCI 84520 102LF Bottom Plug P4 P5 P6 yes 400 0 76 um 30 uin gold over 0 76 um 30 uin nickel 30 grams per contact average 20 grams per contact average 1000 M ohms 200 VAC 0 45 amps 20 to 25 m ohms max initial 10 m ohms max increase after testing 40 C to 85 C MEG Array UL and CSA approved GSe 12 100 from FCI websit yes LCP Copper Alloy 50 www dinigroup com 126 HARDWARE DESCRIPTION 10 Mechanical 10 1 Board Dimensions The DN DualV6 PCIe 4 Logic Emulation Board conforms to the Standard Height PCI Expr
107. high side power switch optimized for Universal Serial Bus USB and other hot swap applications The device complies with USB 2 0 and offer current and thermal limiting including short circuit protection as well as controlled rise time and under voltage lockout functionality 7ms deglitch capability on the open drain Flag output prevents false over cutrent reporting and will turn on LED DS1 during an over current condition see Table 46 Table 46 USB Fault LED Signal Name Source Pin LED 00580 OCn U29 5 1551 7 6 Miscellaneous LEDs Table 47 describes the miscellaneous status LEDs and their associated soutce Table 47 Miscellaneous LEDs Signal Name Marvell 780200 CPU U4 RST_CPU_MPP13n SATA1_Act SATAO_Act U Clock Multipliers LOL Indicators SYNTH LOL U SYNTH LOL G1 U SYNTH_LOL_G2 U Front Panel LED LED_BICLR_RED 8 Power Distribution The DN DualV6 PCle 4 Logic Emulation Board supports a wide range of technologies from legacy devices like serial ports to DDR3 SDRAM Ethernet Transceivers and Transceivers on the Xilinx FPGAs This wide range of technologies including the various FPGA power supplies requires a variety of power supplies These are provided on the DN DualV6 PCle 4 Logic Emulation Board using a combination of switching and linear power regulators DN DualV6 PCle 4 User Manual www dinigroup com 110 HARDWARE DESCRIPTION 8 1 In System Op
108. i x H pg23 FPGAB OUTn FPGAB OUTh 9 CLK MUX 14 J8 13 CLK2p 1 CLK Ten 121 VT 2 CLK2n P2 5VD CLK MUX CLK3 3 R347 AA 47K CLK3p te ND LK CLK3n 90120 0123 G R346 47K CLK KARN FPGA CLKO 6 923 FPGA CLKO 55 MUX FPGA 5 SELO pg23 FPGA CLK1 SEL1 10 1 GND VDD T T 11 20 1 56 52 GND VDD 2 2uF 2 2uF 1 5854057 550 20 6 3 63v ICS854057AGLF Figure 35 External Multiplexed Clocks 4 8 2 Connection between External Clock Header and the Clock Multiplexer The connection between External Clock Header and the Clock Multiplexer are shown in Table 39 Table 39 Connection between External Clock Header and Clock Multiplexer Signal Name FPGA A B Clock MUX 4 1 FPGAA OUTp U22 M23 U6 2 OUTn 1722 124 U6 4 FPGAB OUTp U27 F24 U6 7 OUTn U27 F23 U6 9 MUX TPp 1841 06 14 TPn 18 2 06 12 CLKO U17 T10 U6 6 CLK1 U17 T11 U6 5 5 RS232 Port An 232 serial port J1 J6 is provided for low speed communication with the Marvell MV78200 and the Configuration FPGA The RS 232 standard specifies output voltage levels between 5V to 15V for logical 1 and 5V to 15V for logical 0 Input must be compati
109. ible configuration options SPI and Parallel Flash interface o Multi bitstream support with dedicated fallback reconfiguration logic Automatic bus width detection e System Monitor capability on all devices On chip off chip thermal and supply voltage monitoring JTAG access to all monitored quantities e Integrated interface blocks for PCI Express designs o Designed to the PCI Express Base Specification 2 0 o Gent 2 5 Gb s and Gen2 5 Gb s support with GTX transceivers o Endpoint and Root Port capable o xl x2 x4 or x8 lane support pet block GTX transceivers 150 Mb s to 6 5 Gb s GTH transceivers 2 488 Gb s to beyond 11 Gb s e Integrated 10 100 1000 Mb s Ethernet MAC block o Supports 1000BASE X PCS PMA and SGMII using GTX transceivers o Supports and RGMII using SelectIO technology resources DN DualV6 PCle 4 User Manual www dinigroup com 63 HARDWARE DESCRIPTION 2500 suppott available 40 nm copper CMOS process technology 10 core voltage 1 2 3 speed grades only Lower power 0 9V core voltage option 1L speed grade only e High signal integrity flip chip packaging available in standard or Pb free package options 3 3 FPGA Configuration Virtex 6 Virtex 6 FPGAs are configured by loading application specific configuration data the bitstream into internal memory Because the Xilinx FPGA configuration memory is volatile it must be configured each time it is powered up The bi
110. include embedded memories and multipliers resident in each FPGA One hundred percent 100 of the Virtex 6 FPGA resources are available to the user The DN DualV6 PCIe 4 provides dual Xilinx Virtex 6 FPGAs in the 1156 pin package The architecture of the board maximizes interconnect by providing a number of dedicated busses between the FPGAs see Figure 4 The Marvell MV78200 CPU in conjunction with the Configuration FPGA Virtex 5 is used to configure FPGA A B Virtex 6 using the SeleccMAP configuration mode JTAG configuration using the Xilinx Platform Cable USB download cable is provided as an alternate method of configuration and provides an interface to ChipScope and other third party debug tools The Marvell MV78200 provides a number of high speed interfaces that are available to the user after configuration The PCI Express interface between the Marvell 78200 and the Configuration FPGA provides a high speed data path to the system interface whether that is USB Ethernet or PCI Express Numerous clocking options exist to allow for a flexible clocking scheme Three highly configurable clock multipliers 515326 provide global clock networks External memory to the Virtex 6 FPGAs is realized using 64 bit 204 pin SODIMM that accepts PC3 8500 DDR3 SODIMMs One 400 pin MEG Array connector on the bottom of the printed circuit board assembly PCBA is used to interface to other Dini Group products e g DNMEG Obs Daughter Card In sta
111. ing Refer to the PCI Express Reference Clocks section of this manual 1 6 USB Interface The Marvell MV78200 integrates three USB2 0 compliant ports including integrated PHYs Each USB 2 0 interface contains a single dual role controller that can act as a host a peripheral controller USBO 12 is configured a Host used during Stand alone configuration with a USB Flash Drive USB2 14 is configured as a Device and is used during Stand alone configuration to interface the EMU GUI The USB ports have a dedicated for data transfer between memory and port The USB signals ate routed as differential traces and connect to the Marvell MV78200 via common mode filters 11 2 see Table 7 Table 7 USB Interconnect Signal Name CPU USB D U4 AE13 USB D n0 U4 AF13 USB D p2 U4 AB13 USB D n2 U4 AC13 DN DualV6 PCle 4 User Manual www dinigroup com 38 HARDWARE DESCRIPTION The NUP2201MR6 D4 D5 transient voltage suppressors ate designed to protect the high speed data lines from ESD The 2171 029 is an integrated high side power switches optimized for Universal Serial Bus USB and other hot swap applications P5 0V P5 0V R261 9 4 7K 5 0 VBUSO U29 2 P5 0V VBUSO 3 Tene R242 0 1 10uF VBUSOEN 4 iev 6 3V jd 109 C193 47K i CER CER 0 1uF P5 0V 16V AP2171 SOP8L 051 10 AP2171SG 13 USB
112. is hosted via Ethernet USB PCI Express For the purpose of this example the Ethernet interface will be demonstrated Note The Configuration FPGA must be configured in order to drive the FPGA and FPGA B CSI 0 chips select signals Note This User Manual will not be updated fot every revision of the EMU software application so please be aware of minor differences DN DualV6 PCle 4 User Manual www dinigroup com 14 PROGRAMMING CONFIGURING THE HARDWARE 3 1 Before Powering Up the Board Before powering up the board prepare the board as follows 1 Attach ATX Power Supply to the PCIE PWR header J5 on the DN DUALV6 PCIE 4 Logic Emulation Board 2 Connect the Ethernet Cable to the ETHERNET header J3 on DN DUALV6 PCIE 4 Logic Emulation Board Note In order to be able to access the board over the network the network must support DHCP 3 If the kit contains Memory SODIMMs populate the SODIMM sockets Insert a DDR3 SDRAM SODIMM module into positions J14 J21 P N MTS8JSF12864HZ 1G4F1 Note Ensure voltage jumper JP2 JP3 is set to 1 5V pin 3 1 4 Install the EMU graphical user interfaces software available on the Customer Support Package USB Flash Drive Note Reference the Software Manual regarding driver installation 3 2 Powering Up the Board 5 Power up the board by turning ON the ATX power supply and verify the 12 LED 0544 is ON indicating the presence
113. ite allocate disabled FPU initialized to Run Fast Mode USB 0 host mode USB 1 host mode UsB 2 device mode Serial 1 50 14 SORows 99 Cols VT100 7 Enter the following command at the prompt dini_uboot gt gt protect off 1 0 63 8 Bootinto Linux by entering the following command dini_uboot gt gt boot 9 Once the boot procedure completes enter the following command sh 3 2 mount t tmpfs mnt ram o size 32M 10 Enter the following command at the prompt sh 3 2 cd mnt ram 11 Download the update files from the Dini Group website Place these files on the board see directory above Alternatively if the board is connected to an internet enabled network use the wget command DN DualV6 PCle 4 User Manual www dinigroup com 22 PROGRAMMING CONFIGURING THE HARDWARE 12 13 5 6 sh 3 2 wget http dinigroup com marvellfiles ulmage Note If you do not have access to the internet then you will need to use some other method to transfer files to the board You can use a USB key a network mount or any other linux trick you know Enter the following command at the prompt sh 3 2 cat ulmage gt dev pattition spi Note This command updates the Linux kernel If this command fails the recovety procedure is still possible but is more complicated Enter the following command at the prompt sh sh 3 2 reboot Note It is important to execute the reboot command and not power cycling
114. k column based architecture the Virtex 6 family contains multiple distinct sub families This overview covers the devices in the LXT SXT and HXT sub families Each sub family contains a different ratio of features to most efficiently address the needs of a wide variety of advanced logic designs In addition to the high performance logic fabric Virtex 6 FPGAs contain many built in system level blocks These features allow logic designers to build the highest levels of performance and functionality into their FPGA based systems Built on a 40 nm state of the art copper process technology Virtex 6 FPGAs are a programmable alternative to custom ASIC technology Virtex 6 FPGAs offer the best solution for addressing the needs of high performance logic designers high performance DSP designers and high performance embedded systems designers with unprecedented logic DSP connectivity and soft microprocessor capabilities For more information please reference the Xilinx Virtex 6 documentation DN DualV6 PCle 4 User Manual www dinigroup com 61 HARDWARE DESCRIPTION 3 2 Summary of Virtex 6 FPGA Features e Three sub families o Virtex 6 LXT FPGAs High performance logic with advanced serial connectivity o Virtex 6 SXT FPGAs Highest signal processing capability with advanced serial connectivity o Virtex 6 HXT FPGAs Highest bandwidth serial connectivity e Compatibility across sub families o LXT and SXT devices are footprint compatible i
115. n the same package e Advanced high performance FPGA Logic o Real 6 input look up table LUT technology o Dual LUTS 5 input LUT option o LUT dual flip flop pair for applications requiring rich register mix o Improved routing efficiency 64 bit or 32 x 2 bit distributed LUT RAM option o SRL32 dual SRL16 with registered outputs option e Powerful mixed mode clock managers MMCM o MMCM blocks provide zero delay buffering frequency synthesis clock phase shifting input jitter filtering and phase matched clock division e 36 Kb block RAM FIFOs Dual port RAM blocks o Programmable o Dual port widths up to 36 bits o Simple dual port widths up to 72 bits o Enhanced programmable FIFO logic Built in optional error correction circuitry o Optionally use each block as two independent 18 Kb blocks e High performance parallel SelectIO technology 12 25 1 operation DN DualV6 PCle 4 User Manual www dinigroup com 62 HARDWARE DESCRIPTION Source synchronous interfacing using o ChipSync technology o Digitally controlled impedance active termination o Flexible fine grained I O banking o High speed memory interface support with integrated write leveling capability e Advanced DSP48E1 slices 25 18 two s complement multiplier accumulator Optional pipelining o New optional pre adder to assist filtering applications o Optional bitwise logic functionality o Dedicated cascade connections e Flex
116. nation is needed at both ends of the signal DCI ODT or external termination DN DualV6 PCle 4 User Manual www dinigroup com 68 HARDWARE DESCRIPTION 3 4 3 20 Source P Load P gt 2 X 20 gt 1000 Source N Ba Load N 9406 c1 59 081609 All termination must be placed as close to the load as possible The termination can be placed before or after the load provided that the termination is placed within a small distance of the load pin The allowable distance can be determined by simulation DCI can be used at the FPGA as long as the DCI rules such as VRN VRP are followed The RESET and CKE signals are not terminated These signals should be pulled down during memory initialization with 4 7 kQ resistor connected to GND ODT which terminates a signal at the memory and DCI which terminates a signal at the FPGA are required The MIG tool should be used to specify the configuration of the memory system for setting the mode register propetly Refer to Micron technical note TN 47 01 for additional details on ODT ODT applies to the DQ DQS and DM signals only If ODT is used the mode register must be set appropriately to enable ODT at the memory Voo Switching Power Supply P DIMM x The Texas Instruments PTH12050 POLA DC DC Converter is used to create the supply for the DDR3 SDRAM SODIMM set to 1 5V 6A see Figure 20 A jumper JP2 allows the user to change the voltage to the SODIMM and the FPGA
117. nd select Board followed by Select Board select the DN0199 DNDUALVG6PCIEA xxxxxxx 192 168 2 199 Ethernet board in the drop down list that matches the serial number of your board DN DualV6 PCle 4 User Manual www dinigroup com 9 GETTING STARTED Selection Requested Select Board DNO199_DNDUALV6PCIE4 1004030 192 168 2 199 Ethernet 7 Verify that the board was correctly identified as a DN0199 DNDUALVG6PCIEA xxxxxxx in the window Note The serial number will be different File Board FPGA Clocks Temps Data Test Custom Auto Update Board Interface Refresh DNO199_DNDUALV6PCIE4 1004030 Ethernet CLOCKS 100 002 Synthesizer Gl 100 004 Synthesizer G2 200 005 Synthesizer Clear Save Text FullScreen Auto Scroll DISCONNECTED CONNECTED TO BOARD DN6199_DNDUALUGPCIES 1884838 Ethernet 4 Running the Field Test Select Test followed by Field Test The progress of the tests will be displayed in the EMU log window The following tests will be executed e temperature test e clock field test cpu test DN DualV6 PCle 4 User Manual www dinigroup com 10 GETTING STARTED e nmb blockram test e dram test e single intercon test rocketio field test single intercon fast pull test e vds intercon test Verify that the all the Field tests PASSED File Board FPGA Clocks Temps Data
118. ndalone mode the DN DualV6 PCle 4 receives power from an external 12V power supply An RS232 interface exists to allow communication with the application LEDs are used to indicate configuration status power supply presence and numerous LEDs are provided for the user 1 Marvell MV78200 CPU 1 1 Overview The Marvell MV78200 is a dual core high performance low power highly integrated processor with Marvell s Sheeva ARMv5TE compliant CPU core Built on Marvell s innovative Discovery system controller platform the MV78200 is a complete system on chip SoC solution Optimized for low power operation the MV78200 is ideally suited to a wide range of applications ranging from sophisticated routers switches and wireless base stations to high volume laser printers applications The MV78200 offers unparalleled integration that makes system design simple and cost efficient The SoC integrates e High performance dual issue CPU with Vector Floating Point VFP support e 800 MHz and 1 Ghz operating speed DN DualV6 PCle 4 User Manual www dinigroup com 26 HARDWARE DESCRIPTION 32KB Instruction and 32KB Data 4 way set associative L1 cache core e 512KB unified 8 way set associative L2 cache per core e 40 72 bit high bandwidth DDR2 memory interface up to 800 MHz data rate Four Gigabit Ethernet MACs with interface options Two PCI Express ports x4 or Quad x1 e Three USB 2 0 ports with integrated PHYs
119. ndication The target TWSI slave responds with an acknowledge etc In addition to the RTC the CPU Temperature Monitor U37 and an EEPROM 032 is connected to the TWSI1 bus please see schematic for more information 1 11 Temperature Monitor The 1617 15 a precise digital thermometer that reports the temperature of both a remote sensor and its own package The remote sensor is a diode connected transistor typically a low cost easily mounted 2N3904 NPN type that replaces conventional thermistors or thermocouples Remote accuracy is 3 C for multiple transistor manufacturers with no calibration needed The remote channel can also measure the die temperature of other ICs such as microprocessors that contain an on chip diode connected transistor The Marvell 79200 is connected to a temperature sensor 037 via the TWSI1 serial bus This sensor measures is mapped to address Ox4Ch see Figure 12 The maximum recommended operating temperature of the CPU is 85 degrees When the CPU measures the temperature above 80 degrees it will immediately RESET the CPU DN DualV6 PCle 4 User Manual www dinigroup com 41 HARDWARE DESCRIPTION P3 3VD P3 3VD P1 8VD R294 R302 R303 4 7K 47K lt 4 7K U37 C294 TEMP STBY C 3 CPU TEMP STBY DX CPU TEMP TWSM SCK TWSH 8 DXN 503 TWSH SDAT 503 EE 6554 CPU TEMP IN NC MPP23 R297
120. ng files for the DN DUALV6 DN DualV6 PCle 4 User Manual www dinigroup com 8 GETTING STARTED PCIE 4 reference designs Host Softwate Provides the Host Software for the Windows and Linux platforms including the EMU Software Manual 3 Board Setup The instructions in this section explain how to install the DN DUALV6 PCIE 4 Logic Emulation Board For the purpose of this demonstration the DN DUALV6 PCIE 4 will be configured in Stand Alone mode 3 1 Before Powering Up the Board Before powering up the board prepare the board as follows 1 Attach an ATX Power Supply to the PCIE PWR header 15 on the DN DUALV6 PCIE 4 Logic Emulation Board Connect the Ethernet Cable to the ETHERNET header J3 on DN DUALV6 PCIE 4 Logic Emulation Board If the kit contains Memory SODIMMs populate the SODIMM sockets Insert a DDR3 SDRAM SODIMM module into positions J14 J21 P N MTS8JSF12864HZ 1G4F1 Note Ensure voltage jumper JP2 JP3 is set to 1 5V pin 3 1 Install the graphical user interfaces software available on the Customer Support Package USB Flash Drive Note Reference the EMU Software Manual regarding driver installation 3 2 Powering Up the Board 5 Power up the board by turning ON the ATX power supply and verify the 12V LED 0544 is ON indicating the presence of 12V located at the right side of the PCB Open the EMU application a
121. nnected to the PCI Express Fingers see Table 5 Table 5 PCI Express Port 0 Interconnect Signal Name PCI Express Edge Connector P1 A16 P1 A17 P1 A21 P1 A22 P1 A25 P1 A26 P1 A29 P1 A30 P1 B14 P1 B15 P1 B19 P1 B20 P1 B23 P1 B24 P1 B27 P1 B28 PEXO T PO PEXO T NO PEXO T P1 PEXO T N1 PEXO T P2 PEXO T N2 PEXO T P3 PEXO T N3 PEXO R PO PEXO R PEXO R P1 R N1 PEXO R P2 R N2 PEXO P3 PEXO R N3 1 5 2 PCI Express Port 1 PCI Express Port 1 is always a Root Complex PEX1 T R p 0 3 is routed as differential LVDS traces AC coupled and connected to the Configuration FPGA see Table 6 Table 6 PCI Express Port 1 Interconnect Signal Name CPU Configuration PEX1 T PO U4 AE10 U17 G1 DN DualV6 PCle 4 User Manual www dinigroup com 37 HARDWARE DESCRIPTION Signal Name Configuration FPGA PEX1 T 17 H1 PEXI T P1 17 K1 PEX1 T N1 17 1 PEXI T 2 17 N1 T N2 17 P1 T P3 17 T1 PEX1 T 17 R1 17 2 1 R 17 62 17 12 PEX1 R 17 K2 PEXI R P2 17 M2 N2 17 N2 R P3 17 U2 PEX1 R N3 17 12 C IH ER CLER 1 5 3 PCI Express Clock
122. of 12V located at the right side of the PCB 6 Open the application and select Board followed by Select Board select the DN0199 DNDUALVG6PCIEA xxxxxxx 192 168 2 199 Ethernet board in the drop down list that matches the serial number of your board Selection Requested Select Board DN0199 DNDUALVePCIE4 1004030 192 168 2 199 Ethernet 7 Verify that board was correctly identified as DN0199 DNDUALV6PCIF4 xxxxxxx in the window Note The serial number will be different DN DualV6 PCle 4 User Manual www dinigroup com 15 PROGRAMMING CONFIGURING THE HARDWARE File Board FPGA Clocks Temps Data Test Custom Auto Update Board Interface DNO199_DNDUALVEPCIE4 1004030 Ethernet CLOCKS 100 002 Synthesizer Gl 100 004 Synthesizer G2 200 005 Synthesizer Group Clear save ret Fullscreen Auto Scroll 71 DISCONNECTED CONNECTED TO BOARD DN6199_DNDUALUGPCIE4S 1884038 Ethernet 8 Right click on the FPGA to be configured and assign the required bitfile Enter Bitfile for FPGA A XC6VSX475T Look in 3 Sx475T er Be R fpga_A bit fpga B bit My Recent Documents My Network File name z Places Files of type All Files 9 EMU will perform a sanity check on the bit file and configure the DN DualV6 PCle 4 User Manual www dini
123. or Figure 32 Daughter Card Global Clock Input Output Figure 33 Daughter Card Header Feedback Clock Figure 34 Secondary Daughter Card DC Header Clock Figure 35 External Multiplexed Clocks Figure 36 MCU Configuration FPGA Serial Port Figure 37 Temperature Sensor FPGA A Figure 38 LED Indicator Figure 39 PCI Express Edge Connecto Figure 40 ATX Power Supply Figure 41 External Power Connection Figure 42 Low Voltage Comparator Circu Figure 43 Reset Block Diagram Figure 44 Reset Circuit Figure 45 Daughter Card Header Bank Pin Assignments Figure 46 Adjustable Linear Power Supply 5 Figure 47 Daughter Card Header Power amp RESET y for A B List of Tables D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D let USB Plash Drive Directory 8 e 2 Reset Strapping Options e 3 SPI Flash Programming Interface le 4 NAND Flash Device Bus Interface e 5 PCI Express Port 0 Interconnect e 6 PCI Express Port 1 Interconnec e 7 USB Interconnect 8 SATA II CPU Interconnect e 9 Connection between Marvell MV78200 and Temperature Sensor e 10 CPU TAG connection to the Marvell MV 78200 1 Configuration FPGA
124. ovided on the board see Table 3 Table 3 SPI Flash Programming Interface Signal Name SPI Flash SPI Flash Header SPI CLK 041 16 22 5 SPI CSn U41 7 J22 1 SPI DO U41 15 J22 3 SPI DI U41 8 J22 2 DN DualV6 PCle 4 User Manual www dinigroup com 33 HARDWARE DESCRIPTION 1 3 2 Booting from NAND Flash Device Bus AD 24 23 0 2 selects the Boot from CE don t care NAND Flash on the Marvell MV78200 CPU The Marvell MV78200 CPU supports booting from Flash when the fist block is placed on 00h block address and is guaranteed to be a valid block with no errors see MV S800598 00C Functional Specifications for more information The NAND02G B2C 011 Flash is a non volatile Flash memory that uses NAND cell technology see Figure 6 The device is 2 Gbits and operates from a 1 8V voltage supply The size of a Page is 2112 Bytes 2048 64 spare and is configured as an x8 bus width The address lines are multiplexed with the Data Input Output signals on a multiplexed x8 Input Output bus This interface reduces the pin count and makes it possible to migrate to other densities without changing the footprint m lt lt lt lt lt lt lt lt o gggggggo NC O0 NC 1 NC 2 NC 3 NC 4 DEV WEnO NC 5 WPn AO NC 7 DEV Ai P NC 8 9 NC 10 NF_BUSY NC 12 NC 13 NC 14 NC 15 NC 16 NC 17
125. pulled to 0 0 D 30 Nand flash initialization command 0 Append command 0x30 1 Do not append command 0x30 NOTE Internally pulled to 0 0 DEV D 31 VDDO_C Voltage Select 0 1 8V 1 3 3 NOTE Internally pulled down to 0 1 DEV ALE 0 VDDO Voltage Select 0 1 8 1 3 3 NOTE Internally pulled up to 0 1 DEV ALE 1 VDDO D Voltage Select 0 1 8V 1 33 NOTE Internally pulled up to Ox1 WEn 0 GE Voltage Select 0 1 8V 1 3 3 NOTE Internally pulled up to 0 0 WEn 1 WEn and DEV_OEn multiplexing option for A 16 15 bits 0 A 16 15 bits are not multiplexed on OE and WE signals 1 A 16 15 bits are multiplexed on OE and WE signals NOTE Internally pulled down to 0 0 DEV WEnp2 Reserved ATE NOTE Internally pulled down to 0 0 DEV WEn 3 Reserved IW NOTE Internally pulled down to 0 0 DEV A 0 TCLK Mode Select 0 TCLK is driven from IN input 1 TCLK generated internally by TCLK PLL NOTE Internally pulled up to Ox1 DN DualV6 PCle 4 User Manual www dinigroup com 31 HARDWARE DESCRIPTION Configuration Mode Configuration Resistors Installed Not Installed DEV 2 1 TCLK frequency select TCLK De skew PLL Tune R65 R56 R452 R439 If DEV A 0 is set to 1 DEV_A 2 1 functions as TCLK frequency select 0x0 166MHz 0 1 200MHz Ox2 0x3 Reserved If
126. ration FPGA Table 4 NAND Flash Device Bus Interface Signal Name NAND Flash CPU DEV DO 11 H4 4 U25 DEV 1 11 4 4 U26 DEV D2 11 K4 4 T24 DEV D3 11 K5 4 126 DEV D4 11 K6 4 R21 DEV D5 11 7 4 R22 DEV D6 11 K7 4 R23 DEV D7 11 8 4 R24 DEV_OEn 11 D4 4 21 NF CEn 11 C6 4 U21 DEV_WEn0 11 C7 4 AA23 11 C3 ull up R66 DEV A0 11 D5 4 U22 DEV A1 11 4 23 NF BUSY 11 C8 LED 058 ien CIGI a GIG GIG 1 4 CPU Memory DDR2 The Marvell MV78200 CPU interface to four DDR2 SDRAM 128M x 16 devices a 64 bit bus M DQ 63 0 see Figure 7 The DDR2 SDRAM MT47H128M16HG uses a double data rate architecture to achieve high speed operation The double data rate architecture is essentialy a 4n prefetch architecture with an interface designed to transfer two data wotds per clock cycle at the I O balls A single read or write access for the DDR2 SDRAM effectively consists of a single 4n bit wide one clock cycle data transfer at the internal DRAM core and four corresponding n bit wide one half clock cycle data transfers at the I O balls A bidirectional data strobe DQS DQS is DN DualV6 PCle 4 User Manual www dinigroup com 35 HARDWARE DESCRIPTION transmitted externally along with data for use in data capture at the receiver DOS is a strobe transmitted by the DDR2 SDRAM during
127. rconnect between the Virtex 6 FPGA and the Daughter Card header Table 49 FPGA to Daughter Card Header IO Connections Daughter Card SIGNAL Receptacle Bottom FPGA DN DualV6 PCle 4 User Manual 24 AH24 24 AK24 24 AN24 24 AP29 24 AP26 24 AJ27 24 AM28 24 AK28 24 AM30 24 AH28 24 AK29 www dinigroup com 118 HARDWARE DESCRIPTION 1 229 SIGNAL Receptacle Bottom FPGA NEED AR TIE DCA N9 OUT P11 P12 CC 14 15 P16 17 DCA P2 CC P5 P6 P7 P8 P9 B1 B1 B1 N10 VREF DCA B1 N11 VREF DCA B1 N12 DCA B1 N13 CC P3 DN DualV6 PCle 4 User Manual P2 A7 P2 A9 www dinigroup com 24 AP31 24 AH23 24 AJ24 24 AN25 24 AN29 24 AP27 24 AK27 24 AN28 24 28 24 30 24 27 24 129 24 23 24 25 24 25 24 AG25 24 126 24 27 24 AP30 24 AC27 24 32 24 2 24 AB33 24 AB31 24 AC30 119 HARDWARE DESCRIPTION 4 SIGNAL Receptacle Bottom FPGA EXE EYE DADA DADE ADR ADH DAA DEAN ADD DN DualV6 PCle 4 User Manual www dinigroup com 120 HARDWARE DESCRIPTION RECEN SIGNAL Recept
128. rvell processor see Figure 3 EMU compiles into both a command line menu system program CMD version and a graphical interface program GUI version supporting all functionality in both versions EMU supports Windows and Linux platforms using the QT windowing package for cross platform support of native GUI interfaces QT is freely available from the internet and is required for the GUI versions of EMU It is recommended to use the QT environment in EMU development but the CMD version can be built without it using other standard environments such as GCC and MSVC DN DualV6 PCle 4 User Manual www dinigroup com 13 PROGRAMMING CONFIGURING THE HARDWARE File Board FPGA Clocks Temps Data Test Custom Auto Update Board Interface Refresh DNO199_DNDUALV6PCIE4 1004030 Ethernet CLOCKS GO 500 040 Clear Save Text Fullscreen Auto Scroll Melcome to Emu Figure 3 EMU Graphical User Interface For more information regarding please reference Software Manual available on the Customer Support Package USB Flash Drive 3 Configuring the Virtex 6 FPGAs using EMU This section lists detailed instructions for programming the Xilinx Virtex 6 FPGAs using EMU software application Before configuring the FPGAs ensure that the EMU software and the driver software are installed on the host computer The procedure for configuting the FPGAs 15 the same whether the board
129. s given below IBUFGDS 8 DIFF TERM TRUE IBUFGi ibufg I CLK_GOP IB CLK_GON The pin assignment in the UCF file NET CLK_GON loc M22 NET CLK_GOP loc 123 All global clock networks have a differential test point terminated by a 100R resistor used to measure clock frequency e g TP19 The positive side of the differential signal is connected to pin 1 square and the negative side is connected to pin 2 circular of the test point DN DualV6 PCle 4 User Manual www dinigroup com 89 HARDWARE DESCRIPTION 3701 06574 uid 00 Log auvo INO 995 08 SO Nid LINONT 800 9911 199 6 L LOELXTASOX 2505 2 280 esovo 803 2509 08 11 ZHINSZ nd9 080 E dl 4 bossi 5 ire 280 8 8 19 189 Aviad 29 5011 en no 2509 dl lt 190581 01598501 PO 7HWrz 533308 anann 280 exo sam 0010 ainsez ei zeos dl 4 6140550 sess 20 ZHINGZ gt 280 N39 09 SOM 0019 VIL 310019 H
130. the board Power cycling may cause the SPI Flash not to get written completely due to write buffering Installing the Root File System RFS Update This procedure will result in the loss of user data on the Linux file system Back up your data check the version number of your root file system type the following Linux command 14 15 16 17 sh 3 2 cat root image date Power cycle the DN DUALV6 PCIE 4 Logic Emulation Board and monitor the power up events in the CRT window Note Press ENTER when the Hit any key to stop autoboot appears in the CRT window Enter the following command at the prompt dini_uboot gt gt run spi boot recoveryfs Enter the following command at the prompt sh 3 2 sh root tecover sh Note The recovery process takes about 10 minutes plus longer for the 180MB download from dinigroup com Enter the following command at the prompt sh sh 3 2 reboot DN DualV6 PCle 4 User Manual www dinigroup com 23 HARDWARE DESCRIPTION Chapter Hardware Description This chapter describes the hardware features of the DIN DialV 6 PCle4 Loge Emulation Board 1 Description 1 1 Overview The DN DualV6 PClIe 4 is complete logic prototyping system that enables ASIC or IP designers a vehicle to prototype logic and memoty designs for a fraction of the cost of existing solutions A high level block diagram of the DN DualV6 PCle 4 Logic Emulation Board is shown in Figure 4 follow
131. tion FPGA and FPGA A Signal Name Configuration FPGAA FPGA QA1NO U17 V24 U22 AA29 QA1N1 U17 V27 U22 AA31 QAIN10 U17 AH30 U22 AG32 DN DualV6 PCle 4 User Manual www dinigroup com 53 HARDWARE DESCRIPTION Signal Name QAIN16 1 17 QA1NI8 QAIN19 QAIN2 QAIN3 QAIN4 QA1N5 QA1NG QAIN7 QAIN8 QAIN9 QA1PO 1 10 QAIP11 QAIP12 QAIP13 QAIP14 QAIP15 QAIP16 QAIP17 QAIP18 QAIP19 QA1P2 QA1P3 QAIP5 QA1P6 7 QAIP8 DN DualV6 PCle 4 User Manual Configuration FPGA 17 AC29 17 AA31 17 AA30 17 W26 17 W27 17 AD29 17 W30 17 W25 17 V29 U17 AF30 17 AG30 17 1 17 W24 17 V28 17 AJ30 17 AF31 17 AD31 17 W31 U17 Y28 U17 AB30 17 AD30 17 AB31 17 AA29 U17 Y26 U17 Y27 17 AE29 17 V30 17 V25 17 W29 17 AF29 17 AH29 e e FPGA A U U U U U U U U U U U U U U U 22 AC30 22 AF34 22 AF33 22 AC29 U22 AB31 U22 AB26 U22 Y26 22 AC25 22 AB33 22 34 22 33 22 31 22 28 22 AE34 22 AE33 22 AD29 22 AC33 22 AD34 U22 AD32 www dinigroup com 54 HARDWARE DESCRIPTION Signal Name QAIP9 QA2NO QA2N1 QA2N10 QA2N11 QA2N12 QA2N13 QA2N14 QA2N15 QA2N16 QA2N17 QA2N18 QA2N19 QA2N2 QA2N3 QA2N4 QA2N5 QA2NG QA2N7 QA2N8 QA2N9 QA2P0 QA2P1 QA2P10 QA2P11 QA2P12 QA2P13 QA2P14 QA2P15 QA2P16 QA2P17 DN DualV6 PCle 4 User Manual Configuration FPGA 17 AJ31 17 17 17 99 17
132. tional items that support development efforts not provided Y Xilinx ISE Software DN DualV6 PCle 4 User Manual www dinigroup com 5 INTRODUCTION Y Xilinx Platform Cable USB DDR3 SODIMMs Available upon request 4 Inspect the Board Place the board on an anti static surface and inspect it to ensure that it has not been damaged during shipment Verify that all components are on the board and appear intact 5 Additional Information For additional information please visit http www dinigroup com The following table lists some of the resources you can access from this website You can also directly access these resources using the provided URLs Resource Description URL User Manual This is the main source of technical information The manual should contain most of the answers to your questions Demonstration MEG Array Daughter Card header insertion and removal video Videos Dini Group The web page will contain the latest user manual application notes Web Site FAQ articles and any device errata and manual addenda Please visit and bookmark http www dinigroup com Data Book Pages from Virtex 6 Databook which contains device specific information on Xilinx device characteristics E Mail You may direct questions and feedback to Dini Group using this e mail address support dinigroup com Phone Support Call us at 858 454 3419 during the hours of 8 00am to 5 00pm Pacific Time FAQ The
133. to an external capacitor see Figure 44 sEQ sEQ Pg av_SEQ Iss R342 R343 R21 RiB S 47K 47K P3 3VD FAULTa Ves 7 RST 5 a 1y 1 HA o Los iU Tether E messer 11 27 PWR RST P945 CPU 63 R327 us 47K Vec RST_CPUn TALVCSGUTDCT C TSOPSSPA00Xi30 0N 1 RST amp RST CPUn FORCE RSTn SUPERVISORY wR SEQ P33V SEQ 010 GND 53808501235 TPS3808G01DBVR R348 EM AST POR KRST PORN pg15 23 IX R334 gt R335 Reset Push Button n cpun CPU pgi4 CFPGA RST CFPGA OUTR JT SRSTn R336 DNI 100R Figure 44 Reset Circuit The reset pulse duration is set to approximately 102mS with CT 0 018uF 9 Daughter Card Header One 400 pin MEG Array daughter card header P2 15 placed on the bottom of the PCB All signals on the header are routed as matched length differential 50 Ohm transmission lines Other connections on the daughter card connector system include two dedicated differenti
134. tor pinouts and the connection to FPGA A B Table 24 Connections between the SODIMMs and FPGA Signal Name SODIMM FPGA SODIMM A J14 022 22 AH13 DIMMA A12 14 83 U22 AC17 DIMMA_A13 14 119 U22 AP25 DIMMA_A14 J14 80 U22 AM13 DN DualV6 PCle 4 User Manual www dinigroup com 71 HARDWARE DESCRIPTION ZAK DAM EXT ALI ADI AND ZANI nam EXIT XS ZAKAZ ZND nap ZNN DAM DAN DN DualV6 PCle 4 User Manual www dinigroup com 72 HARDWARE DESCRIPTION DN DualV6 PCle 4 User Manual www dinigroup com 73 HARDWARE DESCRIPTION ZADA ZNA mA mms AND BANDS NI AND AND DEVI ADI ZEE DN DualV6 PCle 4 User Manual www dinigroup com 74 HARDWARE DESCRIPTION m 113 U IMM B 21 FPGA 024 j21 98 U24 DIMMB_A1 J21 97 U24 L16 24 A15 24 A28 24 F20 24 D12 24 C30 24 B18 24 B16 24 D22 DIMMB 5 227 1724 19 DN DualV6 PCle 4 User Manual www dinigroup com 75 HARDWARE DESCRIPTION 2 E gn gn DN DualV6 PCle 4 User Manual www dinigroup com 76 HARDWARE DESCRIPTION DN DualV6 PCle 4 User Manual www dinigroup com 77 HARDWARE DESCRIPTION ngu DN DualV6 PCle 4 User Manual www dinigroup com
135. tstream is loaded into the device through special configuration pins These configuration pins serve as the interface for a number of different configuration modes The following configuration modes are supported e Slave SelectMAP parallel configuration mode x8 e JTAG Boundaty Scan configuration mode The configuration modes are explained in detail in Chapter 2 Configuration Interfaces of the UG360 Virtex 6 FPGA Configuration User Guide The specific configuration mode is selected by setting the appropriate level on the dedicated Mode input pins M 2 0 The M2 and MO mode pins should be set at a constant DC voltage level either through pull up or pull down resistors or tied directly to ground CONFIG see Figure 18 The mode pins should not be toggled during and after configuration The mode pins can also be driven by the CPU in Slave SelectMAP mode The mode pins should not be toggled during and after configuration In Slave SeleccMAP mode FPGA A and FPGA B are independently configured from the Configuration FPGA The mode pins can also be driven by the Configuration FPGA U17 in Slave SeleccMAP mode thus two sets of configuration mode select resistor exists see Figure 18 3 31 FPGA A B M 2 0 Select Resistors The specific configuration mode is selected by setting the appropriate level on the dedicated Mode input pins M 2 0 configuration pins DN DualV6 PCle 4 User Manual www dinigroup com 64 HARDWARE DESC
136. up com 66 HARDWARE DESCRIPTION responsible for developing the standard This standard provides a means to ensure the board level integrity of individual components and the interconnections between them The IEEE 1149 1 Test Access Port and Boundary Scan Architecture is commonly referred to as JTAG JTAG connector J13 is used to download the configuration files to the Configuration FPGA see Figure 19 R649 1K Figure 19 FPGA JTAG Interface Table 21 shows the connection between the JTAG header and FPGA Table 21 Connection between JTAG Header and FPGA Signal Name Connector FPGA A B JTAG 713 6 17 026 U22 AR8 24 8 FPGA TDI 11310 18 125 U22 AD8 B J13 8 18 U25 U24 AC8 JTAG_FPGA_TMS 13 4 22 AF8 U24 AF8 3 4 DDR3 Memory SODIMM The DN DualV6 PCIe 4 supports two 64 bit 204 pin SODIMM modules connected to the Virtex 6 FPGA A and B allowing addressing for up to 4GB DDR3 SDRAM PC3 8500 modules The following transfer speed can be expected e Speed Grade 3 1066Mb s Speed Grade 2 1066Mb s e Speed Grade 1 800Mb s The interface is connected to IO Banks on the Virtex 6 FPGAs and uses a 1 5V switching power supply for Vpp and Veco Vr and ate powered from a separate linear power supply set at 0 75 DDR3 SDRAM modules are available from Micron DN DualV6 PCle 4 User Manual www dinigroup com 6
137. us power to retain their contents During normal operation these memory cells are powered the auxiliary voltage input VCCAUX although a separate VBATT power input is provided for retaining the key when VCCAUX is removed Because VBATT draws vety little current on the order of nanoamperes small watch battery is suitable for this supply To estimate the battery life refer to D 152 Virtex 6 FPGA Data Sheet DC and Switching Characteristics At less than 100 nA load the endurance of the battery should limited only by its shelf VBATT does not draw any current and can be removed while VCCAUX 18 applied VBATT cannot be used for any purpose other than retaining the encryption keys when VCCAUX is removed In addition to supplying the power for FPGAs the backup battery BT1 also provides power for the Real Time Clock U36 Backup Batteries are available Panasonic Lithium Coin Cell 3V 40mAH from Digi Key P N CR1220 DN DualV6 PCle 4 User Manual www dinigroup com 87 HARDWARE DESCRIPTION 3 7 4 Backup Battery Circuit The recommended battery voltage is specified at 1 0V to 2 5V The TPS782 low dropout regulator LDOs offers the benefits of ultra low power 1 see Figure 23 R514 DNI OR TP28 06 Lig BAS40 05 SOT23 P VBATT Oleo P2 5V U14 54 3 2 1 5 2 5 2 IN C80 TRUE 3
138. ware write protection Please note that VDDSPD is connected to P3 3VD Table 22 Serial Presence Detect EEPROM Connections Signal Name FPGA DDR3 SODIMM SODIMM A J14 FPGA 022 714 197 pull down with 47K DIMMA_SAO U22 AM25 R614 714 201 pull down with 47K SA1 U22 AL25 R611 U DIMMA_SCL 22 AD24 J14 202 pull up 4 7K R610 DIMMA_SDA U22 AE24 J14 195 pull up 4 7K R613 SODIMM J21 FPGA 024 721 197 pull down with 4 7K DIMMB 540 U22 K13 R726 21 201 pull down with 47K DIMMB_SA1 U22 K12 R724 DIMMB SCL U24 AE24 21 202 pull up 4 7K R723 DN DualV6 PCle 4 User Manual www dinigroup com 70 HARDWARE DESCRIPTION DIMMB SDA U24 AD24 121 200 pull up 4 7K R722 3 4 6 Clocking Connections between FPGA and DDR3 SDRAM SODIMMs The clocking connections between the FPGA A B and the DDR3 SDRAM SODIMM s ate shown in Table 23 Table 23 Clocking Connections between FPGA A B and the DDR3 SDRAM SODIMMs Signal Name FPGA DDR3 SODIMM SODIMM J14 FPGA 022 DIMMA_CKOP DIMMA_CKON DIMMA_CK1N DIMMA_CK1P SODIMM 21 FPGA 024 DIMMB DIMMB CKON DIMMB CK1N DIMMB 22 11 114 101 22 12 114 103 22 24 114 104 22 22 114 102 U U U U 24 D24 j21 101 24 E24 721 103 24 J14 j21 104 24 K14 121 102 U U U U 3 4 7 SODIMM connections to the FPGA A B Table 24 shows the SODIMM connec
139. work DDR3 Clock Network G1 LVDS Clock Network G2 o External FPGA Clock LVDS Input via Test Point Multiple clocks from the Daughter Card Header o Multiplexed Global clocks from FPGA O Clock Test Points x3 Oscillators for GTP Transceivers x4 CPU Marvel MV78200 Discovery Innovation Dual o CPU Clocks up to 1 GHz o Dual 5 2 0 ports Type B connector o Dual Serial ATA II SATA o Gigabit Ethernet interface 10 100 1000 GbE RJ45 o DDR2 4GB 128M x 64 Sheeva CPU Core ARMv5TE compliant Out of order execution Single and double precision IEEE compliant floating point DN DualV6 PCle 4 User Manual www dinigroup com INTRODUCTION 16 bit Thumb instruction set increases code density DSP instructions boosts performance for signal processing applications to support virtual memory features Dual Cache 32 KB for data and instruction parity protected 2 cache 512 KB unified L2 cache CPU total of 1MB ECC protected 4 GB external DDR2 SDRAM Organized in a 128M x 64 configuration 400 MHz 800 MHz data rate After configuration both CPUs are dedicated entirely to user application o LINUX operating system Source and examples provided via GPL license no charge e Memory o DDR3 4GB 128Meg x 64 204 pin SODIMM PC3 8500 Serial FLASH Memory 64Kb 8192 x 8 e Daughter Card Header x1 LVDS MEG Array 400 pin

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