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1. A Ew 4 wwe LO n D b sw wo gt c N o o E of d N s AD Y Pe 4 4 50 Ohm gt YN 2 w 3 E ono ono ono w nC aw O O O Fig 4 1 System Layout with connections via Auxiliary VME bus Page 17 of 24 CAE 09 07 99 V551B User s Manual Version 1 1 4 2 2 USING MOD V550 AND V551B WITHOUT JAUX DATAWAY If the auxiliary VME bus is not available or if the User prefers not to use it in this case the Jaux Dataway DIP switches must be disabled the following connections must be performed The CONVERT signal must be distributed via 50 coaxial cables from the V551B to the relevant CONV connectors on the V550 Modules in daisy chain connection 50 termination must be inserted in the free CONV connector of the last V550 in a chain The CLEAR OUT signal must be distributed via 50 Q coaxial cables from the V551B to the relevant CLEAR connectors on the V550 Modules in a daisy chain connection A 50 Q termination must be inserted in the free CLEAR connector of the last V550 in a chain All the DATA READY connectors on the V550 Modules and the relevant DRDY connector on the V551B must be connected via 50 coaxial cables in a daisy chain connection In this ca2. TTL differential level that causes a TOKEN input to the first of the Front End chips in a multiplexing chain HOLD It is a level active low available on a front panel CONTROL connector TTL differential level that generates a Track Hold in the Front End chips The HOLD status starts with the peaking time of the shaper and terminates at the end of the readout from the multiplexer DELAY ON It is a level active high available on a front panel CONTROL connector TTL differential level that enables the internal HOLD delay in the VA chips DIGITAL RESET DRESET It is a pulse active high available on a front panel CONTROL connector TTL differential level sent to the Repeater cards at the end of a readout sequence or after a CLEAR ANALOG RESET ARESET It is a pulse active low available on a front panel CONTROL connector TTL differential level sent to the Repeater cards after a CLEAR TEST ON It is a level active high available on a front panel CONTROL connector TTL differential level that places the VA chips in TEST mode It is generated when the V551B itself is placed in TEST mode TEST PULSE It is a level active high available on a front panel CONTROL connector TTL differential level generated via VME VCAL It is an Analog Voltage Level 0 to 5 V 50 mA max current programmable via VME Page 15 of 24 CAE 09 07 99 V551B User s Manual Version 1 1 4 2 CONNECTION SCHEMES The Model V551
3. 19 of 24 CAE 09 07 99 V551B User s Manual Version 1 1 4 3 POWER ON CONFIGURATION At Power On most of the V551B Module is in an undetermined state All registers MUST thus be programmed in order to operate the Module The only determined configurations i e being always in this status at Power On are the following see 3 5 3 8 3 9 a INTERRUPT LEVEL 0 Interrupt Disabled b no INTERNAL DELAY g SHIFT LEVEL NOT ACTIVE TEST MODE h TEST PULSE LEVEL NOT ACTIVE TEST MODE If the Module is not programmed at Power On or if uncorrect settings are performed see 4 any further operation e g sending a TRIGGER may set the Module in a severe undetermined state in this case the only way to exit this state is to send a CLEAR and to program correctly the registers of the Module 4 4 STANDARD OPERATIONS refer to fig 4 3 In order to proceed with an ordinary acquisition cycle the User must perform a series of settings and thereafter start with the ordinary cycle The following describes the settings to be done and the corresponding operation sequence The readout sequence starts with an external or a VME TRIGGER The BUSY becomes active indicating that the module cannot accept another TRIGGER The leading edge of the TRIGGER starts a monostable multivibrator circuit This circuit after a time t1 programmable via VME in 10 ns steps in the range 500 ns to 3 us approx see 3 11 activates the HOLD and the SHI
4. 2 1 Front Panel Page 5 of 24 C A E PS 09 07 99 V551B User s Manual Version 1 1 07 Base address bit 23 20 gt e d Rotary switches X 0 lo for Base Address selection Base address bit lt 19 16 gt gt Boe N x VME P1 connector NEN LZ S Iu gt ON x ARESET ON oe p DRDY WI sw 4 CLEAR SW5 Ss NT Paux connector for CERN VMEbus Z 5 crate type V430 P2 connector Component side of the board lt 24185 Base address bit lt 27 24 gt gt AE 05 Rotary switches I 89 for Base Address selection 9 Base address bit lt 31 282 gt SAE 210 Fig 2 2 Components Locations Page 6 of 24 CAE 09 07 99 V551B User s Manual Version 1 1 3 VME INTERFACE 3 1 ADDRESSING CAPABILITY The module works in A24 A32 mode This implies that the module s address must be specified in a field of 24
5. daisy chaining requires termination if not chained see note 1 here below Min width 50 ns 1 This is a high impedance input and is provided with two bridged connectors for daisy chaining Note that the high impedance makes this input sensitive to noise so the chain has to be terminated on 50 Q on the last module the same is needed also if one module only is used whose input has thus to be properly matched 2 2 OUTPUTS BUSY CONTROL Std TTL positive open collector on 50 impedance active high Two LEMO 00 type bridged connectors for daisy chaining A red LED lights up when a BUSY signal is asserted Header 3M type 10 10 pins carrying the following signals VCAL Analog Voltage 0 to 5 V 50 mA max current Positive or Negative polarity selection via DIP switch SW1 TEST PULSE TTL differential level 110 O impedance Active high TEST ON TTL differential level 110 impedance Active high DELAY ON TTL differential level 110 Q impedance Active high SHIFT IN TTL differential level 110 Q impedance Active low An SH IN test point allows to monitor the SHIFT IN signal CLOCK TTL differential level 110 Q impedance Active low A CLOCK test point allows to monitor the CLOCK signal HOLD TTL differential level 110 Q impedance Active low A HOLD test point allows to monitor the HOLD signal DRESET TTL differential level 110 Q impedance Active high ARESET TTL differential level 110 Q imp
6. enne 11 Side TAVREGIST ER EE 12 3 12 T REGISTER net ede be tin td i pce enfe redis 12 39s REGISTER a ato pote INI Rs 12 3214 REGISTEE G nett sete tp eta o etre be qe een cipue 13 3 15 TY REGISTER aa a e that t e emp Hie dm eut ids beads equ dr Rat Pu renes 13 3 16 WRITE INTERNAL DAG rte ay etre exin 13 4 OPERATING MODES uu ss Dette iba e 14 4 1 GENERAL INFORMATION uuu e tetra te eret inti eto 14 4 2 CONNECTION SCHEMES eene nre 16 4 2 1 USING MOD V550 AND V551B WITH JAUX DATAWAY 16 4 2 2 USING MOD V550 AND V551B WITHOUT JAUX DATAWHAXY 18 4 3 POWER ON CONFIGURATION verrataan eenaa enne 20 4 4 5 terio Sasa aaa ias 20 4 5 TEST OPERATIONS ac u L aa terret otl peret etiatn detect 22 4 6 INTERRUPT GENERATION un nmn 23 5 REFERENCES a it ei eet e utet tv patet 24 APPENDIX A ELECTRICAL DIAGRAMS seen remettre A 1 CAE 09 07 99 V551B User s Manual Version 1 1 LIST OF FIGURES Fig Ved Block Diagram E E iie dau 2 Foce ds Front Pag au uu eet Et etg te t dan qasapaq ERE ve bertus 5 Fig 2 2 Components Locations n enne enne enn 6 Fig 3 1 Module Identifier Words A S 8 Fig 3 2
7. fully programmable via VME it is possible e to set the VME Interrupt level to program the VME Interrupt Vector STATUS ID The interrupt is generated on the assertion of the DRDY input signal which is the logical wired OR of all DRDY signals coming from the acquisition cards Thus the interrupt is requested when at the end of the readout sequence at least one channel in the system has data to be read out and is released when all the FIFOs have been completely read out If the Interrupt Level is set to 0 no Interrupts will be generated from the V551B Module Page 23 of 24 CAE 09 07 99 V551B User s Manual Version 1 1 5 REFERENCES 1 VMEbus Specification Manual Revision C 1 October 1985 2 G Bianchetti et al Specification for VMEbus CRATE Type V430 CERN EP January 1990 Page 24 of 24 CAE 09 07 99 V551B User s Manual Version 1 1 APPENDIX A ELECTRICAL DIAGRAMS A 1
8. 4 CAE 09 07 99 V551B User s Manual Version 1 1 3 11 T1 REGISTER Base address 0E read write 15 14 13 12 11 10 7 6 5 4 3 2 1 0 T1 T1 VALUE Fig 3 7 T1 Register This register allows to set the T1 parameter on 8 bits It gives the delay t1 between the Leading Edge of the TRIGGER and the HOLD assertion The actual delay t1 in nanoseconds is calculated as follows t1 500 T1 10 ns where 0 x T1 lt 255 3 12 T2 REGISTER Base address 9610 read write 15 14 13 12 114 10 9 7 6 5 4 8 2 1 0 T2 2 VALUE Fig 3 8 2 Register This register allows to set the T2 parameter on 9 bits It gives the delay t2 between the HOLD assertion and the start of the CLOCK CONVERT sequence The actual delay t2 in nanoseconds is calculated as follows t2 130 T2 20 10 ns where 10 x T2 x 511 The 10 ns Jitter is due to the synchronization with an internal Oscillator 3 13 T3 REGISTER Base address 9612 read write 15 14 13 12 11 109 1 8 7 6 5 4 S3 2 1 O0 T3 VALUE Fig 3 9 T3 Register This register allows to set the T3 parameter on 8 bits It gives the duration t3 of the active phase of the CLOCK and the CONVERT The actual duration t3 in nanoseconds is calculated as follows t3 T3 20 ns wh
9. AY selected VETO 0 VETO state 1 VETO state AUTOTRIGGER 0 NORMAL mode 1 AUTOTRIGGER mode DATA READY read only 0 DATA READY 1 DATA READY BUSY read only 0 not BUSY 1 BUSY ACTIVE SEQUENCE read only 0 no ACTIVE SEQUENCE 1 ACTIVE SEQUENCE The ACTIVE SEQUENCE bit indicates that the readout sequence is active i e the V551 Module is in a status between an accepted TRIGGER and a DRESET generation Page 10 of 24 4 Ec Pw 09 07 99 V551B User s Manual Version 1 1 3 9 TEST REGISTER Base address 960A read write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 PL SL CL TM TEST MODE CLOCK LEVEL SHIFT IN LEVEL TEST PULSE LEVEL Fig 3 5 Test Register TEST MODE 0 NORMAL selected 1 TEST MODE selected CL CLOCK LEVEL 0 active 1 active SL SHIFT LEVEL 0 active 1 active PL TEST PULSE LEVEL 0 active 1 active 3 10 NUMBER OF CHANNELS REGISTER Base address 0C read write 15 14 12 11 10 9 8 7 6 5l4 3 2 1 0 Number of channels Fig 3 6 Number of Channels Register The number N of detector channels to be read out by the C RAMS can be programmed via this register up to 2047 though the V550 C RAMS can accept only up to 2016 detector channels Page 11 of 2
10. B CAEN C RAMS Sequencer has been designed to control several C RAMS CAEN Readout for Analog Multiplexed Signals units Mod V550 in a single acquisition system When a Mod V551B C RAMS Sequencer controls more than one V550 channel the CONVERT signal is the same for each channel so that each multiplexer is controlled by a single CLOCK In order to operate the whole system properly some connections must be performed between the V550 C RAMS modules and the V551B Sequencer module The V551B CONVERT and CLEAR OUT signals must be distributed to the C RAMS acquisition cards and the V550 and V551B DATA READY signals must be connected together to perform a wired OR All this may involve the use of a large number of 50 Q coaxial cables The Mod V551B uses optionally the auxiliary connector for the CERN V430 VME bus crate Jaux Dataway if the VME auxiliary bus is available it is possible to send via backplane the CONVERT CLEAR OUT and DRDY signals and all the connections mentioned above can be avoided 4 2 1 USING MOD V550 AND V551B WITH JAUX DATAWAY By means of DIP switches both on the V550 and V551B boards it is possible to enable the Jaux Dataway see 2 3 to accomplish the following 1 The CONVERT signal coming from the V551B module is distributed to the V550 channels 2 The CLEAR OUT signal coming from the V551B module is distributed to the V550 channels 3 The wired OR of the V550 DATA READY signals is performed and received b
11. FA FC FE read only The three words located at the highest address of the page are used to identify the module as shown in figure 3 1 15 14 13 1211109 8 7 6 5 4 3 2 1 0 Address Version T e s SONIS Base FE Manufacturer number Module type Base FC FA Fixed code F5 Fixed code Base FA Fig 3 1 Module Identifier Words At the address Base FA the two particular bytes allow the automatic localization of the module For the Mod V551B the word at address Base FC has the following configuration Manufacturer 000010 b Type of module 0000111100 b The word located at the address Base FE identifies the single module via a serial number and any change in the hardware will be shown by the Version number Page 8 of 24 CAE 09 07 99 V551B User s Manual Version 1 1 3 4 INTERRUPT VECTOR REGISTER Base address 00 write only This register contains the value of the STATUS ID that the V551B INTERRUPTER places on the VME data bus during the Interrupt Acknowledge cycle 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 STATUS ID Interrupt STATUS ID Fig 3 2 Interrupt Vector Register 3 5 INTERRUPT LEVEL REGISTER Base address 02 write only This register contains the value of the Interrupt Level that the V551B INTERRUPTER places on the VME data bus during the Interru
12. FT IN signals the latter after t1 300 ns The HOLD signal is used to sample the signal at the output of the shapers at peaking time The SHIFT IN is the TOKEN signal for the first chip in the multiplexing chain and must be active at the occurrence of the first CLOCK For this purpose a hold time of 100 ns is provided Once the HOLD is asserted the CLOCK cycles begin after a time t2 programmable via VME in 20 ns steps in the range 170 ns to 10 us approx see 3 12 The CLOCK is generated by an internal 50 MHz oscillator due to this the actual begin of the readout i e the first MUX CLOCK will be delayed with respect to the HOLD assertion with a 10 ns Jitter In the following readout sequence N CLOCK and CONVERT pulses are generated The number N of detector channels between 1 and 2047 can be programmed via VME though the V550 C RAMS can accept up to 2016 detector channels Each CLOCK pulse is followed by a CONVERT pulse after a delay of t5 ns programmable via VME in 20 ns steps in the range 80 ns to 10 us approx see 3 15 The purpose of this delay is to wait for the settlement of the analog signal coming from the multiplexers The width of the active phase of the CLOCK and CONVERT pulses is t3 ns programmable via VME in 20 ns steps in the range 20 ns to 5 us approx see 3 13 N B The V550 accepts only CONVERT pulses with active phase gt 100 ns see V550 User s Manual Page 20 of 24 CAE 09 07 99 V551B User s Manua
13. Interrupt Vector Register u u rennes 9 Fig 3 3 Interrupt Level ul AE E nnn nnns 9 Fig 3 4 Status Register n n sns 10 Fig 3 5 Test ROJ STO a adn w re Odd tete rrr 11 Fig 3 6 Number of Channels Register I nennen enne 11 Fig 3 7 I ce sete tania ta piti vetet 12 Fig 3 8 T2 Beglster u u EUR ERREUR HEP UE Pana EL PUER 12 Fig 3 9 T3 BOgiSI IP l ege eee eei ette get eet eene ke b em ne e 12 Fig SOs T4 Register nitet er bike ene bate D o 13 Fig Sxl T T5 Register etie eile iue tei epe te ete telle bed estive 13 F1g 3 12 Internal usakuna DERE SERE qay 13 Fig 4 1 System Layout with connections via Auxiliary VME 17 Fig 4 2 System Layout with Connections without Auxiliary VME bus 19 Fig 4 3 Standard Operation Sequencoe enne 21 Fig 4 4 Test Operation Sequence l n nennen nennen 22 LIST OF TABLES Tables t Address MaD u dd ma di eins erii dg bib ai 8 CAE 09 07 99 V551B User s Manual Version 1 1 1 DESCRIPTION 1 1 FUNCTIONAL DESCRIPTION The Model V551B CAEN C RAMS Sequen
14. Technical Information Manual Version 1 1 9 July 1999 MOD V 551 C RAMS SEQUENCER CAE 09 07 99 V551B User s Manual Version 1 1 TABLE OF CONTENTS TABLE OF CONTENTS fece tcc ib i q pia etre ete ate e vts LIST OF FIGURES ioi o TROU DR DER P aie ea ii EIST OFSTABLES tette e m t aN h di ai em ote petes ii 1 IDESGRIPTION nii vede tib i aid testibus Pts 1 1 1 FUNCTIONAL DESCRIPTION titer reti eet retener testae 1 2 Ea tI sua RUBER PURSUING Sie eiie sis 3 2 1 INPUTS ite aeter rte pte een teat n idet eis 3 2 2 OUTBPUTS SI n ate Daten 3 2 3 OTHER COMPONENTS iret itt ett t et ege pea e Rcg 4 2 4 POWER 4 VME INTERFACE tient ee ar e t rp tette dein et i ee 7 3 1 ADDRESSING CAPABILITY nennen 7 3 2 DATA TRANSFER GAPABILTTY tete tte beet ette 7 3 3 MODULE IDENTIFIER WORDS eese enne 8 3 4 INTERRUPT VECTOR REGISTER seen emen 9 3 5 INTERRUPT LEVEL REGISTER 9 3 6 CLEAR REGISTER aie iternm err ert hune te m pet ree ien 9 3 7 TRIGGER REGISTER niihi eet tei ite id UR PRG e Eae Fees Poit kawsas 9 3 8 STATUS REGISTER Gn tm ett tie t mette eda 10 3 95 TEST BEGISTER sua n uska u De eder es 11 3 10 NUMBER OF CHANNELS REGISTER ee ee eene
15. allow to acquire the response of the VA chips to a TEST PULSE In Test Mode the HOLD signal remains not active the BUSY is not generated and the TRIGGER is ignored Via VME it is possible to set a positive or negative selection via SW1 see 2 3 Analog Voltage VCAL via an internal 12 bit DAC see 3 16 Full scale value is 5 V with a maximum current of 50 mA This level can be used to shape a pulse for test purposes after a TEST PULSE generation t6 lt BM TEST PULSE N pulses CONVERT 244 Fig 4 4 Test Operation Sequence Page 22 of 24 CAE 09 07 99 V551B User s Manual Version 1 1 Another test operating mode is achieved by using the AUTOTRIGGER feature It allows an automatic generation of readout sequences not synchronized with any TRIGGER that occur repeatedly at the maximum frequency compatible with the performed settings The AUTOTRIGGER must be operated only in NORMAL MODE bit 0 of Test Register set to 0 see 3 9 To enter the AUTOTRIGGER mode the User should set to 1 the relevant bit of the STATUS Register see 3 8 The actual occurrence of the repeated sequences will occur with an external or VME TRIGGER To exit AUTOTRIGGER mode the User should set to 0 the relevant bit of the STATUS Register see S3 8 This stops automatically the generation of readout sequences 4 6 INTERRUPT GENERATION The operations of the V551B VME RORA INTERRUPTER are
16. cer is a 1 unit wide VME module that handles the Data Acquisition from multiplexing front end chips The module is well suited to handle the VA family of chips produced by IDE AS Oslo but due to its flexibility it can also be used with similar chips Amplex Gasplex etc The V551B has been developed to control the signals from to the C RAMS CAEN Readout for Analog Multiplexed Signals boards Mod V550 the latter taking care of the conversion of the multiplexed signals from the front end boards housing the above chips A single V551B can control up to 19 C RAMS modules in a complete VME crate thus enabling the readout of 19 2 2016 76608 multiplexed detector channels The Mod V551B is controlled via VME bus The number N of detector channels to be read out by the C RAMS can be programmed via VME up to 2047 though the V550 C RAMS can accept up to 2016 detector channels The multiplexing frequency can be set via VME from 100 kHz to 5 MHz with programmable Duty Cycle The delay between the multiplexing Clock signal and the Convert signal of the acquisition cards can be adjusted to wait for the settlement of the analog signal coming from the multiplexers The delay between the Trigger and the Hold signal and the delay between the Hold and the Conversion Cycles are also programmable thus extending the Module s flexibility The module houses VME RORA INTERRUPTER 1 via VME it is possible to program the interrupt generation on the con
17. dition that the DRDY signal is asserted signaling that at least one channel in a system has data to be read out The V551B Model uses the P1 and P2 connectors of VME and optionally the auxiliary connector for the CERN V430 VMEbus crate Jaux Dataway 1 2 in order to handle if desired the CONV DRDY and CLOUT signals via the Jaux connector The module works in A24 A32 mode The data transfer occurs in D16 mode Page 1 of 24 T1 T5 A INTERFACE C A E rl 09 07 99 TRIG gt CONV lt Busy lt MAIN SEQUENCER Dp CLOUT lt CON TROL DRDY Fig 1 1 Block Diagram Page 2 of 24 V551B User s Manual Version 1 1 IDENTIFIER VME INTERRUPTER INT LEVEL STATUS m bs VME BUS 09 07 99 V551B User s Manual Version 1 1 2 SPECIFICATIONS 2 1 INPUTS DATA READY TRIG CLEAR IN Std TTL level 50 Q impedance also on Jaux active high on aLEMO 00 type connector A green LED lights up when a DRDY signal is asserted Std NIM level high impedance on two LEMO 00 type bridged connectors for daisy chaining requires termination if not chained see note 1 here below min width 50 ns must be active high A green LED lights up when a TRIG signal is asserted Std NIM level high impedance on two LEMO 00 type bridged connectors for
18. dress 9618 write only 15 14 13 12 11 109 8 7 6 5 4 S3 2 1 O0 DAC VALUE INTERNAL DAC Fig 3 12 Internal DAC This register allows to set the Analog positive voltage VCAL on the front panel CONTROL connector It is 12 bits long and the full scale value FFF corresponds to a 5 V 50 mA max output on the VCAL line The polarity can be changed via an internal DIP switch 5 1 Page 13 of 24 CAE 09 07 99 V551B User s Manual Version 1 1 4 OPERATING MODES 4 1 GENERAL INFORMATION The Model V551B CAEN C RAMS is well suited to handle the VA family of chips produced by IDE AS Oslo but due to its flexibility it can also be used with similar chips Amplex Gasplex etc The V551B has been developed to control the signals from the C RAMS boards Mod V550 the latter taking care of the conversion of the multiplexed signals from the multiplexer boards housing the above chips A CONTROL Bus allows the use of this Module with the VA Repeater Cards or similar The module handles three kinds of signals Signals that interface with the External World b Signals that interface with the V550 C RAMS Modules c Signals that interface with the VA Repeater Cards or similar a EXTERNAL WORLD SIGNALS TRIGGER TRIG It is a pulse NIM level provided via front panel connectors whose leading edge starts all the conversion sequence The User should provide th
19. edance Active low N B The CLOCK CONV HOLD and SH IN signals on test points are std TTL level all active high disregarding their active level on the Control Bus and front panel connectors Page 3 of 24 CAE 09 07 99 V551B User s Manual Version 1 1 CONVERT Std NIM level on 50 Q impedance two LEMO 00 type connectors fan out of 2 differential ECL on Jaux connector active high A CONV test point allows to monitor the CONVERT signal A green LED lights up during a convert cycle CLEAR OUT Std NIM level on 50 Q impedance two LEMO 00 type connectors fan out of 2 differential ECL on Jaux connector 2 3 OTHER COMPONENTS refer to Fig 2 1 2 2 DISPLAYS 1 DTACK green LED VME Selected It lights up during a VME access or an Interrupt Acknowledge cycle INTERNAL SWITCHES 1 DIP switch SW1 to perform the polarity selection of the VCAL voltage positive negative 1 DIP switch SW2 ARESET to enable disable the analog reset to the front end chips ON Enabled 2 DIP switches SW3 CONV to enable disable the CONV generation via the Jaux backplane lines CK and CK ON Enabled 1 DIP switch SW4 DRDY to enable disable the DRDY detection on the Jaux backplane line SG ON Enabled 2 DIP switches SW5 CLEAR to enable disable the CLEAR generation via the Jaux backplane lines CL and CL ON Enabled 1 DIP switch SW6 VEE AUX for the 5 V power selection via this s
20. ere 1 x x T4 and T3 lt 255 This constraint T3 x T4 follows automatically from the fact that the active phase of the CLOCK and CONVERT must be less than their own period Page 12 of 24 CAE 09 07 99 V551B User s Manual Version 1 1 3 14 T4 REGISTER Base address 14 read write 15 14 13 12 11 109 8 7 6 5 4 3 2 1 O0 T4 T4 VALUE Fig 3 10 T4 Register This register allows to set the T4 parameter on 9 bits It gives the period t4 of both the CLOCK and the CONVERT sequence The actual period t4 in nanoseconds is calculated as follows t4 20 T4 20 ns where 1 T4 511 3 15 T5 REGISTER Base address 9616 read write 15 14 13 12 131 109 8 7 5 4 8 2 1 0 T5 T5 VALUE Fig 3 11 T5 Register This register allows to set the T5 parameter on 9 bits In NORMAL MODE it gives the delay 15 between the CLOCK and the relevant CONVERT The actual delay 15 in nanoseconds is calculated as follows t5 40 T5 20 ns where 2 lt 5 511 In TEST MODE it gives the delay t6 between the leading edge of the TEST PULSE and the first CONVERT pulse The actual delay t6 in nanoseconds is calculated as follows t6 150 T5 20 10 ns where 2 lt T5 x 511 The 10 ns Jitter is due to the synchronization with an internal Oscillator 3 16 WRITE INTERNAL DAC Base ad
21. g Front end chips read out but no data in the V550 buffers All data read out from the V550 buffers External or software Clear Page 14 of 24 CAE 09 07 99 V551B User s Manual Version 1 1 b C RAMS SIGNALS CONVERT It is the start of conversion pulse available on a front panel connector NIM level or via CK and CK pins of the Jaux backplane connector of the V430 VME crate ECL level that goes to all the channels of the V550 Modules CLEAR OUT CLOUT It is a pulse available on a front panel connector NIM level or via CL and CL pins of the Jaux backplane connector ECL level It is asserted when a software CLEAR is performed or when CLEAR IN is asserted It can be used to reset the acquisition cards V550 DATA READY DRDY It is a signal TTL level that indicates by means of a wired OR of the DRDY signals coming from the acquisition cards V550 that at least one of such modules is in DATA READY state and so has data to be read out The DRDY signal is provided via front panel connectors or via the SG pin of the Jaux connector of the V430 crate N B The Jaux signals can be disabled via internal DIP switches c REPEATER CARD SIGNALS CLOCK CK It is a signal active low available on a front panel CONTROL connector TTL differential level that is provided to the Front End chips multiplexers clock SHIFT IN It is a pulse active low available on a front panel CONTROL connector
22. is signal to the module to start the whole acquisition Software generation of the TRIGGER is also available see 3 7 A TRIG is accepted if the Module is not in a BUSY status CLEAR IN CLIN It is a pulse NIM level that resets the V551B board It can be used as a Fast Clear to abort the current multiplexer readout cycle The User should provide this signal to the module to abort the whole acquisition A CLEAR IN pulse causes the following 1 apulse is generated on the CLOUT output same duration as CLIN 2 a pulse is generated on the DRESET line of the CONTROL BUS same duration as CLIN 3 a pulse is generated if enabled on the ARESET line of the CONTROL BUS same duration as CLIN 4 if the conversion sequence is in progress it is aborted and this causes an anticipated pulse 1 us duration on the DRESET also ARESET if enabled line of the CONTROL BUS the BUSY output becomes not active Software generation of the CLEAR IN is also available see 83 6 BUSY BUSY It is a positive open collector signal available on a front panel connector that indicates that the system cannot accept new events In this case the TRIGGER signal is ignored The BUSY condition occurs in the following cases when the V551B Sequencer itself is in the conversion phase when the wired OR of the DRDY signals is high VME reading phase in progress when CLOUT is asserted The BUSY is removed with the occurrence of one of the followin
23. l Version 1 1 The repetition period t4 of the CLOCK and CONVERT pulses and consequently the multiplexing frequency is programmable via VME in 20 ns steps in the range 40 ns to 10 us approx see 3 14 The CLOCK CONVERT HOLD and SHIFT IN signals are available on four test points placed on the front panel The active level on the test points is always high disregarding the normal level of the relevant signals on the front panel connectors see 2 4 With the last CONVERT pulse the DRESET line also the ARESET if enabled becomes active for a 1 us time thus resetting the front end circuitry After the generation of the last CONVERT pulse the BUSY signal becomes not active if none of the V550 acquisition cards has asserted the DRDY signal Otherwise when the DRDY has been raised at least one channel has data ready the BUSY signal remains high until all the V550 FIFOs have been read out i e until the DRDY becomes not active A software controlled VETO is also available The VETO forces the V551B in a BUSY condition no TRIGGER accepted t2 lt TO TRIGGER HOLD CLOCK Manes N pulses CONVERT SHIFT IN 300 ns 100 ns BUSY DRESET ARESET DRDY Fig 4 3 Standard Operation Sequence Page 21 of 24 CAE 09 07 99 V551B User s Ma
24. nual Version 1 1 4 5 TEST OPERATIONS The V551B Module features a Test Mode operation that allows the User to test its acquisition chain In order to proceed with a test acquisition cycle the User must perform a series of settings and thereafter start with the test cycle The following describes the settings to be done and the corresponding operation sequence The TEST mode is enabled via VME setting to 1 bit 0 of the TEST Register see 3 9 The TEST ON line of the CONTROL bus sets the VA chips in Test Mode When the Module is in Test Mode it is possible to drive the CLOCK SHIFT IN and TEST PULSE lines via VME see 3 9 in order to switch the multiplexer on the desired channel and produce a test pulse The transitions on these lines occur at the same time corresponding to the VME access N B Due to the fact that it is possible to set only the level of these signals the User should take care of generating the appropriate sequence via software The leading edge of the TEST PULSE is used to trigger a series of CONVERT pulses see fig 4 4 The delay t6 between the leading edge of the TEST PULSE and the first CONVERT pulse is programmable via VME in 20 ns steps in the range 190 ns to 10 us approx see 3 15 The number of convert pulses N number of channels the width t3 of the active phase of the CONVERT pulse and the repetition period t4 of the CONVERT pulses are programmable via VME as in the Normal mode see 4 4 These pulses
25. or 32 bits The Address Modifier codes recognized by the module are AM 3D A24 supervisory data access AM 39 A24 non privileged data access AM 0D 2 supervisory data access AM 09 2 non privileged data access The module s Base Address is fixed by 4 internal rotary switches housed on two piggy back boards plugged into the main printed circuit board see Fig 2 2 The Base Address can be selected in the range 00 0000 lt gt 0000 24 mode 00000000 lt gt 0000 A32 mode The Address Map of the page is shown in Table 3 1 on the following page 3 2 DATA TRANSFER CAPABILITY The internal registers are accessible in D16 mode Page 7 of 24 CAE 09 07 99 V551B User s Manual Version 1 1 ADDRESS REGISTER CONTENT TYPE Base FE Version amp Series read only Base FC Manufacturer amp module type read only Base FA Fixed code read only Base 18 Internal DAC write only Base 16 T5 Register read write Base 14 T4 Register read write Base 12 T3 Register read write Base 10 T2 Register read write Base 0E T1 Register read write Base 0C Number of channels read write Base 0A Test Register read write Base 08 Status Register read write Base 06 Software Trigger read write Base 04 Software Clear read write Base 02 Interrupt Level write only Base 00 Interrupt Vector write only Table 3 1 Address Map 3 3 MODULE IDENTIFIER WORDS Base address
26. pt Acknowledge cycle 15 14 13 12 11 10 9 87 6 5 4 3 2 1 O INT LEV Interrupt level Fig 3 3 Interrupt Level Register 3 6 CLEAR REGISTER Base address 9604 read write A VME access read or write to this location causes the following 1 apulse 500 ns is generated on the CLEAR output 2 a pulse 500 ns is generated on the DRESET line of the CONTROL BUS 3 a pulse 500 ns is generated if enabled on the ARESET line of the CONTROL BUS 4 if the conversion sequence is in progress it is aborted and this causes an anticipated pulse 1 us duration on the DRESET also ARESET if enabled line of the CONTROL BUS the BUSY output becomes not active 3 7 TRIGGER REGISTER Base address 9606 read write A VME access read or write to this location starts a conversion sequence The same action is performed if the TRIGGER input signal is active Page 9 of 24 CAE 09 07 99 V551B User s Manual Version 1 1 3 8 STATUS REGISTER Base address 08 read write 15 14 13 2 111 10 9 8 7 6 5 4 83 2 1 0 AS B DY AT V ID AT DY AS INTERNAL DELAY VETO AUTOTRIGGER DATA READY read only BUSY read only ACTIVE SEQUENCE read only Fig 3 4 Status Register INTERNAL DELAY 0 no INTERNAL 1 INTERNAL DEL
27. se the 50 Q termination is not necessary as the DRDY connector on the V551B is already terminated It can be useful to note that the CONVERT and CLEAR OUT signals are provided with fan out of 2 via the V551B front panel connectors The load can be thus divided in two chains In this case the 50 Q termination must be placed on both free CONV and CLEAR OUT connectors of the two last loads in the chains N B If the V430 crate is not used the 5 V power supply selection jumper must be set to VEE This allows to obtain the 5 V from the 12 V power supply Page 18 of 24 4 E R 09 07 99 V551B User s Manual Version 1 1 CAEM Mod V551B od 0 0 od 0 DTACK DTACK DTACK DTACK CHO CHO CHO conv ENS c e E N ms N ms zoo ono 9 3 Sh a S Y N CH1 CH1 To Repeater i o Cards rox zoo HEHHHH C ze x 24 9 50 Ohm 2 Vu 2 4 lt lt o lt gt ono w w N Va EB p 9 oS p gt mrb Fig 4 2 System Layout with Connections without Auxiliary VME bus Page
28. witch it is possible to choose the 5 V power supply coming from the 12 V VME power supply VEE position or directly from the 5 V Jaux power supply AUX position 4 rotary switches for the module s VME Base Address selection N B By setting the three DIP switches SW3 SW4 and SW5 in the OFF position it is possible to disable the CONV CLEAR and DRDY signals handling via Jaux backplane In this case the CK CK CL CL and SG Jaux lines are disconnected 2 4 POWER REQUIREMENTS 12 V 100 mA 12V 350 mA 100 mA when Jaux is used 5V 1A 5V 250 mA only if Jaux is used Page 4 of 24 CAE 09 07 99 V551B User s Manual Version 1 1 Mod V551B ptack VME selected LED clock CLOCK signal test point cov CONVERT signal test point amp HOLD signal test point RUN SHIFT IN signal test point CONVERT output lt x o DATA READY input gt E Eh P p PES TRIGGER input za a bes GND IVCAL A ae GND TESTPULSE TEST PULSE TESTON TESTON DELAYON DELAY ON SHIFTIN h SHIFT IN O cK BUSY output lt HOLD HOLD DRESET DRESET o ARESET ARESET CLEAR input gt b a L ee CLEAR output lt Fig
29. y the DRDY input of the Mod V551B If on the backplane there is no termination on the CK CK CL and CL auxiliary VME bus lines the CLEAR and CONVERT signals must be terminated otherwise For this purpose a removable termination package 50 to VTT can be installed on the last V550 C RAMS module in a Crate e g if a V551B is in slot 3 and five V550 modules are in slots 4 to 8 the termination must be inserted in the V550 in slot 8 See V550 User s Manual for further information As the DATA READY is a TTL signal if there is a termination on the SG auxiliary VME bus line it must be removed from the backplane N B With the layout shown in Fig 4 1 it is convenient to set the 5 V power supply selection jumper to AUX This allows to reduce the power consumption on the 12 V power supply Page 16 of 24 4 E R 09 07 99 V551B User s Manual Version 1 1 Mod V551B od 0 od 0 od 0 DTACK i DTACK DTACK DTACK dd e CHO CHO ENS c e z e o S o 9 o N m N m Re w w w 50 Ohm Auxiliary CERN VME bus Bae CONV ho e gt CLEAR 2l zl al gt DRDY b WP MM m P5 0 9 0 D mS To Repeater Cards E z Ue 2 v z
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