User Manual
Contents
1. and values is needed for further noise reductions C2 C3 and C4 can be fitted with LK4 present The Ag5300 Classification is fixed at Class 4 and does not need any external programming components When the EVALAG5300 board is connected to an IEEE802 3at PoE compliant PSE such as a Phihong POE36U 1AT R the PSE will detect Class 4 and output 2 Event classification pulses In turn the Ag5300 detects these pulses and activates the AT DET detect output This output is connected to an opto isolator to cross the isolation barrier and LED 3 will be illuminated Note The EVALAG5300 does not have an on board PHY or u controller so does not perform the Data Link Layer DLL classification communications back to the PSE to confirm its power requirement Many IEEE802 3at PSEs such as the Phihong POE36U 1AT R do not need this and will automatically supply full Type 2 power at start up But there are several Switches e g Cisco that will only output Type 1 power level lt 15 4W until they receive DLL confirmation that the PD is Type 2 and supports the higher power level J1 J2 o M Data amp Data Out Power IN g B 1 a 1 PoE Power Vout J3 Lenz U2 Ra 22 Dutput ON LEDS ci LED1 E D1 BR2 BR1 FE gi a6 A TT 3 sid AT Detect JG C2 C3 I tI tka 4 57 Sy TH zI Vout J5 PI l w S LK2 40 41 Adj2. N aoe a TPZ2O120102 MPZ20125 102A MPZ20128102A ak 1 aos to a Ta i um mm i or 2 OG 1 vor l oe tz 4 Fa vee Haay RE 18 re 4 gt spose Figure 4 Board Schematic 6 3 Link settings LK1 Connects input power LED circuit LK2 Output adjust select LK3 IEEE802 3at PSE detection LED LK4 Option for Y Cap link to be fitted
3. Silvertel EVALAG5300 Rev 1 Evaluation Board User Manual Rev 1 0 September 2013 1 Table of Contents 1 Table of Contents 2 Table of Figures 3 Introduction 4 Board Description 4 1 Input Selection and Classification ve cee casces sess disessasdansesnatescnvectescsvensess 4 2 Output adjustment 5 Typical Set up 6 Using the Board 6 1 Typical Applicaton EEE EE re ee eer er lerende 6 2 EVALAG5300 REV 1R Evaluation Board Schematic 6 3 Link settings 2 Table of Figures Figure 1 Board Layout Fig re2 BA SN ae Figure 3 Example SEE UP Lee Figure 4 Board Schematic 3 Introduction This manual is intended to be a guide to using the EVALAG5300 Rev1 0 evaluation board with a Silvertel Ag5300 Powered Device PD module 4 Board Description The input data and power is supplied to the board through connector J1 The data is passed through to the peripheral equipment via J2 with the power from the PD module supplied via J3 to J5 see Figure 1 amp 4 The EVALAG5300 on board bridge rectifiers will ensure that the correct input polarity is applied to the PD 4 1 Input Selection and Classification The EVALAG5300 board will automatically direct the power from J1 to the Ag5300 s input LED2 will be illuminated when PoE power is being applied to the board LK1 can be removed if you do not want LED2 to illuminate If the need for a Y Capacitor filtering arrangement See apps note ANX POE HD Base T for information
4. ek PZ6122 or PZ6112 ethernet camera The PC ethernet port is connected to the data input of the Phihong POE36U 1AT R PSE via a short Cat5e patch cable The Data amp Power output from the Phihong POE36U 1AT R is connected to the input of the EVALAG5300 evaluation board J1 via a CAT5e crossover cable up to 100m The data output of the EVALAG5300 evaluation board is connected to the data port of the ethernet camera via a short CAT5e patch cable The 12V parallel configuration power output from the EVALAG5300 evaluation board J4 connects to the dc input of the Vivotek PZ6122 ethernet camera CAT5e F Patch Mains Supply Cable POE36U 1AT R EVALAg5300 Vivotek PZ6122 Ethernet Camera Data Mains J2 Data amp Power J1 Ag5300 i 12V 0 PC Data CAT5e CAT5e Patch Crossover Cable Cable Figure 3 Example set up 6 2 EVALAG5300 REV 1R Evaluation Board Schematic Data and nd P Power In Isolation Barrier Data Out i 2 z 3 EE TER lt pme S H r oo raiser i i i i i i i i i i sos mose oe TI i am 5 am ANE Power Output ut r 2 u T 4 vin vos HL seem take Yme sl TER w ox r 15 us 2 a nana aaa E
5. ust U1Ag5300 EvalAg5300 Rev1 0 Figure 1 Board Layout 4 2 Output adjustment The Ag5300 output has an ADJ pin which allows the output voltage to be increased or decreased from its nominal value The EVALAG5300 board has an adjust link LK2 and two resistors R2 68K and R4 OR which allows the Ag5300 output to be adjusted to its maximum and minimum values To increase the output voltage to its maximum connect a link to LK2 in the top position so the link is between the middle and top pin To reduce the output voltage to its minimum connect a link between the bottom pin and middle pin of LK2 If the output voltage needs to be set to a different value within the adjustment range then connect different resistors instead of the OR or 68K link 5 Typical Set up Figure 2 shows the basic set up using the EVALAG5300 evaluation board with a Midspan or Endspan The equipment required gt Midspan or Endspan PSE Power Sourcing Equipment gt Peripheral or Test Equipment gt CAT5e cables gt Output power cable gt Mains cable Mains Supply MidSpan Endspan EVALAg5300 Board Peripheral Equipment Data J2 Data amp Power ij PC or Switch Data J3 J5 Power or J4 Figure 2 Basic set up 6 Using the Board 6 1 Typical Application Figure 3 shows an example set up using an Ag5300 powered by a Phihong POE36U 1AT R Midspan and supplying 12V to a Vivot
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