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Demonstration Source Code

1. eases 109 9 1 REVISION HISTORY nee 109 DIC OPYPIGHI SDATENIENT 109 2 DE1 SoC User Manual www terasic com Chapter 1 DE71 SoC Development Kit The DE1 SoC Development Kit presents a robust hardware design platform built around the Altera System on Chip SoC FPGA which combines the latest dual core Cortex A9 embedded cores with industry leading programmable logic for ultimate design flexibility Users can now leverage the power of tremendous re configurability paired with a high performance low power processor system Altera s SoC integrates an ARM based hard processor system HPS consisting of processor peripherals and memory interfaces tied seamlessly with the FPGA fabric using a high bandwidth interconnect backbone The DEI SoC development board includes hardware such as high speed DDR3 memory video and audio capabilities Ethernet networking and much more The DEI SoC Development Kit contains all components needed to use the board in conjunction with a computer that runs the Microsoft Windows XP or later 1 1 Package Contents Figure 1 1 shows a photograph of the DE1 SoC package Cher DE1 SoC DE1 SoC Board DE1 SoC Quick Start Guide A to B USB Cable l Type A to Mini B USB
2. Standard FPGA I2C SDAT PIN Ki2 2 Data HPS I2C1 SCLK PIN 23 2 Clock of the first HPS 2 concontroller 2 1 SDAT 24 I2CDataofthefirstHPSI2Cconcontroller HPS I2C2 SCLK 2 Clock of the second HPS 12C concontroller 3 3V HPS I2C2 SDAT PIN 5 2 Data of the second HPS I2C concontroller 3 3V 3 6 6 VGA The DEI SoC board includes a 15 pin D SUB connector for VGA output The VGA synchronization signals are provided directly from the Cyclone V SoC FPGA and the Analog Devices ADV7123 triple 10 bit high speed video DAC only the higher 8 bits are used 15 used to produce the analog data signals red green and blue It could support the SXGA standard 1280 1024 with a bandwidth of 100MHz Figure 3 21 gives the associated schematic 30 Terasic DE1 SoC User Manual www terasic com www terasic com R 7 0 G 7 0 UT hs VGA_B 7 0 ATERA VGA_CLK ao a ADV7123 We soc VGA_SYNC_N VGA BLANK VGA VS VGA HS Figure 3 21 VGA Connections between FPGA and The timing specification for VGA synchronization and RGB red green blue data can be found on various educational website for example search for signal timing Figure 3 21 illustrates the basic timing requirements for each row horizontal that is displayed on a VGA monitor An active low pulse of specific
3. o Figure 3 14 Switch debouncing 21 Terasic DE1 SoC User Manual www terasic com www terasic com ANU RYAN There are ten slide switches connected to FPGA on the board See Figure 3 15 These switches are not debounced and are assumed for use as level sensitive data inputs to a circuit Each switch 1s connected directly to a pin on the Cyclone V SoC FPGA When the switch is in the DOWN position closest to the edge of the board it provides a low logic level to the FPGA and when the switch is in the UP position it provides a high logic level PN OTE RYA Cyclone V SoC AD10 AC9 ii AD 11 Ti EY Logic SW9 SW8 SW7 SW6 SW5 SW4 SW3 SW2 SW1 SWO 1 0 Figure 3 15 Connections between the slide switches and Cyclone V SoC FPGA There are also ten user controllable LEDs connected to FPGA on the board Each LED 15 driven directly by a pin on the Cyclone V SoC FPGA driving its associated pin to a high logic level turns the LED on and driving the pin low turns it off Figure 3 16 shows the connections between LEDs and Cyclone V SoC FPGA Table 3 6 Table 3 7 and Table 3 8 list the pin assignments of these user interfaces 22 Terasic DE1 SoC User Manual www terasic com www terasic com Signal 5 0 SW 1 SW 2 SW 3 SWI4 SWI5 SW 6 SWI7 SWI 8 SWI9 Signal Name KEY 0 KEY 1 2 KEY 3 Terasic DE1 SoC User Manual w terasic com ww PIN V16 PIN W16 PIN V
4. fileje Remote Local update difference file NONE Create Memory Map File Generate output file map Create CvP files Generate output file periph jic and output file core rbf Create config data RPD Generate output file auto rpd File Data area Start Address Flash Loader SOF Data age lt auto gt DE1 5oC Default sof Figure 8 3 Highlight Flash Loader Select the targeted FPGA that you are using to program the serial configuration device See Figure 8 4 Click OK The Convert Programming Files page displays See Figure 8 5 Click Generate 104 Terasic DE1 SoC User Manual www terasic com www terasic com Cydone IV Cydone HardCopy IT HardCopy HardCopy IV _ MAX V Programming file type mos canton device File name D faltera 13 1 output file jic Remote Local update difference file NONE Create Memory Map File Generate output_file map Create files Generate output_file periph jic and output_file core rbf Create config data Generate output_file_auto rpd File Data area 4 Flash Loader f 5CSEBAS 4 SOF Data Add Device DE1 SoC Default sof ER Remave Up Down Properties Figure 8 5 Convert Programming Files Page 105 Terasic DE1 SoC User Manual www terasic com ANU RYAN 8 3 Write JIC File into Quad Serial Configuration Device To
5. Figure 8 1 File menu of Quartus In the Convert Programming Files dialog box scroll to the JTAG Indirect Configuration File jic from the Programming file type field In the Configuration device field choose EPCQ256 In the Mode field choose Active Serial X4 In the File name field browse to the target directory and specify an output file name Highlight the SOF data in the Input files to convert section See Figure 8 2 102 Terasic DE1 SoC User Manual www terasic com www terasic com Convert Programmi File Tools Window Conversion setup files Output programming file Programming file type Indirect Configuration File jic hd Qe dee ode File D altera 13 1 output file jic Le name Remote Local update difference file Create Memory Map File Generate output_file map _ Create files Generate output file periph jic and output file core rbf Create config data RPD Generate output file auto rpd Figure 8 2 Convert Programming Files Dialog Box Click Add File Select the SOF that you want to convert to a JIC file Click Open Highlight the Flash Loader and click Add Device See Figure 8 3 Click OK The Select Devices page displays 103 Terasic DE1 SoC User Manual www terasic com www terasic com Lo Search altera com Output programming file Programming type File name
6. USB3300 U30 XTALIN CLKIN HPS_RESET_n ADM812 USBHUB_CLK_24 Figure 3 34 Connections between Cyclone V SoC FPGA and USB OTG PHY Table 3 29 USB OTG PHY Pin Assignments Signal Name FPGA Pin No Description Standard 2 Reference Clock Output 5 USB DATA O PIN E16 HPS USB DATA O 3 3V 47 Terasic DE1 SoC User Manual www terasic com www terasic ANU RYAN HPS USB DATA 1 HPS USB DATA 2 HPS USB DATA 3 HPS USB DATA 4 HPS USB DATA 5 HPS USB DATA 6 HPS USB DATA 7 HPS USB DIR HPS USB NXT HPS USB RESET HPS USB STP 3 7 7 G Sensor The board is equipped with a digital accelerometer sensor module The ADXL345 is a small thin ultralow power assumption 3 axis accelerometer with high resolution measurement Digitalized output 15 formatted as 16 bit twos complement and can be accessed using I2C interface The 12 address of the G Sensor device is OxA6 OxA7 For more detailed information of better using this chip please refer to its datasheet which 15 available on manufacturer s website or under the Datasheet folder of the DEI SoC System CD Figure 3 35 shows the connections between PIN G16 HPS USB DATA 1 3 3V PIN D16 HPS USB DATA 2 3 3V PIN D14 HPS USB DATA 3 3 3V PIN A15 HPS USB DATA 4 3 3V PIN C14 HPS USB DATA 5 3 3V PIN D15 HPS USB DATA 6 3 3V PIN M17 HPS USB DATA 7 3 3V PIN E14 Direction of the Data Bus 3 3V PIN A14 Throttle the D
7. Launch SOC Kit System Builder Launch Quartus II and Open Project Create New SOC Kit System Builder Add User Design Logic Project Generate Compile to generate SOF Configure FPGA Quartus Project and Document Figure 4 1 General design flow of building a design 4 3 Using DE1 SoC System Builder This section provides the detailed procedures on how the DE1 SoC System Builder is used B Install and launch the DE1 SoC System Builder The DE1 SoC System Builder is located in the directory Tools SystemBuilder on the DEI SoC 52 Terasic DE1 SoC User Manual www terasic com www terasic com ANU RYAN System CD Users copy the whole folder to a host computer without installing the utility Launch the DEI SoC System Builder by executing the DEI SoC SystemBuilder exe on the host computer and the GUI window will appear as shown in Figure 4 2 DE1 SoC V1 0 0 na p NB S RYA System Configuration rip ide Project Name R Www Ceresic com DE Soc DE1 SoC FPGA Board CLOCK 4 Seqment x 6 LED x10 Switch x 10 Button x 4 TXIRX WVGA 4 Video In Audio SDRAM 32MB PS2 HPS GPIO 0 Header Noe Prefix Name GPIO 1 Header Save Setting Generate None Prefix Name Load Setting Exit Figure 4 2 The DE1 SoC System Builder window B Input Project Name Input project name as show in Fi
8. SW1 0 4 MSEL3 On 0 SW1 0 5 MSEL4 Off 1 SW10 6 N A N A N A Figure 3 1 shows valid MSEL 4 0 settings for FPGA configuration mode of DEI SoC DEI SoC is shipped with AS mode as the default mode When the board is powered on the FPGA 15 configured from EPCQ which is pre programmed with the manufacturer default code If developers wish to reconfigure FPGA from an application software running on Linux developers need to adjust MSEL 4 0 to 01010 just before the programming process If developers using the Linux Console with framebuffer or Linux LXDE Desktop SD Card image developers need to adjust MSEL 4 0 to 00000 before board is power on Table 3 2 MSEL pin Settings for FPGA Configure of DE1 SoC MSEL 4 0 Configure Scheme Description 10010 AS FPGA configured from EPCQ default 01010 FPPx32 FPGA configured from HPS software Linux FPGA configured from HPS software U Boot with 00000 FPPx16 image stored on the SD card like LXDE Desktop or console Linux with framebuffer edition 3 2 Configuring the Cyclone V SoC FPGA The DEI SoC board contains a serial configuration device that stores configuration data for the Cyclone V SoC FPGA This configuration data is automatically loaded from the configuration device into the FPGA every time while power is applied to the board Using the Quartus software it is possible to reconfigure the FPGA at any time and it is also possible to change the non volatile data th
9. DEI SoC USER MANUAL P d sO of p Rig ui s E ATERA UNIVERSITY www terasic com PROGRAM Copyright 2003 2013 Terasic Technologies Inc All Rights Reserved CONTENTS CHAPTER 1 DE1 SOC DEVELOPMENT KIT ccccccsssssssccssssssssssscscsscccccccsssssssssssssssssssccccecssssssssssssssseees 3 ONS sarc 3 DPE i IMD IM 4 HPE 4 CHAPTER2 INTRODUCTION OF THE DE1 SOC BOARD ccsssssssssscccssssssssssssssssssssscccsssssssssssssssseees 5 2 IM AYOUTANDEC ONPONENTS MuR 5 22 BLOCK DIAGRAM OF THE DE1 SOC BOARD cand conecaanseaacalonsstanteetiaeansdlonswanccnsionnre UR pHdqI a 7 CHAPTER3 USING THE DE1 SOC BOARD 10 3 1 FPGA CONFIGURATION MODE SETTING s nessesesesseeersssscersssseresssreressseeeessseresssreresseeceesssrersssreresssecresseeeressreresssreresses 10 OU CONFIGURING THE CYCLONE V SOC FPUA xs Desa to bre EN AET AEN 11 JI BOARD STATUS ELEMENTS 17 Sd BOARD RESET penia Kean RN pts DENE IREN D DI EEEN KEREN A s 17 OS EE O T EAEE EE EE EEE E AEE 19 S4 INTERPEACEB ON PPT 20 3 6 1 USER PUSH BUTTO
10. Generator Figure 5 5 Setup for the Karaoke Machine 5 4 SDRAM Test by Nios Many applications use SDRAM to provide temporary storage In this demonstration hardware and software designs are provided to illustrate how to perform memory access in QS YS We describe how the Altera s SDRAM Controller IP is used to access a SDRAM and how the Nios II processor is used to read and write the SDRAM for hardware verification The SDRAM controller handles the complex aspects of using SDRAM by initializing the memory devices managing SDRAM banks and keeping the devices refreshed at appropriate intervals B System Block Diagram Figure 5 6 shows the system block diagram of this demonstration The system requires a 50 MHz clock provided from the board The SDRAM controller is configured as a 64MB controller The working frequency of the SDRAM controller is 100MHZz and the Nios II program is running in the on chip memory 64 Terasic DE1 SoC User Manual www terasic com www terasic com S 50 MHz i On Chip lt gt lt gt Memory PIO ze SDRAM mb a dmm SDRAM System Intercoment Fabric Figure 5 6 Block diagram of the SDRAM Basic Demonstration The system flow is controlled by a Nios II program First the Nios II program writes test patterns into the whole 64MB of SDRAM Then it calls Nios II system function alt
11. LSB LSB LSB LSB 1 gms 4 9ms Address Address Logical Inverse Command Command Logical Inverse SP sn EE 1 le 27ms bla 27ms 67 5ms Figure 5 14 Typical frame of NEC protocol Note IR Receiver receives the signal a inverted value e g IR TX Controller send a lead code 9 ms high then 4 5 ms low IR Receiver will receive a 9 ms low then 4 5 ms high lead code B IR Remote When key on the remote controller See Figure 5 15 is pressed the remote controller will emit a 76 DE1 SoC User Manual www terasic com ANU S RYAN standard frame shown in Table 5 6 The beginning of the frame is the lead code represents the start bit and then is the key related information and the last bit end code represents the end of the frame This frame is descript the signal which IR Receiver Received MENU RETURN 9v PLAY ADJUST OW R Figure 5 15 Remote controller Table 5 6 Key code information for each Key on remote controller Key Code Key Code Key Code Key Code Q 77 DE1 SoC User Manual www terasic com www terasic ANU RYA End Inv Key Code Lead Code 1bit Custom Code 16bits Key Code 8bits 8bits Figure 5 16 The transmitting frame of the IR remote controller B IR RX Controller In this demo the IP of IR receiver controller is i
12. described in below B IR TX Controller User can input 8 bit address and 8 bits command into IR TX Controller IR TX Controller will encode the address and command first and send it out according to NEC IR transmission protocol through IR emitter LED Note that the input clock of the Controller should be 50MHz The NEC IR transmission protocol uses pulse distance encoding of the message bits Each pulse burst 1s 562 5us in length at a carrier frequency of 38kHz 26 3us As shown in Figure 5 13 Logical bits are transmitted as follows e Logical 0 a 562 5us pulse burst followed by 562 5us space with a total transmit time of 1 125ms 75 Terasic DE1 SoC User Manual www terasic com www terasic com ANU RYAN e Logical 1 a 562 5us pulse burst followed by 1 6875ms space with a total transmit time of 2 25ms Logical 1 Logical 0 56225us li 56225us gt 562 25us 4 262 2505 y 2 25ms pie 1 125ms pi Figure 5 13 Logical 1 and Logical 0 Figure 5 14 shows the frame of the protocol Protocol will send a lead code first a 9ms leading pulse burst followed by a 4 5msThe second inversed data is sent to verify the accuracy of the information received At last a final 562 5us pulse burst to signify the end of message transmission Because every time it is sent inversed data the overall transmission time is constant 000000001 1 1 4 1 1 1 1 O1 1010101001 O 1 0
13. DQS n 0 PIN M19 HPS DDR3 Data Strobe n 0 Differential 1 5 V SSTL Class 1 HPS DDR3 DQS n 1 PIN N24 HPS DDR3 Data Strobe n 1 Differential 1 5 V SSTL Class HPS DDR3 DQS 2 PIN R18 HPS DDR3 Data Strobe n 2 Differential 1 5 V SSTL Class HPS DDRS3 DQGS n 3 PIN R21 HPS DDR3 Data Strobe n 3 Differential 1 5 V SSTL Class HPS DDRS3 DQGS p 0 PIN N18 HPS DDR3 Data Strobe p 0 Differential 1 5 V SSTL Class HPS DDRS3 DQGS p 1 PIN N25 HPS DDR3 Data Strobe p 1 Differential 1 5 V SSTL Class HPS DDR3_DQS p 2 PIN 19 HPS DDR3 Data Strobe p 2 Differential 1 5 V SSTL Class 1 HPS DDRS3 DQS 3 PIN R22 HPS DDR3 Data Strobe p 3 Differential 1 5 V SSTL Class HPS DDR3 PIN H28 HPS DDR3 On die Termination SSTL 15 Class HPS DDRS3 RAS n PIN D30 DDR3 Row Address Strobe SSTL 15 Class HPS DDR3 RESET n PIN P30 HPS DDR3 Reset SSTL 15 Class HPS DDR3 WE n PIN C28 HPS DDR3 Write Enable SSTL 15 Class HPS DDR3 RZQ PIN D27 External reference ball for 1 5 V output drive calibration 3 7 5 Micro SD The board supports Micro SD card interface using x4 data lines And it may contain secondary boot code for HPS Figure 3 33 shows the related signals Finally Table 3 28 lists all the associated pins for interfacing HPS respectively SD CLK SD CMD 7 Micro SD Card E Lu Ske ycione SoC HPS SD DAT3 CD ue i Vd Figure 3 33 Connections between Cyclone V SoC FPGA and SD Card Socket 46 Terasic DE1 SoC User Manual w
14. If necessary that is if the default factory configuration of the DEI SoC board is not currently stored 1n EPCQ device download the bit stream to the board by using JTAG programming e You should now be able to observe that the 7 segment displays are displaying a sequence of characters and the red LEDs are flashing e Optionally connect a VGA display to the VGA D SUB connector When connected the VGA 58 Terasic DE1 SoC User Manual www terasic com www terasic com display should show a color picture e Optionally connect a powered speaker to the stereo audio out jack Press KEY 1 to hear a 1 kHz humming sound from the audio out port e There is a demo_batch folder in the project It is able to load the bit stream into the FPGA programming or erasing jic file to EPCQ by executing test bat file as shown in the Figure 5 1 If user want to download the new design into the EPCQ the easy method 1s to copy the new sof file into the demo batch folder and Execute the test bat Select the option 2 to covert the sof to jic firstly Then using the option 3 to program jic file into EPCQ Plesase choise your operation a programming sof to FPGA For converting sof to jic For programming jic to EPCQ for erasing jic From EPCQ i Please enter your choise 1 2 3 4 Figure 5 1 Batch file for download FPGA and EPCQ 5 2 Audio Recording and Playing This demonstration shows how to implement an
15. TXIRX iV VGA Video In Audio 4 SDRAM 32MB PS2 HPS GPIO 0 Header Noe Prefix Name GPIO 1 Header Save Setting Generate None Prefix Name Load Setting Exit Figure 4 4 System Configuration Group B GPIO Expansion Users can connect GPIO daughter cards onto the GPIO connector located on the development board shown in Figure 4 5 Select the daughter card you wish to add to your design under the appropriate GPIO connector to which the daughter card is connected The System Builder will automatically generate the associated pin assignment including pin name pin location pin direction and I O standard 55 Terasic DE1 SoC User Manual www terasic com www terasic com DE1 SoC V1 0 0 NO S RYAN ter PRTG System Configuration i eng Ae Project Name DE SOC Www teresic com PROGRAM T DE1 SoC FPGA Board CLOCK 7 Seqment x 6 LED x 10 Switch x 10 Button x 4 TXIRX VI VGA Video In Audio ADC SDRAM 32MB PS2 HPS GPIO 0 Header D5M 5M Pixel Camera Prefix Name GPIO 1 Header Save Setting Generate None Prefix Name Figure 4 5 GPIO Expansion Group The Prefix Name is an optional feature that denotes the pin name of the daughter card assigned in your design Users may leave this field empty B Project Setting Management The DEI SoC System Builder also provides functions t
16. VGA 60Hz VGA 85Hz SVGA 60Hz SVGA 75Hz SVGA 85Hz XGA 60Hz XGA 70Hz XGA 85Hz 1280x1024 60Hz VGA mode Configuration VGA 60Hz VGA 85Hz SVGA 60Hz SVGA 75Hz SVGA 85Hz XGA 60Hz XGA 70Hz XGA 85Hz 1280x1024 60Hz sync a Figure 3 22 VGA horizontal timing specification Table 3 14 Horizontal Timing Specification Horizontal Timing Spec Resolution HxV 640x480 640x480 800x600 800x600 800x600 1024x768 1024x768 1024x768 1280x1024 a us 3 8 1 6 3 2 1 6 1 1 2 1 1 8 1 0 1 0 b us 1 9 2 2 2 2 3 2 2 7 2 5 1 9 2 2 2 3 c us 25 4 17 8 20 16 2 14 2 15 8 13 7 10 8 11 9 d us 0 6 1 6 1 0 3 0 6 0 4 0 3 0 5 0 4 Table 3 15 Vertical Timing Specification Vertical Timing Spec Resolution HxV 640x480 640x480 800x600 800x600 800x600 1024x768 1024x768 1024x768 1280x1024 a lines b lines c lines d lines 0 32 DE1 SoC User Manual www terasic com 33 25 23 21 27 29 29 36 38 480 480 600 600 600 768 768 768 1024 10 Pixel clock MHz Pixel clock MHz 25 www terasic com Signal VGA_R 0 VGA RI 1 VGA RI 2 VGA VGA 4 VGA 5 VGA RI6 VGA RI7 VGA 0 VGA G 1 VGA_G 2 VGA G 3 VGA 4 VGA G 5 VGA 6 VGA GI 7 VGA VGA VGA BI VGA VGA 4 VGA BI5 VGA 6 VGA BI7 VGA CLK VGA BLANK N VGA HS VGA VS VGA
17. and Nios are installed on your PC Make sure the MSEL 4 0 on DEI SoC board is set to 01010 or 01110 Connect the USB blaster cable to the USB blaster connector 713 on the DEI SoC board and host PC install USB Blaster driver if necessary e Connect the USB cable to the USB to UART connector J4 on the DEI SoC board and host PC e Make sure the executable file hps config fpga and HPS LED and the FPGA 99 Terasic DE1 SoC User Manual www terasic com www terasic configure file soc system dc rbf are copied into the SD card under the home root folder in Linux Insert the booting micro SD card into the DEI SoC board For how to build a booting micro SD card image Please refer to the chapter 5 Running Linux on the DEI SoC board on DEI SoC Getting Started Guide pdf Power on the DE1 SoC board Launch PuTTY to connect to the UART port of DEI SoC board and type root to login Altera Yocto Linux In the UART terminal of PuTTY execute hps config fpga soc system dc rbf to configure the FPGA through the FPGA manager After configuring done the message shown in the Putty as shown in Figure 7 2 a e m T d Lar b E d xu riu T e Figure 7 2 running app configure FPGA In the UART terminal of PuTTY execute HPS LED HEX to start the program The putty will show the message as shown in Figure 7 3 and
18. background programming for MAX II and MAX devices File Device Checksum Usercode Program Verify Blank osot Configure Check lh ctn D de1 soc trunk cd CD SCSEMASF31 03888274 03888274 none SOCVHPS 00000000 none 4 Auto Detect Delete Save File T up Down 5CSEMASF31 Figure 3 8 FPGA JTAG Programming Steps 6 B Configuring the FPGA in AS Mode from EPCQ256 e The board contains a quad serial configuration device EPCQ256 that stores configuration data for the Cyclone V SoC FPGA This configuration data 15 automatically loaded from the quad serial configuration device chip into the FPGA when the board is powered up e To program the configuration device users will need to use a Serial Flash Loader SFL function to program the quad serial configuration device via the JTAG interface The FPGA based SFL is a soft intellectual property IP core within the FPGA that bridges the JTAG and flash interfaces The SFL mega function is available from Quartus II software Figure 3 9 shows the programming method when adopting a SFL solution e Please refer to Chapter 9 Steps of Programming the Quad Serial Configuration Device for the basic programming instruction on the serial configuration device 16 Terasic DE1 SoC User Manual www terasic com www terasic com Quartus Programmer Circuit SFL Image to Bridge The JTAG A
19. be configured through the DATA FORAMT O0x31 register In the demonstration we configure the data format as Full resolution mode lt 16g range mode Left justified mode The X Y Z data value can be derived from DATAX0 0x32 DATAX1 0x33 DATAYO 0x34 DATAY 1 0x35 DATAZO 0x36 DATAX1 0x37 registers The DATAXO represents the least significant byte and DATAX1 represents the most significant byte It is recommended to perform multiple byte read of all registers to prevent change in data between reads of sequential registers Developer can use the following statement to read 6 bytes of X Y or Z value read file szData8 sizeof szData8 where szData is an array of six bytes B Demonstration Source Code e Build tool Altera SoC EDS v13 1 e Project directory Demonstration SoC hps_gsensor e Binary file gsensor Build command make make clean to remove all temporal files e Execute command gsensor loop count B Demonstration Setup e Connect the USB cable to the USB to UART connector J4 on the DE1 SoC board and host PC e Make sure the executable file gsensor is copied into the SD card under the home root folder in Linux e Insert the booting micro sdcard into the DEI SoC board 93 Terasic DE1 SoC User Manual www terasic com www terasic ANU S nA e Power on the DEI SoC board Launch PuTTY to connect to the UART port of DEI SoC borad and type root to login Y
20. debugging Table 3 23 gives the all the pin assignments of all the user interfaces 41 Terasic DE1 SoC User Manual www terasic com www terasic ANU RYAN Table 3 23 Pin Assignments for LEDs Switches and Buttons Signal Name HPS GPIO Register bit Function HPS_KEY GPIO54 GPIO1 25 vo HPS LED GPIO53 GPIO1 24 VO 3 7 2 Gigabit Ethernet The board provides Ethernet support via an external Micrel KSZ9021RN PHY chip and HPS Ethernet MAC function The KSZ9021RN chip with integrated 10 100 1000 Mbps Gigabit Ethernet transceiver support RGMII MAC interfaces Figure 3 31 shows the connection setup between the Gigabit Ethernet PHY and Cyclone V SoC FPGA The associated pin assignments are listed in Table 3 24 For detailed information on how to use the KSZ9021RN refers to its datasheet and application notes which are available on the manufacturer s website HPS TX DATA 3 0 TXD 3 0 HPS ENET GTX ctx GLK HPS TX EN EN MDI_HPS_N HPS_ENET_RX_DATAI3 01 oj _HPS_ JNO S RYAN HPS RX CLK ow pig MDI_HPS_P HPS ENET RX DV RX_DV HPS ENET MDC HPS LED2 DUAL 1 HPS ENET MDIO DUAL LED2 DUAL 2 HPS ENET INT N INT HPS ENET RESET N RESET_N 25 S x1 KSZ9021RN RJ45 Figure 3 31 Connections between Cyclone V SoC FPGA and Ethernet Table 3 24 Pin Assignment
21. duration time a in the figure is applied to the horizontal synchronization hsync input of the monitor which signifies the end of one row of data and the start of the next The data RGB output to the monitor must be off driven to V for a time period called the back porch b after the hsync pulse occurs which is followed by the display interval c During the data display interval the RGB data drives each pixel in turn across the row being displayed Finally there is a time period called the front porch d where the RGB signals must again be off before the next hsync pulse can occur The timing of the vertical synchronization vsync is the similar as shown in Figure 3 22 except that a vsync pulse signifies the end of one frame and the start of the next and the data refers to the set of rows in the frame horizontal timing Table 3 14 and Table 3 15 show different resolutions and durations of time periods a b c and d for both horizontal and vertical timing Detailed information for using the ADV7123 video DAC is available in its datasheet which can be found on the manufacturer s website or in the Datasheets VIDEO DAC folder on the DE1 SoC System CD The pin assignments between the Cyclone V SoC FPGA and the ADV7123 are listed in Table 3 16 3l Terasic DE1 SoC User Manual www terasic com www terasic com Back porch b Display interval c Front porch d S DATA RGB HSYNC VGA mode Configuration
22. first one parity check bit odd check and one stop bit always one PS 2 controller samples the data line at the falling edge of the PS 2 clock signal This could easily be implemented using a shift register of 33 bits but be cautious with the clock domain crossing problem B Data transmit from the controller to device Whenever the controller wants to transmit data to device it first pulls the clock line low for more than one clock cycle to inhibit the current transmit process or to indicate the start of a new transmit process which usually be called as inhibit state After that it pulls low the data line then release the clock line and this 1s called the request state The rising edge on the clock line formed by the release action can also be used to indicate the sample time point as for a start bit The device will detect this succession and generates a clock sequence in less than 10ms time The transmit data consists of I2bits one start bit as explained before eight data bits one parity check bit odd check one stop bit always one and one acknowledge bit always zero After sending out the parity check bit the controller should release the data line and the device will detect any state change on the data line in the next clock cycle If there s no change on the data line for one clock cycle the device will pull low the data line again as an acknowledgement which means that the data is correctly received 72 Terasic DE1 S
23. flush all to make sure all data has been written to SDRAM Finally it reads data from SDRAM for data verification The program will show progress in JTAG Terminal when writing reading data to from the SDRAM When verification process is completed the result is displayed in the JTAG Terminal B Design Tools e Quartus II 13 1 e Nios II Eclipse 13 1 B Demonstration Source Code e Quartus Project directory DEI SoC SDRAM Nios Test Nios II Eclipse DEI SoC SDRAM Noios Test Software B Nios II Project Compilation e Before you attempt to compile the reference design under Nios II Eclipse make sure the project is cleaned first by clicking Clean from the Project menu of Nios II Eclipse 65 Terasic DE1 SoC User Manual www terasic com ANU RYAN B Demonstration Batch File Demo Batch File Folder DEI SoC_SDRAM_Nios_ Test Nemo batch The demo batch file includes following files Batch File for USB Blaster ID DEI SoC SDRAM Nios_Test bat DEI SoC SDRAM mNlios Test bashrc FPGA Configure File DEI SoC SDRAM Nlios Test sof Nios II Program DEI SoC SDRAM Nios Test elf Demonstration Setup Make sure Quartus II and Nios II are installed on your PC Power on the DEI SoC board Use USB cable to connect PC and the DE1 SoC board J13 and install USB Blaster driver if necessary Execute the demo batch file DEI SoC SDRAM wNtios Test bat for USB Blaster II under the batch file folder DEI SoC SDRAM Nios
24. shows the function block diagram of this demonstration The controller uses 50 MHz as a reference www terasic com clock generates one 100 MHz clock as memory clock 67 Terasic DE1 SoC User Manual www terasic com SDRAM mE Conrtoller Test 2 CLOCK 50 t Contro w Process Figure 5 8 Block Diagram of the SDRAM Demonstration RW test modules read and write the entire memory space of the SDRAM through the interface of the controller In this project the read write test module will first write the entire memory and then compare the read back data with the regenerated data the same sequence as the write data KEYO will trigger test control signals for the SDRAM and the LEDs will indicate the test results according to Table 5 3 Design Tools Quartus 13 1 Demonstration Source Code Project directory DEI SoC SDRAM RTL Test Bit stream used DEI SoC SDRAM RTL Test sof Demonstration Batch File Demo Batch File Folder DEI SoC SDRAM RTL Testidemo batch The demo batch file includes following files Batch File DE SoC SDRAM RTL Test bat FPGA Configure File DEI SoC SDRAM RTL Test sof Demonstration Setup Make sure Quartus II 1s installed on your PC Connect the USB cable to the USB Blaster connector on the DEI SoC board and host PC 68 Terasic DE1 SoC User Manual www terasic com ANU S RYA e Power on the DEI SoC board e Exe
25. the JTAG Chain the configure flow is different from the one used with DEI The following shows the programming flow with mode step by step e Open Programmer and click Auto Detect as Figure 3 3 12 Terasic DE1 SoC User Manual www terasic com Tools Window Enable real time ISP to allow background programming for MAX and MAX devices Checksum Usercode Program Verify Blank Examine Configure Check ph Start Stop X Delete Save File Figure 3 3 FPGA JTAG Programming Steps 1 Select detected device as Figure 3 4 Please select the device associated with the board Select Device Found devices with shared JTAG ID for device 1 Please select your device e Both FPGA and HPS will be detected as Figure 3 5 13 Terasic DE1 SoC User Manual www terasic com www terasic com ANU S RA Search altera com Jiredwaeseup DESC MSS Enable real time ISP to allow background programming for MAX II and MAX V devices wel Start qi stoo sene 00000000 00000000 Auto Detect 3 Delete 35 Add File us Change File eee Figure 3 5 FPGA JTAG Programming Steps 3 Click the FPGA device right click mouse to popup the manual and then select sof file for FPGA as Figure 3 6 14 Terasic DE1 SoC User Manual w
26. 17 PIN_V18 S RYAN en wir W19 PIN W20 PIN W21 LEDO LED1 LED2 LED3 LED4 LEDS LED6 LED LED8 LED9 PIN Y21 LEDO LED1 LED2 LED3 LED4 LEDS LED6 LED LED8 LEDO Figure 3 16 Connections between the LEDs and Cyclone V SoC FPGA Table 3 6 Pin Assignments for Slide Switches VO Standard FPGA Pin No Description PIN_AB12 Slide Switch 0 PIN_AC12 Slide Switch 1 PIN_AF9 Slide Switch 2 PIN_AF10 Slide Switch 3 PIN_AD11 Slide Switch 4 012 Slide Switch 5 PIN AE11 Slide Switch 6 PIN AC9 Slide Switch 7 PIN AD10 Slide Switch 8 PIN AE12 Slide Switch 9 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V Table 3 7 Pin Assignments for Push buttons Standard FPGA Pin No Description PIN AA14 Push button 0 PIN AA15 Push button 1 PIN W15 Push button 2 PIN Y16 Push button 3 23 3 3V 3 3V 3 3V 3 3V www terasic com ANU RYAN Table 3 8 Pin Assignments for LEDs Signal Name FPGA Pin No Description Standard LEDR 0 PIN_V16 LED 0 3 3V LEDR 1 PIN_W16 LED 1 3 3V LEDR 2 PIN_V17 LED 2 3 3V LEDR 3 PIN V18 LED 3 3 3V LEDR 4 PIN_W17 LED 4 3 3V LEDR 5 PIN_W19 LED 5 3 3V LEDR 6 PIN_Y19 LED 6 3 3V LEDR 7 PIN_W20 LED 7 3 3V LEDR 8 PIN_W21 LED 8 3 3V LEDR 9 PIN 21 LED 9 3 3V 3 6 2 Using the 7 segment Displays The DEI SoC board has six 7 segment displays These displays are arranged into three pairs mea
27. 3 3V 26 Terasic DE1 SoC User Manual www terasic com www terasic com GPIO_0 4 0 5 GPIO 0 6 GPIO 0 7 0 8 GPIO 0 9 GPIO 0 10 GPIO 0 11 GPIO 0 12 GPIO 0 13 GPIO 0 14 GPIO 0 15 GPIO 0 16 GPIO 0 17 GPIO 0 18 GPIO 0 19 GPIO 0 20 GPIO 0 21 GPIO 0 22 GPIO 0 23 GPIO 0 24 GPIO 0 25 GPIO 0 26 GPIO 0 27 GPIO 0 28 GPIO 0 29 GPIO 0 30 GPIO 0 31 GPIO 0 32 GPIO 0 33 GPIO 0 34 GPIO 0 35 GPIO 1 0 GPIO 1 1 GPIO 1 2 GPIO 1 3 GPIO 1 4 GPIO 1 5 GPIO 1 6 GPIO 1 7 GPIO 1 8 GPIO 1 9 GPIO 1 10 GPIO 1 11 PIN AK16 PIN AK18 PIN AK19 PIN AJ19 PIN AJ17 PIN AJ16 PIN AH18 PIN AH17 PIN AG16 PIN AE16 PIN AF16 PIN AG17 PIN AA18 PIN AA19 PIN AE17 PIN AC20 PIN AH19 PIN AJ20 PIN AH20 PIN AK 1 PIN AD19 PIN AD20 PIN AE18 PIN AE19 PIN AF20 PIN AF21 PIN AF19 PIN AG21 PIN AF18 PIN AG20 PIN AG18 PIN AJ21 PIN AB17 PIN AA21 PIN AB21 PIN AC23 PIN AD24 PIN AE23 PIN AE24 PIN AF25 PIN AF26 PIN AG25 PIN AG26 PIN AH24 GPIO Connection 0 4 GPIO Connection O 5 GPIO Connection O 6 GPIO Connection 0 7 GPIO Connection O 8 GPIO Connection O 9 GPIO Connection 0 10 GPIO Connection 0 11 GPIO Connection 0 12 GPIO Connection 0 13 GPIO Connection 0 14 GPIO Connection 0 15 GPIO Connection 0 16 GPIO Connection 0 17 GPIO Connection 0 18 GPIO Connection 0 19 GPIO Connection 0 20 GPIO Connection 0 21 GPIO
28. 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V www terasic com ANU RYAN 3 6 3 Using the 2x20 GPIO Expansion Headers The board provides two 40 pin expansion headers The header connects directly to 36 pins of the Cyclone SoC FPGA and also provides DC 5V VCC5 DC 3 3V VCC3P3 and two GND pins The maximum power consumption of the daughter card that connects to GPIO port is shown in Table 3 10 Table 3 10 Power Supply of the Expansion Header Supplied Voltage Max Current Limit 5V 1A 3 3V 1 5A Each pin on the expansion headers 1s connected to two diodes and a resistor that provides protection against high and low voltages Figure 3 18 shows the protection circuitry for only one of the pin on the header but this circuitry is included for all 72 data pins Table 3 11 shows all the pin assignments of the GPIO connector VCC3P3 JP1 ANU S RYAN Cyclone V Soc GPIO_0 35 0 E EE REE RS 59 999909090990909099999099 m Figure 3 18 Connections between the GPIO connector and Cyclone V SoC FPGA Table 3 11 Pin Assignments for Expansion Headers Signal Name FPGA Pin No Description Standard GPIO O 0 PIN AC18 GPIO Connection 0 0 3 3V GPIO O 1 PIN Y17 GPIO Connection 0 1 3 3V _ GPIO_0 2 PIN_AD17 GPIO Connection 0 2 GPIO_0 3 PIN Y18 GPIO Connection 0 3
29. 4 DDR3 Memory on HPS The DDR3 devices that are connected to the HPS are the exact same devices connected to the FPGA 1n capacity IGB and data width 32 bit comprised of two x16 devices with a single address command bus This interface connects to dedicated Hard Memory Controller for HPS I O banks and the target speed is 400 MHz Table 3 27 lists DDR3 pin assignments I O standards and descriptions with Cyclone V SoC FPGA Table 3 27 Pin Assignments for DDR3 Memory Signal Name FPGA Pin No Description Standard HPS DDR3 A 0 PIN F26 HPS DDR3 Address 0 SSTL 15 Class HPS DDR3_A 1 PIN_G30 HPS DDR3 Address 1 SSTL 15 Class HPS DDR3_A 2 PIN F28 HPS DDR3 Address 2 SSTL 15 Class HPS DDR3_A 3 PIN_F30 HPS DDR3 Address 3 SSTL 15 Class HPS DDR3_A 4 PIN_J25 HPS DDR3 Address 4 SSTL 15 Class HPS DDR3 A 5 PIN J27 HPS DDR3 Address 5 SSTL 15 Class HPS DDR3_A 6 PIN_F29 HPS DDR3 Address 6 SSTL 15 Class HPS DDR3 A T7 PIN E28 HPS DDR3 Address 7 SSTL 15 Class HPS DDR3_A 8 PIN_H27 HPS DDR3 Address 8 SSTL 15 Class HPS DDR3_A 9 PIN_G26 HPS DDR3 Address 9 SSTL 15 Class HPS DDR3 A 10 PIN D29 HPS DDR3 Address 10 SSTL 15 Class 44 Terasic DE1 SoC User Manual www terasic com www terasic com 11 HPS DDR3 A 12 HPS DDR3 A 13 HPS DDR3 A 14 HPS DDR3 BA 0 HPS DDR3 BA 1 HPS DDR3 2 HPS DDR3 CAS n HPS DDR3 CKE HPS DDR3 CK n HPS DDR3 CK p HPS DDR3 CS n HPS DDR3 DM 0 5 DDR3 HPS DD
30. 8 8 8 8 HPS HPS WARM Push Button x4 Slide Switch x10 x1 x1 x1 Figure 2 3 Board Block Diagram Terasic DE1 SoC User Manual www terasic com www terasic co m ANU S RYAN Following is more detailed information about the blocks in Figure 2 3 FPGA Device Cyclone V SoC 5CSEMASF31 Device e Dual core ARM Cortex A9 HPS 85K Programmable Logic Elements e 4 450 Kbits embedded memory Fractional PLLs 2 Hard Memory Controllers Configuration and Debug e Quad Serial Configuration device EPCQ256 on FPGA On Board USB Blaster II Normal type B USB connector Memory Device 64MB 32Mx16 SDRAM on FPGA 1GB 2 256 16 DDR3 SDRAM on HPS e Micro SD Card Socket on HPS Communication e Two Port USB 2 0 Host ULPI interface with USB type A connector UART to USB USB connector 10 100 1000 Ethernet PS 2 mouse keyboard e IR Emitter Receiver 2 Multiplexer Connectors e Two 40 pin Expansion Headers e One 10 pin ADC Input Header One LTC connector One Serial Peripheral Interface SPI Master I2C and one GPIO interface Display Terasic DE1 SoC User Manual www terasic com www terasic com ANU RYAN e 24 bit VGA DAC Audio e 24 bit CODEC Line in line out and microphone in jacks Video Input e TV Decoder NTSC PAL SECAM and TV in connector ADC e Fast throughput rate 1 MSPS e Channel nu
31. C30 PIN AD26 PIN AC27 PIN AD25 PIN AC25 PIN AB28 PIN AB25 PIN AB22 PIN AA24 PIN Y23 PIN Y24 PIN W22 PIN W24 PIN V23 PIN W25 PIN V25 PIN AA28 PIN Y27 PIN AB27 PIN AB26 PIN AA26 PIN AA25 Seven Segment Digit O 1 Seven Segment Digit 0 2 Seven Segment Digit 0 3 Seven Segment Digit 0 4 Seven Segment Digit 0 5 Seven Segment Digit O 6 Seven Segment Digit 1 0 Seven Segment Digit 1 1 Seven Segment Digit 1 2 Seven Segment Digit 1 3 Seven Segment Digit 1 4 Seven Segment Digit 1 5 Seven Segment Digit 1 6 Seven Segment Digit 2 0 Seven Segment Digit 2 1 Seven Segment Digit 2 2 Seven Segment Digit 2 3 Seven Segment Digit 2 4 Seven Segment Digit 2 5 Seven Segment Digit 2 6 Seven Segment Digit 3 0 Seven Segment Digit 3 1 Seven Segment Digit 3 2 Seven Segment Digit 3 3 Seven Segment Digit 3 4 Seven Segment Digit 3 5 Seven Segment Digit 3 6 Seven Segment Digit 4 0 Seven Segment Digit 4 1 Seven Segment Digit 4 2 Seven Segment Digit 4 3 Seven Segment Digit 4 4 Seven Segment Digit 4 5 Seven Segment Digit 4 6 Seven Segment Digit 5 0 Seven Segment Digit 5 1 Seven Segment Digit 5 2 Seven Segment Digit 5 3 Seven Segment Digit 5 4 Seven Segment Digit 5 5 Seven Segment Digit 5 6 25 Terasic DE1 SoC User Manual www terasic com 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3
32. Cable 25 Power DC Adapter 12V ou ane il ES yt E to v S e 9 St Figure 1 1 The DE1 SoC package contents Terasic DE1 SoC User Manual www terasic com www terasic com ANU RYAN The DEI SoC package includes e The DEI SoC development board e DEI SoC Quick Start Guide e USB Cable Type A to B for FPGA programming and control e USB Cable Type A to Mini B for UART control 12V DC power adapter 1 2 DE1 SoC System CD The DEI SoC System CD contains all DEI SoC documentation and supporting materials including the User Manual System Builder reference designs and device datasheets User can download this System CD from the link http del soc terasic com 1 3 Getting Help Here are the addresses where you can get help if you encounter any problems e Altera Corporation e 101 Innovation Drive San Jose California 95134 USA Email university altera com e Terasic Technologies 9F No 176 Sec 2 Gongdao 5th Rd East Dist Hsinchu City 30070 Taiwan Email support terasic com Tel 886 3 575 0880 Web del soc terasic com Terasic DE1 SoC User Manual www terasic com www terasic com Chapter 2 Introduction of the DE 1 SoC Board This chapter presents the features and design characteristics of the board 2 1 Layout and Components A photograph of the board is shown in Figure 2 1 It depicts the layout of the board and indicates the location of
33. Connection 0 22 GPIO Connection 0 23 GPIO Connection 0 24 GPIO Connection 0 25 GPIO Connection 0 26 GPIO Connection 0 27 GPIO Connection 0 28 GPIO Connection 0 29 GPIO Connection 0 30 GPIO Connection 0 31 GPIO Connection 0 32 GPIO Connection 0 33 GPIO Connection 0 34 GPIO Connection 0 35 GPIO Connection 1 0 GPIO Connection 1 1 GPIO Connection 1 2 GPIO Connection 1 3 GPIO Connection 1 4 GPIO Connection 1 5 GPIO Connection 1 6 GPIO Connection 1 7 GPIO Connection 1 8 GPIO Connection 1 9 GPIO Connection 1 10 GPIO Connection 1 11 27 Terasic DE1 SoC User Manual www terasic com 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V www terasic com GPIO 1 12 PIN AH27 GPIO Connection 1 12 3 3V GPIO 1 13 PIN AJ27 GPIO Connection 1 13 3 3V GPIO 1 14 PIN AK29 GPIO Connection 1 14 3 3V GPIO 1 15 PIN AK28 GPIO Connection 1 15 3 3V GPIO 1 16 PIN AK27 GPIO Connection 1 16 3 3V GPIO 1 17 PIN AJ26 GPIO Connection 1 17 3 3V GPIO 1 18 PIN AK26 GPIO Connection 1 18 3 3V GPIO 1 19 PIN AH25 GPIO Connection 1 19 3 3V GPIO 1 20 PIN AJ25 GPIO Connection 1 20 3 3V GPIO 1 21 PIN AJ24 GPIO Connection 1 21 3 3V GPIO 1 22 PIN AK24 GPIO Connection 1 22 3 3V GPIO 1 23 PIN AG23 GPIO Connectio
34. Controller Figure 3 12 Block diagram of the clock distribution Table 3 5 Pin Assignments for Clock Inputs PIN 50 MHz clock input PIN_AA16 50 MHz clock input PIN 50 MHz clock input 3 PIN_Y26 PIN Kia 50 MHz clock input PIN_D25 25 MHz clock input 3 3V 3 6 Interface on FPGA This section describes the interfaces to the FPGA Users can control or monitor the different interfaces with user logic on the FPGA Terasic DE1 SoC User Manual www terasic com 20 www terasic com ANU RYAN 3 6 1 User Push buttons Switches and LEDs on FPGA The board provides four push button switches connected to FPGA as shown in Figure 3 13 Connections between the push button and Cyclone V SoC FPGA Each of these switches is debounced using a Schmitt Trigger circuit as indicated in Figure 3 14 The four outputs called KEYO KEY 1 KEY2 and KEY3 of the Schmitt Trigger devices are connected directly to the Cyclone V SoC FPGA Each push button switch provides a high logic level when it is not pressed and provides a low logic level when depressed Since the push button switches are debounced they are appropriate for using as clock or reset inputs in a circuit VCC3P3 KEYO ws ADIERA w15 Y16 KEY2 74HC245 Figure 3 13 Connections between the push button and Cyclone V SoC FPGA n hbutton depressed released Before o TTL LT UUU Schmitt Trigger Debounced
35. DDR3 Data 11 HPS DDR3 Data 12 HPS DDR3 Data 13 HPS DDR3 Data 14 HPS DDR3 Data 15 HPS DDR3 Data 16 HPS DDR3 Data 17 HPS DDR3 Data 18 HPS DDR3 Data 19 HPS DDR3 Data 20 HPS DDR3 Data 21 HPS DDR3 Data 22 HPS DDR3 Data 23 HPS DDR3 Data 24 HPS DDR3 Data 25 HPS DDR3 Data 26 HPS DDR3 Data 27 45 Terasic DE1 SoC User Manual www terasic com SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class Differential 1 5 V SSTL Class Differential 1 5 V SSTL Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class www terasic com ANU RYAN HPS DDR3_DQ 28 PIN R27 HPS DDR3 Data 28 SSTL 15 Class HPS DDR3_DQ 29 PIN R26 HPS DDR3 Data 29 SSTL 15 Class HPS DDRS3 DQ 30 PIN V30 HPS DDR3 Data 30 SSTL 15 Class HPS DDRS3 DQ 31 PIN W29 HPS DDR3 Data 31 SSTL 15 Class HPS DDRS3
36. D_DACLRCK DACLRCK AUD_ADCDAT ADCDAT AUD_ADCLRCK ADCLRCK Figure 3 19 Connections between FPGA and Audio CODEC Table 3 12 Audio CODEC Pin Assignments Signal Name FPGA Pin No Description AUD ADCLRCK PIN K8 Audio CODEC ADC LR Clock AUD ADCDAT PIN K7 Audio CODEC ADC Data AUD DACLRCK H8 Audio CODEC DAC LR Clock AUD DACDAT PIN J7 Audio CODEC DAC Data AUD XCK 97 Audio CODEC Chip Clock AUD_BCLK PIN H7 Audio CODEC Bit Stream Clock 12C_SCLK PIN 412 or PIN E23 12 Clock 12C_SDAT PIN_K12 or PIN_C24 2 Data 3 6 5 2 Multiplexer The DEI SoC board implements I2C multiplexer so that HPS can access the 12 bus originally owned by FPGA Figure 3 20 shows the connection of I2C multiplexer HPS will own I2C bus and then can access Audio CODEC and TV Decoder when the HPS I2C CONTROL signal 15 set to high By default FPGA owns the I2C bus The FPGA pin assignments of I2C bus are listed in Table 3 13 29 Terasic DE1 SoC User Manual www terasic com Mic In Line In BJ Line Out J3 O Standard 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V www terasic com 12 Bus 55 23157 Switch_Control FPGA I2C HPS ARM Figure 3 20 Connections of I2C Multiplexer Table 3 13 I2C Bus Pin Assignments Signal Name FPGA Pin No Description 2 SCLK PIN_J12 FPGA I2C Clock F
37. EC with line in line out and microphone in jacks e VGA DAC 8 bit high speed triple DACs with VGA out connector Decoder NTSC PAL SECAM and TV in connector PS 2 mouse keyboard connector receiver and IR emitter e Two 40 pin Expansion Header with diode protection e A D Converter 4 pin SPI interface with FPGA 6 Terasic DE1 SoC User Manual www terasic com www terasic com ANU RYAN B HPS Hard Processor System e 800MHz Dual core ARM Cortex A9 MPCore processor DDR3 SDRAM 32 bit data bus Gigabit Ethernet PHY with RJ45 connector 2 port USB Host Normal Type A USB connector e Micro SD card socket e Accelerometer I2C interface interrupt UART to USB USB Mini B connector e Warm reset button and cold reset button e user button and one user LED e LIC 2x7 expansion header 2 2 Block Diagram of the DE1 SoC Board Figure 2 3 gives the block diagram of the board To provide maximum flexibility for the user all connections are made through the Cyclone V SoC FPGA device Thus the user can configure the FPGA to implement any system design Normal Type B JTAG x4 PS 2 x39 m sb m m eee db B USB Host Normal SDRAM x16 64MBMB 40 pin GPIO 40 pin GPIO SCSEMASF31C6N DDR3 SDRAM x16 64 MB FPGA HPS I2C x2 From HPS switch Control 2x7 LTC Header x10 x42 10 xi
38. GA part through Lightweight HPS to FPGA Bridge B A brief view on FPGA manager The FPGA manager in HPS can configure the FPGA fabric from the HPS monitor the state of the FPGA and drive or sample signals to or from the FPGA fabric We provide application software to configure FPGA through the FPGA manager The FPGA configure data is stored in the file with rbf extension Before executing the application software on HPS users should check the MSEL 4 0 is set as 01010 or O1110 B Function Block Diagram Figure 7 1 shows the diagram of this demonstration The HPS use Lightweight HPS to FPGA AXI Bridge to communicate with FPGA The HPS translate data to the FPGA through the Iwaxi bridge 97 Terasic DE1 SoC User Manual www terasic com www terasic com ANU RYAN The hardware in FPGA part is built in Qsys The data translate through Lightweight HPS to FPGA Bridge 15 converted into Avalon MM master interface So the IP PIO controller and HEX Controller works as the Avalon MM slave in the system They control the pins related to the LED and HEX to change the LED and HEX s state This 15 similar to the system using NIOS II processor to control LED and HEX HPS FPGA Qsys LED 9 0 HEX 5 0 Figure 7 1 HPS Control FPGA LED and HEX B LED and HEX control The Lightweight HPS to FPGA Bridge is a peripheral of the HPS The software running on linux operation system can t access the physical address of the HPS perip
39. ISO Cyclone y E24 LTC SoC a2 HPS I2C2 SDAT Connector T HPS I2C2 SCLK HPS HPS LTC GPIO H17 HPS SPIM MOSI U41 nd HPS I2C2 SDAT HPS SPIM CLK LJ HPS I2C2 SCLK MOSI_SDA HPS_LTC_GPIO 4 TS3A5018 Figure 3 36 Connections between the LTC Connector and HPS Table 3 31 LTC Connector Pin Assignments Signal Name FPGA Pin No VO Standard HPS LTC GPIO PIN_H17 HPS LTC GPIO HPS I2C2 SCLK PIN HPSI2C2 Clock share bus with 49 Terasic DE1 SoC User Manual www terasic com www terasic com ANU RYAN HPS I2C2 SDAT HPS SPIM CLK HPS SPIM MISO HPS SPIM MOSI HPS SPIM SS Terasic DE1 SoC User Manual www terasic PIN A25 PIN C23 PIN E24 PIN D22 PIN D24 G Sensor HPS 12 2 Data share bus with G Sensor SPI Clock SPI Master Input Slave Output SPI Master Output Slave Input SPI Slave Select 50 3 3V 3 3V 3 3V 3 3V 3 3V www terasic com Chapter 4 DE 1 SoC System Builder This chapter describes how users can create a custom design project on the board by using the DEI SoC Software Tool DEI SoC System Builder 4 1 Introduction The DEI SoC System Builder is a Windows based software utility designed to assist users to create a Quartus II project for the board within minutes The generated Quartus II project files include e Quartus II Project File qpf e Quartus II Setting File qsf Top Level Design File v e Synopsis Design Constrai
40. In VGA Out CVBS Output Wes Ww 8 t Vol bel bel bot bet bel bel De Interlace Figure 5 10 Setup for the TV box demonstration ITU R 656 YUV 422 Decoder 5 7 PS 2 Mouse Demonstration We offer this simple PS 2 controller coded in Verilog HDL to demonstrate bidirectional 71 Terasic DE1 SoC User Manual www terasic com www terasic com ANU S RYA communication between PS 2 controller and the device the PS 2 mouse You can treat it as a how to basis and develop your own controller that could accomplish more sophisticated instructions like setting the sampling rate or resolution which needs to transfer two data bytes For detailed information about the PS 2 protocol please perform an appropriate search on various educational web sites Here we give a brief introduction B Outline PS 2 protocol uses two wires for bidirectional communication one clock line and one data line The PS 2 controller always has total control over the transmission line but the PS 2 device generates clock signal during data transmission B Data transmit from the device to controller After sending an enabling instruction to the PS 2 mouse at stream mode the device starts to send displacement data out which consists of 33 bits The frame data 15 cut into three similar slices each of them containing a start bit always zero and eight data bits with LSB
41. Linux Kernel Mode Figure 6 1 Block Diagram of GPIO Demonstration B GPIO Interface Block Diagram The HPS provides three general purpose I O GPIO interface modules Figure 6 2 shows the block diagram of the GPIO Interface GPIO 28 0 is controlled by GPIOO controller and GPIO 57 29 15 controlled by GPIOI controller GPIO 70 58 and input only GPI 13 0 are controlled by GPIO2 controller GPI 13 0 Interface Cortex A9 Subsystem Core Generic Interrupt Controller Interrupt amp gpioO Intr In Control Reset gpio rst n n Manager Register Clock 4 clk Block Manager GPIO 28 0 GPIO 57 29 Interface GPIO 70 58 L4 Peripheral Bus Figure 6 2 Block Diagram of GPIO Interface GPIO Register Block The behavior of I O pin is controlled by the registers in the register block In this demonstration we only use three 32 bit registers 1n the GPIO controller The registers are 86 www terasic com Terasic DE1 SoC User Manual www terasic ANU S RYA pio swporta dr used to write output data to output I O pin pio swporta ddr used to configure the direction of I O pin pio ext porta used to read input data of I O input pin For LED control we use gpio swporta ddr to configure the LED pin as output pin and drive the pin high or low by writing data to the gpio swporta dr register For the gpio swporta ddr regist
42. NS SWITCHES AND LEDS ON FPGA 21 3 6 2 USING THE 7 SEGMENT DISPLAYS cccccssssssseeccecccaeesssecceceeaaeesseeceeeesaeeeseeeceeesaaeasseeeeeeesaaaasseeceeseaaaanseeeeeesaagansseses 24 3 6 3 USING THE 2X20 GPIO EXPANSION HEADERS sssssecccccccsessseeccceecauesseccceeeaaaeseeceeeecauanssecceesssaueaseecceessuananeeeess 26 3 04 USING THE 24 BIT AUDIO CODEC 28 Sons m pL SRL IM IPEEXER 29 H 30 ROME NEC ODER 33 TN PLC 35 POREN RE D 35 3 6 10 SDRAM MEMORY ON FPGA ccccccccssssseececeeceaeseeeeccceeeeaeeeeeeeeeeeeasseeeeeeeeeauaesseeeeeeesaaaesseeeeeeesauanseeeseessaaaneeeees 36 SERIA P E 38 2 0 17 A D CONVERTERAND 2X9 HEADER ENE E AS 40 3 7 INTERFACE ON HARD PROCESSOR SYSTEM 41 SJ I USER PUSH BUTTION AND LED ON HPS PETITUM EO 4 SWRAX GIG ETERNE 42 Nc 43 Od DOR Misi 44 NANIensvbwE 46
43. R3 DM 2 HPS DDR3 DM 3 HPS DDR3 DQ O HPS DDR3 DQ 1 HPS DDR3 DQ 2 HPS DDR3 DQ 3 HPS DDR3 4 HPS DDR3 DQ 5 HPS DDR3 DQ 6 HPS DDR3 DQ 7 HPS DDR3 DQ HPS DDR3 DQ 9 HPS DDR3 DQ 10 HPS DDR3 11 HPS DDR3 DQ 12 HPS DDR3 DQ 13 HPS DDR3 14 HPS DDR3 DQ 15 HPS DDR3 16 HPS DDR3 DQ 17 HPS DDR3 18 HPS DDR3 DQ 19 HPS DDR3 DQ 20 HPS DDR3 DQ 21 HPS DDR3 DQ 22 HPS DDR3 DQ 23 HPS DDR3 24 HPS DDR3 DQ 25 HPS DDR3 DQ 26 HPS DDR3 27 PIN C30 PIN B30 PIN C29 PIN H25 PIN E29 PIN J24 PIN J23 PIN E27 PIN L29 PIN L23 PIN M23 PIN H24 PIN K28 PIN M28 PIN R28 PIN W30 PIN K23 PIN K22 PIN H30 PIN G28 PIN L25 PIN L24 PIN J30 PIN J29 PIN K26 PIN L26 PIN K29 PIN K27 PIN M26 PIN M27 PIN L28 PIN M30 PIN U26 PIN T26 PIN N29 PIN N28 PIN P26 PIN P27 PIN N27 PIN R29 PIN P24 PIN P25 PIN T29 PIN T28 HPS DDR3 Address 11 HPS DDR3 Address 12 HPS DDR3 Address 13 HPS DDR3 Address 14 HPS DDR3 Bank Address 0 HPS DDR3 Bank Address 1 HPS DDR3 Bank Address 2 DDR3 Column Address Strobe HPS DDR3 Clock Enable HPS DDR3 Clock HPS DDR3 Clock p HPS DDR3 Chip Select HPS DDR3 Data Mask 0 HPS DDR3 Data Mask 1 HPS DDR3 Data Mask 2 HPS DDR3 Data Mask 3 HPS DDR3 Data 0 HPS DDR3 Data 1 HPS DDR3 Data 2 HPS DDR3 Data 3 HPS DDR3 Data 4 HPS DDR3 Data 5 HPS DDR3 Data 6 HPS DDR3 Data 7 HPS DDR3 Data 8 HPS DDR3 Data 9 HPS DDR3 Data 10 HPS
44. RAM Address 1 3 9V SDRAM Address 2 3 3 SDRAM Address 3 3 3 SDRAM Address 4 SDRAM Address 5 3 9V SDRAM Address 6 33V SDRAM Address 7 3 3V SDRAM Address 8 3 3 SDRAM Address 9 1 SDRAM Address 10 3 39V SDRAM Address 11 13 3 SDRAM Address 12 3 3 SDRAM Data 0 33V SDRAM Data 1 SDRAM Data 2 33V SDRAM Datea 3 q3 39V SDRAM Data 4 3 3V SDRAM Data 5 43 3V SDRAM Data 6 3 3V 31 wwwW terasic com ANU RYA DRAM DQ 7 PIN AJ11 SDRAM Data 7 3 3V DRAM DQ 8 PIN AH10 SDRAM Data 8 3 3V DRAM DQ 9 PIN AJ10 SDRAM Data 9 3 3V DRAM DQ 10 PIN AJ9 SDRAM Data 10 3 3V DRAM DOQ 11 PIN AH9 SDRAM Data 11 3 3V DRAM DQ 12 PIN 8 SDRAM Data 12 3 3V DRAM DQ 13 PIN AH7 SDRAM Data 13 3 3V DRAM_DQ 14 PIN AJ6 SDRAM Data 14 3 3V DRAM DQ 15 PIN AJ5 SDRAM Data 15 3 3V DRAM BA 0 PIN AF13 SDRAM Bank Address 0 3 3V DRAM 1 PIN AJ12 SDRAM Bank Address 1 3 3V DRAM LDQM PIN AB13 SDRAM byte Data Mask 0 3 3V DRAM UDOM PIN AK12 SDRAM byte Data Mask 1 3 3V DRAM RAS N PIN AE13 SDRAM Row Address Strobe 3 3V DRAM CAS N PIN AF11 SDRAM Column Address Strobe 3 3V DRAM CKE PIN AK13 SDRAM Clock Enable 3 3V DRAM CLK PIN AH12 SDRAM Clock 3 3V DRAM WE N PIN AA13 SDRAM Write Enable 3 3V DRAM CS N PIN AG11 SDRAM Chip Select 3 3V 3 6 11 PS 2 Serial Port The DEI SoC board includes a standard PS 2 interface and a connector for a PS 2 keyboard or mouse Figure 3 27 shows the sc
45. SMI Device Figure 3 9 Programming a Quad Serial Configuration Device with the SFL Solution 3 3 Board Status Elements The board includes status LEDs Please refer to Table 3 3 for the status of the LED indicator Table 3 3 LED Indicators Board Reference LED Name Di4 mv Power Illuminates when 12 V power is active TXD when data from FT232R to USB Host RD ABTEXD illuminates when data from Muminates when data from USB Host to FT282R Host to FT232R JTAG RX Reserved 3 4 Board Reset Elements The board equips two HPS reset circuits See Figure 3 10 Table 3 4 shows the buttons references and its descriptions Figure 3 11 shows the reset tree on the board 17 Terasic DE1 SoC User Manual www terasic com www terasic co m i H HPS WARM RST n iilii E HPS RESET Figure 3 10 Board Reset Elements 3 4 Reset Elemen 3 4 miii Elements Board Reference Signal Name KEYS HPS _ RESET to o the HPS Ethernet PHY and USB host device Active low that will reset all HPS logics that reset KEY7 HPS_ WARM_RST_ Warm reset to the HPS block Active low input affects the system reset domains which allows debugging to operate 18 Tasic Terasic DE1 SoC User Manual www terasic com T ADEA Ja Oe V aa USB Blaster JTAG Connector PIN 6 VCC3P3 C
46. SWAP Leu Um 47 ENNIO EN e T 48 1 Terasic DE1 SoC User Manual www terasic com ANU RYAN 3 1 5 LIC CONNECTOR 49 4 DE1 SOC SYSTEM BUILDER eeiesicivsscus soetevuexe ose esa Feu Coe pa eer er CES 51 INTRODUCTION 51 ZA Gino DESICN FLOW 51 4 3 USING DE1 SOC SYSTEM BUIEDEB uo tut ute E Dung piu E tust weg ex ed du ead 232 CHAPTER 5 EXAMPLES FOR EPUA qm 58 5 1 DE I SOC FACTORY CONFIGURATION EA ENA REE 58 2 2 AUDIO RECORDING AND PLAYING nare EE AEE AEEA EEEE 59 5 3 A KARAOKE MACHINE sscsccsccscescecceccsccscesceccsccscesceccecescescescscesceecescsecesesceecsececescescescssessescscsscssescscescesessuscaseucs 62 E eg rd VU MN TE aE E EA 64 ateg a e a AE AA EA A AA 67 GE BO DEMO IRA TO EE EEE EE EET 69 5 7 PS 2 MOUSE DEMONSTRATION cccssceccecceccscecceccsccsceccecceccscecescsccscesceecesesc
47. SYNC N Table 3 16 Pin Assignments for VGA FPGA Pin No PIN A13 PIN C13 PIN E13 PIN B12 PIN C12 PIN D12 PIN E12 PIN F13 PIN J9 PIN J10 PIN H12 PIN G10 PIN G11 PIN G12 PIN F11 PIN E11 PIN B13 PIN G13 PIN H13 PIN F14 PIN H14 PIN F15 PIN G15 PIN J14 PIN A11 PIN F10 PIN B11 PIN D11 PIN C10 3 6 7 TV Decoder The DEI SoC board is equipped with an Analog Device ADV7180 TV decoder chip The ADV7180 is an integrated video decoder that automatically detects and converts a standard analog baseband television signals NTSC PAL and SECAM into 4 2 2 component video data compatible with the 8 bit ITU R BT 656 interface standard The ADV7180 is compatible with a broad range of video devices including DVD players tape based sources broadcast sources and security surveillance cameras Terasic DE1 SoC User Manual www terasic com Description VGA Red 0 VGA Red 1 VGA Red 2 VGA Red 3 VGA Red 4 VGA Red 5 VGA Red 6 VGA Red 7 VGA Green 0 VGA Green 1 VGA Green 2 VGA Green 3 VGA Green 4 VGA Green 5 VGA Green 6 VGA Green 7 VGA Blue 0 VGA Blue 1 VGA Blue 2 VGA Blue 3 VGA Blue 4 VGA Blue 5 VGA Blue 6 VGA Blue 7 VGA Clock VGA BLANK VGAH SYNC VGAV SYNC VGA SYNC 33 O Standard 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V www terasic com ANU RYAN
48. Testdemo batch After Nios II program is downloaded and executed successfully a prompt message will be displayed in nios2 terminal Press KEY3 KEYO of the DEI SoC board to start SDRAM verify process Press KEYO for continued test The program will display progressing and result information as shown in Figure 5 7 66 Terasic DE1 SoC User Manual www terasic com www terasic com Altera Nios I EDS 13 0 Using cable DE So0C USB 11 device 1 instance HxHH Resetting and pausing target processor OK Initializing cache amp if present OK Downloaded 61KB in 1s Werified OK Starting processor at address Hx2ZBH2H1B4 nios2 terminal connected to hardware target using JTAG UART on cable nins2 terminal DE SoG 5 8 1 1 device 1 instance mnios2 terminal Use the IDE stop button or Ctrl C to terminate SDRAM Test Size 64NB Clock 1466000060 gt Press any KEV to start test for continued test gt SDRAM Testing Iteration 1 write 1H 26 304 48 58x 8H Hz 1982 read uerifu 1H 205 382 48 5H ec C fe Figure 5 7 Display Progress and Result Information for the SDRAM Demonstration 5 5 SDRAM RTL Test This demonstration presents a memory test function on the bank of SDRAM on the DEI SoC board The memory size of the SDRAM bank is 64MB and all the test codes on this demonstration are written in Verilog HDL B Function Block Diagram Figure 5 8
49. The registers in the TV decoder be programmed by a serial 12 bus which is connected to HPS or Cyclone V SoC FPGA through an 2C multiplexer as indicated in Figure 3 23 Note that the I2C address W R of the TV decoder U4 is 0x40 0x41 The pin assignments are listed in Table 3 17 Detailed information of the ADV7180 is available on the manufacturer s website or in the DE1_SOC_datasheets Video Decoder folder on the DEI SoC System CD ADV7180 TD DATA T 0 TD VS TD HS J6 me e J TD RESET y Soc RCA JACK I2C_SDAT Y1 Figure 3 23 Connections between FPGA and TV Decoder Table 3 17 TV Decoder Pin Assignments Signal Name FPGA Pin No Description Standard TD DATA 0 PIN D2 TV Decoder Data 0 3 3V TD_DATA 1 PIN B1 TV Decoder JData 1 3 3V TD DATA 2 PIN E2 TV Decoder Data 2 3 3V TD DATA 3 PIN B2 TV Decoder Data 3 3 3V TD DATA 4 PIN D1 TV Decoder Data 4 3 3V TD DATA 5 PIN E1 TV Decoder Data 5 3 3V TD DATA 6 PIN C2 TV Decoder Data 6 3 3V TD DATA 7 PIN B3 TV Decoder Data 7 3 3V TD HS PIN A5 TV Decoder H SYNC 3 3V TD VS PIN A3 TV Decoder V SYNC 3 3V TD CLK27 PIN H15 TV Decoder Clock Input 3 3V TD RESET N PIN F6 TV Decoder Reset 3 3V 2 SCLK PIN J12 or PIN E23 I2C Clock 3 3V I2C_SDAT PIN_K12 or PIN_C24 I2C Data 3 3V 34 Terasic DE1 SoC User Manual www terasic com www terasic com ANU RYA 3 6 8 IR Receiver The board provides an infrare
50. able 3 25 LED Mode Pin Definition LED State LED Definition Link Activity LEDG LEDY LEDG LEDY H H OFF OFF Link off L H ON OFF 1000 Link No Activity Toggle H Blinking OFF 1000 Link Activity RX TX H L OFF ON 100 Link No Activity H Toggle OFF Blinking 100 Link Activity RX TX L L ON ON 10 Link No Activity Toggle Toggle Blinking Blinking 10 Link Activity RX TX 3 7 3 UART The board has one UART interface connected for communication with the HPS This interface wouldn t support HW flow control signals The physical interface is done using UART USB onboard bridge from an FT232R chip and connects to the host using an USB Mini B connector For detailed information on how to use the transceiver please refer to the datasheet which 15 available on the manufacturer s website or in the Datasheets UART TO USB folder on the DEI SoC System CD Figure 3 32 shows the related schematics and Table 3 26 lists the pin assignments of HPS in Cyclone V SoC FPGA 43 Terasic DE1 SoC User Manual www terasic com www terasic com INDERA FT232_DP HPS FT232 DM USB Mini B Connector HPS RESET n o MB FT232R Figure 3 32 Connections between the Cyclone V SoC FPGA and FT232R Chip Table 3 26 UART Interface I O Signal Name FPGA Pin No Description Standard HPS UART RX PIN B25 HPS UART Receiver 3 3V HPS UART TX PIN C25 HPS UART Transmitter 3 3V HPS CONV USB PIN B15 Reserve 3 3V 3 7
51. at is stored in the serial configuration device Both types of programming methods are described below JTAG programming In this method of programming named after the IEEE standards Joint Test Action Group the configuration bit stream is downloaded directly into the Cyclone V SoC FPGA The FPGA will retain this configuration as long as power 15 applied to the board the configuration information will be lost when the power is turned off 11 Terasic DE1 SoC User Manual www terasic com www terasic com ANU RYAN 2 AS programming In this method called Active Serial programming the configuration bit stream is downloaded into the quad serial configuration device EPCQ256 It provides non volatile storage of the bit stream so that the information is retained even when the power supply to the DE1 SoC board is turned off When the board s power is turned on the configuration data in the EPCQ256 device is automatically loaded into the Cyclone V SoC FPGA B JTAG Chain on DE1 SoC Board To use interface for configuring the FPGA device the chain on DEI SoC must form a closed loop that allows Quartus II programmer to detect FPGA device Figure 3 2 illustrates the JTAG chain on DEI SoC board Extemal JTAG Header Installed FPGA _ FPGA FPGA_TDI wu Mini B Connector Figure 3 2 The JTAG chain on the board B Configuring the FPGA in JTAG Mode There are two devices FPGA and HPS on
52. ata 3 3V PIN G17 HPS USB PHY Reset 3 3V PIN C15 Stop Data Stream on the Bus 3 3V ADXL345 and HPS The associated pin assignments are listed in Table 3 30 ANU S RYA SoC HPS HPS I2C1 SCLK HPS I2C1 SDAT HPS GSENSOR INT U28 SCL SCLK SDA SDI SDIO INT1 ADXL345 Figure 3 35 Connections between Cyclone V SoC FPGA and G Sensor Signal Name HPS GSENSOR INT Terasic DE1 SoC User Manual www terasic Table 3 30 G Sensor Pin Assignments FPGA Pin No Description Standard PIN B22 HPS GSENSOR Interrupt Output 3 3V 48 www terasic com ANU RYAN HPS I2C1 SCLK PIN 23 HPSI2C Clock share bus with LTC 3 3V HPS I2C1 SDAT PIN C24 HPS I2C Data share bus 3 7 8 LTC Connector The board allows connection to interface card from Linear Technology The interface 1s implemented using al4 pin header that can be connected to a variety of demo boards from Linear Technology It will be connected to SPI Master and I2C ports of the HPS to allow bidirectional communication with two types of protocols The 14 pin header will allow for GPIO SPI and 2 extension for user purposes if the interfaces to Linear Technology board aren t in use Connections between the LTC connector and the HPS are shown in Figure 3 36 and the functions of the 14 pins is listed in Table 3 31 VCC9 VCC3P3 ey m C23 __ HPS 5 SS D24 S RYAN 022 HPS_SPIM_MOSI HPS SPIM M
53. atures 64MB of SDRAM implemented using a 64MB 32Mx16 SDRAM device The device consists of 16 bit data line control line and address line connected to the FPGA This chip use the 3 3V LVCMOS signaling standard Connections between FPGA and SDRAM are shown in Figure 3 26 while the pin assignments are listed in Table 3 20 36 Terasic DE1 SoC User Manual www terasic com www terasic com Cyclone Signal DRAM_ADDR 0 DRAM ADDR 1 DRAM ADDR DRAM ADDR 3 DRAM_ADDR 4 DRAM ADDR 5 DRAM ADDRIS DRAM ADDR 7 DRAM ADDR DRAM ADDR g9 DRAM ADDR 10 DRAM ADDR 11 DRAM ADDR 12 DRAM DQ O DRAM DQ 1 DRAM DQ DRAM DQ 3 DRAM DO 4 DRAM DQ 5 DRAM DQ 6 Terasic DE1 SoC User Manual www terasic com SoC 32Mx16 SDRAM DRAM DQ 5 0 PS DRAM ADDR 12 0 DRAM BA 1 0 NEN DRAM CLK CK DRAM CKE CKE DRAM_LDQM LDOM DRAM_UDQM UDQM DRAM_WE_N AWE DRAM_CAS_N CAS DRAM RAS N ARAS DRAM_CS_N ncs Figure 3 26 Connections between FPGA and SDRAM Table 3 20 SDRAM Pin Assignments FPGA Pin No PIN_AK14 PIN_AH14 PIN AG15 PIN AE14 PIN AB15 PIN AC14 AD14 PIN AF15 PIN AH15 PIN AG13 PIN AG12 PIN AH13 PIN AJ14 PIN AK6 PIN AJ7 PIN AK7 PIN AK8 PIN AK9 PIN AG10 PIN AK11 O Standard Description SDRAM Address 0 33V SD
54. audio recorder and player using the DEI SoC board with the built in Audio CODEC chip This demonstration is developed based on Qsys and Eclipse Figure 5 2 shows the man machine interface of this demonstration Two push buttons and four slide switches are used for users to configure this audio system SWO is used to specify recording source to be Line in or MIC In SWI SW2 and SW3 are used to specify recording sample rate as 96K 48K 44 1K 32K or 8K Table 5 1 and Table 5 2 summarize the usage of Slide switches for configuring the audio recorder and player 59 Terasic DE1 SoC User Manual www terasic com www terasic com 917 ase Ej 23 gg E CIE t 518 5507 3 Ciis 1 ae LI o el e is 7 nfi o Ki 47 sess Men a 188 BH f 1 i y B 245 H a as Li Tut aH e Audio Source Play MIC or LINE IN Sample Rate Record Figure 5 2 Man Machine Interface of Audio Recorder and Player Figure 5 3 shows the block diagram of the Audio Recorder and Player design There are hardware and software parts in the block diagram The software part stores the Nios II program in the on chip memory The software part is built by Eclipse in C programming language The hardware part is built by Qsys under Quartus II The hardware part inclu
55. com www terasic ANU RYAN In this demo code the following mask is defined to control LED and KEY direction LED s output value define USER IO DIR OxO 1000000 define BIT_LED OxO 1000000 define BUTTON MASK 0x02000000 The following statement can be used to configure the LED associated pins as output pins alt setbits word virtual base Cuint32 t ALT SWPORTA DDR ADDR amp uint32 t HW REGS MASK USER IO DIR The following statement can be used to turn on the LED alt setbits word virtual base Cuint32 t ALT SWPORTA DR ADDR amp uint32 t HW REGS MASK LED The following statement can be used to read the content of gpio ext porta register The bit mask is used to check the status of the key alt read word virtual base 011132 ALT GPIO1 EXT PORTA ADDR amp uint32 t REGS MASK B Demonstration Source Code e Build tool Altera SoC EDS V13 1 e Project directory Demonstration SoC hps_gpio e Binary file hps_gpio Build command make make clean to remove all temporal files e Execute command hps_gpio 90 Terasic DE1 SoC User Manual www terasic com www terasic com B Demonstration Setup e Connect the USB cable to the USB to UART connector J4 on the DEI SoC board and host PC e Make sure the executable file hps_gpio is copied into the SD card under the hom
56. cute the demo batch file DEI SoC SDRAM RTL Test bat under the batch file folder DEI SoC SDRAM RTL Test demo batch e Press KEYO on the DEI SoC board to start the verification process When KEYO is pressed the LEDs LEDR 2 0 should turn on At the instant of releasing KEYO LEDRI LEDR2 should start blinking After approximately 8 seconds LEDRI should stop blinking and stay on to indicate that the SDRAM has passed the test respectively Table 5 3 lists the LED indicators e If LEDR2 is not blinking it means 5OMHz clock source is not working e If LEDRI fail to remain on after 8 seconds the corresponding SDRAM test has failed e Press KEYO again to regenerate the test control signals for a repeat test Table 5 3 LED Indicators Table 5 ANAME Description LEDRO Reset LEDR1 If light SDRAM test pass LEDR2 Blinks 5 6 TV Box Demonstration This demonstration plays video and audio input from a DVD player using the VGA output audio CODEC and one TV decoder on the DEI SoC board Figure 5 9 shows the block diagram of the design There are two major blocks in the circuit called I2C_AV_Config and The TV_to_VGA block consists of the ITU R 656 Decoder SDRAM Frame Buffer YUV422 to YUV444 YCbCr to RGB and VGA Controller The figure also shows the TV Decoder ADV7180 and the VGA DAC ADV7123 chips used As soon as the bit stream is downloaded into the FPGA the register values of the Decoder chip are used to c
57. d MAX V devices Figure 8 8 Erasing setting in Quartus Il programmer window Click Start to erase the serial configuration device 108 asic Terasic DE1 SoC User Manual www terasic com www terasic com 9 Appendix 9 1 Revision History Change Log Initial Version Preliminary Copyright 2014 Terasic Technologies All rights reserved 109 Terasic DE1 SoC User Manual www terasic com www terasic com
58. d remote control receiver module model IRM V538 TR1 whose datasheet is offered in the Datasheets IR Receiver and Emitter folder on DEI SoC System CD The accompanied remote controller with an encoding chip of uPD6121G is very suitable of generating expected infrared signals Figure 3 24 shows the related schematic of the IR receiver Table 3 18 shows the IR receiver interface pin assignments VCC3P3 IRDA_RXD JNO S RA 7 GND CHASSIS Figure 3 24 Connection between FPGA and IR Receiver Table 3 18 Pin Assignments for IR Signal Name FPGA Pin No Description vO Standard IRDA_RXD PIN AA30 IR Receiver 3 3V 3 6 9 IR Emitter LED The board provides an IR Emitter LED for IR communication which is widely used for operating the television device wirelessly from a short line of sight distance Match this IR Emitter LED with an IR receiver will allow the board to communicate with similarly equipped system Figure 3 25 shows the related schematic of the IR emitter LED Table 3 19 shows the IR emitter interface pin assignments 35 Terasic DE1 SoC User Manual www terasic com www terasic com VCC3P3 IR Emitter LED IRDA_TXD N NOTS B4AN HE8050G amp O Figure 3 25 Connection between FPGA and IR Emitter LED Table 3 19 Pin Assignments for IR Signal Name FPGA Pin No Description IRDA_TXD PIN AB30 3 6 10 SDRAM Memory on FPGA The board fe
59. demonstration CC V ANA 89HI q8 SCLK I I2C SDAT Demonstration Source Code e Project directory DEI SoC TV e Bit stream used DEI SoC TV sof Demonstration Batch File Demo Batch File Folder 1 SoC TV Memo batch The demo batch file includes the following files e Batch File DEI SoC TV bat FPGA Configure File DEI SoC TV sof Demonstration Setup File Locations and Instructions e Connect a DVD player s composite video output yellow plug to the Video In RCA jack J6 of 70 Terasic DE1 SoC User Manual www terasic com www terasic ANU RYAN the DE1 SoC board See Figure 5 10 The DVD player has to be configured to provide e NTSC output e 60Hz refresh rate e 4 3 aspect ratio e Non progressive video Connect the VGA output of the DEI SoC board to a VGA monitor both LCD and CRT type of monitors should work e Connect the audio output of the DVD player to the line in port of the DEI SoC board and connect a speaker to the line out port If the audio output jacks from the DVD player are RCA type then an adaptor will be needed to convert to the mini stereo plug supported on the DEI SoC board this is the same type of plug supported on most computers e Load the bit stream into FPGA by execute the batch file DEI SoC TV bat under DE SoC TV Memo batch folder Press KEYO on the DEI SoC board to reset the circuit VGA LCD CRT Monitor dicc Video
60. des all the other blocks The AUDIO Controller is a user defined Qsys component It 1s designed to send audio data to the audio chip or receive audio data from the audio chip The audio chip is programmed through I2C protocol which is implemented in C code The I2C pins from audio chip are connected to Qsys System Interconnect Fabric through PIO controllers In this example the audio chip is configured in Master Mode The audio interface 1s configured as I2S and 16 bit mode 18 432MHz clock generated by the PLL is connected to the MCLK XTI pin of the audio chip through the AUDIO Controller 60 Terasic DE1 SoC User Manual www terasic com joeuuoo1eju 5 Clock to SDRAM 4 milium p d LED KEY 4 ISWII2C Figure 5 3 Block diagram of the audio recorder and player Demonstration Setup File Locations and Instructions Hardware Project directory DEI SoC Audio Bit stream used DEI SoC Audio sof Software Project directory DEI SoC AudioNsoftware Connect an Audio Source to the LINE IN port of the DEI SoC board Connect a Microphone to MIC IN port on the DEI SoC board Connect a speaker or headset to LINE OUT port on the DEI SoC board Load the bit stream into FPGA note 1 Load the Software Execution File into FPGA note 1 Configure audio with the Slide switches SWO as shown in Table 5 1 Press KEY3 on the DEI SoC board to start stop audio recording note 2 Pre
61. e can skip this step The following statement is used to set the output state of the PIO alt write word h2p lw led addr Mask The Mask in this statement decides which bit in the data register of the PIO IP is high or low The bits in data register decide the output state of the pins connected to the LEDs The program for the HEX controlling is similar to the LED Since the linux operate system support mult thread software The software for this system creates two threads one for controlling the LED and the other for controlling the HEX We can use the system call pthread create to complete the job The function is called in the main function and a sub thread is created The program running in the sub thread is to control the led flashing in a loop And the main thread in the main function is to control the digital shown on the HEX changing in a loop The LED and HEX s state changing at the same time when the FPGA 15 configured and the software is running on HPS B Demonstration Source Code Build tool Altera SoC EDS V13 1 e Project directory Demonstration SoC_FPGA HPS_LED_HEX e Quick file directory Demonstration SoC_FPGA HPS_LED_HEX quickfile e FPGA Configure File soc_system_dc rbf Binary file HPS_LED_HEX and hps config fpga e Build app command make make clean to remove all temporal files Execute command hps_config_fpga soc system dc rbf and HPS_LED_HEX Demonstration Setup Make sure Quartus II
62. e root folder in Linux e Insert the booting micro SD card into the DEI SoC board e Power on the DEI SoC board Launch PuTTY to connect to the UART port of DEI SoC board and type root to login Altera Yocto Linux e Inthe UART terminal of PuTTY execute hps_gpio to start the program Figure 6 6 Putty window HPS LED will flashing 2 times first and the user can control the user LED with user Button e Press KEY to light up HPS LED Press CTRL C to terminate the application 6 3 I2C Interfaced G sensor This demonstration shows how to control the G sensor by accessing its registers through the built in I2C kernel driver in Altera Soc Yocto Powered Embedded Linux B Function Block Diagram Figure 6 7 shows the function block diagram of this demonstration The G sensor on the DEI SoC board is connected to the 12 0 controller in HPS The G Sensor I2C 7 bit device address is 0x53 The system I2C bus driver is used to access the register files in the G sensor The G sensor interrupt signal 1s connected to the PIO controller In this demonstration we use polling method to read the register data so the interrupt method 15 not introduced here 91 Terasic DE1 SoC User Manual www terasic com www terasic com FPGA SoC DDR3 ARM Program Linux User Mode HPS I2C CLK I2C SDA G Sensor Linux Kernel Mode I2C address 0x53 Interrupt Figure 6 7 Block Diagram of the G sensor Demonstrat
63. ent for the DEI SoC board The LED is connected to HPS_GPIO53 KEY is connected to HPS_GPIO54 which are controlled by the GPIO1 controller which also controls HPS GPIO29 HPS GPIOS57 HPS_GPIO54 21 KEY 24 HPS LED HPS GPIOS53 Figure 6 4 LED and KEY Pin Assignment Figure 6 5 shows the gpio swporta ddr register of the GPIOI controller The bit O controls the pin direction of HPS_GPIO29 The bit 24 controls the pin direction of HPS_GPIO53 which connects to the HPS_LED the bits 25 controls the pin direction of HPS_GPIO54 which connects to the HPS_KEY and so on In summary the pin direction of HPS_LED HPS_KEY are controlled by the bit 24 bit 25 in the gpio swporta ddr register of the GPIOI controller respectively Similarly the output status of HPS LED is controlled by the bit 24 in the gpio swporta dr register of the GPIOI controller The status of KEY can be queried by reading the value of the bit 24 in the ext porta register of GPIOI controller GPIO1 Controller gpio swporta ddr register Controls the Direction of HPS GPIO29 Controls the Direction of HPS GPIO30 Controls the Direction of HPS GPIO31 Controls the Direction of 5 GPIOS3 HPS LED Controls the Direction of HPS GPIOS54 HPS KEY Controls the Direction of HPS_GPIO55 Controls the Direction of HPS GPIO56 Controls the Direction of HPS GPIO57 Figure 6 5 swporta ddr Register in the GPIO1 80 Terasic DE1 SoC User Manual www terasic
64. er the first bit least significant bit controls direction of the first IO pin in the associated GPIO controller and the second bit controls the direction of second IO pin in the associated GPIO controller and so on The value 1 in the register bit indicates the I O direction 1s output and the value 0 in the register bit indicates the I O direction is input For the gpio swporta dr register the first bit controls the output value of first I O pin in the associated GPIO controller and the second bit controls the output value of second I O pin in the associated GPIO controller and so on The value 1 in the register bit indicates the output value is high and the value 0 indicates the output value 15 low The status of KEY can be queried by reading the value of gpio ext porta register The first bit represents the input status of first IO pin in the associated GPIO controller and the second bit represents the input status of second IO pin in the associated GPIO controller and so on The value in the register bit indicates the input state 15 high and the value 0 indicates the input state 15 low B GPIO Register Address Mapping The registers of HPS peripherals are mapped to HPS base address space OXFC000000 with 64K B size Registers of GPIOI controller are mapped to the base address OXFF208000 with 4KB size and registers of GPIO2 controller are mapped to the base address OxFF20A000 with 4KB size as shown in Figure 6 3 87 Te
65. esceecsecscesceeceeceesesescescesescescesctscssescascuseucs 71 5 8 IR EMITTER LED AND RECEIVER DEMONSTRATION csccscosceccecceccscsceccscesccecescecescescescscescescscsscssescescescssessescescucs 74 Pe ese cd acs Semmes cece tale 80 CHAPTER EXAMPLES POR HPS SOC ANANN EEANN Aa 83 Gy Ty PROGRAM eee oda 83 Dy cc ee se 85 6 3 I2C INTERFACED G SENSOR csccscesceccecceccsccceccscescecceccecescuecescuceeceecsecesescescaeceecectsceecescscsecescescssescescasceseesescuscescass 91 M CE 94 CHAPTER7 EXAMPLES FOR USING BOTH HPS SOC AND 97 OTR Oe HEA MI 97 CHAPTER8 STEPS OF PROGRAMMING THE QUAD SERIAL CONFIGURATION DEVICE 101 Fl BAG OU eee ee ee ee 101 2 CONVERT SOF TO JIC 101 8 3 WRITE FILE INTO QUAD SERIAL CONFIGURATION DEVICE 106 8 4 ERASE THE QUAD SERIAL CONFIGURATION DEVICE cccccceseccesecececcceseccuneccauececueccceneceeeceueeceeeeceseneeeanestenecenes 107 COA APPENDIN aA
66. formation AMA i ae dod At MET NT d Cyclone Soc dH 2 ES H E 8025 4 29 eim len Imm o n Mes e n Figure 5 21 ADC Reading hardware setup 82 Terasic DE1 SoC User Manual www terasic com www terasic com Chapter 6 Examples for HPS SoC This chapter provides a number of C code examples based on the Altera SoC Linux built by Yocto Project These examples provide demonstrations of the major features which connected to HPS interface on the board such as users LED KEY I2C interfaced G sensor and 2 MUX All of the associated files can be found in Demonstrations SOC folder in the DEI SoC System CD To run Linux on DEI SOC Please refer to the chapter 5 Running Linux on the DE1 SoC board on DEI SoC Getting Started Guide pdf B Installation of the Demonstrations To install the demonstrations on your computer Copy the directory Demonstrations into a local directory of your choice Altera SoC EDS v13 1 is required for users to compile the c code project 6 1 Hello Program This demonstration presents how to develop your first HPS program by using Altera SoC EDS tool For operation details please refer to My First HPS pdf in the system CD Here are the major procedures to develop and build HPS project Make sure Altera SoC EDS is installed on your PC Create program c h files with a generic te
67. gure 4 3 Project Name Type in an appropriate name here it will automatically be assigned as the name of your top level design entity 53 Terasic DE1 SoC User Manual www terasic com www terasic com DE1 SoC V1 0 0 E ter UNIVERSITY www terasic com PROGRAM DE1 SoC FPGA Board 7 Seqment x 6 LED x 10 Switch x 10 Button x 4 iv IR TX RX iV VGA Video In Audio ADC SDRAM 32MB PS2 HPS GPIO 0 Header Noe r Prefix Name GPIO 1 Header Save Setting Generate Prefix Name Load Setting Exit Figure 4 3 Board Type and Project Name B System Configuration Under the System Configuration users are given the flexibility of enabling their choice of included components on the board as shown in Figure 4 4 Each component of the board is listed where users can enable or disable a component according to their design by simply marking a check or removing the check in the field provided If the component is enabled the DEI SoC System Builder will automatically generate the associated pin assignments including the pin name pin location pin direction and I O standard 54 Terasic DE1 SoC User Manual www terasic com www terasic com DE1 SoC V1 0 0 NO S RYAN ter PAT System Configuration i Project Name PROGRAM www terasic com DEI SOC DE1 SoC FPGA Board CLOCK 4 7 Seqment x 6 LEDx10 4 Switch x 10 Button x 4
68. hematic of the PS 2 circuit In addition users can use the PS 2 keyboard and mouse on the DE1 SoC board simultaneously by plugging an extension PS 2 Y Cable See Figure 3 28 Instructions for using a PS 2 mouse or keyboard can be found by performing an appropriate search on various educational websites The pin assignments for the associated interface are shown in Table 3 21 Q Note If users connect only one PS 2 equipment the PS 2 interface between FPGA 1 0 should be PS2 CLK and PS2 DAT 38 wwwW terasic com Terasic DE1 SoC User Manual www terasic ADT PS2 CLK IS Ps2 JNO YAN Soc Ae 2_ 2 PS2_DAT Figure 3 27 Connection between FPGA and PS 2 A E Figure 3 28 Y Cable use for both Keyboard and Mouse Table 3 21 PS 2 Pin Assignments FPGA Pin No Description Standard PIN AD7 PS 2 Clock 3 3V PIN AE7 PS 2 Data 3 9 PS 2 Clock reserved for second PS 2 device 3 PIN AEQ PS 2 Data reserved for second PS 2 device 3 3V 39 Terasic DE1 SoC User Manual www terasic com www terasic com JA DTE RYAN 3 6 12 A D Converter and 2x5 Header The DE1 SoC contains AD7928 a lower power eight channel CMOS 12 bit analog to digital converter This A to D provides conversion throughput rates up to IMSPS The analog input range for all input channels can extend from 0 V to 2 5 V or 0 V to 5V as selected via the RANGE bit in the control
69. heral You must map the physical address to the user space at first then you can access to the peripheral or you can write a device driver module and add it to the kernel We only show the first method to the users in this demonstration We actually map in the entire CSR span of the HPS since we want to access various registers within that span If the users want to access any other peripherals whose physical address is in this span they can reuse the mapping function and the macro we defined below define HW REGS BASE ALT STM OFST define HW REGS SPAN 0x04000000 define HW REGS MASK HW REGS SPAN 1 The Iwaxi bridge start address after being mapped can be get using the ALT_LWFPGASLVS_OFST which is defined in altera hps hardware library Then the slave IP connected to the lwaxi bridge can be accessed through the base address and the register offset in these IPs For instance the base address of PIO slave IP in this system is 0x0001 0040 and the direction control register offset 15 0x01 the data register offset is 0x00 The following statement be used to get the base address of PIO slave IP 98 Terasic DE1 SoC User Manual www terasic com www terasic com h2p_lw_led_addr virtual_base unsigned long ALT_LWFPGASLVS_OFST LED_PIO_BASE amp unsigned long HW_REGS_MASK In this demonstration we just need to set the PIO s direction as output which is the default direction of the PIO IP so w
70. ion B 2 Driver Here is the list of procedures in order to read a register value from G sensor register files by using the existing I2C bus driver in the system 1 Open I2C bus driver dev 12c 0 file 2 0 O_RDWR 2 Specify G sensor s I2C address 0x53 ioctl file 2C_SLAVE 0x53 3 Specify desired register index in g sensor write file amp Addr8 sizeof unsigned char 4 Read one byte register value read file amp Data8 sizeof unsigned char Because the G sensor I2C bus is connected to the I2CO controller as shown in the Figure 6 8 the given driver name is dev 12c 0 I2CO SCL E23 HPS 12C1 SCLK 2 0 SDA C24 HPS I2C1 SDAT Figure 6 8 Schematic of I2C To write a value into a register developer can change step 4 to write file amp Data8 sizeof unsigned char To read multiple byte values developer can change step 4 to read file amp szData8 sizeof szData8 where szData 15 an array of bytes 92 Terasic DE1 SoC User Manual www terasic com www terasic com ANU S RYA To write multiple byte values developer can change step 4 to write file amp szData8 sizeof szData where szData is an array of bytes B G sensor Control The ADI ADXL345 provides I2C and SPI interfaces I2C interface is used by setting the CS pin to high on this DEI SoC board The ADI ADXL345 G sensor provides user selectable resolution up to 13 bit 16g The resolution can
71. ion SoC my_first_hps Binary file my_first_hps e Build Command make make clean to remove all temporary files e Execute Command my_first_hps B Demonstration Setup e Connect USB cable to the USB to UART connector J4 on the DEI SoC board and host PC e Make sure the demo file my first hps is copied into the SD card under the home root folder in Linux e Insert the booting micro SD card into the DEI SoC board e Power on the DEI SoC board e Launch PuTTY to connect to the UART port of Putty and type root to login Altera Yocto Linux e Inthe UART terminal of PuTTY type my_first_hps to start the program and you will see Hello World message in the terminal 6 2 Users LED and KEY This demonstration presents how to control the users LED and KEY by accessing the register of GPIO controller through the memory mapped device driver The memory mapped device driver allows developer to access the system physical memory B Function Block Diagram Figure 6 1 shows the function block diagram of this demonstration The users LED and KEY are connected to the GPIOI controller in HPS The behavior of the GPIO controller is controlled by the register in the GPIO controller The registers can be accessed by application software through the memory mapped device driver which is built into Altera SoC Linux 85 Terasic DE1 SoC User Manual www terasic com www terasic com FPGA SoC DDR3 ARM Program HPS Linux User Mode
72. logic into the project and compile the project to generate the SRAM Object File sof 37 Terasic DE1 SoC User Manual www terasic com www terasic com Chapter 5 Examples For FPGA This chapter provides a number of examples of advanced circuits implemented by RTL or Qsys on the DEI SoC board These circuits provide demonstrations of the major features which connected to FPGA interface on the board such as audio SDRAM and IR receiver of the associated files can be found in the Demonstrations FPGA folder on the DEI SoC System CD B Installing the Demonstrations To install the demonstrations on your computer Copy the directory Demonstrations into a local directory of your choice It 15 important to ensure that the path to your local directory contains no spaces otherwise the Nios II software will not work Note Quartus II v13 or later is required for all DE1 SoC demonstrations to support Cyclone V SoC device 5 1 DE1 SoC Factory Configuration The DEI SoC board is shipped from the factory with a default configuration bit stream that demonstrates some of the basic features of the board The setup required for this demonstration and the locations of its files are shown below B Demonstration Setup File Locations and Instructions e Project directory DEI SoC Default e Bit stream used DEI SoC Default sof or DEI SoC Default jic e Power on the DEI SoC board with the USB cable connected to the USB Blaster port
73. mber 8 e Resolution 12 bits Analog input range 0 2 5 V or 0 5V as selected via the RANGE bit in the control register Switches Buttons and Indicators e 5 User Keys FPGA x4 HPS x1 e 10 User switches FPGA x10 11 User LEDs FPGA x10 HPS x 1 e 2 HPS Reset Buttons HPS RESET n HPS WARM RST n e Six 7 segment displays Sensors G Sensor on HPS Power 12V DC input Terasic DE1 SoC User Manual www terasic com www terasic com Chapter 3 Using the DE1 SoC Board This chapter gives instructions for using the board and describes each of its peripherals 3 1 FPGA Configuration Mode Setting When the DEI SoC board is powered on the FPGA can be configured from EPCQ or HPS The MSEL 4 0 pins are used to specify the configuration scheme The MSEL 4 0 is implemented as 6 pin DIP switch SW10 on the DEI SoC board as shown in Figure 3 1 The dip 6 on SW10 is not used ie H E PS TEM EM NEL _ gt ite Ree o SW10 1 SEM EM M OM OM ESI Figure 3 1 The JTAG chain on the board Table 3 1 shows the relation between MSEL 4 0 and DIP switch in 5 10 10 Terasic DE1 SoC User Manual www terasic com www terasic com Table 3 1 SW10 FPGA Configuration Mode Switch Board Reference Signal Name Description Default SW10 1 MSELO On 0 SW10 2 MSEL1 Off 1 Use these pins to set the FPGA SW10 3 MSEL2 i On 0 configuration scheme
74. mmand 12 switch B Demonstration Setup e Connect the USB cable to the USB to UART connector J4 on the DEI SoC board and host PC e Make sure the executable file i2c switch is copied into the SD card under the home root folder 1n Linux e Insert the booting micro sdcard into the DEI SoC board e Power on the DEI SoC board e Launch PuTTY to connect to the UART port of DEI SoC borad and type root to login Yocto Linux e Inthe UART terminal of PuTTY execute 12 switch to start the 2 MUX test e The demo program will show the result in the Putty as shown in Figure 6 11 Figure 6 11 Terminal output of the I2C MUX Test Demonstration Press CTRL C to terminate the program 96 Terasic DE1 SoC User Manual www terasic com www terasic com Chapter 7 Examples for using both HPS SoC and FGPA Although the HPS and the FPGA can operate independently they are tightly coupled via a high bandwidth system interconnect built from high performance ARM AMBA AXITM bus bridges Both FPGA fabric and HPS can access to each other via these interconnect bridges This chapter provides demonstrations for how to using these bridges that can achieve superior performance and lower latency when compared to solutions containing a separate FPGA and discrete processor 7 1 HPS Control LED and HEX This demonstration presents using HPS to configure FPGA through FPGA manager in HPS and control the LED and HEX on the FP
75. mplemented in the FPGA As Figure 5 17 show it includes Code Detector State Machine and Shift Register First the IR receiver demodulates the signal inputs to Code Detector block The Code Detector block will check the Lead Code and feedback the examination result to State Machine block The State Machine block will change the state from IDLE to GUIDANCE once the Lead code 15 detected Once the Code Detector has detected the Custom Code status the current state will change from GUIDANCE to DATAREAD state At this state the Code Detector will save the receiving data and output to Shift Register then displays it on 7 segment displays Figure 5 18 shows the state shift diagram of State Machine block Note that the input clock should be 50MHz IR Signal Cod State Machine Figure 5 17 The IR Receiver controller 78 Terasic DE1 SoC User Manual www terasic com End Code Lead Code Custom Code Figure 5 18 State shift diagram of State Machine Demonstration Source Code e Project directory DEI SoC IR e Bitstream used DEI SOC IR sof Demonstration Batch File Demo Batch File Folder SoC IR demo batch The demo batch file includes the following files e Batch File DEI SoC IR bat FPGA Configure File DEI SOC IR sof Demonstration Setup File Locations and Instructions the bit stream into FPGA by executing DEI IR demo DEI SoC IR bat Press KEY 0 to enable the continuously patte
76. n 1 23 3 3V GPIO 1 24 PIN AK23 GPIO Connection 1 24 3 3V GPIO 1 25 PIN AH23 GPIO Connection 1 25 3 3V GPIO 1 26 PIN AK22 GPIO Connection 1 26 3 3V GPIO 1 27 PIN AJ22 GPIO Connection 1 27 3 3V GPIO 1 28 PIN AH22 GPIO Connection 1 28 3 3V GPIO 1 29 PIN AG22 GPIO Connection 1 29 3 3V GPIO 1 30 PIN AF24 GPIO Connection 1 30 3 3V GPIO 1 31 PIN AF23 GPIO Connection 1 31 3 3V GPIO 1 32 PIN AE22 GPIO Connection 1 32 3 3V GPIO 1 33 PIN AD21 GPIO Connection 1 33 3 3V GPIO 1 34 PIN AA20 GPIO Connection 1 34 3 3V GPIO 1 35 PIN AC22 GPIO Connection 1 35 3 3V 3 6 4 Using the 24 bit Audio CODEC The DEI SoC board provides high quality 24 bit audio via the Wolfson WM8731 audio CODEC Encoder Decoder This chip supports microphone in line in and line out ports with a sample rate adjustable from 8 kHz to 96 kHz The WMS731 is controlled via a serial I2C bus which 1s connected to HPS or Cyclone V SoC FPGA through a I2C multiplexer A schematic diagram of the audio circuitry is shown in Figure 3 19 and the FPGA pin assignments are listed in Table 3 12 Detailed information for using the WM8731 codec is available in its datasheet which can be found on the manufacturer s website or in the DEI SOC datasheetsvVAudio CODEC folder on the DEI SoC System CD 28 www terasic com Terasic DE1 SoC User Manual www terasic ANU S RYA Cyclone SoC WMS8731 LE XTI MCLK AUD_BCLK BCLK AUD_DACDAT DACDAT AU
77. n or middle button is pressed Table 5 5 gives the detailed information Table 5 5 Detailed information of the indicators Indicator Name Description LEDR O Left button press indicator Right button press indicator LEDR 2 Middle button press indicator byte of X displacement HEX1 High byte of X displacement HEX2 byte of Y displacement HEX3 High byte of Y displacement 5 8 IR Emitter LED and Receiver Demonstration In this demonstration we show a simple example of using IR Emitter LED and IR receiver AII the codes in this demonstration are coding by verilog HDL 74 Terasic DE1 SoC User Manual www terasic com www terasic IR RX IR Controller Receiver Six HEXs IR Rmote Figure 5 12 Block Diagram of the IR Emitter LED and Receiver Demonstration Figure 5 12 shows the block diagram of the design It mainly implement a IR TX Controller and a IR RX Controller When is pressed Data test pattern generator continuously generates data to the IR TX Controller When IR TX Controller works it will format the sending data into NEC IR transmission protocol and send it out through IR emitter LED IR receiver will decode the received data and display it on six HEXs Also user can use a remote controller to sending data to IR Receiver The main function of IR TX RX controller and IR remote in this demonstration will be
78. ndow 5 Search altera com Tiree Enable real time ISP to allow background programming for MAX and MAX V devices File Device Checksum Usercode Program Verify Blank Examine Configure Check ipli Start Factory default enhanced 5 5 O0C79AEC 00C79AEC D altera 13 1 outpu 256 9736BC5A FI Auto Detect lt none gt SOCVHPS 00000000 lt none gt Stop Add Change File E Save File 23 Add Device J Down Figure 8 7 Quartus Il programmer window with one JIC file 8 4 Erase the Quad Serial Configuration Device To erase the existed file in the serial configuration device follow the steps listed below Choose Programmer Tools menu and the Chain cdf window appears Click Auto Detect and then select correct device both FPGA device and HPS will detected See Figure 8 6 Double click the green rectangle region as shown in Figure 8 6 the Select New Programming File page will appear and then select the correct JIC file Erase the serial configuration device by clicking the corresponding Erase box a Factory default SFL image will be load See Figure 8 8 107 Terasic DE1 SoC User Manual www terasic com www terasic com D gt Programmer Chain1 cdf File Edit View Processing Tools Window Help 5j sess T Enable real time ISP to allow background programming for MAX II an
79. nt for displaying numbers of various sizes As indicated in the schematic in Figure 3 17 the seven segments common anode are connected to pins on Cyclone V SoC FPGA Applying a low logic level to a segment will light it up and applying a high logic level turns it off Each segment in a display 15 identified by an index from to 6 with the positions given in Figure 3 17 Table 3 9 shows the assignments of FPGA pins to the 7 segment displays HEXO 0 HEXO 1 HEXO 3 Soc 5 a Figure 3 17 Connections between the 7 segment display and Cyclone V SoC FPGA Table 3 9 Pin Assignments for 7 segment Displays FPGA Pin No Description Standard PIN AE26 Seven Segment Digit 0 0 3 3V Signal Name 0 24 www terasic com Terasic DE1 SoC User Manual www terasic com HEXO 1 HEXO 2 HEXO 3 HEXO 4 HEXO 5 HEXO 6 HEX1 0 HEX1 1 HEX1 2 HEX1 3 HEX1 4 HEX1 5 HEX1 6 2 0 2 1 HEX2 2 HEX2 3 HEX2 4 HEX2 5 2 6 HEX3 0 HEX3 1 HEX3 2 HEX3 3 HEX3 4 HEX3 5 HEX3 6 HEXA 0 HEX4 1 HEX4 2 4 3 HEX4 4 HEXA 5 4 6 HEX5 0 HEX5 1 HEX5 2 HEX5 3 HEX5 4 HEX5 5 HEX5 6 PIN AE27 PIN AE28 PIN AG27 PIN AF28 PIN AG28 PIN AH28 PIN AJ29 PIN AH29 PIN AH30 PIN AG30 PIN AF29 PIN AF30 PIN AD27 PIN AB23 PIN AE29 PIN AD29 PIN AC28 PIN AD30 PIN AC29 PIN A
80. nts file sdc e Pin Assignment Document htm By providing the above files the DEI SoC System Builder prevents occurrence of situations that are prone to errors when users manually edit the top level design file or place pin assignments The common mistakes that users encounter are the following 1 Board damage due to wrong pin bank voltage assignments 2 Board malfunction caused by wrong device connections or missing pin counts for connected ends 3 Performance degradation due to improper pin assignments 4 2 General Design Flow This section will introduce the general design flow to build a project for the development board via the DEI SoC System Builder The general design flow is illustrated in Figure 4 1 51 Terasic DE1 SoC User Manual www terasic com www terasic com ANU RYAN Users should launch the DEI SoC System Builder and create a new project according to their design requirements When users complete the settings the DEI SoC System Builder will generate two major files a top level design file v and a Quartus II setting file qsf The top level design file contains top level Verilog HDL wrapper for users to add their own design logic The Quartus II setting file contains information such as FPGA device type top level pin assignment and the I O standard for each user defined I O pin Finally the Quartus II programmer must be used to download SOF file to the development board using a JTAG interface
81. o restore default setting load a setting and save users board configuration file shown in Figure 4 6 Users can save the current board configuration information into a cfg file and load it to the DEI SoC System Builder 56 Terasic DE1 SoC User Manual www terasic com www terasic com DE1 SoC V1 0 0 System Confiquration ter UNIVERSITY x Project Name SP Oa SOC DE1 SoC FPGA Board CLOCK 7 Seqment x 6 LED x 10 4 Switch x 10 Button x 4 iv IR TXIRX iV VGA v Video In Audio ADC SDRAM 32MB PS2 FE HPS GPIO 0 Header None Prefix Name GPIO 1 Header Save Setting Generate Prefix Name Load Setting Exit Figure 4 6 Project Settings B Project Generation When users press the Generate button the DEI SoC System Builder will generate the corresponding Quartus II files and documents as listed in the Table 4 1 Table 4 1 The files generated by DE1 SoC System Builder 0 Filename Description lt Project name gt v Top level Verilog HDL file for Quartus Il M Project name gt qpf Quartus II Project File Wi Project name gt qsf Quartus II Setting File 4 Project name gt sdc Synopsis Design Constraints file for Quartus 5 lt Project name gt htm Pin Assignment Document Users use Quartus software to add custom
82. oC User Manual www terasic com www terasic com ANU RYA After the power on cycle of the PS 2 mouse it enters into stream mode automatically and disable data transmit unless an enabling instruction is received Figure 5 11 shows the waveform while communication happening on two lines Sending command CLK Inhibit qst 2nd gth 10th 11 CLK CLK CLK CLK CLK eooo ee Start bit BitO Bit7 Parity bit Stop Line bit control bit Receiving data CLK 15 2nd 1 oth 1 qth CLK CLK CLK CLK i Start bit Bit0 Bit7 Parity bit Stop bit Figure 5 11 Waveforms on two lines while communication taking place Demonstration Source Code e Project directory DE1_SoC_PS2_DEMO e Bit stream used DEI SoC PS2 DEMO sof Demonstration Batch File Demo Batch File Folder DEI SoC PS2 DEMO Memo batch 73 Terasic DE1 SoC User Manual www terasic com ANU RYA The demo batch file includes the following files e Batch File DEI SoC 52 DEMO bat FPGA Configure File DEI SoC PS2 DEMO sof Demonstration Setup File Locations and Instructions the bit stream into FPGA by executing DEI SoC PS2 DEMO Memo batch DEI SoC PS2 DEMO bat e Plug in the PS 2 mouse Press KEY 0 for enabling data transfer Press KEY 1 to clear the display data cache e You should see digital changes on 7 segment display when the PS 2 mouse moves and the LEDR 2 0 will blink respectively when the left button right butto
83. octo Linux Inthe UART terminal of PuTTY execute gsensor to start the gsensor polling e The demo program will show the X Y and Z values in the Putty as shown in Figure 6 9 Press CTRL C to terminate the program ar cy oy Figure 6 9 Terminal output of the G sensor Demonstration 6 412C MUX Test This demonstration shows how to switch the I2C multiplexer so that HPS can access the I2C bus originally owned by FPGA B Function Block Diagram Figure 6 10 shows the function block diagram of this demonstration The I2C bus from both FPGA and HPS are connected to an 2C multiplexer I2C multiplexer is controlled by HPS I2C CONTROL which connected to GPIO1 controller in HPS The HPS is connected to the I2C0 controller in HPS Gsensor is also connected to I2CO controller See Figure 6 9 FPGA SoC DDR3 ARM Program FPGA_I2C HPS Linux User Mode 2 Mux HPS 2 Linux Kernel Mode Figure 6 10 Block Diagram of the 2 MUX Test Demonstration HPS I2C CONTROL TV nw Decoder 94 Terasic DE1 SoC User Manual www terasic com www terasic ANU S RYA B HPS CONTROL Control HPS CONTROL is connected to HPS 48 bit 19 of GPIOI controller HPS will own I2C bus and then can access Audio CODEC and TV Decoder when the HPS I2C CONTROL signal is set to high In this demo code the following mask is defined to control HPS I2C CONTROL direction and thei
84. onfigure the TV decoder via I2C_AV_Config block which uses the I2C protocol to communicate with the TV Decoder chip Following the power on sequence the TV Decoder chip will be unstable for a time period the Lock Detector is responsible for detecting this instability The ITU R 656 Decoder block extracts YcrCb 4 2 2 YUV 4 2 2 video signals from the ITU R 656 data stream sent from the TV Decoder It also generates a data valid control signal indicating the valid period of data output Because the video signal from the TV Decoder is interlaced we need to perform de interlacing on the data source We used the SDRAM Frame Buffer and a field selection multiplexer MUX which is controlled by the VGA controller to perform the de interlacing operation Internally the VGA Controller generates data request and odd even selection signals to the SDRAM Frame Buffer and filed selection multiplexer MUX The YUV422 to YUV444 block 69 Terasic DE1 SoC User Manual www terasic com www terasic com RYA converts the selected 4 2 2 YUV 4 2 2 video data to the YcrCb 4 4 4 YUV 4 4 4 video data format Finally the YcrCb_to_RGB block converts the YcrCb data into RGB data output The VGA Controller block generates standard VGA synchronous signals VGA_HS and VGA VS to enable the display on a VGA monitor FPGA YUV 422 Data Valid o Control the Figure 5 9 Block diagram of the TV box
85. program the serial configuration device with the JIC file that you just created add the file to the Quartus Programmer window and follow the steps When the SOF to JIC file conversion is complete add the JIC file to the Quartus Programmer window Choose Programmer Tools menu and the Chain cdf window appears Click Auto Detect and then select correct device both FPGA device and HPS will detected See Figure 8 6 Double click the green rectangle region as shown in Figure 8 6 the Select New Programming File page will appear and then select the correct JIC file Program the serial configuration device by clicking the corresponding Program Configure box a factory default SFL image will be loaded See Figure 8 7 Click Start to program serial configuration device Programmer Chain2 cdf e mm File Edit View Processing Tools Window Help 3 Enable real time ISP to allow background programming for and MAX V devices m Device Checksum Usercode Program Verify Blank eu Start Configure Check SCSEMAS Stop SOCVHPS 00000000 lt none gt Auto Detect 35 Add File Change File ill Save File Figure 8 6 Quartus programmer window with two detected devices 106 Terasic DE1 SoC User Manual www terasic com www terasic ANU S 1 Programmer Chaini cdf jm File Edit View Processing Tools Wi
86. r output value HPS I2C CONTROL 0 00080000 The following statement can be used to configure 5 122 CONTROL associated pins as output pin alt setbits word virtual base uint32_t ALT GPIOI SWPORTA DDR ADDR amp uint32 t HW REGS MASK I2C CONTROL The following statement can be used to set HPS5 12 CONTROL high alt setbits word virtual base Cuint32 t ALT SWPORTA DR ADDR amp uint32 t HW REGS MASK I2C CONTROL The following statement can be used to set IZ2C CONTROL low alt clrbits word virtual base Cuint32 t ALT SWPORTA DR ADDR amp uint32_t HW REGS MASK I2C CONTROL B 2 Driver Here 15 the list of procedures in order to read register value from TV Decoder by using the existing I2C bus driver in the system Set 5 DC CONTROL high so that HPS can access I2C bus Open I2C bus driver dev 12c 0 file open dev 12c 0 O_RDWR Specify ADV7180 s address 0x20 ioctl file I2C_SLAVE 0x20 Read or write registers set HPS I2C CONTROL low to release I2C bus B Demonstration Source Code 95 Terasic DE1 SoC User Manual www terasic com www terasic com e Build tool Altera SoC EDS v13 1 Project directory Demonstration SoC hps_i2c_switch Binary file 12c_switch Build command make make clean to remove all temporal files Execute co
87. rasic DE1 SoC User Manual www terasic com www terasic com eco 48 WB DAP O0xF000000 2MB a ee cANUDATA NAND controller data OxFFZ09000 joe a arre OxFFB80000 TanUvAIA FPGA CANO controller registers controller registers OxFFC01000 Figure 6 3 GPIO Address Map B Software API Developers can use the following software API to access the register of GPIO controller Open use to open memory mapped device driver mmap map physical memory to user space alt read word read a value from a specified register alt write word write a value into a specified register munmap clean up memory mapping close close device driver Developers can also use the following MACRO to access the register alt setbits word set specified bit value to zero for a specified register alt clrbits word set specified bit value to one for a specified register To use the above API to access register of GPIO controller the program must include the following header files include lt stdio h gt include lt unistd h gt include lt fcntl h gt include lt sys mman h gt include hwlib h include socal socal h include socal hps h 88 Tasic Terasic DE1 SoC User Manual www terasic com A A A _ ____ include socal alt_gpio h B LED and KEY Control Figure 6 4 shows the HPS users LED and KEY pin assignm
88. register It can be configured to accept eight input signals at inputs INO through INT7 These eight input signals are connected to the 2x5 header as shown in Figure 3 29 For more detailed information on the A D converter chip please refer to its datasheet which 1s available on manufacturer s website or under the datasheet folder of the system CD VCC5 ADC INO IN1 ADC IN2 ADC_IN3 ADC_IN4 ADC_IN5 ADC IN6 IN7 GND Figure 3 29 Pin distribution of the 2x5 Header Figure 3 30 shows the connections on the 2x5 header A D converter and Cyclone V SoC device 40 Terasic DE1 SoC User Manual www terasic com www terasic AD7928BRUZ ADC_INO ADC_SCLK ADC_IN2 8 7 DIN ADC DOUT 2x5 ADC_IN3 Header ADC_IN4 ADC_CS_N ADC IN5 E 7 Cyclone e V IN6 5 SoC ADC_IN7 Figure 3 30 Wiring for 2x5 header and A D converter Table 3 22 Pin Assignments for ADC i 3V PIN_AK4 Digital data output PIN_AK2 Digital clock input 3 7 Interface on Hard Processor System HPS This section introduces the interfaces connected to the HPS section of the FPGA Users can access these interfaces via the HPS processor 3 7 1 User Push button and LED on HPS Like the FPGA the HPS also features its own set of switches buttons LEDs and other user interfaces Users can control these interfaces for observing HPS status and
89. rn sending out by IR TX Controller e Observe the six HEXs See Table 5 7 for detail e Releasing KEY O to stop the IR TX e Point the IR receiver with the remote controller and press any button e Observe the six HEXs See Table 5 7 for detail And User can using Multi DEI SoC boards to do more IR test between boards 79 Terasic DE1 SoC User Manual www terasic com www terasic Table 5 7 Detailed information of the indicators Indicator Name HEX5 nversed high byte of DATA Key Code HEX4 Inversed low byte of DATA Key Code HEX High byte of DATA KeyCode 2 5 9 ADC Reading This demonstration illustrates steps which can be used to evaluate the performance of the 8 channel 12 bit A D Converter ADC7928 The DC 5 0V on the 2x5 header is used to drive the analog signals and by using a trimmer potentiometer the voltage can be adjusted within the range of 0 5 0V The 12 bit voltage measurements are indicated on the NIOS II console Figure 5 19 shows the block diagram of this demonstration Note that the input voltage range is 0 5 and if your input voltage is 2 5 2 5V you can make the pre scale circuit to adjust their range to 0 5 V FPGA 50 MHz ouqe 12euuooJeju uigjes g 4 ADC Controller qmi 2x5 Header 1 Figure 5 19 ADC Reading Block Diagram 80 Terasic DE1 SoC User Manual www terasic com www terasic co m ANU RYAN Figure 5 20 depicts
90. s for Ethernet PHY Signal Name FPGA Pin No Description I O Standard HPS_ENET_TX_EN PIN A20 GMII and MII transmit enable 3 3V HPS TX 0 PIN F20 MII transmit data 0 3 3V 42 Terasic DE1 SoC User Manual www terasic com www terasic com HPS TX DATA 1 PIN J19 MII transmit data 1 3 3V HPS ENET TX DATA 2 PIN F21 MII transmit data 2 3 3V HPS ENET TX DATA 3 PIN F19 MII transmit data 3 3 3V HPS ENET RX DV PIN K17 GMII and MII receive data valid 3 3V HPS DATA O PIN A21 GMII and MII receive data 0 3 3V HPS ENET RX DATA 1 PIN B20 GMII and MII receive data 1 3 3V HPS ENET RX DATA 2 PIN B18 GMII and MII receive data 2 3 3V HPS DATA 3 PIN 021 GMII and MII receive data 3 3 3V HPS ENET RX CLK PIN G20 GMII and MII receive clock 3 3V HPS ENET RESET N PIN E18 Hardware Reset Signal 3 3V HPS ENET MDIO PIN E21 Management Data 3 3V HPS ENET MDC PIN B21 Management Data Clock Reference 3 3V HPS ENET INT N PIN C19 Interrupt Open Drain Output 3 3V HPS ENET GTX CLK PIN H19 GMII Transmit Clock 3 3V Additionally the Ethernet PHY KSZ9021RNI LED status has been set to two LED mode The LED control signals are connected to LEDs yellow and green on the RJ45 connector States and definitions can be found in Table 3 25 which can display the current status of the Ethernet For example once the green LED lights on the board has been connected to Gigabit Ethernet T
91. ss KEY2 on DEI SoC board to start stop audio playing note 3 Table 5 1 Slide switches usage for audio source Slide Switches 0 DOWN Position 1 UP Position swo Audiois from MIC Audio is from LINE IN 61 Terasic DE1 SoC User Manual www terasic com www terasic co m ANU S RYA Table 5 2 Slide switch setting for sample rate switching for audio recorder and player SW5 SW4 SW3 0 DOWN 0 DOWN 0 DOWN Sample Rate 1 UP 1 UP 1 UP 0 0 0 96K 0 0 1 48K 0 1 0 44 1K 0 1 1 32K 1 0 0 8K Unlisted combination 96K Note 7 Execute DE7 SoC Audio demo_batch DE7 SoC Audio bat will download sof and elf files 2 Recording process will stop if audio buffer is full 3 Playing process will stop if audio data is played completely 5 3 A Karaoke Machine This demonstration uses the microphone in line in and line out ports on the DEI SOC board to create a Karaoke Machine application The WM 8731 CODEC is configured in the master mode with which the audio CODEC generates AD DA serial bit clock BCK and the left right channel clock LRCK automatically As indicated in Figure 5 4 the I2C interface is used to configure the Audio CODEC The sample rate and gain of the CODEC are set in this manner and the data input from the line in port is then mixed with the microphone in port and the result is sent to the line out port For this demonstration the sample rate is set to 48kHz Pressing the pushbu
92. the LED 9 0 will flash the number on the HEX 5 0 will change at the same time Press CTRL C to terminate the program Figure 7 3 Running result in putty 100 Terasic DE1 SoC User Manual www terasic com www terasic com Chapter 8 Steps of Programming the Quad Serial Configuration Device This chapter describes how to program the quad serial configuration device with Serial Flash Loader SFL function via the JTAG interface User can program quad serial configuration devices with a JTAG indirect configuration jic file To generate JIC programming files with the Quartus II software users need to generate a user specified SRAM object file sof which is the input file first Next users need to convert the SOF to a JIC file To convert a SOF to a JIC file in Quartus software follow these steps 8 1 Before you Begin To use the Quad serial flash as a FPGA configuration device please make sure the FPGA should be set in Asx4 mode i e let MSEL 4 0 to be set as 10010 8 2 Convert SOF File to JIC file Choose Convert Programming Files on Quartus window File menu See Figure 8 1 101 Terasic DE1 SoC User Manual www terasic com www terasic Edit View Project Assignments Process Close New Project Wizard Open Project Save Project Close Project cave Ctrl s Save Save All Ctrl Shift 5 File Properties Create Update Convert Programming Files
93. the connectors and key components n c 5 5 VGA Out Mic Line Line VGA HPS Gigabit HPS Ethernet In In Out Video In 24 bit DAC JTAG Header Audio Codec Video Decoder PS2 USB Blaster II Power DC Jack Power ON OFF f 64MB SDRAM TR ADC ADC Header 7 Segment Display LED x10 2121 m Button 4 Switch x10 USB Host UART to USB USB HUB UART to USB Controller Micro SD Card USB PHY Ethernet PHY 2x20 GPIO x2 1GB DDR3 SDRAM with ARM Cortex A9 Accelerometer 2x7 LTC Expansion Header HPS User LED IR out IR in WARM RST HPS User Button HPS RST Figure 2 1 Development Board top view Terasic DE1 SoC User Manual www terasic com www terasic com Configuration Mode Switch EPCQ mi i5 I 3 2 pe PES diee 0E Figure 2 2 Development Board bottom view The DEI SoC board has many features that allow users to implement a wide range of designed circuits from simple circuits to various multimedia projects The following hardware is provided on the board B FPGA e Altera Cyclone SE SCSEMASF31C6N device e Altera Serial Configuration device EPCQ256 e USB Blaster board for programming JTAG Mode e 64MB SDRAM 16 bit data bus e 4 Push buttons 10 Slide switches 10 Red user LEDs Six 7 segment displays e Four 50MHz clock sources from clock generator e 24 bit CD quality audio COD
94. the pin arrangement of the 2x5 header In this demonstration this header is the input source of ADC convertor Users can connect a trimmer to the specified ADC channel ADC_INO ADC_IN7 that provides voltage to the ADC convert Then FPGA will read the associated register in the convertor via serial interface and translates it to voltage value displayed on the NIOS II console ADC_INO ADC_IN2 ADC_IN4 ADC_IN6 VCC5 ADC_IN1 ADC_IN3 ADC_IN5 ADC_IN7 2x5 Box Header Figure 5 20 ADC Pin distribution of the 2x5 Header B System Requirements The following items are required for the ADC Reading demonstration o DEI SoC board x1 o Trimmer Potentiometer x1 o Wire Strip x3 B Demonstration File Locations e Hardware Project directory DEI SoC ADC e Bit stream used DEI SoC ADC sof Software Project directory DEI SoC ADC software e Demo batch file DEI SoC ADCMemo batch DE SoC ADC bat B Demonstration Setup and Instructions e Connect the trimmer to corresponding ADC channel on the 2x5 header as shown in Figure 5 21 to read from as well as the 5V and GND signals Note the setup shown above is connected ADC channel 0 81 Terasic DE1 SoC User Manual www terasic com www terasic com JA DTE RYAN Execute the demo batch file DEI SoC ADC bat to load bit stream and software execution file in FPGA e The NIOS II console will display the voltage of the specified channel voltage result in
95. tton KEYO reconfigures the gain of the audio CODEC via 2 bus cycling within ten predefined gain values volume levels provided by the device 62 Terasic DE1 SoC User Manual www terasic com www terasic com lt lt Line In Bien Push Button Figure 5 4 Block diagram of the Karaoke Machine demonstration B Demonstration Setup File Locations and Instructions e Project directory DEI SOC i2sound e Bit stream used DEI SOC i2sound sof e Connect a microphone to the microphone in port pink color on the DEI SOC board e Connect the audio output of a music player such as player or computer to the line in port blue color on the DEI SOC board e Connect a headset speaker to the line out port green color on the DEI SOC board the bit stream into the FPGA by execute the batch file DEI SOC i2sound under the DE SOC 1i2soundMemo batch folder e You should be able to hear a mixture of the microphone sound and the sound from the music player e Press KEYO to adjust the volume it cycles between volume levels to 9 Figure 5 5 illustrates the setup for this demonstration 63 Terasic DE1 SoC User Manual www terasic com www terasic co m MP3 Any Audio Output TT p P mel a T e M n nnam AAA IOMA li Clock Data Frequency
96. ww terasic com www terasic com JA DTE RYAN Table 3 28 SD Card Socket Pin Assignments Signal Name FPGA Pin No Description Standard HPS_SD_CLK PIN_A16 HPS SD Clock 3 3V HPS SD CMD PIN F18 HPS SD Command Line 3 3V HPS SD DATA O PIN G18 HPS SD Data 0 3 3V HPS SD DATA 1 PIN C17 HPS SD Data 1 3 3V HPS SD DATA 2 PIN D17 HPS SD Data 2 3 3V HPS SD DATA 3 PIN B16 HPS SD Data 3 3 3V 3 7 6 2 port USB Host The board provides 2 port USB 2 0 host interfaces using the SMSC USB3300 controller and 2 port hub controller A SMSC USB3300 device in a 32 pin QFN package device is used to interface to a SMSC USB2512B This device supports UTMI Low Pin Interface ULPI to communicate to USB 2 0 controller in HPS By connecting the ID pin of USB3300 to ground the PHY operates in Host mode When operating in Host mode the interface will supply the power to the device through the 2 port USB type A interface Figure 3 34 shows the schematic diagram of the USB circuitry the pin assignments for the associated interface are listed in Table 3 29 U9 HPS USB DATA 7 0 USB CPEN USB VCC5 DATA T 0 CPEN EN OUT USB EXTVBUS HP USB CLKOUT CLKOUT EXTVBUS FAULT_N S RAN HPS_USB_NXT NXT VBUS USB 5 TPS2553DRVR U2 USBUP DM Cyclone HPS USB DIR USBUP_DM HPS USB STP USBUP DP USBUP DP 5 USBDN1_DP USBDN1_DM USB Type A USBPHY_CLK_24 a _ J7 USBDN2 DP USBDN2 DM com USB Type A
97. ww terasic com waw CED rmm 0 Programmer Chain3 File Edit View Processing Tools Window Help 5 Search altera com sd E Enable real time ISP to allow background programming for MAX II and MAX devices 2 Hardware NET File Device Checksum Usercode Program Verify Blank gt Start Configure Check HT Dom lt none gt ISCSEB NM none socw Delete Dd at IE Change Fie W Save File Add IPS File Chanae IPS File Delete IPS File gt Add PR Programming File Change PR Programming File Delete PR Programming File Attach Flash Device Change Flash Device Delete Flash Device 28 Add Device Change Device fh up p Down Figure 3 6 FPGA JTAG Programming Steps 4 e Select sof file for FPGA as Figure 3 7 My Computer 5 demo batch y A hc output A user x DEL Soc File name Files of type Programming Files sof pof jam jbc ekp jic Figure 3 7 FPGA JTAG Programming Steps 5 e Click Program Configure check box and then click Start button to download sof file into FPGA as Figure 3 8 15 DE1 SoC User Manual www terasic com www terasic com File Edit View Processing Tools Window 5 gt Hardware Setup DE SoC USB 1 Mode JTAG Enable real time ISP to allow
98. xt editor Create a Makefile with a generic text editor Build your project under Altera SoC EDS B Program File Here 15 the main program of this Hello World demo 83 Terasic DE1 SoC User Manual www terasic com www terasic com finclude lt stdio h gt int wainfint char argv 1 printf Hello World sr im returni O B Makefile To compile a project a Makefile is required Here is the Makefile used for this demo TARGET my first CROSS COMPILE arm linux gnueabihf CFLAGS g Wall I SOCEDS DEST ROOT ip altera hps altera hpa hwlib include LDFLAGS g Wall CROSS COMPILE APCH arm build TARGET TARGET main o CC LDFLAGS o 8 c 0 9 CFLAGS c F lt PHONY clean clean rm TARGET 4 f 0 B Compile To compile a project please launch Altera SoC EDS Command Shell by executing C altera 13 1 embedded Embedded_Command_ Shell bat Use the cd command to change the current directory to where the Hello World project is located Then type make to build the project The executable file my_first_hps will be generated after the compiling process is finished The clean all command can be used to remove all temporary files 84 Terasic DE1 SoC User Manual www terasic com www terasic com B Demonstration Source Code e Build Tool Altera SoC EDS v13 1 e Project directory Demonstrat
99. yclone V SoC KEY 7 HPS EH B HPS WARM RST n HPS_NRST WARM_RST HPS_RESET_n m HPS NPOR KEY Jm HPS ENET RESET n HPS RESET n GPIO42 10 100 1000 Base T Ethernet PHY KSZ9021RN RESET_N USB 2 0 OTG PHY USB3300 HPS RESET PHY Inverter RESET Figure 3 11 Reset Tree on the Development Board 3 5 Clock Circuitry Figure 3 12 is a diagram showing the default frequencies of all of the external clocks going to the Cyclone V SoC FPGA A clock generator is used to distribute clock signals with low jitter to FPGA The four distributing 50MHz clock signals are connected to the FPGA that are used for clocking the user logic One distributing 25MHz clock signal is connected to HPS clock inputs the other distributing 25MHz clock signal is connected to the clock input of Gigabit Ethernet Transceiver Two distributing 24MHz clock signals are connected to clock inputs of USB Host OTG PHY and USB Hub controller respectively The associated pin assignments for clock inputs to FPGA I O pins are listed in Table 3 5 19 Terasic DE1 SoC User Manual www terasic com www terasic com 515350 25MHz S RYAN CLOCK_50 50MHz CLOCK2_50 50MHz CLOCK4_50 50MHz CLOCK3 50 50MHz S HPS CLK 25 25MHz ere HPS_CLK2 Gigabit Ethernet ENET 25 25MHz Transceiver USB Host PHY USBPHY_CLK_24 24MHz 2 port Hub USBHUB_CLK_24 24MHz

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