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SAK-TC1724N-192F80HR AC Data Sheet

1. ec Infineon Hm Pinning Table 3 1 Pin Definitions and Functions PG LQFP 144 17 package cont d Pin Symbol Ctrl Type Function 134 P0 4 1 00 A1 Port 0 General Purpose I O Line 4 IN4 PD GPTAO Input 4 HWCFG4 l Hardware Configuration Input 4 OUT4 01 GPTAO Output 4 OUT60 O2 GPTAO Output 60 EVTOO O3 MCDS event output 0 135 P0 5 lOO A1 Port 0 General Purpose I O Line 5 IN5 l PD GPTAO Input 5 HWCFG5 l Hardware Configuration Input 5 OUT5 01 GPTAO Output 5 OUT61 O2 GPTAO Output 61 EVTO1 O3 MCDS event output 1 141 P0 6 1 00 A1 Port 0 General Purpose I O Line 6 IN6 l PU GPTAO Input 6 HWCFG6 l Hardware Configuration Input 6 REQ2 l External Request Input 2 OUT6 01 GPTAO Output 6 OUT62 O2 GPTAO Output 62 EVTO2 O3 MCDS event output 2 142 P0 7 1 00 A1 Port 0 General Purpose I O Line 7 IN7 PU GPTAO Input 7 HWCFG7 l Hardware Configuration Input 7 REQ3 l External Request Input 3 OUT7 01 GPTAO Output 7 OUT63 O2 GPTAO Output 63 EVTO3 O3 MCDS event output 3 Data Sheet 3 4 V1 2 2014 06 ec Infineon mm Pinning Table 3 1 Pin Definitions and Functions PG LQFP 144 17 package contd Pin Symbol Ctrl Type Function 136 P0 12 1 00 A2 Port 0 General Purpose I O Line 12 IN12 l PU GPTA
2. Pin Symbol Ctrl Type Function 5 P9 0 1 00 A1 Port 9 General Purpose I O Line 0 RXDCAN2 I PU CAN Node 2 Receiver Input Reserved O1 OUTS80 O2 GPTAO Output 80 Reserved O3 6 P9 1 1 00 A2 Port 9 General Purpose I O Line 1 TXDCAN2 O1 PU CAN Node 2 Transmitter Output OUT81 O2 GPTAO Output 81 Reserved O3 140 P9 2 1 00 A1 Port 9 General Purpose I O Line 2 Reserved O1 PU OUT82 O2 GPTAO Output 82 CCU60 03 COUT63 139 P9 3 lOO A1 Port 9 General Purpose I O Line 3 Reserved O1 PU OUT83 O2 GPTAO Output 83 CCU60 O3 COUT62 138 P94 1 00 A1 Port 9 General Purpose I O Line 4 CCU61 PU CC62INC Reserved O1 OUT84 O2 GPTAO Output 84 CCU60 O3 CC62 87 P9 5 lOO A2 Port 9 General Purpose I O Line 5 TDI l PU JTAG Serial Data Input BRKIN l OCDS Break Input Reserved 01 Reserved O2 Reserved O3 BRKOUT O OCDS Break Output controlled by OCDS module Data Sheet 3 21 V1 2 2014 06 ec Infineon Hm Pinning Table 3 1 Pin Definitions and Functions PG LQFP 144 17 package contd Pin Symbol Ctrl Type Function 89 P9 6 1 00 A2 Port 9 General Purpose I O Line 6 TDO l PU JTAG Serial Data Output BRKIN l OCDS Break Input Reserved 01 Reserved O2 Reserved O3 BRKOUT O OCDS Break Outpu
3. Table 5 SAK TC1724N 192F133HR Identification Registers cont d Short Name Value Address Stepping SCU CHIPID 8300 9B01 F000 06404 AC SCU_RTID 0000 00024 F000 0648 AC Table 6 SAK TC1724N 192F80HL Identification Registers Short Name Value Address Stepping CBS_JDPID 0000 63504 F000 0408 AB CBS_JTAGID 101D 00834 F000 0464 AB SCU_MANID 0000 18204 F000 0644 AB SCU_CHIPID 1300 9B01 F000 06404 AB SCU_RTID 0000 00014 F000 06484 AB Table 7 SAK TC1724N 192F80HR Identification Registers Short Name Value Address Stepping CBS_JDPID 0000 63504 F000 0408 AB CBS_JTAGID 101D 00834 F000 0464 AB SCU_MANID 0000 18204 F000 0644 AB SCU_CHIPID 9300 9B01 F000 0640 AB SCU_RTID 0000 00014 F000 06484 AB Table 8 SAK TC1724N 192F80HR Identification Registers Short Name Value Address Stepping CBS_JDPID 0000 63504 F000 04084 AC CBS_JTAGID 101D 0083 F000 0464 AC SCU_MANID 0000 18204 F000 0644 AC SCU CHIPID 9300 9B01 F000 0640 AC SCU_RTID 0000 0002 F000 06484 AC Data Sheet 4 2 V1 2 2014 06 Infineon nes Electrical Parameters 5 Electrical Parameters This specification provides all electrical parameters of the TC1724 5 1 General Parameters 5 1 1 Parameter Interpretation The parameters listed in this section partly represent the characteristics of the TC1724 and partly its requirements on the system To aid interpreting the parameters easily when evaluating them for a design they are m
4. OCDS Li Debug Interface forsee System Peripheral Bus SPB gt JTAG DAP 8 KB PRAM 8 Interrupt E 2 System MLIO E PCP2 S ce coe 5 3 Ei a STM MemCheck 24KB CMEM ame SCU 3 m S C FCE Ports E 5V E CT ADC Suppy z C BMU ADCO me nne i channels SBCU baag ADCi K m exl channels mm ssc M FADC gt 33V max K 2 differential SSC2 channels Ext MultiCAN msco Request Nodes ssc3 BlockDiagram Unit 64 MO WE Joran Figure 3 Data Sheet SAK TC1724N 192F80HL SAK TC1724N 192F80HR Block Diagram 2 4 V1 2 2014 06 Infineon TC1724 System Overview of the TC1724 Figure 4 shows the block diagram of the SAK TC1724F 192F80HR FPU PMI TriCore 16 KB SPRAM CPU 8 KB ICACHE TCt 3 1 Configurable quu DMI 116 KB LDRAM 4 KB DCACHE Configurable Abbreviations ICACHE Instruction Cache DCACHE Data Cache SPRAM Scratch Pad RAM LDRAM Local Data RAM OVRAM Overlay RAM BROM Boot ROM PFlash Program Flash DFlash Data Flash PRAM Parameter RAM in PCP CMEM Code RAM in PCP E gt 1 Optional Ext Supply Local Memory
5. 1 Only applicable for SAK TC1724F 192F133HL SAK TC1724F 192F133HR 2 Analog input overlayed with digital input functionality The related port logic is used to configure the input as either analog input default after reset or digital input The related port logic supports only the port input features as the connected pads are input only pads 3 IOZ1 valid for this pin is the parameter with overlayed No in the ADC parameter table 4 IOZ1 valid for this pin is the parameter with overlayed Yes in the ADC parameter table 5 For the emulation device ED this pin is bonded to VDDg ED Stand By RAM supply In the production devide device this pin is bonded to a VDD pad Data Sheet 3 25 V1 2 2014 06 Infineon y Pinning Legend for Table 3 1 Column Cirl Input for GPIO port lines with IOCR bit field selection PCx OXXXg O Output O0 Output with IOCR bit field selection PCx 1X00 O1 Output with IOCR bit field selection PCx 1X01 ALT1 O2 Output with IOCR bit field selection PCx 1X10 ALT2 O3 Output with IOCR bit field selection PCx 1X11 ALT3 Column Type A1 Pad class A1 LVTTL A1 Pad class A1 LVTTL A2 Pad class A2 LVTTL D Pad class D ADC Pad class LVTTL S Pad class D ADC Pad class S Digital PU with pull up device connected during reset PORST 0 PD with pull down device connected during reset PORST 0 TR tri state
6. Table 20 Standard Pads Class Parameter Symbol Values Unit Note Min Typ Max Test Condit ion Input Hysteresis Class HYSI CC 0 1x V Vppp Input Leakage Current 7oz CC 1000 1000 nA 40 C lt T 150 C 1500 1500 nA 150 C lt Ty lt 160 C Ratio between low and Vi Vim CC 0 6 i high input threshold Input high voltage class Vi SR 0 6x min Vp V pins Vopp pp 0 3 3 6 Input low voltage Class Vi SR 0 3 0 36 x V pads Vope 1 Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce It can t be guaranteed that it suppresses switching due to external system noise Class S pad parameters are only valid for Vopy 4 75 V to 5 25 V Table 21 Standard Pads Class S Parameter Symbol Values Unit Note Min Typ Max Test Condition Input Hysteresis for HYSS CC 0 3 V class S pads Input leakage current Iozs CC 300 300 nA Input voltage high Ving CC 3 6 V Data Sheet 5 21 V1 2 2014 06 Cinfineon TC1724 Table 21 Standard Pads Class S cont d Electrical Parameters Parameter Symbol Values Unit Note Min Typ Max Test Condition Input voltage low Vis CC 1 9 V Vj s Delta Viso CC 50 50 mV Maximum input low state treshold variation over 1ms Vppe consta nt 1 Hysteresis is implemented to avo
7. Data Sheet 3 19 V1 2 2014 06 Cinfineon TC1724 Pinning Table 3 1 Pin Definitions and Functions PG LQFP 144 17 package cont d Pin Symbol Ctrl Type Function 100 P8 3 1 00 A2 Port 8 General Purpose I O Line 3 SLSI3 l PU SC3 Slave Select Input B CCU60 CC61INC CCU61 O1 CC61 OUT51 O2 GPTAO Output 51 SLSO30 O3 SSC3 Slave Select Output 0 99 P8 4 lOO A2 Port 8 General Purpose I O Line 4 OUT99 o1 PU GPTAO Output 99 CCU61 O2 COUT62 SLSO31 O3 SSC3 Slave Select Output 1 69 P8 5 1 00 A2 Port 8 General Purpose I O Line 5 CCU60 PU CC60INC OUT100 O1 GPTAO Output 100 CCU61 O2 CC60 SLSO32 O3 SSC3 Slave Select Output 2 70 P8 6 1 00 A2 Port 8 General Purpose I O Line 6 OUT101 O1 PU GPTAO Output 101 Reserved O2 CCU61 03 COUT61 71 P8 7 1 00 A2 Port 8 General Purpose I O Line 7 CCU60 l PU CC62INC OUT102 O1 GPTAO Output 102 Reserved O2 CCU61 O3 CC62 101 P8 13 1 00 A2 Port 8 General Purpose I O Line 13 OUT4 o1 PU GPTAo Output 4 Reserved O2 CCU61 O3 COUT60 Port 9 Data Sheet 3 20 V1 2 2014 06 Infineon Ies Pinning Table 3 1 Pin Definitions and Functions PG LQFP 144 17 package cont d
8. Max Unit Note Test Condition Converter clock fanc SR 4 110 MHz SAK TC1724F 192F133HL SAK TC1724F 192F133HR SAK TC1724N 192F133HR 80 MHz SAK TC1724N 192F80HL SAK TC1724N 192F80HR Internal ADC clock Save CC 20 MHz 10 Charge consumption per conversion Qconv CC 70 85 100 pC charge needs to be provided via VAREFO Data Sheet 5 24 V1 2 2014 06 Cinfineon TC1724 Table 22 5V ADC Parameters cont d Electrical Parameters Parameter Symbol Values Min Typ Max Unit Note Test Condition Input leakage at analog inputs lozi CC 100 500 nA V2 0 97 x Voom V VS Voom V overlayed No 100 600 nA V2 0 97 x Voom V V lt Voom V overlayed Yes 500 100 nA V20 V Vi 0 03 x Voom V overlayed No 600 100 nA Vix 0 03 x Voom V V20V overlayed Yes 100 200 nA V gt 0 03 x Voom V V lt 0 97 x Voom V overlayed No 100 300 nA V gt 0 03 x Voom V V lt 0 97 x Voom V overlayed Yes Input leakage current at Varef0 uA Vareroz OV Vareros Voom V Input leakage current at VagndO uA Vacnno OV VacupoS Voom V ON resistance of the transmission gates in the analog voltage path 900 1500 Ohm Data Sheet 5 25
9. Table 37 MSC Parameters cont d Electrical Parameters Parameter Symbol Values Unit Note Min Typ Max Test Condition SOPP ENx outputs delay tas CC 5 5 ns ENx with strong from FCLP rising edge driver and sharp minus edge CMOS mode 2 10 ns ENx with strong driver and medium minus edge 0 21 ns ENx with strong driver and soft edge SDI bit time fa CC 8x ns Tusc SDI rise time t SR 200 ns SDI fall time fag SR 200 ns 1 FCLP signal rise fall times are only defined by the pad rise fall times 2 3 TMSC TSYS 1 fSYS 4 FCLP signal high and low can be minimum 1 TMSC SOP FCLP either propagated by CMOS strong driver and non soft edge FCLP SOP EN SDI 0 9 Vie 0 1 Vane MSC Tmg 1 vsd Figure 23 MSC Interface Timing Data Sheet 5 70 V1 2 2014 06 Infineon Hee Electrical Parameters Note The data at SOP should be sampled with the falling edge of FCLP in the target device Data Sheet 5 71 V1 2 2014 06 Infineon nes Electrical Parameters 5 3 11 3 SSC Master Slave Mode Timing The SSC parameters are valid for C 50 pF strong driver medium edge Table 38 Parameters Parameter Symbol Values Unit Note Min Typ Max Test Conditi on SCLK clock period ran CC 2x1 ns fre MTSR SLSOx delay fr
10. 1000 i 1000 nA Current Class A1 CC Data Sheet 5 13 V1 2 2014 06 Cinfineon TC1724 Table 18 Standard Pads Class A1 cont d Electrical Parameters Parameter Symbo Values Unit Note I Min Typ Max Test Condition On Resistance of Rosonw 450 600 Ohm Joy gt 0 5 mA the class A1 pad CC P MOS weak driver m 210 340 Ohm las 0 5 mA N_MOS On Resistance of Rbsonm 155 Ohm Top 2 mA the class A1 pad CC P MOS medium driver m 110 Ohm las 2mA N MOS On Resistance of Rogona 110 Ohm Top 2 mA the class A1 pad CC P_MOS strong driver B E 80 Ohm Ig lt 2 mA N_MOS Fall time pad type feats 150 ns C 20 pF pin out Ait C driver weak e 28 ns C 50 pF edge slow pin out driver strong 16 ns C 7 50 pF edge soft pin out driver strong 50 ns C 7 50 pF pin out driver medium 140 ns CS 150 pF pin out driver medium 550 ns C 150 pF pin out driver weak 18000 ns C 20000 pF pin out driver medium 65000 ns C 20000 pF pin out driver weak Data Sheet 5 14 V1 2 2014 06 Cinfineon TC1724 Table 18 Standard Pads Class A1 cont d Electrical Parameters Parameter Symbo Values Unit Note I Min Typ Max Test Condition Rise time pad type tray 150 ns C 20 pF pin out
11. 20 mA for one pin group AND 100 mA for the completed device I Os Data Sheet 5 50 V1 2 2014 06 Infineon nes Electrical Parameters AND additionally before power up after power down 1 mA for one pin in inactive mode 0 V on all power supplies The PORST signal may be deactivated after all VDD3 3 and VAREFO power supplies and the oscillator have reached stable operation within the normal operating conditions At normal power down the PORST signal should be activated within the normal operating range and then the power supplies may be switched off Care must be taken that all Flash write or delete sequences have been completed n case of a power loss at any power supply all power supplies must be powered down conforming at the same time to the rule number 2 Although not necessary it is additionally recommended that all power supplies are powered up down together in a controlled way as tight to each other as possible Additionally regarding the ADC reference voltage VAREFO VAREFO must power up at the same time or later then VDDM and VAREFO must power down either earlier or at latest to satisfy the condition VAREFO lt VDDM 0 5 V This is required in order to prevent discharge of VAREFO filter capacitance through the ESD diodes through the VDDM power supply In case of discharging the reference capacitance through the ESD diodes the current must be lower than 5 mA Data Sheet 5 51 V1 2
12. Additionally regarding the ADC reference voltage VAREFO VAREFO must power up at the same time or later then VDDM and VAREFO must power down either earlier or at latest to satisfy the condition VAREFO lt VDDM 0 5 V This is required in order to prevent discharge of VAREFO filter capacitance through the ESD diodes through the VDDM power supply In case of discharging the reference capacitance through the ESD diodes the current must be lower than 5 mA Data Sheet 5 53 V1 2 2014 06 Cinfineon TC1724 5 3 5 Power Pad and Reset Timing Table 28 Reset Timings Parameters Electrical Parameters Parameter Symbo Values Uni Note Test Condition I Min Typ Max t Application Reset t CC 150 810 us SAK TC1724F 192F 133HL Boot Time SAK TC1724F 192F133HR SAK TC1724N 192F133HR 150 1140 us SAK TC1724N 192F80HL SAK TC1724N 192F80HR Power on Reset fgp 2 5 ms Boot Time CC EVR Startup time fgyg 860 1100 jus from Supply CC ramp up till PORST release HWCFG pins tHDH 16 fep ns hold time from SR ESRO rising edge HWCFG pins tups 0 ns setup time to CC ESRO rising edge Ports inactive tp 8 ftp ns after ESRO reset CC active Ports inactive pip 150 ns after PORST CC reset active Minimum PORST fog 4 5 ec ms 9 active time after CC power supplies are stable at operating levels Data Sheet 5 54
13. Infineon nes Electrical Parameters 5 3 AC Parameters All AC parameters are defined with maximum driver strength unless otherwise stated 5 3 1 Testing Waveforms Vopp 90 rise_fall Figure 10 Rise Fall Time Parameters Vope Vopge 2 4 4 Test Points Vppe 2 Vss mc104881 a vsd Figure 11 Testing Waveform Output Delay M AAT 0 1 V fosse Timing pe Qj Vou 0 1V Reference Vioag 0 1 V eee Prs e Vg 0 1V MCT04880 new Figure 12 Testing Waveform Output High Impedance Data Sheet 5 47 V1 2 2014 06 Infineon Mes Electrical Parameters 5 3 2 Power Sequencing 5V Supply Only VA 5 5V BV 4 0V A 3 63V j 3 3V gs Fi l V 7 N 1 43V E Fi 1 3V vy A N i L AC PORST output AA ON PORST input Power Up_EVR_1 vsd Figure 12 5V 3 3V 1 3 V Power Up Down Sequence The events for the above points in the power up down sequence A external supplied voltage reaches operating level B external supplied and internal generated voltages reaches operating levels C internal generated voltage drops below operating level D internal generated voltage resumes operating level E external supplied voltage leaves operating level P0 4 and P0 5 should be kept at the selected setting of 0 or 1 until external supplied voltage has reached its operating level The foll
14. Versatile On chip Peripheral Units Two Asynchronous Synchronous Serial Channels ASC with baud rate generator parity framing and overrun error detection Four High Speed Synchronous Serial Channels SSC with programmable data length and shift direction One serial Micro Second Bus interface MSC for serial port expansion to external power devices One High Speed Micro Link interface MLI for serial inter processor communication One MultiCAN Module with 3 CAN nodes and 64 free assignable message objects for high efficiency data handling via FIFO buffering and gateway data transfer One FlexRay module with 2 channels E Ray Data Sheet 1 1 V1 2 2014 06 Infineon Waiting Summary of Features One General Purpose Timer Array Module GPTA providing a powerful set of digital signal filtering and timer functionality to realize autonomous and complex Input Output management Two Capture Compare Unit 6 CAPCOM6 kernels Two General Purpose Timer GPT12 modules 28 analog input lines for ADC 2independent kernels ADCO and ADC1 Analog supply voltage range from 3 3 V to 5 V single supply Broken wire detection 2different FADC input channels channels with impedance control and overlaid with ADC1 inputs Extreme fast conversion 21 cycles of feapc clock 10 bit A D conversion higher resolution can be achieved by averaging of consecutive conversions in digital data re
15. 15 0 ns Px PDRz PDy 0015 RxD capture delay by dRxdly 10 0 ns sampling flip flop CC 1 This includes the PLL ERAY accumulated jitter 2 Refers to delays caused by the asymmetries of the output drivers of the digital logic and the GPIO pad drivers Quarz tolerance and PLL ERAY accumulated jitter are not included 3 E Ray TxD output drivers have an asymmetry of rising and falling edges of leas traal lt 1 ns 4 Limits of 966ns and 1046 1ns correspond to 30 7096 Vppp FlexRay standard input thresholds For input thresholds of this product a correction of 0 5 ns and 0 1 ns has to be applied Data Sheet 5 75 V1 2 2014 06 Infineon nes Electrical Parameters 5 Valid for output slopes of the bus driver of dRxSlope 5ns 20 Vppp to 80 Vppp according to the FlexRay Electrical Physical Layer Specification V2 1B For A2 pads the rise and fall times of the incoming signal have to satisfy the following inequality 1 6ns lt tz45 traal lt 1 3ns BSS Last CRC Byte FES Byte Start Sequence Frame End Sequence t sample TXD BSS Last CRC Byte FES Byte Start Sequence Frame End Sequence ERAY_TIMING Figure 26 ERAY Timing Data Sheet 5 76 V1 2 2014 06 Infineon nes Electrical Parameters 5 4 Package and Reliability 5 4 1 Package Parameters Table 40 Thermal Characteristics of the Package Device Package ROJCT ROJC
16. Carerto 20 40 pF voltage reference inputs CLC Differential Non Linearity EApy 4 4 LSB ADC Error 9 97 CC resolution 12 bit 8 9 Gain Error 99 EAgaw 3 5 3 5 LSB ADC CC resolution 12 bit 9 9 Integral Non EAw l 4 4 LSB ADC Linearity49 9 CC resolution 12 bit 9 Offset Error 997 EA 4 4 LSB ADC CC resolution 12 bit 9 9 Converter clock fane 4 110 MHz SAK TC1724F SR 192F133HL SAK TC1724F 192F133HR SAK TC1724N 192F133HR 4 80 MHz SAK TC1724N 192F80HL SAK TC1724N 192F80HR Data Sheet 5 28 V1 2 2014 06 Cinfineon TC1724 Table 23 3 3V ADC Parameters cont d Electrical Parameters Parameter Symbo I Values Min Typ Max Unit Note Test Condition Internal ADC clock Saver CC 1 20 MHz 10 Charge consumption per conversion Qconv CC 70 pc charge needs to be provided via VAREFo Input leakage at analog inputs lozi C C 100 500 nA V 0 97 x Voom V Vis Vppy V overlayed No 100 600 nA V2 0 97 x Voom V Vis Voom V overlayed Yes 500 100 nA Vz 0 V Vx 0 03 x Voom V overlayed No 600 100 nA Vx 0 03 x Vppy V V20 V overlayed Yes 100 200 nA V gt 0 03 x Voom V V lt 0 97 x Voom V overlayed No 100 300 nA V gt 0 03 x Voom V Vi 0 97 x Voom V overlayed Yes Input leakage current
17. Typ Max Unit Note Test Condition GRADient error EF crap CC 5 Vin mode differential Gain 4 5 Vin mode single ended Gain lt 4 5 5 Vin mode differential Gain 4 Vin mode single ended Gain 4 Vin mode differential Gain 8 Vin mode single ended Gain 8 INL error EF CC LSB Vin mode differential 4 LSB Vin mode single ended Data Sheet 5 35 V1 2 2014 06 Cinfineon TC1724 Electrical Parameters Table 25 FADC Parameters with Vppy 5V cont d Parameter Symbol Values Unit Note Min Typ Max Test Condition Offset error EF orp CC 90 90 mV Vin mode differential Calibration No 90 90 mV Vi mode single ended Calibration No 20 20 mV Vin mode differential Calibration Yes 2 3 20 e 20 mV VQ mode single ended Calibration Yes 2 3 Error of common mode EF per 80 80 mV voltage Vearer 2 C Channel amplifier cutoff foorp CC 2 MHz frequency Converter clock frane 4 110 MHz SAK TC1724F SR 192F133HL SAK TC1724F 192F133HR SAK TC1724N 192F133HR 4 80 MHz SAK TC1724N 192F80HL SAK TC1724N 192F80HR Conversion time to CC S 21 1 For 10 bit Franc conversion Input resistance of the Rega CC 100 B 200 kOh analog voltage path Rn m Rp Data Sheet 5
18. V1 2 2014 06 Infineon Table 28 Reset Timings Parameters cont d TC1724 Electrical Parameters Parameter Symbo Values Uni Note Test Condition I Min Typ Max t TESTMODE TR fpoy 100 J l ns ST hold time from SR PORST rising edge PORST rise time tpor i x 50 ms SR TESTMODE TR fpos 0 j ns ST setup time to SR PORST rising edge Application Reset fpor app 40 Jus inactive after SR PORST deassertion 1 The duration of the boot time is defined between the rising edge of the internal application reset and the clock cycle when the first user instruction has entered the CPU pipeline and its processing starts 2 The given time includes the time of the internal reset extension for a configured value of SCU RSTCNTCON RELSA 0x05BE 3 The duration of the boot time is defined between the rising edge of the PORST and the clock cycle when the first user instruction has entered the CPU pipeline and its processing starts 4 The given time includes the internal reset extension time for the System and Application Reset which is visible through ESRO 5 This parameter includes the delay of the analog spike filter in the PORST pad 6 This parameter represents the additional time required to ensure that external crystal is stable and operational at PORST 7 Application Reset is assumed not to be extended from external otherwise the time extends
19. wc Qnfineon Never stop thinking 32 Bit Microcontroller TC1724 32 Bit Single Chip Microcontroller Data Sheet V1 2 2014 06 Microcontrollers Edition 2014 06 Published by Infineon Technologies AG 81726 Munich Germany 2014 Infineon Technologies AG All Rights Reserved Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics With respect to any examples or hints given herein any typical values stated herein and or any information regarding the application of the device Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind including without limitation warranties of non infringement of intellectual property rights of any third party Information For further information on technology delivery terms and conditions and prices please contact the nearest Infineon Technologies Office www infineon com Warnings Due to technical requirements components may contain dangerous substances For information on the types in question please contact the nearest Infineon Technologies Office Infineon Technologies components may be used in life support devices or systems only with the express written approval of Infineon Technologies if a failure of such components can reasonably be expected to cause the failure of that life support device or system or to affect the safety or effectiveness of that device o
20. 1000hms Added Rpsouw Changed min value of Vua to 0 6 x Vopp Changed min value of V 4 Vina to 0 6 Standard Pad Class A1 Added HYSA1 Added Virar Vinar Added Rosonw Rpsonm Rpsoni1 added new condition PMOS for 85ohms added a new condition for NMOS with a max value of 7Oohms Changed min value of V 4 to 0 6 x Vppp Deleted 2000nA to 2000nA limits for 7574 Standard Pad Class A2 Added HYSA2 Added Rpsoww Rpsonm Rpsow added new condition PMOS for 25ohms added a new condition for NMOS with a max value of 200hms feaz added max 18000ns for CL 20000pF pinout driverzmedium 65000ns for CL 20000pF pinout driver weak tra removed 140ns for CL 150pF pinout driver weak tear added 550ns for CL 150pF pinout driver weak 18000ns for CL 20000pF pinout driver medium 65000ns for CL 20000pF pinoutdriver weak Standard Pad Class F Added HYSF Data Sheet 5 81 V1 2 2014 06 Infineon nes Electrical Parameters Changed min value of VIHF to 0 6 x VDDP Added min value of V e Vipp as 0 6 Added Rosonw Rpsonm Deleted note for tpp tg Standard Pad Class I Changed min value of V to 0 6 x Vppp Changed min value of Vu Vi as 0 6 LVDS Pads Removed input hysteresis F HYSF Added note Parallel termination 100 Ohm 1 for fpi fai tset vps Standard Pad Class S p Changed max value of Vps to 3
21. 36 V1 2 2014 06 Cinfineon TC1724 Table 25 FADC Parameters with Vppy 5V cont d Electrical Parameters Parameter Symbol Values Unit Note Min Typ Max Test Condition Settling time of a channel fse CC 5 US amplifier after changing ENN or ENP Analog input voltage Vane SR Vasu Vppe V range Wakeup time from analog frwar CC 5 us powerdown fast mode Wakeup time from analog Tewas CC 10 us powerdown slow mode Analog reference ground Veau 0 V Internally CC generated Analog reference voltage Vearer 3 3 99 y Internally CC generated No missing codes M minimium once per week Quo of the pulses does not exceed 1 h g overshoots The accuracy values is valid between 5 and 90960f Vanf The offser error voltage drifts over the whole temperature range maximum 3LSB Calibration should be preformed at each power up In case of a continous operation it should be performed Voltage overshoot to 4V is permissible provided the pulse duration is less than 100 us and the cumulated sum A running conversion may become inexact in case of violating the nomal operating conditions voltage The calibration procedure should run after each power up when all power supply voltages and the reference voltage have stabilized Data Sheet 5 37 V1 2 2014 06 Infineon MENOR Electrical Parameters FADC Ana
22. 5 62 V1 2 2014 06 Infineon nes Electrical Parameters 5 3 9 JTAG Interface Timing The following parameters are applicable for communication through the JTAG debug interface The JTAG module is fully compliant with IEEE1149 1 2000 Note These parameters are not subject to production test but verified by design and or characterization Table 33 JTAG Parameters Parameter Symbol Values Unit Note Min Typ Max Test Condition TCK clock period t4 SR 25 ns TCK high time to SR 10 ns TCK low time tz SR 10 ns TCK clock rise time t4 SR x 4 ns TCK clock fall time f SR 4 ns TDI TMS setup to TCK tg SR 6 0 ns rising edge TDI TMS hold after TCK t SR 6 0 ns rising edge TDO valid after TCK falling t CC 3 0 ns C 20 pF 1 edge 13 ns C 50 pF TDO high impedance to tg CC 14 ns C 50 pF valid from TCK falling edge TDO valid output to high ti CC B 13 5 ns C 50 pF impedance from TCK falling edge TDO hold after TCK falling ti CC 2 ns edge 1 The falling edge on TCK is used to generate the TDO timing 2 The setup time for TDO is given implicitly by the TCK cycle time Data Sheet 5 63 V1 2 2014 06 Infineon Mns Electrical Parameters 0 9 Vpop sa e MC JTAG TCK Figure 17 Test Clock Timing TCK TMS TDO MC_JTAG Figure 18 J
23. Added PD for f p y 80Mhz for max and realistic patterns for both all external mode and 5V only with ext pass device mode Current consumption for LVDS pad pairs is updated for all LVDS pads in total Deleted the redundant ppp Updated ppp rp ppp ponsr pp_porst Deleted R44 parameter Power Sequencing Added Power Sequencing for 3 3V Supply Only section Power Pad and Reset Timing parameters Removed redundant note for tupp fps Added text from note TESTMODE TRST to the name of eou and tpos deleted note EVR Parameters Added Ipy yppo Vi and Vi parameters in Pass Device Detector Table Added EVR Parameter Table PLL SYSCLK parameters Changed max value for fico Added min value of 50us for t Included formula 1 and 2 Removed note for peak to peak noise on pad supply voltage PLL ERAY parameters Changed typ value to 250MHz for fp gAsE Added min value of 50us for t Removed note for peak to peak noise on pad supply voltage JTAG Interface parameters Changed to signs in the notes for tg tg and ty DAP parameters Peripheral Timings Removed note for Peripheral Timings Peripheral timing parameters are not subject to production test They are verified by design characterization MLI Timing Added text for MLI parameters valid for CL 25pF MLI Receiver parameters Changed fsys to 110MHz in footnote 3 MLI Tranmitter parameters Changed ra TCLK rise tim
24. NOTES 1 DOES NOT INCLUDE PLASTIC OR METAL PROTRUSION OF 0 25 MAX PER SIDE 2 PKG CORNER CHAMFER OF 08 x 45 WILL BE AT LOCATION A OR B DEFINING BY MOLD PROCESS 144x 0 08 A 8 D L LOCATION A 022 2005 08 x459 T5 AM 102 A B D Figure 27 Package Outlines PG LQFP 144 17 Table 41 Exposed pad Dimensions Ex 7 5 mm Ey 7 5 mm You can find all of our packages sorts of packing and others in our Infineon Internet Page Products http www infineon com products 5 4 3 Flash Memory Parameters The data retention time of the TC1724 s Flash memory depends on the number of times the Flash memory has been erased and programmed Data Sheet 5 78 V1 2 2014 06 Cinfineon TC1724 Electrical Parameters Table 42 FLASH32 Parameters Parameter Symbol Values Unit Note Min Typ Max Test Condition Data Flash Erase terD CC 39 js Time per Sector Program Flash Erase terp CC 5 S Time per 256 KByte Sector Program time data tpg5 CC 5 3 ms without flash per page reprogramming 15 9 ms with two reprogramming cycles Program time tprp CC 5 3 ms without program flash per reprogramming 3 page 10 6 ms with one reprogramming cycle Data Flash Ng CC 60000 x cycles Min data Endurance 4 retention 5 years Erase suspend delay tr gs CC 1
25. Slave Select Output 7 Data Sheet 3 7 V1 2 2014 06 ec Infineon Hm Pinning Table 3 1 Pin Definitions and Functions PG LQFP 144 17 package cont d Pin Symbol Ctrl Type Function 77 P1 11 1 00 A1 Port 1 General Purpose I O Line 11 IN27 PU GPTAO Input 27 IN51 l GPTAO Input 51 SCLK1B l SSC1 Clock Input B CCU61 l CCPOSOC GPT120 l T2INB GPT121 l T2INA OUT27 01 GPTAO Output 27 OUT51 O2 GPTAO Output 51 SCLK1B O3 SSC1 Clock Output B 93 P1 15 1 00 A2 Port 1 General Purpose I O Line 15 BRKIN PU Break Input Reserved O1 Reserved O2 Reserved O3 BRKOUT O Break Output controlled by OCDS module Port 2 61 P2 0 lOO A2 Port 2 General Purpose I O Line 0 IN32 PU GPTAO Input 32 CCU60 l CC62INB CCU61 l CC62INA OUT32 01 GPTAO Output 32 TCLKO O2 MLIO Transmitter Clock Output 0 CCU61 O3 CC62 Data Sheet 3 8 V1 2 2014 06 ec Infineon Hm Pinning Table 3 1 Pin Definitions and Functions PG LQFP 144 17 package contd Pin Symbol Ctrl Type Function 62 P2 1 1 00 A2 Port 2 General Purpose I O Line 1 IN33 PU GPTAO Input 33 TREADYOA I MLIO Transmitter Ready Input A CCU61 l CCPOS0A CCU60
26. TC1724 ports are reserved for these peripheral units to communicate with the external world Data Sheet 2 1 V1 2 2014 06 Infineon LS System Overview of the TC1724 2 1 Block Diagrams Figure 1 shows the block diagram of the SAK TC1724F 192F133HL SAK TC1724F 192F133HR Abbreviations ICACHE Instruction Cache DCACHE Data Cache SPRAM Scratch Pad RAM PMI DMI LDRAM Local Data RAM TriCore OVRAM Overlay RAM 16 KB SPRAM CPU 116 KB LDRAM BROM Boot ROM 8 KB ICACHE TC1 3 1 4 KB DCACHE PFlash Program Flash Configurable fessus Configurable DFlash Data Flash PRAM Parameter RAM in PCP CMEM Code RAM in PCP CPS Ce gt Lacu H Optional Ext Supply Local Memory Bus LMB PEEVEEN EP 5V 3 3V Tm Int Supply Boro Single source Ext Supply a 1 5 MB PFlash A DMA 64 KB Dflash LFI Bridge 16 channels amp 16 KB BROM T 8 KB OVRAM OCDS 11 Debug fr b Interface System Peripheral Bus JTAG DAP a 8 KB PRAM SEB p g g Interrupt ASCO 2 System MLIO j PCP2 3 z Core H m E sm ASC1 a gt MemCheck J 24KB CMEM E Ra _ Y SCU 2 sl B m CAPCOM F 2 CCU60 CCU61 pr Y S Forts E 5V GPTi2 3 a BMU oe GPT 120 119 ADCO PL
27. Table 1 enumerates these derivatives and summarizes the differences Table 1 TC1724 Derivative Synopsis Derivative Ambient CPU PCP Flash ERAY Wire Temperatur Freq Size Bond e Range T4 Material SAK TC1724F 192F133HL 40 C to 133 MHz 1 5MB Yes Au 125 C SAK TC1724F 192F133HR 40 C to 133 MHz 1 5MB Yes Cu 125 C SAK TC1724N 192F133HR _ 40 C to 133 MHz 1 5MB No Cu 125 C SAK TC1724N 192F80HL 40 C to 80 MHz 1 5MB No Au 125 C SAK TC1724N 192F80HR 40 C to 80 MHz 1 5 MB No Cu 125 C 1 This derivative has the same features as the SAK TC1724F 192F133HL except the wire bonding material 2 This derivative has the same features as the SAK TC1724N 192F80HL except the wire bonding material Data Sheet 1 7 V1 2 2014 06 Infineon LS System Overview of the TC1724 2 System Overview of the TC1724 The TC1724 combines three powerful technologies within one silicon die achieving new levels of power speed and economy for embedded applications Reduced Instruction Set Computing RISC processor architecture Digital Signal Processing DSP operations and addressing modes On chip memories and peripherals DSP operations and addressing modes provide the computational power necessary to efficiently analyze complex real world signals The RISC load store architecture provides high computational bandwidth with low system cost On chip memory and peripherals are des
28. V1 2 2014 06 Cinfineon TC1724 Electrical Parameters Table 22 5V ADC Parameters cont d Parameter Symbol Values Unit Note Min Typ Max Test Condition ON resistance for the Rain7t 180 550 900 Ohm Test feature ADC test pull down for CC available only AIN7 for odd AINx pins Resistance of the Rarer 500 1000 Ohm 500 Ohm reference voltage input CC increased if path AIN 1 0 used as reference input Broken wire detection tewe CC J50 13 delay against VAGND Broken wire detection fewr CC 50 14 delay against VAREF Sample time ts CC 2 257 T Ane Calibration time after bit to CC 4352 cycles ADC_GLOBCFG SUCAL is set Total Unadjusted TUE CC 4 419 LSB ADC Error 915 resolution 12 bit Wakeup time from analog tawar 5 US powerdown fast mode CC Wakeup time from analog tawas 10 US powerdown slow mode CC Analog reference Vacupo VssM l Varero V ground SR 0 05 Vpow2 Analog input voltage Van SR Vacwpo Varero V Analog reference Varero VAGNDO Vopmt V voltage SR 0 05 Vopw2 18 Analog reference voltage Varero Vppgw 2 Vopmt V range 2 VAGNDO 0 05 SR Data Sheet 5 26 V1 2 2014 06 Infineon nes Electrical Parameters The sampling capacity of the conversion C network is pre charged to Varer 2 before the sampling moment Because of the parasitic elements the voltage measured
29. at Varef laza CC uA VaREroS Voom V Input leakage current at Vagnd laza CC VAGNDOS Voom V Data Sheet 5 29 V1 2 2014 06 Cinfineon TC1724 Electrical Parameters Table 23 3 3V ADC Parameters cont d Parameter Symbo Values Unit Note I Min Typ Max Test Condition ON resistance of the Rain 3500 9000 Ohm transmission gates in the C analog voltage path C ON resistance for the Rawz 180 800 1800 Ohm Testfeature ADC test pull down for CC available only AINT for odd AINx pins Resistance of the Rarer 1700 3000 Ohm 1500 Ohm reference voltage input CC increased if path AIN 1 0 used as reference input Broken wire detection fewe 50 19 delay against VAGND CC Broken wire detection fewr CC 50 n delay against VAREF Sample time t CC 2 257 T Ane Calibration time after bit Lea CC 4352 cycles ADC_GLOBCFG SUCAL is set Total Unadjusted TUE 4 5 4 5 9 LSB ADC Error 915 CC resolution 12 bit Analog reference Vacupo VssM Varero V ground SR 0 05 Vopw2 Analog input voltage Vain SR Vacnpo Varero V Analog reference Varero VAGNDO Voom t V voltage SR 0 051 Voow2 ii Analog reference voltage Varero VppW2 Vppm V range 9 VAGNDO 0 05 SR 1 The sampling capacity of the conversion C network is pre charged to Vape 2 before the sampling moment Because of the paras
30. by the time the Application Reset is extended Data Sheet 5 55 V1 2 2014 06 TC1724 Infineon Electrical Parameters Vopppa VDDP Vopepa VDD Vun 12 teva_ tpoa Pad state undefined Tri state or pull device active As programmed Figure 16 Power Pad and Reset Timing Data Sheet 5 56 V1 2 2014 06 Cinfineon TC1724 5 3 6 EVR Parameter Table 29 Pass device detector Electrical Parameters Parameter Symbol Values Unit Note Min Typ Max Test Condition Pull up current at VDPG Ipu ypeg 0 7 2 0 mA Vops2 4 5V SR Vops lt 5 5V Input low voltage Vi SR O 1 5 V Table 30 EVR Parameters Parameter Symbol Values Unit Note Test Condition Min Typ Max Output Cours 6 8 UE TLoap gt 310 mA Capacitance on CC ESR 50mQ Vopp with external pass device additional decoupling capacitor on each supply pin SAK TC1724F 192F133HL SAK TC1724F 192F133HR SAK TC1724N 192F133HR 2 2 UE Ioan 310 mA ESR 50mQ with internal pass device additional decoupling capacitor on each supply pin SAK TC1724N 192F80HL SAK TC1724N 192F80HR Data Sheet 5 57 V1 2 2014 06 Cinfineon TC1724 Electrical Parameters Table 30 EVR Parameters cont d Parameter Symbol Va
31. l T12HRB GPT120 l T2INA GPT121 l T2INB OUT33 01 GPTAO Output 33 SLSO03 O2 SSCO Slave Select Output Line 3 SLSO13 O3 SSC1 Slave Select Output Line 3 63 P2 2 1 00 A2 Port 2 General Purpose I O Line 2 IN34 l PU GPTAO Input 34 CCU60 l CC61INB CCU61 l CC61INA OUT34 O1 GPTAO Output 34 TVALIDOA O2 MLIO Transmitter Valid Output CCU61 O3 CC61 64 P2 3 lOO A2 Port 2 General Purpose I O Line 3 IN35 PU GPTAO Input 35 CCU60 l T12HRC CCU60 l T13HRC CCU61 l CCPOS2A GPT120 l T4EUDA GPT121 l T4EUDB OUT35 01 GPTAO Output 35 TDATAO O2 MLIO Transmitter Data Output Reserved O3 Data Sheet 3 9 V1 2 2014 06 ec Infineon Hm Pinning Table 3 1 Pin Definitions and Functions PG LQFP 144 17 package contd Pin Symbol Ctrl Type Function 65 P2 4 1 00 A2 Port 2 General Purpose I O Line 4 IN36 PU GPTAO Input 36 RCLKOA l MLI Receiver Clock Input A OUT36 01 GPTAO Output 36 CCU61 O2 COUT63 Reserved O3 66 P2 5 1 00 A2 Port 2 General Purpose I O Line 5 IN37 l PU GPTAO Input 37 CCU60 l CC60INB CCU61 l CC60INA OUT37 O1 GPTAO Output 37 RREADYOA 02 MLIO Receiver Ready Output A CCU61 O3 CC60 67 P2 6 lOO A2 Port 2 General Purpose I O Line 6 IN38 l PU GPTAO Input 38 RVALIDOA l MLI Receiver Valid Input A Reserved l OUT38 01 GPTAO Ou
32. the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions may affect device reliability Table 10 Absolute Maximum Rating Parameters Parameter Symbol Values Unit Note Min Typ Max Test Con dition Storage temperature Ta SR 65 160 C Voltage at 1 3 V power supply Van SR 2 0 V pins with respect to Vss Voltage at 3 3 V power supply Vopp 4 33 V pins with respect to Veg SR Voltage at 5 V power supply Vbom SR 7 0 V pins with respect to Vss Voltage on any Class A input Vn SR 0 6 Vppp 0 5 IV Whatever pin and dedicated input pins or max 4 33 is lower with respect to Vss Voltage on any Class D Vain 0 6 7 0 V analog input pin with respect Varery to Vacnp SR Voltage on any shared Class Vaine 0 6 7 0 V D analog input pin with respect to Vssar if the FADC SR is switched through to the pin Input current on any pin Tin 10 10 mA during overload condition Absolute maximum sum of all Zy 75 75 mA input circuit currents for one port group during overload condition Absolute maximum sum ofall Z 200 mA input circuit currents during overload condition Data Sheet 5 3 V1 2 2014 06 Infineon JEN Electrical Parameters 1 The port groups are defined in Table
33. to 6 5V is permissible at Power Up and PORST low provided the pulse duration is less than 100 us and the cumulated sum of the pulses does not exceed 1 h Voltage overshoot to 4 0V is permissible at Power Up and PORST low provided the pulse duration is less than 100 us and the cumulated sum of the pulses does not exceed 1 h No external inductive load permissable if EVR is used This parameter is valid under the assumption the PORST signal is constantly at low level during the power up power down of Vppp Data Sheet 5 9 V1 2 2014 06 Infineon Mes Electrical Parameters Table 15 Pin Groups for Overload Short Circuit Current Sum Parameter Group Pins 1 P5 15 2 P9 1 0 P9 8 7 2 PO 7 0 P0 15 12 P2 13 8 P3 1 0 P3 4 3 P3 7 P3 15 9 P5 1 0 P8 2 0 P9 4 2 3 P1 1 0 P1 15 P3 2 P3 6 5 P3 8 P8 4 3 P8 13 P9 6 5 4 P1 4 3 P1 11 8 P2 7 0 P4 3 2 P8 7 5 Data Sheet 5 10 V1 2 2014 06 Cinfineon TC1724 Electrical Parameters 5 2 DC Parameters 5 2 1 Input Output Pins Table 16 Standard Pads Parameters Parameter Symbol Values Unit Note Min Typ Max Test Condition Pin capacitance digital Co CC 10 pF T 25 C inputs outputs 1 MHZ Pull down current Meg CC 150 HA V20 6x Vopp V 10 uA V gt 0 36 x Vopp V Pull Up current Heu4 CC 10 UA V lt 0 6 xX
34. weak ns CS 50 pF edge medium pin out driver strong 10 ns CS 50 pF edge medium minus pin out driver strong 3 7 ns CS 50 pF edge sharp pin out driver strong ns CS 50 pF edge sharp minus pin out driver strong 16 ns CS 50 pF edge soft pin out driver strong 50 ns C 7 50 pF pin out driver medium 7 5 ns C 7 100 pF edge sharp pin out driver strong 140 ns CS 150 pF pin out driver medium Data Sheet 5 18 V1 2 2014 06 Cinfineon Standard Pads Class A2 cont d Table 19 TC1724 Electrical Parameters Parameter Symbol Values Min Typ Max Unit Note Test Condition 550 ns CS 150 pF pin out driver weak 18000 ns C 20000 pF pin out driver medium 65000 ns C 20000 pF pin out driver weak Rise time pad type A2 trag CC 150 ns C 7 20 pF pin out driver weak 7 0 ns CS 50 pF edge medium pin out driver strong 10 ns CS 50 pF edge medium minus pin out driver strong 3 7 ns C 7 50 pF edge sharp pin out driver strong ns CS 50 pF edge sharp minus pin out driver strong 16 ns C 50 pF edge soft pin out driver strong 50 ns C 50 pF pin out driver medium 7 5 ns CS 100 pF edge sharp
35. 1 CCU60 l CCPOS2A CCU61 l T12HRC CCU61 l T13HRC GPT120 l T4INA GPT121 l T4INB OUT36 01 GPTAO Output 36 Reserved O2 AD1EMUX2 03 ADC1 External Multiplexer Control Output 2 Data Sheet 3 18 V1 2 2014 06 ec Infineon Hm Pinning Table 3 1 Pin Definitions and Functions PG LQFP 144 17 package contd Pin Symbol Ctrl Type Function 11 P5 15 1 00 A1 Port 5 General Purpose I O Line 15 RXDB1 PU E Ray Channel B Receive Data Input 1 OUT37 O1 GPTAO Output 37 Reserved O2 TXDCANO O3 CAN Node 0 Transmitter Output Port 8 117 P8 0 1 00 A2 Port 8 General Purpose I O Line 0 SCLK3 l PU SSC3 Clock Input Slave Mode CCU60 l CCPOSOC GPT120 l T3INB GPT121 l T3INA Reserved 01 OUT48 O2 GPTAO Output 48 SCLK3 O3 SSC3 Clock Output Master Mode 116 P8 1 1 00 A2 Port 8 General Purpose I O Line 1 MRST3 l PU SSC3 Master Receive Input Master Mode CCU60 l CCPOS1C GPT120 l T3EUDB GPT121 l T3EUDA Reserved 01 OUT49 O2 GPTAO Output 49 MRST3 O3 SSC3 Slave Transmit Output Slave Mode 115 P82 lOO A2 Port 8 General Purpose I O Line 2 MTSR3 l PU SC3 Slave Receive Input Slave Mode CCU60 l CCPOS2C GPT120 l T4INB GPT121 l T4INA Reserved O1 OUT50 O2 GPTAO Output 50 MTSR3 O3 SSC3 Master Transmit Output Master Mode
36. 15 Data Sheet 5 4 V1 2 2014 06 Infineon nes Electrical Parameters 5 1 4 Pin Reliability in Overload When receiving signals from higher voltage devices low voltage devices experience overload currents and voltages that go beyond their own IO power supplies specification Table 11 defines overload conditions that will not cause any negative reliability impact if all the following conditions are met full operation life time 24000 h is not exceeded Operating Conditions are met for pad supply levels Vppp or Vppy temperature If a pin current is out of the Operating Conditions but within the overload parameters then the parameters functionality of this pin as stated in the Operating Conditions can no longer be guaranteed Operation is still possible in most cases but with relaxed parameters Note An overload condition on one or more pins does not require a reset Table 11 Overload Parameters Parameter Symbol Values Unit Note Test Con dition Min Typ Max Input current on any digital pin Zi 5 5 mA during overload condition Absolute sum of all input Inc 70 70 mA circuit currents for one port group during overload condition Input current on analog pins Jijana 3 3 mA Absolute sum of all analog ImsAs 15 15 mA input currents for analog inputs of a single ADC during overload condition Absolute sum of all input Lins 100 100 mA circuit
37. 1724 QFP144 Figure 6 Table 3 1 TC1724 Pinning for PG LQFP 144 17 package Pin Definitions and Functions PG LQFP 144 17 package Pin Symbol Ctrl Type Function Port 0 Data Sheet V1 2 2014 06 ec Infineon Hm Pinning Table 3 1 Pin Definitions and Functions PG LQFP 144 17 package contd Pin Symbol Ctrl Type Function 121 P0 0 1 00 A1 Port 0 General Purpose I O Line 0 INO PU GPTAO Input 0 CCU60 l CC60INA CCU61 l CC60INB HWCFGO l Hardware Configuration Input 0 OUTO 01 GPTAO Output 0 OUT56 O2 GPTAO Output 56 CCU60 O3 CC60 122 P0 1 1 00 A1 Port 0 General Purpose I O Line 1 IN1 l PU GPTAO Input 1 SDI1 l MSCO Serial Data Input 1 HWCFG1 l Hardware Configuration Input 1 OUT1 01 GPTAO Output 1 OUT57 O2 GPTAO Output 57 CCU60 O3 COUT60 123 P02 lOO A1 Port 0 General Purpose I O Line 2 IN2 l PU GPTAO Input 2 HWCFG2 l Hardware Configuration Input 2 OUT2 01 GPTAO Output 2 OUT58 O2 GPTAO Output 58 Reserved O3 124 P0 3 1 00 A1 Port 0 General Purpose I O Line 3 IN3 PU GPTAO Input 3 HWCFG3 l Hardware Configuration Input 3 OUT3 O1 GPTAO Output 3 OUT59 O2 GPTAO Output 59 Reserved O3 Data Sheet 3 3 V1 2 2014 06
38. 1724N 192F80HR Inactive device pin current Ip SR mA All power supply voltages Vopx 0 Short circuit current of digital outputs Isc SR mA Data Sheet 5 8 V1 2 2014 06 Infineon nes Electrical Parameters Table 14 Operating Conditions Parameters cont d Parameter Symbol Values Unit Note Min Typ Max Test Condition Absolute sum of Xlgp CC ka 100 mA short circuit currents of the device Absolute sum of Xlsc pg CC 70 mA short circuit currents per pin group Ambient TA SR 40 125 C Temperature Junction T SR 40 160 C temperature Core Supply Voltage Van SR 1 17 11 3 11 43 v Only required if externally supplied ADC analog supply Vyg SR2 97 5 0 5 59 V voltage EVR supply voltage V SR 4 00 5 0 5 5 V 5 0V single supply 2 97 3 3 3 63 V 3 3V single supply Digital supply voltage Vppp SR 2 97 3 3 3 634 v Only required if for IO pads externally supplied VDDP voltage to Vopep CC 0 65 V ensure defined pad states Digital ground Vas SR 0 V voltage Analog ground Vasu SR 0 1 O 0 1 V voltage for Vppy 1 2 Applicable for digital outputs Voltage overshoot to 1 7V is permissible at Power Up and PORST low provided the pulse duration is less than 100 us and the cumulated sum of the pulses does not exceed 1 h Voltage overshoot
39. 2014 06 Infineon nes Electrical Parameters 5 3 4 Power Sequencing all Voltages supplied from External V A 5 5V l WE lb E EA 4 5V 0 3 63V A Vaner 3 3V 2 97V 1 43V y 1 3V 4 t 1 17V i l QV Vppe l EE l PORST l L power power down fail Power Up 10 Figure 15 5V 3 3V 1 3 V Power Up Down Sequence P0 4 and P0 5 should be kept at the selected setting until external supplied voltage has reached its operating level The following list of rules applies to the power up down sequence All ground pins Vas must be externally connected to one single star point in the system Regarding the DC current component all ground pins are internally directly connected Atany moment in time to avoid increased latch up risk each power supply must be higher then any lower power supply 0 5 V or VDD5 gt VDDP 0 5 V VDD5 gt VDD 0 5 V VDDP gt VDD 0 5 V see Figure 15 The latch up risk is minimized if the I O currents are limited to 20 mA for one pin group AND 100 mA for the completed device I Os AND additionally before power up after power down 1 mA for one pin in inactive mode 0 V on all power supplies Data Sheet 5 52 V1 2 2014 06 Infineon Nn Electrical Parameters During power up and power down the voltage difference between the power supply pins of the same voltage 3 3 V 1 3 V and 5 V with different names tha
40. 3 5 1 00 A1 Port 3 General Purpose I O Line 5 SLSO00 o1 PU ssco Slave Select Output 0 SLSO10 O2 SSC1 Slave Select Output 0 SLSOANDOO O3 SSCO AND SSC1 Slave Select Output 0 Data Sheet 3 12 V1 2 2014 06 ec Infineon Hm Pinning Table 3 1 Pin Definitions and Functions PG LQFP 144 17 package cont d Pin Symbol Ctrl Type Function 103 P3 6 1 00 A1 Port 3 General Purpose I O Line 6 SLSOO1 o1 PU ssCo0Slave Select Output 1 SLSO11 O2 SSC1 Slave Select Output 1 SLSOANDO O3 SSCO AND SSC1 Slave Select Output 1 107 P3 7 1 00 A2 Port 3 General Purpose I O Line 7 SLSIO l PU SCO Slave Select Input 1 SLSO02 O1 SSCO Slave Select Output 2 SLSO12 O2 SSC1 Slave Select Output 2 OUT89 O3 GPTAO Output 89 104 P3 8 lOO A2 Port 3 General Purpose I O Line 8 REQ14 PU External Request Input 14 SLSO06 O1 SSCO Slave Select Output 6 TXD1 O2 ASC1 Transmit Output OUT90 O3 GPTAO Output 90 114 P3 9 1 00 A1 Port3 General Purpose I O Line 9 RXD1A PU ASC1 Receiver Input A RXD1A O1 ASC1 Receiver Output A Synchronous Mode Reserved O2 OUT91 O3 GPTAO Output 91 113 P3 10 1 00 A1 Port3 General Purpose I O Line 10 REQO l PU External Request Input 0 Reserved 01 Reserved O2 OUT92 O3 GPTAO Output 92 120 P3 11 lOO A1 Port3 Genera
41. 5 ms Wait time after fe Marginbei SR 10 x US margin change Program Flash RET CC 20 years Max 1000 Retention Time erase Physical Sector 9 program cycles Program Flash RETL CC 20 years Max 100 erase Retention Time program cycles Logical Sector 9 UCB Retention trtu CC 20 years Max 4 erase Time99 program cycles per UCB Wake Up time twu CC 270 us Data Sheet 5 79 V1 2 2014 06 Infineon Mns Electrical Parameters Table 42 FLASH32 Parameters cont d Parameter Symbol Values Unit Note Min Typ Max Test Condition DFlash wait state WSpr SR 50ns x configuration Jime PFlash wait state WSpr SR 26ns x configuration Jime 1 In case of wordline oriented defects see robust EEPROM emulation in the User s Manual this erase time can increase by up to 100 2 In case the Program Verify feature detects weak bits these bits will be programmed up to twice more Each reprogramming takes additional 5 ms 3 In case the Program Verify feature detects weak bits these bits will be programmed once more The reprogramming takes additional 5 ms 4 Only valid when a robust EEPROM emulation algorithm is used For more details see the User s Manual 5 Storage and inactive time included 6 At average weighted junction temperature 7 100 C or the retention time at average weighted temperature of T 110 C is minimum 10 years or the retention ti
42. 6 Changed min value of Vj s to 2 1 Added input leakage current 575 ADC parameters Changed typ value of Cainsw to 9pF Changed typ value of Canror to 20pF Updated notes for EA aw EA gain TUE EA np EA re Changed fapc to max 20MHz Added fpc of 110MHz where ffpimax 110MHz Added fapc of 80MHz where ffpimax 80MHz Updated fapc min of 4MHz Added sample time fs 2 to 255 ADC Added calibration time after reset c4 max 4352 cycles Included footnote for TUE for 10 bit and 8 bit conversion Removed Ayz covered by Ranzt Removed 4gge added Ocony Updated notes for 975 and l Updated typ value of 900Ohm for Ray FADC parameters Updated note for EF grap Updated note for EF opp Added franc of 110MHz where ffpimax 110MHz Added franc of 80MHz where ffpimax 80MHz Added conversion time to Added analog input voltage range V ane OSC XTAL parameters Changed max value of Vi to V555 0 5V Changed min value of V y to 0 5V Added typ values for internal load capacitors C to C 4 2 5pF 2 5pF 4pF 6 5pF Added HYSAX Power Supply parameters Data Sheet 5 82 V1 2 2014 06 Infineon Mns Electrical Parameters Updated Jane ppm DDP rp Added Jpp for fopy 80MHz for max and realistic patterns Updated PD values for max and real patterns all external py 133MHz Added text to of fopy 133MHz to the note for the PD parameter
43. 6 CAN OCDS JTAG Overlaid digital analog inputs Overlaid digital analog inputs Oscillator 1 Only available for SAK TC1724F 192 133HL SAK TC1724F 192F133HR TC1724 LogSym 144 Figure 5 TC1724 Logic Symbol Data Sheet 3 1 V1 2 2014 06 Infineon TC1724 Pinning REQ7 CC62 CC62INA B CAPINA B SLSO20 OUT4O IN4O P5 0 SLSO21 OUTS1 IN41 P5 1 COUT62 SLS022 OUT42 IN42 P5 2 SLS023 OUT43 N43 P5 3 RXDCAN2 OUT80 P9 0 TXDCAN2 OUTB1 PO 1 SLSIZA SLSO24 OUTAA INAAIPS 4 MRST2A OUTAS INASIPS 5 MTSR2A QUTA6 INAGIPS 6 SCLK2A QUTA7 INATIPS 7 TXDCANO OUT3TIRXDB1 IPS 15 CCS0INCICCeQ OUTB7 PO 7 COUTGO OUTB8 PO 5 CC61 CCG1INA BIOUTE TXDA1 IPS 8 OUT7 RXDCANO TXDB1 P5 9 COUTS1 OUTS TXENA PS 10 COUTS OUTS TXENB P511 CCPOSOA TT2HRB TSINAB AD TEMUXD SLSOQ7 OUT19IPS 12 CCPOS1A T13HRB T3EUDA B OUT20 AD 1EMUX1 P5 13 CCPOS2A T12HRG T13HRC TAINAIB OUT36 AD TEMUXZ RXDA 1 IPS 14 Veo AN3QIDIG19 P 12 3 AN3BIDIG18 P 12 2 ANSTIDIGATIP12 1 AN36 DIG16 P 12 0 AN3S AN34 AN33 AN32 ANT AN2SIDIGSIP11 9 AN2SIDIGTIP11 7 1 This pin is used as standby power E 5 z S g 889g 5 Z Bag S sung sad 8 fs 8 gen 5 555 B cess pes 2 3 555 S EEEE BEE ERE B 2255 gol0dis s PUB 5 28 SIEA EEEE 8 898228 E 58 S92288855822550 9 SEECOPS ESE 028 555699 AA TELP 95gs555552Ezzr SoSNOBS55559Dz2a 0 2988 22 BESSE99 229922252 S955955 995233 S EEEIEE REER EREET ER E ZERSESS ESSESS
44. 9 change t4 from 100ns to 200ns in table 29 e extend Kovan conditon from Joyx 0 mA Ioy2 1 mA to las 0 mA Toyz 2 mA e dGlearify leakage definition for A1 and pads for 150 C lt T x 160 C change Vj s from 2 1V to 1 9V in table 25 change tse from 1 fep to 1 fep 1 in table 30 change Ran from 4500 Ohm to 9000 Ohm in table 15 remove the following product options SAK TC1724N 192F133HL SAK TC1724F 128F 133HL SAK TC1724F 128F133HR SAK TC1724N 128F 133HL SAK TC1724N 128F 133HR SAK TC1724N 128F80HL SAK TC1724N 128F80HR SAK TC1724N 192F 133HL Data Sheet 5 87 V1 2 2014 06 Infineon nue Electrical Parameters SAK TC1724F 128F80HR shift the product SAK TC1724N 192F133HR from step AB to AC add for products SAK TC1724F 192F133HR and SAK TC1724N 192F80HR step AC Data Sheet 5 88 V1 2 2014 06
45. AL The OSC_WDT checks for too low frequencies and for too high frequencies The frequency that is monitored is foscrer which is derived for fosc 8 f OSC f a n oscrer OSCVAL 1 The divider value SCU_OSCCON OSCVAL has to be selected in a way that foscrer is 2 5 MHz Note foscrer has to be within the range of 2 MHz to 3 MHz and should be as close as possible to 2 5 MHz The monitored frequency is too low if it is below 1 25 MHz and too high if it is above 7 5 MHz This leads to the following two conditions Too low fosc lt 1 25 MHz x SCU_OSCCON OSCVAL 1 Too high fosc gt 7 5 MHz x SCU_OSCCON OSCVAL 1 Note The accuracy is 30 for these boundaries Data Sheet 5 61 V1 2 2014 06 Cinfineon TC1724 Electrical Parameters 5 3 8 ERAY Phase Locked Loop ERAY PLL Table 32 PLL ERAY Parameters Parameter Symbol Values Unit Note Min Typ Max Test Con dition Accumulated jitter at Dpp CC 0 8 0 8 ns SYSCLK pin Accumulated Jitter Dp CC 0 5 x 0 5 ns PLL Base Frequency of fpitsase eray CC 50 250 360 MHz the ERAY PLL VCO input frequency of fare CC 20 40 MHz the ERAY PLL VCO frequency range fyco eray CC 450 500 MHz of the ERAY PLL PLL lock in time t CC 5 6 200 US Note The specified PLL jitter values are valid if the capacitive load per pin does not exceed C 20 pF with the maximum driver and sharp edge Data Sheet
46. A_ power pattern max mode 5V only with ext pass device SAK TC1724N 192F133HR J 280 mA power pattern real mode 5V only with ext pass device SAK TC1724F 192F133HL SAK TC1724F 192F133HR 275 mA power pattern real mode 5V only with ext pass device SAK TC1724N 192F133HL SAK TC1724N 192F 133HR Data Sheet 5 42 V1 2 2014 06 Infineon nes Electrical Parameters Table 27 Power Supply Parameters cont d Parameter Symbol Values Unit Note Test Condition Min Typ Max EVR Supply lus 310 mA power pattern max current CC mode 5V only without ext pass device SAK TC1724N 192F80HL SAK TC1724N 192F80HR 235 mA power pattern real mode 5V only without ext pass device SAK TC1724N 192F80HL SAK TC1724N 192F80HR Maximum power PD 902 mW power pattern max dissipation CC mode all external SAK TC1724F 192F133HL SAK TC1724F 192F133HR SAK TC1724N 192F133HR j 744 mW power pattern realistic mode all external SAK TC1724F 192F133HL SAK TC1724F 192F133HR SAK TC1724N 192F 133HR Data Sheet 5 43 V1 2 2014 06 Cinfineon Table 27 Power Supply Parameters cont d TC1724 Electrical Parameters Parameter Symbol Values Min Typ Max Unit Note Test Condition Maximum power dissipation PD CC 1970 mW power pattern max mode 5V only with ext pass device SAK
47. Ait C driver weak c 28 ns C 50 pF edge slow pin out driver strong 16 ns C 50 pF edge soft pin out driver strong 50 ns C 7 50 pF pin out driver medium 140 ns C 150 pF pin out driver medium 550 ns C 150 pF pin out driver weak 18000 ns C 20000 pF pin out driver medium 65000 ns C 20000 pF pin out driver weak Input high voltage Vinats 0 6 x Vppp min Vp V Class A1 pads SR pp 0 3 3 6 Input low voltage Vta 0 3 0 36x V Class A1 pads SR Vppp Ratio Vil Vih A1 Vi44 0 6 pads Vinat CC Data Sheet 5 15 V1 2 2014 06 Cinfineon TC1724 Electrical Parameters Table 18 Standard Pads Class A1 cont d Parameter Symbo Values Unit Note I Min Typ Max Test Condition Output voltage high Vonar Vopp 0 4 S V Toyz 1 4 mA pin out class A1 pads CC driver medium Vopr 0 4 V Top 1 4 mA pin out driver strong 24 V Top 2 mA pin out driver medium 24 V Io 2 mA pin out driver strong Vopr 0 4 V Top 400 pA pin out driver weak 2 4 V To 500 pA pin out driver weak Output voltage low Va Ad 0 4 V Io 2 mA pin out class A1 pads CC driver medium ES 0 4 V Io 2 mA pin out driver strong 0 4 V Ig 500 pA pin out driver weak 1 Hysteresis is implemented to avoid metastable states and switching due to inte
48. Bus LMB 1 3V 3 3V 5V 3 3V Int Supply Single source Ext Supply 1 5 MB PFlash A 64 KB Dflash LFI Bridge 16 KB BROM m 8 KB OVRAM OCDS M mete a System Peripheral Bus SPB JTAG DAP 8 KB PRAM g Interrupt ASCO E 2 System MLIO Z PCP2 15 lans aet pa Core 5 a ASC1 R SIM MemCheck pM 24 KB CMEM M E Ray E SCU 2channels LC CAPCOM f idi CCU60 CCU61 Ports E 5v g Ext ADC Supply GPT12 W GPT 120 E BMU ADCO Vmax 16 LE 16 channels GPT12 d SSCO GPT 121 ADCI L8 du Ll 1 chmod um SSC GPTAO FADC Pas 3 3V max C 2 differential SSc2 channels MultiCAN sco 3Nodes Sc SSC3 BlockDiagram 7 TCI7AMF V0 8 Figure 4 SAK TC1724F 192F80HR Block Diagram Data Sheet 2 5 V1 2 2014 06 2 Infineon TC1724 Pinning Figure 5 shows the logic symbol for TC1724 Pinning PORST General Control TESTMODE ES ESRI TRST OCDS JTAG Contro TCK DAPO TMS DAP1 AN 16 0 AN19 AN23 Analog Inputs AN25 TC1724 AN 39 32 Voom Analog Power Vasu Supply Varero Vacnoo Vs Digital Circuitry Voo Power Supply Voss Vss EVR Pass Device Gate Yene Alternate Functions GPTA SCU E RAY MSCO CCU6 SCU GPTA SSC1 OCDS CCU6 GPT12 GPTA SSCO0 1 MSCO MLIO CCU6 GPT12 GPTA ASCO SSCO 1 SCU CAN MSO GPTA SCU CCU6 GPT12 GPTA E RAY SSC0 2 CAN CCU6 GPT12 SCU ADC1 CCU6 GPT12 SSC3 GPTA GPTA CCU
49. CACHE configurable 24 Kbyte Code Scratchpad Memory SPRAM Data Cache up to 4 Kbyte DCACHE configurable 8 Kbyte Overlay Memory OVRAM 16 Kbyte BootROM BROM 16 Channel DMA Controller Sophisticated interrupt system with 2 x 255 hardware priority arbitration levels serviced by CPU or PCP2 High performing on chip bus structure 64 bit Local Memory Buses between CPU Flash and Data Memory 32 bit System Peripheral Bus SPB for on chip peripheral and functional units One bus bridge LFI Bridge Versatile On chip Peripheral Units Two Asynchronous Synchronous Serial Channels ASC with baud rate generator parity framing and overrun error detection Four High Speed Synchronous Serial Channels SSC with programmable data length and shift direction One serial Micro Second Bus interface MSC for serial port expansion to external power devices One High Speed Micro Link interface MLI for serial inter processor communication One MultiCAN Module with 3 CAN nodes and 64 free assignable message objects for high efficiency data handling via FIFO buffering and gateway data transfer One General Purpose Timer Array Module GPTA providing a powerful set of digital signal filtering and timer functionality to realize autonomous and complex Input Output management Two Capture Compare Unit 6 CAPCOM6 kernels Data Sheet 1 5 V1 2 2014 06 Infineon Waiting Summary of Features Two Gen
50. DOT LL LD D DULL LD D LD 3555555559555555 EEE P3 4 MTSRO OUT88 P3 7 SLSO02 SLSO12 STSIOIOUTES P3 3 MRSTOIOUTS7 P3 2 SCLKO OUT86 P3 8 SLSO06 TXD1 OUTSO REQ14 P3 6 SLSOO1 SLSO11 SLSOANDO t P3 5 SLSO00 SLSO10 SLSOANDOO P8 13 0UTA COUTEO P8 3 SLSIS CC61INC CC61 OUTS1 SLSO30 P8 4 0UT99ICOUTE2 SLSO31 ESRO PORST ESRI P4 4 IN17 OUT17 0UT73 T13HRE CTRAPE TESTMODE 107 108 108 104 103 102 101 100 O P1 15 BRKIN BRKOUT PAOIREQIS INTJOUT18 OUT72 T3OUT BRKINIBRKOUT TCKIDAPO TRST P9 6 TDO BRRINIBRKOUT TMSIDAP1 P9 5 TDI BRKIN SRKOUT TC1724 Vss XTAL2 XTALt Vss P1 4 IN20EMGSTOPIOUT20 OUT76ICOUT61 PTS INTSIOUT1SIQUT7S COUT3 1 1 4 IN27 INS1 SCLK1B OUT27 0UTS 1 CCPOSOCIT2INA B P1 10 IN26 INSO OUTB OUTSO SLSO17 P1 S IN25 IN49 MRST 1B OUT25 OUTS9 CCPOS 1C T2EUDA B P1 8 IN24 IN48 MTSR1B OUT24 OUT48 CCPOS2C TAEUDAIB P4 3 IN31 INS5 OUTS 1 OUTSS EXTCLKO T 12HRE CTRAPA 22 JN g 38 55 eo B 83 9 8 U 3 E Z E P 3 E 5 8 g a a 9 2 g 8 g E supply in emulation device JNN BER 829 222 228 888 258 288 55E e 525 335 883 CCG2 CCe2INAIBITCLKO OUTS2 INS2 P2 0 z 61 CCPOSQAT 12HRB T2INAIBISLSOTS SLSODS QUTaS TREADYOAIN33 P2 I Z 62 CCG1 CCG1INAIBITVALIDOA QUT34 IN34 P2 2 Z 63 TI2HRC TI 3HRCICCPOS2A TAEUDA B TDATAQQUTAS IN3S P2 3 Z 64 5 3 2 3 2 4 E z 8 8 S 8 8 1 Only available for SAK TC1724F 192F 193HL SAK TC1724F 192F133HR TC
51. Data Sheet 5 73 V1 2 2014 06 Cinfineon TC1724 Electrical Parameters L b4 1 First shift First latching Last latching SCLK SCLK edge SCLK edge SCLK edge Laa bs a bs lss N 1 This timing is based on the following setup CON PH CON PO 0 SSC_TmgSM Figure 25 Data Sheet Slave Mode Timing 5 74 V1 2 2014 06 Cinfineon TC1724 5 3 11 4 ERAY Interface Timing The timings of this section are valid for the strong driver and either sharp edge or medium edge settings of the output drivers with C 25 pF The ERAY interface is only available for the SAK TC1724F 192F133HL and SAK TC1724F 192F133HR Electrical Parameters Table 39 ERAY Parameters Parameter Symbol Values Unit Note Min Typ Max Test Condition Time span from last BSS ts CC 997 75 1002 25 ns to FES without the influence of quartz tolerancies d10Bit TX TxD data valid from te1 teo E 1 5 ns Asymmetrical fsample flip flop txd reg CC delay of rising TxDA TxDB and falling edge dTxAsym 9 TxDA TxDB Time span between last f SR 966 1046 1 ns BSS and FES without influence of quartz tolerancies d10Bit RX 99 RxD capture by fsample t 4 7te5 3 0 ns Asymmetrical RxDA RxDB sampling CC delay of rising flip flop dRxAsym and falling edge RxDA RxDB TxD data delay from dTxdly 10 0 ns Px PDRz PDy sampling flip flop CC 000
52. Input Circuitry EXT aa AIN On d ad mIo AIN C C AINTOT AINSW TTC Cansw Reference Voltage Input Circuitry Haer On Analog InpRefDiag Figure 7 ADCx Input Circuits Data Sheet 5 32 V1 2 2014 06 TC1724 Cinfineon Electrical Parameters Single ADC Input Vin Vopm gt 100nA 3 97 100 loz1 4 Overlayed ADC FADC Input 600nA 4 300nA 7 100nA TRIER 100nA4 396 97 100 600nA Figure 8 ADCx Analog Inputs Leakage Data Sheet 5 33 V1 2 2014 06 Cinfineon 5 2 3 Table 25 TC1724 FADC Parameters with Vppy 5V Fast Analog to Digital Converter FADC FADC parameter are valid for Vopy 4 75 V to 5 25 V T 150 C Electrical Parameters Parameter Symbol Values Min Typ Max Unit Note Test Condition DNL error Bia CC LSB Vin mode differential Gain 1 2 LSB Vin mode single ended Gain 1 2 LSB Vin mode differential Gain 4 8 T 2 150 C 2 5 LSB Vin mode differential Gain 4 8 T 160 C LSB Vin mode single ended Gain 4 8 T 150 C 2 5 LSB Vin mode single ended Gain 4 8 T 160 C Data Sheet 5 34 V1 2 2014 06 Cinfineon Table 25 TC1724 FADC Parameters with Vppy 5V cont d Electrical Parameters Parameter Symbol Values Min
53. L S 5 GPTi2 l ERAY ssco K L ee GPT 121 SBCU ADC1 gt Li PLL fru GVmax 4 z 24 channels aga SSC1 GPTAO pane fr 1 daitterentia L MultiCAN msco Tog BlockDiagram id TC1724F v0 8 Figure 1 SAK TC1724F 192F133HL SAK TC1724F 192F133HR Block Diagram Data Sheet 2 2 V1 2 2014 06 Infineon TC1724 System Overview of the TC1724 Figure 2 shows the block diagram of the SAK TC1724N 192F133HR Abbreviations ICACHE Instruction Cache DCACHE Data Cache SPRAM Scratch Pad RAM PMI DMI LDRAM Local Data RAM TriCore OVRAM Overlay RAM 16 KB SPRAM CPU 116 KB LDRAM BROM Bont ROM 8 KB ICACHE oe 4KB DCACHE P E SS Configurable z Configurable PRAM Parameter RAM in PCP CMEM Code RAM in PCP CPS ili iml ptional Ext Supply LBCU l EVR Local Memory Bus LMB 13v 3 3V EYR 5v 3 3V Int Supply Be Single source Ext Supply 9 _ 1 5 MB PFlash DMA 64 KB Dflash LFI Bridge 16 channels 16 KB BROM T 8 KB OVRAM OCDS 11 Deb cl Interface System Peripheral Bus JTAG DAP lt gt T 8KBPRAM SES m g a T Interrupt ASCO E 2 System lt gt MLIO PCP2 amp L KG coe E s 9 a ASC1 a iocos STM MemChe
54. O Input 12 CCU60 l CTRAPB CCU61 l T13HRE OUT12 01 GPTAO Output 12 OUT68 O2 GPTAO Output 68 TXENA O3 E Ray Channel A transmit Data Output enable 137 P0 13 1 00 A2 Port 0 General Purpose I O Line 13 IN13 PU GPTAO Input 13 OUT13 O1 GPTAO Output 13 OUT69 O2 GPTAO Output 69 TXENB O3 E Ray Channel B transmit Data Output enable 143 P0 14 1 00 A1 Port 0 General Purpose I O Line 14 IN14 PU GPTAO Input 14 REQ4 l External Request Input 4 CCU61 l CC61INC OUT14 O1 GPTAO Output 14 OUT70 O2 GPTAO Output 70 CCU60 03 CC61 144 P0 15 1 00 A1 Port 0 General Purpose I O Line 15 IN15 PU GPTAO Input 15 REQ5 l External Request Input 5 OUT15 01 GPTAO Output 15 OUT71 O2 GPTAO Output 71 CCU60 O3 COUT61 Port 1 Data Sheet 3 5 V1 2 2014 06 ec Infineon Hm Pinning Table 3 1 Pin Definitions and Functions PG LQFP 144 17 package contd Pin Symbol Ctrl Type Function 92 P1 0 1 00 A2 Port 1 General Purpose I O Line 0 REQ15 l PU External Request Input 15 IN16 l GPTAO Input 16 BRKIN l Break Input OUT16 01 GPTAO Output 16 OUT72 O2 GPTAO Output 72 GPT120 O3 TSOUT BRKOUT O Break Output controlled by OCDS module 95 P1 1 1 00 A1 Port 1 General Purpose I O Line 1 IN17 PU GPTAO Input 17 CCU60 l T13HRE CCU61 l CTRAPB OUT17 01 GPTAO Output 17 OUT73 O2 GPTAO Output 73
55. ON uisus spud meon pce oder RR ve XO eee De s 5 81 Data Sheet l 2 V1 2 2014 06 Infineon Waiting 1 Summary of Features Summary of Features The SAK TC1724F 192F133HL SAK TC1724F 192F133HR has the following features High performance 32 bit super scalar TriCore V1 3 1 CPU with 4 stage pipeline Superior real time performance Strong bit handling Fully integrated DSP capabilities Single precision Floating Point Unit FPU 133 MHz operation at full temperature range 32 bit Peripheral Control Processor with single cycle instruction PCP2 8 Kbyte Parameter Memory PRAM 24 Kbyte Code Memory CMEM 133 MHz operation at full temperature range Multiple on chip memories 1 5 Mbyte Program Flash Memory PFLASH with ECC 64 Kbyte Data Flash Memory DFLASH usable for EEPROM emulation 120 Kbyte Data Memory LDRAM Instruction Cache up to 8Kbyte ICACHE configurable 24 Kbyte Code Scratchpad Memory SPRAM Data Cache up to 4 Kbyte DCACHE configurable 8 Kbyte Overlay Memory OVRAM 16 Kbyte BootROM BROM 16 Channel DMA Controller Sophisticated interrupt system with 2 x 255 hardware priority arbitration levels serviced by CPU or PCP2 High performing on chip bus structure 64 bit Local Memory Buses between CPU Flash and Data Memory 32 bit System Peripheral Bus SPB for on chip peripheral and functional units One bus bridge LFI Bridge
56. ROJCL Unit Note 1 p 1 TC1724 PG LQFP 144 17 9 0 0 4 28 1 K W 1 The top and bottom thermal resistances between the case and the ambient Rycat Rrcap are to be combined with the thermal resistances between the junction and the case given above LK rcr Rz cg in order to calculate the total thermal resistance between the junction and the ambient Rz 4 The thermal resistances between the case and the ambient Ry a7 Rtcag depend on the external system PCB case characteristics and are under user responsibility The junction temperature can be calculated using the following equation T T4 Ryy x Pp where the Rija is the total thermal resistance between the junction and the ambient This total junction ambient resistance Ry can be obtained from the upper four partial thermal resistances Data Sheet 5 77 V1 2 2014 06 Infineon Mes Electrical Parameters 5 4 2 Package Outline Caj 2 204 277 ij 0 MIN El Z S m AT HHHH HIHHH 2 259 08 C 144x COPLANARITY 16 MAX 0 10 05 STAND OFF fo 025 14 2005 KTZ 7 eg b L E G L I s 0 2 MIN 06 4015 C SEATING PLANE 2 LOCATION 8 LOCATION B 10 2 A B DTH 22 hd 2 LOCATION A 1
57. Reserved O3 78 P1 3 1 00 A1 Port 1 General Purpose I O Line 3 IN19 l PU GPTAO Input 19 OUT19 O1 GPTAO Output 19 OUT75 O2 GPTAO Output 75 CCU61 O3 COUT63 79 P1 4 1 00 A1 Port 1 General Purpose I O Line 4 IN20 l PU GPTAO Input 20 EMGSTOP I Emergency Stop Input OUT20 O1 GPTAO Output 20 OUT76 O2 GPTAO Output 76 CCU61 O3 COUT61 Data Sheet 3 6 V1 2 2014 06 ec Infineon mm Pinning Table 3 1 Pin Definitions and Functions PG LQFP 144 17 package cont d Pin Symbol Ctrl Type Function 74 P1 8 1 00 A1 Port 1 General Purpose I O Line 8 IN24 PU GPTAO Input 24 IN48 l GPTAO Input 48 MTSR1B l SSC1 Slave Receive Input B Slave Mode CCU61 l CCPOS2C GPT120 l T4EUDB GPT121 l T4EUDA OUT24 01 GPTAO Output 24 OUT48 O2 GPTAO Output 48 MTSR1B O3 SSC1 Master Transmit Output B Master Mode 75 P1 9 1 00 A1 Port 1 General Purpose I O Line 9 IN25 l PU GPTAO Input 25 IN49 l GPTAO Input 49 MRST1B l SSC1 Master Receive Input B Master Mode CCU61 l CCPOS1C GPT120 l T2EUDB GPT121 l T2EUDA OUT25 01 GPTAO Output 25 OUT49 O2 GPTAO Output 49 MRST1B O3 SSC1 Slave Transmit Output B Slave Mode 76 P1 10 1 00 A1 Port 1 General Purpose I O Line 10 IN26 l PU GPTAO Input 26 IN50 l GPTAO Input 50 OUT26 O1 GPTAO Output 26 OUT50 O2 GPTAO Output 50 SLSO17 O3 SSC1
58. TAG Timing Data Sheet 5 64 V1 2 2014 06 Infineon nes Electrical Parameters 5 3 10 DAP Interface Timing The following parameters are applicable for communication through the DAP debug interface Note These parameters are not subject to production test but verified by design and or characterization Table 34 DAP Parameters Parameter Symbol Values Unit Note Min Typ Max Test Condition DAPO clock period trek SR 12 5 ns DAPO high time ty SR 14 ns DAPO low time ta SR 4 ns DAPO clock rise time t4 SR 2 ns DAPO clock fall time t5 SR 2 ns DAP1 setup to DAPO tig SR 6 0 ns rising edge DAP1 hold after DAPO tuz BR 46 0 ns rising edge DAP1 valid per DAPO fa CC 8 ns C 7 20 pF clock period f 80 MHz 10 ns C 50 pF f 40 MHz 1 See the DAP chapter for clock rate restrictions in the Active IDLE protocol state 2 The Host has to find a suitable sampling point by analyzing the sync telegram response MC DAPO Figure 19 Test Clock Timing DAPO Data Sheet 5 65 V1 2 2014 06 Infineon TENDS Electrical Parameters DAP1 MC DAP1 RX Figure 20 DAP Timing Host to Device MC DAP1 TX Figure 21 DAP Timing Device to Host Data Sheet 5 66 V1 2 2014 06 Infineon nes Electrical Parameters 5 3 11 Peripheral Timings Note Peripheral timings are not subjected t
59. TC1724F 192F133HL SAK TC1724F 192F133HR 1950 mW power pattern max mode 5V only with ext pass device SAK TC1724N 192F 133HR 1428 mW power pattern realistic mode 5V only with ext pass device SAK TC1724F 192F133HL SAK TC1724F 192F133HR 1403 mW power pattern realistic mode 5V only with ext pass device SAK TC1724N 192F 133HR Maximum power dissipation PD CC 810 mW power pattern max mode all external SAK TC1724N 192F80HL SAK TC1724N 192F80HR 669 mW power pattern realistic mode all external SAK TC1724N 192F80HL SAK TC1724N 192F80HR Data Sheet 5 44 V1 2 2014 06 Infineon nes Electrical Parameters Table 27 Power Supply Parameters cont d Parameter Symbol Values Unit Note Test Condition Min Typ Max Maximum power PD 1628 mW power pattern max dissipation CC mode 5V only without ext pass device SAK TC1724N 192F80HL SAK TC1724N 192F80HR 1200 mW power pattern realistic mode 5V only without ext pass device SAK TC1724N 192F80HL SAK TC1724N 192F80HR Infineon Power Loop CPU and PCP running all peripherals active The power consumption of each customer application will most probably be lower than this value but must be evaluated separately zx 2 For operations including the D Flash the required current is always lower than the c
60. Vopp V 100 UA Vx0 36x Vopp V Spike filter always fari CC 10 ns only PORST pin blocked pulse duration Spike filter pass through rar CC 120 x ns only PORST pin pulse duration Table 17 Standard Pads Class A1 Parameter Symbol Values Unit Note Min Typ Max Test Condition Input Hysteresis for HYSA CC 0 1x V pads of all A classes Y sue Input Leakage Current oza CC 500 500 nA Vis Vppp V V20V Class A1 40 C X T lt 150 C 750 750 nA Vi lt Vopr V VE OV 150 C lt T lt 160 C Ratio Vil Vih A1 pads Via 0 6 Vinar CC Data Sheet V1 2 2014 06 Cinfineon TC1724 Electrical Parameters Table 17 Standard Pads Class A1 cont d Parameter Symbol Values Unit Note Min Typ Max Test Condition On Resistance ofthe Rosonw 450 600 Ohm Joy gt 0 5 mA class A1 pad weak CC P MOS driver 210 340 Ohm las 0 5 mA N MOS On Resistance of the Rpsonm m 155 Ohm Top 2 mA class A1 pad medium CC P MOS driver 110 Ohm las 2 mA N_MOS Fall time pad type A1 Itea CC 150 ns CS 20 pF pin out driver weak 50 ns CS 50 pF pin out driver medium 140 ns C 150 pF pin out driver medium 550 ns C 150 pF pin out driver weak 18000 ns C 20000 pF pin out driver medium 65000 ns C 20000 pF pin out driver weak Rise time pad type A1
61. al Input 19 AN39 l Analog Input ADC1 CH23 Analog Input Port 57 ANO D Analog Input 0 ADCO CHO 56 AN1 l D Analog Input 1 ADCO CH1 55 AN2 l D Analog Input 2 ADCO CH2 54 AN3 D Analog Input 3 ADCO CH3 53 AN4 D Analog Input 4 ADCO CHA 52 AN5 D Analog Input 5 ADCO CH5 51 ANG D Analog Input 6 ADCO CH6 34 AN7 l D Analog Input 7 ADCO CH7 50 AN8 l D Analog Input 8 ADCO CH8 49 AN9 D Analog Input 9 ADCO CH9 48 AN10 D Analog Input 10 ADCO CH10 47 AN11 l D Analog Input 11 ADCO CH11 46 AN12 l D Analog Input 12 ADCO CH12 Data Sheet 3 23 V1 2 2014 06 Infineon Ies Pinning Table 3 1 Pin Definitions and Functions PG LQFP 144 17 package cont d Pin Symbol Ctrl Type Function 45 AN13 D Analog Input 13 ADCO CH13 40 AN14 D Analog Input 14 ADCO CH14 39 AN15 D Analog Input 15 ADCO CH15 38 AN16 l D S Analog Input 16 ADC1 CHO Digo 37 AN19 D S Analog Input 19 ADC1 CH3 Dig3 36 AN23 D S Analog Input 23 ADC1 CH7 Dig7 35 AN25 D S Analog Input 25 ADC1 CHG Dig9 33 AN32 l D Analog Input 32 FADC_FADINOP 32 AN33 l D Analog Input 33 FADC_FADINON 31 AN34 l D Analog Input 34 FADC_FADIN1P 30 AN35 l D Analog Input 35 FADC FADIN1N 29 AN36 D S Analog Input 36 ADC1 CH20 Dig16 28 AN37 D S Ana
62. al Purpose I O Line 13 SLSI11 PU SC1 Slave Select Input 1 SDIO l MSCO Serial Data Input 0 CCU60 l CTRAPA CCU61 l T12HRE Reserved 01 SLSO16 O2 SSC1 Slave Select Output 6 GPT120 O3 T6OUT Port 3 Data Sheet 3 11 V1 2 2014 06 ec Infineon eint Pinning Table 3 1 Pin Definitions and Functions PG LQFP 144 17 package contd Pin Symbol Ctrl Type Function 112 P3 0 1 00 A1 Port 3 General Purpose I O Line 0 RXDOA PU ASCO Receiver Input A Async amp Sync Mode REQ6 l External Request Input 6 RXDOA O1 ASCO Output Sync Mode Reserved O2 OUT84 O3 GPTAO Output 84 111 P3 1 1 00 A1 Port 3 General Purpose I O Line 1 TXDO o1 PU asco Output Reserved O2 OUT85 O3 GPTAO Output 85 105 P32 1 00 A1 Port 3 General Purpose I O Line 2 SCLKO l PU SCO Clock Input Slave Mode SCLKO O1 SSCO Clock Output Master Mode Reserved O2 OUT86 O3 GPTAO Output 86 106 P3 3 1 00 A1 Port 3 General Purpose I O Line 3 MRSTO l PU SCo Master Receive Input Master Mode MRSTO 01 SSCO Slave Transmit Output Slave Mode Reserved O2 OUT87 O3 GPTAO Output 87 108 P3 4 lOO A2 Port 3 General Purpose I O Line 4 MTSRO l PU SCO Slave Receive Input Slave Mode MTSRO O1 SSCO Master Transmit Output Master Mode Reserved O2 OUT88 O3 GPTAO Output 88 102 P
63. ar approximation they do not define step function 13 The broken wire detection delay against V4oyp is measured in numbers of consecutive precharge cycles at a conversion rate of not more than 250us Results below 10 199 14 The broken wire detection delay against Varep is measured in numbers of consecutive precharge cycles at a conversion rate of not more than 10us This function is influenced by leakage current in particular at high temperature Results above 60 9994 15 Measured without noise 16 For 10 bit conversion the TUE is 2LSB for 8 bit conversion the TUE is 1LSB 17 A running conversion may become inexact in case of violating the normal conditions voltage overshoot 18 If the reference voltage Varer increase or the Vopy decrease so that Varer Voom 0 05V to Vpom 0 07V then the accuracy of the ADC decrease by 4LSB12 Data Sheet 5 27 V1 2 2014 06 Cinfineon TC1724 Electrical Parameters ADC parameter in Table 23 are valid for Vbp 1 235 V to 1 365 V Vypy 3 135 V to 3 465 V T 150 C Table 23 3 3V ADC Parameters Parameter Symbo Values Unit Note I Min Typ Max Test Condition Switched capacitance at CAwsw 9 20 pF the analog voltage CC inputs Total capacitance ofan T Cantor 20 130 pF analog input CC Switched capacitance at Capers 15 30 pF the positive reference w CC voltage input Total capacitance of the
64. arked with an two letter abbreviation in column Symbol e CC Such parameters indicate Controller Characteristics which are a distinctive feature of the TC1724 and must be regarded for a system design SR Such parameters indicate System Requirements which must provided by the microcontroller system in which the TC1724 designed in Data Sheet 5 1 V1 2 2014 06 Cinfineon 5 1 2 TC1724 Pad Driver and Pad Classes Summary Electrical Parameters This section gives an overview on the different pad driver classes and its basic characteristics More details mainly DC parameters are defined in the Section 5 2 1 Table 9 Pad Driver and Pad Classes Overview Class Power Type Sub Class Speed Load Leakage Termination Supply Grade 150 C A 3 3 V LVTTL A1 6 MHz 100 pF 500 nA No 1 0 e g GPIO LVTTL lady 25 50 pF 1gA Series outputs e g serial MHz termination I Os recommended A2 40 50pF 3 pA Series e g serial MHz termination I Os recommended DE 5V ADC l 3 3 V LVTTL input only 1 Two values are given for T 150 C and a 50 higher value for T 160 C Data Sheet 5 2 V1 2 2014 06 Cinfineon TC1724 5 1 3 Absolute Maximum Ratings Electrical Parameters Stresses above the values listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of
65. at AINx can deviate from Vaper 2 Mr Applies to AINx when used as auxiliary reference input e This represents an equivalent switched capacitance This capacitance is not switched to the reference voltage at once Instead smaller capacitances are successively switched to the reference voltage The sum of DNL INL GAIN OFF errors does not exceed the related TUE total unadjusted error If the analog reference voltage range is below Vpp but still in the defined range of Vopy 2 and Vppy is used then the ADC converter errors increase If the reference voltage is reduced by the factor k k 1 TUE DNL INL Gain and Offset errors increase also by the factor 1 k 6 If a reduced analog reference voltage between 1V and Vppy 2 is used then there are additonal decrease in the ADC speed and accuracy SE 7 Ifthe analog reference voltage is gt Vppy then the ADC converter errors increase co For 10 bit conversions the error value must be multiplied with a factor 0 25 LO For 8 bit conversions the error value must be multiplied with a factor 0 0625 10 If the alternate reference is used or fapc is more than 16 MHz the accuracy of the ADC may decrease 11 For a conversion time of 1 us a rms value of 85pA result for Inger 12 The leakage current definition is a continous function as shown in figure ADCx Analoge Input Leakage The numerical values defined determine the characteristic points of the given countinuous line
66. ck 24KB CMEM SCU a 3 a CAPCOM 5 f y 2 n CCU60 CCU61 5 x Ports 5V E Ext ADC Supply GPT12 Kh GPT 120 E BMU ADCO a ned t GPT12 SSCO LS enne oe SBCU ADCT K ba sE G SSC1 GPTAO 7 FADC Pas T 3 3V max K 2 differential ssc2 95 ER Ext MultiCAN Request 3 Nodes MSCO SSC3 5 BlockDiagram Unit 64 MO TC1724N V0 8 Figure 2 SAK TC1724N 192F133HR Block Diagram Data Sheet 2 3 V1 2 2014 06 Infineon TC1724 System Overview of the TC1724 Figure 3 shows the block diagram of the SAK TC1724N 192F80HL SAK TC1724N 192F80HR ASCO PMI 16 KB SPRAM 8 KB ICACHE Configurable FPU TriCore CPU TC1 3 1 80MHz 1 5 MB PFlash 64 KB Dflash 16 KB BROM 8 KB OVRAM ASC1 CAPCOM CCU60 CCUG1 GPT12 GPT 120 GPT12 GPT121 GPTAO ils H Local Memory Bus Abbreviations ICACHE Instruction Cache DCACHE Data Cache SPRAM Scratch Pad RAM DMI LDRAM Local Data RAM OVRAM Overlay RAM 116 KB LDRAM BROM Boot ROM 4 KB DCACHE PFlash Program Flash DFlash Data Flash Configurable PRAM Parameter RAM in PCP CMEM Code RAM in PCP 777 Optional Ext Supply gt LBCU l EVR 13v 33vy EVR 5V 3 3V Int Supply neuter Single source Ext Supply DMA 16 channels MS K 3 SMIF lt lt
67. current definition is a continous function as shown in figure ADCx Analoge Input Leakage The numerical values defined determine the characteristic points of the given countinuous linear approximation they do not define step function The broken wire detection delay against V4cyp is measured in numbers of consecutive precharge cycles at a conversion rate of not more than 250us Results below 10 1994 The broken wire detection delay against Varep is measured in numbers of consecutive precharge cycles at a conversion rate of not more than 10us This function is influenced by leakage current in particular at high temperature Results above 60 999 Measured without noise For 10 bit conversion the TUE is 2LSB for 8 bit conversion the TUE is 1LSB JA running conversion may become inexact in case of violating the normal conditions voltage overshoot If the reference voltage Varer increase or the Vppy decrease so that Varer Voom 0 05V to Vppy 0 07V then the accuracy of the ADC decrease by 4LSB12 Table 24 Conversion Time Operating Conditions apply Parameter Symbol Values Unit Note Conversion to CC 2xTapgc 4 STC n x Tang us n 8 10 12 for time with n bit conversion post calibration Tanc 1 frp Conversion 2 x Tape 2 STC n x Tape Tyoci 1 fapci time without post calibration Data Sheet 5 31 V1 2 2014 06 Infineon Ines Electrical Parameters Analog
68. currents during overload condition 1 The port groups are defined in Table 15 Note FADC input pins count as analog pin as they are overlayed with an ADC pins Data Sheet 5 5 V1 2 2014 06 Cinfineon TC1724 Electrical Parameters Table 12 PN Junction Characterisitics for positive Overload Pad Type Ty 2 mA Ty 5 mA A1 A1 Un Vopp 0 6 V Un Vopp 0 7 V A2 Uw Vppe 0 5 V Uy Vppp 0 6 V D S Uw Vppy 0 6 V Table 13 PN Junction Characterisitics for negative Overload Pad Type Ty 3 mA Ty 5 mA A1 A1 Uw Vss 0 6 V Uw Vss 0 7 V A2 Uw Vss 0 5 V Uw Vss 0 6 V D S Un Vasu 0 6 V Note A series resistor at the pin to limit the current to the maximum permitted overload current is sufficient to handle failure situations like short to battery without having any negative reliability impact on the operational life time Data Sheet 5 6 V1 2 2014 06 Infineon nes Electrical Parameters 5 1 5 Operating Conditions The following operating conditions must not be exceeded in order to ensure correct operation and reliability of the TC1724 All parameters specified in the following tables refer to these operating conditions unless otherwise noticed Digital supply voltages applied to the TC1724 from external must be static regulated voltages which allow a typical voltage swing of 5 96 All parameters specified in the foll
69. devices with internal pass devices Output AVouti3 30 30 mV 2 97Vs Vy lt 3 63V accuracy of CC 1 MAS laur x250mA EVR13 after trimming Dynamic Load AV oree l 100 mV 5 0V 3 3V single supply Regulation of 43 CC 100 dl dt 150mA 10 ns EVR13 Dynamic Line AViipeg 10 10 mV 5 0V 3 3V single supply Regulation of 4 CC dV5 dt 1V ms EVR13 1 250mA 2 97V 3 63V Undervoltage Vest13 1 17 V Resetthreshold CC for EVR13 Current drawn EXI s 10 mA No inductive loads allowed from EVR13 for SR Decoupling capacitor gt external 100 nF devices Supplyramp up SR 50 V ms SR Data Sheet 5 59 V1 2 2014 06 Infineon nes Electrical Parameters 5 3 7 Phase Locked Loop PLL Table 31 PLL SysCIk Parameters Parameter Symbol Values Unit Note Min Typ Max Test Condition Accumulated Jitter Dp CC 7 7 ns PLL base frequency fpippase CC 50 200 320 MHz VCO input frequency fage CC 8 16 MHz VCO frequency fuco CC 400 720 MHz range PLL lock in time t CC 14 200 us N gt 32 14 400 us N lt 32 Phase Locked Loop Operation When PLL operation is enabled and configured the PLL clock fyco and with it the LMB Bus clock f yg is constantly adjusted to the selected frequency The PLL is constantly adjusting its output frequency to correspond to the input frequency from crystal or clock Source resulting in an accumulated jitter tha
70. duction filter 95 digital general purpose I O lines GPIO Digital I O ports with 3 3 V capability On chip debug support for OCDS Level 1 CPU PCP DMA On Chip Bus Dedicated Emulation Device chip available TC1724ED multi core debugging real time tracing and calibration four five wire JTAG IEEE 1149 1 or two wire DAP Device Access Port interface Power Management System Clock Generation Unit with PLL Data Sheet 1 2 V1 2 2014 06 Infineon Waiting Summary of Features The SAK TC1724N 192F133HR has the following features High performance 32 bit super scalar TriCore V1 3 1 CPU with 4 stage pipeline Superior real time performance Strong bit handling Fully integrated DSP capabilities Single precision Floating Point Unit FPU 133 MHz operation at full temperature range 32 bit Peripheral Control Processor with single cycle instruction PCP2 8 Kbyte Parameter Memory PRAM 24 Kbyte Code Memory CMEM 133 MHz operation at full temperature range Multiple on chip memories 1 5 Mbyte Program Flash Memory PFLASH with ECC 64 Kbyte Data Flash Memory DFLASH usable for EEPROM emulation 120 Kbyte Data Memory LDRAM Instruction Cache up to 8Kbyte ICACHE configurable 24 Kbyte Code Scratchpad Memory SPRAM Data Cache up to 4 Kbyte DCACHE configurable 8 Kbyte Overlay Memory OVRAM 16 Kbyte BootROM BROM 16 Channel DMA Controller Sophisticated interrupt syst
71. during reset PORST 0 Data Sheet 3 26 V1 2 2014 06 TC1724 Cinfineon Identification Registers 4 Identification Registers The Identification Registers uniquely identify the device Table 2 SAK TC1724F 192F133HL Identification Registers Short Name Value Address Stepping CBS_JDPID 0000 6350 F000 0408 AB CBS_JTAGID 101D 0083 F000 0464 AB SCU_MANID 0000 1820 F000 0644 AB SCU_CHIPID 0300 A601 F000 0640 AB SCU_RTID 0000 0001 F000 06484 AB Table 3 SAK TC1724F 192F133HR Identification Registers Short Name Value Address Stepping CBS_JDPID 0000 63504 F000 04084 AB CBS_JTAGID 101D 00834 F000 0464 AB SCU_MANID 0000 18204 F000 0644 AB SCU_CHIPID 8300 A6014 F000 06404 AB SCU_RTID 0000 00014 F000 0648 AB Table 4 SAK TC1724F 192F133HR Identification Registers Short Name Value Address Stepping CBS_JDPID 0000 63504 F000 04084 AC CBS_JTAGID 101D 00834 F000 0464 AC SCU_MANID 0000 1820 F000 0644 AC SCU_CHIPID 8300 A6014 F000 06404 AC SCU_RTID 0000 00024 F000 0648 AC Table 5 SAK TC1724N 192F133HR Identification Registers Short Name Value Address Stepping CBS_JDPID 0000 63504 F000 04084 AC CBS_JTAGID 101D 00834 F000 04644 AC SCU_MANID 0000 1820 F000 0644 AC Data Sheet 4 1 V1 2 2014 06 Cinfineon TC1724 Identification Registers
72. e and t TCLK fall time to 0 3 x t10 MSC parameters Added text for MSC parameters valid for CL 25pF Added limits for different pad drive strength of t45 Data Sheet 5 83 V1 2 2014 06 Infineon nes Electrical Parameters parameters Changed min value of tts to 16 5ns ERAY parameters Changed min value of fg Changed max value of f t 5 Changed min and max values of tc Changed max value of tg fg Added dTxdly dRxdly Updated ERAY timing figure Flash32 parameters Updated tprp tprp Changed min value of WSp to 50ns x fi yug Updated footnote 3 Package parameters Added Ry cr Kren ruue for LQFP144 Package outline Added package outline for LQFP176 Changes from V0 5 to V0 6 Added max limit for Vests for 5 ov single supply Removed note above MLI Transmitter table Updated conditions for re and tg for LVDS pad parameters Updated limits for Rosonw and Rosonm for Class A1 pads Updated limits for Rosonw and Rogonm and Rpsoy for Class A1 pads Updated limits for Rosonw and Rosonm and Rosonz for Class A2 pads Updated limits for Rosonw and Rpsoyy for Class F pads Added footnote 7 to ADC table Updated Qconyof ADC table Updated conditions to of PLL Sysclk Changed 49 of DAP from SR to CC Removed condition for V5 Added FADC input circuit Updated max limit for Vacnpo and min limit for Varro tewe and fgyg are added to ADC table Updated description o
73. em with 2 x 255 hardware priority arbitration levels serviced by CPU or PCP2 High performing on chip bus structure 64 bit Local Memory Buses between CPU Flash and Data Memory 32 bit System Peripheral Bus SPB for on chip peripheral and functional units One bus bridge LFI Bridge Versatile On chip Peripheral Units Two Asynchronous Synchronous Serial Channels ASC with baud rate generator parity framing and overrun error detection Four High Speed Synchronous Serial Channels SSC with programmable data length and shift direction One serial Micro Second Bus interface MSC for serial port expansion to external power devices One High Speed Micro Link interface MLI for serial inter processor communication One MultiCAN Module with 3 CAN nodes and 64 free assignable message objects for high efficiency data handling via FIFO buffering and gateway data transfer One General Purpose Timer Array Module GPTA providing a powerful set of digital signal filtering and timer functionality to realize autonomous and complex Input Output management Two Capture Compare Unit 6 CAPCOM6 kernels Data Sheet 1 3 V1 2 2014 06 Infineon Waiting Summary of Features Two General Purpose Timer GPT12 modules 28 analog input lines for ADC 2 independent kernels ADCO and ADC1 Analog supply voltage range from 3 3 V to 5 V single supply 2 different FADC input channels channels with im
74. er pattern max supply current CC SAK TC1724F 192F133HL SAK TC1724F 192F133HR SAK TC1724N 192F 133HR j 212 mA power pattern realistic SAK TC1724F 192F133HL SAK TC1724F 192F133HR SAK TC1724N 192F133HR 248 mA power pattern max SAK TC1724N 192F80HL SAK TC1724N 192F80HR 160 mA power pattern realistic SAK TC1724N 192F80HL SAK TC1724N 192F80HR Ipp current at Ino porst 110 mA PORST Low PORST pad Ippporst 139 mA output current Sum of all 1 3 V Tppsum 212 mA power pattern realistic supply currents CC SAK TC1724F 192F133HL SAK TC1724F 192F133HR SAK TC1724N 192F133HR 160 mA power pattern realistic SAK TC1724N 192F80HL SAK TC1724N 192F80HR SAK TC1724F 192F80HR Tppp current at lbbp Pors 6 mA PORST Low CC Data Sheet 5 41 V1 2 2014 06 Cinfineon Table 27 Power Supply Parameters cont d TC1724 Electrical Parameters Parameter Symbol Values Unit Note Test Condition Min Typ Max Tppp current no lane CC l Tppp_ mA including flash read current pad activity KORST 83 J Ippp mA including flash programming PORET current 62 j lbp mA including flash erase verify BORS current 91 ADC 5V power Janu 32 mA supply current CC EVR Supply vs 375 mA_ power pattern max current CC mode 5V only with ext pass device SAK TC1724F 192F133HL SAK TC1724F 192F133HR 370 m
75. eral Purpose Timer GPT12 modules 28 analog input lines for ADC 2 independent kernels ADCO and ADC1 Analog supply voltage range from 3 3 V to 5 V single supply 2 different FADC input channels channels with impedance control and overlaid with ADC1 inputs Extreme fast conversion 21 cycles of fanc clock 10 bit A D conversion higher resolution can be achieved by averaging of consecutive conversions in digital data reduction filter 95 digital general purpose I O lines GPIO Digital I O ports with 3 3 V capability On chip debug support for OCDS Level 1 CPU PCP DMA On Chip Bus Dedicated Emulation Device chip available TC1724ED multi core debugging real time tracing and calibration four five wire JTAG IEEE 1149 1 or two wire DAP Device Access Port interface Power Management System Clock Generation Unit with PLL Data Sheet 1 6 V1 2 2014 06 Infineon Waiting Summary of Features Ordering Information The ordering code for Infineon microcontrollers provides an exact reference to the required product This ordering code identifies The derivative itself i e its function set the temperature range and the supply voltage The package and the type of delivery For the available ordering codes for the TC1724 please refer to the Product Catalog Microcontrollers which summarizes all available microcontroller variants This document describes the derivatives of the device The
76. ers from CC to SR for tss t5 Tag and tsg Changed min to max limit for EVR Supply ramp up parameter Updated min limit for Ipu yppc Changes from V0 8 to V1 0 Added limits for EF grap for Gain 4 8 Added limits for EF per Data Sheet 5 86 V1 2 2014 06 Infineon nes Electrical Parameters Updated Vesp Vrareri changed from SR to CC A footnote is added for VeAggri Updated limit for Cout13 Updated limit for Cins e Added min limit for V5 Updated limits for fac awe fewr Tawar tawas fewar Tewas Updated limits for ADC table Vopy 3 3V fanc Tawa fewr gt tawar tawas EwaF gt Tewas Rant EApnis EAcain Ew EAore TUE Qconv e Corrected typo in test condition for Roson Removed footnote 2 from Lge p Addedfootnote3to Voom Corrected typo for Class F in Table 14 and Table 15 Updated max limit for ADC parameter ts Added footnote 2 for tg of JTAG parameter Changed t faz from CC to SR Updated max limit for ADC parameter Vain e Added footnote 5 to tsg Added fpor app parameter of Reset Timing parameters Updated max limit for ERAY parameter fan Changes from V1 0 to V1 1 Updated limits for ADC table Vppy 3 3V fancy tewe fewr gt tawar tawas AINTT EApw EAgaw EAn EA arr TUE Ocowy Added new marking options for TC1724 Updated description for toa Added a footnote to Qcony Changes from V1 1 to V1 2 change as from 100ns to 200ns in table 2
77. es can be used for longer RCLK clock periods Table 36 MLI Transmitter Parameter Symbol Values Unit Note Min Typ Max Test Condition TCLK clock period Hn CC 2x1 ns fre TCLK high time hu CC 0 45x 05x 0 55xhg ns tio tio TCLK low time tp CC 0 45x 05x 0 55xto ns tio tio Data Sheet 5 68 V1 2 2014 06 Cinfineon TC1724 Electrical Parameters Table 36 MLI Transmitter cont d Parameter Symbol Values Unit Note Min Typ Max Test Condition TCLK rise time Ha CC 0 3 X t ns TCLK fall time HA CC l 0 3 X ho Ins TDATA TVALID Hs CC 3 4 4 ns output delay time TREADY setup time 4 SR 18 ns before TCLK rising edge TREADY hold time tz BR 2 ns after TCLK rising edge 1 The following formula is valid t11 t12 t10 2 The min max TCLK low high times t11 t12 include the PLL jitter of fSYS Fractional divider settings must be regarded additionally to t11 t12 3 For high speed MLI interface strong driver sharp or medium edge selection class A2 pad is recommended for TCLK 5 3 11 2 Micro Second Channel MSC Interface Timing The MSC parameters are valid for C 50 pF Table 37 MSC Parameters Parameter Symbol Values Unit Note Min Typ Max Test Condition FCLP clock period ta CC 2x ns Tusc Data Sheet 5 69 V1 2 2014 06 Cinfineon TC1724
78. f toa Added a placeholder for Ran Rainzt Rarer fs fapci Aon EAn ZAcain EAorr TUE at a separate ADC table for V55 73 3V Added a placeholder for tawar tawas to both ADC tables for Vopy 5V and Vopy 3 3V Added a placeholder for tear Tewas to FADC table for Vopy 5V Vppm 3 3V Removed limits of gain 8 for EF grap Added Vearer and Veacnp parameters Updated limit of tse to min 120ns Typo in Note for Jys at 80MHz is corrected Data Sheet 5 84 V1 2 2014 06 Infineon nes Electrical Parameters Updated max limit of Xy Added Jy Added Pin Reliability in Overload subchapter Removed sentence Exposure to conditions within the maximum ratings will not affect device reliability Replaced with the Pin Reliability in Overload subchapter Added definition of driver strength settings updated footnote 4 for ERAY Interface Timing Updated max limits of Flash parameters tprp tprp Updated representation of Jppp Updated limits of Ibp porst to max 110mA Updated limits of ppp porsr to max 6mA Updated limits of lon for real pattern l puv1aaaus to max 212mA Added new parameter Jppsum Updated max limit of 5py to 32mA Updated TC1724 Iys for max and real patterns with and without ERAY fopy 133mHz Updated TC1724 Iys for max pattern fceu souuz Updated PD for real pattern fopu 133MHz all external supplies Updated TC1724 PD for max and real patterns with and without ERAY fopy i33mnz 5V only w
79. finitions and Functions PG LQFP 144 17 package cont d Pin Symbol Ctrl Type Function 72 P4 2 lOO A2 Port 4 General Purpose I O Line 2 IN30 PU GPTAO Input 30 IN54 l GPTAO Input 54 CCU60 l T13HRB CCU61 l CCPOS1A GPT120 l T2EUDA GPT121 l T2EUDB OUT30 01 GPTAO Output 30 OUT54 O2 GPTAO Output 54 EXTCLK1 O3 External Clock 1 Output 73 P4 3 1 00 A2 Port 4 General Purpose I O Line 3 IN31 l PU GPTAO Input 31 IN55 l GPTAO Input 55 CCU60 l T12HRE CCU61 l CTRAPA OUT31 01 GPTAO Output 31 OUT55 O2 GPTAO Output 55 EXTCLKO O3 External Clock 0 Output Port 5 1 P5 0 1 00 A1 Port 5 General Purpose I O Line 0 REQ7 PU External Request Input 7 IN40 l GPTAO Input 40 CCU60 l CC621NA CCU61 l CC621NB GPT120 l CAPINB GPT121 l CAPINA OUT40 01 GPTAO Output 40 CCU60 O2 CC62 SLSO20 O3 SSC2 Slave Select Output 0 Data Sheet 3 15 V1 2 2014 06 ec Infineon mm Pinning Table 3 1 Pin Definitions and Functions PG LQFP 144 17 package contd Pin Symbol Ctrl Type Function 2 P5 1 1 00 A1 Port 5 General Purpose I O Line 1 IN41 PU GPTAO Input 41 OUT41 O1 GPTAO Output 41 Reserved O2 SLSO21 O3 SSC2 Slave Select Output 1 3 P5 2 1 00 A1 Port 5 General Purpose I O Line 2 IN42 PU GPTAO Input 42 OUT42 O1 GPTAO Output 42 CCU60 O2 COUT62 SLSO22 O3 SSC2 Slave Select Out
80. hannel A transmit Data Output CCU60 03 CC61 16 P5 9 lOO A2 Port 5 General Purpose I O Line 9 RXDCANO PU CAN Node 0 Receiver Input OUT7 O1 GPTAO Output 7 TXDB1 02 E Ray Channel B transmit Data Output Reserved O3 17 P5 10 1 00 A2 Port 5 General Purpose I O Line 10 OUT8 o1 PU GPTAO Output 8 TXENA O2 E Ray Channel A transmit Data Output enable CCU60 03 COUT61 Data Sheet 3 17 V1 2 2014 06 ec Infineon Hm Pinning Table 3 1 Pin Definitions and Functions PG LQFP 144 17 package cont d Pin Symbol Ctrl Type Function 18 P5 11 1 00 A2 Port 5 General Purpose I O Line 11 OUT9 o1 PU GPTAO Output 9 TXENB O2 E Ray Channel B transmit Data Output enable CCU60 03 COUT63 19 P5 12 1 00 A1 Port 5 General Purpose I O Line 12 CCU6O PU CCPOSOA CCU61 l T12HRB GPT120 l T3INA GPT121 l T3INB OUT19 01 GPTAO Output 19 SLSOO07 O2 SSCO Slave Select Output 7 AD1EMUXO 03 ADC1 External Multiplexer Control Output 0 20 P5 13 1 00 A1 Port 5 General Purpose I O Line 13 CCU60 PU CCPOS1A CCU61 l T13HRB GPT120 l T3EUDA GPT121 l T3EUDB OUT20 O1 GPTAO Output 20 Reserved O2 AD1EMUX1 O3 ADC1 External Multiplexer Control Output 1 21 P5 14 1 00 A1 Port 5 General Purpose I O Line 14 RXDA1 l PU E Ray Channel A Receive Data Input
81. id metastable states and switching due to internal ground bounce It can t be guaranteed that it suppresses switching due to external system noise 2 Vi sp is implemented to ensure J2716 specification It can t be guaranteed that it suppresses switching due to external noise Data Sheet 5 22 V1 2 2014 06 Cinfineon TC1724 5 2 2 Analog to Digital Converters ADCx ADC parameter in Table 22 are valid for Vpp 1 235 V to 1 365 V Vppy 4 75 V to 5 25 V T 150 C Table 22 5V ADC Parameters Electrical Parameters Parameter Symbol Values Unit Note Min Typ Max Test Condition Switched capacitance at Cansw 9 20 pF the analog voltage CC inputs Total capacitance ofan Caintot 20 30 pF analog input CC Switched capacitance at Capersw 15 30 pF the positive reference CC voltage input Total capacitance of the Carertot 20 40 pF voltage reference inputs CC Differential Non Linearity EApy 3 3 LSB ADC Error CC resolution 12 bit 8 9 Gain Error EAcan 3 5 85 LSB ADC CC resolution 12 bit 9 9 Integral Non EA nL 3 3 LSB ADC Linearity 9 9 CC resolution 12 bit 9 Offset Error 997 EAgep 4 4 LSB ADC CC resolution 12 bit 9 9 Data Sheet 5 23 V1 2 2014 06 Cinfineon Table 22 TC1724 5V ADC Parameters cont d Electrical Parameters Parameter Symbol Values Min Typ
82. igned to support even the most demanding high bandwidth real time embedded control systems tasks Additional high level features of the TC1724 include Efficient memory organization instruction and data scratch memories caches Serial communication interfaces flexible synchronous and asynchronous modes Peripheral Control Processor standalone data operations and interrupt servicing DMA Controller DMA operations and interrupt servicing General purpose timers High performance on chip buses On chip debugging and emulation facilities Flexible interconnections to external components Flexible power management The TC1724 is a high performance microcontroller with TriCore CPU program and data memories buses bus arbitration an interrupt controller a peripheral control processor and a DMA controller and several on chip peripherals The TC1724 is designed to meet the needs of the most demanding embedded control systems applications where the competing issues of price performance real time responsiveness computational power data bandwidth and power consumption are key design elements The TC1724 offers several versatile on chip peripheral units such as serial controllers timer units CAPCOM6 and Analog to Digital converters Within the TC1724 all these peripheral units are connected to the TriCore CPU system via the Flexible Peripheral Interconnect FPI Bus and the Local Memory Bus LMB Several I O lines on the
83. ith external pass device M Updated TC1724 PD for max and real patterns fcPu aoMuz 5V only without external pass device Updated limit for Rpsonz of A2 pad P MOS e Removed Vj for Pass Device Detector Updated limits for V of Pass Device Detector Updated limits and test conditions for AV opE633 and AV iggoas Updated test condition for 5 0V single supply AV orEG13 Updated limits and test condition for 5 0V single supply AV ingo43 e Corrected typ and max limits for Coyt33 and Cours Added limit and test condition for 3 3V single supply AV anges and AV iREG13 Application reset boot time limits are updated Added min limit for 7575 Added a new parameter Vj sp Updated limits for tgp STT Removed typical text from load of Peripheral Timing sections Limits for EF gpap with Gain 4 is changed to TBD e Min limit for V5o is changed to TBD Added EF per Added a placeholder for Rea EF pnt EF int EF crap EF ore at a separate ADC table for Vppy 3 3V Added max and typ limits for Rey for Vopy 3 3V Updated limits of Pp for real pattern fcopy gomrz to max 669mW Added new variant SAK TC1724F 192F80HR Updated text for Note column of Ne Data Sheet 5 85 V1 2 2014 06 Infineon nes Electrical Parameters Corrected typo for Class D pads in PN Junction Characteristics for positive negative overload tables Updated limits of pp for max pattern fopyzi33mHz to max 310mA Updated limits of pp f
84. itic elements the voltage measured at AINx can deviate from Vaper 2 Data Sheet 5 30 V1 2 2014 06 Sg SUE 9 10 11 12 13 14 15 16 17 18 Infineon nes Electrical Parameters Applies to AINx when used as auxiliary reference input This represents an equivalent switched capacitance This capacitance is not switched to the reference voltage at once Instead smaller capacitances are successively switched to the reference voltage The sum of DNL INL GAIN OFF errors does not exceed the related TUE total unadjusted error If the analog reference voltage range is below Vppy but still in the defined range of Vopy 2 and Vppy is used then the ADC converter errors increase If the reference voltage is reduced by the factor k k 1 TUE DNL INL Gain and Offset errors increase also by the factor 1 k If a reduced analog reference voltage between 1V and Vppy 2 is used then there are additonal decrease in the ADC speed and accuracy If the analog reference voltage is gt Vppy then the ADC converter errors increase For 10 bit conversions the error value must be multiplied with a factor 0 25 For 8 bit conversions the error value must be multiplied with a factor 0 0625 If the alternate reference is used or fanc is more than 16 MHz or STC is lower than 8 the accuracy of the ADC may decrease Ocowy is calculated as Ocony Carer Varer The Qconv can be calculated according to this formula The leakage
85. l Purpose I O Line 11 REQ1 PU External Request Input 1 Reserved O1 Reserved O2 OUT93 O3 GPTAO Output 93 Data Sheet 3 13 V1 2 2014 06 ec Infineon Hm Pinning Table 3 1 Pin Definitions and Functions PG LQFP 144 17 package cont d Pin Symbol Ctrl Type Function 119 P3 12 1 00 A1 Port 3 General Purpose I O Line 12 RXDCANO PU CAN Node 0 Receiver Input RXDOB l ASCO Receiver Input B RXDOB O1 ASCO Receiver Output B Synchronous Mode Reserved O2 OUT94 O3 GPTAO Output 94 118 P3 13 1 00 A2 Port 3 General Purpose I O Line 13 TXDCANO 01 PU CAN Node 0 Transmitter Output TXDO O2 ASCO Transmit Output OUT95 O3 GPTAO Output 95 110 P3 14 1 00 A1 Port3 General Purpose I O Line 14 RXDCAN1 PU CAN Node 1 Receiver Input RXD1B l ASC1 Receiver Input B SDI2 l MSCO Serial Data Input 2 RXD1B O1 ASC1 Receiver Output B Synchronous Mode Reserved O2 OUT96 O3 GPTAO Output 96 109 P3 15 1 00 A2 Port 3 General Purpose I O Line 15 TXDCAN1 01 PU CAN Node 1 Transmitter Output TXD1 O2 ASC1 Transmit Output OUT97 O3 GPTAO Output 97 Port 4 Data Sheet 3 14 V1 2 2014 06 ec Infineon Hm Pinning Table 3 1 Pin De
86. log Input 37 ADC1 CH21 Dig17 27 AN38 D S Analog Input 37 ADC1 CH22 Dig18 26 AN39 D S Analog Input 37 ADC1 CH23 Dig19 44 Voom ADC Analog Part Power Supply 3 3V 5V 43 Vssm ADC Analog Part Ground 42 VAREFo ADCO and ADC1 Reference Voltage 41 VAGNDO ADC Reference Ground Vun Digital Core Power Supply 1 3V 12 239 58 84 125 22 Vopp Port Power Supply 3 3V 59 85 126 Data Sheet 3 24 V1 2 2014 06 ge TC1724 Infineon Pinning Table 3 1 Pin Definitions and Functions PG LQFP 144 17 package cont d Pin Symbol Ctrl Type Function 24 Vs EVR Power Supply 5V 60 86 127 25 Vepc EVR Pass Device Gate Ifthis pin is connected to ground the internal pass devices are used and the external pass device bypassed 80 Vas Digital Ground 83 81 XTAL1 l Main Oscillator Input 82 XTAL2 O Main Oscillator Output 88 TMS l A2 JTAG State Machine Control Input DAP1 UO PD Device Access Port Line 1 90 TRST l A1 JTAG Reset Input PD 91 TCK l A1 JTAG Clock Input DAPO l PD Device Access Port Line 0 94 TESTMODE I lPU Test Mode Select Input 96 ESR1 lO A2 External System Request Reset Input 1 PD 97 PORST l I PU Power On Reset 98 ESRO I O A2 External System Request Reset Input 0 Default configuration during and after reset is open drain driver The driver drives low during power on reset
87. log Input Stage FAINxP r 7 FADC Reference Voltage Vines Input Circuitry from IVR eo gt VeaREF VEAGND FADC InpRefDiag Figure 9 Data Sheet FADC Input Circuits 5 38 V1 2 2014 06 Cinfineon TC1724 5 2 4 Oscillator Pins Electrical Parameters Table 26 OSC XTAL Parameters Parameter Symbol Values Unit Note Min Typ Max Test Condition Input current at XTAL1 Jyx CC 25 25 pA Vin gt OV Vi Vope Input frequency fosc SR 4 40 MHz Direct Input Mode selected 8 25 MHz External Crystal Mode selected Oscillator start up time foses CC 10 ms Input high voltage at Vinx SR O7x Vope IV XTAL1 Vous 0 5 Input low voltage at Vix SR 0 5 0 3 x V XTAL1 Vppp Input hysteresis for HYSAX 200 mV XTAL1 pad CC 1 foscs is defined from the moment when Vppp 3 13V until the oscillations reach an amplitude at XTAL1 of 0 3 Vppp The external oscillator circuitry must be optimized by the customer and checked for negative resistance as recommended and specified by crystral suppliers 2 If the XTAL1 pin is driven by a crystal reaching a minimum amplitude peak to peak of 0 3 Vatan is necessary 3 Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce It can t be guaranteed that it suppresses switching due to external system noise Note It is st
88. lues Unit Note Test Condition Min Typ Max Output Cours 6 8 UE Z oap lt 250 mA Capacitance on CC ESR lt 50mQ Vun additional decoupling capacitor on each supply pin SAK TC1724F 192F133HL SAK TC1724F 192F133HR SAK TC1724N 192F133HR 4 7 HF Z oan lt 250 mA ESR 50mQ additional decoupling capacitor on each supply pin SAK TC1724N 192F80HL SAK TC1724N 192F80HR Input Cy CC 6 8 UE depending on ext regulator Capacitance on SAK TC1724F 192F133HL V SAK TC1724F 192F133HR SAK TC1724N 192F133HR 4 7 UE depending on ext regulator SAK TC1724N 192F80HL SAK TC1724N 192F80HR Undervoltage Vests 2 97 V 3 3V single supply Reset threshold CC 45 V 5 0 single supply for external supply Output AVouta3 80 80 mV 4 5V lt Vy x 5 5V accuracy of CC 1 MAS la x310mA EVR33 after trimming Dynamic Load AVi ongc 225 mV dl dt 150mA 10 ns Regulation of 44 CC 225 EVR33 Dynamic Line AV rece 25 25 mV dV5 dt 1V ms Regulation of 44 CC 1 310mA EVR33 4 5V 5 5V Data Sheet 5 58 V1 2 2014 06 Cinfineon TC1724 Electrical Parameters Table 30 EVR Parameters cont d Parameter Symbol Values Unit Note Test Condition Min Typ Max Undervoltage Vkst33 2 97 V Resetthreshold CC for EVR33 Current drawn EXI 4 30 mA No inductive loads allowed from EVR33 for SR Decoupling capacitor gt external 330 nF
89. me at average weighted temperature of 7 150 C is minimum O 7 years 5 4 4 Quality Declarations Table 43 Quality Parameters Parameter Symbol Values Unit Note Test Condition Min Typ Max Operation lob 24000 hours Lifetime ESD susceptibility Via 2000 V Conforming to according to JESD22 A114 B Human Body Model HBM ESD susceptibility Vopy 500 V Conforming to according to JESD22 C101 C Charged Device Model CDM Moisture MSL 3 Conforming to Jedec Sensitivity Level J STD 020C for 240 C 1 This lifetime refers only to the time when the device is powered on Data Sheet 5 80 V1 2 2014 06 Infineon nes Electrical Parameters 2 For worst case temperature profile equivalent to 1200 hours at 7 125 160 C 3600 hours at T 110 125 C 7200 hours at T 100 110 C 11000 hours at T 25 110 C 1000 hours at 7 40 25 C 5 5 Revision History Changes from V0 3 to V0 4D1 Operating Conditions Added footnote 3 and 4 Updated Kovan and Kovap max values Added fopy Jime fece fepimax for SAK TC1724F 192F133HL SAK TC1724F 192F133HR SAK TC1724N 192F80HR SAK TC1724N 128F80HR Updated limits for Vbp Voom Vopp Added Iq I Updated Xlsc pg Standard Pad Class A1 Changed Rpson1 t0 Rpsonm added new condition PMOS for 1400hms added a new condition for NMOS with a max value of
90. o production test They are verified by design characterization 5 3 11 1 Micro Link Interface MLI Timing MLI Transmitter Timing La t TCLKx TDATAx TVALIDx TREADYx MLI Receiver Timing bs b4 RCLKx RDATAx RVALIDx RREADYx MLI_Tmg_2 vsd Figure 22 MLI Interface Timing Data Sheet 5 67 V1 2 2014 06 Infineon nes Electrical Parameters Note The generation of RREADY x is in the input clock domain of the receiver The reception of TREADYx is asynchronous to TCLKx The MLI parameters are valid for C 50 pF strong driver medium edge Table 35 MLI Receiver Parameter Symbol Values Unit Note Min Typ Max Test Condition RCLK clock period too SR 1 fege ns RCLK high time ta SR l 0 5 X tan ns RCLK low time taa BR l 0 5 X tog ns RCLK rise time ta SR l 4 ns RCLK fall time tog BR l 4 ns RDATA RVALID setup t SR 42 ns time before RCLK falling edge RDATA RVALID hold tog SR 2 2 ns time after RCLK falling edge RREADY output delay tz SR 0 16 ns time 1 The following formula is valid t21 t22 t20 2 Min and Max values for this parameter can be derived from the typ value by considering the other receiver timing parameters 3 The RCLK max input rise fall times are best case parameters for fFPImax For reduction of EMI slower input signal rise fall tim
91. om 15 CC 0 8 ns SCLK rising edge MRST setup to SCLK fg SR 165 m ns latching edge MRST hold from SCLK fc SR 0 i ns latching edge SCLK input clock fg SR 4x1 ns period frei SCLK input clock duty fan fg SR 45 55 cycle MTSR setup to SCLK tan SR 1 fep ns latching edge 1 MTSR hold from SCLK taz SR 1 ns latching edge 5 SLSI setup to first SCLK t5 SR 1 lka ns latching edge 5 SLSI hold from last SCLK ts SR 7 ns latching edge MRST delay from SCLK fgg CC 0 16 5 ns shift edge SLSI to valid data on tg CC 16 5 ns MRST 1 SCLK signal rise fall times are the same as the rise fall times of the pad 2 SCLK signal high and low times can be minimum 1xT 3 Tmin TSYS 1 fSYS 4 Fractional divider switched off internal baud rate generation used Data Sheet 5 72 V1 2 2014 06 TC1724 Infineon Electrical Parameters 5 For CON PH 1 slave select must not be removed before the following shifting edge This mean that what ever is configured shifting latching first SLSI must not be de actived before the last trailing edge from the pair of shifting latching edges SCLK MTSR 1 This timing is based on the following setup CON PH CON PO 0 2 The transition at SLSOn is based on the following setup SSOTC TRAIL 0 and the first SCLK high pulse is in the first one of a transmission SSC_TmgMM Figure 24 Master Mode Timing
92. or max pattern fce soy to max 248mA Updated limits of P for max pattern fopy 133mHz to max 902mA Updated limits of Jpp for max pattern fcpu soyuz to max 810mA Corrected typo for Cours Updated load jump current for Coyr33 and Court13 for fopy 80MHz Changed min to typ value for Cins Changes from VO 6 to VO 7 Name of package is updated Changes from V0 7 to V0 8 Absolute maximum rating section for is updated for Vopp Vi Vain Varero VAnF A footnote is added to terp A note is added updated pad supply levels in Pin Reliability in Overload section Updated min limit for t47 of MLI Added a footnote to ppp Included text to power sequencing sections for setting of P0 4 and PO 5 Added limits for EF py for Gain 4 8 Changed STT to teyr updated Power Pad and Reset Timing figure Changed min limit of n for PLL_ERAY timing Changed min limit of t for PLL_Sysclk timing Removed py vpre for V55522 97V Vpps 3 63V Updated limit and test condition for Coursa Cour Updated limit for Cins Updated limit and test condition for AV ongoss Removed PSRR33 PSRR43 Updated test condition for AV oreG13 Updated limit and test condition for AV iREG13 Updated min limit for MSC t45 strong sharp setting CMOS mode Added AVoyr33 AVouyr43 parameters Updated first sentence for Chapter 5 3 Added text for MLI and SSC parameters for validity of strong driver medium edge only Updated description for t5 and ts3 Changed SSC paramet
93. owing list of rules applies to the power up down sequence All ground pins Vas must be externally connected to one single star point in the system Regarding the DC current component all ground pins are internally directly connected The latch up risk is minimized if the I O currents are limited to 20 mA for one pin group AND 100 mA for the completed device I Os Data Sheet 5 48 V1 2 2014 06 Infineon nes Electrical Parameters AND additionally before power up after power down 1 mA for one pin in inactive mode 0 V on all power supplies The PORST signal may be deactivated after all VDD5 and VAREFO power supplies and the oscillator have reached stable operation within the normal operating conditions At normal power down the PORST signal should be activated within the normal operating range and then the power supplies may be switched off Care must be taken that all Flash write or delete sequences have been completed n case of a power loss at any power supply all power supplies must be powered down conforming at the same time to the rule number 2 Although not necessary it is additionally recommended that all power supplies are powered up down together in a controlled way as tight to each other as possible Additionally regarding the ADC reference voltage VAREFO VAREFO must power up at the same time or later then VDDM and VAREFO must power down either earlier or at latest to satisf
94. owing tables refer to these operating conditions Table 14 unless otherwise noticed in the Note Test Condition column Table 14 Operating Conditions Parameters Parameter Symbol Values Unit Note Min Typ Max Test Condition Overload coupling Kovan CC m 0 0001 Ioy2 2 mA factor for analog laws 0 mA analog inputs negative pad 5 0 V Overload coupling Kovap CC 0 00001 Igyz 0 mA factor for analog avs 3 mA analog inputs positive pad 5 0 V CPU Frequency Jepu SR 133 MHz SAK TC1724F 192F133HL SAK TC1724F 192F133HR SAK TC1724N 192F133HR 80 MHz SAK TC1724N 192F80HL SAK TC1724N 192F80HR Data Sheet 5 7 V1 2 2014 06 Cinfineon TC1724 Table 14 Operating Conditions Parameters cont d Electrical Parameters Parameter Symbol Values Min Typ Max Unit Note Test Condition FPI Frequency Jep SR 110 MHz SAK TC1724F 192F133HL SAK TC1724F 192F133HR SAK TC1724N 192F133HR 80 MHz SAK TC1724N 192F80HL SAK TC1724N 192F80HR LMB Frequency Jims SR 133 MHz SAK TC1724F 192F133HL SAK TC1724F 192F133HR SAK TC1724N 192F133HR 80 MHz SAK TC1724N 192F80HL SAK TC1724N 192F80HR PCP Frequency fecr SR 133 MHz SAK TC1724F 192F133HL SAK TC1724F 192F133HR SAK TC1724N 192F133HR 80 MHz SAK TC1724N 192F80HL SAK TC
95. pedance control and overlaid with ADC1 inputs Extreme fast conversion 21 cycles of fanc clock 10 bit A D conversion higher resolution can be achieved by averaging of consecutive conversions in digital data reduction filter 95 digital general purpose I O lines GPIO Digital I O ports with 3 3 V capability On chip debug support for OCDS Level 1 CPU PCP DMA On Chip Bus Dedicated Emulation Device chip available TC1724ED multi core debugging real time tracing and calibration four five wire JTAG IEEE 1149 1 or two wire DAP Device Access Port interface Power Management System Clock Generation Unit with PLL Data Sheet 1 4 V1 2 2014 06 Infineon ences Summary of Features The SAK TC1724N 192F80HL SAK TC1724N 192F80HR has the following features High performance 32 bit super scalar TriCore V1 3 1 CPU with 4 stage pipeline Superior real time performance Strong bit handling Fully integrated DSP capabilities Single precision Floating Point Unit FPU 80 MHz operation at full temperature range 32 bit Peripheral Control Processor with single cycle instruction PCP2 8 Kbyte Parameter Memory PRAM 24 Kbyte Code Memory CMEM 80 MHz operation at full temperature range Multiple on chip memories 1 5 Mbyte Program Flash Memory PFLASH with ECC 64 Kbyte Data Flash Memory DFLASH usable for EEPROM emulation 120 Kbyte Data Memory LDRAM Instruction Cache up to 8Kbyte I
96. pin out driver strong 140 ns C 7 150 pF pin out driver medium Data Sheet 5 19 V1 2 2014 06 Cinfineon Table 19 Standard Pads Class A2 cont d TC1724 Electrical Parameters Parameter Symbol Values Unit Note Min Typ Max Test Condition 550 ns CS 150 pF pin out driver weak 18000 ns C 20000 pF pin out driver medium 65000 ns C 20000 pF pin out driver weak Input high Vinag2 SR 0 6 X Vopp min Vopp V voltage class A2 0 3 pads 3 6 Inputlowvoltage Vas SR 0 3 0 36 x V Class A2 pads Vopp Output voltage Voaz CC Vane 0 4 V Top 1 4 mA pin high class A2 out pads driver medium Vppp 0 4 V Io 1 4 mA pin out driver strong 24 V Toy 2 mA pinout driver medium 24 V Toy 2 mA pin out driver strong Vppp 0 4 V Toy 400 uA pin out driver weak 2 4 V Toy2 500 uA pin out driver weak Output voltage Vo 2CC a 0 4 V Io 2 mA pin out low class A2 driver medium pads 04 V las 2 mA pin out driver strong 0 4 V Ig 500 pA pin out driver weak 1 Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce It can t be guaranteed that it suppresses switching due to external system noise Data Sheet 5 20 V1 2 2014 06 Cinfineon TC1724 Electrical Parameters
97. ply Current 2 00 0066 00 cece eee ee eee 5 40 5 2 5 1 Calculating the 1 3 V Current Consumption 5 45 5 3 AC Parameters ccos kk asd eer ied he ewe eee eevee 5 47 5 3 1 Testing Waveforms ees 5 47 5 3 2 Power Sequencing 5V Supply Only 0 0000 eee eee 5 48 5 3 3 Power Sequencing 3 3V Supply On 000 eee 5 50 5 3 4 Power Sequencing all Voltages supplied from External 5 52 5 3 5 Power Pad and Reset Timing ee eeeee 5 54 5 3 6 EVR Parameter sisse gn RERO EE nua Oy RL eae 5 57 5 3 7 Phase Locked Loop PLL lt s 6 sas ga RR R R RRR RRR R RRR RRR 5 60 5 3 8 ERAY Phase Locked Loop ERAY PLL uaauaaaaaaaaaaaa 5 62 5 3 9 JTAG Interface Timing lt ceres Ra 0 RR 00 eee 5 63 5 3 10 DAP Interface Timing llle 5 65 5 3 11 Peripheral TIMINGS use endte RR dem Re nn 5 67 5 3 11 1 Micro Link Interface MLI Timing 000 0 eee ae 5 67 5 3 11 2 Micro Second Channel MSC Interface Timing 5 69 5 3 11 3 SSC Master Slave Mode Timing eee eens 5 72 5 3 11 4 ERAY Interface Timing llle 5 75 5 4 Package and Reliability llle 5 77 5 4 1 Package Parameters 0c cece eee 5 77 5 4 2 Package Outline coes preissii eie e dn Gero nas wa cea go vine 5 78 Data Sheet l 1 V1 2 2014 06 Infineon Tous Table of Contents 5 4 3 Flash Memory Parameters ele 5 78 5 4 4 Quality Declarations s c 9 R nolo Lb Re eel beached RR RR PER 5 80 5 5 REVISION MISI
98. put 2 4 P5 3 1 00 A1 Port 5 General Purpose I O Line 3 IN43 l PU GPTAO Input 43 OUT43 O1 GPTAO Output 43 Reserved O2 SLSO23 O3 SSC2 Slave Select Output 3 7 P5 4 1 00 A1 Port 5 General Purpose I O Line 4 IN44 l PU GPTAO Input 44 SLSI2A l SSC2 Slave Select Input A OUT44 01 GPTAO Output 44 Reserved O2 SLSO24 O3 SSC2 Slave Select Output 4 8 P5 5 1 00 A1 Port 5 General Purpose I O Line 5 IN45 PU GPTAO Input 45 MRST2A l SSC2 Master Receive Input A Master Mode OUT45 01 GPTAO Output 45 Reserved O2 MRST2 O3 SSC2 Slave Transmit Output Slave Mode Data Sheet 3 16 V1 2 2014 06 ec Infineon mm Pinning Table 3 1 Pin Definitions and Functions PG LQFP 144 17 package cont d Pin Symbol Ctrl Type Function 9 P5 6 1 00 A1 Port 5 General Purpose I O Line 6 IN46 l PU GPTAO Input 46 MTSR2A l SSC2 Slave Receive Input Slave Mode OUT46 01 GPTAO Output 46 Reserved O2 MTSR2 O3 SSC2 Master Transmit Output Master Mode 10 P5 7 1 00 A1 Port 5 General Purpose I O Line 7 IN47 l PU GPTAO Input 47 SCLK2A l SSC2 Clock Input A Slave Mode OUT47 01 GPTAO Output 47 Reserved O2 SCLK2 O3 SSC2 Clock Output Master Mode 15 P5 8 lOO A2 Port 5 General Purpose I O Line 8 CCU60 PU CC61INA CCU61 l CC61INB OUT6 O1 GPTAO Output 6 TXDA1 O2 E Ray C
99. r system Life support devices or systems are intended to be implanted in the human body or to support and or maintain and sustain and or protect human life If they fail it is reasonable to assume that the health of the user or other persons may be endangered Cinfineon Never stop thinking 32 Bit Microcontroller TC1724 32 Bit Single Chip Microcontroller Data Sheet V1 2 2014 06 Microcontrollers Infineon Ms Table of Contents Table of Contents 1 Summary of Features 0 0 0 eee eee 1 1 2 System Overview of the TC1724 0 0c eee eee 2 1 2 1 Block Diagrams 00 e eee 2 2 3 PINNING 1 bs eh ee Oe ep ERE RRR ee eA ed 3 1 4 Identification Registers 0 0 0 0 cee eee 4 1 5 Electrical Parameters 0 00 cece ees 5 1 5 1 General Parameters i 254284 a Re br beak tae 5 1 5 1 1 Parameter Interpretation llle 5 1 5 1 2 Pad Driver and Pad Classes Summary 000 eee 5 2 5 1 3 Absolute Maximum Ratings leeren 5 3 5 1 4 Pin Reliability in Overload BA 5 5 5 1 5 Operating Conditions llle 5 7 5 2 DC Parameters 24s hel pere ne e e ber aee E X ede dur ena 5 11 5 2 1 Input Output PINS trcis Sadek bared FER PvE EA ER ate idee 5 11 5 2 2 Analog to Digital Converters ADCX lessen 5 23 5 2 3 Fast Analog to Digital Converter FADC ssseeessrsse 5 34 5 2 4 Oscillator PINS ieu Meee eee eee 2m Rot doe Mew ae AR ee ae ee 5 39 5 2 5 Power Sup
100. rnal ground bounce It can t be guaranteed that it suppresses switching due to external system noise Table 19 Standard Pads Class A2 Parameter Symbol Values Unit Note Min Typ Max Test Condition Input Hysteresis HYSA2 0 1 X Vppp V for A2 pads CC Data Sheet 5 16 V1 2 2014 06 Cinfineon TC1724 Electrical Parameters Table 19 Standard Pads Class A2 cont d Parameter Symbol Values Unit Note Min Typ Max Test Condition Input Leakage lazaz CC 6000 6000 nA Vi lt Vopp 2 1 current Class A2 V gt Vppp 2 1 V V20V Vis Vope V 3000 3000 nA V Vpyp 2 1V Vi Vppp 2 1V Ratio Vil Vih A2 Vi 42 0 6 pads Via CC On Resistance Rpsouw 450 600 Ohm o gt 0 5 mA of the class A2 CC P_MOS pad weak driver 210 340 Ohm las 0 5 mA N_MOS On Resistance Rbsonm a 155 Ohm Top 2 mA ofthe class A2 CC P MOS pad medium 110 Ohm Ig lt 2 mA driver N_MOS On Resistance Rpsoy CC 42 Ohm Top 2 mA of the class A2 P MOS pad strong driver _ _ 22 Ohm Jo lt 2 mA N_MOS Data Sheet 5 17 V1 2 2014 06 Cinfineon Table 19 TC1724 Standard Pads Class A2 cont d Electrical Parameters Parameter Symbol Values Min Typ Max Unit Note Test Condition Fall time pad type A2 traz CC 150 ns CS 20 pF pin out driver
101. rongly recommended to measure the oscillation allowance negative resistance in the final target system layout to determine the optimal parameters for the oscillator operation Please refer to the limits specified by the crystal or ceramic resonator supplier Data Sheet 5 39 V1 2 2014 06 Infineon nes Electrical Parameters 5 2 5 Power Supply Current The total power supply current defined below consists of leakage and switching component Application relevant values are typically lower than those given in the following two tables and depend on the customer s system operating conditions e g thermal connection or used application configurations The operating conditions for the parameters in the following table are Vpp71 365 V Vopp 3 47 V Vopy 5 1 V fj yg7133 80 MHz T7160 C The realisic power pattern defines the following conditions e T 150 C Simp fece fcpu 133 80 MHz fen 66 5 80 MHz Van 1 326 V Vbpp 3 366 V Voom 5 1 V The max power pattern defines the following conditions T 160 C Jim fpcp fceu 133 80 MHz foni 66 5 80MHz Vun 1 37 V Vppp 3 47 V Voom 5 25 V Data Sheet 5 40 V1 2 2014 06 Cinfineon TC1724 Electrical Parameters Table 27 Power Supply Parameters Parameter Symbol Values Unit Note Test Condition Min Typ Max Core active mode Ipp e 310 mA pow
102. t controlled by OCDS module TDO O JTAG Serial Data Output controlled by OCDS module 13 P9 7 lOO A1 Port 9 General Purpose I O Line 7 CCU61 PU CC60INC Reserved O1 OUT87 O2 GPTAO Output 87 CCU60 03 CC60 14 P9 8 lOO A1 Port 9 General Purpose I O Line 7 Reserved O1 PU OUT88 O2 GPTAO Output 88 CCU60 O3 COUT60 Port 11 38 P11 0 l D S Port 11 General Purpose I O Line 0 DigO l Digital Input 0 AN16 l Analog Input ADC1 CHO 37 P11 3 l D S Port 11 General Purpose I O Line 3 Dig3 l Digital Input 3 AN19 Analog Input ADC1 CH3 36 P11 7 l D S Port 11 General Purpose I O Line 7 Dig7 l Digital Input 7 AN23 l Analog Input ADC1 CH7 Data Sh eet 3 22 V1 2 2014 06 ec Infineon Hes Pinning Table 3 1 Pin Definitions and Functions PG LQFP 144 17 package cont d Pin Symbol Ctrl Type Function 35 P11 9 l D S Port 11 General Purpose I O Line 9 Dig9 l Digital Input 9 AN25 Analog Input ADC1 CH9 Port 12 29 P12 0 l D S Port 12 General Purpose I O Line 0 Dig16 l Digital Input 16 AN36 l Analog Input ADC1 CH20 28 P12 1 l D S Port 12 General Purpose I O Line 1 Dig17 l Digital Input 17 AN37 l Analog Input ADC1 CH21 27 P12 2 l D S Port 12 General Purpose I O Line 2 Dig18 l Digital Input 18 AN38 l Analog Input ADC1 CH22 26 P12 3 l D S Port 12 General Purpose I O Line 3 Dig19 l Digit
103. t are internally connected via diodes must be lower than 100 mV On the other hand all power supply pins with the same name for example all VDDP are internally directly connected It is recommended that the power pins of the same voltage are driven by a single power supply The PORST signal may be deactivated after all VDD5 VDDP VDD and VAREFO power supplies and the oscillator have reached stable operation within the normal operating conditions At normal power down the PORST signal should be activated within the normal operating range and then the power supplies may be switched off Care must be taken that all Flash write or delete sequences have been completed At power fail the PORST signal must be activated at latest when any 3 3 V or 1 3 V power supply voltage falls 1096 below the nominal level If under these conditions the PORST is activated during a Flash write only the memory row that was the target of the write at the moment of the power loss will contain unreliable content In order to ensure clean power down behavior the PORST signal should be activated as close as possible to the normal operating voltage range n case of a power loss at any power supply all power supplies must be powered down conforming at the same time to the rules number 2 and 4 Although not necessary it is additionally recommended that all power supplies are powered up down together in a controlled way as tight to each other as possible
104. t is limited This means that the relative deviation for periods of more than one clock cycle is lower than for a single clock cycle This is especially important for bus cycles using wait states and for the operation of timers serial interfaces etc For all slower operations and longer periods e g pulse train generation or measurement lower baudrates etc the deviation caused by the PLL jitter is negligible Two formulas are defined for the absolute approximate maximum value of jitter D in ns dependent on the K2 factor the LMB clock frequency Lus in MHz and the number m of consecutive f yg clock periods for K2 lt 100 and m lt fi 4g MHz 2 740 1 0 01 x K2 x n 1 6 D 2 1 x K2 Dm ns xf us IMBz 65x fiusIMHz 1 0 01 x 7 else D m ns p up XJLMB Z Data Sheet 5 60 V1 2 2014 06 Infineon nes Electrical Parameters With rising number rn of clock cycles the maximum jitter increases linearly up to a value of m that is defined by the K2 factor of the PLL Beyond this value of m the maximum accumulated jitter remains at a constant value Further a lower LMB Bus clock frequency f mg results in a higher absolute maximum jitter value Note The specified PLL jitter values are valid if the capacitive load per pin does not exceed C 20 pF with the maximum driver and sharp edge Oscillator Watchdog OSC WDT The expected input frequency is selected via the bit field SCU_OSCCON OSCV
105. tana CC 150 ns C 20 pF pin out driver weak 50 ns C 50 pF pin out driver medium 140 ns C 150 pF pin out driver medium 550 ns CS 150 pF pin out driver weak 18000 ns CS 20000 pF pin out driver medium 65000 ns C 20000 pF pin out driver weak Data Sheet 5 12 V1 2 2014 06 Cinfineon TC1724 Electrical Parameters Table 17 Standard Pads Class A1 cont d Parameter Symbol Values Unit Note Min Typ Max Test Condition Input high voltage Vrai SR 06x min Vp V class A1 pads Vbpe pp T 0 3 3 6 Input low voltage class V 4 SR 0 3 0 36x V A1 pads Vopp Output voltage high Vorai CC Vopp i V Top 1 4 mA pin out class A1 pads 0 4 driver medium 24 i V Top 2 mA pin out driver medium Vopr V Top 400 pA pin 0 4 out driver weak 24 V Toy 500 uA pin out driver weak Output voltage low VALA CC 0 4 V Ig 2 mA pin out class A1 pads driver medium 0 4 V Ig 500 uA pin out driver weak 1 Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce It can t be guaranteed that it suppresses switching due to external system noise Table 18 Standard Pads Class A1 Parameter Symbo Values Unit Note I Min Typ Max Test Condition Input Hysteresis for HYSA1 0 1 x Vbpp V A1 pads CC Input Leakage loza
106. tput 38 CCU61 O2 COUT62 Reserved O3 68 P2 7 lOO A2 Port 2 General Purpose I O Line 7 RDATAOA PU MLI Receiver Data Input A IN39 l GPTAO Input 39 OUT39 O1 GPTAO Output 39 CCU61 O2 COUT60 Reserved O3 132 P2 8 lOO A2 Port 2 General Purpose I O Line 8 SLSO04 o1 PU ssco Slave Select Output 4 SLSO14 O2 SSC1 Slave Select Output 4 ENOO O3 MSCO Enable Output 0 Data Sheet V1 2 2014 06 Infineon Ies Pinning Table 3 1 Pin Definitions and Functions PG LQFP 144 17 package cont d Pin Symbol Ctrl Type Function 128 P2 9 lOO A2 Port 2 General Purpose I O Line 9 SLSO05 o1 PU ssco Slave Select Output 5 SLSO15 O2 SSC1 Slave Select Output 5 ENO1 O3 MSCO Enable Output 1 129 P2 10 1 00 A1 Port 2 General Purpose I O Line 10 MRST1A PU SC1 Master Receive Input A MRST1A O1 SSC1 Slave Transmit Output Reserved O2 Reserved O3 130 P2 11 1 00 A1 Port 2 General Purpose I O Line 11 SCLK1A PU ssSci Clock Input A SCLK1A O1 SSC1 Clock Output A Reserved O2 FCLPOB O3 MSCO Clock Output Positive B 131 P2 12 1 00 A1 Port 2 General Purpose I O Line 12 MTSR1A PU ssct Slave Receive Input A MTSR1A O1 SSC1 Master Transmit Output A Reserved O2 SOPOB O3 MSCO Serial Data Output Positive B 133 P2 13 1 00 A1 Port 2 Gener
107. urrent for non DFlash operations 2 Relevant for the power supply dimensioning not for thermal considerations In case of erase of Program Flash PF internal flash array loading effects may generate transient current spikes of up to 15 mA for maximum 5 ms per flash module 5 2 5 1 Calculating the 1 3 V Current Consumption The current consumption of the 1 3 V rail compose out of two parts Static current consumption Dynamic current consumption The static current consumption is related to the device temperature T and the dynamic current consumption depends of the configured clocking frequencies and the software application executed These two parts needs to be added in order to get the rail current consumption 1 A I 0 en vell 02592 x T tj 2 E mA 0 02085x T Ip 3 9 xe TC Data Sheet 5 45 V1 2 2014 06 Infineon oiia Electrical Parameters Function 1 defines the typical static current consumption and Function 2 defines the maximum static current consumption Both functions are valid for Vpp 1 326 V For the dynamic current consumption using the application pattern and T un fpcp 2 fep the function 4 applies 3 mA IDym 0 76 Era x fepy MHz For the dynamic current consumption using the application pattern and fims focp frpi the function 5 applies 4 mA Ipsm 9 SI x fepu MHz and this finally results in 5 Ipp Io IbYyM Data Sheet 5 46 V1 2 2014 06
108. y the condition VAREFO lt VDDM 0 5 V This is required in order to prevent discharge of VAREFO filter capacitance through the ESD diodes through the VDDM power supply In case of discharging the reference capacitance through the ESD diodes the current must be lower than 5 mA Data Sheet 5 49 V1 2 2014 06 Infineon Mes Electrical Parameters 5 3 3 Power Sequencing 3 3V Supply Only 3 63V Y 3 3V t 2 97V 1 43V l 1 3V S S y 1 17V Vv gt t PORST output PORST input A B C D E f Power Up_EVR_2 vsd Figure 14 2 3 V 1 3 V Power Up Down Sequence The events for the above points in the power up down sequence A external supplied voltage reaches operating level B external supplied and internal generated voltages reaches operating levels C internal generated voltage drops below operating level D internal generated voltage resumes operating level E external supplied voltage leaves operating level P0 4 and P0 5 should be kept at the selected setting of 0 or 1 until external supplied voltage has reached its operating level The following list of rules applies to the power up down sequence All ground pins Vas must be externally connected to one single star point in the system Regarding the DC current component all ground pins are internally directly connected The latch up risk is minimized if the I O currents are limited to

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