Home

Vivado Design Suite Tutorial: Programming and Debugging

Contents

1. Set the description and other properties to create and optionally run a scan on the selected link Link Link 1 Description Scan 0 Scan Properties Scan type 2D Full Eyescan Horizontal increment 8 Horizontal range 0 500 UI to 0 500 UI Vertical increment 8 Vertical range 100 Dwell BER 1e 5 C Time IV Run scan a Figure 129 The Create Scan dialog box Programming and Debugging www xilinx com 97 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 5 Using Vivado Serial Analyzer to Debug Serial Links The Scan Plot window opens as shown below Bsepwre 8 Voltage Codes A fa f i 100 Summary Hame SCAN_O Scan 0 2013 5ep 30 10 50 12 2013 Sep 30 10 50 22 Description Started Ended 0 25 Metrics Open area 2880 Settings Link settings N A Unit Interval 0 135 0 0 125 BER 0 235 0 375 05 Horizontal increment amp Horizontal range 0 300 UT te 0 500 UI Vertical increment a Vertical range 100 Figure 130 2D Scan Plot The 2D Scan Plot is a heat map of the BER value 13 You can also perform a Sweep test on the links that you created earlier In the Links window highlight Link 0 under the Link called Link Group SMA right click and select Create Sweep Name amp Link Group EIT on A Link 1 gt Link 2 Link 3 s Link 4 Link 5 Link 6
2. Open Implemented Design _ View Reports Open Hardware Manager Launch iMPACT Don t show this dialog again Figure 154 Open Hardware Manager Step 2 Program the KC705 Board and Interact with the JTAG to AXI Master Core 1 Connect your KC705 board s USB JTAG interface to a machine that has Vivado IDE and cable drivers installed on it and power up the board 2 The Hardware Manager window opens Click Open a new hardware target The Open New Hardware Target dialog box opens proj_netlist C Vivado_Debug proj_netlist proj_netlistxpr Vivado 2013 3 File Edit Flow Tools Window Layout View Help feiwaevbh x d P BU XK E g SSerialyoanayzerr E amp Flow Navigator K Hardware Manager unconnected Cg ag m No hardware target is open Open recent target Open a new ha uate arge Fr rdv a 4 Project Manager eta i SE Project Settings A oo E l b gt E aT Add Sources Name i Figure 155 Connect to a Hardware Target Programming and Debugging www xilinx com 121 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 6 Using Vivado ILA core to Debug JTAG AXI Transactions 3 In the Connect to field choose Local server and click Next g Open New Hardware Target 2 Hardware Server Settings Select local or remote hardware server then configure the host name and port settings Use Local server if the target is attached to the local machin
3. Next program the XC7K325T device using the bit bitstream file that was created previously by 8 right clicking the XC7K325T device and selecting Program Device as shown in the following figure There are no debug cores Program device Refresh device S F bi m Status Name E localhost 1 Connected E lio xilinx_tcf Digilent 210203327962A 1 O lt xc7k325t_0 1 active JNot programmed _ _ z z 7 Hardware Device Properties E XADC System Monitor Refresh Device Wi Add Configuration Memory Device s Hardware Device Properties Export to Spreadsheet Figure 162 Program Active Target Hardware Programming and Debugging www xilinx com 125 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 6 Using Vivado ILA core to Debug JTAG AXI Transactions In the Program Device dialog box verify that the bit file is correct for the lab that you are working on Click the OK to program the device Select a bitstream programming file and download it to your hardware device You can optionally select a debug probes file that corresponds to the debug cores contained in the bitstream programming file Bitstream file axi_0 jtag_axi_0_example jtag_axi_0_example runs impl_i example_jtag_axi_0 bit Debug Probes file ial jtaq_axi_0 jtag_axi_0_example jtag_axi_0_example runs impl_1 debug_nets tx m Figure 163 Select B
4. amp link 7 E Tcl Console Programming and Debugging UG936 v 2014 2 June 4 2014 if X Delete Bits J 2 601612 Delete ow 2 604612 i 2 604E12 4 i 2 605E12 2 605E12 2 605E12 2 606E12 7 RNTC Link Properties Ctrl E amp Create Scan amp Create Sweep Commit Properties Figure 131 Create a Sweep Test www xilinx com 98 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 5 Using Vivado Serial Analyzer to Debug Serial Links 14 The Create Sweep dialog box opens as shown below Various properties for the Sweep test can be changed in this dialog box Leave all the values to its default state and click OK g Create Sweep Oo Select the sweep properties and values to create and optionally run a set of scans on the selected link Link Link 0 Description Sweep 1 Scan Properties Scan type 2D Full Eyescan Horizontal increment 8 Horizontal range 0 500 UI to 0 500 UI Vertical increment 98 Vertical range 100 Dwell BER 1e 5 Time Sweep Properties For each property select values to be swept The sweep will cover all combinations of property values Sweep mode Semi Custom Set Properties amp Values Preview 81 Scans Property Name Values to Sweep of Values RXTERM 100 mV 550 mV 1100 mV TXDIFFSWING 250 mV 0000 600 mV 0111 1000 mV 1111 TXPOST 0 00 dB 00000 4 08 dB 01111 12 96 dB 11111 TXPRE 0 00 dB 00000 4 08 dB 01111 6 02 dB
5. 0 000 ns Total Pulse Width Negative Slack TPWS 0 000 ns E eck Timing 11 i B Intra Clock a i Number of Failing Endpoints 0 Number of Failing Endpoints 0 Number of Failing Endpoints 0 EHS Inter Clock Paths Total Number of Endpoints 3679 Total Number of Endpoints 3679 Total Number of Endpoints 2012 EHS Other Path Groups User Ignored Paths All user specified timing constraints are met 4 Unconstrained Paths Timing Summary timing_1 x 6 Proceed to Using Vivado Logic Analyzer to Debug Hardware Skip forward to Verifying the VIO Core Activity Only applicable to Lab 3 to complete the rest of this lab Programming and Debugging www xilinx com 37 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 4 Using Synplify Pro Synthesis Tool and Vivado for Debugging a Design Lab 4 Using Synplify Pro Synthesis Tool and Vivado for Debugging a Design Introduction This simple tutorial shows how to do the following Create a Synplify Pro project for the wave generator design Mark nets for debug in the Synplify Pro constraints file as well as VHDL source files Synthesize the Synplify Pro project to create an EDIF netlist Create a Vivado project based on the Synplify Pro netlist Use the Vivado IDE to setup and debug the design from the synthesized design using Synplify Pro Version 2013 3 SP1 Step 1 Create a Synplify Pro Project 1 Launch Sy
6. Vivado Design Suite Tutorial Programming and Debugging UG936 v 2014 2 June 4 2014 XILINX ALL PROGRAMMABLE Revision History The following table shows the revision history for this document e pem m 04 07 2014 2014 1 Updates to the tutorials to reflect the 2014 1 Vivado software changes 06 04 2014 2014 2 Updates to the tutorials to reflect the 2014 2 Vivado software changes Programming and Debugging www xilinx com 2 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Table of Contents PROV SIO FT S COV a E E E E A E E E E 2 PS Si IN VIN COs TUOT ooe E A 6 OCTO E E cueatenoce nan cauendauecenansanehoteosenaseetcasecnteuesnecudenes sauemaeseaneeantecedaunteueneoseen 6 USS eit occa se tecc E nce tt arts eats ahs nse cto radars arate acre E E 6 EUNE I apc cctecrc ce sn nace rs et oa cs ees eee es tee sensed ese emcees S 7 BUS O Fi AUS erase ate tetrcrrotce ected A E ane ote AE nd dotet ae E EE N taeeeeee 7 DOM ANS r E E E EE seas vans not auiiecevssnucs E ERA 7 OWE o E E S anaseesnouesenatansun ceeceise 7 Tutorial Design COMIDON ON US esce 8 Board Support and Pinout Information ssesssessssesesrrrserreresrrrrssreresrrressreresererssreressrerssreresereesseeresereessrereserersseeeo 8 SS a EE OAA E E E E A ANE A A ATE O A E E AE AEAT 9 Connecting the Boards and Capless sristi enres AE E E EO 11 Lab 1 Using the Netlist Insertion Method for Debugging a DeSISN ccccces
7. gt Not started Messages No errors or warnings Part MCT k325tffg900 2 Design Runs Part Constraints xc7k325thfg900 2 xc7k325tffig900 2 Strategy Vivado Synthesis Defaults Vivado Synthesis 2013 Nat started Vivado Implementation Defaults Vivado Implementation 2013 Not startec constrs_1 constrs_1 E Td Console Messages Log Reports t Design Runs Programming and Debugging UG936 v 2014 2 June 4 2014 www xilinx com Send Feedback 106 amp XILINX ALL PROGRAMMABLE Lab 6 Using Vivado ILA core to Debug JTAG AXI Transactions 11 In the Search field on the right of the IP Catalog tab type in JTAG to AXI Note The JTAG to AXI Master core shows up under the Debug amp Verification gt Debug category jtag_2_axi_tutorial C jtag_2_axi_tutorial jtag_ _axi_tutorial jtag_2_axi_tutorial xpr Vivado 2013 4 File Edit Flow Tools Window Layout View Help feiwawh km x lt gt bP BH XE S 2 Default Layout E Flow Navigator Project Manager jtag_2_axi_tutorial A ta ge Sources ges ls a E Project Summary x 4F IP Catalog x 2ST TE A A LA e 0 Search Q JTAG to AXI 1 match Project Settings d oe ma Name ai AXI4 GF Add Sources amp Simulation Sources i Debug amp Verification LF IP Catalog sim_i i Debug iF JTAG to AXI Master Included xilinet com tH Pe te amp IP Integrator G Cre
8. ALL PROGRAMMABLE Lab 3 Using a VIO Core for Debugging a Design in Vivado 17 Double click sinegen_demo_inst vhd in the Sources window to open it and inspect the instantiation and port mapping of the ILA core in the HDL code Also note that attributes have been placed in the source file to preserve the net names fl Attributes for preserving the net names and to show debug nets 7 Te attribute mark_debug string 73 attribute mark_debug of GPIO_LBUTTONS_db signal is true ff attribute mark_debug of GPIO_LBUTTONS_d y signal is true 75 attribute mark_debug of GPIO_LBUTTONS_re signal is true f6 attribute mark_debug of sinesel signal is true ff attribute mark_debug of sine signal is true Te attribute mark_debug of push_button_vio signal is true 7O attribute mark_debug of push_button_reset signal is true 0 attribute mark_debug of DONT_LEAT signal is true Figure 33 Using mark_debug attribute to preserve net names and show debug nets in the synthesized netlist U_ILA E E ila port map CLK gt clk PROBEO gt gineSel PROBE1 gt sine PROBE2 Figure 34 Hook signals that need to be debugged in the ILA gt push_button_reset push_button_vio PROBES gt GPIO BUTIONS_re PROBE4 gt GPIO_BUITIONS dly Step 2 Synthesize Implement and Generate Bitstream 1 From the Program and Debug drop down list in Flow Navigator click Generate Bitstre
9. Right click the selected nets and select Mark Debug as shown in the following figure Ni a tse SNe en Ht a ee r J a ye AFAI F r ro eo nt Z Jt M 1 BS om f i E E it File Edit Flow Tools Window Layout View Help amp eEE ev she x gA e NHA g OS XE g Boebug Synthesized Design xc7k325tffg900 2 active Flow Navigator A ek S a Project Manager Project Settings G Add Sources F IP Catalog IP Integrator 4 Create Block Design ge Open Block Design amp Generate Block Design Simulation 5 Simulation Settings Run Simulation RTL Analysis gt E Open Elaborated Design 4 Synthesis 3 Synthesis Settings gt Run Synthesis gt B Synthesized Design 4 Implementation Implementation Settings r E k z MATNA oe n ALO e e e ge pe e pee eee a ee Oe a oe Jado Debua pro netlist pro netlist xpr J rado 20 SS kr PL Se He Shire ies ial iad x o Eo ah a eas oe d i area r eiar te J DONT_EATOO J DONT_EATOO_out J DONT_EAT10 T DONT_EAT20 J DONT_EAT30 J DONT_EAT40 mmm GPIO BUTTONS _IBUFIO T GPIO_BUTTONS_IBU 3 J GPIO_SWITCH Re Net Properties GPIO_SWITCH_IBUF W M J I n_O_DONT_EAT_reg J n_0_GPIO_BUTTONS J n_0_GPIO_BUTTONS A i L amp Sources Net Properties e gt Raia T GPIO_BUTTONS_IBUF O Type Route status Select Driver Pin Schematic Show Connectivity Show Hierarchy Highlight Mark Figu
10. machine and you are running a cse_server application on that machine If you plan to connect locally skip steps 1 3 below 1 Connect the Digilent USB JTAG cable of your KC705 board to a USB port on a Windows system 2 Ensure that the board is plugged in and powered on 3 Assuming you are connecting your KC705 board to a 64 bit Windows machine and you will be running the hw_server from the network instead of your local drive open a cmd prompt and type the following lt Xxilinxz Install Vivado 2014 41 binvaw server Programming and Debugging www xilinx com 53 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Using Vivado Logic Analyzer to Debug Hardware Leave this cmd prompt open while the hw_server is running Note the machine name that you are using you will use this later when opening a connection to this instance of the hw_server application Connecting to the target board locally If you plan to connect locally ensure that you have your KC705 hardware plugged into a Windows machine and then perform the following steps 1 Connect the Digilent USB JTAG cable of your KC705 board to a USB port on a Windows system 2 Ensure that the board is plugged in and powered on 3 Turn DIP switch positions pin 1 on SW13 De bounce Enable to the OFF position Using the Vivado Integrated Logic Analyzer 1 In the Flow Navigator from the Program and Debug drop down list select Open Hardware M
11. ta push_button_reset ta push_button_vio Figure 88 Debug probes window showing probes for ILA as well as VIO Programming and Debugging www xilinx com 71 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Using Vivado Logic Analyzer to Debug Hardware Also note that separate tabs are available for the ILA as the VIO cores as shown below Hardware Manager localhost xilinx_tcf Xilinx Port_ 0002 Hub_ 0004 f TEE Hardware 020x fe hw ia 1 x E hw_ila_data_1 wcfg x A tks a Di gt E a Trigger Cz Name Status Trigger Mode Settings Core stat H localhost 1 Connected Me xilinx tef Xilinx Port_ 0002 Hub Open Trigger mode E XC7K325T_0 2 active hw_vio_1 OK Outputs Reset Trigger in hw_ila_1 Idle BASIC capture Basic Trig Trigger out Capture Mode Settings D Capture mode ALWAYS Data depth 1024 Trigger position 0 0 1023 Properties gt Re by Figure 89 Tabs for ILA and VIO 17 In the VIO Probes window from the hw_vio_1 select all the probes then drag and drop these probes in the VIO core tab Note the initial values of all the probes VIO Probes A Name Value Activity Direction Miki ta push_button_reset_1 B 0 Output hw_vio_1 ro His sineSel_1 1 0 H 0 Input hw_vio_1 8 GPIO_BUTTONS_re_i 1 1 B 0 Input hw_vio_1 x ta push_button_vio_1 B 0 Output hw_vio_1 gii Figure 90
12. 1 Creating a Project with the Vivado New Project Wizard To create a project use the New Project wizard to name the project to add RTL source files and constraints and to specify the target device 1 Invoke the Vivado IDE 2 In the Getting Started screen click Create New Project to start the New Project wizard Click Next 3 Inthe Project Name screen name the new project proj_netlist and provide the project location C Vivado_Debug Ensure that Create Project Subdirectory is selected and click Next 4 In the Project Type screen specify the Type of Project to create as RTL Project Click Next 5 In the Add Sources screen a Set Target Language to VHDL b Click the Add Files button c In the Add Source Files dialog box navigate to the src Lab 1 directory d Select all VHD source files and click OK e Verify that the files are added and Copy Sources into Project is selected Click Next Programming and Debugging www xilinx com 12 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 1 Using the Netlist Insertion Method for Debugging a Design 7 In the Add Existing IP optional dialog box a b C d Click the Add Files button In the Add Configurable IP dialog box navigate to the src lab1 directory Select all XCI source files and click OK Verify that the files are added and Copy Sources into Project is selected Click Next 8 In the Add Constraints optiona
13. 3 In the Project Name page name the new project ibert_tutorial and provide the project location C ibert_tutorial Ensure that Create Project Subdirectory is selected Click Next In the Project Type page specify the Type of Project to create as RTL Project Click Next In the Add Sources page click Next In the Add Existing IP page click Next In the Add Constraints page click Next at Os pi S In the Default Part page select Boards and then select Kintex 7 KC705 Evaluation Platform Click Next 9 Review the New Project Summary page Verify that the data appears as expected per the steps above Click Finish Note It might take a moment for the project to initialize Step 2 Adding an IBERT core to the Vivado Project 1 In the Flow Navigator click IP Catalog The IP Catalog opens g ibert_tutorial C ibert_tutorial ibert_tutorial xpr Vivadc File Edit Flow Tools Window Layout View Help aA bx S eX G Boefa Flow Navigator lt lt om nao p g Card Sources nag og i 4 Project Manager F Design Sources 3 Project Settings a i nie Add Sources Simulation Sources IF P Catal sim_1 Figure 97 Opening the Vivado IP Catalog 2 In the search field of the IP Catalog type IBERT to display the IBERT 7 Series GTX IP Programming and Debugging www xilinx com 78 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 5 Using Vivado Serial Analyzer to Debug Ser
14. Asrc LabA fsm vhd src Lab4 sinegen_demo vhd src Lab4 synplify_l sdc _ src Lab4 synplify_1 cde Remove Aiz Remove gt Figure 42 Adding CDC Constraints File to the Synplify Pro Project Programming and Debugging www xilinx com 42 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 4 Using Synplify Pro Synthesis Tool and Vivado for Debugging a Design 8 Now you need to set the implementation options Click Implementation Options in the Synplify Pro window as shown in the following figure ee a F 7 EA J r fu _ uge us oor p KUE ae Ee ee are Serer T ST A ne Ae PR Bee ae eta E Pro 1 2U13 09 1 C Vive do_Debug VT ie nsvs sy pilry_1 e BE File Edit View Project Import Run Analysis HDL Analys Bteoe Ge ie i QA ee Oo Ds OH PRRR SS 2 4 ws BO Bes a l Rea dy B Open Project Project Files Design Hierarchy synplify_1 rev_1 Xilinx Kintex7 XC7K synplify_1 C Vivado_Debu 3 Lab4 a f VHDL e Logic Constraints SDC Compiler Directive rev_l Figure 43 Opening Implementation Options in Synplify Pro 9 This brings up the Implementation Options dialog box as shown in the following figure In the Device tab set Technology to Xilinx Kintex7 Part to XC7K325T Package to FFG900 and Speed to 2 Leave all the other options at their default values Click OK E Implementation Options sy
15. Drag and drop VIO probes from the Debug Probes window into VIO core tab Programming and Debugging www xilinx com 72 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Using Vivado Logic Analyzer to Debug Hardware 18 Set the push_button_reset output probe by right clicking push_botton_reset and select Toggle Button This will toggle the output driver from logic from 0 to 1 to 0 as you click It is similar to the actual push button behavior though there is no bouncing mechanical effect as with a real push button switch VIO Probes Value Activity Direction VIO button_re a Debug Probe Properties j Ctri E y GPIO_BUTTONS_re push_button_vio_1 Text Active High Button Active Low Button X Remove Export to Spreadsheet Figure 91 Toggle the push_button_reset signal The Value field for push_button_reset is highlighted Click in the Value field to change its value to 1 VIO Probes A Name Value Activity Direction VIO ted re Pt Co ee a ee T His sineSel_1i 1 0 Input hw_vio_1 x gii ig GPIO_BUTTONS_re_1 1 1 8 0 Input hw_vio_1 ta push_button_vio_1 Output hw_vio_1 Figure 92 Toggle the value of push_button_reset 19 Follow the step above to change the push_button_vio to Toggle button as well Programming and Debugging www xilinx com 73 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Using Vivado
16. E E E E E E E 76 pesien Desar DOP E E A 76 Step 1 Creating Customizing and Generating an IBERT De SIQN cccccecccsseccesccceececeeceeeetenseteuseeeeeeeeeeteneens 77 Step 2 Adding an IBERT core to the Vivado Project cccccceeccceseccccnececenseeceseeseeeceseueceeeeeceeeueeseueceseueceeeueeenensss 78 Step 3 Synthesize Implement and Generate Bitstream for the IBERT GeSIQN cccceeesceesecceececeeceeeueeeeenees 84 Step 4 Interact with the IBERT core using Serial I O Analyzer ccccccccccccccccecceseeeseeeeceeeececsssseeeeeseeaeeeeeeeseeeeess 86 Lab 6 Using Vivado ILA core to Debug JTAG AXI TranSactiOns cccccccsssecccceseccecesecceeusececeeeeceeeeneceesauecetsuneess 102 MOGUC CO permereenetenn erecta E eee eR ee en ene er eee 102 What is the JTAG to AXI Master IP COrG cccccssssssscccccccsseeesseecccceeseaeesseeecccesssueausseeceeeessuausseeeeeeessaaaagseseeeees 102 Key FSU CS nate aineactsaectnaciccain Goyotee a nesinnsorsac O EO EE 102 Additional Document atO Mesic EEEE EE 102 pasem DCS CDU ON era A E E E E aes E E E eine eaianienl 103 Step 1 Opening the JTAG to AXI Master IP Example Design and Configuring the AXI Interface Debug CONNECCION S oea E E E E E cateerenanenene 103 Step 2 Program the KC705 Board and Interact with the JTAG to AXI Master Core ccccccesssseeesecenesseeeseeees 121 Step 3 Using ILA 3 0 Advanced Trigger Feature to Trigger on an AXI Read TransSactiOn ccccc
17. HDL Instantiation method is one of the two methods supported in Vivado Debug Probing For this flow you will generate an ILA 3 0 IP using the Vivado IP Catalog and instantiate the core in a design manually as you would with any other IP Step 1 Creating a Project with the Vivado New Project Wizard To create a project use the New Project wizard to name the project to add RTL source files and constraints and to specify the target device 1 Invoke the Vivado IDE 2 In the Getting Started page click Create New Project to start the New Project wizard Click Next 3 In the Project Name page name the new project proj_hdl and provide the project location C Vivado_Debug Ensure that Create Project Subdirectory is selected Click Next 4 In the Project Type page specify the Type of Project to create as RTL Project Click Next 5 In the Add Sources page a Set Target Language to VHDL b Click Add Files c In the Add Source Files dialog box navigate to the src Lab2 directory d Select all VHD source files and click OK e Verify that the files are added and Copy Sources into Project is selected Click Next 6 6 In the Add Existing IP optional page a Click Add Files b In the Add Configurable IP page navigate to the src directory Programming and Debugging www xilinx com 26 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 2 Using the HDL Instantiation Method for Debuggin
18. In the Open IP Example Design dialog box ensure that the Overwrite existing example project is selected and click OK g Open IP Example Design Exi Specify a location where the example project directory ibert_7series_gtx_0_example will be placed Location Put example project directory here _tutorial_example ibert_7series_gqtx_0_example V Overwrite existing example project Conce Figure 105 Open IP Example Design dialog Step 3 Synthesize Implement and Generate Bitstream for the IBERT design 1 Click Generate Bitstream in the Flow Navigator When the No Implementation Results Available dialog box appears Click Yes No Implementation Results Available gt There are no implementation results available OK to launch synthesis and implementation S Generate Bitstream will automatically start when synthesis and implementation completes Don t show this dialog again Figure 104 No Implementation Results Available dialog box Programming and Debugging www xilinx com 84 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 5 Using Vivado Serial Analyzer to Debug Serial Links 2 When the bitstream generation is complete the Bitstream Generation Completed dialog box appears Select Open Hardware Manager Click OK Bitstream Generation Completed i Bitstream Generation successfully completed Next Open Implemented Design View Reports Ope
19. Link Group SMA 1 Link 1 MGT_X0Y8 TX c Link Group Intern Link 2 MGT_XOY9 TX MGT_XO0Y9 RX Link 3 MGT_XOY10 TX MGT_XOY10 Link 4 MGT_XO0Y11 TX MGT_XOY11 Link 5 MGT_X0Y12 TX MGT_XOY12 Link 6 MGT_XOY13 TX MGT_XOY13 Link 7 MGT_X0Y14 TX MGT_XOY14 Be tink OO eT VAVIRI Mer VAVI BTd Console Messages Links E Scans Figure 127 Link Status after changing GT Properties to Near end PCS Change the GT properties of the rest of the transceivers as described above Programming and Debugging www xilinx com 96 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 5 Using Vivado Serial Analyzer to Debug Serial Links 12 Next create a 2D scan Click Create Scan in the Links window Status Link Group Intern Link 2 MGT_X0Y9 TX MGT_X0Y9 RX 8 000 Gbps Link 3 MGT_XO0Y10 TX MGT_XOY10 8 000 Gbps Link 4 MGT_XOY11 TX MGT_XOY11 8 000 Gbps Link 5 MGT_X0Y12 TX MGT_XOY12 8 000 Gbps MGT_X0Y13 TX MGT_XOY13 8 000 Gbps MGT_X0Y14 TX MGT_XOY14 8 000 Gbps CT Whit erry MrT WAWI o nnn Chae s Scans Figure 128 Creating a 2D Scan for Link 1 The Create Scan dialog box opens In this dialog box you can change the various scan properties In this case leave everything to its default value and click OK For more information on the scan properties see Vivado User Guide Programming and Debugging UG908 gt Create Scan
20. Not programmed F XADC System Monitor Figure 115 Hardware Window showing the XC7K325T device on the KC705 board Programming and Debugging www xilinx com 89 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 5 Using Vivado Serial Analyzer to Debug Serial Links 6 Select XC7K325T_0 0 in the Hardware window right click and select Program Device a There are no debug cores Program device Refresh device m Status L 1 Connected _ Wo xilinx_tcf Digilent 210203327962A 1 ____ Open B lt xc7k325t 0 1 active Hardware Device Properties Hardware Device Properties pe a a e Export to Spreadsheet Figure 116 Program target device 7 The Program Device dialog box opens Make sure that the correct bitfile is selected and click OK i Select a bitstream programming file and download it to your hardware device You can optionally select a debug probes file that corresponds to the debug cores contained in the bitstream programming file Bitstream file xample ibert_7series_gtx_0_example runs impl_1 example_ibert_7series_gtx_0 bit zs Debug Probes file t7series_gtx_0_example ibert_7series _gtx_0_example runs impl_1 debug_nets tx ca Figure 117 Program Device dialog box 8 The Hardware window now shows the IBERT IP that you customized and implemented from the previous steps It contains two QUADS ea
21. Open Block Design connecting them to debug cores amp Generate Block Design The wizard is automatically populated with any selected nets and with nets 4 Simulation from the Unassigned Debug Nets folder G Simulation Settings QQ Run Simulation a pa 4 RTL Analysis ia Open Elaborated Desig 4 Synthesis amp Synthesis Settings gt Run Synthesis a H Synthesized Design fA Edit Timing Constrai Report Timing Sumr Ms Report Clock Networ E Report Clock Interac Report DRC His Report totes Ey Site ax areddr oa E Report Utilization e Ta axi_araddr 0 T axi_araddr 1 Report Power ore Ta axi_araddr 2 rl Schematic Ta axi_araddr 3 J amp axi_araddr 4 4 Implementation Lo el endef 1 Implementation Setting Debug Cores Debug Nets Imp g gt Run Implementation Tc Console Messages Log Reports c Design Runs To continue click Next Figure 148 Set up Debug Wizard 23 Once the Set up Debug wizard pops up click Next Programming and Debugging www xilinx com 115 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 6 Using Vivado ILA core to Debug JTAG AXI Transactions 24 In the next page of the Setup Debug wizard note that some of the nets that you would like to debug have no detectable clock domains selected Click the more info link in the message banner jtag_axi_O example c jtag_2_axi_tutorial jtag_2 _axi_tu
22. Open Synthesized Design View Reports Don t show this dialog again caveat Figure 4 Synthesis Completed dialog box Step 3 Probing and Adding Debug IP To add a Vivado ILA 2 0 core to the design take advantage of the integrated flows between the Vivado IDE and Vivado logic analyzer In this step you will accomplish the following tasks e Add debug nets to the project e Run the Set Up Debug wizard e Implement and open the design e Generate the bitstream Adding Debug Nets to the Project Following are some examples of how to add debug nets using the Vivado IDE e Add mark_debug attribute to the target XDC file set property mark debug true get_nets sine Ar IMPORTANT Use these attributes in synthesized designs only Do not use then with pre synthesis or elaborated design netlists Programming and Debugging www xilinx com 15 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 1 Using the Netlist Insertion Method for Debugging a Design e Add mark_debug attribute to HDL files VHDL attribute mark_debug string attribute keep string attribute mark_debug of sine Sagnal ig Crue attribute mark debug of sineSel signal is true Verilog mark_debug true wire sine mark_debug true wire sineSel e Right click and select Mark Debug or Unmark Debug on Synthesis netlist e Usea Tcl prompt to set the mark_debug attribute For example set
23. Properties Ctri E 2 0 Capture mode A i Name Compare Value Run Trigger 3 0 Number of windows 1 r Run Trigger Immediate Y l p 2 0 Window data depth 1024 i Stop Trigger A Enable Auto Re triager dr 31 0 Trigger position in window 0 ILA Core Properties 39 rst 1 0 r All che 3 0 General Settings hw tat Open Hardware Dashboard MaL E foe ee i i a mist i Export to Spreadsheet j Refresh rate ms 500 Name hw_ila_1 is axi_awprot 2 0 Device xc7k325t_0 3 e mi awqat aa te axi_awready HW core core_3 ig axi_awsize 0 Capture sample count 0 of 1024 te axi_avvalid te axi_bid Core status Idle pa te axi_bready Wa EE F ta axi_bresp 1 0 General Properties t gt axi_bvalid k mii adnin 5i Figure 166 Opening the ILA Dashboard 2 In the ILA hw_ila_1 dashboard locate the Trigger Mode Settings area and set Trigger mode to ADVANCED_ONLY Programming and Debugging www xilinx com 128 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE 3 4 ILA Properties Trigger Mode Settings Trigger mode ADVANCED Trigger state machine Trigger in Dl bp Lad Ea Irigger out Capture Mode Settings Capture mode ALWAYS Data depth 1024 Trigger position 512 0 1023 Lab 6 Using Vivado ILA core to Debug JTAG AXI Transactions In the Capture Mode Settings area set the Trigger position to 512 In th
24. TAN ORO GTREFCLKO_I 1 0 TXP_O 7 0 GTREFCLK1 1 1 0 RXOUTCLK_O iSYSCLK_ Figure 100 Setting the Protocol Selection on the IBERT Core 6 Click the Clock Settings tab and make the following changes for both QUAD_117 and QUAD_118 a Leave the Source column at its default value of External b Change the I O Standard column to DIFF SSTL15 c Change the P Package Pin to AD12 d Change the N Package Pin to AD11 e Leave the Frequency MHz at its default value of 200 00 Programming and Debugging www xilinx com 81 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 5 Using Vivado Serial Analyzer to Debug Serial Links F Customize IP IBERT 7 Series GTX 3 0 Documentation 5 IP Location CQ Switch to Defaults Show disabled ports Component Name ibert_7series_gtx_0 Protocol Definition Protocol Selection Clock Settings Summary RXOUTCLE Probe Add RXOUTCLK Probes Clock Type Source yt Standard P Package Pin N Package Pin Frequency MHz system Clock External DIFFSSTLis JADID yADIN SSS idz OOO TXN_O 7 0 System Clock Termination Settings ISTREFCLKO_I 1 0 TXP_O 0 Enable DIFF Term GTREFCLK 1 I 1 0 RXOUTCLK_O iS V SCLE _I Figure 101 Specifying clock settings for the IBERT Core 7 Click the Summary tab and ensure that the content matches the following figure Click OK F Customize IP IBERT 7 Series GTX 3 0 Documentation I
25. Template W RTL Sources Behavioral Simulation sk Figure 30 Generate Output Products for the VIO core Programming and Debugging www xilinx com 34 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 3 Using a VIO Core for Debugging a Design in Vivado Output product generation should take less than a minute At this point you have finished customizing the VIO 3 0 This core has already been instantiated in the top level design as shown in the following figure U_VIO vio_0 Port map CLK gt clk PROBE _INO gt DONI_EAT GPIO BUTTONS re 1 sineSel PROBE_OUIO 0 gt push_button_reset PROBE OUTO 1 gt push_button_vio Figure 31 VIO Instantiation in the top level design At this point the Sources window should look as shown in the following figure Os S ao ae B Design Sources 1 BOA sinegen_demo_inst_vio hdl_inst_vio sinegen_demo_inst_vio vhd 6 i U_DEBOUNCE_0 debounce Mixed debounce vhd gP U_DEBOUNCE_1 debounce Mixed debounce vhd HHE U_SINEGEN sinegen kintex sinegen vhd 3 i i U_LFSM fsm Mixed fsm vhd aut A j ia D Yri G Cons 1 E Simulation Sources 1 Hierarchy IP Sources Libraries Compile Order Figure 32 Instantiated VIO Core in the Sources window Programming and Debugging www xilinx com 35 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX
26. Vivado User Guide Programming and Debugging UG908 11 You can fix the No Link status for all the links by changing the GT properties of these channels to one of the loopback modes To do this select the appropriate transceiver in the Hardware window and modify the GT property in the GT Properties window Name localhost 1 Be xilinx_tcf Digilent 210203327962A 1 XC7K325T_O 1 active BERT Quad_117 5 amp COMMON_X0Y2 B MGT_XOY8 MGT OVO MGT_X0Y10 PB MGT_XOY11 Quad_118 5 m COMMON_X0Y3 MGT_X0Y12 Py MGT_X0Y13 B MGT_X0Y14 P MGT_X0Y15 Status Connected Open Programmed Locked 8 000 mee No Link No Link Locked No Link No Link No Link No Link Figure 125 Select the transceiver whose property needs to be modified Programming and Debugging UG936 v 2014 2 June 4 2014 www xilinx com 95 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 5 Using Vivado Serial Analyzer to Debug Serial Links In the GT Properties window under the Properties tab select LOOPBACK pull down menu and select Near End PCS CPLLREFCLKSEL CPLL_FBDIV CPLL_FBDIV_45 CPLL_REFCLK_DIV ES _HORZ_MIN_MAX LINE_RATE LOOPBACK MORSE Far End PMA RXOUT_DIV Far End PCS RXPLL RXRATE Figure 126 Selecting appropriate Loopback mode for transceivers This changes the Status in the Link window for the transceiver in question as shown TX gt
27. a dialog box asking to close the synthesized design before opening the implemented design click Yes 5 Proceed to Using Vivado Logic Analyzer to Debug Hardware to complete the rest of this lab Programming and Debugging www xilinx com 52 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Using Vivado Logic Analyzer to Debug Hardware Using Vivado Logic Analyzer to Debug Hardware Introduction The final step in debugging is to connect to the hardware and debug your design using the Integrated Logic Analyzer Before continuing make sure you have the KC705 hardware plugged into a machine In this step you learn e How to debug the design using the Vivado logic analyzer e How to use the currently supported Tcl commands to communicate with your target board KC705 e How to discover and correct a circuit problem by identifying unintended behaviors of the push button switch e Some useful techniques for triggering and capturing design data Step 1 Verifying Operation of the Sine Wave Generator After doing some setup work you will use Vivado logic analyzer to verify that the sine wave generator is working correctly Your two primary objectives are to verify that e All sine wave selections are correct e The selection logic works correctly Setting Up Connecting to the target board remotely If you plan to connect remotely you will need to make sure you have KC705 hardware plugged into a
28. and Capture Modes page 29 Click Finish Note See that the ILA core was inserted and attached to the dbg_hub core Programming and Debugging www xilinx com 118 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 6 Using Vivado ILA core to Debug JTAG AXI Transactions jtag_axi_0_example c jtag_2_axi_tutorial jtag_2_axi_tutorial jtag_axi_0 jtag_axi_ Fle Edit Flow Tools Window Layout View Help 28 9o RBexad gt b BH AGOG KES Boe Flow Navigator Synthesized Design xc7k325tffg900 2 active GQ om ie Netlist _oOw a o 1 Project Manaqa Sni Project Set ie nets 324 et Add Source HG Leaf Cells 11 LF IP Catalog H px md bram _etri_inst wd_bram_ etri _o cl k 4 iPintegrator L fao axi full inst itn ai O VEN BB Create Bi A Sources D Netlist J g sl_oport0_i 0 16 sl_iporti_o 0 36 B Open Block Cell Properties i Ly Generate B ale mis sl_oporti_i 0 16 4 Simulation ba dbg_hub Simulation ame dbg_hub UR Run Simuk Reference name dbg_hub_Cv RTL Analysis General Properties Debug Core Options gt E Open Elabe uoo Debug i a Synthesis amp Synthesis gt Run Synthe a synthesize a Constra E ak iA Edit Tin _ Nem Debug Cores Debug Nets Se Set up E Td Console Messages Gi Log 4 Reports gt Design Runs Debug Bus Pin s_iporti_o Type Output Figure 152 ILA core inserted into the d
29. and change flatten_hierarchy option to none as shown in shown in the following figure Click OK A Project Settings axe aj Constraints General Q Default constraint set ia constrs_1 active Simulation Options m Strategy A Vivado Synthesis Defaults Vivado Synthesis 2013 Description Vivado Synthesis Defaults gt Synth Design vivado Implementation tcl pre tcl post boas flatten_hierarchy __ Bitstream gated_clock_conversion bufg fanout_limit directive Default fsm_extraction auto keep_equivalent_registers flatten_hierarchy Flatten hierarchy during LUT mapping Figure 3 The Project Settings dialog box Az IMPORTANT The reason for changing this setting to none is to prevent the synthesis tool from performing any boundary optimizations for this tutorial 4 In the Vivado Flow Navigator expand the Synthesis drop down list and click Run Synthesis Note When synthesis runs a progress indicator appears showing that synthesis is occurring This could take a few minutes Programming and Debugging www xilinx com 14 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 1 Using the Netlist Insertion Method for Debugging a Design 6 In the Synthesis Completed dialog box click Cancel as shown in the following figure You will implement the design later Synthesis Completed dal i Synthesis successfully completed Run Implementation
30. box Programming and Debugging www xilinx com UG936 v 2014 2 June 4 2014 Finish 22 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 1 Using the Netlist Insertion Method for Debugging a Design 9 In the Specify Nets to Debug page ensure that all the nets have been added for debug and click Next Set up Debug Specify Nets to Debug Specify Nets for debugging Clock Domain Driver Cell TRIG DA clk FDRE teh GPIO_BUTTONS_dly 2 clk FDRE ye ct re GPIO_BUTTONS_re 2 clk FDRE 4 J U_SINEGEN sel 2 clk FDRE P H P U_SINEGEN sine 20 clk FDRE p GPIO_BUTTONS_IBUF 0 clk IBUF T GPIO_BUTTONS_IBUF 1 clk IBUF Add Remove Nets Nets to debug 30 lt Back Next gt Finish Cancel o Next gt Figure 14 Specify Nets to Debug 10 In the ILA General Options page go to the Trigger and Storage Settings section Select both the Capture Control and Advanced Trigger settings Click Next Programming and Debugging www xilinx com 23 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 1 Using the Netlist Insertion Method for Debugging a Design 11 In the Setup Debug Summary page make sure that all the information is correct and as expected Click Finish Set up Debug Set up Debug Summary 0 debug cores will be removed G 1 debug core will be created Found 1 clock VIVADO To apply the above changes click Finish
31. index 0 is programmed with a design that has 1 ILA core s in it reset hw axi get_hw axis hw axi 1 Wi Messages Figure 165 Reset JTAG to AXI core 12 The next step is to create a 4 word AXI burst transaction to write to the first four locations of the BRAM set wt create_hw_axi_txn write_txn get_hw_axis hw_axi_1l type WRITE address 00000000 len 128 data 44444444 33333333 22222222 111111117 where o write txn is the name of the transaction o get_hw_axis hw_axi_1 returns the hw_axi_1 object o address 00000000 is the start address o len 4 sets the AXI burst length to 128 words o data 44444444 33333333_22222222 11111111 is the data to be written Note The data direction is MSB to the left te address 3 and LSB to the right te address 0 Also note that the data will be repeated from the LSB to the MSB to fill up the entire burst 13 The next step is to set up a 128 word AXI burst transaction to read the contents of the first four locations of the AXI BRAM core set rt create_hw_axi_txn read_txn get_hw_axis hw_axi_l type READ address 00000000 len 128 where o read_txn is the name of the transaction o get_hw_axis hw_axi_1 returns the hw_axi_1 object o address 00000000 is the start address o len 128 sets the AXI burst length to 4 words Programming and Debugging www xilinx com 127 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 6 Using
32. is true attribute keep of GPIO BUITONS dly signal is true attribute keep of GPIO BUTTONS re signal is true attribute keep of sineSel signal is true attribute keep of sine signal is true Figure 20 Using keep attribute to preserve net names Programming and Debugging www xilinx com 27 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 2 Using the HDL Instantiation Method for Debugging a Design in Vivado U_ILA ilao port map CLK gt clk PROBEO gt sineSel PROBE gt sine PROBE2 gt GPIO BUTTONS db PROBES gt GPIO_BUIIONS re PROBE4 gt GPIO BUTTONS dly PROBES gt GPIO BUITONS Figure 21 Hook signals that need to be debugged in the ILA Step 2 Synthesize Implement and Generate Bitstream 1 From the Program and Debug drop down list in Flow Navigator click Generate Bitstream This will synthesize implement and generate a bitstream for the design 4 Program and Debug aide ETE AAPA 3 Bitstream Settings mI Generate pisuar General Properties a gt Open Hardware N W Launch iMPACT xc7k325tffg900 xc7k325tffq900 Figure 22 Generate Bitstream 2 The No Implementation Results Available dialog box appears Click Yes 3 After bitstream generation completes the Bitstream Generation Completed dialog box appears Open Implemented Design is selected by default Click OK Programming and Debugging www x
33. itx Figure 65 Select Bitstream file to download for Lab 1 CAUTION The file paths of the bitstream to be programmed will be different for different labs Ensure that the relative paths are correct Note Wait for the program device operation to complete This may take few minutes 11 Ensure that an ILA core was detected in the Hardware panel of the Debug view Status Connected i E localhost 1 We xilinx_tcf Digilent 210203327962A 1 Open EEEE hw_ila_1 ILA Idle fCuctam Manitar at XADC SYSTEM Monor Figure 66 ILA Core Detection www xilinx com Programming and Debugging UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Using Vivado Logic Analyzer to Debug Hardware 12 The Integrated Logic Analyzer window opens aka amp Dl DP E rh E Trigger Capture Status Trigger Mode Settings _ Core status Waiting for Tri gj AM Trigger mode BASIC_ONLY Basic Trigger Setup Capture Mode Settings KTA Name Compare Value Capture mode ALWAYS X Number of windows 1 D Window data depth 1024 Drag and drop NSE ILA probes from Trigger position in window 0 ger p Debug Probes window General Settings Refresh rate ms 500 Figure 67 The Vivado Integrated Logic Analyzer window Verifying Sine Wave Activity 13 Click Run Trigger Immediate to trigger and capture data immediately as shown in shown in the following figu
34. my 0000 TXPOST 4 08 d 01111 TXP RXTERM 100 mV TXDIFFSWING 250 mv 0000 TXPOST 4 08 dB 01111 TXP RXTERM 100 mV TXDIFFSWING 250 mv 0000 TXPOST 12 96 dB 11111 TX RXTERM 100 mV TXDIFFSWING 250 mv 0000 TXPOST 12 96 dB 11111 TX RXTERM 100 mV TXDIFFSWING 250 mv 0000 TXPOST 12 96 dB 11111 TX RXTERM 100 mV TXDIFFSWING 600 mV 0111 TXPOST 0 00 dB 00000 TXP RXTERM 100 mV TXDIFFSWING 600 mW 0111 TXPOST 0 00 dB 00000 TXP RXTERM 100 mV TXDIFFSWING 600 mv 0111 TXPOST 0 00 dB 00000 TXP RXTERM 100 mV TXDIFFSWING 600 mV 0111 TXPOST 4 08 dB 01111 TX RXTERM 100 mV TXDIFFSWING 600 mV 0111 TXPOST 4 08 dB 01111 TXP RXTERM 100 mV TXDIFFSWING 600 mW 0111 TXPOST 4 08 dB 01111 TXP RXTERM 100 mV TXDIFFSWING 600 mW 0111 TXPOST 12 96 dB 11111 TX RXTERM 100 mV TXDIFFSWING 600 mW 0111 TXPOST 12 96 dB 11111 TX BXTERM S100 mv TXNIEESWING TAAN mv ANE TeENST 19 OF dR LT Wi Scan Type 2d_full_eye 2d_full_eye 2d_full_eye 2d_full_eye 2d_full_eye 2d_full_eye 2d_full_eye 2d_full_eye 2d_full_eye 2d_full_eye 2d_full_eye 2d_full_eye 2d_full_eye 2d_full_eye 2d_full_eye 2d_full_eye 2d fll eve Status Done Done Donme Dome Dome Done Done Dope Dome Done Done Done Dome Done Done In Pranresc Progress 2d_full_eye In ress Done M 100 2624 100 0 100 0 E 100 0 m
35. of integrated Vivado logic analyzer features in the Vivado design environment that make the debug process faster and simpler e Provide specifics on how to use the Vivado IDE and the Vivado logic analyzer to debug common problems in FPGA logic designs e Provide specifics on how to use the Vivado Serial I O Analyzer to debug high speed serial links After completing this tutorial you will be able to e Validate and debug your design using the Vivado Integrated Design Environment IDE and the Integrated Logic Analyzer ILA core e Understand how to create an RTL project probe your design insert an ILA 3 0 core and implement the design in the Vivado IDE e Generate and customize an IP core netlist in the Vivado IDE e Debug the design using Vivado logic analyzer in real time and iterate the design using the Vivado IDE and a KC705 Evaluation Kit Base Board that incorporates a Kintex 7 device e Analyze high speed serial links using the Serial I O Analyzer Programming and Debugging www xilinx com Sancibecdback 6 UG936 v 2014 2 June 4 2014 amp XILINX ALL PROGRAMMABLE Debugging in Vivado Tutorial Getting Started Setup Requirements Before you start this tutorial make sure you have and understand the hardware and software components needed to perform the labs included in this tutorial as listed below Software e Vivado Design Suite 2014 1 Hardware e Kintex 7 FPGA KC705 Evaluation Kit Base Board e Digilent
36. the list of available targets then set the appropriate JTAG clock TCK frequency If you do not see the expected devices decrease the frequency or select a different target Hardware Targets Type Port Name JTAG Clock Frequency xilinx tcf Digilent 210203327962A 15000000 Hardware Devices for unknown devices specify the Instruction Register IR length Name ID Code IR Length xc7k325t_0 33651093 6 VCSE server localhost 60001 Hardware server localhost 3121 Figure 112 Select Hardware Target page Programming and Debugging www xilinx com 88 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 5 Using Vivado Serial Analyzer to Debug Serial Links 4 In the Open Hardware Target Summary page review the options that you selected Click Finish g Open New Hardware Target Open Hardware Target Summary Hardware Server Settings Server localhost 3121 VCSE Server Settings o Server localhost 60001 o Version 20 Target Settings o Target xilinx_tcf Digilent 210203327962A o Frequency 15000000 VIVADO To connect to the hardware described above click Finish Figure 114 Open Hardware Target Summary dialog box 5 The Hardware window in Vivado IDE should show the status of the target FPGA device on the KC705 board Name Status B localhost 1 Connected Mo xilinx_tef Digilent 210203327962A 1 Open E xc7k325t_O 1 active
37. 0 MGT_XOY15 RX lt it im 0 ounce it fo V Create link group Link group description Link Group Internal Loopback V Open Serial I O Analyzer layout Figure 123 Create Link dialog box to create the second link group Programming and Debugging www xilinx com UG936 v 2014 2 June 4 2014 Send Feedback 94 amp XILINX ALL PROGRAMMABLE Lab 5 Using Vivado Serial Analyzer to Debug Serial Links 10 Once the links have been created they are added to the Links window as shown 3 i He e Link 1 DE BS 4 j Link 2 Link 3 S Link 4 Link 5 Link 6 Link 7 gt Link 8 TX t Link Group SMA 1 MGT_X0Y8 TX MGT_X0Y8 RX 8 000 Gbps Link Group Intern RX Status MGT_X0Y9 TX MGT_X0Y9 RX No Link MGT_XOY10 MGT_XOY11 MGT_XOY12 MGT_XO0Y13 MGT_XOY14 MGT_XO0Y15 MGT_XOY10 MGT_XOY11 MGT_XOY12 MGT_XO0Y13 MGT_XO0Y14 MGT_X0Y15 No Link No Link No Link No Link No Link No Link Bits Erro 2 491 2 491 1 43 2 491 1 495 2 49E13 1 494 2 49E13 1 494 2 491 1 4 2 491 1 43 2 491 1 49 Figure 124 Links window after all the link groups have been created As expected only Link1 indicates a link with 8 0 Gbps line rate and the rest of the GTX channels show No Link status For more information about the different columns of the Links windows refer to
38. 0 axi_arcache mark_debug wire 0 0 axi_arid mark _debug wire 7 0 axi_arlen mark_debug wire axi_arlock mark_debug wire 2 0 axi_arprot mark_debug wire 3 0 axi_argos mark_debug wire axi_arready mark_debug wire 2 0 axli_arsize mark_debug wire axi_arvalid mark_debug wire 31 0 axi_awaddr mark_debug wire 1 0 axi_awburst mark_debug wire 3 0 axi_awcache mark_debug wire 0 0 axi_awid mark_debug wire 7 0 axi_awlen mark_debug wire 7 0 axi_awlen mark _debug wire axi_awlock mark_debug wire 2 0 axi_awprot mark_debug wire 3 0 axi_awgos mark_debug wire axi_awready mark_debug wire 2 0 axli_awsize mark_debug wire axi_awvalid mark_debug wire 0 0 axi_bid mark_debug wire axi_bready mark_debug wire 1 0 axi_bresp Programming and Debugging www xilinx com 111 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE mark_debug mark_debug mark_debug mark_debug mark_debug mark_debug mark_debug mark_debug mark_debug mark_debug mark_debug mark_debug FF FF FF F FF FF FF FF F xo Ne _ Ne NOA NA NA NA NA NA NA NA wire wire wire wire wire wire wire wire wire wire wire wire 19 Save changes to example Lab 6 Using Vivado ILA core to Debug JTAG AXI Transactions axi_bvalid 31 0 axi _rd
39. 100 oO b 100 0 lt 100 0 100 0 SS 100 0 100 0 lt 100 0 _ 2 100 _ 0 100 0 TIA Figure 133 Sweep Test results in the Scans window Open Area Ja Horz Incr Horz Rang 0 500 UI 0 500 UT 1 0 500 UI 1 0 500 UTI 0 500 UL 0 500 UI 0 500 UI 1 0 500 UI 1 0 500 UN 0 500 UI 0 500 UI I 0 500 UI 1 ia id gajdi id ididd d m a g g g g d w o eo ooo ga aft S iT a 0 500 UL 0 500 UI 0 500 UTI 0 500 UI _ P 0 500 UL KETM To see the results of any of the scans that have been performed highlight the scan right click and select Display Scan Plots Programming and Debugging Link Scan Properties scan E Sweep 1 Scan E Sweep 1 Scan Link Settings Run Sweep or Scan E Sweep 1 Scan i E Sweep 1 Scan amp Display E Sweep 1 Scan E Sweep 1 Scan Lo Canan d Ceon X Delete Write Scan Data Apply Link Settings Figure 134 Displaying Scan Plots UG936 v 2014 2 June 4 2014 www xilinx com Send Feedback 100 amp XILINX ALL PROGRAMMABLE Lab 5 Using Vivado Serial Analyzer to Debug Serial Links The Scan Plots window opens showing the details of the scan performed a m Coan Pote ween i Si scan Fits Sweep 1 S can U Unit Interval SE AAYT Voltage Codes Summary Metrics Settings Name SCAN_O Open area 8128 Link settings R
40. 11111 W Run sweep Figure 132 Create Sweep dialog box Since there are four different Sweep Properties and each of these properties has three different values as seen in the Values to Sweep column a total number of 81 sweep tests are carried out The Scans window shows the results of all the scans that have been done for the selected link CAUTION Since there are 81 scans to be done it could be a few minutes before all the scans are complete Programming and Debugging www xilinx com 99 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Link Lab 5 Using Vivado Serial Analyzer to Debug Serial Links Link Settings Link Link 0 Link 0 Link Link Link 0 Link 0 Link 0 Sweep 1 Sean 1 E Sweep 1 Scan 2 E Sweep 1 Scan3 E Sweep 1 Scan 4 Sweep 1 Scan5 E Sweep 1 Scan 6 E Sweep 1 Scan E Sweep 1 Scng Link Sweepil Scan9 Link E Sweep 1 Scan 10 Link oO Sweep 1 Sean 11 Link oO E Sweep 1 Scan 12 Link 0 E Sweep 1 Scan 13 Link E Sweep 1 Scan 14 Link E Sweep 1 Sean 15 Link oO Sweep 1 Scan 16 Link 0 R Sweean t Sean i7 ink fi RXTERM 100 nv TXDIFF on mvt ot ty ET ro ja tog 1 RXTERM 100 mV TXDIFFS 250 mV 0000 TXPOST 0 00 dB 00000 TXF RXTERM 100 mV TXDIFFSWING 250 mv 0000 TXPOST 0 00 dB 00000 TXP RXTERM 100 mV TXDIFFSWING 250 mV 0000 TXPOST 4 08 dB 01111 TXP RXTERM 100 mV TXDIFFSWING 250
41. B Close Project sid Close Project E T rev_1 Xilinx Kintex7 XC7K70T FBG676 1 synplify_1 C Vivado_Debug synopsys synplify_1 prj Tias ba rev amp Change File Figure 39 Adding Files to a Synplify Pro Project 4 In the Add Files to Project dialog box change the Files of Type to HDL File Navigate to C Vivado_Debug src Lab4 which shows all the VHDL source files needed for this lab Select the following three files by pressing the Ctrl key and clicking on them e debounce vhd e fsm vhd e sinegen_demo vhd Click Add Programming and Debugging www xilinx com 39 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 4 Using Synplify Pro Synthesis Tool and Vivado for Debugging a Design Add Files to Project Look in C Vivado_Debug src Lab4 iGOO0 yy My Computer ndutta Filename debounce vhd fsm vhd sinegen_demo vhd Files of type VHDL Verilog lib Files to add to project 3 file s selected Use relative paths Y Add files to Folders Folder Options src Lab4 debounce vhd erc Laba fsmnvhd src Lab4 sinegen_demo vhd Remove All gt Remove gt OK Cancel Figure 40 Adding VHDL Source Files to the Synplify Pro Project Programming and Debugging www xilinx com 40 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 4 Using Synplify Pro Synthesis Tool an
42. Cable e Two SMA Sub miniature version A cables ki Sine Wave eee Ti indicator TEHTE Dp a a i a a 8 2 TESE ES E Tg BETETE et oe er Fr peseeeee ee i i TETTETETT r User j switct a i _ y 3 located under LCD Sne Wave sequencer Figure 1 KC705 Board Showing Key Components Programming and Debugging www xilinx com 7 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Debugging in Vivado Tutorial Tutorial Design Components Labs 1 through 4 include e A simple control state machine e Three sine wave generators using AX Streaming interface native DDS Compiler e Common push buttons GPIO_BUTTON e DIP switches GPIO_SWITCH e LED displays GPIO_LED VIO Core Lab 3 only Push Button Switches Serve as inputs to the de bounce and control state machine circuits Pushing a button generates a high to low transition pulse Each generated output pulse is used as an input into the state machine DIP Switch Enables or disables a de bounce circuit De bounce Circuit In this example when enabled provides a clean pulse or transition from high to low Eliminates a series of spikes or glitches when a button is pressed and released Sine Wave Sequencer State Machine Captures and decodes input from the two push buttons Provides sine wave selection and indicator circuits sequencing among 00 01 10 and 11 zero to three LED Displays GPIO_LED_O and GPIO_LED_1 displa
43. Fart xc7k325t te S WPS z a te axM_awready ID code 33651093 d le mi awsize 2 0 IR length 6 le axd_avevalid Sear aes TE te axi_bid is programmabile le axi_bready a iil I General Properties i axi_bresp 1 0 le axi_bvalid ee eee eh el OOO i Figure 164 ILA core instances in the Hardware window 126 Programming and Debugging UG936 v 2014 2 June 4 2014 www xilinx com Send Feedback amp XILINX ALL PROGRAMMABLE Lab 6 Using Vivado ILA core to Debug JTAG AXI Transactions 11 You can communicate with the JTAG to AXI Master core with Tcl commands only You can issue AXI read and write transactions using the run_hw_axi command However before issuing these transactions it is important to reset the JTAG to AXI Master core Because the aresetn input port of the jtag_axi_0 core instance is not connected to anything you need to use the following Tcl commands to reset the core reset_hw_axi get_hw_axis hw_axi_1 INFO Labtools 27 2154 Reading 11443712 bytes from file C jtag_2_ a8xi_tutorial jtag_2_axi_ tutorials jtag_axi_ 0 example jtag_axi_0 examp INFO Labtools 27 32 Done pin status HIGH program hwoidevices Time s cpu 00 00 05 elapsed 00 00 11 Memory HB peak 2014 715 gain 40 832 refresh _hw_device lindex get_hw_devices 0 INFO Labtools 27 2024 Device xc7k325t JIAG device index 0 has 1 JTAG_AXT cores INFO Labtools 27 1432 Device xcTk325t JTAG device
44. Figure 15 Set up Debug Summary Step 4 Implementing and Generating Bitstream 1 Click Generate Bitstream from the Program and Debug drop down list in the Flow Navigator 4 Program and Debug Bitstream Settings Y Generate Bitstrean a Open Hardwa Generate Bitstream Launch iMPAq Generate a programming file after implementation 1 iJ Figure 16 Implement design and Generate Bitstream 2 Inthe Save Project dialog box click Save This applies the mark_debug attributes on the newly marked nets You can see those constraints can by inspecting the sinegen_demo_kc705 xdc file 3 When the No Implementation Results Available dialog box pops up Click Yes 4 When the bitstream generation completes the Bitstream Generation Completed dialog box pops up Click OK Programming and Debugging www xilinx com 24 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 1 Using the Netlist Insertion Method for Debugging a Design 5 In the dialog box asking to close synthesized design before opening implemented design Click Yes 6 In the Implementation is Out of date dialog box click Yes 7 In the Flow Navigator under Implementation expand the Implemented Design drop down list and select Report Timing Summary 4 Impicementation Implementation Settings gt Run Implementation Eppes 5 Sa 4 24 Implemented Design Me fA Edit Timing Constraints Report Timing Sumn Sources P
45. Files c In the Add Source Files dialog box navigate to the src Lab3 directory d Select all VHD source files and click OK e Verify that the files are added and Copy Sources into Project is selected Click Next 6 In the Add Existing IP optional page a Click the Add Files b In the Add Configurable IP dialog box navigate to the src Lab3 directory c Select all XCI source files and click OK d Verify that the files are added and Copy sources into project is selected Click Next 7 Inthe Add Constraints optional dialog box the provided XDC file sinegen_demo_kc705 xdc should automatically appear in the main window Click Next 8 In the Default Part page specify the xc7k325tffg900 2 part for the KC705 platform You can also select Boards and then select Kintex 7 KC705 Evaluation Platform Click Next Programming and Debugging www xilinx com 31 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 3 Using a VIO Core for Debugging a Design in Vivado 9 Review the New Project Summary page Verify that the data appears as expected per the steps above Click Finish Note It might take a moment for the project to initialize 10 In the Sources window in Vivado IDE expand sinegen_demo_inst_vio to see the source files for this lab Note that ila_0 core has been added to the project However vio_0 the VIO core is missing P ie TA cao e GE A 6 Design Sources 1 ice sinegen
46. Logic Analyzer to Debug Hardware 20 Set these two bits of the sineSel input probe by right clicking PROBE_INO 0 and PROBE_INO 1 and selecting LED VIO Probes A Name Activity Direction VIO e pta push_button_reset_1 Eo tp hw_vio_1 Ee sineSel_i 1 0 sineSel_1 1 Debug Probe Properties Ctri E sineSel_1 0 a t GPIO_BUTTONS_re_1 1 1 Te xt ta push_button_vio_1 i LED Activity Persistence Remove Delete Export to Spreadsheet Figure 93 Change sineSel to LED 21 In the Select LED Colors dialog box pick the Low Value Color and the High Value Color of the LEDs as you desire and click OK Select LED Colors amp Low Value Color Gray High Value Color Red Figure 94 Pick the Low Value and High Value color of the LEDs Programming and Debugging www xilinx com 74 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Using Vivado Logic Analyzer to Debug Hardware 22 When finished your VIO Probes window in the Hardware Manager should look similar to the following figure VIO Probes A Name Value Activity Direction E es ig GPIO_BUTTONS_re_1 1 1 8B 0 Input hw_vio_1 pS Eis sineSel_1 1 0 H 1 Input hw_vio_1 J sineSel_1 1 gt Input hw_vio_1 fj e push_button_reset_1 Output hw_vio_1 x J sineSel_1 0 Input hw_vio_1 ta push_button_vio_1 Output hw_vio_1 Figure 95 Input and Output VIO Signals Displayed 23 To cycle through eac
47. NT OR FITNESS FOR ANY PARTICULAR PURPOSE and 2 Xilinx shall not be liable whether in contract or tort including negligence or under any other theory of liability for any loss or damage of any kind or nature related to arising under or in connection with the Materials including your use of the Materials including for any direct indirect special incidental or consequential loss or damage including loss of data profits goodwill or any type of loss or damage suffered as a result of any action brought by a third party even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications You may not reproduce modify distribute or publicly display the Materials without prior written consent Certain products are subject to the terms and conditions of Xilinx s limited warranty please refer to Xilinx s Terms of Sale which can be viewed at http www xilinx com legal htm tos IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx Xilinx products are not designed or intended to be fail safe or for use in any application requiring fail safe performance you assume sole risk and liability for use of Xilinx products in such critical applications please refer to Xilinx s Terms of Sale which can be viewed a
48. Netlist amp Device C Figure 17 Analyze Timing Results 8 Inthe Report Timing Summary dialog box Click OK 9 Ensure that all the specified timing constraints are met Ats e Re Design Timing Summary General Information Timer Settings Setup Hold Pulse Width ing S y Worst Negative Slack WNS 0 159 ns Worst Hold Slack WHS 0 057 ng Worst Pulse Width Slack WPWS5 1 732 ns i n edr A li Total Negative Slack TNS 0 000 ns Total Hold Slack THS 0 000 ns Total Pulse Width Negative Slack TPWS 0 000 ns H eck Timing 103 3 7 HA Intra Clock sah Number of Failing Endpoints 0 Number of Failing Endpoints 0 Number of Failing Endpoints 0 HS Inter Clock Paths Total Number of Endpoints 11057 Total Number of Endpoints 11057 Total Number of Endpoints 6300 Other Path Groups H User Ignored Paths All user specified timing constraints are met HG Unconstrained Paths Timing Summary timing_1 x Figure 18 View the Timing Summary Report 10 Proceed to Using Vivado Logic Analyzer to Debug Hardware to complete the rest of the steps for debugging the design Programming and Debugging www xilinx com 25 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 2 Using the HDL Instantiation Method for Debugging a Design in Vivado Lab 2 Using the HDL Instantiation Method for Debugging a Design in Vivado Introduction The
49. OY11 RX xc7k325t_0 Quad_117 lt a MGT_XOY12 RX xc7k325t_0 Quad_118 A MGT_XOY13 RX xc7k325t_0 Quad_118 i MGT_XOY14 RX xc7k325t_0 Quad_118 lt MGT_XOY15 RX xc7k325t_0 Quad_118 Lab 5 Using Vivado Serial Analyzer to Debug Serial Links Add Link Delete Links Figure 120 Selecting the transceiver pairs for creating new links Click Add Link In the Link group description field type Link Group SMA Click OK www xilinx com 92 Send Feedback Programming and Debugging UG936 v 2014 2 June 4 2014 amp XILINX ALL PROGRAMMABLE Lab 5 Using Vivado Serial Analyzer to Debug Serial Links 7 To create a new link select a TX GT and or an RX GT then click the Add Link button TX GTS Search Q MGT_XO0Y9 TX xc7k325t_0 Quad_117 E gt MGT_XOY10 TX xc7k325t_0 Quad_117 gt MGT_XOY11 TX xc7k325t_0 Quad_117 E MGT_XOY12 TX xc7k325t_0 Quad_118 E gt MGT_XOY13 TX xc7k325t_0 Quad_118 E gt MGT_XOY14 TX xc7k325t_0 Quad_118 RX GTS Search Q T rrr foe a d Ae hg i Ce yy im 4 MGT X0Y9 RX xc7kK325t 0 Quad 117 A MGT_XOYLO RX xc7k325t_0 Quad_117 i MGT_XOY11 RX xc7k325t_0 Quad_117 A MGT_XOY12 RX xc7k325t_0 Quad_118 A MGT_XOY13 RX xc7k325t_0 Quad_118 A MGT_XOY14 RX xc7k325t_0 Quad_118 gt MGT_XOY15 TX xc7k325t_0 Quad_118 IA MGT_XOY15 RX xc7k325t_0 Quad_118 New Links Description TX RX Link 0 MGT_XOY8 TX xc7k325t_0 Quad_117 MGT_X0Y8 RX xc7k325t_0 Quad_117 De
50. OY8 Ba MGT_XOY9 R4 MGT_X0Y10 Ba MGT_XOY11 j Quad_118 5 m COMMON_X0Y3 Locked 8 000 Gbps No Link No Link No Link Locked No Link No Link No Link No Link g BERT Core Properties i Auto detect Links Open Hardware Dashboard Serial I O Links Serial I O Scans Commit Properties Refresh Serial 1 0 Objects Select E Export to Spreadsheet Figure 119 Create Links The Create Links dialog box opens Make sure the first transceiver pairs MGT_XOY8 TX and MGT_XOY8 RX are selected Programming and Debugging UG936 v 2014 2 June 4 2014 www xilinx com 91 Send Feedback amp XILINX ALL PROGRAMMABLE 7 To create a new link select a TX GT and or an RX GT then click the Add Link button TX GTS Search Q gt 4 Sr i e ka i F i a X xC K325t_U Quad_11 E gt MGT_XOY9 TX xc7k325t_0 Quad_117 E MGT_XOY10 TX xc7k325t_0 Quad_117 E MGT_X0Y11 TX xc7k325t_0 Quad_117 E gt MGT_XOY12 TX xc7k325t_0 Quad_118 MGT_X0Y13 TX xc7k325t_0 Quad_118 E gt MGT_XOY14 TX xc7k325t_0 Quad_118 E MGT_XO0Y15 TX xc7k325t_0 Quad_118 New Links Description TX V Create link group Link group description Link Group 0 Open Serial I O Analyzer layout RX GTs Search Q wT Whivo DwWw Ive dhean f F 147 MGT XO0Y8 RX xc kK325t 0 Quad 117 lt a MGT_XOY9 RX xc7k325t_0 Quad_117 A MGT_XOY10 RX xc7k325t_0 Quad_117 A MGT_X
51. P Location C3 Switch to Defaults FI Show disabled ports Component Name ibert_7series_gt_0 Protocol Definition Protocol Selection Clock Settings Summary IBERT Design Summary Number of Protocols o o QUAD Count See RefClk Sources n A TXN_O 7 0 GTREFCLKO_I 1 0 TXP_O 7 0 GTREFCLK 1_I 1 0 RXCUTCLK_Of ISYSCLK_I Figure 102 IBERT Core Summary Page Programming and Debugging www xilinx com 82 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 5 Using Vivado Serial Analyzer to Debug Serial Links 8 When the Generate Output Products dialog box opens click Generate The following output products will be generated Preview QA ibert_7series_gtx_0 xci wa O Instantiation Template RTL Sources Change Log Generate Figure 103 Generate Output Products 9 In the Project Manager window right click the IP and select Open IP Example Design _ Project Manager xc7k325tffg900 2 Source File Properties Ctri E Re customize IP Generate Output Products Reset Output Products Out of Context Settings Report IP Status Remove IP from Project Delete Set Used In Add Existing IP Figure 104 Open Example IP Design Menu Item Programming and Debugging www xilinx com 83 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 5 Using Vivado Serial Analyzer to Debug Serial Links 10
52. Project Manager SELE BE H Search Q JTAG to AXI 1 match Project Settings oe SEIRET s f om 5 G Add Sources 2 Constraints l Source Node Properties LF IP Catalog BE Simulation Soy an A 4 TP Integrator Generate Output Products F Create Block Desigr j Open Block Design b Generate Block Des 4 Simulation Simulation Settings G Run Simulation 4 RTL Analysis t B gt Open Elaborated Di 4 Synthesis Synthesis Settings gt Run Synthesis gt E Open Synthesized 0 Implementation B Implementation Sel gt Run Implementatioi gt E Open Implemented Program and Debug Bitstream Settings Generate Bitstream g Open Hardware Ma E Launch iMPACT Open Example Reset Output Products Out of Context Settings Source File Propertig E 0 BN i jtag_ad_O xci Vendor xili TFF library ip IP state Gene AG to AXI Master al Rev 1 La 14 Altel aG X Remove File from Project Delete ba 4 J Aa to AXI Master generates AXI transactions The AXI transactions General Properties Alt Equals ated by Disable File Alt Minus Design Runs 02 Bi Hierarchy Update aie Refresh Hierarchy IP Hierarchy tegy Status do Synthesis Defaults Vivado Synthesis 2013 Not started p Implementation Defaults Vivado Implementat Not started do Synthesis Defaults Vi
53. Sources dialog box ensure that Copy Sources into Project is selected Click Next 7 Under Add Constraints a sac file should be automatically populated Remove this file by selecting it and clicking Remove Selected File on the right of the dialog box Click Add Files navigate to the Vivado_debug src folder and select the sinegen_demo_kc705 xdc file This file has the appropriate constraints needed for this Vivado project Click OK in the Add Constraints File Programming and Debugging www xilinx com 47 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 4 Using Synplify Pro Synthesis Tool and Vivado for Debugging a Design dialog box In the Add Constraints optional dialog box ensure that Copy Constraints into Project is selected Click Next 8 Under Default Part select Boards and then select Kintex 7 KC705 Evaluation Platform and the right version number for your hardware Click Next 9 Under New Project Summary ensure that all the settings are correct and click Finish 10 In the Sources window select sinegen_demo edf and select Specify Top Module Managera proj syopiiy a ZAL ot e Design Sources 5 EDF 5 F dds_compiler_v6_0_viv__parameterized1 edn top F dds_compiler_v6_0_viv edn ie sinegen edn a seasinegen_d P dds_come Source File Properties Hi Constraints 1 Eh constrs_1 1 Me sinegen_ Replace File H Simulation Only S Open File Alt Remove F
54. Vivado ILA core to Debug JTAG AXI Transactions 14 After creating the transaction you can run it as a write transaction using the run_hw_axi command run_hw_axi Swt This command should return the following INFO Labtools 27 147 vese_server WRITE DATA is AAAAAAAA SS SOS SOOO 22Z2Z2 AAA ALLII 15 After creating the transaction you can run it as a read transaction using the run_hw_axi command run_hw_axi Srt This command should return the following INFO Labtools 27 147 vcse_server READ DATA is AAAAAAAA SOO OOO OZ 222 22274 ELI Step 3 Using ILA 3 0 Advanced Trigger Feature to Trigger on an AXI Read Transaction 1 Open the ILA core s dashboard by right clicking hw_ila_1 in the Hardware Manager window and selecting Open Dashboard Hardware Manager localhost xilinx_tcf Digilent 210203327962A Hardware Ow x Debug Probes n example_jtag_axi_0 v x Si ILA hw_ila x a oo SE Dl b gt Oy cs Fos ILA Properties Trigger Capture Status a ila 2 b st ig ai araddr 31 0 Trigger Mode Settings Core status uss Idle vz i localhost 1 Lo te axd_arburst 1 0 Window 1 of 1 Wo gt ilinx_tcf Digilent 210203327962A 1 Op ie ad_arcache 3 0 Trigger moce BASIC ONLY Cain sah tdia xc7k325t_0 7 tive Pro te axi_arid 4 mmml SF hw_axi_i AXT ia axi_arlen 7 0 Capture Mode Settings T hw ila 1 2A ES Basic Trigger Setup GB XADC System M 2 ILA Core
55. XTERM 100 mV TXDIFFSWING 250 mV 0000 TXPOST 0 00 dB 00000 TXPRE 0 00 dB 00000 Description Sweep 1 Scand Horizontal increment 8 Started 2013 Oct 07 15 10 53 Horizontal range 0 500 UI to 0 500 UT Ended 2013 Oct 07 15 11 00 Vertical increment 8 Vertical range 100 Figure 135 Analyzing the results of individual scans Programming and Debugging www xilinx com 101 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 6 Using Vivado ILA core to Debug JTAG AXI Transactions Lab 6 Using Vivado ILA core to Debug JTAG AX Transactions Introduction The purpose of this tutorial is to provide a very quick and easy to reproduce introduction to inserting an ILA core into the JTAG to AXI Master IP core example design and using the ILA s advanced trigger and capture capabilities What is the JTAG to AXI Master IP core The LogiCORE IP JTAG AXI core Is a customizable core that can generate AXI transactions and drive AXI signals internal to FPGA at run time This supports all memory mapped AXI interfaces except AXI4 Stream and Lite protocol and can be selected using a parameter The width of AXI data bus is customizable This IP can drive any AXI4 Lite or Memory Mapped Slave directly This can also be connected as master to the interconnect Run time interaction with this core requires the use of the Vivado logic analyzer feature Key Features e AXI4 master interface e Opt
56. _12_U_SINEGEN n_16_U_SINEGEN Figure 11 Netlist view of nets marked for debug Programming and Debugging www xilinx com 21 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 1 Using the Netlist Insertion Method for Debugging a Design Running the Set Up Debug Wizard 7 From the Debug window or Tools menu select Set Up Debug The Set Up Debug wizard opens Name Unassigned Debug Nets 30 EF GPIO_BUTTONS_db 2 J GPIO_BUTTONS_db 0 J GPIO_BUTTONS_db 1 Tu ta BUTTONS diy 2 Set up AE a Launch wizard for choosing nets and connecting them to debug cores PIU BU TN jal J GPIO_BUTTONS_re 1 U_SINEGEN sel 2 U_SINEGEN sine 20 GPIO_BUTTONS_IBUF 0 GPIO_ BUTTONS _IBUF 1 Debug Cores Debug Nets Figure 12 Launching the Set up Debug wizard 8 When the Set up Debug wizard opens click Next f Set up Debug Set up Debug This wizard will guide you through the process of 1 Choosing nets and connecting them to debug cores Driver Cell FDRE FDRE FDRE 2 Associating a clock domain with each of the nets chosen for debug 3 Choosing additional features on the debug cores like Data Depth Advanced Trigger mode and Capture Control Note This setup wizard does not apply to De VIO IDERI JTAG TOANE Master debug cores Please refer to Viva mine ar Da a a Cees A VIVADO To continue click Next Next gt Figure 13 Set up Debug dialog
57. _demo_inst_vio hdl_inst_vio sinegen_cemo_inst_vio vhd amp U_DEBOUNCE_0 debounce Mixed debounce vhd U_SINEGEN sinegen kintex sinegen vhd 3 vi U_FSM fsm Mixed fsm vhd w H Simulation Sources 1 Hierarchy IP Sources Libraries Compile Order Figure 26 Missing source for VIO core In the following step you will instantiate and configure this VIO core 11 From the Flow Navigator click IP Catalog expand Debug amp Verification then expand Debug and double click VIO 3 0 The Customize IP dialog box opens 12 On the General Options tab leave the Component Name to its default value of vio_0 set Input Probe Count to 1 Output Probe Count to 1 and select the Enable Input Probe Activity Detectors check box Programming and Debugging www xilinx com 32 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 3 Using a VIO Core for Debugging a Design in Vivado F Customize IP VIO Virtual Input Output 3 0 Documentation IP Location CJ Switch to Defaults Show disabled ports Component Name To configure more than 64 probe ports use Vivado Tcl Console General Options PROBE_IN Ports 0 0 PROBE_OUT Ports 0 0 T Input Probe Count 1 0 256 srobe_in0 0 0 probe_ourd 0 0 Output Probe Count 1 0 256 V Enable Input Probe Activity Detectors Figure 27 Configure General Options of the VIO core 13 On the PROBE_IN Por
58. achine Behavior The multiple transition glitch or bounce occurs because the mechanical button is making and breaking electrical contact just as you press it To eliminate this signal bounce a de bouncer circuit is required 5 Enable the de bouncer circuit by setting DIP switch position on the KC705 board labeled De bounce Enable in Figure 1 KC705 Board Showing Key Components to the ON or UP position 6 Source the rt tcl file again by typing source rt tcl in the Tcl Console and o Ensure that you no longer see multiple transitions on the GPIO_BUTTON_re 1 signal on a single press of the Sine Wave Sequencer button o Verify that the state machine is working correctly by ensuring that the sineSel signal transitions from 00 to 01 to 10 to 11 and back to 00 with each successive button press Programming and Debugging www xilinx com 67 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Using Vivado Logic Analyzer to Debug Hardware Verifying the VIO Core Activity Only applicable to Lab 3 1 From the Program and Debug section in Flow Navigator click Open Hardware Manager 4 Program and Debug aS synth_1 5 Bitstream Settings E Generate Bitstream Open Hardware Manager y 14 Open Hardware Manager Open the hardware program and debug manager Figure 80 Open Hardware Manager 2 The Hardware Manager window opens Click Open a new hardware target project_3 C te
59. actie amp Hardware Device Properties 9 g Program Device Connected Ctri E Assign Programming File P Refresh Device Export to Spreadsheet Figure 82 Program FPGA In the Program Device dialog box ensure that the bit file to be programmed is correct Click OK Figure 83 Program Device with the sinegen_demo_inst_vio bit file 10 After the FPGA device is programmed you see the VIO and the ILA core in the Hardware window x sE DI gt Name Ee localhost 1 Be xilinx_tef Digilent 210203327962A 1 gt xc7k325t_0 3 active x k k F XADC System Monitor hw_ila_1 ILA 4f hw_vio_1 VIO Status Connected coe Idle OK Outputs Reset Figure 84 The ILA and VIO cores in the Hardware window Programming and Debugging UG936 v 2014 2 June 4 2014 www xilinx com Send Feedback 69 amp XILINX ALL PROGRAMMABLE Using Vivado Logic Analyzer to Debug Hardware 11 Click Run Trigger Immediate to capture the data immediately Run Trigger Immediate Status B localhost 1 Connected Be xilinx_tcf Digilent 210203327962A Open OEE ATE hw_ila_1 ILA Idle F hw_vio_1 VIC OK Outputs Reset Figure 85 Run Trigger Immediate 12 Make sure that there is activity on the sine 19 0 signal 13 Select the sine signal in the Waveform window right click and select Waveform Style gt Analog 14 Select the sine signal in the Waveform wi
60. am This synthesizes implements and generates a bitstream for the design 2 The No Implementation Results Available dialog box appears Click Yes 3 After bitstream generation completes the Bitstream Generation Completed dialog box appears Open Implemented Design is selected by default Click OK Programming and Debugging UG936 v 2014 2 June 4 2014 www xilinx com 36 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 3 Using a VIO Core for Debugging a Design in Vivado 4 From the Implementation drop down list in Flow Navigator expand Implemented Design and select Report Timing Summary A Properties Implementation Settings sain ie S e h P Run Implementation 4 E Implemented Design fA Edit Timing Constraints Report Timing Summary Wy Report Clock Networks 5 Report Clock Interact Report Timing Summary Report DRC __ Specify analysis options and create a timing summary report FA Report Noise Figure 35 Report timing summary for Lab 3 5 In the Report Timing Summary dialog box click OK Make sure that all timing constraints have been met a 2 we a Design Timing Summary General Information lt E E 4 Timer Settings sas Hold Pulse Width SeOesgn Timing Summary Worst Negative Slack WNS 1 274 ns Worst Hold Slack WHS 0 059 ns Worst Pulse Width Slack WPWS 1 732 ns ec dat ena 4 Total Negative Slack TNS 0 000ns Total Hold Slack THS
61. anager Generate Bitstream gt E Hardware eS hy itl E Launch IMPACT Open Hardware Manager Open the hardware program and debug n Figure 56 Open Hardware Manager 2 Click Open a new hardware target in the Hardware Session view proj_netlist C Vivado_Debug proj_netlist proj_netlistxpr Vivado File Edit Flow Tools Window Layout View Help ee ekh lt X d P BS XK E GS l Seia yoAnayzer W amp Flow Navigator K EF pig Dio mpa _ Hardware Manager unconnected No hardware target is open Open recent target Open a n rdv E 4 Project Manager Hardware Ov p tale tie heb E Project Settings sits Ht Ba ow gt bp Gt Add Sources Name Figure 57 Connect to a Hardware Target 3 The Hardware Manager window opens Click Open a new hardware target The Open New Hardware Target wizard opens Programming and Debugging www xilinx com 54 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Using Vivado Logic Analyzer to Debug Hardware 4 In the Hardware Server Settings page type the name of the server or select Local server if the target is on the local machine in the Connect to field g Open New Hardware Target Hardware Server Settings Select local or remote hardware server then configure the host name and port settings Use Local server if the target is attached to the local machine otherwise use Remot
62. ata 0 0Jaxi rid axi_rlast axi_rready 1 O0 axi_rresp axi_rvalid 31 0 axi_wdata axi_wlast axi_wready 3 0 axi_wstrb axi_wvalid jtag_axi_o v file 20 In the Flow Navigator on the left side of the Vivado window click Run Synthesis 21 Open the synthesized design by selecting Open Synthesized Design and clicking OK Programming and Debugging UG936 v 2014 2 June 4 2014 Synthesis Completed xa i Synthesis successfully completed Next Run Implementation Open Synthesized Design View Reports Don t show this dialog again Cr Figure 145 Open Synthesized Design www xilinx com 112 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 6 Using Vivado ILA core to Debug JTAG AXI Transactions 22 Once the synthesized design opens do the following a Select the Debug layout in the main toolbar of the Vivado IDE jtag_axi_O_example c jtag_2_axi_tutorial jtag_2_axi_tutorial jtag_axi_0_example jtag_axi_0_example xpr Vivado 2013 4 bol File Edit Flow Tools Window Layout View Help f ePE wpe xX gt bN Hgo GAl E g E Default tayout e E amp Synthesis Complete Flow Navigator Synthesized Design xc7k325tffig900 2 Default Layout x I O Plannin Oa Newist 2 Clock eis E Project Summary Device x Scen 4 gt B OZ paa a 3 Floorplannin a Project Manager a E p q Project Settings li example_jtag_ax_0 tS Nets 266 5 Timing Analysis a Add Sources t
63. ate Block Desigr a Open Block Design E gt Generate Block Des Hierarchy Librar 4 d Sources V Templ AET Simulation Simulation Settings G Run Simulation Properties Ov x RTL Analysis la Open Elaborated De Details Synthesis Synthesis Settings gt Run Synthesis E Open Synthesized Implementation amp Implementation Set gt Run Implementatior Part Constraints Strategy igen l mc7kK3251ffg900 2 constrs_1 vivado Implementation Defaults Vivado Implementation 2013 Not started penon Suns Program and Debug G Bitstream Settings Generate Bitstream gt B Open Hardware Ma amp Launch iMPACT il 5 Tel Console Messages C Log Reports _ Design Runs Figure 139 JTAG to AXI Master IP Core Programming and Debugging www xilinx com 107 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 6 Using Vivado ILA core to Debug JTAG AXI Transactions 12 Double click JTAG to AXI Master core The Customization dialog of the core appears Accept the default core settings by clicking OK 4F Customize IP JTAG to AXI Master 1 0 I Documentation L5 IP Location C Switch to Defaults A noe open nee Component Name jtag_axi_0 AXI Protocol AXI4 AXI Data Width 32 AXI ID Width 1 Figure 140 JTAG to AXI Master Customization Dialog Programming and Debugging www xilinx com 108 UG936 v 2014 2 Ju
64. ation of the Sine Wave Generator ccccccesccccsecccesececenscecenececeneceeeneeseueceseueceseueseneuesenens 53 EE NO ccs E E emia eermiecrn a oot eae iowa nee eee 53 Using the Vivado Integrated Logic ANalyZer cccccccsssccccessececceseccccesececausececeuaececseescceseesecessunecessugeceeseneeeetas 54 Verifying Sime WWe 4 610 1 15 eee nn en se ee ee ee ee 60 Displaying the Sine WY aes atceteirs ccceessteatecisce ns crncenc ct gvcirrocean sec osteatnaee oacumnnne E E 61 Correcting Display of the Sine Wave oe cecicec tescetautas crave sartectevdeacesicanaesdawesna catuntoeaatesartadneces tavacaannadenteninedaessignces 62 Step 2 Debugging the Sine Wave Sequencer State Machine Optional cccccccecccssessscsseeeesseeeeeseseeeseseenes 64 Sine Wave Sequencer State Machine Overview cccccsseccccsseccccenseccceesececeeeceeseuscceesusecesseeceeeeneceeseusecessuneces 64 Viewing the State Machine Glitch scsccccstesccssscccsescscateavesucesascacedsannvcdesatascaveavaontusiuesdevaawesaesdeesuttacdeeninnnesneniberecs 65 Fixing the Signal Glitch and Verifying the Correct State Machine Behavior ccceccccseccceeecsceeeceeeneseeeeeees 67 Verifying the VIO Core Activity Only applicable to Lab 3 cceesccccccsssseccceeeeeecceseeeesecceseeeeeeseeseeeneeeseseeeees 68 Lab 5 Using Vivado Serial Analyzer to Debug Serial LINKS ccccessccccessececeesececeeeccceeescceseeeceseeecesseeeeeetenseeeeas 76 M FON CU OMe E ones E E
65. bug Layout in the Vivado IDE toolbar Programming and Debugging www xilinx com UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 6 Using Vivado ILA core to Debug JTAG AXI Transactions b Select the Debug window near the bottom of the Vivado IDE 4 jtag_axi_0_example c jtag_ _axi_tutorial jtag_ axi_tutorial jtag_axi_0_example jtag_axi_0 examplexpr Vivado 2013 4 File Edit Flow Tools Window Layout View Help My Search commands f G8B oeRhx a gt p NH g O S RKE G Boeng AE E a E nthesi Flow Navigator Synthesized Design xc7325tffg900 2 active Am fe Netlist Ow x a Schematic x example_jtag_axi_O v x a 2 8 Cells 2 0 Ports 266 Nets 4 Project Manager example_jtag_axi_0 Project Settings GHGS Nets 266 Add Sources FHS Leaf Cells 8 iF IP Catalog eA it axd_bram_ctri_inst axd_bram_ctri_0 dbg_hub dbg_hub_cv a IP Integrator Ee jtag_aod_full_inst jtag_and_0 J Create Block Design BP Open Block Design Generate Block Design 4 Simulation Simulation Settings amp Sources Gi Netlist 4 Run Simulation l Properties 4 RTL Analysis F e Pjr E Open Elaborated Desig amp Synthesis Settings Run Synthesis a E Synthesized Design A Edit Timing Constrai G Report Timing Sumi 3 Us Report Clock Networ Driver Cell Raport Gonk eae a EHI dbg_hub labtools_xsdbmasterlib_v2 Report DRC jtag_axi_full_ins
66. cecenecseeneceeeneeseueeeceueceneueseneness 31 Step 2 Synthesize Implement and Generate Bitstream ccccccccssccccsececeeecsceuececeeceeeneceeeuceseuececeuecseeneeeeeness 36 Lab 4 Using Synplify Pro Synthesis Tool and Vivado for Debugging a Design ccccceeescceseseeeecsceeceeeueceeeeeseees 38 PGE OCC OI e A E E E E E 38 Sepi Create a yP PrO FO C eee E E E S E Sa 38 Send Feedback Programming and Debugging www xilinx com 3 UG936 v 2014 2 June 4 2014 Step 2 Synthesize the Synplify Project incearsceinsccsoaecsierapasesdtanaiuguaeiatensatensssoarsavenddanatesatatetepatenandemtunnvesdanaisseeeiaions 45 Step 3 Create EDIF Netlists for the Black Box Created in Synplify Pro esssessssssssesesseneesreesrerssreesesrrresrreresrressseeee 46 Step 4 Create a Post Synthesis Project in Vivado IDE sesssesssssssesreserrrsrrresrersrrresrrnsrtessrrrsrrrsrteserrrsreesrreserrrereens 47 Step 5 Add more Debug Nets to the Project eesssesesesrrssrrrrssrrressrrresrrressrtrrsrterusreresrrressreresrtresereresreressrerens 50 R nning the Setup Debug Wizard siesienseciicecasresir eiei E souasceedeutaneddentabureers 51 Step 6 Implementing the Design and Generating the Bitstream cccccccseesccseccceseesceeseeeeeceteueseeeueseeeneeeeens 52 Using Vivado Logic Analyzer to Debug Hardware ccccccccsecccceececenececenecseeseseeuecsceuecseeesseeueeseueceseuecseeueceesesenens 53 PURO ICTION e E E E 53 Step 1 Verifying Oper
67. ceed to Using Vivado Logic Analyzer to Debug Hardware to complete the rest of this lab Programming and Debugging www xilinx com 29 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 3 Using a VIO Core for Debugging a Design in Vivado Lab 3 Using a VIO Core for Debugging a Design in Vivado Introduction The Virtual Input Output VIO core is a customizable core that can both monitor and drive internal FPGA signals in real time The number and width of the input and output ports are customizable in size to interface with the FPGA design Because the VIO core is synchronous to the design being monitored and or driven all design clock constraints that are applied to your design are also applied to the components inside the VIO core Run time interaction with this core requires the use of the Vivado logic analyzer feature The following figure is a block diagram of the new VIO 3 0 core VIO PROBE _ NO 0 0 PROBE OUTO 255 0 PROBE_1N1 255 0 pe Input Registers PROBE_OUT1 0 0 Pe and Activity Output Registers _ _ _ _ _ PROBE_1IN255 31 0 po Detectors PROBE _OUT255 127 0 Interface to JTAG through Debug Hub Figure 25 VIO Block Diagram This lab will walk you through the steps of instantiating and configuring a VIO core and connecting the I Os of the design to it This way you can debug your design when you do not have access to the hardware or the hardware is remot
68. cess to ports and the dynamic reconfiguration port attributes of the GTX transceivers Communication logic is also included to allow the design to be run time accessible through JTAG In the course of this tutorial you e Create customize and generate an Integrated Bit Error Ratio Tester IBERT core design in the Vivado Integrated Design Suite e Interact with the design using Serial I O Analyzer This includes connecting to the target KC705 board configuring the device and interacting with the IBERT Transceiver IP cores e Perform a sweep test to optimize your transceiver channel and to plot data using the IBERT sweep plot GUI feature Design Description You can customize the IBERT core and use it to evaluate and monitor the functionality of transceivers for a variety of Xilinx devices The focus for this tutorial is on Kintex 7 GTX transceivers Accordingly the KC705 target board is used for this tutorial The following figure shows a block diagram of the interface between the IBERT Kintex 7 GTX core interfaces with Kintex 7 transceivers Programming and Debugging www xilinx com 76 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 5 Using Vivado Serial Analyzer to Debug Serial Links e DRP Interface and GTX Port Registers IBERT provides you with the flexibility to change GTX transceiver ports and attributes Dynamic reconfiguration port DRP logic is included which allows the runtime
69. ch of which has four GTX transceivers These components of the IBERT were detected while scanning the FPGA after downloading the bitstream If you do not see the QUADS then select the XC7K325 device right click and select Refresh Device Programming and Debugging www xilinx com 90 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 5 Using Vivado Serial Analyzer to Debug Serial Links Status E localhost 1 Connected Ge xilinx_tcf Digilent 210203327962A 1 Open XC7K325T_0 1 active BERT a Quad_117 5 amp COMMON_X0Y2 Locked Programmed By MGT_XOY8 8 000 Gbps Pa MGT_XOY9 No Link MGT_XOY10 No Link By MGT_XOY11 No Link Quad_118 5 m COMMON_X0Y3 Locked MGT_X0Y12 No Link PBa MGT_X0Y13 No Link By MGT_X0Y14 No Link B4 MGT_XOY15 No Link Figure 118 The Hardware window showing the QUADS after the FPGA has been programmed 9 Next create links for all eight transceivers Vivado Serial I O analyzer is a link based analyzer which allows users to link between any transmitter and receiver GTs within the IBERT design For this tutorial simply link the TX and RX of the same channel To create a link right click the IBERT Core in the Hardware window and click Create Links Status 4 Connected Mle xilinx_tcf Digilent 210203327962A 1 Open xc7k325t_O 2 active Programmed T TBERT BERTI Ei Quad_117 5 amp COMMON_X0Y2 Pa MGT_X
70. d Vivado for Debugging a Design 6 In the same dialog box set Files of type to Constraints File This shows the synplify_1 sdc file Select the file and click Add as shown in the following figure Add Files to Project Look in M C Vivado_Debug src Lab4 JO O0 EJ yy My Computer R ndutta File name synplify_1 sdc Files of type Constraint Files sdc z VHDL Verilog lib E Files to add to project 4 file s selected Y Use relative paths Y Add files to Folders Folder Options src Lab4 debounce vhd lt add All src Lab4 fsm vhd src Lab4 sinegen_demo vhd lt Add src Lab4 synplify_l sdc Remove All gt Remove gt Figure 41 Adding SDC Constraints File to the Synplify Pro Project Programming and Debugging www xilinx com 41 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 4 Using Synplify Pro Synthesis Tool and Vivado for Debugging a Design 7 Inthe same dialog box set Files of type to Compiler Directives File This shows the synplify_1 cdc file Select the file and click Add as shown in the following figure Click OK Add Files to Project Look in C Vivado_Debug src Lab4 yy My Computer R ndutta File name synplify_1 cdc Files of type VHDL Verilog lib Files to add to project 5 file s selected Y Use relative paths Y Add files to Folders Folder Options src Lab4 debounce vhd lt Add All
71. d it indicates which of the four sine wave generators is selected Programming and Debugging www xilinx com 64 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Using Vivado Logic Analyzer to Debug Hardware The input signal button connects to the top level signal GPIO_BUTTONS re 1 which is a low to high transition indicator on the Sine Wave Sequencer button The output signal Y connects to the top level signal sineSel which selects the sine wave GPIO_BUTTON_ 1 GPIO_BUTTONS_re 1 sineSel IBU Figure 76 Sine Wave Sequencer Button Schematic Viewing the State Machine Glitch You cannot troubleshoot the issue you identified above by connecting a debug probe to the GPIO_BUTTON 1 input signal itself The GPIO_BUTTON 1 input signal is a PAD signal that is not directly accessible from the FPGA fabric Instead you must trigger on low to high transitions rising edges on the GPIO_BUTTON_IBUF signal which is connected to the output of the input buffer of the GPIO_BUTTON 1 input signal As described earlier the glitch reveals itself as multiple low to high transitions on the GPIO_BUTTONS_1_IBUF signal but it occurs intermittently Because it could take several button presses to detect it you will now set up the Vivado logic analyzer tool to Repetitive Trigger Run Mode This setting makes it easier to repeat the button presses and look for the event in the Waveform viewer 1 Open the Debug Probe
72. debug attributes to show debug nets in the synthesized netlist attribute mark_debug string attribute mark_debug of GPIO BUTTONS db signal is true attribute mark_debug of GPIO_BUTTONS dly signal is true attribute mark debug of GPIO BUTTONS re signal is true Figure 46 Add mark_debug attribute in HDL file 12 The synplify_1 sdc file contains various kinds of constraints such as pin location I O standard and clock definition The synplify_1 cdc file contains directives for the compiler Here is where the nets of interest to us that are marked for debug are located The attribute and the nets selected for debug are shown in the following figure Attributes that are needed to mark debug the nets that are needed to be viewed in ILA define attribute comment Mark sinegen as black box v iwork sinegen syn_black box 1 define attribute comment Set no prune on sinegen v iwork sinegen syn_noprune 1 define attribute comment Mark entire bus for debug 1 sinegen sine mark debug true define attribute comment Mark entire bus for debug 1 sinegen sel mark debug true Figure 47 Synplify Pro Constraints in CDC Files In the above constraints sinegen has been defined as a black box by using the syn_black_box attribute Second the syn_no_prune attribute has been used so that the I Os of this block are not optimized away Finally two nets sine 20 0 and sel 1 0 have been assigned th
73. e Programming and Debugging www xilinx com UG936 v 2014 2 June 4 2014 44 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 4 Using Synplify Pro Synthesis Tool and Vivado for Debugging a Design mark_debug attribute such that these two nets should show up in the synthesized design in Vivado IDE for further debugging For further information on these attributes please refer to the Synplify Pro User Manual and Synplify Pro Reference Manual Step 2 Synthesize the Synplify Project 1 Before implementing the project you need to set the name for the output netlist file By default the name of the output netlist file is synplify_l edf To change the name of the output file type the following command at the Tcl command prompt project result tile rey_1 sinegen demo edr You will use this file in Vivado IDE 2 With all the project settings in place click the Run button in the left panel of the Synplify Pro window to start synthesizing the design S Synplify Pro I 2013 09 1 C Vivado_Debug synopsys s D gt File Edit View Project Import Run Analysis HI BBAD 40 HAA SH mM PRAMS 2B Se Bl sl syneny Pro t 2 Open Project R Close Project 1 Synplify 1 rev_1 Xilinx Kint a gt synplify_1 CAViva Add File 5B Lab4 ES Change File 3 VHDL gs Add Implementation if debounce vh r 8 fsm vhd wo 2 Implementation Options BR Add P amp R Implementation View Log E
74. e otherwise use Remote server Connect to Local server target is on local machine Click Next to launch and or connect to the vcse_server port 60001 and hw_server port 3121 applications on the local machine Figure 156 Hardware Server Name Note Depending on your connection speed this may take about 10 to 15 seconds Programming and Debugging www xilinx com 122 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 6 Using Vivado ILA core to Debug JTAG AXI Transactions 4 If there is more than one target connected to the hardware serve you will see multiple entries in the Select Hardware Target page In this tutorial there is only one target as shown in the following figure Click Next g Open New Hardware Target Select Hardware Target Select a hardware target from the list of available targets then set the appropriate JTAG clock TCK frequency If you do not see the expected devices decrease the frequency or select a different target Hardware Targets Type Port Name JTAG Clock Frequency xilinx tcf Digilent 210203327962A 15000000 Hardware Devices for unknown devices specify the Instruction Register IR length Name ID Code IR Length xc7k325t_0 33651093 6 VCSE server localhost 60001 Hardware server localhost 3121 Figure 157 Select Hardware Target 5 Leave these settings at their default values as shown Click Next Programming and Debugging www x
75. e Trigger State Machine area click the Create new trigger state machine link O2 x Trigger Capture Status 0 Core status Ide Fre Trigge Trigger State Machine Flags Flag 0 0 Flag 1 0 Flag 2 0 Flag 3 0 Trigger state 0 4 Wl Trigger State Machine Figure 167 Setting Trigger mode to ADVANCED and Trigger Position to 512 in the ILA Dashboard Programming and Debugging UG936 v 2014 2 June 4 2014 www xilinx com 2 O n existing tri r te machin Create new trigger state machine Send Feedback amp XILINX ALL PROGRAMMABLE Lab 6 Using Vivado ILA core to Debug JTAG AXI Transactions 5 In the New Trigger State Machine File dialog box set the name of the state machine script to txns tsm New Trigger State Machine File Save in jtag_2_axi_tutorial 98 BPA oox B b jtag_2_axi_tutorial Recent Directories on oO C jtag_2_axi_tutorial Recent Items File Preview select a file to preview My Documents A Dr a Computer File name tins ca Network Files of type Trigger State Machine Files tsm Figure 168 Creating a new Trigger State Machine script 6 A basic template of the trigger state machine script is displayed in the Trigger State Machine gadget Expand the trigger state machine gadget in the ILA dashboard Copy the script below after line 17 of the state machine script and save the file The wait_for_arvalid state is used to detect the star
76. e server Connect to Local server target is on local machine Click Next to launch and or connect to the vcse_server port 60001 and hw_server port 3121 applications on the local machine Figure 58 Hardware Server Settings Note Depending on your connection speed this may take about 10 to 15 seconds Programming and Debugging www xilinx com 55 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Using Vivado Logic Analyzer to Debug Hardware 5 If there is more than one target connected you will see multiple entries in the Select Hardware Target page In this tutorial there is only one target as shown in the following figure Click Next gt Open New Hardware Target Select Hardware Target Select a hardware target from the list of available targets then set the appropriate JTAG clock TCK frequency If you do not see the expected devices decrease the frequency or select a different target Hardware Targets Type Port Name JTAG Clock Frequency xilinx_tcf Digilent 210203327962A 15000000 EEE Hardware Devices for unknown devices specify the Instruction Register IR length Name ID Code IR Length xc7k325t_0 33651093 6 VCSE server localhost 60001 Hardware server localhost 3121 Figure 59 Select Hardware Target 6 Leave these settings at their default values Click Next Programming and Debugging www xilinx com 56 UG936 v 2014 2 June 4 2014 Send Fe
77. edback amp XILINX ALL PROGRAMMABLE Using Vivado Logic Analyzer to Debug Hardware 7 In the Open Hardware Target Summary page click Finish as shown in the following figure f gt Open New Hardware Target Open Hardware Target Summary Hardware Server Settings Server localhost 3121 VCSE Server Settings o Server localhost 60001 o Version 20 Target Settings o Target xilinx_tcf Digilent 210203327962A o Frequency 15000000 VIVADO To connect to the hardware described above click Finish ec Cenn ones Figure 60 Hardware Target Summary 8 Wait for the connection to the hardware to complete The dialog in following figure appears while hardware is connecting Open Hardware Target W Opening target Figure 62 Open Hardware Target After the connection to the hardware target is made the dialog shown in the following figure appears Note The Hardware tab in the Debug view shows the hardware target and XC7K325T device detected in the JTAG chain Programming and Debugging www xilinx com 57 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Using Vivado Logic Analyzer to Debug Hardware a TeS bi m Name Status E localhost 1 Connected le xilinx_tcf Digilent 210203327962A 1 Open E xc7k325t_O 1 active Not programmed GB XADC System Monitor Figure 63 Active Target Hardware 9 Next program the XC7K325T device us
78. eesseeeseeeeeeees 128 Programming and Debugging www xilinx com UG936 v 2014 2 June 4 2014 Send Feedback all INO IC OS ace oapanseueenet yecennecnarisaacceecatsnmne E E T E Please Read Important Legal NOTICES scjcascsdsicnssianntoasacasnmasnesiccsmeceteantioeshataneeidesieb hose bataciednenign iaeaintdcuaeinion anuionaoieaieneds Programming and Debugging www xilinx com UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Debugging in Vivado Tutorial Introduction This document contains a set of tutorials designed to help you debug complex FPGA designs The first four labs explain different kinds of debug flows that you can chose to use during the course of debug These labs introduce the Vivado debug methodology recommended to debug your FPGA designs The labs describe the steps involved in taking a small RTL design and the multiple ways of inserting the Integrated Logic Analyzer ILA core to help debug the design The fifth lab is for debugging high speed serial I O links in Vivado The first four labs converge at the same point when connected to a target hardware board Example RTL designs are used to illustrate overall integration flows between Vivado logic analyzer ILA 3 0 and Vivado Integrated Design Environment IDE In order to be successful using this tutorial you should have some basic knowledge of Vivado Design Suite tool flow Objectives These tutorials e Show you how to take advantage
79. egen block The four netlist files used in this tutorial are already provided as a part of the source files However you can overwrite them by using your own netlist files To do this use the following Tcl command in the Tcl console of Vivado IDE write_edif force Vivado_Debug src Lab4 sinegen edn Ensure that the path specified to the src folder is correct At this point you should see four edn files in the Vivado_Debug src folder as shown below o dds_compiler_v6_0O_viv edn o dds_compiler_v6_O0O_viv_parameterizedl edn o dds_compiler_v6_O_viv_parameterized3 edn o sinegen edn 14 Click File gt Exit in Vivado IDE When the OK to exit dialog box pops up click OK Step 4 Create a Post Synthesis Project in Vivado IDE Launch Vivado IDE Click Create New Project This opens up the New Project wizard Click Next Set the Project Name to proj_synplify Click Next Under Project Type select Post synthesis Project Click Next ae Ye LS FP Under Add Netlist Sources click Add Files navigate to the Vivado_Debug synopsys rev_1l folder and select sinegen_demo edf Click OK 6 Add the four netlist files created in the previous section Click Add Files again navigate to the Vivado_Debug src Lab4 folder and select the following files e sinegen edn e dds_compiler_v6_0_viv edn e dds_compiler_v6_0_viv_parameterizedl edn e dds_compiler_v6_0 viv_parameterized3 edn Click OK in the Add Source Files dialog box In the Add Netlist
80. ely located The following ports are created e One 4 bit PROBE_INO port This has two bits to monitor the 2 bit Sine Wave selector outputs from the finite state machine FSM and other two bits to mimic the state of the other two LEDs on the Programming and Debugging www xilinx com 30 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 3 Using a VIO Core for Debugging a Design in Vivado board We will configure these 4 bit signals as LEDs during run time to mimic the LEDs displayed on the KC705 board One 2 bit PROBE_OUTO port to drive the input buttons on the FSM We will configure it so one bit can be used as a toggle switch during run time to mimic the PUSH_BUTTON SW3 and second bit will be used as the PUSH_BUTTON SW6 Step 1 Creating a Project with the Vivado New Project Wizard To create a project use the New Project wizard to name the project to add RTL source files and constraints and to specify the target device 1 Invoke Vivado IDE 2 In the Getting Started page click Create New Project to start the New Project wizard Click Next 3 Inthe Project Name page name the new project proj_hdl_vio and provide the project location C Vivado_Debug Ensure that Create project subdirectory is selected Click Next 4 In the Project Type page specify the Type of Project to create as RTL Project Click Next 5 In the Add Sources page a Set Target Language to VHDL b Click Add
81. esign 30 Save the constraints by clicking Save Programming and Debugging www xilinx com 119 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 6 Using Vivado ILA core to Debug JTAG AXI Transactions 31 The insertion of debug cores and changing of properties on those debug cores adds constraints to your target XDC constraint file This modification of your target constraints file currently sets your synthesis out of date You can force the design up to date by clicking more info in the upper right corner of the Vivado IDE then clicking Force up to date ce fm Synthesis Out of Date more info Synthesis Out of Date Due to synth_1 Files Modified D coma N a Force up to date Force active runs up to date iia iat SELEICIEIEITIETEIT Waaa OOOO cc cc ncn itaa Axi full inst Figure 153 Forcing Synthesis up to date 32 In the Flow Navigator on the left side of the Vivado IDE click Generate Bitstream 33 Click Yes to implement the design 34 Wait until the Vivado status shows write_bitstream complete Programming and Debugging www xilinx com UG936 v 2014 2 June 4 2014 Send Feedback 120 amp XILINX ALL PROGRAMMABLE Lab 6 Using Vivado ILA core to Debug JTAG AXI Transactions 35 In the Bitstream Generation Completed dialog box select Open Hardware Manager and click OK Bitstream Generation Completed Ed Bitstream Generation successfully completed
82. for each LED selection that the correct sine wave displays Also note that the signals in the Waveform window have been re arranged in the previous three figures Step 2 Debugging the Sine Wave Sequencer State Machine Optional As you were correcting the sine wave display the LEDs might not have lit up in sequence as you pressed the Sine Wave Sequencer button With each push of the button there should be a single cycle wide pulse on the GPIO_BUTTONS re 1 signal If there is more than one the behavior of the LEDs becomes irregular In this section of the tutorial use Vivado logic analyzer to probe the sine wave sequencer state machine and to view and repair the root cause of the problem Before starting the actual debug process it is important to understand more about the sine wave sequencer state machine Sine Wave Sequencer State Machine Overview The sine wave sequencer state machine selects one of the four sine waves to be driven onto the sine signal at the top level of the design The state machine has one input and one output The following figure shows the schematic elements of the state machine Refer to this diagram as you read the following description and as you perform the steps to view and repair the state machine glitch e The input is a scalar signal called button When the button input equals 1 the state machine advances from one state to the next e The output is a 2 bit signal vector called Y an
83. g a Design in Vivado c Select all XCI source files and click OK d Verify that the files are added and Copy Sources into Project is selected Click Next 7 Inthe Add Constraints optional page the provided XDC file sinegen_demo_kc705 xdc should automatically appear in the main window Click Next 8 In the Default Part page specify the xc7k325tffg900 2 part for the KC705 platform You can also select Boards and then select Kintex 7 KC705 Evaluation Platform Click Next 9 Review the New Project Summary page Verify that the data appears as expected per the steps above Click Finish 10 In the Sources window in Vivado IDE expand sinegen_demo_inst to see the source files for this lab Note that tla_O core has been added to the project cos oot GY Bi a2 Design Sources 1 vig sinegen_demo_inst hdl_inst sinegen_cemo_inst amp U_DEBOUNCE_0 debounce Mixed debounce vhd U_DEBOUNCE_1 debounce Mixed debounce vhd H U_SI gen kintex sinegen vhd vehi re Constraints 1 6 Simulation Sources 1 F T a Hierarchy IP Sources Libraries Compile Order Figure 19 ILA instantiation in HDL Double click the sinegen_demo_inst vhd file to open it and inspect the instantiation and port mapping of the ILA core in the HDL code Note that attributes have been placed in the source file to preserve the net names attribute keep string attribute keep of GPIO_BUITONS db signal
84. ge to VHDL Ensure that Copy sources into project box is selected Click Next 6 Under Add Existing IP click Add Files navigate to the Vivado_Debug src Lab4 folder and select the sine _high xci sine_low xci and sine _mid xci files Click Next 7 Under Add Constraints the sac files are automatically added to the project These files are not needed for this step Remove them from this project by clicking Remove Selected File on the right of the dialog box Click Next 8 Under Default Part select Boards and then select the Kintex 7 KC705 Evaluation Platform and correct version for your hardware Click Next 9 Under New Project Summary ensure that all the settings are correct Click Finish 10 Once the project has been created in Vivado Flow Navigator under the Project Manager folder click Project Settings In the pop up dialog box in the left panel click Synthesis From the pull down menu on the right panel set flatten_hierarchy to none Click OK 11 In Vivado IDE Flow Navigator under Synthesis Folder click Run Synthesis 12 When synthesis completes the Synthesis Completed dialog box appears Select Open Synthesized Design and click OK Programming and Debugging www xilinx com 46 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 4 Using Synplify Pro Synthesis Tool and Vivado for Debugging a Design 13 Now you need to write the netlist file for all the components used in the sin
85. h different sine wave output frequency using the virtual push_button_vio from the VIO core follow the following simple steps a Toggle the value of the push_button_vio output driver from 0 to 1 to 0 by clicking on the logic displayed under the Value column You will notice the sineSel LEDs changed accordingly 0 1 2 3 0 etc b Select hw_ila_1 in the Hardware window and click Run Trigger to capture and display the selected sine wave signal from the previous step Programming and Debugging www xilinx com 75 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 5 Using Vivado Serial Analyzer to Debug Serial Links Lab 5 Using Vivado Serial Analyzer to Debug Serial Links Introduction The Serial I O analyzer is used to interact with IBERT Version 3 0 or later debug IP cores contained in a design It is used to debug and verify issues in high speed serial I O links The Serial I O Analyzer has several benefits as listed below e Tight integration with Vivado IDE e Ability to script during netlist customization generation and serial hardware debug e Common interface with the Vivado Integrated Logic Analyzer The customizable LogiCORE IP Integrated Bit Error Ratio Tester IBERT core for 7 series FPGA GTX transceivers is designed for evaluating and monitoring the GTX transceivers This core includes pattern generators and checkers that are implemented in FPGA logic and provides ac
86. ial Links E Project Summary x FIP Catalog x 7 Search IBERT 1 match n m 2 Name Version r g Er Debug amp Verification Debug iF IBERT 7 Series GTX Figure 98 Instantiating the IBERT IP from the Vivado IP Catalog 3 Double click IBERT 7 Series GTX IP This brings up the customization GUI for the IBERT 4 In the Customize IP dialog box choose the following options in the Protocol Definition tab a Type the name of the component in the Component Name field In this case leave the name as the default name ibert_7series_gtx_0 b Ensure that the Silicon Version is selected as General ES Production c Ensure that the Number of Protocols option is set to 1 d Change the LineRate Gbps to 8 e Change DataWidth to 40 f Change Refclk MHz to 125 g Ensure that the Quad Count is set to 2 h Ensure Quad PLL box is selected Programming and Debugging www xilinx com 79 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE F Customize IP IBERT 7 Series GTX 3 0 gl Documentation C3 IP Location C3 Switch to Defaults Show disabled ports RXN_I 3 0 RXP_I 3 0 TXN_O 3 0 GTREFCLKO_I 0 0 TXP_O 3 0 GTREFCLK1_I 0 OUTCLK_O SYSCLK_I Lab 5 Using Vivado Serial Analyzer to Debug Serial Links Component Name gibert_ series_gt_0 Protocol Definition Protocol Selection Clock Settings Summary Silicon Version General ES Production Initial ES The maximum n
87. ial jtag_2_axi_tutorial jtag_2_axi_tutorialxpr Vivado 2013 4 File Edit Flow Tools Z2 aak bh x Flow Navigator Aze Project Settings GF Add Sources LF IP Catalog a IP Integrator J Create Block Desig BP Open Block Design amp Generate Block De 4 Simulation iQ Run Simulation a RTL Analysis a Synthesis Synthesis Settings Run Synthesis gt BP Open Synthesized a Implementation Implementation Si gt Run implementati gt E Open Implementet a Program and Debug Bitstream Settings W Generate Bitstrear b ae Open Hardware M Launch iMPACT Simulation Setting gt E Open Elaborated C Window Layout View Help gt DP WH XX G A Default Layout Project Manager jtag_2_axitutorial Sources Oo S m at A Design Sources EHE Constraints EHS Simulation Sources a2 sim_1 JERE Project Settings Project name Product family Kintex 7 Project part xc7k32atfigo00 2 Top module name Not defined Board jtag_2_axi_tutorial Kintex KC705 Evaluation Platform Board name xilinx com kintex kc705 1 1 URL www dling com ke705 Board overview The KC705 board is intended to showcase and den XC7K325T FFG900 device The board includes Giga memory 128MB BPI Linear Flash 128MB of Platfort port Display name Hierarchy Libraries Compile Order Sources 7 Templates Properties e E Synthesis Status
88. ile from Project Delete Alt Equals Disable File Alt Minus Source File Properties gt BE i sinegen_demo edf i a LAE arii L Figure 49 Specifying the top level module Programming and Debugging www xilinx com 48 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 4 Using Synplify Pro Synthesis Tool and Vivado for Debugging a Design 11 In the Specify Top Module dialog box click Browse f Specify Top Module o Specify the top module name of your design Options Top module name s_compiler_v6_0_viv__parameterized1 lz Co C Figure 50 Browse to the top module 12 In the Select Top Module dialog box select sinegen_demo then click OK gt Select Top Module CT Select a top module from the list Possible top modules dds_compiler_v6_0_xst__parameterized3 idds_compiler_v6_0_xst idds_compiler_v6_0_xst__parameterized1 sinegen sinegen_demo Figure 51 Select the top level module Programming and Debugging www xilinx com UG936 v 2014 2 June 4 2014 49 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 4 Using Synplify Pro Synthesis Tool and Vivado for Debugging a Design 13 Click OK in the Specify Top Module dialog box after ensuring that the top level module is correct gt Specify Top Module rT Specify the top module name of your design Options Top module name sinegen_demo Figure 52 Specify sinege
89. ilinx com 123 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 6 Using Vivado ILA core to Debug JTAG AXI Transactions 6 In the Open Hardware Target Summary page click Finish as shown in the following figure g Open New Hardware Target Open Hardware Target Summary Hardware Server Settings Server localhost 3121 VCSE Server Settings o Server localhost 60001 o Version 20 Target Settings o Target xilinx_tcf Digilent 210203327962A o Frequency 15000000 VIVADOS To connect to the hardware described above click Finish Figure 159 Open Hardware Summary 7 Wait for the connection to the hardware to complete The dialog in the following figure appears while hardware is connecting Open Hardware Target W Opening target Figure 160 Open Hardware Target Programming and Debugging www xilinx com 124 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX Lab 6 Using Vivado ILA core to Debug JTAG AXI Transactions ALL PROGRAMMABLE Once the connection to the hardware target is made the dialog shown in the following figure appears Note The Hardware tab in the Debug view shows the hardware target and XC7K325T device that was detected in the JTAG chain a SB bi a Name 8 localhost 1 Status Connected Ble xilinx_tcf Digilent 210203327962A 1 Open E xc7k325t_O 1 active Not programmed XADC System Monitor
90. ilinx com 28 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 2 Using the HDL Instantiation Method for Debugging a Design in Vivado 4 From the Implementation drop down list expand Implemented Design and select Report Timing Summary 4 Implementation amp Implementation Settings gt Run Implementation 4 H Implemented Design fA Edit Timing Constraints Report Timing Summary Ms Report Clock Networ Figure 23 Report Timing Summary 5 In the Report Timing Summary dialog box Make sure that all timing constraints are met Click OK Aree Re 4 Design Timing Summary l General Information Timer Settings setup Hold Pulse Width a Design Timing Summary Worst Negative Slack WNS 0 981 ns Worst Hold Slack WHS 0 078 ns Worst Pulse Width Slack WPWS 1 732 ng d en e DA A Total Negative Slack TNS 0 000 ns Total Hold Slack THS 0 000 ns Total Pulse Width Negative Slack TPWS 0 000 ns H eck Timing 6 i i HE Intra Clock skia l Number of Failing Endpoints 0 Number of Failing Endpoints 0 Number of Failing Endpoints 0 HA Inter Clock Paths Total Number of Endpoints 3496 Total Number of Endpoints 3496 Total Number of Endpoints 1928 H Other Path Groups HO User Ignored Paths All user specified timing constraints are met H Unconstrained Paths 4 Timing Summary timing_1 x Figure 24 Review Timing Summary 6 Pro
91. ing the bit bitstream file that was created previously by right clicking the XC7K325T device and selecting Program Device as shown in the following figure _ Hardware Manager localhost xilinx_tcf Digilent 210203327962A There are no debug cores Program device Refresh device are sinegen vhd Qs Il Pi gt gt E E C Vivado_Debt F i 164 3a Name Status 165 Ray E localhost 1 Connected GA 166 m a _ Me xilinx_tcf Digilent 210203327962A 1 Open al mm xc7k325t_0 1 active 3 XADC System Monitor 2 Hardware Device Properties Program Device Figure 64 Program Active Target Hardware Programming and Debugging www xilinx com 58 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX Using Vivado Logic Analyzer to Debug Hardware ALL PROGRAMMABLE 10 In the Program Device dialog box verify that the bit file is correct for the lab that you are working on and click Program to program the device as shown in the following figure Program Device 7 Select a bitstream programming file and download it to your hardware device You can optionally select a debug probes file that corresponds to the debug cores contained in the bitstream programming file Bitstream file C Vivado_Debug proj_netlist proj_netlist runs impl_1 sinegen_demo bit Debug Probes file C Vivado_Debug proj_netlist proj_netlist runs impl_1 debug_nets
92. inst U0 gint_inst bmgv81_inst inst_blk_mem_gen gnativ BH Report Clock BL T axi_bram_ctrl_inst U0 gint_inst bmgv81_inst inst_blk_mem _gen gnativ Report DRC CFE Report Noise E Report Utilization Report Power Schematic al sain to select an appropriate clocl I t e Fe J Fd pe Fa F Fo Fa ro a RTL Analysis gt E Open Elaborated Desigi i Synthesis Settings Run Synthesis frm E i E Es H JERE sai irm n uel Jom mi ia iei foji Jo omi baon om i jooh l m elle mno o a m A o m Al ae ax _a add Ta axi_araddr 4 4 Implementation En md mee amp Implementation Setting Debug Cores Debug Nets gt Run Implementation C E Tel Console Messages E Log Reports amp Design Runs Debug Figure 150 Select Clock Domain dialog 27 Observe that all of the nets now have an assigned clock domain Click Next Programming and Debugging www xilinx com 117 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 6 Using Vivado ILA core to Debug JTAG AXI Transactions 28 In the Trigger and Storage Settings page ensure that Advanced Trigger and Capture Control are selected Click Next Set up Debug ILA Integrated Logic Analyzer General Options Sample of Data Depth 1024 Input Pipe Stages 0 Trigger And Storage Settings V Capture Control V Advanced Trigger Figure 151 Trigger
93. ion to select AXI4 Memory Mapped and AXI4 Lite interfaces e User controllable AXI read and write enable e User Selectable AXI datawidth 32 and 64 e User Selectable AXI ID width up to four bits e Vivado logic analyzer Tcl Console interface to interact with hardware Additional Documentation LogiCORE IP JTAG AXI Master v1 0 Product Guide AXI PG174 contains more information the JTAG to AXI Master IP core Programming and Debugging www xilinx com 102 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 6 Using Vivado ILA core to Debug JTAG AXI Transactions Design Description This section has three steps as follows 1 Opening the JTAG to AXI Master IP Example Design project and adding mark_debug to the AXI interface connection Inserting an ILA 3 0 core into the design and configuring it for advanced trigger is also included in this step 2 Programming the KC705 board and interacting with the JTAG to AXI Master IP core 3 Using the ILA 3 0 Advanced Trigger Feature to Trigger on an AXI Read Transaction Step 1 Opening the JTAG to AXI Master IP Example Design and Configuring the AXI Interface Debug Connections To create a project use the New Project wizard to name the project add RTL source files and constraints and specify the target device 1 Invoke the Vivado IDE 2 In the Getting Started screen click Create New Project to start the New Project wizard Click Next 3 In the Projec
94. itstream file to download Note Wait for the program device operation to complete This may take few minutes hw_ila_1 instances in the Hardware Manager window 10 Verify that the JTAG to AXI Master and ILA cores are detected by locating the hw_axi_1 and Hardware Manager localhost linx_tcf Digilent 210203327962A l x mokta Oe Debug Probes O example_jtag_axi_0 v x SRILA hw_ila_1 x ow x X Se ILA Properties Trigger Capture Status eo Name a k hw_ila_1 a localhost 1 Be xlinx_tef Digilent 2102033279624 1 GP hw axi 1 AXT GF hw_ila_i LA XADC System Monitor Hardware Device Properties is axd_araddr 31 0 ia axi_arburst 1 0 ig axd_arcache 3 0 le axi arid t axd_arlen 7 0 te axi_arlock ia axi_arprot 2 0 i axi_argos 3 0 t axi_arready ie axi_arsize 2 0 t axi_arvalid ta axi_awaddr 31 0 Hii TELANE Trigger Mode Settings Trigger mode BASIC_ONLY Capture Mode Settings Capture mode ALWAYS Number of windows 1 Window data depth 1024 Trigger position in window 0 Core status z Waiting for Tr Window 1 of 1 Canture aah Th Window Basic Trigger Setup a Name Pa Compare Value T wn Oe ia axd_awburst 1 0 lel ta a General Settings S ig e axi awi rag and d rop Pdi D ie axi_awlen 7 0 Refresh rate ms 500 ILA probes from gt e axd_awiock Debug Probes name xc7k325t_0 ie axi _awprot 2 0 ida
95. l dialog box the provided XDC file sinegen_demo_kc705 xdc should automatically appear in the main window Click Next 9 In the Default Part dialog box specify the xc7k325tffg900 2 part for the KC705 platform You can also select Boards and then select Kintex 7 KC705 Evaluation Platform Click Next 10 Review the New Project Summary page Verify that the data appears as expected per the steps above and click Finish Note It could take a moment for the project to initialize Step 2 Synthesizing the Design 1 In the Project Manager click Project Settings as shown in the following figure proj_netlist C Vivado_Debug proj_netlist proj_netlistxpr Vivado 2014 1 File Edit Flow Tools Window Layout View Help Ze2 eevRh lt gt DP BB XK E a Z Default Layout Z Flow Navigator amp Project Manager proj_netilist oan Spe Sources E m jae AEA NE a Project Manager amp Project Settings EHE Design Sources 1 ii HAA sinegen_demo Mixed sinegen_demo vhd 4 Project Settings Configure synthesis simulation implementation and IP related options 4 IP Integrator J Create Block Design Figure 2 Configuring the Project Settings Programming and Debugging www xilinx com 13 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 1 Using the Netlist Insertion Method for Debugging a Design 3 In the Project Settings dialog box select Synthesis from the left pane
96. lete Links V Create link group Link group description Link Group SMA Open Serial I O Analyzer layout Figure 121 Create Links dialog box For the first link group call this Link Group SMA as this is the only transceiver channel that is linked through the SMA cables The new link shows up in the Links window RX Status Bits Link Group SMA 1 _ am MGT_XOY8 TX MGT_X0Y8 RX 8 000 Gbps 2 167 Create Links Create serial I O links Figure 122 Create link groups for other transceiver pairs www xilinx com 93 Send Feedback Programming and Debugging UG936 v 2014 2 June 4 2014 amp XILINX ALL PROGRAMMABLE Lab 5 Using Vivado Serial Analyzer to Debug Serial Links Click Create Link again to create link groups for the rest of the transceiver pairs To do this ensure that the transceiver pairs are selected and click the sign icon add new link repeatedly until all the links have been added to the new link group called Link Group Internal Loopback Click OK g Create Links rT To create a new link select a TX and or an RX then press the Add button TX GTS RX GTS Search O Search U New Links Description TX RX Link 2 XC7K325T_0 MGT_X0Y9 RX Device Link 3 XC7K325T_0 MGT_X0Y10 RX Link 4 XC7K325T_0 MGT_XOY11 RX Link 5 XC7K325T_0 MGT_X0Y12 RX Link 6 XC7K325T_0 MGT_XOY13 RX gt Link 7 XC7K325T_0 MGT_XOY14 RX Link 8 XC7K325T_
97. lock Interac Report DRC E Report Utilization kal a axi_araddr 0 Ta ad araddr 1 S Report Power i Ta axi_araddr 2 Schematic Te axi_araddr 3 J axi_araddr 4 4 Implementation p ee radert amp Implementation Setting Debug Cores Debug Nets gt Run Implementation C amp Tcl Console Messages I Log Reports Design Runs Figure 149 Missing Clock Domain dialog 25 In the resulting pop up click Assign All Clock Domains Programming and Debugging www xilinx com 116 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 6 Using Vivado ILA core to Debug JTAG AXI Transactions 26 In the resulting pop up select the aclk clock net then click OK jtag_axi_0 example c jtag_2_axi_tutorial jtag_2_axi_tutorial jtag_axi_0_example jtag_axi_0 example xpr Vivado 2013 4 Ta Exa File Edit Flow Tools Window Layout View Help Q Search commands feb woh xX oP BAG OSG KZ G E Debug Kek Synthesis Complete Flow Navigator Synthesized Design xc7i225tffg900 2 active EEL z a Project Manager Project Settings raf There are 72 net s that do not have a clock domain selection a Add Sources Please select a clock net from the list below to apply to all 72 net s Gp Catalog un If you want to select different clock domains for each net click Cancel and follow the instructions in the wizard a IP Integra
98. mark_debug true get_nets sine This applies the mark_debug on the current open netlist In the following steps you learn how to add debug nets to HDL files and the synthesized design using Vivado IDE 1 In the Flow Navigator under the Synthesis drop down list click Open Synthesized Design as shown in the following figure Properties 4 Synthesis f hay 3 Synthesis Settings gt Run Synthesis a Open Synthesized se Figure 5 Open Synthesized Design Following are some examples alternate methods of adding debug nets using the Vivado IDE o Add mark_debug attribute to the target XDC file set_property mark_debug true get_nets sine IMPORTANT Use these attributes in synthesized designs only Do not use then with pre synthesis or elaborated design netlists Ww Programming and Debugging www xilinx com 16 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 1 Using the Netlist Insertion Method for Debugging a Design o Add mark_debug attribute to HDL files VHDL attribute mark_debug string attribute keep string attribute mark_debug of sine gt Signal is true attribute mark_debug of sineSel signal is true Verilog mark_debug true wire sine mark_debug true wire sineSel o Right click and select Mark Debug or Unmark Debug on Synthesis netlist o Usea Tcl prompt to set the mark_debug attribute For example set mark_debug true get_
99. mp project_3 project_3 xpr Vivado 2013 3 File Edit Flow Tools Window Layout View Help ze ae Rh x lt SDH G xX a E Seria yo Analyze I Flow Navigator x Hardware Manager unconnected gt F oto rao A No hardware target is open Open recent target Open a ne Hardware 4 Project Manager Figure 81 Connect to a new hardware target 3 The Open New Hardware Target wizard opens Click Next 4 In the Hardware Server Settings page type the name of the server or select Local server if the target is on the local machine in the Connect to field 5 Ensure that you are connected to the right target by selecting the target from the Hardware Targets page If there is only one target that target is selected by default Click Next 6 In the Set Hardware Target Properties page click Next 7 In the Open Hardware Target Summary page verify that all the information is correct and click Finish 8 Program the device by selecting and right clicking the device in the Sources window and then selecting Program Device Programming and Debugging www xilinx com 68 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE w Using Vivado Logic Analyzer to Debug Hardware _ Hardware Session localhosi xlinx Digllent 2102033279620 6 There are no gt debug cores Program device Refresh device TIA Name i localhost 1 i aa ae are gilent 21020332796 XC7K3251_0 0
100. n Sinegen_synplify vhd Ssynpliry l sac sinegen_demo_kc7 05 xdc Programming and Debugging www xilinx com UG936 v 2014 2 June 4 2014 Send Feedback 10 amp XILINX ALL PROGRAMMABLE Debugging in Vivado Tutorial Lab 5 Debug high speed serial I O links using the Vivado Serial I O Analyzer This lab uses the Vivado IP example design Lab 6 Using Vivado ILA core to debug JTAG to AXI transactions This lab uses the Vivado IP example design Connecting the Boards and Cables 1 Connect the Digilent cable from the Digilent cable connector to a USB port on your computer 2 Connect the two SMA cables for lab 5 only as follows a Connect one SMA cable from J19 TXP to J17 RXP b Connect the other SMA cable from J20 TXN to J66 RXN The relative locations of SMA cables on the board are shown in Figure 1 KC705 Board Showing Key Components Programming and Debugging www xilinx com 11 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 1 Using the Netlist Insertion Method for Debugging a Design Lab 1 Using the Netlist Insertion Method for Debugging a Design Introduction In this lab you will mark signals for debug in the source HDL as well as the post synthesis netlist Then you will create an ILA core and take the design through implementation Finally you will use Vivado to connect to the KC705 target board and debug your design using Vivado Integrated Logic Analyzer Step
101. n Hardware Manager Launch iMPACT _ Don t show this dialog again Figure 107 Bitstream Generation Completed dialog box 3 The Hardware Manager window appears as shown in the following figure ibert_tutorial C ibert_tutorial ibert_tutorialxpr Vivado 2013 3_EA318433 File Edit Flow Tools Window Layout View Help E 8 CRS Xi gt PEO KFS Ssetyomer JRRD Name BP Open Block Design Cel Generate Block Design 4 Simulation Simulation Settings Run Simulation 4 RTL Analysis E Open Elaborated Design 4 Synthesis Synthesis Settings gt Run Synthesis E Open Synthesized Design sbiadmailalios xc7k32Stffg900 2 active implementation Settings Vivado Synthesis Defaults D gt Run Implementation synth_design Complete E Open Implemented Design Constraints constrs_1 active ex Run directory C ibert_tutorial ibert_tutorial runs synth_1 General Properties Options Log Reports Messages IE Hardware Manager Messages S Launch IMPACT A 323 warnings V 763 infos 272 status _ Show All ms Vivado Commands 17 infos fm open_project C ibert_tutorial ibert_tutorial xpr 3 infos J IP_Flow 19 234 Refreshing IP repositories IP_Flow 19 1704 No user repositories specified IP_Flow 19 2313 Loaded Vivado repository c Xilinx Vivado 2013 3 data ip S connect_hw_server host localhost port 60001 4 infos 9 Lab
102. n_demo as the top level module Step 5 Add more Debug Nets to the Project 1 In Vivado IDE in the Flow Navigator select Open Synthesized Design from the Netlist Analysis folder 2 Select the Netlist tab in the Netlist window to expand Nets Select the following nets for debugging e GPIO BUTTONS _c 2 e sine 20 e sineSel 2 After selecting all the nets mentioned above click Mark Debug Synthesized Design xc7k325tffg900 2 active Ae H GPIO_BUTTONS_re_1 2 GPIO_BUTTONS_re_5 2 LEDS_n 4 f EUERE Bus Net Properties Ctri E a 3 N sine 5 aif sine 6 sine 7 Select Driver Pin sine 8 sine 9 at Feat J we J J J x J J J J Schematic Figure 53 Mark additional signals for debug Programming and Debugging www xilinx com 50 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 4 Using Synplify Pro Synthesis Tool and Vivado for Debugging a Design 3 In the Confirm Debug Net s dialog box click OK 4 You should be able to see all the nets that are marked for debug as shown in the following figure Hame Debug Core Instance Debug Core Type Debug Fort Clock Domain Driver Cell Driver Hame B Assigned Debug Nets E Unassigned Debug Nets 30 EPa GPIO_BUTTONS_c IBUF Multiple S48 GPIO_BUTTONS_db 2 Fi FDE HFa GPIO BUTTONS diy 1 2 FDCE Multiple Es GPIO_BUTTONS_re_1 2 FDCE Multipte HE me sing 2 FORE 2m
103. ncy 2 Correcting Display of the Sine Wave To view the mid and low frequency output sine waves perform the following steps 17 Cycle the sine wave sequential circuit by pressing the GPIO_SW_E push button as shown in the following figure Figure 72 Sine Wave Sequencer Push Button Programming and Debugging www xilinx com 62 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Using Vivado Logic Analyzer to Debug Hardware 18 Click Run Trigger Immediately again to see the new sine selected sine wave You should see the mid frequency as shown in the following figure Notice that the sel signal also changed from 0 to 1 as expected Figure 73 Output Sine Wave Displayed in Analog Format Mid Frequency 19 Repeat step 17 and 18 to view other sine wave outputs Figure 74 Output Sine Wave Displayed in Analog Format Low Frequency Programming and Debugging www xilinx com 63 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Using Vivado Logic Analyzer to Debug Hardware PS rs U_SINEGEN sine 19 0 2J af E GFO BUTTONS IBUF O 0 A GPIO_BUTTONS_IBUF_1 1 1 Figure 75 Output Sine Wave Displayed in Analog Format Mixed Frequency Note As you sequence through the sine wave selections you may notice that the LEDs do not light up in the expected order You will debug this in the next section of this tutorial For now verify
104. ndow again right click and select Radix gt Signed Decimal You should be able to see the sine wave in the Waveform window Ga a Sine 19 0 push_button_vio_ push_button_reset_1 af GPIO_BUTTONS_re 0 0 PROBE_INO_2 2 Si GPIO_BUTTONS_dly 1 0 Figure 86 Sine wave after modifying the properties of the sine 19 0 signal 15 Instead of using the GPIO_SW push button to cycle through each different sine wave output frequency you are going to use the virtual push_button_vio toggle switch from the VIO core Programming and Debugging www xilinx com 70 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Using Vivado Logic Analyzer to Debug Hardware 16 If the Debug Probes window is not open already open it by selecting Window gt Debug Probes from the menu File Edit Flow Tools Window Layout View Help ea A ah x Project Summary Flow Navigator Sources cma DSi IP Catalog 4 Project Manager Language Templates Project Settings Properties Ctri E Add Sources Selection F IP Catalog Hardware 4 IP Integrator Figure 87 Open Debug Probes window The Debug Probes window shows the probes available in the ILA as well as the VIO cores 32 hw_ila_1 wg GPIO_BUTTONS_dly 1 0 4g GPIO_BUTTONS_re 0 0 PROBE_INO_1 1 0 A8 PROBE_INO_2 2 2 le push_button_reset_1 le push_button_vio_1 8 sine 19 0 S hw_vio_1 H S PROBE_INO 3 0
105. ne 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 6 Using Vivado ILA core to Debug JTAG AXI Transactions 13 In the Generate Output Products dialog click Generate f Generate Output Products mm The following output products will be lt generated Preview A G jtag_axi_0 xci a O0 Instantiation Template 0 Synthesized Checkpoint dcp O0 Behavioral Simulation C0 Change Log Figure 141 Generate Output Products dialog 14 The jtag_axi_O IP core is inserted into the design _ Project Manager jtag_2_axi_tutorial lt EA pe Design Sources 1 AFE jtag_axi_0 jtag_axi_0 xci HHS Constraints HA Simulation Sources 1 Hierarchy IP Sources Libraries Compile Order i 25 Templates Figure 142 Generated JTAG to AXI Master IP in the design Programming and Debugging www xilinx com UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 6 Using Vivado ILA core to Debug JTAG AXI Transactions 15 Right click jtag_axi_O and select Open IP Example Design J jtag_2a xi utori 1 C jta 2 axi_tuto jal jtan 2 axi tuto ial j ag_2_axi_tu torial _xpr Vi vado 201 34 Foda File Edit Flow Tools Window Layout View Help Qr Search commands 7 Dja ela hh X gt DP G KE G E Defauk Layout JARE Ready Flow Navigator Project Manager jtag_2_axi_tutorial aX A ia Si Source A _E Project Summary x IP Catalog x ov a
106. nets sine This applies the mark_debug on the current open netlist TIP Before proceeding make sure that the Flow Navigator on the left panel is enabled Use Ctrl Q to toggle it off and on 2 Inthe Window menu select Layout gt Debug When the Debug window opens Click the window if it is not already selected 3 Expand Unassigned Debug Nets folder The following figure shows those debug nets that were tagged in sinegen_demo vhd with mark_debug attributes as shown in Figure 7 attribute mark_debug string attribute mark_debug GPIO BUTTONS db signal is true attribute mark_debug GPIO BUTTONS dly signal is true attribute mark debug of GPIO BUTTONS re signal is true component sinegen port clk in reset in std logic sel in std_logic vector 1 downto 0 sine out std logic vector 19 downto 0 l end component Figure 6 VHDL Example Using MARK_DEBUG Attributes Programming and Debugging www xilinx com 17 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 1 Using the Netlist Insertion Method for Debugging a Design ame Driver Cell N E Unassigned Debug Nets 6 EH GPIO_BUTTONS_db 2 FDRE T amp GPIO_BUTTONS_db 0 FDRE Si GPIO_BUTTONS_db 1 FDRE c GPIO_BUTTONS_dly 2 FDRE J GPIO_BUTTONS_dly 0 FDRE J GPIO_BUTTONS_dly 1 FDRE Ehia GPIO_BUTTONS_re 2 FDRE T GPIO_BUTTONS_re 0 FDRE JS GPIO_BUTTONS_ref 1 FDRE Debug C
107. nplify Pro and select File gt New Set File Type to Project File Project as highlighted in the following figure In the New File Name box enter synplify_1 Click OK Ej New Y amp File Type Select a type i Verilog File VHDL File 7 Tcl Script Cancel Identify Design Constraint a 4 Text File Xilinx Options File E FPGA Design Constraints a Analysis Design Constraints P Project File Project New File Name synplify_1 File Location Help C Vivado_Debug synopsys Full Path C Vivado_Debug synopsys synplify_1 prj Figure 37 Synplify Pro New Project Dialog Box Programming and Debugging www xilinx com 38 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 4 Using Synplify Pro Synthesis Tool and Vivado for Debugging a Design 2 If you get a dialog box asking you to create a non existing directory click OK Synplify Pro The directory C tutorials ug936 does not exist Do you wish to create it A Figure 38 Synplify Pro project confirmation dialog box 3 In the left panel of the Synplify Pro window click Add File as shown in the following figure S sy Synplify Pro I 2013 09 1 C Nivado_ Debug synopsys synplify_1 prj LA File Edit View Project Import Run Analysis HDL Analyst Options Window Teci B amp Bw wis PAM M OVE BYIH Se 2 He BRA Sela BoB BR ws Ready WD Openrrojec __ _ProjectFiles L Design Hierarchy W
108. nplify_1 rev_1 EDES Device Options Constraints Implementation Results Timing Report High Reliability VHD 4 gt Implementations Technology Part Package Speed rev_1 Xilinx Kintex7 XC7K325T x FFG900 x 2 x Device Mapping Options Option Fanout Guide Disable I O Insertion Value 10000 Disable Sequential Optimizations Update Compile Point Timing Data Click on an option for description System Designer Board File Figure 44 Specifying Implementation Options in Synplify Pro Programming and Debugging www xilinx com 43 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 4 Using Synplify Pro Synthesis Tool and Vivado for Debugging a Design 10 You need to preserve the net names that you want to debug by putting attributes in the HDL files These attributes are already placed in the sinegen_demo vhd file of this tutorial Open the sinegen_demo vhd file and inspect the lines shown Attributes for Synplify Pro attribute syn_keep boolean attribute syn_keep of GPIO BUTTONS db Signal is true attribute syn _ keep of GPIO BUTTONS dly Signal is true attribute syn_keep of GPIO_BUTTONS_re Signal is true Figure 45 Specifying attributes to preserve net names in Synplify 11 You also can specify the mark_debug attributes in the source HDL files to mark the signals for debug as shown in the snippet code from singen_demo vhd file Add mark_
109. obes O vx et a eE Name 8 axi_araddr 31 0 E E localhost 1 Connect ie axi_arburst 1 0 le xilinx_tcf Digilent 210203327962A 1 Open te axi_arcache 3 0 E xc7k325t_O 2 active Program le axi_arid hw axi l t axi_arlen 7 0 wate emi enre iT Ctri E Run Trigger Stop Trigger 0 Run Trigger Immediate 31 0 Open Dashboard e 3 0 Export to Spreadsheet te axi_awlock t axi_awprot 2 0 t axi_awqos 3 0 le axi_awready t8 axi_awsize 2 0 Figure 169 Run Trigger Programming and Debugging www xilinx com 131 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 6 Using Vivado ILA core to Debug JTAG AXI Transactions 8 In the Trigger Capture Status window note that the ILA core is waiting for the trigger to occur and that the trigger state machine is in the wait_for_a_valid state Note that the pre trigger capture of 512 samples has completed successfully Trigger Capture Status 2 O Core status Idle FPre Trigger F Trigger State Machine Flags Flag 0 0 Flag 1 0 Flag 2 0 Flag 3 0 Trigger state wait_for_arvalid 0 Window 1 of 1 Window sample 512 of 1024 Total sample 512 of 1024 Capture status 00 rs E e J E a ri iT Figure 167 Trigger Capture Status window 9 In the Tcl console run the read transaction that you set up in the previous section of this tutorial run_hw_axi Srt Note The ILA core has triggered and
110. ores Debug Nets a T e Fri 2 Figure 7 Unassigned Debug Nets Post synthesis 4 Select the Netlist tab and expand Nets Select the following nets for debugging shown in the following figure o GPIO_BUTTONS_IBUF 0 and GPIO_BUTTONS_IBUF 1 Nets folder under the top level hierarchy o sel 2 Nets folder under the U_SINEGEN hierarchy o sine 20 Nets folder under the U_SINEGEN hierarchy Programming and Debugging www xilinx com 18 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 1 Using the Netlist Insertion Method for Debugging a Design x ri 7 sinegen_demo EHS Nets 60 GPIO_BUTTONS 2 H GPIO_BUTTONS_db 2 H k GPIO_BUTTONS_dly 2 P GPIO_BUTTONS_re 2 H LEDS_n 4 lt const0 gt lt constl gt clk CLK_N CLK_P DONT_EATO DONT_EAT1 DONT_EAT2 DONT_EAT3 DONT_EAT4 DONT_EATOO DONT_EATOO_out DONT_EAT10 DONT_EAT20 DONT_EAT30 DONT_EAT40 GPIO_BUTTONS_IBUF 0 GPIO_BUTTONS_IBUF 1 GPIO_SWITCH J J J J fi J J T J J J J J J ir J J Figure 8 Add nets for debug from the synthesized netlist Note These signals represent the significant behavior of this design and are used to verify and debug the design in subsequent steps Programming and Debugging www xilinx com 19 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 1 Using the Netlist Insertion Method for Debugging a Design 6
111. ow xci e sine mid xci e sinegen_demo_kc7 05 xdc Lab2 This lab goes over the details of marking nets for debug in the source HDL HDL instantiation method as well as instantiating an ILA core in the HDL Following are the required files e debounce vhd e fsm vhd Pee COl e sinegen vhd e sinegen_demo_inst vhd e ila_0 xci e sine_high xci e sine low xci Programming and Debugging www xilinx com 9 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Debugging in Vivado Tutorial Sine mid xci Sinegen_demo_kc7 705 xdc Lab 3 You can test your design even if the hardware is not physically accessible using a VIO core This lab will walk you over the steps of instantiating and customizing a VIO core that you will hook to the I Os of the design Following are the required files debounce vhd fsm vnd Sinegen vhd Sinegen_demo_inst_vio vhd Sine_high xci Sine_low xci Sine_mid xci ila 03 3C 1 Sinegen_demo_kc7 05 xdc Lab 4 Nets can also be marked for debug in a third party synthesis tool using directives for the synthesis tool This lab walks you through the steps of marking nets for debug in the Synplify tool and then using Vivado to perform the rest of the debug Following are the required files dds_compiler_v6_0O_viv edn dds_compiler_v6_0_viv_parameterizedl edn dds_compiler_v6_0_viv_parameterized3 edn debounce vhd fsm vhd Ssine_high xci1 Sine low xcl1 Sine mid xci Sinegen ed
112. re B localhost 1 l lt XC7K325T_0 1 active Pro hw_ila_1 O Idle Figure 68 Run Trigger Immediate Button Programming and Debugging www xilinx com 60 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Using Vivado Logic Analyzer to Debug Hardware 14 In the Waveform window verify that there is activity on the 20 bit sine signal as shown in the following figure Baers Peak Figure 69 Output Sine Wave Displayed in Digital Format Displaying the Sine Wave 15 Right click U_SINEGEN sine 19 0 signals and select Waveform Style gt Analog as shown in the following figure TIP The waveform does not look like a sine wave This is because you must change the radix setting from Hex to Signed Decimal as described in the following subsection MA GPIO_BUTTONS_IBUF 0 0 Mi GPIO_BUTTONS_IBUF_1 1 1 Figure 70 Output Sine Wave Displayed in Analog Format High Frequency 1 Programming and Debugging www xilinx com 61 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Using Vivado Logic Analyzer to Debug Hardware 16 Right click U_LSINEGEN sine 19 0 signals and select Radix gt Signed Decimal You should now be able to see the high frequency sine wave as shown in the following figure instead of the square wave GPIO_BUTTONS_IBUF 0 0 GPIO_BUTTONS_IBUF_1 1 1 Figure 71 Output Sine Wave Displayed in Analog Format High Freque
113. re 9 Adding Nets from the Netlist Tab Ctrl E F4 Ctri T F6 Ctrl M TIP In the Debug window you can see the unassigned nets you just selected In the Netlist window you can also see the green bug icon next to each scalar or bus which indicates that a net has the attribute mark_debug true as shown the following two figures Programming and Debugging UG936 v 2014 2 June 4 2014 www xilinx com 20 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 1 Using the Netlist Insertion Method for Debugging a Design Name Unassigned Debug Nets 30 i GPIO_BUTTONS_db 2 J GPIO_BUTTONS_db 0 J GPIO_BUTTONS_db 1 are GPIO_BUTTONS_dly 2 Sa GPIO_BUTTONS_dly 0 _S GPIO_BUTTONS_dly 1 2j a GPIO_BUTTONS_re 2 i GPIO_BUTTONS_re 0 Ti GPIO_BUTTONS_re 1 U SINEGEN sel 2 U_SINEGEN sine 20 GPIO_BUTTONS_IBUF 0 GPIO_BUTTONS_IBUF 1 Debug Cores Debug Nets Figure 10 Newly added nets for debug from the synthesized netlist 7 a5 DONT_EAT2 ry DONT_EAT3 J DONT_EAT4 J DONT_EATOO T DONT_EATOO_out DONT_EAT10 J DONT_EAT20 J DONT_EAT30 J DONT_EAT40 See 3GPIO BUTTONS _IBUF O mee 3GPIO BUTTONS IBUF 1 GPIO_SWITCH GPIO_SWITCH_IBUF seJ I J n_0_DONT_EAT_reg J n_0_GPIO_BUTTONS_dly 0 _i_1 n_0_GPIO_BUTTONS_dly 1 _i_1 J n_0_GPIO_BUTTONS_re 0 _i_1 J n_0_GPIO_BUTTONS_re 1 _i_1 J n_0_U_FSM n_1_U_FSM J n_3_U_SINEGEN J n_4_U_SINEGEN HJ n_8_U_SINEGEN oJ n
114. rtex7 vc709 1 0 xc7vx690tffi E ZYNQ 7 ZC702 Evaluation Board xilinx com zynq zc702 1 0 xc7z020clg _ E iiias 7C706_Fvaluation Roard viliny com 7vna 7c7N6 1 1 amp we77N45ffnac 4 Wi j Figure 136 Choosing the Kintex 7 KC705 Evaluation Platform board Programming and Debugging www xilinx com 104 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 6 Using Vivado ILA core to Debug JTAG AXI Transactions 9 In the New Project Summary page click Finish g New Project New Project Summary A new RTL project named jtag_2_axi_tutorial will be created No source files or directories will be added Use Add Sources to add them later A No Configurable IP files will be added Use Add Sources to add them later No constraints files will be added Use Add Sources to add them later Q The default part and product family for the new project Default Board Kintex 7 KC705 Evaluation Platform Default Part xc7k325tffqg900 2 Product Kintex 7 Family Kintex 7 Package ffq900 Speed Grade 2 VIVADO To create the project click Finish Figure 137 New Project Summary Programming and Debugging www xilinx com 105 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 6 Using Vivado ILA core to Debug JTAG AXI Transactions 10 In the leftmost panel of the Flow Navigator under Project Manager click IP Catalog jtag_2_axi_tutorial C jtag_2_axi_tutor
115. s window if not already open by selecting Window gt Debug Probes from the menu 2 In the ILA Properties window scroll down to the link marked To view editable ILA Properties Open ILA Dashboard and set the following a Trigger Mode to BASIC_ONLY b Capture Mode to BASIC c Window Data Depth to 1024 d Trigger position to 512 e Drag and drop the GPIO_ BUTTONS IBUF_1 1 1 bit from the Debug Probes window in the Basic Trigger Setup dialog box to the Name field Change the Compare Value field to R by clicking in the Compare Value column and typing the value R in the Value field as shown in the following figure Programming and Debugging www xilinx com 65 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Using Vivado Logic Analyzer to Debug Hardware U ILA Properties Trigger Capture Status oi Trigger Mode Settings Basic Trigger Setup Trigger mode BASIC s Name Compare Value Capture Mode Settings Basic Capture Setup s wi Capture mode BASIC Name Compare Value Data depth 1024 a Trigger position 512 0 1023 Figure 77 Setting Trigger Conditions CAUTION For different labs the GPIO_LBUTTONS_IBUF may show up differently This may show up as two individual bits or two bits lumped together in a bus Ensure that you are using bit 1 of this bus to set up your trigger condition For example in case of a two bit bus you will set the Value field in the Compare Val
116. seccccesecceeeecceceesececeeneceeseeceeeaeeeeeeas 12 INV OCC UNO a EE E E ES E E nay E E E E E E A 12 Step 1 Creating a Project with the Vivado New Project WiIZard ccccceeccccsescccsecsceeececeneceeeueeseueceseueceeeueseeensss 12 sa Sys LAU Asks 4 a cad gael DESE iesi a ee ee ee 13 Step 3 Probing and Adding Debug IP ceeccccssseccccseccecenscceceesececeuececeenecceeeesecessuneceesenscesseeeeetsusecessenecetteges 15 Pacing Debug NETS CO Cie POI SCC serine E EEE 15 RUNAING the Set Up Debug Wizardse nE E E EE 22 Step 4 Implementing and Generating Bitstream ccceccccsecccesecscenececeneccesesceueceeeeceeeeceeeueeseueceseueceneueseeensss 24 Lab 2 Using the HDL Instantiation Method for Debugging a Design in ViIVACO ccccsseccceesseceeeeseceeeeeeeeeeeeseeeees 26 ITF OCCU OI eae sae ectteterrneciag E E E E E E E E E 26 Step 1 Creating a Project with the Vivado New Project Wizard esssssssesssesressrsnesrrsrrrsrrresrrrsrrrssrresrersrrreerresns 26 Step 2 Synthesize Implement and Generate Bitstream cccccccccccsseccceecccesecceececeecseenecseeueeeeueceseueceneueseneness 28 Lab 3 Using a VIO Core for Debugging a Design in Vivado ccccceeseccccessececeesececceececeeeeccessusececsenecessuneeeesaeeeeetas 30 IOC arrears esters E oe sane ce eusGoeumcenends seuss meeseneneytesaresuentacudubeseucenoneese tei eevasaeae 30 Step 1 Creating a Project with the Vivado New Project WiIZard ccccccescccescccese
117. sineSel 2 FOCE Debug Nets Debug Cores Figure 54 Nets added for debug through the Synplify Pro Flow in Vivado IDE Running the Set up Debug Wizard 5 Click the Set up Debug icon in the Debug window or select the Tools menu and select Set up Debug The Set up Debug wizard opens Name O Assigned Debug Nets Unassigned Debug Nets 30 E G GPIO_BUTTONS _c 2 a i GPIO_BUTTONS_db 2 EN H GPIO_BUTTONS_dly_1 2 Set up Debug Launch wizard for choosing nets and connecting them to debug cores Debug Nets Debug Cores Tcl Console Messages Sl Log Reports Design Runs Figure 55 Run the Set up Debug wizard 6 Click through the wizard to create Vivado logic analyzer debug cores keeping the default settings Note In the Specify Nets to Debug dialog box ensure that all the nets marked for debug have the same clock domain Programming and Debugging www xilinx com 51 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 4 Using Synplify Pro Synthesis Tool and Vivado for Debugging a Design Step 6 Implementing the Design and Generating the Bitstream 1 In the Flow Navigator under the Program and Debug drop down list click Generate Bitstream 2 In the Save Project dialog box click Save 3 When the Bitstream generation finishes the Bitstream Generation Completed dialog box pops up and Open Implemented Design is selected by default Click OK 4 If you get
118. software to monitor and change any attribute in any of the GTX transceivers included in the IBERT core When applicable readable and writable registers are also included These are connected to the ports of the GTX transceiver All are accessible at run time using the Vivado Logic Analyzer tool e Pattern Generator Each GTX transceiver enabled in the IBERT design has both a pattern generator and a pattern checker The pattern generator sends data out through the transmitter e Error Detector Each GTX transceiver enabled in the IBERT design has both a pattern generator and a pattern checker The pattern checker takes the data coming in through the receiver and checks it against an internally generated pattern on m Interface Pattern TxN TxP Tx ome Generator External Serial Kintex 7 GTX Loopback via Transceiver SMA Cables Error RxN RxP Detector GTX Port Detector Pons Figure 96 IBERT Design Flow Step 1 Creating Customizing and Generating an IBERT Design To create a project use the New Project wizard to name the project to add RTL source files and constraints and to specify the target device Programming and Debugging www xilinx com 77 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 5 Using Vivado Serial Analyzer to Debug Serial Links 1 Invoke the Vivado IDE 2 In the Getting Started screen click Create New Project to start the New Project wizard Click Next
119. synplify_1 sd Figure 48 Synthesize the design in Synplify 3 During synthesis status messages appear in the Tcl Script tab Warning messages are expected but there should not be any Error messages To see detailed messages click the Messages tab in the bottom left hand corner of the Synplify Pro console Programming and Debugging www xilinx com 45 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 4 Using Synplify Pro Synthesis Tool and Vivado for Debugging a Design 4 When synthesis completes the output netlist is written to the file rev_l sinegen_demo edf Optional To view the netlist select View gt View Result File 5 Click File gt Save All to save the project then click File gt Exit Step 3 Create EDIF Netlists for the Black Box Created in Synplify Pro The black box sinegen created in the Synplify Pro project contains the Direct Digital Synthesizer IP You need to create a synthesized design for this block To do this create an RTL type project in Vivado IDE by following the steps outlined below 1 Launch Vivado IDE Click Create New Project This opens up the New Project wizard Click Next Under Project Name set the project name to proj_synplify_netlist Click Next Under Project Type select RTL Project Click Next PE oe US Under Add Sources click Add Files navigate to the Vivado_Debug src Lab4 folder and select the sinegen vhd file Set Target Langua
120. t This wizard will guide you through connecting to a hardware target To connect to a remote hardware target provide the host name and IP port of the remote machine on which the instance of a Vivado Hardware Server is running VIVADO To continue click Next Figure 110 Open New Hardware Target wizard Programming and Debugging www xilinx com 86 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 5 Using Vivado Serial Analyzer to Debug Serial Links 2 Inthe Connect to field choose Local server Click Next g Open New Hardware Target 83 Hardware Server Settings Select local or remote hardware server then configure the host name and port settings Use Local server if the target is attached to the local machine otherwise use Remote server Connect to Local server target is on local machine Click Next to launch and or connect to the vcse_server port 60001 and hw_server port 3121 applications on the local machine Figure 111 Vivado CSE Server Name page Programming and Debugging www xilinx com 87 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 5 Using Vivado Serial Analyzer to Debug Serial Links 3 In the Select Hardware Target page click Next There is only one target board in this case to connect to so the default is selected gt Open New Hardware Target Select Hardware Target Select a hardware target from
121. t of the read address phase of the AXI transaction which is indicated by the axi_arvalid signal equal to 1 state wait for _arvalid if axi_arvalid 1 bl then goto wait_for_rready else goto waltl_Tor arvalid endif The wait_for_rready state is used to detect the start of the read data phase of the AXI transaction which is indicated by the axi_rready signal equal to 1 state wait_for_rready if axi_rready 1 bl then goto wait_for_rlast else goto wait_for_rready endif Programming and Debugging www xilinx com 130 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 6 Using Vivado ILA core to Debug JTAG AXI Transactions The wait_for_rlast state is used to detect the end of the read data phase of the AXI transaction which is indicated by the axi_rlast signal equal to l Once the end of the data phase is detected the ILA core will trigger H HHH H state wait for rlasrt if axi_rlast 1 bl then trigger else goto wait_for_rlast endif Note The state machine ts used to detect the various phases of an AXI read transaction Beginning of the read address phase Beginning of the read data phase End of the read data phase 7 Arm the trigger of the ILA by right clicking the hw_ila_1 core in the Hardware Manager window and selecting Run Trigger _ Hardware Manager localhost xilinx_tcf Digilent 210203327962A Hardware G A 8 Debug Pr
122. t iabtools_xsdbslavelib_v2 TE Rene fh Unassigned Debug Nets 202 RepOT Mosa E ia axi_araddr 32 E Report Utilization J axi_araddr 0 T2 ai_araddr 1 Report Power a amp Repo T axi_araddr 2 J axd_araddr 4 a Implementation wb iddes amp Implementation Setting Debug Cores Debug Nets gt Run Implementation C i Std Console Messages Gi Log 4 Reports amp amp Design Runs Debug Figure 147 Debug window in the Vivado IDE Programming and Debugging www xilinx com 114 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 6 Using Vivado ILA core to Debug JTAG AXI Transactions c Click the Set up Debug toolbar button to launch the Set up Debug wizard jtag_axi_0example c tag_2_axi_tutorial jtag_2_axi_tutorial jtag_axi_0_example jtag_axi_O_example xpr Vivado 2013 4 File Edit Flow Tools Window Layout View Help E d fea mvRh xX 49 PB HgO ARIE g E Debug Ze Synthesis Complete Flow Navigator Synthesized Design xc7k325tffg900 2 active x po a E Netlist O A X Schematic example_jtag_axi_O v x ow x ile s amp cels 2VOPorts 266 Nets GI example_jtag_axi_0 He Nets 266 BF Add Sources i LF IP Catalog amp Set up Debug a Project Manager Project Settings a IP Integrator Set up Debug Cronte POCE Desi This wizard will guide you through the process of choosing nets and B
123. t Name page name the new project jtag_2_axi_tutorial and provide the project location C jtag_2_axi_tutorial Ensure that Create Project Subdirectory is selected Click Next In the Project Type page specify the Type of Project to create as RTL Project Click Next In the Add Sources page click Next In the Add Existing IP page click Next Se In the Add Constraints page click Next Programming and Debugging www xilinx com 103 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 6 Using Vivado ILA core to Debug JTAG AXI Transactions 8 In the Default Part page choose Boards and choose the Kintex 7 KC705 Evaluation Platform Click Next New Project Default Part Choose a default Xilinx part or board for your project This can be changed later Specify Filter Parts Board Vendor All Wy Boards Library All Name All Version Latest Reset All Filters Search Q Board Board Board Board Board Part Vendor Library Name Version MicroZed Board em avnet com zynq microzed xc7z010cla a ZedBoard Zyng Evaluation and Development Kit em avnet com zynq zed d xc7z020clg Artix 7 AC701 Evaluation Platform xilinx com artix7 ac701 1 0 amp xc7a200tfbc _Kintex 7 KC705 Evaluation Platform xilinx com___ kintex7_ kc705_ ft E gi Virtex 7 VC707 Evaluation Platform xilinx com virtex7 vc707 1 1 xc7vx485tffi Virtex 7 VC709 Evaluation Platform xilinx com _ vi
124. t http www xilinx com legal htm tos Copyright 2014 Xilinx Inc Xilinx the Xilinx logo Artix ISE Kintex Spartan Virtex Zyng and other designated brands included herein are trademarks of Xilinx in the United States and other countries All other trademarks are the property of their respective owners Programming and Debugging www xilinx com ena Eo edia 133 UG936 v 2014 2 June 4 2014
125. te Leaf Cells 3 Save AS New Layo ut H j 1 in A LF IP Catalog i ea ihe aa Reset Layout F5 P Integrator Li ey jtag_asd_full_inst jiaq_ J Create Block Design pe Dis d ry ia g sian nen Block Desi Hf HERCK AC PIL a Ge nerate Black Design a Simulation Simulation Settings i Run Simulation amp Sources J Netlist Propert Ax a RTL Analysis 2 R 7 Bus H Open Elaborated Desig F 4 Synthesis G Synthesis Settings gt Run Synthesis a H Synthesized Design A Edit Timing Constrai g Report Timing Sumi Ta Console etal INEU Upt 31 138 Pushed 0 inverters 2 An lock H oa F Shut AEE COCE NENO pas INFO Memdata 26 144 Successfully populated the BRAM INIT atrings from the following elf files at Report Clock Interac INFO Project 1 111 Unisim Transformation Summary Report DRC A total of 212 instances were transformed re he Report Noise fel RAMJZM gt RANM32M RABDSY RAMDGZ RAHD32 BRAMDS2Z RAMDSZ RAMDGZ RAMSS2Z RAMSS2 20 instances a oh BAMG4M gt RAMGdM RAMDG4E RAMDG4E RAHDG4E RAMDG4E 160 instances B Report Utilization E RAM64XiD gt RAMG4X1D RAMD64E RAMD64E 32 instances ay Report Power Xi ti Schematic open run Time 3 cpu 00 00 44 elapsed 00 00 31 Memory MB peak 1871 711 gain 976 688 7 a implementation K Li j implementation Setting gt Run Implementation E J Tcl Console Messages Gf Log Reports Design Runs Figure 146 De
126. the trigger mark is on the sample where the axi_rlast signal is equal to 1 just as the trigger state machine program intended example_jtag_axi_0 v x ILA hw_ila_1 x hw_ila_data_l wcfg x Ow x Eg axi_rdata 31 0 a ES axi_arprot 2 0 few Ea axi_arcache 3 0 A axi_arburst 1 0 MA axi_arsize 2 0 Iq MA axi_arlen 7 0 7f d axi_araddr 31 0 oo000000 2 tT D oopoooo0 cp axi_bresp 1 0 0 iad ES axi_wstrb 3 0 f af axi_wdata 31 0 00000000 ra axi_awprot 2 0 E axi_awcache 3 0 axi_awburst 1 0 S E A axi_awsize 2 0 2 P axi_awaddr 31 0 00000000 OF HHL axi_awlen 7 0 00 axi_arid h axi_arlock h axi_arready h axi_arvalid ih axi_awid i axi_awlock i axi_awready l axi_avwvalid h axi_bid l axi_bready i axi_bvalid i axi_rid l axi_rlast h axi_rready axi_rvalid Figure 170 Waveform window Programming and Debugging www xilinx com 132 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Legal Notices Please Read Important Legal Notices The information disclosed to you hereunder the Materials is provided solely for the selection and use of Xilinx products To the maximum extent permitted by applicable law 1 Materials are made available AS IS and with all faults Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS EXPRESS IMPLIED OR STATUTORY INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY NON INFRINGEME
127. tools 27 147 vese_server Connecting to hw_server Labtools 27 147 vcse_server Connection established Labtools 27 147 vcse_server Connecting to hw_server A Lahtnals 27 147 urse server Cannectinn estahliched E Td Console Messages Figure 108 Hardware Manager Window Programming and Debugging www xilinx com 85 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 5 Using Vivado Serial Analyzer to Debug Serial Links Step 4 Interact with the IBERT core using Serial I O Analyzer In this tutorial step you connect to the KC705 target board program the bitstream created in the previous step and use the Serial I O Analyzer to interact with the IBERT design that you created in Step 1 You perform some analysis using various input patterns and loopback modes while observing the bit error count ibert tutorial C ibert_tutorial ibert tutorialxpr Vivado 2013 3 EA318433 File Edit Flow fools Window Layout View Help Te nAaR x gt bP WB 6 X E S E seria yo Anaye MW amp Flow Navigator Hardware Manager localhost xilinx_tcf Xilinx Port_ 0004 Hub_ 0004 A pd tao Og No hardware target is open Open recent target Open a new hardware 4 Project Manager Figure 109 Open a new hardware target 1 Click Open a new hardware target When the Open New Hardware Target wizard opens click Next Open New Hardware Target Open Hardware Targe
128. tor T Find Results 34 amp Create Block Design IET BP Open Block Design i S Generate Block Design pach T axi_aclk ei E a T axi_bram_ctri_inst s_axi_ack 4 Simulation are T axi_bram_ctri_inst U0 gint_inst abev3_0_int_inst GEN_AXH I_FULL_AX aa amp Simulation Settings T axi_bram_ctri_inst U0 gint_inst abov3 0 int inst GEN AXI FULL_AX Run Simulation T axi_bram_ctrl_inst U0 gint_inst abcv3_0_int_inst GEN_AXI4 1_FULL_AX T axi_bram_ctrl_inst U0 gint_inst abev3_0_int_inst GEN_AXI4 1_FULL_AX _ T axi_bram_ctrl_inst U0 gint_inst abev3_0_int_inst GEN_AXI4 1_FULL_Ax fove Nets X button T axi_bram_ctrl_inst U0 gint_inst abev3_0_int_inst GEN_AXH I_FULL_AX JT axi_bram_ctrl_inst U0 gint_inst abcv3_0_int_inst s_axi_aclk I axi_bram_ctrl_inst U0 gint_inst bmgv81_inst inst_blk_mem_gen gnativ T axi_bram_ctrl_inst U0 gint_inst bmgv81_inst inst_blk_mem_gen gnativ T axi_bram_ctri_inst UO gint_inst bmgv81_inst inst_blk_mem_gen gnativ J axi_bram_ctri_inst U0 gint_inst bmgqv81_inst inst_blk_mem_gen gnativ T axi_bram_ctrl_inst U0 gint_inst bmgv61_inst inst_blk_mem_gen gnativ a Synthesized Design T axi_bram_ctri_inst U0 gint_inst bmgv81_inst inst_blk_mem_gen gnativ ae J axi_bram_ctrl_inst UO gint_inst bmgv81_inst inst_blk_mem_gen gnativ a Edit Timing Sa T axi A ce AONA bea brews PANA BIE ma avert Report Timing sumt we T axi_bram_ctri_inst U0 gint_inst bmqv 1_inst inst_blk_mem_gen gnativ W Report Clock Netwoi T axi_bram_ctri_
129. torial jtag_axi_0_example jtag_axi_0_examplexpr Vivado 2013 4 ala 3 File Edit Flow Tools Window Layout View Help Qr Search commands f eCR oeRhx gt p NHG OSRE G Boeng JERE Synthesis Complete Flow Navigator Synthesized Design xc7k325tffg900 2 active x A om ie Netlist Oe A Schematic x example jtag axiOv x ae 4 Project Manager om Pil DI example_jtag_axi_0 G Project Settings HE Nets 266 B7 Add Sources TE P Catalog amp Set up Debug Specify Nets to Debug Specify Nets for debugging a IP Integrator J Create Block Design BF Open Block Design Tb Generate Block Design Some net s do not have a clock domain more info 4 Simulation Missing Clock Domain E e axi_araddr 32 amp Simulation Settings ea cH Te ax arburst 2 72 nets do not have a clock domain selection GQ Run Simulation Fl Ha axia reache 4 Please right click the nets and choose Select Clock Domain to select an appropriate clocl e Ie axt_arlen 8 or remove the nets from the table below using the Remove Nets X button 4 RTL Analysis 7 Efa axi_arprot 3 ia Open Elaborated Desigr ks vs seg 4 7 H Ta axi_awaddr 32 _4 Synthesis t 4 axi_awburst 2 Synthesis Settings CH axi_awcache 4 gt Run Synthesis Ce dt axi_awlen 8 E S axi_awprot 3 a H Synthesized Design Hra sap 4 fA Edit Timing Constrai ee Efi mui maura Report Timing Sumi Mp Report Clock Netwot Report C
130. ts tab set Probe Width to 4 bits wide F Customize IP VIO Virtual Input Output 3 0 Documentation IP Location CJ Switch to Defaults Show disabled ports Component Name To confiqure more than 64 probe ports use Vivado Tcl Console _ General Options PROBE_IN Ports 0 0 PROBE_OUT Ports 0 0 cl obe_outo 0 0 probe inof3 o h oN tO 0 PROBE_INO 4 Programming and Debugging www xilinx com 33 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 3 Using a VIO Core for Debugging a Design in Vivado 15 On the PROBE OUT Ports set Probe Width to 2 bits wide with an initial value of 0 in hex format F Customize IP VIO Virtual Input Output 3 0 it Documentation 5 IP Location C3 Switch to Defaults _ Show disabled ports Component Name To configure more than 64 probe ports use Vivado Tcl Console General Options PROBE_IN Ports 0 0 PROBE_OUT Ports 0 0 F Initial Value in r utO i Probe Port Probe Width probe inof3 0 obe_out0 1 0 hex PROBE_OUTO 2 1 256 Ox0 Figure 29 Configure the PROBE_OUT Ports of the VIO core 16 Click OK to generate the IP The Generate Output Products dialog box will appear Click Generate g Generate Output Products OG j i The following output products will be generated Generate Options Generate Synthesized Checkpoint dcp Preview A EFF vio_0 xci Instantiation
131. ue dialog box to RX CAUTION The ILA properties window may look slightly different for different labs 9 Select the hw_ila_data_1 wcfg tab or the waveform tab Source the rt tc1 file in the Tcl Console by typing source rt tcl This Tcl command performs the following tasks e Arms the trigger e Waits for the trigger e Uploads and displays waveforms 4 On the KC705 board press the Sine Wave Sequencer button until you see multiple transitions on the GPIO_BUTTONS _1_IBUF signal this could take 10 or more tries This is a visualization of the glitch that occurs on the input An example of the glitch is shown in the following two figures CAUTION You may have to repeat steps 3 and 4 repeatedly to see the glitch Once you can see the glitch you may observe signal glitches are not at exactly the same location as shown tn the figure below Programming and Debugging www xilinx com 66 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Using Vivado Logic Analyzer to Debug Hardware hw _ila_data_1 wecig H Hame Value i MA GPIO_BUTTONS_dhy 1 0 ie GPIO_BUTTONS_db 1 0 Figure 78 GPIO_BUTTONS _BUF1 Signal Glitch hw _ila_data_1 wecfg L ars of E U_SINEGEN sel 1 0 oe 4 GPIO_BUTTONS_re 1 0 oe ia GPIO_BUTTONS_dly 1 0 ay E e GPIO_BUTTONS_db 1 0 a es my Figure 79 GPIO Buttons_1_re Signal Glitch magnified Fixing the Signal Glitch and Verifying the Correct State M
132. umber of quads available for this device is 4 Number of Protocols 1 b Protocol LineRate Gbps DataWidth Refdlk MHz Quad Count Quad PLL Figure 99 Setting the Protocol Definition on the IBERT Core 5 Under the Protocol Selection tab update the following selections a For GTX Location QUAD_117 in the Protocol Selected column click the pull down menu and select Custom 1 8 Gbps This should automatically populate Refclk Selection to MGTREFCLKO 117 and TXUSRCLK Source to Channel 0 b For GTX Location QUAD_118 do the following i In the Protocol Selected column click the pull down menu and select Custom 1 8 Gbps il In the Refclk Selection column change the value to MGTREFCLKO 117 iii In the TXUSRCLK Source column change the value to Channel 0 Programming and Debugging UG936 v 2014 2 June 4 2014 www xilinx com 80 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 5 Using Vivado Serial Analyzer to Debug Serial Links 4F Customize IP IBERT 7 Series GTX 3 0 E Documentation 75 IP Location C3 Switch to Defaults Show disabled ports Component Name ibert_ series_ghy_0 Protocol Definition Protocol Selection Clock Settings Summary Please select Protocol Quad combination GTX Location Protecol Selected Refclk Selection TXUSRCLK Source QUAD_115 None None tf channel CTR a r E CT CT Custom 1 8 Gbps MGTREFCLNO TI RAN_I 7 0 a 118 Custom 1 8 Gbps MGTREFCLKO 117 RXP_I 7 0
133. vado Synthesis 2013 synth_design ce Set Used In Edit Constraints Sets Edit Simulation Sets amp Td Console Add Sources Figure 143 Open IP Example Design menu item 16 In the Open IP Example Design dialog ensure that Overwrite existing example project is selected Click OK Programming and Debugging www xilinx com UG936 v 2014 2 June 4 2014 Send Feedback 110 amp XILINX ALL PROGRAMMABLE Lab 6 Using Vivado ILA core to Debug JTAG AXI Transactions g Open IP Example Design Oo Specify a location where the example project directory jtag_axi_0_example will be placed Location Put example project directory here C jtag_2_axi_tutorial jtag_2_axi_tutorial v7 Overwrite existing example project Cancel _ Figure 144 Open IP Example Design dialog 17 Open the example_jtag_axi_0 v file and notice that the jtag_axi_0 module is connected to an axi_bram_ctrl_O AXI BRAM block memory module 18 In the example_jtag_axi_0 v file add the following string to the beginning of the wire declaration for each axi_ signal from lines 72 108 mark_debug Note Do not put mark_debug on the axi_aclk signal since thts might result in Vivado Synthesis adding a LUTI to the clock path which could possibly cause you to not meet timing Lines 72 108 should look like this mark_debug wire 31 0 axi_araddr mark_debug wire 1 0 axi_arburst mark_debug wire 3
134. y selection status from the state machine outputs each of which represents a different sine wave frequency high medium and low Lab5 includes e An IBERT core e A top level wrapper that instantiates the IBERT core Board Support and Pinout Information Table 1 Pinout Information for the KC705 Board Pemtoatom tating GPIO BUTTONS 1 Sine Wave Sequencer Programming and Debugging www xilinx com 8 UG936 v 2014 2 June 4 2014 Send Feedback amp XILINX ALL PROGRAMMABLE Debugging in Vivado Tutorial Design Files 1 In your C drive create a folder called Vivado_Debug 2 Find the tutorial source files at the following location https secure xilinx com webreg clickthrough do cid 35893 98license RefDesLicense amp filename ug936 vivado tutorial program debug zi CAUTION The tutorial and design files may be updated or modified between software releases You can download the latest version of the material from the Xilinx website 3 Unzip the tutorial source file to the Vivado_Debug folder There are five labs that use different methodologies for debugging your design Select the appropriate lab and follow the steps to complete them Lab 1 This lab walks you through the steps of marking nets for debug in HDL as well as the post synthesis netlist Netlist Insertion Method Following are the required files e debounce vhd e fsm vhd e rt tcl e sinegen vhd e sinegen_demo vhd e sine_high xci e sine l

Download Pdf Manuals

Related Search

Related Contents

USE & CARE GUIDE  Sensor de tiempo de 4 canales con programa anual  Gamber-Johnson Rack-To-Post  ASSMANN Electronic SATA13pin - SATA22pin, F/M  Integral 128GB mSATAIII  Manual - OPTEX Inc.  Outil électrique alimenté par batterie  Notice MakoShark 2 DC  HP Deskjet D4360 User's Manual  Samsung SMT-1921 User Manual  

Copyright © All rights reserved. Failed to retrieve file