A-812PG. Hardware User`s Manual
Contents
1. different boards in one system but only 2 of these cards can use interrupt transfer function A 812PG Hardware Manual 13 2 3 5 JP9 User Timer Counter Clock Input Selection INTCLK EXTCLK EXTCLK The A 812PG has 3 independent 16 bits timer counter The cascaded counter and counter2 are used as pacer timer The counterO can be used as a user programmable timer counter The user programmable timer counter can select 2M internal clock or external clock ExtCLK CN3 pin 37 The block diagram is given in section 2 6 The clock source must be very stable It is recommended to use internal 2M clock The 822PGL PGH software driver use the counter as a machine independent timer If user program call A 812PG Delay subroutine the counterO will be programmed as a machine independent timer The detail information is given in section 2 6 A 812PG Hardware Manual 14 2 3 6 JP6 DMA DACK Selection JP7 DMA DRQ Selection The DMA channel can not shared The A 812PG software driver can support 8 different boards in one PC based system but only two of these boards can use DMA transfer function A 812PG Hardware Manual 15 2 4 O Register Address The A 812PG occupies 16 consecutive PC I O addresses The following table lists the registers and their locations Reserved 8254 Counter Control Base E Reserved DO High Byte A 812PG Hardware Manual 16 2 4 1 8254 Counter The 8254 Programmable timer2. A 812PG Hardware Manual 23 2 4 10 D O Output Latch Register WRITE Base D D O Cup Latch Low Byte Data Format WRITE Base E D O Output Latch High Byte Data Format Dis bi4 bpi3 bi2 fbn pio bo bs D O 16 bits output data D15 D0 DISZMSB DO LSB The A 812PG provide 16 TTL compatible digital output The low 8 bits are stored in address BASE D The high 8 bits are stored in address BASE E A 812PG Hardware Manual 24 2 5 Digital I O The A 812PG provides 16 digital input channels and 16 digital output channels All levels are TTL compatible The connections diagram and block diagram are given below Output Latch Register External Output Latch Register Device Input Buffer Register A 812PG Input Buffer Register External Device A 812PG Hardware Manual 25 2 6 8254 Timer Counter The 8254 Programmable timer counter has 4 resgisters from Base 0 through Base 3 For detailed programming information about 8254 please refer to Intel s Microsystem Components Handbook The block diagram is as below CN3 12 2M CN3 Pin 8 Cin clock input Cout clock output INTCLK internal clock CN3 connector CN3 INTCLK Ovcc 10K Gate CN3 10 in Cout Counter 0 PACER CLK CN3 14 Counter 1 vcc 10K Counter 2 CN3 6 The counterO counter and counter2 are all 16 bits counter The counter 1 and counter 2 cascade as a 32 bits timer
3. A 812PG Hardware Manual 29 2 7 4 Using software trigger and polling transfer If the user need to direct control the A D converter without the A 812PG software driver It is recommended to use software trigger and polling transfer The program steps are listing as below send 0x01 to A D mode control register software trigger polling transfer send channel number to multiplexer control register send the gain control code value to gain control register delay the settling time Dom UE Oba CES send any value to software trigger control register to generate a software rigger signal scan the READY bit of the A D high byte data until READY 0 read the 12 bits A D data convert this 12 bits binary data to the floating point value S SS A 812PG Hardware Manual 30 2 8 D A Conversion The A 812PG provides two 12 bits D A converters Before using the D A conversion function user should notice the following issue D A output register BASE 4 BASE 5 BASE 6 BASE 7 JP3 select internal reference voltage 5V 10V JP1 JP2 select internal external reference voltage If JP1 JP2 select internal and JP3 select 5V the D A output range from 0 to 5V If JP1 JP2 select internal and JP3 select 10V the D A output range from 0 to 10V If JP1 JP2 select external the external reference voltage can be AC DC 10V The block diagram is given as below D A channel 1 NOTE The DA output latch registers are designed as double buff
4. A 812PG Hardware Manual 26 2 A D Conversion This section explains how to use A D conversions The A D conversion can be triggered in any of 3 ways by software trigger by pacer trigger or by external trigger to the A D converter At the end of A D conversion it is possible to transfer data by any of 3 ways those are polling interrupt and DMA Before use the A D conversion function user should notice the following issue A D data register BASE 4 BASE 5 store the A D conversion data A D gain control register BASE 9 select gain A D multiplex control register BASE A select analog input A D mode control register BASE B select trigger type and transfer type A D software trigger control register BASE C JP8 select internal external trigger JP5 select IRQ level JP9 select internal external clock for counter0 JP6 JP7 select DMA channel 3 trigger logic software pacer external trigger 3 transfer logic polling interrupt DMA The block diagram is given below A 812PG Hardware Manual 27 2 7 1 A D conversion flow Before using the A D converter the user should setup the following hardware item select internal trigger or external trigger JP8 select IRQ level if needed JP5 select DMA channel if needed JP6 JP7 select internal clock or external clock for counter if needed JP9 Tp Ese Then the user must decide which A D conversion mode will be used The software driver supports three different
5. CH1 or CH3 jumper selectable Enable via DMA bit of control register Termination by interrupt on T C Transfer rate 100K conversions sec DOS Software manual sec 4 11 A 812PG Hardware Manual 7 1 4 Applications Signal analysis FFT amp frequency analysis Transient analysis Production test Process control Vibration analysis Energy management Industrial and lab measurement and control 1 5 Product Check List In addition to this manual the package includes the following items A 812PG multifunction card A 812PG utility diskette A 812PG DOS software menu Attention If any of these items is missing or damaged contact the dealer who provides you this product Save the shipping materials and carton in case you want to ship or store the product in the future A 812PG Hardware Manual 8 2 Hardware Configuration 2 1 Board Layout DdcISV BB ADS 774 A U SETI AA N N gt ve N N 8 df 6 df A 812PG Hardware Manual 9 2 2 O Base Address Setting The A 812PG occupies 16 consecutive locations in I O address space The base address is set by DIP switch SW1 The default address is 0x220 A9 A8 A7 A6 A5 AF SW1 BASE ADDRESS OFF OFF e Rae E oe EN S MEC MEE S a a ee ee ee ee sPbsrp orr orr orc ore or default base address is 0x220 A 812PG Hardware Manual 10 The PC I O port mapping is given bel
6. DA OFull scale VR 2 DYA1 Full Scale VR 3 A D Full scale VR amp A D Amp Offset nu nu n nu nu nu nu nu nu nu uu nu nu nu nu LN uu nu nu nu A 812PG Hardware Manual 35 3 1 Calibration VR Description There are seven VRs on the A 812PG Calibration need to adjust all seven VRs Description VRI D A channel 0 s gain adjustment VRI IVR2 D A channel 1 s gain adjustment VR3 A D s gain adjustment VR4 A D s Amplifier offset adjustment VR5 A D s offset adjustment Reference tdteee 4 5505 DA Channel 0 DA Channel 1 Fig 3 2 Calibration wiring diagnostics A 812PG Hardware Manual 36 3 2 D A Calibration Steps Tec pr COND t Refer Fig 3 2 Wiring diagnostics Run A812DIAG EXE Press Enter key to start CALIBRATION Connect CN2 pin 13 of CN2 D A Channel 0 and Pin 14 of CN2 GND to DVM DC Voltage Meter Adjust VR1 until DVM 4 9988V Press Enter key Connect D A channel 1 Pin 15 of CN2 and Pin 14 of CN2 GND to DVM Adjust VR2 until DVM 4 9988V Press Enter key 3 3 A D Calibration Steps OND tan FW Ne Refer Fig3 2 wiring diagnostics Run A812DIAG exe Press Enter key until A D calibration start Adjust VR5 until shower 4094 4095 Press Enter Adjuster VR3 until shower 2047 2048 Press Enter Repeater step 4 to step 7 until A D channel 0 equal 2047 2048 and A D channel 1 equal 9 10 Adjust VR4 until A D ch
7. Select Input current 250 nA max 125 nA typical at 25 deg On chip sample and hold Over voltage continuous single channel to 70Vp p Input impedance 10 Q 6pF 1 3 3 A D Converter Type successive approximation Burr Brown ADS 774 or SIPEX SP774B equivalent Conversion time 8 microsec Accuracy 1 bit Resolution 12 bits A 812PG Hardware Manual 5 1 3 4 DA Converter Channels 2 independent Type 12 bit multiplying Analog device AD 7541 Linearity 1 2 bit Output range 0 5V or 0 10V jumper selected may be used with other AC or DC reference input Maximum output limit 10V Output drive 5mA settling time 0 6 microseconds to 0 01 for full scale step 1 3 5 Digital I O Output port 16 bits TTL compatible Input port 16 bits TTL compatible 1 3 6 Interrupt Channel Level 3 4 5 6 7 9 10 11 12 14 15 jumper selectable Enable Via control register A 812PG Hardware Manual 6 1 3 7 Programmable Timer Counter Type 82C54 8 programmable timer counter Counters The counter and counter2 are cascaded as a 32 bits pacer timer The counterO is used as user timer counter The software driver use counter0 to implement a machine independent timer Clock input frequency DC to 10 MHz Pacer output 0 00047Hz to 0 5MHz Input gate TTL compatible Internal Clock 2M Hz 1 3 8 Direct Memory Access Channel DMA Level
8. modes polling interrupt and DMA The user can control the A D conversion by polling mode very easy It is recommended to use the software driver if using interrupt or DMA mode The analog input signals come from CN3 These signals may be single ended or differential type and must match with the setting of JP3 The multiplexer can select 16 single ended or 8 differential signals into the gain control module The settling time of multiplexer depends on the source resistance Because the software don t take care the settling time the user should delay enough settling time if switching from one channel to next channel The gain control module also need settling time if gain control code changed Because the software don t take care the settling time the user should delay enough settling time if gain control code is changed The software driver provides a machine independent timer A 812PG_Delay for settling time delay This subroutine assume that JP6 select internal 2M clock and use counterO to implement a machine independent timer If the user call A 812PG_delay the counterO will be reserved and can t be used as a user programmable timer counter The output of gain control module feed into the A D converter The A D converter need a trigger signal to start a A D conversion cycle The A 812PG supports three trigger mode software pacer and external trigger The result of A D conversion can be transfer into CPU by three mode
9. A 812PG Hardware User s Manual Warranty All products manufactured by ICP DAS are warranted against defective materials for a period of one year from the date of delivery to the original purchaser Warning ICP DAS assume no liability for damages consequent to the use of this product ICP DAS reserves the right to change this manual at any time without notice The information furnished by ICP DAS is believed to be accurate and reliable However no responsibility is assumed by ICP DAS for its use nor for any infringements of patents or other rights of third parties resulting from its use Copyright Copyright 1997 by ICP DAS All rights are reserved Trademark The names used for identification only maybe registered trademarks of their respective companies License The user can use modify and backup this software ON a single machine The user may not reproduce transfer or distribute this software or any copy in whole or in part A 812PG Hardware Manual 1 Tables of Contents 1 Introduction 1 2 Features 1 3 Specifications 1 3 1 1 3 2 1 3 3 1 3 4 1 3 5 1 3 6 1 3 7 1 3 8 1 4 Applications 2 1 Board Layout 2 3 Jumper Setting 2 3 1 2 3 2 2 3 3 2 3 4 2 3 5 2 3 6 2 4 1 2 4 2 2 4 3 2 4 4 2 4 5 2 4 6 2 4 7 2 4 8 4 1 1 General Description 4 4 5 Power Consumption 5 Analog Inputs 5 A D Converter 5 DA Co
10. G Hardware Manual 33 Daughter Board The A 812PG can be connected with many different daughter boards The function of these daughter boards are described as follows 2 10 1 DN 20 for Analog input output The DN 20 is a general purpose 20 pin connector This board direct connect to a 20pin connector It is suitable for easy signal connection and measurement 2 10 2 DB 16P for Digital input The DB 16P or 782 series is a 16 channel isolated digital input board The A 812PG provides 16 channel non isolated TTL compatible digital inputs from CN4 If connecting to DB 16P the A 812PG can provide 16 channel isolated digital input signals Isolation can protect PC if abnormal input signal is occurred 2 10 3 DB 16R for Digital output The DB 16R or 785 series provides 16 channel SPDT relay output The A 812PG provides 16 channel TTL compatible digital output from CN5 If connecting to DB 16R the A 812PG can provide 16 channel relay output to control power device A 812PG Hardware Manual 34 3 Calibration The A 812PG is calibrated to its best state of operation For environment with large vibration recalibration is recommended Before calibrating the A 812PG user should take care the following issue One 6 digit multi meter DVM One stable voltage source 4 9988V Diagnostic program A812DIAG EXE this program included in the delivered package will guide the user to proceed the calibration VR 1
11. annel 0 equal 2047 8 4094 4095 Measure A D Calibration is O K Press lt Enter gt Key until A D Amp calibration is start A 812PG Hardware Manual 37
12. counter has 4 registers from Base 0 through Base 3 For detailed programming information about 8254 please refer to Intel s Microsystem Components Handbook 8254 Counter O 8254 Counter O 8254 Counter 1 8254 Counter 1 Base 2 8254 Counter 2 8254 Counter 2 Base 3 Reserved 8254 Counter Control 2 4 2 A D Input Buffer Register READ _ Base 4 A D Low Byte Data Format D s ps a jp jp fo READ Base 5 A D High Byte Data Format o jo fo jJREADY DI pio o bs A D 12 bits data D11 D0 D11 MSB DO LSB READY 1 A D 12 bits data not ready 0 A D 12 bits data is ready The low 8 bits A D data are stored in address BASE 4 and the high 4 bits data are stored in address BASE 5 The READY bit is used as a indicator for A D conversion When a A D conversion is completed the READY bit will be clear to zero A 812PG Hardware Manual 17 2 4 3 D A Output Latch Register WRITE Base 4 Channel 1 D A Low Dyte Data Format WRITE Base 5 Channel 1 D A High Byte Data Format x k x px ju po jo ps WRITE Base 6 Channel 2 D A Low Byte Data Format D j jp jp jp 2 jn po WRITE Base 7 Channel 2 D A High Byte Data Format x k k k jp jbo jp s D A 12 bits output data D11 D0 D11 MSB DO LSB X don t care The D A converter will convert the 12 bits digital data to analog output The low 8 bits of D A channel 1 are stored in address BASE 4 and high 4 bits are stor
13. ed in address BASE 5 The address BASE 6 and BASE 7 store the 12 bits data for D A channel 2 The D A output latch registers are designed as a double buffered structure so the analog output latch registers will be updated until the high 4 bits digital data are written If the user send the high 4 bits data first the DA 12 bits output latch registers will update at once So the low 8 bits will be the previous data latched in register This action will cause an error on DA output voltage So the user must send low 8 bits first and then send high 4 bits to update the 12 bits AD output latch register NOTE Send low 8 bits first then send high 4 bits A 812PG Hardware Manual 18 2 4 4 D I Input Buffer Register READ Base 6 D I Input Buffer Low Byte Data Format READ Base 7 D I Input Buffer High Byte Data Format pis bi4 p3 p2 fbn pio bo bs D I 16 bits input data D15 D0 D15 MSB DO LSB The A 812PG provides 16 TTL compatible digital input The low 8 bits are stored in address BASE 6 The high 8 bits are stored in address BASE 7 2 4 5 Clear Interrupt Request WRITE Base 8 Clear Interrupt Request Format X don t care XXXXXXXX any 8 bits data is validate If A 812PG is working in the interrupt transfer mode a on board hardware status bit will be set after each A D conversion This bit must be clear by software before next hardware interrupt Writing any value to address BASE 8 will c
14. er structure The user must send the low byte data first then send the high byte data to store the DA 12 bits digital data If the user only send the high byte data then the low byte data will be still the previous value Also if the user send high byte first then send low byte the low byte data of DA are still hold in the previous one A 812PG Hardware Manual 31 2 9 Analog Input Signal Connection FG1 Connecting analog input configuration A 812PG A D CHO A D CHn A 812PG Hardware Manual 32 2 10 Pin Assignment CN1 CN2 Alo 1 OQ 2 AGND AI10 1100 A GND Al1 3 0Q0 4 AGND Al11 3100 A GND Al2 5 OO 6 A GND Al12 5100 A GND Al3 7 OO 8 A GND AI13 7 OQ A GND Al4 9 OOQl 10 A GND Al14 9 00 A GND Al5 11 OO 12 A GND AI15 41 OO A GND Ale 13 OO 14 A GND AO 0 131 OO A GND A7 15 OO 16 A GND AO 1 1 OO A GND Alg 17 QO 18 A GND AO OEXTREF 17 OO A GND Alg 19 OO 20 A GND AO 1 EXT REF 19 OO A GND Analog input connector CN5 DIO 1 OO DI 1 DO 0 OO DO 1 DI2 3100 DI 3 DO 2 DO 3 pia 9 OO DI 9 poa 900 DO 9 Do 11 O00 DI11 DO10 111 OO DO11 pii2 13 OO DI13 Do12 13100 DO13 DM4 15 OO DI15 DO44 15 OO DO15 D GND 17 OO D GND D GND OO D GND 5V 19 OO 12V 5y 19 OO 12V External Trigger N C N C Counter1 amp 2 Gate Internal CLK 2MHz N C External CLK N C Counter 0 Out N C Counter 0 Gate N C Counter 1 Out N C N C D GND Digital Ground PC s 5V N C Timer Counter connector A 812P
15. es three data transfer methods polling interrupt and DMA The polling subroutine A 812PG AD PollingVar or A 812PG AD PollingArray set A D mode control register to 0x01 This control word means software trigger and polling transfer The interrupt subroutine A 812PG AD INT START set A D mode control mode register to ox06 This control word means pacer trigger and interrupt transfer The DMA subroutine A 812PG AD DMA START set A D mode control register to 0x02 This control word means pacer trigger and DMA transfer A 812PG Hardware Manual 22 2 4 9 A D Software Trigger Control Register WRITE Base C A D Software Trigger Control Register Format X don t care XXXXXXXX any 8 bits data is validate The A D converter can be triggered by software trigger or pacer trigger Writing any value to address BASE C will generate a trigger pulse to A D converter and initiated a A D conversion operation The address BASE 5 offers a ready bit to indicate a A D conversion complete The software driver use this control word to detect the A 812PG hardware board The software initiates a software trigger and check the ready bit If the ready bit can not clear to zero in a fixed time the software driver will return a error message If the O BASE address setting error the ready bit will not be clear to zero The software driver A 812PG_CheckAddress use this method to detect the correctness of I O BASE address setting
16. ion Steps 3 3 A D Calibration Steps A 812PG Hardware Manual 3 36 37 37 1 Introduction 1 1 General Description The A 812PG is a high performance multifunction analog digital I O board for the PC AT compatible computer The A 812PG provides low gain 1 2 4 8 16 The A 812PG contains a 12 bit ADC with up to 16 single ended analog inputs The maximum sample rate of A D converter is about 62 5K sample sec There are two 12 bits DAC with voltage outputs 16 channels of TTL compatible digital input 16 channels of TTL compatible digital output and one 16 bit counter timer channel for timing input and output 1 2 Features The maximum sample rate of A D converter is about 62 5 K sample sec Software selectable input ranges PC AT compatible ISA bus A D trigger mode software trigger pacer trigger external trigger 16 single ended or 8 differential analog input signals Programmable low gain 1 2 4 8 16 2 channel 12 bit D A voltage output 16 digital input 16 digital output TTL compatible Interrupt handling 1 channel general purpose programmable 16 bits timer counter A 812PG Hardware Manual 4 1 3 Specifications 1 3 1 Power Consumption 5V 960 mA maximum A 812PG Operating temperature 20 C 60 C 1 3 2 Analog Inputs Channels 16 single ended Input range software programmable A 8 2PG bipolar 10V t5V 2 5V 1 25V 0 625V 0 3125V input range 10V by Jumper
17. lear this hardware bit and the hardware will generate another interrupt when next A D conversion is completed A 812PG Hardware Manual 19 2 4 6 A D Gain Control Register WRITE Base 9 A D Gain Control Register Format y The Only difference between A 812PG and A 812PG is the GAIN control function The A 812PG provides gain factor of 1 2 4 8 16 The gain control register control the gain of A D input signal Bipolar Unipolar will effect the gain factor N OTE e If gain control code changed the hardware need to delay extra gain settling time The gain settling time is different for different gain control code The software driver does not take care the gain settling time so the user need to delay the gain settling time if gain changed If the application program need to run in different machines the user need to implement a machine independent timer A 812PG GAIN CONTROL CODE TABLE o p p pause SV Ba b Wim p b sw p jeisv p n p psw p jeoogsv p ho pn pw he jernv h b p BI Bipolar UNI Unipolar X don t care N A not available A 812PG Hardware Manual 20 2 4 7 A D Multiplex Control Register WRITE Base A A D Multilexer Control Register Format A D input channel selection data 4 bits D3 D0 D32MSB DO LSB X don t care Single ended mode D3 D0 Differential mode D2 D0 D3 don t care The A 812PG provides 16 single ended or 8 diffe
18. nverter 6 Digital I O 6 Interrupt Channel 6 Programmable Timer Counter 7 Direct Memory Access Channel DMA 7 8 1 5 Product Check List 8 2 Hardware Configuration 9 9 2 2 I O Base Address Setting 10 11 JP3 D A Internal Reference Voltage Selection 11 JP1 JP2 D A Int Ext Ref Voltage Selection 12 JP8 A D Trigger Source Selection 12 JP5 Interrupt Level Selection 13 JP9 User Timer Counter Clock Input Selection 14 JP6 DMA DACK Selection JP7 DMA DRQ Selection 15 2 4 T O Register Address 16 8254 Counter 17 A D Input Buffer Register 17 D A Output Latch Register 18 D I Input Buffer Register 19 Clear Interrupt Request 19 A D Gain Control Register 20 A D Multiplex Control Register 21 A D Mode Control Register 21 A D Software Trigger Control Register 23 2 4 8 A 812PG Hardware Manual 2 2 4 9 D O Output Latch Register 24 2 5 Digital O 2 6 8254 Timer Counter 2 7 A D Conversion 2 7 1 A D conversion flow 25 26 27 28 2 7 20 A D Conversion Trigger Modes 29 2 7 3 A D Transfer Modes 29 2 7 4 Using software trigger and polling transfer 2 8 D A Conversion 2 9 Analog Input Signal Connection 2 10 Pin Assignment 2 11 Daughter Board 2 11 1 DN 20 for Analog input output 30 31 32 33 34 34 2 11 2 DB 16P for Digital input 34 2 11 3 DB 16R for Digital output 34 Calibration 35 3 1 Calibration VR Description 3 2 D A Calibrat
19. ow Device ADpREss DEVICE Bus Mouse Alt Bus Mouse 3A0 3AF DEO2E7 ATGPIB BDo 3DF_ CGA 2 3 Jumper Setting 2 3 1 JP3 D A Internal Reference Voltage Selection 10V 5V 10V 5V Select 5V D A voltage output 0 to 5V both channel Select 10V D A voltage output 0 to 10V both channel P1 is validate only if P2 select D A internal reference voltage A 812PG Hardware Manual 11 2 3 2 JP1 JP2 D A Int Ext Ref Voltage Selection JP2 vref JP2 vref JP2 vref If JP2 select internal reference then JP1 select 5V 10V internal reference voltage If JP2 select external reference then ExtRef1 CN3 pin 31 is the external reference voltage for DA channel 1 and ExtRef2 CN3 pin 12 is the external reference voltage for DA Channel 2 If user provides AC 10V external reference voltage the D A output voltage may be AC 10V 2 3 3 JP8 A D Trigger Source Selection INTTRG INTTRG EXTTRG EXTTRG The A 812PG supports two trigger type internal trigger and external trigger The external trigger comes from ExtTrg CN3 pin 17 There are two types of internal trigger software trigger and pacer trigger A 812PG Hardware Manual 12 2 3 4 JP5 Interrupt Level Selection NO Interrupt e eee weeeee e ooo wee IRQ 3 4 5 6 7 9 10 11 12 14 1I5NC IRQ 3 4 5 6 7 9 10 II 12 1415NC The interrupt channel can not be shared The A 812PG software driver can support 8
20. polling interrupt and DMA The operation mode is introduced in A 812PG Hardware Manual 28 2 7 2 A D Conversion Trigger Modes A 812PG supports three trigger modes 1 Software Trigger Write any value to A D software trigger control register BASE A will initiate a A D conversion cycle This mode is very simple but very difficult to control sampling rate 2 Pacer Trigger Mode The pacer timer can give very precise sampling rate 3 External Trigger Mode When a rising edge of external trigger signal is applied a A D conversion will be performed The external trigger source comes from pin 1 of CN3 2 7 3 A D Transfer Modes A 812PG supports three transfer modes 1 polling transfer This mode can be used with all trigger mode The software scans A D high byte data register BASE 5 until READY_BIT 0 The low byte data is also ready in BASE 4 2 interrupt transfer This mode can be used with pacer trigger or external trigger The user can set the IRQ level by adjusting JP5 A hardware interrupt signal is sent to the PC when a A D conversion is completed 3 DMA transfer This mode can be used with pacer trigger or external trigger The user can set the DMA channel by adjusting JP6 JP7 Two hardware DMA requests signal are sent sequentially to the PC when a A D conversion is completed The single mode transfer of 8237 is suggested If using interrupt or DMA transfer it is recommended to use A 812PG software driver
21. rential analog input signals In single ended mode D3 D0 select the active channel In differential mode D2 D0 select the active channel and D3 will be don t care 2 4 8 A D Mode Control Register WRITE Base B A D Mode Control Register Format x k k k w pm po Transfer Type X disable A 812PG Hardware Manual 21 JP4 Select External Trigger Mode Select Trigger Type Transfer Type 0 0 X X X X o p pec X k ele a j jo seee Setect select X The A D conversion operation can be divided into 2 stage trigger stage and transfer stage The trigger stage will generate a trigger signal to A D converter and the transfer stage will transfer the result to the CPU The trigger method may be internal trigger or external trigger The internal trigger can be software trigger or pacer trigger The software trigger is very simple but can not control the sampling rate very precisely In software trigger mode the program issues a software trigger command any time needed Then the program will poll the A D status bit until the ready bit is 0 The pacer trigger can control the sampling rate very precisely So the converted data can be used to reconstructed the waveform of analog input signal In pacer trigger mode the pacer timer will generate trigger signals to A D converter periodic These converted data can be transfer to the CPU by polling or interrupt or DMA transfer method The software driver provid
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