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uPD78018F, 78018FY Subseries 8-bit Single

1. 255 254 253 I E I i I A D conversion i i i i i i result i i i i i poia i i i i l i ADCR 3 i I i SOR _ f I I I 2 is de 1 eS apes A 0 oe Lees 5 1 1 3 2 5 3 507 254 509 255 511 1 512 256 512 256 512 256 512 256 512 256 512 Input voltage AVrer 253 CHAPTER 14 A D CONVERTER 14 4 3 Operation mode of A D converter Select one analog input channel from ANIO ANI7 by using the A D converter input select register ADIS and A D converter mode register ADM and start A D conversion The A D conversion can be started in the following two ways e Hardware start Conversion is started by trigger input INTP3 Software start Conversion is started by setting ADM The result of the A D conversion is stored in the A D conversion result register ADCR and at the same time an interrupt request signal INTAD is generated 1 A D conversion operation by hardware start The A D conversion stands by when both bits 6 TRG and 7 CS of A D converter mode register ADM are set to 1 When an external trigger signal INTP3 is input the voltage applied to the analog input pin specified by bits 1 3 ADM1 ADM3 of ADM is converted into a digital value When the A D conversion has been completed the result of the conversion is stored in the A D conversion result register ADCR and an interrupt request signal INTAD is generated Once the A D conver
2. SO1 latch SiH Shift register 1 SIO1 ba S01 SCK1 The first bit to be transferred is selected by changing the bit sequence in which data is written to SIO1 The shift sequence of SIO1 is unchanged Therefore select the first bit to be transferred MSB or LSB before writing data to the shift register 4 Starting transfer Serial transfer is started by placing transfer data in serial I O shift register 1 SIO1 if the following two conditions are atisfied e Serial interface channel 1 operation control bit CSIE1 1 The internal serial clock is stopped or SCK1 is high after 8 bit serial data has been transferred Caution If CSIE1 is set to 1 after data has been written to SIO1 the transfer is not started Serial transfer is automatically stopped and an interrupt request flag CSIIF1 is set after 8 bits of data have been transferred 17 4 3 Operation in 3 wire serial l O mode with automatic transmit receive function This 3 wire serial I O mode is to transmit receive data of up to 32 bytes without intervention by software When transfer is started data stored in RAM in advance can be transmitted by the set number of bytes or data can be received by the set number of bytes and stored in RAM To transmit receive data successively handshake signals STB and BUSY are supported by hardware so that OSD On Screen Display LSIs and peripheral LSI
3. FFFFH F7FFH BR JUMP lt 2 gt lt 6 gt F7FDH os Correction program 2 OOOOH lt 8 gt Correction program 1 xxxxH s gt lt 7 gt Branch destination lt 3 gt identification program JUMP a a lt 5 gt Internal ROM lt 1 gt Place to be corrected 2 Internal ROM Place to be corrected 1 Internal ROM 0000H lt 1 gt Execution branches to address F7FDH when the fetch address and correction address coincide lt 2 gt Execution branches to the branch destination identification program lt 3 gt The branch destination identification program BTCLR CORSTO xxxxH causes execution to branch to correction program 1 lt 4 gt Execution returns to the internal ROM program lt 5 gt Execution branches to address F7FDH when the fetch address and correction address coincide lt 6 gt Execution branches to the branch destination identification program lt 7 gt The branch destination identification program BTCLR ICORST1 0000H causes execution to branch to correction program 2 lt 8 gt Execution returns to the internal ROM program Remark internal extension RAM JUMP correction program start address 461 CHAPTER 22 ROM CORRECTION 22 7 Notes on ROM Correction 1 2 462 Be sure to set the value of an address where an instruction code is stored in correction address registers 0 and 1 CORADO and CORAD1 Set correction address registers 0 and 1 CORADO and
4. 3 A 3 lt P64 RD D Output latch de P65 WR P64 P67 P66 WAIT P67 ASTB PM64 PM67 PUO pull up resistor option register PM port mode register RD read signal of port 6 WR write signal of port 6 148 CHAPTER 6 PORT FUNCTIONS 6 3 Registers Controlling Port Functions The following four types of registers control the ports Port mode registers PMO PM1 PM2 PM3 PM5 PM6 Pull up resistor option register PUO Memory extension mode register MM Key return mode register KRM 1 Port mode registers PMO PM1 PM2 PM3 PM5 PM6 These registers set the corresponding ports in the input or output mode in 1 bit units PMO PM1 PM2 PM3 PM5 and PM6 are manipulated by a 1 bit or 8 bit memory manipulation instruction When the RESET signal is input the contents of PMO are set to 1FH and those of the other registers are set to FFH To use the multiplexed function of a port pin set the port mode register corresponding to that pin and the output latch as shown in Table 6 5 Cautions 1 P00 and P04 pins are input only pins 2 P40 P47 pins are specified in the input or output mode by the memory extension mode register 3 Because port 0 is multiplexed with external interrupt request input pins interrupt request flags are set when the output mode of the port function is specified and the output level is changed To use this port in the
5. J y EV 9200GC 64 P1E ITEM MILLIMETERS INCHES 19 5 0 768 B 14 8 0 583 C 0 840 02 x 15 12 0 0 05 0 031 8 9 x 0 591 0 472 8 003 D 0 8 0 02 x 15 12 0 0 05 0 031 0 x 0 591 0 472 9 003 E 14 8 0 583 F 19 5 0 768 G 6 00 0 08 0 236 2 883 H 6 00 0 08 0 236 2 083 0 5 0 02 0 197 2 005 J 2 36 0 03 90 093 38 K 2 2 0 1 90 0879 20 L 1 57 0 03 0 062753 Caution Dimensions of mount pad for EV 9200 and that for target device QFP may be different in some parts For the recommended mount pad dimensions for QFP refer to SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL C10535E 507 APPENDIX B DEVELOPMENT TOOLS Dimensions of Conversion Adapter TGK 064SBW Figure B 4 TGK 064SBW Dimensions Reference Lae A K AAN p E X u GC M NY I i 1 H 4 I a f o 7 Sf Pl 4 ark gt Sl G F EDH AU i HI J 77 Q _ i pe 4a 4 Y P
6. fx 27 78 1 kHz fx 28 39 1 kHz fx 29 19 5 kHz fx 2 0 9 8 kHz fx 2 2 2 4 kHz TCL25 Selects frequency of buzzer output Disables buzzer output fx 210 9 8 kHz fx 211 4 9 kHz fx 212 2 4 kHz Setting prohibited Caution Before writing new data to TCL2 stop the timer operation Remarks 1 fx Main system clock oscillation frequency 2 fxt Subsystem clock oscillation frequency 3 x Don t care 4 At fx 10 0 MHz or fxt 32 768 kHz operation 224 CHAPTER 10 WATCH TIMER 2 Watch timer mode control register TMC2 This register sets an operation mode of the watch timer sets a set time of the watch flag enables disables the operation of the prescaler and 5 bit counter and sets the interval time of the prescaler TMC2 is set by using a 1 bit or 8 bit memory manipulation instruction This register is set to OOH when the RESET signal is input Figure 10 3 Format of Watch Timer Mode Control Register Symbol 7 6 5 4 3 2 0 oa TMC25 TMC24 TMC23 TMC22 TM Address On reset R W FF4AH 00H R W TMC23 TMC20 Selects set time of watch flag 214 fw 0 5 s TMC2 1 0 213 fw 0 25 s 25 fw 977 us 24 fw 488 us TMC21 Controls prescaler operation Note 0 Clears after operation stopped 1 Enables operation TMC22 Controls 5 bit counter operation 0 Clears after operation stopped 1 Enables operation Selects in
7. Interrupt request accepted Interrupt request accepted I TO1 i i I mg e gt l I I Interval time l Interval time l Interval time l i Remark Interval time N 1 xt N 0OH FFH 211 CHAPTER 9 8 BIT TIMER EVENT COUNTER Table 9 6 Interval Time of 8 Bit Timer Event Counter 1 Minimum Interval Time Maximum Interval Time Resolution TH input cycle 28 x TI1 input cycle TI1 input edge cycle TH input cycle 28 x TI1 input cycle TI1 input edge cycle 22 x 1 fx 400 ns 210 x 1 fx 102 4 us 22 x 1 fx 400 ns 23 x 1 fx 800 ns 211 x 1 fx 204 8 us 23 x 1 fx 800 ns 24 x 1 fx 1 6 us 212 x 1 fx 409 6 us 24 x 1 fx 1 6 us 25 x 1 fx 3 2 us 213 x 1 tx 819 2 us 25 x 1 fx 3 2 us 26 x 1 tx 6 4 us 214 x 1 fx 1 64 ms 26 x 1 fx 6 4 us 27 x 1 fx 12 8 us 215 x 1 tx 3 28 ms 27 x 1 tx 12 8 us 28 x 1 tx 25 6 us 216 x 1 tx 6 55 ms 28 x 1 tx 25 6 us 29 x 1 tx 51 2 us 217 x 1 tx 13 1 ms 29 x 1 tx 51 2 us 210 x 1 fx 102 4 us 218 x 1 fx 26 2 ms 210 x 1 fx 102 4 us 212 x 1 fx 409 6 us 220 x 1 fx 104 9 ms 212 x 1 fx 409 6 us Others Setting prohibited Remarks 1 fx Main system clock oscillation frequency 2 TCL10 TCL13 Bits 0 through 3 of timer clock select register 1 TCL1 3 At fx 10 0 MHz operation Table 9 7 Interval Time of 8 Bit Timer Event Counter 2 Minimum Int
8. To check the electrical characteristics of the wPD78018F and wPD78018FY subseries Refer to the Data Sheet separately available For the application examples of the respective functions of the uPD78018F and uUPD78018FY subseries Refer to the Application Notes separately available Caution The examples in this manual are for the standard quality grade of general purpose electronic 10 systems If you use an example in this manual for applications where special quality grade is required evaluate the quality of the parts and circuits actually used Chapter Organization The functions that differ between the wPD78018F subseries and u PD78018FY subseries are explained in separate chapters in this manual corresponding to each subseries are shown below Refer to the chapter marked in the following table Chapter CHAPTER 1 GENERAL uPD78018F SUBSERIES uPD78018F Subseries The chapters 4PD78018FY Subseries CHAPTER 2 GENERAL uPD78018FY SUBSERIES CHAPTER 3 PIN FUNCTIONS 14PD78018F SUBSERIES CHAPTER 4 PIN FUNCTIONS 14PD78018FY SUBSERIES CHAPTER 5 CPU ARCHITECTURE CHAPTER 6 PORT FUNCTIONS CHAPTER 7 CLOCK GENERATION CIRCUIT CHAPTER 8 16 BIT TIMER EVENT COUNTER CHAPTER 9 8 BIT TIMER EVENT COUNTER CHAPTER 10 WATCH TIMER CHAPTER 11 WATCHDOG TIMER CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT CHAPTER 13 BUZZER OUTPU
9. PM22 PM27 e Multiplexed function pull up resistor option register 143 i rir lv ed CHAPTER 6 PORT FUNCTIONS 6 2 5 Port 3 This is an 8 bit I O port with output latch P30 P37 pins can be specified in the input or output mode in 1 bit units by using the port mode register 3 PM3 When using P30 P37 pins as input port pins internal pull up resistors can be connected in 8 bit units by using the pull up resistor option register PUO The pins of this port are also used as the timer I O clock output and buzzer output pins This port is set in the input mode when the RESET signal is input Figure 6 10 shows the block diagram of port 3 Figure 6 10 Block Diagram of P30 P37 Voo wee WRpeuo Den lt H e WRPorT P30 TOO P31 TO1 P32 TO2 P33 T11 E O P34 m12 P35 PCL P36 BUZ P37 CA Internal bus Multiplexed function PUO pull up resistor option register PM port mode register RD read signal of port 3 WR write signal of port 3 144 CHAPTER 6 PORT FUNCTIONS i rir lv ed 6 2 6 Port 4 This is an 8 bit I O port with output latch P40 P47 pins can be specified in the input or output mode in 8 bit units by using the memory extension mode register MM When using P40 P47 pins as input port pins internal pull up resistors can be connected in 8 bit units by using the pull up resistor option r
10. If set during this period and ACKE 1 at falling edge of next SCKO c When ACKE 0 at end of transfer SCKO 1 2 7 8 9 SBO SB1 X D7 X D6 X02 X Di X Do ACK signal is not output A When ACKE 0 at this point d If period of ACKE 1 is short KA a f SBO SB1 D2 X D1 X Do ACK signal is not output ACKE c If set and clear during this period and ACKE 0 at falling edge of SCKO 291 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 uPD78018F SUBSERIE Figure 15 23 Operation of ACKD a If ACK signal is output during 9th clock period of SCKO Transfer start command 0 9 SIO0 Transfer start SCKO SBO SB1 ACKD b If ACK signal is output after 9th clock of SCKO Transfer start ik command BOO oe Nat take S O Transfer start SCKO 6 7 8 9 seose X02 X bt X00 ACKD c Clearing timing when transfer start command is issued during BUSY Transfer start command SCKO 6 7 8 9 seo s81 X D2 X01 X 00 ACKD A Figure 15 24 Operation of BSYE SCKO 6 7 8 9 SBO SB1 D2 X Di X Do ACK BUSY A When BSYE 1 at this point If reset during this period and BSYE 0 at falling edge of SCKO 292 62 Signal Name Bus release signal REL Output Device Master Definition At rising edge of SBO SB1 when SCKO 1 Table 15 4 Signals in SBI Mode 1 2 Timing Chart
11. The first bit is selected by changing the bit order in which data is written to SIOO The shift sequence of SIOO is always the same Therefore specify whether the MSB or LSB is first before writing data to the shift register 327 i rN a lu ed CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78018FY SUBSERI7 5 Transfer start Serial transfer is started by setting the transfer data to the serial I O shift register O SIOO when the following two conditions are satisfied e Operation control bit of serial interface channel 0 CSIEO 1 When internal serial clock is stopped or SCKO is high after 8 bit serial transfer Caution Even if CSIEO is set to 1 after data has been written to SIOO transfer is not started Serial transfer is automatically stopped at the end of 8 bit transfer and an interrupt request flag CSIIFO is set 16 4 3 Operation in 2 wire serial I O mode The 2 wire serial l O mode can be used with any communication format by program Basically two lines serial clock SCKO and serial data I O SBO or SB1 are used to establish communication in this mode Figure 16 9 Example of Serial Bus Configuration by 2 Wire Serial I O Voo Vpop e E Master Slave SCKO SCKO SBO SB1 SBO SB1 1 Register setting The 2 wire serial I O mode is set by using the serial operation mode register 0 CSIMO serial bus interface control register SBIC and interrupt timing specification re
12. eee 411 18 8 Configuration of Program Status Word ccceeceeceeeeeeeeeeeeeeeeeeeeeeeeeaeeeeeeeeeeseeeseaeeseaeeeeene 412 18 9 Flowchart of Non Maskable Interrupt Request from Generation to Acceptance 413 18 10 Timing of Non Maskable Interrupt Request Acceptance coooccccnoccccnonccnnnnnncnnnnnnnnnnnnnnnnanonnns 413 18 11 Accepting Non Maskable Interrupt Acceptance Operation oooocciccnnncccnnccnoccnonccnnnncanccnnnnnn 414 18 12 Interrupt Request Acceptance Program Algorithm ooooocccnnncccononcconacanonanaccnnornnnnnrnncrnr cnn 416 18 13 Interrupt Request Acceptance Timing Minimum Time cece eeseeeesneeeeeneeeeeeneeeeeeeees 417 18 14 Interrupt Request Acceptance Timing Maximum Time 0 0 eeseeesseeeeseeeeeeneeeeeneeeeeaeees 417 18 15 Example of Nesting ist is 2 islets eins Sat hn ea nd aden aS 419 18 16 Pending Interrupt Request cocodrilo sabndcceesdacsadecsgedesedeseseecgevacdeesasecees 421 18 17 Basic Configuration of Test Function 0 0 eeeeceeeeeeeeeeeeeeeeeeeeeeeeeaeeeeeeeaeeseeeseaeeseaeeeaeetaaes 422 18 18 Format of Interrupt Request Flag Register OH 2 00 0 eeeseeesseeeeeneeeeeeneeeesaeeeseneeeeseneeeesaeeess 423 18 19 Format of Interrupt Mask Flag Register OH oooconoccccnoncccononccononcnnnancnonananornnn nn cnn n nora n nn nnnnnnnns 423 18 20 Format of Key Return Mode Register oooocccnocccnonccccnoncnnnncnnonancnnnnoncnnnno cnc nono nn nan nn cnn ana rannnnnns 424 19 1 Memory Map when E
13. 95 CHAPTER 5 CPU ARCHITECTURE Data memory space 96 Program memory space Figure 5 6 Memory Map uPD78016F 78016FY Special function register SFR 256 x 8 bits General purpose register 32 x 8 bits Internal high speed RAM 1024 x 8 bits FBOOH FAFFH BFFFH Reserved FAEOH Program area FARER Internal buffer RAM 32 x 8 bits 10007 FACOH OFFFH FABFH Reserved CALLF entry area F800H F7FFH 0800H Internal extension RAM 07FFH 512 x 8 bits F600H Program area F5FFH External memory 0080H 13824 x 8 bits 007FH C000H CALLT table area BFFFH 0040H Internal ROM DORE 49152 x 8 bits Vector table area 0000H 0000H CHAPTER 5 CPU ARCHITECTURE Figure 5 7 Memory Map uPD78018F 78018FY Special function register SFR 256 x 8 bits General purpose register 32 x 8 bits Internal high speed RAM 1024 x 8 bits FBOOH FAFFH EFFFH Reserved FAEOH Program area FADFH Data memory ests ae RAM 1000H space FACOH Roe OFFFH FABFH Reserved CALLF entry area F800H F7FFH 0800H Internal extension RAM 07FFH 1024 x 8 bits ee F400H Program area F3FFH 0080H Reserved 007FH FOOOH CALLT table area cow ERREN d 0040H Space 003FH Internal ROM 61440 x 8 bits Vector table area he ie Y 0000H 0000H Note When the internal ROM capacity is 60 KB the area of FOOOH F3FFH cannot be used The area of FOOO
14. Falling edge Rising edge Setting prohibited Both rising and falling edges Falling edge Rising edge Setting prohibited Both rising and falling edges Caution Set the valid edge of the INTPO TIO POO pin after setting bits 1 through 3 TMC01 through TMC03 of the 16 bit timer mode control register TMCO to 0 0 0 and stopping the timer operation 409 i ri oY a lv ed CHAPTER 18 INTERRUPT FUNCTIONS AND TEST FUNCTIONS 5 Sampling clock select register SCS This register sets the clock with which the valid edge input to INTPO is sampled When receiving a remote controller signal by using INTPO digital noise can be eliminated by the sampling clock SCS is set by an 8 bit memory manipulation instruction This register is set to OOH when the RESET signal is input Figure 18 6 Format of Sampling Clock Select Register Symbol 7 6 0 Address On reset R W 5 4 3 2 1 SOI SCS1 SCSO Selects sampling clock of INTPO fx 2N 1 Setting prohibited fx 26 156kHz 1x 27 78 1kHz Caution fx 2N 1 is the clock supplied to the CPU fx 2 and fx 2 are the clocks supplied to the peripheral hardware tx 2N 1 is stopped in the HALT mode Remarks 1 N Value N 0 4 set to bits O through 2 PCCO PCC2 of processor clock control register 2 fx Main system clock oscillation frequency 3 At fx 10 0 MHz operation 410 CHAPTER 18 INTERRU
15. 437 i rir lv ed MEMO 438 al UNO CHAPTER 20 STANDBY FUNCTION 20 1 Standby Function and Configuration 20 1 1 Standby function The standby function is to reduce the power consumption of the system and can be effected in the following two modes 1 HALT mode This mode is set when the HALT instruction is executed The HALT mode stops the operation clock of the CPU The system clock oscillation circuit continues oscillating This mode does not reduce the current consumption as much as the STOP mode butis useful for resuming processing immediately when an interrupt request is generated or for intermittent operations such as a watch operation 2 STOP mode This mode is set when the STOP instruction is executed The STOP mode stops the main system clock oscillation circuit and stops the entire system The current consumption of the CPU can be substantially reduced in this mode The low voltage Voo 1 8 V of the data memory can be retained Therefore this mode is useful for retaining the contents of the data memory at an extremely low current The STOP mode can be released by an interrupt request so that this mode can be used for the intermittent operation However certain time is required until the system clock oscillation circuit stabilizes after the STOP mode has been released If processing must be resumed immediately by using an interrupt request therefore use the HALT mode In both modes the prev
16. OP code addr16 low order addr16 high order Memory 125 CHAPTER 5 CPU ARCHITECTURE 5 4 5 Short direct addressing Function This addressing directly addresses a memory area to be manipulated from a fixed space by using the 8 bit data in an instruction word This addressing is applicable to the fixed 256 byte space of FE20H FF1FH The internal high speed RAM is mapped to addresses FE20H FEFFH and special function registers SFRs are mapped to addresses FFOOH FF1FH The SFR area FFOOH FF1FH to which short direct addressing is applied is one part of all the SFR areas In this area ports compare and capture registers of timer event counters that are frequently accessed on program are mapped These SFRs can be manipulated with a few bytes and clocks Bit 8 of the effective address is 0 if the 8 bit immediate data is in a range of 20H FFH and 1 if the dataisina range of OOH 1FH Refer to Operation on the next page Operand Format Label or immediate data FE20H FF1FH Label or immediate data FE20H FF1FH even address only 126 CHAPTER 5 CPU ARCHITECTURE Example MOV OFE30H 50H To specify FE30H as saddr and 50H as immediate data Instruction code 0001000 1 OP code 0 01 1 0 0 0 0 30H saddr offset 0 101 0 0 0 O 50H immediate data Operation OP code saddr offset Short direct memory Effective address When 8 bit immediate da
17. 3 Square wave output A square wave of any frequency can be output Table 9 4 Square Wave Output Range of 8 Bit Timer Event Counters Used as 16 Bit Timer Event Counter Minimum Pulse Width Maximum Pulse Width Resolution 22 x 1 fx 400 ns 218 x 1 fx 26 2 ms 22 x 1 fx 400 ns 23 x 1 fx 800 ns 219 x 1 fx 52 4 ms 23 x 1 fx 800 ns 24 x 4 fx 1 6 us 220 x 1 fx 104 9 ms 24 x 4 fx 1 6 us 25 x 1 fx 3 2 us 221 x 1 fx 209 7 ms 25 x 1 fx 3 2 us 28 x 1 fx 6 4 us 222 x 1 fx 419 4 ms 27 x 1 fx 12 8 us 223 x 1 fx 838 9 ms 28 x 1 fx 6 4 us 27 x 1 fx 12 8 us 28 x 1 fx 25 6 us 224 x 1 fx 1 7 s 28 x 1 fx 25 6 us 210 x 1 fx 102 4 us 226 x 1 fx 6 7 s 210 x 1 fx 102 4 us 29 x 1 fx 51 2 us 225 x 1 fx 3 4 s 29 x 1 fx 51 2 us 212 x 1 fx 409 6 us 228 x 1 fx 26 8 s 212 x 1 fx 409 6 us Remarks 1 fx main system clock oscillation frequency 2 atfx 10 0 MHz operation 201 CHAPTER 9 8 BIT TIMER EVENT COUNTER 9 2 Configuration of 8 Bit Timer Event Counter An 8 bit timer event counter consists of the following hardware Table 9 5 Configuration of 8 Bit Timer Event Counter Timer register 8 bits x 2 TM1 TM2 Register Compare register 8 bits x 2 CR10 CR20 Timer output 2 TO1 TO2 Control register Timer clock select register 1 TCL1 8 bit timer mode control register TMC1 8 bi
18. A saddr A CY A saddr A laddr16 OIlNI NIN WIM NM ND Pw A CY lt A addr16 A HL A CY A A HL byte A CY A HL byte A HL B A CY A HL HL B A HL C A CY lt A HL C A byte A CYA byte CY saddr byte saddr CY saddr byte CY A r A CY lt A r CY nA r CY r A CY A saddr A CY lt A saddr A laddr16 VO NDN N N O0O N ND N N A CY A addr16 CY A HL A CY A HL A HL byte A CY lt A HL byte CY A HL B A CY A HL B CY A HL C hm mM Ph A CY A HL C CY Notes 1 When the internal high speed RAM area is accessed or when an instruction that does not access data is executed 2 When an area other than the internal high speed RAM area is accessed 3 Exceptr A Remarks 1 One clock of an instruction is equal to one CPU clock fcru selected by processor clock control register PCC 2 The number of clocks shown is when the program is stored in the internal ROM area 3 n indicates the number of wait states when the external memory extension area is read 482 CHAPTER 24 INSTRUCTION SET Instruction Group 8 bit operation Mnemonic Operand A byte Operation A amp ANbyte
19. CHAPTER 3 PIN FUNCTIONS uPD78018F SUBSERIEY 3 2 11 RESET This pin inputs an active low system reset signal 3 2 12 X1 and X2 These pins are used to connect a crystal resonator for main system clock oscillation To supply an external clock input the clock to X1 and input the inverted signal to X2 3 2 13 XT1 and XT2 These pins are used to connect a crystal resonator for subsystem clock oscillation To supply an external clock input the clock to XT1 and input the inverted signal to XT2 3 2 14 VoD Positive power supply pin 3 2 15 Vss Ground pin 3 2 16 Vrr uPD78P018F only A high voltage should be applied to this pin when the PROM programming mode is set and when the program is written or verified Directly connect this pin to Vss in the normal operation mode 3 2 17 IC mask ROM model only The IC Internally Connected pin is used to set the uPD78011F 78012F 78013F 78014F 78015F 78016F and 78018F in the test mode before shipment In the normal operation mode directly connect this pin to the Vss pin with as short a wiring length as possible If the wiring length between the IC pin and Vss pin is too long or if a potential difference is generated between the IC pin and Vss pin because an external noise is superimposed on the IC pin user s program may not run correctly e Directly connect the IC pin to the Vss pin Keep short 75 CHAPTER 3 PIN FUNCTIONS uPD78018F SUBSERIES 3 3 I O Circuits o
20. Direct addressing Register indirect addressing Based addressing Based indexed addressing CHAPTER 5 CPU ARCHITECTURE FFFFH A A Special function registers SFRs i 256 x 8 bits SFR addressing A A A A AAA FF1FH A FFOOH Y FEFFH 4 General purpose registers i 32 x 8 bits Register addressing FEEOH Short direct FEDFH l addressing Internal high speed RAM 1024 x 8 bits FE2ZO EAE E A AEA Y FE1FH i Direct addressing FBOOH FAFFH Register indirect Reserved addressing FAEOH FADFH Internal buffer RAM Based addressing FACOH 32 x 8 bits l FABFH Based indexed addressing Reserved FA80H FA7FH External memory 39552 x 8 bits 6000H 5FFFH Internal ROM 24576 x 8 bits 0000H Y 117 CHAPTER 5 CPU ARCHITECTURE 118 Figure 5 18 Data Memory Addressing uPD78014F 78014FY FFFFH I Special function registers SFRs 256 x 8 bits SFR addressing E 8 6 of re ote 2 phen a ee ae Hh Prete ae FF1FH FFOOH t FEFFH A General purpose registers 32 x 8 bits Register addressing FEEOH Short direct FEDFH 1 addressing Internal high speed RAM 1024 x 8 bits FE20H e FE1FH FBOOH FAFFH Reserved FAEOH FADFH Internal buffer RAM FACOH 32 x 8 bits FABFH Reserved FA80H FA7FH External memory 31360 x 8 bits 8000H 7FFFH Internal ROM 32768 x 8 bits 0000H Direct addressing Register indirect addressing Bas
21. Remarks 1 fx Main system clock oscillation frequency 2 fxr Subsystem clock oscillation frequency 3 TIO Input pin of 16 bit timer event counter 4 TMO 16 bit timer register 5 At fx 10 0 MHz or fxt 32 768 kHz operation 6 For PCL refer to CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT 182 CHAPTER 8 16 BIT TIMER EVENT COUNTER Figure 8 5 Format of 16 Bit Timer Mode Control Register Symbol 7 6 5 lt 0 gt Address Onreset R W 4 3 2 1 mo CC er o a OVFO Detects overflow in 16 bit timer register 0 Overflow does not occur 1 Overflow occurs Selects operation Selects timing of mode or clear mode TOO output TMC02 TMCO1 Generates interrupt Stops operation TMO is cleared to 0 Not affected Not generated PWM mode free running PWM pulse output Coincidence between TMO and CROO Free running mode Coincidence between TMO and CROO or valid edge of TIO Coincidence between Generated when Clear and start TMO and CROO TMO coincides with CROO at valid edge of TIO Coincidence between TMO and CROO or valid edge of TIO Coincidence Clear and start at coincidence between TMO and CROO between TMO and CROO Coincidence between TMO and CROO or valid edge of TIO Cautions 1 Before changing the clear mode and output timing of TOO stop the timer operation set TMC01 through TMCO3 to 0 0 0 2 The valid edge of the TIO INTPO pin is set by the exte
22. SCK1 p sor Jozppsposfosppsppejoripo fozppsppsiosiesppaioifpo 4 CSIIF1 TRF p Cautions 1 In the basic transmit mode the buffer RAM is read after 1 byte data has been transmitted Therefore there is an interval time until the next transmission is executed Because the buffer RAM is read simultaneously with the CPU processing the maximum interval time depends on the CPU processing and a value of the automatic data transmission reception time interval specification register ADTI refer to 5 Interval time of automatic transmission reception 2 When TRF is cleared the SO1 pin goes low Remark CSIIF1 Interrupt request flag TRF Bit 3 of the automatic transmit receive control register ADTC 384 CHAPTER 17 SERIAL INTERFACE CHANNEL 1 Figure 17 12 Flowchart of Basic Transmit Mode Writes transmit data to buffer RAM Sets value of number of transmit data bytes minus 1 to ADTP pointer value Software execution Sets interval time for transmit receive operation to ADTI Writes any data to SIO1 start trigger Writes transmit data from buffer RAM to SIO1 Transmit operation Decrements pointer value i Hardware execution Pointer value 0 Software execution A A ADTP Automatic data transmit receive address pointer ADTI Automatic data transmit receive interval specification register SIO1 Serial I O shift register 1 TRF Bit 3 of automatic data transmit receive control register
23. Figure 16 24 Releasing Slave from Wait Status during transmission Processing in master device Program processing Hardware Sets Sets i i Transfer line SCL conn EJES A ETA CEY Processing in slave device Sets P27 i Sets P27 Program output lcd output i latch latch processing ateh S100 ale Hardware ACK Sets Releases Ls operation output CSIIFO welt Serial transmission 353 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78018FY SUBSERI7 3 Releasing slave from wait status slave reception A slave is released from the wait status when the WREL flag bit 2 of the interrupt timing specification register SINT is set or when an instruction that writes data to serial I O shift register O S100 is executed When aslave receives data if the SCL line goes into a high impedance state immediately after the instruction that writes data to SIOO has been executed the data of the first bit from the master may not be received This is because SIO does not start its operation if the SCL line is in the high impedance state while the instruction that writes data to SIOO is being executed or until the next instruction is executed Therefore receive the data by manipulating the output latch of P27 by the program as shown in Figure 16 25 For the timing of these operations refer to Figure 16 21 Figure 16 25 Releasing Slave from Wait Status during reception Processing in master device Program Writes processin
24. Internal bus 12 3 Registers Controlling Clock Output Function The following two registers control the clock output function Timer clock select register O TCLO Port mode register 3 PM3 1 Timer clock select register 0 TCLO This register sets the clock for PCL output TCLO is set by a 1 bit or 8 bit memory manipulation instruction This register is set to OOH when the RESET signal is input Remark TCLO also has a function to set the count clock of the 16 bit timer register in addition to a function to set the clock for PCL output 238 CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT Symbol Cautions 1 Remarks lt gt 5 4 3 2 1 0 TCLO CLOE TCLO6 TCLO5 TCL04 TCLO3 TCLO2 TCL01 TCLOO Figure 12 3 Format of Timer Clock Select Register 0 6 Address On reset R W FF40H 00H R W TCLO2 TCLO1 TCLOO Selects clock of PCL output fxr 32 768 kHz fx 23 1 25 MHz fx 24 625 kHz fx 25 313 kHz fx 28 156 kHz fx 27 78 1 kHz fx 28 39 1 kHz Others Setting prohibited fx 2 5 0 MHz fx 22 2 5 MHz fx 28 1 25 MHz Others Setting prohibited Si Be iN se CLOE Controls PCL output 0 Disables output 1 Enables output The valid edge of the TIO POO INTPO pin is set by the external interrupt mode register The frequency of a sampling clock is selected by the sampling clock select register To enable PCL output
25. L TANNVHO SOV4AYSLNI TVINSAS Zt YILAVHO al UNO CHAPTER 17 SERIAL INTERFACE CHANNEL 1 1 2 3 Serial I O shift register 1 SIO1 This 8 bit register converts parallel data into serial data and transmits receives serial data shift operation in synchronization with the serial clock SIO1 is set by an 8 bit memory manipulation instruction When bit 7 CSIE1 of the serial operation mode register 1 CSIM1 is 1 the shift operation is started when data is written to SIO1 When data is transmitted the data written to SIO1 is output to the serial output line SO1 When data is received it is read from the serial input line SI1 to SIO1 The contents of SIO1 become undefined when the RESET signal is input Caution Do not write data to SIO1 when the automatic transmit receive operation is performed Automatic data transmit receive address pointer ADTP This register stores a value of number of transmission data bytes 1 when the automatic transmit receive function is performed lts contents are automatically decremented when data transmission reception is executed ADTP is set by an 8 bit memory manipulation instruction At this time set the high order 3 bits to 0 The contents of this register are set to OOH when the RESET signal is input Caution Do not write data to ADTP when the automatic transmit receive operation is performed Serial clock counter This counter counts the serial clock
26. P01 P02 P03 P04 Table 6 2 5 bit I O port Port Functions uPD78018FY Subseries Function Input only Shared by INTPO TIO Can be specified for input output bitwise When used as input port internal pull up resistor can be connected by software INTP1 INTP2 INTP3 Input only XT1 P10 P17 8 bit I O port Can be specified for input output bitwise When used as input port internal pull up resistor can be connected by software ANIO ANI7 P20 P21 P22 P23 P24 P25 P26 P27 8 bit I O port Can be specified for input output bitwise When used as input port internal pull up resistor can be connected by software sit S01 SCKi STB BUSY SI0 SBO SDAO SO0 SB1 SDA1 SCKO SCL P30 P31 P32 P33 P34 P35 P36 P37 8 bit I O port Can be specified for input output bitwise When used as input port internal pull up resistor can be connected by software TOO TO1 TO2 TH TI2 PCL BUZ P40 P47 8 bit I O port Can be specified for input output in 8 bit units When used as input port internal pull up resistor can be connected by software Test input flag KRIF is set to 1 at falling edge of these pins ADO AD7 P50 P57 8 bit I O port Can directly drive LED Can be specified for input output bitwise When used as input port internal pull up resistor can be connected b
27. POO INTPO P33 P34 TOO TO1 TO2 Output 16 bit timer TMO output shared by 14 bit PWM output 8 bit timer TM1 output 8 bit timer TM2 output P30 P31 P32 PCL Output Clock output for trimming of main system clock subsystem clock P35 BUZ Output Buzzer output P36 ADO AD7 1 0 Low order address data bus when memory is externally extended P40 P47 A8 A15 Output High order address bus when memory is externally extended P50 P57 RD WR Output Strobe signal output for external memory read Strobe signal output for external memory write P64 P65 WAIT Input Wait insertion when external memory is accessed P66 ASTB Output Strobe output that externally latches address information output to ports 4 and 5 to access external memory P67 69 CHAPTER 3 PIN FUNCTIONS uPD78018F SUBSERIES 2 Pins other than port pins 2 2 Pin Name Function ANIO ANI7 Analog input to A D converter AVREF Reference voltage input to A D converter AVoo Analog power to A D converter Connect to Von AVss Ground of A D converter Connect to Vss RESET System reset input Connect crystal resonator for main system clock oscillation Connect crystal resonator for subsystem clock oscillation Positive power supply High voltage application for program write verify Directly connect thi
28. 1 Interrupt request flag registers IFOL IFOH An interrupt request flag is setto 1 when the corresponding interrupt request is generated or when an instruction is executed and is cleared to 0 when the interrupt request is accepted when the RESET signal is input or when an instruction is executed IFOL and IFOH are set by a 1 bit or 8 bit memory manipulation instruction When using IFOL and IFOH as a 16 bit register IFO it is set by a 16 bit memory manipulation instruction These registers are set to 00H when the RESET signal is input Figure 18 2 Format of Interrupt Request Flag Registers Symbol 7 lt 6 lt 5 4 lt 3 lt 2 lt 1 0 Address Onreset R W IFOL TMIF3 CSIF1CSIFO PIF3 PIF2 PIF1 PIFO TMIFA FFEOH 00H R W 6 lt 5 gt 4 gt lt 2 gt lt 1 lt lt Not IFOH baje WTIF ADIF TMIF2 FFE1H 00H R W xxIF Interrupt request flag Interrupt request signal is not generated Interrupt request signal is generated and interrupt is requested Note The WTIF is a test input flag and does not generate a vectored interrupt request Cautions 1 The TMIF4 flag can be read written only when the watchdog timer is used as an interval timer Clear the TMIF4 flag to 0 when the watchdog timer mode 1 is used 2 Be sure to set bits 4 6 7 of IFOH to 0 406 i tinued CHAPTER 18 INTERRUPT FUNCTIONS AND TEST FUNCT 2 Interrupt mask flag registers MKOL MKOH An interrupt mas
29. 64 pin plastic shrink DIP 750 mil 1PD78011FCW XXX 78012FCW XXX 7801 3FCW XXX 1PD78014FCW XXX 78015FCW XXX 78016FCW XXX UPD78018FCW XXX 78P018FCW 1PD78011FCW A XXX 78012FCW A XXX 78013FCW A XXX 1PD78014FCW A XXX 78015FCW A XXX 78016FCW A XXX UPD78018FCW A XXX 78P018FCW A 64 pin ceramic shrink DIP with window 750 mil u4PD78P018FDW CHAPTER 1 GENERAL uPD78018F SUBSERIES P20 SI1 O lt gt 1 O AVrer P21 S01 O 2 O AVoo P22 SCK1 O gt 3 O P17 ANI7 P23 STB O 4 O P16 ANI6 P24 BUSY O gt 5 O P15 ANI5 P25 SI0 SBO O 6 O P14 ANI4 P26 SO0 SB1 O gt 7 O P13 ANI3 P27 SCKO O 8 O P12 ANI2 P30 TOO O O P11 ANI1 P31 T01 O lt gt O P10 ANIO P32 TO2 O O AVss P33 T11 O L lt O P04 XT1 P34 T12 O O XT2 P35 PCL O lt gt O IC Vrr P36 BUZ O O X1 P37 O lt O X2 Vss O O Vo P40 ADO O O PO3 INTP3 P41 AD1 O lt gt O PO2 INTP2 P42 AD2 O O PO1 INTP1 P43 AD3 O lt O POO INTPO TIO P44 AD4 O O RESET P45 AD5 O O P67 ASTB P46 AD6 O O P66 WAIT P47 AD7 O lt gt O P65 WR P50 A8 O lt gt O P64 RD P51 A9 O O P63 P52 A10 O lt gt O P62 P53 A11 O O P61 P54 A12 O lt gt xO P60 P55 A13 O O P57 A15 Vss O O P56 A14 Cautions 1 Directly connect the IC Internally Connected pins to Vss 2 Connect the AVob pin to Vpp 3 Connect the AVss pin to Vss Remark uPD78P018F 41 CHAPTER 1 GENERAL uwPD78018F SUBSERIES 64 pin plastic QFP 14 x 14 mm 1PD78011FGC XXX AB8 7
30. Generates interrupt request signal each time serial clock is counted eight times 2 wire serial l O mode Others Setting prohibited 12C bus mode 0 during transmission Generates interrupt request signal each time serial clock is counted eight times 8 clock wait Normally setting of WAT1 WATO 1 0 is not made during transmission This setting is used only when reception and processing must be systematically arranged by software Because ACK information is generated by reception side ACKE is set to 0 disabled Generates interrupt request signal each time serial clock is counted nine times 9 clock wait Because ACK information is generated by reception side ACKE is set to 0 disabled Others Setting prohibited 12C bus mode 1 during reception Generates interrupt request signal each time serial clock is counted eight times 8 clock wait ACK information is output by manipulating ACKT by sofrware after interrupts request signal are generated Generates interrupt request signal each time serial clock is counted nine times 9 clock wait To generate ACK information automatically ACKE is set to 1 enable before starting transfer However master sets ACKE to 0 disable before receiving last data After receiving an address generates an interrupt request signal when the values of the serial I O shift register 0 SIO0 and slave address register SVA coincide and when
31. enable Vpop nee Output x N ch disable TT IN OUT Vo Pullup i enable po ECN Voo e IN OUT Output disable Input enable Type 10 A Voo ie Pullup E enable Do aN Vo e Open drain Output disable Data gt P ch IN OUT Type 5 E Pullup enable Do Vo Data gt H IN OUT Output disable Type 11 Pullup enable e VoD Output x N ch disable Pchy op Comparator Vrer Threshold voltage Input enable _ 0 IN OUT 77 CHAPTER 3 PIN FUNCTIONS uPD78018F SUBSERIES Figure 3 1 I O Circuits of Pins 2 2 Type 13 B haa option 40 IN OUT Feedback cut off Data Output disable o N ch P ch ve MN ry A hd AD Ez P e gt lt Medium withstanding voltage input buffer 78 HO IN OUT Data Output disable RD Medium withstanding voltage input buffer CHAPTER 4 PIN FUNCTIONS uPD78018FY SUBSERIES 4 1 List of Pin Functions 4 1 1 Pins in normal 1 Port pins 1 2 Pin Name P03 po4Note 1 operation mode Function Port 0 Input only On Reset Shared by INTPO TIO S bit I O port Can be specified for input output bitwise When used as input port internal pull up resistor can be connected by softwar
32. 0 5 fsck 148 0 us 1 5 fsck 0 0 0 0 0 0 0 0 0 0 0 0 159 2 us 0 5 fsck 160 8 us 1 5 fsck 172 0 us 0 5 fsck 173 6 us 1 5 fsck 184 8 us 0 5 fsck 186 4 us 1 5 fsck 197 6 us 0 5 fsck 199 2 us 1 5 fsck oOojojo o 210 4 us 0 5 fsck 212 0 us 1 5 fsck 367 i ri od we GS 4 CHAPTER 17 SERIAL INTERFACE CHANNEL 1 368 Notes 1 The interval time is dependent on the CPU processin only 2 The interval time for data transfer is variable The minimum and maximum values of the interval time for transferring each data can be calculated by the following expressions n value placed in ADTIO through ADTI4 If the minimum value calculated by the following expression is less than 2 fsck however the minimum interval time is assumed to be 2 fsck 7 Minimum value n 1 x RA 0 fx fx fsck 7 Maximum value n 1 x 2 ie 15 fx fx fsck Cautions 1 Do not write data to ADTI while the automatic transmit receive function is in use Remark 2 Be sure to set bits 5 and 6 to 0 3 To control the interval time for data transfer of automatic transmission reception by using ADTI busy control becomes invalid refer to 17 4 3 4 a Busy control option fx Main system clock oscillation frequency fsck Serial clock frequency CHAPTER 17 SERIAL INTERFACE CHANNEL 1 Figure 17 5 Format of Automatic Data Transmit R
33. 0 5 fsck 378 4 us 1 5 fsck 389 6 us 0 5 fsck 391 2 us 1 5 fsck 402 4 us 0 5 fsck 404 0 us 1 5 fsck 415 2 us 0 5 fsck 416 8 us 1 5 fsck Note The interval time for data transfer is variable The minimum and maximum values of the interval time for transferring each data can be calculated by the following expressions n value placed in ADTIO through ADTI4 however the minimum interval time is assumed to be 2 fsck If the minimum value calculated by the following expression is less than 2 fsck 7 Minimum value n 1 x z 29 aS fx fx fsck i 1 Maximum value n 1 x z ie 2 fx fx fsck Cautions 1 Do not write data to ADTI while the automatic transmit receive function is in use 2 Be sure to set bits 5 and 6 to 0 3 To control the interval time for data transfer of automatic transmission reception by using ADTI busy control becomes invalid refer to 17 4 3 4 a Busy control option Remark fx Main system clock oscillation frequency fsck Serial clock frequency 378 al UNO CHAPTER 17 SERIAL INTERFACE CHANNEL 1 2 Setting of automatic transmit receive data a b Setting of transmit data lt 1 gt Write the transmit data from the lowest address FACOH of the buffer RAM up to FADFH However the data must be transmitted from the high order address to the low order address lt 2 gt Set the value of the number of transmit data
34. 23 x 1 fx 800 ns 218 x 1 fx 26 2 ms 22 x 1 fx 400 ns 24 x 1 fx 1 6 us 219 x 1 fx 52 4 ms 23 x 1 fx 800 ns Remarks 1 fx Main system clock oscillation frequency 2 TCLO4 TCLOG Bits 4 through 6 of timer clock select register O TCLO 3 At fx 10 0 MHz operation Figure 8 19 Square Wave Output Timing Countclock LJ LJ LI bJ LILI LI LI LI bJ LI LI LI TMO count value ___0000X0001X0002X XN 1X N X0000X0001X 0002X XN 1X N X 0000 A Count starts o OO ONOS TOQNote l Note The initial value of TOO output can be set by LVSO and LVRO 196 i ri NY a lu ed CHAPTER 8 16 BIT TIMER EVENT COUNTER 8 6 Notes on Using 16 Bit Timer Event Counter 1 Error on starting timer An error of up to 1 clock occurs after the timer has been started until a coincidence signal is generated This is because the 16 bit timer register TMO is started in asynchronization with the count pulse Figure 8 20 Start Timing of 16 Bit Timer Register compas NY NY MS MS AL TMO count value Timer starts 2 Setting of 16 bit compare register Set a value other than OOOOH to the 16 bit compare register CROO Therefore one pulse cannot be counted when the 16 bit timer event counter operates as an event counter 3 Operation after changing value of compare register during timer count operation If a new value of the 16 bit compare register CROO is less than the value of the 16 bit timer register TMO TMO continu
35. 4 8 HHHH Ri Y e N Z H a o a P f j OO 7 i t di A c rH Y bj COMA f g A AA AA A AA A AAA eee ITEM MILLIMETERS INCHES ITEM MILLIMETERS INCHES A 18 4 0 724 a 00 3 0 012 B 0 65x15 9 75 0 026x0 591 0 384 b 1 85 0 073 C 0 65 0 026 c 3 5 0 138 D 7 75 0 305 d 2 0 0 079 E 10 15 0 400 e 3 9 0 154 F 12 55 0 494 f 1 325 0 052 G 14 95 0 589 9 1 325 0 052 H 0 65x15 9 75 0 026x0 591 0 384 h 5 9 0 232 I 11 85 0 467 i 0 8 0 031 J 18 4 0 724 j 2 4 0 094 K C 2 0 C 0 079 E A oo L 12 45 0 490 TGK 064SBW GOE M 10 25 0 404 N 7 7 0 303 O 10 02 0 394 P 14 92 0 587 Q 11 1 0 437 R 1 45 0 057 S 1 45 0 057 T 4 91 3 4 60 051 U 1 8 0 071 V 5 0 0 197 w 05 3 0 209 X 4 C 1 0 4 C 0 039 Y 03 55 0 140 Z 00 9 00 035 note Product by TOKYO ELETECH CORPORATION 508 APPENDIX C EMBEDDED SOFTWARE For efficient program development and maintenance of u PD78018F and 78018FY subseries the following embedded softwares are available 509 APPENDIX C EMBEDDED SOFTWARE Real Time OS 1 2 RX78K 0 RX 78K 0 is a real time OS conforming to the uITRON specifications Real time OS Tool configurator for generating nucleus of RX78K 0 and plural information tables is supplied Used in combination with an optical assembler package RA78 0 and device file DF78014 lt Precaution when using RX78K 0 in PC environment gt The real time OS is a DOS based application It should be used in the
36. CHAPTER 19 EXTERNAL DEVICE EXTENSION FUNCTI 2 Memory size select register IMS This register sets the capacities of the internal ROM and internal high speed RAM Set IMS to the value at reset When the external device extension function of the PD78018F or 78018FY is used set the internal ROM capacity to 56K bytes or less IMS is set by using an 8 bit memory manipulation instruction The value of this register is as shown in Table 19 3 at RESET Figure 19 3 Format of Memory Size Select Register Symbol 7 6 Address At reset R W 5 4 3 2 1 0 IMS RAM2 RAM1 RAMO 0 ROMS ROM2 ROM1 IROMO FFFOH Note WwW ROMO Selects internal ROM capacity 8K 16K bytes 24K bytes 32K bytes 40K bytes 48K bytes 56K bytes 60K bytes Setting prohibited Selects internal high speed RAM capacity 512 bytes 1024 bytes Setting prohibited Note The value of this register at reset differs depending on the model refer to Table 19 3 Table 19 3 Value of Memory Size Select Register on Reset Part Number uPD78011F 78011FY Set Value of IMS uPD78012F 78012FY uPD78013F 78013FY HPD78014F 78014FY uPD78015F 78015FY HPD78016F 78016FY uPD78018F 78018FY 431 al UNO CHAPTER 19 EXTERNAL DEVICE EXTENSION FUNCTION 19 3 Timing of External Device Extension Function The timing control signal
37. CMOS input 2 lines CMOS I O 47 lines Port lines to which internal pull up resistor can be connected via software 47 lines N ch open drain I O 4 lines 15 V pull up resistor can be connected by mask option to mask ROM model only 4 lines A D converter 8 bit resolution x 8 channels Low voltage operation AVop 1 8 to 5 5 V Serial interface 3 wire serial I O 2 wire serial 1 O 12C bus mode selectable 1 channel 3 wire serial l O mode with automatic transmit receive function of up to 32 B 1 channel 16 bit timer event counter 1 channel 8 bit timer event counter 2 channels e Watch timer 1 channel e Watchdog timer 1 channel Timer output 3 lines 14 bit PWM output 1 line Clock output 39 1 kHz 78 1 kHz 156 kHz 313 kHz 625 kHz 1 25 MHz with main system clock 10 0 MHz 32 768 kHz with subsystem clock 32 768 kHz Buzzer output 2 4 kHz 4 9 kHz 9 8 kHz with main system clock 10 0 MHz Notes 1 The capacities of the internal PROM and internal high speed RAM can be changed by using memory size select register IMS 2 The capacity of the internal extension RAM can be changed by using internal extension RAM size select register IXS 64 CHAPTER 2 GENERAL uPD78018FY SUBSERIES Part Number HPD78011FY uPD78012FY uPD78013FY uPD78014FY uPD78015FY uPD78016FY uPD78018FY uPD78P018FY 4 Vectored Maskable Internal 8 external interrupt Non maskable I
38. Don t care PMxx Port mode register Pxx Output latch of port 338 R W An interrupt request signal is generated each time a serial transfer is executed in all modes When in I C bus mode after the start condition is detected CMDD 1 if the received address coincides with the slave address register SVA an interrupt request signal is generated Data of slave address register SVA does not coincide with data of serial I O shift register 0 SIOO Data of slave address register SVA coincides with data of I O shift register O SIOO R W Stops operation Enables operation Notes 1 Set bit 5 SIC of the interrupt timing specification register SINT to 1 when using the wake up function Do not execute an instruction that writes the serial I O shift register 0 S100 while WUP 1 2 COI is 0 when CSIE 0 b Serial bus interface control register SBIC The SBIC is set by using a 1 bit or 8 bit memory manipulation instruction This register is set to OOH when the RESET signal is input Symbol lt 7 lt 3 gt lt 2 gt lt l gt lt 0 gt Address Onreset R W so A en om am R W Used to output stop condition in 12C bus mode SOO0 latch is set to 1 when RELT 1 After SOO latch has been set this bit is automatically cleared to 0 It is also cleared to 0 when CSIE 0 R W Used to output start condition in 12C bus mode SO0 latch is cleared to 0 when CMDT 1 After SOO latch has been cleared this bit i
39. J a nued ii NU 8 5 2 Operation as PWM output coococoncccnocicoccconcconnncnncnnnnncnnnn nn n cnn narran rra 8 5 3 Operation as pulse width measurement coccncccnccnncccnnccnonnnnnnnnnnn nono nnnn cnn rca rca 8 5 4 Operation as external event COUNTER cococccincccnccnonnconccnnnccnnncnnn cnn nan nn cnn aran 8 5 5 Operation as square WAVE OUtPUt ooooccinnccnnnoconccnonnnncccnonncnnnannn cnn cn nnn cnn nn rnn carr crac 8 6 Notes on Using 16 Bit Timer Event Counter ooomcconncnccnonnnnnnncncnnenennnornncc enano ranas CHAPTER 9 8 BIT TIMER EVENT COUNTER cccccssesseesceesceeeensensnnssnescoeeeeseeseensensennsnsanoaees 9 1 Function of 8 Bit Timer Event Counter ooccccnnccncnonnnccnnnnnnnnnnonnnnnnnncnnrnnnnnnenrnnnnanen rra 9 1 1 8 bit timer event counter MOE ccccccnnnncnocucouononononnnnnononnonononononononcnnoninnnnnnannnn a eaa eaaa 9 1 2 16 bit timer event counter mode cccoccnnnnonanocononononoonnnonononononnnnnncncnononennnnananann ono nonnnrnnnnenenons 9 2 Configuration of 8 Bit Timer Event Counter moonnnncncnconnnnnnnccccnnsrnnnna renacer 9 3 Registers Controlling 8 Bit Timer Event Counter ommcccinnncnnncnnccosnnnnnnnecanerenanrrennenennn os 9 4 Operation of 8 Bit Timer Event Counter monmcicccnnnonnnnnccnnncnnner cancer 9 4 1 8 bit timer event COUNTER Mode isc ii 9 4 2 16 bit timer event counter mode cccoccnnnnnnanuconononononnnnonononononnnnnncnnncnonennnnnnanannr ono nonrnnnnonenennns 9 5 Notes on Using 8 Bit
40. N gt YY Y Y E a TCL22 TCL21 TCL20 Timer clock select register 2 Internal bus WDTM WDTM Watchdog timer mode register INTWDT maskable interrupt request RESET INTWDT non maskable interrupt request g3INIL SOGHOLVM LL YALdVHO al UNO CHAPTER 11 WATCHDOG TIMER 11 3 Registers Controlling Watchdog Timer The following two registers control the watchdog timer e Timer clock select register 2 TCL2 Watchdog timer mode register WDTM 1 Timer clock select register 2 TCL2 refer to Figure 11 2 This register sets the count clock of the watchdog timer TCL2 is set by an 8 bit memory manipulation instruction This register is set to OOH when the RESET signal is input Remark TCL2also has a function to set the count clock of the watch timer and the frequency of buzzer output in addition to the function to set the count clock of the watchdog timer 232 CHAPTER 11 WATCHDOG TIMER Symbol TCL2 7 6 5 4 3 2 1 0 TCL27 TCL26 TCL25 roL24 o ToL TCL21 TCL20 Figure 11 2 Format of Timer Clock Select Register 2 Address On reset R W FF42H 00H R W fx 24 625 kHz fx 25 313 kHz fx 28 156 kHz fx 2 78 1 kHz fx 28 39 1 kHz fx 29 19 5 kHz fx 2 0 9 8 kHz fx 212 2 4 kHz TCL24 Selects count clock of watch timer O fx 28 39 1 kHz 1 fxr 82 768 kHz TCL26
41. P10 P17 Port 1 ANIO ANI7 8 bit I O port Can be specified for input output bitwise When used as input port internal pull up resistor can be connected by software Note 2 Port 2 8 bit I O port Can be specified for input output bitwise When used as input port internal pull up resistor can be connected by software SI0 SBO SO0 SB1 Notes 1 Touse the P04 XT1 pin as an input port line set the bit 6 FRC of the processor clock control register PCC to 1 do not use the internal feedback resistor of the subsystem clock oscillation circuit 2 When using the P10 ANIO through P17 ANI7 pins as the analog input lines of the A D converter set port 1 to input mode The internal pull up resistors are automatically disconnected 67 CHAPTER 3 PIN FUNCTIONS uPD78018F SUBSERIES 1 Port pins 2 2 Pin Name Function On Reset Shared by P30 Port 3 Input TOO P31 8 bit I O port 101 Can be specified for input output bitwise When used as input port internal pull up resistor can be connected TO2 P33 by software TH P34 Tl2 P35 PCL P36 BUZ P37 P40 P47 Port 4 ADO AD7 8 bit I O port Can be specified for input output in 8 bit units When used as input port internal pull up resistor can be connected by software Test input flag KRIF is set to 1 at falling edge of these pins P32 P50 P57 Port 5 8 bit I O port Can directly drive LED Can be specified for input output bitwise
42. Part Number Package Quality Grade uPD78011FCW A XXX 64 pin plastic shrink DIP 750 mil Special uPD78011FGC A XXX AB8 64 pin plastic QFP 14 x 14 mm Special uPD78012FCW A XXX 64 pin plastic shrink DIP 750 mil Special uPD78012FGC A XXX AB8 64 pin plastic QFP 14 x 14 mm Special HPD78013FCW A XXX 64 pin plastic shrink DIP 750 mil Special HPD78013FGC A XXX AB8 64 pin plastic QFP 14 x 14 mm Special H4PD78014FCW A XXX 64 pin plastic shrink DIP 750 mil Special 1PD78014FGC A XXX AB8 64 pin plastic QFP 14 x 14 mm Special HPD78015FCW A XXX 64 pin plastic shrink DIP 750 mil Special HPD78015FGC A XXX AB8 64 pin plastic QFP 14 x 14 mm Special HPD78016FCW A XXX 64 pin plastic shrink DIP 750 mil Special HPD78016FGC A XXX AB8 64 pin plastic QFP 14 x 14 mm Special H4PD78018FCW A XXX 64 pin plastic shrink DIP 750 mil Special H4PD78018FGC A XXX AB8 64 pin plastic QFP 14 x 14 mm Special HPD78P018FCW A 64 pin plastic shrink DIP 750 mil Special 4PD78P018FGC A AB8 64 pin plastic QFP 14 x 14 mm Special H4PD78012FGC A2 XXX AB8 64 pin plastic QFP 14 x 14 mm Special Remark XXX indicates ROM code suffix Please refer to Quality Grades on NEC Semiconductor Devices Document No C11531E published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications 39 CHAPTER 1 GENERAL 1 PD78018F SUBSERIES 1 5 Pin Configuration Top View 1 Normal operation mode 40
43. U11801J U11801E Structured Assembly Language U11789E U11789E RA78K Series Structured Assembler Preprocessor U12323J EEU 1402 CC78K0 C Compiler Operation U11517J U11517E Language U11518J U11518E CC78K 0 C Compiler Application Note Programming Know how U13034J EEA 1208 CC78K Series Library Source File U12322J PG 1500 PROM Programmer U11940J EEU 1335 PG 1500 Controller PC 9800 Series MS DOS Base EEU 704 EEU 1291 PG 1500 Controller IBM PC Series PC DOS Base EEU 5008 U10540E 1E 78K0 NS Planned Planned 1E 78001 R A Planned Planned IE 78KO R EX1 Planned Planned 1E 78018 NS EM1 Planned Planned 1E 78014 R EM A EEU 962 EEU 1487 EP 78240 EEU 986 U10332E EP 78012GK R EEU 5012 EEU 1538 SM78K0 System Simulator Windows Base Reference U10181J U10181E SM78K Series System Simulator External Part User Open Interface Specifications U10092J U10092E 1D78K0 NS Integrated Debugger Reference U12900J Planned ID78K 0 Integrated Debugger EWS Base Reference U11151d 1D78K0 Integrated Debugger PC Base Reference U11539J U11539E 1D78K0 Integrated Debugger Windows Base Guide U11649J U11649E Caution The contents of the above related documents are subject to change without notice Be sure to use
44. When MOV A HL B Instruction code 10101011 5 4 10 Stack addressing Function This addressing is to indirectly address the stack area by using the contents of the stack pointer SP This addressing is automatically used to save restore register contents when the PUSH POP subroutine call or return instruction is executed or when an interrupt request is generated The stack addressing can access the internal high speed RAM area only Example When PUSH DE is executed Instruction code 10110101 131 MEMO 132 i rir lv ed CHAPTER 6 PORT FUNCTIONS 6 1 Functions of Ports The uPD78018F 78018FY subseries is provided with two input port pins and 51 I O port pins Figure 6 1 shows these port pins Each port can be manipulated in 1 bit or 8 bit units and controlled in various ways Moreover some port pins also serve as the I O pins of the internal hardware Figure 6 1 Types of Ports Port 0 Port 3 P37 Port 4 P40 P47 Port 1 P50 Port 5 Port 2 Port 6 133 CHAPTER 6 PORT FUNCTIONS Pin Name Port 0 POO P01 P02 P03 P04 Table 6 1 Port Functions uPD78018F Subseries Function 5 bit 1 O port Input only Shared by INTPO TIO Can be specified for input output bitwise When used as input port internal pull up resistor can be connected by software INTP1 INTP2 INTP3 Input only XT1 P10 P17 8 bit I O port Can be spec
45. When used as input port internal pull up resistor can be connected by software Port 6 N ch open drain I O port 8 bit I O port Connection of internal pull up resistor can Can be specified for input be specified by mask option with mask output bitwise ROM model only Can directly drive LED When used as input port internal pull up resistor can be connected by software 68 CHAPTER 3 PIN FUNCTIONS uPD78018F SUBSERIEY 2 Pins other than port pins 1 2 Pin Name INTPO INTP1 INTP2 INTP3 Function External interrupt request input for which valid edge can be specified rising edge falling edge and both rising and falling edges Falling edge detection external interrupt request input On Reset Input Shared by POO TIO P01 P02 P03 SIO Sit Serial data input of serial interface P25 SBO P20 SOO SO1 Serial data output of serial interface P26 SB1 P21 SBO SB1 Serial data I O of serial interface P25 SI0 P26 SO0 SCKO SCK1 Serial clock I O of serial interface P27 P22 STB Output Strobe output for serial interface automatic transmission reception P23 BUSY Input Busy input for serial interface automatic transmission reception P24 TIO TH TI2 Input External count clock input to 16 bit timer TMO External count clock input to 8 bit timer TM1 External count clock input to 8 bit timer TM2
46. i y Serial bus interface Serial operation mode register 0 control register CSIE CSIM CSIM CSIM CSIM CSIM Slave address ee register SVA eee sio sBo P25 gt PM25 SVAM Y CLRSET D Q ZX control S00 SB1 P26 D gt Busy PM26 acknowledge Bus release output circuit control P26 output latch command acknowledge detection circuit WUP Coincidence Serial register P25 output latch Interrupt gt request signal pee generation ale circuit TO2 Serial clock heitan CSIMOO CSIMOO CSIMO1 CSIMO1 TCL TCL TCL TCL Interrupt timing Timer clock select specification register register 3 SCKO P27 go A P27 output latch SAIMSSAENS 48108407 0 TANNVHO AJ0VSYALNI IVIHIS SI HILAVHO Internal bus Remark The output control selects CMOS output or N ch open drain output CHAPTER 15 SERIAL INTERFACE CHANNEL 0 uPD78018F SUZ 1 2 Serial I O shift register 0 SIOO This 8 bit register converts parallel data into serial data and transmits receives serial data shift operation in synchronization with the serial clock SIOO is set by an 8 bit memory manipulation instruction When the bit 7 CSIEO of the serial operation mode regis
47. saddr byte saddr saddr A byte A r AeA r r A rer A A saddr A amp A saddr A laddr16 A amp A adadr16 A HL A HL byte A lt AA HL byte A HL B A amp A HL A lt A HL B A HL C A A HL C A byte A lt AVbyte saddr byte saddr saddr V byte A r A lt cAVr nA rervA A saddr A amp AV sadar A laddr16 VO INDN IN N O0O N N N ND A AV addr16 A HL A amp AV HL A HL byte A amp AV HL byte A HL B A lt AV HL B A HL C A lt AV HL C A byte A amp AY byte saddr byte saddr saddr V byte A r A lt cAvVr nA rervaA A saddr A lt AY saddr A laddr16 VO NDN N N 0O N ND N N A AY addr16 A HL A HL byte A lt AY HL byte A HL B A A HL B A HL C hp hy YM A lt A HL A lt A HL C Notes 1 When the internal high speed RAM area is accessed or when an instruction that does not access data is executed 2 When an area other than the internal high speed RAM area is accessed 3 Exceptr A Remarks 1 One clock of an instruction is equal to one CPU clock fcru selected by processor clock control
48. 00H R W Interval time controlled by ADTI ADTIO ADTI4 ADTI3 ADTI2 ADTI1 Specifies interval time for data transfer fx 10 0 MHz operation Minimum value ote 2 18 4 us 0 5 fsck Maximum valueNote 2 20 0 us 1 5 fsck 31 2 us 0 5 fsck 32 8 us 1 5 fsck 44 0 us 0 5 fsck 45 6 us 1 5 fsck 56 8 us 0 5 fsck 58 4 us 1 5 fsck 69 6 us 0 5 fsck 71 2 us 1 5 fsck 82 4 us 0 5 fsck 84 0 us 1 5 fsck 95 2 us 0 5 fsck 96 8 us 1 5 fsck gt O O o O O O 108 0 us 0 5 fsck 109 6 us 1 5 fsck 120 8 us 0 5 fsck 122 4 us 1 5 fsck 133 6 us 0 5 fsck 135 2 us 1 5 fsck 146 4 us 0 5 fsck 148 0 us 1 5 fsck 0 0 0 0 0 0 0 0 0 0 0 0 159 2 us 0 5 fsck 160 8 us 1 5 fsck 172 0 us 0 5 fsck 173 6 us 1 5 fsck 184 8 us 0 5 fsck 186 4 us 1 5 fsck 197 6 us 0 5 fsck 199 2 us 1 5 fsck O O LO 0 210 4 us 0 5 fsck 212 0 us 1 5 fsck i rN a lu ed CHAPTER 17 SERIAL INTERFACE CHANNEL 1 Notes 1 The interval time is dependent on the CPU processin only 2 The interval time for data transfer is variable The minimum and maximum values of the interval time for transferring each data can be calculated by the following expressions n value placed in ADTIO through ADT14 If the minimum value calculated by the following expre
49. 2 SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT FF61H 00H R W R W SOO0 latch is set to 1 when RELT 1 After setting SOO latch RELT is automatically cleared to 0 This bit is also cleared to 0 when CSIEO 0 R W SO0 latch is cleared to 0 when CMDT 1 After clearing SOO latch CMDT is automatically cleared to 0 This bit is also cleared to 0 when CSIEO 0 CSIEO Bit 7 of the serial operation mode register O CSIMO 273 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 uPD78018F SUBSERIEF 2 Communication operation In the 3 wire serial l O mode data is transmitted received in 8 bit units Data is transmitted received on a 1 bit by 1 bit basis in synchronization with the serial clock The shift operation of the serial I O shift register 0 SIOO is performed in synchronization with the falling edge of the serial clock SCKO The transmitted data is retained by the SOO latch and output from the SOO pin The receive data input to the SIO pin is latched to SIOO at the rising edge of SCKO When the 8 bit data has been completely transferred the operation of SIOO is automatically stopped and an interrupt request flag CSIIFO is set Figure 15 6 Timing of 3 Wire Serial I O Mode SCKO SIO SO0 CSIIFO Transfer ends iis Transfer starts in synchronization with falling edge of SCKO The SOO pin serves as a CMOS output pin and outputs the status of the SO latch The output status of the SOO pin can be manipulated
50. 210 240 244 Port mode register 5 PM5 149 Port mode register 6 PM6 149 Priority specification flag register OH PROH 408 Priority specification flag register OL PROL 408 Processor clock control register PCC 160 Program status word PSW 102 412 Pull up resistor option register PUO 152 S Sampling clock select register SCS 187 410 Serial bus interface control register SBIC 268 377 286 305 319 325 330 339 Serial I O shift register 0 SIOO 263 313 Serial I O shift register 1 S101 362 Serial operation mode register 0 CSIMO 265 271 272 284 303 316 323 324 328 338 Serial operation mode register 1 CSIM1 364 370 371 373 16 bit capture register CRO1 180 16 bit compare register CROO 180 16 bit timer mode control register TMCO 181 16 bit timer output control register TOCO 184 16 bit timer register TMO 180 16 bit timer register TMS 205 Slave address register SVA 263 313 T Timer clock select register 0 TCLO 181 238 Timer clock select register 1 TCL1 206 Timer clock select register 2 TCL2 222 232 242 Timer clock select register 3 TCL3 265 316 363 W Watch timer mode control register TMC2 225 Watchdog timer mode register WDTM 234 514 APPENDIX D REGISTER INDEX D 2 Register Index In Alphabetical Order with Respect to Register Symbol A ADCR A D con
51. 515 APPENDIX E REVISION HISTORY conmmcociccccnncccccccccnnrnnnncrccarrnnna rre 517 23 LIST OF FIGURES 1 7 Figure No Title Page 3 1 VO Gircuits Of PINS ura ia pdas 77 4 1 OUCirCuits Of PINS 5 es oie io e ade See ane ed Se a 89 5 1 Memory Map UPD78011F 78011 FY cooncocincccncccnoccnoncnnnnncnnnananc nono n nan ccn cnn 91 5 2 Memory Map UPD78012F 78012FY cooncccincccncccnocnnoncnnnnncnnnananc conc cnn cnn cnn cnn crac 92 5 3 Memory Map UPD78013F 78013FY cr eea ianiai a aaaea aeii iR E cnn 93 5 4 Memory Map 1PD78014F 78014FY oc eceeecceeeeeeeeeceeeeteeeeeeeeeeaeesaeeseaeeseeeeaeeeeeseeeeeeeteaes 94 5 5 Memory Map uPD78015F 78015FY sssssesssessesseesresresirererrerrrsrrstirsinettnsinstnntnstnsnnsrnsennt 95 5 6 Memory Map UPD78016F 78016FY cocooccincccnccccoccnoncnnnnncnnnnnancconc crac cnn cnn cnn rn rca 96 5 7 Memory Map UPD78018F 78018FY eccceecceeseeeeeeeeeeeceeeeeeeeeeeeeaeeseaeeseeseaeeseeseeeeeeeeeaes 97 5 8 Memory Map uPD78P018F 78PO18FY cecceseceeeeeeseeeeeeeeeeeeeeaeeeeescaeeseeeseaeeseaeeeaeetsae 98 5 9 Program Counter Configuration cceeccsesceseeeceeeeeeeeeeecneeeeaeeeeeeeeaeeseeeeeaeeseaeeeaeessaeeseeeenaees 102 5 10 Program Status Word Configuration ecceeceeseceeeceeeeeeeeeeeeeeeeeeeeeeaeeeaeeseaeeeeeeseaeesseeeeaees 102 5 11 Stack Pointer Configura Oia 103 5 12 Data Saved to Stack Memory coooococcccnocccoccconcconnnonnccconcnnnnnrnn cn nn nc nn nr n cnn 104 5 13 Data
52. 8 bit I O port Can directly drive LED Can be specified for input output bitwise When used as input port internal pull up resistor can be connected by software Port 6 N ch open drain I O port 8 bit I O port Connection of internal pull up resistor can Can be specified for input be specified by mask option with mask output bitwise ROM model only Can directly drive LED When used as input port internal pull up resistor can be connected by software 80 CHAPTER 4 PIN FUNCTIONS uPD78018FY SUBSERIE 2 Pins other than port pins 1 2 Pin Name INTPO INTP1 INTP2 INTP3 Function External interrupt request input for which valid edge can be specified rising edge falling edge and both rising and falling edges Falling edge detection external interrupt request input On Reset Input Shared by POO TIO P01 P02 P03 SIO Sit Serial data input of serial interface P25 SB0 SDA0 P20 SOO SO1 Serial data output of serial interface P26 SB1 SDA1 P21 SBO SB1 SDAO SDA1 Serial data I O of serial interface P25 SI0O SDAO P26 SO0 SDA1 P25 SI0 SBO P26 SO0 SB1 SCKO SCK1 SCL Serial clock I O of serial interface P27 SCL p22 P27 SCKO STB Strobe output for serial interface automatic transmission reception P23 BUSY Busy input for serial interface automatic transmission reception P24 TIO TH TI2 External count clo
53. Clears the output latch of the P25 pin to 0 because the output latch of the P25 pin must be cleared to 0 in the 12C bus mode Sets the P25 pin in the output mode because the P25 pin must be in the output mode in the 12C bus mode Remark RELT Bit 0 of serial bus interface control register SBIC CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78018FY S 16 4 7 Manipulating SCK0 SCL P27 pin output The SCK0 SCL P27 pin can perform static output through software manipulation in addition to the normal serial clock output The value of serial clocks can be set by software the SIO SBO SDAO and SO0 SB1 SDA1 pins are controlled by the RELT and CMDT bits of the serial bus interface control register SBIC The following describes how to manipulate the SCKO SCL P27 pin output 1 In 3 wire serial I O mode or 2 wire serial I O mode The output level of the SCKO SCL P27 pin is manipulated by the P27 output latch lt 1 gt Set serial operation mode register 0 CSIMO SCKO pin output mode serial operation enabled SCKO 1 when serial transfer is stopped lt 2 gt Manipulate the P27 output latch by using a bit manipulation instruction Figure 16 26 Configuration of SCKO SCL P27 Pin Operated by bit manipulation instruction P27 output latch Cl SCKO 1 when transfer is stopped From serial clock control circuit SCKO SCL P27 O 2 gt gt To internal circuit When CSIEO 1 and CSIMO1 CSIMOO are 1 0 or
54. In this mode P40 through P47 function as an 8 bit I O port which can be set in the input or output mode in 8 bit units by using the memory extension mode register MM When used as an input port an internal pull up resistor can be used if so specified by the pull up resistor option register PUO 2 Control mode In this mode P40 through P47 function as the low order address data bus pins ADO AD7 in the external memory extension mode The pins used as address data bus pins are automatically disconnected from the internal pull up resistor 85 CHAPTER 4 PIN FUNCTIONS uPD78018FY SUBSERIES 4 2 6 P50 P57 Port5 These pins form an 8 bit I O port port 5 which also serves as an address bus These pins can directly drive LEDs Port 5 can be set in the following operation modes in 1 bit units 1 2 Port mode In this mode P50 through P57 constitute an 8 bit I O port which can be set in the input or output mode in 1 bit units by using the port mode register 5 PM5 When used as an input port an internal pull up resistor can be used if so specified by the pull up resistor option register PUO Control mode In this mode P50 through P57 function as the high order address bus pins A8 A15 in the external memory extension mode The pins used as address bus pins are automatically disconnected from the internal pull up resistor 4 2 7 P60 P67 Port6 These pins constitute an 8 bit I O port port 6 which can be also used t
55. This chapter lists the instruction set of the u PD78018F and 78018FY subseries For the details of the operation and machine language instruction code of each instruction refer to 78K 0 Series User s Manual Instruction U12326E 477 CHAPTER 24 INSTRUCTION SET 24 1 Legend 24 1 1 Operand representation and formats In the operand field of each instruction an operand is written according to the format for operand representation of that instruction for details refer to the assembler specifications Some operands may be written in two or more formats In this case select one of them Uppercase characters and are keywords and must be written as is The meanings of the symbols are as follows immediate data e relative address e absolute address e indirect address To write immediate data also use an appropriate numeric value or label To write a label be sure to use or Register formats r or rp for an operand can be written as a function name such as X A or C or absolute name the name in parentheses in the table below such as RO R1 or R2 Table 24 1 Operand Representation and Formats r X RO A R1 C R2 B R3 E R4 D R5 L R6 H R7 rp AX RPO BC RP1 DE RP2 HL RP3 sfr Special function register symbolNote sfrp Special function register symbol only even address of register that can be manipulated in 16 bit units Note saddr FE20H FF1FH immed
56. Voo 1 8 to 5 5 V 35 CHAPTER 1 GENERAL 1 PD78018F SUBSERIES 1 2 Application Field 1PD78011F 78012F 78013F 78014F 78015F 78016F 78018F 78P018F Telephones VCRs audio sets cameras home appliances etc 1PD78011F A 78012F A 78012F A2 78013F A 78014F A 78015F A 78016F A 78018F A 78P018F A Control unit of automotive appliances gas leak breaker safety devices etc 3 Ordering Information 1 Standard grade products including not applicable products Part Number Package Internal ROM uPD78011FCW XXX 64 pin plastic shrink DIP 750 mil Mask ROM uPD78011FGC XXX AB8 64 pin plastic QFP 14 x 14 mm Mask ROM uPD78011FGK XXX 8A8 64 pin plastic LQFP 12 x 12 mm Mask ROM uPD78012FCW XXX 64 pin plastic shrink DIP 750 mil Mask ROM uPD78012FGC XXX AB8 64 pin plastic QFP 14 x 14 mm Mask ROM uPD78012FGK XXX 8A8 64 pin plastic LQFP 12 x 12 mm Mask ROM uPD78013FCW XXX 64 pin plastic shrink DIP 750 mil Mask ROM uPD78013FGC XXX AB8 64 pin plastic QFP 14 x 14 mm Mask ROM uPD78013FGK XXX 8A8 64 pin plastic LQFP 12 x 12 mm Mask ROM uPD78014FCW XXX 64 pin plastic shrink DIP 750 mil Mask ROM uPD78014FGC XXX AB8 64 pin plastic QFP 14 x 14 mm Mask ROM uPD78014FGK XXX 8A8 64 pin plastic LQFP 12 x 12 mm Mask ROM uPD78015FCW XXX 64 pin plastic shrink DIP 750 mil Mask ROM uPD78015FGC XXX AB8 64 pin plastic QFP 14 x 14 mm Mask ROM uPD78015FGK XXX 8A8 64 pin plastic LQFP 12 x 12 mm Mask
57. byte A CY lt A HL byte A HL B A CY lt A HL B A HL C A CY A HL C Notes 1 When the internal high speed RAM area is accessed or when an instruction that does not access data is executed 2 When an area other than the internal high speed RAM area is accessed 3 Exceptr A 4 Only when rp BC DE HL Remarks 1 One clock of an instruction is equal to one CPU clock fcru selected by processor clock control register PCC 2 The number of clocks shown is when the program is stored in the internal ROM area 3 n indicates the number of wait states when the external memory extension area is read 4 m indicates the number of wait states when the external memory extension area is written 481 CHAPTER 24 INSTRUCTION SET Instruction Mnemonic Operand A byte Operation A CY lt A byte CY saddr byte saddr CY saddr byte CY A r A CY lt A r CY nA r CY r A CY A saddr A CY lt A saddr CY A laddr16 A CY lt A addr16 CY A HL A HL byte A CY lt A HL byte CY A HL B A CY lt A HL CY A CY lt A HL B CY A HL C A CY lt A HL C CY A byte A CY lt A byte saddr byte saddr CY lt saddr byte A r A CY A r r A r CYer A
58. disable TT Voo Type 10 A Voo bs Pullu Ara o oe Pullup Do i a enable Voo Vo a Data tT pf p ch Data off P ch Output Open drain disable Output disable IN OUT IN OUT Input enable Type 5 E Type 11 Pullup Pullup enable E enable po Vpop Voo Data t f Do gt P on Data E E 0 IN OUT Output x N ch disable Pchy op Comparator IN OUT Output disable Vrer Threshold voltage Input enable 89 CHAPTER 4 PIN FUNCTIONS uPD78018FY SUBSERIES Figure 4 1 I O Circuits of Pins 2 2 Type 13 B haa option 40 IN OUT Feedback cut off Data Output disable o N ch P ch ve MN ry A hd AD Ez P e gt lt Medium withstanding voltage input buffer 90 HO IN OUT Data Output disable RD Medium withstanding voltage input buffer 5 1 Memory Space CHAPTER 5 CPU ARCHITECTURE Each model in the uPD78018F 78018FY subseries can access a memory space of 64 KB Figures 5 1 through 5 8 show memory maps of the respective models Data memory space Program memory space Figure 5 1 Memory Map uPD78011F 78011FY Special function register SFR 256 x 8 bits General purpose register 32 x 8 bits Internal high speed RAM 512 x 8 bits
59. internal extension RAM by using the main program After the main program has been started the comparator in the ROM correction circuit always compares the value in CORADO or CORAD1 with the fetch address value When the two address values coincide a correction branch processing request signal is generated At the same time the correction status flags CORSTO and CORST1 are set to 1 Execution branches to address F7FDH by the correction branch processing request signal The whole address space branch instruction at address F7FDH causes execution to branch to the address in the internal extension RAM set by the main program If only one place is to be corrected execute the correction program If two places must be corrected check the correction status flag by operation of the branch destination identification program and then branch to the correction program al UNO CHAPTER 22 ROM CORRECTION Figure 22 7 Operation of ROM Correction Internal ROM program starts ROM correction Coincidence between fetch address and correction address Yes Sets correction status flag Correction branch processing branches to address F7FDH Executes correction program 22 5 Example of Using ROM Correction Here is an example of using ROM correction to change instruction ADD A 1 at address 1000H to ADD A 2 Figure 22 8 Example of Using ROM Correction Internal ROM Internal extension RAM 0000H
60. master and slave 2 3 b Data Processing in master device S100 write SIO0 lt FFH S100 lt FFH BSYE ACKE CMDT RELT CLC WREL SIC INTCSIO SCL ESOT 1 21 8 14 5 D7 06 XD5AD4 D3 SDAO See Processing in slave device in slave device Eje jejej Ly Liir T SIOO write i ae data col OOOO 00000 ACKD 25 E i o O O O a Es ap IMMNNNA MN P27 ns WUP BSYE ACKE CMDT RELT CLC WREL SIC INTCSIO CSIEO P25 PM25 PM27 ee ee ee ee ee ee G 350 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78018FY S Figure 16 22 Example of Communication from Slave to Master with 9 clock wait selected for both master and slave 3 3 c Stop condition Processing in master device SIOO write SIO0 FFH SIO0 address col ODODOSO 000 ACKD CMDD RELD L CLD P27 H WUP L BSYE ACKE A CMDT A RELT A 13 a O E WREL L EN sic rr o INTCSIO TOA SCL pannan lh ham SDAO _D7 XD8XD5XD4XD3XD2XD1 X00 iS y YN JAS XA5XA4 XAS r SIOO data SlOg write A T RY E NA col DEE UD e do CEN E CEN CTE UE Ge a 2 ACKD APA CMDD ee ee pfs a RELD ee ee a co AMARA ue ie ay WUP BSYE b ACKE poi El CMDT L LE RELT L a clo L PA WREL _ A INTCSIO CSIEO H P25 L PM25 _L PM27 L 351 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78018FY SUBSERI7 9 16 4 5 1 352 Transfer start Serial transfer is started w
61. register PCC 2 The number of clocks shown is when the program is stored in the internal ROM area 3 n indicates the number of wait states when the external memory extension area is read 483 CHAPTER 24 INSTRUCTION SET Instruction Mnemonic Operand A byte Operation A byte saddr byte saddr byte A r r A A saddr A laddr16 A HL A HL byte A HL B A HL C A HL C 16 bit AX word AX CY amp AX word operation AX word AX CY amp AX word AX word AX lt AxX AX word Multiply divide Nijin a o o n AX quotient C remainder AX C Increment rer t decrement saddr saddr 1 rer 1 saddr saddr 1 rperp i rp rp 1 CY A7 lt Ao Am 1 lt Am x 1 time CY Ao lt Az Am 1 Am x 1 time CY lt Ao A7 lt CY Am 1 lt Am x 1 time AJAIAJA Jojolo a ojo CY lt A7 Ao CY Am 1 Am x 1 time N o 24 2n 2m A3 o lt HL 3 o HL 7 4 A3 o HL s 0o HL 7 4 N o 24 2n 2m A3 0 lt HL 7 4 HL s 0 lt A3 o HL 7 4 HL 3 o Notes 1 When the internal high speed RAM area is accessed or when an instruction that does not access data is executed 2 When an area other than the internal high speed RAM area is accessed 3
62. set TCLOO through TCLO3 and then set CLOE to 1 by using a 1 bit memory manipulation instruction Read the count value from TMO not from the 16 bit capture register CRO1 when TIO is used as the count clock of TMO Before writing data other than that already written to TCLO stop the timer operation fx Main system clock oscillation frequency fxt Subsystem clock oscillation frequency TIO Input pin of 16 bit timer event counter TMO 16 bit timer register At fx 10 0 MHz or fxt 32 768 kHz operation 239 i ri oY a lv ed CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT 2 Port mode register 3 PM3 This register sets the input output mode of port 3 in 1 bit units When the P35 PCL pin is used as a clock output function set 0 to the PM35 bit of this register and the output latch of the P35 pin PMS is set by a 1 bit or 8 bit memory manipulation instruction This register is set to FFH when the RESET signal is input Figure 12 4 Format of Port Mode Register 3 Symbol 7 6 5 4 3 2 1 0 Address On reset R W PM3 PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30 FF23H FFH RW PM3n Selects I O mode of P3n pin n 0 7 0 Output mode output buffer ON 1 Input mode output buffer OFF 240 CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT 13 1 Function of Buzzer Output Control Circuit The buzzer output control circuit outputs a square wave with a frequency of 2 4 kHz 4 9 kHz or 9 8 kH
63. slave makes it low SCL of master SCL of slave SCL SDAO SDA1 D2 D1 l l l 3 Register setting The 12C bus mode is set by using the serial operation mode register 0 CSIMO serial bus interface control register SBIC and interrupt timing specification register SINT Output according to value set to ACKE in advance a Serial operation mode register 0 CSIMO CSIMO is set by using a 1 bit or 8 bit memory manipulation instruction This register is set to OOH when the RESET signal is input Symbol lt 7 gt lt 6 Address On reset R W gt lt 5 gt 4 3 2 1 0 CSIM CSIM CSIM CSIM CSIM Note 1 R W Selects clock of serial interface channel 0 External clock input to SCKO SCL pin Output of 8 bit timer register 2 TM2 Note2 Clock specified by bits 0 3 of timer clock select register 3 TCL3 Operation First bit S 0 S80 SDA0 P25 SO0 SB1 SDA1 P26 SCKO SCL P27 mode pin function pin function pin function wire serial er to 16 4 2 Operation in 3 wire serial I O mode pus 3 Note 3 2 wire serial P25 SB1 SDA1 SCKO SCK 1 O mode CMOS 1 0 N ch open N ch open or 12C bus drain I O drain I O mode Note 3 Note 3 SBO SDAO P26 x x N ch open CMOS 1 0 drain I O Cont d Notes 1 Bit 6 COI is read only 2 The clock frequency is 1 16 of the frequency output by TO2 in the 12C bus mode 3 This pin can be used freely as a port pin Remark x
64. wire XT2 and X1 so that they are not in parallel and to correct the IC pin between XT2 and X1 directly to Vss 164 CHAPTER 7 CLOCK GENERATION CIRCUIT 7 4 3 Divider circuit The divider circuit divides the output of the main system clock oscillation circuit fx to generate various clocks 7 4 4 When subsystem clock is not used When the subsystem clock is not necessary for a power saving operation or watch operation handle the XT1 and XT2 pins as follows XT1 Connect to Voo XT2 Open In this status however a tiny amount of current leaks via the internal feedback resistor of the subsystem clock oscillation circuit when the main system clock is stopped To suppress this leakage current it is possible to remove the above internal feedback resistor by using the bit 6 FRC of the processor clock control register PCC At this time process the XT1 and XT2 pins in the same manner as above 165 al UNO CHAPTER 7 CLOCK GENERATION CIRCUIT 7 5 Operation of Clock Generation Circuit The clock generation circuit generates the following clocks and control the operation modes of the CPU such as the standby mode e Main system clock fx e Subsystem clock fxrT e CPU clock fcru e Clock to peripheral hardware The operation of the clock generation circuit is determined by the processor clock control register PCC as follows a 166 The slowest mode 6 4 us at 10 0 MHz operation of the main system clo
65. 0 CSIMO CSIMO is set by using a 1 bit or 8 bit memory manipulation instruction This register is set to OOH when the RESET signal is input The shaded portion in the figure indicates the bits used in the operation stop mode Symbol lt 7 gt lt b gt lt 5 Address On reset R W gt 4 3 2 1 0 csimo csico col wuP FF60H 00H R W R W CSIEO Serial interface channel 0 operation control Stops operation Enables operation 271 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 uPD78018F SUBSERI 15 4 2 Operation in 3 wire serial I O mode This mode is useful for connecting peripheral I Os and display controllers that have the conventional clocked serial interface of the 75X XL series 78K series and 17K series In this mode communication is established by using three signal lines serial clock SCKO serial output SOO and serial input S10 1 Register setting The 3 wire serial I O mode is set by using the serial operation mode register 0 CSIMO and serial bus interface control register SBIC a Serial operation mode register 0 CSIMO CSIMO is set by a 1 bit or 8 bit memory manipulation instruction This register is set to OOH when the RESET signal is input Symbol 7 gt Address On reset R W co fs o pur pn nea e ian o oo ae R W Selects clock of serial interface channel 0 Clock externally input to SCKO pin Output of 8 bit timer register 2 TM2 Clock specified by bits 0 3 of timer clock select
66. 0080H Program starts ADD A 2 BR 11002H 1000H ADD A 1 1002H MOV B A lt 2 gt BR F702H lt 1 gt If 1000H placed in advance in the correction address register coincides with the fetch address value after the main program has started execution branches to address F7FDH lt 2 gt By placing the whole address space branch instruction BR addr16 at address F7FDH by operation of the main program execution branches to any address address F702H in this example lt 3 gt After executing the alternate instruction ADD A 2 execution returns to the internal ROM program 459 CHAPTER 22 ROM CORRECTION 22 6 Program Execution Flow Figures 22 9 and 22 10 show the sequence of program execution when ROM correction is used Figure 22 9 Program Sequence when only one place is corrected FFFFH F7FFH BR JUMP F7FDH lt 2 gt Correction program JUMP lt 3 gt lt 1 gt Internal ROM Place to be corrected xxxxH Internal ROM 0000H lt 1 gt Execution branches to address F7FDH when the fetch address and correction address coincide lt 2 gt Execution branches to the correction program lt 3 gt Execution returns to the internal ROM program Remark internal extension RAM JUMP correction program start address 460 CHAPTER 22 ROM CORRECTION Figure 22 10 Program Sequence when two places are corrected
67. 1 Control register Timer clock select register 2 TCL2 Watch timer mode control register TMC2 10 3 Registers Controlling Watch Timer The following two registers control the watch timer Timer clock select register 2 TCL2 Watch timer mode control register TMC2 1 Timer clock select register 2 TCL2 refer to Figure 10 2 This register sets the count clock of the watch timer TCL2 is set by an 8 bit memory manipulation instruction This register is set to 00H when the RESET signal is input Remark TCL2 also has a function to set the count clock of the watchdog timer and the frequency of buzzer output in addition to the function to set the count clock of the watch timer 222 Ezz Figure 10 1 Block Diagram of Watch Timer fx28 Selector fxt Selector TCL24 Timer clock select register 2 Internal bus fw 2 to 5 bit counter a Q 0 INTWT Clear 3 Ds INTTM3 a aes TMC26 TMC25 TMC24 TMC23 TMC22 TMC21 TMC20 Watch timer mode control register g3INIL HIOLVM OF YALdVHO CHAPTER 10 WATCH TIMER Figure 10 2 Format of Timer Clock Select Register 2 Symbol Address On reset R W TCL2 FF42H 00H R W TCL21 TCL20 Selects count clock of watchdog timer fx 24 625 kHz fx 25 313 kHz fx 28 156 kHz 7 6 5 4 3 2 1 0 TCL27 TCL26 TCL25 ToL24 o ToL TCL21 TCL20
68. 1 1 357 al UNO CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78018FY SUBSERI7 2 In 12C bus mode Manipulate the output level of the SCKO SCL P27 pin by using the CLC bit of the interrupt timing specification register SINT lt 1 gt Set serial operation mode register 0 CSIMO SCL pin output mode serial operation enabled Put 1 on the P27 output latch SCL 0 when serial transfer is stopped lt 2 gt Manipulate the CLC bit of SINT by using a bit manipulation instruction Figure 16 27 Configuration of SCKO SCL P27 Pin Set 1 SCKO SCL P27 O D gt gt To internal circuit P27 output latch a scoL From serial clock control circuit When CSIEO 1 and CSIM01 CSIMOO 1 0 or 1 1 Note The level of the SCL signal is in accordance with the contents of the logic circuit shown in Figure 16 28 Figure 16 28 Logic Circuit for SCL Signal CLC manipulated by bit manipulation instructions SCL Wait request signal Serial clock low level when transfer is stopped Remarks 1 This figure shows the relations of the signals and does not indicate the internal circuit 2 CLC bit 3 of interrupt timing specification register SINT 358 CHAPTER 17 SERIAL INTERFACE CHANNEL 1 17 1 Function of Serial Interface Channel 1 Serial interface channel 1 has the following three modes Operation Mode Operation stop mode Table 17 1 Modes of Serial Interface Channel 1 Pins Used
69. 1 7 R W SIC Selects interrupt source of INTCSIO Note 2 Address On reset R W FF63H 00H R Wnote 0 Sets CSIIFO at end of transfer by serial interface channel 0 4 Sets CSIIFO at end of transfer by serial interface channel 0 or on detection of bus release signal R Level of SCKO P27 pin Notes 0 Low level 1 High level Notes 1 Bit 6 CLD is a read only bit 2 Set SIC to 0 when using the wake up function in SBI mode 3 CLD is 0 when CSIEO 0 Caution Be sure to set bits 0 through 3 to 0 Remark SVA Slave address register CSIIFO Interrupt request flag corresponding to INTCSIO CSIEO Bit 7 of the serial operation mode register 0 CSIMO 270 i ar lu ed CHAPTER 15 SERIAL INTERFACE CHANNEL 0 uPD78018F SUS 15 4 Operation of Serial Interface Channel 0 Serial interface channel O operates in the following four operation modes Operation stop mode e 3 wire serial I O mode SBI mode 2 wire serial I O mode 15 4 1 Operation stop mode Serial transfer is not executed in this mode Consequently the power consumption can be reduced The serial I O shift register 0 SIOO can be used as an ordinary 8 bit register because it does not perform the shift operation In the operation stop mode the P25 SIO SBO P26 SO0 SB1 and P27 SCKO pins can be used as ordinary I O port pins 1 Register setting The operation stop mode is set by using the serial operation mode register
70. 10 Program Sequence when two places are corrected ceeeeceseeeeeeeeeeeeeeeeeeeeeeeeeeeeeeaeen 461 23 1 Format of Memory Size Select Register cecceeecceeseeseeeeeeeeeeeeeaeeeeeeeeeeseaeeseeeseeeeeeeeenees 466 23 2 Format of Internal Extension RAM Size Select Register ccccsceeseeeeeeereteeeeeeeeetees 467 23 3 Page Program Mode FlowcCharto occoncccnoncccnnonnccnoncnnnancnnnnnn cnn non nn nnnn o rn nan n nr rn r nr r rre rr nn nn 470 23 4 Page Program Mode Tide in a aa a 471 23 5 Byte Program Mode FlowChart eesceeeseeeessneeeeeneeeseneeeeseneeeeeaeeeseneeeseeaeeeseaeesenaeeenseeensaaes 472 23 6 Byte Program Mode Timing ooooonccccnnncnnnnnccnnonononnacnnnnn cnn none nc 473 23 7 PROM Read TIMO uta rinitis dildo aE A aAa 474 B 1 Development Tools diiniita at etd eli 496 B 2 EV 9200GC 64 Dimensions Reference eeccceeeeeeeeeeeeeeeeeeeeeceeeeeeeeeeeseaeeeeeeseaeeeeeeeeaeee 506 B 3 EV 9200GC 64 Recommended Pattern of Board Mounting Reference s es 507 B 4 TGK 064SBW Dimensions Reference ccccceeceeeceeeneeeeeeeneeeeaeeseeeseaeeseaeeeaeessaeeeeeetenees 508 30 LIST OF TABLES 1 3 Table No Title Page 1 1 Differences between Special Quality Models and A Models ccceeeceeeeeteeeeereteneees 50 1 2 Differences between A Model and A2 Model cccooccconoccccnoccncnonaninnonccnnnonconann cnc ranannnnn ono 51 1 3 Mask Option for Mask ROM Model c ooocccocccinccccoccconcconccc
71. 17 SERIAL INTERFACE CHANNEL 1 0 c ccccceesseeceeeesseeeeeensnneeeeenseeaeeeensnneeeenenss 359 17 1 Function of Serial Interface Channel 1 ccccssseccsseeeeeeseeeeseeeeeeseeseseeeeeeseesesneeeeneeeees 359 17 2 Configuration of Serial Interface Channel 1 cceecceseeeseneeeeeeeeesneeeeeneeeesneeeenseeeess 360 17 3 Registers Controlling Serial Interface Channel 1 csseeeeesseeseeeeeeeeeeesseeeeneeees 362 17 4 Operation of Serial Interface Channel 1 cccccesceeeeeeeseseeeeseeeeeeeessesneeeeneeesnseaeeeneeeeeas 370 17 431 Operation Stop Modes sci ile ple eer ede ea we een tne 370 17 4 2 Operation in 3 wire serial l O mode 0 ee eeececeeceeeeeeeeeeeneeeeeeeeeeeseaeeeeeeseaeesaeeenaeesieeenaeeesaeesas 371 17 4 3 Operation in 3 wire serial l O mode with automatic transmit receive function 373 CHAPTER 18 INTERRUPT FUNCTIONS AND TEST FUNCTIONS cs ccecsssseeeeeenseeeeeenees 401 18 1 Types of Interrupt FUNCTIONS 000 0 cece eeeete eee eeeeeee eee eeseeeeee ens neeeeeeeeseeeeeeseeseeeeeeeneneeeeneens 401 18 2 Interrupt Sources and Configuration ccccccecssseeseeeeeeeeesesneeeeeeeeeesseeeeenseeesseeeeneeeees 401 18 3 Registers Controlling Interrupt Function cccceseeeeeeeeeeeeeeeeeeeeeeeeneeeeneeeeesseeeeeeeeeeess 405 18 4 Interrupt Processing Operation ccccsssecceseeeessseeeeseeeessceeseseeeeeeseeseseeeeenseesesseeeneeeees 412 18 4 1 Non maskable
72. 28 156kHz fx 27 78 1kHz fx 28 39 1kHz fx 29 19 5kHz Others Setting prohibited Note Can be set only when the main system clock oscillates at 4 19 MHz or less Caution Before writing data other than that already written to TCL3 stop the serial transfer Remarks 1 fx Main system clock oscillation frequency 2 At fx 10 0 MHz 363 CHAPTER 17 SERIAL INTERFACE CHANNEL 1 2 Serial operation mode register 1 CSIM1 This register sets the serial clock and operation mode and enables disables the operation and automatic transmit receive operation of serial interface channel 1 CSIM1 is set by a 1 bit or 8 bit memory manipulation instruction This register is set to OOH when the RESET signal is input Figure 17 3 Format of Serial Operation Mode Register 1 Symbol lt 7 gt 6 lt 5 gt 4 3 2 1 0 Address On reset R W cam oeron re e Jo e ona wom so a CSIM11 cs M10 Selects clock of serial interface channel 1 Clock externally input to SCK1 pinNote 1 Output of 8 bit timer register 2 TM2 Clock specified by bits 4 7 of timer clock select register 3 TCL3 Selects operation mode of serial interface channel 1 0 3 wire serial I O mode 1 3 wire serial I O mode with automatic transmit receive function SI1 pin function SO1 pin function si1 P20 SO1 input CMOS output First bit Serial clock Note 2 x Note 2 x Note 2 x Not
73. 280 Port 63 ccs tel ee Be ce a a E aa 147 6 3 Registers Controlling Port Functions ccccssccesseeeeeseeeeseeeeeeseeeeseeeeenseeeeseseseseeneeeeas 149 6 4 Operation of Port Functions cccccecesesee cess cesses eeeeeeee nee sesneeeeeeneeeaneaeseneeeesseesenseeeeneas 155 6 4 1 Writingito VO ipo ia fishes ante texte deine ne ate ee need at 155 6 42 Reading from Oiport NN 155 6 4 3 Arithmetic operation Of I O POFt eee cece eeceeeneeeeeeeeeeeeeeeeeeeeseeseaeeseeeeaeeseeseaeeteeeseaeesieeeeaeees 155 6 5 Mask Option aaraa ace aci 156 CHAPTER 7 CLOCK GENERATION CIRCUIT cccccsscceeeeseseeeeensneeeeeeenseaeeeeenseeeseeensneseeeeenas 157 7 1 Function of Clock Generation Circuit ccccssccssseeeeeeeeeeseeeeeeeeeeeseeneeeseeeesseeeseseeneeeeas 157 7 2 Configuration of Clock Generation Circuit cceecceeceseeeeeeeeeeeeneeeeeneeeesnneeseneeeeneas 157 7 3 Register Controlling Clock Generation Circuit ccccccssseeeseeeeeseeeeeeeeeeseeeeseseeeeeneas 159 7 4 System Clock Oscillation Circuits ccccseceeeeeeeseseceeeeeeeeenesseseeeeesneeseseeeeeeeeeeenseeeensees 162 7 4 1 Main system clock oscillation CirCuit ooononccnnoniccnnncnnoncccnnoncnnnnrannnnrrnn nn nr nn rnnrn nana rn rr 162 7 4 2 Subsystem clock Oscillation circuit 00 2 eeceeeeeeeeeeeeeeeeeeeeeeeeeeeeeaeeseaeeeeeseaeeeneeteeeseeeseaeees 162 TA cDivider CirGult ii fis ced seeded Bh ri 165 7 4 4 When subsystem clock
74. 6 Detecting address coincidence 7 8 In the 12C bus mode the master can select a specific slave device by transmitting a slave address to it Whether the slave address output by the master coincides with the value of the slave address register SVA of a slave is automatically detected by hardware When the wake up function specification WUP is 1 and only if the slave address transmitted by the master coincides with the address set to the SVA CSIIFO Is set CSIIFO is also set when the stop condition is detected Set SIC to 1 when the wake up function is used Caution Whether a slave is selected or not is detected by coincidence of the data address received after the start condition To detect this coincidence an address coincidence detection interrupt INTCSIO that occurs when WUP 1 is usually used Therefore to enable detection of whether a slave is selected or not be sure that WUP 1 Error detection Because the status of serial bus SDAO SDA1 during transmission is also loaded to the serial I O shift register 0 SIOO in the 12C bus mode a transmission error can be detected in the following ways a By comparing SIOO data before and after transmission If the two data are different it is assumed that a transmission error has occurred b By using slave address register SVA The transmission data is placed in SIOO and SVA and transmission is executed After transmission has been completed the COI bit that indic
75. 79 4 1 List of Pin Functions ccoo cuncecee ccusccateteseceauetssersccectecerdbateresestccuersssscenessausebaterss 79 4 1 1 Pins in normal Operation mode oooccccoccccnoncccnoonnonanonnnnancnnn narco nono nnnnan ocn nn r nr rn r nn nar nr r nn 79 4 1 2 Pins in PROM programming mode uPD78PO18FY Only ococnccnnnccnnccnnnconnccnancnnanncanccnnnns 82 4 2 Description of Pin FUNCTIONS cccccecseeeeceeeeeeseeeeeeeeeseeeenneeseeeesseeeseeeeseeeseeessneeseeeeenenes 83 4 2 1 POO POA PortO ta ile ti ria 83 42 2 P10 P17 Pori A ee ee 83 4 29 P202P27 POMA sia tata dented didn eee ieee 84 4 2 4 P302P37 POMS in ane de david gral lent ae cies 85 4 2 5 P40 P47 Port4 Liar ida 85 4 26 P5O PS7 Portal 86 4 2 7 POO POZ POTG inthe ap aii id a ii 86 432 8 TAVARER Ea ti eee ee ee ee Ra aa tee enced 86 42 97 AN DD sek chee ee ee a N 86 42 AON ANV SS iea eneo aaee aidan cnet aitece in Mites eo E EAEN E peat bn Bates 86 O ald 87 4 2127 A AAA NN 87 A O E 87 NS ae aiid i a ede de eee ed 87 AsO AND VSS ciate ios sth Ae tas oe etl ee ie eh a en ie ee 87 4 2 16 Ver uPD78PO018FY only ici a iaeaea 87 4 2 17 IC mask ROM model only ccceeceeseeseeeeeeeeeeceeeeeeeeeeeeseeeeeaeesaeeseaeeseeseaeeseeeeeeseeeeeeesaaes 87 4 3 I O Circuits of Pins and Handling of Unused Pins csecceeseeesseeeeeeeeeeeseeeeeeeeeeneas 88 CHAPTER 5 CPU ARCHITECTURE sccccssssseceeensesceeesenssceceesnsneceeesense
76. Address address 1 atch Address c address 241 Address address 1 Latch lt X X 1 No 0 1 ms program pulse Verify Fail 4B Pass No Address N i gt Yes Voo 4 5 to 5 5V Ver Vop All bytes Fail gt verified All Pass Defective product End of write G start address N last address of program 470 CHAPTER 23 uPD78P018F 78P018FY Figure 23 4 Page Program Mode Timing Page data latch lt gt D D O EEES OO Hi Z wr DQOO 0Q00 Data input Data output Vep Vep Voo Voo 1 5 Voo Voo Vin CE Vit Vin PGM Vit Vin OE NY VI NY f f XA Vit Page program lt gt Program verify lt lt gt 471 CHAPTER 23 uPD78P018F 78P018FY Figure 23 5 Byte Program Mode Flowchart Start Address G Voo 6 5V VeP 12 5V X X 1 No Address address 1 0 1 ms program pulse Fail Yes Address N Voo 4 5 to 5 5V Ver Vop Fail gt All bytes verified All Pass End of write Defective product G start address N last address of program 472 CHAPTER 23 uPD78P018F 78P018FY Figure 23 6 Byte Program Mode Timing Program Program verify e gt Hi Z DO D7 da Data input Dern Data output E VPP Ver Voo Voo 1 5 Voo Voo Vin CE Vi Vin PGM Vi Vin OE Vit Cautions 1 Ap
77. Bit 6 of pull up resistor option register PUO P60 P63 pins can directly drive an LED P64 P67 pins are also used to output control signals in the external memory extension mode This port is set in the input mode when the RESET signal is input Figures 6 14 and 6 15 show the block diagrams of port 6 Cautions 1 P66 can be used as an I O port pins when no external wait state is used in the external memory extension mode 2 The value of the low level input leakage current flowing through P60 through P63 differs depending on the following conditions Mask ROM model e When pull up resistor is connected always 3 uA MAX e When pull up resistor is not connected For duration of 3 clocks without wait when a read instruction is executed to port 6 P6 or port mode register 6 PM6 200 yA MAX Others 3 uA MAX PROM model For duration of 3 clocks without wait when a read instruction is executed to port 6 P6 or port mode register 6 PM6 200 uA MAX Others 3 uA MAX 147 CHAPTER 6 PORT FUNCTIONS Figure 6 14 Block Diagram of P60 P63 Voo wig Mask option resistor Mask ROM model only Selector No pull up resistor is provided to PROM model tae a e P60 P63 Internal bus PM60 PM63 PM port mode register RD read signal of port 6 WR write signal of port 6 Figure 6 15 Block Diagram of P64 P67 Vo cig gt kes
78. Exceptr A Remarks 1 One clock of an instruction is equal to one CPU clock fcru selected by processor clock control register PCC 2 The number of clocks shown is when the program is stored in the internal ROM area 3 n indicates the number of wait states when the external memory extension area is read 4 m indicates the number of wait states when the external memory extension area is written 484 CHAPTER 24 INSTRUCTION SET Instruction i Clock aan Mnemonic Operand Operation Note 1 Note 2 BCD Decimal Adjust Accumulator after adjustment Addition Decimal Adjust Accumulator after Subtract Bit saddr bit manipulation sfr bit CY lt sadadr bit CY lt sfr bit CY Abit CY lt PSW bit CY HL bit A bit PSW bit CY HL bit saddr bit CY 16 saddr bit CY 16 sfr bit CY A bit CY 16 PSW bit CY 16 2n 2m HL bit CY 14 CY CY A sadar bit sfr bit CY A bit CY PSW bit CY HL bit CY CY saddr bit CY sfr bit 14 CY lt CY Asfr bit CY A bit CY PSW bit CY HL bit CY saddr bit CY sfr bit CY A bit CY PSW bit CY HL bit CY saddr bit CY CYAA bit 14 CY CYAPSW bit CY CYA HL bit CY CY V saddr bit CY CYVsfr bit CY CYVAbit CY CYVPSW bit CY CYV HL bit CY CY Y sadar bit CY CY Y sfr bit CY lt CYVA bit CY CY WPSW bit CY CY Y
79. FDOOH FCFFH Reserved FAEOH FADEN Internal buffer RAM FACOH 32 x 8 bits FABFH Reserved FA80H FA7FH External memory 55936 x 8 bits 2000H 1FFFH Internal ROM 8192 x8 bits 0000H did INIA Program area 1000H OFFFH CALLF entry area 0800H 07FFH Program area 0080H 007FH CALLT table area 0040H 003FH Vector table area 0000H 91 CHAPTER 5 CPU ARCHITECTURE Figure 5 2 Memory Map uPD78012F 78012FY a Special function register SFR 256 x 8 bits General purpose register 32 x 8 bits Internal high speed RAM 512 x 8 bits FDOOH 3FFFH FCFFH Reserved Program area FAEOH pata memory FADER Internal buffer RAM 1000H Space 32 x 8 bits OFFFH FACOH FABFH CALLF entry area Reserved 0800H FA80H 07FFH FA7FH Program area External memory 47744 x 8 bits 0080H 007FH Program memory oreo CALLT table area sre 0040H Internal ROM eet 16384 x8 bits Vector table area MA 0000H 0000H 92 CHAPTER 5 CPU ARCHITECTURE Figure 5 3 Memory Map uPD78013F 78013FY UN Special function register SFR 256 x 8 bits General purpose register 32 x 8 bits Internal high speed RAM 1024 x 8 bits FBOOH 5FFFH FAFFH Reserved Program area FAEOH Data memory FADER Internal buffer RAM 1000H space 32 x 8 bits OFFFH FACOH FABFH CALLF entry area Reserved 0800H FA80H 07FFH FA7FH Program area Exter
80. FFH R W PM2 PM27 PM26 PM25 PM24 PM23 PM22 PM21 PM20 FF22H FFH R W PM3 PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30 FF23H FFH R W PM5 PM57 PM56 PM55 PM54 PM53 PM52 PM51 PM50 FF25H FFH R W PM6 PM67 PM66 PM65 PM64 PM63 PM62 PM61 PM60 FF26H FFH R W Selects I O mode of Pmn pin m 0 1 2 3 5 6 n 0 7 0 Output mode output buffer ON 1 Input mode output buffer OFF 151 i rir lv ed CHAPTER 6 PORT FUNCTIONS 2 Pull up resistor option register PUO 152 This register sets whether the internal pull up resistor is connected to each port The internal pull up resistor can be connected only to the port pin which is specified by PUO to be connected to the internal pull up resistor and the bit which is set in the input mode The bit which is set in the output mode and is used as the analog input pin of the A D converter cannot be connected to the internal pull up resistor regardless of the setting of PUO PUO is set by a 1 bit or 8 bit memory manipulation instruction This register is set to OOH when the RESET signal is input Cautions 1 P00 and P04 pins are not provided with an internal pull up resistor 2 When using the multiplexed functions of ports 1 4 and 5 and P64 P67 pins the internal pull up resistor cannot be used even when PUOm is set to 1 m 1 4 6 3 P60 P63 pins of only the mask ROM model can be connected t
81. IC Internally Connected pins to Vss 2 Connect the AVob pin to Voo 3 Connect the AVss pin to Vss Remark uPD78P018F 42 CHAPTER 1 GENERAL uPD78018F SUBSERIES A8 A15 ADO AD7 ASTB ANIO ANI7 AVDD AVREF AVss BUSY BUZ IC P00 P04 P10 P17 P20 P27 P30 P37 P40 P47 P50 P57 P60 P67 Address Bus Address Data Bus Address Strobe Analog Input Analog Power Supply Analog Reference Voltage Analog Ground Busy Buzzer Clock Internally Connected INTPO INTP3 Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Interrupt from Peripherals PCL RD RESET SBO SB1 SCKO SCK1 Slo SI1 SOO SO1 STB TIO TI2 TOO TO2 WAIT WR X1 X2 XT1 XT2 Vpop VrP Vss Programmable Clock Read Strobe Reset Serial Bus Serial Clock Serial Input Serial Output Strobe Timer Input Timer Output Wait Write Strobe Crystal Main System Clock Crystal Subsystem Clolck Power Supply Programming Power Supply Ground Remark Vpp is for the uPD78P018F It is replaced by an IC pin for the mask ROM model 43 i ar ie ed CHAPTER 1 GENERAL 1 PD78018F SUBSERIES 2 PROM programming mode 64 pin plastic shrink DIP 750 mil u4PD78P018FCW 78P018FCW A 64 pin ceramic shrink DIP with window 750 mil u4PD78P018FDW O 1 O Vss O 2 O Voo O 3 O O 4 O Dio 5 O O 6 O O 7 o 0 O 8 O DO O
82. KRMK Controls standby mode by key return signal KRM FFF6H 02H R W 0 Enables releasing standby mode 1 Disables releasing standby mode Caution Be sure to clear KRIF to 0 by program when using the falling edge detection of port 4 This bit is not automatically cleared by hardware 18 5 2 Test input signal acceptance operation 1 Internal test input signal An internal test input signal INTWT is generated when the watch timer overflows and the WTIF flag is set by it At this time the standby release signal is generated if it is not masked by the interrupt mask flag WTMK By checking the WTIF flag in a cycle shorter than the overflow cycle of the watch timer the watch function can be effected 2 External test signal If a falling edge is input to a pin of port 4 P40 to P47 an external test input signal INTPT4 is generated setting the KRIF flag At this time the standby release signal is generated if it is not masked by the interrupt mask flag KRMK By using port 4 for key return signal input of a key matrix the presence or absence of a key input can be checked by the status of the KRIF flag 424 CHAPTER 19 EXTERNAL DEVICE EXTENSION FUNCTION 19 1 External Device Extension Function The external device extension function is to connect an external device to areas other than the internal ROM RAM and SFR areas To connect an external device ports 4 to 6 are used These ports control address data rea
83. Maximum value n 1 x 2 72 1 5 fx fx fsck Cautions 1 Do not write data to ADTI while the automatic transmit receive function is in use 2 Be sure to set bits 5 and 6 to 0 3 To control the interval time for data transfer of automatic transmission reception by using ADTI busy control becomes invalid refer to 17 4 3 4 a Busy control option Remark fx Main system clock oscillation frequency fsck Serial clock frequency 369 i rir lv ed CHAPTER 17 SERIAL INTERFACE CHANNEL 1 17 4 Operation of Serial Interface Channel 1 Serial interface channel 1 operates in the following three operation modes Operation stop mode e 3 wire serial I O mode e 3 wire serial I O mode with automatic transmit receive function 17 4 1 Operation stop mode Serial transfer is not executed in this mode Consequently the power consumption can be reduced The serial I O shift register 1 SIO1 can be used as an ordinary 8 bit register because it does not perform the sift operation In the operation stop mode the P20 SI1 P21 SO1 P22 SCK1 P23 STB and P24 BUSY pins can be used as ordinary I O port pins 1 Register setting The operation stop mode is set by using the serial operation mode register 1 CSIM1 CSIM1 is set by using a 1 bit or 8 bit memory manipulation instruction This register is set to 00H when the RESET signal is input Symbol lt 7 gt 6 Address On reset R W lt 5 gt 4 3 2 1 0 cow se on ME o To eR em
84. On chip UART capable of operating at low voltage 1 8 V _ Inverter control _ 64 pin J uPD780988 Es Inverter control timer SIO of the PD780964 were enhanced ROM RAM capacity increased 64 pin uPD780964 i A D converter of the uPD780924 was enhanced 64 pin wPD780924 e On chip inverter control circuit and UART EMI noise was reduced FIP drive E 100 pin The I O and FIP C D of the yPD78044F were enhanced Display output total 53 100 pin wPD780228 al The I O and FIP C D of the yPD78044H were enhanced Display output total 48 78K 0 80 pin y uPD78044H 7 An N ch open drain I O was added to the uPD78044F Display output total 34 Seres 80 pin uPD78044F Basic subseries for driving FIP Display output total 34 LCD drive 100 pin The SIO of the uPD78064 was enhanced and ROM RAM capacity increased 100 pin uPD78064B EMI noise reduced version of the 4PD78064 100 pin uPD78064 Basic subseries for driving LCDs on chip UART IEBus supported 80 pin EMI noise reduced version of the PD78098 80 pin An lEBus controller was added to the PD78054 Meter control 80 pin pd HPD780973 e On chip automobile meter driving controller driver Das e Note Under planning 61 CHAPTER 2 GENERAL 1 PD78018FY SUBSERIES The following lists the main functional differences between subseries products Subseries Name Control 1PD78078Y ROM Capacity 48 K 60 K HPD78070AY Serial Interface 3 wire 2 wire I2C 3 wire with automati
85. Operation as watchdog time sisirain an nana nenas 11 4 2 Operation as interval timer oo eee eecececeeeee cence ceeeeeaeeeeaeeeeeeeaaeeesaeeeaeeeseeseaeeeaeeeseeseaeeeeete CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT cccssseeceeseeseeeeeeeeeeeeseeeeenseeessseesenseeeneas 12 1 Function of Clock Output Control Circuit cccccseeeeeeseeeeseeeeeeeeeeeseeeeeeeeeeesseeeeeeeeees 12 2 Configuration of Clock Output Control Circuit ccccceeeeesseeeeeeeeeesneeeeeeeeeeeneeeeneeeees 12 3 Registers Controlling Clock Output FUNCTION ccceseeesseeeeeseeeeseeeeenseeeesseaeenseenenes CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT cccssecceeseeesseeeeeeeeeesseeeseeeeeeseseeseseeeeeeeas 13 1 Function of Buzzer Output Control Circuit ccccccseeeseseeeeseeeeeeeeeeeseeeeeseneeesneeeenseeens 13 2 Configuration of Buzzer Output Control Circuit cccceseeeeeeseeeeeeeeeeeeeeseeeeeeeeeeens 13 3 Registers Controlling Buzzer Output FUNCTION cccceseeeseeeeeeeeeeeseeeeeeeeeeesneeenseeeens CHAPTER 14 A D CONVERTER cccccseccssseeeeeeeeesesaeeeseeeeeesaeseseneeeeeaeeeaneaeenseeeesneaesaeeeeeessaeseneeenenes 1421 Function of A D CONVG rte iiss oc diran rt 14 2 Configuration of A D Converter conmnnicccninnnncncnncrrnrc rr 14 3 Registers Controlling A D Converter cccceeessseceseeeeeseneeesneeeeesneeesneeeeeeseeesseaeeenseenens 20 14 4 Operation of A D Converter ccccse
86. RAM 1024 x 8 bits F400H F3FFH Reserved FOOOH EFFFH Internal PROM 61440 x 8 bits 0000H Direct addressing Register indirect addressing Based addressing Based indexed addressing Note If the internal PROM capacity is 60 KB an area of FOOOH F3FFH cannot be used By setting the internal PROM capacity to 56 KB or less with the memory size select register IMS an area of FOOOH F3FFH can be used as an external memory area 122 TU 1 nued CHAPTER 5 CPU ARCHITECTURE a avert in UY 5 4 2 Implied addressing Function This addressing is to automatically implied address a register that functions as an accumulator A or AX in the general purpose register area Of the instruction words of the uwPD78018F and 78018FY subseries those that use implied addressing are as follows Instruction Register Specified by Implied Addressing MULU Register A to store multiplicand and register AX to store product DIVUW Register AX to store dividend and quotient ADJBA ADJBS Register A to store numeric value subject to decimal adjustment ROR4 ROL4 Register A to store digit data subject to digit rotation Operand Format No specific operand format is used because the operand format is automatically determined by an instruction Example MULU X The product between registers A and X is stored in register AX as a result of executing a multiply instruction of 8 bits x 8 bits In this o
87. READY status With SBI the slave informs the master of the busy status by making the SBO SB1 line low The busy signal is output following the acknowledge signal output by the master or the slave The busy signal is set or released in synchronization with the falling edge of SCKO The master automatically ends outputting serial clock SCKO when the busy signal is released The master can start the next transfer when the busy signal has been released and the ready signal is issued Caution SBI outputs the BUSY signal after the BUSY has been cleared and until the next serial clock falls If WUP is set to 1 by mistake during this period BUSY will not be cleared To set WUP to 1 therefore clear BUSY and make sure that the SBO SB1 pin has gone high 3 Register setting The SBI mode is set by the serial operation mode register 0 CSIMO serial bus interface control register SBIC and interrupt timing specification register SINT a Serial operation mode register 0 CSIMO CSIMO is set by a 1 bit or 8 bit memory manipulation instruction This register is set to OOH when the RESET signal is input 284 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 uPD78018F SUF Symbol CSIMO CSIEO R W R W lt 7 gt Address On reset R W Clock externally input to SCKO pin Output of 8 bit timer register 2 TM2 03 CSIM Clock specified by bits 0 3 of timer clock select register 3 TCL3 Operation f
88. Restored from Stack Memory ccecceseeeeeeeeseeeseeeeeeeeeaeeeeeeeaeeseeeeeaeeseaeeeaeeseaeeneeeeates 104 5 14 General Purpose Register Configuration oocccnnccinncninccnncnonccnonnconnnnonnconnnnncnn cnn anna cnn 106 5 15 Data Memory Addressing uPD78011F 78011FY oooccnnncccnnoccccnoncnonananonanannnnnrnnn nana nnnnnnnnnns 115 5 16 Data Memory Addressing uPD78012F 78012FY oo eee eeseeeeeneeeeeeneeeesaeeeeeeeeeeeneeeseneeees 116 5 17 Data Memory Addressing UuPD78013F 78013FY oooccnnoccccnnccccnoncnnnnannonanonnnnnn cnn nan nnnnnnnnnns 117 5 18 Data Memory Addressing 1PD78014F 78014FY ooocccnnocccnnocccononcnonannnononnnnnnnn cnn nar nnnnnnnnnnns 118 5 19 Data Memory Addressing uPD78015F 78015FY cooonccccccccoccnanccnnnncancnnnnn cnn cnnnn nc nn canario 119 5 20 Data Memory Addressing uPD78016F 78016FY coooccccncccnoccconcconnncancnnnnnconcnnnnn cnn ca nnncnnnn 120 5 21 Data Memory Addressing uPD78018F 78018FY ooooconnocccconccccnoncnonannnononnnnnnnn cnn nan nnnnnnnnnnns 121 5 22 Data Memory Addressing uPD78P018F 78PO18FY c coocconccccocccoccccnccnoncnnnnccancnnancnnncnnnnnnns 122 6 1 Ty pes or PornStars 133 6 2 Block Diagram of POO s 20 cates na ea a i ee Ae i 137 6 3 Block Diagram of PO12POS siii 138 6 4 Block Diagram of POM aiii Riiie ni 138 6 5 Block Diagram of P10 P 47 iii ta 139 6 6 Block Diagram of P20 P21 and P23 26 uPD78018F Subseries esceseeeeeeereeeeee 140 6 7 Block Diagram of P22 and
89. SIO1 Error during automatic transmission reception Controls error check of automatic transmit receive ERCE function 0 1 Disables error check during automatic transmission reception Enables error check during automatic transmission reception only when BUSY1 1 Single mode Repeat mode Controls reception of automatic transmit receive function Disables reception Enables reception Notes 1 Bits 3 and 4 TRF and ERR are read only bits 2 The completion of automatic transmission reception should be determined with TRF instead of CSIIF1 interrupt request flag Caution Set STRB and BUSY1 of ADTC to 0 0 when external clock input is selected by setting bit 1 CSIM11 of the serial operation mode register 1 CSIM1 to 0 handshake control cannot be performed when an external clock is input Remark x Don t care 375 CHAPTER 17 SERIAL INTERFACE CHANNEL 1 Symbol c Automatic data transmit receive interval specification register ADTI 7 This register sets the interval time at which data is transferred by the automatic transmit receive function ADTI is set by using a 1 bit or 8 bit memory manipulation instruction This register is set to OOH when the RESET is input Address ADTI ADTI7 AEAT ADTI4 ADTI3 ADTI2 ADTI1 ADTIO 376 ADTI7 Controls interval time for data transfer Interval time not controlled by ADTINote 1 FF6BH On reset R W
90. SVA bits used as slave address 0 4 Sets CSIIFO to 1 at end of transfer on serial interface channel 0 Sets CSIIFO to 1 at end of transfer on serial interface channel 0 or on detection of stop condition in 12C bus mode Level of SCKO SCL pin Note 2 0 Low level 1 High level Notes 1 Set SIC to 1 when using the wake up function in the 12C bus mode 2 CLD is 0 when CSIEO 0 Remark SVA Slave address register CSIIFO Interrupt request flag corresponding to INTCSIO CSIEO Bit 7 of the serial operation mode register O CSIMO CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78018FY Sp 4 Signals Table 16 5 lists the signals used in the 12C bus mode Signal Name Output Device Start condition Table 16 5 Signals in 12C Bus Mode Definition Falling edge of SDAO SDA1 when SCL is high Note 1 Output Condition Setting of CMDT Influence on Flag Sets CMDD Meaning of Signal Indicates that address is transmitted next and that serial communica tion is started Stop condition Rising edge of SDAO SDA1 when SCL is high Note 1 Setting of RELT Sets RELD Clears CMDD Indicates end of serial transmission Acknowledge Master slave signal ACK Low level signal of SDAO SDA1 output during 1 clock period of SCL after completion of serial reception ACKE 1 Setting of ACKT Sets ACKD Indicates that 1 byte has been completely received Wait WAIT Low le
91. Selector 188 i ar lu ed CHAPTER 8 16 BIT TIMER EVENT COUNTER Figure 8 11 Interval Timer Operation Timing t e l l l l 1 1 Count clock AAA e ana 4 Interrupt request accepted Interrupt request accepted i i i l TOO l Le gt lt gt lt gt i I i l Interval time Interval time Interval time i Remark Interval time N 1 xt N 0001H FFFFH Table 8 5 Interval Time of 16 Bit Timer Event Counter Minimum Interval Time Maximum Interval time Resolution 2 x TIO input cycle 216 x TIO input cycle TIO input edge cycle 22 x 1 fx 400 ns 217 x 1 fx 13 1 ms 2 x 1 fx 200 ns 23 x 1 fx 800 ns 218 x 1 fx 26 2 ms 22 x 1 fx 400 ns 24 x 1 fx 1 6 us 219 x 1 fx 52 4 ms 23 x 1 fx 800 ns Others Setting prohibited Remarks 1 fx Main system clock oscillation frequency 2 TCLO4 TCLOG Bits 4 through 6 of timer clock select register O TCLO 322 At fx 10 0 MHz operation 189 CHAPTER 8 16 BIT TIMER EVENT COUNTER 8 5 2 Operation as PWM output The 16 bit timer event counter performs PWM output when bits 1 through 3 TMC01 03 of the 16 bit timer mode control register TMCO are set to 1 0 0 and outputs a pulse whose duty ratio is determined by the value set to the 16 bit compare register CROO from the TOO P30 pin Set the active level width of the PWM p
92. T1 z SIO1 Transmit data 2 T2 Transmit data 3 T3 Lae Transmit data 4 T4 ee Transmit data 5 T5 FACOH Transmit data 6 T6 o CSIIF1 c When 7th byte has been transmitted FADFH FAC5H Transmit data 1 T1 Transmit data 2 T2 g we Transmit data 3 T3 PA a ae ete A 5 ADTP Transmit data 4 T4 Transmit data 5 T5 e FACOH Transmit data 6 T6 o CSIIF1 391 i rN a lu ed CHAPTER 17 SERIAL INTERFACE CHANNEL 1 d Stopping and resuming automatic transmission reception To temporarily stop automatic transmission or reception under execution reset bit 7 CSIE1 of the serial operation mode register 1 CSIM1 to O At this time transmission or reception is not stopped until transfer of 8 bit data has been completed When transmission or reception has been stopped bit 3 TRF of the automatic data transmit receive control register ADTC is reset to 0 after the data of the eighth bit has been transferred and all the port pins multiplexed with serial interface pins P20 SI1 P21 SO1 P22 SCK1 P23 STB and P24 BUSY are set in the port mode To resume automatic transmission reception set CSIE1 to 1 and write any value to the serial I O shift register 1 SIO1 This allows the rest of the data to be transferred Cautions 1 If the HALT instruction is executed during automatic transmission reception trans fer of 8 bit data even in progress is stopped
93. TCL25 Selects frequency of buzzer output Disables buzzer output fx 210 9 8 kHz fx 211 4 9 kHz fx 212 2 4 kHz Setting prohibited Caution Before writing new data to TCL2 stop the timer operation Remarks 1 2 3 4 fx fxT x Main system clock oscillation frequency Subsystem clock oscillation frequency Don t care At fx 10 0 MHz or fxt 32 768 kHz operation 233 i ri oY a lv ed CHAPTER 11 WATCHDOG TIMER 2 Watchdog timer mode register WDTM This register sets an operation mode of the watchdog timer and enables disables counting of the watchdog timer WDTM is set by a 1 bit or 8 bit memory manipulation instruction This register is set to OOH when the RESET signal is input Figure 11 3 Format of Watchdog Timer Mode Register Symbol 27 6 Address On reset R W 5 4 3 2 1 0 dl AAA e WDTM WDTM Selects operation mode of watchdog 4 3 timer Note 1 Interval timer modenote 2 overflow and maskable interrupt occur Watchdog timer mode 1 overflow and non maskable interrupt occur Watchdog timer mode 2 overflow occurs and reset operation started Selects operation of watchdog timer Note 3 0 Stops counting 1 Clears counter and starts counting Notes 1 Once WDTM3 and WDTM4 have been set to 1 they cannot be cleared to O by software 2 The watchdog timer starts operating as an interval timer as soon as the RUN bit h
94. TIMER 10 1 Functions of Watch Timer The watch timer has the following functions Watch timer Interval timer The watch timer and interval timer can be used at the same time 1 Watch timer The watch timer sets a flag WTIF at time intervals of 0 5 or 0 25 seconds by using the 32 768 kHz subsystem clock By using the 8 38 MHz main system clock the flag WTIF is set at a time interval of 0 5 or 0 25 seconds By using the 4 19 MHz 4 194304 MHz TYP main system clock the flag WTIF is set at a time interval of 0 5 or 1 seconds At the other frequencies the flag is not set at a time interval of 0 5 0 25 or 0 5 1 seconds Caution When the 8 38 MHz or 4 19 MHz system clock is used the time interval includes a slight error 2 Interval timer When the watch timer is used as an interval timer it generates an interrupt request INTTM3 at time intervals set in advance Table 10 1 Interval Time of Interval Timer Interval Time At fx 10 0 MHz At fx 8 38 MHz At fx 4 19 MHz At fxt 32 768 kHz 24 x 1 fw 2 x 1 fw 28 x 1 fw 27 x 1 fw 28 x 1 fw 29 x 1 fw Remark fx main system clock oscillation frequency fxt subsystem clock oscillation frequency fw watch timer clock frequency 221 i rN a lu ed CHAPTER 10 WATCH TIMER 10 2 Configuration of Watch Timer The watch timer consists of the following hardware Table 10 2 Configuration of Watch Timer Counter 5 bits x
95. This port is set in the input mode when the RESET signal is input Figure 6 5 shows the block diagram of port 1 i ri oY a lv ed Caution The internal pull up resistor cannot be connected to the pin that is used as the analog input pin a 5 a oO E o p of the A D converter Figure 6 5 Block Diagram of P10 P17 Output latch P10 P17 PM10 PM17 Voo Za De E o e PUO pull up resistor option register PM port mode register RD read signal of port 1 WR write signal of port 1 P10 ANIO P17 ANI7 139 CHAPTER 6 PORT FUNCTIONS 6 2 3 Port 2 uPD78018F subseries This is an 8 bit I O port with output latch P20 P27 pins can be specified in the input or output mode in 1 bit units by using the port mode register 2 PM2 When using P20 P27 pins as input port pins internal pull up resistors can be connected in 8 bit units by using the pull up resistor option register PUO The pins of this port are also used as the data I O pin clock I O pin busy signal input pin for automatic transmission reception and strobe signal output pin of the serial interface This port is set in the input mode when the RESET signal is input Figures 6 6 and 6 7 show the block diagrams of port 2 Cautions 1 When using the pins of port 2 as multiplexed pins the I O or output latch must be set according to the function to be used For how to set the latches r
96. Timer Event Counters ooommconacnccnonnnnnnnnnncnnenennnorenncn rra racer CHAPTER 10 WATCH TIMER c oooncocicnnnconnnnoncnnnannnnnn rra 10 1 Functions Of Watch Timer cccccceseseeeeeeseeeeeeeenseneeeeeeeseeneeeensneeeeeeeeseceneeeeseeeeeeeenseesneneees 10 2 Configuration Of Watch TimMer ssccccsccessseeeeeseeeeeeeeeeneeeeeseeesseseeeeeseeeseseaeeeneeeeensaeeenseeees 10 3 Registers Controlling Watch TimMer ccscecssseeeeseeeseseeeeseeeeeeseeseseeeeeeseesesseeeeneeeens 10 4 Operation Of Watch Timer ccccsseecceeeeeseseeeeeeeeeeseaeseeseeeeseaeeseneeeeeseessesnaeeeneeeeesnaeseneeeees 10 4 1 Operation as Watch timer ooo ee eece ee eceneeeeeeceeeeeeeeeeaeesaeeeeaeeeeeesseeseaeeeaeeseaeeeaeeseaeeteaeeeeete 10 4 2 Operation as interval timer oo eee eeece eee eeeeeeeneeceeeeeeeeseaeeeeeeeeeeeseaeseaeesaaeesaeeeneeeeeeseaeeeeeee CHAPTER 11 WATCHDOG TIMER sinccccccce ct sccecenedeecusecsceaceccencetessbecnctterecnnerecdadcegsncescensrsaceteceaecesen 11 1 Functions of Watchdog Timer cccccesseteeeeeeseeeeeeensneeeeeeenseceeeeeeeseneeeeensneeeeeeeeseeeeenenes 11 2 Configuration Of Watchdog Timer cccseccecseeeesseeeeeeeeeeeeeeeesneeeeeseeeesneaeeeeeeeeeseaeseneeeees 11 3 Registers Controlling Watchdog Timer ccsscccsseeeeesseeeeseeeeeeeeeseseeeeeeeeeeesseeenseeeess 11 4 Operation Of Watchdog TimMer ssccccsccessseeeeeseeeeseeeseneneeeseeeseenneeeeeeeeseseaeeeneeeeesnaesenseeees 11 41
97. WATO Controls wait and interrupt Note 2 Generates interrupt processing request at rising edge of 8th clock of SCKO clock output goes to high impedance state Setting prohibited Used in 1 C bus mode 8 clock wait Generates interrupt processing request at rising edge of 8th clock of SCL After outputting 8 clocks master makes SCL output low and waits After inputting 8 clocks slave makes SCL pin low and requests wait Used in 1 C bus mode 9 clock wait Generates interrupt processing request at rising edge of 9th clock of SCL After outputting 9 clocks master makes SCL output low and waits After inputting 9 clocks slave makes SCL pin low and requests wait R W WREL Controls releasing wait Wait released status Released wait status This bit is automatically cleared to 0 after wait status has been released used to release wait status set by WATO WAT1 R W Controls clock level Used in 1 C bus mode Makes output level of SCL pin low when serial transfer is not executed Used in C bus mode Puts output level of SCL pin in high impedance state when serial transfer is not executed the clock line is high Master uses this setting to make SCL high to generate start stop condition Cont d Notes 1 Bit 6 CLD is read only bit 2 Set WAT1 and WATO to 1 0 or 1 1 in the 12C bus mode 341 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78018FY SUBSERI7 342 R W SVAM
98. a 5 saws SIC INTCSIO SCL LE 4 ll ls hal 5 SDAO _W AEXASYAAXASXA2XATXAO W AG 07 DS XD5XD4XD3 SIO0 write _ col QO00008G 0000 ACKD Eoo i CMDD a RELD L CLD TE P27 E WUP pel BSYE CE ACKE CMDT RELT CLC WREL SIC INTCSIO CSIEO P25 PM25 PM27 Ij jr jp II Cri j TI 346 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78018FY S Figure 16 21 Example of Communication from Master to Slave with 9 clock wait selected for both master and slave 2 3 b Data Processing in master device SIO0 data SIO0 data SIO0 write col LXXXXXXAXXK SLAAN Co cmoo Csi RELD SS co MMMA 1 P27 H files os oe esye L T T A C emor Loo o ooo o O ol ge A ES co LP S S WREL SIC INTcslo LCC AO 11 12 18 14 5 16 7 81 99 11 21 8 14 5 SCL SDAO D7 XD6XD5XD4XD3XD2XD1 ADO CA D7 ADE ASADA ADS OEI ET IU EUR soe col DOCOOOOOXA DOODO poco LR cS a RELD 4 cop _ TLAinanyi A J UU UU UU gt P27 D O WUP BSYE a al ACKE CMDT RELT CLC WREL SIC INTCSIO CSIEO P25 PM25 PM27 Tiro jr fre ers T Lyre FAESA 347 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78018FY SUBSERI7 Figure 16 21 Example of Communication from Master to Slave with 9 clock wait selected for both master and slave 3 3 c Stop condition Processing in master device S100 write SIO0 data SIOO address col _ XX XXX XX K
99. a chip select signal command data and busy status when a serial bus consists of plural devices because only a data transfer function is provided To perform this control by software the work load of the software increases SBI can constitute a serial bus by using two signal lines serial clock SCKO and serial data bus SBO SB1 Therefore the number of ports of the microcomputer and the wiring length on the printed wiring board can be reduced effectively SBI has the following functions a Address command data identification function Serial data is identified as an address a command or data b Chip select status by address The master selects a slave chip by transferring an address to the slave c Wake up function The slave can easily judge that it has received an address chip select judgement by using the wake up function which can be set or released by software When the wake up function is set an interrupt request signal INTCSIO is generated when the slave receives an address that matches the address of the slave Therefore even when the master communicates with two or more devices the CPU of the slaves other than that selected can operate regardless of serial communication d Acknowledge signal ACK control function An acknowledge signal is controlled to check reception of serial data e Busy signal BUSY control function A busy signal that indicates the busy status of the slave is controlled i ar lu
100. are specified to serve as analog input pins the pull up resistor is automatically disconnected 83 CHAPTER 4 PIN FUNCTIONS uPD78018FY SUBSERIES 4 2 3 P20 P27 Port2 These pins constitute an 8 bit I O port port 2 In addition these pins are also used to input output the data of the serial interface input output a clock signal input a busy signal used for automatic transmission reception and output a strobe signal Port 2 can be specified in the following operation modes in 1 bit units 1 2 84 Port mode In the port mode P20 and P27 function as an 8 bit I O port Port 2 can be set in the input or output mode in 1 bit units by using the port mode register 2 PM2 When the port is used as an input port an internal pull up resistor can be used if so specified by the pull up resistor option register PUO Control mode In this mode P20 through P27 input output the data of the serial interface input output a clock input a busy signal for automatic transmission reception and output a strobe signal a SIO SI1 SOO SO1 SBO SB1 SDAO SDA1 These are the serial data I O pins of the serial interface b SCKO SCK1 SCL These are serial clock I O pins of the serial interface c BUSY This pin inputs the busy signal for the automatic transmit receive function of the serial interface d STB This pin outputs a strobe signal for the automatic transmit receive function of the serial interface Caution Wh
101. automatically saved to the stack At this time the IE flag is reset to 0 If a maskable interrupt request has been accepted the content of the priority flag of that interrupt is transferred to ISP flag The contents of PSW can also be saved to the stack by the PUSH PSW instruction and restored from the stack by RETI RETB or POP PSW instruction PSW is set to 02H when the RESET signal is input Figure 18 8 Configuration of Program Status Word Symbol 7 6 5 4 3 2 1 0 On reset o Le To Jus Te ono seer om gt Used when normal instruction is executed Priority of interrupt currently processed 0 Interrupt with higher priority is processed interrupt with lower priority is disabled Interrupt is not accepted or interrupt with lower 1 priority is processed all maskable interrupts are enabled ie Enables disables accepting interrupt request 0 Disables Enables 18 4 Interrupt Processing Operation 18 4 1 Non maskable interrupt request acceptance operation The non maskable interrupt request is unconditionally accepted even when interrupts are disabled It is not subject to interrupt priority control and takes precedence over all other interrupts When the non maskable interrupt request is acknowledged program status word PSW and program counter PC are saved to the stack in that order the IE flag and ISP flag are reset to 0 the contents of the vector table are loaded to the PC and then program execution
102. be stored and transported in an anti static container static shielding bag or conductive material All test and measurement tools including work bench and floor should be grounded The operator should be grounded using wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken for PW boards with semiconductor devices on it HANDLING OF UNUSED INPUT PINS FOR CMOS Note No connection for CMOS device inputs can be cause of malfunction If no connection is provided to the input pins it is possible that an internal input level may be generated due to noise etc hence causing malfunction CMOS devices behave differently than Bipolar or NMOS devices Input levels of CMOS devices must be fixed high or low by using a pull up or pull down circuitry Each unused pin should be connected to Voo or GND with a resistor if it is considered to have a possibility of being an output pin All handling related to the unused pins must be judged device by device and related specifications governing the devices STATUS BEFORE INITIALIZATION OF MOS DEVICES Note Power on does not necessarily define initial status of MOS device Production process of MOS does not define the initial operation status of the device Immediately after the power source is turned ON the devices with reset function have not yet been initialized Hence power on does not guarantee out pin levels I O settings or contents of registers Devi
103. branches Ifa new non maskable interrupt request is generated while the non maskable interrupt service program is executed the interrupt request is accepted when the current execution of the non maskable interrupt service program has been completed after the RETI instruction has been executed and one instruction in the main routine has been executed If two or more new non maskable interrupt requests are generated while the non maskable interrupt service program is executed only one non maskable interrupt requestis accepted after execution of the non maskable interrupt service program has been completed Figure 18 9 shows the flowchart from generation of the non maskable interrupt to accepting it Figure 18 10 shows the timing of accepting the non maskable interrupt and Figure 18 11 shows the operation performed if the non maskable interrupt occurs in duplicate 412 i a Wi red CHAPTER 18 INTERRUPT FUNCTIONS AND TEST FUNCT Figure 18 9 Flowchart of Non Maskable Interrupt Request from Generation to Acceptance WDTM4 1 watchdog timer mode is selected Interval timer WDT overflows WDTM3 0 non maskable interrupt is selected Reset processing Interrupt request is generated WDT interrupt is not processed Interrupt request pending Interrupt control register is not accessed Interrupt processing is started WDTM Watchdog timer mode reg
104. bytes minus 1 to the automatic data transmit receive address pointer ADTP Setting of automatic transmit receive mode lt 1 gt Set CSIE1 and ATE of the serial operation mode register 1 CSIM1 to 1 lt 2 gt Set RE of the automatic transmit receive control register ADTC to 1 lt 3 gt Set a data transmit receive interval to the automatic data transmit receive interval specification register ADTI lt 4 gt Write any value to the serial I O shift register 1 SIO1 transfer start trigger Caution Writing any value to SIO1 is to indicate the start of the automatic transmit receive operation and the written value has no meaning The following operation is automatically executed by performing a and b above After the data in the buffer RAM specified by ADTP has been transferred to SIO1 transfer is executed start of the automatic transmit receive operation Received data is written to an address of the buffer RAM specified by ADTP The contents of ADTP are decremented and the next data is transmitted received Data transmission reception is performed until the output of the decrementer of ADTP reaches OOH and the data at address FACOH is output end of the automatic transmit receive operation When the automatic transmit receive oeration is completed TRF is cleared to 0 379 i ar lu ed CHAPTER 17 SERIAL INTERFACE CHANNEL 1 3 Communication operation a Basic transmit receive mode This
105. captured until the valid edge is detected two times Consequently noise that may be superimposed on a pulse with a short pulse width can be eliminated Figure 8 16 Pulse Width Measurement Timing by Restarting Timer with both rising and falling edges specified l l I l l Comtoock T ITU U O O O O O O I TMO count vato 0000 X000 X oo Koog X K X Korpo TIO pin input AA i 1 Value captured to CROY A AR el oie e gt a gt i 1 T 1 DO 1 xt D1 1 xt l i i 194 i ri oY a lv ed CHAPTER 8 16 BIT TIMER EVENT COUNTER 8 5 4 Operation as external event counter The external event counter counts the number of clock pulses externally input to the TIO POO pin by using the 16 bit timer register TMO Each time the valid edge specified by the external interrupt mode register INTMO is input the value of TMO is incremented When the measured value of TMO coincides with the value of the 16 bit compare register CROO TMO is cleared to 0 and an interrupt request signal INTTMO is generated Set any other value other than 0000H to CROO one pulse count operation cannot be performed Three types of edges can be selected by bits 2 and 3 ES10 and ES11 of INTMO rising falling and both rising and falling edges To detect the valid edge sampling is performed at the cycle selected by the sampling clock select register SCS The value of TMO is not captured until the
106. control register ADTC 365 374 Automatic data transmit receive interval specification register ADTI 367 376 C Correction address register 0 CORADO 454 Correction address register 1 CORAD1 454 Correciton control register CORCN 455 E 8 bit compare register CR10 CR20 205 8 bit timer mode control register TMC1 208 8 bit timer output control register TOC1 184 8 bit timer register 1 TM1 205 8 bit timer register 2 TM2 205 External interrupt mode register INTMO 186 409 1 Internal extension RAM size select register IXS 467 Interrupt mask flag register OH MKOH 407 423 Interrupt mask flag register OL MKOL 407 Interrupt request flag register OH IFOH 406 423 Interrupt request flag register OL IFOL 406 Interrupt timing specification register SINT 270 288 305 321 330 340 K Key return mode register KRM 154 424 M Memory extension mode register MM 153 430 Memory size select register IMS 431 465 0 Oscillation stabilization time select register OSTS 440 P Port 0 PO 137 Port 1 P1 139 513 APPENDIX D REGISTER INDEX Port 2 P2 140 142 Port 3 P3 144 Port 4 P4 145 Port 5 P5 146 Port 6 P6 147 Port mode register 0 PMO 149 PMO Port mode register 1 PM1 149 Port mode register 2 PM2 149 Port mode register 3 PM3 149 185
107. control register PCC 2 Subsystem clock oscillation circuit This circuit oscillates a frequency of 32 768 kHz Oscillation cannot be stopped When the subsystem clock oscillation circuit is not used it can be set by using the processor clock control register PCC that the internal feedback resistor is not used so that the power consumption in the STOP mode can be reduced 7 2 Configuration of Clock Generation Circuit The clock generation circuit consists of the following hardware Table 7 1 Configuration of Clock Generation Circuit Control register Processor clock control register PCC Oscillation circuit Main system clock oscillation circuit Subsystem clock oscillation circuit 157 SSL XT1 P04 gt XT2 Figure 7 1 Block Diagram of Clock Generation Circuit FRC Subsystem clock fxt oscillation circuit gt Watch timer clock output function Prescaler Main system clock Prescaler Clock to peripheral oscillation hardware circuit fx fx fx fx 5 Standby Wait a control control gt CPU clock oO circuit circuit no To INTPO sampling clock SE A Processor clock control register Internal bus LINDYID NOILVYANAD YOO1D 4 YALdVHO i rir lu ed CHAPTER 7 CLOCK GENERATION CIRCUIT 7 3 Register Controlling Clock Generation Circuit The clock generation circuit is controlled by the processor clock
108. control register PCC This register selects the CPU clock and division ratio starts stops the operation of the main system clock oscillation circuit and sets whether the internal feedback resistor of the subsystem clock oscillation circuit is used or not PCC is set by a 1 bit or 8 bit memory manipulation instruction This register is set to 04H when the RESET signal is input Figure 7 2 Feedback Resistor of Subsystem Clock FRC P ch Feedback resistor Wt Po gt XT1 XT2 159 CHAPTER 7 CLOCK GENERATION CIRCUIT Figure 7 3 Format of Processor Clock Control Register Symbol lt 7 gt lt Address On reset R W 6 gt lt 5 gt lt 4 gt 3 2 1 0 ree us mo ors oss o rece rec roce R W FFFBH 04H R W Not Selects CPU clock fcru f 0 4 us fx 2 0 8 us f 2 1 6 us 23 3 2 us f 24 6 4 us fer 122 us Setting prohibited B CLS Status of CPU clock 1 0 Main system clock Subsystem clock R W FRC Selects feedback resistor of subsystem clock 0 Uses internal feedback resistor 1 Does not use internal feedback resistor R W aie F ote i MCC Controls oscillation of main system clock 0 1 Enables oscillation Stops oscillation Notes 1 Bit 5 is a read only bit 2 Tostop oscillation of the main system clock while the CPU operates on the subsystem clock use MCC Do not use the STOP inst
109. for control 42 44 pin uwPD78083 On chip UART capable of operating at low voltage 1 8 V z inverter control 64 pin a uPD780988 es Inverter control timer SIO of the PD780964 were enhanced ROM RAM capacity increased 64 pin s oe A D converter of the wPD780924 was enhanced 64 pin wPD780924 e On chip inverter control circuit and UART EMI noise was reduced FIP drive i 100 pin The I O and FIP C D of the yPD78044F were enhanced Display output total 53 100 pin e 1PD780228 el The I O and FIP C D of the yPD78044H were enhanced Display output total 48 78K 0 80 pin PD78044H An N ch open drain I O was added to the uPD78044F Display output total 34 Series 80 pin PD78044F Basic subseries for driving FIP Display output total 34 LCD drive 100 pin The SIO of the uPD78064 was enhanced and ROM RAM capacity increased 100 pin uPD78064B EMI noise reduced version of the yPD78064 100 pin uPD78064 Basic subseries for driving LCDs on chip UART IEBus supported 80 pin EMl noise reduced version of the uPD78098 80 pin An IEBus controller was added to the uPD78054 Meter control 80 pin wPD780973 On chip automobile meter driving controller driver A A Note Under planning 46 CHAPTER 1 GENERAL uPD78018F SUBSERIES The following lists the main functional differences between subseries products ROM Subseries Name Capacity Inverter control Meter control 4PD78075B 32 K 40 K Timer uP
110. for experiment or function evaluation only Remark XXX indicates ROM code suffix Please refer to Quality Grades on NEC Semiconductor Devices Document No C11531E published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications 55 CHAPTER 2 GENERAL 1 PD78018FY SUBSERIES 2 5 Pin Configuration Top View 1 Normal operation mode 64 pin plastic shrink DIP 750 mil u4PD78011FYCW XXX 78012FYCW XXX 78013FYCW XXX 1PD78014FYCW XXX 78015FYCW XXX 78016FYCW XXX UPD78018FYCW XXX 78P018FYCW 64 pin ceramic shrink DIP with window 750 mil uPD78P018FYDW P20 SI1 O 1 O AVREF P21 SO1 O 2 O AVoo P22 SCK1 O gt 3 O P17 ANI7 P23 STB O 4 O P16 ANI6 P24 BUSY O gt 5 O P15 ANI5 P25 SIO SBO SDAO O 6 O P14 ANI4 P26 SO0 SB1 SDA1 O 7 O P13 ANI3 P27 SCKO SCL O 8 O P12 ANI2 P30 TOO O O P11 ANI1 P31 TO1 O O P10 ANIO P32 TO2 O O AVss P33 T11 O gt O P04 XT1 P34 T12 O O XT2 P35 PCL O O IC Ver P36 BUZ O O X1 P37 O O X2 Vss O O Voo P40 ADO O O PO3 INTP3 P41 AD1 O O PO2 INTP2 P42 AD2 O O PO1 INTP1 P43 AD3 O lt gt O POO INTPO TIO P44 AD4 O O RESET P45 AD5 O O P67 ASTB P46 AD6 O O P66 WAIT P47 AD7 O O P65 WR P50 A8 O O P64 RD P51 A9 O O P63 P52 A10 O O P62 P53 A11 O O P61 P54 A12 O gt gt O P60 P55 A13 O O P57 A15 Vss O O P56 A14 Cautions 1 Directly connect the IC Internally Connected pins to Vss 2 Connect the AVob pin to Vpp 3 Connect t
111. i ar lu ed CHAPTER 7 CLOCK GENERATION CIRCUIT 7 5 1 Operation of main system clock When the main system clock is used when bit 5 CLS of the processor clock control register PCC is 0 the following operations are performed by the PCC setting a Because the operation guaranteeing instruction execution speed differs depending on the supply voltage the minimum instruction execution time can be changed by using the bits 0 2 PCCO PCC2 of PCC b Oscillation of the main system clock is not stopped even when bit 7 MCC of PCC is set to 1 when the microcontroller operates on the main system clock When bit 4 CSS of PCC is later set to 1 and then subsystem clock is selected CLS 1 oscillation of the main system clock is stopped refer to Figure 7 7 Figure 7 7 Stopping Main System Clock 1 2 a When CSS is set and then MCC is set during main system clock operation MCC css R y p CLS 4 Xf Oscillation of main system clock Oscillation of subsystem clock CPU clock D 167 CHAPTER 7 CLOCK GENERATION CIRCUIT Figure 7 7 Stopping Main System Clock 2 2 b When MCC is set during main system clock operation MCC D CSS E CLS E Oscillation does not stop Oscillation of main system clock Oscillation of subsystem clock pe MW Mn el aed We AA Aaa c When MCC is set and then CSS is set during main system clock oscillation D MCC CSS Q CLS p A Oscillation of main system clock Oscillation of
112. iS not used c coooccccconcccnnonncononnnonancnonanononnnn cnn nnnnnn nan nn nan nn nro nana n nano 165 7 5 Operation of Clock Generation Circuit oncccnninnnnnnnnncmnccinncrnnarernrrrnnce enn 166 7 5 1 Operation of main system clock oooococinnccincccnccnnncnnacnnonnnnnnnnnnnc coronan crac rr cancer 167 7 5 2 Operation of subsystem clock ooocinnncinnnnnnninnccccnnncncnnncnonccnnnncnn cnn arc cnn rra 169 7 6 Changing Setting of System Clock and CPU ClOCK cc cecccseseeeeeeeseceenenseeeenees 170 7 6 1 Time required for switching between system clock and CPU clock oooooococonoccccccoccccnoncnos 170 7 6 2 Switching between system clock and CPU clock ooooccconccincccocccnonananccnncncancnnnnnnnnccnnncnancnn 171 CHAPTER 8 16 BIT TIMER EVENT COUNTER cccs seccceseeeeeeeenseeeeeeeenseaeeeeensneeeeeeensenneeeenens 173 8 1 Outline of Timers in uPD78018F 78018FY Subseries ccsssecenesesseeeeeeeseeeeees 173 8 2 Functions of 16 Bit Timer Event Counter ccsseeeeeeeecesseeeeeeeeeeseaeeenseeeesseesseseeeeeeees 175 8 3 Configuration of 16 Bit Timer Event Counter cccseceesseeesneeeeeeeeeesneeeeeeeeeesneeeneees 176 8 4 Registers Controlling 16 Bit Timer Event Counter ccseccessecessseeeeeeeeeeeeeeseeeeeeeneas 181 8 5 Operation of 16 Bit Timer Event Counter cccsseeceeseeeesseeeenseeeeseeeeeeseeeessseeeeseeneeeeas 188 8 5 1 Operation as interval timet s diniinan a a aa a ai 188 19
113. identify the received data as an address command or data by hardware This function can simplify the application program which controls the serial interface channel 0 The SBI function is provided to some devices such as the 75X XL series and the 78K series Figure 15 9 shows an example of configuration of the serial bus when a CPU or peripheral IC with a serial interface conforming to SBI is used Because the serial data bus pin SBO SB1 in SBI is an open drain output pin the serial data bus line is wired ORed A pull up resistor is necessary for the serial data bus line When using the SBI mode refer to 11 Notes on SBI mode d 276 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 uPD78018F SUS Figure 15 9 Example of Serial Bus Configuration by SBI Vpop Serial clock LEA SCKO A SCKO Slave CPU Master CPU Serial data bus SBO SB1 SBO SB1 Address 1 SCKO Slave CPU e SBO SB1 Address 2 SCKO Slave IC SBO SB1 Address N Caution When the master is exchanged with a slave a pull up resistor is necessary for the serial clock line SCKO because switching over between the input and output mode of the serial clock line SCKO is performed asynchronously between the master and the slave 277 al UNO CHAPTER 15 SERIAL INTERFACE CHANNEL 0 uPD78018F SUBSERIER 1 Function of SBI 278 With the existing serial I O method many ports and wirings are necessary to identify
114. is input Symbol 27 lt B gt lt 5 gt lt 4 gt lt 3 gt lt 2 gt lt gt lt 0 gt Address Onreset R W SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT FF61H 00H R W R W SOO0 latch is set to 1 when RELT 1 After setting SOO latch RELT is automatically cleared to 0 This bit is also cleared to 0 when CSIEO 0 R W S00 latch is cleared to 0 when CMDT 1 After clearing SOO latch CMDT is automatically cleared to 0 This bit is also cleared to 0 when CSIEO 0 CSIEO Bit 7 of the serial operation mode register 0 CSIMO 325 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78018FY SUBSERI7 2 Communication operation In the 3 wire serial l O mode data is transmitted received in 8 bit units Data is transmitted received on a 1 bit by 1 bit basis in synchronization with the serial clock The shift operation of the serial I O shift register 0 SIOO is performed in synchronization with the falling edge of the serial clock SCKO The transmitted data is retained by the SOO latch and output from the SOO pin The receive data input to the SIO pin is latched to SIOO at the rising edge of SCKO When the 8 bit data has been completely transferred the operation of SIOO is automatically stopped and an interrupt request flag CSIIFO is set Figure 16 6 Timing of 3 Wire Serial I O Mode SCKO SIO SO0 CSIIFO Transfer ends t Transfer starts in synchronization with falling edge of SCKO The SOO pin serves as
115. lt gt O D1 O O D2 O O Vss D3 O L D4 O O Open D5 O lt gt O VPP D6 O L D7 O O Open Vss O O Voo A0 O O L A10 O PGM A2 O O L A3 O O A9 A4 O O RESET A5 O O A6 O O 0 A7 O O CE A8 O O OE A16 O O A10 O O A110 o B A12 O O A13 O O A15 Vss O O A14 Cautions 1 L Individually connect this pin to Vss via a pull down resistor 10 kQ 2 Vss Connect this pin to ground 3 RESET Fix this pin to the low level 4 Open Leave this pin unconnected 44 CHAPTER 1 GENERAL 1 PD78018F SUBSERIES 64 pin plastic QFP 14 x 14 mm u4PD78P018FGC AB8 78P018FGC A AB8 e 64 pin plastic LQFP 12 x 12 mm u4PD78P018FGK 8A8 64 pin ceramic WQFN 14 x 14 mm u4PD78P018FKK S a O Vss O Vpop 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 DO O 1 48 O D1O 2 O 47 O jo D2 O 3 46 O Vss D3 O 4 45 O L D4 O 5 44 O Open D5 O 6 43 O Vpp D6 O 7 42 O L D7 O 8 41 O Open Vss O 9 40 O Voo Ao O 10 39 O L Ai O gt 11 38 O PGM A20 12 37 O L A3 O 13 36 O A9 A4 O 14 35 O RESET A5 O 15 34 O A6 O 16 33 O lo 17 18 19 20 24 25 26 27 28 29 30 31 32 TEST oo O N 0 Q WO MA pu ju ttiz z 3 ele Cautions 1 L Individually connect this pin to Vss via a pull down resistor 10 kQ 2 Vss Connect this pin to ground 3 RESET Fix this pin to the low level 4 Open Leave this pin unconnected A0 A16 Address Bus RESET Reset CE Chip Enable Voo Power Su
116. made high impedance state during data reception Serial transfer is automatically stopped at the end of 8 bit transfer and an interrupt request flag CSIIFO is set 5 Error detection In the 2 wire serial l O mode the status of the serial bus SBO SB1 under transmission is also loaded to serial I O shift register O SIOO of the device that is transmitting data therefore a transfer error can be detected by the following method a By comparing data of SIOO before start of and after completion of transmission In this case it is judged that an transmission error has occurred if two data are different b By using slave address register SVA The transmitted data is set to SIOO and SVA and transmission is executed After completion of transmission the COI bit match signal from address comparator of the serial operation mode register 0 CSIMO is tested If this bit is 1 it is judged that transmission has been completed normally If it is 0 it is judged that a transmittion error has occurred 332 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78018FY Sp 16 4 4 Operation in 12C bus mode The 12C bus mode is used to perform single master and slave operations on the 12C bus In this mode a single master serial bus can communicate with two or more slave devices by using two signal lines serial clock SCL and serial data bus SDAO or SDA1 The format of this mode is based on the clocked serial I O mode with a
117. mode 4 byte data of 1 page is latched to the internal address data latch circuit Page write mode Page write is executed by applying a 0 1 ms program pulse active low to the PGM pin with CE H and OE H after latching 1 page 4 byte address and data in the page data latch mode After that the program can be verified when CE L and OE L If the program cannot be written by one program pulse repeatedly execute write and verify X times X lt 10 Byte write mode Byte write is executed when a 0 1 ms program pulse active low is applied to the PGM pin with CE L and OE H After that the program can be verified when OE L If the program cannot be written by one program pulse repeatedly execute write and verify X times X lt 10 Program verify mode The program verify mode is set when CE L PGM H and OE L Use this mode to confirm that the program has written correctly Program inhibit mode The program inhibit mode is used to write one device of the plural uPD78P018F s and 78P018FY s whose OE Vrr and DO D7 pins are connected in parallel To write a program use the page write or byte write mode described above At this time the program is not written to a device whose PGM pin is high 469 CHAPTER 23 uPD78P018F 78P018FY 23 3 2 PROM write sequence Figure 23 3 Page Program Mode Flowchart Start Address G Voo 6 5V Vrr 12 5V x lt 11 o Latch Address address 1 Latch
118. of Interrupt Request Flag Register 0H Symbol 7 6 lt 5 4 43 lt 2 gt lt 1 gt lt 0 Address Onreset R W IFOH o o WTIF o ADIF TMIF2 TMIF1 TMIFO FFE1H 00H R W WTIF Watch timer overflow detection flag 0 Not detected 1 Detected Caution Be sure to set bits 4 6 and 7 to 0 2 Interrupt mask flag register OH MKOH This register enables or disables releasing the standby mode by the watch timer MKOH is set by a 1 bit or 8 bit memory manipulation instruction This register is set to FFH when the RESET signal is input Figure 18 19 Format of Interrupt Mask Flag Register 0H Symbol 7 6 lt 5 gt 4 lt 3 gt lt 2 gt lt gt lt 0 Address Onreset R W no C T ee o p e em o WTMK Controls standby mode by watch timer 0 Enables releasing standby mode 1 Disables releasing standby mode Caution Be sure to set bits 4 6 and 7 to 1 423 CHAPTER 18 INTERRUPT FUNCTIONS AND TEST FUNCTIONS i tinued 3 Key return mode register KRM This register enables or disables releasing the standby mode by using the key return signal detection of the falling edge of port 4 KRM is set by a 1 bit or 8 bit memory manipulation instruction This register is set to 02H when the RESET signal is input Figure 18 20 Format of Key Return Mode Register Symbol 7 2 lt 1 lt 0 Address On reset R W CIAO KRIF Key return signal detection flag Not detected Detected detection of falling edge of port 4
119. of TM1 and TM2 are incremented Either the rising edge or falling edge can be specified as the valid edge When the count values of TM1 and TM2 coincide with the values of the corresponding 8 bit compare registers CR10 and CR20 TM1 and TM2 are cleared to 0 and interrupt request signals INTTM1 and INTTM2 are generated Figure 9 9 External Event Counter Operation Timing with rising edge specified TMi countvalue _ 00 X 01 X 02 X 03 X 04 X os X AN 1A N X 00 X 01 X 02 X o3 X INTTM1 AS Remark N 00H FFH 213 CHAPTER 9 8 BIT TIMER EVENT COUNTER 3 Operation as square wave output The 8 bit timer event counters operate as square wave output of any frequency at time intervals specified by the values set to the corresponding 8 bit compare registers CR10 and CR20 in advance When bit 0 or 4 TOE1 or TOE2 of the 8 bit timer output control register TOC1 is set to 1 the output status of the TO1 P31 or TO2 P32 pin is inverted at time intervals specified by the values set to CR10 or CR20 in advance In this way square waves of any frequency can be output Table 9 8 Square Wave Output Range of 8 Bit Timer Event Counters Minimum Pulse Width 22 x 1 fx 400 ns Maximum Pulse Width 210 x 1 fx 102 4 us Resolution 22 x 1 1x 400 ns 23 x 1 fx 800 ns 211 x 4 fx 204 8 us 23 x 1 fx 800 ns 24 x 1 fx 1 6 us 212 x 1 fx 409 6 us 24 x 1 fx 1 6 us 213 x 1 fx 819 2 us
120. option register PUO Control mode In this mode POO through P04 are used to input external interrupt requests an external count clock to timer and to connect a crystal resonator for subsystem clock oscillation a INTPO INTP3 INTPO through INTP2 are external interrupt request input pins for which valid edge can be specified rising edge falling edge and both rising and falling edges INTPO also functions as the capture trigger input pin of the 16 bit timer event counter when a valid edge is input INTP3 is a falling edge triggered external interrupt request input pin b TIO External count clock input pin of the 16 bit timer event counter c XT1 Subsystem clock oscillation crystal connecting pin 3 2 2 P10 P17 Port1 These pins form an 8 bit I O port port 1 These pins also serve as the analog input pins of the A D converter They can be set in the following operation modes in 1 bit units 1 2 Port mode In this mode P10 through P17 constitute an 8 bit I O port which can be set in the input or output mode in 1 bit units by using the port mode register 1 PM1 When used as an input port an internal pull up resistor can be used if so specified by the pull up resistor option register PUO Control mode In this mode P10 through P17 function as the analog input pins ANIO ANI7 of the A D converter When these pins are specified to serve as analog input pins the internal pull up resistor is automatically disconn
121. output TOC11 Controls timer output F F of 8 bit timer event counter 1 0 Disables inversion 1 Enables inversion LVS1 LVR1 Sets status of timer output F F of 8 bit timer event counter 1 Not affected Resets timer output F F to O Sets timer output F F to 1 Setting prohibited TOE2 Controls output of 8 bit timer event counter 2 0 Disables output port mode 1 Enables output TOC15 Controls timer output F F of 8 bit timer event counter 2 0 Disables inversion 1 Enables inversion LVS2 LVR2 Sets status of timer output F F of 8 bit timer event counter 2 Not affected Resets timer output F F to O Sets timer output F F to 1 Setting prohibited Cautions 1 Be sure to stop the timer operation before setting TOC1 2 0 is read from LVS1 LVS2 LVR1 and LVR2 after data has been set to these bits 209 i mar lu ed CHAPTER 9 8 BIT TIMER EVENT COUNTER 4 3 2 1 0 PM3 PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30 FF23H FFH RW 210 Port mode register 3 PM3 This register sets the input output mode of port 3 in 1 bit units When the P31 TO1 and P32 TO2 pins are used as timer output pins set 0 to the PM31 and PM32 bits of this register and the output latch of the P31 and P32 pins PMS is set by a 1 bit or 8 bit memory manipulation instruction This register is set to FFH when the RESET signal is input Figure
122. output by the master The acknowledge signal ACK is output by either the master or slave usually this signal is output by the side that receives 8 bit data The serial clock SCL is continuously output by the master 334 ar GN CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78018FY Sp a Start condition The start condition is output to the serial data bus when the SDAO SDA1 pin goes low while the SCL pin is high Therefore the start condition of the SCL and SDAO SDA1 pins is a signal output by the master when the master starts serial transfer to a slave For the details about start condition output refer to 16 4 5 Notes on using I2C bus mode The slave has hardware that detects the start condition Figure 16 14 Start Condition SCL SDAO SDA1 b Addresses The 7 bit data following the start condition is defined to be an address An address is 7 bit of data output by the master to select a specific slave from those connected to the bus line Therefore all the slaves on the bus line must have a different address A slave detects the start condition by hardware and checks whether the 7 bit data output by the master coincides with the value of the slave address register SVA of the slave If the 7 bit data coincides with the value of the slave address register of the slave the slave is selected After that communication takes place between the master and this slave until the master transmits a start or stop
123. output mode therefore set 1 to the interrupt mask flags in advance 149 CHAPTER 6 PORT FUNCTIONS Multiplexed Function Multiplexed Function Pin Name Name 1 0 Name 1 0 INTPO Input P36 BUZ Output TIO Input P40 P47 ADO AD7 1 0 P01 P03 INTP1 INTP3 Input P50 P57 A8 A15 Output Po4Note 1 xT1 Input P64 RD Output P10 P17Note 1 ANIO ANI7 Input P65 WR Output P30 P32 TOO TO2 Output P66 WAIT Input P33 P34 TH Tl2 Input P67 ASTB Output P35 PCL Output Notes 1 The contents of the read data are undefined if a read instruction is excuted to these ports while they are used as multiplexed function pins 2 When using the multiplexed function of P40 P47 P50 P57 and P64 P67 pins set the function by using the memory extension mode register MM Caution When using the pins of port 2 as serial interface pins the input output and output latch must be set in accordance with the function to be used For the details of setting refer to Figure 15 3 or 16 3 Format of Serial Operation Mode Register 0 and Figure 17 3 Format of Serial Operation Mode Register 1 Remark x don t care need not to be set PMxx port mode register Pxx output latch of port 150 CHAPTER 6 PORT FUNCTIONS Figure 6 16 Format of Port Mode Register Symbol 7 6 5 4 3 2 1 0 Address On reset R W PMO 0 0 0 1 PMO3 PM02 PMO1 1 FF20H 1FH R W PM1 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 FF21H
124. output pins used in the external memory extension mode are as follows 1 RD pin shared by P64 2 3 4 5 This pin outputs a read strobe signal when an instruction is fetched or data is accessed from the external memory When the internal memory is accessed the read strobe signal is not output instead this pin holds the high level WR pin shared by P65 This pin outputs a write strobe signal when the external memory is accessed for data When the internal memory is accessed the write strobe signal is not output this pin holds the high level WAIT pin shared by P66 This pin inputs an external wait signal When the external wait signal is not used the WAIT pin can be used as an I O port pin When the internal memory is accessed the external wait signal is ignored ASTB pin shared by P67 This pin outputs an address strobe signal which is always output regardless of instruction fetch or data access from the external memory the address strobe signal is also output when the internal memory is accessed ADO AD7 A8 A15 pins shared by P40 P47 P50 P57 These pins output address and data signals The valid signals are output or input when instructions are fetched or data is accessed from the external memory The status of the signal also changes when the internal memory is accessed the output contents are undefined Figures 19 4 through 19 7 show the timing charts 432 CHAPTER 19 EXTERNAL DEVI
125. prohibited gt Setting prohibited Not Setting prohibited 100 fx Setting prohibited Setting prohibited No 20 0 us 200 fx 20 0 us 23 9 us 40 0 us Setting prohibited No external trigger software start mode Conversion started by external trigger hardware start mode Controls A D conversion operation E operation Starts operation Notes 1 Set these bits so that the A D conversion time is 19 1 us or more 2 This setting is prohibited because the A D conversion time is less than 19 1 us Cautions 1 To reduce the power consumption of the A D converter in the standby mode clear bit 7 CS to 0 to stop A D conversion and then execute the HALT or STOP instruction 2 To resume A D conversion that has been once stopped clear the interrupt request flag ADIF to 0 and then start the A D conversion Remark fx Main system clock oscillation frequency 249 CHAPTER 14 A D CONVERTER 2 A D converter input select register ADIS This register sets whether the ANIO P10 ANI7 P17 pins are used as the analog input channels of the A D converter or as port pins Pins not selected as analog input channels can be used as I O port pins ADIS is set by an 8 bit memory manipulation instruction This register is set to OOH when the RESET signal is input Cautions 1 Set an analog input channel in the following procedure lt 1 gt Set the number of analog input channels by
126. sfrp of a 16 bit manipulation instruction To specify address write an even address Table 5 7 lists the special function register The meanings of the symbols in this table are as follows Symbol These symbols indicate the addresses of the special function registers They are reserved words for the RA78K O and defined by header file sfrbit h for the CC78K 0 These symbols can be written as the operands of instructions when the RA78K 0 ID78KO NS ID78KO0 or SM78KO is used R W Indicates whether the special function register in question can be read or written R W Read write R Read only W _ Write only Bit units for manipulation O ndicates the bit units 1 8 16 in which the special function register in question can be manipulated indicates the bit units that cannot be manipulated At reset Indicates the status of the special function register when the RESET signal is input 107 CHAPTER 5 CPU ARCHITECTURE Table 5 7 Special Function Register List 1 2 Bit Units for Manipulation Address Special Function Register SFR Name At Reset 1 bit 8 bits 16 bits Port 0 PO Port 1 P1 Port 2 P2 Port 3 P3 Port 4 P4 Undefined Port 5 P5 Port 6 P6 16 bit compare register CROO 16 bit capture register CRO1 16 bit timer register TMO 0000H 8 bit compare register CR10 Undefined 8 bit compare register CR20 8 bit timer register 1 TM
127. status word PSW and program counter PC are saved to the stack in that order IE flag is reset to 0 and the content of the interrupt priority specification flag of the accepted interrupt is transferred to the ISP flag In addition the data in the vector table determined for each interrupt request is loaded to the PC and execution branches To return from interrupt processing use the RETI instruction 415 al UNO CHAPTER 18 INTERRUPT FUNCTIONS AND TEST FUNCTIONS Figure 18 12 Interrupt Request Acceptance Program Algorithm m l Interrupt request pending Yes high priority interrupt has highest priority of interrupts of xxPR 0 that are generated at same time Yes Interrupt request pending Interrupt request pending Yes Vectored interrupt processing xxIF Interrupt request flag xxMK Interrupt mask flag xxPR Priority specification flag No low priority Two or More interrupt requests of xxPR 0 that are generated at same time 2 Yes Interrupt request pending Which interrupt has highest priority of interrupt requests that are generated at Interrupt request pending Yes same time Interrupt request pending No Interrupt request pending Yes Vectored interrupt processing IE Flag controlling accepting maskable interrupt request 1 enable 0 disable ISP Flag indicating priority of interrup
128. time Remark Interval time N 1 xt N OOOOH FFFFH 215 i tinued CHAPTER 9 8 BIT TIMER EVENT COUNTER Caution Even when the two 8 bit timers are used in combination in a 16 bit timer event counter mode when the count value of TM1 coincides with the value of CR10 an interrupt request INTTM1 is generated and the F F of the 8 bit timer event counter output control circuit 1 is inverted When using the 8 bit timers as a 16 bit interval timer set mask flag TMMK1 which disables accepting INTTM1 to 1 To read the count value of the 16 bit timer register TMS use a 16 bit memory manipulation instruction Table 9 9 Interval Time when Two 8 Bit Timer Event Counters TM1 and TM2 Are Used as One 16 Bit Timer Event Counter Minimum Interval Time TI1 input cycle Maximum Interval Time 28 x TI1 input cycle Resolution TI1 input edge cycle TI1 input cycle 28 x TI1 input cycle TI1 input edge cycle 22 x 1 1x 400 ns 218 x 1 fx 26 2 ms 22 x 1 1x 400 ns 23 x 1 fx 800 ns 219 x 1 fx 52 4 ms 23 x 1 fx 800 ns 24 x 1 fx 1 6 us 220 x 4 fx 104 9 ms 24 x 1 fx 1 6 us 221 x 1 tx 209 7 ms 25 x 1 fx 3 2 us 28 x 1 1x 6 4 us 25 x 1 fx 3 2 us 28 x 1 1x 6 4 us 27 x 1 fx 12 8 us 222 x 1 fx 419 4 ms 223 x 1 fx 838 9 ms 27 x 1 fx 12 8 us 28 x 1 fx 25 6 us 224 x 1 fx 1 7 s 28 x 1 fx 25 6 us 225 x 1 fx
129. timing specification register Serial operation mode register 1 Automatic data transmit receive control register Automatic data transmit receive address pointer OJO OJOJO O OJO Automatic transmit receive interval specification register A D converter mode register A D converter input select register Correction control registerNote 1 OJOJOO External access areaNote 2 Undefined Interrupt request flag register OL Interrupt request flag register OH Interrupt mask flag register OL Interrupt mask flag register OH Priority specification flag register OL Priority specification flag register OH External interrupt mode register Memory size select register Internal extension RAM size select register Key return mode register Pull up resistor option register Memory extension mode register Watchdog timer mode register Oscillation stabilization time select register OlIOl OoOloloIolololololololololo Processor clock control register 109 i YN ne red CHAPTER 5 CPU ARCHITECTURE Notes 1 Provided to uPD78015F 78015FY 78016F 78016FY 78018F 78018FY 78P018F and 78P018FY only 2 The external access area cannot be accessed by SFR addressing Access this area by direct addressing 3 The value on reset for the memory size selected r
130. to 0 when CSIEO 0 R W SO0 latch is cleared to 0 when CMDT 1 After clearing SOO latch CMDT is automatically cleared to 0 This bit is also cleared to 0 when CSIEO 0 CSIEO Bit 7 of the serial operation mode register 0 CSIMO c Interrupt timing specification register SINT SINT is set by a 1 bit or 8 bit memory manipulation instruction This register is set to OOH when the RESET signal is input Symbol 7 lt 6 gt lt 5 gt Address On reset R W cor o eo se m To o e rm om aye R W Selects interrput source of INTCSIO 0 1 Sets CSIIFO at end of transfer by serial interface channel 0 Sets CSIIFO at end of transfer by serial interface channel 0 or on detection of bus release R CLD Level of SCKO P27 pin Note2 0 Low level 1 High level Notes 1 Bit 6 CLD is a read only bit 2 CLD is 0 when CSIEO 0 Caution Be sure to set bits 0 through 3 to 0 Remark CSIIFO Interrupt request flag corresponding to INTCSIO CSIEO Bit 7 of the serial operation mode register 0 CSIMO 305 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 uPD78018F SUBSERIEF 2 Communication operation SCKO SBO0 SB1 CSIIFO 306 In the 2 wire serial l O mode data is transmitted received in 8 bit units Data is transmitted received on a 1 bit by 1 bit basis in synchronization with the serial clock The shift operation of the serial I O shift register 0 SIOO is performed in synchronization with t
131. up function refer to 16 4 4 1 c Wake up function Slave address register SVA This 8 bit register sets the value of a slave address when the microcomputer is connected to the serial bus as a slave device It is not used in the 3 wire serial I O mode SVA is set by an 8 bit memory manipulation instruction The master outputs a slave address to the slaves connected to it to select a specific slave The slave address output by the master and the value of the SVA are compared by an address comparator If the two addresses coincide the slave is selected At this time bit 6 COI of the serial operation mode register 0 CSIMO is set to 1 The high order 7 bits of data with its LSB masked by setting the bit 4 SVAM of the interrupt timing specification register SINT can compare with the slave address If no coincidence is detected when the address is received bit 2 RELD of the serial bus interface control register SBIC is cleared to 0 The wake up function can be used by setting bit 5 WUP of CSIMO to 1 in the 12C bus mode In this case an interrupt request signal INTCSIO is generated when the slave address output by the master coincides with the value of SVA the interrupt request signal is generated also when the stop condition is detected This interrupt indicates that the master requests communication When using the wake up function set SIC to 1 When the microcontroller transmits data as the master or a slave in the 2 wire seri
132. usually used Therefore detect whether a slave is selected or not by reception of a slave address when WUP 1 To detect whether a slave is selected or not when WUP 0 without using the interrupt do so by transmitting receiving a command set by program in advance instead of using the address matching method In the SBI mode output of the BUSY signal continues until the next serial clock SCKO falling edge after a BUSY releasing command has been issued If WUP 1 during this period BUSY cannot be released Therefore to set WUP to 1 be sure to release the BUSY status and make sure that the SBO SB1 pin has gone high Be sure to set the pin used to input or output data after the RESET signal has been input and before serial transfer of the first byte lt 1 gt Set 1 to the output latch of P25 and P26 lt 2 gt Set bit 0 RELT of the serial bus interface control register SBIC to 1 lt 3 gt Set 0 to the output latch of P25 and P26 to which 1 has been set A positive transition of the SBO SB1 pin from low to high or high to low is recognized as a bus release signal or a command signal when the SCKO line is high If the change timing of the bus is shifted due to the influence of the board capacitance data that is transmitted may be identified as bus release signal or a command signal by mistake Exercise care in wiring i ar lu ed CHAPTER 15 SERIAL INTERFACE CHANNEL 0 uPD78018F SUS 15 4 4 Operat
133. valid edge is detected two times Consequently noise that may be superimposed on a pulse with a short pulse width can be eliminated Figure 8 17 Configuration of External Event Counter 16 bit compare register CR00 gt INTTMO Clear 16 bit timer register TMO OVFO Valid edge of TIO gt INTPO 16 bit capture register CRO1 Internal bus 195 CHAPTER 8 16 BIT TIMER EVENT COUNTER Figure 8 18 External Event Counter Operation Timing with rising edge specified tiopininpat LE LE LILI LL bb LL L TMO count value 0000 X0001X0002Y 0003X000s Y 0005X XN 1X N 0000 X oo01Yooo2 Y 0003 I CROO N l ee i INTTMO Po 8 5 5 Operation as square wave output The 16 bit timer event counters operate as square wave output of any frequency at time intervals specified by the count value set to the 16 bit compare register CR00 in advance When the bits 0 and 1 TOEO and TOCO1 of the 16 bit timer output control register TOCO are set to 1 the output status of the TOO P30 pin is inverted at time intervals specified by the count value set to CROO in advance In this way square waves of any frequency can be output Table 8 6 Square Wave Output Range of 16 Bit Timer Event Counter Minimum Pulse Width Maximum Pulse Width Resolution 2 x TIO input cycle 216 x TIO input cycle TIO input edge cycle 22 x 1 fx 400 ns 217 x 1 fx 13 1 ms 2 x 1 fx 200 ns
134. when Tl1 or TI2 selected as count clock Watchdog timer Stops operation A D converter Operable Stops operation Watch timer Operable when fxt selected as count clock Serial interface Other than automatic Operable Operable when external clock transmit receive function selected Automatic transmit receive Stops operation function External interrupt INTPO Operable when clock to peripheral Stops operation hardware fx 2 tx 27 selected as sampling clock INTP1 INTP3 Operable Externally ADO AD7 High impedance extended bus line 18 475 Retains previous status before setting HALT mode ASTB Low level High level High impedance 442 i ri oY a lv ed CHAPTER 20 STANDBY FUNCTION 2 Releasing HALT mode The HALT mode can be released by the following four types of sources a Releasing by unmasked interrupt request The HALT mode is released by an unmasked interrupt request In this case if the interrupt request is enabled to be accepted vectored interrupt processing is performed If the interrupt request is disabled the instruction at the next address is executed Figure 20 2 Releasing HALT Mode by Interrupt Request HALT instruction Interrupt request Standby release signal Operation mode HALT mode Wait Operation mode lt gt n gt Clock Oscillation Remarks 1 The dotted line indicates the case where th
135. wire serial I O mode with automatic transmit receive function If not used in this mode this internal buffer RAM can also be used as an ordinary RAM 100 i ar lu ed CHAPTER 5 CPU ARCHITECTURE 5 1 3 Special function register SFR area Special function registers SFRs of on chip peripheral hardware are allocated to an area of FFOOH FFFFH refer to 5 2 3 Special function registers SFRs Table 5 7 Special Function Regisiter List Caution Do not access an address to which no SFR is allocated 5 1 4 External memory space This is an external memory space that can be accessed by using the memory extension mode register MM This space can store programs and table data and can be assigned peripheral devices 101 CHAPTER 5 CPU ARCHITECTURE 5 2 Processor Registers The uPD78018F 78018FY subseries are provided with the following processor registers 5 2 1 Control registers Each of these registers has a dedicated function such as to control the program sequence status and stack memory The control registers include the program counter PC program status word PSW and stack pointer SP 1 Program counter PC The program counter is a 16 bit register that holds an address of the program to be executed next The contents of this register are automatically incremented according to the number of bytes of an instruction to be fetched when a normal operation is performed When a branch instruction is executed immed
136. x 1 fx 3 28 ms 27 x 1 fx 12 8 us 28 x 1 tx 25 6 us 216 x 1 tx 6 55 ms 28 x 1 fx 25 6 us 217 x 1 fx 13 1 ms 218 x 4 fx 26 2 ms 220 x 1 fx 104 9 ms 210 x 1 fx 102 4 us 212 x 1 fx 409 6 us 210 x 4 fx 102 4 us 212 x 4 fx 409 6 us 29 x 1 fx 51 2 us 29 x 1 fx 51 2 us Remarks 1 fx main system clock oscillation frequency 2 atfx 10 0 MHz operation 2 External event counter The number of pulses of an externally input signal can be measured 3 Square wave output A square wave of any frequency can be output Table 9 2 Square Wave Output Range of 8 Bit Timer Event Counter 200 Minimum Pulse Width 22 x 1 fx 400 ns Maximum Pulse Width 210 x 1 fx 102 4 us Resolution 22 x 1 fx 400 ns 23 x 1 fx 800 ns 211 x 1 fx 204 8 us 23 x 1 fx 800 ns 24 x 1 fx 1 6 us 212 x 1 fx 24 x 1 fx 1 6 us 409 6 us 213 x 1 fx 819 2 us 25 x 1 fx 3 2 us 28 x 1 fx 6 4 us 214 x 1 fx 1 64 ms 25 x 1 fx 3 2 us 26 x 1 fx 6 4 us 27 x 1 fx 12 8 us 215 x 1 fx 3 28 ms 27 x 1 fx 12 8 us 28 x 1 fx 25 6 us 28 x 1 fx 25 6 us 217 x 1 fx 13 1 ms 210 x 4 fx 102 4 us 216 x 1 tx 6 55 ms 218 x 1 fx 26 2 ms 210 x 1 fx 102 4 us Remarks 1 fx 29 x 1 fx 51 2 us 212 x 1 fx 409 6 us 220
137. 05 CHAPTER 5 CPU ARCHITECTURE Figure 5 14 General Purpose Register Configuration a Absolute name 16 bit processing 8 bit processing FEFFH RP3 FEF8H FEF7H RP2 FEFOH FEEFH RP1 FEE8H FEE7H RPO FEEOH 15 0 b Function name 16 bit processing 8 bit processing HL DE BC AX 15 0 FEFFH FEF8H FEF7H FEFOH FEEFH FEE8H FEE7H FEEOH 106 i rit od Y CHAPTER 5 CPU ARCHITECTURE 5 2 3 Special function registers SFRs Unlike the general purpose registers special function registers have their own functions and are allocated to an area of addresses FFOOH FFFFH The special function registers can also be manipulated in the same manner as the general purpose registers by using operation transfer and bit manipulation instructions The bit units in which one register is to be manipulated 1 8 or 16 bits differ from that of another register The bit unit for manipulation is specified as follows 1 bit manipulation A symbol reserved by the assembler is written as the operand sfr bit of a 1 bit manipulation instruction An address can also be specified 8 bit manipulation A symbol reserved by the assembler is written as the operand sfr of an 8 bit manipulation instruction An address can also be specified 16 bit manipulation A symbol reserved by the assembler is written as the operand
138. 10 A D Conversion End Interrupt Generation Timing Rewriting ADM Rewriting ADM ADIF is set but conversion ANIn conversion starts ANIm conversion starts of ANIm is not completed A D conversion ADCR m 0 1 7 AVob pin The AVpp pin is the power supply pin to the analog circuit and supplies power to the input circuit of ANIO P10 ANI7 P17 Therefore even in the application which can be switched over to backup power source be sure to apply the same voltage as Voo as shown in Figure 14 11 Figure 14 11 Processing of AVpp Pin gt m Main power source __ Backup capacitor 258 al i nued ii UGY CHAPTER 15 SERIAL INTERFACE CHANNEL 0 uPD78018F SUBSERIES The uPD78018F subseries is provided with two channels of clocked serial interfaces The differences between channels 0 and 1 are as indicated in the table below for the details of serial interface channel 1 refer to CHAPTER 17 SERIAL INTERFACE CHANNEL 1 Table 15 1 Serial Transfer Mode 3 wire serial I O Clock selection Differences between Channels 0 and 1 Channel 0 fx 22Note 7 23 fx 24 fx 25 tx 28 fx 2 tx 28 fx 29 external clock TO2 output Channel 1 fx 22Note 13 23 fx 24 fx 25 fx 28 fx 27 fx 28 fx 29 external clock TO2 output Transfer method MSB first LSB first selectable MSB first LSB first selectable Automatic transmit receive function Transfer end flag Seri
139. 16 bit timer event counter mode when the count value of TM1 coincides with the value of CR10 an interrupt request INTTM1 is generated and the F F of the 8 bit timer event counter output control circuit 1 is inverted When using the 8 bit timers as a 16 bit interval timer set mask flag TMMK1 which disables accepting INTTM1 to 1 To read the count value of the 16 bit timer register TMS use a 16 bit memory manipulation instruction 217 CHAPTER 9 8 BIT TIMER EVENT COUNTER 3 Operation as square wave output The 8 bit timers event counters operate square wave output of any frequency at time intervals specified by the values set to the corresponding 8 bit compare registers CR10 and CR20 in advance When setting a count value write the value of the high order 8 bits to CR20 and the value of the low order 8 bits to CR10 When the bit 4 TOE2 of the 8 bit timer output control register TOC1 is set to 1 the output status of the TO2 P32 pin is inverted at time intervals specified by the count values set to CR10 or CR20 in advance In this way square waves of any frequency can be output Table 9 10 Square Wave Output Range when Two 8 Bit Timer Event Counters TM1 and TM2 Are Used as One 16 Bit Timer Event Counter Minimum Pulse Width Maximum Pulse Width Resolution 22 x 1 fx 400 ns 218 x 1 fx 26 2 ms 22 x 1 1x 400 ns 23 x 1 fx 800 ns 219 x 1 fx 52 4 ms 23 x 1 fx 800 ns 24 x 1 fx 1 6 us 220 x 1 fx 104 9 ms 24
140. 16 bit timer register 205 16 bit timer output control register 184 8 bit timer output control register 209 Watchdog timer mode register 234 APPENDIX E REVISION HISTORY The following table shows the revision history of this manual Chapter indicates the chapter of the previous edition Edition 2nd edition Major Revisions The following products have been developed e 1PD78013F 78014F 78015F 78016F Addition of the following products e 1PD78011F 78012F e 1 PD78011FY 78012FY 78013FY 78014FY 78015FY 78016FY 78P018FY Change in supply voltage Voo 2 0 to 6 0 V gt Vo 1 8 to 5 5 V 1 3 Chapter Throughout Addition of CHAPTER 2 GENERAL uPD78018FY SUBSERIES CHAPTER 2 GENERAL uPD78018FY SUBSERIES Correction to recommended connections when unused CHAPTER 3 PIN FUNCTIONS uPD78018F SUBSERIES Addition of CHAPTER 4 PIN FUNCTIONS uPD78018FY SUBSERIES CHAPTER 4 PIN FUNCTIONS uPD78018FY SUBSERIES Addition of 6 2 4 Port 2 uPD78018FY subseries CHAPTER 6 PORT FUNCTIONS Change of setting bit 0 of A D converter mode register ADM from 1 gt HSC Addition of notes on processing of AVob pin CHAPTER 14 A D CONVERTER Addition of CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78018FY SUBSERIES CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78018FY SUBSERIES Addition of automatic data transmission reception time interval speci
141. 18F 78P018FY with 32 KB internal PROM Internal high speed RAM Reserved Internal buffer RAM Reserved Full address mode when MM2 MMO 111 16KB extension mode when MM2 MMO 101 4KB extension mode when MM2 MMO 100 256B extension mode when MM2 MMO 011 Single chip mode 427 CHAPTER 19 EXTERNAL DEVICE EXTENSION FUNCTION e Memory map of uPD78015F 78015FY and UPD78P018F 78P018FY with 40 KB internal PROM 428 Figure 19 1 Memory Map when External Device Extension Function Is Used 3 4 FFFFH FFOOH FEFFH Internal high speed RAM FBOOH FAFFH Reserved FAEOH FADFH Internal buffer RAM FACOH FABFH Reserved F800H F7FFH Internal extension RAM F600H F5FFH Full address mode when MM2 MMO 111 E000H DFFFH 16KB extension mode when MM2 MMO 101 BOOOH AFFFH 4KB extension mode when MM2 MMO 100 A100H AOFFH 256B extension mode hen MM2 MMO 011 A000H when OOT 9FFFH Single chip mode 0000H f Memory map of uPD78016F 78016FY and uUPD78P018F 78P018FY with 48 KB internal PROM FFFFH FFOOH FEFFH Internal high speed RAM FBOOH FAFFH Reserved FAEOH FADFH Internal buffer RAM FACOH FABFH Reserved F800H F7FFH Internal extension RAM F600H F5FFH Full address mode when MM2 MMO 111 or 16KB extension mode when MM2 MMO 101 DOOOH CFFFH 4KB ex
142. 1FY 78012F 78012FY 78013F 78013FY 78014F 78014FY 78015F 78015FY 78016F 78016FY 78018F and 78018FY are shown in Table 23 1 463 CHAPTER 23 uPD78P018F 78P018FY ce inued Table 23 1 Differences between uPD78P018F 78P018FY and Mask ROM Models uPD78P018F 78P018FY Mask ROM Model Internal ROM structure One time PROM EPROM Mask ROM Internal ROM capacity 60K bytes uPD78011F 78011FY 8K bytes uPD78012F 78012FY 16K bytes uUPD78013F 78013FY 24K bytes 1PD78014F 78014FY 32K bytes uUPD78015F 78015FY 40K bytes uUPD78016F 78016FY 48K bytes 4PD78018F 78018FY 60K bytes Internal high speed RAM 1024 bytes uPD78011F 78011FY 512 bytes Capacity 1PD78012F 78012FY 512 bytes 1PD78013F 78013FY 1024 bytes 4PD78014F 78014FY 1024 bytes 4PD78015F 78015FY 1024 bytes 4PD78016F 78016FY 1024 bytes 4PD78018F 78018FY 1024 bytes Internal extension RAM 1024 bytes HPD78011F 78011FY None capacity 4PD78012F 78012FY None HPD78013F 78013FY None HPD78014F 78014FY None HPD78015F 78015FY 512 bytes HPD78016F 78016FY 512 bytes HPD78018F 78018FY 1024 bytes Changing internal ROM and YesNote 1 No internal high speed RAM capacities by using memory size select register IMS Changing of internal extended RAM capacity by using internal extension RAM size select register IXS IC pin None Provided VPP pin Provided None Mask option to contain pull up Not provid
143. 2 Table 1 2 Differences between A Model and A2 Model Classification A2 Model Operating ambient temperature 40 to 85 C 40 to 125 C DC characteristics Analog pin input leakage current power supply current and data retention current differ AC characteristics Bus timing differs 1 11 Mask Option The mask ROM models uPD78011F 78012F 78013F 78014F 78015F 78016F and 78018F have a mask option By specifying the mask option when placing your order the pull up resistors shown in Table 1 3 can be connected By using the mask option when a pull up resistor is necessary the number of components and the mounting area can be reduced Table 1 3 shows the mask option for the uwPD78018F subseries Table 1 3 Mask Option for Mask ROM Model Mask Option P60 P63 Pull up resistors can be connected in 1 bit units 51 MEMO 52 i ri oY a lv ed CHAPTER 2 GENERAL uPD78018FY SUBSERIES 2 1 Features e High capacity ROM and RAM Data Memory Program Memory ROM Internal High Speed RAM Internal Extension RAM Internal Buffer RAM 8 KB 16 KB 24 KB 32 KB 40 KB 48 KB 60 KB 1024 B 60 KBNote 1 1024 BNote 2 1024 BNote 3 Notes 1 8 16 24 32 40 48 or 60 KB is selectable by using memory size select register IMS 2 512 or 1024 B is selectable by using IMS 3 0 512 or 1024 B is selectable by using internal extension RAM siz
144. 22 7 Notes on ROM Correction cccscccssseeceseecesseeeenseeeessneeseseeesecaesaseeeeeseeseseeeeenseeeeseneeeneees 462 CHAPTER 23 uPD78P018F 78P018FY cccccccecsseeceeeeeeseeesesnneeeeeeseaneeeeeeseeessaesenseeesssaesenseeeenes 463 23 1 Memory Size Select Register ssssnnssennneunnenunnenunnunnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn nunn nn nnna 465 23 2 Internal Extension RAM Size Select Register ccssecccssccsseeeeeeseesesseeeeeseeeeeseeeeneees 467 23 3 PROM Programming i a cionado 2 indeysecctecentedtabutevecucdavicettsededtsecectuteee 468 23 3 1 Operation mode iii eit nena at ve anes 468 23 3 2 PROM Write Sequence iaa ratio 470 23 3 3 PROM read Sequence 32 2 4 a a E aaae e aa aa a Aa a e Aara Aeaaeai anaE aiae rosaa NAA ai 474 23 4 Erasure uPD78P018FDW 78P018FKK S LPD78PO18FYDW 78P018FYKK S nnssnnnsssnsunnnnnnnennnnnnnenunnnnunnnunnnnnnnnnnnnnnnnnnnne 475 23 5 Erasure Window Stickers ccssecceeseeesseeeeeeeeeeseceeseseeeeessaesesneeeeeseeeesseaeenseeeesseeeseseeeeneas 475 23 6 Screening of One Time PROM Model ccccsscccssseeeeeeeeeeseeeeenseeeeseneeenseeeeseseseseeneeeeas 475 CHAPTER 24 INSTRUC TON SE T oia rE eere r ae arae e aaa e edna rae e aaa rohana aaa aa Ada iaa aa aeiiae 477 24 1 LEGEN A ar E NEA AE E E A r E 478 24 1 1 Operand representation and formats cceeceesceceeeeeeeeeeeeeeeeeeeeeeeeeeseeeeeeeseaeeseeteaeeseneeaes 478 24 1 2 Description of operation column ooooocc
145. 25 x 4 fx 3 2 us 28 x 4 fx 6 4 us 214 x 1 fx 1 64 ms 25 x 4 fx 3 2 us 28 x 4 fx 6 4 us 27 x 1 fx 12 8 us 215 x 1 tx 3 28 ms 27 x 1 fx 12 8 us 28 x 1 fx 25 6 us 29 x 1 fx 51 2 us 217 x 1 fx 13 1 ms 28 x 1 fx 25 6 us 216 x 1 fx 6 55 ms 210 x 1 fx 102 4 us 218 x 1 tx 26 2 ms 212 x 1 fx 409 6 us 210 x 1 fx 102 4 us 212 x 1 fx 409 6 us 29 x 1 fx 51 2 us 220 x 1 fx 104 9 ms Remarks 1 fx Main system clock oscillation frequency 2 TCL10 TCL13 Bits O through 3 of timer clock select register 1 TCL1 3 At fx 10 0 MHz operation Figure 9 10 Square Wave Output Timing Countcock LJ LILI LIU UU UUs uu uo a CSI e O A Count starts oao n 7 AR To noe O e 2 Note The initial value of TO1 output can be set by bits 2 and 3 LVS1 LVR1 of the 8 bit timer output control register TOC1 214 CHAPTER 9 8 BIT TIMER EVENT COUNTER 9 4 2 16 bit timer event counter mode When bit 2 TMC12 of the 8 bit timer mode control register TMC1 is setto 1 the 16 bit timer event counter mode is selected In this mode the count clock is selected by using the bits O through 3 TCL10 through TCL13 of the timer clock select register TCL1 and the overflow signal of the 8 bit timer event counter 1 TM1 is used as the count clock of the 8 bit timer event counter 2 TM2 In this mode coun
146. 27 pin OUtDUL cscscssessesessessesseesessssscsesseessasssesseesesnssssesseeesaeseeess 308 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78018FY SUBSERIES 00 309 16 1 Functions of Serial Interface Channel 0 0 ccccccsccsseeeeseseeeeseeeeeeeeesesneeeeneeeenseaeeenseeeess 310 16 2 Configuration of Serial Interface Channel 0 0 ccc sesecceseesseeeeeeeeeeeneeeeeneeeeeseaeeeneeeeens 311 16 3 Registers Controlling Serial Interface Channel 0 csseeeeseeesseeeeeseeeesseeeeneeeees 316 16 4 Operation of Serial Interface Channel 0 cccccssecceseeeeeeeeeeeseeeeeeeeeseseeeeeeeeeeennaesenseeeeas 323 16 4 1 Operation stop Mode comio ii A aie eid 323 16 4 2 Operation in 3 wire serial l O mode ec eeeceeecceeeeeeeeeeeteeeeeeeeaeeseaeeeaeeeeaeesaeeseaeesseeeeaeeeseeeas 323 16 4 3 Operation in 2 wire serial l O mode ee eecceseceeeeeeeeeeteneeeeeeeeeeeseaeeeaeeseaeesaeeseaeeseeeenaeeenaeesas 328 16 4 4 Operation in IC bus MOE ccssccssscsssscsesescesesesescecesesesescasesessseacesesessscscecensisscscereseseseeceeeses 333 16 4 5 Notes on using 12C bus MOE cscscssssssescssesssescscssesssescesevessscscesenssescscesesssescecesesesesceeereneees 352 16 4 6 Restrictions using 12C bus Mode ccscssssscsescsesesesescscscscscscscssasasssssscacscacsesesescscaesescseseses 355 16 4 7 Manipulating SCKO SCL P27 pin output oo eee eect ect e cece eeeeeteaeeeeeeeeaeeteeeeeaeestaeeeaeetsaeenas 357 CHAPTER
147. 297 15 27 Command Transmit Operation from Master Device to Slave DevViCe ccceeeeeeees 298 15 28 Data Transmit Operation from Master Device to Slave Device ccccceeeseteeeeteees 299 15 29 Data Transmit Operation from Slave Device to Master Device cceccceeeeteeeeeteeees 300 15 30 Example of Serial Bus Configuration by 2 Wire Serial W O eceeeeeeeeeeeeeeeeeeeeeeeeeneees 303 15 31 Timing of 2 Wire Serial l O Mode cecceeeceeeceeeeeeeeeeeeeeeeeeeeeeeseeeeeaeeseeeesaeeseaeesneeeteeseeeeeaeees 306 15 32 Operations of RELT and CMDT c cccccsccccsecceesseeeeeeeeeescaeeeeeeneeeseneeeeceeesscaeeessneeessnseeeee 307 15 33 Configuration of SCKO P27 Pin cccecscsscscssssssescscssesesescesesesescscesssesescasesesssescecenessseaceteseaeseaces 308 16 1 Block Diagram of Serial Interface Channel O ccccccessscceeeeeeeeneeeeseeeeeeneeeeeseeeesneeesennees 312 16 2 Format of Timer Clock Select Register 3 ecccecceeeeeeeeeeeeeeeeeeseeeeeeeeeeeseeeseeeeeeeteeeeeaees 317 16 3 Format of Serial Operation Mode Register 0 ccceeceesceeseeeeeeeseeeeeeeeneeseeeeeeeteeeeeeeteaeess 318 16 4 Format of Serial Bus Interface Control Register ecceeeceeeseeseeeeeeeeeeeeseaeeeeeeeeeeeeeeteaeens 319 16 5 Format of Interrupt Timing Specification Register 00 eeceeeeeeeeeeeeeeeeeeeeeeeeeeeeeeteneteaeee 321 16 6 Timing of 3 Wire Serial I O Mode ccccssccceeecceeeseeeeeeeeeeeeeee
148. 3 4 s 210 x 4 fx 102 4 ps 226 x 1 fx 6 7 s 210 x 1 fx 102 4 us 29 x 1 fx 51 2 us 212 x 1 fx 409 6 us 228 x 1 tx 26 8 s 29 x 1 fx 51 2 us 212 x 1 fx 409 6 us Others Setting prohibited 216 Remarks 1 fx Main system clock oscillation frequency 2 TCL10 TCL13 Bits O through 3 of timer clock select register 1 TCL1 3 At fx 10 0 MHz operation i rN a lu ed CHAPTER 9 8 BIT TIMER EVENT COUNTER 2 Operation as external event counter The external event counter counts the number of clock pulses externally input to the TI1 P33 pin by using the two channels of 8 bit timer registers 1 and 2 TM1 and TM2 Each time the valid edge specified by the timer clock select register 1 TCL1 is input the values of TM1 and TM2 are incremented Either the rising edge or falling edge can be specified as the edge When the count values of TM1 and TM2 coincide with the values of the corresponding 8 bit compare registers CR10 and CR20 TM1 and TM2 are cleared to 0 and an interrupt request signal INTTM2 is generated Figure 9 12 External Event Counter Operation Timing with rising edge specified A LE LE LI LU UU O O O LI l S TM1 TM2 TMS TMt TM2 Y ogo Koon Kooa2X 0003X0004 0005X XN 1X N Kooo0 X000 X 0002 X000 1 CR10 CR20 t N I INTTM2 Caution Even when the two 8 bit timers are used in combination in a
149. 4 SIO1 Receive data 2 R2 See Receive data 3 R3 BGR a 2 ADTP Transmit data 4 T4 Transmit data 5 T5 FACOH Transmit data 6 T6 CSIIF1 l c At end of transmission reception FADFH FAC5H Receive data 1 R1 SIO1 Receive data 2 R2 Receive data 3 R3 ADTP Receive data 4 R4 Receive data 5 R5 FACOH Receive data 6 R6 CSIIF1 ipl 383 i ri oY a lv ed CHAPTER 17 SERIAL INTERFACE CHANNEL 1 b Basic transmit mode This mode is to execute data transmission in 8 bit units by the specified number of times Serial transfer is started by writing any data to the serial I O shift register 1 SIO1 when the bit 7 CSIE1 of the serial operation mode register 1 CSIM1 is set to 1 The interrupt request flag CSIIF1 is set when the last byte has been completely transmitted Note however that the completion of automatic transmission reception should be determined with the bit 3 TRF of the automatic transmit receive control register ADTC instead of CSIIF1 When receive operation busy control and strobe control are not performed the P20 SI1 P23 STB and P24 BUSY pins can be used as ordinary I O ports Figure 17 11 shows the operation timing of the basic transmit mode and Figure 17 12 shows an operation flowchart Figure 17 13 shows the operation of the buffer RAM when 6 bytes are transmitted Figure 17 11 Operation Timing of Basic Transmit Mode Interval
150. 46 16 22 Example of Communication from Slave to Master with 9 clock wait selected for both master and slave oonocnccinncnnocinicnnncnanarnninna nana ninnas 349 16 23 Output of Start CONdItION e PEA A T E E 352 16 24 Releasing Slave from Wait Status during transmission cccceeeeeeeeeeteeeeeeteeeeeeeeeeees 353 16 25 Releasing Slave from Wait Status during reception ceeceeeceeeeeeeeeeeeeeeeeeeteneeeeeeeeees 354 16 26 Configuration of SCKO SCL P27 Pin c ccccescceeeseeeeeeeeeeeeeeeesaaeeeceneeesceeesseeeesseneeessnseeeees 357 16 27 Configuration of SCKO SCL P27 Plica 358 16 28 Logic Gircuit for SCE Sinai id ia aa E aae e ie aias iar iee aaiae 358 17 1 Block Diagram of Serial Interface Channel ou eeeceeecceseceeeeeeeeeeeeeeeeeeseaeeeeeeseaeeseeeeneeesaes 361 17 2 Format of Timer Clock Select Register 3 eecceeceeeeeeeeeeeeeeeneeseeeseeeeeneeseaeeeneeteeeeeeeeeaeee 363 17 3 Format of Serial Operation Mode Register 1 ccceeeceeeseeeeeeeeeeeeeeeeeeeeeeseaeeeeeeteeeeeeeeeaees 364 17 4 Format of Automatic Data Transmit Receive Control RegiStel ooooociccnnnonnnccnncnnccnonccnnnnnns 366 17 5 Format of Automatic Data Transmit Receive Interval Specification Register 367 17 6 Timing of 3 Wire Serial I O Mode oooconcccincccicccioniconcconcncnnncnoncconcnnnncnnnnn ran cn nnnncnn cn nn nnanccnnncnns 369 17 7 Transfer Bit Sequence Select Circuit ooooonnccinccioninncccnncnnonnnnnncnnc
151. 7 are the clocks supplied to the hardware fx 2N 1 is stopped in the HALT mode Remarks 1 N Value N 0 4 set to bits 0 through 2 PCCO PCC2 of processor clock control register PCC 2 fx Main system clock oscillation frequency 3 At fx 10 0 MHz operation 187 CHAPTER 8 16 BIT TIMER EVENT COUNTER 8 5 Operation of 16 Bit Timer Event Counter 8 5 1 Operation as interval timer The 16 bit timer event counter operates as an interval timer when bits 2 and 3 TMC02 and TMCO3 of the 16 bit timer mode control register TMCO are set to 1 1 and repeatedly generates an interrupt request at time intervals specified by the count value set to the 16 bit compare register CROO in advance When the count value of the 16 bit timer register TMO coincides with the value set to CROO the value of TMO is cleared to 0 and TMO continues counting At the same time an interrupt request signal INTTMO is generated The count clock of the 16 bit timer event counter can be selected by bits 4 through 6 TCL04 TCLO6 of the timer clock select register 0 TCLO For the operation when compare register value is changed during timer count operation refer to 8 6 Notes on Using 16 bit Timer Event Counter 3 Figure 8 10 Configuration of Interval Timer 16 bit compare register CROO gt INTTMO fx 2 gt fx 22 gt 16 bit timer register TIMO OVFO TIO POO INTPO gt fx 28 gt
152. 78015F 78016F 78018F and 78P018F are treated as the representative models in this manual If you use the wPD78011F A 78012F A 78013F A 78014F A 78015F A 78016F A 78018F A or 78P018F A take the wPD78011F 78012F 78013F 78014F 78015F 78016F 78018F and 78P018F as the 1PD78011F A 78012F A 78013F A 78014F A 78015F A 78016F A 78018F A and 78P018F A respectively If this manual is used as the manual of the u PD78012F A2 gt Unless otherwise specified the uPD78012F is treated as the representative model of the uwPD78012F A and uPD78012F A2 Ifyou use the uPD78012F A2 take the uwPD78012F as the uPD78012F A2 To understand the overall functions of the uwPD78018F and uPD78018FY subseries Read this manual in the order of the TABLE OF CONTENTS How to read register formats The name of a bit whose number is encircled is reserved for the RA78K 0 and is defined for the CC78K 0 by the header file sfrbit h To learn the detailed functions of a register whose register name is known Refer to APPENDIX D REGISTER INDEX To learn the differences with the uPD78014 and 78014H subseries gt Refer to APPENDIX A DIFFERENCES BETWEEN uPD78014 78014H AND 78018F SUBSERIES To learn the details of the instruction functions of the uPD78018F and uPD78018FY subseries Refer to 78K 0 Series User s Manual Instruction U12326E separately available
153. 8012FGC XXX AB8 78013FGC XXX AB8 1PD78014FGC XXX AB8 78015FGC XXX AB8 78016FGC XXX AB8 1PD78018FGC XXX AB8 78P018FGC AB8 1PD78011FGC A XXX AB8 78012FGC A XXX AB8 78013FGC A XXX AB8 1PD78014FGC A XXX AB8 78015FGC A XXX AB8 78016FGC A XXX AB8 1PD78018FGC A XXX AB8 78P018FGC A AB8 78012FGC A2 XXX AB8 64 pin plastic LQFP 12 x 12 mm 1PD78011FGC XXX 8A8 78012FGK XXX 8A8 78013FGK XXX 8A8 1PD78014FGK XXX 8A8 78015FGK XXX 8A8 78016FGK XXX 8A8 1PD78018FGK XXX 8A8 78P018FGK 8A8 64 pin ceramic WQFN 14 x 14 mm u4PD78P018FKK S O P23 STB O P22 SCK1 O P21 SO1 O P20 SHM O AVnrer O AVoo O P17 ANI7 O P16 ANI6 O P15 ANI5 O P14 ANI4 O P13 ANI3 O P12 ANI2 lt gt 0 P26 SO0 SB1 gt 0 P25 SI0 SBO O P27 SCKO gt 0 P24 BUSY o o o o P30 TOO O lt 1 O P11 ANI1 P31 TO1 O lt gt 2 O P10 ANIO P32 TO2 O O AVss P33 T11 O P04 XT1 P34 T12 O O XT2 P35 PCL O O IC Ver P36 BUZ O O X1 P37 O O X2 Vss O O Vop P40 ADO O O POS INTP3 P41 AD1 O O PO2 INTP2 P42 AD2 O O PO1 INTP1 P43 AD3 O O POO INTPO TIO P44 AD4 O O RESET P45 AD5 O O P67 ASTB P46 AD6 O O P66 WAIT 7 3 P47 AD7 O P55 A13 O lt gt O O O O O O O O O O 0 0 0 0 o Q O r N 29 Y O Or AQI Ll gt gt gt O O O Oj So gt zt cece xataaqaeagoeas Oye OS SS gt FS O oOo N Y N o Y 0 A 10 10 10 LO LO e ao aa a a a Cautions 1 Directly connect the
154. 8012FYCW XXX 64 pin plastic shrink DIP 750 mil Mask ROM uPD78012FYGC XXX AB8 64 pin plastic QFP 14 x 14 mm Mask ROM uUPD78012FYGK XXX 8A8 64 pin plastic LQFP 12 x 12 mm Mask ROM HPD78013FYCW XXX 64 pin plastic shrink DIP 750 mil Mask ROM uPD78013FYGC XXX AB8 64 pin plastic QFP 14 x 14 mm Mask ROM uUPD78014FYCW XXX 64 pin plastic shrink DIP 750 mil Mask ROM uPD78014FYGC XXX AB8 64 pin plastic QFP 14 x 14 mm Mask ROM uUPD78014FYGK XXX 8A8 64 pin plastic LQFP 12 x 12 mm Mask ROM HPD78015FYCW XXX 64 pin plastic shrink DIP 750 mil Mask ROM uPD78015FYGC XXX AB8 64 pin plastic QFP 14 x 14 mm Mask ROM HPD78016FYCW XXX 64 pin plastic shrink DIP 750 mil Mask ROM H4PD78016FYGC XXX AB8 64 pin plastic QFP 14 x 14 mm Mask ROM HPD78018FYCW XXX 64 pin plastic shrink DIP 750 mil Mask ROM uUPD78018FYGC XXX AB8 64 pin plastic QFP 14 x 14 mm Mask ROM HPD78P018FYCW 64 pin plastic shrink DIP 750 mil One time PROM HPD78P018FYDW 64 pin ceramic shrink DIP with window 750 mil EPROM HPD78P018FYGC AB8 HPD78P018FYGK 8A8 HPD78P018FYKK S 64 pin plastic QFP 14 x 14 mm 64 pin plastic LQFP 12 x 12 mm 64 pin ceramic WQFN 14 x 14 mm Remark XXX indicates ROM code suffix 54 One time PROM One time PROM EPROM CHAPTER 2 GENERAL uPD78018FY SUBSERIES 2 4 Quality Grade Part Number Package Quality Grade uPD78011FYCW XXX 64 pin plastic shrink DIP 750 mil Standard uPD78011FYGC XXX AB8 64 pin plastic QFP 14 x 14 mm S
155. 9 7 Format of Port Mode Register 3 Address On reset R W PM3n Selects I O mode of P3n pin n 0 7 0 Output mode output buffer ON 1 Input mode output buffer OFF i ri oY a lv ed CHAPTER 9 8 BIT TIMER EVENT COUNTER 9 4 Operation of 8 Bit Timer Event Counter 9 4 1 8 bit timer event counter mode 1 Operation as interval timer The 8 bit timer event counters operate as interval timers and repeatedly generate an interrupt request at time intervals specified by the count values set to the corresponding 8 bit compare registers CR10 and CR20 in advance When the count values of the 8 bit timer registers 1 and 2 TM1 and TM2 coincide with the values set to the corresponding compare registers CR10 and CR20 the values of TM1 and TM2 are cleared to 0 TM1 and TM2 continue counting and atthe same time interrupt request signals INTTM1 and INTTM2 are generated The count clock ofthe TM1 can be selected by bits Othrough 3 TCL10 TCL13 ofthe timer clock select register 1 TCL1 and the count clock of the TM2 can be selected by the bits 4 through 7 TCL14 TCL17 of TCL1 For the operation when compare register value is changed during timer count operation refer to 8 6 Notes on Using 16 bit Timer Event Counter 3 Figure 9 8 Interval Timer Operation Timing 1 l t 1 e 1 1 1 1 j 1 l 1 TMi count value 00 Ka Xn Xoko Xn OEA A A a Count starts Clear Clear i
156. AA Quality A OT 1 5 Pin Configuration Top View ooo 1 6 Product Development of 78K 0 Series ccceccesseeseeeeeeeeeeesneeeeeeeeeesseaeeneeeeeeseeeeeseeees 1 7 Block DIAM cada AEn Snai Eiaa heia 1 8 Fun tional Qutline ivi raaa aaa aaa aiia aaa a aai 1 9 Differences from Standard Quality Models and A Models cccsssseeeeeees 1 10 Differences between A Model and A2 Model eeceeeeeeeeeeeneeneeeeeeeeeeeeeeeees TVA IMASK AN ida CHAPTER 2 GENERAL uPD78018FY SUBSERIES ccsseeeeeseeeeseeeeeeeeeeeseeeeeeseeeensesenseeeeneas LN A A settvessecactns 2 2 Application Field cccccesseeeceeeeeneeseeeeeeeeseeeesneeeseeessneeseeeesneeeseeeesneeseeeesseeeseeeesneeeseseeenenes 2 3 Ordering Informations 2 4 7 Quality Grade i n 2 5 Pin Configuration Top View ssseccesseessseeeeeeeeseceeseeeeeesecaeseseeeeeeseesesseeeeeeeeeeeneeneneees 2 6 Product Development Of 78K 0 Series cccceccssseeeeseeeeeeeeeseseeeeeseeeseseaeeeeeeeeensaeeeneees 2 1 Block Diagram onera aaa aaa E EAA Eaa N ea a i EA S 2 8 Functional QUUIME srssormires enmen anne este iii dnddntas 2 9 Mask Op O a e a iii ce aE aaa che EE aa Sae dupes inicien CHAPTER 3 PIN FUNCTIONS uPD78018F SUBSERIES 0ccccsccssseeceeeeeessseeseseeeeseseeeeseeeeeeeas S t Listot Pin FUNCHUONS co caccccnanaina adan die cacepeeecereseavacetecducdaes osssseadenbaasenecetecudrects sa steaccsancaces 3 1 1 Pinsiin norm
157. ADIS lt 2 gt Select one channel for A D conversion by using the A D converter mode register ADM from the channels set as analog inputs by ADIS 2 The channel set as an analog input by ADIS is not connected to the internal pull up resistor regardless of the value of bit 1 PUO1 of the pull up resistor option register Figure 14 3 Format of A D Converter Input Select Register Symbol 7 6 Address On reset R W 5 4 3 2 1 0 ADIS fo o ofo ans ADIS2 ADIS1 ADISO FF84H 00H R W ADIS2 ADIS1 ADISO Selects number of analog input channels None P10 P17 1 channel ANIO P11 P17 2 channels ANIO ANI1 P12 P17 3 channels ANIO ANI2 P13 P17 4 channels ANIO ANI3 P14 P17 5 channels ANIO ANI4 P15 P17 6 channels ANIO ANI5 P16 P17 7 channels ANIO ANI6 P17 8 channels ANIO ANI7 Others Setting prohibited 250 CHAPTER 14 A D CONVERTER 14 4 Operation of A D Converter 14 4 1 Basic operation of A D converter lt 1 gt lt 2 gt lt 3 gt lt 4 gt lt 5 gt lt 6 gt lt gt lt 8 gt lt 9 gt Set the number of analog input channels by using the A D converter input select register ADIS Select one channel for A D conversion by using the A D converter mode register ADM from the channels set as analog inputs by ADIS The voltage input to the selected analog input channel is sampled by the sample and hold circuit When the vol
158. ADTC 385 CHAPTER 17 SERIAL INTERFACE CHANNEL 1 386 The buffer RAM operates as follows when 6 bytes are transmitted in the basic transmit mode ARLD 0 RE 0 i Before transmission Refer to Figure 17 13 a Transfer data 1 T1 is transferred from the buffer RAM to serial I O shift register 1 SIO1 after arbitrary data has been written to SIO1 start trigger this data is not transferred When the first byte has been completely transferred automatic data transmit receive address pointer ADTP is decremented Subsequently transfer data 2 T2 is transferred from buffer RAM to SIO1 ii When 4th byte is transmitted Refer to Figure 17 13 b When the third byte has been transmitted completely transmit data 4 T4 is transferred from the buffer RAM to SIO1 When the fourth byte has been transmitted and ADTP is decremented iii End of transmission Refer to Figure 17 13 c When the sixth byte has been transmitted an interrupt request flag CSIIF1 is set INTCSI1 occurs CHAPTER 17 SERIAL INTERFACE CHANNEL 1 Figure 17 13 Buffer RAM Operation when 6 Bytes Are Transmitted in basic transmit mode a Before transmission FADFH FAC5H FACOH Transmit data 1 T1 e SIO1 Transmit data 2 T2 a EEE Transmit data 3 T3 AE AA o CLs A 5 ADTP Transmit data 4 T4 Transmit data 5 T5 e Transmit data 6 T6 3 Fo CSIIF1 b When 4th byte has been transmitte
159. CE EXTENSION FUNCTI ASTB RD ADO AD7 A8 A15 ASTB RD ADO AD7 A8 A15 Internal wait signal 1 clock wait ASTB RD ADO AD7 A8 A15 WAIT Figure 19 4 Instruction Fetch from External Memory a When no wait state is set PW1 PWO 0 0 High order address b When wait state is set PW1 PWO 0 1 High order address c When external wait state is set PW1 PWO 1 1 i es oe o OSES X Low order address X address Instruction code X X High order address X 433 CHAPTER 19 EXTERNAL DEVICE EXTENSION FUNCTION 434 ASTB RD ADO AD7 A8 A15 ASTB RD ADO AD7 A8 A15 Internal wait signal 1 clock wait ASTB ADO AD7 A8 A15 WAIT Figure 19 5 Read Timing of External Memory a When no wait state is set PW1 PWO 0 0 LY a aS n S S O X High order address b When wait state is set PW1 PWO 0 1 _ _ E o SS X High order address c When external wait state is set PW1 PWO 1 1 E A sess Read data X High order address CHAPTER 19 EXTERNAL DEVICE EXTENSION FUNCTI ASTB WR ADO AD7 A8 A15 ASTB WR ADO AD7 A8 A15 Internal wait signal 1 clock wait ASTB ADO AD7 A8 A15 WAIT Figure 19 6 Write Timing of External Memory a When no wait state is set PW1 PWO 0 0 Hi Z 7 pR es Wie da High order address b When wait state is set PW1 PWO 0 1 ge a tia a a m
160. CORAD1 when the corresponding correction enable flags CORENO and COREN1 are 0 i e when correction branch processing is disabled If an address is put into CORADO or CORAD1 when CORENO or COREN1 is 1 when correction branch processing is enabled there is a possibility that correction branch processing will be started from an address different from that intended Do not put an instruction address immediately following an instruction that sets a correction enable flag CORENO or COREN1 into a correction address registers 0 or 1 CORADO or CORAD1 because correction branch processing may not be started Do not put an address value 0040H to 007FH in the table area of the table reference instruction CALLT or an address value 0000H to 003FH in the vector table area into a correction address register O or 1 CORADO or CORAD1 Do not put the two addresses immediately following any of the instructions below into a correction address register 0 or 1 CORADO or CORADY1 if the destination address to which these instructions are mapped is N do not use addresses N 1 and N 2 RET RETI RETB BR addr16 STOP HALT CHAPTER 23 uPD78P018F 78P018FY The uPD78P018F and 78P018FY are provided with a one time PROM which can be written only once or an EPROM from to which a program can be written erased and rewritten The differences between the PROM models uPD78P018F 78P018FY and the mask ROM models 1PD78011F 7801
161. CSIO 0 1 Sets CSIIFO at end of transfer by serial interface channel 0 Sets CSIIFO at end of transfer by serial interface channel 0 or on detection of stop condition in I C mode R CLD Level of SCKO SCL P27 pinNote2 0 Low level 1 High level Notes 1 Bit 6 CLD is a read only bit 2 CLD is 0 when CSIEO 0 Caution When using 2 wire serial l O mode be sure to set bits 0 through 3 to 0 Remark CSIIFO Interrupt request flag corresponding to INTCSIO 330 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78018FY S 2 Communication operation In the 2 wire serial l O mode data is transmitted received in 8 bit units Data is transmitted received on a 1 bit by 1 bit basis in synchronization with the serial clock The shift operation of the serial I O shift register 0 SIOO is performed in synchronization with the falling edge of the serial clock SCKO The transmitted data is retained by the SOO latch and output from the SBO P25 or SB1 P26 pin starting from the MSB The received data input from the SBO or SB1 pin is latched to the SIO0 at the rising edge of SCKO When the 8 bit data has been completely transferred the operation of the shift register is automatically stopped and an interrupt request flag CSIIFO is set Figure 16 10 Timing of 2 Wire Serial I O Mode SCKO SBO0 SB1 CSIIFO Transfer ends Transfer starts in synchronization with falling edge of SCKO The pin specifie
162. Cis 11 00001 PC1o 0 addr11 SP SP 2 addr5 SP 1 PC 1 u SP 2 PC 1 PCH 00000000 addr5 1 PC lt 00000000 addr5 SP SP 2 SP 1 PSW SP 2 PC 1 h SP 3 PC 1 PCH 003FH PC 003EH SP amp SP 3 IE 0 PCH lt SP 1 PCL amp SP SP SP 2 PCH SP 1 PCL lt SP PSW SP 2 SP SP 3 NMIS 0 PCH SP 1 PCL lt SP PSW lt SP 2 SP lt SP 3 Notes 1 When the internal high speed RAM area is accessed or when an instruction that does not access data is executed 2 When an area other than the internal high speed RAM area is accessed Remarks 1 One clock of an instruction is equal to one CPU clock fcru selected by processor clock control register PCC 2 The number of clocks shown is when the program is stored in the internal ROM area 3 n indicates the number of wait states when the external memory extension area is read 4 m indicates the number of wait states when the external memory extension area is written 486 CHAPTER 24 INSTRUCTION SET Instruction Group Stack manipulation Mnemonic Operand Operation SP 1 PSW SP e SP 1 SP 1 lt rph SP 2 lt rp SP e SP 2 PSW lt SP SP SP 1 rph lt SP 1 rpl lt SP SP SP 2 SP word SP lt word SP A
163. D78078 48 K 60 K uPD78070A uPD780058 24 K 60 K HPD78058F 48 K 60 K uPD78054 16 K 60 K uPD780034 8 K 32 K uPD780024 uPD78014H HPD78018F 8 K 60 K uPD78014 16 bit Watch Serial Interface 3ch UART 1ch Voo MIN Value 3ch time division UART 1ch 3ch UART 1ch 3ch UART 1ch time division 3 wire 1ch uPD780001 uPD78002 uPD78083 1PD780988 32 K 60 K 2ch External Expansion 1PD780964 8 K 32 K uUPD780924 1PD780208 32 K 60 K 1ch UART 1ch 3ch UART 2ch 1PD780228 48 K 60 K 2ch UART 2ch 1PD78044H 32 K 48 K 1PD78044F 16 K 40 K 1PD780308 48 K 60 K 1PD78064B 32K uPD78064 16 K 32 K 1PD78098B 40 K 60 K uPD78098 32 K 60 K 1PD780973 24 K 32 K 3ch Ich ich ich Sch 2ch UART 1ch 56 4 5 V Notes 1 16 bit timer 2 channels 10 bit timer 1 channel 2 10 bit timer 1 channel 3ch time division UART 1ch 2ch UART 1ch 3ch UART 1ch 47 CHAPTER 1 GENERAL 1 PD78018F SUBSERIES 1 7 Block Diagram POO PORTO P01 P03 TOO P30 16 bit TIMER TIO INTPO POO gt EVENT COUNTER Spd TO1 P31 8 bit TIMER EVENT PORT1 P10 P17 TH P33 gt COUNTER 1 PORT2 P20 P27 TO2 P32 8 bit TIMER EVENT T12 P34 gt COUNTER 2
164. DOS Prompt when using in Windows Part Number uSxxxxRX78013 AAAA Caution When purchasing the RX78K O fill in the purchase application form in advance and sign the User Agreement Remark xxxx and AAA in the part number differ depending on the host machine and OS used USxxxxRX78013 AAAA aaa Product Outline Maximum Number for Use in Mass Production Evaluation object Do not use for mass produced product Mass production object 0 1 million units 1 million units 10 million units Source program Source program for mass produced object Host Machine Supply Medium PC 9800 Series Windows Japanese version Note 1 2 3 5 inch 2HD FD IBM PC AT and its compatibles Windows Japanese version Note 1 2 3 5 inch 2HC FD Windows English version Note 1 2 HP9000 Series 700 HP UX Rel 9 05 DAT DDS SPARCstation SunOS Rel 4 1 4 3 5 inch 2HC FD 1 4 inch CGMT NEWS RISC NEWS OS Rel 6 1 3 5 inch 2HC FD Notes 1 Can also be operated in DOS environment 2 Not support WindowsNT 510 APPENDIX C EMBEDDED SOFTWARE Real Time OS 2 2 MX78KO OS MX78K 0 is an OS for uITRON specification subsets A nucleus for the MX78K 0 is also included as a companion product This manages tasks events and time In the task management determining the task execution order and switching from task to the next task are performed lt Precaution when using MX78K 0 in PC en
165. E1 FF49H 00H RW TCE1 Controls operation of 8 bit timer register 1 0 Stops operation TM1 is cleared to 0 TMC1 1 Enables operation TCE2 Controls operation of 8 bit timer register 2 0 Stops operation TM2 is cleared to 0 1 Enables operation TMC12 Selects operation mode 0 8 bit timer register x 2 channel mode TM1 TM2 1 16 bit timer register x 1 channel mode TMS Cautions 1 Before changing the operation mode stop the timer operations 2 When TM1 and TM2 are used together as a 16 bit timer register TMS set enable or disable of the operation by using the TCE1 208 CHAPTER 9 8 BIT TIMER EVENT COUNTER 3 8 bit timer output control register TOC1 This register controls the operations of the 8 bit timer event counter output control circuits 1 and 2 lt sets resets an R S flip flops LV1 LV2 enables disables inversion of the timer output F F and enables disables the outputs of 8 bit timer registers 1 and 2 TOC1 is set by a 1 bit or 8 bit memory manipulation instruction This register is set to OOH when the RESET signal is input Figure 9 6 Format of 8 Bit Timer Output Control Register Symbol lt 7 gt lt 6 gt 5 lt 4 gt lt 3 gt lt 2 gt 1 LVS2 LVR2 TOC15 TOE2 LVS1 LVR1 TOC11 El lt 0 gt Address On reset R W TOE1 TOC1 FF4FH 00H R W TOE1 Controls output of 8 bit timer event counter 1 0 Disables output port mode 1 Enables
166. Event Counter 1 cccccccececeeeeeeeseeeeeesceeeeeeeeeessaeeessneeesseees 212 9 7 Interval Time of 8 Bit Timer Event Counter 2 ccccccceccceeeeeeeeeseeeeceeeeseeeeessaeeesseeesseees 212 31 LIST OF TABLES 2 3 Table No Title Page 9 8 Square Wave Output Range of 8 Bit Timer Event Counters cccccceeseeeceeeteeesenseeeeees 214 9 9 Interval Time when Two 8 Bit Timer Event Counters TM1 and TM2 Are Used as One 16 Bit Timer Event Counter ecceeeceeeseeeeeeteeenees 216 9 10 Square Wave Output Range when Two 8 Bit Timer Event Counters TM1 and TM2 Are Used as One 16 Bit Timer Event Counter cococccccnccccnocccanccnonnconcnnnnc conc nran cnn nc ran nannn cnn 218 10 1 Interval Time of Interval Timer 0 ceecssececesceetenseeeeneneeeeseeeeesssenenaeeeseseeenesenensneneeseseeeees 221 10 2 Configuration of Watch Timer c ceccesseseseeseeeeeeeseeeeaeeeseeeeaeeeseeteaeeeeaeseaeeseaeeeaeeseaeesieeseaeene 222 10 3 Interval Time of Interval Timer ooonoccnonncccnnoccnnnncnnnorncnnnoncnnnncn cananea 227 11 1 Inadvertent Loop Detection Time of Watchdog Timer eceeesseeeeeneeeeeneeeeeneeeeeneeeteeeee 229 11 2 Interval iMesh ee 229 11 3 Configuration of Watchdog Time ccecceeeceeeceeeneeeeeeeeeeeeeeeeeeeseaeesaeeseaeeseeeenaeesiaeeeeesnaeenas 230 11 4 Inadvertent Loop Detection Time of Watchdog Timer eceeeeseeeesneeeeeneeeeeeneeteeneeeteeees 235 11 5 Interval Time of Inte
167. F SUS 4 Signals Figures 15 19 through 15 24 show the signals of serial bus interface control register SBIC and the operations of the flags of SBIC Table 15 4 lists the signals of SBI Figure 15 19 Operations of RELT CMDT RELD and CMDD Master Writes slave address to SIOO transfer start command SIO0 ON 7 A SCKO T Z T PI lt a RELD ys WN y CMDD N Figure 15 20 Operations of RELD and CMDD Slave Writes FFH to SIOO transfer start command Transfer start command soo OME SCKO 7 2 7 e o Slave address SBO SB1 When addresses match e When addresses do not mate RELD CMDD 289 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 uPD78018F SUBSERI 290 Figure 15 21 Operation of ACKT SCKO 6 7 8 9 SBO SB1 oz X o X oo ACK ACK signal is output for duration of 1 clock immediately after it has been set ACKT Ss If set during this period Caution Do not set ACKT before end of transfer CHAPTER 15 SERIAL INTERFACE CHANNEL 0 uPD78018F SUS Figure 15 22 Operation of ACKE a When ACKE 1 at end of transfer SCKO 1 2 ssassn EA ACKE ACK signal is output at 9th clock 12 When ACKE 1 at this point b When set after transfer SCKO 6 7 8 9 b sBo sB1 X D2 X Di X Do ACK ACK signal is output for duration of 1 clock immediately after it has been set ACKE gt
168. F78014 Part Number SxxxxSM78K0 Remark xxxx in the part number differs depending on the host machine and OS used uSxxxxSM78K0 Host Machine Supply Medium Note PC 9800 Series Windows Japanese version 3 5 inch 2HD FD IBM PC AT and its compatibles Windows Japanese version Note 3 5 inch 2HC FD Note Windows English version Note Not support WindowsNT 503 APPENDIX B DEVELOPMENT TOOLS B 3 2 Software 2 2 ID78KO NSNote Integrated Debugger supporting in circuit emulator IE 78KO NS 1D78K0 Integrated Debugger supporting in circuit emulator IE 78001 R A Note Under development This debugger is a control program to debug 78K 0 Series microcontrollers It adopts a graphical user interface which is equivalent visually and operationally to Windows or OSF Motif It also has an enhanced debugging function for C language programs and thus trace results can be displayed on screen in C language level by using the windows integration function which links a trace result with its source program disassembled display and memory display In addition by incorporating function modules such as task debugger and system performance analyzer the efficiency of debugging programs which run on real time OSs can be improved It should be used in combination with the optical device file DF78014 Part Number SxxxxID78KO NS uSxxxxID78K0 Remark xxxx in the part number d
169. FERENCES BETWEEN uPD78014 78014H AND 78018F SUBSERIES Table A 1 shows the major differences between the uPD78014 78014H and 78018F subseries Table A 1 Major Differences Between PD78014 78014H and 78018F Subseries 1 2 Pipes Part Number EMI noise measure 1PD78014 Subseries None 1PD78014H Subseries Provided UPD78018F Subseries None 12C bus model Y subseries Provided None Provided PROM model HPD78P014 4PD78P018F Supply voltage Voo 2 7 to 6 0 V Voo 1 8 to 5 5 V Internal high speed RAM size uPD78011B 512 bytes uPD78012B 512 bytes 4PD78013 1024 bytes 1PD78014 1024 bytes HPD78P014 1024 bytes 4PD78011H 512 bytes HPD78012H 512 bytes 4PD78013H 1024 bytes 1PD78014H 1024 bytes HPD78011F 512 bytes 4PD78012F 512 bytes HPD78013F 1024 bytes 4PD78014F 1024 bytes HPD78015F 1024 bytes uUPD78016F 1024 bytes HPD78018F 1024 bytes uPD78P018F 1024 bytes Internal extension RAM size 4PD78011F None 4PD78012F None 4PD78013F None 4PD78014F None 4PD78015F 512 bytes 4PD78016F 512 bytes HPD78018F 1024 bytes H4PD78P018F 1024 bytes Operation mode of serial interface Y subseries 3 wire 2 wire SBI I2C 1 ch 3 wire with automatic transmission reception 1ch 3 wire 2 wire I2C 1 ch 3 wire with automatic transmission reception 1 ch Bit 5 SIC of interrupt timing specification register SINT in SBI mode selection of
170. FGC XXX AB8 78015FGK XXX 8A8 HPD78016FCW XXX 78016FGC XXX AB8 78016FGK XXX 8A8 1PD78018FCW XXX 78018FGC XXX AB8 78018FGK XXX 8A8 HPD78P018FCW 78P018FGC AB8 78P018FGK 8A8 1PD78011FCW A XXX 78011FGC A XXX AB8 HPD78012FCW A XXX 78012FGC A XXX AB8 7801 2FGC A2 XXX AB8 1PD78013FCW A XXX 78013FGC A XXX AB8 HPD78014FCW A XXX 78014FGC A XXX AB8 HPD78015FCW A XXX 78015FGC A XXX AB8 A X ee O 1PD78016FCW A XXX 78016FGC A XXX AB8 uPD78018FCW A XXX 78018FGC A XXX AB8 1PD78P018FCW A 78P018FGC A AB8 uPD78011FYCW XXX 78011FYGC XXX AB8 78011FYGK XXX 8A8 1PD78012FYCW XXX 78012FYGC XXX AB8 78012FYGK XXX 8A8 uPD78013FYCW XXX 78013FYGC XXX AB8 1PD78014FYCW XXX 78014FYGC XXX AB8 78014FYGK XXX 8A8 1PD78015FYCW XXX 78015FYGC XXX AB8 uPD78016FYCW XXX 78016FYGC XXX AB8 uPD78018FYCW XXX 78018FYGC XXX AB8 uPD78P018FYCW 78P018FYGC AB8 78P018FYGK 8A8 al UNO The application circuits and their parameters are for reference only and are not intended for use in actual design ins Purchase of NEC 12C components conveys a license under the Philips 12C Patent Rights to use these components in an 12C system provided that the system conforms to the I2C Standard Specification as defined by Philips The information in this document is subject to change without notice No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corpor
171. Features Mode used when serial transfer is not executed e Can reduce power consumption Applications 3 wire serial l O mode SCK1 serial clock SO1 serial output SI1 serial input e Independent input and output lines Short data transfer processing time because transmission and reception can be executed simultaneously e First bit of 8 bit data to be serial transferred can be specified to be MSB or LSB 3 wire serial I O mode with automatic transmit receive function MSB LSB first selectable SCK1 serial clock SO1 serial output SI1 serial input e This mode has an automatic transmit receive function as well as the same functions as 3 wire serial I O mode e Can transmit receive up to 32 bytes of data Therefore data can be transmitted received by hardware to from display controller driver device for OSD on screen display that operates independently of CPU Asa result workload of software can be reduced Useful for connecting peripheral I Os and display controllers with conventional clocked serial interface such as 75X XL series 78K se ries and 17K series 359 CHAPTER 17 SERIAL INTERFACE CHANNEL 1 17 2 Configuration of Serial Interface Channel 1 Serial interface channel 1 consists of the following hardware Table 17 2 Configuration of Serial Interface Channel 1 Item Configuration Register Serial I O shift register 1 S101 Automatic data transmit receive address
172. H Internal ROM 49152 x 8 bits 0000H Y 120 CHAPTER 5 CPU ARCHITECTURE FFFFH Special function registers SFRs 256 x 8 bits SFR addressing A AAA FF1FH A FFOOH Y FEFFH A General purpose registers 32 x 8 bits Register addressing Short direct FEEOH Y addressing FEDFH Internal high speed RAM 1024 x 8 bits A nee eg ot onsets Y FBOOH FAFFH Reserved FAEOH EADEH Internal buffer RAM FACOH 32 x 8 bits FABFH Reserved F800H F7FFH Internal extension RAM 1024 x 8 bits F400H F3FFH Reserved FOOOH EFFFH Internal ROM 61440 x 8 bits 0000H Direct addressing Register indirect addressing Based addressing Based indexed addressing Note If the internal ROM capacity is 60 KB an area of FOOOH F3FFH cannot be used By setting the internal ROM capacity to 56 KB or less with the memory size select register IMS an area of FOOOH F3FFH can be used as an external memory area 121 CHAPTER 5 CPU ARCHITECTURE FFFFH Special function registers SFRs 256 x 8 bits SFR addressing A MS nereze anit urbane Mare tet Bees AR FF1FH A FFOOH Y FEFFH A General purpose registers 32 x 8 bits Register addressing Short direct FEEOH Y addressing FEDFH Internal high speed RAM 1024 x 8 bits AS Y FBOOH FAFFH Reserved FAEOH FADER Internal buffer RAM FACOH 32 x 8 bits FABFH Reserved F800H F7FFH Internal extension
173. H F3FFH can be used as an external memory by setting the internal ROM capacity to 56 KB or less with the memory size select register IMS 97 CHAPTER 5 CPU ARCHITECTURE Data memory space A Program memory space e A an Ee Figure 5 8 Memory Map uPD78P018F 78P018FY FBOOH FAFFH FAEOH FADFH FACOH FABFH F800H F7FFH F400H F3FFH FOOOH EFFFH 0000H Special function register SFR 256 x 8 bits General purpose register 32 x 8 bits Internal high speed RAM 1024 x 8 bits Reserved eye Ih Program area Internal buffer RAM 32 x 8 bits uel OFFFH Reserved CALLF entry area 0800H Internal extension RAM 07FFH 1024 x 8 bits Program area 0080H Reserved 007FH CALLT table area 0040H 003FH Internal PROM 61440 x 8 bits Vector table area 0000H Note When the internal PROM capacity is 60 KB the area of FOOOH F3FFH cannot be used The area of FOOOH F3FFH can be used as an external memory by setting the internal PROM capacity to 56 KB or less with the memory size select register IMS 98 CHAPTER 5 CPU ARCHITECTURE 5 1 1 Internal program memory space The internal program memory space stores programs and table data This space is usually addressed by the program counter PC Each model in the PD78018F 78018FY subseries is provided with the following internal ROM or PROM Table 5 1 Internal ROM Capacit
174. HL bit CY sfr bit CY A bit CY PSW bit CY HL bit Nj Oo N 0 0O N oa nNn oj oao njo nj oj o n o n o o n oao n o oao Notes 1 When the internal high speed RAM area is accessed or when an instruction that does not access data is executed 2 When an area other than the internal high speed RAM area is accessed Remarks 1 One clock of an instruction is equal to one CPU clock fcru selected by processor clock control register PCC 2 The number of clocks shown is when the program is stored in the internal ROM area 3 n indicates the number of wait states when the external memory extension area is read 4 m indicates the number of wait states when the external memory extension area is written 485 CHAPTER 24 INSTRUCTION SET Instruction Clock Ga Mnemonic Operand Operation Note 1 Note 2 Bit saddr bit manipulation sfr bit 12 saddr bit 1 16 sfr bit 1 Abit PSW bit HL bit A bit 1 12 PSW bit 1 16 2n 2m HL bit 1 saddr bit 12 saddr bit O 16 sfr bit 0 sfr bit A bit PSW bit HL bit oe A bit 0 12 PSW bit 0 Pl NTN wo nym rm NM Ww 16 2n 2m HL bit O CY CY lt 1 CY CY lt 0 CY CY CY Call return laddr16 SP 1 PC 3 n SP 2 PC 3 PC lt addr16 SP e SP 2 laddr11 SP 1 PC 2 h SP 2 PC 2 L P
175. INTCSIO interrupt source When SIC 1 sets CSIIFO interrupt request flag on detection of bus release When SIC 1 Sets CSIIFO interrupt request flag on detection of bus release and at end of transfer Bit 5 SIC of interrupt timing specification register SINT in 12C bus mode selection of INTCSIO interrupt source When SIC 1 Sets CSIIFO interrupt request flag on detection of stop condition When SIC 1 Sets CSIIFO interrupt request flag on detection of stop condition and at end of transfer 493 APPENDIX A DIFFERENCES BETWEEN PD78014 78014H AND 78018F SU Table A 1 Major Differences Between PD78014 78014H and 78018F Subseries 2 2 Part Number 1PD78014 Subseries Function of bit 7 BSYE of serial bus interface control register SBIC Y subseries Control of synchronous bus signal output e When BSYE 0 Disables output of busy signal in synchronization with falling edge of clock of SCKO immediately after instruction that clears this bit to O in SBI mode Make sure that BSYE 0 in 12C bus mode When BSYE 1 Outputs busy signal from falling edge of SCKO following acknowledge signal in SBI mode 1PD78014H Subseries UPD78018F Subseries Control of N ch open drain output for transmission in 12C bus mode e When BSYE 0 Enables output transmis sion e When BSYE 1 Disables output recep tion Automatic data transmit receive interval specif
176. IOO is always the same Therefore specify whether the MSB or LSB is first before writing data to the shift register 275 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 uPD78018F SUBSERIER 5 Transfer start Serial transfer is started by setting the transfer data to the serial I O shift register O SIOO when the following two conditions are satisfied e Operation control bit of serial interface channel 0 CSIEO 1 When internal serial clock is stopped or SCKO is high after 8 bit serial transfer Caution Even if CSIEO is set to 1 after data has been written to SIOO transfer is not started Serial transfer is automatically stopped at the end of 8 bit transfer and an interrupt request flag CSIIFO is set 15 4 3 Operation in SBI mode SBI serial bus interface is a high speed serial interface mode conforming to NEC s serial bus format SBI is a clocked serial I O method in a format with a function for bus configuration added so that a single master can communicate with two or more devices with a high speed serial bus consisting of two signal lines Therefore the number of ports and wirings on a printed wiring board can be reduced when the serial bus consists of plural microcomputers and peripheral ICs The master can output addresses that select the target device s for serial communication commands that directs the target device s and actual data to the slaves via serial data bus A slave can
177. If the output impedance of the reference voltage source is high therefore an error of the reference voltage increases by connecting the impedance in parallel with the series resistor string between the AVrer and AVss pins 8 AVss pin This is a ground pin of the A D converter Be sure to use this pin at the same voltage as that on the Vss pin always even when the A D converter is not used 9 AVob pin This is an analog pin of the A D converter Be sure to use this pin at the same voltage as that on the Vpp pin always even when the A D converter is not used 14 3 Registers Controlling A D Converter The following two registers control the A D converter A D converter mode register ADM A D converter input select register ADIS 1 A D converter mode register ADM This register sets the channel of an analog input to be converted into a digital value conversion time starts stops conversion operation and sets an external trigger ADM is set by a 1 bit or 8 bit memory manipulation instruction This register is set to 01H when the RESET signal is input 248 CHAPTER 14 A D CONVERTER Figure 14 2 Format of A D Converter Mode Register Symbol lt 7 gt Address On reset R W ADM1 Selects analog input channel Selects A D conversion time Note 160 fx At fx 10 0 MHz Setting prohibited At fx 8 38 MHz 19 1 us At fx 5 0 MHz 32 0 us At fx 4 19 MHz 80 fx Setting
178. L D4 O O Open D5 O O VPP D6 O O L D7 O O Open Vss O O Voo A0 O O L A10 O PGM A2 O O L A3 O O A9 A4 O O RESET A5 O O A6 O O L A7 O O CE A8 O O OE A16 O O A10 O gt O A110 o B A12 O O O O O O Cautions 1 L Individually connect this pin to Vss via a pull down resistor 10 kQ 2 Vss Connect this pin to ground 3 RESET Fix this pin to the low level 4 Open Leave this pin unconnected 59 CHAPTER 2 GENERAL uPD78018FY SUBSERIES 64 pin plastic QFP 14 x 14 mm u4PD78P018FYGC AB8 e 64 pin plastic LQFP 12 x 12 mm u4PD78P018FYGK 8A8 64 pin ceramic WQFN 14 x 14 mm u4PD78P018FYKK S gt O Vss O Vpop 64 63 62 61 60 59 58 57 56 54 53 52 51 50 49 DO O 1 48 O D1 O 2 O 47 O lw D2 O 3 46 O Vss D3 O 4 45 O L D4 O 5 44 O Open D5 O 6 43 O Ver D6 O 7 42 O L D7 O 8 41 O Open Vss O 9 40 O Voo Ao O 10 39 O L Ai O gt 11 38 O PGM A2 0 12 37 O L A3 O 13 36 O A9 A4 O 14 35 O RESET A5 15 34 O A6 O 16 33 O lo 17 19 24 25 26 27 28 29 30 31 32 Llosa ld dd O e Cautions 1 L Individually connect this pin to Vss via a pull down resistor 10 kQ 2 Vss Connect this pin to ground 3 RESET Fix this pin to the low level 4 Open Leave this pin unconnected A0 A16 Address Bus RESET Reset CE Chip Enable Vpop Power Supply DO D7 Data Bus VrP Programming Power Supply OE Output Enable Vss Ground PGM Program 60 CHAP
179. M Source program 00H 01H CSEG AT 1000H 02H ADD A 2 RA78K 0 BR 11002H FFH Figure 22 5 Example of Connecting EEPROM in 2 wire serial I O mode 4PD78015F 78015FY 4PD78016F 78016FY 4PD78018F 78018FY EEPROM Vo Vo Vo e SCKO SB1 P32 457 CHAPTER 22 ROM CORRECTION lt 2 gt lt 3 gt lt 4 gt lt 5 gt lt 6 gt lt gt lt 8 gt 458 Develop an initialization routine in advance such as the one shown in Figure 22 6 so that the program can be corrected Figure 22 6 Initialization Routine Initialization ROM correction ROM correction used Store contents of external non volatile memory to internal extension RAM Set correction address register s Enable ROM correction operation Note Whether ROM correction is used is determined by the input level of a port For example if the input level of P20 is high ROM correction is used if it is low ROM correction is not used After reset store the contents of an external non volatile memory to the internal extension RAM by using the user s initialization routine for ROM correction refer to Figure 22 6 Also put the first address of the instruction to be corrected in CORADO or CORAD1 and set bits 1 and 3 CORENO and COREN1 of the correction control register CORCN to 1 Place the whole address space branch instruction BR addr16 at the specific address F7FDH in the
180. M3 of WDTM The watchdog timer continues operation in the HALT mode but stops in the STOP mode Therefore set RUN to 1 before entering the STOP mode to clear the watchdog timer and then execute the STOP instruction Cautions 1 The actual inadvertent loop detection time may be up to 0 5 shorter than the set time 2 The count operation of the watchdog timer is stopped when the subsystem clock is selected as the CPU clock Table 11 4 Inadvertent Loop Detection Time of Watchdog Timer Inadvertent Loop Detection Time At fx 10 0 MHz 212 x 1 fx 213 x 1 fx 214 x 1 fx 215 x 1 fx 216 x 1 fx 217 x 1 fx 218 x 1 fx 220 x 1 fx Remarks 1 fx Main system clock oscillation frequency 2 TCL20 TCL22 Bits 0 through 2 of timer clock select register 2 TCL2 235 i ar lu ed CHAPTER 11 WATCHDOG TIMER 11 4 2 Operation as interval timer When bit 4 WDTM4 of the watchdog timer mode register WDTM is set to 0 the watchdog timer also operates as an interval timer that repeatedly generates an interrupt request at time intervals specified by a count value set in advance Bits 0 through 2 TCL20 through TCL22 of the timer clock select register 2 TCL2 can be used to select a count clock interval time When bit 7 RUN of WDTM is set to 1 the watchdog timer starts operating as an interval timer In the interval timer mode the interrupt mask flag TMMK4 and priority specification fla
181. Mode When Subsystem Clock is Used When Subsystem Clock is Not Used Only main system clock stops oscillation CPU Stops operation Output port output latch Retains previous status immediately before STOP instruction execution 16 bit timer event counter Stops operation 8 bit timer event counter Operable only when Tl1 or TI2 is selected as count clock Watchdog timer A D converter Stops operation Watch timer Operable only when fxr is selected Stops operation as count clock Serial Other than interface automatic transmit receive function Operable only when external input clock is selected as serial clock Automatic transmit receive function Stops operation External INTPO Cannot operate interrupt INTP1 INTPS Operable Externally AD0 AD7 High impedance extended A8 A15 Retains previous status immediately before STOP instruction execution bus line ASTB Low level WR RD High level WAIT High impedance 445 i ARA ed CHAPTER 20 STANDBY FUNCTION 2 Releasing STOP mode The STOP mode can be released by the following three types of sources a Releasing by unmasked interrupt request The STOP mode is released by an unmasked interrupt request In this case if the interrupt request is enabled to be accepted vectored interrupt processing is performed after the oscillation stabilization t
182. NEL 1 SCKI E EE sor _ D7XD6XD5XD4XD3 D2XDIXDO D7XD6XD5 D4XD3 D2XD1XDO A sit _ D7XD6XD5XD4XD3XD2XD1XD0 if Ab7ADSADSADAAD3AD2ADIADO STB E BUSY CSIIF1 less Busy input released Us Eta eta eat de Busy input valid TRF I Caution When TRF is cleared the SO1 pin goes low Remark CSIIF1 Interrupt request flag TRF Bit 3 of automatic data transmit receive control register ADTC 396 CHAPTER 17 SERIAL INTERFACE CHANNEL 1 c Bit shift detection by busy signal During automatic transmission reception a bit shift of the serial clock of the slave device may occur because noise is superimposed on the serial clock signal output by the master device Unless the strobe control option is used at this time the bit shift affects transmission of the next byte In this case the master can detect the bit shift by checking the busy signal during transmission by using the busy control option A bit shift is detected by using the busy signal as follows The slave outputs the busy signal after the rising of the eighth serial clock during data transmission reception to not keep transmission reception waiting by the busy signal at this time make the busy signal inactive within 2 clocks The master samples the busy signal in synchronization of the falling of the leading side of the serial clock If a bit shift does not occur all the eight serial clocks that have been sampled are inactive If the sampled s
183. NX KD ACKD i s AAN RELD SISSI A P27 H feck E BYE SS ACKE L emor o oOo d ij RELT ee CLC r y weer Hoo oo O O sic _ INTCSIO a 2 ene sc 2 8 l4 5 6 7 8 1 12 Bl 4 SDAO D7 XD6XD5XD4XD3XD2XD1 ONO Y EX ASXA4KAS Processing in slave device in slave device ANA SIO0 write col POQ0000O 0000 ACKD cue aa RELD oD anna r P27 wuP Ls BSYE H ACKE H DIA CMDT _L RELT Jooo ce L po WREL L sic H INTCSIO CSIEO P25 PM25 PM27 L 348 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78018FY S Figure 16 22 Example of Communication from Slave to Master with 9 clock wait selected for both master and slave 1 3 a Start condition address Processing in master device SIOO write col LX_XX XANAX XK 0 ACKD CMDD RELD L CLD P27 H WUP L BSYE ACKE CMDT i RELT L Spells WREL iz SIC NTcsio AN SCL 1 12 8 14 5 6 7 81 9 1 21 3 4 5 SDAO A MODE 07 06 XD5XD4XD3 SIOO write A AAA IA col ooog 090000 AGKD E CMDD delo cU T mo i P27 o EE WUP SIO0 address SIO0 FFH i rc E E SIO0 data BSYE ACKE CMDT RELT CLC WREL SIC INTCSIO CSIEO P25 PM25 PM27 Ij jr jr re rie jr TI 349 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78018FY SUBSERI7 Figure 16 22 Example of Communication from Slave to Master with 9 clock wait selected for both
184. O 0 Note Bits 2 3 and 6 RELD CMDD and ACKD are read only bits Remarks 1 Bits 0 1 and 4 RELT CMDT ACKT are 0 when they are read after data has been set 2 CSIEO Bit 7 of the serial operation mode register 0 CSIMO 286 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 uPD78018F SUS R W ACKE Controls output of acknowledge signal Disables automatic output of acknowledge signal output by ACKT is enabled Before completion of Outputs acknowledge signal in synchronization with falling edge of 9th clock of transfer SCKO automatically output when ACKE 1 Outputs acknowledge signal in synchronization with falling edge of clock of SCKO After completion of immediately after instruction that sets this bit to 1 has been executed automat ically transfer output when ACKE 1 However this bit is not automatically cleared to O afte r acknowledge signal has been output R ACKD Detects acknowledge Clearing conditions ACKD 0 Setting condition ACKD 1 At falling edge of clock of SCKO immediately after Zey busy mode is released after transfer start instruction e When acknowledge signal ACK is detected at has been executed rising edge of clock of SCKO after completion of When CSIEO 0 transfer When RESET signal is input Note BSYE Controls synchronous busy signal output Disables output of busy signal in synchronization with falling edge of clock of SCKO immediately after instructi
185. ONS AND TEST FUNCT 18 4 2 Maskable interrupt request acceptance operation A maskable interrupt request can be accepted when the interrupt request flag is set to 1 and the corresponding mask flag MK is cleared to 0 A vectored interrupt request is accepted in the interrupt enabled status when the IE flag is set to 1 However an interrupt with a lower priority cannot be accepted while an interrupt with a higher priority is being processed when the ISP flag is reset to 0 The time required to start the interrupt processing after a maskable interrupt request has been generated is as follows For the timing of interrupt request acceptance refer to Figures 18 3 and 18 4 Table 18 3 Time from Generation of Maskable Interrupt Request to Processing When xxPR 0 13 clocks 63 clocks When xxPR 1 15 clocks 65 clocks Note The wait time is maximum when an interrupt request is generated immediately before a division instruction Remark 1 clock e fcru CPU clock fcPu When two or more maskable interrupt requests are generated at the same time they are accepted starting from the one assigned the highest priority by the priority specification flag When interrupts are assigned the same priority the default priority takes precedence A pended interrupt is accepted when the status where it can be accepted is set Figure 18 12 shows the algorithm of accepting interrupts When a maskable interrupt request is accepted the program
186. ONS IN THIS EDITION 1 6 2 6 Product Development of 78K 0 Series Addition of the following models 1 PD780018AY subseries 1 PD780988 subseries 1PD78098B subseries 1 PD780973 subseries Deletion of the following models 1PD78075BY subseries 1 PD780018 subseries 1 PD780018Y subseries p 140 143 Change of Figures 6 6 6 8 Block Diagram of P20 P21 and P23 P26 Figures 6 7 6 9 Block Diagram of P22 and P27 p 173 Addition of 8 1 Outline of Timers in u PD780018F 780018FY Subseries p 214 218 Addition of Figures 9 10 9 13 Square Wave Output Operation p 247 Addition of Caution to 14 2 6 ANIO ANI7 pins p 248 Addition of Caution to 14 2 7 AVrer pin p 268 Change of Note on BSYE flag in Figure 15 4 Format of Serial Bus Interface Control Register p 280 302 Addition of Caution to 15 4 3 2 a Bus release signal REL b Command signal CMD and 11 Notes on SBI mode p 495 APPENDIX B DEVELOPMENT TOOLS Throughout Support for in circuit emulator IE 78KO NS p 509 APPENDIX C EMBEDDED SOFTWARE Throughout Deletion of fuzzy inference development support system The mark shows major revised points MEMO Readers Purpose Organization INTRODUCTION This manual is intended for user engineers who understand the functions of the HPD78018F and uPD78018FY subseries and wish to design and develop its application systems and programs Target products are as fo
187. P 1 an address is received Only when this address matches the value of the slave address register SVA CSIIFO is set if the address does not match RELD is cleared 2 In the BUSY status transfer is not started until the READY status is set i rir lv ed CHAPTER 15 SERIAL INTERFACE CHANNEL 0 uPD78018F SUS 5 Pin configuration The configuration of the serial clock pin SCKO and serial data bus pin SBO SB1 is as follows a SOKO oessa Pin that inputs outputs serial clock lt 1 gt Master CMOS push pull output lt 2 gt Slave Schmitt input b SBO SB1 Serial data input output dual pin N ch open drain output and Schmitt input for both master and slave Because the serial data bus line is of N ch open drain output an external pull up resistor is necessary Figure 15 25 Pin Configuration Slave device Master device Clock output gt clock input SCKO UU SCKO clock output gt I gt Clock input Serial clock SBO SB1 Voo Ri N ch open drain N ch open drain soo F TIT SBO SB1 Serial data bus H 500 TT 10 XXX s Caution Because it is necessary to make the N ch open drain high impedance state when data is received write FFH to serial I O shift register 0 SIO0 in advance It can always be turned off during transfer However when the wake up function specification bit WUP 1 the N ch open drain output is always at high impe
188. P27 uPD78018F Subseries oooooccnnccincccoccciocnconccnnnnnancnonnncnnnos 141 6 8 Block Diagram of P20 P21 and P23 26 uPD78018FY Subseries ccsseeeeeeeeees 142 6 9 Block Diagram of P22 and P27 uPD78018FY Subseries ccceescessseeeeeeeeeeeeneeeeeeeeaes 143 6 10 Block Diagram of P3O0 PS7Z imc a nos 144 6 11 Block Diagram of P4O0 PAZ cintia 145 6 12 Block Diagram of Falling Edge Detection Circuit ooocccnncinnninincinnnonnccnocconnccncccnarnancnrnncnnnn 145 6 13 Block DiagramorPO0 P Fura lo 146 6 14 Block Diagramiof PO0 P OS iii A AA 148 6 15 Block Diagram of P64 P67 2 aac da 148 6 16 Format of Port Mode Register ccccscccesecceceseeeeeseeeeeseneeseseeeeensaeneseneesesesenesaseeeseneesesenenes 151 6 17 Format of Pull Up Resistor Option Register cceeeeseeeeeeeeeeeeeneeeeeeeeeeeeaeeeeeeteaeeeeeeeeaees 152 24 LIST OF FIGURES 2 7 Figure No Title Page 6 18 Format of Memory Extension Mode Register ceeescceeeseeeeenneesesneeeeeneeeesnneeteseeereaeees 153 6 19 Format of Key Return Mode Register eeesceeseseeeeeeneeteeeeeeeeneeeeesaeeeesaeeeseneeeesnaeeesnaeeess 154 7 1 Block Diagram of Clock Generation Circuit ec eceeeceeeneeeeeeeeeeeeeeeeeaeeseeeeeaeeeneeeeeeeeeeeeaes 158 7 2 Feedback Resistor of Subsystem Clock ecceeccceeeeeeeeeeeeeeeeeeeeeeeaeeseneeeaeeseaeeseeseaeeeeeeeeaees 159 7 3 Format of Processor Clock Control Register cc eecseseeeeeeeeee
189. P27 as serial interface pins the input output mode and output latch must be set according to the functions to be used For the details of the setting refer to Figure 15 3 Format of Serial Operation Mode Register 0 and Figure 17 3 Format of Serial Operation Mode Register 1 CHAPTER 3 PIN FUNCTIONS uPD78018F SUBSERIEY 3 2 4 P30 P37 Port3 These pins constitute an 8 bit I O port port 3 In addition they also functions as timer I O clock output and buzzer output pins Port 3 can be set in the following operation modes in 1 bit units 1 Port mode In this mode port 3 functions as an 8 bit I O port which can be set in the input or output mode in 1 bit units by using the port mode register 3 PM3 When used as an input port an internal pull up resistor can be used if so specified by the pull up resistor option register PUO 2 Control mode In this mode the pins of port 3 can be used as timer I O clock output and buzzer output pins a TH TI2 These pins input an external count clock to the 8 bit timer event counter b TOO TO2 Timer output pins c PCL Clock output pin d BUZ Buzzer output pin 3 2 5 P40 P47 Port4 These pins form an 8 bit I O port port 4 In addition they also form an address data bus When the falling edge of these pins is detected the test input flag KRIF can be set to 1 This port can be set in the following operation modes in 8 bit units 1 Port mode In this mode P40
190. PO2 INTP2 O PO1 INTP1 O POO INTPO TIO O RESET O P67 ASTB O P66 WAIT 57 CHAPTER 2 GENERAL uPD78018FY SUBSERIES A8 A15 ADO AD7 ASTB ANIO ANI7 AVDD AVREF AVss BUSY BUZ IC P00 P04 P10 P17 P20 P27 P30 P37 P40 P47 P50 P57 P60 P67 PCL Address Bus Address Data Bus Address Strobe Analog Input Analog Power Supply Analog Reference Voltage Analog Ground Busy Buzzer Clock Internally Connected INTPO INTP3 Interrupt from Peripherals Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Programmable Clock RD RESET SBO SB1 SCKO SCK1 SCL SDAO SDA1 S10 SI1 SOO SO1 STB TIO TI2 TOO TO2 WAIT WR X1 X2 XT1 XT2 VDD VPP Vss Read Strobe Reset Serial Bus Serial Clock Serial Clock Serial Data Serial Input Serial Output Strobe Timer Input Timer Output Wait Write Strobe Crystal Main System Clock Crystal Subsystem Clolck Power Supply Programming Power Supply Ground Remark Vrr is for the uPD78P018FY lt is replaced by an IC pin for the mask ROM model 58 CHAPTER 2 GENERAL uPD78018FY SUBSERIES 2 PROM programming mode 64 pin plastic shrink DIP 750 mil A15 A14 u4PD78P018FYCW 64 pin ceramic shrink DIP with window 750 mil u4PD78P018FYDW O 1 O Vss O 2 O Voo O 3 O O 4 O L O 5 O O 6 O O 7 o pu O 8 O DO O O D1 O O D2 O O Vss D3 O O
191. PORT3 P30 P37 WATCHDOG TIMER PORT4 P40 P47 WATCH TIMER SI0 SBO P25 lt PORT5 P50 P57 SERIAL SOO SB1 P26 gt INTERFACE 0 78K 0 SCKO P27 P CPU ROM CORE l Gipi PORT6 P60 P67 SO1 P21 biota as SOK P22 INTERFACE ADO P40 STB P23 lie BUSY P24 gt ts EXTERNAL A15 P57 ANIO P10 ACCESS RD P64 ANI7 P17 WR P65 AVoD A D CONVERTER WAIT P66 AVss RAM ASTB P67 AVREF RESET INTPO POO INTERRUPT X1 SYSTEM INTP3 P03 CONTROL CONTROL X2 XT1 P04 XT2 BUZ P36 BUZZER OUTPUT CLOCK OUTPUT PCL P35 CONTRO Voo Vss IC VPP Remarks 1 The internal ROM and RAM capacities differ depending on the product 2 uPD78P018F 48 CHAPTER 1 GENERAL uPD78018F SUBSERIES 1 8 Functional Outline Internal memory Part Number 4PD78011F 1PD78012F Mask ROM uPD78013F uPD78014F uPD78015F uPD78016F uPD78018F HPD78P018F PROM 8 KB 16 KB 60 KBNote 1 High speed RAM 512B 1024 BNote 1 Extension RAM 1024 BNote 2 Buffer RAM 32 B Memory space 64 KB General purpose register 8 bits x 8 x 4 banks Minimum instruction execution time With main system clock 0 4 us 0 8 us 1 6 us 3 2 us 6 4 us at 10 0 MHz With subsystem clock 122 us at 32 768 kHz Instruction set 16 bit operation Multiplication division 8 bits x 8 bits 16 bits 8 bit
192. PT FUNCTIONS AND TEST FUNCT The noise eliminating circuit sets the PIFO flag to 1 when the input level of INTPO is active two times in succession Figure 18 7 I O Timing of Noise Eliminating Circuit when rising edge is detected a When input is equal to sampling cycle tsmr or lower po PIFO Because level of INTPO is not high during sampling output of PIFO remains low b When input is 1 to 2 times the frequency of the sampling cycle tsmr ismP A Sampling clock Because level of sampled INTPO is high two times in succession in lt 2 PIFO flag is set to 1 c When input is two or more times the frequency of the sampling cycle tsmp tSMP ana Sampling clock At the point when level of INTPO is high two times in succession PIFO flag is set to 1 411 CHAPTER 18 INTERRUPT FUNCTIONS AND TEST FUNCTIONS 6 Program status word PSW The program status word is a register that holds the instruction execution result and current status of interrupt request An IE flag that enables disables the maskable interrupts and an ISP flag that controls nesting processing are mapped to this register This register can be read or written in 8 bit units In addition it can also be manipulated by using a bit manipulation instruction or dedicated instructions El and DI When a vectored interrupt request is accepted and when the BRK instruction is executed PSW is
193. RI7 Symbol lt 7 gt lt b gt lt 5 Address On reset R W gt 4 3 2 1 0 R W Clock externally input to SCKO pin Output of 8 bit timer register 2 TM2 Clock specified by bits 0 3 of timer clock select register 3 TCL3 CSIM Operation SIO SBO SDAO P25 S00 SB1 SDA1 P26 SCKO SCL P27 PM25 P25 PM26 P26 PM27 P27 First bit E i y mode pin function pin function pin function 0 0 0 1 3 wire serial SlONote 2 SO0 SCKO 1 0 mode input CMOS output CMOS I O 2 wire serial l O mode Refer to 16 4 3 Operation in 2 wire serial I O mode 1 C bus mode Refer to 16 4 4 Operation in C bus mode R W Generates interrupt request signal in all modes each time serial transfer is executed Generates interrupt request signal when address received after start condition has been detected in 1 C bus mode when CMDD 1 coincides with data of slave address register Stops operation Enables operation Notes 1 Bit 6 COI is a read only bit 2 This pin can be used as P25 CMOS input when used only for transfer 3 Be sure to set WUP to 0 in the 3 wire serial I O mode Remark x Don t care PMxx Port mode register Pxx Output latch of port 324 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78018FY S b Serial bus interface control register SBIC SBIC is set by a 1 bit or 8 bit memory manipulation instruction This register is set to OOH when the RESET signal
194. ROM uPD78016FCW XXX 64 pin plastic shrink DIP 750 mil Mask ROM uPD78016FGC XXX AB8 64 pin plastic QFP 14 x 14 mm Mask ROM uPD78016FGK XXX 8A8 64 pin plastic LQFP 12 x 12 mm Mask ROM uPD78018FCW XXX 64 pin plastic shrink DIP 750 mil Mask ROM uPD78018FGC XXX AB8 64 pin plastic QFP 14 x 14 mm Mask ROM uPD78018FGK XXX 8A8 64 pin plastic LQFP 12 x 12 mm Mask ROM uPD78P018FCW 64 pin plastic shrink DIP 750 mil One time PROM HPD78P018FDW 64 pin ceramic shrink DIP with window 750 mil EPROM HPD78P018FGC AB8 64 pin plastic QFP 14 x 14 mm One time PROM H4PD78P018FGK 8A8 64 pin plastic LQFP 12 x 12 mm One time PROM HPD78P018FKK S 64 pin ceramic WQFN 14 x 14 mm EPROM Remark XXX indicates ROM code suffix 36 CHAPTER 1 GENERAL uPD78018F SUBSERIES 2 Special grade products Part Number Package Internal ROM uPD78011FCW A XXX uPD78011FGC A XXX AB8 uPD78012FCW A XXX uPD78012FGC A XXX AB8 uPD78013FCW A XXX uPD78013FGC A XXX AB8 uPD78014FCW A XXX uPD78014FGC A XXX AB8 uPD78015FCW A XXX uPD78015FGC A XXX AB8 uPD78016FCW A XXX uPD78016FGC A XXX AB8 uPD78018FCW A XXX uPD78018FGC A XXX AB8 uPD78P018FCW A uPD78P018FGC A AB8 HPD78P012FGC A2 XXX AB8 64 pin plastic shrink DIP 750 mil 64 pin plastic QFP 14 x 14 mm 64 pin plastic shrink DIP 750 mil 64 pin plastic QFP 14 x 14 mm 64 pin plastic shrink DIP 750 mil 64 pin plastic QFP 14 x 14 mm 64 pin plastic shrink DIP 750 mil 64 p
195. S 4 3 I O Circuits of Pins and Handling of Unused Pins Table 4 1 shows the I O circuit type of each pin and how to handle unused pins For the configuration of each type of I O circuit refer to Figure 4 1 Table 4 1 I O Circuit Type of Each Pin Pin Name I O Circuit Type Recommended Connection when Unused POO INTPO TIO Connect to Vss PO1 INTP1 Individually connect to Vss via resistor PO2 INTP2 PO3 INTP3 P04 XT1 Connect to Voo P10 ANIO P17 ANI7 Individually connect to Voo or Vss P20 SI1 P21 SO1 P22 SCK1 P23 STB P24 BUSY P25 SI0 SBO SDAO P26 SO0 SB1 SDA1 P27 SCKO SCL P30 TOO P31 TO1 P32 TO2 P33 TI1 P34 T12 P35 PCL P36 BUZ P37 P40 ADO P47 AD7 Individually connect to Von via resistor P50 A8 P57 A15 Individually connect to Voo or Vss via resistor P60 P63 Mask ROM model Individually connect to Voo via resistor P60 P63 PROM model P64 RD Individually connect to Voo or Vss via P65 WR resistor P66 WAIT P67 ASTB RESET XT2 Open AVREF Connect to Vss AVoo Connect to Voo AVss Connect to Vss IC Mask ROM model Directly connect to Vss Ver PROM model 88 CHAPTER 4 PIN FUNCTIONS uPD78018FY SUBSERIE Figure 4 1 I O Circuits of Pins 1 2 Pullup enable Voo e Daa HE Schmitt trigger input with IN OUT hysteresis characteristics Output x N ch
196. S TM1 8 bit timer register 2 TM2 Serial I O shift register 0 SIOO Undefined Serial I O shift register 1 SIO1 A D conversion result register ADCR Port mode register 0 PMO Port mode register 1 PM1 Port mode register 2 PM2 Port mode register 3 PM3 Port mode register 5 PM5 OJOJOJSOSOJO LO SOJSO OJ O OIJO Port mode register 6 PM6 Correction address register 0 Note CORADO Correction address register 1 Note CORAD1 Timer clock select register 0 TCLO Timer clock select register 1 TCL1 Timer clock select register 2 TCL2 Timer clock select register 3 TCL3 Sampling clock select register SCS 16 bit timer mode control register TMCO 8 bit timer mode control register TMC1 Watch timer mode control register TMC2 OJOJOJOJ OJOJ O O O 16 bit timer output control register TOCO Note Only uwPD78015F 78015FY 78016F 78016FY 78018F 78018FY 78P018F and 78P018FY have this register 108 CHAPTER 5 CPU ARCHITECTURE Table 5 7 Special Function Register List 2 2 Bit Units for Manipulation Address Special Function Register SFR Name At Reset 1 bit 8 bits 16 bits O 8 bit timer output control register Serial operation mode register 0 Serial bus interface control register Undefined 00H Slave address register Interrupt
197. SCKO H SBO0 SB1 Output Condition Setting of RELT Influence on Flag RELD is set CMDD is cleared Meaning of Signal Subsequently outputs CMD signal and indicates that transmit data is address Command signal CMD At falling edge of SBO SB1 when SCKO 1 SCKO H SBO SB1 Setting of CMDT CMDD is set i Data transmitted after REL signal is output is address ii Data transferred without REL signal output is command Acknowledge signal ACK Master slave Low level signal output to SBO SB1 for duration of 1 clock of SCKO after serial reception has been completed Busy signal BUSY Synchronous busy signal Low level signal output to SBO SB1 following acknowledge signal Ready signal READY High level signal output to SBO SB1 before start and after completion of serial transfer Synchronous busy output SCKO lo WW pi ACK SBO SB1 DO e ACK gt lt BUSY gt SBO SB1 Do lt 1 gt ACKE 1 lt 2 gt Setting of ACKT ACKD is set Reception completed BSYE 1 Serial reception disabled because processing is in progress lt 1 gt BSYE 0 lt 2 gt Instruction excution that writes data to SIOO transfer start command Serial reception enabled status ry ned E So a UGS SAIMSSANS 4810820d 0 TANNVHO AJOVSYALNI IVIHIS Si YILAVHO
198. SERIAL PORT5 P50 P57 SOO SB1 SDA1 P26 INTERFACE O 78K 0 SCKO SCL P27 CPU ROM CORE Ae EEA PORT6 P60 P67 SO1 P21 SCK1 P22 SERIAL ADO P40 STB P23 INTERFACE AD7 P47 BUSY P24 gt A8 P50 EXTERNAL A15 P57 ANIO P10 ACCESS RD P64 ANI7 P17 WR P65 AVoo A D CONVERTER WAIT P66 AVss RAM ASTB P67 AVREE L RESET INTPO P00 INTERRUPT x YSTEM INTP3 P03 CONTROL oe x2 XT1 P04 XT2 BUZ P36 BUZZER OUTPUT CLOCK OUTPUT PCL P35 CONTROL Voo Vss IC VPP Remarks 1 The internal ROM and RAM capacities differ depending on the product 2 uPD78P018FY 63 CHAPTER 2 GENERAL uPD78018FY SUBSERIES 2 8 Functional Outline Part Number HPD78011FY uPD78012FY uPD78013FY uPD78014FY uPD78015FY uPD78016FY uPD78018FY uPD78P018FY Internal Mask ROM PROM memory 8 KB 16 KB 60 KBNote 1 High speed RAM 512 B 1024 BNote 1 Extension RAM 1024 BNote 2 Buffer RAM 32 B Memory space 64 KB General purpose register 8 bits x 8 x 4 banks Minimum With main system 0 4 us 0 8 us 1 6 us 3 2 us 6 4 us at 10 0 MHz instruction clock execution time With subsystem 122 us at 32 768 kHz clock Instruction set 16 bit operation Multiplication division 8 bits x 8 bits 16 bits 8 bits Bit manipulation set reset test Boolean operation BCD correction etc 1 0 port Total 53 lines
199. SERIES Deletion of 5 inch FD model from Windows supporting development tools Following products developed IE 78000 R A ID78KO Change of conversion adapter name from EV 9500GK 64 to TGK 064SBW APPENDIX B DEVELOPMENT TOOLS APPENDIX E REVISION HISTORY Edition 5th edition Revision from Previous Edition Change of Figures 6 6 6 8 Block Diagram of P20 P21 and P23 P26 Figures 6 7 6 9 Block Diagram of P22 and P27 CHAPTER 6 PORT FUNCTIONS Addition of Figures 9 10 9 13 Square Wave Output Operation CHAPTER 9 8 BIT TIMER EVENT COUNTER Addition of Caution to 14 2 6 ANIO ANI7 pins Addition of Caution to 14 2 7 AVrer pin CHAPTER 14 A D CONVERTER Change of Note on BSYE flag in Figure 15 4 Format of Serial Bus Interface Control Register Addition of Caution to 15 4 3 1 a Bus release signal REL b Command signal CMD and 11 Notes on SBI mode CHAPTER 15 SERIAL INTERFACE CHANNEL 0 APPENDIX B DEVELOPMENT TOOLS Throughout Support for in circuit emulator IE 78KO NS APPENDIX B DEVELOPMENT TOOLS APPENDIX C EMBEDDED SOFTWARE Throughout Deletion of fuzzy inference development support system APPENDIX C EMBEDDED SOFTWARE 519 MEMO 520 Although NEC has taken all possible steps essage to ensure that the documentation supplied to our customers is complete bug free From and up to date we readily accept that er
200. SI0 SBO P25 SO0 SB1 P26 SCKO0 P27 First bit mode pin function pin function pin function 3 wire serial I O mode Refer to 15 4 2 Operation in 3 wire serial l O mode Note 2 Note 2 SB1 x x P25 CMOS l O N ch open drain I O SCKO SBI mode CMOS I O Note 2 Note 2 SBO TAR N ch open P26 CMOS I O drain I O 2 wire serial I O mode Refer to 15 4 4 Operation in 2 wire serial I O mode Generates interrupt request signal in all modes each time serial transfer is executed Generates interrupt request signal when address received after bus has been released in SBI mode when CMDD RELD 1 coincides with data of slave address register SVA Data of slave address register SVA does not coincide with data of serial I O shift register O S100 Data of slave address register SVA coincides with data of serial I O shift register O S100 Stops operation Enables operation Notes 1 Bit 6 COI is a read only bit 2 This pin can be freely used for port function 3 Clear bit 5 SIC of the interrupt timing specification register SINT to O when using the wake up function WUP 1 4 When CSIEO 0 COI is 0 Remark x Don t care PMxx Port mode register Pxx Output latch of port 285 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 uPD78018F SUBSERI b Serial bus interface control register SBIC SBIC is set by a 1 bit or 8 bit memory manipulat
201. T CONTROL CIRCUIT CHAPTER 14 A D CONVERTER OJO JOJO JO JO JO JO JO JO JO CHAPTER 15 SERIAL INTERFACE CHANNEL 0 uPD78018F SUBSERIES O OJO OJO O O O OJO O CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78018FY SUBSERIES CHAPTER 17 SERIAL INTERFACE CHANNEL 1 CHAPTER 18 INTERRUPT FUNCTIONS AND TEST FUNCTIONS CHAPTER 19 EXTERNAL DEVICE EXTENSION FUNCTION CHAPTER 20 STANDBY FUNCTION CHAPTER 21 RESET FUNCTION CHAPTER 22 ROM CORRECTION CHAPTER 23 uPD78P018F 78P018FY CHAPTER 24 INSTRUCTION SET OJOJO OJO O O JO C2 1D OTI JOIO 11 i ri oY a lv ed Differences Between PD78018F Subseries and PD78018FY Subseries The wPD78018F subseries and uPD78018FY subseries differ from each other in some parts of serial interface channel 0 Legend 12 Modes of Serial Interface Channel 0 3 wire serial I O mode HPD78018F uPD78018FY Subseries Subseries 2 wire serial I O mode SBI serial bus interface mode 12C Inter IC bus mode O Supported Not supported Data significance Active low Note Caution Remark Numerical representation Left higher digit right lower digit XXX top bar over pin or signal name Explanation of the text marked Note Important information Supplement Binary XXXX or XXXXB Decimal XXXX Hexadecimal XXXXH Related Documents Some related documents listed below
202. TCL12 TCL11 TCL10 FF41H 00H R W TCL12 TCL11 Falling edge of Tl1 Rising edge of TI1 fx 22 2 5 MHz fx 23 1 25 MHz fx 24 625 kHz 1x 25 313 kHz fx 27 78 1 kHz fx 28 39 1 kHz fx 29 19 5 kHz fx 28 156 kHz fx 210 9 8 kHz fx 212 2 4 kHz Setting prohibited TCL15 Falling edge of T12 Rising edge of T12 fx 22 2 5 MHz fx 23 1 25 MHz fx 24 625 kHz fx 25 313 kHz fx 27 78 1 kHz fx 28 39 1 kHz fx 29 19 5 kHz fx 26 156 kHz fx 210 9 8 kHz fx 212 2 4 kHz Others Setting prohibited Caution Before writing data other than that already written to TCL1 stop the timer operation Remarks 1 fx Main system clock oscillation frequency 2 Tl1 Input pin of 8 bit timer register 1 3 TI2 Input pin of 8 bit timer register 2 4 At fx 10 0 MHz operation 207 CHAPTER 9 8 BIT TIMER EVENT COUNTER 2 8 bit timer mode control register TMC1 This register enables or disables the operations of 8 bit timer registers 1 and 2 and sets an operation mode of 8 bit timer register 1 2 TMC1 is set by a 1 bit or 8 bit memory manipulation instruction This register is set to OOH when the RESET signal is input Figure 9 5 Format of 8 Bit Timer Mode Control Register 5 4 3 2 DEE Symbol 7 6 lt l gt lt 0 gt Address On reset R W TCE2 TC
203. TER 2 GENERAL uPD78018FY SUBSERIES 2 6 Product Development of 78K 0 Series The products in the 78K 0 series are listed below The names enclosed in boxes are subseries names Products in mass production r ATARE Products under development Y subseries products are compatible with 12C bus Control 100 pin EMI noise reduced version of the uPD78078 100 pin uPD78078 A timer was added to the PD78054 and external interface was enhanced 100 pin uPD78070A uPD78070AY E ROM less version of the PD78078 ADO PIM dormancia HIPDTBOO1BAY 2 Serial I O of the PD78078Y was enhanced and the function is limited 80 pin uPD780058 PD780058 Y Note Serial I O of the PD78054 was enhanced and EMI noise was reduced 80 pin EMI noise reduced version of the yPD78054 80 pin _ UART and D A converter were enhanced to the PD78014 and I O was enhanced 64 pin E 1PD780034 ES uPD780034Y _ A D converter of the PD780024 was enhanced 64 pin 1PD780024 uPD780024Y Serial I O of the wPD78018F was added and EMI noise was reduced 64 pin EMI noise reduced version of the PD78018F 64 pin uPD78018F Low voltage 1 8 V operation version of the PD78014 with larger selection of ROM and RAM capacities 64 pin An A D converter and 16 bit timer were added to the wPD78002 64 pin HPD780001 An A D converter was added to the PD78002 64 pin 1PD78002 Basic subseries for control 42 44 pin 1PD78083
204. TION ccssccsseeeeseseeeeseeeeeeseeseseeeeeeseeeseaeeeeseeeeseaesaseeeeeeseesenseeeenes 439 20 1 Standby Function and Configuration ccccescccssseeeeeeeeeesneeeeeeeeeseseeseseeeesseesesneeeeneas 439 20 11 StandDy UNC O arara aii dave Aaa a aaa E a aaa e ani naera 439 20 1 2 Registers controlling standby function oooconnccnnnncccnnoncnnnncnnnnancnonnornnnnnrr nn nnrr cnn cnn nr rra 440 20 2 Operation of Standby Function 0 cccccsseeceeseeeeeseeeeneeeeeseaeeenseeeeeeneesesneeeeneeeeeseaesenseeeeneas 441 20 21 HALT Mode iuris Ree A A et 441 20 22 STOP Mode it tada 445 CHARTER 21 RESET FUN OT ON rr ar aE aee ee raae aa rea aeo areae Sarera are aa ra ind Asia 449 21 1 Reset FUNCION 0 iii i 449 CHAPTER 22 ROM CORRECTION onccccicccccinccccinnnnncrncnnrnrrnn nr 453 22 1 Function of ROM Correction cccccsccecsseeeeeeeeeeeeeeseseeeeeseeseseeeeeeeneeesseaeseeneeesseaesenseeeeneas 453 22 2 Configuration of ROM Correction cccecsssccceseeeeseeeseeeneeesseesseseeeeeseeeeeseeeeeneneseaneeeeneees 453 22 3 Registers Controlling ROM Correction ccccccssscccsseeeesseeseesneeeeeseeseseeeeeeeeeeeseeesenseeeeneas 455 22 4 Using ROM Correction e r T a ae intentan 457 22 5 Example of Using ROM Correction sccccsceessseeeeeseeeeseeeseeseeeeeeeeeseseaeseneeeeeseaeseneeeeeneas 459 22 6 Program Execution FIOW ssssssnnesnnunnnnnnnnennnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn nnmnnn nnmnnn nnmnnn nna 460
205. TM1 and TM2 count values 00H 01H 02H 03H 04H Timer starts 2 Setting of 8 bit compare registers The 8 bit compare registers CR10 and CR20 can be set to 00H Therefore one pulse can be counted when an 8 bit timer event counter operates as an event counter When the two 8 bit timer event counters are used together as a 16 bit timer event counter set bit 0 TCE1 of the 8 bit timer mode control register to O and stop the timers in order to write values to CR10 and CR20 Figure 9 15 External Event Counter Operation Timing TI and Tl2 inputs O O A A ea O ae CR10 CR20 00H TM1 and TM2 count values 00H 00H 00H 00H TO1 TO2 A SS E A A Interrupt request flag P e e a 219 i ri NY a lu ed CHAPTER 9 8 BIT TIMER EVENT COUNTER 3 Operation after changing value of compare register during timer count operation If a new value of an 8 bit compare register CR10 or CR20 is less than the value of the corresponding 8 bit timer register TM1 or TM2 TM1 and TM2 continue counting overflow and restart counting from 0 Therefore ifthe new values of CR10 and CR20 M are less than their old values N itis necessary to restart the timers after changing the values of CR10 and CR20 Figure 9 16 Timing after Changing Values of Compare Registers during Timer Count Operation o E O E A E O OO TM1 and TM2 count values x 1 C x a ss FFH 00H 01H 02H Remark N gt X gt M 220 i rN a lu ed CHAPTER 10 WATCH
206. To our customers Old Company Name in Catalogs and Other Documents On April 1 2010 NEC Electronics Corporation merged with Renesas Technology Corporation and Renesas Electronics Corporation took over all the business of both companies Therefore although the old company name remains in this document it is a valid Renesas Electronics document We appreciate your understanding Renesas Electronics website http www renesas com April 1 2010 Renesas Electronics Corporation Issued by Renesas Electronics Corporation http www renesas com Send any inquiries to http www renesas com inquiry ENESAS 10 11 12 Notice All information included in this document is current as of the date this document is issued Such information however is subject to change without any prior notice Before purchasing or using any Renesas Electronics products listed herein please confirm the latest product information with a Renesas Electronics sales office Also please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website Renesas Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise is granted
207. VERTER Operation of A D converter SAR ADCR INTAD The A D conversion is performed continuously until the bit 7 of ADM CS is reset to 0 by software Le Figure 14 4 Basic Operation of A D Converter Conversion Un defined Sampling time Sampling time A D conversion Conversion result Conversion result If the data of the ADM is rewritten during the A D conversion the conversion is initialized If the CS bit is set to 1 at this time conversion is performed again from the start The contents of the ADCR register become undefined when the RESET signal is input 252 i ri ed CHAPTER 14 A D CONVERTER 14 4 2 Input voltage and conversion result The relation between the analog voltage input to the analog input pins ANIO ANI7 and A D conversion result value stored to A D conversion result register ADCR is as follows ADCR INT Nx 256 0 5 AVREF Or AVREF AVREF A ADCR 0 5 x 256 Vin lt ADCR 0 5 x 256 Remark INT function returning integer of value in VIN analog input voltage AVrer AVrer pin voltage ADCR value of A D conversion result register ADCR Figure 14 5 shows the relations between the analog input voltage and A D conversion result Figure 14 5 Relations between Analog Input Voltage and A D Conversion Result
208. X SP lt AX AX SP AX amp SP Unconditional branch laddr16 PC lt addr16 addr16 PC amp PC 2 jdisp8 AX PCH amp A PCL e X Conditional addr16 PC lt PC 2 jdisp8 if CY 1 branch addr16 PC lt PC 2 jdisps if CY 0 addr16 PC amp PC 2 jdisp8 if Z 1 addr16 PC lt PC 2 jdisps if Z 0 saddr bit addr16 PC lt PC 3 jdisp8 if saddr bit 1 sfr bit addr16 PC lt PC 4 jdisp8 if sfr bit 1 A bit addr16 PC lt PC 3 jdisp8 if A bit 1 PSW bit addr16 PC lt PC 3 jdisp8 if PSW bit 1 HL bit addr16 PC amp PC 3 jdisp8 if HL bit 1 saddr bit addr16 PC lt PC 4 jdisp8 if saddr bit O sfr bit addr16 PC amp PC 4 jdisp8 if sfr bit 0 A bit addr16 PC amp PC 3 jdisp8 if A bit 0 PSW bit addr16 PC lt PC 4 jdisp8 if PSW bit 0 HL bit addr16 OTR LOT TRL AJOJ j RIL WIT nNIT NIT NINI NI NI WO NMI NI A PC PC 3 jdisp8 if HL bit 0 Notes 1 When the internal high speed RAM area is accessed or when an instruction that does not access data is executed 2 When an area other than the internal high speed RAM area is accessed Remarks 1 One clock of an instruction is equal to one CPU clock fcru selected by processor clock control register PCC 2 The number of clocks sh
209. a such as special function registers SFRs and general purpose registers Figures 5 15 through 5 22 illustrate how the data memory is addressed Figure 5 15 Data Memory Addressing uPD78011F 78011FY FFFFH A A Special function registers SFRs 256 x 8 bits SFR addressing A A A E NA E E FF1FH A FFOOH Y FEFFH 4 General purpose registers i f 32 x 8 bits Register addressing FEEOH Short direct FEDFH addressing Internal high speed RAM 512 x 8 bits BESO ls rr AA Phe renee oe Y FE1FH Direct addressing FDOOH FCFFH Register indirect Reserved addressing FAEOH FADFH Internal buffer RAM Based addressing FACOH 32 x 8 bits l FABFH Based indexed addressing Reserved FA80H FA7FH External memory 55936 x 8 bits 2000H 1FFFH Internal ROM 8192 x 8 bits 0000H Y 115 CHAPTER 5 CPU ARCHITECTURE 116 Figure 5 16 Data Memory Addressing uPD78012F 78012FY FFFFH A Special function registers SFRs 256 x 8 bits SFR addressing ECO O E A AM AAN FF1FH A FFOOH Y FEFFH E 4 General purpose registers 32 x 8 bits Register addressing FEEOH Short direct A AA i FEDFH addressing Internal high speed RAM 512 x 8 bits RE20H E erana ence ee Y FE1FH FDOOH FCFFH Reserved FAEOH FADFH Internal buffer RAM FACOH 32 x 8 bits FABFH Reserved FA80H FA7FH External memory 47744 x 8 bits 4000H 3FFFH Internal ROM 16384 x 8 bits 0000H
210. a CMOS output pin and outputs the status of the SOO latch The output status of this pin can be manipulated by setting bit O RELT and bit 1 CMDT of the serial bus interface control register SBIC However do not perform this manipulation during serial transfer The output level of the SCKO pin is controlled by manipulating the P27 output latch in the output mode mode of the internal system clock refer to 16 4 7 Manipulating SCKO SCL P27 pin output 326 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78018FY S 3 Signals Figure 16 7 shows the operations of RELT and CMDT Figure 16 7 Operations of RELT and CMDT SO0 latch RELT CMDT 4 MSB LSB first selection In the 3 wire serial l O mode whether data is transferred with the MSB or LSB first can be selected Figure 16 8 shows the configuration of the serial I O shift register O SIOO and internal bus As shown in the figure data can be read written with the MSB LSB inverted Whether the MSB or LSB is transferred first can be specified by using the bit 2 CSIMO2 of the serial operation mode register 0 CSIMO Figure 16 8 Transfer Bit Sequence Select Circuit 7 e 6 2 Internal bus 4 oe A SOURS Se ea ee 1 i 0 LSB first MSB first Read writegate gt Read write gate SOO0 latch Slo Shift register 0 S100 D al
211. ace conforming to NEC s standard bus format Serial bus has address command data informa tion Wake up function for hand shake output function of acknowledge and busy signals available 2 wire SCKO serial clock Any data transfer format can be supported by the serial I O SBO or SB1 serial program and lines for hand shake conventionally mode data bus necessary for connecting multiple devices can be eliminated Caution Do not change the operation mode 3 wire serial I O 2 wire serial I O or SBI while the operation of serial interface channel 0 is enabled To change the operation mode stop the serial operation 260 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 uPD78018F SUZ 15 2 Configuration of Serial Interface Channel 0 Serial interface channel 0 consists of the following hardware Table 15 3 Configuration of Serial Interface Channel 0 Configuration Register Serial I O shift register O SIOO Slave address register SVA Control register Timer clock select register 3 TCL3 Serial operation mode register O CSIMO Serial bus interface control register SBIC Interrupt timing specification register SINT Port mode register 2 PM2 Note Note Referto Figure 6 6 Block Diagram of P20 P21 and P23 P26 uPD78018F Subseries and Figure 6 7 Block Diagram of P22 and P27 uPD78018F Subseries 261 393 Figure 15 1 Block Diagram of Serial Interface Channel 0 Internal bus
212. address 23 3 1 Operation mode The PROM programming mode is set when 5 V or 12 5 V is applied to the Ver pin or when a low level signal is applied to the RESET pin In this mode the operation modes shown in Table 23 4 can be set by using the CE OE and PGM pins By setting the read mode the contents of the PROM can be read Table 23 4 Operation Modes for PROM Programming Operation Mode i Page data latch Data input Page write High impedance Byte write Data input Program verify Data output Program inhibit High impedance Read Data output Iyer ry coy er co oye Output disable High impedance x Standby High impedance Remark x LorH 1 Read mode The read mode is set by setting CE L and OE L 2 Output disable mode The data output goes into a high impedance state and the output disable mode is set when OE H When two or more uwPD78P018F s or 78P018FY s are connected to the data bus therefore data can be read from any one of the devices by controlling the OE pin 468 CHAPTER 23 uPD78P018F 78P018FY 3 4 5 6 7 8 Standby mode The standby mode is set when CE H In this mode the data output goes into a high impedance state regardless of the status of OE Page data latch mode The page data latch mode is set when CE H PGM H and OE Latthe beginning of the page write mode In this
213. address of the stack area in the memory As the stack area only the internal high speed RAM area can be specified The internal high speed RAM area of each product is as follows Table 5 5 Internal High Speed RAM Area Part Number Internal High Speed RAM Area HPD78011F 78011FY 78012F 78012FY FDOOH FEFFH HPD78013F 78013FY 78014F 78014FY FBOOH FEFFH 4PD78015F 78015FY 78016F 78016FY 4PD78018F 78018FY 78P018F 78P018FY Figure 5 11 Stack Pointer Configuration 15 0 SP The contents of the stack pointer are decremented when data is written saved to the stack memory and incremented when data are read restored from the stack memory The data saved restored as a result of each stack operation are as shown in Figures 5 12 and 5 13 Caution The contents of the SP become undefined when the RESET signal is input Be sure to initialize the SP before executing an instruction 103 CHAPTER 5 CPU ARCHITECTURE Figure 5 12 Data Saved to Stack Memory PUSH rp instruction CALL CALLF CALLT instructions Interrupt BRK instructions SP SP 3 A SP lt SP 2 SP lt SP 2 SP 3 PC7 PCO j sP 2 Register pair low sP 2 PC7 PCO sP 2 PC15 PC8 A A SP 1 Register pair high SP 1 PC15 PC8 SP 1 PSW SP gt SP gt SP gt Figure 5 13 Data Restored from Stack Memory POP rp instruction RET instruction RETI RETB instr
214. ake place because of priority control Main INTxx INTyy processing processing processing IE 0 INTxx INTyy PR 0 PR 1 En Execution of one instruction IE 0 RETI Interrupt request INTyy that is generated while interrupt INTxx is being serviced is not accepted because its priority is lower than that of INTxx and therefore nesting does not take place INTyy request is kept pending and is accepted after one instruction of the main routine has been executed PR 0 High priority level PR 1 Low priority level IE 0 Accepting interrupt request is disabled 419 CHAPTER 18 INTERRUPT FUNCTIONS AND TEST FUNCTIONS Figure 18 15 Example of Nesting 2 2 Example 3 Example where nesting does not take place because interrupts are not enabled Main INTxx INTyy processing processing processing INTxx PR 0 Execution of IE 0 one instruction RETI Because interrupts are not enabled El instruction is not issued in interrupt processing INTxx interrupt request INTyy is not accepted and nesting does not take place INTyy request is kept pending and is accepted after one instruction of the main routine has been executed PR 0 High priority level IE 0 Accepting interrupts is disabled 420 CHAPTER 18 INTERRUPT FUNCTIONS AND TEST FUNCT 18 4 5 Pending interrupt requests Even if an interrupt request is generated the following instructions keep it pendin
215. al I O mode or 12C mode errors can be detected by using SVA The contents of SVA become undefined when the RESET signal is input 313 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78018FY SUBSERI7 3 4 5 6 7 314 SO0 latch This latch retains the levels of SI0 SBO SDAO0 P25 and SO0 SB1 SDA1 P26 pins It can also be directly controlled by software Serial clock counter This counter counts the serial clocks output or input during transmit receive operation and checks whether 8 bit data has been transmitted received Serial clock control circuit This circuit controls supply of the serial clock to the serial I O shift register 0 SIOO When the internal system clock is used it also controls the clock output to the SCKO SCL P27 pin Interrupt request signal generation circuit This circuit controls generation of an interrupt request signal An interrupt request signal is generated as shown in Table 16 4 depending on the setting of bits O and 1 WATO and WAT1 of the interrupt timing specification register SINT and bit 5 WUP of the serial operation mode register 0 CSIMO Acknowledge output circuit and stop condition start condition acknowledge detection circuit These circuits output and detect various control signals in the I2C bus mode They do not operate in the 3 wire serial l O mode and 2 wire serial I O mode al UNO Serial Transfer Mode BSYE 3 wire serial I O mode or Description
216. al Interface Channel 0 The following four types of registers control serial interface channel 0 Timer clock select register 3 TCL3 Serial operation mode register 0 CSIMO Serial bus interface control register SBIC Interrupt timing specification register SINT 1 Timer clock select register 3 TCL3 refer to Figure 15 2 2 This register sets the serial clock of serial interface channel 0 TCL is set by an 8 bit memory manipulation instruction This register is set to 88H when the RESET signal is input Remark TCL3 also has a function to set the serial clock of serial interface channel 1 in addition to the function to set the serial clock of serial interface channel 0 Serial operation mode register 0 CSIMO refer to Figure 15 3 This register sets the serial clock and operation mode of serial interface channel 0 enables disables the operation of the interface sets the wake up function and indicates the coincidence signal of the address comparator CSIMO is set by a 1 bit or 8 bit memory manipulation instruction This register is set to OOH when the RESET signal is input Caution Do not change the operation mode 3 wire serial I O 2 wire serial I O or SBI while the operation of serial interface channel 0 is enabled To change the operation mode stop the serial operation 265 al UNO CHAPTER 15 SERIAL INTERFACE CHANNEL 0 uPD78018F SUBSERI Figure 15 2 Format of Timer Clock Select Reg
217. al interface channel 0 transfer end interrupt request flag CSIIFO Serial interface channel 1 transfer end interrupt request flag CSIIF1 and TRF SBI serial bus interface 2 wire serial I O Available Not available Note Can be set only when the main system clock oscillates at 4 19 MHz or less 259 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 uPD78018F SUBSERIEF iu ed T Pilaz 15 1 Functions of Serial Interface Channel 0 Serial interface channel 0 has the following four modes Table 15 2 Differences in Modes of Serial Interface Channel 0 Operation Pins Used Features Applications Mode Operation Mode used when no serial transfer is performed stop mode Power consumption can be reduced 3 wire SCKO serial clock Short data transfer processing time because Useful for connect serial I O SOO serial output independent input and output lines are used ing peripheral I Os mode SIO serial input allowing simultaneous transmission and reception and display control MSB LSB selectable for first bit of 8 bit data by lers with conven serial transfer tional clocked serial interface such as 75X XL series 78K series and 17K SBI mode SCKO serial clock Because serial bus consists of two signal lines SBO or SB1 serial number of ports can be reduced and wiring data bus distance on PWB can be shortened even when plural microcomputers are connected Series High speed serial interf
218. al operation Modes ikna ee ches eee dt a eee 3 1 2 Pins in PROM programming mode uPD78P018F only eeeesceeeeeeeeeeeeeeeetteteeeeeeeeaees 3 2 Description Of Pin Functions ccceseeeeceeeeeneeeeeeeeneeeeeeeeeneeseeeeeeneeseeeesenesesessneeseeeeenenes 3 2 1 PQO P04 POMO s science ondaa 3 22 PTOP ROM not donde eee Le ne a EE 3 2 3 P20 P27 Portland lar ee es RA PROPIO Po A a aia ds 3 25 PAO PAT PO a a A A ETE EE E A 3 27 3PG60 P67 a S A a aa 328 AVR E is E cas d da 3 2 9 AVDD sins eek okt ae HAS See A IR een el LIO GAN SS a a lec dade ei nee te at eed heed tod tt geet enti anon AR Pace SN NESE Tits acts chess cheer et he E AE Siac oan eht es oll tts oc ales eres thes Ue 3 212 XT and X2 see oe O TN A Kian XT 2 sie eet NO Bi2i14 gt VDD aeti aE E cs ledeeusecesddecyaucgedscsbceseetadevecsuvceedeesesveevsuessseee eda Eaa E E tes A NOR 35 35 36 36 38 40 46 48 49 50 51 51 53 53 54 54 55 56 61 63 64 65 67 67 67 70 71 71 71 72 73 73 74 74 74 74 74 75 75 75 75 75 17 3 2 16 VPP uPD78P018F only acweetiud wins anc Muga eutuie cel eel atece ea lite eck 75 3 2 17 IC mask ROM model only ocoocccncconccononicincnnoccnoncnonnccnnncnnn cnn cnn cnn cnn carr 75 3 3 I O Circuits of Pins and Handling of Unused Pins csecceeseeeseeeeeeeeeeeeeeeeeeeeeeeeneas 76 CHAPTER 4 PIN FUNCTIONS uPD78018FY SUBSERIES ccccesseeeceeeeseeeeeeensnseeeeeenees
219. alling edge of clock of SCKO immediately after busy mode is released after transfer start instruction e When acknowledge signal ACK is detected at has been executed rising edge of clock of SCKO after completion of e When CSIEO 0 transfer When RESET is input Note BSYE Synchronous busy signal output control Disables output of busy signal in synchronization with falling edge of clock of SCKO immediately after instruction that clears this bit to O has been executed Outputs busy signal from falling edge of clock of SCKO following acknowledge signal Note The busy mode can be released when transfer by the serial interface has been started However the BSYE flag is not cleared to 0 Remarks 1 Bits 0 1 and 4 RELT CMDT and ACKT are 0 when they are read after data has been set 2 CSIEO Bit 7 of the serial operation mode register 0 CSIMO 269 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 uPD78018F SUBSERIE 4 Interrupt timing specification register SINT This register sets the bus release interrupt and address mask function and indicates the status of the level of the SCKO P27 pin SINT is set by a 1 bit or 8 bit memory manipulation instruction This register is set to OOH when the RESET signal is input Figure 15 5 Format of Interrupt Timing Specification Register Symbol 7 lt 6 gt lt 5 gt lt 4 gt 3 2 1 0 sor o oo se Jo oe Jo R W SVAM Bits of SVA used as slave address 0 Bits 0 7 1 Bits
220. als in the external memory extension mode P60 through P63 can directly drive LEDs Port 6 can be set in the following operation modes in 1 bit units 1 2 Port mode In this mode P60 through P67 constitute an 8 bit 1 O port which can be set in the input or output mode in 1 bit units by using the port mode register 6 PM6 P60 through P63 are N ch open drain pins These pins of the mask ROM model can be connected to an internal pull up resistor by mask option When using P64 through P67 as input port pins an internal pull up resistor can be used if so specified by the pull up resistor option register PUO Control mode In this mode P60 through P67 functions as control signal output pins RD WR WAIT and ASTB in the external memory extension mode The pins used as control signal output pins are automatically disconnected from the internal pull up resistor Caution Ifthe external wait state is not used in the external memory extension mode P66 can be used as an I O port pin 3 2 8 AVREF This pin inputs a reference voltage to the A D converter Connect this pin to Vss when the A D converter is not used 3 2 9 AVob This is the analog power supply pin of the A D converter Keep this pin at the same voltage as the Voo pin even when the A D converter is not used 3 2 10 AVss This is the ground pin of the A D converter Keep this pin at the same voltage as the Vss pin even when the A D converter is not used 74
221. an operate as an equivalent to the IE 78001 R A by replacing its internal break board with the IE 78001 R BK under development Table B 1 System up Method from Former In circuit Emulator for 78K 0 Series to the IE 78001 R A In circuit Emulator Owned In circuit Emulator Cabinet System upNote Board to be Purchased IE 78000 R Required IE 78001 R BK IE 78000 R A Not required Note For system up of a cabinet send your in circuit emulator to NEC 505 APPENDIX B DEVELOPMENT TOOLS Dimensions of Conversion Socket EV 9200GC 64 and Recommended Board Mounting Pattern Figure B 2 EV 9200GC 64 Dimensions Reference a A E 7 B E Vrs o 1 rr ajo O E Ss E X Homama i r E No 1 pin index P TH H Le l EV 9200GC 64 G0E ITEM MILLIMETERS INCHES 18 8 0 74 B 14 1 0 555 C 14 1 0 555 D 18 8 0 74 E 4 C 3 0 4 C 0 118 F 0 8 0 031 G 6 0 0 236 H 15 8 0 622 18 5 0 728 J 6 0 0 236 K 15 8 0 622 L 18 5 0 728 M 8 0 0 315 N 7 8 0 307 O 2 5 0 098 P 2 0 0 079 Q 1 35 0 053 R 0 35 0 1 0 014 9 008 S 2 3 0 091 91 5 0 059 506 APPENDIX B DEVELOPMENT TOOLS Figure B 3 EV 9200GC 64 Recommended Pattern of Board Mounting Reference OULU
222. and the HALT mode is set When the HALT mode is released automatic transmission reception is resumed from where it was stopped 2 When automatic transmission reception was stopped do not change the operation mode to the 3 wire serial I O mode while TRF 1 Figure 17 17 Stopping and Resuming Automatic Transmission Reception CSIE1 0 stop command Stopped Resume command CSIE1 1 and writing to SIO1 SCK1 sor _ Xo7kosXosXo4kosXo2XoiXoo f Ab7xDexpSADeXo3 AD2 AD ADO sit _ Ao7fpepsADs fos Ap2xor Do f p7ApexoskDsAD3AD2ADiADO CSIE1 Bit 7 of serial operation mode register 1 CSIM1 392 al UNO CHAPTER 17 SERIAL INTERFACE CHANNEL 1 4 Synchronization control Busy control and strobe control are functions to synchronize transmission reception between the master device and a slave device By using these functions a shift in bits being transmitted or received can be detected a Busy control option Busy control is a function to keep the serial transmission reception by the master device waiting while the busy signal output by a slave device to the master is active When using this busy control option the following conditions must be satisfied Bit 5 ATE of the serial operation mode register 1 CSIM1 is set to 1 e Bit 1 BUSY1 of the automatic data transmit receive control register ADTC is set to 1 Figure 17 18 shows the system configuration of the master device and a slave device when the bu
223. and the count operation is stopped To operate the interval timer at the same time set 0 to TMC22 so that the watch timer can be started from zero seconds maximum error 15 6 ms at 32 768 kHz operation 226 CHAPTER 10 WATCH TIMER 10 4 2 Operation as interval timer The watch timer also operates as an interval timer that repeatedly generates an interrupt request at time intervals specified by a count value set in advance The interval time can be selected by the bits 4 through 6 TMC24 TMC26 of the watch timer mode control register Table 10 3 Interval Time of Interval Timer TMC25 TMC24 Interval Time At fx 10 0 MHz At fx 8 38 MHz At fx 4 19 MHz At fxt 32 768 kHz 24 x 1 fw 25 x 1 fw 26 x 1 fw 27 x 1 fw 28 x 1 fw 29 x 1 fw Setting prohibited Remark fx Main system clock oscillation frequency fxt Subsystem clock oscillation frequency fw Watch timer clock frequency fx 28 or fxr 227 MEMO 228 CHAPTER 11 11 1 Functions of Watchdog Timer The watchdog timer has the following functions e Watchdog timer Interval timer WATCHDOG TIMER Caution Select the watchdog timer mode or interval timer mode by using the watchdog timer mode register WDTM The watchdog timer and interval timer cannot be used simultaneously 1 Watchdog timer mode The watchdog timer is used to detect inadvertent program loop When the inadvertent loop i
224. are preliminary editions but not so specified here Device related documents Document Name 4PD78011F 78012F 78013F 78014F 78015F 78016F 78018F Data Sheet Document Number Japanese U10280J English U10280E HPD78011FY 78012FY 78013FY 78014FY 78015FY 78016FY 78018FY Data Sheet U10281J U10281E 4PD78P018F Data Sheet U10955J U10955E 4PD78P018FY Data Sheet U10989J U10989E 14PD78011F A 78012F A 78013F A 78014F A 78015F A 78016F A 78018F A Data Sheet U11921J U11921E 4PD78P018F A Data Sheet U12132J U12132E 1PD78018F 78018FY Subseries User s Manual U10659J This manual 78K 0 Series User s Manual Instruction U12326J U12326E 78K 0 Series Instruction Table U10903J 78K 0 Series Instruction Set U10904J 1PD78018F Subseries Special Function Register Table IEM 5594 1PD78018FY Subseries Special Function Register Table U10287J 78K 0 Series Application Note Basic l U12704J U12704E Floating point Program IEA 718 IEA 1289 Caution The contents of the above related documents are subject to change without notice Be sure to use the latest edition in designing your system 13 Development tool related documents user s manual Document Name RA78KO Assembler Package Operation Document Number Japanese U11802J English U11802E Assembly Language
225. are transmitted in the repetitive transmit mode Figure 17 14 Operation Timing of Repetitive Transmit Mode Interval Interval Sor _forYosfosfoagosyo2forfoo KorfoejosXoefoshoa oiXoo Xor ADe XDS Caution In the repetitive transmit mode the buffer RAM is read after 1 byte data has been transmitted Therefore there is interval time until the next transmission is executed Because the buffer RAM is read simultaneously with the CPU processing the maximum interval time depends on the CPU processing and the value of the automatic data transmit receive time interval specification register ADTI refer to 5 Interval time of automatic transmission reception 388 CHAPTER 17 SERIAL INTERFACE CHANNEL 1 Figure 17 15 Flowchart of Repetitive Transmit Mode Writes transmit data to buffer RAM Sets value of number of transmit data bytes minus 1 to ADTP pointer value Software execution Sets interval time for transmit receive operation to ADTI Writes any data to SIO1 start trigger Writes transmit data from buffer RAM to SIO1 Transmit operation Decrements pointer value Hardware execution Pointer value 0 Sets ADTP again ADTP Automatic data transmit receive address pointer ADTI Automatic data transmit receive interval specification register SIO1 Serial I O shift register 1 389 CHAPTER 17 SERIAL INTERFACE CHANNEL 1 390 The buffer RAM operates as follows when 6 bytes are
226. are used as an input port an internal pull up resistor can be used if so specified by the pull up resistor option register PUO Control mode In this mode POO through P04 are used to input external interrupt requests an external count clock to timer and to connect a crystal resonator for subsystem clock oscillation a INTPO INTP3 INTPO INTP2 are external interrupt request input pins for which valid edge can be specified rising edge falling edge and both rising and falling edges INTPO also functions as the capture trigger input pin of the 16 bit timer event counter when a valid edge is input INTP3 is a falling edge triggered external interrupt request input pin b TIO External count clock input pin of the 16 bit timer event counter c XT1 Subsystem clock oscillation crystal connecting pin 4 2 2 P10 P17 Port1 These pins form an 8 bit I O port port 1 These pins also serve as the analog input pins of the A D converter They can be set in the following operation modes in 1 bit units 1 2 Port mode In this mode P10 through P17 constitute an 8 bit I O port which can be set in the input or output mode in 1 bit units by using the port mode register 1 PM1 When used as an input port an internal pull up resistor can be used if so specified by the pull up resistor option register PUO Control mode In this mode P10 through P17 function as the analog input pins ANIO ANI7 of the A D converter When these pins
227. as been set to 1 3 Once RUN has been set to 1 it cannot be cleared to O by software Therefore when counting is started it cannot be stopped by any means other than RESET input Cautions 1 When the watchdog timer is cleared by setting 1 to RUN the actual overflow time is up to 0 5 shorter than the time set by the timer clock select register 2 TCL2 2 To use watchdog timer modes 1 and 2 set the WDTM4 bit to 1 after confirming that the interrupt request flag TMIF4 is 0 If WDTM4 is set when TMIF4 is 1 a non maskable interrupt request is generated regardless of the contents of WDTM3 Remark x Don t care 234 CHAPTER 11 WATCHDOG TIMER 11 4 Operation of Watchdog Timer 11 4 1 Operation as watchdog timer The watchdog timer detects an inadvertent program loop when bit 4 WDTM4 of the watchdog timer mode register WDTM is set to 1 The count clock inadvertent loop detection time interval of the watchdog timer can be selected by bits 0 through 2 TCL20 TCL22 of the timer clock select register 2 TCL2 By setting bit 7 RUN of WDTM to 1 the watchdog timer is started Set RUN to 1 within the set inadvertent loop detection time interval after the watchdog timer has been started By setting RUN to 1 the watchdog timer can be cleared and started counting If RUN is not set to 1 and the inadvertent loop detection time is exceeded the system is reset or a non maskable interrupt is generated by the value of bit 3 WDT
228. ates the coincidence signal from the address comparator of serial operation mode register 0 CSIMO is tested If this bit is 1 transmission has been completed normally If it is 0 a transmission error has occurred Communication operation In the 12C bus mode the master outputs an address onto the serial bus to select one of the slave devices to be communicated Following the slave address the master transmits an R W bit that indicates the transfer direction of data and starts serial communication with the slave Timing charts for data communication are shown in Figures 16 21 to 16 22 The serial I O shift register 0 SIOO performs a shift operation in synchronization with the falling edge of the serial clock SCL and the transmitted data is transferred to the SOO latch and is output from the SDAO or SDA1 pin with MSB first The data input to the SDAO or SDA1 pin is loaded to the shift register SIOO at the rising edge of SCL 345 al UNO CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78018FY SUBSERI7 y Figure 16 21 Example of Communication from Master to Slave with 9 clock wait selected for both master and slave 1 3 a Start condition address Processing in master device SIOO write col X_ XXX AANA XX XX ACKD 2 oan ee CMDD pS RELD L A AA SIO0 lt address SIO0 data CLD LLL P27 H weroo o Po ____ BSYE L IN PEN ACKE L A E oo E CMDT RELT L o G CLC H e WREL L
229. ation NEC Corporation assumes no responsibility for any errors which may appear in this document NEC Corporation does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device No license either express implied or otherwise is granted under any patents copyrights or other intellectual property rights of NEC Corporation or others While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices the possibility of defects cannot be eliminated entirely To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device customers must incorporate sufficient safety measures in its design such as redundancy fire containment and anti failure features NEC devices are classified into the following three quality grades Standard Special and Specific The Specific quality grade applies only to devices developed based on a customer designated quality assurance program for a specific application The recommended applications of a device depend on its quality grade as indicated below Customers must check the quality grade of each device before using it in a particular application Standard Computers office equipment communications equipment test and measurement equipment audio a
230. ation instruction This register is set to OOH when the RESET signal is input Caution Do not change the operation mode 3 wire serial I O 2 wire serial I O or 12C bus while the operation of serial interface channel 0 is enabled To change the operation mode stop the serial operation al UNO CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78018FY S Figure 16 2 Format of Timer Clock Select Register 3 Address On reset R W FF43H 88H RW TCL32 TCL31 TCL30 Selects serial clock of serial interface channel 0 Serial clock in 12C bus mode Serial clock in 3 wire serial I O mode or 2 wire serial l O mode fx 26 fx 27 fx 28 156 kHz fx 22 Note 78 1 kHz fx 28 1 25 MHz 39 1 kHz fx 24 625 kHz fx 22 19 5 kHz fx 25 313 kHz fx 211 4 9 kHz fx 27 78 1 kHz fx 28 39 1 kHz fx 210 9 8 kHz fx 212 2 4 kHz fx 213 1 2 kHz fx 25 156 kHz fx 22 19 5 kHz Others Setting prohibited TCL36 TCL35 fx 22Note fx 23 1 25 MHz fx 24 625 kHz fx 25 313 kHz fx 28 156 kHz fx 27 78 1 kHz fx 28 39 1kHz fx 29 19 5 kHz Others Setting prohibited Note Can be set only when the main system clock oscillates at 4 19 MHz or less Caution Before writing data other than that already written to TCL3 stop the serial transfer Remarks 1 fx Main system cl
231. ation instruction This register is set to OOH when the RESET signal is input 455 CHAPTER 22 ROM CORRECTION Symbol Figure 22 3 Format of Correction Control Register lt 1 gt lt 0 gt 7 6 5 4 lt 3 gt lt 2 gt coron o o o o frenler erenlere 456 Address On reset R W FF8AH 00H emos corsTo Flag detecting coincidence between correction address register O and fetch address 0 Coincidence not detected 1 Coincidence detected CORENO Controls detection of coincidence between correction address register 0 and fetch address 0 Detection disabled 1 Detection enabled corsT1 Flag detecting coincidence between correction address register 1 and fetch address 0 Coincidence not detected 1 Coincidence detected Note Bits 0 and 2 are read only bits COREN1 Controls detection of coincidence between correction address register 1 and fetch address 0 Detection disabled 1 Detection enabled CHAPTER 22 ROM CORRECTION 22 4 Using ROM Correction lt 1 gt Store the correction address and corrected instruction corrected program to an external non volatile memory EEPROM If two places must be corrected a branch destination identification program is also stored This program identifies at which of the two addresses in CORADO or CORAD1 correction branch processing occurred Figure 22 4 Example of Storing in EEPROM when only one place is to be corrected EEPRO
232. bit timer event counter Timer register TM1 TM2 00H Compare register CR10 CR20 Undefined Clock select register TCL1 00H Mode control register TMC1 00H Output control register TOC1 00H Notes 1 Only the contents of the PC among hardware become undefined during reset input and oscillation stabilization time wait The other status is not different from that after reset as above 2 The status before reset is retained in the standby mode 3 The values at reset of the memory size select register IMS and internal extension RAM size select register IXS differ depending on the model as follows HPD78011F uPD78012F uPD78013F uPD78014F uwPD78015F uPD78016F wPD78018F uPD78P018F HPD78011FY uPD78012FY wPD78013FY uPD78014FY wPD78015FY uPD78016FY wPD78018FY wPD78P018FY IMS 42H IXS OCH OBH OAH When using the mask ROM model do not set a value other than that at reset to IMS and IXS except when the external device extension function of the PD78018F and 78018FY is used 451 CHAPTER 21 RESET FUNCTION Table 21 1 Status of Each Hardware after Reset 2 2 Hardware Status after Reset Watch timer Mode control register TMC2 Watchdog timer Clock select register TCL2 Mode register WDTM 00H Serial interface Clock select register TCL3 88H Shift register SIOO SIO1 Undefined Mode register CSIMO CSIM1 00H Serial bus i
233. by setting the bits O RELT and 1 CMDT of the serial bus interface control register SBIC However do not perform this manipulation during serial transfer The output level of the SCKO pin is controlled by manipulating the P27 output latch in the output mode mode of the internal system clock refer to 15 4 5 Manipulating SCKO P27 pin output 274 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 uPD78018F SUF 3 Signals Figure 15 7 shows the operations of RELT and CMDT Figure 15 7 Operations of RELT and CMDT SO0 latch RELT CMDT 4 MSB LSB first selection In the 3 wire serial l O mode whether data is transferred with the MSB or LSB first can be selected Figure 15 8 shows the configuration of the serial I O shift register O SIOO and internal bus As shown in the figure data can be read written with the MSB LSB inverted Whether the MSB or LSB is transferred first can be specified by using the bit 2 CSIMO2 of the serial operation mode register 0 CSIMO Figure 15 8 Transfer Bit Sequence Select Circuit 7 e 6 2 Internal bus 4 oe A SOURS Se ea ee 1 i 0 LSB first MSB first Read writegate gt Read write gate SOO0 latch Slo Shift register 0 S100 D al The first bit is selected by changing the bit order in which data is written to SIOO The shift sequence of S
234. c When external wait state is set PW1 PWO 1 1 A a e Hi Z wie data o A e Write data X High order address X 435 CHAPTER 19 EXTERNAL DEVICE EXTENSION FUNCTION 436 ASTB RD WR ADO AD7 A8 A15 ASTB RD WR ADO AD7 A8 A15 Internal wait signal 1 clock wait ADO AD7 A8 A15 WAIT Figure 19 7 Read Modify Write Timing of External Memory a When no wait state is set PW1 PWO 0 0 A A A NA AAA H z SSS Read data Write data High order address b When wait state is set PW1 PWO 0 1 dS ye SH NO TOA Hi Read data Write data High order address c When external wait state is set PW1 PWO 1 1 O 2 a EA C a os Xara addres Read data er i Write data X X High order address i X CHAPTER 19 EXTERNAL DEVICE EXTENSION FUNCTI 19 4 Example of Connection with Memory Figure 19 8 shows an example of connecting the uPD78014F and external memories In this application example SRAM is connected In addition the external device extension function is used in the full address mode and 32K bytes of addresses 0000H through 7FFFH are allocated to internal ROM addresses 8000H and higher are allocated uPD43256B cs OE WE 1 01 1 08 A0 A14 to SRAM Figure 19 8 Example of Connecting u PD78014F and Memories Vi uPD78014F a Address bus uPD74HC573 ADO AD7 Data bus
235. c transmit receive function 3 wire UART HPD780018AY 48 K 60 K 3 wire with automatic transmit receive function Time division 3 wire 12C bus multi master compatible uPD780058Y 24 K 60 K 3 wire 2 wire I2C 3 wire with automatic transmit receive function 3 wire time division UART uPD78058FY 48 K 60 K uPD78054Y 16 K 60 K 3 wire 2 wire I2C 3 wire with automatic transmit receive function 3 wire UART uPD780034Y 1PD780024Y 8 K 32 K UART 3 wire 12C bus multi master compatible uPD78018FY 3 wire 2 wire I2C 3 wire with automatic transmit receive function HPD78014Y 3 wire 2 wire SBI I2C 3 wire with automatic transmit receive function HPD78002Y 8 K 16 K 3 wire 2 wire SBI I2C LCD drive Remark 62 uPD780308Y 48 K 60 K 3 wire 2 wire I2C 3 wire time division UART 3 wire HPD78064Y The functions other than serial interface are common to the uPD78018F subseries 16 K 32 K 3 wire 2 wire I2C 3 wire UART CHAPTER 2 GENERAL uPD78018FY SUBSERIES 2 7 Block Diagram POO TOO P30 16 bit TIMER a POR TIO INTPO POO EVENT COUNTER ORTO es P03 TO1 P31 8 bit TIMER EVENT PORTA P10 P17 TH P33 gt COUNTER 1 PORT2 P20 P27 TO2 P32 8 bit TIMER EVENT TI2 P34 gt COUNTER 2 PORT3 P30 P37 WATCHDOG TIMER PORT4 P40 P47 WATCH TIMER S10 SB0 SDA0 P25 lt
236. ccecseeseteeeeeeeeeeeceeseseeeeenseesesneeeeeseesessnaeeneeeeeeseeeseeeeees 251 14 4 1 Basic operation of A D converter 0 eee eeceeeeneeeeeneeeeesaeeeeeaeeeteaeeeetaeetenaeeeteeeeeneneeeenaees 251 14 4 2 Input voltage and conversion reSUlt oo eee eeseeeeeneeeeeeeeeeeneeeeeneeeeeeaeeeseeeeeesateeseeeersaeees 253 14 4 3 Operation mode of A D converter ooocncocnnccncccincicncccnncncnncnnnnnnancn non c cono cnn cnn nn ran c cnn nnnnn nana 254 14 5 Notes on A D Converter ccmmiocccccncnnnccncnninnnc rn 256 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 uPD78018F SUBSERIES oooooccccononocccnonoas 259 15 1 Functions of Serial Interface Channel 0 ccccsscccsseeeeeeseeeeseeeeeeeeeseseeeeeeeeesesnaeeeneeeeeas 260 15 2 Configuration of Serial Interface Channel 0 onnnnnnnnccnccconnnsnnnnnrccnsernnrerarerccrner 261 15 3 Registers Controlling Serial Interface Channel 0 csseeeeesteesseeeeeseeeeseeeeeeeeeeees 265 15 4 Operation of Serial Interface Channel 0 ccccccssccesseeeeeeseeeeseeeeeeeeeseseeeeeeeeeseseaesenseeeeas 271 15 41 Operation Stop Mode csie ni tats Ansan tee el te ton ate 271 15 4 2 Operation in 3 wire serial l O mode ou ceeceeecceeeeeeeeeeeneeeeeeeeeeeseaeeeaeeeeaeeseeeeaeeseeeeeaeeeeaeesas 272 15 43 Operation in SBI iMOde i 20 csi said ado ie ae 276 15 4 4 Operation in 2 wire serial l O mode ee eeeceeeeeeeneeeeeeeeeeeeeeeeeaeeteaeeeeeeseaeesaeeenaeesneeseaeeenaeesas 303 15 4 5 Manipulating SCKO P
237. cceensnsseeeensnseceeneenss 91 5 1 ES AP sennedestouesuscacenscuesesstavesctecdsussescntcestecte 91 5 1 1 Internal program memory Space ooccccnncccnonoccnnnonnnnnnnnnnn arc r cnn 99 5 1 2 Internal data memory space coomcccccnccccnonecccnnancnnnnrncnnne cnn nc 100 5 1 3 Special function register SFR area onccincninncnnconnnccnnccnocnnnnnnnann conc n nac n rra 101 51 4 External memory Spaces tina aia ia 101 5 2 Processor Registers c cseeccecceseeeeeeeesseeeeeeeeseeeeeeenssneeeeeeesneeesesensneeseeeasaneesesessneeeeeeesananes 102 5 2 1 Control registers iii rica 102 5 2 2 General Purpose registers eccceseesceseneeeeeeceeeeeseeeeaeeeseeseaeeeseeseaeeseeeseaeeseaeeeeessaeeeeeeeaees 105 5 2 3 Special function registers SFRS cecceesseesseeeseeeeeeeeneeceaeeeeeseaeeeseeesaeeseeeeeaeessaeeeaeeeaees 107 5 3 Addressing Instruction Address 0 scccceseeeeeeseeeeeeseseseeeeseeseeeeeeeesseeneeseeseeenenensneeenees 111 5 3 1 Relative addressing aiee aaa iii bara isa 111 9 3 2 immediate Addressing nisinsin dd ad lesiones 112 5 3 3 Table indirect addressing ocoomocconnncnnnnocnnnsncnnnccnnn rre rra 113 5 3 4 Register addressing ica nachos 114 5 4 Addressing of Operand Address cccsseccececeseteeeeseeeeeeseeseseeeeenseeeesseaeseeeeeessseeseneeeeeneas 115 5 4 1 Data Memory addressing cccseceeecceeeseeeeeeeeeeeesenseesceeeeeeceneeeeeeeneeeeenenseseneceessenenerenseneees 115 5 42 Implied addres
238. ce is not initialized until the reset signal is received Reset operation must be executed immediately after power on for devices having reset function FIP EEPROM IEBus and QTOP are trademarks of NEC Corp MS DOS Windows and WindowsNT are trademarks of Microsoft Corp IBM DOS PC AT and PC DOS are trademarks of IBM Corp HP9000 series 700 and HP UX are trademarks of Hewlett Packard Co SPARCstation is a trademark of SPARC International Inc SunOS is a trademark of Sun Microsystems Inc Ethernet is a trademark of Xerox Corp NEWS NEWS OS are trademarks of Sony Corp OSF Motif is a trademark of Open Software Foundation Inc TRON is an abbreviation of the Realtime Operating system Nucleus ITRON is an abbreviation of Industrial TRON The export of these products from Japan is regulated by the Japanese government The export of some or all of these products may be prohibited without governmental license To export or re export some or all of these products from a country other than Japan may also be prohibited without a license from that country Please call an NEC sales representative License not needed UPD78P018FDW 78P018FKK S 78P018FYDW 78P018FYKK S The customer must judge the need for license wPD78011FCW XXX 78011FGC XXX AB8 78011FGK XXX 8A8 HPD78012FCW XXX 78012FGC XXX AB8 78012FGK XXX 8A8 1PD78013FCW XXX 78013FGC XXX AB8 78013FGK XXX 8A8 HPD78014FCW XXX 78014FGC XXX AB8 78014FGK XXX 8A8 HPD78015FCW XXX 78015
239. ces are available Software interrupts This is a vectored interrupt generated when the BRK instruction is executed and can be accepted even in the interrupt disabled status This interrupt is not subject to interrupt priority control 18 2 Interrupt Sources and Configuration A total of 14 interrupt sources including non maskable maskable and software interrupt sources are available refer to Table 18 1 401 al UNO CHAPTER 18 INTERRUPT FUNCTIONS AND TEST FUNCTIONS Table 18 1 Interrupt Sources Note 1 Interrupt Source Vector Interrupt Default i Internal Table Basic Configu Type Priority ate External Address ration Type rigger Non INTWDT Overflow of watchdog timer when Internal maskable watchdog timer mode 1 is selected Maskable INTWDT Overflow of watchdog timer when interval timer mode is selected INTPO Pin input edge detection External INTP1 INTP2 INTP3 INTCSIO End of transfer of serial interface channel Internal 0 INTCSI1 End of transfer of serial interface channel 1 INTTM3 Reference time interval signal from watch timer INTTMO Generation of coincidence signal from 16 bit timer event counter INTTM1 Generation of coincidence signal from 8 bit timer event counter 1 INTTM2 Generation of coincidence signal from 8 bit timer event counter 2 End of conversion of A D converter S
240. ck input to 16 bit timer TMO External count clock input to 8 bit timer TM1 External count clock input to 8 bit timer TM2 POO INTPO P33 P34 TOO TO1 TO2 16 bit timer TMO output shared by 14 bit PWM output 8 bit timer TM1 output 8 bit timer TM2 output P30 P31 P32 PCL Output Clock output for trimming of main system clock subsystem clock P35 BUZ Output Buzzer output P36 ADO AD7 1 0 Low order address data bus when memory is externally extended P40 P47 A8 A15 Output High order address bus when memory is externally extended P50 P57 RD WR Output Strobe signal output for external memory read Strobe signal output for external memory write P64 P65 Input Wait insertion when external memory is accessed P66 Output Strobe output that externally latches address information output to ports 4 and 5 to access external memory P67 81 CHAPTER 4 PIN FUNCTIONS uPD78018FY SUBSERIES 2 Pins other than port pins 2 2 Pin Name Function ANIO ANI7 Analog input to A D converter AVREF Reference voltage input to A D converter AVoo Analog power to A D converter Connect to Von AVss Ground of A D converter Connect to Vss RESET System reset input Connect crystal resonator for main system clock oscillation Connect crystal resonator for subsystem clock oscillati
241. ck is selected when the RESET signal is generated PCC 04H While a low level is input to the RESET pin oscillation of the main system clock is stopped Five types of CPU clocks 0 4 us 0 8 us 1 6 us 3 2 us and 6 4 us at 10 0 MHz operation can be selected by the PCC setting with the main system clock selected Two standby modes STOP and HALT can be used when the main system clock is selected In a system where the subsystem clock is not used the current consumption in the STOP mode can be further reduced by specifying not to use the internal feedback resistor by using the bit 6 FRC of PCC The subsystem clock can be selected by PCC and the microcomputer can operate with a low current consumption 122 us at 32 768 kHz operation Oscillation of the main system clock can be stopped by PCC with the subsystem clock selected Moreover the HALT mode can be used However the STOP mode cannot be used oscillation of the subsystem clock cannot be stopped The clock to the peripheral hardware is supplied by dividing the main system clock However the subsystem clock is supplied to the watch timer and clock output function only Therefore the watch function and clock output function can be continuously used even in the standby status The other peripheral hardware is stopped when the main system clock is stopped because the peripheral hardware operates on the main system clock except however the external clock input operation
242. cnnnnccononccnnnnonnnnnon corno corn n cnn nan nrr nar n rr rr rra 479 22 24 1 3 Description in flag Operation COLUMN 2 0 eee eesseeeesneeeeeneeeteneeeersaeeeeeaeeeenneeeseeeeeseneetenaees 479 24 2 Op ra O List csr ssc reste es aoe ai adan 480 24 3 Instruction List by Addressing moococccnnnnnnnonnnnannccnnnnnnnn nn 488 APPENDIX A DIFFERENCES BETWEEN uPD78014 78014H AND 78018F SUBSERIES 493 APPENDIX B DEVELOPMENT TOOLS eccccseseeeeeseeeeeeeeeeeeeeesseeeseeeeeessaeseneeeesseaeseeseeeeseeeseeseeeenes 495 B 1 Language Processing Software cscccssseceseeessseeesseeeeseseeseseeeeeeseeseseeeeeesneseseeeeeneenens 498 B 2 PROM Writing T O S e aaraa ea eaa eaa ea aae aeaaeae ea aa eaaa aaaeeeaa 500 227A AE m EON TA EA EETA TEET 500 B22 S0tWaAlE ie i a A 500 B 3 Debugging TOOIS css iii cda 501 B3 1 Hardware neci ai aie ee ee ARA 501 B327 SOWA Ori e a a dis adas 503 B4 OS for BM PG a a e ainda 505 B 5 System Upgrade from Former In circuit Emulator for 78K 0 Series to 1E 78001 R A oo ccccescceseeeeeeeeeeesneeeeeeeeeaneaeeeeeeeeasaaeseneeeeescaeseaseeeseseesenseeeenes 505 APPENDIX C EMBEDDED SOFTWARE ccssseecesseeeseeeeeeseeeeesneeenseeeessnaeseseeeeeseeseseneeeseneseseeeeenes 509 APPENDIX D REGISTER INDEX oc coco ondaa anti 513 D 1 Register Index In Alphabetical Order with Respect to Register Name 513 D 2 Register Index In Alphabetical Order with Respect to Register Symbol
243. condition Figure 16 15 Addresses SCL 1 2 3 4 5 6 7 Senos et SDAO SDA1 A6 A5 A4 A3 A2 Al AO R W N N i N N N i Address 335 i TAA Y ed CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78018FY SUBSERI7 c Transfer direction specification Following the 7 bit address the master transmits 1 bit of data to specify the direction of transfer If this transfer direction specification bit is O the master transmits data to the slave If the bit is 1 the master receives data from the slave Figure 16 16 Transfer Direction Specification SCL 1 2 3 4 5 6 7 8 ee eee SDAO SDA1 as as a4 as a2 ar ao RW i l I i i i i l UY Transfer direction specification d Acknowledge signal ACK The acknowledge signal is used to confirm that serial data has been received at transmission and reception sides The reception side returns the acknowledge signal each time it has received 8 bits of data The reception side outputs the acknowledge signal usually after it received 8 bits of data If the master is receiving data however it does not output the acknowledge signal after it has received the last data The transmission side checks whether the reception side has returned the acknowledge signal after it has transmitted 8 bits of data When the acknowledge signal has been returned it is assumed that the 8 bit data has been correctly received and the next processing is performed If a slave does not return the ackno
244. condition is detected 343 i ri oY a lv ed CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78018FY SUBSERI7 5 Pin configuration The serial clock pin SCL and serial data bus pin SDAO or SDA1 are configured as follows a SCL ee Pin that inputs outputs serial clock lt 1 gt Master N ch open drain output lt 2 gt Slave Schmitt input b SDAO SDA1 Serial data input output dual pin N ch open drain output and Schmitt input for both master and slave Because both the serial clock and serial data bus are N ch open drain output they must be connected to external pull up resistors Figure 16 20 Pin Configuration Slave device Voo Master device SCL SCL a Clock output F gt Clock output TT TT Clock input Von Clock input _SDAO SDA1 SDAO SDA1 _ Data output F gt Data output TT TT Data input Data input Caution Because the N ch open drain output must be made high impedance state when data is received set bit 7 BSYE of the serial bus interface control register SBIC to 1 in advance and write FFH to the serial I O shift register 0 S100 However when the wake up function is used when bit 5 WUP of the serial operation mode register 0 CSIMO is set the N ch open drain output is always at high impedance state even if FFH is not written to SIOO 344 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78018FY Sp
245. connecting the EP 78240GC R the wPD78P018FKK S or 78P018FYKK S ceramic WQFN can also be connected EP 78012GK R Emulation Probe This probe is used to connect the in circuit emulator to the target system and is designed for 64 pin plastic LQFP GK 8A8 type TGK 064SBW Conversion Adapter Refer to Figure B 4 This conversion socket connects the EP 78012GK R to the target system board designed to mount a 64 pin plastic LQFP GK 8A8 type EV 9900 Note Under development Jig used to remove the wPD78P018FKK S or 78P018FYKK S from the EV9200GC 64 Remarks 1 TGK 064SBW is a product of TOKYO ELETECH Corporation Reference Daimaru Kogyo Ltd Electronics Dept TEL Tokyo 03 3820 7112 Electronics 2nd Dept TEL Osaka 06 244 6672 2 EV 9200GC 64 is sold in five units 3 TGK 064SBW is sold in one units 502 APPENDIX B DEVELOPMENT TOOLS B 3 2 Software 1 2 SM78K0 This system simulator is used to perform debugging at C source level or assembler System Simulator level while simulating the operation of the target system on a host machine This simulator runs on Windows Use of the SM78KO0 allows the execution of application logical testing and performance testing on an independent basis from hardware development without having to use an in circuit emulator thereby providing higher development efficiency and software quality The SM78K0 should be used in combination with the optical device file D
246. corresponding test input flag and generates a standby release signal when an overflow occurs in the watch timer and when a falling edge at port 4 is detected Unlike the interrupt function this function does not perform vector processing Table 18 5 Test Input Sources Test Input Source Internal External Trigger INTWT Overflow of watch timer Internal INTPT4 Detection of falling edge of port 4 External Figure 18 17 Basic Configuration of Test Function Internal bus Standby Test input release signal signal IF Test input flag MK Test mask flag 18 5 1 Registers controlling test functions The test function is controlled by the following three types of registers e Interrupt request flag register OH IFOH Interrupt mask flag register OH MKOH Key return mode register KRM Table 18 6 shows the names of the test input flags and test mask flags corresponding to the respective test input signals 422 CHAPTER 18 INTERRUPT FUNCTIONS AND TEST FUNCT Table 18 6 Flags Corresponding to Test Input Signals Test Input Signal Name Test Input Flag Test Mask Flag INTWT WTIF WTMK INTPT4 KRIF KRMK 1 Interrupt request flag register OH IFOH This register indicates whether an overflow in the watch timer is detected or not IFOH is set by a 1 bit or 8 bit memory manipulation instruction This register is set to OOH when the RESET signal is input Figure 18 18 Format
247. d FADFH FAC5H FACOH Transmit data 1 T1 Z FE SIO1 Transmit data 2 T2 Transmit data 3 T3 2 ADTP Transmit data 4 T4 Transmit data 5 T5 Transmit data 6 T6 CSIIF1 c At end of transmission FADFH FAC5H FACOH Transmit data 1 T1 fl SIO1 Transmit data 2 T2 Transmit data 3 T3 Transmit data 4 T4 Transmit data 5 T5 Transmit data 6 T6 CSIIF1 387 i ri oY a lv ed CHAPTER 17 SERIAL INTERFACE CHANNEL 1 c Repetitive transmit mode This mode is to repeatedly transmit the data stored in the buffer RAM The serial transfer is started by writing any data to the serial I O shift register 1 SIO1 when the bit 7 CSIE1 of the serial operation mode register 1 CSIM1 is set to 1 Unlike the basic transmit mode the interrupt request flag CSIIF1 is not set after the last byte data at address FACOH has been transmitted the value at which the transmission reception has been started is set again to the automatic data transmit receive address pointer ADTP and the contents of the buffer RAM are transmitted again When receive operation busy control and strobe control are not performed the P20 SI1 P23 STB and P24 BUSY pins can be used as ordinary I O ports Figure 17 14 shows the operation timing of the repetitive transmit mode and Figure 17 15 shows an operation flowchart And Figure 17 16 shows the operation of the buffer RAM when 6 bytes
248. d as the serial data bus SBO or SB1 must be externally pulled up because this pin is an N ch open drain I O pin When data is received write FFH to SIOO in advance because the N ch open drain output must be made high impedance state Because the SBO or SB1 pin outputs the status of the SOO latch the output status of the SBO or SB1 pin can be manipulated by setting bit 0 RELT and bit 1 CMDT of the serial bus interface control register SBIC However do not manipulate the output status of the pin during serial transfer The output level of the SCKO pin is controlled by manipulating the P27 output latch in the output mode mode of the internal system clock refer to 16 4 7 Manipulating SCK0 SCL P27 pin output 331 i rN a lu ed CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78018FY SUBSERI7 3 Signals Figure 16 11 shows the operations of RELT and CMDT Figure 16 11 Operations of RELT and CMDT SO0 latch RELT CMDT 4 Transfer start Serial transfer is started by setting the transfer data to the serial I O shift register O SIOO when the following two conditions are satisfied Operation control bit of serial interface channel 0 CSIEO 1 When internal serial clock is stopped or SCKO is high after 8 bit serial transfer Cautions 1 Even if CSIEO is set to 1 after data has been written to SIOO transfer is not started 2 Write FFH to SIOO in advance because the N ch open drain output must be
249. d in I C bus mode Puts output level of SCL pin in high impedance state when serial transfer is not executed the clock line is high Master uses this setting to make SCL high to generate start stop condition Notes 1 Bit 6 CLD is read only bit 2 Set CLC to 0 when the 12C bus mode is not used 321 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78018FY SUBSERI7 Figure 16 5 Format of Interrupt Timing Specification Register 2 2 R W SVAM Bits of SVA used as slave address 0 Bits 0 7 1 Bits 1 7 SIC Selects interrupt source of INTCSIO Note 1 0 Sets CSIIFO to 1 at end of transfer by serial interface channel O A Sets CSIIFO to 1 at end of transfer by serial interface channel 0 or on detection of stop condition in I C bus mode Level of SCKO SCL pin Note 2 0 Low level 1 High level Notes 1 Set SIC to 1 when using wake up function in the 12C bus mode 2 CLD is 0 when CSIEO 0 Remark SVA Slave address register CSIIFO Interrupt request flag corresponding to INTCSIO CSIEO Bit 7 of the serial operation mode register O CSIMO 322 i tinued CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78018FY Sp 16 4 Operation of Serial Interface Channel 0 Serial interface channel O operates in the following four operation modes Operation stop mode e 3 wire serial I O mode e 2 wire serial I O mode e 12C Inter IC bus mode 16 4 1 Operation stop mode Serial transfer is not executed in thi
250. d when the CALLT addr5 instruction is executed This instruction references an address stored in the memory table between 40H through 7FH and can be used to branch to any location in the memory Operation 7 6 5 1 0 15 8 7 6 5 10 Effective address 0 00 0 0 0 0 0 0 IO ol 7 Memory table 0 Low addr Effective address 1 High addr 15 8 7 0 PC 113 CHAPTER 5 CPU ARCHITECTURE 5 3 4 Register addressing Function The contents of the register pair AX specified by an instruction word are transferred to the program counter PC and program execution branches This addressing is used when the BR AX instruction is executed Operation 114 CHAPTER 5 CPU ARCHITECTURE 5 4 Addressing of Operand Address 5 4 1 Data memory addressing The method of specifying the address of the instruction to be executed next or the address of the register or memory to be manipulated when an instruction is executed is called addressing The address of the instruction to be executed next is specified by the program counter PC for details refer to 5 3 Addressing Instruction Address To address the memory to be manipulated when an instruction is executed the uwPD78018F and 78018FY subseries have many addressing modes to improve the operability In particular the area assigned as the data memory can be addressed using special addressing modes in accordance with the functions of the are
251. d write strobe wait and address strobe signals Table 19 1 Pin Functions in External Memory Extension Mode Pin Function when External Device is Connected Name ADO AD7 Function Multiplexed address data bus Shared by P40 P47 A8 A15 Address bus P50 P57 RD Read strobe signal P64 WR Write strobe signal P65 Wait signal P66 Address strobe signal P67 Table 19 2 Status of Ports 4 6 in External Memory Extension Mode External Extension Mode Single chip mode 256B extension mode Address data 4KB extension mode Address data Address 16KB extension mode Address data Address Full address mode Address data Address Caution When the external wait function is not used the WAIT pin can be used as a port pin in all the modes 425 CHAPTER 19 EXTERNAL DEVICE EXTENSION FUNCTION The memory map is as follows when the external device extension function is used Figure 19 1 Memory Map when External Device Extension Function Is Used 1 4 a Memory map of PD78011F 78011FY and b Memory map of PD78012F 78012FY and LPD78P018F 78P018FY with 8 KB internal PROM HPD78P018F 78P018FY with 16 KB internal PROM FFFFH FFFFH FFOOH FFOOH FEFFH FEFFH Internal high speed RAM Internal high speed RAM FDOOH FDOOH FCFFH FCFFH Reserved Reserved FAEOH FAEOH FADFH FADFH Internal buff
252. dance state therefore itis not necessary to write FFH to SIOO before reception 295 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 uPD78018F SUBSERIER 6 7 8 296 Method of detecting address matching In the SBIC mode a specific slave device can be selected when the master transmits a slave address Whether the slave address output by the master coincides with the value of the slave address register SVA of a slave is automatically detected by hardware When the wake up function specification bit WUP is 1 and only if the slave address transmitted by the master coincides with the address set to the SVA CSIIFO is set If bit 5 SIC of the interrupt timing specification register is set to 1 the wake up function does not operate even if WUP is set to 1 an interrupt request signal is generated on detection of bus release Clear SIC to 0 to use the wake up function Cautions 1 Whether a slave is selected or not is detected by matching of a slave address that has been received after the bus release signal has been issued RELD 1 To detect matching of addresses an address maich interrupt INTCSIO that is generated when WUP 1 is usually used Therefore check whether a slave device is selected or not by reception of a slave address when WUP 1 2 To detect whether a slave is selected or not when WUP 0 without using the interrupt do so by transmitting receiving a command set by program in advance instead of using
253. dded functions to configure the bus When organizing a serial bus with several microcomputers and peripheral ICs therefore the number of ports and wiring length on the printed wiring board can be reduced The master can output a start condition data and stop condition to slaves on the serial data bus Aslave receives and automatically detects these data by hardware This function simplifies the application program that controls the 12C bus Figure 16 12 shows an example of serial bus configuration by using CPUs or peripheral ICs having a serial interface conforming to the I2C bus Because the serial clock pin SCL and serial data bus pin SDAO or SDA1 are N ch open drain output pins in the 12C bus pull up resistors must be connected to the serial clock line and serial data bus line Table 16 5 describes the signals used in the 12C bus mode Figure 16 12 Example of Serial Bus Configuration in 12C Bus Mode Voo Voo Master CPU t Slave CPU1 sc Serial clock E Jael sbao SDA1 2918 data bus gt SDAO SDA1 Slave CPU2 Slave IC SCL SDAO 333 al UNO CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78018FY SUBSERI7 1 Functions in the 12C bus mode The following functions are available in the 12C bus mode a Automatic identification of serial data The start condition data and stop condition on the serial data bus are automatically detec
254. ddressing the program branches in the range 128 to 127 relative to the first address of the next instruction This addressing is used when BR addr16 instruction or conditional branch instruction is executed Operation o 15 yl PC holds first address of instruction disp8 09 A When S 0 all bits of a are 0 When S 1 all bits of a are 1 o 111 i rir lv ed i mar lu ed CHAPTER 5 CPU ARCHITECTURE 5 3 2 Immediate addressing Function The immediate data in an instruction word is transferred to the program counter PC and execution branches This addressing is used when the CALL addr16 BR addr16 or CALLF addr11 instruction is executed The CALL addr16 BR addr16 instructions can be used to branch to any location in the memory The CALLF laddr11 instruction is used to branch to the area between 0800H through OFFFH Operation When CALL addr16 or BR addr16 instruction is executed 7 0 CALL or BR Low addr High addr 15 87 0 PC When CALLF addr11 instruction is executed 112 CHAPTER 5 CPU ARCHITECTURE 5 3 3 Table indirect addressing Function The contents of a specific location table branch destination address addressed by the immediate data of bits 1 to 5 of an instruction code are transferred to the program counter PC and program execution branches This addressing is use
255. de P25 CMOS 1 0 SB1 N ch open drain I O SBO N ch open drain I O P26 CMOS 1 0 Generates interrupt request signal in all modes each time serial transfer is executed SCKO N ch open drain I O Generates interrupt request signal when address received after bus has been released in SBI mode when CMDD RELD 1 coincides with data of slave address register Data of slave address register SVA does not coincide with data of serial I O shift register 0 S100 Data of slave address register SVA coincides with data of serial I O shift register 0 SIOO Stops operation Enables operation Notes 1 Bit 6 COI is a read only bit 2 This pin can be used freely as a port pin 3 Be sure to set WUP to 0 in the 2 wire serial I O mode 4 COl is 0 when CSIEO 0 Remark x Don t care PMxx Port mode register Pxx Output latch of port i Wi red CHAPTER 15 SERIAL INTERFACE CHANNEL 0 uPD78018F SUS b Serial bus interface control register SBIC SBIC is set by a 1 bit or 8 bit memory manipulation instruction This register is set to OOH when the RESET signal is input Symbol lt 7 lt 6 gt lt 5 gt lt 4 gt lt 3 gt lt 2 gt lt gt lt 0 gt Address Onreset R W SBIC BSYE ACKD ACKE Serr D RELD CMDT RELT FF61H 00H R W R W SO0 latch is set to 1 when RELT 1 After setting SOO latch RELT is automatically cleared to 0 This bit is also cleared
256. disp8 signed 8 bit data displacement value 24 1 3 Description in flag operation column Blank not affected cleared to 0 set to 1 set cleared according to result yxX 30 value saved before is restored 479 CHAPTER 24 INSTRUCTION SET 24 2 Operation List Instruction y Clock l Slade Mnemonic Operand Operation Note 1 Note 2 8 bit data r byte transfer sadar byte r lt byte saddr lt byte wj Pp sfr byte A r nA sfr byte Aer rcoA A saddr A lt saddr saddr A A sfr saddr A A lt sfr sfr A sfr A A laddr16 laddr16 A A lt addr16 addr16 A PSW byte A PSW PSW A PSW lt byte A lt PSW PSW lt A Ni injo0o o0o 0O N N N Nn A DE A lt DE DE A DE A A HL A lt HL HL A HL A A HL byte A HL byte HL byte A HL byte A A HL B A lt HL B HL B A HL B A A HL C A lt HL C HL C A HL C cA Notes 1 When the internal high speed RAM area is accessed or when an instruction that does not access data is executed 2 When an area other than the internal high speed RAM area is accessed 3 Exceptr A Remarks 1 One clock of an instruction is equal to one CPU clock fcru selected by processor clock control register PCC 2 The number of clocks sh
257. dress An address is an 8 bit data which the master outputs to the slaves connected to the bus lines in order to select a specific slave Figure 15 13 Address SCKO 1 2 3 4 5 6 7 8 SBO SB1 ad Address Bus release signal Command signal The 8 bit data that follows the bus release signal and command signal is defined as an address The slave detects this condition by hardware and checks by hardware whether the 8 bit data matches the identification number of the slave itself slave address If the 8 bit data matches the slave address of aslave that slave is selected After that the slave communicates with the master until it is later directed to be disconnected from the master Figure 15 14 Selecting Slave by Address etc slave 2 sme Selected saves Not selected saves Not selected 281 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 uPD78018F SUBSERIE 282 d Command and data The master transmits commands or transmits receives data to the slave it has selected by transmitting an address Figure 15 15 Command SCKO 1f lef la laf 15 lef 171 l8 SBO SB1 Ne Command signal Command Figure 15 16 Data SCKO 1 l2 ls laf 5 lef l7 le SB0 S81 To Xba Xos Ks XOX 2 Di o Data The 8 bit data following the command signal is defined as acommand The 8 bit data that does not follow the command signal is defined as data The method of using the command and data can be arbitrarily d
258. e INTP1 INTP3 Input only XT1 P10 P17 Port 1 8 bit I O port Can be specified for input output bitwise When used as input port internal pull up resistor can be connected by software Note 2 ANIO ANI7 Notes 1 Port 2 8 bit I O port Can be specified for input output bitwise When used as input port internal pull up resistor can be connected by software SI0 SBO SDAO SO0 SB1 SDA1 SCKO0 SCL To use the P04 XT1 pin as an input port line set the bit 6 FRC of the processor clock control register PCC to 1 do not use the internal feedback resistor of the subsystem clock oscillation circuit 2 When using the P10 ANIO through P17 ANI7 pins as the analog input lines of the A D converter set port 1 to input mode The internal pull up resistors are automatically disconnected 79 CHAPTER 4 PIN FUNCTIONS uPD78018FY SUBSERIES 1 Port pins 2 2 Pin Name Function On Reset Shared by P30 Port 3 Input TOO P31 8 bit I O port 101 Can be specified for input output bitwise When used as input port internal pull up resistor can be connected TO2 P33 by software TH P34 Tl2 P35 PCL P36 BUZ P37 P40 P47 Port 4 ADO AD7 8 bit I O port Can be specified for input output in 8 bit units When used as input port internal pull up resistor can be connected by software Test input flag KRIF is set to 1 at falling edge of these pins P32 P50 P57 Port 5
259. e e C library source file e Device file PROM Writing Tool PG 1500 controller Embedded Software Real time OS OS Host Machine PC Interface adapter PC card interface etc PROM Writing In circuit Emulator Environment PROM programmer Emulation board Programmer adapter a Emulation probe PROM contained model Power supply unit Conversion socket or conversion adapter Target system 496 APPENDIX B DEVELOPMENT TOOLS Figure B 1 Development Tool Configuration 2 2 2 When using the in circuit emulator IE 78001 R A Language Processing Software Debugging Tool e System simulator Integrated debugger Device file Assembler package e C compller package e C library source file al Device file PROM Writing Tool e PG 1500 controller Embedded Software e Real time OS OS Host Machine PC or EWS Interface board PROM Writing In circuit Emulator Environment Interface adapter PROM programmer i Programmer adapter PROM contained model Emulation probe Conversion socket or conversion adapter Target system Remark Items in broken line boxes differ according to the development environment Refer to B 3 1 Hardware 497 APPENDIX B DEVELOPMENT TOOLS B 1 Language Processing Software RA78K 0 Assembler Package This assemb
260. e 2 x CSIM SIE1 PM20 P20 PM21 P21 PM22 P22 11 Note 2 x Shift register 1 operation Operation disabled count operation control 11 P20 pin function P20 CMOS 1 0 SO1 P21 pin function P21 CMOS 1 0 SCK1 P22 pin function P22 CMOS 1 0 Note 3 4 Notes 1 Note 3 x Operation enabled Count operation S 1Note 3 input so1 CMOS output of the automatic data transmit receive control register ADTC to 0 0 N These pins can be used freely as port pins SCK1 input SCK1 CMOS output When external clock input is selected by setting CSIM11 to 0 set bit 1 BUSY1 and bit 2 STRB 3 When data is only transmitted this pin can be used as P20 CMOS I O set bit 7 RE of ADTC to 0 Remark x PMxx Port mode register Pxx 364 Don t care Output latch of port CHAPTER 17 SERIAL INTERFACE CHANNEL 1 3 Automatic data transmit receive control register ADTC This register enables disables reception of automatic transmission reception operation mode strobe output busy input and error check and indicates execution of automatic transmission reception and error detection ADTC is set by a 1 bit or 8 bit memory manipulation instruction The contents of this register are reset to OOH when the RESET signal is input 365 CHAPTER 17 SERIAL INTERFACE CHANNEL 1 Figure 17 4 Format of Aut
261. e 21 4 Reset Timing by RESET Input in STOP Mode er A IES STOP instruction execution Reset period Oscillation During normal operation ia E oscillation stabilization During normal operation Normal operation reset processing y stops i time wait 1 RESET ql J I S I Internal l reset signal i l f Delay Delay i gt Hi Z RS E ais Sais 450 CHAPTER 21 RESET FUNCTION Table 21 1 Status of Each Hardware after Reset 1 2 Hardware Status after Reset Program counter PC Note 1 Contents of reset vector table OOOOH 0001H are set Stack pointer SP Undefined Program status word PSW 02H RAM Data memory UndefinedNote 2 General purpose register UndefinedNote 2 Port output latch Ports 0 3 PO P3 00H Ports 4 6 P4 P6 Undefined Port mode register PMO 1FH PM1 PM2 PM3 PM5 PM6 FFH Pull up resistor option register PUO 00H Processor clock control register PCC 04H Memory extension mode register MM 10H Memory size select register IMS Note 3 Internal extension RAM size select register IXS Note 3 Oscillation stabilization time select register OSTS 04H 16 bit timer event counter Timer register TMO 0000H Compare register CROO Undefined Capture register CR01 Undefined Clock select register TCLO 00H Mode control register TMCO 00H Output control register TOCO 00H 8
262. e SS X2 X2 Se Sa ee IC ena yi ee HPD74HCU04 or ceramic resonator Caution Do not execute the STOP instruction and do not set MCC bit 7 of the processor clock control register PCC to 1 when the external clock is input Otherwise operation of the main system clock is stopped and the X2 pin is pulled up by Vob 7 4 2 Subsystem clock oscillation circuit The subsystem clock oscillation circuit is oscillated by the crystal resonator connected across the XT1 and XT2 pins 32 768 kHz TYP An external clock can also be input to the circuit In this case input the clock signal to the XT1 pin and input the reversed signal to the XT2 pin Figure 7 5 shows the external circuit of the subsystem clock oscillation circuit Figure 7 5 External Circuit of Subsystem Clock Oscillation Circuit a Crystal oscillation b External clock eer IC XT2 i T XT2 32 768 T kHz XT1 External XTi Ce egy clock HPD74HCU04 Refer to Cautions on the following pages 162 CHAPTER 7 CLOCK GENERATION CIRCUIT Caution 1 When using the main system clock or subsystem clock oscillator circuit to avoid influence of wiring capacity etc wire the portion enclosed by dotted line in Figures 7 4 and 7 5 as follows Keep the wiring length as short as possible Do not cross the wiring with any other signal lines Do not route the wiring in the vicinity of a line through which a high alternating current flow
263. e Signal SCKO HY SBO SB1 f The bus release signal indicates that the master is to transmit an address to the slave The slave is provided with hardware that detects the bus release signal Caution A positive transition of the SBO SB1 pin from low to high is recognized as a bus release signal when the SCKO line is high If the change timing of the bus is shifted due to the influence of the board capacitance data that is transmitted may be identified as bus release signal by mistake Exercise care in wiring b Command signal CMD The command signal is the negative transition signal of the SBO SB1 line i e transition from the high to low level when the SCKO line is high when the serial clock is not output This signal is output by the master Figure 15 12 Command Signal The command signal indicates that the master is going to transmit a command to the slave however the command signal following the bus release signal indicates that an address is to be transmitted The slave is provided with hardware that detects the command signal Caution A positive transition of the SBO SB1 pin from high to low is recognized as a command signal when the SCKO line is high If the change timing of the bus is shifted due to the influence of the board capacitance data that is transmitted may be identified as command signal by mistake Exercise care in wiring 280 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 uPD78018F SUS c Ad
264. e Stalt nnocnncinnccnncinnncnnncncncccnncncancnnnnncnn nr rca 254 14 7 A D Conversion by Software Start onnicnccinnicincinnnccnncnnocncnnnncan cn non nconnn narran 255 14 8 Example of Reducing Current Consumption in Standby Mode ceccceeceeeeesseeeeteeeeees 256 14 9 Processing Analog Input Pin oooocconnncccnnonccononnnononcnonnnnncnnnr cnn non cnn nano nr ran rre 257 14 10 A D Conversion End Interrupt Generation Timing ooocnncinncnnncinnncnnnccnnncanancnarncnnrnnanccrncnn 258 14 11 Processing of AVob PInit ici fat Ah ee ee a i A AA 258 15 1 Block Diagram of Serial Interface Channel O 00 eeeeeceseeeeeeeeeeeeeeeeeeeeteeeeeeeseaeeseeeeenenaaee 262 15 2 Format of Timer Clock Select Register 3 ecceeceeeeeeeeeeeeeeeeeeseeeeeeeeeeeeeaeeseeeeeneeteneeeaees 266 26 LIST OF FIGURES 4 7 Figure No Title Page 15 3 Format of Serial Operation Mode Register 0 ccceecsesceeeeeeeeeeseeeeeeeeeseeeeaeeeeeeteeeeeeeeenees 267 15 4 Format of Serial Bus Interface Control Register cecceeeceeeeeeeeeeeeeeeeeeeeeeeeeteeeeeneteeess 268 15 5 Format of Interrupt Timing Specification Register 0 0 ec eeceeeeeeeeeeeeeeneeeeeeeeeeeeeaeeeeeeeeaeees 270 15 6 Timing of 3 Wire Serial I O MOde ccccesceeeesceeeesceeeeeeeeeseaeeeseeneceeseeeeseneeseneaeeessneeessineeess 274 15 7 Operations of RELT and CMDT suicide di 275 15 8 Transfer Bit Sequence Select Circuit cee eceeeeeeeneeceeeeeeeeseeeeeseeeeaeeeaees
265. e interrupt request that has released the standby mode is accepted 2 The wait time is as follows e When vectored interrupt processing is performed 16 5 to 17 5 clocks e When vectored interrupt processing is not performed 4 5 to 5 5 clocks b Releasing by non maskable interrupt request The HALT mode is released by a non maskable interrupt request regardless of whether the interrupt request is enabled or disabled and vectored interrupt processing is performed c Releasing by unmasked test input The HALT mode is released by an unmasked test signal input and the instruction at the address next to that of the HALT instruction is executed 443 CHAPTER 20 STANDBY FUNCTION d Releasing by RESET input The HALT mode is released by the RESET signal input and execution branches to the reset vector address in the same manner as the ordinary reset operation and program execution is started Figure 20 3 Releasing HALT Mode by RESET Input HALT instruction Wait 218 fx 26 2ms e gt RESET signal Oscillation Operation Reset stabilization Operation mode HALT mode period wait status mode gt a gt a Oscillation Clock Oscillation Ne stops a Oscillation Remarks 1 fx Main system clock oscillation frequency 2 At fx 10 0 MHz operation Table 20 2 Operation after Release of HALT Mode Releasing Source MKxx Operation Maskable interrupt request Executes next address instruction E
266. e pins selected for analog input by A D converter input select register ADIS can be used as I O ports Cautions 1 Observe the specified input voltage range of ANIO ANI7 If a voltage of AVrer or higher or AVss or lower even within the range of absolute maximum ratings is applied to a channel the converted value of that channel becomes undefined or the converted value of the other channels may be affected 2 The analog input pins ANIO ANI7 are also used as I O port pins port 1 When A D conversion is performed with any of ANIO ANI7 selected do not execute the input instruction for port 1 while conversion is in progress otherwise the conversion reso lution may be degraded If a digital pulse is applied to the pins adjacent to the pins currently used for A D conversion the expected value of the A D conversion may not be obtained due to coupling noise Therefore do not apply a pulse to the adjacent pins to the pin under A D conversion 247 i rN a lu ed al UNO CHAPTER 14 A D CONVERTER 7 AVrer pin This pin inputs a reference voltage to the A D converter Based on the voltage applied between AVrer and AVss the signal input to ANIO ANI7 is converted into a digital signal Inthe standby mode the current flowing through the series resistor string can be reduced by inputting a voltage of AVss level to the AVrer pin Caution A series resistor string of about 10 kQ is connected between the AVrer and AVss pins
267. e select register IXS External memory extension space 64 KB Variable minimum instruction execution time from high speed 0 4 us with 10 0 MHz main system clock to ultra slow 122 us with 32 768 kHz subsystem clock e Instruction set suitable for system control Bit processing in entire address space Multiplication division instructions e I O port 53 lines N ch open drain 4 lines e 8 bit resolution A D converter 8 channels Low voltage operation AVop 1 8 to 5 5 V operable in supply voltage range same as that of the CPU e Serial interface 2 channels 3 wire serial I O 2 wire serial I O 12C bus mode 1 channel 3 wire serial I O mode with automatic transmit receive function 1 channel Timer 5 channels 16 bit timer event counter 1 channel 8 bit timer event counter 2 channels Watch timer 1 channel Watchdog timer 1 channel e Vectored interrupt source 14 lines e Test input 2 lines e Two types of clock oscillation circuits main system clock and subsystem clock Supply voltage Voo 1 8 to 5 5 V 53 CHAPTER 2 GENERAL 1 PD78018FY SUBSERIES 2 2 Application Field Telephones VCRs audio sets cameras home appliances etc 2 3 Ordering Information Part Number Package Internal ROM HPD78011FYCW XXX 64 pin plastic shrink DIP 750 mil Mask ROM uPD78011FYGC XXX AB8 64 pin plastic QFP 14 x 14 mm Mask ROM uPD78011FYGK XXX 8A8 64 pin plastic LQFP 12 x 12 mm Mask ROM uPD7
268. eaeeeeeseeeeeeeeeaeees 275 15 9 Example of Serial Bus Configuration by SBI o eceeceeeeeeeeeeeeeeeeeeeeeeeeeeseaeeeeeeteaeeeeeeeeaees 277 15 10 SBI Transfer Timing s 8 0c awtag acute etal pe hat aa enacted 279 15 11 Bus Release Signal ARET STE heck sepsis acdc eae decdecaban cpas nant ET 280 15 12 Command Signaliciiectas a is eee ee 280 15 13 Adm id meee dada 281 15 14 Selecting Slave by Address oooconcocincccocccnonnnonnnconcnnoncnoncnnnn ccoo nono ncnn anna cnn nr nn cn nnn cnn nc nana ncnncnns 281 15 15 COMNM Muir a ihe inde Me eh ie apie eee 282 15 16 Dita ii ad naractihieee iat einai adhe ata 282 15 17 Acknowl dge Signal viciosa 283 15 18 Busy Signal and Ready Signal ccccecceeseeeeeeeeneeeeeeeeeeeseeeeeeeseaeeseeeeaeesieeseaeesseeesieeseeeeeaes 284 15 19 Operations of RELT CMDT RELD and CMDD Master ceeceeseeeeeeeeereeeeeeeeeeseeees 289 15 20 Operations of RELD and CMDD Slave cceeccecceeeceeeeeeeeeeeeeeeceaeeeeeeeeeeeseeeeaeeseeeeeeeenaeeeas 289 15 21 Operation ol ACK E Soustaides ben te t5hiescibanacdehstabecaadesaecssdiguase ceeds E sash ited 290 15 22 peration Of ACKE 20 Seth ees ete hes aghast nods Laos chat ete 291 15 23 Operation oMACKD in dct hearths e ooh e A Sete ater ter e assets ibe tects os 292 15 24 Operation of BS Ei ee Shed e eek Ae alee eel ae ae 292 15 25 Pin Configuration art e OE Ea A Ee EE 295 15 26 Address Transmit Operation from Master Device to Slave Device WUP 1 nasse
269. eased after reset and program execution is started after the oscillation stabilization time 2 8 fx has elapsed refer to Figures 21 2 through 21 4 Cautions 1 Input a low level signal to the RESET pin for 10 us or longer to execute external reset 2 Oscillation of the main system clock is stopped while the RESET signal is input Oscillation of the subsystem clock is not stopped but continues 3 To release the STOP mode by the RESET input the contents in the STOP mode are retained while the RESET signal is input However the port pins go into a high impedance state RESET Figure 21 1 Block Diagram of Reset Function Reset 2 Reset control circuit signal Interrupt Count clock Overflow gt Watchdog timer l Stops function 449 CHAPTER 21 RESET FUNCTION Figure 21 2 Reset Timing by RESET Input PIM Oscillation i R ri Peon Normal ration During normal Lo eset period 2d stabilization ormal operatio operation oscillation stops time wait reset processing l RESET A A Internal reset signal l i i gt Hi Z O E aS Figure 21 3 Reset Timing by Overflow in Watchdog Timer TAO ___ ae E Oscillation _ Reset period H stabilization Normal operation oscillation stops time wait reset processing i Overflow in watchdog timer i i Internal i l reset signal i i gt Hi Z POPIN a a a aac Figur
270. eceive Interval Specification Register 2 2 Symbol 7 6 Address On reset R W 5 4 3 2 1 0 ADTI ADTI7 EJES ADTI4 ADTI3 ADTI2 ADTI1 ADTIO FF6BH 00H R W ADTI3 ADTI1 Specifies interval time for data transfer fx 10 0 MHz operation Minimum value ote Maximum valueNote 223 2 us 0 5 fsck 224 8 us 1 5 fsck 236 0 us 0 5 fsck 237 6 us 1 5 fsck 248 8 us 0 5 fsck 250 4 us 1 5 fsck 261 6 us 0 5 fsck 263 2 us 1 5 fsck 274 4 us 0 5 fsck 276 0 us 1 5 fsck 287 2 us 0 5 fsck 288 8 us 1 5 fsck 300 0 us 0 5 fsck 301 6 us 1 5 fsck o 1 o o o o o o o 312 8 us 0 5 fsck 314 4 us 1 5 fsck 325 6 us 0 5 fsck 327 2 us 1 5 fsck 338 4 us 0 5 fsck 340 0 us 1 5 fsck 351 2 us 0 5 fsck 352 8 us 1 5 fsck 364 0 us 0 5 fsck 365 6 us 1 5 fsck 376 8 us 0 5 fsck 378 4 us 1 5 fsck 389 6 us 0 5 fsck 391 2 us 1 5 fsck 402 4 us 0 5 fsck 404 0 us 1 5 fsck 415 2 us 0 5 fsck 416 8 us 1 5 fsck Note The interval time for data transfer is variable The minimum and maximum values of the interval time for transferring each data can be calculated by the following expressions n value placed in ADTIO through ADTI4 If the minimum value calculated by the following expression is less than 2 fsck however the minimum interval time is assumed to be 2 fsck 7 Minimum value n 1 x oie 28 g 0S fx fx fsck 7
271. ected 71 al UNO CHAPTER 3 PIN FUNCTIONS uPD78018F SUBSERIES 3 2 3 P20 P27 Port2 These pins constitute an 8 bit I O port port 2 In addition these pins are also used to input output the data of the serial interface input output a clock signal input a busy signal used for automatic transmission reception and output a strobe signal Port 2 can be specified in the following operation modes in 1 bit units 1 2 72 Port mode In the port mode P20 and P27 function as an 8 bit I O port Port 2 can be set in the input or output mode in 1 bit units by using the port mode register 2 PM2 When the port is used as an input port an internal pull up resistor can be used if so specified by the pull up resistor option register PUO Control mode In this mode P20 through P27 input output the data of the serial interface input output a clock input a busy signal for automatic transmission reception and output a strobe signal a SIO SI1 SOO SO1 These are the serial data I O pins of the serial interface b SCKO SCK1 These are serial clock I O pins of the serial interface c SBO SB1 These are I O pins of the NEC standard serial bus interface d BUSY This pin inputs the busy signal for the automatic transmit receive function of the serial interface e STB This pin outputs a strobe signal for the automatic transmit receive function of the serial interface Caution When using P20 through
272. ed CHAPTER 15 SERIAL INTERFACE CHANNEL 0 uPD78018F SUS 2 Definition of SBI This section describes the serial data format of SBI and the meaning of used data The serial data transferred by SBI are classified into addresses commands and data Figure 15 10 shows the transfer timing of the address command and data Figure 15 10 SBI Transfer Timing Address transfer BUSY SB0 SB1 Bus release y signal Address Command transfer Command signal SCKO PILI LILI LI LIL le LILI LI 80 S81 aX K AOX Ko ac susy reno Command Data transfer SCKO PLE LI LILI LS Li del del LILI LIL SBO SB1 WA Ko ack susy reaow Data Remark The dotted line indicates the READY status The bus release signal and command signal are output by the master BUSY is output by the slave ACK can be output by both the master and slave usually this signal is output by the 8 bit data reception side The master continues outputting the serial clock from the start of 8 bit data transfer until BUSY is released 279 i ri oY a lv ed CHAPTER 15 SERIAL INTERFACE CHANNEL 0 uPD78018F SUBSERIER a Bus release signal REL The bus release signal is the positive transition signal of the SBO SB1 line i e transition from the low to high level when the SCKO line is high when the serial clock is not output This signal is output by the master Figure 15 11 Bus Releas
273. ed Provided resistor of P60 P63 pins Electrical characteristics and Refer to individual Data Sheet recommended soldering conditions Notes 1 The internal PROM is set to 60K bytes and internal high speed RAM is set to 1024 bytes at RESET 2 The internal extension RAM is set to 1024 bytes at RESET Caution The noise immunity and radiation differ between the PROM model and mask ROM model To replace a PROM model with a mask ROM model in the course from experimental production to mass production evaluate your system with the CS model not ES model of the mask ROM model 464 CHAPTER 23 uPD78P018F 78P018FY 23 1 Memory Size Select Register The uPD78P018F and 78P018FY are provided with a memory size select register IMS that can select the internal memory By setting IMS the memory of the wPD78P018F and 78P018FY can be mapped in the same manner as that of the mask ROM models each having a different memory capacity from those of the others To map the memory of the PD78P018F and 78P018FY in the same manner as that of a mask ROM model set the value of the mask ROM model at reset to IMS IMS of a mask ROM model need not to be set IMS is set by an 8 bit memory manipulation instruction This register is set as shown in Table 23 2 when the RESET signal is input Caution When using the mask ROM model do not set a value other than the value at reset shown in Table 23 2 to IMS except when the external device extension fu
274. ed addressing Based indexed addressing CHAPTER 5 CPU ARCHITECTURE FFFFH A A Special function registers SFRs i 256 x 8 bits SFR addressing O A E E EEEN E AN FF1FH A FFOOH Y FEFFH A General purpose registers A 32 x 8 bits Register addressing Short direct FEEOH Y addressing FEDFH Internal high speed RAM 1024 x 8 bits A TA O Y FBOOH Direct addressing FAFFH Reserved Register indirect FAEOH addressing FADFH Internal buffer RAM i Based addressin FACOH 32 x 8 bits g SABER Reserved Based indexed F800H addressing F7FFH Internal extension RAM 512 x 8 bits F600H F5FFH External memory 22016 x 8 bits A000H 9FFFH Internal ROM 40960 x 8 bits 0000H Y 119 CHAPTER 5 CPU ARCHITECTURE Figure 5 20 Data Memory Addressing uPD78016F 78016FY FFFFH A A Special function registers SFRs 256 x 8 bits SFR addressing BOM O MI A Oe lle ARA FF1FH A FFOOH Y FEFFH A General purpose registers a 32 x 8 bits Register addressing Short direct FEEOH Y addressing FEDFH Internal high speed RAM 1024 x 8 bits A NS O A hata ten Y FBOOH Direct addressing FAFFH Reserved Register indirect FAEOH addressing FADFH Internal buffer RAM i Based addressin FACOH 32 x 8 bits g FABER Reserved Based indexed F800H addressing F7FFH Internal extension RAM 512 x 8 bits F600H F5FFH External memory 13824 x 8 bits C000H BFFF
275. ee 157 7 2 Relation between CPU Clock and Minimum Instruction Execution Time 161 7 3 Maximum Time Required for Switching CPU Clock 00 eceeeeeeeseeeeeeeeteeeeeeeeneeeeneeteneeeaes 170 8 1 Operations of Timer Event Counters c ccecceeeceeeneeeeeeeeneeeeeeeeaeeeeeeeeaeeseeeeaeeseeeeeeeseaeeeneene 174 8 2 Interval Time of 16 Bit Timer Event Counter ccccccccsseceseneceesneeeesneeeeeseeeecnaeeesseeesseees 175 8 3 Square Wave Output Range of 16 Bit Timer Event Counter cccceeeeeeeeteeeeenreeeeees 175 8 4 Configuration of 16 Bit Timer Event Counter ccecceeeceeeeeeeeeeseeeeeeeseeeeeeeeeeeeseeeeaeeeieeeeas 176 8 5 Interval Time of 16 Bit Timer Event Counter cccccceeseceseceeeeeeeeeeeeeeeeeseeeessaeeesneeessaeees 189 8 6 Square Wave Output Range of 16 Bit Timer Event Counter ccccceceeseeeeeeeeeenreeseees 196 9 1 Interval Time of 8 Bit Timer Event Counter cccccecescceeeseeeesneeeeeeeeeeseaeeeeceeeessseeessneeess 200 9 2 Square Wave Output Range of 8 Bit Timer Event Counter ccecccesesceeeeeteeeesteeeeees 200 9 3 Interval Time of 8 Bit Timer Event Counters Used as 16 Bit Timer Event Counter 201 9 4 Square Wave Output Range of 8 Bit Timer Event Counters Used as 16 Bit Timer Event Counter s ele a add dida 201 9 5 Configuration of 8 Bit Timer Event Counter ecceeeceeeceeeeeeeeeeeeneeeeaeeeneeeeaeeseeeeeaeeseaeeeaeenes 202 9 6 Interval Time of 8 Bit Timer
276. eeeeeeeaeeeeeeeeeeseaeeeeeee 360 17 3 Interval Time by CPU Processing with internal clock eecceeeceeeceeeeeeeeeeeeeeteeeeeneeeenees 399 17 4 Interval Time by CPU Processing with external clock eecceesceeeeeeeeeeseeeeeeeeseeeeeeeeenees 400 18 1 Interrupt SOUrC S sic nie sat a o mates 402 18 2 Flags Corresponding to Respective Interrupt Request Sources ocoocccincccnociconccioncnancconnnnnn 405 18 3 Time from Generation of Maskable Interrupt Request to Processing ccceeeeeees 415 18 4 Interrupt Requests that Can Be Nested during Interrupt Processing ccseeeeeees 418 18 5 Test Input Sources O dees sadleaa sense ET 423 32 LIST OF TABLES 3 3 Table No Title Page 18 6 Flags Corresponding to Test Input Signals eceeseesceeeneeeeeeeeeeeteeeeeaeeseaeeeaeetsaeeseeeeaees 423 19 1 Pin Functions in External Memory Extension Mode eseeesseeeeeneeeseneeeeeneeeeeneeeneneees 425 19 2 Status of Ports 4 6 in External Memory Extension Mode c ceeceeesceeeeeeeeeeseeeeeteeeneeees 425 19 3 Value of Memory Size Select Register at Reset eceeceeseeeseeeeeeeeeeeeeeeeeeeeetieeeeaeeeeeesas 431 20 1 Operation Status in HALT Mode eeececceeeseeseeteeeeseeceaeeeeeeceaeecsaeeeaeessaeeeaeeeeaeesieeteaeeeeeee 441 20 2 Operation after Release of HALT Mode oooccccccoccciocacocccoonccnnnconn non nnnnnc conc nnnnn nan nn rn ccnnnc rn 444 20 3 Operation Status in STOP Mode c coooccncccc
277. eeeneeereneeees 186 8 9 Format of Sampling Clock Select Register ccecceesceeseeceneeeeeeteneeseeeeeaeeseeeenaeeseaeeeneeeeates 187 8 10 Configuration of Interval Timer cceeceeeceeeeeeeeeeeeeeeeeeseeeeeeeseaeeeeeseaeeseeseaeeseeeteaeeseaeeeeenes 188 8 11 Interval Timer Operation Timing cccceceeeeeceseecseeeeeeeceeeeeaceeaeeeaeeeeaeeeaeeseaeeeaeeteaeeeeeeeeaees 189 8 12 Example of Configuration of D A Converter Using PWM Output cococcccnccccoccconccnnnccanccinnnons 191 8 13 Example of Application Circuit TV Tuner coccccnccnnncnnnccnonnnnncnnonc conc cnn ccn nr r acc 191 8 14 Configuration of Pulse Width Measurement by Free Running e ceeceeeeeseeeeeteeeeeeees 192 8 15 Pulse Width Measurement Timing by Free Running with both rising and falling edges specified oooonncccnnnnicononccnnnncncnncrnnnnorncnnranr rar nnnnnnnn 193 8 16 Pulse Width Measurement Timing by Restarting Timer with both rising and falling edges specified oooonncccnnnicononccnnnocncnncrnnnnornnnnnrrncrnrrnannn nn 194 8 17 Configuration of External Event Counter cecccecceeeceeeseeeeeeeeeeeceaeeeeeseeeesaeeenaeeseeseaeeeneeesas 195 8 18 External Event Counter Operation Timing with rising edge specified o occconncconnnnninsncnnmscncnnnrernne rn nncn rra 196 8 19 Square Wave Output Timing oococonccnnncconocnnoncnonnnonnccnnnnonn cana n nono nn nn nnn cnn cnn anna rancia cannccns 196 8 20 Start Timing of 16 Bi
278. efer to Figure 15 3 Format of Serial Operation Mode Register 0 and Figure 17 3 Format of Serial Operation Mode Register 1 2 To read the status of the pin in the SBI mode set PM2n bit of PM2 to 1 n 5 6 refer to 15 4 3 10 Method to judge busy state of a slave Figure 6 6 Block Diagram of P20 P21 and P23 26 uPD78018F Subseries Voo DES j T WRrorT o g P20 S11 P21 SO1 J gt l P23 STB P24 BUSY P25 SI0 SBO P26 S00 SB1 Multiplexed function PUO pull up resistor option register PM port mode register RD read signal of port 2 WR write signal of port 2 140 CHAPTER 6 PORT FUNCTIONS A n 5 a L o T 5 Output latch po 2 P22 SCK1 P22 P27 SN a ae i po7iSCKO PM22 PM27 e Multiplexed function PUO pull up resistor option register PM port mode register RD read signal of port 2 WR write signal of port 2 141 CHAPTER 6 PORT FUNCTIONS i rN a lu ed 6 2 4 Port 2 uPD78018FY subseries This is an 8 bit I O port with output latch P20 P27 pins can be specified in the input or output mode in 1 bit units by using the port mode register 2 PM2 When using P20 P27 pins as input port pins internal pull up resistors can be connected in 8 bit units by using the pull up resistor option register PUO The pins of this p
279. egister IMS internal extension RAM size select register IXS differs depending on the product as follows OBH OAH HPD78011F PD78012F wPD78013F wPD78014F uwPD78015F wPD78016F wPD78018F uPD78P018F HPD78011FY wPD78012FY oS age a ror TENER a UPD78P018FY To use a mask ROM version do not set to IMS and IXS a value other than that on reset Except however when the external device extension function is used with the wPD78018F or 78018FY 110 CHAPTER 5 CPU ARCHITECTURE 5 3 Addressing Instruction Address An instruction address is determined by the contents of the program counter PC The contents of the PC are usually automatically incremented by the number of bytes of an instruction to be fetched by 1 per byte every time an instruction is excuted When an instruction that causes program execution to branch is performed the address information of the branch destination is set to the PC by means of the following addressing for details of each instruction refer to 78K 0 Series User s Manual Instruction U12326E 5 3 1 Relative addressing Function The 8 bit immediate data displacement value jdisp8 of the instruction code is added to the first address of the next instruction the resultant sum is transferred to the program counter PC and the program branches The displacement value is treated as signed 2 s complement data 128 to 127 and bit 7 serves as a sign bit That is using relative a
280. egister PUO When the falling edge of any of the pins of this port is detected a test input flag KRIF can be set to 1 These port pins are also multiplexed with an address data bus that is used in the external memory extension mode This port is set in the input mode when the RESET signal is input Figure 6 11 shows the block diagram of port 4 and Figure 6 12 shows the block diagram of the falling edge detection circuit Figure 6 11 Block Diagram of P40 P47 o 3 a oO c o 2 Output latch P40 P47 Vo wigs DE A ________ P40 ADO P47 AD7 PUO pull up resistor option register MM memory extension mode register RD read signal of port 4 WR write signal of port 4 Figure 6 12 Block Diagram of Falling Edge Detection Circuit P40 4 P41 O P42 P43 O gt KRIF set signal P44 P45 O P46 _ P47 Falling edge detection circuit Standby release signal 145 CHAPTER 6 PORT FUNCTIONS i ar lu ed 6 2 7 Port 5 This is an 8 bit I O port with output latch P50 P57 pins can be specified in the input or output mode in 1 bit units by using the port mode register 5 PM5 When using P50 P57 pins as input port pins internal pull up resistors can be connected in 8 bit units by using the pull up resistor option register PUO Port 5 can directly drive a
281. en the RESET signal is input Caution Set data to these registers when the two 8 bit timer event counters are used as a 16 bit timer event counter after stopping the operation of the timer 8 bit timer registers 1 and 2 TM1 and TM2 These 8 bit registers count the number of count pulses When TM1 and TM2 are used individually the value of each timer register can be read by an 8 bit memory manipulation instruction When the two timer registers are used in combination as a 16 bit timer the value of the 16 bit timer register TMS can be read by a 16 bit memory manipulation instruction These registers are initialized to OOH when the RESET signal is input 205 al UNO i TAA Y ed CHAPTER 9 8 BIT TIMER EVENT COUNTER 9 3 Registers Controlling 8 Bit Timer Event Counter The following four types of registers control the 8 bit timer event counters Timer clock select register 1 TCL1 8 bit timer mode control register TMC1 8 bit timer output control register TOC1 Port mode register 3 PM3 1 Timer clock select register 1 TCL1 This register sets the count clocks of the 8 bit timer registers 1 and 2 TCL1 is set by an 8 bit memory manipulation instruction This register is set to OOH when the RESET signal is input 206 CHAPTER 9 8 BIT TIMER EVENT COUNTER Figure 9 4 Format of Timer Clock Select Register 1 Symbol 7 6 5 4 3 2 1 0 Address On reset R W TCL1 JTCL17 TCL16 TCL15 TCL14 TCL13
282. en using P20 through P27 as serial interface pins the input output mode and output latch must be set according to the functions to be used For the details of the setting refer to Figure 16 3 Format of Serial Operation Mode Register 0 and Figure 17 3 Format of Serial Operation Mode Register 1 CHAPTER 4 PIN FUNCTIONS uPD78018FY SUBSERIE 4 2 4 P30 P37 Port3 These pins constitute an 8 bit I O port port 3 In addition they also functions as timer I O clock output and buzzer output pins Port 3 can be set in the following operation modes in 1 bit units 1 Port mode In this mode port 3 functions as an 8 bit I O port which can be set in the input or output mode in 1 bit units by using the port mode register 3 PM3 When used as an input port an internal pull up resistor can be used if so specified by the pull up resistor option register PUO 2 Control mode In this mode the pins of port 3 can be used as timer I O clock output and buzzer output pins a TH TI2 These pins input an external count clock to the 8 bit timer event counter b TOO TO2 Timer output pins c PCL Clock output pin d BUZ Buzzer output pin 4 2 5 P40 P47 Port4 These pins form an 8 bit I O port port 4 In addition they also form an address data bus When the falling edge of these pins is detected the test input flag KRIF can be set to 1 This port can be set in the following operation modes in 8 bit units 1 Port mode
283. er RAM Internal buffer RAM FACOH FACOH FABFH FABFH Reserved Reserved FA80H FA80H FA7FH FA7FH Full address mode Full address mode when MM2 MMO 111 when MM2 MMO 111 8000H 7FFFH 6000H 16KB extension mode SFFFH when MM2 MMO 101 16KB extension mode when MM2 MMO 101 5000H 4FFFH 4KB extension mode ei when MM2 MM0 100 4100H 4KB extension mode 40FFH when MM2 MMO 100 256B extension mode when MM2 MMO 011 2100H 4000H FFFH a 256B extension mode 9 ee when MM2 MMO 011 1FFFH Single chip mode Single chip mode 0000H 0000H 426 CHAPTER 19 EXTERNAL DEVICE EXTENSION FUNCTI Figure 19 1 Memory Map when External Device Extension Function Is Used 2 4 c Memory map of uPD78013F 78013FY and UPD78P018F 78P018FY with 24 KB internal PROM FFFFH FFOOH FEFFH Internal high speed RAM FBOOH FAFFH Reserved FAEOH FADFH Internal buffer RAM FACOH FABFH Reserved FA80H FA7FH Full address mode when MM2 MMO 111 A000H 9FFFH 16KB extension mode when MM2 MMO 101 7000H 6FFFH 4KB extension mode when MM2 MMO 100 6100H 60FFH 256B extension mode when MM2 MMO 011 6000H 5FFFH Single chip mode 0000H FFFFH FFOOH FEFFH FBOOH FAFFH FAEOH FADFH FACOH FABFH FA80H FA7FH CO00H BFFFH 9000H 8FFFH 8100H 80FFH 8000H 7FFFH 0000H d Memory map of uPD78014F 78014FY and LPD78P0
284. erial clocks are active it is assumed that a bit shift has occurred and error processing is executed by setting bit 4 ERR of the automatic transmit receive control register ADTC to 1 Figure 17 22 shows the operation timing of the bit shift detection function by the busy signal Figure 17 22 Operation Timing of Bit Shift Detection Function by Busy Signal when BUSYO 1 SCK1 master SCK1 slave SO a CSIIF1 CSIE1 ERR CSIIF1 CSIE1 ERR T hs 1 al Bit shift due to noise XD7XD6XD5XD4XD3XD2XD1XDO _ XO7K O7XDeXDSKD4XDsXO2X01K D0_ DIODADVA A PALA E Error interrupt request generated ES Error detected Interrupt request flag Bit 7 of serial operation mode register1 CSIM1 Bit 4 of automatic data transmit receive control register ADTC 397 al UNO CHAPTER 17 SERIAL INTERFACE CHANNEL 1 5 Interval time of automatic transmission reception When using the automatic transmit receive function an interval time elapses after 1 byte has been transmitted or received until the next transmission reception is executed because data is written to or read from the buffer RAM To use the automatic transmit receive function with the internal clock the interval time is dependent on the CPU processing of the timing of the eighth rising of the serial clock and the set value of the automatic data transmit receive interval specification register ADTI Whether the inter
285. ero flag Z This flag is set to 1 when the result of an operation performed is zero otherwise it is reset to 0 102 al UNO i ri oY a lv ed CHAPTER 5 CPU ARCHITECTURE 3 c d e f Register bank select flags RBSO and RBS1 These 2 bit flags select one of the four register banks Information of 2 bits that indicate the register bank selected by execution of the SEL RBn instruction is stored in these flags Auxiliary carry flag AC This flag is set to 1 when a carry occurs from bit 3 or a borrow to bit 3 occurs as a result of an operation performed otherwise it is reset to 0 In service priority flag ISP This flag controls the priority of maskable vectored interrupts that can be acknowledged When ISP 0 the vectored interrupt which is assigned a low priority by the priority specification flag registers PROL and PROH refer to 18 3 3 Priority specification flag registers PROL PROH should not be accepted Whether the interrupt is actually accepted is controlled by the status of the interrupt enable flag IE Carry flag CY This flag records an overflow or underflow that occurs as the result of executing an add or subtract instruction It also records the value shifted out when a rotate instruction is executed In addition it also functions as a bit accumulator when a bit operation instruction is executed Stack pointer SP This is a 16 bit register that holds the first
286. erval Time Maximum Interval Time Resolution TI2 input cycle 28 x TI2 input cycle TI2 input edge cycle Tl2 input cycle 28 x TI2 input cycle Tl2 input edge cycle 22 x 1 1x 400 ns 210 x 1 fx 102 4 us 22 x 1 1x 400 ns 23 x 1 fx 800 ns 24 x 1 tx 1 6 us 212 x 1 fx 409 6 us 211 x 1 fx 204 8 us 23 x 1 fx 800 ns 24 x 1 fx 1 6 us 25 x 4 fx 3 2 us 213 x 1 fx 819 2 us 25 x 1 fx 3 2 us 28 x 1 1x 6 4 us 214 x 1 tx 1 64 ms 28 x 1 1x 6 4 us 27 x 1 fx 12 8 us 215 x 1 fx 3 28 ms 27 x 1 fx 12 8 us 28 x 1 fx 25 6 us 216 x 4 fx 6 55 ms 28 x 1 fx 25 6 us 29 x 1 fx 51 2 us 210 x 4 fx 102 4 us 210 x 1 fx 102 4 us 218 x 1 fx 26 2 ms 212 x 1 fx 409 6 us 220 x 1 tx 104 9 ms 212 x 1 fx 409 6 us 29 x 1 1x 51 2 us 217 x 1 tx 13 1 ms Setting prohibited Remarks 1 fx Main system clock oscillation frequency 2 TCL14 TCL17 Bits 4 through 7 of timer clock select register 1 TCL1 3 At fx 10 0 MHz operation 212 i ri oY a lv ed CHAPTER 9 8 BIT TIMER EVENT COUNTER 2 Operation as external event counter The external event counter counts the number of clock pulses externally input to the T11 P33 and T12 P34 pins by using the 8 bit timer registers 1 and 2 TM1 and TM2 Each time the valid edge specified by the timer clock select register 1 TCL1 is input the values
287. es automatic output of acknowledge signal output by ACKT is enabled Used for transmission or reception with 8 clock wait selected Note2 Enables automatic output of acknowledge signal Outputs acknowledge signal in synchronization with falling edge of 9th clock of SCL automatically outputs when ACKE 1 This bit is not automatically cleared to O after acknowledge signal has been output Used for reception with 9 clock wait selected R ACKD Acknowledge detection Clearing conditions ACKD 0 Setting condition ACKD 1 e When acknowledge signal is detected at rising edge of clock of SCL after completion of transfer When transfer start instruction is executed e When CSIEO 0 e When RESET is input R W Note 4 BSYE Controls N ch open drain output for transmission in I C bus mode Enables output transmission Disables output reception Notes 1 Set this bit before starting transfer 2 Output the acknowledge signal during reception by using ACKT when 8 clock wait is selected 3 The wait mode can be released when transfer by the serial interface has been started when an address signal has been received However the BSYE flag is not cleared to 0 4 Be sure to set BSYE to 1 when using the wake up function Remark CSIEO Bit 7 of the serial operation mode register 0 CSIMO 320 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78018FY S 4 Interrupt timing specification register SINT This re
288. es counting overflows and restarts counting from O Therefore if the new value of CROO M is less than its old value N it is necessary to restart the timer after changing the value of CROO Figure 8 21 Timing after Changing Value of Compare Register during Timer Count Operation Count pulse of AR Nee O NE AA SN NA amoo XRO Remark N gt X gt M 197 CHAPTER 8 16 BIT TIMER EVENT COUNTER a e inued 4 Data hold timing of capture register When the valid edge is input to the TIO POO pin while data is read from the 16 bit capture register CRO1 CRO1 does not perform the capture operation but holds the data However the interrupt request flag PIFO is set when the valid edge is detected Figure 8 22 Data Hold Timing of Capture Register Count pulse A AMO A O E Edge input Interrupt request flag Capture read signal Capture operation ignored 5 Setting valid edge Set the valid edge of the TIO POO INTPO pin after setting the bits 1 through 3 TMC01 TMCO3 of the 16 bit timer mode control register TMCO to 0 0 O and then stopping the timer operation The valid edge is set by using bits 2 and 3 ES10 and ES11 of the external interrupt mode register INTMO 6 Operation of OVFO flag The OVFO flag is set to 1 in the following case Mode in which the timer is cleared and started on coincidence between TMO and CROO is selected y CROO is set to FFFFH L TMO counts up from FFFFH to 0000H Fig
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290. eseeeeeeseeeeseneeeeseneeesseeeesnneeens 326 16 7 Operations of RELT and GMDT iii ao 327 16 8 Transfer Bit Sequence Select Circuit oooncccnncnnnnicicccnnccnnoncnnnncononcnncnnnn crac cnn crac nr rcnnnc cnn 327 16 9 Example of Serial Bus Configuration by 2 Wire Serial W O oooconnnininininccninccnnccnnccnnnccnannno 328 16 10 Timing of 2 Wire Serial l O Mode oooocncccinnccinccinncconccnnonconnnnonnconc nono cnnnnnran can nc rn rca rnn cnn 331 16 11 Operations of RELT and CMDT c cccccscccesncceeeeeeeeeeeeeeseaeeeeseneeecnneeeseeeeeseneeessneeesenseeeees 332 27 LIST OF FIGURES 5 7 Figure No Title Page 16 12 Example of Serial Bus Configuration in I2C BUS Mode scscsssssssscseeesesesceteseseseeceeneseees 333 16 13 Serial Data Transfer Timing on I2C BUS c cccscssssssescscesesesescesesssesesceseseseecetenesesesceteneiesesees 334 16 14 Start Condition dolia 335 16 15 Addresse Sirian mnnn ei db Deas 335 16 16 Transfer Direction Specification oooonccnnnnnnnnnnncnnncnnnccnnnccnnccn nn rnrcn arcano 336 16 17 Acknowledge Signal sarsies risainia ede a e Ea iaaa etc 336 16 18 Siop GONMGITION i a a a aa a a ii iran a e ata 337 16 19 Wait Signal e temana distin depts deta eel eden ete taste nantes 337 16 20 Pin Configurations ssi rs Ae NS ee ee A ees ta 344 16 21 Example of Communication from Master to Slave with 9 clock wait selected for both master and slave esceseeeesseeeeeneeeeeneeeeeeeeeennees 3
291. et CORADO and CORAD1 when bits 1 CORENO and 3 COREN1 of the correction control register CORCN refer to Figure 22 3 are 0 2 Only an address to an instruction code can be set in CORADO and CORAD1 3 Do not put the following addresses in CORADO and CORAD1 Address value of table area of table reference instruction CALLT instruction 0040H through 007FH Address value of vector table area 0000H through 003FH 454 CHAPTER 22 ROM CORRECTION 2 Comparator The comparator always compares the correction address values in correction address registers 0 and 1 CORADO and CORAD1 with the fetch address value If the correction address coincides with the fetch address value when bit 1 CORENO or bit 3 COREN1 of the correction control register CORCN is 1 the ROM correction circuit generates a correction branch processing request signal BR F7FDH 22 3 Registers Controlling ROM Correction ROM correction is controlled by the correction control register CORCN 1 Correction control register CORCN This register controls generation of the correction branch processing request signal when the correction address in correction address register 0 or 1 coincides with the fetch address It consists of correction enable flags CORENO and COREN1 that enable or disable detection of coincidence by the comparator and correction status flags CORSTO and CORST1 that indicate coincidence CORCN is set by using a 1 bit or 8 bit memory manipul
292. etermined by the communication specifications i rir lv ed CHAPTER 15 SERIAL INTERFACE CHANNEL 0 uPD78018F SUS e Acknowledge signal ACK The acknowledge signal is used for confirmation of reception of serial data between the transmission and reception sides Figure 15 17 Acknowledge Signal When output in synchronization with SCKO of 11th clock SCKO sf lof hol h1 seo 81 XT XT XXIII When output in synchronization with SCKO of 9th clock som LLL er Remark The dotted line indicates the READY status The acknowledge signal is a one shot pulse synchronized with the falling edge of SCKO after 8 bit data has been transferred Its position is arbitrary and may be synchronized with SCKO of clock n After the transmission side has transferred 8 bit data it checks whether the reception side has returned an acknowledge signal If no acknowledge signal is returned within a specific time after data transmission it is judged that the data was not received correctly 283 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 uPD78018F SUBSERIEF f Busy signal BUSY ready signal READY The busy signal informs the master that the slave is getting ready for transmitting receiving data The ready signal informs the master that the slave is ready to transmit receive data Figure 15 18 Busy Signal and Ready Signal SCKO le le l l l l SBO SB1 ACK BUSY READY Remark The dotted line indicates the
293. etting prohibited Wait control by external wait pin Note The full address mode is a mode in which all the areas of the 64 KB address space except the internal ROM RAM SFR and prohibited areas can be externally extended Remark P60 P63 pins are set in the port mode regardless of whether the single chip mode or memory extension mode is specified 153 CHAPTER 6 PORT FUNCTIONS 4 Key return mode register KRM This register enables disables releasing the standby mode by key return signals detection of the falling edge of port 4 KRM is set by a 1 bit or 8 bit memory manipulation instruction This register is set to 02H when the RESET signal is input Figure 6 19 Format of Key Return Mode Register Symbol 7 6 5 4 3 2 lt l gt lt 0 gt Address On reset R W o o To Too To Tomar FFF6H 02H R W KRIF Key return signal detection flag 0 Falling edge of port 4 not detected 1 Falling edge of port 4 detected Controls standby mode by key return signal 0 Enables releasing standby mode 1 Disables releasing standby mode Caution Be sure to clear KRIF to 0 to detect the falling edge of port 4 KRIF is not cleared to 0 automatically 154 CHAPTER 6 PORT FUNCTIONS 6 4 Operation of Port Functions The operation of a port differs depending on whether the port is set in the input or output mode as described below 6 4 1 Writing to I O port 1 2 In out
294. f 16 Bit Timer Event Counter Minimum Interval Time Maximum Interval Time Resolution 2 x TIO input cycle 216 x TIO input cycle TIO input edge cycle 22 x 1 fx 400 ns 217 x 1 fx 13 1 ms 2 x 1 fx 200 ns 23 x 1 fx 800 ns 218 x 1 fx 26 2 ms 22 x 1 fx 400 ns 24 x 4 fx 1 6 us 219 x 1 fx 52 4 ms 23 x 1 fx 800 ns Remarks 1 fx main system clock oscillation frequency 2 fx 10 0 MHz operation 2 PWM output The 16 bit timer event counter can be used for PWM output with a resolution of 14 bits 3 Pulse width measurement The 16 bit timer event counter can be used to measure the pulse width of an externally input signal 4 External event counter The number of pulses of an externally input signal can be measured 5 Square wave output A square wave of any frequency can be output Table 8 3 Square Wave Output Range of 16 Bit Timer Event Counter Minimum Interval Time Maximum Interval Time Resolution 2 x TIO input cycle 216 x TIO input cycle TIO input edge cycle 22 x 1 fx 400 ns 217 x 1 fx 13 1 ms 2 x 1 fx 200 ns 23 x 1 fx 800 ns 218 x 1 fx 26 2 ms 22 x 1 fx 400 ns 24 x 4 fx 1 6 us 219 x 1 fx 52 4 ms 23 x 1 fx 800 ns Remarks 1 fx main system clock oscillation frequency 2 fx 10 0 MHz operation 175 CHAPTER 8 16 BIT TIMER EVENT COUNTER 8 3 Configuration of 16 Bit Timer Event Counter The 16 bit timer event counter consists of the foll
295. f Pins and Handling of Unused Pins Table 3 1 shows the I O circuit type of each pin and how to handle unused pins For the configuration of each type of I O circuit refer to Figure 3 1 76 Pin Name POO INTPO TIO Table 3 1 I O Circuit Type of Each Pin I O Circuit Type Recommended Connection when Unused Connect to Vss PO1 INTP1 PO2 INTP2 PO3 INTP3 Individually connect to Vss via resistor P04 XT1 Connect to Von P10 ANIO P17 ANI7 P20 SI1 P21 SO1 P22 SCK1 P23 STB P24 BUSY P25 SI0 SBO P26 SO0 SB1 P27 SCKO P30 TOO P31 TO1 P32 TO2 P33 TI1 P34 T12 P35 PCL P36 BUZ P37 Individually connect to Voo or Vss P40 AD0 P47 AD7 Individually connect to Von via resistor P50 A8 P57 A15 Individually connect to Voo or Vss via resistor P60 P63 Mask ROM model P60 P63 PROM model P64 RD P65 WR P66 WAIT P67 ASTB Individually connect to Von via resistor Individually connect to Voo or Vss via resistor RESET XT2 AV REF AVop AVss IC Mask ROM model Ver PROM model Open Connect to Vss Connect to Voo Connect to Vss Directly connect to Vss CHAPTER 3 PIN FUNCTIONS uPD78018F SUBSERIEY Figure 3 1 I O Circuits of Pins 1 2 Schmitt trigger input with hysteresis characteristics Pullup
296. f functions configuring the object library included in the C compiler package CC78K 0 This file is required to match the object library included in C compiler package to the customer s specifications Part Number SxxxxCC78K0 L Note The DF78014 can be used in common with the RA78K 0 CC78K 0 SM78KO ID78KO NS and ID78KO Remark xxxx in the part number differs depending on the host machine and OS used 498 APPENDIX B DEVELOPMENT TOOLS uSxxxxRA78K0 HSxxxxCC78K0 uSxxxxDF78014 HSxxxxCC78K0 L Host Machine PC 9800 Series Windows Japanese version Note 1 2 Supply Medium 3 5 inch 2HD FD IBM PC ATTM and its compatibles Windows Japanese version Note 1 2 Windows English version Note 1 2 3 5 inch 2HC FD HP9000 Series 700 HP UXTM Rel 9 05 DAT DDS SPARCstation SunOS Rel 4 1 4 3 5 inch 2HC FD 1 4 inch CGMT NEWS RISC NEWS OS Rel 6 1 Notes 1 Can be operated in DOS environment 2 Not support WindowsNTTM 3 5 inch 2HC FD 499 APPENDIX B DEVELOPMENT TOOLS B 2 PROM Writing Tools B 2 1 Hardware PG 1500 PROM Programmer PROM programmer that can program PROM contained single chip microcontrollers in stand alone mode or through manipulation from host machine when connected to board supplied as accessory and optional PROM programmer adapter Can program representative PROMs from 256K bit to 4M bit mode
297. f slave address register SVA coincides with data of serial I O shift register O SIOO CSIEO Controls operation of serial interface channel O Stops operation Enables operation Notes 1 Bit 6 COI is a read only bit 2 3 4 5 1 6 COI is 0 when CSIEO 0 Remark x Don t care 318 Pxx The clock frequency is 1 16 of the frequency output by TO2 in the I2C bus mode This pin can be used as P25 CMOS input when used only for transmission This pin can be freely used for port function Set bit 5 SIC of the interrupt timing specification register SINT to 1 when using the wake up function Do not execute an instruction that writes the serial I O shift register O S100 while WUP PMxx Port mode register Output latch of port CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78018FY S 3 Serial bus interface control register SBIC This register sets the operation of the serial bus interface and indicates the status SBIC is set by a 1 bit or 8 bit memory manipulation instruction This register is set to OOH when the RESET signal is input Figure 16 4 Format of Serial Bus Interface Control Register 1 2 Symbol lt 7 2 gt lt l gt lt 0 gt Address Onreset R W SBIC BSYE ACKD ACKE dor RELD CMDT RELT FF61H 00H R WNote Used to output stop condition in C bus mode SO0 latch is set to 1 when RELT 1 After setting SOO latch RELT is automatically cleared to 0 This bit is also cleared
298. fication register ADTI CHAPTER 17 SERIAL INTERFACE CHANNEL 1 Addition of CHAPTER 22 ROM CORRECTION CHAPTER 22 ROM CORRECTION Addition of HP9000 series 700 as host machine for language processing software Addition of system simulator SM78KO Addition of A 4 OS for IBM PC APPENDIX A DEVELOPMENT TOOLS Addition of HP9000 series 700 as host machine for real time OS RX78K 0 Addition of OS MX78KO0 APPENDIX B EMBEDDED SOFTWARE 3rd edition Addition of following applicable models 1PD78018F and 78018FY Change of following products from under development to developed pPD78P018F 78P018FY except EPROM models Change of quality grade of following products from standard to not applicable pPD78P018FDW 78P018FKK S 78P018FYDW 78P018FYKK S Throughout 517 APPENDIX E REVISION HISTORY Edition 3rd edition Revision from Previous Edition Change of format of watchdog timer mode register WDTM and addition of Notes CHAPTER 11 WATCHDOG TIMER Addition of Notes on serial I O shift register 0 SIOO of uUPD78018FY subseries Correction of Figure 16 21 Example of Communication from Master to Slave with 9 clock wait selected for both master and slave Correction of Figure 16 22 Example of Communication from slave to Master with 9 clock wait selected for both master and slave Correction of 16 4 6 Restrictions using 12C b
299. from the SBO P25 or SB1 P26 pin starting from the MSB The receive data input to the SBO or SB1 pin at the rising edge of SCKO is latched to the SIOO al UNO 163 Figure 15 26 Address Transmit Operation from Master Device to Slave Device WUP 1 Master device processing transmission side Program processing Hardware operation Transfer line SCKO pin SBO SB1 pin Slave device processing reception side Program processing Hardware operation sjea III NW resora nse ses Clears ses INTCSIO Serial reception operation occurs Sets RELD e ZETE output _ output __ _ BUSY When SVA SIO0 mA Wy e i Ya d SAIMSSAENS 4810820d 0 TANNVHO AJ0VSYALNI IVIHIS Si YJLdAVH 862 Figure 15 27 Command Transmit Operation from Master Device to Slave Device Master device processing transmission side Program processing ON LLL LI II IIL DN CE scala Hardware operation Transfer line SCKO pin SBO SB1 pin Slave device processing reception side Hardware operation SAIMSSAENS 481084Ud7 0 TANNVHO AJ0VSYALNI IVIHIS SI YILAVHO 662 Figure 15 28 Data Transmit Operation from Master Device to Slave Device Master device processing transmission side Program processing ELI III EE eo ane Hardware operation Transfer line SCKO pin SBO SB1 pin ACK BUSY READY Li Slave device processing reception
300. g TMPR4 are valid and a maskable interrupt request INTWDT can be generated The default priority of INTWDT is set the highest of all the maskable interrupt requests The interval timer continues operation in the HALT mode but stops in the STOP mode Therefore set bit 7 of WDTM RUN to 1 before entering the STOP mode to clear the interval timer and then execute the STOP instruction Cautions 1 Once bit 4 WDTM4 of WDTM has been set to 1 when the watchdog timer mode is selected the interval timer mode is not set unless the RESET signal is input 2 The interval time immediately after it has been set by WDTM may be up to 0 5 shorter than the set time 3 The watchdog timer stops its counting operation when the subsystem clock is selected as the CPU clock Table 11 5 Interval Time of Interval Timer TCL20 Interval Time At fx 10 0 MHz 212 x 1 fx 409 6 us 213 x 1 fx 819 2 us 214 x 1 fx 1 64 ms 215 x 1 fx 3 28 ms 216 x 1 fx 6 55 ms 217 x 1 fx 13 1 ms 218 x 1 fx 26 2 ms 220 x 1 fx 104 9 ms Remarks 1 fx Main system clock oscillation frequency 2 TCL20 TCL22 Bits 0 through 2 of timer clock select register 2 TCL2 236 i rN a lu ed CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT 12 1 Function of Clock Output Control Circuit The clock output control circuit outputs a carrier when a remote controller signal is transmitted or a clock to be supplied to peripheral LSIs It
301. g Paa Hardware Sets Sets Af CON SCL 1 2 3 Processing in slave device Sets P27 A Sets P27 Prog ram petits pemes opat atc atc processing atch S100 n Release Hardware ACK Sets from i operation output CSIIFO wait Serial reception status 354 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78018FY S 4 Completion processing of reception by slave Make sure that bit 3 CMDD of the serial bus interface control register SBIC and bit 6 COI of the serial operation mode register O CSIMO when CMDD 1 are checked in the reception completion processing of the slave interrupt processing This is to prevent the slave from being unable to identify whether the start condition or data comes first and therefore to prevent the wake up function from being unusable when a non specific amount of data is received from the master 16 4 6 Restrictions in I2C bus mode The following restrictions apply to the wPD78018FY subseries e Restrictions when used as slave device in 12C bus ode Applicable models Description Preventive measure UPD78011FY 78012FY 78013FY 78014FY 78015FY 78016FY 78018FY 78P018FY and IE 78014 R EM A When the wake up function is executed by setting the WUP flag bit 5 of the serial operation mode register O CSIMO in the serial transfer statusN te data between the other slaves and master will be judged as an address If this data happens to coincide with the slave address of the wPD78018FY
302. g edge of 9th clock of SCL automatically output when ACKE 1 This bit is not automatically cleared to 0 after acknowledge signal has been output Used for reception with 9 clock wait selected R ACKD Detects acknowledge Clearing conditions ACKD 0 Setting condition ACKD 1 e On execution of transfer start instruction e On detection of acknowledge signal at rising edge e When CSIEO 0 of SCL clock after transfer has been completed e On RESET R W BSYE Controls N ch open drain output for transmission in C bus mode Note 4 Enables output transmission Disables output reception Notes 1 Set this bit before starting transfer 2 Output the acknowledge signal during reception by using ACKT when 8 clock wait is selected 3 The wait status can be released by starting the transfer of the serial interface or receiving an address signal However BSYE is not cleared to 0 4 Be sure to set BSYE to 1 when using the wake up function Remark CSIEO Bit 7 of the serial operation mode register 0 CSIMO 340 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78018FY S c Interrupt timing specification register SINT SINT is set by using a 1 bit or 8 bit memory manipulation instruction This register is set to OOH when the RESET signal is input Symbol 7 lt 6 gt lt 5 gt lt b gt lt 3 gt lt 2 gt 1 0 Address On reset R W SINT 0 CLD SIC SVAM CLC WREL WAT1 WATO FF63H 00H R wreret R W WAT1
303. g until the next instruction execution has ended MOV PSW byte MOV A PSW MOV PSW A MOV1 PSW bit CY e MOV1 CY PSW bit AND1 CY PSW bit OR1 CY PSW bit XOR1 CY PSW bit SET1 PSW bit e CLR1 PSW bit RETB RETI PUSH PSW POP PSW BT PSW bit addr16 e BF PSW bit addr16 e BTCLR PSW bit addr16 El DI e Instructions manipulating IFOL IFOH MKOL MKOH PROL PROH and INTMO registers Caution The BRK instruction is not one of the above instructions that keep an interrupt request pending However the software interrupt that is started by execution of the BRK instruction clears the IE flag to 0 Therefore even if a maskable interrupt request is generated while the BRK instruction is being executed it is not accepted However the non maskable interrupt is accepted Figure 18 16 shows the timing at which an interrupt request is accepted Figure 18 16 Pending Interrupt Request Saves PSW and PC and Interrupt servicing CPU processing Instruction N Instruction M jumps to interrupt servicing program xxIF Remarks 1 Instruction N Instruction that keeps interrupt request pending 2 Instruction M Instruction that does not keep interrupt request pending 3 Operation of xxIF interrupt request is not affected by value of xxPR priority level 421 i ARA ed CHAPTER 18 INTERRUPT FUNCTIONS AND TEST FUNCTIONS 18 5 Test Functions The test function sets the
304. gister SINT a Serial operation mode register 0 CSIMO CSIMO is set by a 1 bit or 8 bit memory manipulation instruction This register is set to OOH when the RESET signal is input 328 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78018FY S Symbol lt 7 Address On reset EI nin fem R W R W R W Clock externally input to SCKO pin R W R W Note 1 Output of 8 bit timer register 2 TM2 CSIM 03 Clock specified by bits 0 3 of timer clock select register 3 TCL3 Operation mode 3 wire serial I O mode Refer to 16 4 2 Operati First bit SIO SBO SDA0 P25 pin function S00 SB1 SDA1 P26 pin function ion in 3 wire serial I O mode SCK0 SCL P27 pin function 0 Note 2 x 2 wire serial 1 0 mode or 12C bus mode Note 2 x Controls wake up function Note 3 P25 CMOS 1 0 SB1 SDA1 N ch open drain I O SBO SDAO N ch open drain I O P26 CMOS 1 0 Generates interrupt request signal in all modes each time serial transfer is executed SCKO SCL N ch open drain I O Generates interrupt request signal when address received after start condition has been detected in 12C bus mode when CMDD 1 coincides with data of slave address register SVA Data of slave address register SVA does not coincide with data of serial I O shift register 0 SIOO Data of slave address register SVA coincides with da
305. gister controls the interrupt wait and clock level sets address mask function and indicates the status of the level of the SCKO SCL P27 pin SINT is set by a 1 bit or 8 bit memory manipulation instruction This register is set to OOH when the RESET signal is input Figure 16 5 Format of Interrupt Timing Specification Register 1 2 Symbol 7 4 gt lt 3 gt Address On reset R W SINT O CLD EZ FF63H 00H R WNote 1 R W WAT1 WATO Controls wait and interrupt Generates interrupt processing request at rising edge of 8th clock of SCKO clock output goes to high impedance state Setting prohibited Used in 1 C bus mode 8 clock wait Generates interrupt processing request at rising edge of 8th clock of SCL master makes SCL output low and waits after outputting 8 clocks Slave makes SCL pin low and requests for wait after inputting 8 clocks Used in I C bus mode 9 clock wait Generates interrupt processing request at rising edge of 9th clock of SCL master makes SCL output low and waits after outputting 9 clocks Slave makes SCL pin low land requests for wait after inputting 9 clocks R W WREL Controls clearing wait Wait clear status Clears wait status This bit is automatically cleared to 0 after wait status has been cleared used to clear wait status set by WATO WAT1 R W Controls clock level Note 2 Used in I C bus mode Makes output level of SCL pin low when serial transfer is not executed Use
306. he AVss pin to Vss Remark uPD78P018FY 56 CHAPTER 2 GENERAL 1 PD78018FY SUBSERIES 64 pin plastic QFP 14 x 14 mm 4PD78011FYGC XXX AB8 78012FYGC XXX AB8 78013FYGC XXX AB8 1PD78014FYGC XXX AB8 78015FYGC XXX AB8 78016FYGC XXX AB8 u4PD78018FYGC XXX AB8 78P018FYGC AB8 e 64 pin plastic LQFP 12 x 12 mm 1PD78011FYGK XXX 8A8 78012FYGK XXX 8A8 1PD78014FYGK XXX 8A8 78P018FYGK 8A8 64 pin ceramic WQFN 14 x 14 mm H4PD78P018FYKK S O P27 SCKO SCL lt gt 0 P26 S00 SB1 SDA1 0 P25 SI0 SBO SDAO o OQ P30 TOO O P31 TO1 O P32 TO2 O P33 TI1 O P34 T12 O P35 PCL O P36 BUZ O P37 Vss P40 ADO O O O P41 AD1 O O O O 2 3 4 5 6 7 8 9 ah ee N O P42 AD2 P43 AD3 P44 AD4 P45 AD5 O lt x gt 15 P46 AD6 O lt gt 16 a o A 0 7 18 P47 AD7 O P50 A8 O lt gt Cautions 1 Directly connect the IC Internally Connected pins to Vss O P51 A9 O P52 A10 O O P24 BUSY O P23 STB O P22 SCK1 O P21 SO1 O P20 SI1 O AVnrer O AVoo P53 A11 O P54 A12 O w P55 A13 O lt Vss O P56 A14 O 2 Connect the AVpp pin to Vpp 3 Connect the AVss pin to Vss Remark HPD78P018FY P57 A15 O O P17 ANI7 O P16 ANI6 O P15 ANI5 O P14 ANI4 O P13 ANI3 O P12 ANI2 P60 O P61 O P62 O P63 O P64 RD O P65 WR O O P11 ANI1 O P10 ANIO O AVss O P04 XT1 O XT2 O IC Vep O X1 O X2 O Vop O POS INTP3 O
307. he falling edge of the serial clock SCKO The transmitted data is retained by the SOO latch and output from the SBO P25 or SB1 P26 pin starting from the MSB The received data input from the SBO or SB1 pin is latched to the SIO0 at the rising edge of SCKO When the 8 bit data has been completely transferred the operation of the SIOO is automatically stopped and an interrupt request flag CSIIFO is set Figure 15 31 Timing of 2 Wire Serial I O Mode Transfer ends Transfer starts in synchronization with falling edge of SCKO The SBO or SB1 pin specified as the serial data bus must be externally pulled up because this pin is an N ch open drain I O pin When data is received write FFH to SIOO in advance because the N ch open drain output must be made high impedance state Because the SBO or SB1 pin outputs the status of the SOO latch the output status of the SBO or SB1 pin can be manipulated by setting the bit O RELT and bit 1 CMDT of serial bus interface control register SBIC However do not manipulate the output status of the pin during serial transfer The output level of the SCKO pin is controlled by manipulating the P27 output latch in the output mode mode of the internal system clock refer to 15 4 5 Manipulating SCKO P27 pin output i rN a lu ed CHAPTER 15 SERIAL INTERFACE CHANNEL 0 uPD78018F SUS 3 Signals Figure 15 32 shows the operations of RELT and CMDT Figure 15 32 Operat
308. he interrupt timing specification register SINT can also compare the slave address If no coincidence is detected when the address is received bit 2 RELD of the serial bus interface control register SBIC is cleared to 0 The wake up function can be used by setting bit 5 WUP of CSIMO to 1 in the SBI mode In this case an interrupt request signal INTCIO is generated only when the slave address output by the master coincides with the value of SVA This is interrupt signal indicates that the master requests communication If bit 5 SIC of the interrupt timing specification register SINT is set to 1 the wake up function cannot be used even if WUP is set to 1 the interrupt request signal is generated on detection of bus release Clear SIC to O when using the wake up function When the microcontroller transmits data as the master or a slave in the SBI mode or 2 wire serial I O mode errors can be detected by using SVA The contents of SVA become undefined when the RESET signal is input 263 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 uPD78018F SUBSERIER 3 4 5 6 7 264 SO0 latch This latch retains the levels of SIO SBO P25 and SO0 SB1 P26 pins It can also be directly controlled by software In the SBI mode this latch is set when the eighth serial clock has been input Serial clock counter This counter counts the serial clocks output or input during transmit receive operation and checks whether 8 b
309. hen transfer data is placed in SIOO if the following two conditions are satisfied The serial interface channel 0 operation control bit CSIEO 1 The internal serial clock is stopped or SCL is low after 8 bit serial data has been transferred Cautions 1 IfCSIEO is set to 1 after the data has been written to SIOO the transfer is not started 2 Because the N ch open drain output must be made high impedance state when data is to be received set bit 7 BSYE of serial bus interface control register SBIC to 1 and write FFH to SIOO in advance However when the wake up function is used when bit 5 WUP of the serial operation mode register 0 CSIMO is set do not write FFH to SIOO before reception The N ch open drain output is always at high impedance state even if FFH is not written to SIO0 3 If data is written to SIOO with the slave in the wait status the data is not lost Transfer is started when SCL is output after the wait status has been released Serial transfer is automatically stopped when 8 bits of data have been completely transferred and an interrupt request flag CSIIFO is set Notes on using I2C bus mode Output of start condition master The SCL pin usually outputs low level when the serial clock is not output To output the start condition the SCL pin must be made high once To make the SCL pin high set the CLC bit of interrupt timing specification register SINT to 1 After setting CLC clear CLC to 0 a
310. hereby under any patents copyrights or other intellectual property rights of Renesas Electronics or others You should not alter modify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part Descriptions of circuits software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information When exporting the products or technology described in this document you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military including but not limited to the development of weapons of mass destruction Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicable domestic or foreign laws or regulations Renesas Electronics has used reasonable care in preparing the information included in this document but Ren
311. iate data or the contents of a register is set to the program counter When the RESET signal is input the value of the reset vector table at addresses 0000H and 0001H is set to the program counter Figure 5 9 Program Counter Configuration 15 0 pors pote pota pote c11 peto PC PCB C7 Pce Pcs Pca PCS PC2 PCI PCO 2 Program status word PSW The program status word is an 8 bit register consisting of flags that are set or reset as a result of instruction PC execution The contents of the program status word are automatically pushed to the stack when an interrupt request is generated or when the PUSH PSW instruction is executed and are automatically popped from the stack when the RETB RETI or POP PSW instruction is executed The contents of the program status word are set to 02H when the RESET signal is input Figure 5 10 Program Status Word Configuration 7 0 a Interrupt enable flag IE This flag controls acknowledgement of an interrupt request by the CPU When IE 0 all the interrupts are disabled except the non maskable interrupt When IE 1 the interrupts are enabled At this time accepting an interrupt is controlled by the in service priority flag ISP interrupt mask flag corresponding to each interrupt and interrupt priority specification flag These flags are reset to 0 when the DI instruction is executed or when an interrupt request is accepted and is set to 1 when the El instruction is executed b Z
312. iate data or label saddrp FE20H FF1FH immediate data or label even address only addr16 0000H FFFFH immediate data or label even address only for 16 bit data transfer instruction addr11 0800H OFFFH immediate data or label addr5 0040H 007FH immediate data or label even address only word 16 bit immediate data or label byte 8 bit immediate data or label bit 3 bit immediate data or label RBn RBO RB3 Note FFDOH FFDFH cannot be addressed Remark For the symbols of the special function registers refer to Table 5 7 Special Function Register List 478 CHAPTER 24 INSTRUCTION SET 24 1 2 Description of operation column A A register 8 bit accumulator X X register B Bregister C C register D D register E E register H H register L L register AX AX register pair 16 bit accumulator BC BC register pair DE DE register pair HL HL register pair PC program counter SP stack pointer PSW program status word CY carry flag AC auxiliary carry flag Z zero flag RBS register bank select flag IE interrupt request enable flag NMIS non maskable interrupt processing flag memory contents indicated by contents of address or register in xuw XL high order 8 bits and low order 8 bits of 16 bit register A logical product AND Vv logical sum OR Y exclusive logical sum exclusive OR inverted data addri6 16 bit immediate data or label j
313. ication register ADTI None Provided Package e 64 pin plastic shrink DIP 750 mil e 64 pin ceramic shrink DIP w window 750 mil Note e 64 pin plastic QFP 14 x 14 mm e 64 pin plastic shrink DIP 750 mil e 64 pin plastic QFP 14 x 14 mm e 64 pin plastic LQFP 12 x 12 mm e 64 pin plastic shrink DIP 750 mil 64 pin ceramic shrink DIP w window 750 mil Note e 64 pin plastic QFP 14 x 14 mm 64 pin plastic LQFP 12 x 12 mm 64 pin ceramic WQFN 14 x 14 mm Note Programmer adapter PA 78P014CW PA 78P014GC PA 78P018CW PA 78P018GC PA 78P018GK PA 78P018KK S Emulation board IE 78014 R EM or IE 78014 R EM A IE 78014 R EM A Access timing to external memory Differs between uPD78014 subseries and other subseries Refer to individual data sheet Electrical characteristics recom mended soldering conditions Note PROM model only 494 Refer to individual data sheet APPENDIX B DEVELOPMENT TOOLS The following development tools are available for development of systems using the uwPD78018F and 78018FY subseries Figure B 1 shows development tools 495 APPENDIX B DEVELOPMENT TOOLS Figure B 1 Development Tool Configuration 1 2 1 When using the in circuit emulator IE 78K0 NS Language Processing Software Debugging Tool e System simulator Integrated debugger e Device file Assembler package C compller packag
314. iffers depending on the host machine and OS used LSxxxxID78KO NS Host Machine PC 9800 Series Supply Medium Note Windows Japanese version 3 5 inch 2HD FD IBM PC AT and its compatibles Windows Japanese version Note 3 5 inch 2HC FD Note Windows English version Note Not support WindowsNT uUSxxxxID78KO0 Host Machine PC 9800 Series Supply Medium Note 35 inch 2HD FD Windows Japanese version IBM PC AT and its compatibles Windows Japanese version Note 35 inch 2HC FD Windows English version note HP9000 Series 700 HP UX Rel 9 05 DAT DDS SPARCstation SunOS Rel 4 1 4 3 5 inch 2HC FD 1 4 inch CGMT NEWS RISC NEWS OS Rel 6 1 3 5 inch 2HC FD Note Not support WindowsNT 504 APPENDIX B DEVELOPMENT TOOLS B 4 OS for IBM PC The following OSs for the IBM PC are supported Version PC DOS Ver 5 02 to Ver 6 3 J6 1 VNote to J6 3 VNote IBM DOS J5 02 VNote MS DOS Ver 5 0 to Ver 6 22 5 0 VNote to 6 2 yNote Note Only English mode is supported Caution Although Ver 5 0 and above have a task swap function this function cannot be used with this software B 5 System Upgrade from Former In circuit Emulator for 78K 0 Series to IE 78001 R A If you already have a former in circuit emulator for 78K 0 Series microcontrollers IE 78000 R or IE 78000 R A that in circuit emulator c
315. ified for input output bitwise When used as input port internal pull up resistor can be connected by software ANIO ANI7 P20 P21 P22 P23 P24 P25 P26 P27 8 bit I O port Can be specified for input output bitwise When used as input port internal pull up resistor can be connected by software sit S01 SCK1 STB BUSY S10 SBO SO0 SB1 SCKO P30 P31 P32 P33 P34 P35 P36 P37 8 bit I O port Can be specified for input output bitwise When used as input port internal pull up resistor can be connected by software TOO TO1 TO2 TH TI2 PCL BUZ P40 P47 8 bit I O port Can be specified for input output in 8 bit units When used as input port internal pull up resistor can be connected by software Test input flag KRIF is set to 1 at falling edge of these pins ADO AD7 P50 P57 8 bit I O port Can directly drive LED Can be specified for input output bitwise When used as input port internal pull up resistor can be connected by software 134 8 bit I O port N ch open drain I O port Can be specified for input output bitwise Internal pull up resistor can be specified by mask option with mask ROM model only Can directly drive LED When used as input port internal pull up resistor can be connected by software CHAPTER 6 PORT FUNCTIONS Pin Name Port 0 POO
316. ime has elapsed If the interrupt is disabled to be accepted the instruction at the next address is executed Figure 20 4 Releasing STOP Mode by Interrupt Request Interrupt request Wait STOP set time by OSTS instruction gt Standby H release signal CAN Operation Oscillation stabilization Operation mode STOP mode wait status mode Oscillation Clock Oscillation stops Oscillation gt E Remark The dotted line indicates the case where the interrupt request that has released the standby mode is accepted b Releasing by unmasked test input The STOP mode is released by an unmasked test signal input and the instruction at the address next to that of the STOP instruction is executed after the oscillation stabilization time has elapsed 446 CHAPTER 20 STANDBY FUNCTION c Releasing by RESET input The STOP mode is released by the RESET signal input and the reset operation is performed after the oscillation stabilization time has elapsed Figure 20 5 Releasing STOP Mode by RESET Input Wait 218 fx 26 2ms STOP instruction RESET KC signal Oscillation Operation Reset stabilization Operation mode AE STOP mode period eS wait status ne mode Oscillation Clock Oscillation stops Oscillation Remarks 1 fx Main system clock oscillation frequency 2 At fx 10 0 MHz operation Table 20 4 Operation after Release of STOP Mode Releasing Source Operation Ma
317. ime because independent input and output lines are used allowing simultaneous tranmission and reception MSB LSB selectable for first bit of 8 bit data by serial transfer 2 wire serial I O mode SCKO serial clock SBO or SB1 serial data bus Any data transfer format can be supported by the program and lines for Ihand shake conventionally necessary for connecting multiple devices can be eliminated Useful for connecting peripheral I Os and display controllers with conventional clocked serial interface such as 75X XLseries 78K series and 17K series 12C bus mode Caution 310 SCL serial clock SDAO or SDA1 serial data bus Supports 12C bus format Because serial bus consists of two signal lines number of ports can be reduced and wiring distance on PWB can be shortened even when plural micro computers are connected Useful for connecting CPU and peripheral IC containing serial interface conforming to I2C bus Do not change the operation mode 3 wire serial I O 2 wire serial I O or 12C bus while the operation of serial interface channel 0 is enabled To change the operation mode stop the serial operation CHAPTER 16 SERIAL INTERFACE CHANNEL 0 1PD78018FY S 16 2 Configuration of Serial Interface Channel 0 Serial interface channel 0 consists of the following hardware Table 16 3 Configuration of Serial Interface Channel 0 Item Configuration Register Serial I O shift
318. iming of each signal when this program is executed refer to Figure 16 21 355 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78018FY SUBSERI7 Example of program releasing serial transfer status 356 SET1 P2 5 lt 1 gt SET1PM2 5 lt 2 gt SET1 PM2 7 lt 3 gt CLR1 CSIEO lt 4 gt SET1 CSIEO lt 5 gt SET1 RELT lt 6 gt CLR1 PM2 7 lt 7 gt CLR1 P2 5 lt 8 gt CLR1 PM2 5 lt 9 gt lt 1 gt lt 2 gt lt 3 gt lt 4 gt lt 5 gt lt 6 gt lt 7 gt lt 8 gt lt 9 gt Prevents the SDAO pin from outputting a low level when the 12C bus mode is restored by the instruction in lt 5 gt The output of the SDAO pin goes into a high impedance state Sets the P25 SDAO pin in the input mode to prevent the SDAO line from being affected when the port mode is set by the instruction in lt 4 gt The P25 pin is set in the input mode when the instruction in lt 2 gt is executed Sets the P27 SCL pin in the input mode to prevent the SCL line from being affected when the port mode is set by the instruction in lt 4 gt The P27 pin is set in the input mode when the instruction in lt 3 gt is executed Changes the mode from the 12C bus mode to port mode Restores the mode from the port mode to the I2C bus mode Prevents the instruction in lt 8 gt from causing the SDAO pin to output a low level Sets the P27 pin in the output mode because the P27 pin must be in the output mode in the 12C bus mode
319. in plastic QFP 14 x 14 mm 64 pin plastic shrink DIP 750 mil 64 pin plastic QFP 14 x 14 mm 64 pin plastic shrink DIP 750 mil 64 pin plastic QFP 14 x 14 mm 64 pin plastic shrink DIP 750 mil 64 pin plastic QFP 14 x 14 mm 64 pin plastic shrink DIP 750 mil 64 pin plastic QFP 14 x 14 mm 64 pin plastic QFP 14 x 14 mm Remark XXX indicates ROM code suffix Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM One time PROM One time PROM Mask ROM 37 CHAPTER 1 GENERAL 1 PD78018F SUBSERIES 1 4 Quality Grade 1 Standard grade products including not applicable products Part Number Package Quality Grade uPD78011FCW XXX 64 pin plastic shrink DIP 750 mil Standard HPD78011FGC XXX AB8 64 pin plastic QFP 14 x 14 mm Standard uPD78011FGK XXX 8A8 64 pin plastic LQFP 12 x 12 mm Standard uPD78012FCW XXX 64 pin plastic shrink DIP 750 mil Standard uUPD78012FGC XXX AB8 64 pin plastic QFP 14 x 14 mm Standard uPD78012FGK XXX 8A8 64 pin plastic LQFP 12 x 12 mm Standard uPD78013FCW XXX 64 pin plastic shrink DIP 750 mil Standard HPD78013FGC XXX AB8 64 pin plastic QFP 14 x 14 mm Standard uUPD78013FGK XXX 8A8 64 pin plastic LQFP 12 x 12 mm Standard uPD78014FCW XXX 64 pin plastic shrink DIP 750 mil Standard uUPD78014FGC XXX AB8 64 pin plastic QFP 14 x 14 mm Standard uUPD78014FGK XXX 8A8 64 pin plastic LQFP 12 x 12
320. indicates the number of wait states when the external memory extension area is read 4 m indicates the number of wait states when the external memory extension area is written 24 3 Instruction List by Addressing 1 8 bit instructions MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MULU DIVUW INC DEC ROR ROL RORC ROLC ROR4 ROL4 PUSH POP DBNZ 488 CHAPTER 24 INSTRUCTION SET 2nd Operand 1st Operand laddr16 HL byte HL B HL C addr16 HL byte HL B HL C X C Note Except for r A 489 CHAPTER 24 INSTRUCTION SET 2 16 bit instructions MOVW XCHW ADDW SUBW CMPW PUSH POP INCW DECW 2nd Operand laddr16 1st Operand MOVWNote Note Only when rp BC DE HL 3 Bit manipulation instructions MOV1 AND1 OR1 XOR1 SET1 CLR1 NOT1 BT BF BTCLR 2nd Operand sfr bit saddr bit PSW bit HL bit addr16 1st Operand 490 CHAPTER 24 INSTRUCTION SET 4 Call branch instructions CALL CALLF CALLT BR BC BNC BZ BNZ BT BF BTCLR DBNZ 2nd Operand laddr16 laddr11 addr5 addr16 1st Operand Basic instruction Compound instruction 5 Other instructions ADJBA ADJBS BRK RET RETI RETB SEL NOP El DI HALT STOP 491 MEMO 492 APPENDIX A DIF
321. ins previous status before setting HALT mode 16 bit timer event counter Operable 8 bit timer event counter Watchdog timer A D converter Watch timer Operable when fx 28 selected as Operatable count clock Serial interface Other than automatic Operable transmit receive function Automatic transmit receive Stops operation function External interrupt INTPO Operable when clock to peripheral hardware fx 28 fx 27 selected as sampling clock INTP1 INTP3 Operable Externally ADO AD7 High impedance extended bus line A8 A15 Retains previous status before setting HALT mode ASTB Low level High level High impedance Notes 1 Includes the case where an external clock is not supplied as the subsystem clock 2 Includes the case where an external clock is supplied as the subsystem clock 441 CHAPTER 20 STANDBY FUNCTION Table 20 1 Operation Status in HALT Mode 2 2 b When HALT instruction is executed while system operates on subsystem clock Setting of HALT Mode When Main System Clock When Main System Clock Oscillation Continues Oscillation Stops Clock generation circuit Both main system clock and subsystem clock can oscillate Supply of clock to CPU is stopped CPU Stops operation Port output latch Retains previous status before setting HALT mode 16 bit timer event counter Operable Stops operation 8 bit timer event counter Operable
322. interrupt is being serviced Table 18 4 shows the interrupts that can be nested and Figure 18 15 shows an example of nesting Table 18 4 Interrupt Requests that Can Be Nested during Interrupt Processing Nesting Request Maskable Interrupt Request Non Maskable PR 0 PR 1 Interrupt Interrupt Request being accepted IE 1 IE 1 Non maskable interrupt processing Maskable interrupt ISP 0 processing ISP 1 Software interrupt processing Remarks 1 nesting enabled 2 x nesting disabled 3 ISP and IE are flags included in PSW ISP 0 Interrupt with higher priority is processed ISP 1 Interrupt is not accepted or interrupt with lower priority is processed IE 0 Accepting interrupt is disabled IE 1 Accepting interrupt is enabled 4 PR is a flag included in PROL PROH PR 0 Higher priority flag PR 1 Lower priority flag 418 CHAPTER 18 INTERRUPT FUNCTIONS AND TEST FUNCT Figure 18 15 Example of Nesting 1 2 Example 1 Example where nesting takes place two times Main processing INTxx processing INTyy processing INTzz processing INTxx PR 1 PR 0 PR 0 RETI Two interrupt requests INTyy and INTzz are accepted while interrupt INTxx is serviced and nesting takes place Before each interrupt request is accepted the El instruction is always executed and the interrupt is enabled Example 2 Example where nesting does not t
323. interrupt request acceptance operation ooconoccccnoncccnonancnonnnnnnnncnnnarnnnnnnnnnos 412 18 4 2 Maskable interrupt request acceptance operation oooccoccccnoncccnnonnconannnononononnon corran coran cnn 415 18 4 3 Software interrupt request acceptance Operation cceecceeceeeeeeeeeeeeeteeeeeeeeeeneeseeeeeeete 417 21 18 4 4 N Stingsc Antec ag ee ied RL a E 418 18 4 5 Pending interrupt request eeececceeeeeeeeeceeeseeeeeeeeeeeeeneeseseeeeeneneeseenseseneeesenseeenseneesenanes 421 18 5 Test FUNCtIONS ccccccseeeeceeeeseeeeeeenseeeeseeenseeeeeeensnneeeeeenseeeeeeensaeeeeeeensnceeeesenseeeeeeensaeceeeeeess 422 18 5 1 Registers controlling test FUNCTIONS 00 0 eee eceeeeeeeneeeeeeaeeeseaeeeeeneeeeeeneeeseaeeeeenneeeeeneeeneaeees 422 18 5 2 Test input signal acceptance operation eee eeeeeeseeeeeneeeseneeeeeeeeeeeeeeeeseeeteneeeeeneeersaeees 424 CHAPTER 19 EXTERNAL DEVICE EXTENSION FUNCTION cccsseccesseeseseeeeseeeesseeesesseeeeneas 425 19 1 External Device Extension FUNCtiOn cccccseeeeeeeesseeeeeeeeseeeeeeeenseeeeeensneeeseeenseceeeeeens 425 19 2 Registers Controlling External Device Extension FUunction c ccssscssseesseeees 430 19 3 Timing of External Device Extension Function ccccessseeeeeeeeeeeeeeeesneeeeeeenseeeeeeeeees 432 19 4 Example of Connection with Memory cccecccesseeseeeeeeseeeeseeeeeeseeeesseeeeneeeeeesneeseneeeees 437 CHAPTER 20 STANDBY FUNC
324. ion in 2 wire serial I O mode The 2 wire serial l O mode can be used with any communication format by program Basically two lines serial clock SCKO and serial data I O SBO or SB1 are used to establish communication in this mode Figure 15 30 Example of Serial Bus Configuration by 2 Wire Serial I O Voo Vpop e x a Master Slave SCKO SCKO SBO SB1 SBO SB1 1 Register setting The 2 wire serial I O mode is set by using the serial operation mode register 0 CSIMO serial bus interface control register SBIC and interrupt timing specification register SINT a Serial operation mode register 0 CSIMO CSIMO is set by a 1 bit or 8 bit memory manipulation instruction This register is set to OOH when the RESET signal is input 303 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 uPD78018F SUBSERI Symbol R W R W 304 lt 7 gt Address EN a Clock externally input to SCKO pin On reset 00H R W R MNote 1 Output of 8 bit timer register 2 TM2 CSIM 3 wire serial Operation mode First bit Clock specified by bits 0 3 of timer clock select register 3 TCL3 SIO SB0 P25 pin function SO0 SB1 P26 pin function I O mode Refer to 15 4 2 Operation in 3 wire serial I O mode SCKO P27 pin function SBI mode Refer to 15 4 3 Operation in SBI mode Note 2 Note 2 x x 2 wire serial x Note 2 Note 2 x 1 0 mo
325. ion instruction This register is set to OOH when the RESET signal is input Symbol 73 2 gt lt gt 0 gt Address Onreset R W SBIC BSYE ACKD ACKE sehen corns RELD CMDT RELT FF61H 00H R MNote R W Used to output bus release signal SOO0 latch is set to 1 when RELT 1 Atter setting SOO latch RELT is automatically cleared to 0 This bit is also cleared to 0 when CSIEO 0 R W Used to output command signal SO0 latch is cleared to 0 when CMDT 1 After clearing SOO latch CMDT is automatically cleared to 0 This bit is also cleared to 0 when CSIEO 0 R RELD Bus release detection Clearing conditions RELD 0 Setting condition RELD 1 When transfer start instruction is executed When values of SIOO and SVA do not coincide when address is received When bus release signal REL is detected e When CSIEO 0 When RESET is input R CMDD Command detection Clearing conditions CMDD 0 Setting condition CMDD 1 When transter start instruction is executed When bus release signal REL is detected e When CSIEO 0 When RESET is input When command signal CMD is detected R W Outputs an acknowledge signal in synchronization with the falling edge of the SCKO clock immediately after the instruction that sets this bit to 1 has been executed and then is automatically cleared to 0 Used as ACKE 0 This bit is also cleared to 0 when transfer of serial interface is started or when CSIE
326. ions of RELT and CMDT SO0 latch RELT CMDT 4 Transfer start Serial transfer is started by setting the transfer data to the serial I O shift register O SIOO when the following two conditions are satisfied Operation control bit of serial interface channel 0 CSIEO 1 When internal serial clock is stopped or SCKO is high after 8 bit serial transfer Cautions 1 Even if CSIEO is set to 1 after data has been written to SIOO transfer is not started 2 Write FFH to SIOO in advance because the N ch open drain output must be made high impedance state during data reception Serial transfer is automatically stopped at the end of 8 bit transfer and an interrupt request flag CSIIFO is set 5 Error detection In the 2 wire serial I O mode the status of the serial bus SBO SB1 under transmission is also loaded to serial I O shift register O SIOO of the device that is transmitting data therefore a transfer error can be detected by the following method a By comparing data of SIOO before start of and after completion of transmission In this case it is judged that an transmission error has occurred if two data are different b By using slave address register SVA The transmitted data is set to SIOO and SVA and transmission is executed After completion of transmission the COI bit match signal from address comparator of the serial operation mode register 0 CSIMO is tested If this bit is 1 it is judged that t
327. ious contents of the registers flags and data memory before setting the standby mode are all retained In addition the statuses of the output latch of the I O ports and output buffer are also retained Cautions 1 The STOP mode can be used only when the system operates on the main system clock this mode cannot be used to stop the oscillation of the subsystem clock The HALT mode can be used regardless of whether the system operates on the main system clock or subsystem clock 2 To set the STOP mode be sure to stop the operations of the peripheral hardware and then execute the STOP instruction 3 To reduce the power consumption of the A D converter clear bit 7 CS of A D converter mode register ADM to 0 to stop the A D conversion and then execute the HALT or STOP instruction 439 i ar lu ed CHAPTER 20 STANDBY FUNCTION 20 1 2 Registers controlling standby function The wait time during which oscillation is stabilized after the STOP mode has been released by an interrupt request is controlled by the oscillation stabilization time select register OSTS OSTS is set by an 8 bit memory manipulation instruction This register is set to 04H when the RESET signal is input Therefore to release the STOP mode by inputting the RESET signal the time required to release the mode is 218 fx Figure 20 1 Format of Oscillation Stabilization Time Select Register Symbol 7 6 Address On reset R W 5 4 3 2 1 0 ors o Jo Jo ToDo
328. ipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots High Quality Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems medical equipment or systems for life support e g artificial life support devices or systems surgical implantations or healthcare intervention e g excision etc and any other applications or purposes that pose a direct threat to human life You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges Although Renesas Electronics endeavors to improve the quality and reliability of its products semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certai
329. ister WDT Watchdog timer Figure 18 10 Timing of Non Maskable Interrupt Request Acceptance Saving PSW and PC and CPU processing Instruction Instruction jump to interrupt processing erupt processing program TMIF4 E The interrupt generated in this period is accepted at the point of T TMIF4 Watchdog timer interrupt request flag 413 CHAPTER 18 INTERRUPT FUNCTIONS AND TEST FUNCTIONS Figure 18 11 Non Maskable Interrupt Acceptance Operation a If anew non maskable interrupt request is generated while non maskable interrupt service program is being executed NMI request lt 1 gt rd NMI request lt 2 gt gt Execution of one instruction e NMI request lt 1 gt is executed NMI request lt 2 gt is kept pending Pending NMI request lt 2 gt is serviced b If two new non maskable interrupt requests are generated while non maskable interrupt service program is being executed NMI request lt 1 gt ee NMI request lt 1 gt is executed NMI request lt 2 gt NMI request lt 2 gt is kept pending NMI request lt 3 gt is kept pending Execution of one instruction NMI request lt 3 gt Pending NMI request lt 2 gt is serviced NMI request lt 3 gt is not accepted only one NMI request is accepted even if two or more NMI requests are generated in duplicate 414 CHAPTER 18 INTERRUPT FUNCTI
330. ister 3 Symbol 7 6 5 4 3 2 1 0 Address On reset R W TCL3 TCL37 TCL36 TCL35 TCL34 TCL33 TCL32 TCL31 TCL30 FF43H 88H R W TCL32 TCL31 TCL30 Selects serial clock of serial interface channel 0 fx 22 Note fx 23 1 25 MHz fx 24 625 kHz fx 25 313 kHz fx 25 156 kHz fx 27 78 1 kHz fx 28 39 1 kHz fx 28 19 5 kHz Setting prohibited TCL36 TCL35 TCL34 Selects serial clock of serial interface channel 1 fx 22Note fx 23 1 25 MHz fx 24 625 kHz fx 25 313 kHz fx 26 156 kHz fx 27 78 1 kHz fx 28 39 1kHz fx 29 19 5 kHz Others Setting prohibited Note Can be set only when the main system clock oscillates at 4 19 MHz or less Caution Before writing data other than that already written to TCL3 stop the serial transfer Remarks 1 fx Main system clock oscillation frequency 2 At fx 10 0 MHz operation 266 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 uPD78018F SUF Symbol lt 7 gt Figure 15 3 Format of Serial Operation Mode Register 0 6 gt lt 5 gt Address cave fs co wr nanan monn e On reset 00H R W R W Note 1 R W Selects clock of serial interface channel 0 Clock externally input to SCKO pin Output of 8 bit timer register 2 TM2 Clock specified by bits 0 3 of timer clock se
331. it data has been transmitted received Serial clock control circuit This circuit controls supply of the serial clock to the serial I O shift register 0 SIOO When the internal system clock is used it also controls the clock output to the SCKO P27 pin Interrupt request signal generation circuit This circuit controls generation of an interrupt request signal It generates an interrupt request signal in the following cases In 3 wire serial l O mode and 2 wire serial I O mode Generates the interrupt request signal each time eight serial clocks have been counted In SBI mode When WUPNOote jg 0 Generates the interrupt request signal each time eight serial clocks have been counted When WUP ote is 1 Generates the interrupt request signal when the values of the serial I O shift register 0 SIOO and slave address register SVA coincide after an address has been received Note WUP wake up function specification bit Bit 5 of serial operation mode register 0 CSIMO Clear bit 5 SIC of the interrupt timing specification register SINT to 0 when using the wake up function WUP 1 Busy acknowledge output circuit and bus release command acknowledge detection circuit These circuits output and detect various control signals in the SBI mode They do not operate in the 3 wire serial l O mode and 2 wire serial I O mode al UNO CHAPTER 15 SERIAL INTERFACE CHANNEL 0 uPD78018F SUS 15 3 Registers Controlling Seri
332. k The output control selects CMOS output or N ch open drain output CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78018FY S 1 2 Serial I O shift register 0 S100 This 8 bit register converts parallel data into serial data and transmits receives serial data shift operation in synchronization with the serial clock SIOO is set by an 8 bit memory manipulation instruction When the bit 7 CSIEO of the serial operation mode register 0 CSIMO is 1 the serial operation is started when data is written to SIOO The data written to SIOO is output to the serial output line SOO or serial data bus SBO SB1 for transmission When data is received it is read from the serial input line SIO or SBO SB1 to SIOO In the 2 wire serial I O mode and I2C bus mode bus configuration the input and output pins are shared The device that is to receive data therefore must be made the N ch open drain output for transmission high impedance state in advance Therefore write FFH to SIOO in the 2 wire serial I O mode In the 12C bus mode set bit 7 BSYE of the serial bus interface control register SBIC to 1 and write FFH to SIOO SIO0 becomes undefined at RESET Caution Do not execute an instruction that writes SIOO in the I2C bus mode while WUP bit 5 of serial operation mode register 0 CSIMO is 1 Even if such an instruction is not executed data can be received while the wake up function is being used WUP 1 For the details of the wake
333. k flag enables or disables the corresponding maskable interrupt processing and releasing the standby mode MKOL and MKOH are set by a 1 bit or 8 bit memory manipulation instruction When using MKOL and MKOH as a 16 bit register MKO it is set by a 16 bit memory manipulation instruction These registers are reset to FFH when the RESET signal is input Figure 18 3 Format of Interrupt Mask Flag Register Symbol lt 73 lt 6 gt lt 5 lt 4 lt 3 lt 2 lt 1 lt 0 Address Onreset R W MKOL PMK3 PMK2 PMKO FFE4H FFH R W 7 6 lt 5 gt 4 38 gt 22 lt td OD Note CEL A set Controls interrupt processing 0 Enables interrupt processing 1 Disables interrupt processing Note The WTMK controls enabling disabling the release of the standby mode It does not control interrupt function Cautions 1 The TMMK4 flag is undefined when it is read while the watchdog timer is used in the watchdog timer mode 1 2 Because port 0 is shared with external interrupt request inputs the corresponding interrupt request flag is set when the output mode is specified and output level of a port pin is changed To use the port in the output mode therefore set the corresponding interrupt mask flag to 1 in advance 3 Be sure to set bits 4 6 7 of MKOH to 1 407 i tinued CHAPTER 18 INTERRUPT FUNCTIONS AND TEST FUNCTIONS 3 Priority specification flag registers PROL PROH A priority specification flag sets the priori
334. laces in the internal ROM program Caution ROM correction cannot be emulated by an in circuit emulator IE 78000 R IE 78000 R A IE 78001 R A and IE 78KO NS 22 2 Configuration of ROM Correction ROM correction consists of the following hardware Table 22 1 Configuration of ROM Correction Configuration Register Correction address registers O and 1 CORADO and CORAD1 Control register Correction control register CORCN 453 i rN a lu ed CHAPTER 22 ROM CORRECTION Figure 22 1 shows the block diagram of ROM correction Figure 22 1 Block Diagram of ROM Correction Program counter PC Correction address register n CORADn Correction branch processing request signal BR F7FDH Coincidence Correction control CORENn register CORCN Remark n O 1 1 Correction address registers 0 and 1 CORADO and CORAD1 These registers set the first address correction address of the instruction in the mask ROM to be corrected ROM correction can correct up to two places in a program Therefore two addresses can be set in CORADO and CORAD1 To correct only one place put the address in either of the registers CORADO and CORADY1 are set by using a 16 bit memory manipulation instruction These registers are set to 0000H when the RESET signal is input Figure 22 2 Formats of Correction Address Registers 0 and 1 Symbol 45 0 Address On reset R W Cautions 1 S
335. latch Remark The output control circuit is shown enclosed by dotted line Figure 9 3 Block Diagram of 8 Bit Timer Event Counter Output Control Circuit 2 Level F F LV2 gt fsck i 2 TO2 P32 PM32 output latch Remarks 1 The output control circuit is shown enclosed by dotted line 2 fsck serial clock frequency 204 CHAPTER 9 8 BIT TIMER EVENT COUNTER 1 2 8 bit compare registers CR10 and CR20 These 8 bit registers always compare their set values with the count values of the 8 bit timer registers 1 and 2 TM1 and TM2 CR10 compares its set value with TM1 while CR20 compares its set value with TM2 When the value of a compare register coincides with the count value of the corresponding timer register the compare register generates an interrupt request INTTM1 or INTTM2 When TM1 or TM2 is used as an interval timer the corresponding compare register can also be used to hold interval time CR10 and CR20 are set by an 8 bit memory manipulation instruction and cannot be set by a 16 bit memory manipulation instruction When TM1 and TM2 are used as 8 bit timer event counters a value in a range of 00H FFH can be set to the corresponding compare registers When the two 8 bit timer event counters are used in combination as a 16 bit timer event counter a value in a range of 0OOOH FFFFH can be set to the two compare registers The contents of these registers become undefined wh
336. latch are output from the port pins The data once written to the output latch is retained until new data is written to the output latch In input mode The contents of the output latch become undefined However the status of the pin is not changed because the output buffer is OFF Caution A 1 bit memory manipulation instruction is executed to manipulate 1 bit of a port However this instruction accesses the port in 8 bit units When this instruction is executed to manipulate a bit of an input output port therefore the contents of the output latch of the pin that is set in the input mode and not subject to manipulation become undefined 155 i rir lv ed i rir lv ed CHAPTER 6 PORT FUNCTIONS 6 5 Mask Option The P60 P63 pins of the mask ROM model can be connected to an internal pull up resistor in 1 bit units by mask option No mask option is available for the PD78P018F 78P018FY and no internal pull up resistor is provided for P60 P63 pins 156 i rir lv ed CHAPTER 7 CLOCK GENERATION CIRCUIT 7 1 Function of Clock Generation Circuit The clock generation circuit generates the clock to be supplied to the CPU and peripheral hardware The following two types of system clock oscillation circuits are available 1 Main system clock oscillation circuit This circuit oscillates a frequency of 1 0 to 10 0 MHz Oscillation can be stopped by executing the STOP instruction or by setting the processor clock
337. lect register 3 TCL3 R W csim csim csim Operation SIO SBO P25 SO0 SB1 P26 SCKO0 P27 PM25 P25 PM26 P26 PM27 P27 First bit i 04 03 02 mode pin function pin function pin function 3 wire serial SIO Note 2 SOO SCKO O mode input CMOS output CMOS I O Note 3 Note 3 SB1 x x P25 CMOS I O _ N ch open drain 1 0 SCKO SBI mode CMOS I O Note 3 Note 3 SBO x x N ch open P26 CMOS 1 0 drain I O Note 3 Note 3 SB1 x x P25 CMOS 1 O N ch open 2 wire serial icin SCO O mode ce YO Note 3 Note 3 SBO x x N ch open P26 CMOS 1 0 drain I O R W Generates interrupt request signal in all modes each time serial transfer is executed Generates interrupt request signal when address received after bus has been released in SBI mode when CMDD RELD 1 coincides with data of slave address register R Data of slave address register SVA does not coincide with data of serial I O shift register O SIOO Data of slave address register SVA coincides with data of serial I O shift register O SIO0 R W CSIEO Controls operation of serial interface channel O Stops operation Enables operation Notes 1 Bit 6 COI is a read only bit 2 This pin can be used as P25 CMOS input when used only for transmission 3 This pin can be freely used for port function 4 Clear bit 5 SIC of the interrupt timing specification register SINT to 0 when using the wake up function WUP 1 5 COI is 0 when CSIEO 0 Rema
338. ler converts programs written in mnemonics into an object codes executable with a microcomputer Further this assembler is provided with functions capable of automatically creating symbol tables and branch instruction optimization This assembler should be used in combination with an optical device file DF78014 lt Precaution when using RA78K 0 in PC environment gt This assembler package is a DOS based application It can also be used in Win dows however by using the Project Manager included in assembler package on Windows Part Number uSxxxxRA78K0O CC78K 0 C Compiler Package This compiler converts programs written in C language into object codes executable with a microcomputer This compiler should be used in combination with an optical assembler package RA78K 0 and device file DF78014 lt Precaution when using RA78K 0 in PC environment gt This C compiler package is a DOS based application lt can also be used in Win dows however by using the Project Manager included in assembler package on Windows Part Number SxxxxCC78K0 DF78014Note Device File This file contains information peculiar to the device This device file should be used in combination with an optical tool RA78K 0 CC78K 0 SM78K0 ID78KO NS and ID78KO0 Corresponding OS and host machine differ depending on the tool to be used with Part Number uSxxxxDF78014 CC78K 0 L C Library Source File This is a source file o
339. lization time by program and then select the main system clock 171 MEMO 172 CHAPTER 8 16 BIT TIMER EVENT COUNTER 8 1 Outline of Timers in uPD78018F 78018FY Subseries This chapter explains the 16 bit timer event counter For reference an outline of the timers provided in the HPD78018F 78018FY subseries is shown below 1 16 bit timer event counter TMO This timer can be used as an interval timer for PWM output for pulse width measurement infrared remote controller signal reception function as an external event counter and for output of square waves of any frequency 2 8 bit timer event counters TM1 and TM2 These counters can be used as interval timers external event counters and for output of square waves of any frequency Moreover the two 8 bit timer event counters can be used in combination as a 16 bit time event counter refer to CHAPTER 9 8 BIT TIMER EVENT COUNTER 3 Watch timer TM3 This timer can be used to set a flag every 0 5 second or to generate an interrupt request at any time intervals set in advance at the same time refer to CHAPTER 10 WATCH TIMER 4 Watchdog timer WDTM The watchdog timer can also be used to generate a non maskable interrupt request maskable interrupt request or RESET signal at any time intervals set in advance refer to CHAPTER 11 WATCHDOG TIMER 5 Clock output control circuit This circuit supplies a clock obtained by dividing the main system clock and the
340. llows PD78018F subseries uPD78011F 78012F 78013F 78014F 78015F 78016F 78018F 78P018F uPD78011F A 78012F A 78013F A 78014F A 78015F A 78016F A 78018F A 78P018F A 78012F A2 e uPD78018FY subseries uPD78011FY 78012FY 78013FY 78014FY 78015FY 78016FY 78018FY 78P018FY Caution Of the u PD78018F and 78018FY subseries the u PD78P018FDW 78P018FKK S 78P018FYDW and 78P018FYKK S do not have a reliability intended for mass production of your systems Use these models for experiment or function evaluation only This manual is designed to deepen your understanding of the following functions using the following organization Two manuals are available for the PD78018F and uPD78018FY subseries this manual and Instruction Manual common to the 78K 0 series 1PD78018F 78018FY subseries User s Manual This manual 78K 0 series User s Manual Instruction e Pin functions e CPU function Internal block functions Instruction set e Interrupt e Instruction description Other internal peripheral functions How to Read This Manual It is assumed that the readers of this manual have general knowledge on electric engineering logic circuits and microcomputers If this manual is used as the manual of the uPD78011F A 78012F A 78013F A 78014F A 78015F A 78016F A 78018F A or 78P018F A Unless otherwise specified the yPD78011F 78012F 78013F 78014F
341. lock CPU Processing Interval Time With multiplication instruction used 13Tcru MIN With division instruction used 20Tcru MIN External access 1 wait mode 9Tcru MIN Others 7Tcru MIN Tcpu_ 1 fcru fcru CPU clock set by bits 0 through 2 PCCO through PCC2 of processor clock control register PCC CHAPTER 18 INTERRUPT FUNCTIONS AND TEST FUNCTIONS 18 1 Types of Interrupt Functions The following three types of interrupt functions are available 1 2 3 Non maskable interrupts This interrupt is unconditionally accepted even in the interrupt disabled status It is not subject to interrupt priority control and therefore takes precedence over all interrupt requests This interrupt generates a standby release signal The non maskable interrupts have one interrupt request source from the watchdog timer Maskable interrupts These interrupts are subject to mask control and can be divided into two groups according to the setting of the priority specification flag register PROL PROH one with higher priority and the other with lower priority Higher priority interrupts can nest lower priority interrupts The priority when two or more interrupt requests with the same priority occur at the same time is predetermined refer to Table 18 1 This interrupt generates a standby release signal As the maskable interrupts four external interrupt request sources and eight internal interrupt request sour
342. ls PA 78P018CW PA 78P018GC PA 78P018GK PA 78P018KK S PROM Programmer Adapter B 2 2 Software PG 1500 Controller PROM programmer adapter for wPD78P018F and 78P018FY and con nected to PG 1500 PA 78P018CW PA 78P018GC PA 78P018GK PA 78P018KK S for 64 pin plastic shrink DIP 750 mil for 64 pin plastic QFP GC AB8 type for 64 pin plastic LQFP GK 8A8 type for 64 pin ceramic WQFN KK S type Connects the PG 1500 to the host machine with a serial or parallel interface and controls the PG 1500 on the host machine The PG 1500 controller is a DOS based application It should be used in the DOS Prompt when using in Windows Part Number uSxxxxPG1500 Remark xxxx in the part number differs depending on the host machine and OS used HSxxxxPG1500 PC 9800 series Host Machine Supply Medium MS DOS 3 5 inch 2HD FD Ver 3 30 to Ver 6 2Note IBM PC AT and its compatibles Refer to B 4 3 5 inch 2HC FD Note MS DOS ver 5 0 or above has a task swap function but this function cannot be 500 used with the above software APPENDIX B DEVELOPMENT TOOLS B 3 Debugging Tools B 3 1 Hardware 1 2 1 When using the in circuit emulator IE 78K0 NS IE 78KO NSNote In circuit Emulator The in circuit emulator serves to debug hardware and software when developing application systems using a 78K 0 Series product It corresponds to integrated debugger ID78K0 NS This emulato
343. mm Standard uUPD78015FCW XXX 64 pin plastic shrink DIP 750 mil Standard HPD78015FGC XXX AB8 64 pin plastic QFP 14 x 14 mm Standard UPD78015FGK XXX 8A8 64 pin plastic LQFP 12 x 12 mm Standard uPD78016FCW XXX 64 pin plastic shrink DIP 750 mil Standard uUPD78016FGC XXX AB8 64 pin plastic QFP 14 x 14 mm Standard uUPD78016FGK XXX 8A8 64 pin plastic LQFP 12 x 12 mm Standard uPD78018FCW XXX 64 pin plastic shrink DIP 750 mil Standard HPD78018FGC XXX AB8 64 pin plastic QFP 14 x 14 mm Standard uUPD78018FGK XXX 8A8 64 pin plastic LQFP 12 x 12 mm Standard uPD78P018FCW 64 pin plastic shrink DIP 750 mil Standard HPD78P018FDW 64 pin ceramic shrink DIP with window 750 mil Not applicable HPD78P018FGC AB8 HPD78P018FGK 8A8 HPD78P018FKK S Caution Of the uwPD78P018FDW 78P018FKK S do not have a reliability intended for mass production of 64 pin plastic QFP 14 x 14 mm 64 pin plastic LQFP 12 x 12 mm 64 pin ceramic WQFN 14 x 14 mm for function evaluation Standard Standard Not applicable for function evaluation your systems Use these models for experiment or function evaluation only Remark XXX indicates ROM code suffix Please refer to Quality Grades on NEC Semiconductor Devices Document No C11531E published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications 38 CHAPTER 1 GENERAL uPD78018F SUBSERIES 2 Standard grade products
344. mode is to execute data transmission reception in 8 bit units by the specified number of times like in the 3 wire serial I O mode Serial transfer is started by writing any data to the serial I O shift register 1 SIO1 when the bit 7 CSIE1 of the serial operation mode register 1 CSIM1 is set to 1 When the last byte has been completely transmitted an interrupt request flag CSIIF1 is set Note however that the completion of automatic transmission reception should be determined with the bit 3 TRF of the automatic transmit receive control register ADTC instead of CSIIF1 When busy or strobe control is not performed the P23 STB and P24 BUSY pins can be used as ordinary I O port pins Figure 17 8 shows the operation timing of the basic transmit receive mode and Figure 17 9 shows an operation flowchart The buffer RAM operation when six bytes are transmitted received is shown in Figure 17 10 Figure 17 8 Operation Timing of Basic Transmit Receive Mode Interval SCK1 Q sor forfoeXosyoafosXo24oifoo e7fpsposiosibspozioripo A sm _ pozppsfesposppsppejorfpo ezfpsposposfosfpzpprppy CSIIF1 i TRF t Cautions 1 In the basic transmit receive mode the buffer RAM is written read after 1 byte data has been transmitted received Therefore there is interval time until the next transmission reception is executed Because the buffer RAM is written read simul taneously with the CPU processing the maximum interval time depends on the CPU p
345. n Is Used when BUSYO 0 eee 394 17 20 Busy Signal and Wati Release when BUSYO 0 eeceeeceeeeeeseeeeeeeeeneeeeaeeeneeeeeeteeeeeaes 395 17 21 Operation Timing when Busy and Strobe Control Options Are Used When BUSY0 0 c 6 ccc ta eee ed teen diene A oa ds 396 28 LIST OF FIGURES 6 7 Figure No Title Page 17 22 Operation Timing of Bit Shift Detection Function by Busy Signal when BUSYO 1 397 17 23 Interval Time of Automatic Transmission ReCeption cooncccinniccnnnncnnnonnnnnnrncnnnnannnnarnnnnnn nn 398 17 24 Operation Timing when Automatic Transmit Receive Function ls Used with internal ClO CK sts ences evs natal 400 18 1 Basic Configuration of Interrupt FUNCTION eee eeceeeneeeeeeeeeeeeeeeeeaeeeaeeteaeeeeeeeaeeteaeeeaeersaee 403 18 2 Format of Interrupt Request Flag Registers 00 0 ee eeeeseeeseneeeeeeeeeeeaeeeseneeeeesaeeseeneeereaeeees 406 18 3 Format of Interrupt Mask Flag Register oconoocconoccccnoncccnnocnnnncncnnnnrnnonana corno n cn cnn one rnnncnnnn nn 407 18 4 Format of Priority Specification Flag Register ooonnccnnicinnicnccnnccnoccnnocnconncnarnconccnnrnnnnc cnn 408 18 5 Format of External Interrupt Mode Register oooocccnnnccconoccnonoccnonanononananonnnn cnn nano nc rnrrnnnnn nn 409 18 6 Format of Sampling Clock Select Register oooooonccnnnccnnccconccnoccconcconcnnanccn nan cnrc cnn rra rn 410 18 7 I O Timing of Noise Eliminating Circuit when rising edge is detected
346. n LED These port pins are also multiplexed with an address bus that is used in the external memory extension mode This port is set in the input mode when the RESET signal is input Figure 6 13 shows the block diagram of port 5 Figure 6 13 Block Diagram of P50 P57 Voo SENA Output latch P50 P57 n 3 a oO E oO 2 PM50 PM57 A LC De P50 A8 O P57 A15 PUO pull up resistor option register PM port mode register RD read signal of port 5 WR write signal of port 5 146 FU TW ad CHAPTER 6 PORT FUNCTIONS O Inuec 6 2 8 Port 6 This is an 8 bit I O port with output latch P60 P67 pins can be specified in the input or output mode in 1 bit units by using the port mode register 6 PM6 This port can be connected with pull up resistors as described in the following table The number of bits in units of which the pull up resistor can be connected differs depending on whether the high order or low order 4 bits of the port are involved and also depending on whether the product is ROM or PROM model Table 6 4 Pull Up Resistors in Port 6 Esso High order 4 Bits P64 P67 pins Low order 4 Bits P60 P63 pins Mask ROM model Internal pull up resistor can be connected in Internal pull up resistor can be connected in 1 bit 4 bit units by PUO6 units by mask option PROM model Internal pull up resistor is not connected PUO
347. n completed once an interrupt request INTAD is generated 14 2 Configuration of A D Converter The A D converter consists of the following hardware Table 14 1 Configuration of A D Converter Item Configuration Analog input 8 channels ANIO ANI7 Control register A D converter mode register ADM A D converter input select register ADIS Register Successive approximation register SAR A D conversion result register ADCR 245 902 Figure 14 1 Block Diagram of A D Converter Internal bus A D converter input select register ADIS3 ADIS2 ADIS1 ADISO ANIO P10 ANI1 P11 ANI2 P12 ANI3 P13 ANI4 P14 ANI5 P15 ANI6 P16 ANI7 P17 Series resistor string Sample and hold circuit pS ae Voltage comparator SelectorNote 1 SelectorNote 2 Successive approximation register SAR ADM1 ADM3 Falling edge INTP3 P03 O detection gt INTAD circuit circuit gt INTP3 Trigger enable 3 A D conversion oe nei ii TA oe ADCR A D converter mode register Internal bus Notes 1 Selector that selects the number of channels used for analog input 2 Selector selecting a channel for A D conversion YSALYSANOO C V tl YSLdVHO CHAPTER 14 A D CONVERTER 1 2 3 4 5 6 Successive approximation register SAR This register compares the voltage value
348. n naar cnc nan nnrnrnnnnns 234 12 1 Application Example of Remote Controller Output ooococnncinnccnnnicincnnccconcnnnnncnnncnancnnnncrancnns 237 12 2 Block Diagram of Clock Output Control Circuit c oooooonncinnininninnnccnconnccanncnn arca nnrcrnrncnnrccnrccnnn 238 12 3 Format of Timer Clock Select Register O ooonnnnnicinnicnccnncinoncconcnnoncnonnncnrnnnnnncnncc nan ncancnnnnnnns 239 12 4 Format of Port Mode Register B oooonnccinncccnnocccononcnnnanononanononnon cnn nano nn nano nn n nr n tinaaa aiit 240 13 1 Block Diagram of Buzzer Output Control Circuit ooocccnnccnnccnccnnncnnocnconnnccnnanccnncnrarcnnnncnn 241 13 2 Format of Timer Clock Select Register B oooncccnccinnccnccnociccccconcncnnnnnnnnnnrnnnnnncnncn nan ccancnnnnnnns 243 13 3 Format of Port Mode Register 3 oo eeseesesceeeeseeeeeeeeeeeeeeeaeeeeesaeeeseaeeeseaeeeeesaeeeeeneeeseneeees 244 14 1 Block Diagram of A D Converter eeceecceeeceeeeeeeneeeeeeeneeeeaeeteeeeeaeeseaeeeaeeseaeetaeeseaeesieeenanenies 246 14 2 Format of A D Converter Mode Register oooococcconcciocccoccccocnconcconncnonnnoncncnnccnnnc conc nnnnccanccnnnnnns 249 14 3 Format of A D Converter Input Select Register oooooooincccnicinncconccnocnnonccnornconcn nan nn nnnnnnncnnn cn 250 14 4 Basic Operation of A D Converter cncocccccnccnocicocccnonnnancnnnnn conc nanc rn cnn cnn cnn 252 14 5 Relations between Analog Input Voltage and A D Conversion ReSUlt oooococoniococinocccccnncos 253 14 6 A D Conversion by Hardwar
349. n use conditions Further Renesas Electronics products are not subject to radiation resistance design Please be sure to implement safety measures to guard them against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas Electronics product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other appropriate measures Because the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or system manufactured by you Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances including without limitation the EU RoHS Directive Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations This document may not be reproduced or duplicated in any form in whole or in part without prior written consent of Renesas Electronics Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics
350. nal memory 39552 x 8 bits 0080H 007FH Program 6000H CALLT table area memory 5FFFH space 0040H Internal ROM peers 24576 x8 bits Vector table area y 0000H 0000H 93 CHAPTER 5 CPU ARCHITECTURE Figure 5 4 Memory Map uPD78014F 78014FY Special function register SFR 256 x 8 bits General purpose register 32 x 8 bits Internal high speed RAM 1024 x 8 bits FBOOH 7FFFH FAFFH Reserved Program area FAEOH Zata eat FADEH Internal buffer RAM 1000H ec 32 x 8 bits OFFFH FACOH FABFH CALLF entry area Reserved 0800H a FA80H 07FFH A FA7FH Program area External memory 31360 x 8 bits 0080H 007FH Program 8000H memory SEEEN CALLT table area space 0040H Internal ROM 00h 32768 x 8 bits Vector table area Y Y 0000H 0000H 94 CHAPTER 5 CPU ARCHITECTURE Figure 5 5 Memory Map uPD78015F 78015FY AH Special function register SFR 256 x 8 bits General purpose register 32 x 8 bits Internal high speed RAM 1024 x 8 bits FBOOH FAFFH 9FFFH Reserved FAEOH Program area FADFH Data memory ee ee RAM 1000H space FACOH Tui OFFFH FABFH Reserved CALLF entry area F800H F7FFH 0800H Internal extension RAM O7FFH 512 x 8 bits F600H Program area A F5FFH External memory 0080H 22016 x 8 bits 007FH A000H CALLT table area ed 9FFFH 40H space 003FH Internal ROM 40380 ss Vector table area Vv yi 0000H 0000H
351. nction of the uPD78018F and 78018FY is used 465 CHAPTER 23 uPD78P018F 78P018FY Figure 23 1 Format of Memory Size Select Register Symbol 7 1 0 Address Onreset R W IMS RAM2 do ie ROM3 ROM2 ROM1 ROMO FFFOH CFH WwW ROMO Selects internal ROM capacity 8 KB 16 KB 24 KB 32 KB 40 KB 48 KB 56 KBNote 60 KB Setting prohibited 0 Selects internal high speed RAM capacity 512B 1024B Others Setting prohibited Note Set the internal ROM capacity to 56K bytes or less when using the external device extension function of the uwPD78018F 78018FY 78P018F or 78P018FY The set value of IMS to map the memory of the wPD78P018F and 78P018FY in the same manner as that of the mask ROM model is shown in Table 23 2 Table 23 2 Set Value of Memory Size Select Register Set value of IMS uPD78011F 78011FY HPD78012F 78012FY HPD78013F 78013FY HPD78014F 78014FY HPD78015F 78015FY HPD78016F 78016FY HPD78018F 78018FY 466 CHAPTER 23 uPD78P018F 78P018FY 23 2 Internal Extension RAM Size Select Register The internal extension RAM of the uPD78P018F and 78P018FY can be mapped in the same manner as the memory map of a mask ROM model with a different sized internal extension RAM by setting the internal extension RAM size select register IXS IXS of a mask ROM model does not need to be set IXS is set by an 8 bit memo
352. nd make the SCL pin low The serial clock is not output if CLC remains 1 When the master outputs the start condition or stop condition make sure that CLD is 1 after CLC has been set to 1 This is because a slave may make SCL low wait status Figure 16 23 Output of Start Condition SCL SDAO SDA1 CLC CMDT CLD i ar lu ed CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78018FY S 2 Releasing slave from wait status slave transmission A slave is released from the wait status when the WREL flag bit 2 of the interrupt timing specification register SINT is set or when an instruction that writes data to serial I O shift register O SIOO is executed When the slave transmits data it is immediately released from the wait status when the instruction that writes data to SIOO is executed and the clock rises without the first transmit bit output to the data line It is therefore necessary to transmit the data by manipulating the output latch of P27 by the program as shown in Figure 16 24 At this time control the low level width portion a in Figure 16 24 of the first serial clock with the timing when P27 s output latch is set to 1 after the instruction that writes data to SIOO has been executed If the master does not output an acknowledge signal when data has been transmitted from a slave set the WREL flag of SINT to 1 to release the slave from the wait status For the timing of these operations refer to Figure 16 22
353. nd visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots Special Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircrafts aerospace equipment submersible repeaters nuclear reactor control systems life support systems or medical equipment for life support etc The quality grade of NEC devices is Standard unless otherwise specified in NEC s Data Sheets or Data Books If customers intend to use NEC devices for applications other than those specified for Standard quality grade they should contact an NEC sales representative in advance Anti radioactive design is not implemented in this product M7 96 5 al a nued Inuec Regional Information Some information contained in this document may vary from country to country Before using any NEC product in your application please contact the NEC office in your country to obtain a list of authorized representatives and distributors They will verify e Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications for example specifications for third party tools and components host computers power plugs AC supply voltages and so fo
354. ng is performed at the cycle selected by the sampling clock select register SCS The value of TMO is not captured until the valid edge is detected two times Consequently noise that may be superimposed on a pulse with a short pulse width can be eliminated Figure 8 14 Configuration of Pulse Width Measurement by Free Running 16 bit timer register TIMO OVFO fx 2 gt fx 2 gt 2 gt a 16 bit capture register CRO1 TIO POO INTPO Internal bus gt INTPO 192 CHAPTER 8 16 BIT TIMER EVENT COUNTER Figure 8 15 Pulse Width Measurement Timing by Free Running with both rising and falling edges specified t t l M l l IO CY o SW A I TIO pin input JA ft l 1 193 i ri oY a lv ed CHAPTER 8 16 BIT TIMER EVENT COUNTER 2 Pulse width measurement by restarting timer The pulse width of the signal input to the TIO POO pin is measured by clearing TMO and restarting counting after the count value of the 16 bit timer register TMO has been captured to the 16 bit capture register CRO1 when the valid edge is detected on the TIO POO pin Three types of edges can be selected by bits 2 and 3 ES10 and ES11 of INTMO rising falling and both rising and falling edges To detect the valid edge sampling is performed at the cycle selected by the sampling clock select register SCS The value of TMO is not
355. nnnnn conc cnn nan ran cnn rca 370 17 8 Operation Timing of Basic Transmit Receive Mode oococcciccnncniconncnicnnacnncnnccannr ana teeteaetenes 380 17 9 Flowchart of Basic Transmit Receive Mode c oocococcccnonccccnoncnononcnnnonononanononnon nn cnn o nn rnnnnnnnnn nens 381 17 10 Buffer RAM Operation when 6 Bytes Are Transmitted Received in basic transmit receive mode ocooccccnnnccnnnnoncnannononnnncnnnnnncnnnnn cnn annonces 383 17 11 Operation Timing of Basic Transmit Mode occococccnccnnccconccnnccconcnnnnncnnnn non cc nnnnnanc cnn nn rana nana 384 17 12 Flowchart of Basic Transmit Mode c ooocooccccncocccnoncnonnonnnnnnrnnonnnonnnnon cnn nan nnn ran n cn nan nr enn rra rnnnnnns 385 17 13 Buffer RAM Operation when 6 Bytes Are Transmitted in basic transmit mode 387 17 14 Operation Timing of Repetitive Transmit Mode eeccececeeeeeeeeeeeeeeeeeeeaeeeeeeseeeseaeeeaeenee 388 17 15 Flowchart of Repetitive Transmit Mode oooonccnnnnccnnoncccnnonncononcnnnannncnnnn nor nrn conan cnn nan nnnnn rn 389 17 16 Buffer RAM Operation when 6 Bytes Are Transmitted in repetitive transmit MOUS s2ci c cpcheceedsckeng shedessdsdesasecegcsfasaddeanadacshdesshscsicnetvans ici 391 17 17 Stopping and Resuming Automatic Transmission ReCeption oooocncccinccincccnncnnonccnncnnnnnnnns 392 17 18 System Configuration when Busy Control Option Is Used ecceeceeeeeeeeeeeeeseeeeeteeeneeeees 393 17 19 Operation Timing when Busy Control Optio
356. not used 86 CHAPTER 4 PIN FUNCTIONS uPD78018FY SUBSERIE 4 2 11 RESET This pin inputs an active low system reset signal 4 2 12 X1 and X2 These pins are used to connect a crystal resonator for main system clock oscillation To supply an external clock input the clock to X1 and input the inverted signal to X2 4 2 13 XT1 and XT2 These pins are used to connect a crystal resonator for subsystem clock oscillation To supply an external clock input the clock to XT1 and input the inverted signal to XT2 4 2 14 Voo Positive power supply pin 4 2 15 Vss Ground pin 4 2 16 Vpr uPD78P018FY only A high voltage should be applied to this pin when the PROM programming mode is set and when the program is written or verified Directly connect this pin to Vss in the normal operation mode 4 2 17 IC mask ROM model only The IC Internally Connected pin is used to set the wPD78011FY 78012FY 78013FY 78014FY 78015FY 78016FY and 78018FY in the test mode before shipment In the normal operation mode directly connect this pin to the Vss pin with as short a wiring length as possible If the wiring length between the IC pin and Vss pin is too long or if a potential difference is generated between the IC pin and Vss pin because an external noise is superimposed on the IC pin user s program may not run correctly Directly connect the IC pin to the Vss pin Keep short 87 CHAPTER 4 PIN FUNCTIONS uPD78018FY SUBSERIE
357. nstructions 16 instructions 16 instructions 16 instructions 77 instructions fx 8fxr instruction 8 instructions 8 instructions 8 instructions 8 instructions j 39 instructions fx 16fxt instructions 4 instructions 4 instructions 4 instructions 4 instructions 20 instructions fx 32fxr instructions 10 instructions 2 instructions 2 instructions 2 instructions 2 instructions fx 64fxr instructions 1 instruction 1 instruction 1 instruction 1 instruction 5 instructions 1 instruction 1 instruction 1 instruction 1 instruction 1 instruction Caution Do not select the division ratio of the CPU clock PCC0 PCC2 and switch the main system clock to the subsystem clock CSS 0 gt 1 at the same time However the division ratio of the CPU clock PCCO PCC2 can be selected and the subsystem clock can be switched to the main system clock at the same time CSS 1 gt 0 Remarks 1 One instruction is the minimum instruction execution time of the CPU clock before switching 2 fx 10 0 MHz fxt 32 768 kHz 170 i a Wi red CHAPTER 7 CLOCK GENERATION CIRCUIT 7 6 2 Switching between system clock and CPU clock The following figure illustrates how the system clock is switched to the CPU clock or vice versa Figure 7 8 Switching between System Clock and CPU Clock RESET Interrupt request signal System clock fx fx fxr fx CPU clock a Fastest Subsy
358. nterface control register SBIC 00H Slave address register SVA Undefined Automatic data transmit receive control register ADTC 00H Automatic data transmit receive interval specification register ADTI 00H Automatic data transmit receive address pointer ADTP 00H Interrupt timing specification register SINT 00H A D converter Mode register ADM 01H Conversion result register ADCR Undefined Input select register ADIS 00H ROM correction Correction address register CORADO CORAD1 Note 0000H Correction control register CORCN Note 00H Interrupt Request flag register IFOL IFOH 00H Mask flag register MKOL MKOH FFH Priority specification flag register PROL PROH FFH External interrupt mode register INTMO 00H Key return mode register KRM 02H Sampling clock select register SCS 00H Note Provided to yPD78015F 78015FY 78016F 78018F 78018FY 78016FY 78P018F 78P018FY only 452 CHAPTER 22 ROM CORRECTION 22 1 Function of ROM Correction The uwPD78015F 78015FY 78016F 78016FY 78018F and 78018FY can execute a part of the program in the mask ROM replacing it with the program in the internal extension RAM By using ROM correction instruction bugs found in the mask ROM can be avoided or the flow of the program can be changed ROM correction can be used in up to two p
359. nternal 1 sources Software 1 Test input Internal 1 external 1 Supply voltage Voo 1 8 to 5 5 V Operating ambient temperature Ta 40 to 85 C Package e 64 pin plastic shrink DIP 750 mil 64 pin plastic QFP 14 x 14 mm 64 pin plastic LQFP 12 x 12 mm Note 64 pin ceramic shrink DIP with window 750 mil yPD78P018FY only 64 pin ceramic WQFN 14 x 14 mm uwPD78P018FY only Note uPD78011FY 78012FY 78014FY and 78018FY only 2 9 Mask Option The mask ROM models uPD78011FY 78012FY 78013FY 78014FY 78015FY 78016FY and 78018FY have a mask option By specifying the mask option when placing your order the pull up resistors shown in Table 2 1 can be connected By using the mask option when a pull up resistor is necessary the number of components and the mounting area can be reduced Table 2 1 shows the mask option for the wPD78018FY subseries Table 2 1 Mask Option for Mask ROM Model Mask Option P60 P63 Pull up resistors can be connected in 1 bit units 65 MEMO 66 CHAPTER 3 PIN FUNCTIONS uPD78018F SUBSERIES 3 1 List of Pin Functions 3 1 1 Pins in normal operation mode 1 Port pins 1 2 Pin Name Function On Reset Shared by Port 0 Input only INTPO TIO 5 bit I O port Can be specified for input output bitwise INTP1 When used as input port internal pull up resistor can be connected by software P03 INTP3 po4Note 1 Input only XT1
360. o output control signals in the external memory extension mode P60 through P63 can directly drive LEDs Port 6 can be set in the following operation modes in 1 bit units 1 2 Port mode In this mode P60 through P67 constitute an 8 bit 1 O port which can be set in the input or output mode in 1 bit units by using the port mode register 6 PM6 P60 through P63 are N ch open drain pins These pins of the mask ROM model can be connected to an internal pull up resistor by mask option When using P64 through P67 as input port pins an internal pull up resistor can be used if so specified by the pull up resistor option register PUO Control mode In this mode P60 through P67 functions as control signal output pins RD WR WAIT and ASTB in the external memory extension mode The pins used as control signal output pins are automatically disconnected from the internal pull up resistor Caution Ifthe external wait state is not used in the external memory extension mode P66 can be used as an I O port pin 4 2 8 AVREF This pin inputs a reference voltage to the A D converter Connect this pin to Vss when the A D converter is not used 4 2 9 AVDD This is the analog power supply pin of the A D converter Keep this pin at the same voltage as the Voo pin even when the A D converter is not used 4 2 10 AVss This is the ground pin of the A D converter Keep this pin at the same voltage as the Vss pin even when the A D converter is
361. o the internal pull up resistor with mask option Figure 6 17 Format of Pull Up Resistor Option Register Symbol 7 lt 6 gt lt 1 gt lt 0 gt Address On reset R W lt b gt lt b gt lt 3 gt lt 2 gt PUO PUO6 PUO5 PUO4 PUO3 PUO2 PUO1 PUOO FFF7H 00H R W Selects internal pull up resistor of Pm m 0 1 2 3 4 5 6 0 Internal pull up resistor is not used 1 Internal pull up resistor is used CHAPTER 6 PORT FUNCTIONS 3 Memory extension mode register MM This register sets port 4 in the input or output mode MM is set by a 1 bit or 8 bit memory manipulation instruction This register is set to 10H when the RESET signal is input Remark MM also has functions to set the number of wait states and an external extension area in addition to the function to set the input output mode of port 4 Figure 6 18 Format of Memory Extension Mode Register Symbol 7 6 5 4 0 Address On reset R W 3 2 1 MM 0 0 PW1 PWO 0 MM2 MM1 MMO FFF8H 10H R W Selects single chip P40 P47 P50 P57 P64 P67 pin status memory extension mode 49 p47 P50 P53 P54 P55 P56 P57 P64 P67 Port Put mode Out put Port mode Single chip mode 256 B mode P64 RD 4 KB Port mode a Memory mode P65 WR extension ADO AD7 O Port mode mode P67 ASTB ee A14 A15 Setting prohibited No wait Wait 1 wait state inserted S
362. occconccconcconnncnnccnnnnnancnnnnn conca nnnn conca nnn nan nn ran ca nacen 445 20 4 Operation after Release of STOP Mode c oooccccccoccconccconcconnncnncnoncncnnnnnnnc cnn cnnnnn nan nana n cnn nn narcos 447 21 1 Status of Each Hardware after Reset c oooccconccncccnccccoccnnoccnnnnnoncnnnnn nan cn nn n conc crac cnn nn nanc nana 451 22 1 Configuration of ROM Correction ccecceesceseseeeeeeeeeeeeneeeeaeeeeeeseaeeeeeeseaeeseeeenaeesiaeseaeesneeeas 453 23 1 Differences between wuPD78P018F 78P018FY and Mask ROM Models c ccoococccccccnccco 464 23 2 Set Value of Memory Size Select Register oooonocincccnccicconocccnncnnonnnnonnnanccnnnn cnc cnnnncana nana 466 23 3 Set Value of Internal Extension RAM Size Select Register ooooonnnccinccninconnccccccnonncnnccnnnnnnno 467 23 4 Operation Modes for PROM Programming c cceeceeeceeeeeeeeeeeeneeeeaeeeeeeeaeeseeeteaeeteaeeeeete 468 24 1 Operand Representation and Formats ccesceceseeseeeeeeeeeeeeeeeeeneeeeaeeeneeseaeeeeeeseaeeseaeeeaeeee 478 A 1 Major Differences Between uPD78014 78014H and 78018F Subseries oocicicinconncccnn 493 B 1 System up Method from Former In circuit Emulator for 78K 0 Series to the JE 7800 E a a EEA O T TE Aaa 505 33 MEMO 34 i ar Iv ed CHAPTER 1 GENERAL uPD78018F SUBSERIES 1 1 Features e High capacity ROM and RAM Program Memory Data Memory Part Number ROM Internal High Speed RAM Internal Extension RAM Internal B
363. ock oscillation frequency 2 At fx 10 0 MHz operation 317 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78018FY SUBSERI7 Symbol 73 R W Figure 16 3 Format of Serial Operation Mode Register 0 Clock externally input to SCKO SCL pin Address cono coro en en a o csimo1 csimoo Selects clock of serial interface channel O On reset 00H R W R W Note 1 Output of 8 bit timer register 2 TM2 Note R W Clock specified by bits 0 3 of timer clock select register 3 TCL3 CSIM CSIM CSIM PM25 P25 PM26 P26 PM27 P27 04 03 02 Operation mode 3 wire serial O mode First bit S10 SBO P25 pin function SI0 Note 3 input SO0 SB1 P26 pin function soo CMOS output SCKO0 P27 pin function SCKO CMOS I O R W Note 4 Note 4 x x x Note 4 Note 4 x 2 wire serial 1 0 mode or 12C bus mode P25 CMOS 1 0 SB1 SDA1 N ch open drain I O SBO SDAO N ch open drain I O P26 CMOS 1 0 Generates interrupt request signal in all modes each time serial transfer is executed SCKO SCL N ch open drain I O Generates interrupt request signal when address received after start condition is detected in 1 C bus mode when CMDD 1 coincides with data of slave address register SVA Data of slave address register SVA does not coincide with data of serial I O shift register O S100 R W Data o
364. of External Interrupt Mode Register Symbol 7 6 5 4 3 2 1 0 Address On reset R W INTMO ES31 ES30 ES21 ES20 ES11 ES10 bea FFECH 00H R W ES11 ES10 Selects valid edge of INTPO Falling edge Rising edge Setting prohibited Both rising and falling edges Falling edge Rising edge Setting prohibited Both rising and falling edges Falling edge Rising edge Setting prohibited Both rising and falling edges Caution Before setting the valid edge of the INPO TIO POO pin clear the bits 1 through 3 TMC01 through TMC03 of the 16 bit timer mode control register to 0 0 0 and stop the timer operation 186 i ri oY a lv ed CHAPTER 8 16 BIT TIMER EVENT COUNTER 6 Sampling clock select register SCS This register sets the clock with which the valid edge input to INTPO is to be sampled When a remote controller signal is eliminated by using INTPO digital noise is eliminated by sampling clock SCS is set by an 8 bit memory manipulation instruction This register is set to OOH when the RESET signal is input Figure 8 9 Format of Sampling Clock Select Register Symbol 7 6 0 Address On reset R W 5 4 3 2 1 ese To To To ToDo esis ren oman SCS1 SCSO Selects sampling clock of INTPO fx 2N 1 Setting prohibited fx 28 156 kHz fx 27 78 1 kHz Caution fx 2N 1 is the clock supplied to the CPU and fx 26 and fx 2
365. of analog input with the value of a voltage tap compare voltage from the series resistor string and holds the result of the comparison starting from the most significant bit MSB When the result is held down to the least significant bit LSB end of A D conversion the contents of SAR are transferred to the A D conversion result register ADCR A D conversion result register ADCR This register holds the result of A D conversion result Each time A D conversion has been completed the result of the conversion is loaded to this register from the successive approximation register ADCR can be read by an 8 bit memory manipulation instruction The contents of this register become undefined when the RESET signal is input Sample and hold circuit The sample and hold circuit samples analog input signals sequentially sent from the input circuit on a one by one basis and sends the sampled signals to the voltage comparator This circuit holds the sampled analog input voltage value during A D conversion Voltage comparator The voltage comparator compares the analog input with the output voltage of the series resistor string Series resistor string The series resistor string is connected between AVrer and AVss and generates a voltage to be compared with an analog input ANIO ANI7 pins These are eight channels of analog input pins of the A D converter They input analog signals that are converted to digital values Pins other than thos
366. oftware Execution of BRK instruction Notes 1 The default priority is used when two or more maskable interrupt requests occur at the same time 0 is the highest and 11 is the lowest priority 2 Basic configuration types A to E respectively correspond to A to E on the following pages 402 CHAPTER 18 INTERRUPT FUNCTIONS AND TEST FUNCT Figure 18 1 Basic Configuration of Interrupt Function 1 2 Internal bus A Internal non maskable interrupt Vector table Interrupt address request generation circuit Standby release signal B Internal maskable interrupt Internal bus Vector table address generation circuit Interrupt request Priority control circuit Standby release signal C External maskable interrupt INTPO Sampling clock External interrupt select register mode register SCS INTMO Interrupt Sampling eos oe request clock circui Vector table address generation circuit Standby release signal 403 CHAPTER 18 INTERRUPT FUNCTIONS AND TEST FUNCTIONS Figure 18 1 Basic Configuration of Interrupt Function 2 2 D External maskable interrupt except INTPO External interrupt mode register INTMO Edge detection circuit Interrupt request a Vector table Priority Cael address circul generation circuit Standby release signal E Software interr
367. om the buffer RAM to serial I O shift register 1 SIO1 after arbitrary data has been written to SIO1 start trigger this data is not transferred When the first byte has been completely transmitted receive data 1 R1 is transferred from SIO1 to buffer RAM and automatic data transmit receive address pointer ADTP is decremented Subsequently transmit data 2 T2 is transferred from buffer RAM to SIO1 When 4th byte is transmitted received Refer to Figure 17 10 b When the third byte has been transmitted received completely transmit data 4 T4 is transferred from the buffer RAM to SIO1 When the fourth byte has been transmitted receive data 4 R4 is transferred from SIO1 to buffer RAM and ADTP is decremented End of transmission reception Refer to Figure 17 10 c When the sixth byte has been transmitted receive data 6 R6 is transferred from SIO1 to the buffer RAM and an interrupt request flag CSIIF1 is set INTCSI1 occurs CHAPTER 17 SERIAL INTERFACE CHANNEL 1 Figure 17 10 Buffer RAM Operation when 6 Bytes Are Transmitted Received in basic transmit receive mode a Before transmission reception FADFH FAC5H Transmit data 1 T1 Transmit data 2 T2 a sete Transmit data 3 T3 LAG arto Transmit data 4 T4 Sha Transmit data 5 T5 FACOH Transmit data 6 T6 4 o CSIIF1 b When 4th byte has been transmitted received FADFH FAC5H Receive data 1 R1 z Receive data 4 R
368. oman Shift register Serial clock S11 P20 SO1 P21 SCK1 P22 count operation 5 p 1 operation control pin function pin function pin function Note 1 Note 1 Note 1 Note 1 Note 1 Operation P20 P21 P22 xixixi x x disabled CMOS 1 0 CMOS I O CMOS I O SCK1 Note 2 Note 2 Operation Count S 1Note 2 sot input 1 x enabled operation input CMOS output SCKi CMOS output Notes 1 These pins can be used freely as port pins 2 P20 CMOS I O is used when only transmission is executed Clear bit 7 RE of the automatic data transmit receive control register ADCT to 0 Remark x Don t care PMxx Port mode register Pxx Output latch of port 370 CHAPTER 17 SERIAL INTERFACE CHANNEL 1 17 4 2 Operation in 3 wire serial I O mode This mode is useful for connecting peripheral I Os and display controllers that have the conventional clocked serial interface of the 75X XL series 78K series and 17K series In this mode communication is established by using three signal lines serial clock SCK1 serial output SO1 and serial input SI1 1 Register setting The 3 wire serial I O mode is set by using the serial operation mode register 1 CSIM1 CSIM1 is set by a 1 bit or 8 bit memory manipulation instruction This register is set to OOH when the RESET signal is input Symbol 7 6 lt 5 4 3 Address On reset R W 2 1 0 com Fee on ae o Jo To onfa o om aw Selec
369. omatic Data Transmit Receive Control Register Symbol lt 7 lt 6 lt 5 4 3 lt 2 lt 1 lt 0 gt Address Onreset R W ADTC ARLD ERCE STRB BUSY1BUSYO FF69H 00H R WNote 1 Does not use busy input Enables busy input high active Enables busy input low active STRB Controls strobe output 0 1 Disables strobe output Enables strobe output Detects end of automatic transmission reception set to 0 when automatic transmission reception is aborted or when ARLD 0 Automatic transfer reception is in progress set to 1 when this bit is written to SIO1 No error during automatic transmission reception set to 0 when this bit is written to SIO1 Error during automatic transmission reception Controls error check of automatic transmit receive 0 Disables error check during automatic transmission reception Enables error check during automatic transmission reception only when BUSY1 1 Selects operation mode of automatic transmit ARLD P receive function 0 1 Single mode Repeated mode Controls reception of automatic transmit receive function Disables reception Enables reception Notes 1 Bits 3 and 4 TRF and ERR are read only bits 2 The completion of automatic transmission reception should be determined with TRF instead of CSIIF1 interrupt request flag Caution Set STRB and BUSY1 of ADTC to 0 0 when external clock input i
370. on Positive power supply High voltage application for program write verify Directly connect this pin to Vss in normal operation mode Ground Internally connected Directly connect to Vss 4 1 2 Pins in PROM programming mode uPD78P018FY only Pin Name Function Sets PROM programming mode When 5 V or 12 5 V is applied to Ver pin and low level is input to RESET pin PROM programming mode is set Applies high voltage when setting PROM programming mode and when writing verifying program Address bus Data bus PROM enable input program pulse input Read strobe input to PROM Program program inhibit input in PROM programming mode Positive power supply Ground 82 CHAPTER 4 PIN FUNCTIONS uPD78018FY SUBSERIE 4 2 Description of Pin Functions 4 2 1 P00 P04 Port0 These pins constitute a 5 bit I O port port 0 In addition these pins are also used to input external interrupt request signals an external count clock to timer a capture trigger signal and to connect a crystal resonator for subsystem clock oscillation Port O can be specified in the following operation modes in 1 bit units 1 2 Port mode In the port mode POO and P04 function as input port lines and P0O1 through P03 function as I O port lines P01 through PO3 can be set in the input or output port mode in 1 bit units by using port mode register 0 PMO When these pins
371. on Memory address specified by the register pair DE The contents of the addressed memory are transferred 7 0 i 129 CHAPTER 5 CPU ARCHITECTURE 5 4 8 Based addressing Function This addressing mode is used to address the memory by using the result of adding 8 bit immediate data to the contents of the HL register pair as a base register The HL register pair to be accessed is in the register bank specified by the register bank select flags RBSO and RBS1 The addition is executed by extending the offset data to a 16 bit positive number A carry from the 16th bit is ignored if any This addressing mode can be used across the entire memory space Operand Format arr Example MOV A HL 10H To specify 10H as byte Instruction code 10101110 00010000 130 CHAPTER 5 CPU ARCHITECTURE 5 4 9 Based indexed addressing Function This addressing mode is used to address the memory by using the result of adding the contents of the B or C register specified in the instruction word to the HL register pair as a base register The HL B and C registers to be accessed are in the register bank specified by the register bank select flags RBSO and RBS1 The addition is executed by extending the contents of the B or C register to a 16 bit positive number A carry from the 16th bit is ignored if any This addressing mode can be used across the entire memory space Operand Format mane Example
372. on This register is set to OOH when the RESET signal is input Remark TCL2also has a function to set the count clock of the watch timer and the count clock of the watchdog timer in addition to the function to set the frequency of buzzer output 242 CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT gt Symbol Figure 13 2 Format of Timer Clock Select Register 2 Address Onreset R W 7 6 5 4 3 2 1 0 TCL2 TCL27 TCL26 TCL25 ToL24 o prerez TCL21 TCL20 FF42H 00H R W TCL21 TCL20 Selects count clock of watchdog timer fx 24 625 kHz fx 25 313 kHz fx 28 156 kHz fx 27 78 1 kHz fx 28 39 1 kHz fx 29 19 5 kHz fx 2 0 9 8 kHz 1x 212 2 4 kHz TCL24 Selects count clock of watch timer 0 fx 28 39 1 kHz fxt 32 768 kHz TCL26 TCL25 Selects frequency of buzzer output Buzzer output disabled fx 210 9 8 kHz fx 211 4 9 kHz fx 212 2 4 kHz Setting prohibited Caution Before writing data other than that already written to TCL2 stop the timer operation Remarks 1 2 3 4 fx fxT x O Main system clock oscillation frequency Subsystem clock oscillation frequency Don t care At fx 10 0 MHz or fxt 32 768 kHz operation 243 CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT 2 Port mode register 3 PM3 This register sets the input output mode of port 3 in 1 bit units When the P36 BUZ pin is used as a b
373. on 1 Low active Enables inversion LVSO LvRo Sets status of timer output F F of 16 bit timer event counter Not affected Resets timer output F F to 0 Sets timer output F F to 1 Setting prohibited Cautions 1 Be sure to stop the timer operation before setting TOCO 2 0 is read from LVSO and LVRO after data has been set to these bits 184 i tinued CHAPTER 8 16 BIT TIMER EVENT COUNTER 4 Port mode register 3 PM3 This register sets the input output mode of port 3 in 1 bit units When the P30 TO0 pin is used as a timer output pin set O to the PM30 bit of this register and the output latch of the P30 pin PMS is set by a 1 bit or 8 bit memory manipulation instruction This register is set to FFH when the RESET signal is input Figure 8 7 Format of Port Mode Register 3 Symbol 7 6 5 4 Address On reset R W PM3 PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30 FF23H FFH R W Selects I O mode of P3n pin n 0 7 0 Output mode output buffer ON Input mode output buffer OFF 185 CHAPTER 8 16 BIT TIMER EVENT COUNTER 5 External interrupt mode register INTMO This register sets the valid edges of the INTPO INTP2 pins INTMO is set by an 8 bit memory manipulation register This register is set to OOH when the RESET signal is input Remarks 1 The INTPO pin is multiplexed with TI0 P00 2 INTP3 is fixed to the falling edge Figure 8 8 Format
374. on that clears this bit to 0 has been executed Outputs busy signal from falling edge of clock of SCKO following acknowledge sig nal Note The busy mode can be released when transfer by the serial interface has been started However the BSYE flag is not cleared to 0 Remark CSIEO Bit 7 of the serial operation mode register 0 CSIMO 287 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 uPD78018F SUBSERI c Interrupt timing specification register SINT SINT is set by a 1 bit or 8 bit memory manipulation instruction This register is set to OOH when the RESET signal is input Symbol lt 6 gt lt 5 gt lt 4 Address On reset R W oor o ee e e e e e or maa R W SVAM Bits of SVA used as slave address channel 0 0 Bits 0 7 1 Bits 1 7 R W Selects interrupt source of INTCSIONote 2 Sets CSIIFO at end of transfer by serial interface Sets CSIIFO at end of transfer by serial interface channel 0 or on detection of bus release R Level of SCKO P27 pins Notes 0 Low level 1 High level Notes 1 Bit 6 CLD is a read only bit 2 Set SIC to 0 when using the wake up function in the SBI mode 3 CLD is 0 when CSIEO 0 Caution Be sure to set bits 0 through 3 to 0 Remark SVA Slave address register CSIIFO Interrupt request flag corresponding to INTCSIO CSIEO Bit 7 of the serial operation mode register 0 CSIMO 288 i tinued CHAPTER 15 SERIAL INTERFACE CHANNEL 0 uPD78018
375. oncconncconcnonnn ran cnn cnn arca rn nc rca rnc cnc 51 2 1 Mask Option for Mask ROM Model c ooocconccconcconoccconcconccconccinnncnnccnn cnn nn cnn cnn anna nn nr rca 65 3 1 VO Circuit Type of Each Piti 76 4 1 Circuit Type of Each a ET R E EAE 88 5 1 Internal ROM Capacity coccion deat ihe alin aaa aaea aaiae a eed 99 5 2 Vector Table nkan tid eid ete ed en ee a 99 5 3 Internal High Speed RAM Capacity cocccncccincccnccconcccnonanaccnoncnnnnc conc c non cnn cnn nr 100 5 4 Internal Extension RAM Capacity coccccincccocccnoccconccnonnconcconnncnnnnnnnn cnn nan nn cnn nar nc cnnc cnn cnn cnnnnas 100 5 5 Internal High Speed RAM Area c coocccocccncccnoccconcnonancnnanonancnncnrnncnnnc nro n cnn rre 103 5 6 Absolute Addresses of General Purpose Registers ococinnconnccnonccnonncacccnonnnancnnnnncnrnnnnncnancn 105 5 7 Special Function Register List eecceccesseesseeeeseeeeeeesseeeeaeeeeeeseseeseaeeeaeeseaeeseeeseaeeteaeeeaeetea 108 6 1 Port Functions uPD78018F Subseries ccooooncccincccncccnoccconccnoncnoncnnon ccoo cnn cnn cnn rra 134 6 2 Port Functions uPD78018FY Subseries ooooocccnccioncconcccncnnonccnncncnrnannn cnn ca nnnccnnc cnn cnc cnn 135 6 3 POM GonfiguratiO sita li id dr Ai 136 6 4 Pull Up Resistors in POr una i es Le ee 147 6 5 Setting of Port Mode Register and Output Latch when Multiplexed Function Is Used 150 7 1 Configuration of Clock Generation Circuit ceeceecceeeeeeeneeeeeeeeneeeeeeeeneeteaeeeeeseaeeseeeenaee
376. operation but holds data However the interrupt request flag RIFO is set by detection of the valid edge 16 bit timer register TMO This 16 bit register counts the number of count pulses The value of TMO can be read by a 16 bit memory manipulation instruction This register is initialized to 0000H when the RESET signal is input Caution Because the value of TMO is read via CRO1 the value of CRO1 is destroyed CHAPTER 8 16 BIT TIMER EVENT COUNTER 8 4 Registers Controlling 16 Bit Timer Event Counter The following six types of registers control the 16 bit timer event counter Timer clock select register 0 TCLO 16 bit timer mode control register TMCO e 16 bit timer output control register TOCO Port mode register 3 PM3 External interrupt mode register INTMO Sampling clock select register SCS 1 Timer clock select register 0 TCLO refer to Figure 8 4 This register sets the count clock of the 16 bit timer register TCLO is set by a 1 bit or 8 bit memory manipulation instruction This register is set to OOH when the RESET signal is input Remark TCLO also has a function to set the clock for PCL output in addition to the function to set the count clock of the 16 bit timer register 2 16 bit timer mode control register TMCO refer to Figure 8 5 This register sets an operation mode of the 16 bit timer clear mode of the 16 bit timer register and output timing and detects an overflow TMCO i
377. ort 5 146 P6 Port 6 147 PCC Processor clock control register 160 515 APPENDIX D REGISTER INDEX S T w 516 PMO PM1 PM2 PM3 PM5 PM6 PROH PROL PSW PUO SBIC SCS SINT S100 SIO1 SVA TCLO TCL1 TCL2 TCL3 TMO TM1 TM2 TMCO TMC1 TMC2 TMS TOCO TOC1 WDTM Port mode register 0 149 Port mode register 1 149 Port mode register 2 149 Port mode register 3 149 185 210 240 244 Port mode register 5 149 Port mode register 6 149 Priority specification flag register OH 408 Priority specification flag register OL 408 Program status word 102 412 Pull up resistor option register 152 Serial bus interface control register 268 377 286 305 319 325 330 339 Sampling clock select register 187 410 Interrupt timing specification register 270 288 305 321 330 340 Serial I O shift register 0 263 313 Serial I O shift register 1 362 Slave address register 263 313 Timer clock select register 0 181 238 Timer clock select register 1 206 Timer clock select register 2 222 232 242 Timer clock select register 3 265 316 363 16 bit timer register 180 8 bit timer register 1 205 8 bit timer register 2 205 16 bit timer mode control register 181 8 bit timer mode control register 208 Watch timer mode control register 225
378. ort are also used as the data I O pin clock I O pin busy signal input pin for automatic transmission reception and strobe signal output pin of the serial interface This port is set in the input mode when the RESET signal is input Figures 6 8 and 6 9 show the block diagrams of port 2 Cautions 1 When using the pins of port 2 as multiplexed pins the I O or output latch must be set according to the function to be used For how to set the latches refer to Figure 16 3 Format of Serial Operation Mode Register 0 and Figure 17 3 Format of Serial Operation Mode Register 1 2 To read the status of the pin in the SBI mode set PM2n to 1 n 5 6 Figure 6 8 Block Diagram of P20 P21 and P23 26 uPD78018FY Subseries Vo WReuo ES Dk j A Jog n aa WRport E i P20 SI1 E Output latch aa zA P20 P21 P23 P2 eee gt poapusy P25 SI0 SBO SDAO P26 SO0 SB1 SDA1 Multiplexed function PUO pull up resistor option register PM port mode register RD read signal of port 2 WR write signal of port 2 142 CHAPTER 6 PORT FUNCTIONS o 5 re oO E oO Lg Figure 6 9 Block Diagram of P22 and P27 uPD78018FY Subseries Voo WRreort PUO port mode register read signal of port 2 write signal of port 2 PM RD WR A A Output latch Sh e Pesca P27 SCKO SCL
379. outine can be directly called by using a 2 byte call instruction CALLF 99 i rN a lu ed CHAPTER 5 CPU ARCHITECTURE 5 1 2 Internal data memory space The uPD78018F 78018FY subseries have the following RAMs 1 Internal high speed RAM The uPD78018F and 78018FY subseries are provided with the following internal high speed RAM Table 5 3 Internal High Speed RAM Capacity Part Number Internal High Speed RAM HPD78011F 78011FY 512 x 8 bits FDOOH FEFFH HPD78012F 78012FY HPD78013F 78013FY 1024 x 8 bits FBOOH FEFFH HPD78014F 78014FY HPD78015F 78015FY 4PD78016F 78016FY HPD78018F 78018FY HPD78P018F 78P018FY A 32 byte area of addresses FEEOH FEFFH is assigned four banks of general registers Each bank consists of eight 8 bit registers The internal high speed RAM can also be used as a stack memory 2 Internal extension RAM Only the following products of the wPD78018F 78018FY subseries are provided with the following internal extension RAM Table 5 4 Internal Extension RAM Capacity Part Number Internal Extension RAM HPD78015F 78015FY 512 x 8 bits F600H F7FFH HPD78016F 78016FY HPD78018F 78018FY 1024 x 8 bits F400H F7FFH HPD78P018F 78P018FY 3 Internal buffer RAM To a 32 byte area of addresses FACOH FADFH an internal buffer RAM is allocated The internal buffer RAM is used to store the transmit receive data of the serial interface channel 1 3
380. outputs the clock selected by the timer clock select register O TCLO from the PCL P35 pin The clock pulse is output in the following procedure lt 1 gt Select the output frequency of the clock pulse by using bits 0 3 TCLOO TCLO3 of TCLO output of the clock pulse is disabled lt 2 gt Set 0 to the output latch of the P35 pin lt 3 gt Set 0 to bit 5 PM35 of the port mode register 3 to set the output mode lt 4 gt Set bit 7 CLOE of TCLO to 1 Caution When 1 is set to the output latch of the P35 pin clock output cannot be used Remark The clock output control circuit is designed not to output a narrow pulse when clock output is enabled or disabled refer to in Figure 12 1 Figure 12 1 Application Example of Remote Controller Output 237 i rN a lu ed CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT 12 2 Configuration of Clock Output Control Circuit The clock output control circuit consists of the following hardware Table 12 1 Configuration of Clock Output Control Circuit Control register Timer clock select register 0 TCLO Port mode register 3 PM3 Figure 12 2 Block Diagram of Clock Output Control Circuit fx 23 fx 2 fx 25 5 D Synchronization fx 2 2 circuit Mea D PCL P35 fx 27 6 fx 28 gt fxt gt 4 4 CLOE TCLO3 TCL02 TCLO1 TCLOO P35 output latch PM35 Timer clock select register 0 Port mode register 3
381. owing hardware Table 8 4 Configuration of 16 Bit Timer Event Counter Item Configuration Timer register 16 bits x 1 TMO Register Compare register 16 bits x 1 CROO Capture register 16 bits x 1 CRO1 Timer output 1 TOO Control register Timer clock select register 0 TCLO 16 bit timer mode control register TMCO 16 bit timer output control register TOCO Port mode register 3 PM3 External interrupt mode register INTMO Sampling clock select register SCS Note Note Refer to Figure 18 1 Basic Configuration of Interrupt Function 176 25 Figure 8 1 Block Diagram of 16 Bit Timer Event Counter Timer Mode Internal bus 16 bit compare register CROO Coincidence Coincidence X lt 1 gt INTTMO Note 2 gt 16 bit timer event counter output TOO P30 fy 2 control circuit fx 22 S 16 bit timer 16 bit timer 28 D register low order register high order OVF 3 8 bits TMOL 8 bits TMOH TIO POO INTPO Noter Clear A 3 0 15 16 bit capture register CR01 Internal bus l 1 gt INTPO NN EAN OVFO LVSO LVRO TOCO1 TOEO 16 bit timer mode 16 bit timer output control register control register Timer clock select register O pl TCLO6 TCLO5 TCLO4 Notes 1 Edge detection circuit 2 For the configuration of the output control circuit of the 16 bit timer event co
382. own is when the program is stored in the internal ROM area 3 n indicates the number of wait states when the external memory extension area is read 487 CHAPTER 24 INSTRUCTION SET Instruction Group Mnemonic Operand Operation Conditional saddr bit addr16 PC lt PC 4 jdisp8 if saddr bit 1 branch then reset saddr bit sfr bit addr16 PC lt PC 4 jdisp8 if sfr bit 1 then reset sfr bit A bit addr16 PC lt PC 3 jdisp8 if A bit 1 then reset A bit PSW bit addr16 24 PC lt PC 4 jdisp8 if PSW bit 1 then reset PSW bit HL bit addr16 24 2n 2m PC lt PC 3 jdisp8 if HL bit 1 then reset HL bit B addr16 B e B 1 then PC e PC 2 jdisp8 if B 0 C addr16 C e C 1 then PC PC 2 jdisp8 if C 0 saddr addr16 saddr saddr 1 then PC lt PC 3 jdisp8 if saddr 0 RBn RBS1 0 lt n No operation IE 1 Enable interrupt IE O Disable interrupt Set HALT mode Set STOP mode Notes 1 When the internal high speed RAM area is accessed or when an instruction that does not access data is executed 2 When an area other than the internal high speed RAM area is accessed Remarks 1 One clock of an instruction is equal to one CPU clock fcru selected by processor clock control register PCC 2 The number of clocks shown is when the program is stored in the internal ROM area 3 n
383. own is when the program is stored in the internal ROM area 3 n indicates the number of wait states when the external memory extension area is read 4 m indicates the number of wait states when the external memory extension area is written 480 CHAPTER 24 INSTRUCTION SET Instruction Group 8 bit data transfer Mnemonic Operand Operation Aer 12 A saddr 12 Ao sfr 20 2n 2m addr16 DE 12 2N 2m DE HL 12 2N 2m HL HL byte 20 2n 2m HL byte HL B 20 2n 2m HL B Be Oe le ee ea HL C 20 2n 2m As As As As As As HL C rp word rp lt word saddrp word 20 saddrp lt word sfrp word 20 sfrp lt word AX saddrp 16 AX lt saddrp saddrp AX 16 saddrp AX AX sfrp 16 AX lt sfrp sfrp AX MYI NI NINI AJI RR oO mM DM Pw 16 sfrp AX AX rp AX amp rp rp AX rp AX AX laddr16 AX addr16 laddr16 AX Ww ow addr16 AX AX rp AX rp 8 bit operation A byte A CY lt A byte saddr byte saddr CY saddr byte A r A CY lt eA r nA r CY er A A saddr A CY lt A saddr A laddr16 A CY lt A saddr16 A HL A CY lt A HL A HL
384. peee err o mn Selects oscillation stabilization time OT eens when released the STOP mode 213 fx 819 us 2 5 fx 3 28ms 2 7 tx 13 1ms 218 fx 26 2ms 216 fx 6 55ms Others Setting prohibited Caution The wait time when the STOP mode is released does not include the time required for the clock oscillation to start after the STOP mode has been released see a in the figure below regardless of whether the mode has been released by the RESET signal or an interrupt request STOP mode released Voltage waveform of X1 pin Vss Remarks 1 fx Main system clock oscillation frequency 2 At fx 10 0 MHz operation 440 CHAPTER 20 STANDBY FUNCTION 20 2 Operation of Standby Function 20 2 1 HALT mode 1 Setting and operation status of HALT mode The HALT mode is set by executing the HALT instruction This mode can be set regardless of whether the system has been operating on the main system clock or subsystem clock The operation status in the HALT mode is shown in the table below Table 20 1 Operation Status in HALT Mode 1 2 a When HALT instruction is executed while system operates on main system clock Setting of HALT Mode Without Subsystem ClockNote 1 With Subsystem ClockNote 2 Clock generation circuit Both main system clock and subsystem clock can oscillate Supply of clock to CPU is stopped CPU Stops operation Port output latch Reta
385. peration registers A and AX are specified by implied addressing 123 CHAPTER 5 CPU ARCHITECTURE 5 4 3 Register addressing Function This addressing mode is used to access a general purpose register as an operand The register to be accessed is specified by the register bank select flags RBSO and RBS1 and the register specification code Rn and RPn in the instruction code Register addressing is used when an instruction that has the following operand format is executed When an 8 bit register is specified one of the eight registers is specified by 3 bits in the instruction code Operand Format X A C B E D L H AX BC DE HL r and rp can be written not only in function name X A C B E D L H AX BC DE or HL but also in absolute name R0 R7 RPO RP3 Example MOV A C To select C register as r Instruction code 01100010 INCW DE To select DE register pair as rp Instruction code 10000100 Register specification code Register specification code 124 CHAPTER 5 CPU ARCHITECTURE 5 4 4 Direct addressing Function This addressing is directly to address a memory indicating the immediate data in an instruction word as an operand address Operand Format Representation Description Label or 16 bit immediate data Example MOV A OFEOOH To specify FEOOH as addr16 Instruction code 10001 1 1 0 OP code 000000 0 0 OOH 111111 1 0 FEH Operation
386. ply Voo before Vrr and turn it off after Vpr 2 Keep Vpp to within 13 5 V including the overshoot 3 If the Vrr is disconnected from the socket while 12 5 V is applied to it the reliability of the u4PD78P018F and 78P018FY may be degraded 473 CHAPTER 23 uPD78P018F 78P018FY 23 3 3 PROM read sequence The contents of the PROM can be read to the external data bus DO D7 in the following sequence 1 Fix the RESET pin to the low level Supply 5 V to the Ver pin Process the pins not used by referring to 1 5 or 2 5 Pin Configuration 2 PROM programming mode 2 Supply 5 V to the Vop and VPP pins 3 Input the address of the data to be read to the AO A16 pins 4 5 4 5 Read mode Data is output to the DO D7 pins Figure 23 7 shows the timing of steps 2 to 5 above Figure 23 7 PROM Read Timing A0 A16 Address input 474 CHAPTER 23 uPD78P018F 78P018FY 23 4 Erasure PD78P018FDW 78P018FKK S LPD78P018FYDW 78P018FYKK S The data written to the program memory of the wPD78P018FDW 78P018FKK S 78P018FYDW and 78P018FYKK S can be erased to FFH and new data can be rewritten to it To erase the data contents cast a light whose wavelength is shorter than approximately 400 nm onto the erasure window Usually an ultraviolet ray of 254 nm is used The light intensity and time required to completely erase the data contents are as follows e Intensity of ultraviolet ray x erasure time 30 We
387. pointer ADTP Control register Timer clock select register 3 TCL3 Serial operation mode register 1 CSIM1 Automatic data transmit receive control register ADTC Automatic data transmit receive interval specification register ADTI Port mode register 2 PM2 Note Note Refer to Figure 6 6 6 8 Block Diagram of P20 P21 P23 P26 and Figure 6 7 6 9 Block Diagram of P22 and P27 360 19 Figure 17 1 Block Diagram of Serial Interface Channel 1 Internal bus Automatic data transmit receive Buffer RAM Ko address pointer ADTP Internal bus Automatic data transmit receive interval specification register ADTIO ADTI4 Coincidence 5 bit counter Automatic data transmit receive control register SIE ATE CSIM CSIM 11 10 me E DIR DIR Serial 1 O shift SI1 P20 gt register 1 SIO1 PM21 SO1 P21 lt P21 output latch PM23 STB P23 lt Hand BUSY P24 al Serial clock counter D SCK1 P22 O gt Selector ARLD Serial operation mode register 1 gt INTCSI1 S101 write PM22 E a Cc P22 output latch TO2 a a re TCL TCL TCL TCL 37 36 35 34 Internal bus fx 22 fx 29 Timer clock select register 3
388. pply DO D7 Data Bus VPP Programming Power Supply OE Output Enable Vss Ground PGM Program 45 CHAPTER 1 GENERAL 1 PD78018F SUBSERIES 1 6 Product Development of 78K 0 Series The products in the 78K 0 series are listed below The names enclosed in boxes are subseries names L Products in mass production G Products under development Y subseries products are compatible with 1 C bus Control E 100 pin EMI noise reduced version of the uPD78078 100 pin uPD78078 A timer was added to the 4PD78054 and external interface was enhanced 100 pin HPD78070A HPD78070AY 2 ROM less version of the uPD78078 POP LVN Serial I O of the PD78078Y was enhanced and the function is limited 80 pin Serial I O of the yPD78054 was enhanced and EMI noise was reduced 80 pin EMI noise reduced version of the yPD78054 80 pin _ UART and D A converter were enhanced to the PD78014 and I O was enhanced 64 pin K Ae Ales de uPD780034Y FA A D converter of the PD780024 was enhanced 64 pin Ef uPD780024Y Serial I O of the uPD78018F was added and EMI noise was reduced 64 pin EMI noise reduced version of the w PD78018F 64 pin 1PD78018F Low voltage 1 8 V operation version of the PD78014 with larger selection of ROM and RAM capacities 64 pin An A D converter and 16 bit timer were added to the wPD78002 64 pin uPD780001 An A D converter was added to the PD78002 64 pin 1PD78002 Basic subseries
389. products or if you have any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics User s Manual uPD78018F 78018FY Subseries 8 bit Single chip Microcontroller uPD78011F PD78011FY PD78011F A uPD78012F uPD78012FY PD78012F A uPD78013F PD78013FY PD78013F A uPD78014F uPD78014FY PD78014F A uPD78015F PD78015FY PD78015F A uPD78016F PD78016FY PD78016F A uPD78018F PD78018FY PD78018F A uPD78P018F PD78P018FY uPD78P018F A uPD78012F A2 Document No U10659EJ5VOUMOO 5th edition Date Published January 1998 N CP K NEC Corporation 1994 Printed in Japan MEMO i rit od he NOTES FOR CMOS DEVICES PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note Strong electric field when exposed to a MOS device can cause destruction of the gate oxide and ultimately degrade the device operation Steps must be taken to stop generation of static electricity as much as possible and quickly dissipate it once when it has occurred Environmental control must be adequate When it is dry humidifier should be used It is recommended to avoid using insulators that easily build static electricity Semiconductor devices must
390. put mode A value can be written to the output latch of a port by using a transfer instruction The contents of the output latch can be output from the pins of the port The data once written to the output latch is retained until new data is written to the output latch In input mode A value can be written to the output latch by using a transfer instruction However the status of the port pin is not changed because the output buffer is OFF The data once written to the output latch is retained until new data is written to the output latch Caution A 1 bit memory manipulation instruction is executed to manipulate 1 bit of a port However this instruction accesses the port in 8 bit units When this instruction is executed to manipulate a bit of an input output port therefore the contents of the output latch of the pin that is set in the input mode and not subject to manipulation become undefined 6 4 2 Reading from I O port 1 2 In output mode The contents of the output latch can be read by using a transfer instruction The contents of the output latch are not changed In input mode The status of a pin can be read by using a transfer instruction The contents of the output latch are not changed 6 4 3 Arithmetic operation of I O port 1 2 In output mode An arithmetic operation can be performed with the contents of the output latch The result of the operation is written to the output latch The contents of the output
391. r should be used in combination with power supply unit emulation probe and interface adapter which is required to connect this emulator to the host machine IE 70000 MC PS B Power Supply Unit This adapter is used for supplying power from a receptacle of 100 V to 240 V AC IE 70000 98 IF CNote Interface Adapter This adapter is required when using the PC 9800 Series computer except notebook type as the IE 78KO NS host machine IE 70000 CD IFNote PC Card Interface This is PC card and interface cable required when using the PC 9800 Series notebook type computer as the IE 78KO NS host machine IE 70000 PC IF CNote Interface Adapter This adapter is required when using the IBM PC AT and its compatible computers as the IE 78K0 NS host machine IE 78018 NS EM1 Note Emulation Board This board emulates the operations of the peripheral hardware peculiar to a device It should be used in combination with an in circuit emulator NP 64GC Emulation Probe This probe is used to connect the in circuit emulator to the target system and is designed for 64 pin plastic QFP GC AB8 type EV 9200GC 64 Conversion Socket Refer to Figure B 2 This conversion socket connects the NP 64GC to the target system board designed to mount a 64 pin plastic QFP GC AB8 type Instead of connecting the NP 64GC the wPD78P018FKK S or 78P018FYKK S ceramic WQFN can also be connected NP 64GK Emulation Probe This probe i
392. ransmission has been completed normally If it is 0 it is judged that a transmission error has occurred 307 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 uPD78018F SUBSERIER al UNO 15 4 5 Manipulating SCK0 P27 pin output Because the SCK0 P27 pin is provided with an output latch it can also perform static output through software manipulation in addition to output through the ordinary serial clock By manipulating the P27 output latch the value of SCKO can be arbitrarily set by software the SIO SBO and SOO SB1 pins are controlled by the RELT and CMDT bits of serial bus interface control register SBIC The SCKO P27 pin output is manipulated as follows lt 1 gt Set the serial operation mode register O CSIMO SCKO pin output mode serial operation enabled SCKO 1 while serial transfer is stopped lt 2 gt Manipulate the P27 output latch by using a bit manipulation instruction Figure 15 33 Configuration of SCK0 P27 Pin Operated by bit manipulation instruction ann To internal SCKO P27 O gt circuit P27 output latch O a 1 when transfer is stopped When CSIEO 1 From serial clock and control circuit CSIMO1 CSIMOO are 1 0 or 1 1 308 al i nued i NUS CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78018FY SUBSERIES The uPD78018FY subseries is provided with two channels of clocked serial interfaces The differences between channels 0 and 1 are a
393. register 3 TCL3 R W_ esim csim csim Operation _ SI0 SBO P25 SOO SB1 P26 SCKO P27 PM25 P25 PM26 P26 PM27 P27 First bit i j 04 03 02 mode pin function pin function pin function 3 wire serial SlONote 2 SO0 SCKO 1 0 mode input CMOS output CMOS I O SBI mode Refer to 15 4 3 Operation in SBI mode 2 wire serial I O mode Refer to 15 4 4 Operation in 2 wire serial I O mode R W Controls wake up functionNote 3 0 Generates interrupt request signal in all modes each time serial transfer is executed Generates interrupt request signal when address received after bus has been released in SBI mode when CMDD RELD 1 coincides with data of slave address register SVA R W cstEo Controls operation of serial interface channel O Stops operation Enables operation Notes 1 Bit 6 COI is a read only bit 2 This pin can be used as P25 CMOS input when used only for transfer 3 Be sure to set WUP to 0 in the 3 wire serial I O mode Remark x Don t care PMxx Port mode register Pxx Output latch of port 272 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 uPD78018F SUF b Serial bus interface control register SBIC SBIC is set by a 1 bit or 8 bit memory manipulation instruction This register is set to OOH when the RESET signal is input Symbol lt 7 lt B gt lt 5 gt lt b gt lt lt 2 gt lt l gt lt 0 gt Address On reset R W 3 gt
394. register O SIOO Slave address register SVA Control register Timer clock select register 3 TCL3 Serial operation mode register 0 CSIMO Serial bus interface control register SBIC Interrupt timing specification register SINT Port mode register 2 PM2 Note Note Refer to Figure 6 8 Block Diagram of P20 P21 and P23 26 uPD78018FY Subseries and Figure 6 9 Block Diagram of P22 and P27 uPD78018FY Subseries 311 cle Figure 16 1 Block Diagram of Serial Interface Channel 0 Internal bus Serial bus interface control register Serial operation mode register 0 CSIE CSIM CSIM CSIM CSIM CSIM Slave address 03 02 register SVA BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT lt SVAM i BSYE Coincidence SZ CLRSET D Q A VO shift SIO0 Serial register 0 SI0 SB0 SDA0 P25 P25 output latch Acknowledge output circuit P26 output latch acknowledge detection circuit gt INTCSIO SCKO SCL P27 gt generation El E circuit Output control CSIMOO CSIMO1 CSIMOO CSIMO1 P27 output latch Timer clock select register 3 Interrupt timing specification register SSIMASAENS A481084Ud7 0 TANNVHO AJ0VSYALNI IVIHIS 91 YILAVHO Internal bus Remar
395. rk x Don t care PMxx Port mode register Pxx Output latch of port 267 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 uPD78018F SUBSERI 3 Symbol 5 gt 4 SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT FF61H 00H R W Note Serial bus interface control register SBIC This register sets the operation of the serial bus interface and indicates the status SBIC is set by a 1 bit or 8 bit memory manipulation instruction This register is set to 00H when the RESET signal is input Figure 15 4 Format of Serial Bus Interface Control Register 1 2 lt 7 gt lt b gt lt lt b gt lt 3 gt lt 2 gt lt l gt lt 0 gt Address On reset R W R W Used to output bus release signal SO0 latch is set to 1 when RELT 1 After setting SOO latch RELT is automatically cleared to 0 This bit is also cleared to O when CSIEO 0 R W Used to output command signal 268 SO0 latch is cleared to 0 when CMDT 1 After clearing SOO latch CMDT is automatically cleared to 0 This bit is also cleared to O when CSIEO 0 R RELD Bus release detection Clear condition RELD 0 Set condition RELD 1 When transfer start instruction is executed When values of SIOO and SVA do not coincide when address is received When bus release signal REL is detected When CSIEO 0 e When RESET is input R CMDD Command detection Clearing conditions CMDD 0 Setting condition CMDD 1 When transfer
396. rnal interrupt mode register INTMO The frequency of the sampling clock is selected by the sampling clock select register SCS 3 When using the PWM mode set the PWM mode and then set data to CROO 4 When a mode in which the 16 bit timer is cleared and started on coincidence between TMO and CROO is selected the OVFO flag is set to 1 when the value of TMO changes from FFFFH to 0000H with FFFFH set to CROO Remark TOO Output pin of 16 bit timer event counter TIO Input pin of 16 bit timer event counter TMO 16 bit timer register CROO 16 bit compare register 183 CHAPTER 8 16 BIT TIMER EVENT COUNTER 3 16 bit timer output control register TOCO This register controls the operation of the 16 bit timer event counter output control circuit It sets resets an R S flip flop LVO sets an active level in the PWM mode enables disables inversion of the output in a mode other than PWM mode and sets a data output mode TOCO is set by a 1 bit or 8 bit memory manipulation instruction This register is set to 00H when the RESET signal is input Figure 8 6 Format of 16 Bit Timer Output Control Register Symbol 7 6 TOCO 5 4 lt 3 gt lt 2 gt 1 lt 0 gt Address Onreset R W TOEO Controls output of 16 bit timer event counter 0 Disables output port mode 1 FF4EH 00H R W Enables output PWM mode Other than PWM mode TOCO1 Selects active level Controls timer output F F 0 High active Disables inversi
397. rocessing and a value of the automatic data transmit receive interval specification register ADTI refer to 5 Interval time of automatic transmission reception 2 When TRF is cleared the SO1 pin goes low Remark CSIIF1 Interrupt request flag TRF Bit 3 of the automatic transmit receive control register ADTC 380 CHAPTER 17 SERIAL INTERFACE CHANNEL 1 Figure 17 9 Flowchart of Basic Transmit Receive Mode Writes transmit data to buffer RAM Sets value of number of transmit data bytes minus 1 to ADTP pointer value Software execution Sets interval time for transmit receive operation to ADTI Writes any data to SIO1 start trigger Writes transmit data from buffer RAM to SIO1 Transmit receive operation Decrements pointer value Hardware execution Writes received data from SIO1 to buffer RAM Pointer value 0 gt Software execution ee AA ADTP Automatic data transmit receive address pointer ADTI Automatic data transmit receive interval specification register SIO1 Serial I O shift register 1 TRF Bit 3 of automatic data transmit receive control register ADTC 381 CHAPTER 17 SERIAL INTERFACE CHANNEL 1 382 The buffer RAM operates as follows when 6 bytes are transmitted received in the basic transmit receive mode ARLD 0 RE 1 i ii iii Before transmission reception Refer to Figure 17 10 a Transmit data 1 T1 is transferred fr
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399. rsion is immediately started In this way A D conversion is repeatedly executed until new data is written to ADM If data whose CS is 1 is written again to ADM during A D conversion the conversion under execution is stopped and the A D conversion of the newly written data is started If data whose CS is 0 is written to ADM during A D conversion the conversion is immediately stopped Figure 14 7 A D Conversion by Software Start Conversion start Rewriting ADM Rewriting ADM CS 1 TRG 0 CS 1 TRG 0 CS 0 TRG 0 A D conversion ANIn ANIn ANIn ANIm ANIm y Conversion is stopped A Conversion result Stopped is not retained INTAD Remark n 0 1 7 m 0 1 7 255 al UNO CHAPTER 14 A D CONVERTER 14 5 Notes on A D Converter 1 Current consumption in standby mode The A D converter operates on the main system clock Therefore its operation is stopped in the STOP mode or in the HALT mode on the subsystem clock Even at this time a current flows into the AVrer pin and it is necessary to cut this current in order to reduce the current consumption of the entire system In the case shown in Figure 14 8 below the current consumption can be reduced if a low level is output to the output ports in the standby mode However the actual AVrer voltage is not accurate and therefore the conversion value itself is not accurate but can be used for relative comparison only Figure 14 8 E
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401. ruction Caution Be sure to clear bit 3 to 0 Remarks 1 fx main system clock oscillation frequency 2 fxr subsystem clock oscillation frequency 3 minimum instruction execution time at fx 10 0 MHz or fxt 32 768 kHz 4 fcru 160 CHAPTER 7 CLOCK GENERATION CIRCUIT The fastest instruction of the uPD78018F 78018FY subseries is executed within four CPU clocks Therefore the relation between the CPU clock fcru and minimum instruction execution time is as shown in Table 7 2 Table 7 2 Relation between CPU Clock and Minimum Instruction Execution Time CPU Clock fcru Minimum Instruction Execution Time 4 fceu fx 10 0 MHz fxt 32 768 kHz fx Main system clock oscillation frequency fxt Subsystem clock oscillation frequency 161 i rir lv ed CHAPTER 7 CLOCK GENERATION CIRCUIT 7 4 System Clock Oscillation Circuits 7 4 1 Main system clock oscillation circuit The main system clock oscillation circuit is oscillated by the crystal or ceramic resonator 10 0 MHz TYP connected across the X1 and X2 pins An external clock can also be input to the circuit In this case input the clock signal to the X1 pin and input the reversed signal to the X2 pin Figure 7 4 shows the external circuit of the main system clock oscillation circuit Figure 7 4 External Circuit of Main System Clock Oscillation Circuit a Crystal or ceramic oscillation b External clock Pree toe Se
402. rval Timer oooconnccnnoncccnnnancnononcnnonnncnnrn non onn cnn nan nr rra narrar nena 236 12 1 Configuration of Clock Output Control Circuit 2 0 eee eeeeeeeeeeeeeeeeeeseeeseeeeeaeeseaeeeeeeeetees 238 13 1 Configuration of Buzzer Output Control Circuit oooooonccninccinccconccnonnnnncncnnnnnnancancn nara nana cnn 241 14 1 Configuration of A D Converter ici rai 245 15 1 Differences between Channels 0 and 1 0 eeeceeeceeeceeeeeeeeeeeeeeeeeeeeaeeseeeeeaeeseaeeseeseaeeseeeenaees 259 15 2 Differences in Modes of Serial Interface Channel 0 cceeceeesceseeeeeteeeeeeeeeeeeeeteaeeeeeeeeaeen 260 15 3 Configuration of Serial Interface Channel 0 0 cee eeeceeeeeeceeeeeeeeeeeeeeeeeeeeeeseeeeeeeseaeeeeeee 261 15 4 Signals I SBli MOS essa esc sce eat agaceciestesace dida epica 293 16 1 Differences between Channels 0 and 1 o eeeeeseceeeeeeeeeeeeeeeeeeeeeeeaeeseeeeeaeeseaeeeeeseaeeseeeeeaees 309 16 2 Differences in Modes of Serial Interface Channel O eeceeseeeseeeeeeeeeeeseneeeeeeteaeeeeeeeeaten 310 16 3 Configuration of Serial Interface Channel 0 0 eeeceeeeeseeeeeeeeeeeeeaeeeeeeeeaeeeeeeeeeeseaeeeeeee 311 16 4 Generation of Interrupt Request Signal by Serial Interface Channel 0 eceeeeeee 315 16 5 Signals ini l4 Bus Mode sui iii 343 17 1 Modes of Serial Interface Channel 1 oo ec eeeceseeceeeeeeeeeceeeeeeeeeeeeeeaeeeeeseaeeseeeseaeeseaeeeeeeaaee 359 17 2 Configuration of Serial Interface Channel 1 oo eeeceeeeceseeeeeeeeeeeeeee
403. ry manipulation instruction This register is set to OAH when the RESET signal is input Caution To use a mask ROM model do not set a value other than those listed in Table 23 3 to IXS Figure 23 2 Format of Internal Extension RAM Size Select Register Symbol 7 6 1 0 Address On reset R W 5 4 3 2 IX IX IX IX IX Selects internal extension RAMO RAM capacity 1024 B F400H F7FFH 512 B F600H F7FFH 0B Others Setting prohibited The set value of IXS to map the internal extension RAM of the wPD78P018F and 78P018FY in the same manner as that of the mask ROM model is shown in Table 23 3 Table 23 3 Set Value of Internal Extension RAM Size Select Register Value at reset HPD78011F 78011FY HPD78012F 78012FY HPD78013F 78013FY HPD78014F 78014FY HPD78015F 78015FY HPD78016F 78016FY HPD78018F 78018FY 467 CHAPTER 23 uPD78P018F 78P018FY 23 3 PROM Programming The uPD78P018F and 78P018FY are provided with 60 KB PROM as a program memory This memory is set in the PROM programming mode when it is programmed by using the Vpr and RESET pins When these pins are not used process them by referring to 1 5 or 2 5 Pin Configuration 2 PROM programming mode Caution Write a program to the program memory in an address range of 0000H to EFFFH specify the last address EFFFH The program cannot be written with a PROM programmer that cannot specify a write
404. s Always keep the ground of the capacitor of the oscillation circuit at the same potential as Vss Do not ground the capacitor to a ground pattern through which a high current flows Do not extract a signal from the oscillation circuit Note that the amplification factor of the subsystem clock oscillation circuit is kept low to reduce the current consumption Figure 7 6 shows incorrect examples of resonator connection Figure 7 6 Incorrect Examples of Resonator Connection 1 2 a Too long wiring b Crossed signal line PORTn n 0 6 X2 X1 IC Remark X1 and X2 in this figure should be XT1 and XT2 when the subsystem clock is used Connect a resistor to XT2 in series 163 CHAPTER 7 CLOCK GENERATION CIRCUIT Figure 7 6 Incorrect Examples of Resonator Connection 2 2 c Wiring near high alternating current d Current flowing through ground line of oscillation circuit potential at points A B and C fluctuates Voo Pnm X2 Xd IC X2 X1 IC High current JA 8 c High current 777 777 e Signal is fetched ILI if gu 777 Remark When using a subsystem clock replace X1 and X2 with TX1 and TX2 respectively Also insert resistors in series on the XT2 side Caution 2 InFigure 7 8 f XT2 and X1 are wired in parallel Thus the cross talk noise of X1 may increase with XT2 resulting in malfunctioning To prevent that from occurring it is recommended to
405. s Bit manipulation set reset test Boolean operation BCD correction etc 1 0 port Total CMOS input CMOS I O 53 lines 2 lines 47 lines Port lines to which internal pull up resistor can be connected via software 47 lines N ch open drain I O 4 lines 15 V pull up resistor can be connected by mask option to mask ROM model only 4 lines A D converter 8 bit resolution x 8 channels Low voltage operation AVpp 1 8 to 5 5 V Serial interface 3 wire serial O SBI 2 wire serial I O mode selectable 1 channel 3 wire serial I O mode with automatic transmit receive function of up to 32 B 1 channel 1 channel 2 channels 1 channel 1 channel 16 bit timer event counter 8 bit timer event counter e Watch timer Watchdog timer Timer output 3 lines 14 bit PWM output 1 line Clock output 39 1 kHz 78 1 kHz 156 kHz 313 kHz 625 kHz 1 25 MHz with main system clock 10 0 MHz 32 768 kHz with subsystem clock 32 768 kHz Buzzer output Notes 1 2 4 kHz 4 9 kHz 9 8 kHz with main system clock 10 0 MHz The capacities of the internal PROM and internal high speed RAM can be changed by using memory size select register IMS select register IXS The capacity of the internal extension RAM can be changed by using internal extension RAM size 49 CHAPTER 1 GENERAL 1 PD78018F SUBSERIES Part Number HPD78011F 1PD78012F uPD78013F uPD78014F uPD78015F
406. s pin to Vss in normal operation mode Ground Internally connected Directly connect to Vss 3 1 2 Pins in PROM programming mode uPD78P018F only Pin Name Function Sets PROM programming mode When 5 V or 12 5 V is applied to Ver pin and low level is input to RESET pin PROM programming mode is set Applies high voltage when setting PROM programming mode and when writing verifying program Address bus Data bus PROM enable input program pulse input Read strobe input to PROM Program program inhibit input in PROM programming mode Positive power supply Ground 70 CHAPTER 3 PIN FUNCTIONS uPD78018F SUBSERIEY 3 2 Description of Pin Functions 3 2 1 P00 P04 Port0 These pins constitute a 5 bit I O port port 0 In addition these pins are also used to input external interrupt request signals an external count clock to timer a capture trigger signal and to connect a crystal resonator for subsystem clock oscillation Port O can be specified in the following operation modes in 1 bit units 1 2 Port mode In the port mode POO and P04 function as input port lines and P0O1 through P03 function as I O port lines P01 through PO3 can be set in the input or output port mode in 1 bit units by using port mode register 0 PMO When these pins are used as an input port an internal pull up resistor can be used if so specified by the pull up resistor
407. s Used when BUSYO 0 SCK1 XD7XD6XD5XD4XD3XD2XD1XDo Ab7ADOXDS ADOS AD2ADi ADO A Xo7XdeXDsXo4XosXp2XoiXoo_ AD7ADSADSADAXD3XD2AD1XD0 BUSY 3 T e E CSIIF1 A Clears busy input SO S A at ica Busy input is valid TRF Caution If the TRF is cleared the SO1 pin goes low Remark CSIIF1 Interrupt request flag TRF Bit 3 of automatic data transmit receive control register ADTC When the busy signal becomes inactive waiting is released If the sampled busy signal is inactive transmission reception of the next 8 bit data is started at the falling edge of the next clock Because the busy signal is asynchronous with the serial clock it takes up to 1 clock until the busy signal even if made inactive by the slave is sampled It takes 0 5 clock until data transfer is started after the busy signal was sampled To accurately release waiting the slave must keep the busy signal inactive at least for the duration of 1 5 clock Figure 17 20 shows the timing of the busy signal and releasing the waiting This figure shows an example where the busy signal is active as soon as transmission reception has been started i ri oY a lv ed SCK1 sor __Ko7XdeXosXoaXosXo2Xo1Xoo0_ Xo7XDeXDsXD4XD3XD2XD1 DO sh _ AD7DSADSAD4AD3AD2AD1ADO XD7ADSXDSADAXD3AD2AD1 ADO A sy ih in Bie nian If made inactive r ic immediately after or sampled Wait Fike Busy input released E eee Busy input
408. s automatically cleared to 0 It is also cleared to 0 when CSIEO 0 R RELD Detects stop condition Clearing conditions RELD 0 Setting condition RELD 1 e On execution of transfer start instruction e When stop condition is detected in 1 C bus mode e If values of SIOO and SVA do not coincide on address reception e When CSIEO 0 e On RESET Cont d Note Bits 2 3 and 6 RELD CMDD and ACKD are read only bits Remark CSIEO Bit 7 of the serial operation mode register 0 CSIMO 339 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78018FY SUBSERI7 R CMDD Detects start condition Clearing conditions CMDD 0 Setting condition CMDD 1 e On execution of transfer start instruction e On detection of start condition in 12 bus mode e On detection of stop condition in 1 C bus mode e When CSIEO 0 e On RESET R W Makes SDAO SDA1 low immediately after execution of setting instruction ACKT 1 until falling edge of next SCL Used to generate ACK signal by software when 8 clock wait is selected Cleared to 0 when serial interface starts transfer or when CSIEO 0 R W ACKE Controls automatic output of acknowledge signal Note1 Disables automatic output of acknowledge signal output by ACKT is possible Used for transmission or reception with 8 clock wait selected Note 2 Enables automatic output of acknowledge signal Outputs acknowledge signal in synchronization with fallin
409. s cm2 min e Erasure time 40 minutes or longer with an ultraviolet lamp of 12 mW cm However the erase time may be extended if the performance of the ultraviolet lamp is degraded or if the erasure window is dirty To erase the data place the ultraviolet lamp at a distance of within 2 5 cm from the erasure window If a filter is attached to the ultraviolet lamp remove the filter before casting ultraviolet ray 23 5 Erasure Window Sticker uwPD78P018FDW 78P018FKK S UPD78P018FYDW 78P018FYKK S To protect from accidental erasure by light sources other than that of the EPROM eraser and to protect internal circuit other than the EPROM from misoperation due to light stick a protective sticker over the erasure window when EPROM erasure is not being performed 23 6 Screening of One Time PROM Model Because of their structure the one time PROM models uPD78P018FCW 78P018FGC AB8 78P018FGK 8A8 78P018FYCW 78P018FYGC AB8 and 78P018FYGK 8A8 cannot be completely tested by NEC before shipment It is recommended that screening be implemented to verify the PROM contents after necessary data have been written to the PROM and the product has been stored under the following temperature conditions Storage Temperature Storage Time NEC offers a service at a charge called QTOP microcontroller for writing marking screening and verifying one time PROMs For details consult NEC 475 MEMO 476 CHAPTER 24 INSTRUCTION SET
410. s detected a non maskable interrupt request or the RESET signal can be generated Table 11 1 Inadvertent Loop Detection Time of Watchdog Timer Inadvertent Loop Detection Time 212 x 1 fx At fx 10 0 MHz Inadvertent Loop Detection Time 216 x 1 fx At fx 10 0 MHz 6 55 ms 213 x 1 fx 217 x 1 fx 13 1 ms 214 x 1 fx 218 x 1 fx 26 2 ms 215 x 1 fx fx main system clock oscillation frequency 2 Interval timer mode 220 x 1 fx 104 9 ms When the watchdog timer is used as an interval timer it generates an interrupt at time intervals setin advance Interval Time 212 x 1 fx Table 11 2 At fx 10 0 MHz Interval Time Interval Time 216 x 1 fx At fx 10 0 MHz 6 55 ms 213 x 1 fx 217 x 1 fx 13 1 ms 214 x 1 fx 218 x 1 fx 26 2 ms 215 x 1 fx fx main system clock oscillation frequency 220 x 1 fx 104 9 ms 229 CHAPTER 11 WATCHDOG TIMER 11 2 Configuration of Watchdog Timer The watchdog timer consists of the following hardware Table 11 3 Configuration of Watchdog Timer Control register Timer clock select register 2 TCL2 Watchdog timer mode register WDTM 230 LES fx 24 fx fx 8 bit prescaler fx x Figure 11 1 Block Diagram of Watchdog Timer Internal bus RUN 25 26 27 A Y TMMK4 8 bit counter Control circuit fe 2 O D o
411. s indicated in the table below for the details of serial interface channel 1 refer to CHAPTER 17 SERIAL INTERFACE CHANNEL 1 Table 16 1 Serial Transfer Mode 3 wire serial I O Clock selection Differences between Channels 0 and 1 Channel 0 fx 22Note 17 23 fx 24 fx 25 tx 28 fx 27 fx 28 fx 29 external clock TO2 output Channel 1 fx 22Note 13 23 fx 24 fx 25 fx 28 fx 27 fx 28 fx 29 external clock TO2 output Transfer method MSB first LSB first selectable MSB first LSB first selectable Automatic transmit receive function Transfer end flag Serial interface channel 0 transfer end interrupt request flag CSIIFO Serial interface channel 1 transfer end interrupt request flag CSIIF1 and TRF 2 wire serial I O 12C bus Inter IC Bus Available Not available Note Can be set only when the main system clock oscillates at 4 19 MHz or less 309 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78018FY SUBSERI7 16 1 Functions of Serial Interface Channel 0 Serial interface channel 0 has the following four modes Operation Mode Operation stop mode Table 16 2 Differences in Modes of Serial Interface Channel 0 Pins Used Features Mode used when no serial transfer is performed Power consumption can be reduced Applications 3 wire serial I O mode SCKO serial clock SO0 serial output SIO serial input Short data transfer processing t
412. s mode Consequently the power consumption can be reduced The serial I O shift register 0 SIOO can be used as an ordinary 8 bit register because it does not perform the shift operation In the operation stop mode the P25 SIO SB0 SDAO P26 SO0 SB1 SDA1 and P27 SCKO SCL pins can be used as ordinary I O port pins 1 Register setting The operation stop mode is set by using the serial operation mode register 0 CSIMO CSIMO is set by using a 1 bit or 8 bit memory manipulation instruction This register is set to OOH when the RESET signal is input Symbol lt 7 gt Address On reset R W R W CSIEO Serial interface channel 0 operation control Stops operation Enables operation 16 4 2 Operation in 3 wire serial I O mode This mode is useful for connecting peripheral I Os and display controllers that have the conventional clocked serial interface of the 75X XL series 78K series and 17K series In this mode communication is established by using three signal lines serial clock SCKO serial output SOO and serial input S10 1 Register setting The 3 wire serial I O mode is set by using the serial operation mode register 0 CSIMO and serial bus interface control register SBIC a Serial operation mode register 0 CSIMO CSIMO is set by a 1 bit or 8 bit memory manipulation instruction This register is set to OOH when the RESET signal is input 323 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78018FY SUBSE
413. s output or input during transmit receive operation and checks whether 8 bit serial data has been transmitted received 17 3 Registers Controlling Serial Interface Channel 1 The following four types of registers control serial interface channel 1 Timer clock select register 3 TCL3 Serial operation mode register 1 CSIM1 Automatic data transmit receive control register ADTC Automatic data transmit receive interval specification register ADTI 1 362 Timer clock select register 3 TCL3 This register sets the serial clock of serial interface channel 1 TCL3 is set by an 8 bit memory manipulation instruction This register is set to 88H when the RESET signal is input Remark TCL3 also has a function to setthe serial clock of serial interface channel 0 in addition to the function to set the serial clock of serial interface channel 1 CHAPTER 17 SERIAL INTERFACE CHANNEL 1 Figure 17 2 Format of Timer Clock Select Register 3 Symbol 7 6 5 4 3 2 1 0 Address On reset R W TCL3 TCL37 TCL36 TCL35 TCL34 TCL33 TCL32 TCL31 TCL30 FF43H 88H R W TCL32 TCL31 fx 22Note fx 23 1 25MHz fx 24 625kHz fx 25 313kHz fx 28 156kHz fx 27 78 1kHz fx 28 39 1kHz fx 29 19 5kHz Others Setting prohibited TCL36 TCL35 TCL34 Selects serial clock of serial interface channel 1 fx 22Note fx 23 1 25MHz fx 24 625kHz fx 25 313kHz fx
414. s s e sss2 csencides cctciascdevedsacsiceessaauesasiesisedcchassaenenesnsassepepsaecesstdecsdseeedesacidies 123 5 4 3 Register addr sSii gasnie a E E E da 124 9 4 4 Directaddressihg cert a a a a a i 125 18 5 4 5 Short direct addressing 2 t c ncive dhe die dele vides 126 5 4 6 Special function register SFR addressing eeceeeceeeeeeseeeeeeeeeeeeeeeeeeeeeeaeeteeteaeeseeeeeaeees 128 5 4 7 Register indirect addressing ccesecccceseceeeeeeeeseeceeesceeeeseneesteneesesceeeseeeeseeaseneseeeneneeneess 129 5 4 8 Based addressing itive abit aaae E e a Aaa 130 5 49 Based indexed addressing ccscccceecceeseeeeesseceesseneeesneeseseeeesnenseseeeeeseneesensenseeseeeeersoeenes 131 54 10 Stack addressing iii A eee iii ad nde 131 CHAPTER 6 PORT FUNCTIONS ccss cccceseseeceenseeeeeeeenseaaeeeeenseseeeeensseaeeeeeeseaeeesnsseneaeeenseeeeeneess 133 6 1 FUNCTIONS Of POPS aa cee eeeeee eee eeeneee ee ESAE EEEE EEn E AEAEE 133 6 2 Port Configuration oanet nanea ndante ae denenean aneen eE aeaaeae Gupte cenit arcas 136 O Por Oane e e E nes a eee 137 622 Port Tanen eika Gas Mead abhi ra a a Aon a adeat 139 6 2 3 Port 2 uPD78018F SUDSeries decies droee rine ES e aiia 140 6 2 4 Port 2 uPD78018FY SUDSETIES sismici een eeeeeeeeeeneeeeeeneeeeeeaeeeeaeeeseaaeeeeeaeeeenaeeeeeneeees 142 A A OR eee tees ne lee Se LSet S ee 144 02 67 Pond tc e es e e e a ere ee 145 627 PO Dinar iO Ar Dl ie i 146 6
415. s selected by setting bit 1 CSIM11 of the serial operation mode register 1 CSIM1 to 0 Remark x Don t care 366 CHAPTER 17 SERIAL INTERFACE CHANNEL 1 4 Automatic data transmit receive interval specification register ADTI This register sets the interval time at which data is transferred by the automatic transmit receive function ADTI is set by using a 1 bit or 8 bit memory manipulation instruction This register is set to OOH when the RESET signal is input Figure 17 5 Format of Automatic Data Transmit Receive Interval Specification Register 1 2 Symbol 7 Address On reset R W ADTI ADTI7 CAEN ADTI4 ADTI3 ADTI2 ADTI1 ADTIO FF6BH 00H R W ADTI7 Controls interval time of data transfer Interval time not controlled by ADTINote 1 Interval time controlled by ADTI ADTIO ADTI4 ADTI3 ADTI2 ADTI1 Specifies interval time of data transfer fx 10 0 MHz operation Minimum value ote 2 18 4 us 0 5 fsck Maximum value ote 2 20 0 us 1 5 fsck 31 2 us 0 5 fsck 32 8 us 1 5 fsck 44 0 us 0 5 fsck 45 6 us 1 5 fsck 56 8 us 0 5 fsck 58 4 us 1 5 fsck 69 6 us 0 5 fsck 71 2 us 1 5 fsck 82 4 us 0 5 fsck 84 0 us 1 5 fsck 95 2 us 0 5 fsck 96 8 us 1 5 fsck O O O TO O VO O 108 0 us 0 5 fsck 109 6 us 1 5 fsck 120 8 us 0 5 fsck 122 4 us 1 5 fsck 133 6 us 0 5 fsck 135 2 us 1 5 fsck 146 4 us
416. s set by a 1 bit or 8 bit memory manipulation instruction This register is set to OOH when the RESET signal is input Caution The 16 bit timer register TMO starts operation when a value other than 0 0 0 is set to TMC01 TMCO3 operation stop mode To stop the operation set TMC01 TMCO3 to O 0 0 181 CHAPTER 8 16 BIT TIMER EVENT COUNTER Figure 8 4 Format of Timer Clock Select Register 0 Symbol lt 7 6 5 4 3 1 0 Address On reset R W 2 TCLO CLOE TCLO6 TCLO5 TCLO4 TCLO3 TCLO2 TCLO1 TCLOO FF40H 00H R W TCLO2 TCLO1 TCLOO Selects clock of PCL output fxt 32 768 kHz fx 28 1 25 MHz fx 24 625 kHz 1x 25 156 kHz fx 27 78 1 kHz fx 25 313 kHz fx 28 39 1 kHz Setting prohibited fx 2 5 0 MHz fx 22 2 5 MHz fx 23 1 25 MHz Setting prohibited 0 Disables output Enables output Cautions 1 The valid edge of the TIO INTPO pin is set by the external interrupt mode register INTMO The frequency of a sampling clock is selected by the sampling clock select register SCS 2 To enable PCL output set TCLOO through TCLO3 and then set CLOE to 1 by using a 1 bit memory manipulation instruction 3 Read the count value from TMO not from the 16 bit capture register CRO1 when TIO is used as the count clock of TMO 4 Before writing data other than that already written to TCLO stop the timer operation
417. s such as LCD controllers drivers can be easily connected 1 Register setting The 3 wire serial I O mode with automatic transmit receive function is set by using the serial operation mode register 1 CSIM1 and automatic data transmit receive control register ADTC and automatic data transmit receive interval specification register ADTI a Serial operation mode register 1 CSIM1 CSIM1 is set by a 1 bit or 8 bit memory manipulation instruction This register is set to OOH when the RESET signal is input 373 CHAPTER 17 SERIAL INTERFACE CHANNEL 1 Symbol De 6 lt 5 4 3 Address On reset R W 2 1 0 com om me o o To onfe rum om aw Selects clock of serial interface channel 1 Clock externally input to SCK1 pinNote 1 Output of 8 bit timer register 2 TM2 Clock specified by bits 4 7 of timer clock select register 3 TCL3 Selects operation mode of serial interface channel 1 0 3 wire serial I O mode 1 3 wire serial I O mode with automatic transmit receive function First bit SI1 pin function SO1 pin function si1 P20 soi input CMOS output CSIM Shift register Serial clock SI1 P20 SO1 P21 SCK1 P22 SIE1 PM20 P20 PM21 P21 PM22 P22 i counter operation _ A i i 11 1 operation control pin function pin function pin function Note 2 Note 2 Note 2 Note 2 Note 2 Operation P20 P21 P22 x x x x x disabled CMOS I O CMOS I O CMOS I O SCK1 Note 3 Note 3 Operation Count S Notes So
418. s the IE 78001 R A host machine IE 70000 PC IF B or IE 7000 PC IF CNote Interface Adapter This adapter is required when using the IBM PC AT and its compatible computers as the IE 78001 R A host machine IE 78000 R SV3 Interface Adapter This is adapter and cable required when using an EWS computer as the IE 78001 R A host machine and is used connected to the board in the IE 78000 R A As Ethernet 10Base 5 is supported If the other methods are used a commer cially available conversion adapter is necessary IE 78018 NS EM1 Note Emulation Board This board emulates the operations of the peripheral hardware peculiar to a device It should be used in combination with an in circuit emulator and emulation conver sion board IE 78K0 R EX1 Note Emulation Probe Conversion Board This board is required when using the IE 78018 NS EM1 on the IE 78001 R A IE 78014R EM A Emulation Board This board emulates the operations of the peripheral hardware peculiar to a device 3 0 to 6 0 V supported It should be used in combination with the IE 78001 R A EP 78240GC R Emulation Probe This probe is used to connect the in circuit emulator to the target system and is designed for 64 pin plastic QFP GC AB8 type EV 9200GC 64 Conversion Socket Refer to Figure B 2 This conversion socket connects the EP 78240GC R to the target system board designed to mount a 64 pin plastic QFP GC AB8 type Instead of
419. s used to connect the in circuit emulator to the target system and is designed for 64 pin plastic LQFP GK 8A8 type TGK 064SBW Conversion Adapter Refer to Figure B 4 This conversion socket connects the NP 64GK to the target system board designed to mount a 64 pin plastic LQFP GK 8A8 type EV 9900 Note Under development Jig used to remove the uPD78P018FKK S or 78P018FYKK S from the EV9200GC 64 Remarks 1 NP 64GC and NP 64GK are products of Naito Densei Machida Mfg Co Ltd Naito Densei Machida Mfg Co Ltd TEL 044 822 3813 2 TGK 064SBW is a product of TOKYO ELETECH Corporation Reference Daimaru Kogyo Ltd Electronics Dept TEL Tokyo 03 3820 7112 Electronics 2nd Dept TEL Osaka 06 244 6672 3 EV 9200GC 64 is sold in five units 4 TGK 064SBW is sold in one units 501 APPENDIX B DEVELOPMENT TOOLS B 3 1 Hardware 2 2 2 When using the in circuit emulator IE 78001 R A IE 78001 R ANote In circuit Emulator The in circuit emulator serves to debug hardware and software when developing application systems using a 78K 0 Series product It corresponds to integrated debugger ID78K0 This emulator should be used in combination with emulation probe and interface adapter which is required to connect this emulator to the host machine IE 70000 98 IF B or IE 7000 98 IF CNote Interface Adapter This adapter is required when using the PC 9800 Series computer except notebook type a
420. seeeeeeeeeneeseaeeeeeeeeeeeeeeteee 160 7 4 External Circuit of Main System Clock Oscillation Circuit ceceeeeeeeeeeeeeeeeeneeeeeeeeneees 162 7 5 External Circuit of Subsystem Clock Oscillation Circuit eeceeeeeeeeeneceeeeeeeeseeeeneeeneees 162 7 6 Incorrect Examples of Resonator Connection ceecceesceeeeeeeeeeeeeeeeeeeceeeeeaeeeeeeesneeeeneeeeee 163 7 7 Stopping Main System Clock cceeceeeceseeeeeeeeeeeeeeeeeeeeseaeeseeeeeaeeseaeeeeeseeeesieeeeaeesieeseaeeeeaeees 168 7 8 Switching between System Clock and CPU Clock ooocconcccioccconccconnconcnnoncconcnnnncnnnnncnncnonnnnnn 171 8 1 Block Diagram of 16 Bit Timer Event Counter Timer Mode cooocioccncccnocacaccconcnnnancnancnanca 177 8 2 Block Diagram of 16 Bit Timer Event Counter PWM Mode eecceeeeeeeeeeeeeeeeeeeeeeetsees 178 8 3 Block Diagram of 16 Bit Timer Event Counter Output Control Circuit eee 179 8 4 Format of Timer Clock Select Register O eeccceceeseeeeeeeeeeeeereceeeeeeeeeeeeseaeeseeeeeeeeeeeeeaeess 182 8 5 Format of 16 Bit Timer Mode Control Register oooococnccnnnicinconcccnnconncccnorn conc nnnnnrnrcnnnncn nc 183 8 6 Format of 16 Bit Timer Output Control Register ooooncccinncnnccnccnnncnnoccnannconancnncconnncnncnnnnnnns 184 8 7 Format of Port Mode Register 3 c cccsscccceseeeteseeceeseneeseseneneneneesneeeesseeeneneneesenneenteenenes 185 8 8 Format of External Interrupt Mode Register 0 0 eeeeeeesceeeseeeeeeneeeeeeeeseneeeeesaee
421. side Pe A se et aa l i i i INTCSIo J ACK BUSY Clears Hardware operation Serial reception operation A __ BUSY SAIMSSENS 481084007 0 TANNVHO 39V44831NI IVIHIS Si YILAVHO 00 Figure 15 29 Data Transmit Operation from Slave Device to Master Device Master device processing reception side Hardware operation SCKO Serial reception Transfer line SCKO pin SBO SB1 pin Slave device processing transmission side SAIMSSAENS 481084007 0 TANNVHO AJ0VSYALNI IVIHIS SI YILAVHO CHAPTER 15 SERIAL INTERFACE CHANNEL 0 uPD78018F SUF 9 Transfer start Serial transfer is started by setting the transfer data to the serial I O shift register O SIOO when the following two conditions are satisfied e Operation control bit of serial interface channel 0 CSIEO 1 e Internal serial clock is stopped or SCKO is high after 8 bit serial transfer Cautions 1 Transfer is not started even when CSIE0 is set to 1 after data has been written to SIOO 2 Because the N ch open drain output must be made high impedance state during data reception write FFH to SIOO in advance However when the wake up function specification bit WUP 1 the N ch open drain output is always at high impedance state and FFH needs not to be written to SIOO before reception 3 If data is written to SIOO when the slave is busy that data is not lost When SBO or SB1 input goes high ready after the busy stat
422. sion has been started and when one A D conversion has been completed the next A D conversion is not started unless a new external trigger signal is input If data whose CS is 1 is written again to ADM during A D conversion the AD conversion under execution is stopped and stands by until a new external trigger signal is input When the external trigger signal is input A D conversion is performed again from the start When 0 is written to the CS bit of ADM during A D conversion the conversion is immediately stopped Figure 14 6 A D Conversion by Hardware Start INTP3 a Rewriting ADM Rewriting ADM CS 1 TRG 1 CS 1 TRG 1 Standby Standby Standby A D conversion ANIn ANIn Gants ANIn status ANIm ANIm ANIm 254 bh q UM E S A L INTAD Remark n 0 1 7 i ri od we GK i ar lu ed CHAPTER 14 A D CONVERTER 2 A D conversion by software start By setting bit 6 TRG of the A D converter mode register ADM to 0 and setting bit 7 CS to 1 the voltage applied to the analog input pin specified by bits 1 3 ADM1 ADM3 of ADM is converted into digital values When the A D conversion has been completed the result of the conversion is stored in the A D conversion result register ADCR and an interrupt request signal INTAD is generated When the A D conversion has been started once and one A D conversion has been completed the next A D conve
423. skable interrupt request Executes next address instruction Executes interrupt processing Executes next address instruction Executes interrupt processing Retains STOP mode Test input Executes next address instruction Retains STOP mode RESET input Reset processing Remark x Don t care 447 MEMO 448 21 1 Reset Function CHAPTER 21 RESET FUNCTION The reset signal can be effected by the following two methods 1 External reset input from RESET pin 2 Internal reset by inadvertent loop time detection by watchdog timer i ri oY a lv ed There is no functional difference between the external reset and internal reset and execution of the program is started from addresses written to addresses 0000H and 0001H when the RESET signal is input The reset function is effected when a low level signal is input to the RESET pin or when an overflow occurs in the watchdog timer As a result each hardware enters the status shown in Table 21 1 Each pin goes into a high impedance state while the RESET signal is input and during the oscillation stabilization time immediately after the reset function has been released When a high level signal is input to the RESET pin the reset function is released and program execution is started after oscillation stabilization time 218 fx has elapsed The reset function effected by an overflow in the watchdog timer is automatically rel
424. ssesessessessessessssesseessesssessesseesseesseess 447 21 1 Block Diagram of Reset Function oooocccinncccnnoocnnnoncnnnnnanonnn non nnn cnn nano nrrnnr nn rr rra 449 21 2 Reset Timing by RESET Input ad 450 29 LIST OF FIGURES 7 7 Figure No Title Page 21 3 Reset Timing by Overflow in Watchdog Timer cccceccceeseeeeeeeeeeeeeeseeeeseeeeeaeeseeeeeeeeeaees 450 21 4 Reset Timing by RESET Input in STOP Mode cccsssssssessessessesessessessssessessessssesseeseeeeees 450 22 1 Block Diagram of ROM Correction 0 cecceecceeeceeeeeeeeeeeeeeceaeeeeeceaeeeeeseeeeseeseaeesneeesieeeeeeeeaes 454 22 2 Formats of Correction Address Registers 0 and 1 oi eeeeeeeeeeeceeeeeeeeeeeeeeeeeeeaeesneeeeeeennees 454 22 3 Format of Correction Control Register ecceecceseceeeeeeeeeeeeeeeeeeseaeeeeeeeaeeseeeeaeesseeeeaeeeaees 456 22 4 Example of Storing in EEPROM when only one place is to be corrected 457 22 5 Example of Connecting EEPROM in 2 wire serial l O mode ceecceeeeeeeteeeeeeeteeeneees 457 22 6 InitialiZation ROWING ssc io E A E 458 22 7 Operation of ROM Correction cccessecescessceeeeeeeseeceaeeeseeeeaeeeeeseaeeseaeeeaeeseaeeeaeeseaeeseeeseaeeee 459 22 8 Example of Using ROM Correction ecceesceeeeeceeeeeneeeeeeeeaeeeneeseaeeseeeseaeeseaeeeaeessaeeneeeenaees 459 22 9 Program Sequence when only one place iS Corrected e ceeeeeeeeeeeeeeeeeeeeeeeteaeeeeeeteeeens 460 22
425. ssion is less than 2 fsck however the minimum interval time is assumed to be 2 fsck 7 Minimum value n 1 x A A fx fx fsck 7 Maximum value n 1 x 2 72 15 fx fx fsck Cautions 1 Do not write data to ADTI while the automatic transmit receive function is in use 2 Be sure to set bits 5 and 6 to 0 3 To control the interval time for data transfer of automatic transmission reception by using ADTI busy control becomes invalid refer to 17 4 3 4 a Busy control option Remark fx Main system clock oscillation frequency fsck Serial clock frequency 377 CHAPTER 17 SERIAL INTERFACE CHANNEL 1 Symbol 7 6 5 4 3 2 1 0 Address On reset R W ADTI ADTI7 0 O ADTI4 ADTI3 ADTI2 ADTI1 ADTIO FF6BH 00H R W ADTI3 ADTI2 ADTI1 Specifies interval time for data transfer fx 10 0 MHz operation Minimum value ote 223 2 us 0 5 fsck Maximum valueNote 224 8 us 1 5 fsck 236 0 us 0 5 fsck 237 6 us 1 5 fsck 248 8 us 0 5 fsck 250 4 us 1 5 fsck 261 6 us 0 5 fsck 263 2 us 1 5 fsck 274 4 us 0 5 fsck 276 0 us 1 5 fsck 287 2 us 0 5 fsck 288 8 us 1 5 fsck 300 0 us 0 5 fsck 312 8 us 0 5 fsck 301 6 us 1 5 fsck 314 4 us 1 5 fsck o o o o o o o o 325 6 us 0 5 fsck 327 2 us 1 5 fsck 338 4 us 0 5 fsck 340 0 us 1 5 fsck 351 2 us 0 5 fsck 352 8 us 1 5 fsck 364 0 us 0 5 fsck 365 6 us 1 5 fsck 376 8 us
426. start instruction is executed When bus release signal REL is detected e When CSIEO 0 e When RESET is input When command signal CMD is detected Note Bits 2 3 and 6 RELD CMDD and ACKD are read only bits Remark CSIEO Bit 7 of the serial operation mode register 0 CSIMO CHAPTER 15 SERIAL INTERFACE CHANNEL 0 uPD78018F SUS Figure 15 4 Format of Serial Bus Interface Control Register 2 2 Outputs acknowledge signal in synchronization with falling edge of clock of SCKO immediately after instruction that sets this bit to 1 has been executed After acknowledge signal has been output this bit is automatically cleared to 0 This bit is also cleared to 0 when transfer of serial interface is started or when CSIEO 0 R W ACKE Acknowledge signal output control Disables automatic output of acknowledge signal output by ACKT is enabled Before completion of Outputs acknowledge signal in synchronization with falling edge of 9th clock of transfer SCKO automatically outputs when ACKE 1 Outputs acknowledge signal in synchronization with falling edge of clock of SCKO After completion of immediately after instruction that sets this bit to 1 has been executed automatically transfer output when ACKE 1 However this bit is not automatically cleared to 0 after acknowledge signal has been output R ACKD Acknowledge detection Clearing conditions ACKD 0 Setting condition ACKD 1 At f
427. stem clock High speed a operation operation operation 26 2 ms at 10 0 MHz operation Internal reset operation lt 1 gt The CPU is reset when the RESET pin is made low on power application The effect of resetting is released when the RESET pin is later made high and the main system clock starts oscillating At this time the time during which oscillation stabilizes 218 fx is automatically secured After that the CPU starts instruction execution at the slowest speed of the main system clock 6 4 us at 10 0 MHz operation lt 2 gt After the time during which the Vob voltage rises to the level at which the CPU can operate at the highest speed has elapsed processor clock control register PCC is rewritten so that the highest speed can be selected lt 3 gt A drop of the Vop voltage is detected by using an interrupt request signal If this happens the subsystem clock is selected at this time the subsystem clock must be in the oscillation stabilization status lt 4 gt The recovery of Voo voltage to the original level is detected by using an interrupt 0 is set to bit 7 of PCC MCC and oscillation of the main system clock is started After the time required for oscillation to stabilize has elapsed PCC is rewritten so that the highest speed can be selected Caution To select the main system clock again when the system operates on the subsystem clock with the main system clock stopped be sure to secure the oscillation stabi
428. subseries the yPD78018FY subseries will initiate communication destroying the communication data Note Theserial transfer status is the status in which the interrupt request flag CSIIFO is set because of the end of serial transfer after the serial I O shift register O SIOO has been written This restriction can be avoided by modifying the program Before executing the wake up function execute the following program that releases serial transfer status To execute the wake up function do not execute an instruction that writes SIOO Even if such an instruction is not executed data can be received when the wake up function is executed This program releases the serial transfer status To release the serial transfer status the serial interface channel 0 must be set once in the operation stop status by clearing the CSIEO flag bit 7 of the serial operation mode register CSIMO to 0 However if the serial interface channel 0 is set in the operation stop status in the 12C bus mode the SCL pin output a high level and the SDAO SDA1 pin outputs a low level affecting communication of the I2C bus Therefore this program places the SCL and SDAO SDA1 pins in the high impedance state to prevent the 12C bus from being affected In the example below SDAO P25 is used as a serial data input output pin When SDA1 P26 is used as the serial data input output pin take P2 5 and PM2 5 in the program below as P2 6 and PM2 6 respectively For the t
429. subsystem clock CPU clock D 168 i mar lu ed CHAPTER 7 CLOCK GENERATION CIRCUIT 7 5 2 Operation of subsystem clock When the subsystem clock is used when bit 5 CLS of the processor clock control register PCC is 1 the following operations are performed a Minimum instruction execution time is held constant 122 us at 32 768 kHz operation regardless of the setting of bits 0 2 PCCO PCC2 of PCC b The watchdog timer stops counting Caution Do not execute the STOP instruction during subsystem clock operation 169 CHAPTER 7 CLOCK GENERATION CIRCUIT 7 6 Changing Setting of System Clock and CPU Clock 7 6 1 Time required for switching between system clock and CPU clock The system clock or CPU clock can be selected by using bits 0 through 2 PCCO PCC2 and bit 4 CSS of the processor clock control register PCC Actually the specified clock is not selected immediately after the setting of PCC has been changed and the old clock is used for the duration of several instructions after that refer to Table 7 3 Whether the system operates on the main system clock or subsystem clock can be checked by using bit 5 CLS of PCC Table 7 3 Maximum Time Required for Switching CPU Clock Set Value before Set Value after Switching Switching PCC2 PCC1 PCCO PCC2 PCC1 PCCO CSS PCC2 PCC1 CSS PCC2 PCC1 0 0 1 0popo 1 fx 4fxt instructions 16 i
430. subsystem clock to other devices refer to CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT 6 Buzzer output control circuit This circuit outputs a buzzer frequency that is obtained by dividing the main system clock refer to CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT 173 CHAPTER 8 16 BIT TIMER EVENT COUNTER Table 8 1 Operations of Timer Event Counters Interval timer 16 bit Timer Event Counter 1 channel 8 bit Timer Event Counter 2 channels Watch Timer 1 channelNote 1 Watchdog Timer 1 channelNote 2 External event counter O Function Notes 174 Timer output O PWM output Pulse width measurement Square wave output Interrupt request Test input 1 Watch timer can be used as a watch timer and an interval timer at the same time 2 Watchdog timer has a watchdog timer and interval timer functions Select one of them CHAPTER 8 16 BIT TIMER EVENT COUNTER 8 2 Functions of 16 Bit Timer Event Counter The 16 bit timer event counter TMO has the following functions Interval timer PWM output Pulse width measurement External event counter Square wave output The PWM output and pulse width measurement functions can be used at the same time 1 Interval timer When the 16 bit timer event counter is used as an interval timer it generates an interrupt request at any time intervals set in advance Table 8 2 Interval Time o
431. sy control option is used Figure 17 18 System Configuration when Busy Control Option Is Used Master device 1PD78018F 78018FY subseries Slave device The master device inputs the busy signal output by the slave device to the BUSY P24 pin The master device samples the input busy signal in synchronization with the falling of the serial clock Even if the busy signal becomes active while 8 bit data is being transmitted or received transmission reception by the master is not kept waiting If the busy signal is active at the rising edge of the serial clock 2 clocks after completion of transmission reception of the 8 bit data the busy input becomes valid After that the master transmission reception is kept waiting while the busy signal is active The active level of the busy signal is set by bit O BUSYO of ADTC BUSYO 0 Active high BUSYO 1 Active low 393 i rN a lu ed CHAPTER 17 SERIAL INTERFACE CHANNEL 1 394 When using the busy control option select the internal clock as the serial clock Control with the busy signal cannot be implemented with the external clock Figure 17 19 shows the operation timing when the busy control option is used Caution Busy control cannot be used simultaneously with the interval time control function of the automatic data transmit receive interval specification register ADTI If used busy control is invalid Figure 17 19 Operation Timing When Busy Control Option I
432. t input 1 x enabled operation input CMOS output SCK1 CMOS output Notes 1 When external clock input is selected by setting CSIM11 to 0 set bit 1 BUSY1 and bit 2 STRB of the automatic data transmit receive control register ADTC to 0 0 2 These pins can be used freely as port pins 3 When data is only transferred this pin can be used as P20 CMOS I O set bit 7 RE of ADTC to 0 Remark x Don t care PMxx Port mode register Pxx Output latch of port b Automatic data transmit receive control register ADTC ADTC is set by a 1 bit or 8 bit memory manipulation instruction The contents of this register are set to OOH when the RESET signal is input 374 CHAPTER 17 SERIAL INTERFACE CHANNEL 1 Symbol lt 7 lt 0 gt Address On reset R W lt 6 gt lt lt 4 lt gt 2 1 gt ADTC RE ARLD ERCE STRB BUSY1 BUSY0 FF69H 00H R W Note 1 Does not use busy input Enables busy input high active Enables busy input low active STRB Controls strobe output 0 1 Disables strobe output Enables strobe output Detects end of automatic transmission reception set to 0 when automatic transmission reception is aborted or when ARLD 0 Automatic transmission reception is in progress set to 1 when this bit is written to SIO1 No error during automatic transmission reception cleared to 0 when this bit is written to
433. t Operation eee ecceeeeeeeseceeeeeeeseaeeeeeeenaeeesaeeeaeesaeeeaeeseeeseseeteaeeeaeeee 214 9 11 Interval Timer Operation Timing cccceesceeececeeeecsceeeaeeceeeeeaeeeeaeeeaeeeeaeeeaeeseaeeeaeeseaeeeseeteaees 215 9 12 External Event Counter Operation Timing with rising edge specified e eee 217 9 13 Square Wave Output Operation oooocccncononicinccnonnconnnnanccononcnnc nono n cnn nn nn nn anna rnn nan rn cnn nrnncanns 218 9 14 Start Timing of 8 Bit Timer Register cceeceeececeneeeeeeeeneeeeeeeeaeeeeaeeeaeeseeeeaeeseeeseeeeeaeeeaeeee 219 9 15 External Event Counter Operation Timing ooocconnccnnccnnccnnnconncncnnnonnn cano co nara nnnn rancia 219 9 16 Timing after Changing Values of Compare Registers during Timer Count Operation 220 10 1 Block Diagram of Watch Timer eeeceesceessneeeeeneeeseneeeeeeneeeeeaeeeseeeeeneaeeeesaaeesenaeeeneneeensaaes 223 10 2 Format of Timer Clock Select Register 2 ecccceeceeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeseaeeeeeeseeeteeeeeaees 224 10 3 Format of Watch Timer Mode Control ReQiSter c cccccceeseeeseeeeeeeseeeeeneeseeeeeeessaeeneeenaees 225 11 1 Block Diagram of Watchdog Timer oooooccoccccnnocccononcnononcnnnnrnnonanr cnn non cnn nan rr rar nn rn n rr 231 11 2 Format of Timer Clock Select Register B ooooncccnccincccicccnonnnoccconcnconcnoncnnnnccnnnncnncn nn nccancnnncnns 233 11 3 Format of Watchdog Timer Mode Register ooocoocccononcccnocaccnoncconnonnnnnaranonono n
434. t Timer Register oooocccnnncnnnccnnnccncccnnoccnnnnnoncnnnnn conc n nn cronn anar cnn nn rancnannnnnn 197 8 21 Timing after Changing Value of Compare Register during Timer Count Operation 197 8 22 Data Hold Timing of Capture Register oooooccnccninccinnccnnccnonnnnnnnnnnccnnnnnnncc nr nro 198 8 23 Operation Timing of OVFO Flag eeeceecceeeeeeeseeceeeeseeeeaeeseeeeaeeesaeeeaeessaeeeaeeeaeseseeteaeeeaeetea 198 9 1 Block Diagram of 8 Bit Timer Event CoUNtBTF ococcccinnccnccnnccnnnccnonnnonn crono conc narran 203 9 2 Block Diagram of 8 Bit Timer Event Counter Output Control Circuit 1 0 eee 204 9 3 Block Diagram of 8 Bit Timer Event Counter Output Control Circuit 2 0 0 eee 204 9 4 Format of Timer Clock Select Register 1 ceeceeeeeeeeeeeeeeeeeeeeseeeeeeeeeeeeeaeesneeeeneeteeeeeaeees 207 25 LIST OF FIGURES 3 7 Figure No Title Page 9 5 Format of 8 Bit Timer Mode Control Register cecccecceeeeeeeeeeeeeeeeeeeeneeseeeseeeeteeteeeeeneee 208 9 6 Format of 8 Bit Timer Output Control Register cece eeceeeeeeeeeceeeeeeeeeeeeseeeeeaeeteaeeeeeeeaees 209 9 7 Format of Port Mode Register 3 o eeeceeseseeeeeneeeeeeeeeeeeaeeeseaeeeeesaeeeeeaeeeseaeesensaeeeeeeeeteneeees 210 9 8 Interval Timer Operation Timing ceccceceeeeeceneeceeeeeaeeceeeeeaeeeaeeeaeeseaeeeaeeseaeeeaeeseaeeneeeeeaees 211 9 9 External Event Counter Operation Timing with rising edge specified eee 213 9 10 Square Wave Outpu
435. t currently serviced 0 interrupt with high priority serviced 1 interrupt request is not accepted or interrupt with low priority is serviced 416 i ri oY a lv ed CHAPTER 18 INTERRUPT FUNCTIONS AND TEST FUNCT Figure 18 13 Interrupt Request Acceptance Timing Minimum Time 12 clocks A R P Interrupt Saving PSW and PC jump F CPU processing Instruction Instruction to interrupt processing leet xxIF S VEN IN xxPR 1 15 clocks xxPR 0 13 clocks Remark 1 clock ait fcpu CPU clock fcpu Figure 18 14 Interrupt Request Acceptance Timing Maximum Time 50 clocks 12 clocks i i Interrupt 7 se Saving PSW and PC jump F CPU processing Instruction Division instruction to interrupt processing processing program wr A TTT TTT TT e xxPR 1 65 clocks xF A oo xxPR 0 63 clocks Remark 1 clock gal fcru CPU clock fcpu 18 4 3 Software interrupt request acceptance operation The software interrupt request can be accepted when the BRK instruction is executed This interrupt cannot be disabled When the software interrupt request is accepted the program status word PSW and program counter PC are saved to the stack in that order the IE flag is reset to 0 the contents of the vector table 003EH and 003FH are loaded to the PC and execution branches To return from the software interrupt processing use the RETB instruction Caution Do not
436. t timer output control register TOC1 Port mode register 3 PM3 Note Port 3 P3 Note Refer to Figure 6 10 Block Diagram of P30 P37 202 02 fx 22 fx 210 fx 212 TI P33 fx 22 fx 210 fx 212 TI2 P34 O Selector Selector 8 bit compare register CR10 Figure 9 1 Block Diagram of 8 Bit Timer Event Counter Internal bus gt INTTM1 8 bit timer register 1 TM SZ Coincidence 1 Selector Clear aa TCL 17 Note For the configuration of the 8 bit timer event counter output control circuits 1 and 2 refer to Figures 9 2 and 9 3 TCL TCL TCL TCL TCL TCL TCL 16 15 14 13 12 11 10 Timer clock select register 1 8 bit compare register CR20 Coincidence 8 bit timer register 2 Clear Selector Note 8 bit timer event counter output control circuit 2 TO2 P32 8 bit timer mode control register Note 8 bit timer event TCE1 Internal bus gt counter output control circuit 1 gt INTTM2 4 LVS LVR TOC TOE LVS LVR TOC TOE 2 2 15 2 1 1 11 1 8 bit timer output control register TO1 P31 YSLNNOO LNSAR YHAWIL LIG 8 6 YILAVHO CHAPTER 9 8 BIT TIMER EVENT COUNTER Level F F LV1 LVR1 LVS1 TOC11 gt 2 O TO1 P31 P31 PM31 output
437. ta is 20H FFH a 0 When 8 bit immediate data is OOH 1FH a 1 127 CHAPTER 5 CPU ARCHITECTURE 5 4 6 Special function register SFR addressing Function This addressing is to address special function registers SFRs mapped to the memory by using an 8 bit immediate data in an instruction word This addressing is applied to a 240 byte space of FFOOH FFCFH and FFEOH FFFFH However the SFRs mapped to an area of FFOOH FF1FH can also be accessed by means of short direct addressing Operand Format Representation Description Special function register name Name of special function register that can be manipulated in 16 bit units even address only Example MOV PMO A To select PMO FF20H as sfr Instruction code 11110 1 1 0 OP code 00100 0 0 O 20H sfr offset Operation OP code sfr offset SFR 15 8 7 0 128 i ri oY a lv ed CHAPTER 5 CPU ARCHITECTURE 5 4 7 Register indirect addressing Function This addressing mode is used to address the memory by using the contents of a register pair specified as an operand The register pair to be accessed is specified by the register bank select flags RBSO and RBS1 and the register pair specification code in the instruction code This addressing mode can be used across the entire memory space Operand Format P mam Example MOV A DE To select DE as register pair Instruction code 1000010 1 Operati
438. ta of serial I O shift register 0 S100 Stops operation Notes Remark x Enables operation 1 2 3 4 Bit 6 COI is a read only bit This pin can be used freely as a port COI is 0 when CSIEO 0 Don t care PMxx Port mode register Pxx Output latch of port pin Be sure to clear WUP to 0 in the 2 wire serial I O mode 329 Wi red CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78018FY SUBSERI7 b Serial bus interface control register SBIC SBIC is set by a 1 bit or 8 bit memory manipulation instruction This register is set to OOH when the RESET signal is input Symbol lt 7 gt lt 6 gt lt B gt lt 4 gt lt 3 gt lt l gt lt 0 gt Address Onreset R W SBIC BSYE ACKD ACKE a RELD CMDT RELT FF61H 00H R W SO0 latch is set to 1 when RELT 1 After setting SOO latch RELT is automatically cleared to 0 This bit is also cleared to O when CSIEO 0 R W SOO0 latch is cleared to 0 when CMDT 1 After clearing SOO latch CMDT is automatically cleared to 0 This bit is also cleared to 0 when CSIEO 0 CSIEO Bit 7 of the serial operation mode register 0 CSIMO c Interrupt timing specification register SINT SINT is set by a 1 bit or 8 bit memory manipulation instruction This register is set to OOH when the RESET signal is input Symbol 7 lt gt lt 5 gt lt 4 Address Onreset R W sur o es se sv ac paean rom om mwe R W Selects interrput source of INT
439. tage has been sampled for a specific time the sample and hold circuit enters the hold status and holds the input analog voltage until A D conversion is completed Bit 7 of the successive approximation register SAR is set The tap selector selects 1 2 AVrer as the voltage tap of the series resistor string The voltage difference between the voltage tap of the series resistor string and the analog input is compared by the voltage comparator If the analog input is higher than 1 2 AVrer the MSB of SAR remains set If it is less than 1 2 AVrer the MSB is reset Next bit 6 of SAR is automatically set and the next voltage difference is compared Here the voltage tap of the series resistor string is selected as follows according to the value of bit 7 to which the result of the first comparison has been already set e Bit7 1 3 4 AVREF e Bit7 0 1 4 AVrer This voltage tap and analog input voltage are compared and bit 6 of SAR is manipulated as follows according to the result of the comparison Analog input voltage gt voltage tap bit 6 1 Analog input voltage lt voltage tap bit 6 0 In this way all the bits of SAR including bit 0 are compared When all the 8 bits of SAR have been compared SAR holds the valid digital result whose values are transferred and latched to the A D conversion result register ADCR At the same time an A D conversion end interrupt request INTAD can be generated 251 CHAPTER 14 A D CON
440. tandard uPD78011FYGK XXX 8A8 64 pin plastic LQFP 12 x 12 mm Standard uPD78012FYCW XXX 64 pin plastic shrink DIP 750 mil Standard uUPD78012FYGC XXX AB8 64 pin plastic QFP 14 x 14 mm Standard uUPD78012FYGK XXX 8A8 64 pin plastic LQFP 12 x 12 mm Standard uUPD78013FYCW XXX 64 pin plastic shrink DIP 750 mil Standard 4PD78013FYGC XXX AB8 64 pin plastic QFP 14 x 14 mm Standard uPD78014FYCW XXX 64 pin plastic shrink DIP 750 mil Standard 4PD78014FYGC XXX AB8 64 pin plastic QFP 14 x 14 mm Standard UPD78014FYGK XXX 8A8 64 pin plastic LQFP 12 x 12 mm Standard uUPD78015FYCW XXX 64 pin plastic shrink DIP 750 mil Standard uUPD78015FYGC XXX AB8 64 pin plastic QFP 14 x 14 mm Standard uPD78016FYCW XXX 64 pin plastic shrink DIP 750 mil Standard uUPD78016FYGC XXX AB8 64 pin plastic QFP 14 x 14 mm Standard 1PD78018FYCW XXX 64 pin plastic shrink DIP 750 mil Standard uUPD78018FYGC XXX AB8 64 pin plastic QFP 14 x 14 mm Standard 4PD78P018FYCW 64 pin plastic shrink DIP 750 mil Standard HPD78P018FYDW 64 pin ceramic shrink DIP with window 750 mil Not applicable for function evaluation u4PD78P018FYGC AB8 64 pin plastic QFP 14 x 14 mm Standard uUPD78018FYGK 8A8 64 pin plastic LQFP 12 x 12 mm Standard 4PD78P018FYKK S 64 pin ceramic WQFN 14 x 14 mm Not applicable for function evaluation Caution Of the PD78P018FYDW and 78P018FYKK S do not have a reliability intended for mass production of your systems Use these models
441. ted b Chip select by address The master can select a specific slave device from those connected to the 12C bus by transmitting a slave address and communicate with that slave c Wake up function When a slave operates it generates an interrupt request when the address it has received from the master coincides with the value of the slave address register SVA the interrupt request is generated also when the stop condition is detected Therefore the slaves on the 12C bus other than the one selected by the master can operate independently of the serial communication d Acknowledge signal ACK control function The acknowledge signal that is used to check whether serial communication has been correctly executed can be controlled during the master and slave operations e Wait signal WAIT control function A slave device can control the wait signal that indicates the busy status of the slave 2 Definition of the 12C bus The following describes the serial data communication format of the 12C bus and the meanings of the signals used Figure 16 13 shows the transfer timing of the start condition data and stop condition output to the I2C serial data bus Figure 16 13 Serial Data Transfer Timing on I C Bus SDAD HO E Ne SDA1 A tee en ENTE Aa ee ATEO Taser Wace 2 eh oa haaa Gos Start Address R W ACK Data ACK Data ACK Stop condition condition The start condition slave address and stop condition are
442. tension mode when MM2 MMO 100 C100H CORE 256B extension mode COO0H when MM2 MMO 011 BFFFH Single chip mode 0000H CHAPTER 19 EXTERNAL DEVICE EXTENSION FUNCTI Figure 19 1 Memory Map when External Device Extension Function Is Used 4 4 g Memory map of uPD78018F 78018FY h Memory map of uPD78018F 78018FY 78P018F 78P018FY with 56 KB internal 78P018F 78P018FY with 60 KB internal ROM PROM ROM PROM FFFFH FFFFH FFOOH FFOOH FEFFH FEFFH Internal high speed RAM Internal high speed RAM FBOOH FBOOH FAFFH FAFFH Reserved Reserved FAEOH FAEOH FADFH FADFH Internal buffer RAM Internal buffer RAM FACOH FACOH FABFH FABFH Reserved Reserved F800H F7FFH F800H F7FFH Internal extension RAM Internal extension RAM F400H F3FFH F400H F3FFH Full address mode when MM2 MMO 111 or 16KB extension mode when MM2 MMO 101 Reserved FOOOH EFFFH FOOOH EFFFH 4KB extension mode when MM2 MMO 100 E100H EOFFH 256B extension mode oook when MM2 MMO 011 DFFFH Single chip mode Single chip mode 0000H 0000H Caution When the internal ROM PROM capacity is 60 KB the area FOOOH F3FFH is reserved This area can be used as an external memory by setting the internal ROM PROM capacity to 56 KB or less by using the memory size select register IMS 429 CHAPTER 19 EXTERNAL DEVICE EXTENSION FUNCTION 19 2 Regis
443. ter 0 CSIMO is 1 the serial operation is started when data is written to SIOO The data written to SIOO is output to the serial output line SOO or serial data bus SBO SB1 for transmission When data is received it is read from the serial input line SIO or SBO SB1 to SIOO In the SBI mode and 2 wire serial I O mode bus configuration the input and output pins are shared Therefore the device that is to receive data must write FFH to SIOO in advance except however when an address is received by setting 1 to bit 5 WUP of CSIMO In the SBI mode the busy status can be released by writing data to SIOO In this case bit 7 BSYE of the serial bus interface control register SBIC is not cleared to 0 The contents of SIOO become undefined when the RESET signal is input Slave address register SVA This 8 bit register sets the value of a slave address when the microcontroller is connected to the serial bus as a slave device It is not used in the 3 wire serial I O mode SVA is set by an 8 bit memory manipulation instruction The master outputs a slave address to the slaves connected to it to select a specific slave The slave address output by the master and the value of the SVA are compared by an address comparator If the two addresses coincide the slave is selected At this time bit 6 COI of the serial operation mode register 0 CSIMO is set to 1 The high order 7 bits of data with its LSB masked by setting the bit 4 SVAM of t
444. ters Controlling External Device Extension Function The external device expansion function is controlled by the memory expansion mode register MM and memory size select register IMS 1 Memory expansion mode register MM MM is a register that sets the number of wait states and an external expansion area lt also sets the input or output mode of port 4 MM is set by using a 1 bit or an 8 bit memory manipulation instruction Its value is set to 10H at RESET Figure 19 2 Format of Memory Extension Mode Register Symbol 7 6 5 1 0 Address On reset R W 4 3 2 MM 0 0 PW1 NE MM2 MM1 FFF8H 10H R W Selects single chip Status of P40 P47 P50 P57 P64 P67 pins MMO memory extension mode P40 P47 P50 P53 P64 P67 Single chip mode Port mode 256B Port mode mode 4KB P64 RD Memory mode P65 WR extension ADO AD7 P66 WAIT mode 16KB Port mod mode ortmode P67 ASTB A12 A13 FullNote address mode A14 A15 Setting prohibited No wait Wait 1 wait state is inserted Setting prohibited Wait control by external wait pin Note The full address mode is a mode in which the entire area of the 64K address space except the internal ROM RAM SFR and unused areas can be externally extended Remark The P60 P63 pins can be used in the port mode regardless of the single chip mode and memory extension mode 430
445. terval time of prescaler 24 fw 488 us 25 fw 977 us 28 fw 1 95 ms 27 fw 3 91 ms 28 fw 7 81 ms 29 fw 15 6 ms Others Setting prohibited Note Do not clear the prescaler frequently when using the watch timer Remarks 1 fw Watch timer clock frequency fx 28 or fxr 2 At fw 32 768 kHz operation 225 CHAPTER 10 WATCH TIMER 10 4 Operation of Watch Timer 10 4 1 Operation as watch timer The watch timer operates at time intervals of 0 5 or 0 25 seconds when the 32 768 kHz subsystem clock or 8 38 MHz main system clock is used When the 4 19 MHz main system clock is used the watch timer can operate at time intervals of 0 5 or 1 seconds Caution When the 8 38 MHz or 4 19 MHz system clock is used a slight error occurs When fx 8 38 MHz 98 214 922 X 0 5005136 seconds fx 8 38 x 106 When fx 4 19 MHz 28 221 x213 0 5005136 seconds fx 4 19 x 10 When fxt 32 768 kHz 1 14 E E 0 50000 seconds fxt 32 768 x 103 When fx 10 0 MHz this is not subject 28 922 x2M__ __ 0 4194304 seconds fx 10 0 x 10 amp The watch timer sets the test input flag WTIF to 1 at fixed time intervals When WTIF is set to 1 the standby status STOP HALT mode is released By setting bit 2 TMC22 of the watch timer mode control register to 0 the 5 bit counter is cleared
446. the stop condition is detected To generate ACK information automatically ACKE is set to 1 enable before starting transfer Others Setting prohibited Remark BSYE Bit 7 of serial bus interface control register SBIC ACKE Bit 5 of serial bus interface control register SBIC 315 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78018FY SUBSERI7 16 3 Registers Controlling Serial Interface Channel 0 The following four types of registers control serial interface channel 0 e Timer clock select register 3 TCL3 Serial operation mode register 0 CSIMO Serial bus interface control register SBIC Interrupt timing specification register SINT 1 2 316 Timer clock select register 3 TCL3 refer to Figure 16 2 This register sets the serial clock of serial interface channel 0 TCL3 is set by an 8 bit memory manipulation instruction This register is set to 88H when the RESET signal is input Remark TCL3also has a function to set the serial clock of serial interface channel 1 in addition to the function to set the serial clock of serial interface channel 0 Serial operation mode register 0 CSIMO refer to Figure 16 3 This register sets the serial clock and operation mode of serial interface channel 0 enables disables the operation of the interface sets the wakeup function and indicates the coincidence signal of the address comparator CSIMO is set by a 1 bit memory or 8 bit memory manipul
447. the address matching detection method Error detection In the SBI mode the status of the serial bus SBO SB1 is also loaded to the serial I O shift register 0 S100 of the device that is transmitting data therefore a transmit error can be detected by the following method a By comparing data of SIOO before start and after completion of transmission In this case it is judged that an error has occurred if two data are different b By using slave address register SVA The transmission data is set to SIOO and SVA and transmission is executed After completion of transmission the COI bit match signal from address comparator of the serial operation mode register 0 CSIMO is tested If this bit is 1 it is judged that transmission has been completed normally If it is 0 it is judged that an error has occurred Communication operation In the SBI mode the master usually selects one slave device for communication from two or more devices by outputting an address to the serial bus After the target device for communication has been determined commands and data are transmitted received between the master device and slave device realizing serial communication Figures 15 26 through 15 29 show the timing chart of data communication The serial I O shift register O SIOO performs shift operation in synchronization with the falling edge of the serial clock SCKO The transmit data is latched to the SOO latch and is output
448. the input instruction for port 1 while conversion is in progress otherwise the conversion resolution may be degraded If a digital pulse is applied to the pins adjacent to the pins currently used for A D conversion the expected value of the A D conversion may not be obtained due to coupling noise Therefore do not apply a pulse to the adjacent pins to the pin under A D conversion Input impedance to AVrer pin A series resistor string of about 10 kQ is connected between the AVrer and AVss pins If the output impedance of the reference voltage source is high therefore an error of the reference voltage increases by connecting the impedance in parallel with the series resistor string between the AVrer and AVss pins 257 CHAPTER 14 A D CONVERTER 6 Interrupt request flag ADIF The interrupt request flag ADIF is not cleared even when the contents of the A D converter mode register ADM are changed When the analog input pin is changed during A D conversion therefore the chances are that the A D conversion result of the old analog input and interrupt request flags are set immediately before the contents of ADM are rewritten Consequently ADIF is set even if A D conversion for the newly specified analog input pin has not yet been completed when ADIF is read immediately after ADM has been rewritten refer to Figure 14 10 To resume A D conversion that has been once stopped clear ADIF before resuming the conversion Figure 14
449. the latest version of a document for designing 14 Embedded software related documents user s manual Document Number Document Name Japanese English Fundamentals U11537J U11537E Installation U11536J U11536E Fundamental U12257J U12257E 78K 0 Series Real time OS 78K 0 Series OS MX78K0 Other related documents Document Number Document Name IC Package Manual Japanese C10943X English Semiconductor Device Mounting Technology Manual C10535J C10535E Quality Grades on NEC Semiconductor Devices C11531J C11531E Reliability and Quality Control of NEC Semiconductor Devices C10983J C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge ESD C11892J C11892E Semiconductor Quality Reliability Handbook C11893J MEI 1202 Microcomputer Related Product Guide Other Manufactures U11416J Caution The contents of the above related documents are subject to change without notice Be sure to use the latest version of a document for designing 15 MEMO 16 TABLE OF CONTENTS CHAPTER 1 GENERAL uPD78018F SUBSERIES cccsseeeeeseeeesseeeenseeeeseeeeseseeeeesseeseseeeeeneas e A scceeteetcasecevsetac aeensuccedecqugcastuanet acutess cesdavatnadsaductsceetaacterssstanuahsdeincustueastaests 1 2 Application Field secnm AKSA EAEra 1 3 Ordering Information oonmnocnccconnninnncccnarc rr
450. through P47 function as an 8 bit I O port which can be set in the input or output mode in 8 bit units by using the memory extension mode register MM When used as an input port an internal pull up resistor can be used if so specified by the pull up resistor option register PUO 2 Control mode In this mode P40 through P47 function as the low order address data bus pins ADO AD7 in the external memory extension mode The pins used as address data bus pins are automatically disconnected from the internal pull up resistor 73 CHAPTER 3 PIN FUNCTIONS uPD78018F SUBSERIES 3 2 6 P50 P57 Port5 These pins form an 8 bit I O port port 5 which also serves as an address bus These pins can directly drive LEDs Port 5 can be set in the following operation modes in 1 bit units 1 2 Port mode In this mode P50 through P57 constitute an 8 bit I O port which can be set in the input or output mode in 1 bit units by using the port mode register 5 PM5 When used as an input port an internal pull up resistor can be used if so specified by the pull up resistor option register PUO Control mode In this mode P50 through P57 function as the high order address bus pins A8 A15 in the external memory extension mode The pins used as address bus pins are automatically disconnected from the internal pull up resistor 3 2 7 P60 P67 Port6 These pins constitute an 8 bit I O port port 6 which can be also used to output control sign
451. time by ADTI refer to Figure 17 5 Format of Automatic Data Transmit Receive Interval Time Specification Register Table 17 3 Interval Time by CPU Processing with internal clock CPU Processing Interval Time With multiplication instruction used MAX 2 5 Tsck 13Tcru With division instruction used MAX 2 5 Tsck 20Tcru External access 1 wait mode MAX 2 5 Tsck 9Tcru Others Tsck fsck Tcru fcru MAX a b MAX 2 5 Tsck 7Tcru 1 fsck Serial clock frequency 1 fcpu CPU clock set by bits 0 through 2 PCCO through PCC2 of processor clock control register PCC Value of a or b whichever greater 399 CHAPTER 17 SERIAL INTERFACE CHANNEL 1 fcru SCK1 SO1 Sit fx fcPu Tcpu Tsck fsck b 400 Tsck Interval Kor X os X os Kbs Ko Yo Yor Yo X Kor X os Y os Ko Xoo Ko Yor Yo fx Main system clock oscillation frequency CPU clock set by bits 0 through 2 PCCO through PCC2 of processor clock control register PCC 1 fcPu 1 fsck Serial clock frequency When using automatic transmit receive function with external clock The external clock is used when bit 1 CSIM11 of the serial operation mode register 1 CSIM1 is cleared to 0 To use the automatic transmit receive function with the external clock the external clock must be input such that the interval time is as follows Table 17 4 Interval Time by CPU Processing with external c
452. timer and connect a crystal for oscillator for subsystem clock oscillation Port 0 is set in the input mode when the RESET signal is input Figures 6 2 through 6 4 show the block diagrams of port 0 Caution Because port 0 is also used as an external interrupt request input pin an interrupt request flag is set when the port is specified in the output mode and its output level is changed When using port 0 in the output mode therefore set the interrupt mask flag to 1 Figure 6 2 Block Diagram of P00 RD lt Edge detection Internal bus POO INTPO TIO 137 CHAPTER 6 PORT FUNCTIONS Figure 6 3 Block Diagram of P01 P03 A o PO1 INTP1 Output latch i PO1 P03 PO3 INTP3 o 3 re T f oO Lg lt PM01 PM03 e PUO pull up resistor option register PM port mode register RD read signal of port 0 WR write signal of port 0 Figure 6 4 Block Diagram of P04 Internal bus q lt Cs PO4 XT1 138 CHAPTER 6 PORT FUNCTIONS 6 2 2 Port 1 This is an 8 bit I O port with output latch It can be specified in the input or output mode in 1 bit units by using the port mode register 1 PM1 When using P10 P17 pins as input port pins internal pull up resistors can be connected in 8 bit units by using the pull up resistor option register PUO The pins of this port are also used as the analog input pins of the A D converter
453. ting is disabled or enabled by bit O TCE1 of TMC1 1 Operation as interval timer The two channels of 8 bit timer event counters are used as a 16 bit interval timer that repeatedly generates an interrupt request at time intervals specified by the count values set to the two 8 bit compare registers CR10 and CR20 in advance When setting a count value write the value of the high order 8 bits to CR20 and the value of the low order 8 bits to CR10 For the count value that can be set interval time refer to Table 9 9 When the count values of the 8 bit timer registers 1 and 2 TM1 and TM2 coincide with the values set to the corresponding compare registers CR10 and CR20 the values of TM1 and TM2 are cleared to 0 TM1 and TM2 continue counting and at the same time an interrupt request signal INTTM2 is generated For the operation timing of the interval timer refer to Figure 9 11 The count clock can be selected by the bits O through 3 TCL10 TCL13 of the timer clock select register 1 TCL1 The overflow signal of TM1 is used as the count clock for TM2 Figure 9 11 Interval Timer Operation Timing t l l l gt l 1 1 Count clock le ll de aa gee age TMS TM1 TM2 goooKoo01X X N XooooK 0001 n XooooXoo01K count value i cout starts clear clear mi i i nr i i Interrupt re accepted Interrupt oad accepted Interval time Interval time Interval
454. tion operation In the 3 wire serial I O mode data is transmitted received in 8 bit units Data is transmitted received on a 1 bit by 1 bit basis in synchronization with the serial clock The shift operation of the serial I O shift register 1 SIO1 is performed in synchronization with the falling edge of the serial clock SCK1 The transmitted data is retained by the SO1 latch and output from the SO1 pin The receive data input to the SI1 pin is latched to SIO1 at the rising edge of SCK1 When the 8 bit data has been completely transferred the operation of SIO1 is automatically stopped and a interrupt request flag CSIIF1 is set Figure 17 6 Timing of 3 Wire Serial I O Mode Transfer ends a Transfer starts in synchronization with falling edge of SCK1 Caution The SIO1 pin goes low when SO1 is written Selecting MSB LSB first In the 3 wire serial I O mode a function to select whether data is transferred with its MSB or LSB first can be used Figure 17 7 shows the configuration of the serial I O shift register 1 SIO1 and internal bus As shown in the figure data can be read or written by inverting the MSB or LSB Whether data is transferred with the MSB or LSB first can be specified by using bit 6 DIR of the serial operation mode register 1 CSIM1 al Mie 6 Internal bus 4 ed ere oe ree a a ake ie ae 1 0 LSB first MSB first Read write gate Read write gate
455. to O when CSIEO 0 R W Used to output start condition in 1 C bus mode SO0 latch is cleared to 0 when CMDT 1 After clearing SOO latch CMDT is automatically cleared to 0 This bit is also cleared to O when CSIEO 0 R RELD Stop condition detection Clearing conditions RELD 0 Setting condition RELD 1 e When transfer start instruction is executed e When values of SIOO and SVA do not coincide when address is received e When stop condition is detected in I C mode e When CSIEO 0 e When RESET is input R CMDD Start condition detection Clearing conditions CMDD 0 Setting condition CMDD 1 e When transfer start instruction is executed e When stop condition is detected in 1 C mode e When CSIEO 0 e When RESET is input e When start condition is detected in I C bus mode Note Bits 2 3 and 6 RELD CMDD and ACKD are read only bits Remark CSIEO Bit 7 of the serial operation mode register 0 CSIMO 319 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78018FY SUBSERI7 Figure 16 4 Format of Serial Bus Interface Control Register 2 2 R W Makes SDAO SDA1 low immediately after execution of setting instruction ACKT 1 until falling edge of next SCL Used to generate ACK signal by software when 8 clock wait is selected This bit is cleared to 0 when transfer of serial interface is started or when CSIEO 0 R W ACKE Acknowledge signal automatic output control Note 1 Disabl
456. transmitted in the repetitive transmit mode ARLD 1 RE 0 i Before transmission Refer to Figure 17 16 a Transmit data 1 T1 is transferred from the buffer RAM to serial I O shift register 1 SIO1 after arbitrary data has been written to SIO1 start trigger this data is not transferred When the first byte has been completely transmitted automatic data transmit receive address pointer ADTP is decremented Subsequently transmit data 2 T2 is transferred from buffer RAM to SIO1 ii When 6th byte has been transmitted Refer to Figure 17 16 b When the sixth byte has been transmitted the interrupt request flag CSIIF1 is not set The previous pointer value is assigned to the ADTP iii When 7th byte is transmitted Refer to Figure 17 16 c Transmit data 1 T1 is transferred from the buffer RAM to SIO1 again When the first byte has been completely transmitted the ADTP is decremented Subsequently transmit data 2 T2 is transferred from the buffer RAM to SIO1 CHAPTER 17 SERIAL INTERFACE CHANNEL 1 Figure 17 16 Buffer RAM Operation when 6 Bytes Are Transmitted in repetitive transmit mode a Before transmission FADFH FAC5H Transmit data 1 T1 s SIO1 Transmit data 2 T2 Da fee Transmit data 3 T3 A Ar Transmit data 4 T4 NS Transmit data 5 T5 oa FACOH Transmit data 6 T6 i o e CSIIF1 b When 6th byte has been transmitted FADFH FAC5H Transmit data 1
457. ts clock of serial interface channel 1 Clock externally input to SCK1 pinNote 1 Output of 8 bit timer register 2 TM2 Clock specified by bits 4 7 of timer clock select register 3 TCL3 Selects operation mode of serial interface channel 1 0 3 wire serial I O mode 1 3 wire serial I O mode with automatic transmit receive function DIR First bit SI1 pin function SO1 pin function Sl1 P20 SO1 input CMOS output CSIM Shift register Serial clock S11 P20 S01 P21 SCK1 P22 SIE1 PM20 P20 PM21 P21 PM22 P22 count operation i 11 1 operation control pin function pin function pin function Note 2 Note 2 Note 2 Note 2 Note 2 Operation Cleared P20 P21 P22 xixixi x x disabled CMOS 1 0 CMOS 1 0 CMOS 1 0 SCK1 Note 3 Note 3 Operation Count S 1Note 3 sot input 1 x enabled operation input CMOS output SEKI CMOS output Notes 1 When external clock input is selected by setting CSIM11 to 0 set bit 1 BUSY1 and bit 2 STRB of the automatic data transmit receive control register ADTC to 0 0 2 These pins can be used freely as port pins 3 When data is only transmitted this pin can be used as P20 CMOS I O set bit 7 RE of ADTC to 0 Remark x Don t care PMxx Port mode register Pxx Output latch of port 371 CHAPTER 17 SERIAL INTERFACE CHANNEL 1 2 SCK1 sh SO1 CSIIF1 SIO1 write 3 372 Communica
458. ty of the corresponding maskable interrupt PROL and PROH are set by a 1 bit or 8 bit memory manipulation instruction When using PROL and PROH as a 16 bit register PRO it is set by a 16 bit memory manipulation instruction These registers are set to FFH when the RESET signal is input Figure 18 4 Format of Priority Specification Flag Register Symbol 7 lt 6 lt 5 gt lt 4 lt 3 lt 2 lt 1 lt 0 Address Onreset R W PROL PPR3 PPR2 PPR1 ppro TPR FFE8H FFH RW lt 3 gt 2 lt 1 gt lt 0 gt Bo o nk ow xxPR Selects priority level 0 High priority level 1 Low priority level Cautions 1 Set the TMPR4 flag to 1 when using the watchdog timer in the watchdog timer mode 1 2 Be sure to set bits 4 through 7 of PROH to 1 408 CHAPTER 18 INTERRUPT FUNCTIONS AND TEST FUNCT 4 External interrupt mode register INTMO This register sets the valid edges of INTPO through INTP2 INTMO is set by an 8 bit memory manipulation instruction This register is set to OOH when the RESET signal is input Remarks 1 The INTPO pin is shared with TI0 PO00 2 INTP3 is fixed to the falling edge Figure 18 5 Format of External Interrupt Mode Register Symbol 7 6 5 4 3 2 1 0 Address On reset R W INTMO ES31 ES30 ES21 ES20 ES11 ES10 ofo FFECH 00H R W ES11 ES10 Selects valid edge of INTPO Falling edge Rising edge Setting prohibited Both rising and falling edges
459. uPD78016F wPD78018F uPD78P018F 4 Vectored Maskable Internal 8 external interrupt sources Non maskable Internal 1 Software 1 Test input Internal 1 external 1 Supply voltage Voo 1 8 to 5 5 V Operating ambient temperature Ta 40 to 85 C Package e 64 pin plastic shrink DIP 750 mil 64 pin plastic QFP 14 x 14 mm 64 pin plastic LQFP 12 x 12 mm 64 pin ceramic shrink DIP with window 750 mil PD78P018F only 64 pin ceramic WQFN 14 x 14 mm PD78P018F only 1 9 Differences from Standard Quality Models and A Models Table 1 1 shows the differences between the standard quality models uPD78011F 78012F 78013F 78014F 78015F 78016F 78018F and 78P018F and A models Table 1 1 Differences between Special Quality Models and A Models Classification Standard Quality Models A Models Quality grade Standard Special Package e 64 pin plastic shrink DIP 750 mil 64 pin plastic shrink DIP 750 mil e 64 pin plastic QFP 14 x 14 mm 64 pin plastic QFP 14 x 14 mm e 64 pin plastic LQFP 12 x 12 mm e 64 pin ceramic shrink DIP with window 750 mil uPD78P018F only 64 pin ceramic WQFN 14 x 14 mm uPD78P018F only 50 CHAPTER 1 GENERAL uPD78018F SUBSERIES Z ADS inued 1 10 Differences between A Model and A2 Model Table 1 2 shows the differences between the A model uPD78012F A and A2 model uPD78012F A
460. ubseries TOO P30 Switching circuit Low pass filter Analog output Van signal Figure 8 13 shows an example where the PWM output is converted into an analog voltage and applied for a TV tuner of voltage synthesizer type Figure 8 13 Example of Application Circuit TV Tuner uPD78018F 110V uPD78018FY subseries BA 22 kQ 47 KQ 47KQ 47KQ 100 pF m sae 0 22uF 0 22uF 0 22uF Electronic A s 8 2k0 2352 uPC tuner 574J 8 2 kQ 777 191 i ri oY a lv ed CHAPTER 8 16 BIT TIMER EVENT COUNTER 8 5 3 Operation as pulse width measurement The 16 bit timer register TMO can be used to measure the pulse width of the signal input to the TIO POO pin Measurement is carried out in two ways One is to measure the pulse width with the TMO in the free running status and the other is to measure the pulse width by restarting the timer in synchronization with the valid edge of the signal input to the TIO POO pin 1 Free running pulse width measurement If an edge specified by the external interrupt mode register INTMO is input to the TIO POO pin while the 16 bit timer register TMO operates in free running the value of TMO is captured to the 16 bit capture register CRO1 and an external interrupt request signal INTPO is set Three types of edges can be selected by bits 2 and 3 ES10 and ES11 of INTMO rising falling and both rising and falling edges To detect the valid edge sampli
461. uctions SP gt Register pair low SP gt PC7 PCO SP gt PC7 PCO SP 1 Register pair high SP 1 PC15 PC8 SP 1 PC15 PC8 SP lt SP 2 SP lt SP 2 SP 2 PSW SP lt SP 3 104 CHAPTER 5 CPU ARCHITECTURE 5 2 2 General purpose registers General purpose registers are mapped to the specific addresses of the data memory FEEOH FEFFH Four banks of general purpose registers each consisting of eight 8 bit registers X A C B E D L and H are available Each register can be used as an 8 bit register Moreover two 8 bit registers can be used as a register pair which are 16 bit registers AX BC DE and HL Each register can be written not only in function name X A C B E D L H AX BC DE or HL but also in absolute name RO R7 RPO RP3 The register bank used for instruction execution is set by the CPU control instruction SEL RBn Because four register banks are provided an efficient program can be developed by using one register bank for ordinary processing and another bank for interrupt processing Table 5 6 Absolute Addresses of General Purpose Registers Register Register Absolute Absolute Function Absolute Address Bank valine Function Absolute Address Name Name Name Name Bank Name H L D E B e A x H L D E B Cc A x X gt OJO0O mM O rr T X gt O U m O ri Tt 1
462. uffer RAM uPD78011F 8 KB HPD78012F 16 KB 4PD78013F 24 KB uPD78014F 32 KB uPD78015F 40 KB uPD78016F 48 KB uPD78018F 60 KB 1024 B uPD78P018F 60 KBNote 1 1024 BNote 2 1024 BNote 3 Notes 1 8 16 24 32 40 48 or 60 KB is selectable by using memory size select register IMS 2 512 or 1024 B is selectable by using IMS 3 0 512 or 1024 B is selectable by using internal extension RAM size select register IXS External memory extension space 64 KB Variable minimum instruction execution time from high speed 0 4 us with 10 0 MHz main system clock to ultra slow 122 us with 32 768 kHz subsystem clock e Instruction set suitable for system control Bit processing in entire address space Multiplication division instructions e I O port 53 lines N ch open drain 4 lines e 8 bit resolution A D converter 8 channels Low voltage operation AVpp 1 8 to 5 5 V operable in supply voltage range same as that of the CPU e Serial interface 2 channels 3 wire serial I O SBI 2 wire mode 1 channel 3 wire serial I O mode with automatic transmit receive function 1 channel Timer 5 channels 16 bit timer event counter 1 channel 8 bit timer event counter 2 channels Watch timer 1 channel Watchdog timer 1 channel e Vectored interrupt source 14 e Test input 2 lines e Two types of clock oscillation circuits main system clock and subsystem clock Supply voltage
463. ulse to the high order 14 bits of CROO Select the active level by the bit 1 TOCO1 of the 16 bit timer output control register TOCO The PWM pulse has a resolution of 14 bits lt can be converted into an analog voltage when integrated by an external low pass filter LPF This pulse is created by using the basic cycle determined by 28 and subcycle determined by 21 4 in combination and is designed to shorten the time constant of the external LPF Count clock 9 can be selected by bits 4 through 6 TCLO4 TCLO6 of the timer clock select register O TCLO PWM output can be enabled or disabled by the bit 0 TOE0 of TOCO Cautions 1 Set CROO after selecting the PWM operation mode 2 Be sure to write 0 to the bits 0 and 1 of CROO 3 When an external clock is input from the TIO POO INTPO pin do not select the PWM operation mode 190 CHAPTER 8 16 BIT TIMER EVENT COUNTER By integrating the PWM pulse with a 14 bit resolution by using an external low pass filter the pulse can be converted into an analog voltage which can be used for electronic tuning and D A conversion The analog output voltage Van used for D A conversion whose configuration is shown in Figure 8 12 can be calculated by the following expression Value of compare register CROO Van VREF X 216 where Vrer reference voltage of external switching circuit Figure 8 12 Example of Configuration of D A Converter Using PWM Output uUPD78018F HPD78018FY s
464. unter refer to Figure 8 3 ae iF Aa i Ya d ES YSLNNOO 1N3A3 43NIL LI8 91 8 YILAVHO 821 Figure 8 2 Block Diagram of 16 Bit Timer Event Counter PWM Mode Internal bus 16 bit compare register CROO f 2 gt PWM pulse generation circuit fx 2 Selector 2 16 bit timer register TMO O T TCLOS TCLOS TCLO4 16 bit capture register CRO1 TOCO1 TOEO Timer clock select register 0 16 bit timer output control register Internal bus Remark The portion enclosed in dotted line is included in the output control circuit P30 output A A TOO P30 Port mode register 3 YSLNNOO LNSAR YAWIL LI8 91 8 YILAVHO 6ZI Figure 8 3 Block Diagram of 16 Bit Timer Event Counter Output Control Circuit Level F F LVO Y LVRO i i l 2 LVSO 3 D TOC01 l l ps o 3 2 INTTMO gt F 3 Edge i TIO POO INTPO detection circuit 3 Active level control PWM pulse ES10 ES11 generation a i circuit i l l TMC01 TMC03 TOCO1 TMC01 TMCO3 Remark The output control circuit is shown enclosed by dotted line TOEO P30 output latch TOO P30 YSLNNOO LNSAS YAWIL LIG 9l 8 YILAVHO CHAPTER 8 16 BIT TIMER EVENT COUNTER 1 2 3 180 16 bit compare register CR00 This register always compares its set value in CROO
465. upt Internal bus Interrupt Priority control macior taole p Y it address request circu generation circuit IF Interrupt request flag IE Interrupt enable flag ISP In service priority flag MK Interrupt mask flag PR Priority specification flag 404 CHAPTER 18 INTERRUPT FUNCTIONS AND TEST FUNCT 18 3 Registers Controlling Interrupt Function The following six types of registers control the interrupt function Interrupt request flag registers IFOL IFOH Interrupt mask flag registers MKOL MKOH e Priority specification flag registers PROL PROH External interrupt mode register INTMO Sampling clock select register SCS Program status word PSW Table 18 2 shows the names of the interrupt request flags interrupt mask flags and priority specification flags corresponding to the respective interrupt request sources Table 18 2 Flags Corresponding to Respective Interrupt Request Sources Interrupt Source Interrupt Request Flag Interrupt Mask Flag Priority Specification Flag Register Register Register NTWDT TMIF4 TMMK4 TMPR4 NTPO PIFO PMKO PPRO NTP1 PIF1 PMK1 PPR1 INTP2 PIF2 PMK2 PPR2 INTP3 PIF3 PMK3 PPR3 INTCSIO CSIIFO CSIMKO CSIPRO INTCSI1 CSIIF1 CSIMK1 CSIPR1 INTTM3 TMIF3 TMMK3 TMPR3 NTTMO TMIFO TMMKO TMPRO NTTM1 TMIF1 TMMK1 TMPR1 NTTM2 TMIF2 TMMK2 TMPR2 NTAD ADIF ADMK ADPR 405 CHAPTER 18 INTERRUPT FUNCTIONS AND TEST FUNCTIONS
466. ure 8 23 Operation Timing of OVFO Flag Count pulse Y CROO FFFFH mo er eX oe Xe Y OVFO INTTMOO 198 al UNO CHAPTER 9 8 BIT TIMER EVENT COUNTER 9 1 Function of 8 Bit Timer Event Counter The PD78018F 78018FY subseries is provided with 8 bit timer event counters which can be used in the following two modes e 8 bit timer event counter mode Two channels of 8 bit timer event counters are individually used 16 bit timer event counter mode Two channels of 8 bit timer event counters are used in combination as a 16 bit timer event counter 9 1 1 8 bit timer event counter mode The 8 bit timer event counters 1 and 2 TM1 and TM2 have the following functions Interval timer External event counter Square wave output 199 CHAPTER 9 8 BIT TIMER EVENT COUNTER 1 8 bit interval timer When an 8 bit timer event counter is used as an interval timer it generates an interrupt request at any time intervals set in advance Table 9 1 Interval Time of 8 Bit Timer Event Counter Maximum Interval Time Resolution 210 x 1 fx 102 4 us 22 x 1 fx 400 ns Minimum Interval Time 22 x 1 fx 400 ns 23 x 1 fx 800 ns 211 x 1 fx 204 8 us 23 x 1 fx 800 ns 24 x 1 fx 1 6 us 25 x 1 fx 3 2 us 212 x 1 fx 409 6 us 24 x 1 fx 1 6 us 213 x 4 fx 819 2 us 25 x 1 fx 3 2 us 28 x 1 fx 6 4 us 214 x 1 fx 1 64 ms 28 x 1 fx 6 4 us 27 x 1 fx 12 8 us 215
467. us has been released transfer is started When 8 bit transfer has been completed serial transfer is automatically stopped and an interrupt request flag CSIIFO is set Be sure to perform the following setting to the pin that is used to input output data SBO or SB1 before serial transfer of 1 byte after the RESET signal has been input lt 1 gt Set 1 to the output latches of P25 and P26 lt 2 gt Set bit 0 RELT of the serial bus interface control register SBIC to 1 lt 3 gt Set 0 to the output latches of P25 and P26 to which 1 has been set before 10 Method to judge busy state of a slave Check whether a slave is in the busy status from the device in the master mode in the following procedure lt 1 gt Detect generation of the acknowledge signal ACK or interrupt request signal lt 2 gt Set the port mode register PM25 or PM26 of the SBO P25 or SB1 P26 pin in the input mode lt 3 gt Read the status of the pin if the pin is high it is in the ready status After detecting the ready status set 0 to the port mode register to restore the output mode 301 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 uPD78018F SUBSERIEF 11 Notes on SBI mode 302 a Whether a slave is selected or not is detected by matching of a slave address that has been received after the bus release signal has been issued RELD 1 To detect matching of addresses an address match interrupt INTCSIO that is generated when WUP 1 is
468. us mode CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78018FY SUBSERIES Addition of Notes to Figure 17 5 Format of Automatic Data Transmission Reception Interval Specification Register Addition of Notes to 17 4 3 3 d Busy control option CHAPTER 17 SERIAL INTERFACE CHANNEL 1 Addition of following products IE 78000 R A IE 70000 98 IF B IE 70000 98N IF IF 70000 PC IF B IE 78000 R SV3 ID78KO Addition of description on how to upgrade other in circuit emulators to IE 78000 R A APPENDIX A DEVELOPMENT TOOLS Version of supported OS upgraded APPENDIX A DEVELOPMENT TOOLS APPENDIX B EMBEDDED SOFTWARE 4th edition 518 Addition of following products as applicable models 1PD78011F A 78012F A 78013F A 78014F A 78015F A 78016F A 78018F A 78P018F A 78012F A2 1PD78011FYGK 78012FYGK 78014FYGK 78P018FYGK Following products developed uUPD78P018FDW 78P018FKK S 78P018FYDW 78P018FYKK S Throughout Addition of notes on changing operation mode of serial interface channel O CHAPTER 15 SERIAL INTERFACE CHANNEL 0 uPD78018F SUBSERIES CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78018FY SUBSERIES Addition of notes to Table 23 1 Differences between uUPD78P018F 78P018FY and Mask ROM Model CHAPTER 23 uPD780P018F 78P018FY Addition of APPENDIX A DIFFERENCES BETWEEN uPD78014 78014H AND 78018F SUBSERIES APPENDIX A DIFFERENCES BETWEEN 1PD78014 78014H AND 78018F SUB
469. use the RETI instruction to return from the software interrupt 417 al UNO CHAPTER 18 INTERRUPT FUNCTIONS AND TEST FUNCTIONS 18 4 4 Nesting Accepting another interrupt request while an interrupt is being serviced is called nesting Nesting does not take place unless the interrupts except the non maskable interrupt are enabled to be accepted IE 1 Accepting another interrupt request is disabled IE 0 when one interrupt has been accepted Therefore to enable nesting the El flag must be set to 1 during interrupt servicing to enable the another interrupt Nesting may not occur even when the interrupts are enabled This is controlled by the priorities of the interrupts Although two types of priorities default priority and programmable priority may be assigned to an interrupt nesting is controlled by using the programmable priority If an interrupt with the same level of priority as or the higher priority than the interrupt currently serviced occurs that interrupt can be accepted and nested If an interrupt with a priority lower than that of the currently serviced interrupt occurs that interrupt cannot be accepted and nested An interrupt that is not accepted and nested because it is disabled or it has a low priority is kept pending This interrupt is accepted after servicing of the current interrupt has been completed and one instruction of the main routine has been executed Nesting is not enabled while the non maskable
470. uzzer output function set 0 to the PM36 bit of this register and the output latch of the P36 pin PMS is set by a 1 bit or 8 bit memory manipulation instruction This register is set to FFH when the RESET signal is input Figure 13 3 Format of Port Mode Register 3 Address On reset R W 3 2 1 0 PM3 PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30 FF23H FFH RW 244 PM3n Selects I O mode of P3n pin n 0 7 0 Output mode output buffer ON 1 Input mode output buffer OFF CHAPTER 14 A D CONVERTER 14 1 Function of A D Converter The A D converter converts an analog input signal into a digital value and consists of eight channels ANIO ANI7 with a resolution of 8 bits This A D converter is of successive approximation type and the result of conversion is held by an 8 bit A D conversion result register ADCR A D conversion can be started in the following two ways 1 Hardware start Conversion is started by trigger input INTP3 2 Software start Conversion is started by setting the A D conversion mode register ADM Select one channel of analog input from ANIO ANI7 and execute A D conversion When A D conversion has been started by means of hardware start conversion is stopped after the operation has been completed and an interrupt request INTAD is generated When A D conversion has been started by means of software start conversion is repeatedly performed Each time conversion has bee
471. val time is dependent on ADIT is selected by setting of the bit 7 ADTI7 of ADTI If ADTI7 is reset to 0 the interval time is dependent on the CPU processing only If ADTI7 is set to 1 the interval time determined by the set contents of ADTI or interval time by the CPU processing is selected whichever greater To use the automatic transmit receive function with the external clock the external clock must be input in the manner that the interval time is equal to or greater than the time described in b below Figure 17 23 Interval Time of Automatic Transmission Reception Interval SOKi sor _ Xo7KpsXosKoaXosKo2Xoixoo XD7XD6XD5XD4XD3XD2XD1XD0 sit __Ko7XveXoskoaXosXo2koiXo0___Xo7kosXosXD4kosXD2X01 Xoo CSIIF1 CSIIF1 Interrupt request flag 398 CHAPTER 17 SERIAL INTERFACE CHANNEL 1 i ri oY a lv ed a When using automatic transmit receive function with internal clock The internal clock is used when bit 1 CSIM11 of the serial operation mode register 1 CSIM1 is set to 1 To use the automatic transmit receive function with the internal clock the interval time by the CPU processing is as follows When bit 7 ADTI7 of the automatic data transmit receive interval specification register ADTI is reset to O the interval time is that by the CPU processing When ADTI7 is set to 1 the interval time is that determined by the set contents of ADTI or that by the CPU processing whichever greater For the interval
472. valid b Busy amp strobe control option Strobe control is a function to synchronize data transmission reception between the master and slave devices The master device outputs the strobe signal from the STB P23 pin when 8 bit transmission reception has been completed By this signal the slave device can determine the timing of the end of data transmission Therefore synchronization is established even if a bit shift occurs because noise is superimposed on the serial clock and transmission of the next byte is not affected by the bit shift To use the strobe control option the following conditions must be satisfied Bit 5 ATE of the serial operation mode register 1 CSIM1 is set to 1 Bit 2 STRB of the automatic data transmit receive control register ADTC is set to 1 Usually the busy control and strobe control options are simultaneously used as handshake signals In this case the strobe signal is output from the STB P23 pin and the BUSY P24 pin is sampled and transmission reception can be kept waiting while the busy signal is input When the strobe control option is not used the P23 STB pin can be used as a normal I O port pin Figure 17 21 shows the operation timing when the busy amp strobe control options are used When the strobe control option is used the interrupt request flag CSIIF1 that is set on completion of transmission reception is set after the strobe signal is output 395 CHAPTER 17 SERIAL INTERFACE CHAN
473. vel signal output to SCL WAT1 WATO 1 X Indicates that serial reception cannot be executed Serial clock SCL Synchronization clock for outputting signals Address A6 A0 Master 7 bit data output in synchronization with SCL after start condition has been output Transfer direction R W 1 bit data output in synchronization with SCL after address has been output Data D7 DO Master slave 8 bit data output in synchronization with SCL not immediately after start condition Execution of instruction that writes data to SIO0 when CSIEO 1 serial transfer start instruction Note 2 Sets CSIIFO Note 3 Synchronization signal for serial communica tion Indicates address value on serial bus that specifies slave Indicates whether data is transmitted or received Indicates data actually communicated Notes 1 The level of the serial clock can be controlled by the CLC bit in interrupt timing specification register SINT 2 Serial transfer is started in the wait status after the wait status has been released 3 If 8 clock wait is selected with WUP 0 CSIIFO is set at the rising edge of the eighth clock of SCL When 9 clock wait is selected with WUP 0 CSIIFO is set at the rising edge of the ninth clock of SCL An address is received when WUP 1 and CSIIFO is set if that address coincides with the value of the slave address register SVA and if the stop
474. version result register 247 ADIS A D converter input select register 250 ADM A D converter mode register 248 ADTC Automatic data transmit receive control register 365 374 ADTI Automatic data transmit receive interval specification register 367 376 ADTP Automatic data transmit receive address pointer 362 C CORADO Correction address register 0 454 CORAD1 Correction address register 1 454 CORCN Correction control register 455 CROO 16 bit compare register 180 CRO1 16 bit capture register 180 CR10 8 bit compare register 205 CR20 8 bit compare register 205 CSIMO Serial operation mode register 0 265 271 272 284 303 316 323 324 328 338 CSIM1 Serial operation mode register 1 364 370 371 373 1 IFOH Interrupt request flag register OH 406 423 IFOL Interrupt request flag register OL 406 IMS Memory size select register 431 465 INTMO External interrupt mode register 186 409 IXS Internal extension RAM size select register 467 K KRM Key return mode register 154 424 M MKOH Interrupt mask flag register OH 407 423 MKOL Interrupt mask flag register OL 407 MM Memory extension mode register 153 430 0 OSTS Oscillation stabilization time select register 440 P PO Port 0 137 P1 Port 1 139 P2 Port 2 140 142 P3 Port 3 144 P4 Port 4 145 P5 P
475. vironment gt The MX78K 0 is a DOS based application It should be used in the DOS Prompt when using in Windows Part Number uSxxxxMX78K0 AAA Remark xxxx and AAA in the part number differ depending on the host machine and OS used uSxxxxMX78K0 AAA AAA Product Outline Maximum Number for Use in Mass Production Evaluation object Use in preproduction stages Mass production object Use in mass production stages Source program Only the users who purchased mass production objects are allowed to purchase this program Host Machine Supply Medium AA13 PC 9800 Series Windows Japanese version Note 1 2 3 5 inch 2HD FD AB13 IBM PC AT and its compatibles Windows Japanese version Note 1 2 3 5 inch 2HC FD BB10 Windows English version Note 1 2 3P16 HP9000 Series 700 HP UX Rel 9 05 DAT DDS 3K13 SPARCstation SunOS Rel 4 1 4 3 5 inch 2HC FD 3K15 1 4 inch CGMT 3R13 NEWS RISC NEWS OS Rel 6 1 3 5 inch 2HC FD Notes 1 Can also be operated in DOS environment 2 Not support WindowsNT 511 MEMO 512 APPENDIX D REGISTER INDEX D 1 Register Index In Alphabetical Order with Respect to Register Name A A D conversion result register ADCR 247 A D converter input select register ADIS 250 A D converter mode register ADM 248 Automatic data transmit receive address pointer ADTP 362 Automatic data transmit receive
476. voz Signal Name Serial clock SCKO Definition Synchronous clock for output of address com mand data ACK signal and synchronous BUSY signal Address command data is transferred when first eight of this signal are output Table 15 4 Signals in SBI Mode 2 2 Timing Chart SCKO 1 2 7 10 Address A7 A0 Master 8 bit data transferred in synchronization with SCKO after REL and CMD signals have been output SCKO 2 7 REL CMD Command C7 C0 Master 8 bit data transferred in synchronization with SCKO after only CMD signal is output REL signal is not output SCKO a 2 7 Ls CMD Master slave 8 bit data transferred in synchronization with SCKO when both REL and CMD signals are not output SCKO 1 2 z Le Notes 1 When WUP 0 CSIIFO is always set at the rising edge of the 9th clock of SCKO Output Condition Execution of instruction that writes data to SIO0 when CSIEO 1 serial transfer start command Note 2 Influence on Flag CSIIFO is set rising edge of 9th clock of SCKO Note 1 Meaning of Signal Timing of signal output to serial data bus Address value of slave device on serial bus Command or message to slave device Numeric value processed by slave or master device al akmal WOU GMD Legh i UA SAIMSSAENS 481084007 0 TANNVHO AJ0VAYALNI IVIHIS SI HILAVHO When WU
477. with the count value of the 16 bit timer register TMO When the two values coincide an interrupt request INTTMO is generated When TMO is set as an interval timer this register can also be used to hold interval time and when set as a PWM output operation this can also be used to set a pulse width CROO is set by a 16 bit memory manipulation instruction in a range of 0001 H FFFFH The contents of this register become undefined when the RESET signal is input Cautions 1 Set data of PWM 14 bits to the high order 14 bits of CROO At this time set the low order 2 bits to 00 2 Set CROO to any value other than 0000H Thus one pulse will not be counted when the timer is used as an event counter 3 If the new value of CROO is less than the value of the 16 bit timer register TMO TMO continues counting overflows and counts again from 0 If the new value of CROO M is less than the previous value N it is necessary to restart the timer 16 bit capture register CRO1 This 16 bit register captures the contents of the 16 bit timer register TMO The capture trigger is the valid edge input to the INTPO TIO pin The valid edge of INTPO is set by the external interrupt mode register INTMO CRO1 is read by a 16 bit memory manipulation instruction The contents of this register become undefined when the RESET signal is input Caution If the valid edge of the TIO POO pin is input while CRO1 is read CRO1 does not perform the capture
478. wledge signal it has not received the data correctly Consequently the master outputs a stop condition to abort transmission Figure 16 17 Acknowledge Signal SCL 1 leal sl Jal 5 Je Iz Jel lo SDAO SDA1 336 i rir lv ed CHAPTER 16 SERIAL INTERFACE CHANNEL 0 1PD78018FY S e Stop condition The stop condition is output when the SDAO SDA1 pin goes high while the SCL pin is high The stop condition is output by the master to the slave when serial transfer has been completed The slave has hardware to detect the stop condition Figure 16 18 Stop Condition SCL f Wait signal WAIT The wait signal is output by a slave to the master to indicate that the slave is getting ready for data transmission reception in wait status The slave informs the master that it is in the wait status by making the SCL pin low When the slave is released from the wait status the master can start the next transfer For how to release a slave from the wait status refer to 16 4 5 Notes on using 1 C bus mode Figure 16 19 Wait Signal a 8 clock wait Master makes SCL Hi Z slave makes it low Slave does not wait after 9th clock has been transmitted time required by master to start next transmission SCL of master SCL of slave SDAO SDA1 lize Output through manipulation of ACKT 337 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78018FY SUBSERI7 b 9 clock wait ES Master makes SCL Hi Z
479. x 1 fx 1 6 us 25 x 1 1x 3 2 us 221 x 1 fx 209 7 ms 25 x 1 1x 3 2 us 28 x 4 fx 6 4 us 222 x 1 fx 419 4 ms 27 x 1 fx 12 8 us 223 x 1 fx 838 9 ms 28 x 1 fx 6 4 us 27 x 1 fx 12 8 us 28 x 1 1x 25 6 us 224 x 1 fx 1 7 s 28 x 1 1x 25 6 us 210 x 1 fx 102 4 us 226 x 1 fx 6 7 s 210 x 1 fx 102 4 us 29 x 1 fx 51 2 us 225 x 1 fx 3 4 s 29 x 1 fx 51 2 us 212 x 1 fx 409 6 us 228 x 1 fx 26 8 s 212 x 1 fx 409 6 us Remarks 1 fx Main system clock oscillation frequency 2 TCL10 TCL13 Bits O through 3 of timer clock select register 1 TCL1 3 At fx 10 0 MHz operation Figure 9 13 Square Wave Output Timing Count Ap e 9 pp o pp o pp y y o LS clock TM1 OOH JOA TN TNT 7 JEFHIOOAI a a TJFFHIOOHIOTHT A T OT lt TM2 OOH ora TRA cc MAA CR10 j N i CR20 j M i TO2 n Interval time E 4 4 Count starts Level inversion Counter cleared 218 i ri oY a lv ed CHAPTER 9 8 BIT TIMER EVENT COUNTER 9 5 Notes on Using 8 Bit Timer Event Counters 1 Error on starting timer An error of up to 1 clock occurs after the timer has been started until a coincidence signal is generated This is because the 8 bit timer registers 1 and 2 TM1 and TM2 are started in asynchronization with the count pulse Figure 9 14 Start Timing of 8 Bit Timer Register Gountpulse A NENA NEAL NA
480. x 1 fx 104 9 ms 2 at fx 10 0 MHz operation 29 x 1 fx 51 2 us 212 x 1 fx 409 6 us main system clock oscillation frequency CHAPTER 9 8 BIT TIMER EVENT COUNTER 9 1 2 16 bit timer event counter mode 1 16 bit interval timer When two 8 bit timer event counters are used in combination as a 16 bit interval timer it generates an interrupt request at any time intervals set in advance Table 9 3 Interval Time of 8 Bit Timer Event Counters Used as 16 Bit Timer Event Counter Minimum Interval Time Maximum Interval Time Resolution 22 x 1 fx 400 ns 218 x 1 fx 26 2 ms 22 x 1 fx 400 ns 23 x 1 fx 800 ns 219 x 1 fx 52 4 ms 23 x 1 fx 800 ns 24 x 1 fx 1 6 us 220 x 1 fx 104 9 ms 24 x 1 fx 1 6 us 25 x 1 fx 3 2 us 221 x 1 fx 209 7 ms 25 x 1 fx 3 2 us 28 x 4 fx 6 4 us 222 x 1 fx 419 4 ms 27 x 1 fx 12 8 us 223 x 1 fx 838 9 ms 28 x 1 fx 6 4 us 27 x 4 fx 12 8 us 28 x 1 fx 25 6 us 22 x 1 fx 1 7 s 28 x 1 fx 25 6 us 210 x 1 fx 102 4 us 228 x 1 fx 6 7 s 210 x 1 fx 102 4 us 29 x 1 fx 51 2 us 225 x 1 fx 3 4 s 29 x 1 fx 51 2 us 212 x 1 fx 409 6 us 228 x 1 fx 26 8 s 212 x 1 fx 409 6 us Remarks 1 fx main system clock oscillation frequency 2 at fx 10 0 MHz operation 2 External event counter The number of pulses of an externally input signal can be measured
481. xample of Reducing Current Consumption in Standby Mode Voo Output port gt La TIT AVREF AVrer Voo Series resistor string AVss H4PD78018F 78018FY subseries 2 ANIO ANI7 input range 256 Observe the rated range of the ANIO ANI7 input voltage If a voltage of AVrer or higher or AVss or lower even in the range of absolute maximum ratings is input to an analog input channel the converted value of that channel becomes undefined In addition the converted values of the other channels may also be affected al UNO CHAPTER 14 A D CONVERTER 3 4 5 Countermeasures against noise To keep the resolution of 8 bits noise superimposed on the AVrer and ANIO ANI7 pins must be suppressed as much as possible The higher the output impedance of the analog input source the greater the effect To suppress noise connecting an external capacitor as shown in Figure 14 9 is recommended Figure 14 9 Processing Analog Input Pin If there is a possibility that noise AVrer or higher or AVss or lower is input clamp the noise by using a diode with a low Vr 0 3 V MAX Reference AVhrer voltage input O y A AVher ANIO ANI7 ANIO P10 ANI7 P17 The analog input pins ANIO ANI7 are also used as I O port pins port 1 To use these pins as the analog input pins specify the input mode When A D conversion is performed with any of ANIO ANI7 selected do not execute
482. xecutes interrupt processing Executes next address instruction Executes interrupt processing Retains HALT mode Non maskable interrupt request Executes interrupt processing Test input Executes next address instruction Retains HALT mode RESET input Reset processing Remark x Don t care 444 CHAPTER 20 STANDBY FUNCTION 20 2 2 STOP mode 1 Setting and operation status of STOP mode The STOP modeis set by executing the STOP instruction This mode can be set only when the system operates on the main system clock Cautions 1 When the STOP mode is set X2 pin is internally pulled up circuited to Voo to suppress the current leakage of the crystal oscillation circuit block Therefore do not use the STOP mode in a system where the external clock is used as the main system clock 2 Because the standby mode can be released by an interrupt request signal the standby mode is released as soonas it is set if there is an interrupt source whose interrupt request flag is set and interrupt mask flag is reset When the STOP mode is set therefore the HALT mode is set immediately after the STOP instruction has been executed the wait times set by the oscillation stabilization time select register OSTS elapses and then an operation mode is set The following table shows the operation status in the STOP mode Setting of STOP Clock generation circuit Table 20 3 Operation Status in STOP
483. xternal Device Extension Function Is Used oooocccnccccccncccccoccccnnccnnns 426 19 2 Format of Memory Extension Mode Register ooooocconnnccononcccnnonncnnonnnononnnnn non nnnnnn cnc ran narran nn 430 19 3 Format of Memory Size Select Register eccceeceeseeeeeeeeeeeeeeeeeeeseeeeeaeeseaeeeeeteeeeeeeeeaees 431 19 4 Instruction Fetch from External Memory eeeeeeeseeseneeeeeneeeeeeaeeeeeaeeeseeeeeesaeeeeeneeereneeees 433 19 5 Read Timing of External Memory coooooccnnccccnnonccononononanononnnnnnnn nn nnnnnn cnn ran nnn rn nr rn 434 19 6 Write Timing of External Memory coooocccnoccccnoncncnnonccnnnoncnnoncnnnnn cn naar nnn nano nn nan nnrnnr nr enana na nnnnnncnns 435 19 7 Read Modify Write Timing of External Memory c oooooioccccnnocccnonccnnnoncnonannnononnnn naar cnc nan nnnnnnnnnns 436 19 8 Example of Connecting uPD78014F and Memories occoocccnccccoccnoncnonccconncnnnncnnccnnnncancnnnnnnns 437 20 1 Format of Oscillation Stabilization Time Select Register oooooonccnnnnninccninccnncnconcnnncncancninnnons 440 20 2 Releasing HALT Mode by Interrupt Request coooooccccnoccconoccconoccnonanncnnonccnnnn ono nnno nro r na nnnnn nn 443 20 3 Releasing HALT Mode by RESET Input csesscssssssssssessessssssssssessessssessesseesesessesseeseeneees 444 20 4 Releasing STOP Mode by Interrupt Request ccoccococccncconociconcconcncnncnnnncnancnnnnc nan cc nn nc cancnnnncnns 446 20 5 Releasing STOP Mode by RESET Input ccsssssssessesse
484. y Part Number Capacity Structure uPD78011F 78011FY Mask ROM 8192 x 8 bits 0000H 1FFFH HPD78012F 78012FY 16384 x 8 bits 0000H 3FFFH HPD78013F 78013FY 24576 x 8 bits 0000H 5FFFH HPD78014F 78014FY 32768 x 8 bits 0000H 7FFFH HPD78016F 78016FY 49152 x 8 bits 0000H BFFFH 1PD78015F 78015FY 40960 x 8 bits 0000H 9FFFH 4PD78018F 78018FY 61440 x 8 bits QOOOH EFFFH HPD78P018F 78P018FY 61440 x 8 bits QOOOH EFFFH The following areas are allocated to the internal program memory space 1 Vector table area A 64 byte area of addresses 0000H 003FH is reserved as a vector table area This area stores program start addresses to which execution branches when the RESET signal is input or when an interrupt request is generated Of a 16 bit program start address the low order 8 bits are stored in an even address and the high order 8 bits are stored in an odd address Table 5 2 Vector Table Vector Table Address Interrupt Source Vector Table Address Interrupt Source RESET input INTCSI1 INTWDT INTTM3 INTPO INTTMO INTP1 INTTM1 INTP2 INTTM2 INTP3 INTAD INTCSIO BRK instruction 2 CALLT instruction table area In a 64 byte area of addresses 0040H 007FH the subroutine entry address of a 1 byte call instruction CALLT can be stored 3 CALLF instruction entry area From an area of addresses 0800H OFFFH a subr
485. y software 8 bit I O port N ch open drain I O port Can be specified for input output bitwise Internal pull up resistor can be specified by mask option with mask ROM model only Can directly drive LED When used as input port internal pull up resistor can be connected by software 135 CHAPTER 6 PORT FUNCTIONS 6 2 Port Configuration A port consists of the following hardware Table 6 3 Port Configuration Item Configuration Control register Port mode register PMm m 0 1 2 3 5 or 6 Pull up resistor option register PUO Memory extension mode register MM Note Key return mode register KRM Total 53 lines Input 2 lines 1 0 51 lines Pull up resistor Total 51 lines Software control 47 lines Mask option control 4 lines Note The memory extension mode register specifies the input output mode of port 4 136 i rN a lu ed CHAPTER 6 PORT FUNCTIONS 6 2 1 Port 0 This is a 5 bit I O port with output latch P01 P03 pins can be specified in the input or output mode in 1 bit units by using the port mode register 0 PMO POO and P04 pins are input port pins When P01 P03 pins are used as input port pins internal pull up resistors can be connected in 3 bit units by using the pull up resistor option register PUO The five port pins are also used to input external interrupt requests an external count clock to the
486. z The buzzer frequency selected by using the timer clock select register TCL2 is output from the BUZ P36 pin The buzzer frequency is output in the following procedure lt 1 gt Select a buzzer output frequency by the bits 5 through 7 TCL25 TCL27 of TCL2 lt 2 gt Set 0 to the output latch of the P36 pin lt 3 gt Set 0 to bit 6 PM36 of port mode register 3 to set the output mode Caution When 1 is set to the output latch of the P36 pin the buzzer output function cannot be used 13 2 Configuration of Buzzer Output Control Circuit The buzzer output control circuit consists of the following hardware Table 13 1 Configuration of Buzzer Output Control Circuit Control register Timer clock select register 2 TCL2 Port mode register 3 PM3 Figure 13 1 Block Diagram of Buzzer Output Control Circuit fx 210 5 1 y ia 2 ie Bo BUZ P36 fx 212 oO 3 Hb YT TCL27 TCL26 TCL25 P36 output latch PM36 Timer clock select register 2 Port mode register 3 Internal bus 241 i ri oY a lv ed CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT 13 3 Registers Controlling Buzzer Output Function The following two types of registers control the buzzer output function e Timer clock select register 2 TCL2 Port mode register 3 PM3 1 Timer clock select register 2 TCL2 This register sets the frequency of buzzer output TCL2 is set by an 8 bit memory manipulation instructi

uPD78018F, 78018FY Subseries 8-bit Single

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