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ADSP-2189M DSP Microcomputer

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1. ADSP 2189M Fabricated in a high speed low power CMOS process the ADSP 2189M operates with a 13 3 ns instruction cycle time Every instruction can execute in a single processor cycle The ADSP 2189M s flexible architecture and comprehensive instruction set allow the processor to perform multiple opera tions in parallel In one processor cycle the ADSP 2189M can Generate the next program address Fetch the next instruction Perform one or two data moves Update one or two data address pointers Perform a computational operation This takes place while the processor continues to Receive and transmit data through the two serial ports Receive and or transmit data through the internal DMA port Receive and or transmit data through the byte DMA port Decrement timer DEVELOPMENT SYSTEM The ADSP 2100 Family Development Software a complete set of tools for software and hardware system development sup ports the ADSP 2189M The System Builder provides a high level method for defining the architecture of systems under development The Assembler has an algebraic syntax that is easy to program and debug The Linker combines object files into an executable file The Simulator provides an interactive instruc tion level simulation with a reconfigurable user interface to display different portions of the hardware environment A PROM Splitter generates PROM programmer compatible files The C Compiler based on the Free Software
2. I O Memory Interface with 2048 Locations Supports Parallel Peripherals Mode Selectable Programmable Memory Strobe and Separate 1 0 Memory Space Permits Glueless System Design Programmable Wait State Generation Two Double Buffered Serial Ports with Companding Hardware and Automatic Data Buffering Automatic Booting of On Chip Program Memory from Byte Wide External Memory e g EPROM or Through Internal DMA Port ICE Port is a trademark of Analog Devices Inc REV A Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices FUNCTIONAL BLOCK DIAGRAM POWER DOWN CONTROL FULL MEMORY aap PROGRAMMABLE ME DATA ADDRESS PROGRAM DATA VO GENERATORS P MEMORY MEMORY AND EXTERNAL ADDRESS 4 32K x 48K x FLAGS 24 BIT 16 BIT Bus EXTERNAL PROGRAM MEMORY ADDRESS RATA m 4 J L t DATA MEMORY ADDRESS BYTE DMA s Doe LE CONTROLLER PROGRAM MEMORY DATA OR DATA MEMORY DATA EXTERNAL DATA gt BUS ARITHMETIC UNITS SERIAL PORTS INTERNAL MAC SHIFTER SPORT 0 SPORT 1 l PORT ADSP 2100 BASE J HOST MODE ARCHITECTURE Six External Interrupts 13
3. processor to use its ERESET EBR and EBG pins instead of the RESET BR and BG pins The BG output is three stated These signals do not need to be jumper isolated in your system The EZ ICE connects to your target system via a ribbon cable and a 14 pin female plug The female plug is plugged onto the 14 pin connector a pin strip header on the target board Target Board Connector for EZ ICE Probe The EZ ICE connector a standard pin strip header is shown in Figure 13 You must add this connector to your target board design if you intend to use the EZ ICE Be sure to allow enough room in your system to fit the EZ ICE probe onto the 14 pin connector KEY NO PIN Bo 8 volo E ELOUT Em 2 4 L 6 L 8 E 10 E 12 E 14 E E TOP VIEW Figure 13 Target Board Connector for EZ ICE The 14 pin 2 row pin strip header is keyed at the Pin 7 loca tion you must remove Pin 7 from the header The pins must be 0 025 inch square and at least 0 20 inch in length Pin spac ing should be 0 1 x 0 1 inches The pin strip header must have at least 0 15 inch clearance on all sides to accept the EZ ICE probe plug Pin strip headers are available from vendors such as 3M McKenzie and Samtec REV A Target Memory Interface For your target system to be compatible with the EZ ICE emu lator it must comply with the memory interface guidelines listed below PM DM BM IOM and CM Design your Program Me
4. the Byte DMA port and the power down circuitry There is also a master REV A RESET signal The two serial ports provide a complete synchro nous serial interface with optional companding in hardware and a wide variety of framed or frameless data transmit and receive modes of operation Each port can generate an internal programmable serial clock or accept an external serial clock The ADSP 2189M provides up to 13 general purpose flag pins The data input and output pins on SPORT 1 can be alternatively configured as an input flag and an output flag In addition eight flags are programmable as inputs or outputs and three flags are always outputs A programmable interval timer generates periodic interrupts A 16 bit count register TCOUNT decrements every n processor cycles where n is a scaling value stored in an 8 bit register TSCALE When the value of the count register reaches zero an interrupt is generated and the count register is reloaded from a 16 bit period register TPERIOD Serial Ports The ADSP 2189M incorporates two complete synchronous serial ports SPORTO and SPORT for serial communications and multiprocessor communication Here is a brief list of the capabilities of the ADSP 2189M SPORTS For additional information on Serial Ports refer to the ADSP 2100 Family User s Manual Third Edition SPORTS are bidirectional and have a separate double buff ered transmit and receive section SPORTS can use an exter
5. 100 Lead LQFP Package Pinout zE o wW W x aa Q aro lO oo O qaqa Ed xz SSSeERREZESRESTIRNAR ZEEE 2 eh S9ESEGEtsSeeete see S888 AAAA e BlslsisislsssssssS ss Ss elslslsl elei e X PIN IDENTIFIER TOP VIEW Not to Scale amp SIR Y R BY o ES SS Seo 9 SS xS SS LeS SL See D oro ooo rc ul I PEZEEERBSESEERRESS HR BESS SE 2 OSCR EFF OGTR ET SOGZARBuM Qonim ues l Jw o 2 O e ioc Ww Sis Be S ui fe fe 30 D15 D14 D13 D12 GND D11 69 D10 D6 IRD 62 D5AAL DA IS 60 GND 59 Voor 58 D3 IACK D2 IAD15 REV A ADSP 2189M The ADSP 2189M package pinout appears in the following table Pin names in bold text replace the plain text named functions when Mode C 1 A sign separates two functions when either function can be active for either major I O mode Signals enclosed in brackets are state bits latched from the value of the pin at the deassertion of RESET PIN CONFIGURATION LQFP LQFP LQFP LQFP Number Pin Name Number Pin Name Number Pin Name Number Pin Name 1 A4 IAD3 26 IRQE PF4 51 EBR 76 D16 2 A5 IAD4 27 IRQLO PF5 52 BR TI D17 3 GND 28 GND 53 EBG 78 D18 4 A6 IADS 29 IRQLI PF6 54 BG 79 D19 5 A7 IAD6 30 IRQ2 PF7 55 DO IAD13 80 GND 6 A8 IAD7 31 DTO 56 DI IAD14 81 D20 7 A9 IADS 32 TFSO 57 D2 IAD15 82 D21 8 A10 IAD9 33 RFSO 58 D3 IACK 83 D22 9 A11 IAD10 34 DRO 59 VppINT 84 D23 10 A12 IAD11 35 SCLKO 60 GND 85 FL2 11 A13 IAD12 36 VppEXT 61 DA S 86 F
6. 6 V Vor Hi Level Output Voltage Vppgxr min loy 0 5 mA 2 0 V Q VpDEXT 3 0 V lou 0 5mA 2 4 V Vppexr min Ion 100 pA Vppzxr 0 2 V Vor Lo Level Output Voltage Vppext min IoL 2 mA 0 4 V Im Hi Level Input Current Vppint max Vy 3 6 V 10 uA Ir Lo Level Input Current Vppint max Vin 0 V 10 uA Iozu Three State Leakage Current Vppmr max Vy 3 6 V 10 uA Iozr Three State Leakage Current Vppmt max Vy 0 V 10 uA Ipp Supply Current Idle Vppint 2 5 tex 15 ns 9 mA Ipp Supply Current Idle Vpprwr 2 5 tcx 13 3 ns 10 mA Ipp Supply Current Dynamic Vppmt 2 5 tcx 15 ns Tamp 25 C 32 mA Ipp Supply Current Dynamic Vppmt 2 5 tex 13 3 ns Tamp 25 C 36 mA Ipp Supply Current Power Down Lowest Power Mode 150 uA Cy Input Pin Capacitance 5 Vin 2 5 V fin 1 0 MHz Tamp 25 C 8 pF Co Output Pin Capacitance 14 Vin 2 5 V fin 1 0 MHz TAMB 25 C 8 pF NOTES Bidirectional pins D0 D23 RFS0 RFS1 SCLK0 SCLK1 TFS0 TFS1 A1 A13 PF0 PF7 Input Only pins RESET BR DRO DR1 PWD Input Only pins CLKIN RESET BR DRO DR1 PWD Output pins BG PMS DMS BMS IOMS CMS RD WR PWDACK A0 DT0 DT1 CLKOUT FL2 0 BGH Although specified for TTL outputs all ADSP 2189M outputs are CMOS compatible and will drive to V ppgxr and GND assuming no dc lo
7. BDMA access but is stopped The other device can release the bus by deasserting bus request Once the bus is released the ADSP 2189M deasserts BG and BGH and executes the external memory access Flag I O Pins The ADSP 2189M has eight general purpose programmable input output flag pins They are controlled by two memory mapped registers The PFTYPE register determines the direc tion 1 output and 0 input The PFDATA register is used to read and write the values on the pins Data being read from a pin configured as an input is synchronized to the ADSP 2189M s clock Bits that are programmed as outputs will read the value being output The PF pins default to input during reset In addition to the programmable flags the ADSP 2189M has five fixed mode flags FLAG_IN FLAG_OUT FLO FL1 and FL2 FLO FL2 are dedicated output flags FLAG_IN and FLAG_OUT are available as an alternate configuration of SPORTI Note Pins PF0 PF1 PF2 and PF3 are also used for device configuration during reset INSTRUCTION SET DESCRIPTION The ADSP 2189M assembly language instruction set has an algebraic syntax that was designed for ease of coding and read ability The assembly language which takes full advantage of the processor s unique architecture offers the following benefits d s The algebraic syntax eliminates the need to remember cryp tic assembler mnemonics For example a typical arithmetic add instruction such as AR AX0 AYO r
8. LOAD FROM BM 1 2 STORE TO BM BCR 0 RUN DURING BDMA 1 HALT DURING BDMA Figure 9 BDMA Control Register The BDMA circuit supports four different data formats which are selected by the BTYPE register field The appropriate num ber of 8 bit accesses are done from the byte memory space to build the word size selected Table VI shows the data formats supported by the BDMA circuit Table VI Data Formats Internal BTYPE Memory Space Word Size Alignment 00 Program Memory 24 Full Word 01 Data Memory 16 Full Word 10 Data Memory MSBs 11 Data Memory 8 LSBs Unused bits in the 8 bit data memory formats are filled with 0s The BIAD register field is used to specify the starting address for the on chip memory involved with the transfer The 14 bit BEAD register specifies the starting address for the external byte memory space The 8 bit BMPAGE register specifies the start ing page for the external byte memory space The BDIR register field selects the direction of the transfer Finally the 14 bit BWCOUNT register specifies the number of DSP words to transfer and initiates the BDMA circuit transfers 10 BDMA accesses can cross page boundaries during sequential addressing A BDMA interrupt is generated on the completion of the number of transfers specified by the BWCOUNT register The BWCOUNT register is updated after each transfer so it can be used to check the status of the transfers When it reaches Zero the tra
9. Programmable Flag Pins Provide Flexible System Signaling UART Emulation through Software SPORT Reconfiguration ICE Port Emulator Interface Supports Debugging in Final Systems GENERAL DESCRIPTION The ADSP 2189M is a single chip microcomputer optimized for digital signal processing DSP and other high speed nu meric processing applications The ADSP 2189M combines the ADSP 2100 family base archi tecture three computational units data address generators and a program sequencer with two serial ports a 16 bit internal DMA port a byte DMA port a programmable timer Flag I O extensive interrupt capabilities and on chip program and data memory The ADSP 2189M integrates 192K bytes of on chip memory configured as 32K words 24 bit of program RAM and 48K words 16 bit of data RAM Power down circuitry is also pro vided to meet the low power needs of battery operated portable equipment The ADSP 2189M is available in a 100 lead LQFP package In addition the ADSP 2189M supports new instructions which include bit manipulations bit set bit clear bit toggle bit test new ALU constants new multiplication instruction x squared biased rounding result free ALU operations I O memory trans fers and global interrupt masking for increased flexibility One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 World Wide Web Site http www analog com Fax 781 326 8703 Analog Devices Inc 2000
10. dress ranges as shown in Table V Table V Wait States Address Range 0x000 0x1 FF 0x200 0x3FF 0x400 0x5FF 0x600 0x7FF Wait State Register IOWAITO and Wait State Mode Select Bit IOWAIT1 and Wait State Mode Select Bit IOWAIT2 and Wait State Mode Select Bit IOWAIT3 and Wait State Mode Select Bit Composite Memory Select CMS The ADSP 2189M has a programmable memory select signal that is useful for generating memory select signals for memories mapped to more than one space The CMS signal is generated to have the same timing as each of the individual memory select signals PMS DMS BMS IOMS but can combine their functionality When set each bit in the CMSSEL register causes the CMS signal to be asserted when the selected memory select is as serted For example to use a 32K word memory to act as both program and data memory set the PMS and DMS bits in the CMSSEL register and use the CMS pin to drive the chip select of the memory and use either DMS or PMS as the additional address bit The CMS pin functions like the other memory select signals with the same timing and bus request logic A 1 in the enable bit causes the assertion of the CMS signal at the same time as the selected memory select signal All enable bits default to 1 at reset except the BMS bit Byte Memory Select BMS The ADSP 2189M s BMS disable feature combined with the CMS pin lets you use multiple memories in the byte mem
11. edge sensitive The priorities and vector addresses of all interrupts are shown in Table I REV A ADSP 2189M Table I Interrupt Priority and Interrupt Vector Addresses Interrupt Vector Source Of Interrupt Address Hex RESET or Power Up with PUCR 1 0000 Highest Priority Power Down Nonmaskable 002C IRQ2 0004 IRQLI 0008 IRQLO 000C SPORTO Transmit 0010 SPORTO Receive 0014 IRQE 0018 BDMaA Interrupt 001C SPORT 1 Transmit or IROI 0020 SPORT 1 Receive or IRQO 0024 Timer 0028 Lowest Priority Interrupt routines can either be nested with higher priority interrupts taking precedence or processed sequentially Inter rupts can be masked or unmasked with the IMASK register Individual interrupt requests are logically ANDed with the bits in IMASK the highest priority unmasked interrupt is then selected The power down interrupt is nonmaskable The ADSP 2189M masks all interrupts for one instruction cycle following the execution of an instruction that modifies the IMASK register This does not affect serial port autobuffering or DMA transfers The interrupt control register ICNTL controls interrupt nest ing and defines the IRQO IRQI and IRQ2 external interrupts to be either edge or level sensitive The IRQE pin is an external edge sensitive interrupt and can be forced and cleared The IRQLO and IRQLI pins are external level sensitive interrupts The IFC register is a write
12. is specified by a select able divisor given in the IDLE instruction The format of the instruction is IDLE n where n 16 32 64 or 128 This instruction keeps the proces sor fully functional but operating at the slower clock rate While it is in this state the processor s other internal clock signals such as SCLK CLKOUT and timer clock are reduced by the same ratio The default form of the instruction when no clock divisor is given is the standard IDLE instruction When the IDLE n instruction is used it effectively slows down the processor s internal clock and thus its response time to in coming interrupts The one cycle response time of the standard idle state is increased by n the clock divisor When an enabled interrupt is received the ADSP 2189M will remain in the idle state for up to a maximum of n processor cycles n 16 32 64 or 128 before resuming normal operation When the IDLE n instruction is used in systems that have an externally generated serial clock SCLK the serial clock rate may be faster than the processor s reduced internal clock rate Under these conditions interrupts must not be generated at a ADSP 2189M faster rate than can be serviced due to the additional time the processor takes to come out of the idle state a maximum of n processor cycles SYSTEM INTERFACE Figure 2 shows typical basic system configurations with the ADSP 2189M two serial devices a byte wide EPROM and opti
13. of Read 0 ns ikpD IAD15 0 Data Disabled after End of Read 10 ns URDE IAD15 0 Previous Data Enabled after Start of Read 0 ns trrpv IAD 15 0 Previous Data Valid after Start of Read 11 ns tmpHi IAD15 0 Previous Data Hold after Start of Read DM PM1 2tck 2 ns trrpH2 IAD 15 0 Previous Data Hold after Start of Read PM2 tcx 5 ns NOTES IStart of Read IS Low and IRD Low End of Read IS High or IRD High 3DM read or first half of PM read 4Second half of PM read TACK gt tikur tkr 1s IRD IAD15 0 Figure 31 IDMA Read Long Read Cycle 28 REV A ADSP 2189M Parameter Min Max Unit IDMA Read Short Read Cycle Timing Requirements tr IACK Low before Start of Read 0 ns tIRP Duration of Read 10 ns Switching Characteristics UKHR IACK High after Start of Read 10 ns trkpH IAD15 0 Data Hold after End of Read 0 ns ikbD IAD15 0 Data Disabled after End of Read 10 ns trRDE IAD15 0 Previous Data Enabled after Start of Read 0 ns trrpv IAD 15 0 Previous Data Valid after Start of Read 10 ns NOTES IStart of Read IS Low and IRD Low End of Read IS High or IRD High tiroe IAD15 0 Figure 32 IDMA Read Short Read Cycle REV A 29 ADSP 2189M A4 IAD3 AS IAD4 GND A6 IADS A7NAD6 A8 IAD7 A9 IAD8 A10 IAD9 A11 IAD10 A12 IAD11 A13 IAD12 GND CLKIN XTAL VppExT CLKOUT GND VppiNT las gi ul age oi o o 9o al o Ol NY gt N
14. only register used to force and clear interrupts On chip stacks preserve the processor status and are automatically maintained during interrupt handling The stacks are twelve levels deep to allow interrupt loop and subroutine nesting The following instructions allow global enable or dis able servicing of the interrupts including power down regard less of the state of IMASK Disabling the interrupts does not affect serial port autobuffering or DMA ENA INTS DIS INTS When the processor is reset interrupt servicing is enabled LOW POWER OPERATION The ADSP 2189M has three low power modes that significantly reduce the power dissipation when the device operates under standby conditions These modes are Power Down dle Slow Idle The CLKOUT pin may also be disabled to reduce external power dissipation Power Down The ADSP 2189M processor has a low power feature that lets the processor enter a very low power dormant state through hardware or software control Here is a brief list of power down features Refer to the ADSP 2100 Family User s Manual REV A 5 Third Edition System Interface chapter for detailed infor mation about the power down feature Quick recovery from power down The processor begins executing instructions in as few as 200 CLKIN cycles Support for an externally generated TTL or CMOS proces sor clock The external clock can continue running during power down without affecting th
15. program memory and data memory of the DSP with only one DSP cycle per word overhead The IDMA port cannot however be used to write to the DSP s memory mapped control registers A typical IDMA transfer process is described as follows 1 Host starts IDMA transfer 2 Host checks IACK control line to see if the DSP is busy 3 Host uses IS and IAL control lines to latch either the DMA starting address IDMAA or the PM DM OVLAY selection into the DSP s IDMA control registers If Bit 15 1 the value of bits 7 0 represent the IDMA overlay Bits 14 8 must be set to 0 If Bit 15 0 the value of bits 13 0 represent the starting address of internal memory to be accessed and Bit 14 reflects PM or DM for access 4 Host uses IS and IRD or IWR to read or write DSP inter nal memory PM or DM 5 Host checks IACK line to see if the DSP has completed the previous IDMA operation 6 Host ends IDMA transfer REV A ADSP 2189M The IDMA port has a 16 bit multiplexed address and data bus and supports 24 bit program memory The IDMA port is com pletely asynchronous and can be written while the ADSP 2189M is operating at full speed The DSP memory address is latched and then automatically incremented after each IDMA transaction An external device can therefore access a block of sequentially addressed memory by specifying only the starting address of the block This in creases throughput as the address does not have to be sent for ea
16. with a frequency equal to half the instruction rate a 37 50 MHz input clock which is equivalent to 28 ns yields a 13 ns proces sor cycle equivalent to 75 MHz tcx values within the range of 0 5tcxy period should be substituted for all relevant timing pa rameters to obtain the specification value Example tcxy O 5tck 7 ns 0 5 15 ns 7 ns 0 5 ns ENVIRONMENTAL CONDITIONS Rating Description Symbol Value Thermal Resistance Case to Ambient Oca 48 C W Junction to Ambient Oya 50 C W Junction to Case ic 2 C W NOTE Where the ambient temperature rating T mp is Tams Tcasz PD x Oca Tcasg Case temperature in C PD Power dissipation in W POWER DISSIPATION To determine total power dissipation in a specific application the following equation should be applied for each output Cx Vpp x f C load capacitance f output switching frequency Example In an application where external data memory is used and no other outputs are active power dissipation is calculated as follows Assumptions External data memory is accessed every cycle with 50 of the address pins switching External data memory writes occur every other cycle with 50 of the data pins switching Each address and data pin has a 10 pF total load at the pin The application operates at Vppgxr 3 3 V and tcp 15 ns Total Power Dissipation Pry C x Vppexr X f Pinr internal power dissipation from P
17. 0 300 200 100 2 25 2 35 2 5 2 65 2 75 Vpp INTERNAL Volts Figure 18 IDD Power Down ADSP 2189M TEST CONDITIONS Output Disable Time Output pins are considered to be disabled when they have stopped driving and started a transition from the measured output high or low voltage to a high impedance state The out put disable time tpys is the difference of tugAsuggp and tprcays as shown in the Output Enable Disable diagram The time is the interval from when a reference signal reaches a high or low voltage level to when the output voltages have changed by 0 5 V from the measured output high or low voltage The decay time tpgcay is dependent on the capacitive load Ci and the current load ir on the output pin It can be ap proximated by the following equation Cr x0 57V tpECAY ir from which tpis tMEASURED DECAY is calculated If multiple pins such as the data bus are disabled the measurement value is that of the last pin to stop driving INPUT 1 5V 2 0V OUTPUT 1 5V 0 8V Figure 19 Voltage Reference Levels for AC Measurements Except Output Enable Disable Output Enable Time Output pins are considered to be enabled when they have made a transition from a high impedance state to when they start 18 driving The output enable time tgya is the interval from when a reference signal reaches a high or low voltage level to when the output has reached a s
18. 24 I O Data I O Pins for Program Data Byte and I O Spaces 8 MSBs are also used as Byte Memory addresses Host Mode Pins Mode C 1 Pin of Name Pins I O Function IAD15 0 16 I O IDMA Port Address Data Bus AO 1 O Address Pin for External I O Program Data or Byte Access D23 8 16 IO Data I O Pins for Program Data Byte and I O Spaces IWR 1 I IDMA Write Enable IRD 1 I IDMA Read Enable IAL 1 I IDMA Address Latch Pin IS 1 I IDMA Select IACK 1 O IDMA Port Acknowledge Config urable in Mode D Open Drain NOTE lIn Host Mode external peripheral addresses can be decoded using the A0 CMS PMS DMS and IOMS signals Interrupts The interrupt controller allows the processor to respond to the eleven possible interrupts and reset with minimum overhead The ADSP 2189M provides four dedicated external interrupt input pins IRQ2 IRQLO IRQL1 and IRQE shared with the PF7 4 pins In addition SPORT1 may be reconfigured for IRQO IRQ1 FLAG_IN and FLAG_OUT for a total of six external interrupts The ADSP 2189M also supports internal interrupts from the timer the byte DMA port the two serial ports software and the power down control circuit The inter rupt levels are internally prioritized and individually maskable except power down and reset The IRQ2 IRQO and IRQI input pins can be programmed to be either level or edge sensi tive IRQLO and IRQL are level sensitive and IRQE is
19. A a aaa BMWAIT CMSSEL PFTYPE BIT 15 ADSP 2189M 0 DISABLE CMS 0 INPUT 1 ENABLE CMS 1 OUTPUT WHERE BIT 11 IOM 10BM 9 DM 8 PM Figure 7 Programmable Flag and Composite Select Con trol Register SYSTEM CONTROL 15 14 1312 1110 9 8 7 6 5 4 3 2 TeTeT T IsTeTeTeTeTs To T 7 owoorro ST OT RESERVED ALWAYS 0 PWAIT ADSP 2189M PROGRAM MEMORY SPORTO ENABLE WAIT STATES 0 DISABLE 1 ENABLE DISABLE BMS ADSP 2189M 0 ENABLE BMS 1 DISABLE BMS EXCEPT WHEN MEMORY STROBES ARE THREE STATED SPORT1 ENABLE 0 DISABLE 1 ENABLE SPORT1 CONFIGURE 0 FI FO IRQO IRQ1 SCLK 12 SPORT1 Figure 8 System Control Register REV A 9 I O Space Full Memory Mode The ADSP 2189M supports an additional external memory space called I O space This space is designed to support simple connections to peripherals such as data converters and external registers or to bus interface ASIC data registers I O space supports 2048 locations of 16 bit wide data The lower eleven bits of the external address bus are used the upper three bits are undefined Two instructions were added to the core ADSP 2100 Family instruction set to read from and write to I O memory space The I O space also has four dedicated three bit wait state registers IOWAITO0 3 which in combination with the wait state mode bit specify up to 15 wait states to be automatically generated for each of four regions The wait states act on ad
20. ANALOG DEVICES DSP Microcomputer ADSP 2189M FEATURES PERFORMANCE 13 3 ns Instruction Cycle Time 9 2 5 Volts Internal 75 MIPS Sustained Performance Single Cycle Instruction Execution Single Cycle Context Switch 3 Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle Multifunction Instructions Power Down Mode Featuring Low CMOS Standby Power Dissipation with 200 CLKIN Cycle Recovery from Power Down Condition Low Power Dissipation in Idle Mode INTEGRATION ADSP 2100 Family Code Compatible Easy to Use Alge braic Syntax with Instruction Set Extensions 192K Bytes of On Chip RAM Configured as 32K Words On Chip Program Memory RAM and 48K Words On Chip Data Memory RAM Dual Purpose Program Memory for Both Instruction and Data Storage Independent ALU Multiplier Accumulator and Barrel Shifter Computational Units Two Independent Data Address Generators Powerful Program Sequencer Provides Zero Overhead Looping Conditional Instruction Execution Programmable 16 Bit Interval Timer with Prescaler 100 Lead LOFP SYSTEM INTERFACE Flexible I O Structure Allows 2 5 V or 3 3 V Operation All Inputs Tolerate Up to 3 6 V Regardless of Mode 16 Bit Internal DMA Port for High Speed Access to On Chip Memory Mode Selectable 4 MByte Memory Interface for Storage of Data Tables and Program Overlays Mode Selectable 8 Bit DMA to Byte Memory for Transparent Program and Data Memory Transfers Mode Selectable
21. DE C PFO IS MODE A Figure 22 Clock Signals REV A 19 ADSP 2189M Parameter Min Max Unit Interrupts and Flags Timing Requirements tres IRQx FI or PFx Setup before CLKOUT Low 4 0 25tcy 10 ns iH IRQx FI or PFx Hold after CLKOUT High 0 25tcK ns Switching Characteristics tFOH Flag Output Hold after CLKOUT Low 0 5tck 5 ns trop Flag Output Delay from CLKOUT Low 0 5tcg 4 ns NOTES If IRQx and FI inputs meet typs and typy setup hold requirements they will be recognized during the current clock cycle otherwise the signals will be recognized on the following cycle Refer to Interrupt Controller Operation in the Program Control chapter of the ADSP 2100 Family User s Manual Third Edition for further information on interrupt servicing Edge sensitive interrupts require pulsewidths greater than 10 ns level sensitive interrupts must be held low until serviced IRQx IRQO IRQI IRQ2 IRQLO IRQLI IRQLE PFx PFO PF1 PF2 PF3 PF4 PF5 PF6 PF7 Flag Outputs PFx FLO FL1 FL2 Flag out4 CLKOUT FLAG OUTPUTS a iru IRQx FI PFx 4 trs gt Figure 23 Interrupts and Flags 20 REV A ADSP 2189M Parameter Min Max Unit Bus Request Bus Grant Timing Requirements aS tay BR Hold after CLKOUT High 0 25tcx 2 ns tps BR Setup before CLKOUT Low 0 25tck 10 ns Switching Characteristics SUME tsp CLKOUT High to
22. ERNAL ACCESSIBLE WHEN MEMORY PMOVLAY 4 Ox3FFF RESERVED 0x1FFF2 0x2000 ACCESSIBLE WHEN Ox3FFF ACCESSIBLE WHEN 0x0000 PMOVLAY 5 PMOVLAY 1 Ox1FFF ACCESSIBLE WHEN 0x2000 EXTERNAL PMOVLAY 1 0x3FFF2 MEMORY RESERVED EXTERNAL ACCESSIBLE WHEN MEMORY PMOVLAY 2 1WHEN MODE B 1 PMOVLAY MUST BE SET TO 0 PROGRAM MEMORY MODE B 0 ADDRESS Ox3FFF 8K INTERNAL PMOVLAY 0 4 5 OR 8K EXTERNAL PMOVLAY 1 2 0x2000 Ox1FFF 8K INTERNAL 0x0000 SEE TABLE Ill FOR PMOVLAY BITS PROGRAM MEMORY MODE B 1 ADDRESS OX3FFF 8K INTERNAL PMOVLAY 0 0x2000 Ox1FFF 8K EXTERNAL 0x0000 Figure 4 Program Memory Mode D 1 and in host mode IACK is an open source and requires an external pull down but multiple IACK pins can be wire OR ed together MEMORY ARCHITECTURE The ADSP 2189M provides a variety of memory and peripheral interface options The key functional groups are Program Memory Data Memory Byte Memory and I O Refer to the following figures and tables for PM and DM memory allocations in the ADSP 2189M Program Memory Program Memory Full Memory Mode is a 24 bit wide space for storing both instruction op codes and data The ADSP 2189M has 32K words of Program Memory RAM on chip and the capability of accessing up to two 8K external memory overlay spaces using the external data bus Program Memory Host Mode allows access to all internal memory External overlay acce
23. Foundation s GNU C Compiler generates ADSP 2189M assembly source code The source code debugger allows programs to be cor rected in the C environment The Runtime Library includes over 100 ANSI standard mathematical and DSP specific functions The EZ KIT Lite is a hardware software kit offering a complete development environment for the entire ADSP 21xx family an ADSP 218x based evaluation board with PC monitor software plus Assembler Linker Simulator and PROM Splitter software The ADSP 218x EZ KIT Lite is a low cost easy to use hard ware platform on which you can quickly get started with your DSP software design The EZ KIT Lite includes the following features 33 MHz ADSP 218x Full 16 bit Stereo Audio I O with AD1847 SoundPort Codec RS 232 Interface to PC with Windows 3 1 Control Software EZ ICE Connector for Emulator Control DSP Demo Programs The ADSP 218x EZ ICE Emulator aids in the hardware de bugging of an ADSP 2189M system The emulator consists of hardware host computer resident software and the target board connector The ADSP 2189M integrates on chip emulation support with a 14 pin ICE Port interface This interface pro vides a simpler target board connection that requires fewer mechanical clearance considerations than other ADSP 2100 Family EZ ICEs The ADSP 2189M device need not be re moved from the target system when using the EZ ICE nor are any adapters needed Due to the small footprint of the EZ ICE connec
24. I O Pin During Normal Operation CLKIN XTAL 2 I Clock or Quartz Crystal Input CLKOUT 1 O Processor Clock Output SPORTO 5 I O Serial Port I O Pins SPORTI 5 I O Serial Port I O Pins IRQI 0 FI FO Edge or Level Sensitive Interrupts Flag In Flag Out PWD 1 I Power Down Control Input PWDACK 1 O Power Down Control Output FLO FL1 FL2 3 O Output Flags VppINT 2 I Internal VDD 2 5 V Power VDDEXT 4 I External VDD 2 5 V or 3 3 V Power GND 10 I Ground EZ Port 9 T O For Emulation Use NOTES nterrupt Flag Pins retain both functions concurrently If IMASK is set to enable the corresponding interrupts then the DSP will vector to the appropri ate interrupt vector address when the pin is asserted either by external devices or set as a programmable flag SPORT configuration determined by the DSP System Control Register Soft ware configurable Memory Interface Pins The ADSP 2189M processor can be used in one of two modes Full Memory Mode which allows BDMA operation with full external overlay memory and I O capability or Host Mode which allows IDMA operation with limited external addressing capabilities The operating mode is determined by the state of the Mode C pin during RESET and cannot be changed while the processor is running Full Memory Mode Pins Mode C 0 Pin of Name Pins I O Function A13 0 14 O Address Output Pins for Program Data Byte and I O Spaces D23 0
25. KST 300 ADSP 2189MBST 266 75 MHz 66 MHz 0 C to 70 C 40 C to 85 C 100 Lead LQFP 100 Lead LQFP ST 100 ST 100 In 1998 JEDEC reevaluated the specifications for the TQFP package designation assigning it to packages 1 0 mm thick Previously labelled TQFP packages 1 6 mm thick are now designated as LQFP 32 REV A C3605a 0 4 00 rev A PRINTED IN U S A
26. L1 12 GND 37 DTI 62 D5 IAL 87 FLO 13 CLKIN 38 TFS1 63 D6 IRD 88 PF3 Mode D 14 XTAL 39 RFSI 64 D7 IWR 89 PF2 Mode C 15 VppExT 40 DRI 65 D8 90 VppEXT 16 CLKOUT 41 GND 66 GND 91 PWD 17 GND 42 SCLK1 67 VppEXT 92 GND 19 WR 44 RESET 69 D10 94 PFO Mode A 20 RD 45 EMS 70 D11 95 BGH 21 BMS 46 EE 71 GND 96 PWDACK 22 DMS 47 ECLK 72 D12 97 AO 23 PMS 48 ELOUT 73 D13 98 Al IADO 24 IOMS 49 ELIN 74 D14 99 A2 IAD1 25 CMS 50 EINT 75 D15 100 A3 IAD2 REV A 31 ADSP 2189M OUTLINE DIMENSIONS Dimensions shown in inches and mm 100 Lead Metric Thin Plastic Quad Flatpack ST 100 0 638 16 20 0 630 16 00 TY 0 622 15 80 0 553 14 05 0 549 13 95 0 063 1 60 MAX 0 551 14 00 TYP SQ P SQ gt 0050075 4 r 0 472 12 00 BSC 0 024 0 60 TYP__ Fa 76 0 020 0 50 ld n x oo 1 75 SEATING PLANE TOP VIEW PINS DOWN 0 003 E 0 08 m 51 MAX LEAD toa 26 50 COPLANARITY 6x4 0 7 fle gt e a ls 0 007 0 177 0 020 0 50 0 011 0 27 0 005 0 127 TYP BSC 0 009 0 22 TYP 0 003 0 077 LEADPITCH 0 007 0 17 LEAD WIDTH NOTE THE ACTUAL POSITION OF EACH LEAD IS WITHIN 0 08 0 0032 FROM ITS IDEAL POSITION WHEN MEASURED IN THE LATERAL DIRECTION CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED ORDERING GUIDE Part Number Ambient Temperature Range Instruction Rate Package Description Package Option ADSP 2189M
27. MODE pins specify BDMA booting the ADSP 2189M initiates a BDMA boot sequence when reset is released The BDMA interface is set up during reset to the following defaults when BDMA booting is specified the BDIR BMPAGE BIAD and BEAD registers are set to 0 the BTYDE register is set to 0 to specify program memory 24 bit words and the BWCOUNT register is set to 32 This causes 32 words of on chip program memory to be loaded from byte memory These 32 words are used to set up the BDMA to load in the remaining program code The BCR bit is also set to 1 which causes pro gram execution to be held off until all 32 words are loaded into on chip program memory Execution then begins at address 0 The ADSP 2100 Family development software Revision 5 02 and later fully supports the BDMA booting feature and can generate byte memory space compatible boot code The IDLE instruction can also be used to allow the processor to hold off execution while booting continues through the BDMA interface For BDMA accesses while in Host Mode the ad dresses to boot memory must be constructed externally to the ADSP 2189M The only memory address bit provided by the processor is AO IDMA Port Booting The ADSP 2189M can also boot programs through its Internal DMA port If Mode C 1 Mode B 0 and Mode A 1 the ADSP 2189M boots from the IDMA port IDMA feature can load as much on chip memory as desired Program execution is held off until on chip program mem
28. Note that the latched address IDMAA cannot be read back by the host Refer to the following figures for more information on IDMA and DMA memory maps IDMA OVERLAY 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 L jerororo o o ojo o ojo ojo o o jomoxsre7 EI o RESERVED SET TOO IDDMOVLAY ID PMOVLAY IDMA CONTROL U UNDEFINED AT RESET 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Lu v u u v uju u uj u v u u u v pwoxsreo SE ee i IDMAA ADDRESS IDMAD DESTINATION MEMORY TYPE PM 1 DM Figure 10 IDMA Control OVLAY Registers REV A DMA DATA MEMORY OVLAY ALWAYS ACCESSIBLE AT ADDRESS 0x2000 0x3FFF DMA PROGRAM MEMORY OVLAY ALWAYS ACCESSIBLE 0x0000 AT ADDRESS Ox1FFF 0x0000 0x 1FFF ACCESSIBLE WHEN DMOVLAY 0 0x0000 0x2000 0x1FFF ACCESSIBLE WHEN PMOVLAY 0 0x0000 Ox1FFF 0x0000 Ox 1FFF 0x0000 Ox1FFF 0x2000 Ox3FFF ACCESSIBLE WHEN DMOVLAY 4 ACCESSIBLE WHEN 0x2000 Ox3FFF DMOVLAY 5 ACCESSIBLE WHEN DMOVLAY 6 ACCESSIBLE WHEN DMOVLAY 7 ACCESSIBLE WHEN PMOVLAY 4 ACCESSIBLE WHEN PMOVLAY 5 NOTE IDMA AND BDMA HAVEN SEPARATE DMA CONTROL REGISTERS Figure 11 Direct Memory Access PM and DM Memory Maps Bootstrap Loading Booting The ADSP 2189M has two mechanisms to allow automatic loading of the internal program memory after reset The method for booting is controlled by the Mode A B and C configuration bits When the
29. OWER PipLen mW Se Vpp 2 35V IDLE 128 50 14 25mW 55 60 65 i tck MHz VALID FOR ALL TEMPERATURE GRADES 1POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS TYPICAL POWER DISSIPATION AT 2 5V Vppint AND 25 C EXCEPT WHERE SPECIFIED 31pp MEASUREMENT TAKEN WITH ALL INSTRUCTIONS EXECUTING FROM INTERNAL MEMORY 50 OF THE INSTRUCTIONS ARE MULTIFUNCTION TYPES 1 4 5 12 13 14 30 ARE TYPE 2 AND TYPE 6 AND 20 ARE IDLE INSTRUCTIONS IDLE REFERS TO ADSP 2189M STATE OF OPERATION DURING EXECUTION OF IDLE INSTRUCTION DEASSERTED PINS ARE DRIVEN TO EITHER Vpp OR GND REV A Figure 15 Power vs Frequency 70 15 7mW 75 80 ADSP 2189M CAPACITIVE LOADING Figure 16 and Figure 17 show the capacitive loading character istics of the ADSP 2189M RISE TIME 0 4V 2 4V ns 30 T 85 C Vpp OV TO 2 0V 25 20 15 10 5 0 0 50 100 150 200 250 300 C pF Figure 16 Typical Output Rise Time vs Load Capacitance C at Maximum Ambient Operating Temperature VALID OUTPUT DELAY OR HOLD ns NOMINAL 18 16 14 12 10 8 6 4 2 0 50 100 150 200 250 CL pF Figure 17 Typical Output Valid Delay or Hold vs Load Capacitance C at Maximum Ambient Operating Temperature 17 CURRENT pA 900 800 I TEMP 85 C 772pA 600 500 TEMP 70 C 4754A 40
30. S IOMS BMS CLKOUT A0 A13 DMS PMS BMS IOMS cms RD D WR Figure 25 Memory Read 22 REV A ADSP 2189M Parameter Min Max Unit Memory Write Switching Characteristics tpw Data Setup before WR High O 5tck 4 w ns tpu Data Hold after WR High 0 25tcg 1 ns twp WR Pulsewidth 0 5tcx 3 w ns twpE WR Low to Data Enabled 0 ns tasw A0 A13 xMS Setup before WR Low 0 25tck 3 ns tppR Data Disable before WR or RD Low 0 25tck 3 ns cwn CLKOUT High to WR Low 0 25tcx 2 0 25tck 4 ns taw A0 A13 xMS Setup before WR Deasserted 0 75tck 5 w ns WRA A0 A13 xMS Hold after WR Deasserted 0 25tck 1 ns twwR WR High to RD or WR Low Q 5tck 3 ns w wait states X tcp xMS PMS DMS CMS IOMS BMS REV A Figure 26 Memory Write 23 ADSP 2189M Parameter Min Max Unit Serial Ports Timing Requirements tscx SCLK Period 26 67 ns tscs DR TFS RFS Setup before SCLK Low 4 ns tscH DR TFS RFS Hold after SCLK Low 7 ns tscp SCLKIN Width 12 ns Switching Characteristics tec CLKOUT High to SCLKOUT 0 25tcx 0 25tck 6 ns tscDE SCLK High to DT Enable 0 ns tscpv SCLK High to DT Valid 12 ns try TFS RFSoyr Hold after SCLK High 0 ns tgp TFS RFSour Delay from SCLK High 12 ns tscpH DT Hold after SCLK High 0 ns trpE TES Alt to DT Enable 0 ns trpv TES Alt to DT Valid 12 ns tscpp SCLK High to DT Disable 12 ns trpv RFS Multichannel Frame Delay Zero to DT
31. VLAY 7 Ox1FFF ACCESSIBLE WHEN DMOVLAY 1 ACCESSIBLE WHEN DMOVLAY 2 0x0000 Ox1FFF EXTERNAL MEMORY Figure 5 Data Memory Map REV A ADSP 2189M Data Memory Host Mode allows access to all internal memory External overlay access is limited by a single external address line A0 Table IV DMOVLAY Bits PMOVLAY Memory A13 A12 0 0 4 5 6 7 Internal Not Applicable Not Applicable 1 External 0 13 LSBs of Address Overlay 1 Between 0x2000 and 0x3FFF 2 External 1 13 LSBs of Address Overlay 2 Between 0x2000 and 0x3FFF Memory Mapped Registers New to the ADSP 2189M The ADSP 2189M has three memory mapped registers that differ from other ADSP 21xx Family DSPs The slight modifi cations to these registers Wait State Control Programmable Flag and Composite Select Control and System Control pro vide the ADSP 2189M s wait state and BMS control features WAIT STATE CONTROL 15 14 1312 1110 9 8 7 6 5 4 3 2 REN ENEN EO EN ED EDEN ERERENEOEN ERED DM 0x3FFE SY a a aa I DWAIT IOWAIT3 IOWAIT2 IOWAIT1 IOWAITO WAIT STATE MODE SELECT ADSP 2189M 0 NORMAL MODE DWAIT IOWAITO 3 N WAIT STATES RANGING FROM 0 TO 7 1 2N 1 MODE DWAIT IOWAITO 3 N WAIT STATES RANGING FROM 0 TO 15 Figure 6 Wait State Control Register ADSP 2189M PROGRAMMABLE FLAG amp COMPOSITE SELECT CONTROL 15 14 13 12 11 10 9 8 7 6 5 4 3 2 PEN EN EN ENED EN ED En ED EE DM 0x3FE6 TS Ar a
32. Valid 12 ns CLKOUT SCLK DR TFSin RFSin RFSout TFSout H tscpv gt DT TFSour ALTERNATE FRAME MODE RFSour MULTICHANNEL MODE FRAME DELAY 0 t MFD 0 TDE 4 m trov gt TFSiN ALTERNATE X FRAME MODE H trov gt RFSin MULTICHANNEL j MODE FRAME DELAY 0 MFD 0 Figure 27 Serial Ports 24 REV A ADSP 2189M Parameter Min Max Unit IDMA Address Latch Timing Requirements trate Duration of Address Latch 10 ns trasu IAD 15 0 Address Setup before Address Latch End 5 ns tran IAD 15 0 Address Hold after Address Latch End 3 ns trea IACK Low before Start of Address Latch 0 ns tras Start of Write or Read after Address Latch End 3 ns traLD Address Latch Start after Address Latch End 2 ns NOTES IStart of Address Latch IS Low and IAL High End of Address Latch IS High or IAL Low 3Start of Write or Read IS Low and IWR Low or IRD Low liasu gt tiasu lian lian e lacs RD OR WR Figure 28 IDMA Address Latch REV A 25 ADSP 2189M Parameter Min Max Unit IDMA Write Short Write Cycle Timing Requirements trew IACK Low before Start of Write ns trwp Duration of Write 10 ns tipsu IAD15 0 Data Setup before End of Write ns tmH IAD15 0 Data Hold after End of Write 2 ns Switching Characteristics thew Start of Write to IACK High 10 ns NOTES Start of Write IS Low and IWR Low End of Write IS Hig
33. a permit ting the ADSP 2189M to fetch two operands in a single cycle one from program memory and one from data memory The ADSP 2189M can fetch an operand from program memory and the next instruction in the same cycle In lieu of the address and data bus for external memory connec tion the ADSP 2189M may be configured for 16 bit Internal DMaA port IDMA port connection to external systems The IDMA port is made up of 16 data address pins and five control pins The IDMA port provides transparent direct access to the DSPs on chip program and data RAM An interface to low cost byte wide memory is provided by the Byte DMA port BDMA port The BDMA port is bidirectional and can directly address up to four megabytes of external RAM or ROM for off chip storage of program overlays or data tables The byte memory and I O memory space interface supports slow memories and I O memory mapped peripherals with pro grammable wait state generation External devices can gain control of external buses with bus request grant signals BR BGH and BG One execution mode Go Mode allows the ADSP 2189M to continue running from on chip memory Normal execution mode requires the processor to halt while buses are granted The ADSP 2189M can respond to eleven interrupts There can be up to six external interrupts one edge sensitive two level sensitive and three configurable and seven internal interrupts generated by the timer the serial ports SPORTs
34. ads SGuaranteed but not tested Three statable pins A0 A12 D0 D23 PMS DMS BMS IOMS CMS RD WR DT0 DT1 SCLK0 SCLK1 TFS0 TFS1 RFS0 RFS1 PFO PF7 80 V on BR Idle refers to ADSP 2189M state of operation during execution of IDLE instruction Deasserted pins are driven to either V pp or GND 10T 5 measurement taken with all instructions executing from internal memory 50 of the instructions are multifunction types 1 4 5 12 13 14 30 are type 2 and type 6 and 20 are idle instructions lV 0 V and 3 V For typical figures for supply currents refer to Power Dissipation section See Chapter 9 of the ADSP 2100 Family User s Manual Third Edition for details 13 Applies to LQFP package type 14 Output pin capacitance is the capacitive load for any three stated output pin BV om 2 5 V T 25 C Specifications subject to change without notice 14 REV A ADSP 2189M ABSOLUTE MAXIMUM RATINGS Value Parameter Min Max Internal Supply Voltage Vppmr 0 3V 3 0V External Supply Voltage Vppexr 0 3V 46V Input Voltage 0 5V 46V Output Voltage Swing 0 5V Vppexr 0 5 V Operating Temperature Range Ambient 40 C 85 C Storage Temperature Range 65 C 150 C Lead Temperature 5 sec LOFP 280 C NOTES I Stresses above those listed under Absolute Maximum Ratings may cause perma nent damage to the device These are stress ratings only functional operation of the devic
35. ch memory access IDMA Port access occurs in two phases The first is the IDMA Address Latch cycle When the acknowledge is asserted a 14 bit address and 1 bit destination type can be driven onto the bus by an external device The address specifies an on chip memory location the destination type specifies whether it is a DM or PM access The falling edge of the IDMA address latch signal IAL or the missing edge of the IDMA select signal IS latches this value into the IDMAA register Once the address is stored data can then be either read from or written to the ADSP 2189M s on chip memory Asserting the select line IS and the appropriate read or write line IRD and IWR respectively signals the ADSP 2189M that a particular transaction is required In either case there is a one processor cycle delay for synchronization The memory access consumes one additional processor cycle Once an access has occurred the latched address is automati cally incremented and another access can occur Through the IDMAA register the DSP can also specify the starting address and data format for DMA operation Asserting the IDMA port select IS and address latch enable IAL di rects the ADSP 2189M to write the address onto the IADO 14 bus into the IDMA Control Register If Bit 15 is set to 0 IDMA latches the address If Bit 15 is set to 1 IDMA latches into the OVLAY register This register shown below is memory mapped at address DM 0x3FE0
36. during program execution Flag and interrupt functionality is retained concurrently on multiplexed pins In cases where pin ADSP 2189M functionality is reconfigurable the default state is shown in plain text alternate functionality is shown in italics Common Mode Pins Pin of Name s Pins O Function RESET 1 I Processor Reset Input BR 1 I Bus Request Input BG 1 O Bus Grant Output BGH 1 O Bus Grant Hung Output DMS 1 O Data Memory Select Output PMS 1 O Program Memory Select Output TOMS 1 O Memory Select Output BMS 1 O Byte Memory Select Output CMS 1 O Combined Memory Select Output RD 1 O Memory Read Enable Output WR 1 O Memory Write Enable Output IRQ2 1 I Edge or Level Sensitive Interrupt Requests PF7 T O Programmable I O Pin IRQLI 1 I Level Sensitive Interrupt Requests PF6 I O Programmable I O Pin IRQLO 1 I Level Sensitive Interrupt Requests PF5 I O Programmable I O Pin IROE 1 I Edge Sensitive Interrupt Requests PF4 T O Programmable I O Pin Mode D 1 I Mode Select Input Checked Only During RESET PF3 I O Programmable I O Pin During Normal Operation Mode C 1 I Mode Select Input Checked Only During RESET PF2 T O Programmable I O Pin During Normal Operation Mode B 1 I Mode Select Input Checked Only During RESET PFI T O Programmable I O Pin During Normal Operation Mode A 1 I Mode Select Input Checked Only During RESET PFO T O Programmable
37. e at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability Applies to Bidirectional pins D0 D23 RFS0 RFS1 SCLK0 SCLK1 TFSO0 TFS1 A1 A13 PF0 PF7 and Input only pins CLKIN RESET BR DRO DRI PWD 3 Applies to Output pins BG PMS DMS BMS IOMS CMS RD WR PWDACK A0 DT0 DT1 CLKOUT FL2 0 BGH CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although the ADSP 2189M features proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality TIMING PARAMETERS GENERAL NOTES Use the exact timing information given Do not attempt to derive parameters from the addition or subtraction of others While addition or subtraction would yield meaningful results for an individual device the values given in this data sheet reflect statistical variations and worst cases Consequently you cannot meaningfully add up parameters to derive longer times TIMING NOTES Switching characteristics specify how the processor changes its signals You have no co
38. e lowest power rating and 200 CLKIN cycle recovery Support for crystal operation includes disabling the oscillator to save power the processor automatically waits approxi mately 4096 CLKIN cycles for the crystal oscillator to start or stabilize and letting the oscillator run to allow 200 CLKIN cycle start up Power down is initiated by either the power down pin PWD or the software power down force bit Interrupt support allows an unlimited number of instructions to be executed before optionally powering down The power down interrupt also can be used as a nonmaskable edge sensitive interrupt Context clear save control allows the processor to continue where it left off or start with a clean context when leaving the power down state The RESET pin also can be used to terminate power down Power down acknowledge pin indicates when the processor has entered power down Idle When the ADSP 2189M is in the Idle Mode the processor waits indefinitely in a low power state until an interrupt occurs When an unmasked interrupt occurs it is serviced execution then continues with the instruction following the IDLE instruc tion In Idle mode IDMA BDMA and autobuffer cycle steals still occur Slow Idle The IDLE instruction is enhanced on the ADSP 2189M to let the processor s internal clock signal be slowed further reducing power consumption The reduced clock frequency a program mable fraction of the normal clock rate
39. ects the computational units so that the output of any unit may be the input of any unit on the next cycle A powerful program sequencer and two dedicated data address generators ensure efficient delivery of operands to these compu tational units The sequencer supports conditional jumps sub routine calls and returns in a single cycle With internal loop counters and loop stacks the ADSP 2189M executes looped code with zero overhead no explicit jump instructions are re quired to maintain loops Two data address generators DAGs provide addresses for simultaneous dual operand fetches from data memory and program memory Each DAG maintains and updates four address pointers Whenever the pointer is used to access data indirect addressing it is post modified by the value of one of four possible modify registers A length value may be associated with each pointer to implement automatic modulo addressing for circular buffers Efficient data transfer is achieved with the use of five internal buses Program Memory Address PMA Bus Program Memory Data PMD Bus Data Memory Address DMA Bus Data Memory Data DMD Bus Result R Bus The two address buses PMA and DMA share a single external address bus allowing memory to be expanded off chip and the two data buses PMD and DMD share a single external data bus Byte memory space and I O memory space also share the external buses Program memory can store both instructions and dat
40. ed by the EZ ICE board EZ ICE emulation introduces an 8 ns propagation delay between your target circuitry and the DSP on the RESET signal EZ ICE emulation introduces an 8 ns propagation delay between your target circuitry and the DSP on the BR signal EZ ICE emulation ignores RESET and BR when single stepping EZ ICE emulation ignores RESET and BR when in Emula tor Space DSP halted EZ ICE emulation ignores the state of target BR in certain modes As a result the target system may take control of the DSP s external memory bus only if bus grant BG is as serted by the EZ ICE board s DSP 13 ADSP 2183M SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS K Grade Parameter Min Max Min Max Unit VppINT 2 37 2 63 2 25 2 75 V VDDEXT 2 37 3 6 2 25 3 6 V Vrut Vit 0 3 Vint 3 6 0 03 3 6 V Tamp 0 70 40 85 C NOTES The ADSP 2189M is 3 3 V tolerant always accepts up to 3 6 Volt max V gy but voltage compliance on outputs Voy depends on the input Vppgxr because Voy max Vppexr max This applies to Bidirectional pins D0 D23 RFSO RFS1 SCLK0 SCLK1 TFSO TFS1 A1 A13 PF0 PF7 and Input Only pins CLKIN RESET BR DRO DR1 PWD ELECTRICAL CHARACTERISTICS K B Grades Parameter Test Conditions Min Typ Max Unit Vm Hi Level Input Voltage Vppint max 1 5 V Vin Hi Level CLKIN Voltage Vppint max 2 0 V Vir Lo Level Input Voltage Vppinr min 0
41. ers to the empty stack condition masks all interrupts and clears the MSTAT register When RESET is released if there is no pending bus request and the chip is configured for booting the boot loading sequence is performed The first instruction is fetched from on chip program memory location 0x0000 once boot loading completes Power Supplies The ADSP 2189M has separate power supply connections for the internal Vppinr and external Vppgxr power supplies The internal supply must meet the 2 5 V requirement The external supply can be connected to either a 2 5 V or 3 3 V supply All external supply pins must be connected to the same supply All input and I O pins can tolerate input voltages up to 3 6 V regardless of the external supply voltage This fea ture provides maximum flexibility in mixing 2 5 V and 3 3 V components MODES OF OPERATION Setting Memory Mode Memory Mode selection for the ADSP 2189M is made during chip reset through the use of the Mode C pin This pin is multi plexed with the DSP s PF2 pin so care must be taken in how the mode selection is made The two methods for selecting the value of Mode C are active and passive REV A Passive Configuration involves the use a pull up or pull down resistor connected to the Mode C pin To minimize power consumption or if the PF2 pin is to be used as an output in the DSP application a weak pull up or pull down on the order of 10 kQ can be used This value should be s
42. esembles a simple equation Every instruction assembles into a single 24 bit word that can execute in a single instruction cycle The syntax is a superset ADSP 2100 Family assembly language and is completely source and object code compatible with other family members Programs may need to be relocated to utilize on chip memory and conform to the ADSP 2189M s interrupt vector and reset vector map Sixteen condition codes are available For conditional jump call return or arithmetic instructions the condition can be checked and the operation executed in the same instruction cycle Multifunction instructions allow parallel execution of an arithmetic instruction with up to two fetches or one write to processor memory space during a single instruction cycle DESIGNING AN EZ ICE COMPATIBLE SYSTEM The ADSP 2189M has on chip emulation support and an ICE Port a special set of pins that interface to the EZ ICE These features allow in circuit emulation without replacing the target system processor by using only a 14 pin connection from the target system to the EZ ICE Target systems must have a 14 pin connector to accept the EZ ICE s in circuit probe a 14 pin plug Issuing the chip reset command during emulation causes the DSP to perform a full chip reset including a reset of its memory mode Therefore it is vital that the mode pins are set correctly PRIOR to issuing a chip reset command from the emulator user interface If y
43. h or IWR High If Write Pulse ends before IACK Low use specifications tipsu tipy 4If Write Pulse ends after IACK Low use specifications tyxsy trey TACK IS IWR o vVNV NNNM l oaa Y YY YY VY YY worse XX KXXXQOK TOK XK KX KKK XX Figure 29 IDMA Write Short Write Cycle 26 REV A ADSP 2189M Parameter Min Max Unit IDMA Write Long Write Cycle Timing Requirements threw IACK Low before Start of Write 0 ns tiksu IAD15 0 Data Setup before End of Write O 5tck 5 ns tre IAD15 0 Data Hold after End of Write 4 0 ns Switching Characteristics kLw Start of Write to IACK Low l 5tck ns threw Start of Write to IACK High 10 ns NOTES Start of Write IS Low and IWR Low If Write Pulse ends before IACK Low use specifications tipsu tgp If Write Pulse ends after IACK Low use specifications tyxgy tH This is the earliest time for IACK Low from Start of Write For IDMA Write cycle relationships please refer to the ADSP 2100 Family User s Manual Third Edition IAD15 0 Figure 30 IDMA Write Long Write Cycle REV A 21 ADSP 2189M Parameter Min Max Unit IDMA Read Long Read Cycle Timing Requirements tre TACK Low before Start of Read 0 ns URK End of Read after IACK Low 2 ns Switching Characteristics ikHR IACK High after Start of Read 10 ns trkps IADI15 0 Data Setup before IACK Low 0 5tck 2 ns trkpH IAD15 0 Data Hold after End
44. ignal The CLKIN input cannot be halted changed during operation or operated below the specified frequency during normal opera tion The only exception is while the processor is in the power down state For additional information refer to Chapter 9 ADSP 2100 Family User s Manual Third Edition for detailed information on this power down feature If an external clock is used it should be a TTL compatible signal running at half the instruction rate The signal is con nected to the processor s CLKIN input When an external clock is used the XTAL input must be left unconnected The ADSP 2189M uses an input clock with a frequency equal to half the instruction rate a 37 50 MHz input clock yields a 13 3 ns processor cycle which is equivalent to 75 MHz Nor mally instructions are executed in a single processor cycle All device timing is relative to the internal instruction clock rate which is indicated by the CLKOUT signal when enabled Because the ADSP 2189M includes an on chip oscillator cir cuit an external crystal may be used The crystal should be connected across the CLKIN and XTAL pins with two capaci tors connected as shown in Figure 3 Capacitor values are de pendent on crystal type and should be specified by the crystal manufacturer A parallel resonant fundamental frequency microprocessor grade crystal should be used A clock output CLKOUT signal is generated by the processor at the processor s cycle rate Thi
45. ion is held off until all 32 words have been loaded Chip is configured in Full Memory Mode No automatic boot operations occur Program execution starts at external memory location 0 Chip is configured in Full Memory Mode BDMA can still be used but the processor does not automatically use or wait for these operations BDMA feature is used to load the first 32 program memory words from the byte memory space Program execution is held off until all 32 words have been loaded Chip is configured in Host Mode IACK has active pull down REQUIRES ADDITIONAL HARDWARE IDMA feature is used to load any internal memory as desired Program ex ecution is held off until internal program memory location 0 is written to Chip is configured in Host Mode IACK has active pull down BDMA feature is used to load the first 32 program memory words from the byte memory space Program execution is held off until all 32 words have been loaded Chip is configured in Host Mode IACK requires external pull down REQUIRES ADDITIONAL HARDWARE IDMA feature is used to load any internal memory as desired Program ex ecution is held off until internal program memory location 0 is written to Chip is configured in Host Mode IACK requires external pull down NOTE 1Considered as standard operating settings Using these configurations allows for easier design and better memory management The master reset sets all internal stack point
46. mory PM Data Memory DM Byte Memory BM I O Memory IOM and Composite Memory CM external interfaces to comply with worst case device timing requirements and switching characteristics as specified in this data sheet The performance of the EZ ICE may approach published worst case specification for some memory access timing requirements and switching characteristics Note If your target does not meet the worst case chip specifica tion for memory access parameters you may not be able to emulate your circuitry at the desired CLKIN frequency De pending on the severity of the specification violation you may have trouble manufacturing your system as DSP components statistically vary in switching characteristic and timing require ments within published limits Restriction All memory strobe signals on the ADSP 2189M RD WR PMS DMS BMS CMS and IOMS used in your target system must have 10 kQ pull up resistors connected when the EZ ICE is being used The pull up resistors are necessary because there are no internal pull ups to guarantee their state during prolonged three state conditions resulting from typical EZ ICE debugging sessions These resistors may be removed at your option when the EZ ICE is not being used Target System Interface Signals When the EZ ICE board is installed the performance on some system signals change Design your system to be compatible with the following system interface signal changes introduc
47. nal serial clock or generate their own serial clock internally SPORTS have independent framing for the receive and trans mit sections Sections run in a frameless mode or with frame synchronization signals internally or externally generated Frame sync signals are active high or inverted with either of two pulsewidths and timings SPORTS support serial data word lengths from 3 to 16 bits and provide optional A law and u law companding according to CCITT recommendation G 711 SPORT receive and transmit sections can generate unique interrupts on completing a data word transfer SPORTS can receive and transmit an entire circular buffer of data with only one overhead cycle per data word An interrupt is generated after a data buffer transfer SPORTO has a multichannel interface to selectively receive and transmit a 24 or 32 word time division multiplexed serial bitstream SPORT can be configured to have two external interrupts IRQO and IRQI and the Flag In and Flag Out signals The internally generated serial clock may still be used in this con figuration PIN DESCRIPTIONS The ADSP 2189M will be available in a 100 lead LQFP pack age In order to maintain maximum functionality and reduce package size and pin count some serial port programmable flag interrupt and external bus pins have dual multiplexed functionality The external bus pins are configured during RESET only while serial port pins are software configurable
48. nsfers have finished and a BDMA interrupt is gener ated The BMPAGE and BEAD registers must not be accessed by the DSP during BDMA operations The source or destination of a BDMA transfer will always be on chip program or data memory When the BWCOUNT register is written with a nonzero value the BDMA circuit starts executing byte memory accesses with wait states set by BMWAIT These accesses continue until the count reaches zero When enough accesses have occurred to create a destination word it is transferred to or from on chip memory The transfer takes one DSP cycle DSP accesses to external memory have priority over BDMA byte memory accesses The BDMA Context Reset bit BCR controls whether the processor is held off while the BDMA accesses are occurring Setting the BCR bit to 0 allows the processor to continue opera tions Setting the BCR bit to 1 causes the processor to stop execution while the BDMA accesses are occurring to clear the context of the processor and start execution at address 0 when the BDMA accesses have completed The BDMA overlay bits specify the OVLAY memory blocks to be accessed for internal memory The BMWAIT field which has four bits on ADSP 2189M allows selection of up to 15 wait states for BDMA transfers Internal Memory DMA Port IDMA Port Host Memory Mode The IDMA Port provides an efficient means of communication between a host system and the ADSP 2189M The port is used to access the on chip
49. ntrol over this timing circuitry external to the processor must be designed for compatibility with these signal characteristics Switching characteristics tell you what the processor will do in a given circumstance You can also use switching characteristics to ensure that any timing requirement of a device connected to the processor such as memory is satisfied Timing requirements apply to signals that are controlled by circuitry external to the processor such as the data input for a read operation Timing requirements guarantee that the proces sor operates correctly with other devices REV A WARNING uma ESD SENSITIVE DEVICE MEMORY TIMING SPECIFICATIONS The table below shows common memory device specifications and the corresponding ADSP 2189M timing parameters for your convenience Memory Timing Device Parameter Specification Parameter Definition Address Setup to tasw A0 A13 xMS Setup before Write Start WR Low Address Setup to taw A0 A13 xMS Setup before Write End WR Deasserted Address Hold Time twra A0 A13 xMS Hold before WR Low Data Setup Time tpw Data Setup before WR High Data Hold Time toy Data Hold after WR High OE to Data Valid trpp RD Low to Data Valid Address Access Time ta A0 A13 xMS to Data Valid NOTE 1XMS PMS DMS BMS CMS or IOMS 15 ADSP 2189M FREQUENCY DEPENDENCY FOR TIMING SPECIFICATIONS tcx is defined as 0 5tcxy The ADSP 2189M uses an input clock
50. of development tools supports program development POWER DOWN CONTROL y FULL MEMORY MEMORY PROGRAMMABLE ZOPE DATA ADDRESS DATA PROGRAMMABLE 4 GENERATORS PROGRAM FROGRAM EMORY Eo EXTERNAL SEQUENCER 48K x ADDRESS lt gt 24BIT teBm BUS EXTERNAL PROGRAM MEMORY ADDRESS DATA wi DATA MEMORY ADDRESS PROGRAM MEMORY DATA 8 oO 35 a ce n L Ol R 4 EXTERNAL DATA p BUS INTERNAL DMA PORT L HOST MODE DATA MEMORY DATA ARITHMETIC UNITS ADSP 2100 BASE ARCHITECTURE SERIAL PORTS Figure 1 Functional Block Diagram Figure 1 is an overall block diagram of the ADSP 2189M The processor contains three independent computational units the ALU the multiplier accumulator MAC and the shifter The computational units process 16 bit data directly and have provi sions to support multiprecision computations The ALU per forms a standard set of arithmetic and logic operations division primitives are also supported The MAC performs single cycle multiply multiply add and multiply subtract operations with 40 bits of accumulation The shifter performs logical and arith metic shifts normalization denormalization and derive expo nent operations The shifter can be used to efficiently implement numeric format control including multiword and block floating point representations REV A ADSP 2189M The internal result R bus conn
51. onal external program and data overlay memories mode selectable Programmable Wait State generation allows the processor connects easily to slow peripheral devices The ADSP 2189M also provides four external interrupts and two serial ports or six external interrupts and one serial port Host Memory Mode allows access to the full external data bus but limits addressing to a single address bit A0 Additional system peripherals can be added in this mode through the use of exter nal hardware to generate and latch address signals FULL MEMORY MODE 1 2x CLOCK OR CRYSTAL YT MEMORY IRQL1 PF6 MODE D PF3 VO SPACE DATA PERIPHERALS CS 2048 LOCATIONS ADDR OVERLAY MEMORY TWO 8K PM SEGMENTS RFS1 OR IRGO SERIAL 4 gt TFS1 ORROT DEVICE prionro pni oR FI DATA TWO 8K SPORTO DM SEGMENTS SCLKO 4 e RESO SERIAL SOS teso DEVICE __ aX gt l pro ADSP 2189M CLKIN XTAL FLO 2 TRQ2 PF7 IRQE PFA IRQLO PF5 IRQL1 PF6 MODE D PF3 MODE C PF2 WR MODE B PF1 RD MODE A PFO SPORT1 1 2x CLOCK OR CRYSTAL PEN SERIAL TFS1 oR IRAT DEVICE 4 1 oR FO bR1 OR Fi SPORTO SCLKO Le SERIAL T PFSO DEVICE 7 77 SYSTEM INTERFACE OR p CONTROLLER Figure 2 ADSP 2189M Basic System Interface Clock Signals The ADSP 2189M can be clocked by either a crystal or a TTL compatible clock s
52. ory space For example an EPROM could be attached to the BMS select and an SRAM could be connected to CMS Because BMS is enabled at reset the EPROM would be used for boot ing After booting software could disable BMS and set the CMS signal to respond to BMS enabling the SRAM ADSP 2189M Byte Memory The byte memory space is a bidirectional 8 bit wide external memory space used to store programs and data Byte memory is accessed using the BDMA feature The byte memory space consists of 256 pages each of which is 16K x 8 The byte memory space on the ADSP 2189M supports read and write operations as well as four different data formats The byte memory uses data bits 15 8 for data The byte memory uses data bits 23 16 and address bits 13 0 to create a 22 bit address This allows up to a 4 meg x 8 32 megabit ROM or RAM to be used without glue logic All byte memory accesses are timed by the BMWAIT register and the wait state mode bit Byte Memory DMA BDMA Full Memory Mode The Byte memory DMA controller allows loading and storing of program instructions and data using the byte memory space The BDMA circuit is able to access the byte memory space while the processor is operating normally and steals only one DSP cycle per 8 16 or 24 bit word transferred BDMA CONTROL 15 14 1312 1110 9 8 7 6 5 4 3 2 Te Te e Te To To eTe TT Te e DM 0x3FE3 v0 BR BMPAGE BDMA BTYPE OVERLAY BITS BDIR 0
53. ory location 0 is written to 11 ADSP 2189M Bus Request and Bus Grant The ADSP 2189M can relinquish control of the data and ad dress buses to an external device When the external device requires access to memory it asserts the bus request BR sig nal If the ADSP 2189M is not performing an external memory access it responds to the active BR input in the following pro cessor cycle by Three stating the data and address buses and the PMS Asserting the bus grant BG signal and Halting program execution If Go Mode is enabled the ADSP 2189M will not halt program execution until it encounters an instruction that requires an external memory access If the ADSP 2189M is performing an external memory access when the external device asserts the BR signal it will not three state the memory interfaces or assert the BG signal until the processor cycle after the access completes The instruction does not need to be completed when the bus is granted If a single instruction requires two external memory accesses the bus will be granted between the two accesses When the BR signal is released the processor releases the BG signal reenables the output drivers and continues program execution from the point at which it stopped The bus request feature operates at all times including when the processor is booting and when RESET is active The BGH pin is asserted when the ADSP 2189M requires the external bus for a memory or
54. ou are using a passive method of maintaining mode information as discussed in Setting Memory Modes then it does not matter that the mode information is latched by an emulator reset However if using the RESET pin as a method of setting the value of the mode pins the effects of an emulator reset must be taken into consideration One method of ensuring that the values located on the mode pins are those desired is to construct a circuit like the one shown in Figure 12 This circuit forces the value located on the Mode A pin to logic high regardless if it latched via the RESET or ERESET pin ADSP 2189M O MODE A PFO PROGRAMMABLE I O Figure 12 Mode A Pin EZ ICE Circuit See the ADSP 2100 Family EZ Tools data sheet for complete information on ICE products REV A ADSP 2189M The ICE Port interface consists of the following ADSP 2189M pins EBR EINT EE EBG ECLK ERESET ELIN EMS and ELOUT These ADSP 2189M pins must be connected only to the EZ ICE connector in the target system These pins have no function except during emulation and do not require pull up or pull down resistors The traces for these signals between the ADSP 2189M and the connector must be kept as short as possible no longer than three inches The following pins are also used by the EZ ICE BR BG RESET and GND The EZ ICE uses the EE emulator enable signal to take con trol of the ADSP 2189M in the target system This causes the
55. ower vs Frequency graph Figure 15 C x Vppexr X f is calculated for each output of x x x Parameters Pins C Vppext f PD Address DMS 8 10 pF 3 37V_ 33 3 MHz 29 0 mW Data Output WRI 9 10 pF 3 37V_ 16 67 MHz 16 3 mW RD 1 10 pF 3 37V_ 16 67 MHz 1 8 mW CLKOUT 1 10pF 3 2V 33 3 MHz 3 6 mW 50 7 mW Total power dissipation for this example is Pnr 50 7 mW 16 Output Drive Currents Figure 14 shows typical I V characteristics for the output drivers on the ADSP 2189M The curves represent the current drive capability of the output drivers as a function of output voltage 80 60 VoH Vppexr 3 6V 40 C 40 Vppext 3 3V 25 C 20 Vppext 2 5V 85 C 20 Vppexr 3 6V 40 C SOURCE CURRENT mA o Vppext 2 5V 85 C y Vppexr 3 3V 25 C y 0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 SOURCE VOLTAGE V 40 VoL Figure 14 Typical Output Driver Characteristics REV A 115 110 2189L POWER INTERNAL 2 3 105 100 95 90 85 80 75 POWER Pint mW 70 65 60 55 50 55 60 65 i tck MHz 70 POWER IDLE 2 4 75 80 POWER Pipi mW 60 POWER IDLE n MODES 65 i tck MHz 70 75 80 IDLE Vpp 2 5V 16 4mW IDLE 16 P
56. pecified high or low trip point as shown in the Output Enable Disable diagram If multiple pins such as the data bus are enabled the measurement value is that of the first pin to start driving REFERENCE SIGNAL Vou Vou MEASURED MEASURED Von MEASURED 0 5V 2 0V OUTPUT Vor MEASURED 0 5V Vou toecay VoL MEASURED MEASURED OUTPUT STARTS DRIVING OUTPUT STOPS DRIVING HIGH IMPEDANCE STATE TEST CONDITIONS CAUSE THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1 5V Figure 20 Output Enable Disable loL TO OUTPUT 1 5V 50pF ur lon Figure 21 Equivalent Device Loading for AC Measure ments Including All Fixtures REV A ADSP 2189M TIMING PARAMETERS Parameter Min Max Unit Clock Signals and Reset Timing Requirements tckr CLKIN Period 26 6 80 ns tckIL CLKIN Width Low 13 ns tckiH CLKIN Width High 13 ns Switching Characteristics tckr CLKOUT Width Low 0 5tck 2 ns tcKH CLKOUT Width High 0 5tck 2 ns tcxou CLKIN High to CLKOUT High 0 13 ns Control Signals Timing Requirements trsp RESET Width Low 5tcx ns tus Mode Setup before RESET High 2 ns tMH Mode Hold after RESET High 5 ns NOTE Applies after power up sequence is complete Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN not including crystal oscillator start up time teki gt CLKIN CLKOUT PF 3 0 tms tun PF3 IS MODE D PF2 IS MO
57. s can be enabled and disabled by the CLKODIS bit in the SPORTO Autobuffer Control Register XTAL CLKOUT Figure 3 External Crystal Connections Reset The RESET signal initiates a master reset of the ADSP 2189M The RESET signal must be asserted during the power up se quence to assure proper initialization RESET during initial power up must be held long enough to allow the internal clock to stabilize If RESET is activated any time after power up the clock continues to run and does not require stabilization time The power up sequence is defined as the total time required for the crystal oscillator circuit to stabilize after a valid Vpp is ap plied to the processor and for the internal phase locked loop PLL to lock onto the specific crystal frequency A minimum of 2000 CLKIN cycles ensures that the PLL has locked but does not include the crystal oscillator start up time During this power up sequence the RESET signal should be held low On any subsequent resets the RESET signal must meet the mini mum pulsewidth specification tgsp The RESET input contains some hysteresis however if you use an RC circuit to generate your RESET signal the use of an external Schmidt trigger is recommended REV A ADSP 2189M Table II ADSP 2189M Modes of Operation MODED MODEC MODEB MODEA Booting Method X 0 0 0 BDMA feature is used to load the first 32 program memory words from the byte memory space Program execut
58. ss is limited by a single external address line A0 External program execution is not available in host mode due to a restricted data bus that is 16 bits wide only Table III PMOVLAY Bits PMOVLAY Memory A13 A12 0 0 4 5 Internal Not Applicable Not Applicable 1 External 0 13 LSBs of Address Overlay 1 Between 0x2000 and 0x3FFF 2 External 1 13 LSBs of Address Overlay 2 Between 0x2000 and 0x3FFF Data Memory Data Memory Full Memory Mode is a 16 bit wide space used for the storage of data variables and for memory mapped control registers The ADSP 2189M has 48K words on Data Memory RAM on chip Part of this space is used by 32 memory mapped registers Support also exists for up to two 8K external memory overlay spaces through the external data bus All inter nal accesses complete in one cycle Accesses to external memory are timed using the wait states specified by the DWAIT register and the wait state mode bit DATA MEMORY ADDRESS DATA MEMORY 32 MEMORY OX3FFF MAPPED MAE REGISTERS 0x3FE0 AT ADDRESS INTERNAL 0x3FDF 0x2000 0x3FFF 8160 oxo WORDS 0x2000 OX1FFF ACCESSIBLE WHEN _ 1FFF 8K INTERNAL DMOVLAY 0 0x0000 DMOVLAY 0x1FFF 0 A 7 0x0000 EXTERNAL 8K ACCESSIBLE WHEN L DMOVLAY 4 OxiFFF DMOVLAY 1 2 ox o000 0x0000 Ox1FFF ACCESSIBLE WHEN DMOVLAY 5 INTERNAL ACCESSIBLE WHEN 0x0000 MEMORY DMOVLAY 6 0x 1FFF ACCESSIBLE WHEN 0x0000 DMO
59. tor emulation can be supported in final board designs EZ ICE and SoundPort are registered trademarks of Analog Devices Inc 2 The EZ ICE performs a full range of functions including n target operation Up to 20 breakpoints Single step or full speed operation Registers and memory values can be examined and altered PC upload and download functions Instruction level emulation of program booting and execution Complete assembly and disassembly of instructions C source level debugging See Designing An EZ ICE Compatible Target System in the ADSP 2100 Family EZ Tools Manual ADSP 2181 sections as well as the Designing an EZ ICE compatible System section of this data sheet for the exact specifications of the EZ ICE target board connector Additional Information This data sheet provides a general overview of ADSP 2189M functionality For additional information on the architecture and instruction set of the processor refer to the ADSP 2100 Family User s Manual Third Edition For more information about the development tools refer to the ADSP 2100 Family Develop ment Tools Data Sheet ARCHITECTURE OVERVIEW The ADSP 2189M instruction set provides flexible data moves and multifunction one or two data moves with a computation instructions Every instruction can be executed in a single pro cessor cycle The ADSP 2189M assembly language uses an algebraic syntax for ease of coding and readability A compre hensive set
60. ufficient to pull the pin to the desired level and still allow the pin to operate as a programmable flag output without undue strain on the processor s output driver For minimum power consumption during power down reconfigure PF2 to be an input as the pull up or pull down will hold the pin in a known state and will not switch Active Configuration involves the use of a three statable ex ternal driver connected to the Mode C pin A driver s output enable should be connected to the DSP s RESET signal such that it only drives the PF2 pin when RESET is active low When RESET is deasserted the driver should three state thus allowing full use of the PF2 pin as either an input or output To minimize power consumption during power down configure the programmable flag as an output when connected to a three stated buffer This ensures that the pin will be held at a constant level and will not oscillate should the three state driver s level hover around the logic switching point IACK Configuration Mode D 0 and in host mode IACK is an active driven signal and cannot be wire OR ed ADSP 2189M PM MODE B 0 PM MODE B 1 ALWAYS ACCESSIBLE RESERVED AT ADDRESS 0x2000 00000 0x1 FFF OXaFFE 0x2000 ACCESSIBLE WHEN DESEE PMOVLAY 0 ACCESSIBLE WHEN PMOVLAY 0 e INTERNAL TPE MEMORY 0x2000 0x0000 INT
61. xMS RD WR Disable 0 25tcy 8 ns tspB xMS RD WR Disable to BG Low 0 ns tsE BG High to xMS RD WR Enable 0 ns tsEc xMS RD WR Enable to CLKOUT High 0 25tck 3 ns tspBH xMS RD WR Disable to BGH Low 0 ns TSEH BGH High to xMS RD WR Enable 0 ns NOTES xMS PMS DMS CMS IOMS BMS TBR is an asynchronous signal If BR meets the setup hold requirements it will be recognized during the current clock cycle otherwise the signal will be recognized on the following cycle Refer to the ADSP 2100 Family User s Manual Third Edition for BR BG cycle relationships BGH is asserted when the bus is granted and the processor or BDMA requires control of the bus to continue REV A teu CLKOUT v AME CU ZEE tas CLKOUT PMS DMS BMS RD WR tsp lt lt BG tsps gt tsec tse ke BGH tspBx tseH 4 Figure 24 Bus Request Bus Grant 21 ADSP 2189M Parameter Min Max Unit Memory Read Timing Requirements J trpp RD Low to Data Valid O 5tck 5 w ns taa A0 A13 xMS to Data Valid 0 75tck 6 w ns tgpH Data Hold from RD High 0 ns Switching Characteristics tgp RD Pulsewidth EN O 5otck 9 w ns tcRD CLKOUT High to RD Low 0 25tck 2 0 25tck 4 ns tASR A0 A13 xMS Setup before RD Low 0 25tcK 3 ns TRDA A0 A13 xMS Hold after RD Deasserted 0 25tcK 3 ns trwR RD High to RD or WR Low Q0 5tck 3 ns w wait states X tcp xMS PMS DMS CM

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