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MPC866/MPC859 Hardware Specifications

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1. 2 86 1234567891 BOTTOM VIEW 0 30 0 150 557X SEATING PLANE CN 0 21A 0 25 0 35 1224 A A BEG OD CO ON ON le 1 1 2 5 2 1 gt N SIDE VIEW Note Solder sphere composition for MPC866XZP MPC859PZP MPC859DSLZP and MPC859TZP 15 62 Sn 3696Pb 2 Ag Figure 79 Mechanical Dimensions and Bottom Surface Nomenclature of the PBGA Package MPC866 MPC859 Hardware Specifications Rev 2 92 Freescale Semiconductor Document Revision History 16 Document Revision History Table 40 lists significant changes betvveen revisions of this document Table 40 Document Revision History Revision Date Substantive Changes Number 0 5 2002 nitial revision 1 11 2002 Added the 5 V tolerant pins nevv package dimensions and other changes 1 1 4 2003 Added the Spec B1d and changed spec B1a Added the Note Solder sphere composition for MPC866XZP MPC859DSLZP and MPC859TZP is 62 Sn 36 Pb 296Ag to Figure 15 79 1 2 4 2003 Added the MPC859P 1 3 5 2003 Changed the SPI Master Timing Specs 162 and 164 1 4 7 8 2003 e Added TxClav and RxClav to PB15 and PC15 Changed B28a through B28d and B29b to sh
2. oa MPC866 MPC859 Hardware Specifications Rev 2 Freescale Semiconductor 11 Thermal Calculation and Measurement 7 Thermal Calculation and Measurement For the following discussions Pp VDDL x IDDL PI O where PI O is the power dissipation of the I O drivers The VDDSYN power dissipation is negligible 7 1 Estimation with Junction to Ambient Thermal Resistance An estimation of the chip junction temperature T in C can be obtained from the equation Ty TA Roya X Pp where TA ambient temperature C Roya package junction to ambient thermal resistance C W Pp power dissipation in package The junction to ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performance However the answer is only an estimate test cases have demonstrated that errors of a factor of two in the quantity Ty TA are possible 7 2 Estimation with Junction to Case Thermal Resistance Historically the thermal resistance has frequently been expressed as the sum of a junction to case thermal resistance and a case to ambient thermal resistance Resa Reyc Roca where Roya Junction to ambient thermal resistance C W Royc junction to case thermal resistance C W Reca case to ambient thermal resistance C W Rgjc is device related and cannot be influenced by the user The user adjusts the ther
3. Table 9 shows the timings for the MPC866 859 at 33 40 50 and 66 MHz bus operation The timing for the MPC866 859 bus shown in this table assumes a 50 pF load for maximum delays and a 0 pF load for minimum delays CLKOUT assumes a 100 pF load maximum delay Table 9 Bus Operation Timings 33 MHz 40 MHz 50 MHz 66 MHz Num Characteristic Unit Min Max Min Max Min Max Min Max B1 1 Bus Period CLKOUT See Table 7 ns Bia EXTCLK to CLKOUT phase skew 2 2 2 2 2 2 2 2 ns Bib CLKOUT frequency jitter peak to peak 1 1 1 1 ns Bic Frequency jitter on EXTCLK 0 50 0 50 0 50 0 50 MPC866 MPC859 Hardware Specifications Rev 2 Freescale Semiconductor Table 9 Bus Operation Timings continued Bus Signal Timing Num Characteristic 33 MHz 40 MHz 50 MHz 66 MHz Min Max Min Max Min Max Min Max Unit Bid CLKOUT phase jitter peak to peak for OSCLK 15 MHz 4 4 ns CLKOUT phase jitter peak to peak for OSCLK lt 15 MHz ns B2 CLKOUT pulse width low MIN 0 4 x B1 MAX 0 6 x B1 12 1 18 2 10 0 15 0 8 0 12 0 6 1 9 1 ns B3 CLKOUT pulse width high MIN 0 4 x B1 MAX 0 6 x B1 12 1 18 2 10 0 15 0 8 0 12 0 6 1 9 1 ns B4 CLKOUT rise time 4 00 4 00
4. Figure 17 External Bus Write Timing Controlled TRLX 0 CSNT 1 MPC866 MPC859 Hardware Specifications Rev 2 32 Freescale Semiconductor Bus Signal Timing oa 85 829 gt B28 B29h gt 28 A 0 31 CSx VVE 0 3 010 311 DP 0 3 Figure 18 External Bus Write Timing GPCM Controlled TRLX 1 CSNT 1 MPC866 MPC859 Hardware Specifications Rev 2 Freescale Semiconductor 33 Bus Signal Timing Figure 19 shows the timing for the external bus controlled by the UPM CLKOUT s CSx BS_A 0 3 BS 10 3 GPL_A 0 5 GPL Bi0 5 Figure 19 External Bus Timing UPM Controlled Signals MPC866 MPC859 Hardware Specifications Rev 2 34 Freescale Semiconductor Bus Signal Timing Figure 20 shovvs the timing for the asynchronous asserted UPVVATT signal controlled by the UPM CLKOUT UPWAIT BS Al0 3 BS 10 3 GPL 10 5 GPL 10 5 Figure 20 Asynchronous UPWAIT Asserted Detection in UPM Handled Cycles Timing Figure 21 shovvs the timing for the asynchronous negated UPVVATT signal controlled by the UPM CLKOUT UPWAIT 5 0 3 5 10 3 GPL 0 5 GPL Bi0 5 Figure 21 Asynchronous UPWAIT Negated Detection in UPM Handled Cycles Timing MPC866 MPC859 Hardware Specifications Rev 2 Freesc
5. 2 IP_B3 IWP2 VF2 IP_B4 LWPO VFO IP_B5 LWP1 VF1 IP_B6 DSDI ATO IP_B7 PTR AT3 RXD1 PA15 RXD2 PA13 L1TXDB PA11 L1RXDB PA10 L1TXDA PAQ L1RXDA PA8 TIN1 L1RCLKA BRGO1 CLK1 PA7 BRGCLK1 TOUT1 CLK2 PA6 TIN2 L1TCLKA BRGO2 CLK3 PA5 TOUT2 CLK4 PA4 TIN3 BRGO3 CLK5 PA3 BRGCLK2 L1RCLKB TOUT3 CLK6 PA2 TIN4 BRGO4 CLK7 PA1 L1TCLKB TOUT4 CLK8 PAO REJCT1 SPISEL PB31 SPICLK PB30 SPIMOSI PB29 BRGO4 SPIMISO PB28 BRGO1 lI2CSDA PB27 BRGO2 2CSCL PB26 SMTXD1 PB25 SMRXD1 PB24 SMSYN1 SDACK1 PB23 SMSYN2 SDACK2 PB22 SMTXD2 L1CLKOB PB21 SMRXD2 L1CLKOA PB20 L1ST1 RTS1 PB19 L1ST2 RTS2 PB18 L1ST3 L1RQB PB17 L1ST4 L1RQA PB16 BRGO3 PB15 RSTRT1 PB14 L1ST1 RTS1 DREQO PC15 L1ST2 RTS2 DREQ1 PC14 L1ST3 L1RQB PC13 L1ST4 L1RQA PC12 CTS1 PC11 TGATE1 CD1 PC10 CTS2 PC9 TGATE2 CD2 PC8 CTS3 SDACK2 L1TSYNCB PC7 CD3 L1RSYNCB PC6 CTS4 SDACK1 L1TSYNCA PC5 CD4 L1RSYNCA PC4 PD15 L1TSYNCA PD14 L1RSYNCA PD13 L1TSYNCB PD12 L1RSYNCB PD11 RXD3 PD10 TXD3 PD9 RXD4 PD8 TXD4 PD5 REJECT2 PD6 RTS4 PD7 RTS3 4 Mil ER MII_EN MII_MDIO MII_TXD 0 3 BDIP GPL_B 5 BR BG FRZ IRQ6 CS 0 5 5 6 1 CS 7 CE 2 _B WE0 BS_BO IORD WE1 BS_B1 IOWR WE2 BS_B2 PCOE WE3 BS_B3 PCWE BS A 0 3 GPL A0 GPL BO OE GPL_A1 GPL_B1 GPL A 2 3 GPL B 2 3 CS 2 3 UPWAITA GPL_A4 UPWAITB GPL_B4 GPL ALE A CE1_A CE2_A ALE B DSCK AT1 OP 0 1 OP2 MODCK1 STS OP3 MODCK2 DSDO BADDR 28 30
6. 25 00 ns R77 data out drive MAX 0 00 x B1 25 00 R78 RSTCONF negated to data out high 25 00 25 00 25 00 25 00 ns impedance MAX 0 00 x B1 25 00 CLKOUT of last rising edge before chip 25 00 25 00 25 00 25 00 ns R79 three states HRESET to data out high impedance MAX 0 00 x B1 25 00 R80 DSDI DSCK setup MIN 3 00 x B1 190 90 75 00 60 00 45 50 1 ns DSDI DSCK hold time MIN 0 00 xB1 10 00 0 00 1 0 00 1 0 00 1 ns R81 0 00 SRESET negated to CLKOUT rising 242 40 200 00 160 00 121 20 ns R82 edge for DSDI and DSCK sample MIN 8 00 x B1 MPC866 MPC859 Hardware Specifications Rev 2 44 Freescale Semiconductor Bus Signal Timing Figure 34 shows the reset timing for the data bus configuration HRESET RSTCONF Figure 34 Reset Timing Configuration from Data Bus 5 Figure 35 shovvs the reset timing for the data bus vveak drive during configuration HRESET 4 RSTCONF ez 010 31 Figure 35 Reset Timing Data Bus VVeak Drive During Configuration MPC866 MPC859 Hardware Specifications Rev 2 Freescale Semiconductor 45 IEEE 1149 1 Electrical Specifications Figure 36 shovvs the reset timing for the debug port configuration R82 SRESET DSCK 0501 Figure 36 Reset Timin
7. 4 00 4 00 4 00 ns time 4 MIN 0 00 x B1 0 00 B17 CLKOUT to TA TEA BI BB BG BR 1 00 1 00 1 00 200 ns valid hold time MIN 0 00 x B1 1 00 5 B17a CLKOUT to KR RETRY CR valid hold 2 00 2 00 200 2001 ns time MIN 0 00 x 1 2 00 B18 1 D 0 31 DP 0 3 valid to CLKOUT 6 00 6 00 6 00 6 00 ns rising edge setup time MIN 0 00 x B1 6 00 B19 CLKOUT rising edge to D 0 31 1 00 1 00 1 00 2 00 ns DP 0 3 valid hold time MIN 0 00 x B1 1 00 5 B20 D 0 31 DP 0 3 valid to CLKOUT 4 00 4 00 4 00 4 00 ns falling edge setup time MIN 0 00 x B1 4 00 B21 CLKOUT falling edge to D 0 31 2 00 2 00 2 00 2 00 ns DP 0 3 valid hold Time MIN 0 00 x B1 2 00 B22 CLKOUT rising edge to CS asserted 7 60 13 80 6 30 12 50 5 00 11 30 3 80 10 00 ns GPCM ACS 00 MAX 0 25 x B1 6 3 B22a CLKOUT falling edge to CS asserted 8 00 8 00 8 00 8 00 ns GPCM ACS 10 TRLX 0 MAX 0 00 x B1 8 00 MPC866 MPC859 Hardware Specifications Rev 2 18 Freescale Semiconductor Table 9 Bus Operation Timings continued Bus Signal Timing Num Characteristic 33 MHz 40 MHz 50 MHz 66 MHz Min Max Min
8. 15 ns 46 TA assertion to falling edge of the clock setup time applies to external TA 7 ns CLKO Output DREQ Input Figure 47 IDMA External Requests Timing Diagram MPC866 MPC859 Hardware Specifications Rev 2 Freescale Semiconductor 51 CPM Electrical Characteristics CLKO Output TS Output Output TA Input SDACK Figure 48 SDACK Timing Diagram Peripheral Write Externally Generated TA CLKO Output TS Output RW Output TA Output SDACK Figure 49 SDACK Timing Diagram Peripheral Write Internally Generated TA MPC866 MPC859 Hardware Specifications Rev 2 52 Freescale Semiconductor CPM Electrical Characteristics CLKO Output TS Output R W Output TA Output SDACK Nf Figure 50 SDACK Timing Diagram Peripheral Read Internally Generated TA 12 4 Baud Rate Generator AC Electrical Specifications Table 19 shows the baud rate generator timings as shown in Figure 51 Table 19 Baud Rate Generator Timing All Frequencies Num Characteristic Unit Min Max 50 BRGO rise and fall time 10 ns 51 BRGO duty cycle 40 60 52 BRGO cycle 40 ns BRGOX Figure 51 Baud Rate Generator Timing Diagram MPC866 MPC859 Hardware Specifications Rev 2 Freescale Semiconductor 53 CPM Electrical Characteristics 12 5 Timer AC Electrical Specifications
9. 4 00 4 00 ns B5 CLKOUT fall time 4 00 4 00 4 00 4 00 ns B7 CLKOUT to A 0 31 BADDR 28 30 RD WR BURST D 0 31 DP 0 3 output hold MIN 0 25 x B1 7 60 6 30 5 00 3 80 ns B7a CLKOUT to TSIZ 0 1 REG RSV AT 0 3 BDIP PTR output hold MIN 0 25 x B1 7 60 6 30 5 00 3 80 ns B7b CLKOUT to BR BG FRZ VFLS 0 1 VF 0 2 IVVP 0 2 LVVP 0 1 STS output hold MIN 0 25 x B1 7 60 6 30 5 00 3 80 ns B8 CLKOUT to A 0 31 BADDR 28 30 RD VVR BURST D 0 31 DP 0 3 valid MAX 0 25 x B1 6 3 13 80 12 50 11 30 10 00 ns B8a CLKOUT to TSIZ 0 1 REG RSV AT 0 3 BDIP PTR valid MAX 0 25 x B1 6 3 13 80 12 50 11 30 10 00 ns B8b CLKOUT to BR BG VFLS 0 1 VF 0 2 IWP 0 2 FRZ LWP 0 1 STS valid MAX 0 25 x B1 6 3 13 80 12 50 11 30 10 00 ns B9 CLKOUT to A 0 31 BADDR 28 30 RD WR BURST D 0 31 DP 0 3 TSIZ 0 1 REG RSV AT 0 3 PTR High Z MAX 0 25 x B1 6 3 7 60 13 80 6 30 12 50 5 00 11 30 3 80 10 00 ns B11 CLKOUT to TS BB assertion MAX 0 25 x B1 6 0 7 60 13 60 6 30 12 30 5 00 11 00 3 80 9 80 ns Bila CLKOUT to TA BI assertion when driven by the memory controller or PCMCIA interface MAX 0 00 x B1 9 30 1 2 50 9 30 2 50 9 30 2
10. 8 Freescale Semiconductor Thermal Characteristics 4 Thermal Characteristics Table 4 shows the thermal characteristics for the MPC866 859 Table 4 MPC866 859 Thermal Resistance Data Rating Environment Symbol Value Unit Junction to ambient 1 Natural Convection Single layer board 1s Roja 2 37 C W Four layer board 2s2p Regma 23 Airflow 200 ft min Single layer board 1s Roma 30 Four layer board 2s2p Regma 19 Junction to board 4 Reus 13 Junction to case 5 Resc 6 Junction to package top 5 Natural Convection Wor 2 Airflow 200 ft min VT 2 1 Junction temperature is a function of on chip povver dissipation package thermal resistance mounting site board temperature ambient temperature airflovv povver dissipation of other components on the board and board thermal resistance 2 Per SEMI G38 87 and JESD51 2 with the single layer board horizontal 3 Per JEDEC JESD51 6 with the board horizontal 4 Thermal resistance between the die and the printed circuit board per JEDEC JESD51 8 Board temperature is measured on the top surface of the board near the package Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method MIL SPEC 883 Method 1012 1 with the cold plate temperature used for the case temperature For exposed pad packages where the pad would be expected to be soldered junction to case thermal re
11. 0 CSNT 1 EBDF 0 MIN 0 50 x B1 2 00 13 20 10 50 8 00 5 60 ns B29b CS negated to D 0 31 DP 0 3 High Z GPCM write access ACS 00 TRLX 0 1 amp CSNT MIN 0 25 x B1 2 00 5 60 4 30 3 00 1 80 ns B29c CS negated to D 0 31 DP 0 3 High Z GPCM write access TRLX 0 CSNT 1 ACS 10 or ACS 11 EBDF 0 MIN 0 50 x B1 2 00 13 20 10 50 8 00 5 60 ns B29d WE 0 3 negated to D 0 31 DP 0 3 High Z GPCM write access TRLX 1 CSNT 1 EBDF 0 MIN 1 50 x B1 2 00 43 50 35 50 28 00 20 70 ns B29e CS negated to D 0 31 DP 0 3 High Z GPCM write access TRLX 1 CSNT 1 ACS 10 or ACS 11 EBDF 0 MIN 1 50 x B1 2 00 43 50 35 50 28 00 20 70 ns B29f VVE 0 3 negated to D 0 31 DP 0 3 High Z GPCM write access TRLX 0 CSNT 1 EBDF 1 MIN 0 375 x B1 6 30 5 00 3 00 0 00 ns B29g CS negated to D 0 31 DP 0 3 High Z GPCM write access TRLX 0 CSNT 1 ACS 10 or ACS 11 EBDF 1 MIN 0 375 x B1 6 30 5 00 3 00 0 00 ns B29h WE 0 3 negated to D 0 31 DP 0 3 High Z GPCM write access TRLX 1 CSNT 1 EBDF 1 MIN 0 375 x B1 3 30 38 40 31 10 24 20 17 50 ns B29i CS negated to D 0 31 DP 0 3 High Z GPCM write access TRLX 1 CSNT 1 ACS 10 or ACS 11 EBDF 1 MIN
12. Freescale Semiconductor 60 CPM Electrical Characteristics 12 7 SCC in NMSI Mode Electrical Specifications Table 22 shows the NMSI external clock timings Table 22 NMSI External Clock Timings All Frequencies Num Characteristic Unit Min Max 100 RCLK1 and TCLK1 width high 1 SYNCCLK ns 101 RCLK1 and TCLK1 width low 1 SYNCCLK 5 ns 102 RCLK1 and TCLKT rise fall time 15 00 ns 103 TXD1 active delay from TCLK1 falling edge 0 00 50 00 ns 104 RTS1 active inactive delay from TCLK1 falling edge 0 00 50 00 ns 105 CTS1 setup time to TCLK1 rising edge 5 00 ns 106 RXD1 setup time to RCLK1 rising edge 5 00 ns 107 RXD1 hold time from RCLKT rising edge 5 00 ns 108 CD1 setup time to RCLKT rising edge 5 00 ns 1 The ratios SyncCLK RCLK1 and SyncCLK TCLK1 must be greater than or equal to 2 25 1 2 Also applies to CD and CTS hold time when they are used as an external sync signal Table 23 shows the NMSI internal clock timings Table 23 NMSI Internal Clock Timings All Frequencies Num Characteristic Unit Min Max 100 RCLK1 and TCLK1 frequency 1 0 00 SYNCCLK 3 MHz 102 RCLK1 and TCLKT rise fall time ns 103 TXD1 active delay from TCLK1 falling edge 0 00 30 00 ns 104 RTS1 active inactive delay from TCLKT falling edge 0 00 30 00 ns 105 CTS1 setup time to TCLK1 rising edge 40 00 ns 106 RXD1 setup time to RCLK1 rising edge
13. Independent can be connected to any SCC or SMC Allow changes during operation Autobaud support option e MPC866P and MPC866T have four SCCs serial communication controller MPCS59P MPC859T and MPCS59DSL have one SCC and SCC1 on MPC859DSL supports Ethernet only Serial ATM capability on all SCCs Optional UTOPIA port on SCC4 Ethernet IEEE 802 3 optional on SCC1 4 supporting full 10 Mbps operation HDLC SDLC HDLC bus implements an HDLC based local area network LAN Asynchronous HDLC to support PPP point to point protocol AppleTalk Universal asynchronous receiver transmitter UART Synchronous UART Serial infrared IrDA Binary synchronous communication BISYNC Totally transparent bit streams Totally transparent frame based with optional cyclic redundancy check CRC e Two SMCs serial management channels MPC859DSL has one SMC SMC1 for UART UART Transparent General circuit interface GCI controller Can be connected to the time division multiplexed TDM channels MPC866 MPC859 Hardware Specifications Rev 2 Freescale Semiconductor Features e One serial peripheral interface SPI Supports master and slave modes Supports multiple master operation on the same bus e One inter integrated circuit port Supports master and slave modes Multiple master environment support e Time slot assigner TSA MPC859DSL does not have TSA Allows SCCs and SMCs to run in multiplexed an
14. Name Pin Number Type PB16 LTRQa L1ST4 RTS4 1 RXADDRO N16 Bidirectional Optional Open drain PB15 BRGO3 TxClav RxClav R17 Bidirectional PB14 22 RSTRT1 U18 Bidirectional PC15 DREQO RTS1 L1ST1 RxClav TxClav D16 Bidirectional PC14 DREQi RTS2 L1ST2 D18 Bidirectional PC13 L1RQb L1ST3 RTS3 E18 Bidirectional PC12 L1RQa L1ST4 RTS4 F18 Bidirectional PC11 CTS1 J19 Bidirectional PC10 CD1 TGATE1 K19 Bidirectional PC9 CTS2 L18 Bidirectional PC8 CD2 TGATE2 M18 Bidirectional MPC866 MPC859 Hardware Specifications Rev 2 88 Freescale Semiconductor Mechanical Data and Ordering Information Table 39 Pin Assignments continued Name Pin Number Type PC7 CTS3 LTTSYNCB SDACK2 M16 Bidirectional PC6 CD3 LTRSYNCB R19 Bidirectional PC5 CTS4 LTTSYNCA SDACK1 T18 Bidirectional PC4 CD4 LTRSYNCA T17 Bidirectional PD15 LTTSYNCA Mil RXD3 UTPBO U17 Bidirectional PD14 LTRSYNCA Mil RXD2 UTPB1 V19 Bidirectional PD13 LTTSYNCB Mil RXD1 UTPB2 V18 Bidirectional PD12 LTRSYNCB MI MDC UTPB3 R16 Bidirectional PD11 RXD3 Mil TXERR RXENB T16 Bidirectional PD10 TXD3 Mil RXDO TXENB VV18 Bidirectional MPC866 MPC859 Ha
15. RENA active delay from RCLKT rising edge of the last data bit 10 ns 127 RENA width low 100 ns 128 TCLKT rise fall time 15 ns 129 TCLK1 width low 40 ns 130 TCLKT1 clock period 1 99 101 ns 131 TXD1 active delay from TCLK1 rising edge 50 ns 132 TXD1 inactive delay from TCLK1 rising edge 6 5 50 ns 133 TENA active delay from TCLK1 rising edge 10 50 ns MPC866 MPC859 Hardware Specifications Rev 2 Freescale Semiconductor 63 CPM Electrical Characteristics Table 24 Ethernet Timing continued All Frequencies Num Characteristic Unit Min Max 134 TENA inactive delay from TCLK1 rising edge 10 50 ns 135 RSTRT active delay from TCLK1 falling edge 10 50 ns 136 RSTRT inactive delay from TCLK1 falling edge 10 50 ns 137 REJECT width low 1 CLK 138 CLKO1 low to SDACK asserted 20 ns 139 CLKO1 low to SDACK negated 20 ns 1 The ratios SyncCLK RCLK1 and SyncCLK TCLK1 must be greater or equal to 2 1 2 SDACK is asserted whenever the SDMA writes the incoming frame DA into memory CLSN CTS1 Input 5 gt Figure 61 Ethernet Collision Timing Diagram RENA CD1 Input Figure 62 Ethernet Receive Timing Diagram MPC866 MPC859 Hardware Specifications Rev 2 64 Freescale Semiconductor CPM Electrical Characteristics TCLK1 TxD1 Output TENA RTS1 Input
16. Max Min Max Min Max Unit B22b CLKOUT falling edge to CS asserted GPCM ACS 11 TRLX 0 EBDF 0 MAX 0 25 x B1 6 3 7 60 13 80 6 30 12 50 5 00 11 30 3 80 10 00 ns B22c CLKOUT falling edge to CS asserted GPCM ACS 11 TRLX 0 EBDF 1 MAX 0 375 x B1 6 6 10 90 18 00 10 90 16 00 7 00 14 10 5 20 12 30 ns B23 CLKOUT rising edge to CS negated GPCM read access GPCM write access ACS 00 0 amp CSNT 0 MAX 0 00 x B1 8 00 2 00 8 00 2 00 8 00 2 00 8 00 2 00 8 00 ns B24 A 0 31 and BADDR 28 30 to CS asserted GPCM ACS 10 TRLX 0 MIN 0 25 x B1 2 00 5 60 4 30 3 00 1 80 ns B24a A 0 31 and BADDR 28 30 to CS asserted GPCM ACS 11 TRLX 0 MIN 0 50 x B1 2 00 13 20 10 50 8 00 5 60 ns B25 CLKOUT rising edge to OE WE 0 3 asserted MAX 0 00 x B1 9 00 9 00 9 00 9 00 9 00 ns B26 CLKOUT rising edge to OE negated MAX 0 00 x B1 9 00 2 00 9 00 2 00 9 00 2 00 9 00 2 00 9 00 ns B27 A 0 31 and BADDR 28 30 to CS asserted GPCM ACS 10 TRLX 1 MIN 1 25 x B1 2 00 35 90 29 30 23 00 16 90 ns B27a A 0 31 and BADDR 28 30 to CS asserted GPCM ACS 11 TRLX 1 MIN 1 50 x B1 2 00 43 50 35 50 28 00 20 70 ns B28 CLKOUT rising edge
17. N8 N9 N10 N11 N12 N13 N14 P6 P7 P8 P9 P10 P11 P12 P13 P14 VDDL A8 M1 W8 H19 F4 F16 P4 P16 R1 Power VDDH E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 F5 F15 G5 Power G15 H5 H15 J5 J15 K5 K15 L5 L15 M5 M15 N5 N15 P5 P15 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 T14 N C D6 D13 D14 U2 V2 T2 No connect 1 Classic SAR mode only 2 ESAR mode only MPC866 MPC859 Hardware Specifications Rev 2 Freescale Semiconductor 91 Mechanical Data and Ordering Information 15 2 Mechanical Dimensions of the PBGA Package For more information on the printed circuit board layout of the PBGA package including thermal via design and suggested pad layout please refer to P asric Ball Grid Array Application Note order number AN1231 D available from your local Freescale sales office Figure 79 shows the mechanical dimensions of the PBGA package 25 B le 22 6 A1 INDEX 22 4 22 6 22 4 125 1 4X CN 0 2 1 TOP VIEVV 22 86 M 18X 1 27 EY 2 o o oo 2 0 PP or 0 00 0 0 00 2000 04 b555665 18X 1 27 9 ooo 9 257 0 OO O 2 OG ODO o O PP O 6 65 0 o 2
18. Rev 2 2 Freescale Semiconductor Features ATM port to port svvitching capability vvithout the need for RAM based microcode Simultaneous MII 10 100Base T and UTOPIA half duplex capability Optional statistical cell counters per PHY UTOPIA level 2 compliant interface with added FIFO buffering to reduce the total cell transmission time The earlier UTOPIA level 1 specification is also supported Multi PHY support on the MPC866 MPC859P and MPC859T Four PHY support on the MPC866 859 Parameter RAM for both SPI and 17C can be relocated without RAM based microcode Supports full duplex UTOPIA both master ATM side and slave PHY side operation using a split bus AAL2 VBR functionality is ROM resident to 32 bit data bus dynamic bus sizing for 8 16 and 32 bits e Thirty two address lines e Memory controller eight banks Contains complete dynamic RAM DRAM controller Each bank can be a chip select or RAS to support a DRAM bank Up to 30 wait states programmable per memory bank Glueless interface to page mode EDO SDRAM SRAM EPROMs flash EPROMs and other memory devices DRAM controller programmable to support most size and speed memory interfaces Four CAS lines four WE lines and one OE line Boot chip select available at reset options for 8 16 or 32 bit memory Variable block sizes 32 Kbytes 256 Mbytes Selectable write protection On chip bus arbitration logic General purpose
19. high or lovv time 1 teye 174 Slave sequential transfer delay does not require deselect 1 teye 175 Slave data setup time inputs 20 ns 176 Slave data hold time inputs 20 ns 177 Slave access time 50 ns MPC866 MPC859 Hardware Specifications Rev 2 68 Freescale Semiconductor SPISEL Input SPICLK 1 0 Input SPICLK Cl 1 Input SPIMISO Output SPIMOSI Input Figure 69 SPI Slave CP 0 Timing Diagram MPC866 MPC859 Hardware Specifications Rev 2 CPM Electrical Characteristics Freescale Semiconductor 69 CPM Electrical Characteristics SPISEL Input SPICLK Cl 0 Input SPICLK Cl 1 Input SPIMISO Output SPIMOSI Input Figure 70 SPI Slave CP 1 Timing Diagram 12 1217C AC Electrical Specifications MPC866 MPC859 Hardware Specifications Rev 2 70 Freescale Semiconductor CPM Electrical Characteristics Table 28 shows the I C SCL lt 100 kHz timings Table 28 12 Timing SCL 100 kHz All Frequencies Num Characteristic Unit Min Max 200 SCL clock frequency slave 0 100 kHz 200 SCL clock frequency master 1 5 100 kHz 202 1 Bus free time betvveen transmissions 4 7 us 203 Low period of SCL 4 7 H
20. 0 375 x B1 3 30 38 40 31 10 24 20 17 50 ns MPC866 MPC859 Hardware Specifications Rev 2 20 Freescale Semiconductor Bus Signal Timing Table 9 Bus Operation Timings continued 33 MHz 40 MHz 50 MHz 66 MHz Num Characteristic Unit Min Max Min Max Min Max Min Max B30 CS VVE 0 3 negated to A 0 31 5 60 430 3001 1 80 ns BADDR 28 30 invalid GPCM write access 7 MIN 0 25 x B1 2 00 B30a WE 0 3 negated to A 0 31 13 20 10 50 8 00 5 60 ns BADDR 28 30 invalid GPCM write access TRLX 0 CSNT 1 CS negated to A 0 31 invalid GPCM write access TRLX 0 CSNT 1 ACS 10 or ACS 11 EBDF 0 MIN 0 50 x B1 2 00 B30b WE 0 3 negated to A 0 31 invalid 43 50 35 50 28 00 20 70 ns GPCM BADDR 28 30 invalid GPCM write access TRLX 1 CSNT 1 CS negated to A 0 31 invalid GPCM write access TRLX 1 CSNT 1 ACS 10 or ACS 11 EBDF 0 MIN 1 50 x B1 2 00 B30c WE 0 3 negated to A 0 31 8 40 6 40 4 50 2 70 ns BADDR 28 30 invalid GPCM write access TRLX 0 CSNT 1 CS negated to A 0 31 invalid GPCM write access TRLX 0 CSNT 1 ACS 10 ACS 11 EBDF 1 MIN 0 375 x B1 3 00 B30d WE 0 3 negated to A 0 31 38 67 31 38 24 50 17 83 ns BADDR 28 30 invalid GPCM write access TRLX 1 CSNT 1 CS negated to A 0
21. 31 invalid GPCM write access TRLX 1 CSNT 1 ACS 10 or 11 EBDF 1 B31 CLKOUT falling edge to CS valid as 1 50 6 00 1 50 6 00 1 50 6 00 1 50 6 00 ns requested by control bit CST4 in the corresponding word in the UPM MAX 0 00 X B1 6 00 B31a CLKOUT falling edge to CS valid as 7 60 14 30 6 30 13 00 5 00 11 80 3 80 10 50 ns requested by control bit CST1 in the corresponding word in the UPM MAX 0 25 x B1 6 80 B31b CLKOUT rising edge to CS valid as 1 50 8 00 1 50 8 00 1 50 8 00 1 50 8 00 ns requested by control bit CST2 in the corresponding word in the UPM MAX 0 00 x B1 8 00 B31c CLKOUT rising edge to CS valid as 7 60 13 80 6 30 12 50 5 00 11 30 3 80 10 00 ns requested by control bit CST3 in the corresponding word in the UPM MAX 0 25 x B1 6 30 MPC866 MPC859 Hardware Specifications Rev 2 Freescale Semiconductor 21 Bus Signal Timing Table 9 Bus Operation Timings continued 33 MHz 40 MHz 50 MHz 66 MHz Num Characteristic Unit Min Max Min Max Min Max Min Max B31d CLKOUT falling edge to CS valid as 13 30 18 00 11 30 16 00 9 40 14 10 7 60 12 30 ns requested by control bit CST1 in the corresponding word in the UPM EBDF 1 MAX 0 375 x B1 6 6 B32 CLKOUT falling edge to BS valid as 1 50 6 00 1 50 6 00 1 50 6 00 1 50 6 00
22. 40 00 ns 107 1 RXD1 hold time from RCLK1 rising edge 0 00 ns 108 CD1 setup time to RCLK1 rising edge 40 00 ns The ratios SyncCLK RCLK1 and SyncCLK TCLK1 must be greater or equal to 3 1 Also applies to CD and CTS hold time when they are used as an external sync signals MPC866 MPC859 Hardware Specifications Rev 2 Freescale Semiconductor 61 CPM Electrical Characteristics Figure 58 through Figure 60 shovv the NMSI timings RCLK1 RxD1 Input AN nput 01 SYNC Input Figure 58 SCC NMSI Receive Timing Diagram TCLK1 TxD1 Output 4 RTS1 Output 51 Input CTS1 SYNC Input Figure 59 SCC NMSI Transmit Timing Diagram MPC866 MPC859 Hardware Specifications Rev 2 62 Freescale Semiconductor TCLK1 RTS1 Output CTS1 Echo Input Figure 60 HDLC Bus Timing Diagram 12 8 Ethernet Electrical Specifications Table 24 shows the Ethernet timings as shown in Figure 61 through Figure 65 Table 24 Ethernet Timing CPM Electrical Characteristics All Frequencies Num Characteristic Unit Min Max 120 CLSN width high 40 ns 121 RCLKT rise fall time 15 ns 122 RCLK1 width low 40 ns 123 RCLK1 clock period 1 80 120 ns 124 RXD1 setup time 20 ns 125 1 RXD1 hold time 5 ns 126
23. 60 6 30 14 30 5 00 13 00 3 80 11 80 1 ns MAX 0 25 x B1 8 00 P49 CLKOUT to CE1 CE2 negated 7 60 15 60 6 30 14 30 5 00 13 00 3 80 11 80 ns MAX 0 25 x B1 8 00 MPC866 MPC859 Hardware Specifications Rev 2 38 Freescale Semiconductor Table 11 PCMCIA Timing continued Bus Signal Timing Num Characteristic 33 MHz 40 MHz 50 MHz 66 MHz Min Max Min Max Min Max Min Max Unit P50 CLKOUT to PCOE IORD PCWE IOWR assert time MAX 0 00 x B1 11 00 11 00 11 00 11 00 11 00 ns P51 CLKOUT to PCOE IORD PCWE IOWR negate time MAX 0 00 x B1 11 00 2 00 11 00 2 00 11 00 2 00 11 00 2 00 11 00 ns P52 CLKOUT to ALE assert time MAX 0 25 x B1 6 30 7 60 13 80 6 30 12 50 5 00 11 30 3 80 10 00 ns P53 CLKOUT to ALE negate time MAX 0 25 x B1 8 00 15 60 14 30 13 00 11 80 ns P54 PCVVE IOWR negated to D 0 31 invalid MIN 0 25 x B1 2 00 5 60 4 30 3 00 1 80 ns P55 VVA TA and WAITB valid to CLKOUT rising edge MIN 0 00 x B1 8 00 8 00 8 00 8 00 8 00 ns P56 CLKOUT rising edge to WAITA and WAITB invalid MIN 0 00 x B1 2 00 2 00 2 00 2 00 2 00 ns T PSST 1 Otherwise
24. Ambient Divided by Package Power Figure 3 Effect of Board Temperature Rise on Thermal Behavior If the board temperature is known an estimate of the junction temperature in the environment can be made using the following equation Ty Ta Ro x Pp where Roy junction to board thermal resistance C W Tp board temperature C Pp power dissipation in package If the board temperature is known and the heat loss from the package case to the air can be ignored acceptable predictions of junction temperature can be made For this method to work the board and board mounting must be similar to the test board used to determine the junction to board thermal resistance namely a 2s2p board with a power and a ground plane and vias attaching the thermal balls to the ground plane 7 4 Estimation Using Simulation When the board temperature is not known a thermal simulation of the application is needed The simple two resistor model can be used with the thermal simulation of the application 2 or a more accurate and complex model of the package can be used in the thermal simulation MPC866 MPC859 Hardware Specifications Rev 2 Freescale Semiconductor 13 Thermal Calculation and Measurement 7 5 Experimental Determination To determine the function temperature of the device in the application after prototypes are available the thermal characterization parameter can be used to determine the junction temperature with a
25. Freescale Semiconductor Table 39 Pin Assignments continued Name Pin Number Type UPWAITB B1 Bidirectional 4 GPL_A5 D3 Output PORESET R2 Input RSTCONF P3 Input HRESET N4 Open drain SRESET P2 Open drain XTAL P1 Analog Output EXTAL N1 Analog Input 3 3V only CLKOUT W3 Output EXTCLK N2 Input 3 3V only TEXP N3 Output ALE_A K2 Output MII TXD1 CE1_A B3 Output MII TXD2 2 A3 Output MII TXD3 WAIT_A R3 Input SOC_Split WAIT_B R4 Input IP_AO T5 nput UTPB Splito MII RXD3 P 1 T4 nput UTPB Split1 MII RXD2 IP_A2 U3 Input 101516 A Split MII RXD1 IP A3 W2 Input UTPB_Split3 MII RXDO IP_A4 U4 Input UTPB_Split4 MII RXCLK MPC866 MPC859 Hardware Specifications Rev 2 Mechanical Data and Ordering Information Freescale Semiconductor 83 Mechanical Data and Ordering Information Table 39 Pin Assignments continued Name Pin Number Type P U5 Input UTPB Split5 MII RXERR IP_A6 T6 Input UTPB Splite MII TXERR P A7 T3 nput UTPB Split7 MII RXDV ALE B J1 Bidirectional DSCK AT1 Three state IP_B 0 1 H2 J3 Bidirectional 10 11 VFLS 0 1 IP_B2 J2 Bidirectional 101816 B Three state AT2 IP B3 G1 Bidirectional IWP2 VF2 IP_B4 G2 Bidirectional LWPO VFO IP_B5 J4 Bidirectional LVVP1 VF1 IP_B6 K3 Bidirectional D
26. GPL_B5 TS F3 Bidirectional Active Pull up TA C2 Bidirectional Active Pull up TEA D1 Open drain BI E3 Bidirectional Active Pull up IRQ2 H3 Bidirectional RSV Three state IRQ4 K1 Bidirectional KR Three state RETRY SPKROUT CR F2 Input IRQ3 D 0 31 W14 W12 W11 W10 W13 W9 W7 W6 U13 T11 V11 U11 Bidirectional T13 V13 V10 T10 U10 T12 V9 U9 V8 U8 T9 U12 V7 T8 Three state U7 V12 V6 W5 U6 T7 DPO V3 Bidirectional IRQ3 Three state DP1 V5 Bidirectional IRQ4 Three state DP2 VV4 Bidirectional IRQB Three state DP3 V4 Bidirectional IRQ6 Three state MPC866 MPC859 Hardware Specifications Rev 2 Freescale Semiconductor 81 Mechanical Data and Ordering Information Table 39 Pin Assignments continued Name Pin Number Type BR G4 Bidirectional BG E2 Bidirectional BB E1 Bidirectional Active Pull up FRZ G3 Bidirectional IRQ6 IRQO V14 nput IRQ1 U14 Input M_TX_CLK W15 Input IRQ7 CS 0 5 C3 A2 D4 E4 A4 B4 Output CS6 D5 Output CE1_B CS7 C4 Output CE2_B WEO C7 Output BS BO IORD WE1 A6 Output 5 1 IOWR WE2 B6 Output BS_B2 PCOE WE3 A5 Output BS_B3 PCWE BS_A 0 3 D8 C8 A7 B8 Output GPL_AO D7 Output GPL BO OE C6 Output GPL_A1 GPL_B1 GPL_A 2 3 B5 C5 Output GPL_B 2 3 CS 2 3 UPWAITA C1 Bidirectional GPL_A4 MPC866 MPC859 Hardware Specifications Rev 2 82
27. Hardware Specifications Rev 2 14 Freescale Semiconductor Povver Supply and Povver Sequencing 8 Power Supply and Power Sequencing This section provides design considerations for the MPC866 859 power supply The MPC866 859 has a core voltage VDDL and PLL voltage VDDSYN that operates at a lower voltage than the I O voltage VDDH The I O section of the MPC866 859 is supplied with 3 3 V across VDDH and Vss GND Signals PA 0 15 PB 14 31 PC 4 15 PD 3 15 TDI TDO TCK TRST_B TMS M T TXEN and MII_MDIO are 5 V tolerant All inputs cannot be more than 2 5 V greater than VDDH In addition 5 V tolerant pins cannot exceed 5 5 V and the remaining input pins cannot exceed 3 465 V This restriction applies to power up down and normal operation One consequence of multiple power supplies is that when power is initially applied the voltage rails ramp up at different rates The rates depend on the nature of the power supply the type of load on each power supply and the manner in which different voltages are derived The following restrictions apply VDDL must not exceed VDDH during power up and power down e VDDL must not exceed 1 9 V and VDDH must not exceed 3 465 V These cautions are necessary for the long term reliability of the part If they are violated the electrostatic discharge ESD protection diodes are forward biased and excessive current can flow through these diodes If the system power supply design does not control
28. O Timers 4 Interrupt System Interface Unit SIU Memory Controller Internal External Bus Interface Bus Interface Unit Unit System Functions Controllers 1 Dual Port RAM PCMCIA ATA Interface 10 Virtual Serial 32 Bit RISC Controller and Program Timers ROM and 2 Independent DMA Channels 1 0 1 z 4 Baud Rate ase Generators Media Access Control Parallel Interface Port and UTOPIA A y SCC1 l SMC1 SMC2 SPI eC Time Slot Assigner Serial Interface Yy y t The MPC859P has a 16 Kbyte instruction cache and a 8 Kbyte data cache The MPC859DSL does not contain SMC2 nor the time slot assigner and provides eight SDMA controllers Figure 2 MPC859P 859T MPC859DSL Block Diagram MPC866 MPC859 Hardware Specifications Rev 2 Features Freescale Semiconductor Maximum Tolerated Ratings 3 Maximum Tolerated Ratings This section provides the maximum tolerated voltage and temperature ranges for the MPC866 859 Table 2 shows the maximum tolerated ratings and Table 3 shows the operating temperatures Table 2 Maximum Tolerated Ratings Rating Symbol Value Unit Supply voltage 1 VDDH 0 3 to 4 0 V VDDL 0 3 to 2 0 VDDSYN 0 3 to 2 0 Difference betvveen VDDL to VDDSYN 100 mv Input voltage Vin GND 0 3 to S
29. RENA CD1 Input Notes 1 Transmit clock invert TCI bit in GSMR is set 2 If RENA is deasserted before TENA or RENA is not asserted at all during transmit then the CSL bit is set in the buffer descriptor at the end of the frame transmission Figure 63 Ethernet Transmit Timing Diagram RxD1 lt _ Start Frame Delimiter RSTRT Output Figure 64 CAM Interface Receive Start Timing Diagram REJECT 137 Figure 65 CAM Interface Timing Diagram 12 9 SMC Transparent AC Electrical Specifications Table 25 shovvs the SMC transparent timings as shovvn in Figure 66 MPC866 MPC859 Hardware Specifications Rev 2 Freescale Semiconductor 65 CPM Electrical Characteristics Table 25 SMC Transparent Timing All Frequencies Num Characteristic Unit Min Max 150 SMCLK clock period 1 100 ns 151 SMCLK width low 50 ns 151A SMCLK width high 50 ns 152 SMCLK rise fall time 15 ns 153 SMTXD active delay from SMCLK falling edge 10 50 ns 154 1SMRXD SMSYNC setup time 20 ns 155 1 RXD1 SMSYNC hold time 5 ns Sync CLK must be at least tvvice as fast as SMCLK SMCLK SMTXD Output SMSYNC SMRXD Input NOTE 1 This delay is equal to an integer number of character length clocks Figure 66 SMC Transparent Timing Diagram MPC866 MPC859 Hardware Specifications Rev
30. Table 20 shows the general purpose timer timings as shown in Figure 52 Table 20 Timer Timing All Frequencies Num Characteristic Unit Min Max 61 TIN TGATE rise and fall time 10 ns 62 TIN TGATE low time 1 clk 63 TIN TGATE high time 2 clk 64 TIN TGATE cycle time 3 clk 65 CLKO low to TOUT valid 3 25 ns CLKO TIN TGATE Input 2 65 TOUT Output Figure 52 CPM General Purpose Timers Timing Diagram 12 6 Serial Interface AC Electrical Specifications Table 21 shows the serial interface timings as shown in Figure 53 through Figure 57 Table 21 SI Timing All Frequencies Num Characteristic Unit Min Max 70 L1RCLK L1TCLK frequency DSC 0 1 2 SYNCCLK 2 5 MHz 71 LTRCLK L1TCLK width low DSC 0 P 10 ns 71a L1RCLK L1TCLK width high DSC 0 3 P 10 ns 72 L1TXD L1S1T 1 4 L1RQ L1CLKO rise fall time 15 00 ns 73 LTRSYNC L1TSYNC valid to L1CLK edge SYNC 20 00 ns setup time MPC866 MPC859 Hardware Specifications Rev 2 54 Freescale Semiconductor CPM Electrical Characteristics Table 21 SI Timing continued All Frequencies Num Characteristic Unit Min Max 74 L1CLK edge to L1RSYNC L1TSYNC invalid 35 00 ns SYNC hold time 75 LIRSYNC L1TSYNC rise fall time 15 00 ns 76 L1RXD valid to
31. U19 Bidirectional CLK8 TOUT4 LTTCLKB PB31 C17 Bidirectional SPISEL Optional Open drain REJECT1 PB30 C19 Bidirectional SPICLK Optional Open drain RSTRT2 PB29 E16 Bidirectional SPIMOSI Optional Open drain PB28 D19 Bidirectional SPIMISO Optional Open drain BRGO4 PB27 E19 Bidirectional 12CSDA Optional Open drain BRGO1 PB26 F19 Bidirectional I2CSCL Optional Open drain BRGO2 MPC866 MPC859 Hardware Specifications Rev 2 86 Freescale Semiconductor Mechanical Data and Ordering Information Table 39 Pin Assignments continued Name Pin Number Type PB25 J16 Bidirectional RXADDR3 Optional Open drain SMTXD1 PB24 J18 Bidirectional TXADDR3 Optional Open drain SMRXD1 PB23 K17 Bidirectional TXADDR22 Optional Open drain SDACK1 SMSYN1 PB22 L19 Bidirectional TXADDR42 Optional Open drain SDACK2 SMSYN2 PB21 K16 Bidirectional SMTXD2 Optional Open drain L1CLKOB PHSEL1 1 2 20 116 Bidirectional SMRXD2 Optional Open drain L1CLKOA PHSELO TXADDRO PB19 N19 Bidirectional RTS1 Optional Open drain L1ST1 PB18 N17 Bidirectional RXADDR4 Optional Open drain RTS2 L1ST2 PB17 P18 Bidirectional L1RQb Optional Open drain L1ST3 RTS3 PHREQ11 RXADDR1 MPC866 MPC859 Hardware Specifications Rev 2 Freescale Semiconductor 87 Mechanical Data and Ordering Information Table 39 Pin Assignments continued
32. add PSST times cycle time PSHT 0 Otherwise add PSHT times cycle time These synchronous timings define when the WAITx signals are detected in order to freeze or relieve the PCMCIA current cycle The WAITx assertion will be effective only if itis detected 2 cycles before the PSL timer expiration See PCMCIA Interface in the MPC866 PowerQUICC User s Manual MPC866 MPC859 Hardware Specifications Rev 2 Freescale Semiconductor 39 Bus Signal Timing Figure 27 shows the PCMCIA access cycle timing for the external bus read pu PCOE IORD ALE 010 311 Figure 27 PCMCIA Access Cycles Timing External Bus Read MPC866 MPC859 Hardware Specifications Rev 2 40 Freescale Semiconductor Bus Signal Timing Figure 28 shows the PCMCIA access cycle timing for the external bus write ini gt 48 9 pag P46 9 o an a Figure 28 PCMCIA Access Cycles Timing External Bus Write Figure 29 shows the PCMCIA WAIT signals detection timing CLKOUT WAITx Figure 29 PCMCIA WAIT Signals Detection Timing MPC866 MPC859 Hardware Specifications Rev 2 Freescale Semiconductor 41 Bus Signal Timing Table 12 shows the PCMCIA port timing for the MPC866 859 Table 12 PCMCIA Port Timing 33 MHz 40 MHz 50 MHz 66 MHz Num Characteristic Unit Min Max Min Max Min Max Min Max
33. e e TRST TMS TDO PA11 A7 PB15 PD12 PA3 VDDL PA8 PB20 A3 A6 PC4 PD11 PA6 A4 A5 0 0 09 4 3 10 1 A28 PC8 O O ORMO O O O ORF PB22 PC9 A2 PA2 A1 PB28 PC14 PA14 PC15 OQ O O 4 O O O O CO 4 OD 0 1 41 QO O OG A25 O O O U O O O O OD O 0 O O QO O U OlL3445 10 9 23 21 26 12 PA12 VDDL 27 PC13 PA13 29 ORC ee GND O O O ORMO O00000 O ORF GND ORMO O 0000000 ORJ G Q a O O PC6 PB19 PA5 PB18 PB16 PC11 PB24 PA10 PB25 PAO PB14 PD15 PC5 O PA1 PA4 17 PB30 PA15 PB31 PA7 AO Freescale Semiconductor Figure 78 Pinout of the PBGA Package MPC866 MPC859 Hardware Specifications Rev 2 80 Mechanical Data and Ordering Information Table 39 contains a list of the MPC866 input and output signals and shows multiplexing and pin assignments Table 39 Pin Assignments Name Pin Number Type A 0 31 B19 B18 A18 C16 B17 A17 B16 A16 D15 C15 B15 A15 Bidirectional C14 B14 A14 D12 C13 B13 D9 D11 C12 B12 B10 B11 C11 Three state D10 C10 A13 A10 A12 A11 A9 TSIZO B9 Bidirectional REG Three state TSIZ1 c9 Bidirectional Three state RDAVR B2 Bidirectional Three state BURST F1 Bidirectional Three state BDIP D2 Output
34. ns propagation delay MII_MDIO input to MIl_MDC rising edge setup 1 ons MPC866 MPC859 Hardware Specifications Rev 2 76 Freescale Semiconductor FEC Electrical Characteristics Table 36 MII Serial Management Channel Timing Rum Characteristic MII_MDIO input to rising edge hold MII_MDC pulse width high MII_MDC period MIl_MDC pulse width low MII_MDC period Figure 77 shows the MII serial management channel timing diagram M14 TY MM15 MII_MDC output M10 _ MII_MDIO output XX M11 MII_MDIO input pan ed M12 M13 Figure 77 MII Serial Management Channel Timing Diagram MPC866 MPC859 Hardware Specifications Rev 2 Freescale Semiconductor 77 Mechanical Data and Ordering Information 15 Mechanical Data and Ordering information Table 37 shovvs information on the MPC866 859 derivative devices Table 37 MPC866 859 Derivatives Device 5 Ethernet Multi Channel ATM Support cache Size sccs1 Support HDLC Support Instruction Data MPC866T 4 10 100 Mbps Yes Yes 4 Kbyte 4 Kbytes MPC866P 4 10 100 Mbps Yes Yes 16 Kbyte 8 Kbytes MPC859T 1 SCC1 10 100 Mbps Yes Yes 4 Kbyte 4 Kbytes MPC859DSL 1 SCC1 10 100 Mbps No Up to 4 addresses 4 Kbyte 4 Kbytes 1 Serial communications controller SCC Table 38 identifies the packages and operating frequencies orderable for the MPC866 859 derivative devices Tabl
35. ns requested by control bit BST4 in the corresponding word in the UPM MAX 0 00 x B1 6 00 B32a CLKOUT falling edge to BS valid as 7 60 14 30 6 30 13 00 5 00 11 80 3 80 10 50 ns requested by control bit BST1 in the corresponding word in the UPM EBDF 0 MAX 0 25 x B1 6 80 B32b CLKOUT rising edge to BS valid as 1 50 8 00 1 50 8 00 1 50 8 00 1 50 8 00 ns requested by control bit BST2 in the corresponding word in the UPM MAX 0 00 x B1 8 00 B32c CLKOUT rising edge to BS valid as 7 60 14 30 6 30 13 00 5 00 11 80 3 80 10 50 ns requested by control bit BST3 in the corresponding word in the UPM MAX 0 25 x B1 6 80 B32d CLKOUT falling edge to BS valid as 13 30 18 00 11 30 16 00 9 40 14 10 7 60 12 30 ns requested by control bit BST1 in the corresponding word in the UPM EBDF 1 MAX 0 375 x B1 6 60 B33 CLKOUT falling edge to GPL valid as 1 50 6 00 1 50 6 00 1 50 6 00 1 50 6 00 ns requested by control bit GxT4 in the corresponding word in the UPM MAX 0 00 x B1 6 00 B33a CLKOUT rising edge to GPL valid 7 60 14 30 6 30 13 00 5 00 11 80 3 80 10 50 ns requested by control bit GxT3 in the corresponding word in the UPM MAX 0 25 x B1 6 80 B34 A 0 31 BADDR 28 30 and D 0 31 5 60 4 30 3 00 1 80 ns to CS valid as requested by control bit CST4 in th
36. the voltage sequencing the circuit shown in Figure 4 can be added to meet these requirements The MUR420 Schottky diodes control the maximum potential difference between the external bus and core power supplies on powerup and the 1N5820 diodes regulate the maximum potential difference on powerdown VDDH VDDL MUR420 Figure 4 Example Voltage Sequencing Circuit 9 Layout Practices Each Vpp pin on the MPC866 859 should be provided with a low impedance path to the board s supply Furthermore each GND pin should be provided with a low impedance path to ground The power supply pins drive distinct groups of logic on chip The Vpp power supply should be bypassed to ground using at least four 0 1 uF bypass capacitors located as close as possible to the four sides of the package Each board designed should be characterized and additional appropriate decoupling capacitors should be used if required The capacitor leads and associated printed circuit traces connecting to chip Vpp and GND should be kept to less than 1 2 per capacitor lead At a minimum a four layer board employing two inner layers as Vpp and GND planes should be used All output pins on the MPC866 859 have fast rise and fall times Printed circuit PC trace interconnection length should be minimized in order to minimize undershoot and reflections caused by these fast output switching times MPC866 MPC859 Hardware Specifications Rev 2 Freescale Sem
37. timers Four 16 bit timers cascadable to be two 32 bit timers Gate mode can enable disable counting Interrupt can be masked on reference match and event capture Fast Ethernet controller FEC Simultaneous MII 10 100Base T and UTOPIA operation when using the UTOPIA multiplexed bus e System integration unit SIU Bus monitor Software watchdog Periodic interrupt timer PIT Low power stop mode Clock synthesizer Decrementer and time base from the PowerPC architecture Reset controller TEEE 1149 1 test access port JTAG MPC866 MPC859 Hardware Specifications Rev 2 Freescale Semiconductor 3 Features e Interrupts Seven external interrupt request IRQ lines Twelve port pins with interrupt capability The MPC866P and MPC866T have 23 internal interrupt sources the MPC859P MPCS59T and MPCS59DSL have 20 internal interrupt sources Programmable priority between SCCs MPC866P and MPC866T Programmable highest priority request e Communications processor module CPM RISC controller Communication specific commands for example GRACEFUL STOP TRANSMIT ENTER HUNT MODE and RESTART TRANSMIT Supports continuous mode transmission and reception on all serial channels Up to 8 Kbytes of dual port RAM MPCS66P and MPC866T have 16 serial DMA SDMA channels MPCS59P MPC859T and MPC859DSL have 10 serial DMA SDMA channels Three parallel I O registers with open drain capability e Four baud rate generators
38. to WE 0 3 negated GPCM write access CSNT 0 MAX 0 00 x B1 9 00 9 00 9 00 9 00 9 00 ns B28a CLKOUT falling edge to WE 0 3 negated GPCM write access TRLX 0 1 CSNT 1 EBDF 0 MAX 0 25 x B1 6 80 7 60 14 30 6 30 13 00 5 00 11 80 3 80 10 50 ns B28b CLKOUT falling edge to CS negated GPCM write access TRLX 0 1 CSNT 1 ACS 10 or ACS 11 EBDF 0 MAX 0 25 x B1 6 80 14 30 13 00 11 80 10 50 ns B28c CLKOUT falling edge to WE 0 3 negated GPCM write access TRLX 0 CSNT 1 write access TRLX 0 1 CSNT 1 EBDF 1 MAX 0 375 x B1 6 6 10 90 18 00 10 90 18 00 7 00 14 30 5 20 12 30 ns MPC866 MPC859 Hardware Specifications Rev 2 Freescale Semiconductor 19 Bus Signal Timing Table 9 Bus Operation Timings continued Num Characteristic 33 MHz 40 MHz 50 MHz 66 MHz Min Max Min Max Min Max Min Max Unit B28d CLKOUT falling edge to CS negated GPCM write access TRLX 0 1 CSNT 1 ACS 10 or ACS 11 EBDF 1 MAX 0 375 x B1 6 6 18 00 18 00 14 30 12 30 ns B29 WE 0 3 negated to D 0 31 DP 0 3 High Z GPCM write access CSNT 0 EBDF 0 MIN 0 25 x B1 2 00 5 60 4 30 3 00 1 80 ns B29a WE 0 3 negated to D 0 31 DP 0 3 High Z GPCM write access TRLX
39. 2 66 Freescale Semiconductor CPM Electrical Characteristics 12 10SPI Master AC Electrical Specifications Table 26 shovvs the SPI master timings as shovvn in Figure 67 and Figure 68 Table 26 SPI Master Timing All Frequencies Num Characteristic Unit Min Max 160 MASTER cycle time 4 1024 toye 161 MASTER clock SCK high or low time 2 512 toye 162 MASTER data setup time inputs 15 ns 163 Master data hold time inputs 0 ns 164 Master data valid after SCK edge 10 ns 165 Master data hold time outputs 0 ns 166 Rise time output 15 ns 167 Fall time output 15 ns SPICLK Cl 0 Output SPICLK Cl 1 Output SPIMISO Input SPIMOSI Output Figure 67 SPI Master CP 0 Timing Diagram MPC866 MPC859 Hardware Specifications Rev 2 Freescale Semiconductor 67 CPM Electrical Characteristics SPICLK 1 0 Output SPICLK Cl 1 Output SPIMISO Input SPIMOSI Output Figure 68 SPI Master CP 1 Timing Diagram 12 11SPI Slave AC Electrical Specifications Table 27 shows the SPI slave timings as shown in Figure 69 and Figure 70 Table 27 SPI Slave Timing All Frequencies Num Characteristic Unit Min Max 170 Slave cycle time 2 teyc 171 Slave enable lead time 15 ns 172 Slave enable lag time 15 m ns 173 Slave clock SPICLK
40. 5 1 Pin Assignments w v U R P N M L J H G 3 F E BB URST M_COL IRQ2 1 1 7 RQ O TS 2 Bi VDDL O IRQ4 D24 N C VSSSYN1 O O O O O O O O 4 O OO 41 D26 N C VSSSYN O N C VDDSYN SRESET XTAL Q Q OP1 MODCK1 IPB2 ALEB B BG TA GPLA4 O O O QOS5BV OBRIO O O O VDDL M_MDIO TDI DPO IPA2 IPA7 O AS 6 CS2 GPLA5 BD P TEA 50 2 CLKOUT IPA3 IPA4 IPA1 VDDL RSTCONF OPO IPB5 1 1 BR CS4 CE2A CS1 HRESET TEXP EXTCLK EXTAL CS3 O ORS T H T E E E lLLO O O MODCK2 BADDR28 BADDR29 VDDL BADDR30 IPB6 ALEA D29 DP1 IPAS VDDH WaT B WAM PORESET VDDL o GND 0 O ORMO O O00000 O ORJ 2 D7 IPA6 IPAO D28 D30 GND D20 D21 D25 VDDL D5 O O O O U 0O 0 O 0O 0 O 11 18 BSAO GPLAO N C CS6 A31 VDDL BSA2 WET WES D18 D19 D22 A22 TSIZO BSA3 M_CRS VVE2 GPLA2 CS5 CETA WR GPLB4 A26 TSIZ1 BSA1 VVEO GPLA1 GPLA3 CS7 D3 D14 D16 D15 O O O O 0O QO O O O oo OD 0 4 oe Go D2 D10 D11 D9 A19 A24 A23 A30 O O O Os O O D1 D27 D23 D17 D31 6e 0 0000000 0O H GND N C A15 A16 A20 A17 A21 A27 A29 15 50 VDDH D8 O N C A12 A13 A14 PD5 IRQ1 PD7 D12 VDDH OO O 0O O 0 OG OO Q 206 A8 A9 A10 A11 PD4 PC7 TCK O O O ORS T
41. 5 shovv the timing for the external bus read controlled by various GPCM factors CSx VVE 0 3 D 0 31 10 3 Figure 12 External Bus Read Timing GPCM Controlled ACS 00 MPC866 MPC859 Hardware Specifications Rev 2 28 Freescale Semiconductor Bus Signal Timing A 0 31 CSx 010 311 10 3 Figure 13 External Bus Read Timing GPCM Controlled TRLX 0 or 1 5 10 TS eo me gt c B 2b 5 x CSx D 0 31 DP 0 3 Figure 14 External Bus Read Timing GPCM Controlled TRLX 0 or 1 ACS 11 MPC866 MPC859 Hardware Specifications Rev 2 Freescale Semiconductor 29 Bus Signal Timing CLKOUT A 0 31 CSx 010 311 10 3 B19 Figure 15 External Bus Read Timing GPCM Controlled TRLX 0 or 1 ACS 10 ACS 11 MPC866 MPC859 Hardware Specifications Rev 2 30 Freescale Semiconductor Bus Signal Timing Figure 16 through Figure 18 shovv the timing for the external bus vvrite controlled by various GPCM factors A 0 31 CSx D 0 31 2 Figure 16 External Bus VVrite Timing GPCM Controlled TRLX 0 or 1 CSNT 0 MPC866 MPC859 Hardware Specifications Rev 2 Freescale Semiconductor 31 Bus Signal Timing 010 311 10 3
42. 50 9 30 2 50 9 80 ns B12 CLKOUT to TS BB negation MAX 0 25 x B1 4 8 7 60 12 30 6 30 11 00 5 00 9 80 3 80 8 50 ns MPC866 MPC859 Hardware Specifications Rev 2 Freescale Semiconductor 17 Bus Signal Timing Table 9 Bus Operation Timings continued 33 MHz 40 MHz 50 MHz 66 MHz Num Characteristic Unit Min Max Min Max Min Max Min Max B12a CLKOUT to TA BI negation when 2 50 9 00 2 50 9 00 2 50 9 00 2 50 9 00 ns driven by the memory controller or PCMCIA interface MAX 0 00 x B1 9 00 B13 CLKOUT to TS BB High Z MIN 0 25 7 60 21 60 6 30 20 30 5 00 19 00 3 80 14 00 ns x B1 B13a CLKOUT to TA BI High Z when driven 2 50 15 00 2 50 15 00 2 50 15 00 2 50 15 00 ns by the memory controller or PCMCIA interface MIN 0 00 x B1 2 5 B14 CLKOUT to TEA assertion MAX 2 50 9 00 2 50 9 00 2 50 9 00 2 50 9 00 ns 0 00 x B1 9 00 B15 CLKOUT to TEA High Z MIN 0 00 2 50 15 00 2 50 15 00 2 50 15 00 2 50 15 00 ns B1 2 50 B16 TA BI valid to CLKOUT setup time 6 00 6 00 6 00 6 00 ns MIN 0 00 x B1 6 00 16 TEA KR RETRY CRvalidtoCLKOUT 4 50 450 4501 450 ns setup time MIN 0 00 x B1 4 5 B16b BB BG BR valid to CLKOUT setup 4 00
43. 80 support asia freescale com For Literature Requests Only Freescale Semiconductor Literature Distribution Center P O Box 5405 Denver Colorado 80217 800 441 2447 303 675 2140 Fax 303 675 2150 LDCForFreescaleSemiconductor hibbertgroup com MPC866EC Rev 2 2 2006 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters which may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its pa
44. CLKOUT to OPx valid MAX 0 00 x B1 19 00 19 00 19 00 19 00 ns P57 19 00 P58 HRESET negated to OPx drive MIN 25 70 121701 18 00 14 40 ns 0 75 x B1 3 00 P59 IP_Xx valid to CLKOUT rising edge MIN 5 00 5 00 5 00 5 00 ns 0 00 x B1 5 00 P60 CLKOUT rising edge to IP_Xx invalid 1 00 1 00 1 00 1 00 ns MIN 0 00 x B1 1 00 1 OP2 and OP3 only Figure 30 shows the PCMCIA output port timing for the MPC866 859 CLKOUT Output Signals HRESET OP2 OP3 Figure 30 PCMCIA Output Port Timing Figure 31 shows the PCMCIA output port timing for the MPC866 859 CLKOUT Input Signals Figure 31 PCMCIA Input Port Timing MPC866 MPC859 Hardware Specifications Rev 2 42 Freescale Semiconductor Bus Signal Timing Table 13 shows the debug port timing for the MPC866 859 Table 13 Debug Port Timing All Frequencies Num Characteristic Unit Min Max D61 DSCK cycle time 3xT CLOCKOUT D62 DSCK clock pulse width 1 25XTCLOCKOUT D63 DSCK rise and fall times 0 00 3 00 ns D64 DSDI input data setup time 8 00 ns D65 DSDI data hold time 5 00 ns 66 1DSCK low to DSDO data valid 0 00 15 00 ns D67 1 DSCK low to DSDO invalid 0 00 2 00 ns Figure 32 shovvs the input timing for the debug port clock DSCK Figure 32 Debug
45. D i E 5 Figure 7 Synchronous Output Signals Timing MPC866 MPC859 Hardware Specifications Rev 2 Freescale Semiconductor 25 Bus Signal Timing Figure 8 shows the timing for the synchronous active pull up and open drain output signals CLKOUT A Y i i A b Y i TEA Figure 8 Synchronous Active Pull Up Resistor and Open Drain Output Signals Timing Figure 9 shows the timing for the synchronous input signals CLKOUT OO OSS N ANAS TEA KR RETRY CR Figure 9 Synchronous Input Signals Timing MPC866 MPC859 Hardware Specifications Rev 2 26 Freescale Semiconductor Bus Signal Timing Figure 10 shows normal case timing for input data It also applies to normal read accesses under the control of the UPM in the memory controller CLKOUT ee a a a ee B18 wi XA XX 10 3 Figure 10 Input Data Timing in Normal Case Figure 11 shows the timing for the input data controlled by the UPM for data beats where DLT3 1 in the UPM RAM vvords This is only the case vvhere data is latched on the falling edge of CLKOUT CLKOUT OO O S OJS uu 010 311 10 3 Figure 11 Input Data Timing when Controlled by UPM in the Memory Controller and DLT3 1 MPC866 MPC859 Hardware Specifications Rev 2 Freescale Semiconductor 27 Bus Signal Timing Figure 12 through Figure 1
46. Freescale Semiconductor Technical Data MPC866 MPC859 MPC866EC Rev 2 2 2006 Hardware Specifications This document contains detailed information on power considerations DC AC electrical characteristics and AC timing specifications for the MPC866 859 family refer to Table 1 for a list of devices The MPC866P is the superset device of the MPC866 859 family This document describes pertinent electrical and physical characteristics of the MPC8245 For functional characteristics of the processor refer to the MPC866 PowerQUICC Family Users Manual MPCS66UM D 1 Overview The MPC866 859 is a derivative of Freescale s MPC860 PowerQUICC family of devices It is a versatile single chip integrated microprocessor and peripheral combination that can be used in a variety of controller applications and communications and networking systems The MPC866 859 859DSL provides enhanced ATM functionality over that of other ATM enabled members of the MPC860 family Freescale Semiconductor Inc 2006 All rights reserved 00 U ee ee O OO 16 Contents iL WOVERVIEW ise lar 1 s HEALUTES s n Las co Yas m n 2 Maximum Tolerated Ratings 8 Thermal Characteristics 9 Power Dissipation 10 DC Characteristics 10 Thermal Calculation and Measurement 12 Power Supply and Po
47. II RX ER MII RX CLK The receiver functions correctly up to a maximum frequency of 25 MHz 1 There is no minimum frequency requirement In addition the processor clock frequency must exceed the MIT RX CLK frequency 1 Table 33 shows the timings for MII receive signal Table 33 MII Receive Signal Timing Num Characteristic Min Max Unit M1 MII_RXD 3 0 MIl_RX_DV MII_RX_ER toMil RX CLK setup 5 ns M2 MII_RX_CLK to MII_RXDJ 3 0 MII_RX_DV hold 5 ns M3 MII_RX_CLK pulse width high 35 65 period 4 1 pulse width low 3596 6576 MII_RX_CLK period Figure 74 shows the timings for MII receive signal MPC866 MPC859 Hardware Specifications Rev 2 74 Freescale Semiconductor FEC Electrical Characteristics M3 MIL RX CLK input M4 MIL 13 0 inputs MII_RX_DV MII_RX_ER M1 M2 Figure 74 MII Receive Signal Timing Diagram 14 2 Transmit Signal Timing MII TXDI3 01 TX EN Mil TX CLK The transmitter functions correctly up to a MII TX CLK maximum frequency of 25 MHz 1 There is no minimum frequency requirement In addition the processor clock frequency must exceed the MII_TX_CLK frequency 1 Table 34 shows information on the MII transmit signal timing Table 34 MII Transmit Signal Timing o e M5 MIL_TX_CLK to MII_TXD 3 0 MII_TX_EN MII
48. L1CLK edge L1RXD setup time 17 00 m ns 77 L1CLK edge to L1RXD invalid L1RXD hold time 13 00 ns 78 L1CLK edge to L1ST 1 4 valid 10 00 45 00 ns 78A 1 L18SYNC valid to L1ST 1 4 valid 10 00 45 00 ns 79 L1CLK edge to L1ST 1 4 invalid 10 00 45 00 ns 80 L1CLK edge to L1TXD valid 10 00 55 00 ns 80A L1TSYNC valid to L1TXD valid 4 10 00 55 00 ns 81 11 edge to L1TXD high impedance 0 00 42 00 ns 82 L1RCLK L1TCLK frequency DSC 1 16 00 or SYNCCLK 2 MHz 83 L1RCLK L1TCLK width low DSC 1 P 10 ns 83a LTRCLK L1TCLK width high DSC 1 P 10 ns 84 L1CLK edge to L1CLKO valid DSC 1 30 00 ns 85 L1RQ valid before falling edge of L1TSYNC 1 00 LITCLK 86 L1GR setup time 42 00 ns 87 L1GR hold time 42 00 ns 88 L1CLK edge to L1SYNC valid FSD 00 CNT 0 00 ns 0000 BYT 0 DSC 0 A O m The ratio SyncCLK L1RCLK must be greater than 2 5 1 These specs are valid for IDL mode only Where P 1 CLKOUT Thus for a 25 MHz CLKOT rate P 40 ns These strobes and TxD on the first bit of the frame become valid after L1CLK edge or L1SYNC whichever is later MPC866 MPC859 Hardware Specifications Rev 2 Freescale Semiconductor 55 CPM Electrical Characteristics LTRCLK FE 0 CE 0 Input LIRCLK FE 1 CE 1 Input LIRSYNC Input L1RXD Input L1ST 4 1 Output 0 lt XXX Q Figure 53 SI Receive Timing Diagram with
49. Normal Clocking DSC 0 MPC866 MPC859 Hardware Specifications Rev 2 56 Freescale Semiconductor CPM Electrical Characteristics 5 LIRCLK FE 1 CE 1 Input LIRCLK FE 0 CE 0 Input LIRSYNC Input L1RXD Input L1ST 4 1 Output L1CLKO Output Figure 54 SI Receive Timing with Double Speed Clocking DSC 1 MPC866 MPC859 Hardware Specifications Rev 2 Freescale Semiconductor 57 CPM Electrical Characteristics LITCLK FE 0 CE 0 Input LITCLK FE 1 CE 1 Input LITSYNC Input L1TXD Output L1ST 4 1 Output y Figure 55 SI Transmit Timing Diagram DSC 0 MPC866 MPC859 Hardware Specifications Rev 2 58 Freescale Semiconductor CPM Electrical Characteristics LiRCLK FE 0 CE 0 2 Input LIRCLK FE 1 CE 1 Input LIRSYNC Input L1TXD Output L1ST 4 1 Output L1CLKO Output Figure 56 SI Transmit Timing with Double Speed Clocking DSC 1 MPC866 MPC859 Hardware Specifications Rev 2 Freescale Semiconductor 59 CPM Electrical Characteristics ndur 4947 ndino OH31 ndino 1 1517 ndur axy ndino ax indu ONASHIT YTOH11 Figure 57 IDL Timing MPC866 MPC859 Hardware Specifications Rev 2
50. Port Clock Input Timing Figure 33 shows the timing for the debug port DSCK DSDI Figure 33 Debug Port Timings MPC866 MPC859 Hardware Specifications Rev 2 Freescale Semiconductor 43 Bus Signal Timing Table 14 shovvs the reset timing for the MPC866 859 Table 14 Reset Timing 33 MHz 40 MHz 50 MHz 66 MHz Num Characteristic Unit Min Max Min Min Max Min Max R69 CLKOUT to HRESET high impedance 20 00 20 00 20 00 20 00 ns MAX 0 00 x B1 20 00 R70 CLKOUT to SRESET high impedance 20 00 20 00 20 00 20 00 ns MAX 0 00 x B1 20 00 R71 RSTCONF pulse width MIN 17 00 x 1515 20 425 00 340 00 257 60 ns B1 R72 Configuration data to HRESET rising 504 50 1 425 00 350 00 277 30 ns R73 edge setup time MIN 15 00 x B1 50 00 Configuration data to RSTCONF rising 350 00 350 00 350 00 350 00 ns R74 edge setup time MIN 0 00 x B1 350 00 Configuration data hold time after 0 00 0 00 1 0 00 1 0 00 1 ns R75 RSTCONF negation MIN 0 00 x B1 0 00 Configuration data hold time after 0 00 0 00 1 0 00 1 0 00 1 ns R76 HRESET negation MIN 0 00 x B1 0 00 HRESET and RSTCONF asserted to 25 00 25 00 25 00
51. S 204 1High period of SCL 4 0 us 205 Start condition setup time 4 7 us 206 1 Start condition hold time 4 0 us 207 1TData hold time 0 HS 208 Data setup time 250 ns 209 1 SDL SCL rise time 1 us 210 SDL SCL fall time 300 ns 211 Stop condition setup time 4 7 us 1 SCL frequency is given by SCL BRGCLK_frequency BRG register 3 pre_scaler 2 The ratio SyncClk BRGCLK pre_scaler must be greater or equal to 4 1 Table 29 shows the I C SCL gt 100 kHz timings Table 29 I C Timing SCL gt 100 kHz All Frequencies Num Characteristic Expression Unit Min Max 200 SCL clock frequency slave fSCL 0 BRGCLK 48 Hz 200 SCL clock frequency master fSCL BRGCLK 16512 BRGCLK 48 Hz 202 1 Bus free time between transmissions 1 2 2 fSCL 5 203 1Lovv period of SCL 1 2 2 fSCL 5 204 High period of SCL 1 2 2 fSCL s 205 1 Start condition setup time 1 2 2 fSCL s 206 1 Start condition hold time 1 2 2 fSCL 5 207 1 Data hold time 0 5 208 1Data setup time 1 40 fSCL 5 209 1 SDL SCL rise time 1 10 fSCL s 210 SDL SCL fall time 1 33 fSCL 5 211 Stop condition setup time 1 2 2 2 fSCL 5 The ratio SyncClk Brg_Clk pre_scaler must be greater or equal to 4 1 MPC866 MPC859 Hardware Specifications Rev 2 SCL frequency is given by SCL BrgClk_frequency BRG register 3 pre_scale
52. SDI Three state ATO IP_B7 H1 Bidirectional PTR Three state AT3 OPO L4 Bidirectional MII TXDO UtpCik Split OP1 L2 Output OP2 L1 Bidirectional MODCK1 STS MPC866 MPC859 Hardware Specifications Rev 2 84 Freescale Semiconductor Mechanical Data and Ordering Information Table 39 Pin Assignments continued Name Pin Number Type OP3 M4 Bidirectional MODCK2 DSDO BADDR30 K4 Output REG BADDR 28 29 M3 M2 Output AS L3 Input PA15 C18 Bidirectional RXD1 RXD4 PA14 D17 Bidirectional TXD1 Optional Open drain TXD4 PA13 E17 Bidirectional RXD2 PA12 F17 Bidirectional TXD2 Optional Open drain PA11 G16 Bidirectional L1TXDB Optional Open drain RXD3 PA10 J17 Bidirectional L1RXDB Optional Open drain TXD3 PA9 K18 Bidirectional LITXDA Optional Open drain RXD4 PA8 L17 Bidirectional L1RXDA Optional Open drain TXD4 PA7 M19 Bidirectional CLK1 L1RCLKA BRGO1 TIN1 PA6 M17 Bidirectional CLK2 TOUT1 MPC866 MPC859 Hardware Specifications Rev 2 Freescale Semiconductor 85 Mechanical Data and Ordering Information Table 39 Pin Assignments continued Name Pin Number Type PA5 N18 Bidirectional CLK3 LTTCLKA BRGO2 TIN2 PA4 P19 Bidirectional CLK4 TOUT2 PA3 P17 Bidirectional CLK5 BRGO3 TINS PA2 R18 Bidirectional CLK6 TOUT3 L1RCLKB PA1 T19 Bidirectional CLK7 BRGO4 TIN4 PAO
53. VDDSYN 1 1 7 1 9 V Difference betvveen 100 mv VDDL to VDDSYN nput high voltage all inputs except EXTAL and VIH 2 0 3 465 V EXTCLK 2 MPC866 MPC859 Hardware Specifications Rev 2 Freescale Semiconductor DC Characteristics Table 6 DC Electrical Specifications continued Characteristic Symbol Min Max Unit nput lovv voltage VIL GND 0 8 V EXTAL EXTCLK input high voltage VIHC 0 7 VDDH 1 VDDH nput leakage current Vin 5 5V except TMS TRST lin 100 HA DSCK and DSDI pins for 5 Volts Tolerant Pins 2 Input leakage current Vin except TMS TRST lin 10 HA DSCK and DSD nput leakage current Vin 0 V except TMS TRST lin m 10 HA DSCK and DSD pins Input capacitance 3 Cin 20 pF Output high voltage IOH 2 0 mA VOH 2 4 except XTAL and Open drain pins Output low voltage VOL 0 5 IOL 2 0 mA CLKOUT IOL 3 2 mA IOL 5 3 mA5 IOL 7 0 mA TXD1 PA14 TXD2 PA12 IOL 8 9 mA TS TA TEA B BB HRESET SRESET 1 The difference between VDDL and VDDSYN can not be more than 100 m V 2 The signals PA 0 15 PB 14 31 PC 4 15 PD 3 15 TDI TDO TCK TRST_B TMS MII_TXEN MII_MDIO are 5 V tolerant Input capacitance is periodically sampled 4 A 0 31 TSIZO REG TSIZ1 D 0 31 DP 0 3 IRQ 3 6 RD WR BURST RSV IRQ2 IP_B 0 1 IWP 0 1 VFLS 0 1 IP 2 1516
54. _TX_ER 5 ns invalid RA MII TXD 3 0 MII_TX_EN 4 25 valid MIl_TX_CLK pulse width high 65 MIl_TX_CLK period MIl_TX_CLK pulse width low 65 MIl_TX_CLK period MPC866 MPC859 Hardware Specifications Rev 2 75 Freescale Semiconductor FEC Electrical Characteristics Figure 75 shows the MH transmit signal timing diagram M7 1 input 5 MIl_TXD 3 0 outputs MII_TX_EN MII_TX_ER M M8 6 Figure 75 MII Transmit Signal Timing Diagram 14 3 MII Async Inputs Signal Timing MII CRS MII COL Table 35 shows the timing for on the MII async inputs signal Table 35 MII Async Inputs Signal Timing Num Characteristic Min Max Unit M9 MII_CRS MII_COL minimum pulse width 1 5 MII CLK period Figure 76 shows the MII asynchronous inputs signal timing diagram 5 MII_COL lt M9 Figure 76 MII Async Inputs Timing Diagram 14 4 MII Serial Management Channel Timing MII MDIO Table 36 shows the timing for the MII serial management channel signal The FEC functions correctly with a maximum MDC frequency in excess of 2 5 MHz The exact upper bound is under investigation Table 36 MII Serial Management Channel Timing 2555 M10 MDC falling edge to MII_MDIO output invalid minimum ns propagation delay MDC falling edge to 1 output valid maximum 25
55. ale Semiconductor 35 Bus Signal Timing Figure 22 shows the timing for the synchronous external master access controlled by the GPCM CLKOUT Al0 31 _TSIZ 0 1 R W BURST CSx koa B40 o Figure 22 Synchronous External Master Access Timing GPCM Handled ACS 00 MPC866 MPC859 Hardware Specifications Rev 2 36 Freescale Semiconductor Bus Signal Timing Figure 23 shovvs the timing for the asynchronous external master memory access controlled by the GPCM B40 A 0 31 TSIZ 0 1 RW CSx Figure 23 Asynchronous External Master Memory Access Timing GPCM Controlled ACS 00 Figure 24 shovvs the timing for the asynchronous external master control signals negation AS CSx WE 0 3 OE GPLx 510 3 Figure 24 Asynchronous External Master Control Signals Negation Timing Table 10 shovvs the interrupt timing for the MPC866 859 Table 10 Interrupt Timing All Frequencies Num Characteristic 1 Unit Min Max 139 IRQx valid to CLKOUT rising edge setup time 6 00 ns 140 RQx hold time after CLKOUT 2 00 ns 141 IRQx pulse width low 3 00 ns 142 IRQx pulse width high 3 00 ns 143 IRQx edge to edge time 4xToLockour The timings 139 and 140 describe the testing conditions under which the IRQ lines are tested when being defined as level sensitive The IRQ lines are synchronized internal
56. alling edge of CLKOUT This timing is valid only for read accesses controlled by chip selects under control of the UPM in the memory controller for data beats where DLT3 1 in the UPM RAM words This is only the case where data is latched on the falling edge of CLKOUT The timing B30 refers to CS when ACS 00 and to WE 0 3 when CSNT 0 N MPC866 MPC859 Hardware Specifications Rev 2 Freescale Semiconductor 23 Bus Signal Timing 8 The signal UPWAIT is considered asynchronous to CLKOUT and synchronized internally The timings specified in B37 and B38 are specified to enable the freeze of the UPM output signals as described in Figure 20 9 The AS signal is considered asynchronous to CLKOUT The timing B39 is specified in order to allow the behavior specified in Figure 23 Figure 5 shows the control timing diagram CLKOUT Outputs Outputs Inputs Inputs a Maximum output delay specification 8 Minimum output hold time Minimum input setup time specification Minimum input hold time specification Figure 5 Control Timing MPC866 MPC859 Hardware Specifications Rev 2 24 Freescale Semiconductor Bus Signal Timing Figure 6 shovvs the timing for the external clock CLKOUT Figure 6 External Clock Timing Figure 7 shows the timing for the synchronous output signals CLKOUT Output Signals Output Signals Output Signals 8 FE A Ww co
57. bit internal bus MPC8xx core system integration unit SIU and communication processor module CPM The MPCS66P block diagram is shown in Figure 1 The MPC859P 859T 859DSL block diagram is shown in Figure 2 Instruction 16 Kbyte System Interface Unit SIU Bus Instruction Cache Instruction MMU a Memory Controller 32 Entry ITLB Internal External Bus Interface Bus Interface Processor Core Load Store 8 Kbyte Bus Data Cache Data MMU 32 Entry DTLB Unit Unit System Functions PCMCIA ATA Interface Fast Ethernet Controller 4 Interrupt 16 Virtual Timers Controllers Dual Port RAM Serial and Parallel I O 10 100 4 Baud Rate Base T 32 Bit RISC Controller 2 Media Access Generatore and Program Independent Control Parallel Interface Port Ti ROM DMA and UTOPIA mers Channels 1114 t p g od y y scci scc2 soca scca smci smc2 sei Pc Time Slot Assigner Serial Interface Figure 1 MPC866P Block Diagram MPC866 MPC859 Hardware Specifications Rev 2 6 Freescale Semiconductor Instruction 4 Kbyte Bus nstruction Cache Instruction MMU Embedded 2 MPC8xx 32 Entry ITLB a Processor Core Load Store 4 Kbyte t Bus Data Cache gt Data MMU 32 Entry DTLB Fast Ethernet Controller Parallel I
58. d or non multiplexed operation Supports T1 CEPT PCM highway ISDN basic rate ISDN primary rate user defined 1 or 8 bit resolution Allows independent transmit and receive routing frame synchronization and clocking Allows dynamic changes On MPC866P and MPC866T can be internally connected to six serial channels four SCCs and two SMCs on MPC859P and MPC859T can be connected to three serial channels one SCC and two SMCs e Parallel interface port PIP Centronics interface support Supports fast connection between compatible ports on MPC866 859 or MC68360 e PCMCIA interface Master socket interface compliant with PCI Local Bus Specification Rev 2 1 Supports one or two PCMCIA sockets whether ESAR functionality is enabled Eight memory or I O windows supported e Debug interface Eight comparators four operate on instruction address two operate on data address and two operate on data Supports conditions z lt gt Each watchpoint can generate a breakpoint internally e Normal high and normal low power modes to conserve power 1 8 V core and 3 3 V VO operation with 5 V TTL compatibility refer to Table 6 for a listing of the 5 V tolerant pins e 357 pin plastic ball grid array PBGA package e Operation up to 133 MHz MPC866 MPC859 Hardware Specifications Rev 2 Freescale Semiconductor 5 Features The MPC866 859 is comprised of three modules that each use a 32
59. e 38 MPC866 859 Package Frequency Orderable Package Type Temperature Tj Frequency MHz Order Number Plastic ball grid array 0 to 95 C 50 MPC859DSLZP50A ZP suffix Non lead free 66 MPC859DSLZP66A 100 MPC859PZP100A MPC859TZP100A MPC866PZP100A MPC866TZP100A 133 MPC859PZP133A MPC859TZP133A MPC866PZP133A MPC866TZP133A Plastic ball grid array 40 to 100 C 50 MPC859DSLCZP50A CZP suffix Non lead free 66 MPC859DSLCZP66A 100 MPC859PCZP100A MPC859TCZP100A MPC866PCZP100A MPC866TCZP100A MPC866 MPC859 Hardware Specifications Rev 2 78 Freescale Semiconductor Mechanical Data and Ordering Information Table 38 MPC866 859 Package Frequency Orderable continued Plastic ball grid array 0 to 95 C 50 MPC859DSLVR50A VR suffix Lead free 66 MPC859DSLVR66A 100 MPC859PVR100A MPC859TVR100A MPC866PVR100A MPC866TVR100A 133 MPC859PVR133A MPC859TVR133A MPC866PVR133A MPC866TVR133A Plastic ball grid array 40 to 100 C 50 MPC859DSLCVR50A CVR suffix Lead free 66 MPC859DSLCVR66A 100 MPC859PCVR100A MPC859TCVR100A MPC866PCVR100A MPC866TCVR100A MPC866 MPC859 Hardware Specifications Rev 2 Freescale Semiconductor 79 Figure 78 shows the top view pinout of the PBGA package For additional information see the MPC866 NOTE This is the top vievv of the device Mechanical Data and Ordering Information PowerQUICC Family User 5 Manual 1
60. e corresponding word in the UPM MIN 0 25 x B1 2 00 B34a A 0 31 BADDR 28 30 and D 0 31 13 20 10 50 1 8 00 5 60 ns to CS valid as requested by control bit CST1 in the corresponding word in the UPM MIN 0 50 x B1 2 00 B34b A 0 31 BADDR 28 30 and D 0 31 20 70 16 701 13 00 9 40 ns to CS valid as requested by CST2 in the corresponding word in UPM MIN 0 75 x B1 2 00 MPC866 MPC859 Hardware Specifications Rev 2 22 Freescale Semiconductor Bus Signal Timing Table 9 Bus Operation Timings continued 33 MHz 40 MHz 50 MHz 66 MHz Num Characteristic Unit Min Max Min Max Min Max Min Max B35 A 0 31 BADDR 28 30 to CS valid as 5 60 4 30 3 00 1 80 ns requested by control bit BST4 in the corresponding vvord in the UPM MIN 0 25 x B1 2 00 B35a A 0 31 BADDR 28 30 and D 0 31 13 20 110501 8 00 5 60 ns to BS valid as Requested by BST1 in the corresponding word in the UPM MIN 0 50 x B1 2 00 B35b A 0 31 BADDR 28 30 and D 0 31 20 70 16 70 13 00 9 40 ns to BS valid as requested by control bit BST2 in the corresponding vvord in the UPM MIN 0 75 x B1 2 00 B36 A 0 31 BADDR 28 30 and D 0 31 5 60 4 30 3 00 1 80 ns to GPL valid as requested by control bit GxT4 in the corresponding word in t
61. g Debug Port Configuration 11 IEEE 1149 1 Electrical Specifications Table 15 shows the JTAG timings for the MPC866 859 shown in Figure 37 through Figure 40 Table 15 JTAG Timing All Frequencies Num Characteristic Unit Min Max J82 TCK cycle time 100 00 ns J83 TCK clock pulse width measured at 1 5 V 40 00 ns J84 TCK rise and fall times 0 00 10 00 ns J85 TMS TDI data setup time 5 00 ns J86 TMS TDI data hold time 25 00 ns J87 TCK low to TDO data valid 27 00 ns J88 TCK low to TDO data invalid 0 00 ns J89 TCK low to TDO high impedance 20 00 ns 490 TRST assert time 100 00 ns J91 TRST setup time to TCK low 40 00 ns J92 TCK falling edge to output valid 50 00 ns J93 TCK falling edge to output valid out of high impedance 50 00 ns J94 TCK falling edge to output high impedance 50 00 ns J95 Boundary scan input valid to TCK rising edge 50 00 ns J96 TCK rising edge to boundary scan input invalid 50 00 ns MPC866 MPC859 Hardware Specifications Rev 2 46 Freescale Semiconductor IEEE 1149 1 Electrical Specifications TCK Figure 37 JTAG Test Clock Input Timing TCK TMS TDI TDO Figure 38 JTAG Test Access Port Timing Diagram TCK 80 i J90 7 TRST Figure 39 JTAG TRST Timing Diagram MPC866 MPC859 Hardware Specifications Rev 2 Freescale Semiconductor 47 CPM Electrical Charac
62. he UPM MIN 0 25 x B1 2 00 B37 UPWAIT valid to CLKOUT falling 6 00 600 6 00 600 ns edge 2 MIN 0 00 x B1 6 00 B38 CLKOUT falling edge to UPWAIT 1 00 1 00 1 00 1 00 ns valid MIN 0 00 x B1 1 00 B39 AS valid to CLKOUT rising edge 3 MIN 7 00 7 00 7 00 7 00 ns 0 00 x B1 7 00 B40 A 0 31 TSIZ 0 1 BURST 7 00 7 00 700 7001 ns valid to CLKOUT rising edge MIN 0 00 x B1 7 00 B41 TS valid to CLKOUT rising edge setup 7 00 7 00 m 7 00 7 00 ns time MIN 0 00 x B1 7 00 B42 CLKOUT rising edge to TS valid hold 2 00 m 2 00 m 2 00 2 00 ns time MIN 0 00 x B1 2 00 B43 AS negation to memory controller m TBD TBD TBD TBD ns signals negation MAX TBD For part speeds above 50 MHz use 9 80 ns for B11a The timing required for BR input is relevant when the MPC866 859 is selected to work with the internal bus arbiter The timing for BG input is relevant when the MPC866 859 is selected to work with the external bus arbiter For part speeds above 50 MHz use 2 ns for B17 The D 0 31 and DP 0 3 input timings B18 and B19 refer to the rising edge of CLKOUT in which the TA input signal is asserted For part speeds above 50 MHz use 2 ns for B19 6 The D 0 31 and DP 0 3 input timings B20 and B21 refer to the f
63. iconductor 15 Bus Signal Timing This recommendation particularly applies to the address and data buses Maximum PC trace lengths of 6 are recommended Capacitance calculations should consider all device loads as vvell as parasitic capacitances due to the PC traces Attention to proper PCB layout and bypassing becomes especially critical in systems with higher capacitive loads because these loads create higher transient currents in the Vpp and GND circuits Pull up all unused inputs or signals that will be inputs during reset Special care should be taken to minimize the noise levels on the PLL supply pins For more information please refer to Section 14 4 3 Clock Synthesizer Power VDDSYN VSSSYN VSSSYN1 in the MPC866 User 5 Manual 10 Bus Signal Timing The maximum bus speed supported by the MPC866 859 is 66 MHz Higher speed parts must be operated in half speed bus mode for example an MPC866 859 used at 100 MHz must be configured for a 50 MHz bus Table 7 and Table 8 show the frequency ranges for standard part frequencies Table 7 Frequency Ranges for Standard Part Frequencies 1 1 Bus Mode Part Freq 50 MHz 66 MHz Min Max Min Max Core 40 50 40 66 67 Bus 40 50 40 66 67 Table 8 Frequency Ranges for Standard Part Frequencies 2 1 Bus Mode Part 50 MHz 66 MHz 100 MHz 133 MHz Freq Min Max Min Max Min Max Min Max Core 40 50 40 66 67 40 100 40 133 34 Bus 20 25 20 33 33 20 50 20 66 67
64. lave Split Bus Mode Electrical Specifications Num Signal Characteristic Direction Min Max Unit U1 UtpClk rise fall time external clock option Input 4 ns Duty cycle 40 60 96 Frequency 33 MHz U2 UTPB SOC Rxclav and Txclav active delay Output 2 16 ns U3 UTPB_AUX SOC_Aux RxEnb TxEnb RxAddr and TxAddr Input 4 ns setup time U4 UTPB_AUX SOC_Aux RxEnb TxEnb RxAddr and TxAddr nput 1 ns hold time Figure 72 shows signal timings during UTOPIA receive operations Ok 0 UtpClk PHREQn kO A RxClav HighZ at MPHY HighZ at MPHY RxEnb Ppk UTPB SOC Figure 72 UTOPIA Receive Timing MPC866 MPC859 Hardware Specifications Rev 2 Freescale Semiconductor 73 FEC Electrical Characteristics Figure 73 shows signal timings during UTOPIA transmit operations UtpClk PHSELn O lt 0 TxClav HighZ at MPHY High Z at MPHY TxEnb rv 1 y UTPB SOC Figure 73 UTOPIA Transmit Ti 14 FEC Electrical Characteristics This section provides the AC electrical specifications for the fast Ethernet controller FEC Note that the timing specifications for the MII signals are independent of system clock frequency part speed designation Also MII signals use TTL signal levels compatible with devices operating at either 5 0 or 3 3 V ming 14 1 MII Receive Signal Timing MII RXD 3 0 MII RX DV M
65. lse Mode Timing Diagram MPC866 MPC859 Hardware Specifications Rev 2 Freescale Semiconductor 49 CPM Electrical Characteristics DATA OUT STBO Output STBI Input Figure 44 PIP TX Pulse Mode Timing Diagram CLKO DATA IN DATA OUT Figure 45 Parallel I O Data In Data Out Timing Diagram 12 2 Port C Interrupt AC Electrical Specifications Table 17 shows timings for port C interrupts Table 17 Port C Interrupt Timing 33 34 MHz Num Characteristic Unit Min Max 35 Port C interrupt pulse width low edge triggered mode 55 ns 36 1 Port C interrupt minimum time between active edges 55 ns Figure 46 shovvs the port C interrupt detection timing MPC866 MPC859 Hardware Specifications Rev 2 50 Freescale Semiconductor CPM Electrical Characteristics Port C Input Figure 46 Port C Interrupt Detection Timing 12 3 IDMA Controller AC Electrical Specifications Table 18 shows the IDMA controller timings as shown in Figure 47 through Figure 50 Table 18 IDMA Controller Timing All Frequencies Num Characteristic Unit Min Max 40 DREQ setup time to clock high 7 ns 41 DREQ hold time from clock high 3 ns 42 SDACK assertion delay from clock high 12 ns 43 SDACK negation delay from clock low 12 ns 44 SDACK negation delay from TA lovv m 20 ns 45 SDACK negation delay from clock high
66. ly and do not have to be asserted or negated with reference to the CLKOUT The timings 141 142 and 143 are specified to allow the correct function of the IRQ lines detection circuitry and has no direct relation with the total system interrupt latency that the MPC866 859 is able to support MPC866 MPC859 Hardware Specifications Rev 2 Freescale Semiconductor 37 Bus Signal Timing Figure 25 shovvs the interrupt detection timing for the external level sensitive lines CLKOUT RQx Figure 25 Interrupt Detection Timing for External Level Sensitive Lines Figure 26 shows the interrupt detection timing for the external edge sensitive lines CLKOUT Q 0 F amp F RQx Figure 26 Interrupt Detection Timing for External Edge Sensitive Lines Table 11 shows the PCMCIA timing for the MPC866 859 Table 11 PCMCIA Timing 33 MHz 40 MHz 50 MHz 66 MHz Num Characteristic Unit Min Max Min Max Min Max Min Max A 0 31 REG valid to PCMCIA 20 70 16 70 13 00 9 40 ns P44 Strobe asserted MIN 0 75 x B1 2 00 P45 A 0 31 REG valid to ALE 28 30 23 00 18 00 13 20 ns negation MIN 1 00 x B1 2 00 CLKOUT to REG valid MAX 0 25 7 60 15 60 6 30 14 30 5 00 13 00 3 80 11 80 ns P46 x B1 8 00 P47 CLKOUT to REG invalid MIN 8 60 7 30 6 00 4 80 ns 0 25 x B1 1 00 P48 CLKOUT to CE1 CE2 asserted 7 60 15
67. mal environment to affect the case to ambient thermal resistance Roca For instance the user can change the airflow around the device add a heat sink change the mounting arrangement on the printed circuit board or change the thermal dissipation on the printed circuit board surrounding the device This thermal model is most useful for ceramic packages with heat sinks where some 90 of the heat flows through the case and the heat sink to the ambient environment For most packages a better model is required 7 3 Estimation with Junction to Board Thermal Resistance A simple package thermal model that has demonstrated reasonable accuracy about 20 is a two resistor model consisting of a junction to board and a junction to case thermal resistance The junction to case covers the situation where a heat sink is used or where a substantial amount of heat is dissipated from the top of the package The junction to board thermal resistance describes the thermal performance when most of the heat is conducted to the printed circuit board It has been observed that the thermal performance of most plastic packages and especially PBGA packages is strongly dependent on the board temperature see Figure 3 MPC866 MPC859 Hardware Specifications Rev 2 12 Freescale Semiconductor Thermal Calculation and Measurement 100 25 90 28 lt gt 80 g ng 70 TE 5 8 60 2 50 ES 40 x 20 5 20 5 5 8 10 0 0 20 40 60 80 Board Temperture Rise Above
68. measurement of the temperature at the top center of the package case using the following equation where M r thermal characterization parameter Tr thermocouple temperature on top of package Pp power dissipation in package The thermal characterization parameter is measured per JESD51 2 specification published by JEDEC using a 40 gauge type T thermocouple epoxied to the top center of the package case The thermocouple should be positioned so that the thermocouple junction rests on the package A small amount of epoxy is placed over the thermocouple junction and over about mm of wire extending from the junction The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire 7 6 References Semiconductor Equipment and Materials International 415 964 5111 805 East Middlefield Rd Mountain View CA 94043 MIL SPEC and EIA JESD JEDEC specifications800 854 7179 or Available from Global Engineering Documents 303 397 7956 JEDEC Specifications http www jedec org 1 C E Triplett and B Joiner An Experimental Characterization of a 272 PBGA Within an Automotive Engine Controller Module Proceedings of SemiTherm San Diego 1998 pp 47 54 2 B Joiner and V Adams Measurement and Simulation of Junction to Board Thermal Resistance and Its Application in Thermal Modeling Proceedings of SemiTherm San Diego 1999 pp 212 220 MPC866 MPC859
69. ow that TRLX can be 0 or 1 e Added nontechnical reformatting 1 5 3 14 2005 Updated document template 2 2 10 2006 Updated orderable parts table MPC866 MPC859 Hardware Specifications Rev 2 Freescale Semiconductor 93 Document Revision History THIS PAGE INTENTIONALLY LEFT BLANK MPC866 MPC859 Hardware Specifications Rev 2 94 Freescale Semiconductor Document Revision History THIS PAGE INTENTIONALLY LEFT BLANK MPC866 MPC859 Hardware Specifications Rev 2 Freescale Semiconductor 95 How to Reach Us Home Page www freescale com email support freescale com USA Europe or Locations Not Listed Freescale Semiconductor Technical Information Center CH370 1300 N Alma School Road Chandler Arizona 85224 800 521 6274 480 768 2130 support freescale com Europe Middle East and Africa Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen Germany 44 1296 380 456 English 46 8 52200080 English 49 89 92103 559 German 33 1 69 35 48 48 French support efreescale com Japan Freescale Semiconductor Japan Ltd Technical Information Center 3 20 1 Minami Azabu Minato ku Tokyo 106 0047 Japan 0120 191014 81 3 3440 3569 support japan O freescale com Asia Pacific Freescale Semiconductor Hong Kong Ltd Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 800 2666 80
70. r 2 Freescale Semiconductor 71 UTOPIA AC Electrical Specifications Figure 71 shows the 12 bus timing Figure 71 IC Bus Timing Diagram 13 UTOPIA AC Electrical Specifications Table 30 through Table 32 show the AC electrical specifications for the UTOPIA interface Table 30 UTOPIA Master Muxed Mode Electrical Specifications Num Signal Characteristic Direction Min Max Unit U1 UtpClk rise fall time Internal clock option Output 4 ns Duty cycle 50 50 Frequency 33 MHz U2 1UTPB SOC RxEnb TxEnb RxAddr and TxAddr active Output 2 16 ns delay and PHREQ and PHSEL active delay in MPHY mode U3 UTPB SOC Rxclav and Txclav setup time Input 4 ns U4 UTPB SOC Rxclav and Txclav hold time Input 1 ns Table 31 UTOPIA Master Split Bus Mode Electrical Specifications Num Signal Characteristic Direction Min Max Unit U1 UtpClk rise fall time Internal clock option Output 4 ns Duty cycle 50 50 96 Frequency 33 MHz U2 1TUTPB SOC RxEnb TxEnb RxAddr and TxAddr active Output 2 16 ns delay PHREQ and PHSEL active delay in MPHY mode U3 UTPB_Aux SOC_Aux Rxclav and Txclav setup time Input 4 ns U4 UTPB_Aux SOC_Aux Rxclav and Txclav hold time Input 1 ns MPC866 MPC859 Hardware Specifications Rev 2 72 Freescale Semiconductor UTOPIA AC Electrical Specifications Table 32 UTOPIA S
71. rdware Specifications Rev 2 Freescale Semiconductor 89 Mechanical Data and Ordering Information Table 39 Pin Assignments continued Name Pin Number Type PD9 RXD4 MII TXDO UTPCLK V17 Bidirectional PD8 TXD4 MI MDC Mil RXCLK W17 Bidirectional PD7 RTS3 Mil RXERR UTPB4 T15 Bidirectional PD6 RTS4 Mil RXDV UTPB5 V16 Bidirectional PD5 REJECT2 6 15 Bidirectional PD4 MII TXD2 UTPB7 U16 Bidirectional PD3 REJECT4 MII TXD1 SOC VV16 Bidirectional TMS G18 nput TDI DSDI H17 nput TCK DSCK H16 nput TRST G19 nput TDO DSDO G17 Output 5 7 nput MILMDIO H18 Bidirectional MILTXEN V15 Output MPC866 MPC859 Hardware Specifications Rev 2 90 Freescale Semiconductor Mechanical Data and Ordering Information Table 39 Pin Assignments continued Name Pin Number Type MIL COL H4 nput VSSSYN1 V1 PLL analog VDD and GND VSSSYN U1 Povver VDDSYN T1 Povver GND F6 F7 F8 F9 F10 F11 F12 F13 F14 G6 G7 G8 G9 G10 Power G11 G12 G13 G14 H6 H7 H8 H9 H10 H11 H12 H13 H14 J6 J7 J8 J9 J10 J11 J12 J13 J14 K6 K7 K8 K9 K10 K11 K12 K13 K14 L6 L7 L8 L9 L10 L11 L12 L13 L14 M6 M7 M8 M9 M10 M11 M12 M13 M14 N6 N7
72. rms branch prediction with conditional prefetch without conditional execution 4 or 8 Kbyte data cache and 4 or 16 Kbyte instruction cache see Table 1 16 Kbyte instruction cache MPC866P and MPC859P is four way set associative with 256 sets 4 Kbyte instruction cache MPC866T MPC859T and MPC859DSL is two way set associative with 128 sets 8 Kbyte data cache MPC866P and MPC859P is two way set associative with 256 sets 4 Kbyte data cache MPC866T MPCS59T and MPC859DSL is two way set associative with 128 sets Cache coherency for both instruction and data caches is maintained on 128 bit 4 word cache blocks Caches are physically addressed implement a least recently used LRU replacement algorithm and are lockable on a cache block basis MMwUs with 32 entry TLB fully associative instruction and data TLBs MMwUs support multiple page sizes of 4 16 and 512 Kbytes and 8 Mbytes 16 virtual address spaces and 16 protection groups Advanced on chip emulation debug mode e The MPC866 859 provides enhanced ATM functionality over that of the MPCS60S AR The MPC866 859 adds major new features available in enhanced SAR ESAR mode including the following Improved operation administration and maintenance OAM support OAM performance monitoring PM support Multiple APC priority levels available to support a range of traffic pace requirements MPC866 MPC859 Hardware Specifications
73. sistance is a simulated value from the junction to the exposed pad without contact resistance Thermal characterization parameter indicating the temperature difference between package top and junction temperature per JEDEC JESD51 2 MPC866 MPC859 Hardware Specifications Rev 2 Freescale Semiconductor 9 Povver Dissipation 5 Power Dissipation Table 5 shows power dissipation information The modes are 1 1 where CPU and bus speeds are equal and 2 1 mode where CPU frequency is twice the bus speed Table 5 Power Dissipation Pp Die Revision Bus Mode CPU Typical Maximum Unit Frequency 0 1 1 50 MHz 110 140 mW 66 MHz 150 180 mW 2 1 66 MHz 140 160 mW 80 MHz 170 200 mW 100 MHz 210 250 mW 133 MHz 260 320 mW Typical power dissipation at VDDL and VDDSYN is at 1 8 V and is at 3 3 V 2 Maximum povver dissipation at VDDL and VDDSYN is at 1 9 V and VDDH is at 3 465 V NOTE Values in Table 5 represent VDDL based povver dissipation and do not include VO povver dissipation over VDDH VO povver dissipation varies widely by application due to buffer current depending on external circuitry The VDDSYN power dissipation is negligible 6 DC Characteristics Table 6 shows the DC electrical characteristics for the MPC866 859 Table 6 DC Electrical Specifications Characteristic Symbol Min Max Unit Operating voltage VDDL core 1 7 1 9 V VDDH I O 3 135 3 465 V
74. tent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc The described product contains a PowerPC processor core The PowerPC name is a trademark of IBM Corp and used under license All other product or service names are the property of their respective owners Freescale Semiconductor Inc 2006 z freescale semiconductor
75. teristics TCK 94 J94 2 Output Signals Output Signals 95 J95 a 96 2 Output Signals Figure 40 Boundary Scan JTAG Timing Diagram 12 CPM Electrical Characteristics This section provides the AC and DC electrical specifications for the communications processor module CPM of the MPC866 859 12 1 PIP PIO AC Electrical Specifications Table 16 shows the PIP PIO AC timings as shown in Figure 41 through Figure 45 Table 16 PIP PIO Timing All Frequencies Num Characteristic Unit Min Max 21 Data in setup time to STBI low 0 ns 22 1TData ln hold time to STBI high 25 13 clk 23 STBI pulse width 1 5 clk 24 STBO pulse width 1 clk 5ns ns 25 1 Data out setup time to STBO lovv 2 clk 26 Data out hold time from STBO high 5 clk 27 STBI low to STBO low Rx interlock 2 clk 28 STBI low to STBO high Tx interlock 2 clk 29 Data in setup time to clock high 15 ns 30 1TData in hold time from clock high 7 5 ns 31 Clock low to data out valid CPU writes data control or direction 25 ns 13 Specification 23 MPC866 MPC859 Hardware Specifications Rev 2 48 Freescale Semiconductor CPM Electrical Characteristics DATA IN STBO DATA OUT STBO Output STBI Input DATA IN STBI Input STBO Output Figure 43 PIP Rx Pu
76. torage temperature range Tstg 55 to 150 C 1 The power supply of the device must start its ramp from 0 0 V 2 Functional operating conditions are provided with the DC electrical specifications in Table 6 Absolute maximum ratings are stress ratings only functional operation at the maxima is not guaranteed Stress beyond those listed may affect device reliability or cause permanent damage to the device See page 15 Caution All inputs that tolerate 5 V cannot be more than 2 5 V greater than VDDH This restriction applies to power up and normal operation that is if the MPC866 859 is unpowered a voltage greater than 2 5 V must not be applied to its inputs Table 3 Operating Temperatures Rating Symbol Value Unit Temperature 1 standard Th min 0 eC Timax 95 C Temperature extended TA min 40 C Timax 100 C 1 Minimum temperatures are guaranteed as ambient temperature TA Maximum temperatures are guaranteed as junction temperature Tj This device contains circuitry protecting against damage due to high static voltage or electrical fields however it is advised that normal precautions be taken to avoid application of any voltages higher than maximum rated voltages to this high impedance circuit Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level for example either GND or Vpp MPC866 MPC859 Hardware Specifications Rev 2
77. wer Sequencing 15 Layout Practices 15 Bus Signal Timing 16 IEEE 1149 1 Electrical Specifications 46 CPM Electrical Characteristics 48 UTOPIA AC Electrical Specifications 72 FEC Electrical Characteristics 74 Mechanical Data and Ordering Information 78 Document Revision History 93 ey z freescale semiconductor Features Table 1 shows the functionality supported by the members of the MPC866 859 family 2 Features Table 1 MPC866 Family Functionality Cache Ethernet Part scc SMC Instruction Data 10T 10 100 MPC866P 16 Kbytes 8 Kbytes Up to 4 1 4 2 MPC866T 4 Kbytes 4 Kbytes Up to 4 1 4 2 MPC859P 16 Kbytes 8 Kbytes 1 1 1 2 MPC859T 4 Kbytes 4 Kbytes 1 1 1 2 MPC859DSL 4 Kbytes 4 Kbytes 1 1 11 1 MPC852T 3 4 KBytes 4 Kbytes 2 1 2 1 1 On the MPC859DSL the SCC SCC1 is for ethernet only Also the MPC859DSL does not support the Time Slot Assigner TSA 2 On the MPC859DSL the SMC SMCT is for UART only 3 For more details on the MPC852T please refer to the MPC852T Hardware Specifications The following list summarizes the key MPC866 859 features e Embedded single issue 32 bit PowerPC core implementing the PowerPC architecture with thirty two 32 bit general purpose registers GPRs The core perfo

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