PDF document - Eetasia.com
Contents
1. VY ADCU port ADCV port ADCW port ADCAUX port SYSSTAT 4DS200 input ports writes port RHO port PHIP1 VD port PHIP2 VQ PHIP3 port RHOP port PWMTM PWMTCHA_ PWMTCHB PWMTCHC PWMDT_ port PWMPD port SYSCTRL 1rotation registers ADC registers System status register rho for reverse PARK frotation input regs rho for forward PARK PWM master clock frequency PWM on time channel A PWM dead time PWM pulse deletion System control register READ WRITE 211 APPENDIX ADMC200 DSP MODULE ram abs 0 boot 0 a200ev20 REV 2 0 This is a general purpose test demo file for the ADMC200 EVAL board for use with the ADSP 21xx EZLAB or the ADM 21 EZLAB The program exercises the ADC PWM and PARK functions the ADM C200 ection 1 Program constants include lt admc200c h gt 4 C200 amp ADSP 2101 constants definitions file Program user constants expressed in SI units These are used to derive working program constants such as PWM period etc change these parameters to match your system CONST CLOCK 12 ADM C200 SYSTEM CLOCK counts per micro s CONST PWMFREQ kHz 15 PWM frequency kHz 1 5 25 kHz CONST DEADTIME_ns 4000 deadtime in ns CONST DELETION_ns 2000 pulse deletion in ns CONST PARK 2 80 PARK rotation frequency Hz Program2. 0x0100 ADC ch aux enable CONST DIV2_EN 0 0200 clock divide by 2 mode 5 PARK_INT_EN 0x0400 PARK int enable 5 INT EN 0 0800 ADC int enable CONST FOR_PARK_EN 0 4000 3 3 mode enable 4DMC200 SYSSTAT read constants used to confirm IRQ2 status CONST ADMC200 INT 0x8000 generated by ADM C200 CONST ADC INT 0x0010 ADC IRQB CONST PARK_INT 0x0020 PARK IRQB ADC Macro definition section This macro set the loadDAC bit in the hardware control register When this bit is set the data registers are latched directly into the DAC buffers macro SetLDAC ay1 LDAC ar dm HARDWARE_REGISTER ar ar OR 1 dm HARDWARE_REGISTER ar endmacro macro DAC ay1 LDAC ar dm HARDWARE_REGISTER ar ar AND 1 dm HARDWARE_REGISTER ar endmacro macro ResetDAC ayl DAC RESET ar dm HARDWARE REGISTER ar ar AND 1 dm HARDWARE_REGISTER ar NOP NOP NOP ayl DAC RESET arzdm HARDWARE REGISTER ar ar OR 1 dm HARDWARE REGISTER ar endmacro 10 APPENDIX D ADMC200P H This file defines the port addresses on the AD2S200 Demo card used with the EZLAB EZLAB DAC ports write dacO write dac1 port write dac2 write dac3 load_dac_ extem config 4025201 Demo ports AD2S200 reset 405200 output ports reads ID PHV1 IQ PHV2 IX PHV3
3. D If not bit 2 is checked for a PARK interrupt causing the program to read the PARK registers IRQ2 ISR ayO dm sysstat fread the ADM C 200 status dm sys_read ay0 Save the status for debugging ar ADMC200 INT AND 0 check for ADMC_200 interrupt IF eq jump FALSE_IRQ2 rror if false interrupt ar ADC INT ar AND 0 check for ADM C200 A D interrupt IF ne jump ADC input if ADC INT jump to ADC interrupt code ar PARK INT ar AND 0 check for ADMC 200 PARK interrupt IF ne jump PARK input if PARK INT jump to PARK interrupt code ferror handling code ar 0x3 Should not get here except on error call error_set ferror3 neither interrupt RTI FALSE IRQ2 0 2 call error_set ferror2 false IRQ2 RTI main loop starts by reading the A D converter registers All four ADC channels are read into the buffer but in this program only two channels are digitally filtered It should be noted here that the A D registers do not have to be read in any particular sequence ADC input ifndef ADMC21xx dm load dac Load the DAC at the start of each cycle ClearLDAC Set LDAC low for a minimum of 180ns nop nop nop nop SetLDAC Set LDAC high again endif axO TIMEOUT reload the TIMER counter if you get here dm TCOUNT ax0 normal operation TCOUNT never reaches 0 This section of code reads the ADC2 and ADC3 values into a buffer filters the buffer
4. config AD2S200 reset 13 12 5 4 A13 A12 A10 A9 ADM C200 base address for reads ID PHV1 frotation registers IQ PHV2 IX PHV3 IY VY ADCU ADCV ADCW ADCAUX SYSSTAT ADC registers System status register A13 A12 A5 A4 bit 6 don t care ADM C200 base address for write RHO rho for reverse PARK PHIP1 VD frotation input regs PHIP2_VQ PHIP3 RHOP 1oad rho for forward PARK PWMTM PWM master clock frequency PWMTCHA PWM on times PWMTCHB PWMTCHC PWMDT dead time PWMPD pulse deletion SYSCTRL System control reg R W APPENDIX ADMC200C H 1ADSP 21xx intemal memory mapped registers CONST TSCALE Ox3FFB TIMER SCALE REG CONST TCOUNT Ox3FFC TIMER COUNTER REG CONST TPERIOD Ox3FFD TIMER RE LOAD REG CONST WS_Control_Reg Ox3FFE ADSP 21xx System Control CONST System_Control_Reg Ox3FFF ADSP 21xx wait state Control 05 21 Interrupt MASKs CONST TIMER_INT 0 1 timer CONST SPO TX INT 0x2 PORTO transmit CONST SPO RX INT Ox4 PORTO receive CONST SP1 TX INT 0x8 transmit 5 1 INT 0 10 receive CONST IRQ2_INT 0x20 RQ2 44DSP21xx DAC and hardware control register CONST LDAC 0x0040 CONST DAC RESET 0 0080 CONST HARDWARE_REGISTER 0x3500 ADMC 200 SYSCTRL mode setting bits CONST ADCU_EN 0 0080 ADC ch U enable CONST AUX_EN
5. constants derived from the above inputs CONST PWMSF CLOCK 1000 PWMFREQ_kHz CONST PWMDT CLOCK DEADTIME ns 2000 2 must be an even number CONST PWMPD CLOCK DELETION ns 2000 2 CONST DELTH PARK HZ 65536 PWMFREQ_kHz 1000 CONST DELVP 1 Define the SYSCTRL write values for each mode by logically ORing the constants defined in the file ADMC200C H Thus for example ADC_MODE requires ADC interrupts enabled and the U and AUX channels enabled In this mode of opera tion the program is timed by A D converter interrupts ADM C200 clock modes The ADMC200 has a max clock input frequency of 12 5 MHz If you use a DSP clock faster than this say 20 MHz the ADM C200 can divide the clock by 2 by writing to bit 5 in the system control reg Use the mode definitions below for divide by 2 operation change the CLOCK constant in user constant definition section ifdef CLK12MHz CONST ADC_MODE ADC_INT_EN ADCU_EN AUX_EN CONST REV_PARK_MODE PARK_INT_EN CONST FOR PARK MODE PARK INT EN FOR PARK EN endif ifdef CLK20MHz CONST ADC_MODE ADC_INT_EN ADCU_EN AUX_EN DIV2_ EN CONST REV PARK MODE PARK_INT_EN DIV2_EN CONST FOR PARK MODE PARK INT EN FOR PARK EN DIV2 EN endif Define the ADC channel circular buffer for them FIR filter One buffer stores samples for all buffered channels in this case the stored values are ADCV 0 ADCW 0 ADCV 1 ADCW 1 ADCV 2 ADCW 2 ADCV 3 ADCW 3 ADCV 4 ADCWIA CONST ADC
6. frequencies can be selected by replacing the re sistor networks 7XR DIL isolated resistor network Table Ill ADMC200 EVAL Analog Connector Connector Name ADMC200 Connection SHIELD Connected to 0 VL Ground Plane SGND Connected to SGND Ground Plane U Connected to U via RC Filter SGND Connected to SGND Ground Plane V Connected to V via RC Filter SGND Connected to SGND Ground Plane Connected to W via RC Filter SGND Connected to SGND Ground Plane AUXO Connect to AUX AUX1 ADMC201 Only AUX2 ADMC201 Only AUX3 ADMC201 Only SGND Connected to SGND Ground Plane REFIN Connected to REFIN Pin PWM Output Signals The six PWM outputs signals are buffered by a 74LS04 HEX buffer IC and brought to the 8 way terminal block If active low signals are required direct from the ADM C200 this inverter IC can be bypassed The buffer can be replaced by an open collector device to drive opto isolating LED input type gate drive circuits The PWM STOP input is brought directly from the connector to ADMC200 If this input is unused it should be pulled low through a 10K resistor to prevent spurious tripping of the PWM signals Table IV ADMC200 EVAL PWM Connector Connector Name ADMC200 Connection OVL Connected to 0 VL Ground Plane PWMSTOP Input to ADMC200 STOP Pin CP Driven by ADMC200 CP through Buffer Driven ADMC200 through Buffer BP Driven by ADMC200 BP through Buffer B Driven by ADMC200 B through Buffer
7. the SYSCTRL registers and checking that it matches what was written It should be noted here that the lower 4 bits read must be ignored since the ADMC200 has only a 12 bit address bus Therefore the value read back is logically ANDed with OxFFFO before being compared with the value written out If the two values do not match an error condition will be set and the FLAG OUT LED will start flashing This type of error can be caused either by an address decoding error or a completely faulty ADMC200 readback_test test ADMC200 SYSCTRL READBACK function if error jump to stall condition ay0 ADC MODE ADM C200 set up in A D mode ay1 OxfffO dm SYSCTRL 0 NOP ax0 dm SYSCTRL read ax0 AND 1 strip lower 4 bits ar ar XOR 0 compare with value written to reg if eq RTS freadback correct if zero 0 1 ferror condition 1 call error set RTS 15 ection 6 Interrupt service routine code The program loop is timed on the IRQ2 signal The first operation in the IRQ2 interrupt service routine IRQ2_ISR is to read the ADMC200 SYSSTAT register and to check bit 11 for an ADMC200 interrupt An error condition is set if this bit is not set since there are no other interrupt sources on the board The next operation is to look for an A D interrupt bit 1 indicating the beginning of a new program cycle If this is the case the program jumps to the section of code which reads the A
8. tions and pinout is included in the product data sheet There is also a companion application note describing the digital implementation of a high speed motor control systems using the ADM 200 ADM C201 and an ADSP 2105 DSP This document only relates to REV 2 0 of the ADM C200 EVAL board and REV 2 0 of the demon stration software ADMC200 EVAL BOARD HARDWARE The system block diagram is shown in Figure 1 while the full circuit diagram is in Appendix A The board has the ADM C200 ADM C201 as the main com ponent a 745138 address decoder a 741504 hex in verting buffer and some passive components The user connections to the board are made via three ter minal blocks PWM output analog input and digital Separate analog 5 VA and logic 5 VL power is supplied through a 4 way terminal block The analog input channels have Zener diode protec tion and a two pole passive anti aliasing filter with a default cutoff frequency of 5 kHz The reference input PWM CONNECTOR ADDRESS DECODE gt 5 Figure 1 ADMC200 EVAL Board System Block Diagram can be taken from the ADMC200 ADMC201 reference output or through the analog connection block The CONVST pin can be connected to the PWMSYNC pin or to the external digital connector The ADMC200 ADMC201 PWM outputs are buffered using a 74LS04 hex inverter to give active high PWM signals at the connec tor Other signal formats can be obtained by using a dif fere
9. ALAR 60 261 MACRO used to initialize data memory variables ax0 1 dm 0 ax0 initialize PM data init firl_coeff 0x049200 0x1edb00 0x392600 0x1edb00 0x49200 PM fixed point constants derived using MATLAB function fir1 4 0 01 Section 3 Interrupt code table Two interrupts are used IRQ2 from the ADMC200 for ADC complete and PARK complete TIMER for error detection and indication resulting in flashing flagout The DSP code begins at address 0x0000 with the interrupt vector table An IRQ2 interrupt causes the program to jump to an interrupt routine that reads the ADMC200 SYSSTAT register and determines the interrupt source The TIMER in terrupt is used to toggle the FLAG out LED when the program is in an error condition In normal operation the timer TCOUNT register is not allowed to reach zero nterupt vector table JUMP start NOP NOP NOP Chip RESET JUMP IRQ2_ISR RTI NOP NOP 1802 ADMC 200 interrupt RTI NOP NOP NOP not used RTI NOP NOP NOP not used RTI NOP NOP NOP not used RTI NOP NOP NOP not used TOGGLE FLAG_OUT RTI NOP NOP TIMER interrupt on TIMEOUT 13 Section 4 Initialization code The main program starts by initializing the ADSP 2101 System_Control_Reg and setting up the ADSP 2101 wait state register to have zero wait states for them ADMC200 and 2 wait states for the 8 bit DAC This section initializes the data address generators some program v
10. ANALOG AN 407 DEVICES APPLICATION NOTE ONE TECHNOLOGY WAY e P O BOX 9106 NORWOOD MASSACHUSETTS 02062 9106 e 617 329 4700 AC Motor Control Experiments Using the ADMC200 EVAL Board by Aengus Murray and Paul Kettle INTRODUCTION The ADM C200 EVAL board can be used to build simple motor control demonstration based around the ADM C200 motion coprocessor The board is designed to interface directly to the ADDS 2101 EZ LAB or the ADMC21xx EZ LAB boards through the 60 pin user interface con nector This board can be used with processors that are compatible with the ADM C200 address and data bus The evaluation board is supplied with a DSP assembly code for a demonstration program that exercises all the ADM C200 functions The software provided with the evaluation board serves two purposes Running the software demonstrates ADM C200 functions and verifies the operation of the IC The software can also serve as a useful template around which to write motor control software using the ADM C200 This application note describes the ADMC200 EVAL board hardware setting up with the ADSP 2101 EZ LAB board and a description of the demonstration software Instructions on how to load and run the software is given in the Running the Demonstration Program section E o 2 lt a POWER CONNECTOR n T RCFILTER NETWORK ANALOG INPUT CONNECTOR A more detailed description of the ADM C200 func
11. AP Driven by ADMC200 AP through Buffer A Driven by ADMC200 A through Buffer Digital I O Signals Only two of the digital I O signals are used with the ADMC200 An external start of conversion signal can be supplied via the EXTSAMPLE connection and the PWMSYNC pulse is brought out to this connector Table V ADMC200 EVAL Digital I O Connector Connector Name ADMC200 Connection OVL Connected to 0 VL Ground Plane PIOO ADMC201 Only PIOL ADMC201 Only PIO2 ADMC201 Only PIO3 ADMC201 Only PIO4 ADMC201 Only PIO5 ADMC201 Only PWMSYNC ADMC200 PWMSYNC Output EXTSAM PLE External CONVST Signal Input Data and Address Bus Interface The ADMC200 board connects to the ADSP 2101 data and address busses via the 60 pin user interface con nector The ADMC200 4 bit address bus is connected to the lower 4 bits of the DSP address bus ADO AD3 The ADMC200 chip select line CS is derived using the 745138 address decoder from the DSP address lines AD9 AD10 AD12 and 013 according to Table VI The memory space between 1000 and 2FFF is used by the EZ LAB DAC The ADMC200 read registers are memory mapped to the DSP data memory between 0x3000 and 0x300F To allow read and write registers to have differ ent names the write registers are mapped between 0x3010 and 0x301F The memory map for the system is given in Table VII The DSP reads and writes data directly to and from the ADMC200 registers The 200 data bus is con ne
12. C 37 38 GND GND AD7 NC 39 40 D16 D16 AD8 NC 41 42 D17 D17 GND GND 43 44 D18 D18 AD9 AD9 45 46 D19 D19 AD10 AD10 47 48 D20 D20 AD11 NC 49 50 D21 D21 AD12 AD12 51 52 D22 D22 AD13 AD13 53 54 D23 D23 GND GND 55 56 GND GND DMS DMS 57 58 CLK CLOUT GND GND 59 60 GND GND Using the ADMC200 EVAL Board with the ADSP 2101 EZ LAB To run the supplied demonstration software the ADSP 2101 EZ LAB board IRQ2 must be enabled from the user interface connector 60 pin IDC and The FLAG IN push button must be enabled The required jumper configura tions are shown below If you are using higher clock frequencies you need to edit the software and run in the divide by two clock mode see source code listing Table IX ADSP 2101 EZ LAB J umper Configuration J umper Position Function J P2 3 2 Enable FLAG IN Pushbutton 8 Don t Care JP1 2 1 Enable IRQ2 from the User Interface Connector ADMC200 EVAL Board Software The demonstration software exercises the three main functional blocks on the ADMC200 the A D converter the vector transformation block and the PWM block The program can be loaded on to the EZ LAB using the EZ ICE or by burning a boot EPROM The program runs in a loop timed by the ADM C200 A D converter interrupt signal that is synchronized to the PWM frequency There are four modes of operation that can be sequenced through by pressing the FLAG IN button on the EZ LAB board n the ADC
13. CONN 30X SGND SHIELD 30X2 EZ LAB INTERFACE O SGND OVA CON14 Figure 2 ADMC200 ADMC201 Evaluation Board APPENDIX B ADMC200 SYS code for ADSP 2101 and ADM C200DB rev 2 0 SYSTEM admc200 ADSP 2101 seg rom boot 0 SEG PM RAM ABS 0 CODE DATA SEG DM RAM ABS 0x3800 DATA EZLAB DAC ports dm abs 0x3700 dm abs 0x3701 dm abs 0x3702 dm abs 0x3703 dm abs 0x2000 dm abs 0x3500 ADM C200 Demo board ports dm abs 0x3200 ADM C200 output ports reads CONST BASE200 RD 0x3000 port dm abs BASE200 RD dm abs BASE200 1 dm abs BASE200 RD42 port dm abs BASE200 RD 3 port dm abs BASE200 RD48 port dm abs BASE200 RD 5 port dm abs BASE200 RD46 dm abs BASE200 RD47 dm abs BASE200 RD 414 A DM C200 input ports writes ADM C200 output ports reads CONST BASE200 WR 0x3010 port dm abs BASE200 WR dm abs BASE200 WR 1 dm abs BASE200 WR42 dm abs BASE200 WR 43 dm abs BASE200 WR44 dm abs BASE200 WR 45 port dm abs BASE200 WR46 dm abs BASE200 WR 47 port dm abs BASE200 WR48 port dm abs BASE200 WR 9 port dm abs BASE200 WR H10 port dm abs BASE200_WR 13 ENDSYS Boot at reset boot page 0 2048 int pm 2048 int dm 1024 write write write dac2 write dac3 load dac extem
14. FOR PARK TEST ax0 FOR PARK MODE Set ADMC200 in PARK mode dm SYSCTRL ax0 ar dm theta increment theta ayO dm dtheta dm theta ar 10 pointer for PARK inputs from V_d call FOR_PARK_WR i0 V_ph pointer for PARK results into V_ph on PARK interrupt RTI in REV PARK mode and new values of V ph 1 V ph 2 and rho are written to the PARK registers The PARK interrupt is enabled by writing to the SYSCTRL register Writing to rhop initiates a PARK transform and an IRQ2 interrupt is gener ated on completion REV PARK TEST axO REV PARK MODE Set ADMC200 in PARK mode dm SYSCTRL ax0 ar dm theta increment theta ayO dm dtheta dm theta ar i0 V_ph pointer for PARK inputs from previous FOR PARK results call REV_park_wr i0 ld pointer for read PARK results into V ph on PARK interrupt RTI 17 PWM test the values in the V_ph array are incremented by one count each A D interrupt cycle When writing to the PWM outputs the voltage values must be scaled according to half the PWM period pwm tm 2 as t x T 2 1 Vout PWM_TEST i0 V_ph ayO dm dV ph cntr 3 do Vph_incr until ce ar dm i0 m0 ar ar ay0 dm i0 m1 ar call PWMOUT_200 RTI Vph_incr fend this segment of the ISR Each time the ADM C200 is set up for PARK interrupts an IRQ2 interrupt is generated on completion The PARK inter rupt service routine reads the PAR
15. K registers and writes them to the DAC outputs The ADM C200 is then returned to ADC INT mode PARK input 1 PHV1 I2 WRITE CNTR 4 DO READ LOOP UNTIL CE AXO DM i1 M1 DM 10 M1 AXO READ LOOP DM i2 M1 AXO ax0 ADC MODE dm SYSCTRL ax0 RTI READ ADM C200 PARK registers Store in buffer depending on mode write to DAC registers Section 7 This block of code includes all the subroutines FOR PARK WR axO dm i0 m1 dm PHIP1 VD ax0 dm i0 m1 dm PHIP2_VQ_ ax0 axO dm theta dm rhop_ ax0 RTS REV_PARK_WR ax0 dm i0 m1 dm PHIP2_VQ_ ax0 ax0 dm i0 m1 dm PHIP3 ax0 axO dm theta ax0 RTS PHIP2 input result of previous FOR PHIP3 input result of previous FOR This writes correctly scaled V ph to the PWMchx registers PWMOUT 200 i1 PWMTCHA i0 V ph myO dm pwm t0 cntr 3 do pwm loop until mr 0 1 mxO dm i0 m1 mr mr mxO myO ss pwm loop dm i1 m1 mr1 rts pointers to PWMTCHX 7 pwm scale factor pwmtm 2 wm 0 ph ch 2pwm TO4V ph pwm scale write to PWMTCHX_ 18 PWM SETUP The PWMTM register is first loaded with the PWM period in units of counts It should be noted that when the pwm_tm program variable was initialized the value was shifted up four bits since the ADMC200 is connected to the DSPs 12 most significant bits The constant pwm_tO pwm_tm 2 is calc
16. OV and 5 V to at least two of the ADC inputs PHIP2 and PHIP3 The ADC converts these to a 2s complement numbers between 8000 REFIN 2 5 V and 7FFF REFIN 2 5V corresponding to fixed point values between 1 0 and 1 0 These ADC inputs are the Vd and Vq inputs for the FORWARD PARK demonstra tion so they must have a vector magnitude less than 1 i e Vd Vg lt 1 To switch between modes press FLAG key on the EZ LAB Board The demonstration results will be dis played on either the PWM output connector or the EZ LAB DAC connector For completeness the full demonstration code algorithm is presented in pseudo code format here Start reset the admc200 setup dsp interrupts Test1 read back test if error flash led Setup start pwm Main wait for interrupts if FLAG IN change mode IRQ2 ISR check ADM C200 interrupt status ADC interrupt read U V W AUX filter V W and save as vd and vq select case mode Case mode 0 pwm test increment phase voltages calculate new pwmchx values write to pwm registers Case mode 1 ADC_TEST write ADC inputs to DAC save values as Vd vector Case mode 2 FOR_PARK_TEST increment theta checks sysctrl read write required to generate convst for ADC start of interrupt service routine generates slowly changing pwm reads ADC and writes to DACs generates three phase sinewave write Vd values and theta to park registers set park read pointer to V_ph C
17. R 0 8 ADCU A D Conversion Result 0x300E R 0 E SYSSTAT System Status Register 0x3010 W 0 0 _ Forward Rotation Angle Input 0x3011 W 0 1 PHIP1 VD Forward Reverse Rotation Input 0x3012 W 0 2 PHIP2 VQ Forward Reverse Rotation Input 0x3013 W 0 3 _ Reverse Rotation Input 0x3014 W 0 4 RHOP_ Reverse Rotation Angle Input 0x3015 W 0 5 PWMTM_ PWM Period Input 0x3016 W 0 6 PWMCHA_ PWM Channel On Time Input 0x3017 W 0 7 PWMCHB PWM Channel On Time Input 0x3018 W 0 8 PWMCHC_ PWM Channel On Time Input 0x3019 W 0 9 PWMDT_ PWM Deadtime Input 0x301A W 0 A PWMPD PWM Pulse Deletion Input 0x301D R W 0 D SYSCTRL System Control Register The ADMC200 EVAL board connects to the DSP over the EZ LAB user interface connector according to the following table Here the ADM C200 connections in bold are direct connections to the DSP while the connections shown in italic are used to produce CS and RESET sig nals for the ADMC200 The relevant EZ LAB DSP con nections are shown for reference Table VIII ADMC200 EVAL DSP Interface Connector ADSP 2101 ADMC200 Pin Pin ADMC200 ADSP 2101 1802 1802 1 2 GND GND NC 3 4 NC NC 5 6 NC NC 7 8 NC IRO1 IRO1 9 10 NC HOST RESET HOST RESET 11 12 NC NC 13 14 NC NC 15 16 NC WR WR 17 18 NC RD RD 19 20 GND GND GND GND 21 22 NC ADO 23 24 AD1 Al 25 26 NC AD2 A2 27 28 NC AD3 A3 29 30 012 012 GND GND 31 32 D13 D13 AD4 NC 33 34 D14 D14 AD5 NC 35 36 D15 D15 AD6 N
18. SMP 5 ADC buff samples per ch CONST ADC CHS 2 ADC buff ch s used define the timer constants for error conditions CONST PRESCALE 250 timer prescale 20 us for 12M clock CONST TIMEOUT 500 program timeout 1000 us CONST FLASHING 10000 error flag flash rate 1 1 0 2s 2 2 5 Hz 12 Section 2 This section of the code defines the variables and ports used the program include lt admc200p h gt ADMC200 PORT Definitions file dm ram Id 4 feverse Park results ram V ph AT Forward PARK results var dm Vdl4T Forward PARK inputs from ADC var dm ram dV ph V ph incr test ram dtheta theta incr in PARK tests ram theta frotation angle dm ram pwm tm PWM period ram pwm_to PWM period 2 dm ram pwm dt PWM deadtime var dm ram pwm pd PWM pulse deletion var dm ram errstat program error status dm ram sys read ADM C200 systat readback dm ram sys read ADM C200 sys control readback var dm ram mode program mode dm circ ADC_buf ADC_SMP ADC CHS ADC buffer for filter var pm ram coeff ADC 5 filter coefficients var dm ram temp The program memory variables for the FIR filter are initialized using the INIT statement the other constants are ini tialized explicitly in the start up code MACRO INIT DM SC
19. TEST mode the program reads the four A D channels and writes the values to the EZ LAB DAC outputs DACO 3 n the FOR PARK TEST mode two of the A D chan nels V and W are used as the Vd and Vq inputs for a forward PARK and CLARKE transformation The rota tion angle is incremented at a constant rate and the PARK results are displayed 2asa set of three phase voltages n the REV PARK TEST mode the most recent PHV1 results of the forward PARK and CLARKE trans formation are used as the PHIP2 and PHIP3 inputs for a reverse PARK and CLARKE transformation The ro tation angle is again incremented at a constant rate but this time the PARK results displayed on 1 as a set of quadrature sin cos voltages Inthe PWM_TEST mode a set of three phase voltages are incremented by 1 count per PWM cycle thus giving a slowly varying duty cycle on each of the channels The demonstration software disks includes a system file ADMC200 SYS two include files ADM C200C H ADM C200P H the main DSP code A200EVAL DSP and a GO batch file The System Hardware File ADMC200 SYS Appendix B The system file describes the ADM C200 EVAL and the ADSP 2101 EZ LAB board address decode schemes The EZ LAB DAC ports are mapped between memory loca tions 0x1000 and 0x2000 The ADMC200 reset line is mapped to the data memory location 0x3000 The ADM C200 read registers are mapped to data memory locations running from 0x3000 to 0
20. TPERIOD TIMEOUT INIT DM SCALAR TCOUNT TIMEOUT ENA TIMER et up interrupts ICNTL 0x07 IFC 0x3f NOP IMASK RQ2 INT TIMER INT edge triggered interrupts clear all pending interrupt IRQ2 and timer set 14 Start to use the ADM C200 by resetting the chip which puts the IC into a known state A dummy write this address causes the 74S138 address decode IC to pull the ADMC200 RESET line low dm AD2S200 reset ax0 ADM C200 Chip reset for ADSP 21xx board ifdef ADMC21xx ResetDAC endif Now test chip readback on sysctrl call readback_test error code for this test 1 To start the main tests we need to generate a CONVST pulse for the A D converter We start the PWM block and the PWMSYNC pulse produces the CONVST pulse call PWMSET_200 Section 5 Mode change code The program now waits for the first A D converter interrupt While waiting in this loop the DSP checks the FLAG_IN for a request for a program mode change wait int idle if NOT FLAG in jump no mode change jump wait int wait here for interrupt no mode change if NOT FLAG in jump no mode change change test mode on flag in push button ayO dm mode present mode ay1 0x4 4 modes possible 0 1 2 3 ar ay0 1 change mode if It 1 if lt 0 set back to mode 3 dm mode ar Save new mode jump wait_int The first test is the ADMC200 read back test This involves writing to the SYSCTRL registers reading
21. ariables and the timer registers The DSP interrupt mode is set for TIMER and IRQ2 interrupts start ax0 0038 dm System_Control_Reg ax0 RESET FLAG OUT 40 000 001 010 000 000 0 000 000 088 880 000 ifdef ADMC21xx ax0 0x2080 ax0 0x0080 endif dm WS Control Reg ax0 et up DAGs 10 0 mO 0 11 0 m1 1 12 0 m2 2 i3 ADC buf I3ZADC SMP ADC m3 ADC CHS 1420 m4 1 1520 m5 0 16 0 m6 0 1720 7 0 clear some DM variables ax0 0x0 dm theta ax0 dm mode ax0 Clear ADC Buffer CNTR ADC SMP ADC CHS do clear buf until CE clear buf dm i3 m1 ax0 initialize DM variables 50 0 S1 0 SC1 0 BF 0 0 BW 9 PW 0 Clear error flag Wait sate calculation DW420 DW3 1 DW2 2 DW1 0 dWO0 0 W4 2 for DAC DW3 0 for ADMC200 DW2 2 for DAC DW3 0 for ADMC200 DAGO GP Linear data DAG1 GP Linear data DAG2 GP Linear data DAG3 ADC circular buffer DAG4 GP LINEAR DAG5 GP LINEAR DAG6 GP LINEAR DAG7 used as program pointer tart up in PWM_TEST mode INIT_DM_SCALAR dtheta DELTH INIT_DM_SCALAR dV_ph DELVP theta incr V ph incr PWM constants are in system clock cycles and need to be shifted up 4 bits since the ADM C200 registers are only 12 bits wide INIT DM SCALAR pwm tm PWMSF 4 INIT DM SCALAR pwm dt PWMDT 4 INIT DM SCALAR pwm pd PWMPD 4 et up timer for timeout INIT DM SCALAR TSCALE PRESCALE INIT DM SCALAR
22. as described in the following table Table 1 ADMC200 EVAL Ground J umpers JUMPER Position Function J PG1 IN Connects Analog Ground 0 VA to Star Point J PG2 IN Connects Logic Ground 0 VL to Star Point J PG3 IN Connects Signal Ground SGND to Star Point The ADMC200 ADMC201 A D converter connections can be configured using jumpers J 1 and J P2 as described in Table Il Here the names in bold are ADMC200 ADMC201 pins while the names in italic are brought from one of the terminal blocks The start of conversion signal can be syn chronized to the PWM switching frequency using PWMSYNC or to an external CONVST signal The A D reference REFIN can be derived from the on board refer ence REFOUT or through the analog connector Table Il ADMC200 ADMC201 EVAL ADC J umpers J umper Position Function JP1 1 2 Connects PWMSYNC to CONVST 2 3 Connects EXTSAMPLE to CONVST JP2 1 2 Connects REFOUT to REFIN 2 3 Connects REFIN to REFIN J 1 2 Connect IRQ on ADM C200 ADM C201 to DSP IRQ2 2 3 Connect IRQ on ADM C200 ADM C201 to DSP IRQ1 Analog Input Signals Analog inputs to the Analog to Digital A D converter are brought through a 14 way connector block de scribed in Table Ill There is a two stage passive anti aliasing low pass filter at the input to each of the A D converter channels The filter R and C values are 10 kQ and 3 3 nF which gives a cutoff frequency of 5 kHz Other cutoff
23. ase mode 3 REV PARK TEST increment theta generates quadrature sinewave write V ph values and theta to park registers set park read pointer to id End of ADC interrupt service routine return to main Park interrupt read park registers write values to DAC save values as V ph or id vector End of park interrupt service routine return to main APPENDIX ADMC200 EVAL CIRCUIT DIAGRAM POWER TERMINAL BLOCK 5VL 012 013 014 015 016 D17 D18 D19 D20 D21 EXTSAMPLE D22 PWMSYNC D23 PIO5 x PIO4 JP3 ES PIO3 IRQ1 10kQ PIO2 nos EFEHEEEERBE SION IRQ2 rr PIOO mis Hone O roo 2 RD WR DMs Fro 59 i GND ovu PWM TERMINAL BLOCK 12 T U1A JA a 1 2 A E ris ADO 14 3 4 Ns AD1 7407 U1C AD2 5 6 B AD3 ERU n U1D Pre AD9 CONVST ADMC201 B 53 9 8 AD10 Nc 5 wr 19 Vp TOP VIEW 51 11 p c o 120 c 50 7407 AD12 3 STOP 7 24 CS DGND 46 JP1 25 NC 6 AD13 ze v OVL CONVST EXTSAMPLE JP2 ANALOG ADCREF TERMINAL BLOCK J4 CLKOUT 023 022 REFINHI D21 D20 019 1 018 0 0 0 LGND JPG2 D16 o o o JPG3 SGND O O SGND D14 013 012 RN1F OVL 6 10kQ 9 RESISTOR 14 E 6 8
24. cted to the top 12 bits of the DSP data bus 012 D23 thus lowest 4 bits read by the DSP will always be invalid This data bus connection scheme easily allows the use of the DSP fixed 1 15 mode of operation There fore a full scale negative input on the A D converter giving 25 complement number 0x800 will be read into the DSP as 0x8000 HEX or 1 0000000 fixed point See Chapter 2 of the ADSP 2100 Family User s Manual The ADM C200 interrupt line is connected to DSP interrupt IRQ2 Table VI ADMC200 EVAL Chip Select Logic 21xx EZ LAB DMS AD13 AD12 AD10 AD9 ADMC200 EVAL DMS A3 A2 Al AO ADMC200 CS ADMC200 RESET H X X X X 1 1 L 1 1 0 0 1 0 L 1 1 0 1 0 1 Table Vil ADMC200 EVAL Memory Address Direction ADMC200 HEX amp Wait States Address Mnemonic Function 0x1000 W 2 Write_DACO_ DAC Channel 0 Data Input 0x1001 W 2 Write DACI DAC Channel 1 Data Input 0x1002 W 2 Write DAC2 DAC Channel 2 Data Input 0x1003 W 2 Write DAC3 DAC Channel 3 Data Input 0x2000 W 2 Load DAC Load DAC Data 0x3000 W 0 ADMC200 RESET ADMC200 Chip Reset 0x3000 R 0 0 ID_PHV1_ Forward Reverse Rotation Result 0x3001 R 0 1 IQ PHV2 Forward Reverse Rotation Result 0x3002 R 0 2 IX Forward Reverse Rotation Result 0x3003 R 0 3 IY_VY_ Forward Reverse Rotation Result 0x3005 R 0 5 ADCV_ A D Conversion Result 0x3006 R 0 6 ADCW_ A D Conversion Result 0x3007 R 0 7 ADCAUX A D Conversion Result 0x3008
25. nt buffer The ADMC200 board connects to the ADSP 2101 data and address busses via the 60 pin user interface connec tor The ADMC200 ADMC201 data bus is connected to the top 12 bits of the DSP data bus 012 023 The ADMC200 ADMC201 4 bit address bus is connected to the lower 4 bits of the DSP address bus ADO AD3 The ADMC200 ADMC201 chip select line CS is derived using the 74S 138 address decoder from the DSP address lines AD4 AD5 AD12 and AD13 The memory space between 1000 and 2FFF is used by the EZ LAB Digital to Analog Converter The ADMC200 read registers are memory mapped to the DSP data memory between 3000 and 300F To allow read and write registers to have dif ferent names the write registers are mapped between 3010 and 301F The DSP read write and output clock lines are connected directly to the ADMC200 The 200 interrupt line IRQ is connected to DSP inter rupt IRO2 Power Supply Connections The board requires a 5 V power supply Separate ana log 45 VA and OVA and logic 5 VL and 0 VL supply connections are provided to minimize noise on supply cables It is recommended that the logic analog and sig nal grounds be connected to a common star point on the board using jumpers J 1 J umper Configuration The board has three ground planes a logic ground plane OVL an analog ground plane OVA and a signal ground plane These can all be connected to a common star point using jumpers J PG1 3
26. ode consists of interrupt service routines ISR which services the ADM C200 interrupt There are two sources of ADM C200 interrupt enabled enabled namely the A D conversion and the Park and Clarke transformation The ISR is partitioned into three portions one for each of the interrupt sources and an initial portion that parses the ADM C200 SYSSTAT register to determine the source of the interrupt and subsequently call one of the two service portions The A D portion of the ISR is sub divided into four sections depending on which one of four modes is in operation The source code file can be split into a number of sections Definition of program constants Definition of program variables Interrupt jump table code Initialization code Mode change code Interrupt service routine code Subroutine code NOURWNE RUNNING THE ADMC200 EVAL BOARD DEMONSTRATION SOFTWARE Running the Demonstration Program The demonstration software is supplied as source code and so it must be assembled and linked before being downloaded onto the EZ LAB board The following com mand line is used to compile the demonstration program go clock_freq processor board rev daughter board rev where clock is either CLK20MHz or CLK12M Hz processor board revis either ADSP2101 or ADM C21xx For example the most common configuration would be go CLK12MHz ADSP2101 DEMONSTRATION PROGRAM ALGORITHM To run the demonstration you will need dc inputs be tween
27. to give Vd inputs for the PARK tests pointer for filtered inputs for PARK axO dm ADCV READ ADCV dm i3 m0 ax0 write to ADC_BUF without incr i3 call ADC_FIR1 filter inputs 13 unchanged dm i1 m1 mr1 write filtered result to Vd 0 modify i3 m1 Skip to NEXT CHANNEL ax0 dm ADCW_ READ ADCW dm i3 m0 ax0 write to ADC_BUF without incr i3 call ADC_FIR1 filter inputs i3 unchanged dm i1 m1 mr1 write filtered result to Vd 1 modify i3 m1 Skip to NEXT CHANNEL 16 The next section of code involves selection of one of the four sections of code depending on the value of the variable mode This determines the entry to the jump table according to the test mode ar dm mode fest mode ay0 test jump table Start of jump table 0 fadd mode offset i7 ar jump table pointer jump i7 test jump table jump PWM TEST MODE 0 jump REV PARK TEST MODE 1 jump FOR PARK TEST MODE 2 jump ADC TEST MODE 3 ADC Test read ADCX values to the EZ LAB DAC ADC TEST i1 ADCV i2 WRITE CNTR 4 DO ADC_LOOP UNTIL CE AXO DM I1 M1 READ ADMC200 A D channel ADC_LOOP DM I2 M1 AXO0 write to EZ LAB DAC registers RTI n FOR PARK mode and new values of Vd Vq and rhop are written to the PARK registers The PARK interrupt is enabled by writing to the SYSCTRL register Writing to rhop initiates a PARK transform and an IRQ2 interrupt is generated on completion
28. ulated at this point using a shift instruction The deadtime and pulse deletion constants are loaded next Finally pwm tm 2 is loaded into each of the PWM chan nels to start a PWM cycle with a 50 duty cycle Each PWM cycle will produce a PWM SYNC pulse to start an A D conversion which will produce an ADC interrupt every PWM period This sub initializes PWM registers and variables kicks off PWM PWMSET 200 pointers to PWMTCHX_ si dm pwm tm dm PWMTM si write PERIOD to ADMC200 srSshift si by 1 hi dm pwm tO sr1 t0 PERIOD 2 axO dm pwm dt dm PWMDT ax0 Write deadTIM E to ADM C200 axO dm pwm dm PWMPD ax0 Write pulse deletion to ADM C200 dm i1 m1 sr1 write PERIOD 2 to PWMTCHA_ dm i1 m1 sr1 write PERIOD 2 to PWMTCHB dm i1 m1 sr1 write PERIOD 2 to PWMTCHC rts This is a 5th order FIR filter ADC firl filter starts at current point in buffer i4 firl coeff mxO zdm i3 m3 myO pm i4 m4 mr 0 CNTR ADC_SMP 1 do filter_loop until ce filter loop mr mr mxO myO ss mx0O dm i3 m3 myO pm i4 m4 mr mr nx0 myO ss rts f an error condition is encountered this code sets the LED flash rate and saves the error code in a register for debugging purposes error_set DM ERRSTAT ar ERROR MODE IN AR myO FLASHING mr ar myO UU dm TPERIOD mr0 RTS ENDMOD 19 96 9 S OVTZ4 V S f NI GALNIdd 20
29. x300F The ADM C200 write registers are mapped to data memory locations running from 0x3010 to 0x301F this does not effect the address decode hardware but it allows the use of differ ent register names for data memory reads and writes ADMC200 Constants File ADMC200C H Appendix C This file includes a number of universal constants used in the program The first group of constants define some ADSP 2101 memory mapped registers The second group of constants define ADSP 2101 interrupt masks The next group of constants define the bits that must be set in the ADM C200 ADM C201 system control register to operate the device in different modes e g AUX EN enable the A D AUX channel by setting Bit 7 The last set of constants define the bits in the SYSSTAT register that should be compared with in order to determine the ADM C200 interrupt source ADMC200 Port File ADMC200P H Appendix D This file includes all the port definitions required for the ADM C200 memory mapped registers ADMC200 DSP Code A200EVAL DSP Appendix E There is a single file for the main DSP assembly code The file can be edited to change the user program parameters such as system clock frequency etc as listed below These parameters in SI units used to derive program constants such as the PWM period in clock counts etc The code at the beginning of the program performs initialization of the DSP and ADM C200 The program is interrupt driven The main part of the c
Download Pdf Manuals
Related Search