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MCF5272 Interrupt Service Routine

1. Yes Yes ASR GSR Set Read PLGCR PLICR GCT Se ar Yes Read PLGCITS Read PLGMR PLICR GMT Read PLGMTS Set 2 Figure 11 One Port Processing Aperiodic Interrupt Service Routine Flow Diagram ASR GMR 6 2 Multi Port Case Once the PLIC has many GCI ports enabled a generic aperiodic interrupt is required to handle all of the possibilities As previously done in the periodic interrupt the PnICR will be read so it can save some MIPS in case the port is not enabled The flow chart is shown in Figure 12 MCF5272 Interrupt Service Routine For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Aperiodic Interrupt Process Brief Register Explanation Yes Yes ieee Process Port No Yes ES PADRES Process Portl No No _ 1 Vex Yes PASR 11 8 1 0 Process Port No Yes Yes PASR 15 12 0 Process Port3 Process End Z 1 Z Figure 12 Multi Processing Aperiodic Interrupt Service Routine Flow Diagram 6 3 Brief Register Explanation This section describes the registers involved in the aperiodic interrupts service routine The GCI oriented registers are Pa AGMR PnGMT PnGCIR and PnGCIT These are the only register that affect the PASR register For more information about the definition of all those registers please refer to the PLIC section in the MCF5272 User s Manual for a more de
2. Go to www freescale com Freescale Semiconductor Inc Appendix A Software Configuration Port2TxD jsr Port2DTDESet move b D6 P2DTR A5 jsr Port2DTDEReset bra EndSR Port3TransmitBl jsr Port3BlTDESet move 1 DO P3B1TR A5 jsr Port3BlTDEReset bra EndSR Port3TransmitB2 jsr Port3B2TDESet move 1 DO P3B2TR A5 jsr Port3B2TDEReset bra EndSR Port3TxD jsr Port3DTDESet move b D6 P3DTR A5 jsr Port3DTDEReset bra EndSR kk ee ee hehehe ee e he ee he he ke e e he de ee he ee eee dece eee e eee ee dee e e hee eee e e e End of Transmit Bx M kk ee ee e ehe ee e de ee he dee e e ehe ee he ee eee dece e eee eee ee deese ehe kkk ee e e e E Bx RDF reset F p tkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk kkk kkk kkk kkk kkk kkk kkk PortOBlRDFReset nop move w POPSR A5 D3 To make sure BIRDF is reset andi l S00000001 D3 cmp 1 S00000000 D3 bne Port0B1RDFReset rts Port0B2RDFReset nop move w POPSR A5 D3 To make sure B2RDF is reset andi 1l 800000002 D3 cmp 1 S00000000 D3 bne Port0B2RDFReset rts PortODRDFReset nop move w POPSR A5 D3 andi l S00000004 D3 cmp 1 S00000000 D3 bne PortODRDFReset rts PortlBlRDFReset nop move w PnPSR1 A5 D3 andi 1l S00000001 D3 cmp 1 S00000000 D3 bne PortlBlRDFReset rts PortlB2RDFReset nop move w PnPSR1 A5 D3 andi l S00000002 D3 MCF5272 Interrupt Service Routine For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Appendix A Software C
3. Port2DTDESet nop Port3BlTDESet nop Port3B2TDESet nop Port3DTDESet nop bne rts move w andi 1 cmp 1 bne rts move w andi 1 cmp 1 bne rts move w andi 1 cmp 1 bne rts move w andi 1 cmp 1 bne rts move w andi 1 cmp 1 bne rts move w andi 1 cmp 1 bne rts move w andi 1 cmp 1 bne rts move w andi 1 cmp 1 bne rts move w andi 1 cmp 1 bne rts move w andi 1 cmp 1 bne rts PortOB2TDESet POPSR A5 D3 00000020 D3 00000020 D3 PortODTDESet P1PSR A5 D3 00000008 D3 00000008 D3 Port1B1TDESet P1PSR A5 D3 00000010 D3 00000010 D3 Port1B2TDESet P1PSR A5 D3 00000020 D3 00000020 D3 Port 1DTDESet P2PSR A5 D3 00000008 D3 00000008 D3 Port2B1TDESet P2PSR A5 D3 00000010 D3 00000010 D3 Port2B2TDESet P2PSR A5 D3 00000020 D3 00000020 D3 Port2DTDESet P3PSR A5 D3 00000008 D3 00000008 D3 Port3B1TDESet P3PSR A5 D3 00000010 D3 00000010 D3 Port3B2TDESet P3PSR A5 D3 00000020 D3 00000020 D3 Port3DTDESet g khe ee ee he ehe ee ee ee eee EKER ERE RRR ERE eee eee e e ek End of Bx TDE Set procedures Freescale Semiconductor Inc Appendix A Software Configuration MCF5272 Interrupt Service Routine For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Appendix A Software Configuration g khe ee ee he dee ee hee ee eee ee eee eee e e dee ee eee ee
4. EndPort3Rx move w andi 1 cmp 1 bne move 1 andi 1 cmp 1 beq EndSR rte me Ne Ne Ne Ne PortOReadBl move l jsr bra PortOReadB2 move l jsr bra PortORxD move b jsr bra Port1ReadB1 move l jsr bra Port1ReadB2 move l jsr bra PortlRxD move b jsr bra Port2ReadBl move l jsr bra Port2ReadB2 move l jsr bra Port2RxD move b jsr bra Freescale Semiconductor Inc Appendix A Software Configuration 00000004 D7 00000004 D7 Port3RxD P3ICR A5 D2 00000020 D2 00000020 D2 EndSR D1 D7 DTDE Test 00000020 D7 00000020 D7 Port3TxD kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk End of Interrupt Procedure kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk Read Procedure for each port ad kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk POBIRR A5 D0 Read Bl on Port0 PortOB1RDFReset test if RDF is reset EndSR go to ISR end POB2RR A5 D0 Read B2 on Port0 Port0B2RDFReset test if RDF is reset EndSR go to ISR end PODRR A5 D6 PortODRDFReset EndSR PIBIRR A5 D0 PortlBlRDFReset EndSR P1B2RR A5 DO Port1B2RDFReset EndSR PIDRR A5 D6 PortlDRDFReset EndSR P2BIRR A5 D0 Port2BlRDFReset EndSR P2B2RR A5 D0 Port2B2RDFReset EndSR P2DRR A5 D6 Port2DRDFReset EndSR MCF5272 Interrupt Service Routine For More Information On This Product Go to www freescale com Port3ReadBl move l jsr bra Port3ReadB2 move l jsr bra Port
5. 00000080 D7 00000080 D7 Port1CommandIndRx D1 D7 00000040 D7 00000040 D7 Port1CommandIndTx D1 D7 00000020 D7 00000020 D7 Port1MonitorChanRx D1 D7 00000010 D7 00000010 D7 PortlMonitorChanTx PASR A5 D1 D1 D7 00000800 D7 00000800 D7 Port2CommandIndRx D1 D7 00000400 D7 00000400 D7 Port2CommandIndTx D1 D7 00000200 D7 00000200 D7 Port2MonitorChanRx D1 D7 00000100 D7 00000100 D7 Port2MonitorChanTx PASR A5 D1 D1 D7 00008000 D7 00008000 D7 Port3CommandIndRx D1 D7 00004000 D7 00004000 D7 Port3CommandIndTx D1 D7 00002000 D7 00002000 D7 Port3MonitorChanRx D1 D7 00001000 D7 00001000 D7 Port3MonitorChanTx Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne compare with 4 if equal go to Store PASR into mask D7 compare with 2 if equal go to Store PASR into mask D7 compare with 1 if equal go to Store PASR into mask D7 compare with 8 if equal go to Store PASR into mask D7 compare with 4 if equal go to Store PASR into mask D7 compare with 2 if equal go to Store PASR into mask D7 compare with 1 if equal go to Store PASR into mask D7 compare with 8 if equal go to Store PASR into mask D7 compare with 4 if equal go to Store PASR into mask D7 compare with 2 if equal go to Store PASR into mask D7
6. Freescale Semiconductor Inc Appendix A Software Configuration Port3B2TDEReset nop move w P3PSR A5 D3 andi l S00000010 D3 cmp 1 S00000000 D3 bne Port3B2TDEReset rts Port3DTDEReset nop move w P3PSR A5 D3 andi l S00000020 D3 cmp 1 S00000000 D3 bne Port3DTDEReset rts The following file describes all the aperiodic interrupts that only occur in GCI mode of operation Given that the ports are supposed to work in conjunction with periodic process this example below does not show IE tests The file is as follows PLIC Aperiodic Interrupt Subroutine Can handle up to 4 GCI Ports in a dynamic way As soon as the action has been taken the program counter quits the interrupt In case of many interrupts at the same time the program counter will re enter the Aperiodic Interrupt All the comments will be written for the Port0 For the other Ports the same comments apply Use of register D1 PASR Value D2 No use D3 Monitor Channel Receive or Transmit register D4 Monitor Channel Receive or Transmit Buffer of D3 D5 First Byte of the Received Monitor Channel Register D6 Second Byte of the Received Monitor Channel Register D7 Buffer of Dl Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne i PLIC Aperiodic move w PASR A5 D1 Store PASR into D1 move w D1 D7 Buffering D1 into D7 andi 1l 2 0000000F D7 mask D7 cmp 1 80 D7 compare with 0 bne AperPort0 go to AperPort0 otherwise move w D1 D7 Store PASR into
7. compare with 1 if equal go to Store PASR into mask D7 compare with 8 if equal go to Store PASR into mask D7 compare with 4 if equal go to Store PASR into mask D7 compare with 2 if equal go to Store PASR into mask D7 compare with 1 if equal go to MCF5272 Interrupt Service Routine For More Information On This Product Go to www freescale com Freescale Semiconductor Inc CI D7 MC D7 MC D7 CI D7 CI D7 MC D7 MC D7 CI D7 CI D7 MC D7 MC D7 CI D7 CI D7 MC D7 MC Transmit receive Transmit Receive Transmit receive Transmit Receive Transmit receive Transmit Receive Transmit receive Transmit Freescale Semiconductor Inc Appendix A Software Configuration EndASR nop move l 0 D1 clear all registers move 1l 0 D2 move 1 7 0 D3 move b 0 D4 move b 7 0 D5 move b 7 0 D6 move 1l 0 D7 rte End of ISR p tkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk P Port0 Subroutines khe e ee ee he dee ee he dece e he ee ee hee e e eee hehe eee e hee e he dee ee esee eee e eee e eee e Hes Monitor Channel Subroutine g khe e KEKE KER KHER RRR ERK REE KER ERE REE RE RK ehe eee ehe e e ede e eee e e eee Port0MonitorChanTx move b PGMTS A5 D3 read PGMTS to clear the bit jsr PortO0GMTCheck to make sure GMT 0 bra EndASR ends the CI Tx Port0MonitorChanRx move w POGMR A5 D3 read GMR jsr PortO0G
8. 0000 D0 DO P2SDR A5 0000 D0 DO P3SDR A5 0000 D0 DO PDROR A5 S0F000 D0 DO POICR A5 001B D0 D0 P2ICR A5 0000 D0 DO P3ICR A5 S8F1B D0 DO P1ICR A5 20 D2 D2 PGMTA A5 1F D0 DO P1GCIT A5 B1B2En A2 A2 D0 RTxCheck1 DO P1GMT A5 2 000000AA D0 S000000AA DO EndLoop2 Loop0 P1GMT A5 D2 00000100 D2 Freescale Semiconductor Inc portO off GCI B1 B2 on portl on S FSM GCI B1 B2 on port3 off Slave GCI B1 B2 on port2 off Slave GCI B1 B2 on M9 9e Ne Ne NPM disabled DCL 512kHz MULT 64 MUX FSC SIE delay Max delay at 512kHz 40 Total delay 20 but not used Total delay 20 but not used D channel off IE 0 GCI Interrupt Off B1 B2 D Interrupt Off Interrupt off on Port2 Interrupt off on Port3 IE 1 GCI Interrupts On B1 B2 Interrupts On Abort previous Portl GCI MC Portl Deactivation Request Send Monitor Channel MCF5272 Interrupt Service Routine For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Appendix A Software Configuration cmp 1 S0 D2 bne RTxCheck1 rts CICommand nop lea 1 CICom A2 jsr RCheck LoopCI move b A2 D0 andi 1 S000000FF DO jsr RCheck move b DO P1GCIT A5 cmp 1 1C D0 bne LoopCI rts CheckACK nop move b PGCITSR A5 D1 andi l 02 D1 cmp 1 802 D1 bne CheckACK rts RCheck nop move b P1GCIT A5 D2 andi 1 00000010 D2 cmp
9. 1 00000010 D2 beq RCheck rts WaitLoop nop Move 1 SFFF DO LoopGCI sub 1 1 D0 cmp 1 0 D0 bne LoopGCI rts The following file is used to configure the ColdFire CPU core Before using this file the user must check to make sure the configuration matches his requirements The file is as follows RegisterInit to initialize the registers cir l DO cir l D1 cir l D2 cir l D3 cir l D4 cir l D5 cir l D6 cir l D7 rts IntInit move l ZVBR Init DO to set the vector base reg movec DO VBR move w 2400 D0 to set the status register move w DO SR move b 40 D0 to point the interrupts move b DO PIVR A6 move 1 88888888 D0 Disable all type of ISR move 1 DO ICR1 A6 move 1 DO ICR3 A6 move 1 DO ICR4 A6 reset all types of interrupt move 1 S88EF8888 D0 PLIC APer Interrupt on level 7 move l DO ICR2 A6 PLIC Per Interrupt on level 6 MCF5272 Interrupt Service Routine For More Information On This Product Go to www freescale com move l move l move l move l move l move l rts Freescale Semiconductor Inc Appendix A Software Configuration 0 D0 DO PIWR A6 i PLIC Periodic D0 D0 i plic per vec i PLIC Aperiodic D0 D0 i plic aper vec this case No wake up process yet Point to the address vector M9 Ne Ne Point to the address vector e The final file represents the table allocation of configuration data that can be sent to the peripheral to control various funcions B
10. GMT 0 EndASR P2GMR A5 D3 Port2GMRCheck to make sure GMR 0 D3 D4 2 000000FF D4 00000035 D4 FirstByte2 D3 D4 2 000000FF D4 2 000000CF D4 SecondByte2 EndASR D3 D5 EndASR D3 D6 EndASR koe ee ee ee hehehe ee hehe ee ee ee e e e ee eee ehe eee ehe ee e hee e he deese ehe kkk kkk e eee eee e eee e Command Indicate Subroutine koe ee eee e e dee e e he he ee he e ee e he eee he ee e he eee ee ee e hee e he ehe ke e he he ke eee e eee eee e eee e Port2CommandIndTx move b jsr bra Port2CommandIndRx move l move b andi l cmp 1 beq cmp 1 beq cmp 1 beq cmp 1 beq bra 50 PGCITSR A5 D3 Port2RCheck EndASR 0 D3 P2GCIR A5 D3 S000000FF D3 00000010 D3 Port2DeacReq 00000018 D3 Port2ActInd 0000001C D3 EndASR S 0000001F D3 Port2DeacInd EndASR MCF5272 Interrupt Service Routine For More Information On This Product Go to www freescale com Port2DeacReq move b move b jsr bra Port2DeacConf bra Port2ActInd move b move b jsr bra Port2DeacInd move b move b jsr bra Freescale Semiconductor Inc Appendix A Software Configuration S1F D0 D0 P2GCIT A5 Port2RCheck EndASR EndASR 1C D0 dO P2GCIT A5 Port2RCheck EndASR S1F D0 DO P2GCIT A5 Port2RCheck EndASR g kc ee ee he dee EHR ERK REE RK KER EKER ERE RHE RE RHR ERK KEE ERR EERE RE REE RE eee de eee ee es Checking Subroutines g kk ee ee KKK ERK KR ERK REE KK REE KER ERE REE RE RHR ERK R
11. Information On This Product Go to www freescale com Freescale Semiconductor Inc Summary and Scope Contents 1 2 Contents Paragraph Number II 2 1 III 3 1 3 2 3 3 IV 4 1 4 2 4 2 1 4 2 2 4 3 4 3 1 4 3 2 5 1 2 2 5 3 VI 6 1 6 2 6 3 6 4 6 4 1 6 4 2 6 5 6 6 6 6 1 6 6 2 Title Inter Digital Link Mode of Operation Introduction General Circuit Interface Mode of Operation GCI History Monitor Channel Operation Command Indicate Operation GCI IDL to the MCF5272 Data Registers Monitor Channel Registers Monitor Channel Receive Monitor Channel Transmit Command Indicate Registers Command Indicate Receive Command Indicate Transmit Periodic Interrupt Process Bubbles Definitions One Port Processing Multi Ports Processing Aperiodic Interrupt Process Aperiodic One Port Sequence Multi Ports Case Brief Register Explanation Monitor Channel Sequence Transmit Sequence Receive Sequence Transmit Abort Condition Command Indicate Channel Transmit Sequence Receive Sequence MCF5272 Interrupt Service Routine For More Information On This Product Go to www freescale com Page oN U A A QN t tA Ann A d LUN WN e nm onm onm onm onm Lm mm Lm du oN NN A tA tA A O N N e Freescale Semiconductor Inc Summary and Scope Contents VII Assembly Code 19 7 1 Interrupt Controller 19 7 2 Interrupt Vector Generation 20 7 3 Prioritization Level ICR2 Register 21 7 4 Programmable Interrupt Vector Register PI
12. On This Product Go to www freescale com Freescale Semiconductor Inc Assembly Code MBAR Configuration MBASE 0x3C 7 6 5 4 3 2 1 0 Write IV7 IV6 IV5 Read IV7 IV6 IV5 O0 1111 Reset 0000 1111 Figure 19 Programmable Interrupt Vector Register Table 5 PIV Register Field Descriptions Bits Name Description 7 5 IV7 IV5 Interrupt vectors 7 5 These bits provide the three MSB s of the interrupt vector for interrupt acknowledge cycles from all sources To conform to ColdFire interrupt vector allocation these bits should be set equal to or greater than 010 This is the same as writing a value of 0x40 to the register 4 0 Reserved should be cleared 7 5 MBAR Configuration This is one of the first registers that should be written after reset MBAR configuration is arbitrarily set by the user 7 6 Hardware Configuration The evaluation board that is used in this setup is the M5272C3 The four ports are available through PCI sockets on the evaluation board Be sure that in addition to supplying the evaluation board with power the user supplies 5V to J7 which supplies power to the daughter cards connected into the PCI sockets The wire connection between the PC and the board is a BDM wiggler cable Depending on the tested registers the external environment could be either MC145572EVK U Transceiver oriented board or MC145574EVK T transceiver oriented board Alon
13. controller Part VIII Appendix A This appendix deals with an example of program that has been used to evaluate the MCF5272 Scope of the program The purpose of that program was not to productize the MCF5272 but to simply evaluate the silicon This is the reason why the internal architecture might not be optimized to the fullest Some knowledge of Freescale ISDN products is required in order to fully activate and send data over the data link For more information the user must refer to the MC145572 and MC145574 User s Manuals Once the hardware has been correctly set up see Figure 20 the NT configured MC145574 chip activates the NR2 to 0x1 down to the TE configured MC145574 device When the link is up and running NRI to 0x9 the TE must have the B1 and B2 channels on NR5 to OxC Once connected to the NT configured T chip the bit error rate tester HP 1645A sends data from the NT device through the link down to the TE device The purpose of MCF5272 is to capture the received data and to perform a loopback in the ColdFire core via the interrupt service routine The possible loopbacks that can be tested are all combinations of B channels or D channel by itself Due to the internal architecture and the special processing of the D channel the 2B D loopback cannot be performed The entire loopback process runs in the ISR The flow diagram of the program for both IDL and GCI modes except that there is no aperiodic interrupt in IDL mode is a
14. must be downloaded to the board via the BDM Shown below are all the files included in main s Configuration h is the file used for all the definition of the equates In order to save space only the important and used equates are shown i e the Initialization registers and the PLIC registers Default initial register values Most of the values are not used for the PLIC evaluation Module Regs Addr EQU 00300000 Addr of on chip reg Init MBAR EQU 10000001 MBAR value Init SCR EQU 0000 Init PMR EQU 0 Initial value of PMR UserProgram EQU 00020000 Put program in SDRAM Init SPR EQU S00E8 Initial value of SPR Init SCFR EQU 1211 Initial value of SCFR Init PIVR EQU 40 Initial value of PIVR VBR Init EQU 00000000 SRValue EQU 2500 LED EQU 3 ADDRESSES OF SYSTEM CONFIGURATION REGISTERS These are absolute addresses Sys Config Regs EQU 00000400 Absolute address of sers MBAR EQU Sys Config Regs 0 Module Base Add Register SCR EQU Sys Config Regs 4 System Config Register SPR EQU Sys Config Regs 6 System Protection Register PMR EQU Sys Config Regs 8 Power Management Register SCFR EQU Sys Config Regs C Synthesized Clock Freq DIR EQU Sys Config Regs 10 Device ID Register OFFSETS TO MODULES Offsets w r t contents of MBAR don t use directly use register names below Intc Reg Offset EQU 000 Offset of SIM s IntC Csel Reg Offset EQU 040 Offset of SIM s CSel Port Reg Offset EQU 080 Offset of SIM s Ports OS
15. the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part freescale semiconductor For More Information On This Product Go to www freescale com
16. vec i tim3 vec i tim4 vec i uartl vec i uart2 vec i plic per vec i plic aper vec i usb0 vec i usbl vec i usb2 vec i usb3 vec i usb4 vec i usb5 vec i usb6 vec i usb7 vec i dma vec i ether rx vec i ether tx vec i ether ntc vec i qspi vec int5 vec int6 vec berr handler aerr handler illeg handler divz handler chk handler trapv handler privv handler trace handler aline handler fline handler rsrv handler uninit handler spuri handler trap0 handler trapl handler trap2 handler trap3 handler trap4 handler trap5 handler trap6 handler trap7 handler trap8 handler trap9 handler trap10 handler trapll handler trapl2 handler trapl3 handler trapl4 handler trap15 handler mbar handler i spur handler intl handler DC DC L E DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L Freescale Semiconductor Inc Appendix A Software Configuration mbar handler mbar handler i spur handler intl handler int2 handler int3 handler int4 handler i timl handler Timer interrupt handler i tim2 handler Timer interrupt handler i tim3 handler Timer interrupt handler i tim4 handler Timer interrupt handler i uartl handler UART interrupt handler i uart2 handler UART interrupt handler i PLIC Periodic PLIC periodic interrupt i PLIC Aperiodic PLIC Aperiodic interrupt i usb0
17. 1B2En DC W DC W DC W DC W DC W DC W DC W DC W DC W B1B2Read DC W DC W BlSend CICom DC B TxData DC W B1B2Read DC W DC W BlSend CICom TxData 56 0125 01C0 03AA 0126 0180 03FF 0105 01EE 03FF 0135 03FF 00112233 A00A5FF5 F708D728 SFFFFFFFF 18 1C 95 SA5 SAA 03FF 0135 03FF 00112233 A00A5FF5 F708D728 SFFFFFFFF 18 1C 95 A5 AA Ne Ne Ne Ne Ne 9e Ne Ne Ne LIII M9 Ne 90 99 se Ne e M9 9 Ne Ne se Ne see MC145574 NR5 access Enabling the B1 B2 Channels End of sending should see SFF MC145574 NR5 access Enabling Loopabck End of sending Access to BR5 Send SEE End of sending Read NR5 End of Process Value written to TBx Value written to TBx Value written to TBx Value written to TBx Command Indicate Activation Request Command Indicate Activation Confirmed End of sending Read NR5 End of Process Value written to TBx Value written to TBx Value written to TBx Value written to TBx Command Indicate Activation Request Command Indicate Activation Confirmed MCF5272 Interrupt Service Routine For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Appendix A Software Configuration MCF5272 Interrupt Service Routine For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Appendix A Software Configuration 58 MCF5272 Int
18. 2 Interrupt Service Routine For More Information On This Product Go to www freescale com Freescale Semiconductor Inc General Circuit Interface Mode of Operation Monitor Channel Operation Frame Sync FSO pu Chek PA EL SRP RREREEEREEEEEREEREEEEERERE EEE Data Out Dout l N Ar n B1 Channel B2 Channel Monitor Channel D Channel CI A E Figure 3 GCI Frame 3 2 Monitor Channel Operation This feature is available only in GCI mode The monitor channel is used to access the internal registers of any GCI device in order to support maintenance channel operations All monitor channel messages are two bytes in length Each byte is sent twice to permit the receiving GCI device to verify data integrity In ISDN applications the monitor channel is used for access to the maintenance messages The A and E bits in the GCI channel are used to control and acknowledge monitor channel transfers between the MCF5272 and another GCI device Figure 4 shows the monitor channel protocol used When the monitor channel is inactive the A and E bits are both high The A and E bits are active when they are driven low during their respective bit times Note that pull up resistors are required on Din and Dout The E bit represents the transmission of a new monitor channel byte The A bit from the opposite direction is used to acknowledge the monitor channel byte transfer An idle monitor channel is indicated by both A and E bits being inacti
19. 3 USB3IPL2 USB2IPL1 USB2IPLO Reset 0000 0000 Figure 18 Interrupt Controller Register 2 For more explanation about the meaning of those bits the user should read the MCF5272 User s Manual Here is a brief summary ICRx bits xPIR When set to one the new IPL value is stored When set to zero the corresponding INTx interrupt latch and IPL level is unaffected Any pending interrupt on that line will remain pending xIPL 2 0 Interrupt Priority Level 1 7 When set to zero the corresponding INTx interrupt line is inhibited and will not generate interrupts Its state can still be read via the ISR1 register Otherwise the corresponding INT1x interrupt line is enabled and will generate an interrupt to the MCFE52xx core with the indicated priority level For more explanation about the meaning of these bits see the MCF5272 User s Manual 7 4 Programmable Interrupt Vector Register PIVR This register specifies the vector numbers which will be returned by the interrupt controller in response to interrupt acknowledge cycles for the various peripherals and discrete interrupt sources The high three bits of the vector number are programmed in the PIVR The low five bits are provided by the interrupt controller depending on the highest priority source which is currently active for the specific interrupt priority level IPL being responded to in the current acknowledge cycle MCF5272 Interrupt Service Routine For More Information
20. 35 D4 FirstByte3 D3 D4 S000000FF D4 S000000CF D4 SecondByte3 EndASR D3 D5 EndASR D3 D6 EndASR kk e ee ee he ehe ee hehe ee hehe e ee he e ee eee ehe eee hehe ee e he e e he ehe e eee e eek e eee ke P Command Indicate Subroutine gk ee ee he dee ee he de ee e ee e e he e ee e ee ehe eee e hee e he dee e e ehe e eee e eee e eee e Port3CommandIndTx move b jsr bra Port3CommandIndRx move l move b andi l cmp 1 beq cmp 1 beq cmp 1 beq cmp 1 beq bra Port3DeacReq move b move b jsr bra Port3DeacConf nop bra Port3ActInd move b move b jsr bra Port3DeacInd move b move b jsr bra PGCITSR A5 D3 Port3RCheck EndASR 0 D3 P3GCIR A5 D3 S000000FF D3 00000010 D3 Port3DeacReq 00000018 D3 Port3ActInd 0000001C D3 EndASR S0000001F D3 Port3DeacInd EndASR S1F D0 DO P3GCIT A5 Port3RCheck EndASR EndASR 1C D0 d0 P3GCIT A5 Port3RCheck EndASR S1F D0 DO P3GCIT A5 Port3RCheck EndASR g kk ee ee he ehe EHR ERK KERR RK KER E RRR ERE REE REE RE RK REE ERE ehe e eee e e eee His Checking Subroutines g kk e KEK e he ERK e hehe RK hehe EKER EERE RE RE RK RE e ee he RK e ehe RK ehe e eee e e eee Port3GMTCheck move w andi 1 cmp 1 bne rts 52 PASR A5 D4 to make sure GMT 0 00001000 D4 0 D4 Port3GMTCheck MCF5272 Interrupt Service Routine For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Append
21. 3RxD move b jsr bra se se Ne Port0TransmitB1 jsr move l jsr bra Port0TransmitB2 jsr move l jsr bra PortOTxD jsr move b jsr bra PortlTransmitBl jsr move l jsr bra PortlTransmitB2 jsr move l jsr bra PortlTxD jsr move b jsr bra Port2TransmitBl jsr move l jsr bra Port2TransmitB2 jsr move l jsr bra 40 Freescale Semiconductor Inc Appendix A Software Configuration P3BIRR A5 DO Port3BlRDFReset EndSR P3B2RR A5 D0 Port3B2RDFReset EndSR P3DRR A5 D6 Port3DRDFReset EndSR PortOBlTDESet D0 POBLITR A5 PortOBlTDEReset EndSR PortOB2TDESet DO POB2TR A5 PortOB2TDEReset EndSR PortODTDESet D6 PODTR A5 PortODTDEReset EndSR PortlBlTDESet D0 P1B1TR A5 PortlBlTDEReset EndSR Port1B2TDESet DO P1B2TR A5 Port1B2TDEReset EndSR Port 1DTDESet D6 P1DTR A5 PortlDTDEReset EndSR Port2BlTDESet D0 P2B1TR A5 Port2B1TDEReset EndSR Port2B2TDESet D0 P2B2TR A5 Port2B2TDEReset EndSR se Ne CE M9 9e 9 Ne kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk Transmit Procedure deck ecce ecce ec eec ecce ce e ke ce ec e ec ce ke e ce ke ec ce ke e ke ke ke e ke kc ke kA o kA kx ko kA ko ko kk Make sure CPU can write move to the register Make sure the bit is reset go to ISR end Make sure CPU can write move to the register Make sure the bit is reset go to ISR end MCF5272 Interrupt Service Routine For More Information On This Product
22. D7 andi l 2 000000F0 D7 mask D7 cmp 1 S0 D7 compare with 0 bne AperPortl go to AperPoprtl otherwise move w D1 D7 Store PASR into D7 andi l 2 00000F00 D7 mask D7 cmp 1 S0 D7 compare with 0 bne AperPort2 go to AperPort2 otherwise move w D1 D7 Store PASR into D7 andi 1l 2 0000F000 D7 mask D7 cmp 1 S0 D7 compare with 0 bne AperPort3 go to AperPort3 otherwise bra EndASR exit w o taking action AperPort0 move w D1 D7 Store PASR into D7 andi l S0000008 D7 mask D7 cmp 1 500000008 D7 compare with 8 beq PortO0CommandIndRx if equal go to CI Receive move w D1 D7 Store PASR into D7 andi l 00000004 D7 mask D7 MCF5272 Interrupt Service Routine For More Information On This Product Go to www freescale com Appendix A Software Configuration cmp 1 beq move w andi 1 cmp 1 beq move w andi 1 cmp 1 beq AperPortl move w move w andi 1 cmp 1 beq move w andi 1 cmp 1 beq move w andi 1 cmp 1 beq move w andi 1 cmp 1 beq AperPort2 move w move w andi 1 cmp 1 beq move w andi 1 cmp 1 beq move w andi 1 cmp 1 beq move w andi 1 cmp 1 beq AperPort3 move w move w andi 1 cmp 1 beq move w andi 1 cmp 1 beq move w andi 1 cmp 1 beq move w andi 1 cmp 1 beq 46 00000004 D7 Port0CommandIndTx D1 D7 00000002 D7 00000002 D7 Port0MonitorChanRx D1 D7 00000001 D7 00000001 D7 Port0MonitorChanTx PASR A5 D1 D1 D7
23. EE ERR EERE RE REE RE eee de eee ee Port2GMTCheck move w PASR A5 D4 to make sure GMT 0 andi 1l 800000100 D4 cmp 1 80 D4 bne Port2GMTCheck rts Port2GMRCheck move w PASR A5 D4 to make sure GMR 0 andi l 800000200 D4 cmp 1 80 D4 bne Port2GMRCheck rts Port2LCheck move w P2GMT A5 D4 to make sure L 0 andi l S00000200 D4 cmp 1 S0 D4 bne Port2LCheck rts Port2RTxCheck move w P2GMT A5 D4 to make sure R 0 andi l 800000100 D4 cmp 1 S0 D4 bne Port2RTxCheck rts Port2RCheck move b P2GCIT A5 D4 to make sure R 0 andi 1l S00000010 D4 cmp 1 S0 D4 bne Port2RCheck rts khe e ee ee e dee ee e he ke e hehe eee hee e ehe ee ehe eee ehe e he he eee esee eee e eee e eee e P Port3 Subroutines g khe eee ee he dee ee he de ee hee e e e hee ee hee ehe eee e ehe ee e hee e e ehe eee e eee e e eee e Monitor Channel Subroutines e e ee ee he dee ee he he ee he e e e e he e ee he ee ehe ke eee hee e he he ee e esee eee e eee e eee ee Port3MonitorChanTx move b PGMTS A5 D3 jsr Port3GMTCheck to make sure GMT 0 bra EndASR Port3MonitorChanRx move w P3GMR A5 D3 jsr Port3GMRCheck to make sure GMR 0 move w D3 D4 MCF5272 Interrupt Service Routine For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Appendix A Software Configuration andi 1 cmp 1 beq move w andi 1 cmp 1 beq bra FirstByte3 move w bra SecondByte3 move w bra 2 000000FF D4 8000000
24. EndASR PortlMonitorChanRx move w P1GMR A5 D3 jsr Port1GMRCheck to make sure GMR 0 move w D3 D4 andi 1l 2 000000FF D4 cmp 1 800000035 D4 beq FirstBytel move w D3 D4 andi l S000000FF D4 cmp 1 S000000CF D4 beq SecondBytel bra EndASR 48 MCF5272 Interrupt Service Routine For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Appendix A Software Configuration FirstBytel move w D3 D5 bra EndASR SecondBytel move w D3 D6 bra EndASR Port1CommandIndTx move b PGCITSR A5 D3 jsr Port1RCheck bra EndASR g koe ee ee ee he de he e KEKE KKK EERE RE KER EKER KK RE KH REE KK ehe ke e eee ee ee e eee e eee de eee dee Command Indicate Subroutine koe ee ee ee he de he e e he de ee ee eee hee ee hee ee eee e ehe ee hehe ee e ehe e e hee eee e e dee e e eee de eee ee Port1CommandIndRx move 1 0 D3 move b P1GCIR A5 D3 andi 1l S000000FF D3 cmp 1 800000010 D3 beq Port1DeacReq cmp 1 S00000018 D3 beq PortlActInd cmp 1 S0000001C D3 beq EndASR cmp 1 S0000001F D3 beq PortlDeacInd bra EndASR Port1DeacReq move b S1F D0 move b DO P1GCIT A5 jsr PortlRCheck bra EndASR PortlDeacConf nop bra EndASR PortlActInd move b 1C D0 move b d0 P1GCIT A5 jsr Port1RCheck bra EndASR PortlDeacInd move b S1F D0 move b DO P1GCIT A5 jsr Port1RCheck bra EndASR khe ee ee ee he dee ee he he ee he he e e KR EEK ERE RE REE RE RHEE RRR EERE EERE RE e eee e ee
25. Freescale Semiconductor Order Number AN2184 D Rev 1 1 10 2001 68KOldFIRE IC RO PRO CES SORS Application Note MCF5272 Interrupt Service Routine for the Physical Layer Interface Controller Jean Louis Dolmeta Networking and Computing Systems Group Part Summary and Scope 1 1 Overview The physical layer interface controller PLIC is a peripheral module of the ColdFire MCF5272 intended to support ISDN applications such as CODECs ISDN transceivers and other peripherals The PLIC supports two modes of operation IDL and GCI physical layer protocols It also has four dedicated TDM ports for connecting to external devices This document consists of four main parts A brief description of the inter digital link IDL mode of operation The general circuit interface GCI explanation 3 A description of the interrupt service routine used to handle the data transfer for both modes of operation 4 Someexamples of ColdFire microprocessor assembly code to perform quick evaluation of the MCF5272 See Part VIII Appendix A The reader is strongly recommended to read the MCF5272 User s Manual at www mot com ColdFire before going through this document The register and bit explanations therein help the reader to better understand the device s internal architecture Freescale Semiconductor Inc 2004 All rights reserved t freescale semiconductor Motorola Inc 2001 All rights reserved For More
26. IC Reg Offset 88 Port Status Port2 P3PSR EQU PLIC Reg Offset 8A Port Status Port3 PASR EQU PLIC Reg Offset 8C Aperiodic Status Reg PLCR EQU PLIC Reg Offset 8F Loopback Control PDROR EQU PLIC Reg Offset 92 D Channel Request POSDR EQU PLIC Reg Offset 94 Sync Delay Port0 P1SDR EQU PLIC Reg Offset 96 Sync Delay Portl P2SDR EQU PLIC Reg Offset 98 Sync Delay Port2 P3SDR EQU PLIC Reg Offset 9A Sync Delay Port3 PCSR EQU PLIC Reg Offset 9E Clock Select Shown below are the interrupt vector file As long as the purpose of this evaluation is PLIC oriented not all vectors need to correspond to a real ISR address MCF5272 Interrupt Service Routine For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Appendix A Software Configuration reset vec berr vec aerr vec illeg vec divz vec chk vec trapv vec privv vec trace vec aline vec fline vec resl2 vec resl3 vec resl4 vec uninit vec resl6 vec resl7 vec resl8 vec res19 vec res20 vec res21 vec res22 vec res23 vec spuri vec res25 vec res26 vec res27 vec res28 vec res29 vec res30 vec res3l vec trap0 vec trapl vec trap2 vec trap3 vec trap4 vec trap5 vec trap6 vec trap7 vec trap8 vec trap9 vec trapl0 vec trapll vec trapl2 vec trapl3 vec trapl4 vec trapl5 vec res48 vec res49 vec res50 vec res5l vec res52 vec res53 vec res54 vec res55 vec res56 vec res57 vec res58 vec res59 vec res60 vec res6l
27. LT mi IE eur EE End a el dd i ToU ee e esse PES B1 Channel B2 Channel D Channel Figure 2 IDL 8 bit Mode For more information about the different configurations of IDL please refer to any ISDN product user s manual such as the MC145574 572 or MC145576 at http www freescale com Part Ill General Circuit Interface Mode of Operation 3 1 GCI History The GCI mode was defined by European companies Italtel Siemens Alcatel and GPT GCI is a time division multiplex TDM bus that combines the ISDN 2B D data control and status information onto four signal pins Some benefits of the GCI include the following Operation and maintenance features Activation and deactivation facilities via CI channel Well defined transmission protocols to ensure correct information transfer between GCI compatible devices Point to point and multi point communication links Multiplexed mode of operation where up to eight GCI channels can be combined to form a single data stream Those four signals consist of the following FSC frame synchronization 8 kHz frame pulse DCL data clock signal two clocks per data bit Din data in the data in Dout data out This pin is an open drain output and must be pulled to Vdd through a 1 2 kQ resistor The GCI frame structure has the following format two B channels a monitor channel the ISDN D channel the command indicate channel and the A and E bits The frame is shown in Figure 3 MCF527
28. MRCheck to make sure R 0 move w D3 D4 Save D3 into D4 andi l 2 000000FF D4 cmp 1 00000035 D4 to access to NR5 MC145574 beq FirstByte if equal go to FirstByte move w D3 D4 otherwise continue andi 1 2 000000FF D4 cmp 1 S000000CF D4 SCF is NR5 Value of MC145574 beq SecondByte if equal go to SecondByte bra EndASR ends the ISR FirstByte move w D3 D5 move D3 into D5 to check bra EndASR SecondByte move w D3 D6 move D3 into D6 to check bra EndASR g ke ee ee eee ee e e ee e de ee e ede ee he de ee he e eee hee ee he eee eee eee e eee e ee eee eee e Command Indicate Subroutine khe dece ee eee e ee hee e hehe ee e e he e e hehe ee he e ee e he e ee hee ee ee ee e eee eee e ee ee e eee e Port0CommandIndTx move 1 PGCITSR A5 D3 clear the bit jsr PortORcheck to make sure R 0 bra EndASR Port0CommandIndRx move l 0 D3 move b POGCIR A5 D3 Move GCRO into D3 andi l 2 000000FF D3 cmp 1 2 00000010 D3 Deactivation Request beq Port0DeacReq cmp 1 00000018 D3 Activation Indication Value beq Port0Actind cmp 1 0000001C D3 Activation Confirmed beq EndASR nothing to do cmp 1 S S0000001F D3 Deactivation Indication beq Port0DeacInd bra EndASR Port0DeacReq move b S1F D0 Send Deactivation Indication move b DO POGCIT A5 in response of dea Request jsr PortORcheck to make sure R 0 bra EndASR Port0DeacConf nop nothing else to do MCF5272 Interrupt Service Routine For More Information On This
29. MT Register Field Descriptions 8 Table 3 PnGCIR Register Field Descriptions 9 Table 4 PnGCIT Register Field Descriptions 10 Table 5 PIV Register Field Descriptions 24 Table 6 Port Pins Assignment 25 Table 7 Port Control Register Values 26 Part I Interchip Digital Link Mode of Operation 2 1 Introduction The IDL mode of operation is a four wire interface used for full duplex communication between ICs at the board level This interface consists of a transmit path a receive path an associated clock and a synchronization signal These signals are known as Dout Din DCL and FSC The clock determines the rate of exchange of data in both transmit and receive directions and the sync controls when this exchange is to take place Three channels of data are exchanged every 125 microseconds These channels consist of two 64 kbps B channels and one 16 kbps D channel used for full duplex communication The waveform diagrams are shown in Figure 1 and Figure 2 Two modes are available e The 10 bit mode mmesmeso 1 d a ex OL NANNA Data ni OIL Data Out bou TEE Y D1 Channel Dummy Bit D2 Channel B1 Channel B2 Channel Figure 1 IDL 10 bit Mode 4 MCF5272 Interrupt Service Routine For More Information On This Product Go to www freescale com Freescale Semiconductor Inc General Circuit Interface Mode of Operation GCI History The 8 bit mode Frame Sync FSC Data Clock DCL NT mii I Mi iii iii IE LU I U
30. PI Reg Offset EQU 0A0 Offset of OSPI module PWM Reg Offset EQU 0C0 Offset of PWM module DMA Reg Offset EQU SOEO Offset of DMA module Uartl Reg Offset EQU 100 Offset of UART module Uart2 Reg Offset EQU 140 Offset of UART module SDRAM Reg Offset EQU 180 Offset of SDRAM module Timer Reg Offset EQU 200 Offset of Timer module PLIC Reg Offset EQU 300 Offset of PLIC module Ether Reg Offset EQU 800 Offset of Ethernet module USB Reg Offset EQU 1000 Offset of USB module MCF5272 Interrupt Service Routine For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Appendix A Software Configuration SIM INTERRUPT CONTROLLER REGISTERS ICR1 ICR2 ICR3 ICR4 ISR PITR PIWR PIVR EQU EQU EQU EQU EQU EQU EQU EQU Intc_Reg Offset 20 Intc Reg Offset 24 Intc Reg Offset 28 Intc Reg Offset 2C Intc Reg Offset 30 Intc Reg Offset 34 Intc Reg Offset 38 Intc Reg Offset 3F SIM CHIP SELECT REGISTERS BRO ORO BR1 OR1 BR2 OR2 BR3 OR3 BR4 OR4 BR5 OR5 BR6 OR6 BR7 OR7 SIM PORTS REGISTERS PACNT PADDR PADAT PBCNT PBDDR PBDAT EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU Csel Reg Offset 0 Csel Reg Offset 4 Csel Reg Offset 8 Csel Reg Offset C Csel Reg Offset 10 Csel Reg Offset 14 Csel Reg Offset 18 Csel Reg Offset 1C Csel Reg Offset 20 Csel Reg Offset 24 Csel Reg Offset 28 Cse
31. Product Go to www freescale com Freescale Semiconductor Inc Appendix A Software Configuration bra EndASR PortOActInd move b 1C D0 Send Activation Indication move b d0 POGCIT A5 jsr PortORCheck bra EndASR PortODeacInd move b S1F D0 Send Deactivation Indication move b DO POGCIT A5 jsr PortORCheck bra EndASR g kc eee e ee he dee ee he de ee he de ee e hehe ee hehe e ehe e eee eee eee e e dee ke eee eee hee eee hee e ke ee e ee oe Checking Procedure g kk eee ee EEK HR ERK he he ERK REE RRR EKER EEK KER ERE RHR EERE RE e ehe hee ee hehe e e ee e de ee Port0GMTCheck move w PASR A5 D3 to make sure GMT 0 andi 1l S00000001 D3 cmp 1 7 0 D3 bne PortO0GMTCheck rts PortOGMRCheck move w PASR A5 D4 to make sure GMR 0 andi l 800000002 D4 cmp 1 S0 D4 bne PortO0GMRCheck rts Port0LCheck move wW POGMT A5 D3 to make sure L 0 andi l S00000200 D3 cmp 1 7 0 D3 bne PortORTxCheck rts PortORTxCheck move w POGMT A5 D3 to make sure R 0 andi l S00000100 D3 cmp 1 7 0 D3 bne PortORTxCheck rts PortORCheck move b POGCIT A5 D3 to make sure R 0 andi l S00000010 D3 cmp 1 7 0 D3 bne PortORCheck rts kk e ee ee he ehe ee he he ee he e e ee hee ee eee ehe eee hehe ee he he e e e ehe e e ee e eee de eee e P Portl Subroutines g Kk ee ee he ehe ee he de ee he ee e e hee ee eee hehe ke ee e eee he dee e e eee eee e eee e eee e PortlMonitorChanTx move b PGMTS A5 D3 jsr Port1GMTCheck to make sure GMT 0 bra
32. R A5 D2 Read ICRO to make sure BlTIE andi l S00000008 D2 is set cmp 1 S00000008 D2 bne EndPortOTxB1l move l D1 D7 BITDE Test andi l S00000008 D7 cmp 1 S00000008 D7 beq PortOTransmitBl go to Transmit Bl if bit set EndPortOTxBl move w POICR A5 D2 Read ICRO to make sure B2RIE andi l S00000002 D2 is set cmp 1 800000002 D2 bne EndPortORxB2 move l D1 D7 R2RDF Test andi l S00000002 D7 cmp 1 800000002 D7 beq Port 0ReadB2 Go to read B2 if bit set EndPortORxB2 move w POICR A5 D2 andi 1l 800000010 D2 cmp 1 800000010 D2 bne Port0D move l D1 D7 B2TDE Test andi l S00000010 D7 cmp 1 S00000010 D7 beq Port0TransmitB2 go to Transmit B2 if bit set PortOD move w POICR A5 D2 Read ICRO to make sure DRIE andi 1 00000004 D2 is set cmp 1 00000004 D2 bne EndPortORx if not go to next source move l D1 D7 DRIE is set needs to andi 1 00000004 D7 receive the D data cmp 1 00000004 D7 beq PortORxD Go to Read D if bit set EndPortORx move w POICR A5 D2 Read ICRO DTIE to make andi 1 00000020 D2 sure the bit is set cmp 1 00000020 D2 bne PortlTest go to next port move l D1 D7 DTDE Test andi 1 00000020 D7 cmp 1 00000020 D7 beq PortOTxD PortlTest move w PlICR A5 D1 IE Test on Portl MCF5272 Interrupt Service Routine For More Information On This Product Go to www freescale com Appendix A Software Configuration andi 1 cmp 1 bne PortlInt
33. TE1 BYTEI BYTE2 BYTE2 NULL NULL NULL Din Ebit Dout A bit l f f l Figure 4 Monitor Channel Protocol 6 MCF5272 Interrupt Service Routine For More Information On This Product Go to www freescale com Freescale Semiconductor Inc GCIIDL and the MCF5272 Command Indicate Operation 3 3 Command Indicate Operation The command indicate or C I channel is used to activate and deactivate any GCI devices Some control functions such as loopbacks are also supported over the C I channel C I codes are four bits in length and must be received for two consecutive GCI frames before they are acted on C I channel bits are numbered bit 3 through 0 with bit 3 being the most significant The C I channel bits are transmitted starting with bit 3 Part IV GClI IDL and the MCF5272 This section gives a brief description of the internal registers in the PLIC 4 1 Data Registers For both GCI and IDL modes of operation the maximum data rate transmitted for each digital port is 144 kbps two 64 kbps B channels and one 16 kbps D channel Frames of B1 B2 and D channels are packed together in PnRBx PnTBx registers with x 1 2 3 4 for receive and transmit direction respectively Since the reception and transmission of information on the GCT IDL interface is deterministic a common interrupt is generated at 2 kHz It is expected that a common interrupt service routine will be programmed to service the transmit and receive registers After res
34. VR 22 7 5 MBAR Configuration 22 7 6 Hardware Configuration 22 7 7 Software Configuration 23 7 7 1 Customer Premises Equipment Software 23 7 7 2 ColdFire Port Configuration 23 7 1 3 Debugger Configuration 25 VIII Appendix A 26 FIGURES and TABLES Item Title Page Figure 1 IDL 10 Bit Mode 4 Figure 2 IDL 8 Bit Mode 5 Figure 3 GCI Frame 6 Figure 4 Monitor Channel Protocol 6 Figure 5 GCI Monitor Channel Receive Register 7 Figure 6 GCI Monitor Channel Transmit Register 8 Figure 7 PnGCIR Register 9 Figure 8 PnGCIT Register 10 Figure One Port Processing Interrupt Service Routine Flow Diagram 13 Figure 10 Multi Port Processing Interrupt Service Routine Flow Diagram 14 Figure 11 One Port Processing Aperiodic Interrupt Service Routine Flow Diagram 15 Figure 12 Multi Processing Aperiodic Interrupt Service Routine Flow Diagram 16 Figure 13 Monitor Channel Transmit Sequence Flow Diagram 17 Figure 14 Monitor Channel Receive Sequence Flow Diagram 18 Figure 15 Transmit Abort Condition Flow Diagram 19 Figure 16 CI Transmit Sequence Flow Diagram 20 Figure 17 CI Receive Sequence Flow Diagram 21 Figure 18 Interrupt Control Register 2 23 MCF5272 Interrupt Service Routine For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Interchip Digital Link Mode of Operation Introduction Figure 19 Programmable Interrupt Vector Register 24 Figure 20 Hardware Configuration 25 Table 1 PnGMR Register Field Descriptions 8 Table 2 PnG
35. ary the port control registers values are Table 7 Port Control Register Values Port Control Register Indirect Mode Hex Direct Mode Hex PACNT MBAR 0x80 PDCNT MBAR 0x98 55150000 00000105 55158000 00000905 7 7 3 Debugger Configuration Once the code has been compiled with the Diab compiler to the file main elf the user can download it to the M5272C3 evaluation board via the BDM cable The configuration file is as follows 0x00000000 0x00000000 set vectbase set vectaddr MBAR RAMBAR 0x10000001 0x20000001 2MB FLASH on CSO at OxFFE00000 write 1 0x10000040 0xFFE00201 write 1 0x10000044 20xFFE00014 Nothing on CS1 at 0x00000000 write 1 0x10000048 0x00000000 write 1 0x1000004C 0x00000000 External FSRAM on CS2 at 0x30000000 write 1 0x10000050 0x30000001 write l 0x10000054 0xFFF80008 26 MCF5272 Interrupt Service Routine For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Appendix A Software Configuration Nothing on CS3 at 0x00000000 write 1 0x10000058 0x00000000 write 1 0x1000005C 0x00000000 CS7 from address 0x00000000 4M byte SDRAM write 1 0x10000078 0x00000701 write 1 0x1000007C OxFFC0007c setup SDRAM Timing and Control Registers SDCTR then SDCCR write 1 0x10000184 0x0000f415 write 1 0x10000180 0x00004211 rem initialize SDRAM with a write write r 0x00040000 0x55555555 STARTS SDRAM
36. d be cleared 4 F Full This bit is set by the C I channel controller to indicate to the CPU that new C I channel data has been received and is available for processing It is automatically cleared by a CPU read The clearing of this bit by reading this register also clears the aperiodic GCR interrupt 3 0 C3 CO C I bits These four bits are received on the GCI or SCIT channel 0 When a change in the C I data value is received in two successive frames it is interpreted as being valid and is passed on to the CPU via this register A maskable interrupt is generated when data is written into any of the four available positions 4 3 2 Command Indicate Transmit The PnGCIT registers are 8 bit registers containing the monitor channel bits to be transmitted for each of the four ports on the MCF5272 The register is shown in Figure 8 and described in Table 4 MCF5272 Interrupt Service Routine For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Periodic Interrupt Process ISR Bubble Definitions 7 5 4 3 2 1 0 Field F C3 C2 C1 CO Read R W Reset 0000 0000 Figure 8 PnGCIT Register Table 4 PnGCIT Register Field Descriptions Bits Name Description 7 5 Reserved should be cleared 4 R Ready This bit is set by the CPU to indicate to the C I channel controller that data is ready for transmission Setting this bit starts the C I
37. e Information On This Product andi 1 cmp 1 beq Port2Test move w andi 1 cmp 1 bne Port2Int nop move w move 1 andi 1 cmp 1 beq move w andi 1 cmp 1 bne move 1 andi 1 cmp 1 beq EndPort2RxBl move w andi 1 cmp 1 bne move l andi l cmp 1 beq EndPort2TxB1 move w andi 1 cmp 1 bne move l andi l cmp 1 beq EndPort2RxB2 move w andi l cmp 1 bne move l andi l cmp 1 beq Port2D move w andi 1 cmp 1 bne move l andi l cmp 1 beq 00000020 D7 00000020 D7 Port1TxD P2ICR A5 D1 00008000 D1 00008000 D1 Port3Test P2PSR A5 D1 D1 D7 0000003F D7 7 0 D7 Port3Test P2ICR A5 D2 00000001 D2 00000001 D2 EndPort2RxB1 D1 D7 00000001 D7 00000001 D7 Port2ReadBl P2ICR A5 D2 00000008 D2 00000008 D2 EndPort2TxB1 D1 D7 00000008 D7 00000008 D7 Port2TransmitBl P2ICR A5 D2 00000002 D2 00000002 D2 EndPort2RxB2 D1 D7 00000002 D7 00000002 D7 Port2ReadB2 P2ICR A5 D2 00000010 D2 00000010 D2 Port2D D1 D7 00000010 D7 00000010 D7 Port2TransmitB2 P2ICR A5 D2 00000004 D2 00000004 D2 EndPort2Rx D1 D7 00000004 D7 00000004 D7 Port2RxD Freescale Semiconductor Inc Appendix A Software Configuration IE Test on Port2 Port2 BIRDF Test BITDE Test B2RDF Test B2TDE Test DRDF Test MCF5272 Interrupt Service Routine For More Information On This Product Go to www freescale com Appendix A Softwa
38. e e 7 Checking Procedures koe ee KEK HK EEK KEKE RK KEE RK KER E KER EKER EK RE RHR ERK KEE ERR EERE ER ERE EERE Port1GMTCheck move w PASR A5 D4 to make sure GMT 0 andi 1 00000010 D4 cmp 1 80 D4 bne Port 1GMTCheck rts PortlGMRCheck move w PASR A5 D4 to make sure GMR 0 andi 1 00000020 D4 cmp 1 S0 D4 bne Port1GMRCheck rts PortlLCheck move w P1GMT A5 D4 to make sure L 0 andi 1 800000200 D4 cmp 1 S0 D4 MCF5272 Interrupt Service Routine For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Appendix A Software Configuration bne rts Port1RTxCheck move w andi 1 cmp 1 bne rts Port1RCheck move b andi 1 cmp 1 bne rts Port1LCheck P1GMT A5 D4 to make sure R 0 00000100 D4 0 D4 Port1RTxCheck P1GCIT A5 D4 to make sure R 0 800000010 D4 0 D4 Port1RCheck kk e ee ee he dee KKK EEK KER ERK KER EKER KR ER EKER KR he ERE ehe e ERE eee de eee e P Port2 Subroutines eckokckckckckckckckckokckckckckckckckckckckckckckckckckckckckck ckckockckckck ck ckckckck ckckockckockck ck ckockockckckckockckck kk M Mos Port2MonitorChanTx move b jsr bra Port2MonitorChanRx move w jsr move w andi 1 cmp 1 beq move w andi l cmp 1 beq bra FirstByte2 move w bra SecondByte2 move w bra Monitor Channel Subroutines kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk PGMTS A5 D3 Port2GMTCheck to make sure
39. e e e ee x Bx TDE Reset g khe ee ee he ehe ee he he ke e he ee ee he ee ee ke e eee ee eee eee e e ek PortOBlTDEReset nop move w andi l cmp 1 bne rts Port0B2TDEReset nop move w andi 1l cmp 1 bne rts PortODTDEReset nop move w andi l cmp 1 bne rts Port1B1TDEReset nop move w andi l cmp 1 bne rts Port1B2TDEReset nop move w andi l cmp 1 bne rts Port1DTDEReset nop move w andi l cmp 1 bne rts Port2B1TDEReset nop move w andi 1l cmp 1 bne rts Port2B2TDEReset nop move w andi 1l cmp 1 bne rts Port2DTDEReset nop move w andi l cmp 1 bne rts Port3B1TDEReset nop move w andi 1l cmp 1 bne rts 44 POPSR A5 D3 to make sure BITDE is Reset 00000008 D3 00000000 D3 Port0B1TDEReset POPSR A5 D3 to make sure B2TDE is Reset S00000010 D3 00000000 D3 Port0B2TDEReset POPSR A5 D3 00000020 D3 00000000 D3 PortODTDEReset P1PSR A5 D3 00000008 D3 00000000 D3 Port1B1TDEReset P1PSR A5 D3 00000010 D3 00000000 D3 Port1B2TDEReset P1PSR A5 D3 00000020 D3 00000000 D3 Port 1DTDEReset P2PSR A5 D3 00000008 D3 00000000 D3 Port2B1TDEReset P2PSR A5 D3 00000010 D3 00000000 D3 Port2B2TDEReset P2PSR A5 D3 00000020 D3 00000000 D3 Port2DTDEReset P3PSR A5 D3 00000008 D3 00000000 D3 Port3B1TDEReset MCF5272 Interrupt Service Routine For More Information On This Product Go to www freescale com
40. en this RAM will be selected by one of the programmable chip selects So upon system startup there is a brief period where RAM is not available for the stack To ensure no problems resulting from interrupts particularly of priority level 7 during this period there is an interlock which prevents any interrupt from reaching the ColdFire core until the first write cycle to the programmable interrupt vector register PIVR The user should ensure that both RAM chip selects and the system stack are set up prior to this write operation The interrupt controller includes daisy chaining functions in order to avoid contention when the ColdFire core issues an interrupt acknowledge cycle So if more than one interrupt source has the same interrupt priority level IPL they are daisy chained with INT1 being the highest priority There are four interrupt control registers which control the interrupt priorities for the external general purpose latched interrupt input signals and the internal I O modules signals These registers allow software to reset any pending interrupts from these external interrupt lines or internal modules There are up to 32 interrupt inputs each of which has four bits assigned to it in these registers The registers can be read or written at any time When read the data returned is the last value that was written to the register with the exception of the reset bits which are transitory functions The registers can be accessed by either lo
41. errupt Service Routine For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Appendix A Software Configuration MCF5272 Interrupt Service Routine For More Information On This Product Go to www freescale com Freescale Semiconductor Inc How to Reach Us Home Page www freescale com E mail support freescale com USA Europe or Locations Not Listed Freescale Semiconductor Technical Information Center CH370 1300 N Alma School Road Chandler Arizona 85224 1 800 521 6274 or 1 480 768 2130 support freescale com Europe Middle East and Africa Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen Germany 44 1296 380 456 English 46 8 52200080 English 49 89 92103 559 German 33 1 69 35 48 48 French support freescale com Japan Freescale Semiconductor Japan Ltd Headquarters ARCO Tower 15F 1 8 1 Shimo Meguro Meguro ku Tokyo 153 0064 Japan 0120 191014 or 81 3 5437 9125 support japan freescale com Asia Pacific Freescale Semiconductor Hong Kong Ltd Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 800 2666 8080 support asia freescale com For Literature Requests Only Freescale Semiconductor Literature Distribution Center P O Box 5405 Denver Colorado 80217 1 800 441 2447 or 303 675 2140 Fax 303 675 2150 LDCForFreescaleSemiconductor hibber
42. et the B and D channel shift registers and shadow registers are initialized to all 1 s For more information about the data registers please refer to the MCF5272 User s Manual 4 2 Monitor Channel Registers This section describes receive and transmit channels 4 2 1 Monitor Channel Receive The PnGMR registers are 16 bit registers containing the received monitor channel bits for each of the four receive ports on the MCF5272 A byte of monitor channel data received on a certain port is put into an associated register using the format shown in Figure 5 and described in Table 1 A maskable interrupt is generated when a byte is written into any of the four available MCF5272 ports 15 11 10 9 8 7 0 Addr MBAR 0x360 POGMR 0x362 P1GMR 0x364 P2GMR 0x366 PSGMR Figure 5 GCI Monitor Channel Receive Register PhGMR MCF5272 Interrupt Service Routine For More Information On This Product Go to www freescale com Freescale Semiconductor Inc GCIADL and the MCF5272 Monitor Channel Registers Table 1 PnGMR Register Field Descriptions Bits Name Description 15 11 Reserved should be cleared 10 EOM End of message 0 Default at reset 1 Indicates to the CPU that an end of message condition has been recognized on the E bit EOM is automatically cleared when the PnGMR register has been read by the CPU 9 AB Abort O Default at reset 1 Indicates that the GCI controller has recognized an abort condition and
43. et the program counter will enter the 7 every time an Interrupt has been handled the program counter exits 7 7 ISR again goce ee e ERE RK he e e KER HR ERE RE RK RE RK REE EHR EEK KER ERK ERE KER ERE REE KERR ER e eee e DO D1 D2 D3 D4 D5 D6 D7 Ne Ne Ne Ne Ne Ne Ne Ne is is is is is is is used used used used used used used for for for for for LED for Data recovering the PnPSR checking the T RIE bits by reading PnICR checking bits B2 Data in case of crossing the B1 B2 data if necessary D channel for comparing values i PLIC Periodic Port0Test move w POICR A5 D1 Interrupt Config Register 34 andi 1 00008000 D1 Mask the IE bit cmp 1 S 00008000 D1 compare bne PortlTest Go to Portl move w POPSR A5 D1 Port0 is the cause move l D1 D7 Save D1 into D7 MCF5272 Interrupt Service Routine For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Appendix A Software Configuration andi l S 0000003F D7 mask with all Port0 bits cmp 1 S0 D7 compare to 0 beq PortlTest go to Portl if not equal PortOInt move w POICR A5 D2 Read ICRO andi 1 S 00000001 D2 to make sure BIRIE is set cmp 1 S00000001 D2 bne EndPortORxBl if not go to next interrupt move l D1 D7 POPSR check andi 1 00000001 D7 D1 has the PLPSPO value cmp 1 S00000001 D7 beq Port0ReadB1 Go to read Bl if bit set EndPortORxBl move w POIC
44. g Portl PLCR2 EQU PLIC Reg Offset 54 GCI IDL config Port2 PLCR3 EQU PLIC Reg Offset 56 GCI IDL config Port3 POICR EQU PLIC Reg Offset 58 GCI Int config Port0 P1ICR EQU PLIC Reg Offset 5A GCI Int config Portl P2ICR EQU PLIC Reg Offset 5C GCI Int config Port2 P3ICR EQU PLIC Reg Offset 5E GCI Int config Port3 POGMR EQU PLIC Reg Offset 60 GCI Monitor RX Port0 P1GMR EQU PLIC Reg Offset 62 GCI Monitor RX Portl P2GMR EQU PLIC Reg Offset 64 GCI Monitor RX Port2 P3GMR EQU PLIC Reg Offset 66 GCI Monitor RX Port3 POGMT EQU PLIC Reg Offset 68 GCI Monitor TX Port0 P1GMT EQU PLIC Reg Offset S6A GCI Monitor TX Portl P2GMT EQU PLIC Reg Offset 6C GCI Monitor TX Port2 P3GMT EQU PLIC Reg Offset 6E GCI Monitor TX Port3 PGMTS EQU PLIC Reg Offset 71 GCI Monitor TX status PGMTA EQU PLIC Reg Offset 72 GCI Monitor TX abort POGCIR EQU PLIC Reg Offset 74 GCI C I RX Porto P1GCIR EQU PLIC Reg Offset 75 GCI C I RX Portl P2GCIR EQU PLIC Reg Offset 76 GCI C I RX Port2 P3GCIR EQU PLIC Reg Offset 77 GCI C I RX Port3 POGCIT EQU PLIC Reg Offset 78 GCI C I TX Porto P1GCIT EQU PLIC_Reg Offset 79 GCI C I TX Portl P2GCIT EQU PLIC Reg Offset 7A GCI C I TX Port2 P3GCIT EQU PLIC Reg Offset 7B GCI C I TX Port3 PGCITSR EQU PLIC Reg Offset 7F GCI C I TX status PDCSR EQU PLIC Reg Offset 83 D Channel Status POPSR EQU PLIC Reg Offset 84 Port Status Port0 P1PSR EQU PLIC_Reg Offset 86 Port Status Portl P2PSR EQU PL
45. g Offset 0C PLIC Reg Offset 10 PLIC Reg Offset 14 Bl Data Receive Port0 Bl Data Bl Data Bl Data B2 Data B2 Data MCF5272 Interrupt Service Routine For More Information On This Product Go to www freescale com Receive Receive Receive Receive Receive Portl Port2 Port3 Port0 Portl Freescale Semiconductor Inc Appendix A Software Configuration P2B2RR EQU PLIC Reg Offset 18 B2 Data Receive Port2 P3B2RR EQU PLIC Reg Offset 1c B2 Data Receive Port3 PODRR EQU PLIC Reg Offset 20 D Data Receive Port0 P1DRR EQU PLIC_Reg Offset 21 D Data Receive Portl P2DRR EQU PLIC Reg Offset 22 D Data Receive Port2 P3DRR EQU PLIC Reg Offset 23 D Data Receive Port3 POBITR EQU PLIC Reg Offset 28 Bl Data Transmit Porto P1B1TR EQU PLIC Reg Offset 2C Bl Data Transmit Portl P2B1TR EQU PLIC Reg Offset 30 Bl Data Transmit Port2 P3B1TR EQU PLIC Reg Offset 34 Bl Data Transmit Port3 POB2TR EQU PLIC Reg Offset 38 B2 Data Transmit Porto P1B2TR EQU PLIC Reg Offset 3Cc B2 Data Transmit Portl P2B2TR EQU PLIC Reg Offset 40 B2 Data Transmit Port2 P3B2TR EQU PLIC Reg Offset 44 B2 Data Transmit Port3 PODTR EQU PLIC Reg Offset 48 D Data Transmit Port0 P1DTR EQU PLIC Reg Offset 49 D Data Transmit Portl P2DTR EQU PLIC Reg Offset S4A D Data Transmit Port2 P3DTR EQU PLIC Reg Offset 4B D Data Transmit Port3 PLCRO EQU PLIC Reg Offset 50 GCI IDL config Port0 PLCR1 EQU PLIC Reg Offset 52 GCI IDL confi
46. g with the M5272C3 board daughter cards will be plugged into these PCI sockets Most of the time the T2 daughter boards will be plugged in to evaluate multi port functionality D channel access and other features The U2 daughter card will be used for IDL BER measurement The BER tester is the HP1645A which is directly connected to either the MC145572EVK or MC145574EVK The hardware setup is as follows 24 MCF5272 Interrupt Service Routine For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Assembly Code Software Configuration BER Tester HP1645A Coax Cables For BER Measurement MC145572EVK PCI Sockets BDM Cable RS232 Cable Figure 20 Hardware Configuration 7 7 Software Configuration This section describes software configuration 7 7 1 Customer Premises Equipment CPE Depending on the CPE board used the control software will run differently This gives the user the ability to control the sourcing transceiver If the MC145572EVK is used the RS232 cable is connected and the embedded software will automatically come up with power on reset If the MC145574EVK is used the scp exe software must be run on a Windows based PC Note scp exe software will not run on Windows NT Please refer to the specific EVK user s manual for more detailed information about the hardware and software for each 7 7 2 ColdFire Port Configuration Writing into the ColdFire core general pur
47. handle all the bits involved in PrPSR e Multiple ports are enabled description of how to access the ports that created this interrupt 5 1 ISR Bubble Definitions To assure that the following flow charts are well understood this section defines the bubble shapes used in the illustrations e Start or End of the process e Test Condition 10 MCF5272 Interrupt Service Routine For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Periodic Interrupt Process One Port Processing Q e Interrupt creation e Return from Interrupt PASR GMT 0 e Action taken PortO Read 5 2 One Port Processing For this PLIC interrupt service routine the channel priorities are fixed In the periodic status registers the BIRDF BITDE and DRDF have top priority then the B2RDF B2TDE and DTDE follow The xTUE and XROE should be given lowest priority because they should be cleared This interrupt service routine implementation gives some flexibility by dynamically jumping between the action to take and the verification of the bit that creates the interrupt Furthermore the purpose of the code was to first evaluate the product after first silicon The code and the ISR have been written with this objective in mind In conclusion all the actions are taken inside the ISR instead of raising a flag in order to perform it once the ISR has completed The flow chart is shown in Figure 9 MCF5272 Interrupt Service Ro
48. handler i usbl handler i usb2 handler i usb3 handler i usb4 handler i usb5 handler i usb6 handler i usb7 handler i dma handler i ether rx handler i ether tx handler i ether ntc handler i qspi handler int5 handler int6 handler MCF5272 Interrupt Service Routine For More Information On This Product Go to www freescale com Appendix A Software Configuration int2 handler int3 handler int4 handler i timl handler i tim2 handler i tim3 handler i tim4 handler i uartl handler i uart2 handler i usb0 handler i usbl handler i usb2 handler i usb3 handler i usb4 handler i usb5 handler i usb6 handler i usb7 handler i dma handler i ether rx handler i ether tx handler i ether ntc handler i qspi handler int5 handler int6 handler Freescale Semiconductor Inc nop stop 2700 org UserProgram User_Ram ds b 10 Leave 1K for user variables Stack ds b 10 Supervisor Stack 1Kbytes Init SSP Initial SSP The file below deals with the general periodic interrupt service routine including all of the bit handling Not all of the overrun and underrun bits are implemented in this file Nevertheless those bits have been verified Further more this file has been written as dynamic as possible c KER ERK he e e RE RHR ERE ERE RHR ERK REE ERR EERE RE RK REE KER ERE REE KERR eee de eee ee The program below has been written in the dynamic way That means In case that other bits are s
49. iodic Interrupt Process Aperiodic One Port Sequence 1 PnICR PLIC Interrupt Configuration register 2 PnPSR PLIC Periodic Status Register In fact even if the PLPSR has been updated the corresponding bit in the PnICR IE may not have been programmed thus the ISR process cannot be called by this port The flow chart is shown in Figure 10 Yes POPSR 0 Y l PIPSR 0 Process Port1 Yes bli I P2PSR 0 Process Port2 No No o Yes No No ae Figure 10 Multi Port Processing Interrupt Service Routine Flow Diagram P3PSR 0 Process Port3 Part VI Aperiodic Interrupt Process This part describes port sequence multi port case registers channel sequence abort condition and the command indicate channel 6 1 Aperiodic One Port Sequence This section explains how the aperiodic interrupt is used with one port enabled The next section describes a multi channel approach When one port is enabled a level of priority must be set up For obvious reasons the CI channel will be top priority because of its ability to activate and deactivate As far the 14 MCF5272 Interrupt Service Routine For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Aperiodic Interrupt Process Multi Port Case monitor channel is concerned the same philosophy will be applied and the received path takes higher priority The flow chart is shown in Figure 11 PLICR GCR Se
50. ion One register is used to indicate an abort condition The flow chart is shown in Figure 15 GMTA AR 1 Figure 15 Transmit Abort Condition Flow Diagram MCF5272 Interrupt Service Routine For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Aperiodic Interrupt Process Command Indicate Channel 6 6 Command Indicate Channel This section details the channel for command indication 6 6 1 Transmit Sequence Figure 16 explains CI channel operation Write CI into PnGCIT R 1 C3 CO PASR GCT 20 Process End Figure 16 CI Transmit Sequence Flow Diagram 20 MCF5272 Interrupt Service Routine For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Assembly Code Interrupt Controller 6 6 2 Receive Sequence The flow chart for the receive sequence is shown in Figure 17 PASR GCR 1 Silicon Issue Read PnGCIR C3 CO PASR GCR 20 Figure 17 CI Receive Sequence Flow Diagram Part VII Assembly Code This section outlines how the ColdFire core will handle the PLIC Some assembly code will be shown to better describe the sequence flow of the interrupt service routine An interrupt occurs every 500 microseconds therefore all the actions must be performed within this time 7 1 Interrupt Controller The MCF5272 microprocessor device has some registers that set the interrupt prioritization levels for each interrupt so
51. is acknowledging the abort It is automatically cleared by the CPU when the PnGMR register has been read 8 MC Monitor change 0 Default at reset 1 Indicates to the CPU that the monitor channel data byte written to the respective PnGMR register has changed and that the data is available for processing This bit is automatically cleared by the CPU when the PnGMR register has been read Clearing this bit also clears the aperiodic GMR interrupt 7 0 M Monitor channel data byte These bits are written by the monitor channel controller when valid monitor channel bytes are received 4 2 2 Monitor Channel Transmit The PrnGMT registers are 16 bit registers containing the control and monitor channel bits to be transmitted for each of the four ports on the MCF5272 A byte of monitor channel data to be transmitted on a certain port is put into an associated register using the format shown in Figure 6 and described in Table 2 A maskable interrupt is generated when this byte of data has been successfully transmitted 15 10 9 8 7 0 Field L R M Reset 0000 0000 0000 0000 R W Read Write Addr MBAR 0x368 POGMT 0x36A P1GMT 0x36C P2GMT 0x36E PSGMT Figure 6 GCI Monitor Channel Transmit Register PnGMT Table 2 PnGMT Register Field Descriptions Bits Name Description 15 10 Reserved should be cleared 9 L Last 0 Default reset value 1 Set by the CPU Indicates to the
52. ix A Software Configuration Port3GMRCheck move w PASR A5 D4 to make sure GMR 0 andi 1l 800002000 D4 cmp 1 80 D4 bne Port3GMRCheck rts Port3LCheck move W P3GMT A5 D4 to make sure L 0 andi l S00000200 D4 cmp 1 S0 D4 bne Port3LCheck rts Port3RTxCheck move w P3GMT A5 D4 to make sure R 0 andi l 800000100 D4 cmp 1 S0 D4 bne Port3RTxCheck rts Port3RCheck move b P3GCIT A5 D4 to make sure R 0 andi l S00000010 D4 cmp 1 80 D4 bne Port3RCheck rts The following file is called Corelnit s It is the core of the program with the program counter starting at the address defined by the user Obviously this program will require modifications depending on the evaluation the user wants to perform This example shows a very generic flow Users are welcome to make further modifications which should not affect the core of the program itself Code_Start nop move 1 40000000 A3 address allocation move l 10000000 A6 move l 10000000 A5 move l 20001000 A7 jsr IntInit Interrupt Initialization jsr RegisterInit Register Initialization jsr GCIInit if used GCI mode on jsr GCIIntEnable GCI Interrupt on jsr WaitLoop loop to configure in GCI jsr CI2F jsr MonitorAbort Monitor initialization jsr CICommand to Initialization CI jsr ST1BchannelEn to Send Value to MC jsr ReadPort0MC rts The file shown below is the initialization file configuring some registers in order to perform the right te
53. l Reg Offset 2C Csel Reg Offset 30 Csel Reg Offset 34 Csel Reg Offset 38 Csel Reg Offset 3C PORT A and PORT B Port Reg Offset 00 Port Reg Offset 04 Port Reg Offset 06 Port Reg Offset 08 Port Reg Offset 0C Port Reg Offset 0E Int Control Register Int Control Register Int Control Register Int Control Register Interrupt Source Register Prog Interrupt Transition Prog Interrupt Wakeup Prog Interrupt Vector Chip Select Base Register CS Option Register Chip Select Base Register CS Option Register 1 Chip Select Base Register CS Option Register Chip Select Base Register CS Option Register 3 CS Base Register 4 CS Option Register 4 CS Base Register 5 CS Option Register 5 CS Base Register 6 CS Option Register 6 CS Base Register 7 CS Option Register 7 Port A Control Reg Port A Data Direction Port A Data Register Port B Control Register Port B Data Direction Port B Data Register Port C has no CNT register pins controlled by data bus 16 32 bit mode PCDDR PCDAT PDCNT EQU EQU EQU Port Reg Offset 14 Port Reg Offset 16 Port Reg Offset 18 Port C Data Direction Port C Data Register Port C Control Register Port D has no DDR or DAT register used for pin asignment only PLIC MODULE REGISTERS POB1RR P1B1RR P2B1RR P3B1RR POB2RR P1B2RR 30 EQU EQU EQU EQU EQU EQU PLIC Reg Offset 00 PLIC Reg Offset 04 PLIC Reg Offset 08 PLIC Re
54. monitor channel controller to transmit the end of message signal on the E bit Both PnGMT L and PnGMT R must be set for the monitor channel controller to send the end of message signal The L bit is automatically cleared by the GCI controller 8 MCF5272 Interrupt Service Routine For More Information On This Product Go to www freescale com Freescale Semiconductor Inc GCIADL and the MCF5272 Command Indicate Registers Table 2 PnGMT Register Field Descriptions Bits Name Description 8 R Ready 0 Default reset value 1 Set by the CPU Indicate to the monitor channel controller that a byte of data is ready for transmission Automatically cleared by the GCI controller when it generates a transmit acknowledge ACK bit in PnGMTS register or when the L bit is reset 7 0 M Monitor channel data byte Written by the CPU when a byte is ready for transmission 4 3 Command Indicate Registers This section describes receive and transmit command registers 4 3 1 Command Indicate Receive The PnGCIR register is an 8 bit register containing the received C I bits for one of each of the four ports on the MCF5272 The register is shown in Figure 7 and described in Table 3 7 5 4 3 2 1 0 Field F C3 C2 C1 CO Read R W Reset 0000 0000 Figure 7 PnGCIR Register Table 3 PnGCIR Register Field Descriptions Bits Name Description 7 5 Reserved shoul
55. ng word 32 bit word 16 bit or byte 8 bit data transfer instructions An 8 bit write to one half of a register will leave the other half intact 7 2 Interrupt Vector Generation Pending interrupts are presented to the MCF52xx core in order of priority The core responds to an interrupt request by initiating an interrupt acknowledge cycle to receive a vector number which allows the core to locate the interrupt s service routine The interrupt controller is able to identify the source of the interrupt which is being acknowledged and indicates this to the interrupt module mapper The mapper determines which slave bus module is to provide the interrupt vector for the identified interrupt source In most instances it is the interrupt controller itself which will provide the interrupt vector in which case the following procedure is used The three most significant bits of the interrupt vector are programmed by the user in the programmable interrupt vector register 7 3 Prioritization Level ICR2 Register The interrupt control registers ICRx allow the user to define which interrupt priority level IPL each of these peripheral sources will use For those modules whose interrupt sources are mapped to the interrupt controller for the vector source the programmable interrupt vector register PIVR allows the user to define a particular vector number to be presented when the respective module receives an interrupt acknowledge from the MCF52xx core
56. nop move w move l andi 1 cmp 1 beq move w andi 1 cmp 1 bne move 1 andi 1 cmp 1 beq EndPortlRxBl move w andi 1 cmp 1 bne move l andi l cmp 1 beq EndPort1TxB1 move w andi 1 cmp 1 bne move 1 andi l cmp 1 beq EndPort1RxB2 move w andi 1 cmp 1 bne move 1 andi 1 cmp 1 beq PortlD move w andi 1 cmp 1 bne move 1 andi 1 cmp 1 beq EndPort1Rx move w andi 1 cmp 1 bne move l 36 00008000 D1 00008000 D1 Port2Test PnPSR1 A5 D1 D1 D7 0000003F D7 7 0 D7 Port2Test PlICR A5 D2 00000001 D2 00000001 D2 EndPortlRxBl D1 D7 00000001 D7 00000001 D7 Port1ReadB1 P1ICR A5 D2 00000008 D2 00000008 D2 EndPort1TxB1 D1 D7 00000008 D7 00000008 D7 PortlTransmitBl P1ICR A5 D2 00000002 D2 00000002 D2 EndPort1RxB2 D1 D7 00000002 D7 00000002 D7 Port1ReadB2 P1ICR A5 D2 00000010 D2 00000010 D2 Port1D D1 D7 00000010 D7 00000010 D7 PortlTransmitB2 P1ICR A5 D2 00000004 D2 00000004 D2 EndPort1Rx D1 D7 00000004 D7 00000004 D7 Port1RxD P1ICR A5 D2 00000020 D2 00000020 D2 Port2Test D1 D7 7 go to Portl go to BIRDF BITDE B2RDF B2TDE MCF5272 Interrupt Service Routine Go to www freescale com Freescale Semiconductor Inc Port2 if not equal Port2 if not equal Test Test Test Test DRDF Test DTDE Test For Mor
57. onfiguration cmp 1 00000000 D3 bne Port1B2RDFReset rts Port2B1RDFReset nop move w P2PSR A5 D3 andi l 00000001 D3 cmp 1 00000000 D3 bne Port2B1RDFReset rts Port2B2RDFReset nop move w P2PSR A5 D3 andi l 00000002 D3 cmp 1 00000000 D3 bne Port2B2RDFReset rts Port2DRDFReset nop move w P2PSR A5 D3 andi 1 00000004 D3 cmp 1 00000000 D3 bne Port2DRDFReset rts Port3B1RDFReset nop move w P3PSR A5 D3 andi 1 00000001 D3 cmp 1 00000000 D3 bne Port3B1RDFReset rts Port3B2RDFReset nop move w P3PSR A5 D3 andi 1 00000002 D3 cmp 1 00000000 D3 bne Port3B2RDFReset rts Port3DRDFReset nop move w P3PSR A5 D3 andi l 00000004 D3 cmp 1 00000000 D3 bne Port3DRDFReset rts gk ERK e ee KK RE RHR ER KKK ERK he he RRR ERE KERR e e eee eee e e e ee PES End of Bx RDF Procedures khe ee ee eee ee ee ee hehe ee e e eee he he ee ee eee e e e eee e eee e e kkk Bx TDE Set ekkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk LA PortOBlTDESet nop move w POPSR A5 D3 to make sure BITDE is set andi l S00000008 D3 cmp 1 S00000008 D3 bne PortOBlTDESet rts Port0B2TDESet nop move w POPSR A5 D3 to make sure B2TDE is set andi 1l S00000010 D3 cmp 1 800000010 D3 42 MCF5272 Interrupt Service Routine For More Information On This Product Go to www freescale com PortODTDESet nop PortlBlTDESet nop PortlB2TDESet nop PortlDTDESet nop Port2BlTDESet nop Port2B2TDESet nop
58. pose registers must configure the TDM pins of the MCF5272 With power on reset port will be automatically configured Then portO and some pins of port3 must be configured as a result of the GPIO register access Table 6 shows the values Table 6 Port Pin Assignments Fieldin Control Control Register Register Value Binary MAR BGAPIN Port Pins Configured by FSCO PortA PACNT8 01 J2 DCLO PDCNTO J4 Dino PDCNT1 K1 DoutO PDCNT4 K4 DREQO PACNT10 K5 DGRANTO PACNT9 J3 FSC1 N A L4 DCL1 DCL2 Reset N A M1 MCF5272 Interrupt Service Routine For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Assembly Code Software Configuration Table 6 Port Pin Assignments Port Pins Configured by ind ie Map BGA Pin Dint Din2 N A N2 Dout1 Dout2 N A N1 DREQI PACNT14 M2 DGRANTI PACNT15 M3 FSC2 PACNT12 L2 FSC3 PACNT13 L3 Din3 PortD Reset PDCNT5 10 00 P3 N2 Dout3 PortA Reset PACNT 7 10 00 P1 N1 Note The user must keep in mind that ports 1 2 and 3 share the same resource as long as DCL Din and Dout are concerned This is called the indirect mode Only the FSC pins are different In some applications Din3 and Dout3 might come from other resources called the direct mode In this case PDCNT and PACNT values must be programmed as the above array shows The MAP BGA pins will of course be different As a summ
59. re Configuration EndPort2Rx move w andi 1 cmp 1 bne move l andi l cmp 1 beq Port3Test move w andi 1 cmp 1 bne Port3Int move w move l andi l cmp 1 beq move w andi 1 cmp 1 bne move l andi l cmp 1 beq EndPort3RxB1 move w andi 1 cmp 1 bne move l andi l cmp 1 beq EndPort3TxB1 move w andi 1 cmp 1 bne move l andi l cmp 1 beq EndPort3RxB2 move w andi 1 cmp 1 bne move l andi l cmp 1 beq Port3D nop move w andi 1 cmp 1 bne move l 38 P2ICR A5 D2 00000020 D2 00000020 D2 Port3Test D1 D7 00000020 D7 00000020 D7 Port2TxD P3ICR A5 D1 00008000 D1 00008000 D1 EndSR P3PSR A5 D1 D1 D7 0000003F D7 7 0 D7 EndSR P3ICR A5 D2 00000001 D2 00000001 D2 EndPort3RxBl D1 D7 00000001 D7 00000001 D7 Port3ReadBl P3ICR A5 D2 00000008 D2 00000008 D2 EndPort3TxBl D1 D7 00000008 D7 00000008 D7 Port3TransmitBl P3ICR A5 D2 00000002 D2 00000002 D2 EndPort3RxB2 D1 D7 00000002 D7 00000002 D7 Port3ReadB2 P3ICR A5 D2 00000010 D2 00000010 D2 Port3D D1 D7 00000010 D7 00000010 D7 Port3TransmitB2 P3ICR A5 D2 00000004 D2 00000004 D2 EndPort3Rx D1 D7 Freescale Semiconductor Inc DTDE Test Port3 IE Test BIRDF Test BITDE Test B2RDF Test B2TDE test DRDF Test MCF5272 Interrupt Service Routine For More Information On This Product Go to www freescale com andi 1 cmp 1 beq
60. s follows MCF5272 Interrupt Service Routine For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Appendix A Software Configuration Program ISR Start Start Periodic Multi Port Processing CPU and PLI Initialization ISR End MC145574 Initialization Aperiodic processing APER 0 APER 0 Main Core of the Program where the ISR takes place Program End Figure 21 Main Program and ISR Flow Diagram Here below is the MAIN file with all the invoked files that are necessary include configuration h Equates include PLIInterupt s Interrupt Vectors include PerIntVector s Periodic Interrupt include AperIntVector s Aperiodic Interrupt include CoreInit s Main file include Init s Subroutine to init include CPUInit s Linked to ColdFire Core include Table s Note The user must add a space at each beginning of line to make sure the code will be correctly compiled This is the file that must be compiled with the following executable file makeit 28 MCF5272 Interrupt Service Routine For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Appendix A Software Configuration das l g Xalign value tMCF5206eFN simple Xasm debug on I o main o target s dld m2 o main elf main o lc gt map ddump Rv o try mot main elf Once the main elf file has been generated it
61. state machine which responds with the transmit acknowledge ACK bit in the PnGCITS register once transmission of two successive C I words is complete This bit is automatically cleared by the GCI controller when it generates an ACK The clearing of this bit by reading this register also clears the aperiodic GCT interrupt 3 0 C3 CO C I bits The CPU writes C I data to be transmitted on the GCI or SCIT channel 0 into these positions The CPU must ensure that this data is not overwritten before it has been transmitted the required minimum number of times that is before a change is detected and confirmed by a receiver A maskable interrupt is generated when this data has been successfully transmitted Part V Periodic Interrupt Process This document does not intend to define all the meanings of the PnPSR register For more information the user should read the MCF5272 User s Manual This PnPSR register is involved in the data processing AII PnRBx and Pr TBx registers either in IDL or GCI modes of operation will use these registers There is no difference between those two modes as far as they are concerned PnPSR register is updated every 500ys As long as the interrupt enable IE bits are set to invoke the interrupt service routine the BxRDF bits will be set every 500ys and a register access will be achieved to clear this interrupt This section is explained in two parts e One port only is enabled description of how to
62. sts Before performing any tests the user definitely needs to know the PLIC registers set to make sure the PLIC configuration will match the test requirements The following example tests Port in GCI Slave Mode Some monitor channel information is sent and the 2kHz rate works The other ports are off e ee de e e eee he e e e he ee ehe eee ehe ee he hee e hehehe ee he eee he eee e eee e eee eee dee eee e eee de eee e Different Subroutine used for init and checking GCI IDL c ke ee ee e eee he e e e he e e ehe eee e hee e hehe ee hehehe ee he hee ehe e ke ee he ee ee ee eee dee eee e eee de e eee e GCIInit MCF5272 Interrupt Service Routine For More Information On This Product Go to www freescale com Appendix A Software Configuration move w move w move w move w move w move w move w move w move b move b move b move w move w move w move w move w move w move w move w move w move w move w move w rts GCIIntEnable move w move w move w move w move w move w move w move w rts MonitorAbort move b move b rts CI2F move b move b rts ST1BChannelEn lea 1 Loop0 nop move w jsr move w and 1 cmp 1 beq bra EndLoop2 nop rts RTxCheckl move w andi 1 54 0003 d0 dO PLCRO A5 A203 D0 DO PLCR1 A5 0003 D0 DO PLCR3 A5 0003 D0 DO PLCR2 A5 PGMTS A5 DO PGCITSR A5 DO POGCIR A5 DO 0000 D0 DO PCSR A5 0000 D0 DO POSDR A5 0000 D0 DO P1SDR A5
63. tailed description 6 4 Monitor Channel Sequence This section details the manner in which GCI monitor channel data is handled Based on the low level protocol specification the following information will help the user better understand the GCI monitor channel operation 16 MCF5272 Interrupt Service Routine For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Aperiodic Interrupt Process Monitor Channel Sequence 6 4 1 Transmit Sequence Here is the transmit sequence of the GCI protocol using the GCI monitor channel transmit registers The flow chart is shown in Figure 13 Write Value into PnGMT with R 1 L 0 PASR GMT 0 Write into PaG MT with R 1 L 1 Figure 13 Monitor Channel Transmit Sequence Flow Diagram MCF5272 Interrupt Service Routine For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Aperiodic Interrupt Process Monitor Channel Sequence 6 4 2 Receive Sequence This section describes with the receive sequence of the GCI protocol The flow chart is shown in Figure 14 PASR GMR 1 PASR GMR 0 Abort Message Read PRhGMR D7 D0 Figure 14 Monitor Channel Receive Sequence Flow Diagram 18 MCF5272 Interrupt Service Routine For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Aperiodic Interrupt Process Transmit Abort Condition 6 5 Transmit Abort Condit
64. tgroup com Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters which may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which
65. urce The on chip system integration module contains an interrupt controller that is capable of providing up to 32 interrupt sources These sources include the following e External interrupt signals INT 6 1 e Software watchdog timer e Four general purpose timers Two USARTS e Ethernet controller e PLIC controller e DMA controller e QSPI e USB module MCF5272 Interrupt Service Routine For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Assembly Code Interrupt Vector Generation All external interrupt inputs are edge sensitive where the active edge is programmable The active edge is programmable An interrupt request must be held valid for at least three consecutive CPU clock cycles to be considered a valid input Each interrupt input can have its priority programmed by programming the xIPL 2 0 bits in the interrupt control registers When the ColdFire core responds to a request with an interrupt acknowledge cycle as is standard in MC52xx implementations the interrupt controller logic will forward the correct vector depending on the original source of the interrupt Software can clear pending interrupts from any source via the registers in the interrupt controller logic and can program the location of the block of vectors used for interrupt sources via the programmable interrupt vector register For an interrupt to be successfully processed RAM must be available for the stack and oft
66. utine For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Periodic Interrupt Process One Port Processing Process Port PaPSR 0 Yes BIRIE Set Move 1 PriB IRR DO No No Yes Yes BITDE Set No Yes Yes B2RIE Move l PnB2RR DO No NO Yes Yes BITDE Set No No Yes Yes DRDF Set No Yes Yes 2 MN S Move l DO PnDTR No No Figure 9 One Port Processing Interrupt Service Routine Flow Diagram Move l DO PnB ITR Move DO PrnB2TR Move l PrDRR D0 12 MCF5272 Interrupt Service Routine For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Periodic Interrupt Process Multi Ports Processing BIROE Yes Generate Error Set Read PnPSR B2ROE Set Generate Error Read PnPSR A Read PrPSR es Y m Read PnPSR Y No es DROE Generate Error Set Read PnPSR No Yes Read PnPSR D Figure 9 One Port Processing Interrupt Service Routine Flow Diagram Continued 5 3 Multi Ports Processing Most of the time more than one port will be enabled and in order to make the ISR subroutine more efficient several steps should be taken When the periodic interrupt occurs the user does not know yet which port has caused it To find out check the following registers MCF5272 Interrupt Service Routine For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Aper
67. ve for two GCI frames The monitor channel data is OXFF when inactive The originating GCI device transmits a byte onto the monitor channel after receiving the A and E bits equal to 1 for at least two consecutive GCI frames The originating GCI device also clears its outgoing E bit in the same GCI frame as the byte that is transmitted The transmitted byte is repeated for at least two GCI frames or is repeated in subsequent GCI frames until the MCF5272 acknowledges receiving two consecutive GCI frames containing the same monitor byte Once the MCF5272 acknowledges the first byte the sending device sets E high and transmits the first frame of the second byte Then the second byte is repeated with the E bit low until it is acknowledged The destination GCI device verifies that it has received the first byte by clearing the A bit towards the originating GCI device for at least two GCI frames Successive bytes are acknowledged by the receiving device setting high on the first instance of the next byte followed by A being cleared when the second instance of the byte is received If the receiving GCI device does not receive the same monitor channel byte in two consecutive GCI frames it indicates this by leaving A 0 until two consecutive identical bytes are received The last byte of the sequence is indicated by the originating GCI device when it sets its E bit for two successive GCI frames The procedure is summarized in Figure 4 125 us lt NULL BY
68. vec 32 org DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L DC L VBR Init Init SSP Code Start berr handler aerr handler illeg handler divz handler chk handler trapv handler privv handler trace handler aline handler fline handler rsrv handler rsrv handler rsrv handler uninit handler rsrv handler rsrv handler rsrv handler rsrv handler rsrv handler rsrv handler rsrv handler rsrv handler spuri handler rsrv handler rsrv handler rsrv handler rsrv handler rsrv handler rsrv handler rsrv handler trap0 handler trapl handler trap2 handler trap3 handler trap4 handler trap5 handler trap6 handler trap7 handler trap8 handler trap9 handler trapl0 handler trapll handler trapl2 handler trapl3 handler trapl4 handler trap15 handler rsrv handler rsrv handler rsrv handler rsrv handler rsrv handler rsrv handler rsrv handler rsrv handler rsrv handler rsrv handler rsrv handler rsrv handler mbar handler mbar handler MCF5272 Interrupt Service Routine For More Information On This Product Go to www freescale com res62 vec res63 vec i spur vec intl vec int2 vec int3 vec int4 vec i timl vec i tim2
69. via the interrupt controller logic The interrupt vector register is initialized upon system reset with the uninitialized interrupt vector hexadecimal OxOF and must be programmed with the required vector number for normal operation It is important not to use reserved interrupt vector locations for this purpose The dedicated ICRx for the periodic and aperiodic interrupts is ICR2 22 MCF5272 Interrupt Service Routine For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Assembly Code Programmable Interrupt Vector Register PIVR MBASE 0x24 31 30 29 28 27 26 25 24 Write UART1PIR UART1PL2 UART1 PL1 UART1 PLO UART2PIR UART2 PL2 UART2 PL1 UART2PLO Read UART1 UARTIPL2 UART1 PL1 UART1 PLO UART2 UART2 PL2 UART2 PL1 UART2PLO Reset 0000 0000 23 22 21 20 19 18 17 16 Write PLIPIR PLIIPL2 PLIIPL1 PLIPLO PLIAPIR PLIAIPL2 PLIAIPL1 PLIAIPLO Read PLIP PLIIPL2 PLIIPL1 PLIPLO PLIA PLIAIPL2 PLIAIPL1 PLIAIPLO Reset 0000 0000 15 14 13 12 11 10 9 8 USBOPIR USBOIPL2 ISBOIPL1 USBOIPLO USB1PIR USB1IPL2 USB1IPL1 USBOIPLO USBO USBOIPL2 ISBOIPL1 USBOIPLO USB1 USB1IPL2 USB1IPL1 USBOIPLO Write Read 0000 0000 Reset 7 6 5 4 3 2 1 0 Write USB2PIR USB2IPL2 USB2IPL1 USB2IPLO USBSPIR USB3IPL2 USB2IPL1 USB2IPLO Read ISB2 USB2IPL2 USB2IPL1 USB2IPLO USB

MCF5272 Interrupt Service Routine

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