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Conexant Bt835 VideoStream III Decoder

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1. 4 46 Figure 2 4 Luma and Chroma 2x Oversampling Filter 47 Figure 2 5 Output Mode 48 Figure 2 6 YCrCb 4 2 2 Pixel Stream Format SPI Mode 8 and 16 49 Figure 2 7 81835 Synchronous Pixel Interface Mode 1 1 50 Rockwell D835DSA vii List of Figures Bt835 Figure 2 8 Figure 2 9 Figure 2 10 Figure 2 11 Figure 2 12 Figure 2 13 Figure 2 14 Figure 2 15 Figure 3 1 Figure 3 2 Figure 3 3 Figure 3 4 Figure 3 5 Figure 3 6 Figure 5 1 Figure 5 2 Figure 5 3 VideoStream III Decoder Basic Timing Relationships for SPI 1 50 Data Output in SPI Mode 2 52 Video Timing in SPI Modes 1 02 53 Horizontal Timing Signals in the SPI 0 54 The Relationship between SCL and 0 61 IC Slave Address Configuration sv naked eee anes 62 Diagram 64 Instruction c HERE DR RR er aaa 66 Example Ground Plane Layout 67 Optional Regulator Circuitry for 5
2. eN v 089 0018 8 eu juewnoog 929 do 8 818 anu 12126 vo ues 5 8986 uoisiwQ SWALSAS HOLONGNOOIWAS NOISSIINH3d LNOHLIM Q3MOTIV 3Sn HO NOLLVNINSSSIG ON NOLLVINHOJNI Zd vas 7195 Soo Sseippv AL 4 10199 90199 50199 vOldo 20189 2049 10199 00199 19 Sid Hola 13534 30 cono Doro X790 3ALLOVA 991380 qiu 3ALLOV 13538 0 Did Hold 13538 30 3ALLOVA 719 d 99 99 vd Sseippv Oel AL 105 vas 5 1480 50081 3ALOV 13S34H 3S3HA 3509 00 AL o7 ZA 3 31dOL vas 2 O3GIA AL OAGIA Rockwell D835DSA 74 3 0 PC Board Layout Considerations Bt835 3 9 Sample Schematics VideoStream III Decoder Figure 3 6 Bt835 Typical Circuit Schematic 2 of 5 E jo 2 19908 8661 20104 epson oed v 089 0018 8 Joquinnweunoog 925 H3MOd 12126 VO ues 5 8
3. sc 9 1499 lt vr v1485 quic 65 1 91313 12 lt A3S3HH lt i gt 3304001 noires segia 300 99 3338 75 TN MIO 910 s ea Heid LE 1099 7 al 1069 g tOld9 z 70199 52 gt 90190 9 209 10189 s 10199 4 2 1 00189 62 0049 exn 55 9 lt Lg 15 55 AL D835DSA Rockwell 835 VideoStream III Decoder 3 0 PC Board Layout Considerations 3 9 Sample Schematics Figure 3 6 Bt835 Typical Circuit Schematic 5 of 5 19905 5661 BO OY AEPS sed 089x 0018 lsno 521 4A3segia NOISS H3d 3SN HONOLLVNIWASSIO ON NOUVWEOJNI 1 S80 0HvzvS 499 100 4 5080 Nd 160 02u0v6 WHO SL ees 5080 N E VSI ail j 2 TNL PA zd 80 Lourers Le0 ozuPors 5080 Y 5080 WHO SL HOLO3NNOO mro EN lt 1 150 aN 1002 v19 580 0 5 9005 oes 5080 xovr vou 1e0 0zuvors WHO SL ue 5080 i mro d susoco lt z 90 vas 15 lt l
4. EN CLKSLP YSLP CSLP EN 0X1D WC_UP MAJS 1 0 UPCNT 5 0 OX1E WC_DN WCFRM DNCNT 5 0 OX1F CC_STATUS PARERR INT_EN EDS cc OR DA CC EDS LO HI 0X20 CC_DATA CCDATA 7 0 0X21 GPIO GPIO 7 0 Asewiuing 19151694 uonduoseq 4 151 07 86 vsasesd Table 4 1 Register ADDR Register Read Bit Number hex Label Write 7 6 5 4 3 2 1 0 0 22 GPIO_NOE NOE 7 0 0X23 VSIF BCF 1 0 VSFMT 2 0 0X24 TG_CTL CKDIR TGEN TGARST TGCKO 1 0 TGCKI 1 0 0X27 PLL XCI 28 HMZ PLL X PLL C PLL I 5 0 0X2A PLL 35 HMZ PLL X PLL C PLL I 5 0 OXFB COMB2H_CTL DISIF INVCBF DISADAPT FORCE2H FORCEREMOD NCHROMAEN NRMDEN OXFE IDCODE ID 3 0 REV 3 0 Asewuing 1 516 4 segia uondioseg 1 1 1 023002 07 5 0 Parametric Information 5 1 DC Electrical Parameters Table 5 1 Recommended Operating Conditions Parameter Symbol Min Typ Max Units Power Supply Analog 4 75 5 00 5 25 V Power Supply 5 0 V Digital Vpp 4 75 5 00 5 25 V Power Supply 3 3 V Digital 3 00 3 3 3 6 Maximum Vaal 5 V 0 5 V MUXO MUX1 and MUX2 Input Range 0 5 1 00 2 00 V AC coupling req
5. a 8 8 oo aozo att lt lt _ gt gt gt gt gt VSS GND 1 VDD VD 15 2 FRST VD 14 3 NC VD 13 4 NC VD 12 5 NC VD 11 6 NC VD 10 7 NC 0 9 8 NC VD 8 NC VDDO NC VSSO GND NC VDI 7 NC VD 6 NC VD 5 NC VDI 4 VAA VD 3 MUX3 VD 2 AGND MUX2 VD 0 VAA VDD MUX1 VSS GND VAA GPIO 7 MUXO GPIO 6 AGND GPIO 5 REFP GPIO 4 AGCCAP GPIO 3 VAA GPIO 2 CIN GPIO 1 AGND GPIO 0 NC VDDO VSSO GND Wy j j utu aonoxounuononirzc o xo 2 5 gt gt lt 5 112 65 5 2 gt 684 20278 99 gt 2 550 g gt 2 gt Sas gt 8 D835DSA Rockwell Bt835 1 0 Functional Description VideoStream III Decoder Table 1 2 Bt835 Pin Descriptions 1 of 2 1 2 Pin Descriptions Pin 1 0 Pin Name Description 9 2 VD 15 8 In 16 bit output mode these pins represent the luma portion of the decoded video signal In 8 bit output mode these pins are the 4 2 2 multiplexed data stream In test mode these pins may be configured to be the test bus output 19 12 1 0 VD 7 0 In 16 bit mode these pins represent the multiplexed Cr Cb portion of the decoded video signal In 8 bit mode these pins are three stated When in 8 bit mode these pins may be
6. 99 51 DCElectrical Parameters 99 5 2 ACElectrical Parameters 102 Rockwell D835DSA Bt835 VideoStream III Decoder vi D835DSA Rockwell Bt835 List of Figures VideoStream III Decoder List of Figures Figure 1 1 Bt835 Detailed Block Diagram 2 Figure 1 2 BESS rr teu exe ef RENE ILLE CERT 8 Figure 1 3 UltraLock Behavior for NTSC Square Pixel 12 Figure 1 4 Y C Separation and Chroma Demodulation for Composite NTSC Video 15 Figure 1 5 Y C Separation and Chroma Demodulation for Composite PAL 16 Figure 1 6 NTSC and PAL SECAM Y C Separation Filter Responses 16 Figure 1 7 Filtering and Scaling Heel RS xs 17 Figure 1 8 Optional Horizontal Luma Low Pass Filter Responses 18 Figure 1 9 Combined Luma Notch 2x Oversampling and Optional Low Pass Filter Response NTSC 19 Figure 1 10 Combined Luma Notch 2x Oversampling and Optional Low Pass Filter Response PAL SECAM 19 Figure 1 11 Frequency Responses for the Four Optional Vertical Luma Low Pass Filters 20 Figure 1 12 Combined Luma Notch and 2x Oversampling
7. 4 CLKx1 y jy eue Control Pixel and Data 5 16 Bit Mode QCLK Pixel and Table 5 6 Power Supply Current Parameters 3 5 operation Parameter Symbol Min Typ Max Units Supply Current 5 0 V 28 64 MHz T 25 C 145 170 5 25 V 0735 47 MHz T 70 C 200 250 5 25 V Fo 2735 47 MHz T 0 C 240 280 mA Supply Current Power Down 25 Table 5 7 Output Enable Timing Parameters Parameter Symbol Min Typ Max Units OE Asserted to Data Bus Driven 9 0 ns OE Asserted to Data Valid 10 100 5 Negated to Data Bus Not Driven 11 100 ns RST Low Time 8 XTAL cycles 104 D835DSA Rockwell Bt835 5 0 Parametric Information VideoStream III Decoder 5 2 AC Electrical Parameters Figure 5 2 Output Enable Timing Diagram Pixel Clock Control Data Table 5 8 JTAG Timing Parameters Parameter Symbol Min Typ Max Units TMS TDI Setup Time 12 10 ns TMS TDI Hold Time 13 10 ns TCK Asserted to TDO Valid 14 60 ns Asserted to Driven 15 5 ns Negated to TDO Three stated 16 80 ns TCK Low Time 17 25 ns High Time 18 25 ns Figure 5 3 JTAG Timing Diagram
8. The Bt835 provides a 16 x 10 location FIFO for storing CC EDS data Once the video decoder detects the start signal in the CC EDS signal it captures the low byte of CC EDS data first and checks to see if the FIFO is full If the FIFO is not full then the data is stored in the FIFO and is available to the user through the CC_DATA register 0x20 The high byte of CC EDS data is captured next and placed in the FIFO Upon being placed in the 10 bit FIFO two additional bits are attached to the CC EDS data byte by Bt835 s CC EDS decoder These two bits indicate whether the given byte stored in the FIFO corresponds to CC or EDS data and whether it is the high or low byte of CC EDS These two bits are available to the user through the CC_STATUS register bits CC EDS and LO HI respectively The parity bit is stored in the FIFO as shown in Figure 1 26 Additionally the Bt835 stores the results of the parity check in the PAR_ERR bit in the CC_STATUS register Figure 1 26 Closed Captioning Extended Data Services FIFO Location 0 Location 1 Location 15 E 7 bit ASCII code available through CC_DATA Register Parity Bit Available through CC_DATA Register LO_HI Available through CC_STATUS Register CC_EDS Available through CC_STATUS Register The 16 location FIFO can hold eight lines worth of CC EDS data at two bytes per line Initially when the FIFO is empty bit DA in the CC_STATUS register Ox 1F is set low and indic
9. D835DSA Rockwell Bt835 1 0 Functional Description VideoStream III Decoder 1 1 4 UltraLock 1 1 Functional Overview In order to overcome this hanging dot problem and the loss of vertical resolution Rockwell has designed a sophisticated 3 line adaptive comb filter to separate the Y C components in a composite video signal This circuit is used in the new Bt835 video decoder As stated above simple line comb filters can not eliminate hanging dots on a vertical color transition The problem is caused by comb filtering two successive scan lines with different color values at the same horizontal positions along the lines The line comb filter cannot separate the Y C signals correctly in this situation The color signal crosses over into the luminance signal creating the cross luminance artifact In a 3 line adaptive Y C separation filter adaptive logic is used to continuously evaluate the video image and then select the most efficient processing algorithm available in the filter This is sometimes called a 2 D filter because both the horizontal scan lines and vertical transitions are processed This type of filter eliminates the hanging dot problem by detecting the vertical transitions in the image The logic examines three successive horizontal scan lines simultaneously If a vertical transition occurs between the first and third lines the notch filtered luminance and bandpass filtered chrominance will be used directly without
10. RANGE 0 RANGE 1 Y 16 235 0 gt 255 Cr 2 253 2 253 Cb 2 gt 253 2 gt 253 54 D835DSA Rockwell Bt835 2 0 Electrical Interfaces VideoStream Decoder 2 2 Output Interface 2 2 5 Synchronous Pixel Interface Mode 3 VIP Interface In VIP Interface mode the Bt835 video decoder transports several types of real time signal streams Among these signals are 1 Active visible video represented in digital baseband component YUV which can be scaled both horizontally and vertically 2 Raw ADC output samples of digital CVBS composite video during selected VBI lines representing VBI data 3 Other real time capture related data excluding ancillary data The VIP Interface will accept decoded active visible video as selected by a video acquisition window definition of active pixels per line and active lines per field Active video and raw ADC samples are interleaved into one single data stream and they are synchronized and separated by unique ITU R 656 header codes According to the data type and the timing references luma and chroma signals will be enveloped by appropriate SAV start of active video or EAV end of active video header codes VBI data are transported as raw ADC samples The VIP Interface port does not support ancillary data All timing reference control signals are transported through a VIP Interface block pipelined to match any delay introduced in the datapaths VIP Interfac
11. 12 13 TDI TMS x X TDO 2 ze y Table 5 9 Decoder Performance Parameters Parameter Symbol Min Typ Max Units Horizontal Lock Range 7 of Line Length Fsc Lock in Range 800 Hz Gain Range 6 6 dB Note Test conditions unless otherwise specified Recommended Operating Conditions TTL input values are 0 3 V with input rise fall times lt 3 ns measured between the 10 and 90 points Timing reference points at 50 for digital inputs and outputs Pixel and control data loads lt 30 pF and gt 10 pF CLKx1 and CLKx2 loads lt 50 pF Control data includes CBFLAG DVALID ACTIVE VACTIVE HRESET VRESET and FIELD Rockwell D835DSA 105 5 0 Parametric Information Bt835 5 2 AC Electrical Parameters Table 5 10 100 Pin PQFP Package Mechanical Drawing VideoStream III Decoder ALL DIMENSIONS IN MILLIMETERS 2 0 REF D 22 95 23 45 D 20 00 REF E Eq L 0 25 0 45 e 0 66 856 5 Y M B L 106 D835DSA Rockwell
12. 7 11 27 172 4 327143224123 zd 1 az EE 16 Optional 6 Tap 32 Phase m 3 MHz Interpolation On chip Memory Luma Comb Y Horizontal and Vertical Scaling Y Vertical Filtering Low Pass Horizontal Filter Scaling 2 Tap 32 Phase chi Interpolation On chip Memory PRIORE Cone Vertical Scaling Horizontal Scaling 2 1 refers to a pixel delay the horizontal direction and a line delay in the vertical direction The coefficients are de Note termined by UltraLock and the scaling algorithm Rockwell D835DSA 17 1 0 Functional Description Bt835 1 6 Video Scaling Cropping and Temporal Decimation VideoStream Decoder 1 6 Video Scaling Cropping and Temporal Decimation The Bt835 provides three mechanisms to reduce the amount of video pixel data in its output stream down scaling cropping and temporal decimation All three can be controlled independently 1 6 1 Horizontal and Vertical Scaling The Bt835 provides independent and arbitrary horizontal and vertical down scaling The maximum scaling ratio is 16 1 in both X and Y dimensions The maximum vertical scaling ratio is reduced from 16 1 when using frames to 8 1 The following sections describe the different methods used for scaling luminance and chrominance 1 6 2 Luminance Scaling The first stage in horizontal luminance scaling is an optional pre filter which provides the capabili
13. Xx Filtered Vertical Scaling 3 line Adaptive Comb Filter Single Crystal Operation for all Video Formats Digital Video Input Port PAL 60 NTSC 4 43 Decoding 8 bit GPIO OK 0X 0X XJ X XxX Xx VIP Interface 1 1 2 Bt835 Architecture and Partitioning The Bt835 provides the most cost effective high quality video input solution for low cost multimedia subsystems that integrate both graphics display and video capabilities The feature set of the Bt835 supports a video graphics system partitioning which optimizes the total cost of a system configured with and without video capture capabilities This enables system vendors to easily offer products with graphics display and video support using a single base system design As graphics chip vendors move from PCI video graphics processors to 3D AGP graphics processors the ability to efficiently use silicon and package pins to support 2D 3D graphics acceleration video playback acceleration and video capture becomes critical This problem becomes more acute as the race toward higher performance graphics requires more and more package pins to be consumed for wide 128 bit memory interfaces and glueless local bus interfaces Rockwell D835DSA 3 1 0 Functional Description Bt835 1 1 Functional Overview 1 1 3 Comb Filter VideoStream Decoder The Bt835 minimizes the cost of video capture function integration in tw
14. 13538 13S3HH vas e 708 109100 O3GIA pace Y T I z T Rockwell D835DSA 76 3 9 Sample Schematics 3 0 PC Board Layout Considerations Figure 3 6 Bt835 Typical Circuit Schematic 4 of 5 VideoStream III Decoder Bt835 77 1 5 Jo 7 yous 8661 80 ad NOISSISd 0018 NA Q3MOTTV seg jequnwiueumoog 526 5 51 ON lA Gca1 A3ccia ABV L3IHdOHd 12126 v9 ues 8986 wwie 121 610 Bz SWLSAS HOLONGNOOIWSS GUN lt 97 E 592 2 ON OX as z 02 2 ON 69 10 ZLHvZ S 25 89 5080 H 3 ni A 90ND Te I 7 1 Te FE Ha OND SUL 9 6 x 98 TH Wane 25 85 Nov 5 v9 JexaNov 1583 7188 30 3 5 Li 99 5002 86 lt 5220 7 zono Sos E vos pass md lt zt 5080 nro zo lt ANLOVA lt 57 anova
15. 1 Sleep system clock YSLP Sleep luma ADC 0 Normal luma ADC operation DEFAULT 1 Sleep luma ADC CSLP Sleep chroma ADC 0 Normal chroma ADC operation 1 Sleep chroma ADC DEFAULT CRUSH Enable white crush circuitry O0 Disable white crush DEFAULT 1 white crush 0X1D WC UP DEFAULT OxCF MAJS 1 0 UPCNT 5 0 MAJS 1 0 UPCNT 5 0 These bits determine the majority comparison point for the white crush up function 00 3 4 maximum luma 01 1 2 maximum luma 10 1 4 maximum luma 11 Automatic DEFAULT White crush up value Twos complement number a negative sign bit is assumed Rockwell D835DSA 89 4 0 Control Register Description Bt835 VideoStream III Decoder 0X1E WC DN DEFAULT 0x7F 7 6 5 4 3 2 1 0 Reserved WCFRM DNCNT 5 0 RESERVED Reserved for future use Set to 0 WCFRM This bit programs the rate at which the DNCNT and UPCNT values are accumulated 0 Once per field 1 per frame DEFAULT DNCNT 5 0 White crush down count value Two s complement a positive sign bit is assumed DEFAULT 0X1F CC STATUS DEFAULT 0x82 7 6 5 4 3 2 1 0 PARERR INT EN EDS CC OR DA CC EDS LO HI PARERR INT_EN EDS cc OR DA CC EDS LO HI Parity Error flag 0 parity error 1 Parity error DEFAULT CCVALID interrupt mask 0 CCVALID
16. Decoder 1 6 8 Temporal Decimation Temporal decimation provides a solution for video synchronization during periods when full frame rate cannot be supported due to bandwidth and system restrictions For example when capturing live video for storage system limitations such as hard disk transfer rates or system bus bandwidth may limit the frame capture rate If these restrictions limit the frame rate to 15 frames per second the Bt835 s time scaling operation enables the system to capture every other frame instead of allowing the hard disk timing restrictions to dictate which frame to capture This maintains an even distribution of captured frames and alleviates the jerky effects caused by systems that simply burst in data when bandwidth becomes available The Bt835 provides temporal decimation on either a field or frame basis The temporal decimation register TDEC is loaded with a value from 1 to 60 NTSC or 1 to 50 PAL SECAM This value represents the number of fields or frames skipped by the chip during a sequence of 60 for NTSC or 50 for PAL SECAM Skipped fields and frames are considered inactive indicated by the ACTIVE pin remaining low Consequently if QCLK is programmed to depend on ACTIVE QCLK becomes inactive as well Examples TDEC 0x02 Decimation is performed by frames Two frames are skipped per 60 frames of video assuming NTSC decoding Frames 1 29 are output normally then ACTIVE remains low for one frame Frame
17. RST When low resets the Bt835 Internal pullup 20 40 80 P VDD Core power Can be connected to 3 3 V or 5 V 100 1 21 41 G VSS Core ground Must be connected to ground 81 10 30 50 P VDDO Pad ring power 90 11 31 51 G VSSO GND Pad ring ground 91 94 P VPP PLL power 97 G PGND PLL ground 55 60 66 P VAA Analog power Must always be connected to 5 V 53 58 64 G AGND Analog ground Must always be connected to ground 54 The analog chroma input to the C ADC 57 The top of the ADC reference must be connected to a 0 1 uF input capacitor to ground 56 AGCCAP The AGC time constant control Must be connected to a 0 1 uF capacitor to ground 59 61 63 MUX 3 0 Analog composite video inputs to the on chip input multiplexer They are used to 65 select between four composite sources or three composite and one S Video source Unused pins should be connected to GND 10 D835DSA Rockwell Bt835 1 0 Functional Description VideoStream III Decoder 1 3 1 The Challenge 1 3 UltraLock 1 3 UltraLock The line length the interval between the midpoints of the falling edges of succeeding horizontal sync pulses of analog video sources is not constant For a stable source such as a studio grade video source or test signal generators this variation is very small 2 ns For an unstable source such as a VCR laser disk player or TV tuner line length variation can be a few microseconds Despite
18. VBIEN FRAME VBIFMT CAGC CKILL SC_SPD HACT SCAGC Enables VBI capture 0 Disable VBI capture DEFAULT 1 Enable VBI capture VBI Frame raw mode 0 frame mode disabled DEFAULT 1 VBI frame mode enabled VBI Output Format Byteswap 0 Pixel on VD 15 8 Pixel N 1 on VD 7 0 DEFAULT Pixel on VD 7 0 Pixel N 1 on VD 15 8 Enables QAM Chroma AGC for NTSC PAL 0 disabled SECAM Chroma AGC enabled DEFAULT NTSC PAL Enable Low color removal 0 killer disabled Color killer enabled DEFAULT Chroma lock speed 0 Slow Normal DEFAULT HACTIVE extend O0 Reset HACTIVE with HRESET DEFAULT Extend HACTIVE beyond HRESET SECAM Chroma AGC SECAM color killer 0 SECAM killer disabled DEFAULT 1 SECAM killer enabled Rockwell D835DSA 85 4 0 Control Register Description Bt835 VideoStream ITI Decoder 0X17 CONTROL_2 DEFAULT 0x01 7 6 5 4 3 2 1 0 YCORE 1 0 CCORE 1 0 VIPEN BSTRM RANGE VERTEN YCORE 1 0 Selectable Luma coring 00 luma coring DEFAULT 01 8 Isbs 10 16 Isbs 11 32 Isbs CCORE 1 0 Selectable Chroma coring 00 chroma coring DEFAULT 01 2 Isbs 10 4 Isbs 11 8 Isbs VIPEN Enables VIP control code insertion 0 No VIP control codes DEFAULT 1 control codes inserted BSTRM Enables ByteStream contro
19. data ass through MOXI PC JTAG 9 MUX2 Ultralock Video Single crystal for any video format an Timing i imah MUX3 Clock Video Arbitrary temporal decimation for a reduced AGCCAP Generation gt Timing frame rate video sequence REFP Programmable hue brightness saturation E Output and contrast D Control n Digital video input port i F A m Separation Spatial arid 8 e 2 oversampling to simplify external Pape 5 Scaling Digital analog filtering E s Video Two wire Inter Integrated Circuit 12 bus CIN Output interface a Data SENE 8 or 16 bit pixel interface YCrCb 4 2 2 output format e Software selectable four input analog MUX Digital Input Video Digital Video Eight fully programmable GPIO bits and Timing input Data Auto NTSC PAL format detect Automatic Gain Control AGC Typical power consumption 500 mW 3 3 V 1149 1 Joint Test Action Group JTAG interface 100 PQFP package VIP VMI ByteStream interfaces Related Products Bt829B Bt868 869 Applications Multimedia mage processing Desktop video Video phone Interactive video Rockwell 5ystems Ordering Information Model Number Package Operating Temperature Bt835KRF 100 pin PQFP 0 C to 70 C Copyright 1998 Rock
20. during the last half of a NVRESET has gone low E C NVRESET 1 LASTF 1 line before and the first 1110 1100 half of a line after NVRESET is active EAV Previous pixel was last pixel 00 00 HACTIVE 0 VACTIVE 0 LASTNVBI indicates the of the line immediately FIELD 0 VBISEL 0 arrival of last line before before VBI mode is enabled M m NVRESET 0 LASTNVBI 1 VBI mode is enabled SAV Next pixel is first pixel of line FF 00 00 1 VACTIVE 0 VBIEN signal triggers immediately after mode FIELD 1 VBISEL 1 data in VBISEL lines to be is enabled 6 2 NVRESET 1 LASTNVBI 1 processed 0110 0010 EAV Previous pixel was last pixel FF 00 00 HACTIVE 0 VACTIVE 0 LASTNV indicates last in vertical blanking interval FIELD 1 VBISEL 1 line before active video during VBI mode D NVRESET 1 LASTNV 1 ines 1101 1010 Next pixel is first pixel of FF 00 00 1 VACTIVE 1 During the odd to even first active acquired line FIELD 1 VBISEL 1 field transition VBISEL C 7 NVRESET 1 LASTNV 1 stays HIGH during the 1100 0111 first half of first active line Rockwell D835DSA 59 2 0 Electrical Interfaces Bt835 2 2 Output Interface VideoStream III Decoder Table 2 6 VIP SAV and EAV Codes Under Full Resolution 3 of 3 Code Event Description Inserted Headers and Type raster Reference Code TASKS Comments FIELD
21. Bt835 VideoStream Decoder 0x09 0x08 HACTIVE DEFAULT 0x0280 The HACTIVE register is a 16 bit register starting at location 0x08 Values between 0 and 1023 inclusive may be programmed into the HACTIVE register 0x0B 0 0 HSCALE DEFAULT 0x02AC The HSCALE register is 16 bit register starting at location This register is programmed according to the equations given in the Bt835 datasheet 0x0D 0x0C VSCALE DEFAULT 0x0000 The VSCALE register is a 16 bit register starting at location OxOC The VSCALE value is a 13 bit value stored in the LSBs of the register 0 0 VSCALE DEFAULT 0x00 The VSCALE CTL register configures the vertical scaler 7 6 5 4 3 2 1 0 Reserved COMB 1 0 NVINT FIELD VFILT 2 0 RESERVED Not used Set to 0 COMB 1 0 Comb Filter selection 00 Full Comb filter DEFAULT 01 Comb filter ONLY 10 RSRVD 11 Comb Filter NVINT VS Interlace Format 0 Non Interlace VS DEFAULT Interlace VS FIELD Interfield interpolation 0 Disables interfield interpolation DEFAULT Enables interfield interpolation VFILT 2 0 Vertical filter format 000 2 tap amp Interpolation DEFAULT 001 3 tap amp Interpolation 010 4 tap amp Interpolation 011 5 tap amp Interpolation 100 2 tap amp No Interpolation 101 3 tap amp No Interpolation 110 4 tap amp No Interpolation 111 5 tap amp No Int
22. Filter Response 20 Figure 1 13 NTSC Peaking 21 Figure 1 14 PAL SECAM Peaking 5 21 Figure 1 15 Effect of the Cropping and Active Registers 25 Figure 1 16 Regions of the Video Signal 26 Figure 1 17 Regions of the Video 30 Figure 1 18 Bt835 YCrCb 4 2 2 Data Path 30 Figure 1 19 81835 52 ive EN ROO baa eed 31 Figure 1 20 VBI Line Output Mode nn 32 Figure 1 21 VBI Sample 33 Figure 1 22 Location of VBI 34 Figure 1 23 VBI Sample eee Hen 35 Figure 1 24 5 Data Processing 37 Figure 1 25 CO EDS Incoming Signal 0 0 0 cece en 38 Figure 1 26 Closed Captioning Extended Data Services 38 Figure 1 27 Goring Map ss tt eda eed ce eap ete eit etat roit pee na 40 Figure 2 1 Diode Protections oss sobre ede e ee tac 42 Figure 2 2 ClOCK OPHION S Mee 44 Figure 2 3 81835 Typical External Circuitry
23. ID Active Video or VBI mode 9 000 No valid data between 00 VALID 0 Value 00 is not compliant and EAV don t capture and to ITU R 656 but don t increment compatible with straightforward encoder and decoder logic implementation 00 and FF are not valid pixel values VIP Application Notes 1 decimation of fields or frames in VIP Certain VIP applications such as a VCR in fast forward mode can move the memory pointer of a FIFO to a new field at the leading edge of VRESET instead of the leading edge of VACTIVE In the Bt835 the signal NVRESET is used instead to indicate that VRESET is an active low signal During VIP mode Field ID is gated by NVRESET and the Field ID transitions at the leading edge of NVRESET However if the leading edge of VACTIVE arrives before the trailing edge of NVRESET the memory pointer may move to anew location prematurely causing the first line of one field to be written at the bottom of another field Thus we recommend that the leading edge of VACTIVE be used to move the memory pointer of a FIFO in VCR applications During vertical scaling the VALID and HACTIVE signals are gated off This means that during a dropped line no SAV EAV codes are generated And because the VALID signal is gated off all pixels are treated as invalid pixels Only invalid code 00 is inserted into the data stream of dropped lines However in the Bt835 HACTIVE is held HI
24. Input Formats 13 1 5 Y C Separation and Chroma 15 1 6 Video Scaling Cropping and Temporal 18 1 6 1 Horizontal and Vertical Scaling 18 1 6 2 Luminance Scaling 18 TESO Peaklrig zi ete e Paes REIR ORE RE ee 21 1 6 4 5 22 1 65 Sealing Registers eR e etae ee RU E OSEE Pat 22 1 6 6 Image Croppingzas oss t osse dt e ds de Sdn 24 1 6 7 Cropping cett eR b Eve E d 26 1 6 8 Temporal Decimationy eres op b Ra pe db onere 28 Rockwell D835DSA iii Bt835 VideoStream III Decoder 1 7 Video Adjustments 29 1 71 4 The Hue Adjust Register 29 1 7 2 Contrast Adjust Register 29 1 7 3 The Saturation Adjust Registers SAT 29 1 74 Brightness Register 29 1 8 835 VBI Data Output Interface 3
25. Separation Filter Responses Luma Notch Filter Frequency Responses for NTSC and PAL SECAM Chroma Band Pass Filter Frequency Responses for NTSC and PAL SECAM PALISECAM PAL SECAM Amplitude in dB 20 log10 ampi Amplitude in dB 20 log10 amp w gt 100 Frequency in MHz Frequency in MHz Figure 1 7 describes the filtering and scaling operations In addition to the Y C separation and chroma demodulation illustrated in Figure 1 5 the Bt835 also supports chrominance comb filtering as an optional filtering stage after chroma demodulation The chroma demodulation generates baseband I and Q NTSC or U and V PAL SECAM color difference signals For S Video operation the digitized luma data bypasses the Y C separation block completely and the digitized chrominance is passed directly to the chroma demodulator For monochrome operation the Y C separation block is also bypassed and the saturation registers SAT_U and SAT_V are set to zero 16 D835DSA Rockwell 1835 1 0 Functional Description VideoStream III Decoder 1 5 Y C Separation and Chroma Demodulation Figure 1 7 Filtering and Scaling Horizontal Scaler Vertical Scaler Luminance A voz 7 pz Luminance C pz 1 Chroma Comb i 17 2 mI Chrominance Chrominance Vertical Filter Options 1 Luminance
26. Test Clock TCK Test Data Input TDI Test Data Out and Test Reset TRST The TRST pin will reset the JTAG controller when pulled low at any time Verification of the integrated circuit and its connection to other modules on the printed circuit board can be achieved through these five TAP pins With boundary scan cells at each digital interface and pin the Bt835 has the capability to apply and capture the respective logic levels Because all the digital pins are interconnected as a long shift register the TAP logic has access and control of all the necessary pins to verify functionality The TAP controller can shift in any number of test vectors through the TDI input and apply them to the internal circuitry The output result is scanned on the TDO pin and is externally checked While isolating the Bt835 from other components on the board the user has easy access to all Bt835 digital pins and digital interfaces through the TAP and can perform complete functionality tests without using expensive bed of nails testers Rockwell D835DSA 65 2 0 Electrical Interfaces Bt835 2 4 JTAG Interface VideoStream III Decoder 2 4 3 Optional Device ID Register The Bt835 has the optional device identification register defined by the JTAG specification This register contains information concerning the revision actual part number and manufacturer s identification code specific to Rockwell This register can be accessed through the TAP
27. by Subaddress 2 3 4 Software Reset The contents of the control registers can be reset to their default values by issuing a software reset A software reset can be accomplished by writing any value to subaddress Ox1E A read of this location returns an undefined value 64 D835DSA Rockwell Bt835 2 0 Electrical Interfaces VideoStream III Decoder 2 4 JTAG Interface 2 4 JTAG Interface 2 4 1 Need for Functional Verification As the complexity of imaging chips increases the need to easily access individual chips for functional verification becomes vital The Bt835 incorporates special circuitry that allows it to be accessed in full compliance with standards set by the Joint Test Action Group Conforming to IEEE P1149 1 Standard Test Access Port and Boundary Scan Architecture the Bt835 has dedicated pins that are used for testability purposes only 2 4 2 Approach to Testability JTAG s approach to testability uses boundary scan cells placed at each digital pin and at the digital interface a digital interface 1 the boundary between an analog block and a digital block within the Bt835 cells are interconnected into a boundary scan register that applies or captures test data to verify functionality of the integrated circuit JTAG is particularly useful for board testers using functional testing methods JTAG consists of five dedicated pins comprising the Test Access Port TAP These pins are Test Mode Select TMS
28. data load clock from the Bt835 for pixel qualifi cation and use only valid pixel cycles to load image data a default Bt835 operation Handle large and varying number of horizontal pixels per line in the VBI region compared to the active image region Rockwell D835DSA 35 1 0 Functional Description Bt835 1 8 Bt835 VBI Data Output Interface VideoStream Decoder 1 8 5 VBI Frame Output Mode In VBI frame output mode the Bt835 generates VBI data continuously i e there is no VBI active interval In essence the Bt835 acts as an ADC continuously sampling the entire video signal at 8 Fsc The Bt835 generates HRESET VRESET and FIELD timing signals in addition to the VBI data but the DVALID HACTIVE and VACTIVE signals are all held high during VBI frame output operation The behavior of the HRESET VRESET and FIELD timing signals is the same as normal YCrCb 4 2 2 output operation The HRESET VRESET and FIELD timing signals can be used by the video processor to detect the beginning of a video frame field at which point it can start to capture a full frame field of VBI data The number of VBI data samples generated on each line may vary depending on the stability of the analog composite video signal input to the Bt835 The Bt835 generates 910 16 bit VBI data words for NTSC and 1 135 16 bit VBI data words for PAL SECAM for each line of analog video input at a CLKx1 rate This is assuming a nominal or ideal video
29. immediately after NVRESET FIELD 1 VBISEL 0 blanking interval becomes active low A NVRESET 1 LASTF 1 1010 1011 EAV Previous pixel was last pixel FF 00 00 HACTIVE 0 VACTIVE 0 VBI mode occurs during of the line immediately FIELD 1 VBISEL 0 the vertical blanking before VBI mode is enabled 3 8 0 LASTNVBI 1 interval 0011 1000 SAV Next pixel is first pixel of a FF 00 00 HACTIVE 1 VACTIVE 0 VBISEL is an active HIGH line immediately after VBI FIELD 0 VBISEL 1 signal which selects VBI mode is enabled 2 5 NVRESET 1 LASTNVBI 1 data line 0010 0101 EAV Previous pixel was last FF 00 00 HACTIVE 0 VACTIVE 0 In Bt835 this EAV code pixel of last line in FIELD 0 VBISEL 1 occurs during VBI mode vertical blanking 9 D NVRESET 1 LASTNV 1 interval during VBI 1001 40 mode SAV Next pixel is first pixel FF 00 00 HACTIVE 1 VACTIVE 1 Active video line data are of FIRST active FIELD 0 VBISEL 0 processed at the rising acquired line 8 0 NVRESET 1 1 or leading edge of 1000 0000 58 D835DSA Rockwell Bt835 2 0 Electrical Interfaces VideoStream III Decoder Table 2 6 VIP SAV and EAV Codes Under Full Resolution 2 of 3 2 2 Output Interface Code Event Description Inserted Headers and Type raster Reference Code TASKS 8 pee F
30. implemented with a six tap interpolation filter while a maximum of five tap interpolation is used for vertical scaling with a line store The video image can be arbitrarily cropped by programming the ACTIVE flag to reduce the number of active scan lines and active horizontal pixels per line The Bt835 also supports a temporal decimation feature that reduces video bandwidth by allowing frames or fields to be dropped from a video sequence at regular but arbitrarily selected intervals Rockwell D835DSA 5 1 0 Functional Description Bt835 1 1 Functional Overview VideoStream Decoder 1 1 6 Input Interfaces Analog Video Input Analog video signals are input to the Bt835 via a four input multiplexer that can select between four composite source inputs or between three composite input sources and a single S Video input source When an S Video source is input to the Bt835 the luma component is fed through the input analog multiplexer and the chroma component is fed directly into the C input pin An AGC circuit enables the Bt835 to compensate for reduced amplitude in the analog signal input The clock signal interface consists of two pins for crystal connection and two clock output pins These crystal pins connect to any standard 14 318 MHz low jitter 50 ppm or better crystal for NTSC PAL SECAM operation The on board PLL circuit generates output clocks for interface to the graphics controller or frame buffer CLKx2 is output at ful
31. in detail Table 2 5 Reference Byte XY 7 0 and its Individual Bit Information Bits Name Event Description XY 7 T bit Task Bit Active Video Data T bit 1 VBI Data T bit 0 XY 6 F bit Field ID Even Field F bit 1 Odd Field F bit 0 XY 5 V bit Vertical Blanking ID Active Video Line V bit 0 Lines during Vertical Blanking V bit 1 XY 4 H bit Horizontal Blanking ID Active Pixels H bit 0 Pixels during Horizontal Blanking H bit 1 XY 3 Parity Error Detection Bit H bit V bit __ Inverse T bit XY 2 P2 Parity Error Detection Bit Fbit H bit Inverse T bit XY 1 P1 Parity Error Detection Bit Fbit X V bit 1 Inverse T bit XY 0 PO Parity Error Detection Bit Fbit V bit __ H bit NOTE S _ indicates Exclusive OR bit wise operation The task bit T distinguishes between visible active video to be displayed and selected raw VBI ADC samples that are to be placed in off screen memory The V bit indicates the vertical blanking region of a digital video field it is derived from the VACTIVE signal The H bit indicates the horizontal blanking region of a digital video line For SAV codes the H bit is always zero and for EAV codes the H bit is always one Video lines that are not selected by the active video acquisition window do not need to appear on the VIP bus and during this time the VIPEN signal 15 held LOW VBI data is
32. interrupt masked DEFAULT 1 CCVALID interrupts enabled Enables EDS capture 0 EDS capture DEFAULT 1 EDS capture enabled Enables CC capture 0 CC capture DEFAULT 1 CC capture enabled FIFO overflow 0 overflow since bit was cleared DEFAULT 1 Overflow Data Available 0 FIFO is empty DEFAULT 1 or more bytes available Status of current byte in FIFO 0 byte 1 5 byte DEFAULT Status of current byte in FIFO 0 Low byte DEFAULT 1 High byte 90 D835DSA Rockwell 1835 4 0 Control Register Description VideoStream III Decoder 0X20 CC DATA DEFAULT 0xB8 CCDATA 7 0 CCDATA 7 0 Captured CC or EDS data 0X21 GPIO DEFAULT 0x00 The GPIO register is an eight bit register which either drives the GPIO pins or reflects their state Writes to this register drive the related GPIO pins Reads reflect the status of the GPIO pins To properly read a GPIO pin it must be tristated via the GPIO NOE register GPIO 7 0 GPIO 7 0 GPIO Data 0X22 GPIO NOE DEFAULT OxFF The GPIO NOE register controls the drive of each GPIO pin The reset condition tristates all GPIO pins This allows the user to configure the power up condition of their board NOE 7 0 NOE 7 0 Tristate controls for the GPIO pins 0 GPIO outputs enabled 1 GPIO outputs tristated DEFAULT Rockwell D835DSA 91 4 0 Control Register Desc
33. is mapped to VD 15 8 and the second byte is mapped to VD 7 0 with VD 7 and VD 15 being the MSBs The Bt835 uses the same 16 pin data port for VBI data and YCrCb 4 2 2 image data The byte pair ordering is programmable Figure 1 19 Bt835 Data Path VBI Data imati Y C Composite _ Decimation Analog Filter Interpolation Filter 8xFsc 4xFsc Decimation Filter Y C Separation Filter VBI Composite Data Analog e The VBI datastream is not pipeline delayed to match the YCrCb 4 2 2 image output data with respect to horizontal timing i e valid VBI data is output earlier than YCrCb 4 2 2 relative to the Bt835 HRESET signal A larger number of pixels per line is generated in VBI output mode than in YCrCb 4 2 2 output mode The downstream video processor must be capa ble of dealing with a varying number of pixels per line to capture VBI data as well as YCrCb 4 2 2 data from the same frame The following pins be used to implement this solution VD 15 0 VACTIVE HACTIVE DVALID VRESET HRESET CLKx1 CLKx2 QCLK This should allow the downstream video processor to correctly load the VBI data and the YCrCb 4 2 2 data Because the 8 Fsc data stream does not pass through the interpolation fil ter the sample stream is not locked synchronized to the horizontal sync timing The only implication of this is that the sample locations on ea
34. is because the square pixel clock rates are slower than 4 Fsc clock rate i e 12 27 MHz for NTSC and 14 75 MHz for PAL UltraLock accommodates line length variations from nominal time line intervals in the incoming video by always acquiring more samples at an effective 4 Fsc rate than the particular video format requires UltraLock interpolates to the required number of pixels so that it maintains the stability of the original image despite variation in the line length of the incoming analog waveform The example illustrated in Figure 1 3 shows three successive lines of video being decoded for square pixel NTSC output The first line is shorter than the nominal NTSC line time interval of 63 5 us On this first line a line time of 63 2 us sampled at 4 Fsc 14 32 MHz generates only 905 pixels The second line matches the nominal line time of 63 5 us and provides the expected 910 pixels Finally the third line is too long at 63 8 within which 913 pixels are generated In all three cases UltraLock outputs only 780 pixels Rockwell D835DSA 11 1 0 Functional Description Bt835 1 3 UltraLock VideoStream III Decoder Figure 1 3 UltraLock Behavior for NTSC Square Pixel Output Analog Waveform Line 63 2 us 63 5 us 63 8 us Length Pixels 905 pixels 910 pixels 913 pixels Per Line Pixels Sent to 4 7 the Pixel 780 pixels ______ 780 pixels 780 pixels Bus by UltraLock UltraLock can be used to e
35. locked PLL locked CCVLD CC Data Valid 0 No CC EDS data CC EDS data available LOF Luma ADC overflow Indeterminate when ADC is sleeping 0 Normal Luma ADC overflow Chroma ADC overflow Indeterminate when ADC is sleeping 0 Normal Chroma ADC overflow Rockwell D835DSA 79 4 0 Control Register Description Bt835 VideoStream Decoder When bit 0 of the test register at location OxFC is set to 1 the STATUS register reports back the following conditions NSPLAY NLVTTL FIELD NUML PLL CCVLD LOF COF NSPLAY NLVTTL FIELD NUML PLL CCVLD LOF COF Special Play Status Input vertical sync timing non standard 0 In VCR special play mode Normal mode Pad threshold indicator 0 3 3 input thresholds 1 5 input thresholds Field Identifier 0 Field 1 Field Number of lines per frame 0 525 1 625 PLL Lock O PLL not locked PLL locked CC Data valid 0 No CC EDS data CC EDS data available Luma ADC overflow Indeterminate when ADC is sleeping 0 Normal Luma ADC overflow Chroma ADC overflow Indeterminate when ADC is sleeping 0 Normal 1 ADC overflow 80 D835DSA Rockwell 1835 4 0 Control Register Description VideoStream III Decoder 0X01 INPUT DEFAULT 0x00 The INPUT register controls the format of the incoming video which mux input is being use
36. minimize artifacts when scaling to non integer scaling ratios 1 6 4 Chrominance Scaling A 2 tap 32 phase interpolation filter is used for horizontal scaling of chrominance Vertical scaling of chrominance is implemented through chrominance comb filtering using a line store followed by simple decimation or line dropping 1 6 5 Scaling Registers Horizontal Scaling Ratio Register HSCALE HSCALE is programmed with the horizontal scaling ratio When outputting unscaled video in NTSC the Bt835 will produce 910 pixels per line This corresponds to the pixel rate at fo 4 Fsc This register is the control for scaling the video to the desired size For example square pixel NTSC requires 780 samples per line while CCIR601 requires 858 samples per line HSCALE HI and HSCALE LO are two 8 bit registers that when concatenated form the 16 bit HSCALE register The method below uses pixel ratios to determine the scaling ratio The following formula is used to determine the scaling ratio to be entered into the 16 bit register NTSC HSCALE 910 1 4096 PAL SECAM HSCALE 1135 Puesirea 1 4096 where Desired number of pixels per line of video includ ing active sync and blanking For example to scale PAL SECAM input to square pixel QCIE the total number of horizontal pixels is 236 HSCALE 1135 236 1 4096 15602 0x3CF2 An alternative method for determining
37. remain the same for 16 bit or 8 bit modes 16 bit modes use CLKx1 as the reference 8 bit modes use CLKx2 Figure 2 8 shows the video timing for SPI mode 1 Figure 2 7 Bt835 Synchronous Pixel Interface Mode 1 SPI 1 CBFLAG FIELD QCLK L e VD 15 0 OE CLKx1 4 Fsc CLKx2 8 Fsc Bt835 Figure 2 8 Basic Timing Relationships for SPI Mode 1 DVALID ACTIVE CLKx1 or CLKx2 QCLK CbFLAG 5 0 50 D835DSA Rockwell Bt835 2 0 Electrical Interfaces VideoStream Decoder 2 2 Output Interface 2 2 4 Synchronous Pixel Interface SPI Mode 2 ByteStream In SPI mode 2 the Bt835 encodes all video timing control signals onto the pixel data bus ByteStream is the 8 bit version of this configuration Because all timing data is included on the data bus a complete interface to a video controller can be implemented in only nine pins one for CLKx2 and eight for data When using coded control the RANGE bit and the CODE bit must be programmed high When the RANGE bit is high the chrominance pixels both Cr and Cb are saturated to the range 2 to 253 and the luminance range is limited to the range 16 to 253 In SPI mode 2 the chroma values of 255 and 254 and the luminance values of 0 to 15 are inserted as control codes to indicate video events Table 2 2 chroma value of 255 is
38. setup 8 bit mode QCLK to data hold 8 bit mode 1 Because QCLK is generated with a gated version of CLKx1 or CLKx2 the timing in symbols 7 and 8 are subject to changes in the duty cycle of CLKx1 and CLKx2 If crystals are used as clock sources for the Bt829A the duty cycle is symmetric This assumption is used to generate the timing numbers shown in 7 and 8 For non symmetric clock sources use the following 2 Parenthesis indicate max CLKx1 CLKx2 to Data Delay when using VDDO 3 3 V xtal period CLKx1 to qclk max CLKx1 to data max or symbol 1 symbol 41 max symbol 5 max NTSC 34 9 ns 8 ns 11 ns 31 9 ns PAL 28 2 ns 8 ns 11 25 2 ns xtal period CLKx1 to qclk CLKx1 to data min or symbol 1 symbol 41 min symbol 5 min NTSC 34 9 ns 0 ns 3 ns 37 9 ns PAL 28 3 ns 0 ns 3 ns 31 3 ns xtal period 2 CLKx2 to qclk max CLKx2 to data max or symbol 1 2 symbol 42 max symbol 6 max NTSC 17 5 ns 8ns 11 ns 14 5 ns PAL 14 1 ns 8 ns 11 ns 11 1 ns period 2 CLKx2 to qclk CLKx2 to data min or symbol 1 2 symbol 42 min symbol 6 min NTSC 17 5 ns 0 ns 3 ns 20 5 ns PAL 14 1 ns 0 ns 3 ns 17 1 ns Rockwell D835DSA 103 5 0 Parametric Information Bt835 5 2 AC Electrical Parameters VideoStream III Decoder Figure 5 1 Clock Timing Diagram or XT1I b oc er
39. the equation becomes NTSC HDELAY 135 754 HACTIVE amp Ox3FE PAL SECAM HDELAY 186 922 HACTIVE amp Ox3FE In this equation the HACTIVE value cannot be cropped Vertical Delay Register VDELAY VDELAY is programmed with the delay between the rising edge of VRESET and the start of active video lines It determines how many lines to skip before initiating the ACTIVE signal and is programmed with the number of lines to skip at the beginning of a frame Vertical Active Register VACTIVE VACTIVE is programmed with the number of lines used in the vertical scaling process The actual number of vertical lines output from the Bt835 is equal to this register multiplied by the vertical scaling ratio If VSCALE is set to 0x1 A00 4 1 then the actual number of lines output is VACTIVE 4 If VSCALE is set to 0x0000 1 1 then VACTIVE contains the actual number of vertical lines output NOTE S It is important to note the difference between the implementation of the horizontal registers HSCALE HDELAY and HACTIVE and the vertical registers VSCALE VDELAY and VACTIVE Horizontally HDELAY and HACTIVE are programmed with respect to the scaled pixels defined by HSCALE Vertically VDELAY and VACTIVE are programmed with respect to the number of lines before scaling before VSCALE is applied Rockwell D835DSA 27 1 0 Functional Description Bt835 1 6 Video Scaling Cropping and Temporal Decimation VideoStream
40. the decoded V vector of the chrominance Values from 0x00 to OxFF are allowed 0 14 HUE DEFAULT 0x00 The HUE register is an 8 bit value which applies phase offset to the decoders internal subcarrier Values from 0x00 to OxFF are allowed Rockwell D835DSA 83 4 0 Control Register Description Bt835 VideoStream Decoder 0 15 CONTROL_0 DEFAULT 0x00 7 6 5 4 3 2 1 0 LNOTCH SVID LDEC HFILT 1 0 PEAKEN PSEL 1 0 LNOTCH SVID LDEC HFILT 1 0 PEAKEN PSEL 1 0 Enables luma notch filter 0 enabled DEFAULT 1 Notch disabled Enables Y C video SVID has no effect on LNOTCH 0 disabled DEFAULT 1 Y C enabled Enables luma filtering 0 Luma filters enabled DEFAULT Luma filters disabled When LDEC is a 0 used to select which horizontal low pass filter is used 00 DEFAULT 01 CIF 10 QCIF Required for SECAM 11 ICON Enables luminance peaking filters 0 Peaking filters disabled DEFAULT 1 filters enabled Selects peaking response 00 2 dB at 3 58 4 43 MHz DEFAULT 01 3 5 dB at 3 58 4 43 MHz 10 5 0 dB at 3 58 4 43 MHz fsc 11 6 0 dB at 3 58 4 43 MHz fsc 84 D835DSA Rockwell 835 4 0 Control Register Description VideoStream III Decoder 0x16 CONTROL_1 DEFAULT 0x1C 6 5 4 3 2 1 0 VBIEN FRAME VBITFMT CAGC CKILL SC_SPD HACT Reserved
41. the value in the saturation adjust register for a total chrominance gain range of 0 to 16 times the original signal Automatic chrominance gain control can be disabled by setting the CAGC bit in the CONTROL_1 0x16 register to a logical 0 1 9 2 Low Color Detection and Removal If a color burst of 25 percent NTSC or 35 percent PAL SECAM or less of the nominal amplitude is detected for 127 consecutive scan lines the color difference signals U and V are set to 0 When the low color detection is active the reduced chrominance signal is separated from the composite signal to generate the luminance portion of the signal The resulting Cr and Cb values are 128 Output of the chrominance signal is re enabled when a color burst of 43 percent NTSC or 60 percent PAL SECAM or greater of nominal amplitude is detected for 127 consecutive scan lines Low color detection and removal can be disabled by setting the CKILL bit in the CONTROL 1 0x16 register to a logical 0 Rockwell D835DSA 39 1 0 Functional Description Bt835 1 9 Closed Captioning and Extended Data Services Decoding VideoStream Decoder 1 9 3 Coring The Bt835 video decoder performs a coring function in which it forces all values below a programmed level to zero This is useful because the human eye is more sensitive to variations in black images By taking near black images and turning them into black the image appears clearer to the eye Four luma coring values c
42. used to indicate that the associated luma pixel is a control code a pixel value of 255 also indicates that the CbFlag is high 1 the current pixel is a Cb pixel Similarly a pixel value of 254 indicates that the luma value is a control code and the CbFlag is low Cr pixel The first pixel of a line is guaranteed to be a Cb flag however due to code precedence relationships the HRESET code may be delayed by one pixel so HRESET can occur on a Cr or a Cb pixel Also at the beginning of a new field the relationship between VRESET and HRESET may be lost typically with video from a VCR As a result VRESET can occur during either a Cb or a Cr pixel Figure 2 9 demonstrates coded control for SPI mode 2 ByteStream Table 2 3 shows the pixel data output ranges Independent of RANGE decimal 128 indicates zero color information for Cr and Cb Black is decimal 16 when RANGE is equal to 0 Code 0 occurs when RANGE 1 Figures 2 10 and 2 11 illustrate video timing for SPI modes 1 and 2 Table 2 2 Description of the Control Codes in the Pixel Stream Luma Video Event Description Value Value 0x00 OxFF This is an invalid pixel last valid pixel was a Cb pixel OxFE This is an invalid pixel last valid pixel was a Cr pixel 0x01 OxFF Cb pixel last pixel was the last active pixel of the line OxFE Cr pixel last pixel was the last active pixel of the line 0x02 OxFF Cb pixel next pixel is the first active pixel of the lin
43. values set the pixel dimensions of the cropped image as illustrated in Figure 1 15 24 D835DSA Rockwell 1835 1 0 Functional Description VideoStream Decoder 1 6 Video Scaling Cropping and Temporal Decimation Figure 1 15 Effect of the Cropping and Active Registers Hm pese gt Video Frame lt gt a apes oc gt s s AE 2 lt 5 7 Ue EE Video Frame VDELAY VACTIVE Cropped Image Scaled to 1 2 Size HDELAY HACTIVE Falling Edge of HRESET Rockwell D835DSA 25 1 0 Functional Description Bt835 1 6 Video Scaling Cropping and Temporal Decimation VideoStream Decoder 1 6 7 Cropping Registers Horizontal Delay Register HDELAY HDELAY is programmed with the delay between the falling edge of HRESET and the rising edge of ACTIVE The count is programmed with respect to the scaled frequency clock HDELAY should always be an even number Horizontal Active Register HACTIVE HACTIVE is programmed with the actual number of active pixels per line of video This is equivalent to the number of scaled pixels that the Bt835 should output on a line For example if this register contained 90 and HSCALE was programmed to down scale by 4 1 then 90 active pixels would be output The 90 pixels would be a 4 1 scaled image of the 360 pixels at CLKx1 starting at count HDELAY HAC
44. 0 1 9 1 InttOdUctlOn uos ore Hoa cte erg eos a ehe t A has pte 30 1 9 2 lt lt de tate el e IK Poen tae PE OU qose 30 1 8 3 Functional 32 1 8 0 Line Output 0 4 32 1 8 5 VBI Frame Output Mode 36 1 9 Closed Captioning and Extended Data Services 37 1 9 1 Automatic Chrominance Gain 39 1 9 2 Low Color Detection and 39 1 9 95 etae estote as Tatio ee 40 2 0 Electrical 41 2 1 mmm 41 2 1 1 Analog Signal 2 2 41 2 1 2 Multiplexer Considerations 4 41 2 1 8 Autodetection of NTSC or PAL SECAM 42 2 1 4 Hash A D 42 241 5 AD Glamping eoe cx Rec e RE ER ER RC CAR 42 2 1 6 Power Up Operation 42 217 Digi
45. 12 Start gt Master sends 81835 chip address i e 0x89 or 0 8 ACK Bt835 generates ACK on successful receipt of chip address Data 0 Bt835 sends first data byte to Master 0 Master generates on successful receipt of 1st data byte 2 Data n 1 Bt835 sends n 1 th data byte to Master ACK n 1 Master generates ACK on successful receipt of n 1 th data byte Data n Bt835 sends nth data byte to Master NO ACK Master does not acknowledge nth data byte 2 Stop Master generates STOP to end transfer where 26 Start 12 start condition and 81835 chip address including the R W bit Subaddress the 8 bit subaddress of the Bt835 register MSB first Data n the data to be transferred to from the addressed register 12 Stop 2 stop condition Figure 2 14 Protocol Diagram Data Write START SR REPEATED START CHIP ADDR A SUB ADDR A DATA A DATA P STOP 0x88 or 0 8 8 Bits A ACKNOWLEDGE NON ACKNOWLEDGE Data Read From M B 5 CHIP ADDR A DATA A ee DATA P TORT Master to 0x89 or 0 8 From Bt835 to Master Write Followed by Read CHIP ADDR A SUB ADDR A sr CHIP ADDR data A eee A DATA P 0 88 Repeated Register Start Pointed to
46. 2x Oversampling and Optional Low Pass Filter Response PAL SECAM Amplitude in dB 20 log10 ampl T T Full Spectrum Pass Band 0 4 CIF gar 1 5 Jos gt cw 8 2 4 AT 5 o 1 8 2 5L 4 5 6 i L m i 0 0 5 1 1 5 2 2 5 3 3 5 Frequency MHz The Bt835 implements horizontal scaling through poly phase interpolation The Bt835 uses 32 different phases to accurately interpolate the value of a pixel This provides an effective pixel jitter of less than 6 ns In simple pixel and line dropping algorithms non integer scaling ratios introduce a step function in the video signal that effectively introduces high frequency spectral components Poly phase interpolation accurately interpolates to the correct pixel and line position providing more accurate information This results in more aesthetically pleasing video as well as higher compression ratios in bandwidth limited applications For vertical scaling the Bt835 uses a line store to implement four different filtering options The filter characteristics are shown in Figure 1 11 The Bt835 provides up to 5 tap filtering to ensure removal of aliasing artifacts Figure 1 12 shows the combined responses of the luma notch and 2x oversampling filters Rockwell D835DSA 19 1 0 Functional Description Bt835 1 6 Video Scaling Cropping and Temporal Decimation Figure 1 11 Frequency
47. 7 Bt835 Address Matrix 12C Address I2CCS Pin Bt835 Base R W Bit Action 88 0 10001000 0 Write 10001000 1 Read 8A 1 10001010 0 Write 10001010 1 Read 2 3 3 Reading and Writing After transmitting a start pulse to initiate a cycle the master must address the Bt835 To do this the master must transmit one of the four valid Bt835 addresses with the Most Significant Bit MSB transmitted first After transmitting the address the master must release the SDA line during the low phase of the SCL and wait for an acknowledge If the transmitted address matches the selected Bt835 address the Bt835 responds by driving the SDA line low generating an acknowledge to the master The master samples the SDA line at the rising edge of the SCL line and proceeds with the cycle If no device responds including the Bt835 the master transmits a stop pulse and ends the cycle If the slave address R W bit is low indicating a write the master transmits an 8 bit byte to the Bt835 with the MSB transmitted first The Bt835 acknowledges the transfer and loads data into its internal address register The master then issues a stop command a start command or transfers another 8 bit byte MSB first which is loaded into the register specified to by the internal address register The Bt835 then acknowledges the transfer and increments the address register in preparation for the next transfer As before the master may issue a stop comman
48. 818 879 7414 Fax 818 879 7417 Standard Part H143 18 Low Profile Part HH143 18 The clock source tolerance should be 50 parts per million ppm or less but 100 ppm is acceptable Devices that output CMOS voltage levels are required The load capacitance in the crystal configurations may vary depending on the magnitude of board parasitic capacitance The Bt835 is dynamic to ensure proper operation the clocks must always be running with a minimum frequency of 14 318 MHz See Figure 2 2 for a diagram of the two clock options The CLKx1 and CLKx2 outputs from the Bt835 are generated from an internal PLL CLKx2 operates at 8x FSC while CLKx1 operates at 4xFSC where FSc represents the frequency of the NTSC or PAL subcarrier Figure 2 2 Clock Options XTOI XTOO Osc 14 318 MHz Typical Single ended Oscillator 14 318 MHz 47 47 pF Typical Fundamental Crystal Oscillator 44 D835DSA Rockwell Bt835 2 0 Electrical Interfaces VideoStream III Decoder 2 1 Interface 2 1 10 2X Oversampling and Input Filtering To avoid aliasing artifacts digitized video may need to be band limited Because the Bt835 samples at 8xFsc no filtering is usually required at the input to the A Ds However if noise or other signal content is expected above 14 32 MHz in NTSC and 17 73 MHz in PAL the optional anti aliasing filter shown in Figure 2 3 may be included in the input signal pa
49. 835 decodes this signal as if it were video For example it will digitize at 8xFsc decimate filter to a 4xFsc sample stream separate color to derive luma and chroma component information and interpolate for video synchronization and horizontal scaling This process is shown in Figure 1 18 Figure 1 18 Bt835 YCrCb 4 2 2 Data Path P Composite Decimation Interpolation YCrCb a Que ici fa 8xFsc 4xFsc 30 D835DSA Rockwell Bt835 1 0 Functional Description VideoStream III Decoder 1 8 Bt835 VBI Data Output Interface The Bt835 can be configured in a mode known as VBI data passthrough to enable capture of the VBI region ancillary data for later processing by software In this mode the VBI region of the video signal is processed as follows The analog composite video signal is digitized at 8 Fsc 28 63636 MHz for NTSC and 35 46895 MHz for PAL SECAM This 8 bit value repre sents a number range from the bottom of the sync tip to the peak of the composite video signal The 8 bit data stream bypasses the decimation filter Y C separation fil ters and the interpolation filter see Figure 1 19 The Bt835 provides the option to pack the 8 Fsc data stream into a 2 byte wide stream at 4 before outputting it to the VD 15 0 data pins Alter natively it can be output as an 8 bit 8 Fsc data stream on pins VD 15 8 In the packed format the first byte of each pair on a 4 Fsc clock cycle
50. 986 uoisiwq 1ueuurejoju 21161q SW31SAS HOLOnQNOOIN3S 18 8235 Sio NOISSIWH3d N3LLIHM 1 G3MOTYV 3SN NOLLVNIW3SSIQ 0 20 5 20 2042095 7202042098 eo ozuvors LebozuvOrS ieh ozuvors iebozuvors idpozuvors 9080 9080 9080 9080 9080 9080 9080 n NE foe nro nro nro nuo 220 120 020 810 W 0 4 1 0 0 0 5 5080 00 20 0 0 Ho m 93 ta e 580 EX vo 0 SH zio X oro HK 69 80 4 29 LX 99 5 so R 5 4 55 29 50 02470 X1 PX S080 BOO0 ZOHZOYO 291 Mee 18 Qe 10 osa x Se szy Lx Hw 158 EAA 928 lt revved C ev eza LX zzv 228 12 iza 51 S 618 91 91 v SH Liv 4 ov to 0zuvovs ev S080 2082070 av myo Shed 19 9v 99 ov H v ew IN d3MOd 75 D835DSA Rockwell 835 VideoStream III
51. Advance Information This document contains information on a product under development The parametric information contains target parameters that are subject to change Bt835 VideoStream Decoder Video Capture Processor and Scaler for TV VCR Analog Input The Bt835 VideoStream 11 Decoder is a high quality single chip composite Distinguishing Features NTSC PAL SECAM video and S Video decoder Low operating power Single chip composite S Video NTSC PAL consumption and power down capability make it an ideal low cost solution for SECAM to YCrCb digitizer PC video capture applications on both desktop and portable system platforms Ultralock The 81835 supports square pixel and CCIR601 resolutions for NTSC PAL and Square pixel and CCIR601 resolution for SECAM video The Bt835 has a sophisticated 3 line adaptive comb filter that NTSC NTSC 4 43 maintains full vertical video resolution and eliminates traditional comb filter NTSC without 7 51 pedestal artifacts The Bt835 s flexible pixel ports support digital video input as well as PAL B D G H I N combination VIP VMI and ByteStream interfaces to popular graphics controllers im NTSC 3 line adaptive comb filter Functional Block Diagram e Arbitrary horizontal and 5 tap vertical filtered scaling XTO Hardware closed caption decoder MUXO Vertical Blanking Interval VBI
52. DELAY 7 0 0 50 0 50 0 72 0 50 0 72 0 72 0 50 0 50 0x1B 512 104 oopiA ayisoduiog segia uondijoseq jeuonoung 0 4 Bt835 1 0 Functional Description VideoStream III Decoder 1 5 Y C Separation and Chroma Demodulation 1 5 Y C Separation and Chroma Demodulation Y C separation and chroma decoding are handled as shown in Figure 1 4 and Figure 1 5 A 3 line adaptive comb filter is used to separate luminance and chrominance for NTSC video A notch band pass filter is used for PAL SECAM video Figure 1 6 displays the filter responses The optional chroma comb filter when using notch filter is implemented in the vertical scaling block See the section on Video Scaling Cropping and Temporal Decimation in this chapter Figure 1 4 Y C Separation and Chroma Demodulation for Composite NTSC Video Composite Notch Filter Y Y Luma Switch DAAA Luma Comb Video Delay ES Adaptive Logic and Vertical Transition Detector Band Pass Filter Low Pass Filter Rockwell D835DSA 15 1 0 Functional Description Bt835 1 5 Y C Separation and Chroma Demodulation VideoStream III Decoder Figure 1 5 Y C Separation and Chroma Demodulation for Composite PAL Video Composite Y Notch Filter Band Pass Filter Low Pass Filter cos Figure 1 6 NTSC and PAL SECAM Y C
53. Decoder 3 0 PC Board Layout Considerations Figure 3 6 Bt835 Typical Circuit Schematic 3 of 5 3 9 Sample Schematics Y 5 jo aus 8661 80 _ NOISSIH3d N3 LLIBM v 089X 0018 wama Q3MOTTV 526 YO NOLLYNINaSSIG ON ino Adseera JNI AHV L3lHd 12126 Wo ues SW3ISAS HOLONGNOOINES gt BOK SPN AL aN A LY 99 55 29 s 13554 SH 89 4H 150 80 2 5 zso eouvrers 5 S0 80HvZvG 5080 5080 5080 60 190090298 wee Wee 5080 5080 T TO Wee 2 va L L H SIG 99 NO AT NOO 9 Xu T XT 5 88 99 29 2 20189 E 440 Iai 00198 79 59 v Odo f enu A F4 19 J3I8VN3 L m 2080 8 T 70195 935818 55 6691 4 2 2 50190 5 55 8691 gt 2090 9 20149 AL z 15 4641 1099 S v 10195
54. GH and VALID is held LOW during vertical scaling This behavior causes a SAV code to be generated at the start of active video but an EAV code does not get generated until after all dropped lines are filled with hex 00 EAV codes follow invalid data lines but precede another valid pixel line During temporal decimation VACTIVE signal is forced inactive during a dropped field or frame This means that although SAV and EAV codes are generated all lines are being treated as occurring in the vertical blanking interval Thus vertical blanking ID V bit must be set to HIGH during dropped fields indicating vertical blanking However the Bt835 does not support the temporal 2 2 6 CCIR601 Compliance When the RANGE bit is set to zero the output levels are fully compliant with the CCIR601 recommendation CCIR601 specifies that nominal video has Y values ranging from 16 to 235 and Cr and Cb values ranging from 16 to 240 Excursions outside this range are allowed to handle non standard video It is mandatory that 0 and 255 be reserved for timing information 60 D835DSA Rockwell Bt835 2 0 Electrical Interfaces VideoStream III Decoder 2 3 1 C Interface 2 3 I C Interface The inter integrated circuit bus is a two wire serial interface Serial Clock SCL and Data Lines SDA are used to transfer data between the bus master and the slave device The Bt835 can transfer data at a maximum rate of 100 kbps The Bt835 operates as a sla
55. IELD ID Active Video or VBI mode ODD EVEN EAV Previous pixel was last pixel 00 00 HACTIVE 0 VACTIVE 1 FIELD signal and F bit in of any active line but NOT FIELD 0 VBISEL 0 control codes do not the line immediately before 9 D NVRESET 1 transition at the same last active line 1991 10 time SAV Next pixel is first pixel of any 00 00 HACTIVE 1 VACTIVE 1 EAV code always active acquired line FIELD 0 VBISEL 0 precedes SAV code 8 0 NVRESET 1 digital video line 1000 0000 EAV Previous pixel was last pixel 00 00 HACTIVE 0 VACTIVE 1 LASTV indicates the of the line immediately FIELD 0 VBISEL 0 arrival of last active line before last active line ONLY Pe 0 NVRESET 1 LASTV 1 during active video SAV Next pixel is first pixel of FF 00 00 HACTIVE 1 VACTIVE 0 LASTV is active high only first inactive line FIELD 0 VBISEL 0 during the last half of last ee NVRESET 1 LASTV 1 active line and the first 1010 1011 half of first vertical blanking line EAV Previous pixel was last pixel 00 00 HACTIVE 0 VACTIVE 0 LASTF indicates the of the line immediately FIELD 0 VBISEL 0 arrival of last line before before NVRESET goes low F 1 NVRESET 1 LASTF 1 NVRESET becomes active 1111 0001 low SAV Next pixel is first pixel of the 00 00 HACTIVE 1 VACTIVE 0 LASTF is active high only first inactive line after FIELD 0 VBISEL 0
56. Odi AL E 9NH 5552 9641 EI T WHS 30 vy v 5641 zx 2 2 EZE 2 lt ZU bong 9 TXATO 13834 or 6t 2641 S v 11 25 13538 e 8 16 2591 ANY e 9 SE Sid lt 62235 T SRUDVA amp 16 2 ROG m A 05 62 51385 vas 82 42 v aly 195 A Sid ae ee t LU 109 ve ez zi 20 T ININ 1099 lt 1 o A IAE E E aoa lt p e 1353 MM OE AA os lt 7 fod 6 L TA 8049 2 2 A vorNoo lt t zoo 9 5 or 05 gt 5 1 Xm 4 oa 2 2 oe i 1045 5 T 330 0045 HOLOANNOO 18 Eon 2 d Vx y 0095 lt Sabe e P 2 lt aono Ha a 8 8 ZTO m wono NI TIV G3l3IGOIN 52 52 x TXHTO pn ae T ES NO 628 X 2 DA 2 z Ur at S 5100 Hi S ZTA T Hi s lt vas BIA 5 TWA 1 9 T ETA y 2 7 tu 7 2 FIA TA A VIE ga 9 STA OIA i lt au 6991 5 Y T0 lt iny moy lt 19539 390433 TIY
57. R601 429 x 262 360 x 240 11F0 1E00 1A00 PAL CCIR601 432 x 312 360 x 288 1A09 1E00 1A00 PAL SQ Pixel 472 x 312 384 x 288 1677 1E00 1A00 QCIF NTSC SQ Pixel 195 x 131 160 x 120 1 00 1200 4 1 NTSC CCIR601 214 x 131 180 x 120 3409 1A00 1200 PAL CCIR601 216 x 156 180 x 144 4412 1A00 1200 PAL SQ Pixel 236 x 156 192 144 3CF2 1A00 1200 ICON NTSC SQ Pixel 97 x 65 80 x 60 861A 1200 0200 8 1 NTSC CCIR601 107 x 65 90 x 60 7813 1200 0200 PAL CCIR601 108 x 78 90 x 72 9825 1200 0200 PAL SQ Pixel 118 x 78 96 x 72 89E5 1200 0200 1 PAL M HSCALE and VSCALE register values should be the same for NTSC 2 SECAM HSCALE and VSCALE register values should be the same as for PAL Vertical Scaling Ratio Register VSCALE VSCALE is programmed with the vertical scaling ratio It defines the number of vertical lines output by the Bt835 The following formula should be used to determine the value to be entered into this 13 bit register The loaded value is a two s complement negative value VSCALE 0 10000 scaling ratio 1 512 6 For example to scale PAL SECAM input to square pixel QCIE the total number of vertical lines for PAL square pixel is 156 see Table 1 5 VSCALE 0x10000 4 1 1 512 amp Ox FFF 0x 1A00 NOTE S Only the 13 least significant bits of the VSCALE value are used The user must take care not to alter the values of the three most significant bits when writing a vert
58. Responses for the Four Optional Vertical Luma Low Pass Filters Amplitude in dB 20 log10 ampl 0 0 05 0 1 0 15 0 2 0 25 03 0 35 0 4 0 45 0 5 Frequency Sampling_Frequency VideoStream Decoder Figure 1 12 Combined Luma Notch and 2x Oversampling Filter Response 3 PAL SECAM Amplitude in dB 20 log10 ampl Frequency in MHz 20 D835DSA Rockwell 1835 1 0 Functional Description VideoStream III Decoder 1 6 Video Scaling Cropping and Temporal Decimation 1 6 3 Peaking The Bt835 enables four different peaking levels by programming the PSEL 1 0 bits in the CONTROL 0 register The filter responses are shown in Figures 1 13 and 1 14 Figure 1 13 NTSC Peaking Filters Peaking Filters Amplitude dB Frequency Fs 14 3182 MHz Figure 1 14 PAL SECAM Peaking Filters Peaking Filters Amplitude dB Frequency Fs 17 7345 MHz Rockwell D835DSA 21 1 0 Functional Description Bt835 1 6 Video Scaling Cropping and Temporal Decimation VideoStream Decoder The number of taps in the vertical filter is set by the VSCALE_CTL register The user may select 2 3 4 or 5 taps The number of taps must be chosen in conjunction with the horizontal scale factor As the scaling ratio is increased the number of taps available for vertical scaling is increased In addition to low pass filtering vertical interpolation is also employed to
59. TIVE is restricted in the following manner HACTIVE HDELAY lt Total Number of Scaled Pixels For example in the NTSC square pixel format there is a total of 780 pixels including blanking sync and active regions Therefore HACTIVE HDELAY lt 780 When scaled 2 1 for the total number of active pixels is 390 Therefore HACTIVE HDELAY lt 390 The HDELAY register is programmed with the number of scaled pixels between HRESET and the first active pixel Because the front porch is defined as the distance between the last active pixel and the next horizontal sync the video line can be considered in three components HDELAY HACTIVE and the front porch Figure 1 16 illustrates the video signal regions Figure 1 16 Regions of the Video Signal Front a HDELAY Porch T Table 1 6 shows the number of clocks at the 4x sample rate the CLKx1 rate when cropping is not implemented Table 1 6 Uncropped Clock Totals CLKx1 CLKx1 CLKx1 CLKx1 Front Porch HDELAY HACTIVE Total NTSC 21 135 754 910 PAL SECAM 27 186 922 1135 26 D835DSA Rockwell Bt835 1 0 Functional Description VideoStream III Decoder 1 6 Video Scaling Cropping and Temporal Decimation The value for HDELAY is calculated using the following formula HDELAY CLKx1_HDELAY CLKx1_HACTIVE HACTIVE amp Ox3FE CLKx1 HDELAY and CLKx1 HACTIVE are constant values so
60. V Systems 68 Typical Power and Ground Connection Diagram and Parts List for 5 VI OMode 69 Typical Power and Ground Connection Diagram and Parts List for 3 3 V Mode 70 Optional 3 3 V 71 81835 typical Circuit 74 Clock Timing t ek 104 Output Enable Timing 105 JTAG Timing Diagram men 105 viii D835DSA Rockwell Bt835 List of Tables VideoStream III Decoder List of Tables Table 1 1 VideoStream Features 3 Table 1 2 81835 Pin 9 Table 1 3 Video Input Formats Supported by the 835 13 Table 1 4 Register Values for Video Input 14 Table 1 5 Scaling Ratios for Popular Formats Using Frequency Values 23 Table 1 6 Uncropped Clock Totals sias ERE 26 Table 2 1 Pixel Piti Map zt e EE OLI Cb SES Nob Ct 49 Table 2 2 Description of the Control Codes in the Pixel Stream 51 Table 2 3 Data Output Ran
61. alog Pin Input Capacitance 5 Rockwell D835DSA 101 5 0 Parametric Information Bt835 5 2 AC Electrical Parameters 5 2 AC Electrical Parameters Table 5 5 Clock Timing Parameters 1 of 2 VideoStream III Decoder Parameter Symbol Min Typ Max Units NTSC CLKx1 Rate Fei 14 318180 x MHz CLKx2 Rate 50 PPM source required Foo 28 636360 MHz PAL SECAM CLKx1 Rate Foy 17 734475 MHz CLKx2 Rate 50 PPM source required Foo 35 468950 MHz XTO and XT1 Inputs Cycle Time 1 28 2 ns High Time 2 12 ns Low Time 3 12 ES ns 102 D835DSA Rockwell Bt835 5 0 Parametric Information VideoStream III Decoder Table 5 5 Clock Timing Parameters 2 of 2 5 2 AC Electrical Parameters Parameter Symbol Min Typ Max Units CLKx1 Duty Cycle 45 55 CLKx2 Duty Cycle 40 60 CLKx2 to CLKx1 Delay 4 0 2 ns to Data Delay 5 3 11 25 ns CLKx2 to Data Delay 6 3 11 25 2 ns CLKx1 Falling Edge to QCLK Rising Edge 41 0 8 ns CLKx2 Falling Edge to QCLK Rising Edge 42 0 8 ns 8 Bit Mode Data to QCLK Rising Edge Delay 7b ns QCLK Rising Edge to Data Delay 8b 15 ns 16 Bit Mode Data to QCLK Rising Edge Delay 7a 14 ns QCLK Rising Edge to Data Delay 8a 25 ns NOTE S equations Data to QCLK setup 16 bit mode QCLK to Data hold 16 bit mode Data to QCLK
62. am III Decoder 2 2 Output Interface Figure 2 10 Video Timing in SPI Modes 1 and 2 HRESET Beginning of fields 1 3 5 7 VRESET FIELD HRESET 2 6 scan lines VDELAY 2 scan lines Beginning of fields 2 4 6 8 VRESET ACTIVE ps cc Vd i pq E ae 2 6 scan lines i VDELAY 2 scan lines VPOLE register 1 HRESET precedes VRESET by two clock cycles at the beginning of fields 1 3 5 and 7 to facilitate external field generation 2 ACTIVE pin may be programmed to be composite ACTIVE or horizontal ACTIVE 3 ACTIVE HRESET VRESET and FIELD are shown here with their default polarity The polarity is programmable via the 4 FIELD transitions with the end of horizontal active video defined by HDELAY and HACTIVE Rockwell D835DSA 53 2 0 Electrical Interfaces Bt835 2 2 Output Interface VideoStream III Decoder Figure 2 11 Horizontal Timing Signals in the SPI Modes 64 Clock Cycles at FCLKx1 HRESET gt HDELAY Clock Cycles at FDesired ACTIVE lt gt Clock Cycles at FDesired Table 2 3 Data Output Ranges
63. amples The number of VBI data samples generated on each line may vary depending on the stability of the analog composite video signal input to the Bt835 The Bt835 generates 845 16 bit VBI data words for NTSC and 1070 16 bit VBI data words for PAL SECAM on each VBI line at a CLKx1 rate This is assuming nominal or ideal video input signal 1 the analog video signal has a stable horizontal time base This is equivalent to 1690 8 bit VBI data samples for NTSC and 2 140 8 bit VBI data samples for PAL SECAM These values can deviate from the nominal depending on the actual line length of the analog video signal The VBI vertical active period is defined as the period between the trailing edge of the Bt835 VRESET signal and the leading edge of VACTIVE Note that the extent of the VBI vertical active region can be controlled by setting different values in the VDELAY register This provides the flexibility to configure the VBI vertical active region as any group of consecutive lines starting with line 10 and extending to the line number set by the equivalent line count value in the VDELAY register the VBI vertical active region can be extended into the video image region of the video signal The VBI horizontal active period starts with the trailing edge of an HRESET therefore if a rising edge of VRESET occurs after the horizontal active period has already started the VBI active period starts on the following line The HACTIVE
64. an be selected by the CONTROL_2 0x17 register These are 0 8 16 or 32 above black If the total luminance level is below the selected limit the luminance signal is truncated to the black value If the luma range is limited i e black is 16 the coring circuitry automatically references the appropriate value for black as illustrated in Figure 1 27 Similarly four chroma coring values can be selected by the CONTROL_2 0x17 register These 0 2 4 or 8 above black Figure 1 27 Coring Map Output Luma Value o 0 8 16 32 Calculated Luma Value 40 D835DSA Rockwell 2 0 Electrical Interfaces 2 1 Input Interface 2 1 1 Analog Signal Selection The Bt835 contains an on chip 4 1 MUX For the Bt835 this multiplexer can be used to switch between four composite sources or three composite sources and one S Video source In the first configuration connect the inputs of the multiplexer MUX 0 MUX 1 MUX 2 and MUX 3 to the four composite sources In the second configuration connect three inputs to the composite sources and the other input to the luma component of the S Video connector When implementing S Video the input to the chroma A D CIN should be connected to the chroma signal of the S Video connector 2 1 2 Multiplexer Considerations The multiplexer is not a break before make design Therefore during the multiplexer switching time it is possible for the input video signals to be mom
65. ates that no data is available in the FIFO Subsequently when data has been stored in the FIFO the DA bit is set to logical high Once the FIFO is half full the VALID interrupts pin signals to the system that the FIFO contents should be read in the near future The VALID pin is enabled via the INT EN bit in the STATUS register Ox 1F The system controller can then poll the CC VALID bit in the STATUS register 0x00 This ensures that the Bt835 initiated the VALID interrupt This bit can also be used applications where the VALID pin is disabled by the user 38 D835DSA Rockwell Bt835 1 0 Functional Description VideoStream III Decoder 1 9 Closed Captioning and Extended Data Services Decoding When the first byte of CC EDS data is decoded and stored in the FIFO the data is immediately placed in the CC_DATA and CC_STATUS registers and is available to be read Once the data is read from the CC_DATA register the information in the next location of the FIFO is placed in the CC_DATA and CC_STATUS registers If the controller in the system ignores the Bt835 CC_VALID interrupt pin for a sufficiently long period of time then the CC EDS FIFO will become full and the Bt835 will not be able to write additional data to the FIFO Any incoming bytes of data will be lost and an overflow condition will occur bit OR in the CC_STATUS register will be set to a logical 1 The system can clear the overflow condition
66. aturation and brightness 1 7 1 The Hue Adjust Register HUE The hue adjust register is used to offset the hue of the decoded signal In NTSC the hue of the video signal is defined as the phase of the subcarrier with reference to the burst The value programmed in this register is added or subtracted from the phase of the subcarrier which effectively changes the hue of the video The hue can be shifted by plus or minus 90 degrees Because of the nature of PAL SECAM encoding hue adjustments cannot be made when decoding PAL SECAM 1 7 2 The Contrast Adjust Register CONTRAST The contrast adjust register also called the luma gain provides the ability to change the contrast from approximately 0 percent to 200 percent of the original value The decoded luma value is multiplied by the 9 bit coefficient loaded into this register 1 7 8 The Saturation Adjust Registers SAT U SAT V The saturation adjust registers are additional color adjustment registers It is a multiplicative gain of the U and V signals The value programmed in these registers are the coefficients for the multiplication The saturation ranges from approximately 0 percent to 200 percent of the original value 1 7 4 The Brightness Register BRIGHT The brightness register is simply an offset for the decoded luma value The programmed value is added or subtracted from the original luma value which changes the brightness of the video output The luma output ranges from 0
67. by reading the CC EDS data and creating space in the FIFO for new information As a result the overflow bit is reset to a logical 0 Asynchronous reads and writes to the CC EDS FIFO will routinely occur The CC EDS circuitry writes the data the reads occur as the system controller reads CC EDS data from Bt835 These reads and writes sometimes occur simultaneously The Bt835 is designed to give priority to the read operations When the CC_DATA register data is specifically being read to clear an overflow condition the simultaneous occurrence of a read and a write will not cause the overflow bit to be reset even though the read has priority An additional read must be made to the CC_DATA register to clear the overflow condition As always the write data will be lost while the FIFO is in overflow condition The FIFO is reset when both CC and EDS bits are disabled in the CC_STATUS register any data in the FIFO is lost 1 9 1 Automatic Chrominance Gain Control The automatic chrominance gain control compensates for reduced chrominance and color burst amplitude This can be caused by high frequency loss in cabling Here the color burst amplitude is calculated and compared to nominal The color difference signals are then increased or decreased in amplitude according to the color burst amplitude difference from nominal The maximum amount of chrominance gain is 0 5 to 16 times the original amplitude This compensation coefficient is then multiplied by
68. cations are subject to change without notice PRINTED IN THE UNITED STATES OF AMERICA Table of Contents EcdRIDI rcr vii Hr PU uUuU ix 1 0 Functional Description ieee gee rk Re ea en e oec es 1 1 1 Functional OVerVIeW i S ens RR EA Qe ioo E od en bad 1 1 1 1 Bt835 Video Capture Processor for TV VCR Analog 3 1 1 2 Bt835 Architecture and 0 3 12 9 Comb Filter zs enr ou x ERES RR es ie RM 4 T 4 4 UitraboCk oes ber NIE rtr viet mor eerte gere ur v 5 1 1 5 Scaling and Cropping 5 11 67 Inp tIntertaces coss ty tu t cee 6 17 Outputinterface eesis 6 14 8 VBl Data Pass through eee bed 7 1 1 9 Closed Caption 7 Deck ae 7 Tally SIVAN Operation sats v E UE AR 7 1 2 3PimDescrIptiOns 8 1 9 UItraLOCK oet head 11 1 31 Te Challenge tete Set wee det 11 1 3 2 Operation Principles of 11 1 4 Composite Video
69. ch line are not correlated vertically Rockwell D835DSA 31 1 0 Functional Description Bt835 1 8 Bt835 VBI Data Output Interface VideoStream Decoder 1 8 3 Functional Description There are three modes of operation for the Bt835 VBI data passthrough feature 1 VBI data passthrough disabled During this default mode of operation the device decodes composite video and generates a YCrCb 4 2 2 data stream 2 VBI line output mode The device outputs unfiltered 8 Fsc data only during the vertical interval which is defined by the VACTIVE output signal provided by the Bt835 Data is output between the trailing edge of the VRESET signal and the leading edge of VACTIVE When VACTIVE is high the Bt835 outputs standard YCrCb 4 2 2 data This mode of operation is intended to enable capture of VBI lines containing ancillary data in addition to processing normal YCrCb 4 2 2 video image data 3 VBI frame output mode In this mode the Bt835 treats every line in the video signal as if it were a vertical interval line and outputs only the unfiltered 8 Fsc data on every line 1 it does not output any image data This mode of operation is designed for use in still frame capture processing applications 1 8 4 VBI Line Output Mode The VBI line output mode is enabled via the VBIEN bit in the CONTROL 1 register 0x16 When enabled the VBI data is output during the VBI active period The VBI horizontal active period is defined as the
70. cing VideoStream III Decoder 3 5 Power Up Sequencing Time between analog and digital power application to the Bt835 should always be kept to a minimum Although it is very difficult to apply all power at exactly the same time analog and digital power should be applied as closely together as possible 3 6 Digital Signal Interconnect The digital signals of the Bt835 should be isolated as much as possible from the analog signals and other analog circuitry Also the digital signals should not overlay the analog power plane Any termination resistors for the digital signals should be connected to the regular PCB power and ground planes 3 7 Analog Signal Interconnect Long lengths of closely spaced parallel video signals should be avoided to minimize crosstalk Ideally there should be a ground line between the video signal traces driving the YIN and CIN inputs Also high speed TTL signals should not be routed close to the analog signals to minimize noise coupling 72 D835DSA Rockwell 835 3 0 Board Layout Considerations VideoStream III Decoder 3 8 Latch up Avoidance 3 8 Latch up Avoidance Latch up is a failure mechanism inherent to any CMOS device It is triggered by static or impulse voltages on any signal input pin exceeding the voltage on the power pins by more than 0 5 V or falling below the GND pins by more than 0 5 V Latch up can also occur if the voltage on any power pin exceeds the voltage on a
71. comb filtering Hence two lines with different colors will not be input to the comb filter at a transition boundary Therefore the Y C signals will be fully separated and the hanging dots eliminated The Bt835 can accomplish this adaptive task on a pixel by pixel basis by using powerful DSP techniques This also ensures that the Y C separated image does not suffer from any loss of vertical resolution The Bt835 employs a proprietary technique known as UltraLock to lock to the incoming analog video signal It will always generate the required number of pixels per line from an analog source in which the line length can vary by as much as a few microseconds UltraLock s digital locking circuitry enables the VideoStream decoders to quickly and accurately lock on to video signals regardless of their source Because the technique is completely digital UltraLock can recognize unstable signals caused by VCR head switches or any other deviation and adapt the locking mechanism to accommodate the source UltraLock uses nonlinear techniques which are difficult if not impossible to implement for genlock systems Unlike linear techniques it automatically adapts the locking mechanism 1 1 5 Scaling and Cropping The Bt835 can independently reduce the video image size in both horizontal and vertical directions Using arbitrarily selected scaling ratios the X and Y dimensions can be scaled down to one sixteenth of the full resolution Horizontal scaling is
72. controller via an optional JTAG instruction Refer to Table 2 9 Table 2 9 Device Identification Register Version Part Number Manufacturer ID 0 0829 0x033D 0x0D6 4 Bits 16 Bits 11 Bits 2 4 4 Verification with the Tap Controller A variety of verification procedures can be performed through the TAP controller Using a set of four instructions the Bt835 can verify board connectivity at all digital interfaces and pins The instructions can be accessed by using a state machine standard to all JTAG controllers These are Sample Preload Extest ID Code and Bypass see Figure 2 15 Refer to the IEEE P1149 1 specification for details concerning the instruction register and JTAG state machine Rockwell has created a BSDL with the AT amp T BSD editor Should JTAG testing be implemented a disk with an ASCII version of the complete BSDL file can be obtained by contacting your local Rockwell sales office Figure 2 15 Instruction Register DUI EXTEST 0 0 Sample Preload 0 0 ID Code 0 1 Bypass 1 1 66 D835DSA Rockwell 3 0 Board Layout Considerations The layout for the Bt835 power and ground lines should be optimized for lowest noise This is accomplished by shielding the digital inputs and outputs and by providing good decoupling The lead length between groups of power and ground pins should be minimized to reduce inductive ringing 3 1 Ground Planes The ground plane area should encompas
73. d a start command or transfer another 8 bits to be loaded into the next location If the slave address R W bit is high indicating a read the Bt835 transfers the contents of the register specified to by its internal address register MSB first The master acknowledges receipt of the data and pulls the SDA line low As with the write cycle the address register 15 auto incremented in preparation for the next read 62 D835DSA Rockwell Bt835 2 0 Electrical Interfaces VideoStream III Decoder 2 3 17C Interface To stop a read transfer the host must not acknowledge the last read cycle The Bt835 will then release the data bus in preparation for a stop command If an acknowledge is received the Bt835 proceeds to transfer the next register When the master generates a read from the Bt835 the Bt835 starts its transfer from whatever location is currently loaded in the address register Because the address register might not contain the address of the desired register the master executes a write cycle and sets the address register to the desired location After receiving an acknowledgment for the transfer of data into the address register the master initiates a read of the Bt835 by starting a new PC cycle with an appropriate read address The Bt835 then transfers the contents of the desired register For example to read register brightness control the master starts write cycle with an address of 0x88 or Ox8A After recei
74. d and the source of the sample clock The details of this register are given below 7 6 5 4 3 2 1 0 Reserved MUXS 1 0 Reserved FMT 3 0 RESERVED Not used Set to 0 MUXS 1 0 Selects one of four video inputs 00 MUXO DEFAULT 01 MUXI 10 MUX2 11 MUX3 RESERVED Not used Set to 0 FMT 3 0 Selects input video format 0000 Auto format detection DEFAULT 0001 NTSC M 0010 NTSC J 0011 NTSC 4 43 0100 PAL BDGHI 0101 PAL M 0110 PAL N 0111 1000 PAL 60 1001 SECAM 0x03 0x02 VDELAY DEFAULT 0x0016 The VDELAY register is a 16 bit register which occupies two address locations starting at 0x02 VDELAY as with all 16 bit registers in the Bt835 is little endian That is the LSBs are stored at the lower address and the MSBs are stored in the upper address this case VDELAY 7 0 are at location 0x02 while VDELAY 15 8 are at location 0x03 Values between 1 and 1023 inclusive can be programmed into the VDELAY register 0x05 0x04 VACTIVE DEFAULT 0 01 0 The VACTIVE register is a 16 bit register starting at location Ox04 Values between 0 and 1023 inclusive can be programmed into the VACTIVE register 0x07 0x06 HDELAY DEFAULT 0x0078 The HDELAY register is 16 bit register starting at location 0x06 Values between 1 and 1023 inclusive can be programmed into the HDELAY register Rockwell D835DSA 81 4 0 Control Register Description
75. e OxFE Cr pixel next pixel is the first active pixel of the line 0x03 OxFF Cb pixel HRESET of a vertical active line OxFE Cr pixel HRESET of a vertical active line 0x04 OxFF Cb pixel HRESET of a vertical blank line OxFE Cr pixel HRESET of a vertical blank line 0x05 OxFF Cb pixel VRESET followed by an even field OxFE Cr pixel VRESET followed by an even field 0x06 OxFF Cb pixel VRESET followed by an odd field OxFE Cr pixel VRESET followed by an odd field Rockwell D835DSA 51 2 0 Electrical Interfaces Bt835 2 2 Output Interface Figure 2 9 Data Output in SPI Mode 2 ByteStream CLKx2 X VideoStream Decoder HRESET beginning of horizontal line during vertical blanking HRESET beginning of horizontal line during active video VD 15 8 X OxFF 0x04 X __ X 0 03 X Cb pixel Cb pixel X X 0x02 X Cb X Y X Cr X Y X Next pixel is first First active pixel of the line active pixel of the line DS X Cb X Y X OxFF X 0x00 X Cr Invalid pixel during active video Last valid pixel was a Cb pixel 424 Cb X OFE X 0x01 XX XX Last pixel of the line Last pixel code Cb pixel Cr pixel F VRESET an odd field follows yes X XX X XX X OXFE X 0x06 X XX X XX X Cr pixel 52 D835DSA Rockwell Bt835 2 0 Electrical Interfaces VideoStre
76. e mode is enabled via a user programmable bit VIPEN When the VIPEN bit is disabled all video signals are transported through the interface undisturbed Table 2 4 ITU R 656 Specification on Range of Active Video Data LUMA CHROMA Range decimal Y Range decimal CR CB Black 16 No Color 128 128 White 235 100 Saturation 16 240 16 240 Active video data are sampled as 4 2 2 and transmitted as a byte serial stream in the following order Rockwell D835DSA 55 2 0 Electrical Interfaces Bt835 2 2 Output Interface VideoStream Decoder and data all represented in 8 bit word format However during VIP mode control codes SAV and are inserted into the data stream at the start of active video and at the end of active video respectively in a digital video line SAV and EAV codes consist of a hexadecimal four word sequence in the following format 00 00 XY The first three words 00 00 a fixed preamble where FF and 00 are reserved for use in timing reference signals The fourth word contains information such as the state of field blanking the state of vertical line blanking and the state of horizontal line blanking The upper nibble of the byte XY represents the actual reference information and the lower nibble is used as error protection and correction parity bits Table 2 5 describes each bit in a word XY
77. entarily connected together through the equivalent of 200 The multiplexers cannot be switched on a real time pixel by pixel basis To improve input robustness it has been determined that adding external protection diodes and a series resistor in the path of the composite luma inputs reduces the risk of voltage or current spikes coming into and possibly damaging the part The diodes must be fast Shottky type diodes See Figure 2 1 for specifics These modifications will not degrade the video quality or sync locking capability of the Bt835 decoder They are strictly to help prevent damage due in part to unusually high out of specification voltage or current spikes on the video inputs Rockwell D835DSA 41 2 0 Electrical Interfaces Bt835 2 1 Input Interface VideoStream III Decoder Figure 2 1 Diode Protection BAT54SWT1 Schottky Barrier Diode Bt835 0 1 uF 1000 MUX 0 3 RESISTOR COAX W 0 2 750 BAT54SWT1 Schottky Barrier Diode 2 1 3 Autodetection of NTSC or PAL SECAM Video If the Bt835 is configured to decode both NTSC and PAL SECAM the Bt835 can be programmed to automatically detect which format is being input to the chip Autodetection will automatically reprogram the PLL for the format detected The Bt835 determines the video source input to the chip by counting the number of lines in a frame 2 1 4 Flash A D Converters The Bt835 uses two on chip flash A D converters to digiti
78. erpolation 82 D835DSA Rockwell 1835 4 0 Control Register Description VideoStream Decoder 0x0F TDEC DEFAULT 0x00 The TDEC register controls the temporal decimation of the input video stream 7 6 5 4 3 2 1 0 DECFLD FLDALN DRATE 5 0 DECFLD Defines whether decimation is by fields or frames 0 Decimate frames DEFAULT 1 Decimate fields FLDALN Aligns start of decimation with even or odd field 0 Start on odd field DEFAULT 1 Start on even field DRATE 5 0 Number of fields or frames dropped out of 50 625 50 or 60 525 60 This value should not exceed 60 for 60 Hz systems or 50 for 50 Hz systems DEFAULT is 0 0x10 BRIGHT DEFAULT 0x00 The BRIGHT register is an 8 bit register which controls the brightness offset applied to the video Values from 0x00 to OxFF are allowed The two s complement value programmed into this register is added to the decoded luminance portion of the video signal Brightness is applied after contrast 0x11 CONTRAST DEFAULT 0x39 The CONTRAST register holds the 8 bit contrast value The decoded luminance portion of the video is multiplied by the contrast value Values from 0x00 to OxFF are allowed 0x12 SAT U DEFAULT 0x7F The SAT_U register is an 8 bit gain applied to the decoded U vector of the chrominance Values from 0x00 to OxFF are allowed 0x13 SAT V DEFAULT 0x5A The SAT V register is an 8 bit gain applied to
79. ertical Filtering BS and Scaling UBESET 20 VRESET ge e ACTIVE gU S tU NE 2 VACTIVE z 9 FIELD d ue amp 8 JTAG Digital Video m g CBFLAG Output Formatting 9 o lt g 8 Y Ne e x z o P gt 2 D835DSA Rockwell Bt835 1 0 Functional Description VideoStream III Decoder 1 1 Functional Overview 1 1 1 Bt835 Video Capture Processor for TV VCR Analog Input The Bt835 Video Capture Processor is a fully integrated single chip decoding and scaling solution for analog NTSC PAL SECAM input signals from TV tuners VCRs cameras and other sources of composite or Y C video It is the third generation front end input solution for low cost PC video graphics systems The Bt835 delivers complete integration and high performance video synchronization Y C separation and filtered scaling It has all the mixed signal and DSP circuitry required to convert an analog composite waveform into a scaled digital video stream supporting a variety of video formats resolutions and frame rates The Bt835 builds on the previous Bt829B VideoStream II decoder by adding the following features as detailed in Table 1 1 Table 1 1 VideoStream Features Options Feature Options Bt829B Bt835 Composite Video Decoding S Video Decoding SECAM Video Hardware Closed Caption Decoding lt lt
80. eters 105 Table 5 10 100 PQFP Package Mechanical 0 106 Rockwell D835DSA ix List of Tables Bt835 VideoStream III Decoder X D835DSA Rockwell 1 0 Functional Description 1 1 Functional Overview Rockwell s VideoStream decoder is a high quality single chip solution for processing all analog NTSC PAL SECAM video standards into 4 2 2 YCrCb video The Bt835 offers the highest price performance of any video decoder with its unique 3 line adaptive comb filter digital video input port flexible digital video output port single crystal operation and low power consumption A detailed block diagram of the decoder is shown in Figure 1 1 Rockwell D835DSA 1 1 0 Functional Description Bt835 1 1 Functional Overview Figure 1 1 Bt835 Detailed Block Diagram VideoStream III Decoder GPIO 7 0 Input Interface Y C Separation and Chroma Demodulation Adjustments Sync Detect Oversampling Low Pass Filter Separation GPIO Port Chroma Demod Contrast Saturation and Brightness Adjust Digital Video Input Formatting 1 Clock Interface 2 MUXO MUX1 MUX2 MUX3 L RST SDA _ 2 5 SCL gt CLKx1 gt CLKx2 DIG V gt CCVALID DIG_H x QCLK 22 Horizontal and gg V
81. ges dad ER rn Ro BEL NE E ER FERE RE 54 Table 2 4 ITU R 656 Specification on Range of Active Video 55 Table 2 5 Reference Byte XY 7 0 and its Individual Bit 56 Table 2 6 VIP SAV and EAV Codes Under Full 58 Table 2 7 81835 Address Matrix ERR tu EE RES 62 Table 2 8 Example Data Transactions cie ocio case bed od doy deret da e 63 Table 2 9 Device Identification Register 66 Table 4 1 REGISTER EAE Lus 97 Table 5 1 Recommended Operating 5 99 Table 5 2 Absolute Maximum 5 100 Table 5 3 DC Characteristics 3 3 V digital 100 Table 5 4 DC Characteristics 5 V only operation 101 Table 5 5 Clock Timing Parameters 102 Table 5 6 Power Supply Current Parameters 3 V 5 V 104 Table 5 7 Output Enable Timing 5 104 Table 5 8 JTAG Timing 105 Table 5 9 Decoder Performance Param
82. he video signal is relevant Therefore the composite signal goes through the decimation and Y C separation blocks of the Bt835 before any CC EDS decoding takes place See Figure 1 24 for a representation of this procedure Figure 1 24 CC EDS Data Processing Path EE Composite Decimation _ Interpolation YCrCb sgh uic a CC EDS CC EDS CC Status 2 Register EN CC Data 2 Register The Bt835 can be programmed to decode CC EDS data via the corresponding bits in the CC_STATUS register The CC and EDS are independent and the video decoder may capture one or both in a given frame The CC EDS signal is displayed in Figure 1 25 In CC EDS decode mode the CC EDS data capture commences once the following occurs 1 Bt835 has detected that line 21 of the field is being displayed 2 clock run in signal is present 3 The correct start code 001 is recognized by Bt835 Each of the two bytes of data transmitted to the video decoder per field contains a 7 bit ASCII code and a parity bit The convention for CC EDS data is odd parity Rockwell D835DSA 37 1 0 Functional Description Bt835 1 9 Closed Captioning and Extended Data Services Decoding VideoStream Decoder Figure 1 25 CC EDS Incoming Signal HSync Start Bits 1 52 53 1 Character Two b1 02 b3 b4 b5 b6 P1 b0 b1 b2 b3 b4 b5 b6 P2 Color Burst
83. hroma or luma If the video being digitized has a non standard sync height to video height ratio the digital code used for AGC can be changed by enabling the CRUSH bit in the ADC register 0 1 WC DN Ox1E registers appropriately 2 1 9 Crystal Inputs and Clock Generation The Bt835 has two pins for crystal or oscillator connection XTOI XTOO A typical crystal is specified as follows 14 318 MHz Fundamental e Parallel resonant 30 pF load capacitance 50ppm Series resistance 80 or less The following crystals are recommended for use with the Bt835 1 Standard Crystal Corp Phone 626 443 2121 Fax 626 443 9049 Standard Part AAK14M318180KLE20A 2 MMD Phone 714 753 5888 Fax 714 753 5889 Standard Part 18 1 14 31818 MHz Low Profile Part 18 1 14 31818 MHz 3 General Electric Devices G E D Phone 760 591 4170 Fax 760 591 4164 Standard Part PKHCA9 U14 31818 020 005 050R Low Profile Part PKHC49 US 14 31818 020 005 050R Rockwell D835DSA 43 2 0 Electrical Interfaces Bt835 2 1 Input Interface VideoStream III Decoder 4 Monitor Products Co Inc Phone 619 433 4510 Fax 619 434 0255 Standard Part MM49N1C3A 14 31818 MHz Low Profile Part SMS49N1C3A 14 31818 MHz 5 Fox Electronics Phone 941 693 0099 Fax 941 693 1554 Standard Part 49 014 318180 1 Low Profile Part 49S 014 318180 1 6 Hooray Electronics Co H E C Phone
84. ical scaling value Rockwell D835DSA 23 1 0 Functional Description Bt835 1 6 Video Scaling Cropping and Temporal Decimation VideoStream Decoder When vertical scaling below CIF resolution it may be useful to use a single field as opposed to using both fields Using a single field ensures that no inter field motion artifacts occur on the scaled output When performing single field scaling the vertical scaling ratio is twice as large as when scaling with both fields For example CIF scaling from one field does not require any vertical scaling but when scaling from both fields the scaling ratio is 50 The non interlaced bit should be reset when scaling from a single field NVINT 0 in the VSCALE_CTL register Table 1 5 lists scaling ratios for various video formats and the register values required 1 6 6 Image Cropping Cropping enables the user to output any subsection of the video image The ACTIVE flag can be programmed to start and stop at any position on the video frame as shown in Figure 1 15 The start of the active area in the vertical direction is referenced to VRESET beginning of a new field In the horizontal direction it is referenced to HRESET beginning of a new line The dimensions of the active video region are defined by HDELAY HACTIVE VDELAY and VACTIVE The vertical and horizontal delay values determine the position of the cropped image within a frame while the horizontal and vertical active
85. input signal 1 the analog video signal has a stable horizontal time base This is equivalent to 1 820 8 bit VBI data samples for NTSC and 2 270 8 bit VBI data samples for PAL SECAM for each line of analog video input These values can deviate from the nominal depending on the actual line length of the analog video signal VBI frame output mode is enabled via the FRAME bit in the CONTROL 1 register The output byte ordering can be controlled by the VBIFMT bit as described for VBI line output mode If both VBI line output and VBI frame output modes are enabled at the same time the VBI frame output mode takes precedence 36 D835DSA Rockwell 1835 1 0 Functional Description VideoStream III Decoder 1 9 Closed Captioning and Extended Data Services Decoding 1 9 Closed Captioning and Extended Data Services Decoding For systems capable of capturing Closed Captioning CC and Extended Data Services EDS and which adhere to the 608 standard two bytes of information are presented to the video decoder on line 21 odd field for CC An additional two bytes are presented on line 284 even field for EDS The data presented to the video decoder is an analog signal on the composite video input The signal contains information which identifies it as the CC EDS data It is followed by a control code and two bytes of digital information transmitted by the analog signal For purposes of CC EDS only the luma component of t
86. interval between consecutive Bt835 HRESET signals Specifically it starts at a point one CLKx1 interval after the trailing edge of the first HRESET and ends with the leading edge of the following HRESET This interval is coincident with the HACTIVE signal as indicated in Figure 1 20 Figure 1 20 VBI Line Output Mode Timing V HACTIVE VD 15 0 Data DVALID is always at a logical value of one during VBI Also QCLK is operating continuously at CLKx1 or CLKx2 rate during VBI Valid VBI data is available one CLKx1 or QCLK interval after the trailing edge of HRESET When the Bt835 is configured in VBI line output mode it generates invalid data outside the VBI horizontal active period In standard YCrCb output mode the horizontal active period starts at a time point that 1s delayed from the leading edge of HRESET as defined by the value programmed in the HDELAY register 32 D835DSA Rockwell 1835 1 0 Functional Description VideoStream III Decoder 1 8 Bt835 VBI Data Output Interface The VBI data sample stream which is output during the VBI horizontal active period represents an 8 Fsc sampled version of the analog video signal starting in the vicinity of the sub carrier burst and ending after the leading edge of the horizontal synchronization pulse This is illustrated in Figure 1 21 Figure 1 21 VBI Sample Region Extent of Analog Signal Captured in VBI S
87. ion 1 of 3 VideoStream Decoder Code Event Description Inserted Headers and Type raster Reference Code TASKS om FIELD ID Active Video or VBI mode 9 000 EAV Previous pixel was last pixel FF 00 00 1 VACTIVE 1 FIELD signal transitions of any active line but NOT FIELD 1 VBISEL 0 with trailing edge of the last line D NVRESET 1 NVRESET 1101 1010 Next pixel is first pixel of any FF 00 00 HACTIVE 0 VACTIVE 1 NVRESET is an active active acquired line but FIELD 1 VBISEL 0 LOW signal NOT the last line C 7 t 1100 0111 EAV Previous pixel was the last FF 00 00 0 VACTIVE 1 EAV code marks the pixel of the last active line FIELD 1 VBISEL 0 beginning of a digital F 1 1 LASTV 1 video line 1111 0001 SAV Next pixel is first pixel of FF 00 00 1 VACTIVE 0 SAV arrives after EAV first inactive line FIELD 1 VBISEL 0 following HACTIVE NVRESET 1 LASTV 1 _ signal 1110 1100 EAV Previous pixel was last pixel FF 00 00 HACTIVE 0 VACTIVE 0 F bit toggles with leading of the line immediately FIELD 1 VBISEL 0 edge of NVRESET before NVRESET goes low B 6 1 LASTF 1 1011 0110 SAV Next pixel is first pixel of line FF 00 00 1 VACTIVE 0 F bit toggles in vertical
88. ion Diagram and Parts List for 5 Mode 45V VDD LVTTL ad VDDO VPP C2 ANALOG AREA C1 Ground VSSO PGND VSS Location Description Vendor Part Number C1 20 0 1 ceramic capacitor Erie RPE112Z5U104M50V C3 c4 10 uF tantalum capacitor Mallory CSR13G106KM Notes 1 A 0 1 uF capacitor should be connected between each group of power pins and ground as close to the device as possible ceramic chip capacitors are preferred 2 The 10 uF capacitors should be connected between the analog supply and the analog ground as well as the digital supply and the digital ground These should be connected as close to the Bt835 as possible 3 Vendor numbers are listed only as a guide Substitution of devices with similar characteristics will not affect the per formance of the Bt835 Rockwell D835DSA 69 3 0 Board Layout Considerations Bt835 3 3 Supply Decoupling VideoStream III Decoder Figure 3 4 Typical Power and Ground Connection Diagram and Parts List for 3 3 1 0 Mode 3 3 V e VDDO VDD VPP 1 _ C3 C2 ANALOG mE Cil Ground VSSO VSS LVTTL PGND Location Description Vendor Part Number C1 C2 1 0 1 uF ceramic capacitor Erie RPE112Z5U104M50V C3 4 2 10 uF tantalum capacitor Mallory CSR13G106KM Notes 1 0 1 uF capacitor sho
89. l code insertion 0 No Bytestream control codes DEFAULT 1 ByteStream control codes inserted RANGE Luma output range control 0 Normal 16 253 DEFAULT 1 Range 0 255 VERTEN Adds vertical detection to VPRES algorithm 0 vertical detection Use vertical detection in VPRES DEFAULT 86 D835DSA Rockwell Bt835 4 0 Control Register Description VideoStream III Decoder 0X18 CONTROL_3 DEFAULT 0 00 7 NOUTEN OES 1 0 LEN HSFMT ACTFMT VLDFMT CLKGT NOUTEN OES 1 0 LEN HSFMT ACTFMT VLDFMT CLKGT Output enable 0 outputs 1 Three state outputs selected by OES 1 0 DEFAULT Output enable select 00 Tristate timing and data only 01 Tristate data only 10 Tristate all DEFAULT 11 Tristate clocks and data only Output bus width 0 8 bit output on VD 15 8 1 16 bit output on VD 15 0 DEFAULT NHRESET format O0 NHRESET is 64 CLKXI cycles DEFAULT 1 NHRESET is 1 CLKX1 cycle ACTIVE format 0 is composite active DEFAULT 1 is horizontal active VALID format 0 VALID indicates nonscaled pixels DEFAULT 1 VALID is logical AND of nominal VALID and ACTIVE where ACTIVE is controlled by QCLK is inverted CLKX1 or CLKX2 QCLK gating O0 CLKx1 or CLKx2 is inverted and gated with VALID and ACTIVE to create QCLK DEFAULT 1 CLKx1 CLKx2 is inverted and gated with VALID to crea
90. l frequency 8 Fsc whereas CLKx1 operates at half the synthesized crystal frequency 4 Fsc Either crystals or CMOS oscillators may be used for the clock source Digital Video Input The Bt835 will accept digital video data as 8 bit 26 30 MHz 4 2 2 YCrCb samples on the VD 7 0 pins The digital video clock DIG CLK can be configured either as an input or output for slave or master mode timing Timing and synchronization control is provided by the DIG H and DIG V pins These pins are not required if the video source has CCIR656 timing with embedded SAV EAV timing codes When accepting digital video the Bt835 can control contrast saturation and brightness There is no provision for hue adjustment 1 1 7 Output Interface The Bt835 supports a Synchronous Pixel Interface SPI mode The SPI supports a YCrCb 4 2 2 data stream over an 8 or 16 bit wide path When the pixel output port is configured to operate 8 bits wide 8 bits of chrominance data are output on the first clock cycle followed by 8 bits of luminance data on the next clock cycle for each pixel Two clocks are required to output one pixel in this mode and so a 2x clock is used to output the data The Bt835 outputs all horizontal and vertical blanking pixels in addition to the active pixels synchronous with CLKX1 16 bit mode or CLKX2 8 bit mode It is possible to insert control codes into the pixel stream using chrominance and luminance values that are outside the allowable ch
91. lution of the luminance signal and fine details in the picture are lost The chrominance signal is derived by bandpass filtering the composite video signal to extract the frequency band centered at 3 58 MHz which contains the color information The Bt829 employs a chrominance comb filter to remove any residual luminance Y signal that overlaps the chrominance C signal in this frequency range Other video decoders employ a line comb filter These line comb filters operate by delaying the previous composite video horizontal scan line and comparing it to the current horizontal scan line Adding the two lines together cancels the C signal and provides the Y signal Subtracting the current line from the delayed line provides the C signal This process creates two filters which have a frequency response that look like teeth in a comb This type of filter is usually known as a 1 H line comb filter since it uses a 1 horizontal scan line delay to process the signals More complex filters can be built using 2 horizontal scan line delays and are called 2 H line comb filters While these filters will show improvement with a multiburst test pattern compared to a notch filter and demonstrate a horizontal flat frequency response the multiburst pattern does not show that 50 of the vertical resolution is lost due to the averaging of two lines These filters still suffer the hanging dot problem noticeable on test patterns such as the SMPTE color bar test pattern
92. m PAL I 625 50 4 43 MHz Great Britain others PAL M 525 60 3 58 MHz Brazil PAL N 625 50 4 43 Paraguay Uruguay PAL N 625 50 3 58 MHz Argentina combination SECAM 625 50 4 406 MHz Eastern Europe France 4 250 MHz Middle East PAL 60 2 525 60 4 43 MHz China NTSC 4 43 525 60 4 43 MHz Transcoding Application 1 NTSC Japan has 0 IRE setup 2 Typically used in Chinese Video CD players The video decoder must be appropriately programmed for each of the composite video input formats Table 1 4 lists the register values that need to be programmed for each input format Rockwell D835DSA 13 vi vsasesd Table 1 4 Register Values for Video Input Formats 2 PAL N NTSC Register Bit NTSC Japan Combination PAL 60 SECAM 4 43 INPUT FMT 3 0 0010 0111 1000 1001 0011 0x01 Cropping 7 0inall5 Settodesired Setto NTSC M desired SettoNTSC M Set PAL B Set to PAL B Set to PAL B Set to PAL B Set HDELAY registers cropping square pixel cropping square pixel 0 G H D G H square 0 G H D G H NTSC M VDELAY values in values values in values square pixel pixels values square pixel square pixel square VACTIVE registers registers values values values pixel CROP values HSCALE 15 0 0x02AA 0x02AA 0x033C 0 02 0x033C 0 00 8 0x02AA 0x033C 0x02AA 0x0A 0x09 ADELAY 7 0 0x68 0x68 Ox7F 0x68 0 7 Ox7F 0x68 Ox7F 0x68 0x1A B
93. nput High Voltage TTL 2 0 Vppo 0 5 V Input Low Voltage TTL ViL 0 8 V Input High Voltage XTI 2 3 Vppo 0 5 V Input Low Voltage ViL GND 0 5 1 0 V Input High Current Vie Vpp 10 Input Low Current Viy GND li 10 Input Capacitance f 1 MHz Viy 2 4 V Cin Input High Voltage NUMXTAL I2CCS 2 5 E V Digital Outputs E Output High Voltage 400 uA 2 4 Vppo V Output Low Voltage Io 3 2 mA VoL 0 4 V Three State Current loz 10 Output Capacitance Co 5 Analog Pin Input Capacitance Ca 5 100 D835DSA Rockwell Bt835 VideoStream III Decoder 5 0 Parametric Information 5 1 DC Electrical Parameters Table 5 4 DC Characteristics 5 V only operation Parameter Symbol Min Typ Max Units Digital Inputs Input High Voltage TTL Vin 2 0 Vpp 0 5 V Input Low Voltage TTL ViL 0 8 V Input High Voltage XTI 3 5 Vpp 0 5 V Input Low Voltage ViL GND 0 5 1 5 V Input High Current Vin Vpp 10 Input Low Current Viy GND li 10 uA Input Capacitance f 1 MHz Viy 2 4 V Cin 5 pF Digital Outputs Output High Voltage 400 uA Vou 2 4 Vpp V Output Low Voltage Io 3 2 mA VoL 0 4 V Three State Current loz 10 Output Capacitance Co 5 An
94. ny other power pin by more than 0 5 V In some cases devices with mixed signal interfaces such as the Bt835 can appear more sensitive to latch up In reality this is not the case However mixed signal devices tend to interact with peripheral devices such as video monitors or cameras that are referenced to different ground potentials or apply voltages to the device prior to the time that its power system is stable This interaction sometimes creates conditions amenable to the onset of latch up To maintain a robust design with the Bt835 the following precautions should be taken e Apply power to the device before or at the same time as the interface circuitry Do not apply voltages below GND 0 5 V or higher than 0 5 V to any pin on the device Do not use negative supply op amps or any other negative voltage interface circuitry All logic inputs should be held low until power to the device has settled to the specified tolerance Connect all VDDO VPP and VDD pins together through a low impedance plane Connect all VSSO VSS and PGND pins together through a low impedance plane 3 9 Sample Schematics An example of a Bt835 typical circuit schematic is illustrated in Figure 3 6 Rockwell D835DSA 73 835 VideoStream III Decoder 3 0 PC Board Layout Considerations 3 9 Sample Schematics Figure 3 6 Bt835 typical Circuit Schematic 1 of 5 70 T Pug 866180102
95. o ways First recognizing that YCrCb to RGB color space conversion is a standard feature of multimedia controllers for acceleration of digital video playback the Bt835 avoids redundant functionality and allows the downstream controller to perform this task Second the Bt835 can minimize the number of interface pins required by a downstream multimedia controller to keep package costs to a minimum This is accomplished by using industry standards interfaces such as the VESA Video Interface Port VIP or the Rockwell ByteSteam interface Controller systems designed to take advantage of these features allow video capture capability to be added to the base system in a modular fashion using only a single Integrated Circuit IC The Bt829 video decoder and many other video decoders employ a luminance notch filter a chrominance bandpass filter and a chrominance comb filter This means that the luminance signal is derived by filtering out the color information chrominance from a composite video signal with a notch filter This works because the NTSC color information is in a frequency band centered at about 3 58 MHz which extends about 1 3 MHz 1 from 2 3 to 4 9 MHz The Y filter is thus designed to reject frequencies in that range Although this effectively filters most of the chrominance signal out of the luminance signal it also removes the higher frequency luminance signal components This loss of bandwidth reduces the horizontal reso
96. ontrolled by the VIPEN bit 1 1 9 Closed Caption Decoding 1 1 10 122 Interface The Bt835 provides a Closed Captioning CC and Extended Data Services EDS decoder Data presented to the video decoder on the CC and EDS lines is decoded and made available to the system through the DATA and CCSTATUS registers The Bt835 registers are accessed via a two wire interface The Bt835 operates as a slave device Serial clock and data lines SCL and SDA transfer data from the bus master at a maximum rate of 100 kbps Chip select and reset signals are also available to select one of two possible Bt835 devices in the same system and to set the registers to their default values 1 1 11 3 3 V 5 V Operation The Bt835 can interface to either 5 V or 3 3 V signal level graphics system controllers When in 5 V mode all power pins should be tied to 5 V levels LVTTL must also be tied to 5 V When in 3 3 V mode the digital inputs outputs are not 5 V tolerant they can only interface to 3 3 V signal levels When in 3 3 V mode all VDD VPP and VDDO pins must be tied to 3 3 V all VAA pins must be tied to 5 V for ADC biasing LVTTL must be tied to ground Rockwell D835DSA 7 1 0 Functional Description Bt835 1 2 Descriptions VideoStream III Decoder 1 2 Pin Descriptions Figure 1 2 details the Bt835 pinout Table 1 2 provides pin numbers names input and output functions and descriptions Figure 1 2 Bt835 Pinout
97. ous Pixel Interface SPI SPI supports 8 bit and 16 bit YCrCb 4 2 2 data streams Bt835 outputs all pixel and control data synchronous with CLKx1 16 bit mode or CLKx2 8 bit mode Events such as HRESET and VRESET can be encoded as control codes in the data stream to enable a reduced pin interface ByteStream The VESA VIP interface mode is similar in concept to ByteStream but uses ITU R 656 header codes for video synchronization Mode selections are controlled by the CONTROL 2 0x17 register Figure 2 5 shows a diagram summarizing the different operating modes Each mode will be covered individually in detail On power up the Bt835 automatically initializes to SPI mode 1 at 16 bits wide Figure 2 5 Output Mode Summary Parallel Control 8 bit SPI Mode 1 16 bit Coded Control 8 bit SPI Mode 2 16 bit Coded Control SPI Mode 3 SPI 8 bit 48 D835DSA Rockwell Bt835 2 0 Electrical Interfaces VideoStream III Decoder 2 2 Output Interface 2 2 2 YCrCb Pixel Stream Format SPI Mode 8 and 16 bit Formats When the output is configured for an 8 bit pixel interface the data is output on pins VD 15 8 with eight bits of chrominance data preceding eight bits of luminance data for each pixel New pixel data is output on the pixel port after each rising edge of CLKx2 When the output is configured for the 16 bit pixel interface the luminance data is output on VD 15 8 and the ch
98. pin is held at a logical value of one during the VBI horizontal active period DVALID is held high during both the VBI horizontal active and horizontal inactive periods 1 it is held high during the whole VBI scan line These relationships are illustrated Figure 1 22 Rockwell D835DSA 33 1 0 Functional Description Bt835 1 8 Bt835 VBI Data Output Interface VideoStream III Decoder Figure 1 22 Location of VBI Data Odd Field VRESET HRESET 227 Pj 227 DVALID 5 VD 15 0 VBI Data VBI Data VBI Data 227 Invalid YCrCb Data VBI Active Region Even Field VRESET Cy i HRESET HACTIVE VACTIVE A DVALID jj VD 15 0 VBI Data VBI Data VBI Data ec c Invalid ee YCrCb Data VBI Active Region 34 D835DSA Rockwell Bt835 1 0 Functional Description VideoStream III Decoder 1 8 Bt835 VBI Data Output Interface The Bt835 can provide VBI data in all the pixel port output configurations i e 16 bit SPI 8 bit SPI ByteStream and VIP modes A video signal must be present on the Bt835 analog input as defined by the status of the VPRES bit in the STATUS register This enables the Bt835 to generate VBI data If the status of the VPRES bit reflects no analog input the B
99. r Cakes ain ee CM aaa las 65 2 4 1 Need for Functional 65 2 4 2 JTAG Approach to 65 2 4 3 Optional Device ID 66 2 4 4 Verification with the Tap 66 PC Board Layout 67 Sele Ground Planes qne pp De 67 9 2 PoWwerPlanes uoce RED e UP COD UM ota e UP Oe eU el fes odas 68 3 3 Supply Decoupling IH 68 3 4 Volt Regulator 71 3 5 0 71 3 6 Digital Signal 72 3 7 Analog Signal 72 9 8 2222 ee aly hana Rege Heb pl ga 72 3 9 Sample Schematics 2 2 2 5222222 73 Control Register 79 Parametric Information
100. re divider 0 Divide XTAL by 1 DEFAULT 1 XTAL by 2 PLL C PLL VCO post divider 0 Use 6 for post divider DEFAULT 1 Use 4 for post divider 1 5 0 PLL Iinput Range 6 63 00 sleeps PLL 0x2B DVLCNT DEFAULT 0x00 Digital video line count This register allows the user to program the number of lines in a digital video source If a zero is programmed the decoder defaults to the standard number of lines for the selected format Values of 0 to 1023 inclusive may be programmed into the DVLCNT register 94 D835DSA Rockwell Bt835 4 0 Control Register Description VideoStream III Decoder 0 2 DEFAULT 0x00 6 5 4 3 2 1 0 DISIF INVCBF DISADAPT NARROWADAPT FORCE2H FORCEREMOD NCHROMAEN NRMDEN DISIF INVCBF DISADAPT NARROWADAPT FORCE2H FORCEREMOD NCHROM AEN NRMDEN Disable Interpolation O Enable DEFAULT Disable IFX Invert sense of CBFLAG 0 Normal DEFAULT 1 Invert CBFLAG Disable adaption algorithm O0 Enable Adaption DEFAULT Disable Adaption Narrow adaption algorithm 0 Normal DEFAULT Narrow Forces selection of 2H comb filtered chroma data 2H comb enabled with NCHROMAEN O0 Adaptive 2H comb DEFAULT 1 2 comb forced Forces remodulation of excess chroma O0 Adaptive remodulation DEFAULT Forced remodulation Chroma 2H comb enable 0 2 ch
101. reset 0 Normal mode DEFAULT Reset TG ram address Digital video clock output select 00 CLKx1 DEFAULT 01 XTAL 10 PLL 11 PLL inverted Decoder input clock select 00 X TAL DEFAULT 01 PLL 10 DIG CLK 11 DIG CLK inverted 0x25 PLL F 28MHz DEFAULT 0x0000 Fractional PLL bits This register is selected automatically for 28 63636 MHz operation or digital video input mode Defaults to 0x0000 Rockwell D835DSA 93 4 0 Control Register Description Bt835 VideoStream Decoder 0x27 PLL XCI 28 MHz DEFAULT 0x0C Integer PLL bits This register is selected automatically for 28 63636 MHz operation or digital video input mode Defaults to 0 0 7 6 5 4 3 2 1 0 PLL_X PLL_C PLL_I 5 0 PLL_X PLL Reference XTAL pre divider 0 Divide XTAL by 1 DEFAULT 1 XTAL by 2 PLL C PLL VCO post divider 0 Use 6 for post divider DEFAULT 1 Use 4 for post divider 5 0 PLL Iinput Range 6 63 00 sleeps PLL 0x28 PLL F 35MHz DEFAULT OxDCF9 Fractional PLL bits This register is selected automatically for 35 468950 MHz operation or digital video input mode Defaults to OXDCF9 0 2 PLL 35 MHz DEFAULT 0 0 Integer PLL bits This register is selected automatically for 35 468950 MHz operation or digital video input mode Defaults to OxOE 7 6 5 4 3 2 1 0 PLL_X PLL_C PLL_I 5 0 PLL_X PLL Reference XTAL p
102. ription Bt835 VideoStream III Decoder 0X23 VSIF DEFAULT 0x00 The VSIF register controls various aspects of the digital video input port 7 6 5 1 0 Reserved BCF Reserved SVREF 1 0 VSFMT 2 0 RESERVED BCF RESERVED SVREF 1 0 VSFMT 2 0 Reserved for future use Set to 0 Allows the chroma BPF to be bypassed Reserved for future use 0 Do not bypass chroma BPF DEFAULT 1 chroma BPF Sync video reference 00 HS VS aligned with Cb DEFAULT 01 HS VS aligned with YO 10 HS VS aligned with Cr 11 HS VS aligned with Y1 Video signal format 000 Analog DEFAULT 001 CCIR 656 010 ByteStream 011 Reserved 100 External HSYNC VSYNC 101 HSYNC FIELD 110 Reserved 111 92 D835DSA Rockwell Bt835 4 0 Control Register Description VideoStream III Decoder 0 24 DEFAULT 0x00 This register controls access to the timing generator RAM and all timing generator clocks 7 6 5 4 3 2 1 0 Reserved CKDIR TGEN TGARST TGCKO 1 0 TGCKI 1 0 CKDIR TGEN TGARST TGCKO 1 0 TGCKI 1 0 Digital video clock direction 0 DIGCLK is output DEFAULT Always active at power up NOT tri stated at power up 1 DIGCLK is input Timing generator video mode enable O0 Read Write mode DEFAULT Timing generator mode Timing generator address
103. roma and luma ranges These control codes can be used to flag video events such as ACTIVE HRESET and VRESET Decoding these video events downstream enables the video controller to eliminate pins required for the corresponding video control signals The Bt835 supports the VESA VIP interface and the Rockwell ByteStream interface for embedding control codes into the digital video pixel stream 6 D835DSA Rockwell Bt835 1 0 Functional Description VideoStream III Decoder 1 1 Functional Overview 1 1 8 VBI Data Pass through The Bt835 provides VBI data passthrough capability The VBI region ancillary data is captured by the video decoder and is made available to the system for subsequent software processing The Bt835 may operate in a VBI line output mode in which the VBI data is only made available during select lines This mode of operation is intended to enable capture of VBI lines containing ancillary data as well as processing normal YCrCb video image data In addition the Bt835 supports a VBI frame output mode in which every line in the video signal is treated as if it were a vertical interval line and no image data is output This mode of operation is designed for use in still frame capture processing applications In VIP mode the Bt835 passes VBI data raw samples During selected VBI lines the VIP task bit T is set The protection bits P 3 0 are not used and are forced to 0 Ancillary data is not supported This mode is c
104. roma comb enabled DEFAULT 1 2 chroma comb disabled Remodulation enable 0 Luma remodulation enable DEFAULT Luma remodulation disabled Rockwell D835DSA 95 4 0 Control Register Description Bt835 VideoStream Decoder 0xFE IDCODE Reflects device ID and part revision Read only ID 3 0 REV 3 0 ID 3 0 Device ID 1010 Bt835 REV 3 0 Device revision 0000 Rev A 0001 0011 Rev D OxFF SW RESET A write of any data to this address will reset all internal registers to the default state 96 D835DSA Rockwell vsdsesd 16 4 1 Register Summary Table 4 1 Register Map ADDR Register Read Label Write 7 6 5 4 3 2 1 0 0 00 STATUS VPRES HLOCK FIELD NUML PLL CCVLD_CC CC EDS COF NSPLAY NLVTTL FIELD NUML PLL CCVLD LOF COF 0X01 INPUT MUXS 1 0 FMT 3 0 VSCALE_CTL COMB 1 0 NVINT FIELD VFILT 2 0 TDEC DECFLD FLDALN DRATE 5 0 0X15 CONTROL 0 LNOTCH SVID LDEC HFILT 1 0 PEAKEN PSEL 1 0 0X16 CONTROL 1 VBIEN FRAME VBITFMT CAGC CKILL SC SPD HACT 0X17 CONTROL 2 YCORE 1 0 CCORE 1 0 VIPEN BSTRM RANGE VERTEN 0X18 CONTROL 3 NOUTEN OES 1 0 LEN HSFMT ACTFMT VLDFMT CLKGT 0X19 VPOLE VALID VACTIVE CBFALG FIELD ACTIVE HRESET VRESET 0X1A DELAY AGC 7 0 0X1B BG_DELAY BG 7 0 0X1C ADC
105. rominance data is output on VD 7 0 In 16 bit mode the data is output with respect to CLKx1 See Table 2 1 for a summary of output interface configurations The YCrCb 4 2 2 pixel stream follows the CCIR recommendation as illustrated in Figure 2 6 Table 2 1 Pixel Pin Map 16 bit Pixel Interface Pin Name VD15 VD14 VD13 VD12 VD11 VD10 VD9 VD8 VD7 VD6 VD5 VD4 VD3 VD2 VD1 VDO Data Bit Y7 Y6 Y5 Y4 Y3 Y2 Y1 YO CrCb CrCb CrCb CrCb CrCb CrCb CrCb CrCb 7 6 5 4 3 2 1 0 8 bit Pixel Interface Pin Name VD15 VD14 VD13 VD12 VD11 VD10 VD9 VD8 VD7 VD6 VD5 VD4 VD8 VD2 VD1 VDO Y DataBit Y7 Y6 5 Y4 Y3 Y2 Y1 YO C Data Bit CrCb CrCb CrCb CrCb CrCb CrCb CrCb CrCb 7 6 5 4 3 2 1 0 Figure 2 6 YCrCb 4 2 2 Pixel Stream Format SPI Mode 8 and 16 Bits CLKx2 CLKx1 8 Bit Pixel Interface VD 15 8 VD 15 8 VD 7 0 CbO Cb2 2 Rockwell D835DSA 49 2 0 Electrical Interfaces Bt835 2 2 Output Interface VideoStream Decoder 2 2 3 Synchronous Pixel Interface SPI Mode 1 Upon power on reset the Bt835 initializes to SPI output mode 1 In this mode Bt835 outputs all horizontal and vertical blanking interval pixels in addition to the active pixels synchronous with CLKx1 16 bit mode or CLKx2 8 bit mode Figure 2 7 illustrates Bt835 SPI 1 The basic timing relationships
106. s 30 59 are then output followed by another frame of inactive video TDEC 0x9E Decimation is performed by fields Thirty fields are output per 60 fields of video assuming NTSC decoding This value outputs every other field or every odd field of video starting with field one in frame one TDEC 20x01 Decimation is performed by frames One frame is skipped per 50 frames of video assuming PAL SECAM decoding TDEC 20x00 Decimation is not performed Full frame rate video is output by the Bt835 When changing programming in the temporal decimation register 0 00 should be loaded first and then the decimation value This ensures that the decimation counter is reset to zero If zero is not first loaded the decimation may start on any field or frame in the sequence of 60 or 50 for PAL SECAM On power up this preload is not necessary because the counter is internally reset When decimating fields the FLDALN bit in the TDEC register can be programmed to choose whether the decimation starts with an odd field or an even field If the FLDALN bit is set to logical 0 the first field that is dropped during the decimation process will be an odd field Conversely setting the FLDALN bit to logical 1 causes the even field to be dropped first in the decimation process 28 D835DSA Rockwell 1835 1 0 Functional Description VideoStream III Decoder 1 7 Video Adjustments 1 7 Video Adjustments The Bt835 provides programmable hue contrast s
107. s all Bt835 ground pins voltage reference circuitry power supply bypass circuitry for the Bt835 analog input traces any input amplifiers and all digital signal traces leading to the Bt835 The Bt835 has digital grounds GND and analog grounds AGND The layout for the ground plane should be set up so the two planes are at the same electrical potential but they should be isolated from each other in the areas surrounding the chip The return path for the current should occur through the digital plane See Figure 3 1 for an example of ground plane layout Figure 3 1 Example Ground Plane Layout 44 Ground Return i e ISA Bus Connection 1 Bt835 p 8 5 Digital Analog Ground Ground Rockwell D835DSA 67 3 0 Board Layout Considerations Bt835 3 2 Power Planes VideoStream Decoder 3 2 Power Planes The power plane area should encompass all Bt835 power pins the voltage reference circuitry the power supply bypass circuitry the analog input traces any input amplifiers and all the digital signal traces leading to the Bt835 The Bt835 has digital power VDD and analog power VAA The layout for the power plane should be set up so the two planes are at the same electrical potential but they should be isolated from each other in the areas surrounding the chip Also the return path for the current should occur through the digital plane This is the
108. same layout as shown for the ground plane Figure 3 1 When using a regulator circuitry must be included to ensure proper power sequencing The circuitry shown in Figure 3 2 illustrates this circuitry layout Figure 3 2 Optional Regulator Circuitry for 5 V Systems System Power VAA VDD System Power 12 V 5 V 5 V ME NT Diodes Must Handle Ground the Current Requirements of the Bt835 and the Peripheral Circuitry Suggested Part Numbers Regulator Texas Instruments 78 MO5M 68 D835DSA Rockwell Bt835 3 0 PC Board Layout Considerations VideoStream Decoder 3 3 Supply Decoupling 3 3 Supply Decoupling The bypass capacitors should be installed with the shortest leads possible consistent with reliable operation to reduce the lead inductance These capacitors should also be placed as close as possible to the device Each group of VAA and VDD pins should have 0 1 uF ceramic bypass capacitor to ground located as close as possible to the device Additionally 10 UF capacitors should be connected between the analog power and ground planes as well as between the digital power and ground planes These capacitors are at the same electrical potential but provide additional decoupling by being physically close to the Bt835 power and ground planes See Figures 3 3 and 3 4 for additional information about power supply decoupling Figure 3 3 Typical Power and Ground Connect
109. t Sseippy og AL YOLOANNOO ALISOdNOD 2020 20 deo s AD 2 so e A 4 980209029 5080 aoa 5 HOLIOJNNOO eiu mee NOO 18041 veo gt 195 5 ano 2 150 80 295 15040 2 5080 69 5 HOLO3NNOO LYOd _owaL 5080 WHO 92 seo zouZors 5080 mro no ony z lino do 5 A 5 sv 31 vas vano te sano 150 T arth tono LZ 5080 E FI Far T zn 4 09 95 ed X oon YANNLAL ane er SLAdNI O3GIA Oel YANNL Rockwell D835DSA 78 4 0 Control Register Description 0x00 STATUS The STATUS register reports status from various decoder functions When bit 0 of the test register at location is a 0 its default setting the STATUS register reports back the following conditions 7 6 5 4 3 2 1 0 VPRES HLOCK FIELD NUML PLL CCVLD LOF COF VPRES Video Present 0 video detected 1 detected HLOCK Horizontal Lock 0 Not locked 1 Locked FIELD Field Identifier 0 field Even field NUML Number of lines per frame 0 525 1 625 PLL PLL Lock O PLL not
110. t835 generates YCrCb data to create a flat blue field image The order in which VBI data is presented on the output pins is programmable Setting the VBIFMT bit in the CONTROL 1 register to a logical 0 places the nth data sample on VD 15 8 and the nth 1 sample on VD 7 0 Setting VBIFMT to a logical 1 reverses the above Similarly in ByteStream and in 8 bit output modes setting VBIFMT 0 generates a VBI sample stream with an ordering sequence of n l n 0 3 2 n 5 0 4 etc Setting VBIFMT 1 for ByteStream 8 bit output generates a sequence of n 1 n 2 n 3 etc as shown in Figure 1 23 Figure 1 23 VBI Sample Ordering 16 bit SPI Mode VBIFMT 0 VD 15 8 n n 2 VD 7 0 X n 1 X n 3 8 bit SPI Mode VBIFMT 1 VD 15 8 x n x n 1 x n 2 x 3 X To capture VBI data output by the Bt835 a video processor controller should be able to do the following Keep track of the line count to select a limited number of specific lines for processing of VBI data Handle data type transitioning on the fly from the vertical interval to the active video 1mage region For example during the vertical interval with VBI data passthrough enabled the processor controller must grab every byte pair while HACTIVE is high using the 4 Fsc clock or QCLK How ever when the data stream transitions into YCrCb 4 2 2 data mode with VACTIVE going high the video processor must interpret the DVALID sig nal or use QCLK for the
111. tal Video Input 43 2 18 Automatic Gain Controls xot SEMPER Rs 43 2 1 9 Crystal Inputs and Clock Generation n 43 2 1 10 2X Oversampling and Input Filtering lisse I 45 2 2 2 icici tig nai cede be RO C Deu GA 48 2 24 48 2 2 2 YCrCb Pixel Stream Format SPI Mode 8 and 16 bit Formats 49 2 2 3 Synchronous Pixel Interface SPI 1 50 2 24 Synchronous Pixel Interface SPI Mode 2 ByteStream 51 2 2 5 Synchronous Pixel Interface Mode 3 VIP 55 2 2 5 1 Bt835 VIP CODE T V H GENERATION 57 2 26 CCIR601 Compliance ix expe e rr REN TENA Aa E 60 2 3 TPC IHteHats E Da nione E Rat 61 2 31 Starting and Stopping ur ees eer UN Ev wee EXER REP RIP EE USER M 61 2 3 2 Addressing the Bt835 62 2 33 Reading Writing tease tae De boo ates 62 2 9 4 Software Reset 2 a wan RUE ut e eR Rn ERA 65 iv Rockwell Bt835 VideoStream III Decoder 3 0 4 0 5 0 2 4 UTAG Interface ot Ste h
112. te QCLK Rockwell D835DSA 87 4 0 Control Register Description Bt835 VideoStream IIT Decoder 0X19 DEFAULT 0x00 7 6 5 4 3 2 1 0 Reserved VALID VACTIVE CBFLAG FIELD ACTIVE HRESET VRESET RESERVED Reserved for future use Set to 0 VALID 0 VALID pin active high DEFAULT 1 VALID pin active low VACTIVE 0 VACTIVE pin active high DEFAULT 1 pin active low CBFLAG 0 pin active high DEFAULT 1 CBFLAG pin active low FIELD O0 FIELD pin active indicates EVEN field DEFAULT 1 FIELD pin active indicates ODD field ACTIVE 0 pin active high DEFAULT 1 pin active low HRESET 0 HRESET pin active high DEFAULT 1 HRESET pin active low VRESET O0 NVRESET pin active low DEFAULT 1 NVRESET pin active high 0X1A DELAY DEFAULT 0x68 AGC 7 0 AGC 7 0 AGC Delay value 0X1B BG DELAY DEFAULT 0x5D BG 7 0 BG 7 0 Burst Gate delay value 88 D835DSA Rockwell 835 4 0 Control Register Description VideoStream III Decoder 0X1C ADC DEFAULT 0x02 7 6 5 4 3 2 1 0 Reserved Reserved Reserved AGC_EN CLKSLP YSLP CSLP CRUSH RESERVED Reserved for future use Set to 0 AGC_EN AGC enable O0 Enable AGC DEFAULT 1 Disable AGC CLKSLP Sleeps system clock 0 Normal clock operation DEFAULT
113. th After digitization the samples are digitally low pass filtered and then decimated to CLKx1 The response of the digital low pass filter is shown in Figure 2 4 The digital low pass filter provides the digital bandwidth reduction to limit the video to 6 MHz Rockwell D835DSA 45 2 0 Electrical Interfaces Bt835 2 1 Input Interface VideoStream III Decoder Figure 2 3 Bt835 Typical External Circuitry Optional Anti aliasing Filter 83pH 1 04 MF eo Y Y e MUX 0 3 830pF 330 5 750 VDD pF Video Timing 0 1 uF VDD 100 750 CCVALID 0 1 uF cu Q 0 1 uF 47 pF ej L 14 318 CA 750 MHz 1 47 75 Termination a pian Lys Digital Ground 0 1 UF V Analog Ground AC Coupling Capacitor 46 D835DSA Rockwell 835 2 0 Electrical Interfaces VideoStream III Decoder Figure 2 4 Luma and Chroma 2x Oversampling Filter Luma amp Chro Amplitude in dB 20 log10 amp Amplitude in dB 20 log10 amp Frequency in MHz Luma amp Chror 2 1 Input Interface Frequency in MHz Rockwell D835DSA 47 2 0 Electrical Interfaces Bt835 2 2 Output Interface VideoStream III Decoder 2 2 Output Interface 2 2 1 Output Interfaces The Bt835 supports a Synchron
114. the HSCALE value uses the ratio of the scaled active region to the unscaled active region as shown below NTSC HSCALE 754 HACTIVE 1 4096 PAL SECAM HSCALE 922 HACTIVE 1 4096 where HACTIVE Desired number of pixels per line of video not in cluding sync or blanking 22 D835DSA Rockwell Bt835 1 0 Functional Description VideoStream III Decoder 1 6 Video Scaling Cropping and Temporal Decimation In this equation the HACTIVE value cannot be cropped it represents the total active region of the video line This equation produces roughly the same result as using the full line length ratio shown in the first example However due to truncation the HSCALE values determined using the active pixel ratio will be slightly different than those obtained using the total line length pixel ratio The values in Table 1 5 were calculated using the full line length ratio Table 1 5 Scaling Ratios for Popular Formats Using Frequency Values Total VSCALE Register Output HSCALE Scaling Ratio Format ED Resolution Register banking Active Pixels Values Use Both Single 2 Fields Field interval Full Resolution NTSC SQ Pixel 780 x 525 640 x 480 02 0000 1 00 14 NTSC CCIR601 858 x 525 720 x 480 00 8 0000 1 00 PAL CCIR601 864 x 625 720 x 576 0504 0000 1200 PAL SQ Pixel 944 x 625 768 x 576 033C 0000 1 00 CIF NTSC SQ Pixel 390 x 262 320 x 240 1555 1E00 1A00 2 1 NTSC CCI
115. these variations digital display systems require a fixed number of pixels per line The Bt835 employs the UltraLock technique to lock to the horizontal sync and the subcarrier of the incoming analog video signal and to generate the required number of pixels per line 1 3 2 Operation Principles of UltraLock UltraLock is based on sampling using a fixed frequency stable clock Because the video line length varies the number of samples generated using a fixed frequency sample clock also varies from line to line If the number of generated samples per line is always greater than the number of samples per line required by the particular video format the number of acquired samples can be reduced to fit the required number of pixels per line The Bt835 PLL generates a 8 Fsc 28 64 MHz for NTSC and 35 47 MHz for PAL clock from a crystal or oscillator input signal source The 8 Fsc clock signal or CLKx2 is divided down to CLKx1 internally 14 32 MHz for NTSC and 17 73 MHz for PAL Both CLKx2 and CLKx1 are made available to the system UltraLock operates at CLKx1 although the input waveform is sampled at CLKx2 then low pass filtered and decimated to a CLKx1 sample rate A 4 Fsc CLKx1 sample rate produces 910 pixels for NTSC and 1 135 pixels for PAL SECAM within a nominal line time interval 63 5 us for NTSC and 64 us for PAL SECAM Square pixel NTSC PAL SECAM formats should produce only 780 and 944 pixels per video line respectively This
116. timing control signal triggers the field bit to switch its polarity This polarity value is maintained until the next time LASTF transitions to HIGH LASTF is held HIGH for one line length The field bit changes only on EAV codes The vertical blanking interval bit V must change in an EAV code at the beginning of a digital line In the Bt835 the signals VACTIVE and LASTV determine the polarity of the V bit LASTV indicates the last active line of a field whether it is an even or odd field and is held HIGH for one line VACTIVE transitions to LOW in the middle of LASTV signal while it is held HIGH Then the V bit transitions to LOW while VACTIVE and LASTV are both held HIGH The Bt835 complies with the specification that V bit must change its polarity only in EAV codes The horizontal blanking ID H bit switches its polarity between zero and one in both SAV and EAV codes At the start of active video the HACTIVE signal is held HIGH and H bit is set LOW At the end of active video HACTIVE goes LOW and the H bit is set to HIGH In other words the EAV code contains an H bit equal to one and SAV code contains an H bit equal to zero Note that EAV marks the beginning of a digital video line Table 2 6 lists SAV and EAV codes in relation to specific events occurring during a digital video line Rockwell D835DSA 57 2 0 Electrical Interfaces Bt835 2 2 Output Interface Table 2 6 VIP SAV and EAV Codes Under Full Resolut
117. to 255 Brightness adjustment can be made over a range of 128 to 127 Rockwell D835DSA 29 1 0 Functional Description Bt835 1 8 Bt835 VBI Data Output Interface VideoStream Decoder 1 8 Bt835 Data Output Interface 1 8 1 Introduction A frame of video is composed of 525 lines for NSTC and 625 for PAL SECAM Figure 1 17 illustrates an NTSC video frame in which there are a number of distinct regions The video image or picture data is contained in the ODD and EVEN fields within lines 21 to 262 and lines 283 to 525 respectively Each field of video also contains a region for vertical synchronization lines 1 through 9 and 263 through 272 as well as a region which can contain non video ancillary data lines 10 through 20 and 273 through 282 We will refer to the regions which are between the vertical synchronization region and the video picture region as the vertical blanking interval or VBI portion of the video signal Figure 1 17 Regions of the Video Frame Lines 1 9 27 vertica Lines 10 20 Vertical Blanking Interval Region RU 5 Lines 21 262 Video Image Region 8 Vertical Lines 263 272 Synchronization Lines 273 282 Vertical Blanking Interval 2 Region Lines 283 525 Video Image Region S 1 8 2 Overview In the default configuration of the Bt835 the VBI region of the video signal is treated the same way as the video image region of the signal The Bt
118. transported in a manner similar to the active video data However VBI data is not multiplexed into Chroma and Luma but as a single stream of ADC samples When VBISEL and VBIEN are both held HIGH VBI data is selected and treated as raw ADC samples According to ITU R 656 and VESA VIP Interface Spec 1 1 the upper nibble X of the reference byte contains the three reference bits F V The bits T E V can only change in the EAV code which is indicated the beginning of a digital video line 56 D835DSA Rockwell Bt835 2 0 Electrical Interfaces VideoStream III Decoder 2 2 5 1 Bt835 VIP CODE T F V H GENERATION 2 2 Output Interface The task bit T changes when the VBIEN and VBISEL input signals are both HIGH and it depends on two other timing signals LASTNVBI and LASTNV LASTNVBI and LASTNV are held HIGH for one line near the vertical blanking interval When VBIEN VBISEL and LASTNVBI are all held HIGH the task bit is set to LOW LASTNVBI represents the last line containing non VBI data and it also flags the upcoming VBI data stream VRESET transitions to LOW in the middle of LASTNVBI When VBIEN VBISEL and LASTNV are all held HIGH the task bit is set to HIGH LASTNV indicates activation of VACTIVE and flags upcoming active video data VACTIVE transitions to HIGH in the middle of LASTNV The task bit changes only on EAV codes The field bit toggles to the opposite polarity at the leading edge of NVRESET The
119. ty to reduce anti aliasing artifacts It is generally desirable to limit the bandwidth of the luminance spectrum prior to performing horizontal scaling This is because the scaling of high frequency components may create image artifacts in the resized image The optional low pass filters shown in Figure 1 8 reduce the horizontal high frequency spectrum in the luminance signal Figures 1 9 and 1 10 show the combined results of the optional low pass filters and the luma notch and 2x oversampling filter Figure 1 8 Optional Horizontal Luma Low Pass Filter Responses T T T PAL SECAM a i Amplitude in dB 20 log10 ampl Amplitude in dB 20 log0 ampl i 1 Frequency MHz 18 D835DSA Rockwell Bt835 1 0 Functional Description VideoStream III Decoder 1 6 Video Scaling Cropping and Temporal Decimation Figure 1 9 Combined Luma Notch 2x Oversampling and Optional Low Pass Filter Response NTSC Amplitude in dB 20 log10 ampl do S5 S E A i e i eo e I o m Pass Band 0 4 SES mee Ns Sar N 2 MN oL RS 4 LOS x ICON QCIF a 5 ax o 3r N 4 x s o X e 4r B x i 5 4 E x Y 6 1 1 i 0 0 5 1 1 5 2 3 Frequency in MHz Figure 1 10 Combined Luma Notch
120. uired VIN Amplitude Range AC coupling required 0 5 1 00 2 00 V Ambient Operating Temperature Ta 0 70 C Rockwell D835DSA 99 5 0 Parametric Information Bt835 5 1 DC Electrical Parameters Table 5 2 Absolute Maximum Ratings VideoStream Decoder 0 5 V can induce destructive latch up operation at these or any other conditions above those listed in the operationa Exposure to absolute maximum rating conditions for extended periods may affect device reliability This device employs high impedance CMOS devices on all signal pins It must be handled as an ESD sensitive device Voltage on any signal pin that exceeds the power supply voltage by more than 0 5 V or drops below ground by more than Parameter Symbol Min Typ Max Units Vaa measured to AGND 7 00 V Vpp measured to DGND 7 00 V Voltage on any signal pin See the note below DGND 0 5 Vpp 0 5 V Analog Input Voltage AGND 0 5 Vaa 0 5 V Storage Temperature Ts 65 150 C Junction Temperature Ty 125 C Vapor Phase Soldering TvsoL 220 C 15 Seconds Note Stresses above those listed may cause permanent damage to the device This is a stress rating only and functional section of this specification is not implied Table 5 3 DC Characteristics 3 3 V digital I O operation Parameter Symbol Min Typ Max Units Digital Inputs E I
121. uld be connected between each group of power pins the ground as close to the device as possible ceramic chip capacitors are preferred 2 10 uF capacitors should be connected between the analog supply and the analog ground as well as the digital supply and the digital ground These should be connected as close to the Bt835 as possible 3 Vendor numbers are listed only as a guide Substitution of devices with similar characteristics will not affect the per formance of the Bt835 70 D835DSA Rockwell Bt835 3 0 PC Board Layout Considerations VideoStream Decoder 3 4 Volt Regulator Circuit 3 4 Volt Regulator Circuit Figure 3 5 demonstrates a regulator circuit which can be used to operate the digital portion of the Bt835 at 3 3 V For simplicity supply decoupling is not shown here please see Figure 3 4 The analog power supply must always remain at5 V All digital power including Vdd Vddo and Vpp must be run at either 3 3 V or 5 V The part may be damaged if all of the digital power is not run at the same supply voltage The LVTTL pin must be tied to ground for digital 3 3 V operation and tied to Vcc for digital 5 V operation Figure 3 5 Optional 3 3 V Regulator Vcc gt Vaa 3 3 Regulator 3 2 Vdd 33269 gt LVTTL 93 10K GND Rockwell D835DSA 71 3 0 PC Board Layout Considerations Bt835 3 5 Power Up Sequen
122. up 46 DIG_H Digital video horizontal reset input Can be tied high low if not used 47 DIG_V Digital video vertical reset input Can be tied high low if not used 49 1 0 DIG_CLK Digital video clock May be configured as either input or output Bidirectional Do not tie if not used 79 FRST Active HIGH FIFO reset Used for testing purposes only JTAG Tie high for normal use 82 TWREN FIFO test write input JTAG pin Tie low for normal use 83 TRST Active low JTAG reset Tie low for normal use 84 JTAG clock low for normal use 85 JTAG test mode select high for normal use Rockwell D835DSA 9 1 0 Functional Description Bt835 1 2 Pin Descriptions Table 1 2 81835 Pin Descriptions 2 of 2 VideoStream III Decoder Pin 0 Description 86 0 TDO JTAG test data out Do not connect this pin for normal use 87 TDI JTAG test data in Tie high for normal use 88 SCL 12 clock 89 SDA IC data Open drain 1 0 Must be externally pulled up typically with a 10 resistor 92 PWRDN Powers down the decoder when high 93 LVTTL When connected to ground configures the Bt835 to operate at 3 3 V When connected to VDD configures the Bt835 to operate at 5 V 95 Crystal in 96 XTO Crystal out 98 I CCS Used to select alternate 12 address High 0x8A low 0x88 99
123. used to input digital video In test mode these pins are used as the test bus input 29 22 1 0 GPIO 7 0 These pins are used to control or sample external devices These pins will power up three stated 32 0 CLKx2 ADC sample clock output 33 Active low output enable When pulled high this pin will three state the pins defined by the OES 1 0 register bits This pin works in conjunction with the NOUTEN register bit When either NOE or OUTEN is high the selected pins will be three stated 34 0 CLKx1 ADC sample clock divided by two 35 0 HRESET Active low Horizontal reset output 36 0 VRESET Active low Vertical reset output 37 ACTIVE Composite active video region Indicates non blanked region of decoded video May be configured to represent the horizontal active region of each line 38 0 Vertical active output Indicates the non blanked vertical region of the decoded video 39 0 VALID Valid pixel output This signal in conjunction with ACTIVE indicates which pixels will be used in the construction of the decoded video field frame May be internally and logically ANDED with the ACTIVE pin 42 0 QCLK Gated output clock In 16 bit mode this pin is created by inverting and gating the CLKX1 clock In 8 bit mode the CLKx2 clock is used 43 FIELD Even Field indicator 44 CBFLAG Cb pixel indicator 45 CCVALID Open drain output Indicates that the CC FIFO has CC data to be read If used must be externally pulled
124. ve device 2 3 1 Starting and Stopping The relationship between SCL and SDA is decoded to provide both a start and stop condition on the bus To initiate a transfer on the bus the master must transmit a start pulse to the slave device This is accomplished by taking the SDA line low while the SCL line is held high The master should only generate a start pulse at the beginning of the cycle or after the transfer of a data byte to or from the slave To terminate a transfer the master must take the SDA line high while the SCL line is held high The master can issue a stop pulse at any time during an PC cycle Since the PC bus will interpret any transition on the SDA line during the high phase of the SCL line as a start or stop pulse care must be taken to ensure that data is stable during the high phase of the clock This is illustrated in Figure 2 12 Figure 2 12 The Relationship between SCL and SDA SCL SDA Start Stop Rockwell D835DSA 61 2 0 Electrical Interfaces Bt835 2 3 1 C Interface VideoStream III Decoder 2 3 2 Addressing the Bt835 An slave address consists of two parts a 7 bit base address and a single bit R W command The R W bit is appended to the base address to form the transmitted address as shown in Figure 2 13 and Table 2 7 Figure 2 13 12 Slave Address Configuration A6 A5 A4 2 Ao Rw Base Address R W Bit Table 2
125. ving an acknowledge from the Bt835 the master transmits the desired address 0xOA After receiving an acknowledgment the master then starts a read cycle with an slave address of 0x89 or Ox8B The Bt835 acknowledges transfer and then transfers the contents of register Issuing a stop command after the write cycle is not needed The Bt835 detects the repeated start command and starts a new cycle This process is illustrated in Table 2 8 and Figure 2 14 For detailed information on the bus refer to The Reference Guide reprinted by Rockwell Table 2 8 Example Data Transactions 1 of 2 Master Data Bt835 Comment Flow Write to Bt835 2 Start gt Master sends Bt835 chip address i e 0x88 or 0 8 Bt835 generates ACK on successful receipt of chip address subaddress gt Master sends subaddress to 81835 Bt835 generates ACK on successful receipt of subaddress Data 0 gt Master sends first data byte to 81835 Bt835 generates ACK on successful receipt of 1st data byte Data n gt Master sends nth data byte to Bt835 Bt835 generates ACK on successful receipt of nth data byte 12 Stop Master generates STOP to end transfer Rockwell D835DSA 63 2 0 Electrical Interfaces Bt835 2 3 17C Interface VideoStream III Decoder Table 2 8 Example Data Transactions 2 of 2 Master 275 Bt835 Comment Read from Bt835
126. well Semiconductor Systems Inc All rights reserved Print date October 1998 Rockwell Semiconductor Systems Inc reserves the right to make changes to its products or specifications to improve performance reliability or manufacturability Information furnished is believed to be accurate and reliable However no responsibility is assumed for its use nor for any infringement of patents or other rights of third parties which may result from its use No license is granted by its implication or otherwise under any patent or intellectual property rights of Rockwell Semiconductor Systems Inc Rockwell Semiconductor Systems Inc products are not designed or intended for use in life support appliances devices or systems where malfunction of a Rockwell Semiconductor Systems Inc product can reasonably be expected to result in personal injury or death Rockwell Semiconductor Systems Inc customers using or selling Rockwell Semiconductor Systems Inc products for use in such applications do so at their own risk and agree to fully indemnify Rockwell Semiconductor Systems Inc for any damages resulting from such improper use or sale Bt is a registered trademark of Rockwell Semiconductor Systems Inc Product names or services listed in this publication are for identification purposes only and may be trademarks or registered trademarks of their respective companies All other marks mentioned herein are the property of their respective holders Specifi
127. xtract any programmable number of pixels from the original video stream as long as the sum of the nominal pixel line length 910 for NTSC and 1 135 for PAL SECAM and the worst case line length variation in the active region is greater than or equal to the required number of output pixels per line 1 PNom Pyar 2 P Desired where Nominal number of pixels per line at 4 Fsc sample rate 910 for NTSC 1 135 for PAL SECAM Pyar Variation of pixel count from nominal at 4 Fsc can be a positive or negative number Desired number of output pixels per line NOTE S For stable inputs UltraLock guarantees the time between the falling edges of HRESET to within only one pixel UltraLock guarantees the number of active pixels in a line as long as the above relationship holds 12 D835DSA Rockwell Bt835 1 0 Functional Description VideoStream III Decoder 1 4 Composite Video Input Formats 1 4 Composite Video Input Formats The Bt835 supports all composite video input formats Table 1 3 shows the different video formats and shows some of the countries in which each format is used Table 1 3 Video Input Formats Supported by the Bt835 Format Lines Fields Country NTSC M 525 60 3 58 MHz U S many others NTSC Japan 7 525 60 3 58 MHz Japan PAL B 625 50 4 43 MHz Many PAL D 625 50 4 43 MHz China PAL G 625 50 4 43 MHz Many PAL H 625 50 4 43 MHz Belgiu
128. ze the video signals 2 1 5 A D Clamping An internally generated clamp control signal is used to clamp the inputs of the A D converter for DC restoration of the video signals Clamping for composite and S video analog inputs occurs within the horizontal sync tip 2 1 6 Power Up Operation Upon power up the Bt835 device defaults to NTSC M format with all digital outputs three stated 42 D835DSA Rockwell Bt835 2 0 Electrical Interfaces VideoStream III Decoder 2 1 Input Interface 2 1 7 Digital Video Input Option The digital video port on the Bt835 is controlled by the VSIF and TG_CTL registers 0x23 and 0x24 The VSIF register controls the format of the video input to the decoder The default is analog video from the 835 A D s To use the digital input change the 2 0 bits in the VSIF register Several input format options are available including CCIR 656 Bytestream and external sync methods of accepting the digital video The system clock is controlled in the TG CTL register Typically in this application the user inputs the digital clock corresponding to the digital video In cases where the digital input clock frequency is different from the crystal input to the PLL e g CCIR 656 the TG RAM must also be reprogrammed The option also exists to output a clock on the DIG pin 2 1 8 Automatic Gain Controls The Bt835 automatically applies gain to any video signals with suppressed amplitude c

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