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User Manual - ESA Microelectronics Section

1. rarrrannnanrnaneranenanenanevanenanenanenanenanenanennnennnennnennennnnennnnnnnennnsnnesnnesnnesene 15 Table 6 1 Output Reset Values 21 Table G 2 CrG BITCLK e alte ER Table 6 3 Transmit configuration and signals OVEervieW rrrrnnrrranrrnanernnnernnrrrnnrrranennnnennarrnnsennnsennnsennn 35 Table 6 4 Configuration signals overview rrrararareraneraneraneranenanennnevnernrnnernnnenneennenneenneennuenneennusnnnsenn 41 Table UK ON signals je 43 Table 7 2 Transmit data interface signale 48 Table 7 3 Receive data interface signals 0 n0annnnnnnnannnnnnnnnnnnnnnnnnnnenrenrsnrerrenrsrrsnrsnrnnrrnrrnrrnrrnrrnrrnrrni 48 Table 7 4 Timecode interface signals cccsscccsecccesecceeeceucecaucecaeeeseecsucecsueeseeesueessueessueesseesseeeseas 50 Table 7 5 Status NE EE 51 Table 7 6 Error Recovery SIQnals AE 52 Tabi 8 1 Seral internace SINAN Las eek 56 Table 10 1 Status timing clock analysis 00n0nnnannannnannnannennnnnnnnnnnnsnnnnnrsnrrsnrnnrrnnrrnrrnnrrrrrnnrrnnrenrrnne 59 Table 10 2 Data and Clock Recovery Timing Parameters rrrrnnnnrnnnnennnnennnnnnnnrnranennnnennnnnnnnrnnnnennnnennn 61 Table 10 3 Extra Clock Recovery Timing Harameters 61 Table 10 4 Skew Tolerance Mavimums 64 Page 8 of 69 Ref UoD Link User EBI Vv Q EADS E SpaceWire CODEC IP 2 4 paceWire ASTRIUM DUNDEE Issue 27 March 2009 User Manual Date Page 9 69 Austrian Aerospace 1 SCOPE This document de
2. C Standard FIFO First Word Fall Through Supported Bum In FIFO Options Features The frequency relationship of WR_GLK and RD_GLK MUST be specified to generate the correct Read Write Clock Domains Memory Type 1 2 3 4 a Common Cock CLK Block RAM x Read Clock Frequency MHz fi Range 1 1000 C Gommon Clock CLK Distributed RAM x Write Glock Frequency MHz fi Range 1 1000 Common Clock Ki Shift Register j Data Port Parameters Gommon Gock CLK Bullt in FIFO x x less fp mange 123 286 Independent Ciocks AD GLK WA CLK Block RAM TK write Depth 16 Actual wite Depth 17 independent Cocks RD GLK WA_CLK Distributed RAM x Parad Width Bb J Independent Giocks RD_GLK WA_CLK Bultin FIFO Read Depth 16 Actual Read Depth 17 1 Non symmetric aspect ratios different read and write data widths 2 First Word Fall Theough 3 Uses Virtex 4 and Virtex 6 built in FIFO primitives 4 EGG support Implementation Options F Enable ECC I Use Embedded Registers In BRAM or FIFO when possible Read Latency From Rising Edge of Read Clock 0 Fifo Generator me Fifo Generator vas Optional Flags Initialization I Almost Full Flag F Reset Pin E Asynchronous Reset Synchronous Reset Full Flags Reset vane 1 T Almost Empty Flag Hands haking Options Write Port Handshaking Write Acknowledge Overtlow Write Error F Use Dout
3. WERSIT S A ASTRIUM DUNDEE GH Austrian Aerospace SpaceWire CODEC IP User Manual Ref Uod Link User Document Revision 2 4 Date 27 March 2009 SpaceWire Interface User doc Pam Ref UoD Link User d K 2 4 EADS SpaceWire CODEC IP ASTRIUM DUNDEE Issue 27 March 2009 User Manual Date Page 2 69 GH Austrian Aerospace Document Ref UoD Link User Issue No 2 4 Issue Date 27 March 2009 Author Chris McClements VHDL Code tag uodcodec cvsrel 2 3 Number of pages in document 69 Document History Date leave Description mr 6 Oct 2003 New UoD CODEC VHDL user manual 19 Apr 2004 DDR output multiplexer synthesis description updated 27 Oct 05 1 2 Use Latches configuration removed CFG SLOWRATE_SYSCLK description updated 2 July 2007 2 1 Fixed serial reset problem of txencode and transmit clock cmc generators 22 January 2 3 Update with CFG SLOWCLK_10MHZ reference signal cmc 2008 27 Mar 2009 Corrections after ESTEC review Page 2 of 69 gemm Ref UoD Link User Vv e ie EADS z SpaceWire CODEC IP 2 4 pe DUNDEE Issue 27 March 2009 User Manual l EN Austrian Aerospace Date Page 3 69 CONTENTS LEMEN NN 3 IN BAR el e LA 6 Ur VSEOFIMEES 44242424 8 1 SCEE 9 2 APPLICABLE DOCUMENTS ane 10 2 BERN eebe 11 Oe TERMS AENEAS 11 3 2 VHDL CODE TERMS AND DEFINITIONS iiccicscssesteiccscecsncessnethacenededueontdec couse anesecssthecsedonssuepiuncencoaes 11 3 3 DOCUMENT TE
4. Enable Rx Figure 1 Initialisation state machine 7 1 1 Link Start up Link start up is implemented as described in AD1 section 8 5 The CODEC attempts to make a connection with the other end of the link when in state Started The interface state machine moves to Started when in state Ready and LINK ENABLED is asserted The signal LINK ENABLED is defined below LINK ENABLED not LINK DISABLED and LINK START or AUTO START and GOT NULL When LINK_START is asserted and LINK_DISABLED is de asserted the CODEC will always try to establish a connection with the other end of the link If no connection is established i e no NULLs received after sending NULLs for 12 8 us the exchange of silence protocol is performed If a NULL is received then an FCT character is expected before moving to the Run state where data and timecodes can be transmitted Page 42 of 69 ee Ref UoD Link User Vv EADS E SpaceWire CODEC IP 2 4 paceWire ASTRIUM DUNDEE Issue 27 March 2009 User Manual Date Page 43 69 Austrian Aerospace When AUTO START is asserted and LINK START and LINK DISABLE are de asserted the CODEC will remain in state Ready until reception of a NULL 7 1 2 Link Disable Link Disable is implemented as described in AD1 section 8 5 LINK_DISABLE should be asserted to cause a safe link disconnection Error recovery is performed when LINK_DISABLE causes the state machine to move from Run to ErrorReset Link
5. Taverage Minpgdchk 100 E 6 100 E 9 40 E 09 1 140 E 09 70 E 09 14 286E 06 50 E 6 200 E 9 80 E 09 280 E 09 140 E 09 7 143E 06 25 E 6 400 E 9 160 E 09 1 560 E 09 280 E 09 3 571E 06 Minimum read clock with different minimum packet data sizes BitRate Tdata__ Teop MinNumData Tpacket Taverage MinRdClk 200 E 6 50 E 9 20 E 09 Of 20 E 09 20 E 09 50 E 06 200 E 6 50 E 9 20 E 09 6 320 E 09 46 E 09 21 875E 06 200 E 6 50 E 9 20 E 09 8420 E 09 47 E 09 21 429E 06 200 E 6 50 E 9 20 E 09 9 470 E 09 47 E 09 21 277E 06 Legend MinNumData 0 MinNumData 1 MinNumData 2 MinNumData 3 etc Tdata Time for one data byte to be received Teop Time for one EOP byte to be received Tpacket Time for one packet to be received Taverage Average time for one N Char to be received MinRdClk Minimum frequency of read clock to resynchronise n chars Figure 7 4 Minimum Receive buffer clock frequency From the table above the function for minimum read clock frequency is 1 MinNumDataxTaata Teop MinNumData l Min 1 Tdata vs 10 SCH aa Page 46 of 69 ee Ref UoD Link User Kps E i a SpaceWire CODEC IP ASTRIUM DUNDEE Issue 27 March 2009 User Manual Date Page 47 69 Austrian Aerospace x 4 1 Ten ee a S SH and MinNumData is the minimum number of data bytes in a packet The table and functions above shows the absolute minimum frequency for RXBUF CLK Depe
6. Transmit clock configuration SYS SLOWCLK VERSI Sv Ee Vv z SpaceWire CODEC IP DUNDEE User Manual SH Austrian Aerospace data rate is used or 5MHz when DDR outputs are used This configuration can be implemented when system clock frequency can be changed externally if required An external 10 5MHz reference clock is desired Figure 6 2 shows the clock configuration SYS SLOWCLK FSM SEL SLOW SYSCLK TXBITCLK Tx Encode SLOWCLK Glitch Free Clock Multiplexer XENR XENF D Ref Issue Date Figure 6 2 SYS SLOWCLK transmit clock configuration Page 24 of 69 UoD Link User 2 4 27 March 2009 Page 24 69 Only one system clock is used and no internal variable data rate generation is required The gemm Ref UoD Link User Vv EADS z SpaceWire CODEC IP 2 4 ASTRIUM DUNDEE Issue 27 March 2009 User Manual Date Page 25 69 H Austrian Aerospace 6 5 3 Transmit bit clock configuration SYS SLOWCLK DIV The transmit clock configuration SYS SLOWCLK DIV allows an independent 10 5MHz default transmit rate SLOWCLK and a generated variable transmit rate from SYSCLK This configuration generates a new transmit clock tree asynchronous from SYSCLK The SYS SLOWCLK DIV configuration can be used when e An internal variable data rate scheme is required and the transmit clock is SYSCLK e An external 10 5MHz reference clock is desired The configuration SYS_DIV is shown
7. by 2 when CFG DDROUT 1 TXBITCLK Internal Should be constrained to the same frequency as TXCLK txclkgen_1 XCLKTX Internal Should be constrained to the same frequency as TXBITCLK XCLKTX is the transmit clock multiplexed with the SLOWCLK input txclkgen 1 txdiv Internal Should be constrained to the same frequency as XICLKDIV TXBITCLK XICLKDIV is the transmit clock multiplexed with the divided clock RXBUF CLK Internal Present if CFG SYNCRDCLK 0 RXBUF_CLK should be constrained according to the guidelines provided in section 7 2 8 Receive buffer clock frequency Table 10 1 Status timing clock analysis Note Clocks are used according to the configuration signals see section 6 The baseline minimum number of clock nets required for the SpaceWire CODEC is SYSCLK and RXCLK for configurations SYS DEFAULT and SYS EN Page 59 of 69 ee Ref UoD Link User ops P i p SpaceWire CODEC IP ASTRIUM DUNDEE Issue 27 March 2009 User Manual Date Page 60 69 Austrian Aerospace 10 2 Receiver Clock Static Timing Analysis The effects of skew and jitter in the SpaceWire point to point link are discussed in the SpaceWire standard AD1 section 6 6 4 The specification T mara is the available timing margin for the input bit stream unit interval Ty The value Tyarcin IS defined as TMARGIN Tur TsKew 2 x TyiTTEr TpoLk TpHorD Analysis of the timing parameters Tsxew Tyitter Ipcik and Tun Must be
8. 2 Receive On reception of a timecode the signal TICK_OUT is asserted and the timecode value is placed on the output TIME OUT 7 0 The TIME OUT value is registered in the RXCLK clock domain and is valid only on the rising edge SYSCLK when TICK OUT is asserted The TIME OUT interface is shown in Figure 7 6 1 2 3 4 5 6 TICK OUT TIME OUT AM D A Figure 7 6 TICK OUT interface 7 3 3 Timecode Interface Signals Timecode interface signals are listed in Type Description Sync To Clk Timestamp which is sent over the SpaceWire link when the Page 49 of 69 ee Ref UoD Link User Vv EADS E SpaceWire CODEC IP 2 4 paceWire ASTRIUM DUNDEE Issue 27 March 2009 User Manual Date Page 50 69 Austrian Aerospace control signal TICK_IN is asserted The timecode is sent immediately after the transmitter has completed sending the previous character TICK IN In Tick in strobe causes a timecode to be sent over the SYSCLK spacewire link The signal is synchronous TIME OUT 7 0 Out Received timecode output The timecode on TIME OUT is RXCLK valid when TICK_OUT is asserted TICK OUT Out Asserted when a timecode is received and the timecode SYSCLK on TIME OUT is valid The TICK_OUT signal is synchronous to the system clock Table 7 4 Timecode interface signals 7 4 Status Signals Status reporting is performed through the output signal STATUS 15 0 Run errors are reported through the RUNERR output
9. ASTRIUM DUNDEE Issue 27 March 2009 User Manual Date Page 48 69 Austrian Aerospace 7 2 10 Data Interface Signals Data interface signals are listed in Table 7 3 Description Sync To Clk TX n DATA P BE data which is read by the transmitter The most TXBITCLK significant bit is the data control flag which indicates if the character is an end of packet or data character TX FIFO READ Asserted when the transmitter reads one N char from the TXBITCLK transmitter FIFO TX FIFO EMPTY Transmitter FIFO empty flag indicates the empty status of TXBITCLK the transmitter When high the transmitter is empty Table 7 2 Transmit data interface signals Note TXBITCLK may be SYSCLK SLOWCLK or divided clock kg Description Sync To Clk a DATA bie data which is written from the receiver to the RXBUF CLK receiver FIFO The most significant bit is the character control flag which indicates when the character is an end of packet marker RXBUF WRVALID Asserted when data is received and ready on RXBUF CLK RXBUF DATA RXBUF WRADDR WRADDR Out Address to write RXBUF DATAto S to write RXBUF DATA to RXBUF RXBUF_CLK sin Out Empty KL JE for receive buffer When asserted then no data is in the buffer RXBUF READ In Read from receive buffer Asserted for one RXBUF_CLK RXBUF CLK period RXBUF RDVALID Out Asserted when RXBUF READ is asserted and the buffer is RXBUF_CLK not empty RXBUF RDADDR Out Address to read
10. Figure 10 12 Method Two DDR output encodin No changes need to be made to the UoD SpaceWire CODEC to use either of these methods Page 67 of 69 Ref UoD Link User VERSI Sv Ee Vv a G d EADS b4 SpaceWire CODEC IP 2 4 paceWire ASTRIUM DUNDEE Issue 27 March 2009 User Manual Date Page 68 69 H Austrian Aerospace 11 CONFORMITY The SpaceWire CODEC VHDL core is conformant with the SpaceWire standard AD 1 The SpaceWire CODEC verification has been performed in accordance with AD1 section 12 2 4 Page 68 of 69 gemm Ref UoD Link User Vv A EADS z SpaceWire CODEC IP 2 4 ASTRIUM DUNDEE Issue 27 March 2009 User Manual Date Page 69 69 H Austrian Aerospace 12 APPENDIX I CLOCK MULTIPLEXER The glitch free clock multiplexer used by the UoD SpaceWire CODEC is shown in Figure 12 1 CLKOUT Figure 12 1 Glitch Free clock multiplexer Two flip flop synchronisation of SELA is used to stop meta stable events occurring Therefore the inputs SELA CLKA and CLKB can be completely asynchronous The output clock CLKOUT is enabled by the falling edge of CLKA or CLKB only when the other clock has been disabled As no reset is used the flip flops require a few clock cycles to reach a steady state These cycles are consumed when the transmitter is not doing anything so glitches cannot occur The maximum number of cycles which can be consumed occurs when all flip flops come out of reset in a 1 sta
11. Figure 4 2 VHDL files Nierarchy ccccccccceseccseeceececeueeceueecaueeceecececsueeceuseseeecaeessueessueesusesseeeseeeseas 15 Figure 5 1 User Implementation with UoD Codec nannnnnnennnannennnannnnnnnrrnnnnnnnnnrrsnrnrrrnnrnnrrnnrrerrnnrennne 16 Figure 6 1 SYS DEFAULT transmit clock configuration rrranrnnnnernnnnrnnnnranrrnanennnnrnnnnrrnnrnrnrrnnnennnsennn 23 Figure 6 2 SYS SLOWCLK transmit clock configuration rarrnnnrernnnrrnnrrranrrnanernnnrrnnnrrnnrnrnnernnennnnennn 24 Figure 6 3 SYS SLOWGCLK DIV transmit clock configuration rrnrrnnnnrrrrnnnrrnnnnrnnnnnennnnrennnrrnnnnnrnnnnne 25 Figure 6 4 SYS DIV transmit clock configuration a nn0annannnannnnnnannnnnnennnnnnennnnrrnnnnnrrnnrnnnrnnrrenrnnrennne 26 Figure 6 5 SYS EN transmit clock configuration a0nnaannannnannennnennnnnnennnnnnnnrnnrnnnnnrrrnnrnnrrnnrrerrnnrennne 27 Figure 6 6 TX DEFAULT transmit clock configuration nannaannannnannnnnnennnnnnnnnnnnnnnnnrrrnnrnnnronrrenrnnrennne 28 Figure 6 7 TX SLOWGOCLK transmit clock Gonfguraton 29 Figure 6 8 TX SLOWGCLK DIV transmit clock contfguraton 30 Figure 6 9 TXCLK DIV transmit clock configuration rrranarnnnrnnnnevnnnnrnnnrnanrnnnnrnnnnennnnrnnnrrrnnennnrennnsennn 31 Figure 6 10 TXCLK EN transmit clock configuration rrranrrnanennnnernnnrrnnrrranernnnennnnrnnnnrrnnrnranennanennnsennn 32 Figure 6 11 Receive buffer data How 36 Figure 6 12 CFG SLOW CE SEL co
12. TXBITCLK Figure 8 2 Transmit DDR register transmit txddrreg vhd The file transmit txddrreg_noenable vhd can be used for configurations which do not use a clock enable to generate the variable data rate This includes configurations SYS DEFAULT SYS SLOWCLK SYS SLOWCLK DIV SYS DIV TXCLK DEFAULT TXCLK SLOWCLK TXCLK SLOWCLK DIV and TXCLK DIV It rebuilds the transmit clock into a multiplexer select signal for the output DDR multiplexer using clock enables if required to generate a variable data rate The DDR output is shown in Figure 8 3 DSJOUT DO DSJOUT F TXBITCLK TXBITCLK TXBITCLK At Mux Dous Ty ma y m Dou F mm y DOUT my ma y m ID Figure 8 3 txddrreg noenable vhd double data rate generation logic and waveform Page 54 of 69 gr Ref UoD Link User EADS z SpaceWire CODEC IP 2 4 ASTRIUM DUNDEE Issue 27 March 2009 User Manual Date Page 55 69 Austrian Aerospace The advantages of using the generic DDR output buffer method include e Support for SYS EN and TXCLK EN transmit bit clock configurations where two clock enable signals XENR and XENF are used to control the data rate by enabling rising and falling clock edges independently typically not supported in vendor specific DDR output buffers e Generic implementation which is suitable for all architectures Disadvantages of using the generic DDR output buffer method include e Delays between DOUT SOUT
13. This allows EEPs to be written to the receive buffer when an error occurs 7 2 5 Data Received On reception of a data character the data is placed on the output signal RXBUF_DATA 8 0 and RXBUF WRVALID is asserted for one cycle see figures Figure 5 1 and Figure 7 3 RXBUF WRVALID should be connected to the write enable port of the receive buffer If a credit error occurs N char s received when not expected requested the link is disconnected and the error bytes are written to the receive buffer if not full If the receive buffer is full the N chars are discarded The output RXBUF WRADDR should be connected to the write address port of the memory storage used for the receive buffer 7 2 6 Host read When the user reads an N char from the receive buffer the signal RXBUF READ should be asserted for one RXBUF_CLK cycle The UoD CODEC will assert the signal RXBUF_RDVALID if the read is Page 44 of 69 ee Ref UoD Link User Vv d EADS E SpaceWire CODEC IP 2 4 paceWire ASTRIUM DUNDEE Issue 27 March 2009 User Manual Date Page 45 69 H Austrian Aerospace valid i e the FIFO is not empty The output RXBUF RDVALID can be connected to the enable port of the receive buffer storage output register if required The output RXBUF RDADDR should be connected to the read address port of the storage method used for the receive buffer 7 2 1 Flags The receive port implements an empty flag RXBUF EMPTY and a programmable flag R
14. and DOUT F SOUT F and the select signals for the DDR output multiplexer must be delay matched to ensure no glitches occur on the outputs see section 10 3 e Output skew may be introduced between DOUT and SOUT as the output is not directly at the output pad DOUT DOUT_F SOUT_F L DOUT Vendor specific DDR output buffer UoD SpaceWire CODEC DOUTSOUT_CLR TXBITCLK Figure 8 4 Vendor specific DOUT and SOUT DDR encode The advantages of using the vendor specific DDR output buffer method include e Output select multiplexer is optimised to ensure no glitches occur on the outputs e The DDR output is directly at the output buffer therefore no output skew is introduced into DOUT and SOUT The disadvantages of using the vendor specific DDR output buffer method include e Transmit clock configurations SYS EN and TXCLK EN may not be supported as independent clock enables for rising and falling edge data are required 8 1 3 Data Strobe Timing To achieve the high data rates required in SpaceWire then output skew between DOUT SOUT and DIN SIN must be kept as low as possible Page 55 of 69 ee Ref UoD Link User Vv EADS E SpaceWire CODEC IP 2 4 paceWire ASTRIUM DUNDEE Issue 27 March 2009 User Manual Date Page 56 69 Austrian Aerospace 8 1 4 Serial Interface signals The following table gives an overview of the serial interface signals Signal Type Description Syn
15. characters and end of packet markers from the transmitter FIFO N char characters are transmitted when there is data in the FIFO and the transmitter has credit to send one more N char The transmitter sends an FCT character for each block of space for eight N chars in the receive FIFO As the host system reads out data from the receive FIFO so the transmitter sends more FCTs to indicate that the receiver has room to receive eight more N chars The transmitter sends NULLs when there is no other information to send 5 2 7 Transmitter Clock Generator The transmitter clock enable generator is responsible for generating the variable transmitter bit rate and default data signalling rate depending on the configuration 5 2 8 Transmitter Credit Counter The transmitter credit counter holds a count register which indicates the number of SpaceWire N char characters which can be sent along the link 5 2 9 Transmitter Error Recovery The transmitter error recovery module recovers the transmitter FIFO after an error occurs In a network situation the first byte of a packet is interpreted as the packet address therefore the error recovery block reads from the transmitter FIFO until the next end of packet marker was read from the Page 18 of 69 gr Ref UoD Link User A EADS z SpaceWire CODEC IP 2 4 ASTRIUM DUNDEE Issue 27 March 2009 User Manual Date Page 19 69 Austrian Aerospace FIFO The transmitter is allowed to start up when error rec
16. in Figure 6 4 FSM SEL_SLOW TXRATE Tx TXBITCLK Encode n Glitch Free Clock Multiplexer SLOWCLK Glitch Free Clock Multiplexer XENR XENF Figure 6 3 SYS SLOWGCLK DIV transmit clock configuration The variable data rate is implemented using a programmable divider which enables a toggle flip flop When the SpaceWire CODEC is performing link start up FSM SEL SLOW the input SLOWCLK is selected When link start up has been performed and a link connection has been established the input TXRATE determines the data rate When TXRATE is equal to zero maximum rate then XIMAX is asserted and SYSCLK is selected by the glitch free clock multiplexer When TXRATE is not equal to zero the clock generator output XI CLK DIV is selected by the multiplexer Synchronisation is automatically performed by the SpaceWire CODEC as TXBITCLK is asynchronous to SYSCLK in this configuration Page 25 of 69 gemm Ref UoD Link User Vv A EADS z SpaceWire CODEC IP 2 4 ASTRIUM DUNDEE Issue 27 March 2009 User Manual Date Page 26 69 H Austrian Aerospace 6 5 4 Transmit bit clock configuration SYS DIV The transmit clock configuration SYS DIV allows a variable rate and default 10MHz transmitter bit clock to be generated from SYSCLK This configuration generates a new transmit clock tree asynchronous from SYSCLK The SYS DIV configuration can be used when e A variable data rate scheme is required but the use
17. performed to determine the maximum bit rate which the receiver can accept The maximum input data rate shall be set so that Tmarain gt 0 In terms of maximum skew and jitter input to the system the function below must be observed TskEw 2 x Tyrrrer lt Tur Trxskew Tpork THotp The receive clock data and recovery flip flops are analysed to determine the setup time of the data recovery flip flops and the skew tolerance of the design The clock recovery circuit is shown in Figure 10 1 DIN i DR Tock oF Teo pp Figure 10 1 Receive Clock Data Recover Four checks are performed on the design 1 A clock edge generated by a change in DIN captures the correct DIN value A clock edge generated by strobe captures the correct DIN value Skew does not cause the minimum clock pulse specification of the flip flop to be violated gt Data recovery from flip flop DF to DF_1 is possible The following sub sections define how the terms above can be measured using static timing analysis 10 2 1 Timing Parameters The timings are described in Table 10 2 Page 60 of 69 ee Ref UoD Link User Vv EADS E SpaceWire CODEC IP 2 4 paceWire ASTRIUM DUNDEE Issue 27 March 2009 User Manual Date Page 61 69 H Austrian Aerospace Maximum of Tock pr and Tperk DF Maximum of Tpr and Tpr Table 10 2 Data and Clock Recovery Timing Parameters Other parameters which affect the receive clock recovery is
18. start up signals are listed in Table 7 1 Type Description Sync To Clk Enable the CODEC to establish a connection SYSCLK LINK DISABLE In Disable or stop the CODEC When LINK DISABLE is asserted SYSCLK it causes the initialisation state machine to move from Run to ErrorReset then error recovery is performed AUTOSTART Auto start the CODEC When set the CODEC will wait in state SYSCLK Ready until the first NULL character is received Table 7 1 Link control signals 7 2 Data Interface The data interface consists of a transmit interface and a receive interface As shown in Figure 5 1 a transmitter FIFO and receiver buffer should be placed between the UoD SpaceWire CODEC and the host data bus controller or equivalent The transmit FIFO should be reset when the CODEC is reset 7 2 1 Transmit The transmit FIFO should be clocked by the UoD SpaceWire CODEC signal TXBITCLK This ensures that the maximum data rate can be achieved by allowing the transmitter to read data characters synchronously from the transmit FIFO using the transmit clock In cases where TXBITCLK can be variable the transmit FIFO should be capable of independent read and write clock operation 7 2 2 Transmit FIFO signals operation When the host FIFO has data then it should de assert the CODEC input signal TX_FIFO EMPTY and place the data on the input TX_FIFO DATA 8 0 The transmitter asserts TX_FIFO READ for one cycle to read the data into the transmitter for
19. transmission over the link The interface between the transmitter FIFO and the transmitter bus controller or equivalent is dependent on the application The expected transmitter FIFO interface waveforms are shown in Figure 7 2 Page 43 of 69 Pa Ref UoD Link User Vv EADS E SpaceWire CODEC IP 2 4 paceWire ASTRIUM DUNDEE Issue 27 March 2009 User Manual Date Page 44 69 H Austrian Aerospace 1 2 3 4 5 6 7 8 9 10 11 12 verek ff V VU VLSI VL VL UUU UUV AE TXFIFOEMPTY TT ML PIM III TE TI TX FIFO DATA YYXXXYXXXXXKK Dara WMM Co X DATA 000000000000000 TX FIFOREAD NN PN Figure 7 2 Transmit Timing Specification Note If a read from the FIFO causes the FIFO to become empty on the next clock cycle the empty signal must be asserted before the next clock cycle e g cycle 4 above Note After an EOP transmit 4 serial bits the next data character can be read immediately for transmission 7 2 3 Receive The receive port of the UoD SpaceWire CODEC implements the read write and FCT pointers for the receive buffer The user simply has to choose the size of the read buffer and implement the memory storage for received N chars 7 2 4 Receive buffer signals operation All receive buffer output signals as synchronous to RXBUF_CLK Note The receiver buffer pointers are implemented synchronously to RXBUF_CLK as N chars are resynchronised to the RXBUF_CLK domain before being written to the receiver buffer
20. 5 4 Transmit bit clock configuration SYS DIN 26 6 5 5 Transmit bit clock configuration SYS EN 27 6 5 6 Transmit bit clock configuration TXCLK DEFEAULT 28 6 5 7 Transmit bit clock configuration TXCLK SLOWCLK rrrnnnrnanrrnarennnrennnnrnnnrrranennanennnnennn 29 6 5 8 Transmit bit clock configuration TXCLK SLOWGCLK DIN 30 6 5 9 Transmit bit clock configuration TXCLK DIN 31 6 5 10 Transmit bit clock configuration TXCLK EN 32 6 5 11 Variable data rate and default 10Mbits sec data rate generation rrrrnrrnrnnnrnrnnnrnrnnnen 33 6 5 12 Double Data Rate outputs rrranrrnnnrrnanrrnnnernnnrnnnnvvnnrrnanrrnanrnnnnnnnnnnnnnrnnanennnnennnnnnnnsnnnnennnne 34 6 5 13 Transmit clock configuration and signals OVErVieW cccccccseccceeeeceeeeseeeeaeeeseeeeseueesaees 35 6 6 10 5 MHZ REFERENCE CLOCK SLOWCLK rrunnnnnnrnnnnnnrrrrnnnrrnrnnnrrennnnnnenrnnnnernnnnerenrnnsnennnnsnnen 36 6 RECEIVE BUFFER ClO eege eebe Een 36 obo PENG are 36 6 9 DISCARDING EMPTY PACKETS au bie 37 6 10 MAXIMUM OUTSTANDING CREDIN su dddedneee 37 6 11 TRANSMIT TIME CODE HANDLING n nnsennnnennnennneniesnrnnenrrsrrrnrrrnerrrenrrnnrrrenrrnnrrnnrrrenrrnnrrenrrnenrene 37 6 12 INTENAL RECEIVER DISCONNECT AND INIT FSM TIMEOUT COUNTERS annnnnnnennnennennnenennnennene 38 6 13 TINGO YOLE Ke 39 6 14 DISCONNECT TIMEOUT UNCERTAINTY Le 40 6 15 CONFIGURATION SIGNALS OVERVIEW c csccccsscecceececceececaseeceaseeceaeeeccuacesauaeseaseessaseeseeseeneua
21. Divider value to derive the TXCLK when CFG BITCLK 10Mbits s default rate when TXCLK_ SYSCLK when generated internally CFG BITCLK SYS Divider value to derive the TXCLK when CFG BITCLK variable transmit rate when it is TXCLK_ SYSCLK when generated internally CFG BITCLK SYS om Out Clock enable for rising edges TXBITCLK when CFG BITCLK SYS TXCLK EN Out Clock enable for falling edges TXBITCLK when CFG BITCLK SYS TXCLK_EN Table 6 3 Transmit configuration and signals overview Page 35 of 69 gemm Ref UoD Link User Vv A EADS z SpaceWire CODEC IP 2 4 ASTRIUM DUNDEE Issue 27 March 2009 User Manual Date Page 36 69 H Austrian Aerospace 6 6 10 5 MHz Reference Clock SLOWCLK The interface signal SLOWCLK can be used to input a 10 5 MHz reference clock for the UoD SpaceWire CODEC Depending on the transmit clock configuration SLOWCLK can provide the default 10Mbits s data signalling rate at start up and connection SLOWCLK is also used as the reference clock for receive disconnect detection and state machine timeout detection This is the most efficient implementation as no internal counter is required to generate a 10MHz reference clock enable signal although extra synchronisation is required between the system clock domain and the 10MHz clock domain When a double data rate configuration is used the bit rate is twice the SLOWCLK clock speed i e 5MHz clock and double data rate output giv
22. OWRATE TXCLK 5 then 10MbitRate TL 11Mbit s If CFG SLOWRATE TXCLK 6 then 10MbitRate PT 9 428Mbit s Note both values above are inside the 10Mbits s 10 defined in the SpaceWire standard Page 33 of 69 ee Ref UoD Link User Vv EADS E SpaceWire CODEC IP 2 4 paceWire ASTRIUM DUNDEE Issue 27 March 2009 User Manual Date Page 34 69 H Austrian Aerospace 6 5 12 Double Data Rate outputs The configuration input CFG DDROUT determines if the transmit encoder outputs will be encoded as double data rate DDR or single data rate Two bits per clock cycle are output for each bit clock period when CFG_DDROUT is equal to 1 The UoD SpaceWire CODEC does not implement an internal DDR output register but one is provided for reference in the file transmit txddrreg vhd This allows the user to implement a vendor specific DDR output register scheme e g Virtex2 DDR output buffers if appropriate The usage of DDR output buffers is described in section 8 1 2 Page 34 of 69 gemm Ref UoD Link User Vv aye EADS z SpaceWire CODEC IP 2 4 ASTRIUM DUNDEE Issue 27 March 2009 User Manual Date Page 35 69 Austrian Aerospace 6 5 13 Transmit clock configuration and signals overview signal constant Type Sync To Clk Independent transmit clock SLOWCLK In Independent 10 5 MHz reference n a clock CFG BITCLK 3 0 In Configuration selection for n a transmit clock CFG SLOWRATE TXCLK In
23. RMS AND DEFINITIONS veccsasciccsacdncdwcnasauedaesaantovenscdunsendnedauensacatselceedmntiandeasdeedoceseace 12 4 CONFIGURATION MANAGEMENT unnnnnnnnnnnnnnnannnnnennnnnnnnnnnnnnnnnnnnnnennnnnennnnnennnnnnnnnnnnnnnnennnnnennnnne 13 al BREMSENE 13 4 1 1 CODEC E EE e EEE EN E 14 41 2 VADE File AO PAG re 15 5 FUNCTIONAL OVERVIEW E 16 EVER E 16 db FN NN 16 5 2 1 Configuration Overview cccccscccsscccescecseeccseeceucecaueecaueecaeeecaeessaseseueesaueeseeeeeseeseueessanens 17 5 2 2 Initialisation State Machme 17 0 20 FSS CCI EE E EAA EEEE 17 5 2 4 Receiver Credit Coumter 18 5 2 9 Receiver Error Recovery ccccsscccssecceeeccuceceucecueecueeceuceceueessueesaeessueessusessueesseeseaeessaeess 18 5 2 6 TEST Le 18 St Transmitter Clock Generator 18 5 2 8 Transmitter Credit Counter 18 329 Transmitter Emor RECON La eee 18 6 TOP LEVEL CLOCK AND CONFIGURATION INTERFACE mrennnrnnnrnnnnrnnnarnnnennnnnnnnnnnnnennnnennnneenn 20 oi CFO REF PLEN hj 20 or CFO RAIE TE E 20 JE EE EEE EEE ED 20 ENN 21 TR COC E 21 6 5 1 Transmit clock configuration SYS DEFAULT rarunnnnennnnnnnnnnnnnennnnennnnennnnnnnnnnnnnennnnennnnennn 23 Page 3 of 69 ee Ref UoD Link User EADS E SpaceWire CODEC IP 2 4 paceWire ASTRIUM DUNDEE Issue 27 March 2009 User Manual Date Page 4 69 SH Austrian Aerospace 6 5 2 Transmit clock configuration SYS SGLOWWCIKR 24 6 5 3 Transmit bit clock configuration SYS SLOWCLK DIN 25 6
24. Reset T Write Acknowledge Flag l Overfiow Flag Use Dout Reset Value k Hex Active High Active High Programmable Flags Programmabie Full Type No Programmable Full Thresnoid Ea Full Threshold Assert Value fis Range 13 15 Full Threshold Negate Value fia Range 12 14 Active Low C Active Low Read Port Handshaking Valid Read Acknowledge gt r Underflow Read Error I valid Flag I Underfiow Flag Active High Active High Programmable Empty Type No Programmable Empty Threshold Empty Threshold Assert Value f Range 4 13 Empty Threshold Negate Value 5 Range 5 14 Active Low Active Low OPE Fifo Generator Fifo Generator SS Data Count Options FIFO Generator Summary I Use extra logic for more accurate Data Counts Selected FIFO Type Data Count Glocking Scheme Independent Giocks Synchronized With Cik Memory Type Distributed RAM Data Gount Width a Range 7 A Write Data Count FIFO Dimensions Synchronized With Write Ok r Write Width 9 Read Width 9 Write Data Count Width j4 Range 1 A Write Depth 17 Read Depth 17 I r Read Data Gount d Synchronized With Read Ok Read Data Count Width f Range 1 4 Additional Foutures Almost FuWEmpty Flags Not Selected Not Selected Programmabte FulvEmpty Flags Not Selected Not Selected Data Gount Outputs Not Selected Handshaking Not Selected Read Mode First word Fall th
25. SLOWRATE TXCLK CFG SLOWRATE SYSCLK CFG SLOW CE TICK IN TIME IN 7 0 TICK OUT TIME OUT 7 0 Time code Controller LINK DISABLE LINK START DOUT AUTO START DOUT F FLUSH TX SOUT TXRATE SOUT E Control Registers spwrlink STATUS 15 0 DIN DISC RUN ERR SIN PARITY RUN ERR Status ESCAPE RUN ERR Registers CREDIT RUN ERR TXBITCLK TX FIFO EMPTY TX FIFO DATA 8 0 TX FIFO READ Transmit RXBUF READ RXBUF PROGFLAG RXBUF CLK Receive Buffer i Figure 5 1 User Implementation with UoD Codec 5 2 Functions The UoD CODEC is a high speed serial transmitter receiver compliant with the SpaceWire standard AD1 The SpaceWire CODEC is responsible for making a connection with the SpaceWire interface Page 16 of 69 gemm Ref UoD Link User Vv EADS z SpaceWire CODEC IP 2 4 ASTRIUM DUNDEE Issue 27 March 2009 User Manual Date Page 17 69 H Austrian Aerospace at the other end of a link and managing the flow of N char across the link The interface transmits and receives SpaceWire characters which can be link characters L Char or normal characters N char L Chars are characters that are used to manage the flow of N char across a link NULL amp FCT N chars are the characters that are used to pass information across the link N char characters EOP EEP and TIMECODEs The following sub sections define the functional blocks which make up the SpaceWire interface are listed below 5 2 1 Conf
26. XBUF PROGFLAG for the receive buffer The empty flag is asserted when there are no N chars in the buffer The programmable flag is asserted when the number of characters in the buffer equals the input signal RXBUF PROGVAL In this way a half full or almost full flag can be generated dependent on the user application needs Note The RXBUF PROGFLAG has a one clock cycle latency before assertion and de assertion therefore it should be used as a guide for half full and almost full Figure 7 3 shows the timing specification for the receive buffer signals 1 2 3 4 5 6 7 8 9 10 11 12 RXBUF_WRADDR 0 2 RXBUF_WRVALID RXBUF DATA x ym y lt y XX RXBUF RDADDR 0 2 RXBUF READ SL NA RXBUF RDVALID RXBUF EMPTY A IV Ir Figure 7 3 Receive timing specification Note RXBUF READ can be asserted when the receive buffer is empty The read pointer will only be updated when RXBUF RDVALID is asserted The FIFO is not empty 7 2 8 Receive buffer clock frequency The minimum frequency of the receive buffer clock is dependent on the maximum data rate the SpaceWire CODEC will receive and the minimum size of packets which will be expected by the SpaceWire CODEC Page 45 of 69 gr Ref UoD Link User Ei Se EADS z SpaceWire CODEC IP 2 4 ASTRIUM DUNDEE Issue 27 March 2009 User Manual Date Page 46 69 Austrian Aerospace Minimum read clock with different input bit rates BitRate Tdata__ Teop _ MinNumData Tpacket
27. XCLK CFG SLOWRATE SYSCLK and TXRATE are affected by the generic ratenumbits 6 3 System Reset The interface signal RST N is an active low asynchronous reset of the UoD CODEG The RST N signal should be asserted for at least two system clock cycles to ensure synchronous reset elements register the reset The transmitter is reset synchronously to ensure no simultaneous transitions occur of DOUT SOUT The reset values are listed in Table 6 1 DOUT MG Reset in controlled manner DOUT F OO Reset in controlled manner SOUT SO Reset in controlled manner DOUT FE O Reset in controlled manner Page 20 of 69 ee Ref UoD Link User Vv EADS z SpaceWire CODEC IP 2 4 ASTRIUM DUNDEE Issue 27 March 2009 User Manual Date Page 21 69 Austrian Aerospace xno o Resetinconiroledmanner xeo In Resetincontroledmanner Goen o Restin controled manner sour ern o Resetinacontroledmanner mor o o S mon ag on RXBUF WRVALID RXBUFWRADDR an Rsu ane av gt aucun nu mac Rova In mac Prose v 1 n m 1 mec au Esc ul S PARTY RUN ERROR oo o oo oo EscaPe RUN ERROR oo gt Cap RN ERR o 1 STATUS 15 mv Table 6 1 Output Reset Values 6 4 System clock The interface signal SYSCLK clocks the interface state machine which controls link start up and link reconnection after an error is detected The system clock can also clock the receiver buffer and the transmitter dependen
28. aformat vhd Receive data formatter Formats double EOPs into a form which can be synchronised between receive clock and receive buffer successfully receive rxnchar resync ff vhd Receive data resynchronisation to receive buffer clock receive rxnchar resync ffstore vhd Receive data resynchronisation data storage flip flops Receive data resynchronisation data storage written to infer FPGA ram receive rxnchar_resync_ffstore_inferfogaram vhd receive rxnchar resync ffcell vhd Memory row built from flip flops receive rxnchar resync and vhd And gate for memory output multiplexer receive rxnchar resync dataena vhd Data enabled for memory output multiplexer receive rxnchar resync demux vhd De multiplexer for writing to memory receive rxnchar resync valid vhd Presents valid data synchronised with the empty flag receive rxdiscerr vhd Receiver disconnect detection receive rxtcode resync vhd Receiver time code resynchronisation from receive clock to system clock Transmit files transmit txencode vhd Serial output bit stream encoder transmit txtcode send vhd Time code input component transmit txddrreg vhd Transmit double data rate register Page 14 of 69 gemm Ref UoD Link User Vv 4 EADS z SpaceWire CODEC IP 2 4 ASTRIUM DUNDEE Issue 27 March 2009 User Manual Date Page 15 69 H Austrian Aerospace transmit txddrreg noenable vhd Transmit double data rate register without clock enable generated data
29. al Date Page 37 69 H Austrian Aerospace An increase in area footprint can be expected when CFG PIPELINE is equal to 1 6 9 Discarding Empty Packets The configuration input signal CFG DISCARD EMPTY PACKET when equal to 1 discards packets which have no cargo and consist only of an EOP EEP 6 10 Maximum Outstanding credit The configuration input signal CFG MAXCREDIT should be set to the maximum number of outstanding N chars which can be expected by the UoD SpaceWire CODEC The maximum number of N chars should be set in accordance with the generic rxbufaddrlen For example if a 16 byte buffer is used then CFG MAXCREDIT could be set to any value between 8 and 16 If CFG MAXCREDIT is set to greater than 16 the UoD SpaceWire link CODEC will not request more than 16 outstanding characters Typically the user should set CFG MAXCREDIT to the maximum value their buffer will support up to the value 56 The binary equivalent of the maximum outstanding credit value should be placed on CFG MAXCREDIT 5 0 i e Maximum outstanding N chars is 32 then CFG MAXCREDIT should be set to 100000 For SpaceWire compliant operation the following condition must be met 8 lt CFG_MAXCREDIT lt 56 Note the CFG_MAXCREDIT value does not have to be a factor of 8 and can be equal to 9 10 etc 6 11 Transmit Time code Handling The configuration constant CFG TICK IN KEEP determines how the SpaceWire interface handles TICK_IN requests when the link is
30. c ToCik DIN n a SIN n a eem Out Clock enable fr rising edge data when DDR outputs are used TXBTTCEK eg Out Clock enable for falling edge data when DDR outputs are used TXBTTCEK Table 8 1 Serial interface signals Page 56 of 69 gemm Ref UoD Link User Vv EADS z SpaceWire CODEC IP 2 4 ASTRIUM DUNDEE Issue 27 March 2009 User Manual Date Page 57 69 H Austrian Aerospace 9 SYNTHESIS 9 1 General The UoD CODEC was designed to be synthesised with hierarchy Synthesising in this way allows simple analysis of the resulting gate description As multiple configurations of the UoD SpaceWire CODEC are supported in one model the synthesis tool should be set to perform maximum optimisation This ensures that unused logic or constant input Signals are removed optimised by the synthesis tool If hierarchy is used the synthesis tool must be capable of optimising constant signals logic 1 0 across hierarchical boundaries 9 2 Memory The UoD CODEC is designed to support synthesis by multiple tool vendors For this purpose no internal FIFO or buffering memory structure was implemented with the CODEC and the memory must be generated externally dependent on the application Typically ASIC and FPGA process vendors supply generic FIFO structures which can be built to suit the application e g Internal RAM structures in the Xilinx Virtex series 9 3 Vendor Specific Information The following sections g
31. data from the receive buffer Updated on RXBUF CLK a valid read RXBUF PROGFLAG Out Programmable flag which can be used to indicate a half RXBUF CLK full condition or as a level indicator RXBUF PROGVAL Programmable flag value RXBUF CLK Table 7 3 Receive data interface signals 7 3 Timecode Interface The timecode interface consists of a transmit and receive interface Timecode signals are synchronous to the system clock Page 48 of 69 ee Ref UoD Link User Vv EADS E SpaceWire CODEC IP 2 4 paceWire ASTRIUM DUNDEE Issue 27 March 2009 User Manual Date Page 49 69 H Austrian Aerospace 7 3 1 Transmit The host timecode controller will typically include a six bit counter which is incremented decremented when a timecode is transmitted The timecode value should be placed on the input TIME IN 7 0 and TICK_IN should be asserted when a timecode is to be transmitted TICK_IN can be asserted for more than one clock cycle but only one timecode will be transmitted The timecode value which is present on TIME IN on the rising edge of SYSCLK when TICK IN is asserted will be transmitted The timecode timing specification is shown in Figure 7 5 1 2 3 4 5 6 TICK_IN TIMEN JA MM D AWA Figure 7 5 TICK IN interface Note No timecode buffering is employed and if the CODEC is not in state Run the TICK IN request is ignored This is consistent with the nature of timecode processing in a SpaceWire network 7 3
32. dependent transmit clock is required asynchronous to SYSCLK e All transmit clock generation is implemented externally e g external PLL The SpaceWire standard states a default 10Mbits s transmit rate shall be used at start up To implement this requirement the user can monitor the link running status bit and determine the TXCLK input frequency i e when the link is not running not in run state the TXCLK frequency should be 10 5 MHz When the link is running then TXCLK can be set to any frequency up to the maximum frequency supported by the users implementation LINK_RUNING External Clock generation e g PLL Tx Encode XENR XENF TT Figure 6 6 TX DEFAULT transmit clock configuration Page 28 of 69 gemm Ref UoD Link User Vv 4 EADS z SpaceWire CODEC IP 2 4 ASTRIUM DUNDEE Issue 27 March 2009 User Manual Date Page 29 69 H Austrian Aerospace 6 5 7 Transmit bit clock configuration TXCLK SLOWCLK The TXCLK_SLOWCLK configuration can be used when e An independent transmit clock is required asynchronous to SYSCLK e Transmit clock variable data rate is implemented externally or fixed e An independent 10 5MHz reference clock is desired The block diagram shown in Figure 6 7 describes the TX SLOWCLK configuration When the FSM SEL SLOW signal is asserted the link is not running or is starting up then SLOWCLK is selected by the glitch free multiplexer When the link is running then TXCLK is selec
33. e code interface control for the testbench VHDL SpaceWire link src verif uut tb Control status data and time code interface control for the UUT SpaceWire link src verif top Top level testbench components verif rtl RTL verification directory where the verification run is performed reference directory for scripts src verif Location of verification files scripts and test case commands Page 13 of 69 ee Ref UoD Link User Vv EADS E SpaceWire CODEC IP 2 4 paceWire ASTRIUM DUNDEE Issue 27 March 2009 User Manual Date Page 14 69 Austrian Aerospace Table 4 1 Directory descriptions 4 1 1 CODEC RTL files The RTL files are found in the codec_actel ip codec_actel src vhdl directory Description Initialisation state machine initfsm init_fsm vhd Initialisation state machine initfsm initfsm_counter vhd Initialisation state machine counter Initfsm initfsm_sync vhd Synchronisation of receiver signals for initialisation state machine Generic files other clk10gen vhd other clkmux vhd Generation of 100 ns clock enable pulse Clock multiplexer for multiplexing two clocks with an asynchronous signal Receive Files receive rxclock vhd Receiver clock recovery exclusive or gate Receiver credit counter and receive buffer pointer management receive rxcredit vhd receive bit stream decoder Decodes the input bit stream input SpaceWire character receive rxdecode vhd receive rxdat
34. e data rate SDR or double data rate DDR encoding depending on the configuration signal CFG_DDROUT 8 1 1 Single data rate outputs When SDR outputs are used then DOUT and SOUT port output signals can be connected directly to the implementation technology output buffers 8 1 2 Double data rate outputs When CFG DDROUT is equal to 1 the outputs DOUT_F and SOUT F are used as the falling edge data and DOUT and SOUT is the rising edge data The following diagrams show the configurations which can be used for DDR outputs DOUT DOUT_F SOUT SOUT_F UoD Generic CODEC DOUT_CLR_N SOUT_CLR_N TXBITCLK Figure 8 1 Generic DOUT and SOUT DDR encode The generic DOUT and SOUT DDR encode method is included in the file transmit txddrreg vhd and transmit txddrreg_noenable vhd The file transmit txddrreg vhd can be used for all configurations It rebuilds the transmit clock into a multiplexer select signal for the output DDR multiplexer using clock enables if required to generate a variable data rate The DDR output is shown in Figure 8 2 Page 53 of 69 ANERSITE Ref UoD Link User Q Ze EADS E SpaceWire CODEC IP 2 4 paceWire ASTRIUM DUNDEE Issue 27 March 2009 User Manual Date Page 54 69 SEH Austrian Aerospace EN RISE MUX SEL TXBITCLK MUX_SEL 4 EEE EN FALL poutr Ty mm y P DSJOUT OUT F mm y DSJOUT F DOUT Aa y a y e y
35. edit counter can hold CFG SLOWRATE SYSCLK Number of clock cycles for a 10MHz rate n a TIMING 6 4 In Number of 10MHz rate clock cycles to count for n a the 6 4us timeout TIMING 12 8 In Number of 10MHz rate clock cycles to count for n a the 12 8us timeout TIMING 850ns In Number of 10MHz rate clock cycles to count for n a the 850 ns disconnect period timer Table 6 4 Configuration signals overview Page 41 of 69 VERSI sn Ref UoD Link User 2 EADS z SpaceWire CODEC IP 2 4 ASTRIUM DUNDEE Issue 27 March 2009 User Manual Date Page 42 69 H Austrian Aerospace INTERNAL INTERFACE The following sub sections define the operation of the UoD SpaceWire CODEC 7 1 Link State Operation The link state operation signals control the enabling and disabling of the SpaceWire CODEC The SpaceWire link state machine is shown in Figure 7 1 Reset RxErr OR ErrorReset CreditError OR R f eset Tx Link Disabled Reset Rx Run Send Time Codes FCTs N Chars NULLs RxErr OR gotN Char OR gotTime Code OR after 12 8 us RxErr OR gotFCT OR gotN Char OR Connecting after 12 8 us Send FCTs NULLs Enable Rx gotTime Code OR RxErr OR gotFCT OR gotN Char OR gotTime Code After 6 4 us ErrorWait Reset Tx Enable Rx RxErr OR gotFCT OR gotN Char OR gotTime Code After 12 8 us Ready Reset Tx Enable Rx gotNULL Started Link Enabled Send NULLs
36. equivalent of the entity name e g The entity rxcredit is represented in the file rxcredit vhd All VHDL entity names can be mixed case or lower case All VHDL signal and port names are in UPPERCASE Signals which have multi word names are split with an underscore character e g credit error is represented as CREDIT ERROR For all signals the ieee std_logic_1164 STD LOGIC and STD LOGIC VECTOR types are used This ensures that all types are consistent through all VHDL files and no conversions between STD LOGIC and STD_ULOGIC are required or necessary For all vector signals the highest number index is the MSB and the lowest number index is the LSB i e the n downto 0 vector type is used For all arithmetic signals the ieee numeric_std UNSIGNED type is used Arithmetic functions such as or are implemented in the numeric_std package Page 11 of 69 gemm Ref UoD Link User Vv A EADS z SpaceWire CODEC IP 2 4 ASTRIUM DUNDEE Issue 27 March 2009 User Manual Date Page 12 69 H Austrian Aerospace Conversions from UNSIGNED to STD LOGIC VECTOR are implemented using type conversion e g STD LOGIC VECTOR unsigned signal Conversions from STD LOGIC VECTOR to UNSIGNED are implemented using type conversion e g UNSIGNED std_logic vector signal Conversions from UNSIGNED to integer are implemented using the numeric_std function to_integer unsigned_sig Conversions from integers to UNSIGNED are imple
37. er When TXRATE is not equal to zero the clock divider output XI CLK DIV is selected by the multiplexer Page 31 of 69 ee Ref UoD Link User Vv EADS E SpaceWire CODEC IP 2 4 paceWire ASTRIUM DUNDEE Issue 27 March 2009 User Manual Date Page 32 69 H Austrian Aerospace 6 5 10 Transmit bit clock configuration TXCLK EN The configuration TXCLK EN can be used when e An independent transmit clock is required asynchronous to SYSCLK e The number of clock nets available to the user is limited TXCLK is used as the baseline transmit clock and synchronous clock enables are used to generate the variable data rate Figure 6 10 shows the block diagram for TXCLK_EN DOUT DOUT_F TXCLK Tx Encode SOUT EH SOUT F EI FSM SEL SLOW XENR TXRATE Glock x E Enable Generator XENF E CFG SLOWRATE TXCLK Figure 6 10 TXCLK EN transmit clock configuration When the internal state machine signal FSM SEL SLOW is asserted the input CFG SLOWRATE TXCLK determines the final data rate When FSM SEL SLOW is de asserted then TXRATE determines the final data rate The outputs XENR and XENF should be connected to the rising edge enable and falling edge enable of the transmit double data rate output register Note When DDR output are selected and CFG SLOWRATE TXCLK or TXRATE is an odd number the duty cycle on DOUT SOUT will not be 50 50 The worst case duty cycle when TXRATE or CFG SLOWRATE TX 7 will be 75 25 i e 15ns dns f
38. es 10Mbit s For better resolution of the disconnect and state machine timers a 10MHz reference clock rate can be used by setting CFG_SLOWCLK_10MHZ to 1 Internally the 10MHz signal is divided to give a 5MHz reference clock to the transmitter when initialisation is performed 6 7 Receive buffer clock The user can select which clock is used to resynchronise N chars from the receiver clock domain and write them to the receiver buffer When the configuration signal CFG SYNCRDCLK 1 then SYSCLK is used When CFG _SYNCRDCLK 0 the input RDCLK is used The interface signal RDCLK can be used as an independent read clock for the receiver buffer This can be useful if very high data rates are implemented and RDCLK should be partitioned from SYSCLK The receive buffer data flow is shown in Figure 6 11 I DIN 4 Byte Re sync I Receive Clock Receive buffer Domain Glock Domain GODEC boundary Figure 6 11 Receive buffer data flow 6 8 Pipelining The configuration signal CFG PIPELINE allows the UoD SpaceWire CODEC to insert pipeline registers where appropriate to decrease the delays between flip flops and increase clock speed and transmission speed When CFG PIPELINE 1 then an extra cycle of latency is required to transmit receive one Timecode N char Page 36 of 69 ee Ref UoD Link User Vv d EADS E SpaceWire CODEC IP 2 4 paceWire ASTRIUM DUNDEE Issue 27 March 2009 User Manu
39. es 40 7 NEEN NEEN 42 LINK STATE OPERATION eege SE 42 7 1 1 EE EE e EEE EE EE NE 42 7 1 2 Ka IS AIO IG EE ET EN 43 Cea DATANT R SR 43 7 2 1 RI UE 43 7 2 2 Transmit FIFO signals Operation c ccccceeccceecceeeeeeeeeseeeeseeeeseeeeseeeeseeesaeeeseeeeseeeeseeeeaes 43 7 2 3 Fe 44 7 2 4 Receive buffer signals operation cccccccceeccceeeeceeecaeeseeeeseeeeseeeeseeseeeeseueeseeeseeesaeeess 44 7 2 5 PARENT 44 7 2 6 EE aera pees atc eee a EEE 44 7 2 1 FA el 45 7 2 8 Receive buffer clock frequency cccccscccsseeceseeceeeceueeceeeseueeceessueeseaeessuesseeeesaeesageess 45 7 2 9 Maximum input bit rate dependent on receive buffer clock Treouency 47 7210 Data Interface ett EE 48 Tao TIMECODE INTERFACE yack oetenae cies oeentenses 48 7 3 1 TANS EE EEE RE EEE EE EEE 49 Page 4 of 69 ee Ref UoD Link User EADS E SpaceWire CODEC IP 2 4 paceWire ASTRIUM DUNDEE Issue 27 March 2009 User Manual Date Page 5 69 H Austrian Aerospace 1 3 2 KN 49 7 33 Timecode Interface Signals A 49 EE SE NER EEE ERE EEE ENE EE 50 LE ERROR RECOVERY E 51 7 5 1 Transmitter Error Recovery ccccccscccececesceceeecceeecceeeceuceceueesaueesaeeseueeseusesaueeseenenaeeseas 51 1 9 2 Transmitter Buffer Flushing EE 51 7 5 3 Receiver Error Recovery aa 51 6 EXTERNAL INTERFACE EE 53 8 1 DATA STROBE ENCODING ees deeg aa seem desk DEE 53 8 1 1 TEEN 53 8 1 2 Double data rate outputs esac ncitodiien ccisscewiweiadeceusence
40. fines how the University of Dundee SpaceWire CODEC VHDL code shall be used Page 9 of 69 Fn Ref UoD Link User E a A EADS z SpaceWire CODEC IP 2 4 ASTRIUM DUNDEE Issue 27 March 2009 User Manual Date Page 10 69 H Austrian Aerospace 2 APPLICABLE DOCUMENTS In this section the documents referenced in this document are listed Document Reference Rf Document name ECSS E ST 50 12C European Cooperation for Space Standardization 31July2008 SpaceWire Links Nodes Routers and Networks March 2003 Table 2 1 Applicable Documents Page 10 of 69 ee Ref UoD Link User Vv EADS E SpaceWire CODEC IP 2 4 paceWire ASTRIUM DUNDEE Issue 27 March 2009 User Manual Date Page 11 69 H Austrian Aerospace 3 DEFINITIONS In this Document the following conventions are used 3 1 Terms and definitions Number of bits transmitted received every second byte Eight bits of information DDR Double data rate Two bits of data transmitted for each transmit clock period FCT Flow control token Transmitter sends one FCT when room in receive buffer for eight more N chars Init FSM SpaceWire exchange level initialisation state machine which controls start up and link connection other edges in that signal SDR UoD 3 2 VHDL Code Terms and Definitions In the VHDL code the following VHDL conventions are VHDL entity architecture pairs are placed in the same VHDL file The filename is a lowercase
41. he design of the glitch free multiplexer Page 22 of 69 gemm Ref UoD Link User Vv A EADS z SpaceWire CODEC IP 2 4 ASTRIUM DUNDEE Issue 27 March 2009 User Manual Date Page 23 69 H Austrian Aerospace 6 5 1 Transmit clock configuration SYS DEFAULT The SYS DEFAULT configuration is used when SYSCLK is equal to the default 10MHz data signalling rate The SYSCLK frequency should be set to 10MHz when single data rate is used or 5MHz when DDR outputs are used Note The data rate in this configuration is fixed to 10Mbits s as the SYSCLK input is used as the timings reference state machine timeout and receive disconnect timeout This configuration is the most efficient implementation of the UoD SpaceWire CODEC as e No internal clock generation is required e Synchronisation of signals is not required between SYSCLK and the transmit bit clock e SYSCLK is used as the 10 5Mhz reference clock for disconnect detection and state machine timeouts Figure 6 1 shows the transmission scheme configuration SYSCLK XENR XENF Figure 6 1 SYS DEFAULT transmit clock configuration Page 23 of 69 EADS 6 5 2 The SYS SLOWCLK configuration can be used when an independent 10MHz clock is used for the default 10Mbits sec transmit rate and the transmitter clock is the system clock No internal variable data rate generator is implemented The SLOWCLK frequency should be set to 10MHz when single ASTRIUM
42. hen loading state machine counter Example System Clock Frequency 30MHz 33 333 ns period CFG BITCLK SYS SLOWCLK 6 4418 333ns 100ns TIMING 64 61 12 8us 333ns 100ns TIMING 128 125 6 14 Disconnect Timeout Uncertainty The disconnect period of the SpaceWire link is specified to be from 727ns to 1000ns see the SpaceWire Standard section 8 11 12 In the SpaceWire CODEC model the timeout period for the disconnect timeout counter has a one cycle uncertainty For example if the disconnect timer is set to 9 cycles of a 100ns period timeout clock the disconnect period will be from 800 ns to 900 ns as shown in Figure 6 14 100 ns H Clock Cycles KEENE EN EN ERE EEE 800 ns Disconnect Detected Latest transition of RXCLK Earliest transition of RXCLK Figure 6 14 Disconnect timeout uncertainty 100ns period 6 15 Configuration Signals Overview Type Description Sync To Clk Is receive buffer clock synchronous to SYSCLK la CFG PIPELINE In Should pipelining flip flops be inserted into the n UoD SpaceWire CODEC to increase achievable data rate Page 40 of 69 ee Ref UoD Link User Vv EADS E SpaceWire CODEC IP 2 4 paceWire ASTRIUM DUNDEE Issue 27 March 2009 User Manual Date Page 41 69 H Austrian Aerospace CFG DISCARD EMPTY PKT In Should empty packets be discarded by the n a receiver CFG MAXCREDIT In Maximum outstanding credit the receive buffer RXBUF CLK cr
43. iguration Overview The UoD SpaceWire codec can be configured to suit the users application as follows e Pipelined to increase transmission speed or non pipelined to save area e DDR outputs or SDR outputs depending the on required data rate and the users selected technology e Transmission clock configuration options to allow an independent transmit clock and default reference clock therefore greatly increasing the achievable data rate and decoupling the transmit logic from the system clock logic e Internal variable data rate generation e Configurable receive buffer size Internal FCT credit counter operations are handled internally 5 2 2 Initialisation State Machine The CODEC state machine is responsible for initiating a connection on the link and performing related synchronisation The state machine determines its next state by monitoring receiver signals which indicate the type of characters received and any receiver errors The state machine enables the transmitter to send NULLs FCTs N char characters time codes and end of packet markers EOP and EEP 5 2 3 Receiver The receiver is responsible for decoding the received data strobe encoded bit stream into SpaceWire characters The receiver reports the type of characters received and any errors encountered to the initialisation state machine which enables and disables the receiver as appropriate The receiver is implemented in two parts a decoder which decodes characters i
44. ive information on specific vendor issues when synthesising the CODEC 9 3 1 XST When synthesising with XST the Automatic FSM Extraction option in the XST synthesis options dialog should be set to NO XST does not synthesise the rxnchar_resync_ff vhd buffer correctly A simple option is to use a separate coregent module to implement the buffer as a dual port clocked FIFO as shown in the coregen generation options dialogs in Figure 9 1 The buffer is implemented using LUT RAM resources which consume minimal area in the final design Once the XST coregent module has been generated the component should be inserted in lt path to codec gt src vhal top spwrlink vhd so the port map is correct with the newly generated coregent module The VHDL code is shown below receiver nchar resynchronisation with coregen module rxnchar resync ff 1 rxnchar resync ff port map wr clk gt RX CLK rd clk gt RDCLK i Page 57 of 69 4 me Ref UoD Link User EADS d SpaceWire CODEC IP 2 4 pe DUNDEE Issue 27 March 2009 User Manual Austrian Aerospace Date Page 58 69 rd en gt NCHAR RESYNC READ rst gt RST wr_en gt GOT DATA empty gt NCHAR RESYNC EMPTY full gt open din gt FORMATTED DATA dout gt NCHAR RESYNCED CT Fifo Generator Sc CT Fifo Generator SS Component Name fxncnar resyn MFIFO Implementation Choose the FIFO implementation trom one ot the following Read Mode
45. lscweiedtanadnedendnadeciaredinndebemtedescatendentsedeneasads 53 8 1 3 Data Sope TMN EEE aE EEREN EN E EEEE T Ea ES EAU NE 55 8 1 4 Serial Interface signals cccccccssccceeccceeeccseeceuceceucecucesaeeeeseeceuceceueesseeeseeeseueessaeessaeess 56 EN ALL EE 57 EE EEE EE EEE NE ee ee ee eee 57 I EV 57 9 3 VENDOR SPECIFIC INFORMATION senere gd 57 9 3 1 NT 57 10 STATIC TIMING ANALYSIS usb 59 10 1 CLOCK CONSTRAINT ANALYSIS oeh oncececddianontin geed Eed eebe 59 10 2 RECEIVER CLOCK STATIC TIMING ANALYSIS 0cccceccceeeeceeeeeeeeceeeeseeeeeeeeseueeeeeeeseueesaueesaeeeaes 60 af Ze OR El leen 60 1022 Re oe SEE NE 61 10 2 3 Strobe Setup CIC CK EE 62 10 2 4 Minimum Pulse With 63 1025 Skew TANGEN EE en ed 64 10 3 GENERIC TRANSMITTER DOUBLE DATA RATE OUTPUTS runranrrnanennnnnvnnnnvnnennnnennnnennnnnnnnnnnnnennnne 65 10 3 1 Generic DDR output Method one cece ceeceeeeeeeeeeceeeeseeeeseeesseeeseeeseeeeseeeeaeeesaeeees 65 10 3 2 Generic DDR Method Two 67 11 CONFORMITY se 68 12 APPENDIX I CLOCK MULTIPLEXER eennurnnnnornnnnennnnnnnnnnnnnnnnennnnnevnnnnennnnnnnnnnnnnnnnennnnnennnnnunnnn 69 Page 5 of 69 ee Ref UoD Link User EADS E SpaceWire CODEC IP 2 4 paceWire ASTRIUM DUNDEE Issue 27 March 2009 User Manual Date Page 6 69 H Austrian Aerospace Il LIST OF FIGURES Figure 4 1 CODEC directory Structure ccccccccssccceseeceeeceeeccueeceeeceuceceueeseeesseeseueessueesausesseessaeeseas 13
46. mented using the numeric std function to_unsigned integer_val sign length Active low signals are labelled SIGNAL NAME N Output signals from entities are often required internally for circuit feedback purposes Redundant signals which are required for this purpose are labelled PORT SIGNAL i and assigned to the output in the code as PORT SIGNAL lt PORT SIGNAL i in the VHDL code 3 3 Document Terms and Definitions In this Document the following conventions are used Signal and port names are written using the bold courier new font e g SIGNAL NAME Page 12 of 69 ee Ref UoD Link User Vv Ei Ge EADS b4 SpaceWire CODEC IP 2 4 paceWire ASTRIUM DUNDEE Issue 27 March 2009 User Manual Date Page 13 69 H Austrian Aerospace 4 CONFIGURATION MANAGEMENT 4 1 Directory Structure The directory structure of the SpaceWire CODEC directory structure is shown in the list below lt root gt Figure 4 1 CODEC directory structure A description of each directory is listed in the Table 4 1 Directory Function OOOO srlvhalothe srclvhalreceive srclvhaltxck chte src verif cmd Command files which perform the verification test cases of the SpaceWire CODEC src verif scripts Scripts to compile and run the verification of the SpaceWire CODEC src verif gen tb General testbench components and units VHDL files src verif package Testbench VHDL package files src verif spwr tb Control status data and tim
47. n rising and falling edge data on each clock cycle The net delays which feed the multiplexer should be balanced to ensure no glitches occur on DOUT or SOUT The skew between DOUT and SOUT should be minimised as this affects the maximum data rate achievable Two methods can be considered for the generic DDR output encoding when using the UoD CODEC 10 3 1 Generic DDR output method one The first DDR output method uses the CODEC generic DDR multiplexer to drive the outputs DOUT and SOUT Figure 10 9 shows the block diagram for the first method of DDR encoding where two lines are output from the transmit shift register and are multiplexed on the output Spwr_Link_Interface LVDS DS OUT TX SHIFT TX DDR P Fiqure 10 9 DDR output encoding Method one CLK 100MHz This method requires delay balancing on the inputs to the multiplexer to avoid high speed glitches in the DOUT and SOUT signals The following diagram shows the paths which must be constrained such that the LR LF net delays are equal and the DR DFD net delays are equal The path delay from the multiplexer select flip flops LR LF to the output must be greater than the paths from multiplexer Page 65 of 69 ee Ref UoD Link User Vv EADS E SpaceWire CODEC IP 2 4 paceWire ASTRIUM DUNDEE Issue 27 March 2009 User Manual Date Page 66 69 Austrian Aerospace output signal This is because the multiplexer select signal selects one output while
48. n the receiver clock domain and a synchroniser which then synchronises receiver signals to the system clock domain This method ensures all receiver outputs are synchronous to the system clock Page 17 of 69 gemm Ref UoD Link User Vv A EADS z SpaceWire CODEC IP 2 4 ASTRIUM DUNDEE Issue 27 March 2009 User Manual Date Page 18 69 H Austrian Aerospace 5 2 4 Receiver Credit Counter The receiver credit counter keeps a record of the buffer space available in the receiver FIFO and the number of characters which have been requested from the link This allows the CODEC to implement flow control The receiver credit counter implements the receiver buffer pointers This makes the implementation of the receiver credit counter and the receiver buffer more efficient as the number of counters required is kept to a minimum 5 2 5 Receiver Error Recovery The receiver error recovery block recovers the receiver credit counters and the receiver FIFO after an error occurs After an error an EEP marker is added to the receiver FIFO The receiver credit counter must be updated because all previously transmitted FCTs are discarded at the other end of the link due to error recovery 5 2 6 Transmitter The transmitter is responsible for transmitting L Chars and N chars over a link using data strobe encoding The interface state machine determines which type of character the transmitter can send over the link The transmitter accepts N char
49. ndent on the actual bit rate transmit clock values or the average jitter on DIN SIN a tolerance should be added to the receive buffer clock e g 1 Example If characters are received at the maximum rate then jitter on DIN and SIN and therefore RXCLK can cause the Taverage time to drop below the expected value For example if jitter on DIN SIN caused the bit rate to vary between 200 and 205 Mbits sec then Taverage will vary between 34 and 35 ns therefore the minimum read clock should be 29 286 MHz 7 2 9 Maximum input bit rate dependent on receive buffer clock frequency Analysis of the maximum input bit rate can be useful when the receive buffer clock frequency is fixed E g receive buffer clock is tied to the system clock which is dependent on an external processor The function below shows the maximum input bit rate dependent on the receive buffer clock 1 ae Texan cy x NumPRIN chars NumPktBits T 7 1 TER RrBufClkFrequency NumPktNchars MinNumbata I NumPktBits MinNumData x 10 4 Example If the receive buffer frequency is 50MHz and the minimum packet expected is 1 N char EOP then Trxbuf_clk 20ns and NumPktNchars 2 and NumPktBits 14 therefore 1 Maz Bit Rate 350M bit s 20ns x 2 14 i e The maximum bit rate can be 7 times the receive buffer clock rate when MinNumData 1 Page 47 of 69 ee Ref UoD Link User Vv EADS E SpaceWire CODEC IP 2 4 paceWire
50. nfiguration agnale 38 Figure 6 13 Additional time added when loading state machine counter rrranrrnnnrrnnnrranrrvanernnnrvnnnennn 40 Figure 6 14 Disconnect timeout uncertainty 100ns period 40 Figure 7 1 Initialisation state machine rranunnnnnnnnnnnnnnnrnnnnranernanennnnernnnnnnnrnnanennaennuennasennnennanennasennnsennn 42 Figure 7 2 Transmit Timing Specification rarrnnnrernnnnrnnrrranernnnrnnnnevnnnnrnnnnnanennnnennanennnnnnnnennanennnsennnsennn 44 Figure 7 3 Receive timing specification rrnnnrnnnnrnnnnnnnnnrnnnrrnanrrnnnrnnnnnnnnrnnanrnnanrnnnnennnnnnnnsnnanennanennnsennn 45 Figure 7 4 Minimum Receive buffer clock TIreouency 46 PIQUE 1 5 TICK IN lat 49 Figure 7 6 TICK OUT mtertace AA 49 Figure 8 1 Generic DOUT and SOUT DDR encode rrrannnnannnnanennnnevnnnnnnnrnnanennnnennnnennnnnnnnennanennasennnsennn 53 Figure 8 2 Transmit DDR register Transmmttvddrreg vd 54 Figure 8 3 txddrreg noenable vhd double data rate generation logic and waveform rrrararnanrnnnnennn 54 Figure 8 4 Vendor specific DOUT and SOUT DDR encode arrnnnnrnnnnnnnnnnnanernanennnnennnnnnnnrnnnnennnsennnnennn 55 Figure 9 1 ISE coregent settings for rxnchar resync Tv 58 Figure 10 1 Receive Clock Data Recovery sunsnnnennsnnnerrnnrrnnrnnrrnnrnrrrnrrnrrnnrrnnrnnrrnnrnnnrnnrrenrnnernnee 60 Figure 10 2 Data Setup Time Timing Diagram 0nnn0nnonnnennnnnnsnnnernnnnnrrrnnrrenrnnrrnnrnerrsnrnnrrnnrrenrnnrennne 62 Figu
51. not running The default behaviour of the link CFG TICK IN KEEP 0 discards time codes when the interface is not in the run state When the link is running time codes are transmitted with priority over other characters as normal The legacy behaviour of the link CFG TICK IN KEEP 1 keeps time codes in a 1 time code storage buffer until the link enters the run state If a new time code is requested to be transmitted TICK IN the currently held time code is discarded and the new time code is the next time code to be sent When the link enters the run state the held time code will be immediately sent Page 37 of 69 ee Ref UoD Link User gue ES 2 4 SpaceWire CODEC IP ASTRIUM DUNDEE Issue 27 March 2009 User Manual Date Page 38 69 KP Austrian Aerospace 6 12 Intenal receiver disconnect and Init FSM timeout Counters If the CFG BITCLK configuration signal is set to a value which does not support an external 10 5MHz clock signal the internal receiver disconnect and state machine timeout counters will be enabled from an internal or external 10MHz clock enable pulse generator The configuration signal CFG SLOW CE SEL determines if an internal or external clock enable pulse is used If an internal clock enable generator is used the number of clock cycles to count is set to CFG SLOWRATE SYSCLK Additional to CFG SLOWRATE SYSCLK the configuration signals TIMING 6 4 TIMING 12 8 and TIMING 850ns determine the number of cycles of the cl
52. ock enable pulse to count The diagram below shows the configuration steps between the configuration signals and the internal SpaceWire link blocks CFG SLOW CE SEL TIMING 6 4 TIMING 12 8 CFG SLOWRATE SYSCLK CIk10Gen 0 gt E Init FSM Counter 1 gt TIMING 850ns Init FSM Counter gt Figure 6 12 CFG SLOW CE SEL configuration signals SYSCLK SLOW_CE When the signal CFG SLOW CE SEL 1 the input SLOW CE will be selected as the 10MHz clock enable pulse When CFG SLOW CE SEL 0 then an internal 10MHz pulse will be generated dependent on the signal CFG SLOWRATE SYSCLK The CFG SLOWRATE SYSCLK value should be set via the function equation SysClock Frequency CFG_SLOW RAT E SY SCLK WM _ 1 10M Hz Equation 6 1 CFG SLOWRATE SYSCLK rounded down to nearest integer Example System Clock Frequency 30MHz SLOW CFG_SLOW RATE SY SCLK Carne 30M H dE The system clock frequency may not provide an adequate 10MHz timeout rate for the initialisation state machine timeouts i e a system clock is 25MHz gives a clock period of 40 ns and a Page 38 of 69 ee Ref UoD Link User Vv EADS E SpaceWire CODEC IP 2 4 paceWire ASTRIUM DUNDEE Issue 27 March 2009 User Manual Date Page 39 69 H Austrian Aerospace CFG SLOWRATE SYSCLK value of 1 This will give a clock enable rate of 80 ns 40 ns CFG SLOWRATE SYSCLK 1 for the 10MHz timeout rate counter
53. of clock enables is not desired typically clock enabled DDR outputs not supported when external vendor specific DDR outputs are used e An external 10MHz reference clock is not available The configuration SYS DIV is shown in Figure 6 4 FSM SEL SLOW TXBITCLK Tx Encode SYSCLK Glitch Free Clock Multiplexer XENR XENF D Figure 6 4 SYS DIV transmit clock configuration The variable data rate and 10MHz default data rate are implemented using a programmable divider which enables a toggle flip flop When the SpaceWire CODEC is performing link start up FSM SEL SLOW the input CFG SLOWRATE TXCLK determines the frequency of TXBITCLK When link start up has been performed and a link connection has been established the input TXRATE determines the data rate When TXRATE is equal to zero maximum rate then XIMAX is asserted and SYSCLK is selected by the glitch free clock multiplexer When TXRATE is not equal to zero the clock generator output XI CLK DIV is selected by the multiplexer Synchronisation is automatically performed by the SpaceWire CODEC as TXBITCLK is asynchronous to SYSCLK in this configuration Page 26 of 69 dn Ref UoD Link User d ES 2 4 EADS SpaceWire CODEC IP ASTRIUM DUNDEE Issue 27 March 2009 User Manual Date Page 27 I 69 H Austrian Aerospace 6 5 5 Transmit bit clock configuration SYS EN The configuration SYS EN allows the default 10Mbits s transmit rate and the variable transmission ra
54. or 2 transitions at a 20 ns period This is still a valid configuration under the SpaceWire standard Page 32 of 69 ee Ref UoD Link User frit ES 2 4 SpaceWire CODEC IP ASTRIUM DUNDEE Issue 27 March 2009 User Manual Date Page 33 69 KP Austrian Aerospace 6 5 11 Variable data rate and default 10Mbits sec data rate generation In the previous sections the signals CFG SLOWRATE TXCLK and TXRATE are used to determine the variable and default data rates The following functions should be used to determine the value of each signal me CFG SLOW RATE_TXCLK 1 tpi ee TXRATE 1 The top level generic CFG RATENUMBITS should be set according to the maximum value which will be used to divide the value TxMaxBitRate Warning TXRATE is used in the transmit clock domain therefore should be synchronous to the SpaceWire link signal TXBITCLK In some configurations TXBITCLK is variable The following examples show values of CFG SLOWRATE TXCLK and TXCLK dependent on the maximum bit rate and also the generic ratenumbits Example 1 TxMaxBitRate 200Mbits s 200M bit CFG SLOWRATE TXCLK OMH 1 _ 19 10M tit s lf TXRATE is equal to 3 then 200M bit TxBitRate DMS _ some 3 1 If the slowest clock speed is 10Mbits sec CFG SLOWRATE TXCLK 19 the generic ratenumbits should be set to 5 2 5 max value 31 Example 2 TxMaxBitRate 66Mbits s CFG SLOW RATE TXCLK TOMBE 1 5 6 5 or 6 can be used If CFG SL
55. overy is taking place but the transmitter is prevented from reading from the transmit FIFO until error recovery is complete Page 19 of 69 ee Ref UoD Link User Vv EADS E SpaceWire CODEC IP 2 4 paceWire ASTRIUM DUNDEE Issue 27 March 2009 User Manual Date Page 20 69 H Austrian Aerospace 6 TOP LEVEL CLOCK AND CONFIGURATION INTERFACE The following sections define the internal and external interfaces which are employed in the UoD SpaceWire CODEC Each section has a detailed description of the signal functions and an overview table for each signal and the clock which the signal is synchronous to Note The configuration constants mentioned in the following sections are defined in the package top Spwrlink pkg vhd 6 1 CFG RXBUF ADDRLEN The configuration constant CFG RXBUF ADDRLEN determines the length of the read and write addresses for the receive buffer and therefore the size of the receive buffer The buffer size is defined as 2A rxbufaddrlen For example the receive buffer address length is 10 the receive buffer size will be 1 Kbytes The SpaceWire CODEC will automatically handle FCT credit operations dependent on the size of the buffer 62 CFG RATE NUMBITS The configuration constant CFG RATE NUMBITS determines the signal length of slow rate and transmitter rate inputs The signal length determines the size of the internal down counters used for variable data rate generation The signals CFG SLOWRATE T
56. r TMIND eq 4 Note when data is skewed then Tsskew IS Zero and when strobe is skewed Tpskew IS Zero for eq 4 Figure 10 5 shows the data and strobe skew relationships Tur Toskew T Tu Tss MIND gt Sin es Sin Pp Din Din Din at D pin of FF N Din at D pin of FF Latest Sin at CLK pin of FF N Latest Sin at CLK pin of FF Data Skewed Invalid Strobe Skewed Invalid Figure 10 5 Data and Strobe Skew effects on Strobe Setup Time 10 2 4 Minimum Pulse Width The minimum pulse width of the data and strobe signals must be greater than the bit period The minimum pulse width of the SpaceWire receive clock with no skew is defined as the minimum of the following IMAXDCLK MINSCLK IMAXSCLK MINDCLK eq5 When data and strobe are skewed and jitter is added the minimum pulse with is defined as follows Tur TpsKew 2 x Tyrrrer gt Tmaxp Tminscik Tsu Tup eq6 Tur Tsskew 2 x Tyrrrer gt Tmaxscek Tminp Tsu Tup eq7 The timing parameters are shown in Figure 10 6 Page 63 of 69 ee Ref UoD Link User Kos amp i SS SpaceWire CODEC IP ASTRIUM DUNDEE Issue 27 March 2009 User Manual Date Page 64 69 Austrian Aerospace Din Din Sin Sin wan Max Din at FF Min Din at FF RxCIk RxClk TMINSCLK Data Skewed Strobe Skewed Figure 10 6 Minimum Pulse Width 10 2 5 Skew Tolerance To define the tolerance of the data and strobe signals to skew the following timing parame
57. rate Variable data rate files txclk txclkgen vhd Transmit clock generation and multiplexing component txclk txclk_divider vhd Transmit clock divider to generate different data rates txclk txclk_en_gen vhd Generation of variable rate transmit data rate enable pulse Table 4 2 RIL file descriptions 4 1 2 VHDL File Hierachy The hierarchy of the VHDL files is described in the following tree diagram LOp spwrlink vad others clklOgen vhd et ADIGE EE FSM VG ASH NLP SM INE ESN GONE VA Vet Iinitism initism resync vhd receive rxcredit vhd receive rxdecode vhd receive rxtcode resync vhd V Pecelve rxnchar resyne ff vhd rec ive rxnchar resync demux vhd N receive rxnchar resync dataena vhd rec ive rxnchar resync valid vhd transmit txencode vhd V Uransmit txtcode send vhd Vert texclk txclkgen vid txclk txclk en gen vhd N de tee divaider vid others clkmux vhd Figure 4 2 VHDL files hierarchy Page 15 of 69 A Lager Ref UoD Link User EADS SpaceWire CODEC IP 2 4 ASTRIUM DUNDEE Issue 27 March 2009 User Manual l Austrian aerospace Date Page 16 69 5 FUNCTIONAL OVERVIEW In this section an overview of the SpaceWire Codec architecture is provided 5 1 System Overview A block diagram of the SpaceWire CODEC and expected usage is given in Figure 5 1 RST_N SYSCLK TXCLK SLOWCLK RDCLK CFG MAXCREDIT CFG
58. re 10 3 Large clock delay setup time violaton 62 Figure 10 4 Latest Strobe Setup Time When no SKeWw rrarrnnanrrnnnnennnnrvnnrrnanennnnennnnennnnnnnnennnnennaennnnennn 63 Figure 10 5 Data and Strobe Skew effects on Strobe Setup Tme 63 Page 6 of 69 ee Ref UoD Link User EADS E SpaceWire CODEC IP 2 4 paceWire ASTRIUM DUNDEE Issue 27 March 2009 User Manual Date Page 7 69 Austrian Aerospace Figure 10 6 Minimum Pulse Wd 64 Figure 10 7 Data Skew Tolerance n nnnnennnnnnnnnnrrrsnnnrnnsnrnrrrnnrrnnrnnrrnrrsrrnnrrnrrnnrrnnrrnrrnnrnnnrnnrrenrnnrennnn 64 Figure 10 8 Maximum Strobe Gkeuw cess eeseeeeseeeeseeessaeeseueesaueeseeesseeeeaes 65 Figure 10 9 DDR output encoding Method one 65 Figure 10 10 DDR output multiplexer seier 66 Figure 10 11 DDR output multiplexer timing SPECIFICATION rrrnrernnrrrnnrrranrrrarernnnrrnnnrrnrrranernnrrnnnnennn 66 Figure 10 12 Method Two DDR output encoding cece eeseeeeseeeeaeeeeaeeeseeeesaueesaeeeseeeaes 67 Figure 12 1 Glitch Free clock multiplexer A 69 Page 7 of 69 ee Ref UoD Link User EADS E SpaceWire CODEC IP 2 4 paceWire ASTRIUM DUNDEE Issue 27 March 2009 User Manual Date Page 8 69 H Austrian Aerospace ll LIST OF TABLES Table 2 1 Applicable Renn En CET 10 Table 4 1 Directory descriptions ccccccccseeccesceceeeeceeeceeceucecaueesauesceeceueeceueesaeeesaeessueessusenseeeseeeseas 14 Table 4 2 RTL file descriptions
59. rough Reset Asynchronous Read Latency From Rising Edge of Read Clock 0 Consult Data Sheet tor Performance Resource Impact of each feature ay on as De Figure 9 1 ISE coregent settings for rxnchar resync ff vhd Page 58 of 69 ee Ref UoD Link User Vv Ss EADS gt SpaceWire CODEC IP 2 4 paceWire ASTRIUM DUNDEE Issue 27 March 2009 User Manual Date Page 59 69 H Austrian Aerospace 10 STATIC TIMING ANALYSIS 10 1 Clock constraint analysis Dependent on the interface configuration signals a number of different clocks can be generated by the UoD SpaceWire CODEC SYSCLK External Always present SYSCLK should be constrained to the desired system clock frequency of the internal control and status registers employed If CFG SYNCRDCLK is equal to 1 then SYSCLK should be constrained according to the guidelines provided in section 7 2 8 Receive buffer clock frequency RX CLK Internal Always present RX_CLK should be constrained to half the maximum bit rate received Section 10 2 discusses static timing analysis of RX_CLK SLOWCLK External The slow clock input should be constrained to 5SMHz when CFG DDROUT 1 or 10MHz when CFG DDROUT 0 RDCLK External RDCLK should be constrained according to the guidelines provided in section 7 2 8 Receive buffer clock frequency TXCLK External TXCLK should be constrained to the maximum bit rate when CFG DDROUT U or maximum bit rate divided
60. ry is initiated when the CODEC state machine moves to state ErrorReset after an error or if LINK DISABLE is asserted 7 5 1 Transmitter Error Recovery Transmitter error recovery is performed when the CODEC state machine moves from state Run to state ErrorReset Error recovery is performed as follows If the previous character read from the transmitter FIFO was not an end of packet marker then each consecutive character is read until an end of packet marker is encountered In this way the next character to be sent after a link disconnection is the header character of the next packet Transmitter error recovery does not affect link start up after an error 7 5 2 Transmitter Buffer Flushing The transmitter may hold more than one SpaceWire packet and it may be necessary to flush all packets from the transmitter buffer during operation or after error recovery The input signal FLUSH TX cause the transmitter error recovery module to continually read packets from the transmitter buffer until the signal is de asserted 7 5 3 Receiver Error Recovery Receiver error recovery is performed when the CODEC state machine moves from state Run or Connecting to state ErrorReset Error Recovery is performed as follows The error recovery module waits for space in the receiver FIFO to write an error end of packet character EEP If the receiver FIFO is full then link initialisation is stalled until the host reads at least nine data characters from the FIFO 8 da
61. signals The status bits are listed in Table 7 5 Type Description Sync to Clk Out SYSCLK SYSCLK SYSCLK Out SYSCLK STATUS 15 0 Out SpaceWire interface status signals All status signals are SYSCLK synchronous to CLK Out SYSCLK SYSCLK Out SYSCLK characters then requested STATUS 4 Out Transmitter credit error The transmitter has credit to send SYSCLK more than the allowed 56 data characters Out Receiver got FCT Remains asserted after first FCT SYSCLK Receiver got N chars Remains asserted after first N Char SYSCLK STATUS 12 Out Receiver got Timecodes Remains asserted after first SYSCLK Timecode Transmitter has credit to send one more data character SYSCLK STATUS 14 Out N char sequence error N char received before link state is SYSCLK Run Out Timecode sequence error Timecode received before link SYSCLK STATUS 7 5 Out Interface state encoded into three bits 6 states SYSCLK Interface state machine is in the Run state SYSCLK ut Receiver got NULL Remains asserted after first NULL SYSCLK Page 50 of 69 ee Ref UoD Link User Vv d EADS E SpaceWire CODEC IP 2 4 paceWire ASTRIUM DUNDEE Issue 27 March 2009 User Manual Date Page 51 69 H Austrian Aerospace OT states Run mm Table 7 5 Status signals The state encoding used for STATUS 7 5 is shown in the following table Interface state STATUS 7 5 State Connecting 7 9 Error Recovery Error recove
62. t clock configuration Page 30 of 69 gemm Ref UoD Link User Vv A EADS z SpaceWire CODEC IP 2 4 ASTRIUM DUNDEE Issue 27 March 2009 User Manual Date Page 31 69 H Austrian Aerospace 6 5 9 Transmit bit clock configuration TXCLK DIV The TXCLK DIV configuration can be used when e An independent transmit clock is required asynchronous to SYSCLK e Internal variable data rate generation is required e Internal 10Mbits s data rate generation is required The block diagram shown in Figure 6 8 describes the TXCLK_DIV configuration When either the FSM SEL SLOW signal is asserted the link is not running or it is starting up then TXCLK is selected by the glitch free multiplexer When the link is running the internally generated XI DIV CLK clock is selected TXBITCLK Tx Encode CFG_SLOWRATE_TXCLK Divider mm Glitch Free Clock Multiplexer XENR XENF TT Figure 6 9 TXCLK DIV transmit clock configuration The variable data rate and the 10MHz default data rate are implemented using a programmable divider which enables a toggle flip flop When the SpaceWire CODEC is performing link start up FSM SEL SLOW the input CFG SLOWRATE TXCLK determines the frequency of TXBITCLK When link start up has been performed and a link connection has been established the input TXRATE determines the data rate When TXRATE is equal to zero maximum rate then XIMAX is asserted and TXCLK is selected by the glitch free clock multiplex
63. t on the configuration signals 6 5 Transmit bit clock The UoD SpaceWire CODEC can be configured to implement a number of transmission clocking schemes The valid transmitter bit clock configurations can be selected by the user via the package constant CFG BITCLK The valid configurations are listed in Table 6 2 e The transmit bit clock configuration determines the source or method used for the following e Baseline bit clock system clock or independent transmit clock e 10MHz default data signalling rate internally generated or input SLOWCLK e Variable data signalling rate not enabled clock enables or clock divider Page 21 of 69 gemm Ref UoD Link User Vv E Se EADS z SpaceWire CODEC IP 2 4 ASTRIUM DUNDEE Issue 27 March 2009 User Manual Date Page 22 69 Austrian Aerospace GFE ane Symbolic named input clock Default ENEE Variable data rate 0000 OF SE SES OOIT Gh 0100 4h SYS_EN Clock enable Clock enable 1000 Eh ege 1010 Ah ee TOTEN Table 6 2 CFG BITCLK options Note 1 The symbolic names are defined as VHDL constants in the package top spwrlink_pkg vhd Note 2 10MHz for single data rate or 5MHz for double data rate The following sub sections define the meaning of the configurations in Table 6 2 Note The following configurations reference the use a glitch free multiplexer to select between two asynchronous clocks Appendix I in section 12 details t
64. ta characters for one FCT and one data character for EEP The receiver credit counters are updated accordingly before the next link initialisation procedure Page 51 of 69 Ref UoD Link User VERSI Vv j EADS E SpaceWire CODEC IP 2 4 paceWire ASTRIUM DUNDEE Issue 27 March 2009 User Manual Date Page 52 69 H Austrian Aerospace Error Recovery signals are listed in table Table 7 6 Type Description Sync to Clk FLUSH TX In Cause the transmitter error recovery controller to continually flush SYSCLK the transmitter buffer read from the buffer when data available independent of the CODEC state Table 7 6 Error Recovery Signals Page 52 of 69 ee Ref UoD Link User Vv d EADS E SpaceWire CODEC IP 2 4 paceWire ASTRIUM DUNDEE Issue 27 March 2009 User Manual Date Page 53 69 H Austrian Aerospace 8 EXTERNAL INTERFACE 8 1 Data Strobe Encoding The UoD CODEC uses Data Strobe DS encoding as defined in the SpaceWire standard AD1 When transmitting DS encoding defines that the strobe signal keeps its value when data changes and strobe changes when data retains its value In this way the receiver can recover the transmitter clock by an exclusive or XOR operation between the data and strobe lines The recovered clock is half the rate of transmitted bit rate therefore rising and falling edges of the recovered clock are used to sample the data input The CODEC can encode the bit stream using singl
65. te AS SELA is HIGH when reset then CLKA will be enabled and it will take one and a half CLKB cycles until CLKB is disabled and a further one and a half clock cycles until CLKA is properly enabled Page 69 of 69
66. te to be generated by an internal clock enable generator This configuration can be used when e The number of clock nets available to the user is limited only one clock net is required for this transmission scheme e TXBITCLK is synchronous with SYSCLK Figure 6 5 shows the block diagram for SYS EN DOUT DOUT F SYSCLK Tx Encode SOUT E SOUT FE EN FSM SEL SLOW XENR TXRATE Geen a iz Enable Generator XENF iz CFG_SLOWRATE_TXCLK Figure 6 5 SYS EN transmit clock configuration When the internal state machine signal FSM SEL SLOW is asserted the input CFG SLOWRATE TXCLK determines the final data rate When FSM SEL SLOW is de asserted then TXRATE determines the final data rate The outputs XENR and XENF should be connected to the rising edge enable and falling edge enable of the transmit double data rate output register Note When DDR outputs are selected and CFG SLOWRATE TXCLK or TXRATE is an odd number the duty cycle on DOUT SOUT will not be 50 50 The worst case duty cycle when TXRATE or CFG SLOWRATE TX 1 will be 75 25 i e 15ns dns for 2 transitions at a 20 ns period This is still a valid configuration under the SpaceWire standard Page 27 of 69 gemm Ref UoD Link User Vv A EADS z SpaceWire CODEC IP 2 4 ASTRIUM DUNDEE Issue 27 March 2009 User Manual Date Page 28 69 H Austrian Aerospace 6 5 6 Transmit bit clock configuration TXCLK DEFAULT The TXCLK DEFAULT can be used when e An in
67. ted as the transmit bit clock FSM SEL_SLOW TXBITCLK Tx Encode SLOWCLK Glitch Free Clock Multiplexer XENR XENF Figure 6 7 TX SLOWCLK transmit clock configuration Page 29 of 69 ee Ref UoD Link User Vv d EADS E SpaceWire CODEC IP 2 4 paceWire ASTRIUM DUNDEE Issue 27 March 2009 User Manual Date Page 30 69 SH Austrian Aerospace 6 5 8 Transmit bit clock configuration TXCLK SLOWCLK DIV The TXCLK SLOWCLK DIV configuration can be used when e An independent transmit clock is required asynchronous to SYSCLK e Internal variable data rate generation is required e An independent 10 5MHz reference clock is required and available externally The variable data rate is implemented using a programmable divider which enables a toggle flip flop When the SpaceWire CODEC is performing link start up FSM SEL SLOW the input TXCLK is selected When link start up has been performed and a link connection has been established the input TXRATE determines the data rate When TXRATE is equal to zero maximum rate then XIMAX is asserted and TXCLK is selected by the glitch free clock multiplexer When TXRATE is not equal to zero the clock generator output XI CLK DIV is selected by the multiplexer FSM SEL_SLOW TXRATE Tx TXBITCLK Encode gt Glitch Free Clock Multiplexer SLOWCLK Glitch Free Clock Multiplexer XENR XENF Figure 6 8 TX SLOWCLK DIV transmi
68. ters are defined for each SpaceWire system Maximum data skew and jitter the system can tolerate Maximum strobe skew and jitter the system can tolerate Table 10 4 Skew Tolerance Maximums The calculation of the maximum data skew tolerance is depicted in Figure 10 7 The maximum data skew depends on the maximum time from Din to the data pin of the flip flop and the minimum time from the next strobe edge to the clock pin at the flip flop Din ldea si ege J Din at FF D E a Sin at FF CLK C X SS TMINSCLK Tmax_pskew Tsu Tho Figure 10 7 Data Skew Tolerance The parameter Tmax pskew s evaluated as the bit period plus the minimum strobe clock delay minus the maximum time from Din to the data pin of the flip flop and the setup and hold time IMAX_psKEW lur Tuinscik 7 Imaxp Lsu IHD 8 The calculation of the maximum strobe skew tolerance is depicted in Figure 10 7 Page 64 of 69 gemm Ref UoD Link User V 4 EADS z SpaceWire CODEC IP 2 4 ASTRIUM DUNDEE Issue 27 March 2009 User Manual Date Page 65 69 Austrian Aerospace Din Ideal Sin Ideal Din at FF D Sin at FF CLK Figure 10 8 Maximum Strobe Skew The maximum strobe skew parameter Tmax sskew IS evaluated as shown below Imax sskEw lur T1minD IMaxscix Lsu Tup 9 10 3 Generic Transmitter Double Data Rate Outputs The generic double data rate output is implemented as a multiplexer which selects betwee
69. the other output is changing as shown in the timing diagram below EN_RISE CE MUX_SEL EN_FALL DSJOUT DSJOUT F TXBITCLK Fiqure 10 10 DDR output multiplexer select The timing diagram below shows the operation of the DDR multiplexer TXBITCLK MUX_SEL eo L RA RB DOUT F yY DOUT L RA A FA A RB A FB Figure 10 11 DDR output multiplexer timing specification Typical ways of constraining the paths to ensure that no glitches can occur include e Timing delay constraints on the nets shown e Area constraints to pack the outputs into a small area and therefore minimise and equalise net delays Page 66 of 69 ee Ref UoD Link User Vv d EADS E SpaceWire CODEC IP 2 4 paceWire ASTRIUM DUNDEE Issue 27 March 2009 User Manual Date Page 67 69 H Austrian Aerospace 10 3 2 Generic DDR Method Two The second DDR method uses the combinational output from method one see section 10 3 1 aboce but adds an extra register to the output stage which is clocked by a clock which is twice the frequency of the transmitter clock In this instance a DLL or PLL can be used to derive the two clocks in the same application This method requires no delay matching on the outputs of the transmitter and the only requirement is that the output O meets the setup time for the doubled clock The scheme is shown in Figure 10 12 Spwr_Link_Interface TX SHIFT CLK 100MHz 1 DLL PLL 2
70. the skew and jitter on data and strobe Jitter is equal for data and strobe therefore it only has one timing parameter The table below defines the extra timing parameters Ty Unit interval or bit period Strobe skew Data and strobe jitter Table 10 3 Extra Clock Recovery Timing Parameters 10 2 2 Data Setup Check The following timing diagram defines the correct placement for data at the D pin of the capturing flip flop Page 61 of 69 ee Ref UoD Link User ops P i p SpaceWire CODEC IP ASTRIUM DUNDEE Issue 27 March 2009 User Manual Date Page 62 69 Austrian Aerospace Edge 1 Edge 2 Bit Period DIN RXCLK at FF Edge 2 Valid Setup Time Figure 10 2 Data Setup Time Timing Diagram In Figure 10 2 the maximum delay from DIN to the data pin at the flip flop must be less than the time from DIN edge 2 to the clock pin at the flip flop for edge 2 minus the setup time of the flip flop as shown below ImAxD lt TMiNDCLK Lsu eq1 The bit period is the bit period minus two times data jitter budget jitter reduces the bit period The clock edge generated by edge 1 must not capture the data at edge 2 therefore the clock delay must not be greater than the data delay plus the bit period minus the data jitter as shown below TmaxpoLk lt Turn Tsu Tur 2 x TiiTTER eq2 i e the clock delay should be less than the data delay plus the bit period An example violating this rule is shown belo
71. w DIN DIN at D pin of FF DIN at CLK pin of FF Figure 10 3 Large clock delay setup time violation Note Usually the clock delay will be comparable with the data delay therefore more care needs to be taken with the first data setup time rule Also for skew tolerance it is preferable to keep the data and clock edges relatively close together 10 2 3 Strobe Setup Check An edge on strobe captures the correct DIN value only if DIN satisfies the setup and hold time of the clock generated by strobe changes When there is no skew on the cable then the valid strobe clock delay is defined as the bit period plus the DIN data delay to the D pin of the flip flop plus the setup and hold time of the flip flop as below Page 62 of 69 4 gr Ref UoD Link User EADS ba SpaceWire CODEC IP 2 4 ASTRIUM DUNDEE Issue 27 March 2009 User Manual Date Page 63 69 Austrian Aerospace ImaxscLk 1pu lt lur T1MIND eg 3 This relationship can be seen in Figure 10 4 Sin Din Din at D pin of FF Latest Sin at CLK pin of FF Invalid Figure 10 4 Latest Strobe Setup Time When no Skew When data or strobe are skewed and jitter is added then the bit period Ty is adjusted accordingly When data is skewed the period is larger therefore Tpskew is added to Ty When strobe is skewed the bit period Ty is smaller therefore Tssxew is subtracted from Ty Therefore eq 3 becomes Tu axsciK Tun lt Tur Tpskew Tssxew 2X TyrTtE
72. which will give invalid timeout periods for the system clock 6 13 Timing cycle settings The configuration signals TIMING 6 4 TIMING 12 8 and TIMING 850ns are used to select the number of 10MHz clock cycles which are counted for the 6 4us 12 8us and 850 ns timeouts The default values are set to 64 and 128 respectively The values should be set as follows 6 411 TIMING 6 4 _ SlowClockRate Equation 6 2 Deriving TIMING 6 4 12 841 TIMING 12 Z o SlowClockRate Equation 6 3 Deriving TIMING 12 8 Example System Clock Frequency 25MHz 40 ns period 30M Hz or 10M Hz 8 C FG SLOW RAT E SY SCLK 10 MHz clock enable period is 80 ns TIMING 6 4 l4 8Ons TIMING 12 8 294 60 Ons S50ns e NS TIMING _ 850ns When the configuration bit clock is SYS SLOWCLK SYS SLOWCLK DIV TXCLK SLOWCLK or TXCLK SLOWCLK DIV then the TIMING 6 4 and TIMING 12 8 settings should be adjusted to allow for the synchronisation time to load the initialisation state machine counter The additional time to load the counter as shown in Figure 6 13 is calculated as 1 system clock cycle plus 3 reference clock cycles Page 39 of 69 ee Ref UoD Link User Kps E 7 A SpaceWire CODEC IP ASTRIUM DUNDEE Issue 27 March 2009 User Manual Date Page 40 69 Austrian Aerospace State ErrorReset X ErrorWait Load Ack SSS Fo Dead Counter Starts Couting Time Figure 6 13 Additional time added w

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