PLL Synthesizer User`s Manual
Contents
1. mount this module on chassis firmly Or installing heat sink of heat resistance less than 5 0 degree C W is recommended Refer to Page 5 outer dimensions about mounting holes It will be more effective if silicon compound is put on the surface of the mounting section of the module 7 Control by SPI serial data 1 SPI specification Max clock speed 20MHz Data bits width 32bits Frequency data bits Logic level 3 3V CMOS 2 Timing characteristic CS ti 2 CLK so eeo e Timing characteristic Parameter Condition Min Unit t1 CLK set up time to CS 50 ns t2 CLK period 50 ns t3 SDI set up time to CLK rise edge 10 ns t4 SDI hold time to CLK rise edge 10 ns t5 CS set up time to CLK rise edge 50 15 3 Command Definitions 32 bits frequency data is transferred by serial data Bit definition is as follows Bit Name Bit Remarks width Bit 31 0 Frequency 32 bits Frequency data in 1 KHz resolution in binary 0 Digital Signal Technology For example when you set 4 2GHz frequency data of Hz unit must be converted to binary data Therefore 4 2GHz is converted to FAbGEAO0 hex 32 bits binary data 8 Control by asynchronous serial data How to set from a PC serial port RS 232C is explained below 8 1 Communication specification opeed 9600bps Data bits 8 bits Stop bits 1 bit Parity none Flow control none Logic level 3 3V CMOS 8 2 Interface Option USB inter2. 0 inspection shall be performed for the electrical specification in 2 10 Warranty If any defect is found due to the manufacturer s improper production or design within one year after delivery a repair or a replacement shall be performed under the manufacturer s responsibility 11 Others 11 1 This product which employs a CMOS device may be easily damaged by static electricity Digital Signal Technology Inc assumed no liability for damages that may occur as the result of handling by users even though the above warranty period 11 2 Do not supply over voltage power supply as the module may be damaged Digital Signal Technology assumes liability for the damages that may Occur as a result of handling by users even though within the warranty period Descriptions of this manual are subject to change without notice No portion of this manual can be reproduced without the permission of Digital Signal Technology Digital Signal Technology assumed no liability for damages that may occur as a result of handling by users The contents of this manual do not apply to the warranty in executing an industrial property or other rights nor permission for the right of execution Digital Signal Technology assumes no responsibility for the third party s industrial property occurred from using the circuits described in this manual Mz Digital Signal Technology
3. PLL Synthesizer User s Manual DPL 4 2GF DPL 4 2GFH Digital Signal Technology Inc 2 9 10 Kitahara Asaka Saitama 351 0036 Japan TEL 81 48 470 7030 FAX 81 48 470 7022 URL http www dst co jp ERI Digital Signal Technology ZA O Contents General Description 3 Specification ee eee 3 Outer Dimensions e 5 Circuit Configuration D e llIl 7 Connector Interface 7 Thermal Consideration 8 Control by SPI 8 Control by Asynchronous Serial data 9 Shipping Inspection 10 222 222 10 Olles 10 er 2 Digital Signal Technology 1 General Description DPL 4 2GF is a frequency synthesizer which can generate any frequency from 50MHz to 4 2GHz utilizing PLL technique Phase Locked Loop in 1Hz step It can be used as a clock source or local oscillator for any application because of its excellent phase noise and low spurious level When a sine wave is needed put a low pass filter at the outside of the module to remove the harmonics 2 Specification Power Supply Current Frequency Range Frequency Resolution Output Level Output Impedance Spurious Harmonics Phase Noise 4 GHz typical Internal Reference Clock Accuracy External Re
4. face USBIF 01 is available as an option for DPL 4 2GF 8 3 Command definitions Character strings marked as double quotation marks means ASCII code CR and LF are control codes which means OD hex and OA hex If any invalid command is entered INVALID DATA CR LF is returned All characters used for input should be uppercase When a normal command is entered is returned Also the entered data is echoed back 6 3 1 Frequency setting command For frequency setting the input can be made in MHz KHz and Hz unit 1 Setting in GHz For setting 4GHz input the following data 4G CR All the data below 100MHz is set to 0 In case of setting 4 2GHz set in MHz like below because a decimal point cannot be used 2 Setting in MHz For setting 2400MHZ input the following data 2400M CR All the data below 100KHz is set to O 3 Setting in KHz For setting 22400002KHZz input the following data 2400002K CR Or 72400002 0 Digital Signal Technology 8 3 2 READ Command By entering READ CR the currently set frequency is output The response is as follows ffffffffKHz CR LF shows the frequency of currently outputting in KHz unit 8 3 3 SAVE Command By entering the current frequency can be memorized into EEPROM When the power is on next time the stored data can be output If any invalid command is entered ERROR CR UET is returned 9 Shipping Inspection 10
5. ference Clock and Level External Clock Input Impedance Lock Time Operating Temperature Range Outer Dimensions Weight Interface 6V 5 lt 00MA 50MHz 4 2GHz 1Hz step gt 10dBm 500 lt 60dBc lt 8dBc 80dBc Hz 100Hz 97dBc Hz 1kHz 102dBc Hz 10kHz 105dBc Hz 100kHz 126dBc Hz 1MHz lt 2ppm 0 50 degree 10MHz 6dBm 6dBm High Impedance gt 1kQ max 5 1 SPI from SPI STRB rise edge to detection of PLL LD 2 SCI from receipt of CR to detection of PLL LD O 50 degree C In case of being installed with Thermal resistance 5 0 degree C W heat sink 50mmx60mmx12 5mm about 80gs module about 160gs including Heat Sink 1 Asynchronous Serial Communication 9600bps 8 bit 1 stop bit non parity 3 3V CMOS level 2 serial communication bytes data 3 3V CMOS level Digital Signal Technology Phase Noise 20 40 60 80 100 eb Phase Noise dBc Hz 140 SO 180 10 100 1000 10000 100000 1000000 10000000 Offset Frequenoy Hz Digital Signal Technology 3 Outer Dimensions 1 DPL 4 2GF Feedthrough Capacitor Interface Connector Supply 6V lOpin LOCK LED 12 5 i i Mounting Hole 4 M2 6 Depth 4 Omm eie Mount Ing Hole 4 22 5 Through Hole NOTES Dimensions are in mm edges Digital Signal Technology 2 DPL 4 2GFH NOTES Dimensions are n mm b Digital Signal Technology 4 C
6. ircuit Configuration INT_FREQ_ADJ 10MHZ VCXO O 100MHz REF IN EXT_10MHz LOCK UNLOCK PLL2 250MHz LOCK UNLOCK RF OUT 50 4200MHz PLL3 50 4200MHz BUER LOCK UNLOCK OUT C gt LED um SEG Sol LOCK UNLOCK MPU 6V C GND CPLD 5 Connector Interface 1 External 10MHz Input SMA J 2 Output Supply Pin SMA J 500 3 Supply Pin Feedthrough Capacitor Supply 6V 4 Internal Freq Adjust Frequency adjustment for internal reference clock 5 Connector 2 54mm 5x2 10pin Connector for Flat Cable Part number Pin Assignment HIROSE HIFSFC 10PA 2 54DSA Pin number Name Description 1 GND oignal GND 2 GND oignal GND 3 Power Supply Power Input 6V Connected to Feedthrough capacitor internally 4 INT EXT Mode selection pin External or Internal reference clock HIGH Internal LOW External Internally pulled up 5 LOCK PLL lock status output HIGH lock LOW unlock 3 3V CMOS level 6 ICS Chip select under SPI mode Input low active 3 3V CMOS Internally pulled up 7 RXD Asynchronous serial RX data 3 3V CMOS level Internally pulled up 8 SDI Serial data input under SPI mode 3 3V CMOS level 9 TXD Asynchronous serial TX data 3 3V CMOS level 10 CLK Serial input under SPI mode 3 3V CMOS level Eu Digital Signal Technology 6 Thermal Consideration Power dissipation of this module is about 4 2 watts so in order to flow heat
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