FS4435 DP State Analysis Preprocessor User Manual
Contents
1. 65535 65537 65538 SC 65539 E la xl le xl I Dummy Data Dummy Data Dummy Data Dummy Data Dummy Data Dummy Data ete dii ecl 200000000000000000000000o0000 2 000000Pooooooooooooooooooo Add Measurement Drag and Drop n Period a Frequency en Positive m Hegative FL Duty Cycle FL Duty Cycle Statistics 41 Positive uy Negative Pulse Width Pulse Width jz Channel to patte P Enable All Measurements Trigger For Help press F1 The FS4435 Disassemblers will perform the following functions Decode all DP or AUX protocol data Color code the transaction type The colors used by the software are as follows o Main Stream Attributes Green o Secondary Data Packets Blue o All other states White o AuxPort Source initiated Green In order for the FS4435 Main Link DP Disassembler to decode the pixel data they must be set to the proper Pixel Width which is found in the Properties tab of it s column heading DP Groups Besides de serializing the data stream for the logic analyzer the FS4435 generates a number of identification and control bits that are used by the Protocol Disassembler and logic analyzer These are also available to the user and are described below These are the same for any DP link AUX port is defined separately Field Bits Definition Storage Flag 1 1 Store this state 0 Discar2. FS44xx Probe Manager application and USB drivers on a CD A USB cable is provided for connecting the FS4435 preprocessor to the Windows based machine that the Probe Manager is loaded on e This User Manual and Quick Start sheet The minimum equipment required for analysis of a DP consists of the following equipment e Tektronix TLA analysis frame with the TLA7AA4 modules One is required for each DP and AUX link e 4FS1055 cables for connection of the Preprocessor to the TLA e ADP target bus It is STRONGLY recommended that the user review and apply the probing guidelines described in the application note DisplayPort Probing when planning for use of the preprocessor on any target system Probing System Overview The architecture of the FS4435 preprocessor and the design of the DP link to be probed should both be thoroughly understood before attempting to use the probe The following is a general outline of the steps to be taken when probing a new link Read the following pages for more specific information The FS4435 preprocessor requires the understanding and correct set up of 4 different systems before a trace should be taken 1 Probe Manager software This software is identified as FS44xx Probe Mgrr exe and is on the CD that comes with the FS4435 Additionally there is a folder within this CD that contains all the necessary USB drivers that your Windows system requires When Windows searches for the USB drivers to
3. Ctrl P E amp Compact Disc D Recent System Files Sy Removable Disk E MyN raed p 9 Share on Snap180542 Z Recent LA Module Fies GE My Network Places Recent Trigger Files Ext The first Trigger is designed to allow the user to trigger on a particular pixel value in a horizontal line that is not the first line of the Frame Note that these Triggers require that Active Video Stuff Data Symbols are being filtered The Trigger is shown below with some detail on those settings which will need adjustment based on the user s needs Overview E Run g _ State 2 3 ia a e mq eo z e 3 e Lal Jal a r g 5 T v UR Group Storage 1 Store Sample Group E ventCode Vertical Blanking BE Group EventCode Vertical Blanking BE BoTo1 State 2 Look for the statt of a ine Group EventCode Horizontal Blanking BE Then Inc Courter 1 And Go To 3 4 Group E ventCode l Honzontal Blanking BE Then GoTo2 Counter equals ine number 1 Counter lt 1 Check for desred color at desired location if nol found go to next video fieme Counta 2 gt 560 And Group Storage 1 And Group Pixel Recognizer 1 Trigger All Modules Counta 2 lt 560 And Group Storage 1 Inc Counter 2 And Go To 4 Channel FktRieceg 0 Low And Group Storage 1 GoTc1 x Reset Counter 1 And Reset Counter 2 And Go To 2 This is the simple pixel Trigger for use when the desired
4. Decoded 8b value Clock is on A1 bit 16 and B1 bit 16 Pod A4 B4 A3 B3 A1 B1 2 0 16 15 14 11 10 7 4 0 16 14 13 11 4 1 0 15 10 Event Code symbol definitions Event Code Symbol Bit 7 Bit 6 Bit Bit Bit Bit Bit 1 Bit 0 5 4 3 2 Err bits Err bits Video Field FO Pixel 1 0 0 0 1 X 0 0 FO Filler including FS FE 1 0 0 1 0 X 0 Mismatch BS 1 X 0 1 1 X 0 Mismatch SR 1 X 1 0 0 X 0 Mismatch Content Protection BS 1 X 1 0 1 X 0 Mismatch Content Protection SR 1 X 1 1 0 X 0 Mismatch F1 Pixel 1 1 0 0 1 X 0 0 F1 Filler including FS FE 1 1 0 1 0 X 0 Mismatch Blanking Horizontal Horizontal Blanking BE 0 0 0 0 0 1 Missed Mismatch SR Horizontal Blanking VBID 0 0 0 0 1 0 0 Mismatch Horizontal Blanking MVID 0 0 0 0 1 1 V err Mismatch Horizontal Blanking MAUD 0 0 0 1 0 0 A err Mismatch SR 0 X 0 1 0 1 0 Mismatch Horizontal Blanking Dummy 0 0 0 1 1 0 0 0 Horizontal Blanking Audio 0 0 1 0 0 0 0 0 Stream Horizontal Blanking Audio TS 0 0 1 0 0 1 0 0 Horizontal Blanking Reserved 0 0 1 0 1 0 0 0 Horizontal Blanking 0 0 1 0 1 1 0 0 Extension Horizontal Blanking Info 0 0 1 1 0 0 0 0 Frame Blanking Vertical Vertical Blanking BE 0 1 0 0 0 1 Missed Mismatch SR Vertical Blanking VBID 0 1 0 0 1 0 0 Mismatch Vertical Blanking MVID 0 1 0 0 1 1 V err Mismatch Vertical Blanking MAUD 0 1 0 1 0 0 A err Mismatch SR 0 X 0 1 0 1 0 Mismatch Vertical Blank
5. Run time preprocessor status DP Probe Config Previous DP Probe Config X1 X2 X4 Dialog Note there is no Config required for Aux or HPD signals Dynamic Lane width tracking The functions provided on these forms include Selection of the Probing Cable type Link width and pad arrangement referring to the arrangement of lanes on the mid bus probe pads see the PCI Express Probing Design Guide for the FS440X for more specific information The Pad Assignment graphic shows the assignment of logical lanes as a result of user selections and also represents the physical layout of mid bus pads The FS4435 processes channels from the left column in link processor A and from the right column in link processor B Next or Previous buttons scroll through the various types of currently supported pad assignments Lane Inversion can be selected on an individual channel basis by clicking the INV button associated with each lane While the preprocessor is stopped signal activity indicators are provided on each channel Signal presence is indicated by an up down arrow symbol and a lack of signal presence is indicated by a flat horizontal line symbol Selection of Lane Reversal on each link Selection of Data Descrambling on each link Hot Plug Cable If the HPD cable from the probe is not connected to the target uncheck this box Selection of Toggle mode When activated the preprocessor output signals to the logic analyz
6. and remove any adapter cables that may be attached to the module cables When probing a single direction of a x1 x2 or x4 link the FS4435 drives 4 pods of signals 2 FS1055 cables to the logic analyzer It is important before you load a system file you initiate a self test on all your modules installed in your logic analyzer to insure all modules are working properly Loading System files From the system window of the TLA application select a logic analyzer module After selecting the module in the System window either right click the mouse and select Load Support Package or go the File gt Load Support Package After clicking Load Support Package a list of installed support packages will appear Select the support package that matches the desired analysis requirements The dis assembler will load along with the system file If you are analyzing more than 1 link simply choose another analyzer module from the system window and select Load Support Package to load the second module The analyzers supported by the FS4435 system files are theTLA7AA4 cards DP x1 x2 x4 DP link analysis Requires 2 FS1055 cables and 68 logic analysis channels AUX AUX analysis Requires 2 FS1055 cables and 68 logic analysis channels Offline Analysis uso BOSS BA Suma ide Data that is saved as a tla file can be imported into the TLA7xxx environment for analysis You can do offline analysis on a PC if you have the TLA7xxx operating
7. date listing please see http www futureplus com contact html I Limitation of Warranty Exclusive Remedies Assistance Product Warranty This FuturePlus Systems product has a warranty against defects in material and workmanship for a period of 1 year from the date of shipment During the warranty period FuturePlus Systems will at its option either replace or repair products proven to be defective For warranty service or repair this product must be returned to the factory Due to the complex nature of the FS4435 and the wide variety of customer target implementations the FS4435 has a 30 day acceptance period by the customer from the date of receipt If the customer does not contact FuturePlus Systems within 30 days of the receipt of the product it will be said that the product has been accepted by the customer If the customer is not satisfied with the FS4435 they may return the FS4435 within 30 days for a refund For products returned to FuturePlus Systems for warranty service the Buyer shall prepay shipping charges to FuturePlus Systems and FuturePlus Systems shall pay shipping charges to return the product to the Buyer However the Buyer shall pay all shipping charges duties and taxes for products returned to FuturePlus Systems from another country FuturePlus Systems warrants that its software and hardware designated by FuturePlus Systems for use with an instrument will execute its programming instructions when properl
8. on the desktop Follow the directions that follow including agreeing to the license terms once the software installation is complete click on finish To start the program manager simply double click its desktop icon The Probe Manager application detects all FS44xx probes that are connected to the USB bus and allows the user to select which preprocessor will be controlled by the current instance of the Probe Manager application from the initial screen as seen below FS44xx Probe List ManufacturerFPSystems Description F 4436 CAAOO00N1M1 SN Intel DP 1 Y Qu The initial screen is followed by the Protocol Selection screen in which the user selects a protocol to configure the FS4435 Preprocessor The FS4435 has choices for DP and raw 10b decode Protocol Selection Once the protocol has been selected the application displays the Main dialog as seen below WI DP Probe Mgr SN Intel DP 1 az File Edit Run Stop Upgrade Help Bi n Probe Config Packet Recognizers Filters Log Entries Probe is ready to be configured The user configures and controls the preprocessor from the main form The form is composed of a menu bar a tool bar and a status message bar The menu bar provides options that allow the user to configure and run the probe The tool bar provides options to configure the preprocessor and the status bar displays the probes current status and or any errors that may have been encountered Error messages displ
9. the very first sample pu If Group EventCode FO Pixel And Group LaneQ 10Bits 000 Then Trigger Else If Group EventCode FO Pixel And Group Lane1_10Bits 000 Then Trigger Else If Group EventCode FO Pizel And Group Lane2_10Bits 000 h Then Trigger MJ Else If Group EventCode F Pixel And Group Lane3_10Bits 000 Then Trigger For Help press F1 Tektronix Restart de 3j EE S SH E ra risgerpisplay DP Probe Mor sv 2906105 SOMES BS 412m Log File Log File Once started logging continues even if the preprocessor is stopped and started or if the log window is closed and re opened The log file will not repeat an error that repeats itself constantly Once a preprocessor has been stopped the log entries can be written to a file of the user s choice by clicking the Write Log File button State Analysis This chapter explains how to use the FS4435 to perform state analysis From the system window of the TLA application select a logic analyzer module After selecting the module in the System window either right click the mouse and select Load Support Package or go the File gt Load Support Package After clicking Load Support Package a list of installed support packages will appear Select the support package that matches the desired analysis requirements The dis assembler will load along wit
10. 0 26 23 no 21 0 5c 26 23 o0 21 0 65544 5C 80 80 no 00 0 aso 65545 5C 88 06 oo oo 0 oss 5c 0 88 06 00 oo 0 5c 0 88 06 00 no 0 5c 0 88 De oo oo 0 65546 5C 1 FD FD FD FD 0 1FD 65547 58 Dummy Data 0 oo oo o0 o0 000 65548 58 Dummy Data 00 oo no 00 0 0o00 65549 58 Dummy Data 0 o0 oo o0 00 0 ooo 65550 58 Dummy Data 00 oo oo 00 ooo 65551 58 Dummy Data 0 o0 oo oo o0 000 65552 58 Dummy Data 0 oo oo 00 oo 0 000 pr lre Peet tobe an an an 6 nan x 4 gt Add Measurement Drag and Drop H ir Period ar Frequency e en Positive rm Negative Duty Cycle FL Duty Cycle 1 Positive ir Negative 5 Pulse Width Pulse Width Channel to TEM g Enable All Disable All Delete All For Help press F1 Tektronix The following is an example listing screen showing the protocol decode provided by the Disassembler for AuxPort 4 Aux Listing S Fie Edit view Data System Tools Window Help T activity AJAJ xaa Gal i Search 130us 342 00103 TRAINING LANE 3 SET Training Patt 1 Volt swing level O Max Swing Reached 1 Training Patt 2 with Pre emphasis level 3 Max Pre emphasis Reached 1 00 375 00 750 XN N x LaneO cR Done 0 LaneO Channel EQ Done LaneO Symbol locked Lanel CR Done 0 Lanel Channel EQ Done Lanel LANE 2 AND 3 STATUS 00 000 Lane2 CR Done 0 Lane Channel EQ Done Lane2 Symbol locked Lane3 CR Done 0 Lane
11. 040 Installing your The following outlines the software installation procedure when using the preprocessor for the first time Please do not attach the preprocessor to the analyzer or computer that CIT for the First will be controlling the preprocessor until told to do so ime 1 Place the software CD that came with the product into the logic analyzer or computer that you will be installing the software on In the case of a machine that does not have a CD drive the machine will either have to be put ona network and the files loaded remotely or the CD files can be transferred from a USB drive 2 Navigate to the installation CD using Windows explorer and click on the following files Follow the instructions on the screen to install e FS1163 AUX exe Protocol Dis assembler e FS44xx Probe Mgr exe 3 Once all the above files have been installed connect the FS4435 to the analyzer computer via the USB port Power on the FS4435 probe 4 The found new hardware wizard should appear the first time the preprocessor is attached and powered up Select No not this time when it asks if the computer can go to Windows update to search for the software Then select Next 5 On the next screen select the Advanced option not the Recommended to select from a specific list or location Select Next 6 Select the CD ROM drive to load the driver from you do not have to select a specific directory Select Next 7 There may be a warning th
12. 3 cu 15 Done 0 Lane3 Symbol locked onu LANE ALIGN STATUS UPDATED 2 X 00110 CT nterlane align done 01111 cc 01111 ec Downstream port status changed Link status updated EEk SINK_STATUS H Mm a pE 99 875 us 01111 Receive Port 1 status Sink out of sync 3 349 00102 350 0010 RAININ A F O010 P d 200 12 00102 22 Training Patt Sete Training pattern 2 2 00102 22 Link Qual Patt Set pattern not transmitted Ls 00102 22 Recovered clock out enable Disabled mi 00102 22 Scrambling Disable Scrambler disabled 00102 22 Symbol error cnt sel Di llegal Plugged x00 125 us 2 2 00102 3c TRAINING LANE O SET 2 00110 1 Plugged 00 125 us 00102 3c Training Patt 1 Volt swing level 0 2 00102 3c Max Swing Reached 1 2 00102 3c Training Patt 2 with Pre emphasis level 3 2 00102 3 Max Pre emphasis Reached 1 2 00102 3c TRAINING LANE 1 SET 00111 1 d 00 000 us 00102 3c Training Patt 1 Volt swing level 0 00102 3c Max Swing Reached 1 00102 3c Training Patt 2 with Pre emphasis level 3 00102 3c Max Pre emphasis Reached 1 00102 3c TRAINING LANE 2 SET 01000 1 Plugged 99 875 us 00102 3c Training Patt 1 Volt swing level O 00102 3c Max Swing Reached 1 00102 3c Training Patt 2 with Pre emphasis level 3 00102 3c Max Pre emphasis Reached 1 00102 3c TRAINING LANE 3 SET J 00102 3c Training Patt 1 Volt swing level
13. 5 0 A1 15 12 Lane 3 Disparity Error 1 17 Lane 3 data has incorrect 8b10b disparity A1 11 Lane 3 Invalid Decode Error 1 1 7 Lane 3 data is not a valid 8b10b code A1 10 Lane3 10 Physical Lane 3 Data 10 bit encoded A1 9 0 Clock is inputted to CK3 FPGA Upgrade The FS4435 Probe Manager has the ability to reprogram any of the2 firmware program locations in the probe If a FS4435 probe firmware upgrade is required a new file will be provided by FuturePlus Systems Copy the file on the hard drive of the PC that hosts the FS4435 Probe Manager Click on the Upgrade button on the Probe Manager and then browse to the location where the firmware upgrade was stored Il DP Probe Mgr SN DP 6 File Edit Run Stop RES E FS44xx FPGA Update File Name CATEMP FPGA DP_FDI DP_FPGA6B_M bit When the upgrade process is complete the Probe Manager will remind the user to reboot the FS4435 probe and the Probe Manager software m DP Probe Mgr SN DP 6 Flash successfully programmed Cycle Power for newly written flash partition to take effect General Information Characteristics Standards Supported Power Requirements Logic Analyzer Required Number of Probes Used Environmental Temperature Altitude Humidity Testing and Troubleshooting Servicing This chapter provides additional reference information including the characteristics and signal connections for the FS4435 probe The following operating charac
14. FuturePlus Systems Corporation FS4435 DP State Analysis Preprocessor User Manual For use with Tektronix Logic Analyzers Revision 1 2 Copyright 2009 FuturePlus Systems Corporation FuturePlus is a trademark of FuturePlus Systems Corporation Howto reach istic a a ATS doo Pede oda 4 Product Warranty uso oap edo SE ORE AALA Ns 5 Limitation Of Warranty eee eese eo ese eene eo eva eo eo estns eEa e oen Eu baee a aeo eee V en Ee Een Ceo ee RUE 5 Excl sive Remedies erre eerte ex E d aS X Ue eee a eei e 5 EC M 5 Introduction m 6 How to Use This Manual eere eroe top ern oou Ee aerae tea ere eate eee o toss oaa ions 6 Definiti nS ossee e M 6 Analyzing the DP BUS aee n ons ho Pa sib dense ms cin aa avon to RR pq Z Accessories Supplied eee ee ceres ee ee ee stesse seen sete testate t eeeP ee ea sese eas tete sesso ee eaas 7 Minimum Equipment Required 4 e eee ecce eee ee ee eee ee ee te seen nest en setate seta aset eaae 7 Probing System Overview wisicsessisiversssvvevsssbevsessdcqecsssseensesasescesvadensenedeensssvonssvsnsben 8 BrOnt i2 LT 10 FS4435 Probing Cables sccssicssscssssecssssesssonsscdescscstsesontedensessincs taro r oen eset ae sena Morena ine oas 11 Side band cables tat eoe toe c maim bre Etat 11 Flying Lead Probing FS1036 cabl
15. O w uals o no n n 01001 1 PTugged 400 125 us o rf DP Probe Mgr 5N 2906105 Symbol files The Support package includes symbol files for the following e DP lane data e Event Codes e AUX channel Commands e 10b decode These are separate files that can be loaded to provide more information in the lister or for use in defining triggers Triggering The system files allows logic analyzer based trigger set ups that utilize the pre defined symbols described earlier ATLA Trigger FDI E 18 x H Fie Edit View System Tools Window Help lal xl CE EasyTrigger Power rigge Ji overview Stoxage If Group Storage 1 Run Then Store Sample State 1 Trigger on the very first sample If Group LaneO_10Bits BS Then Trigger Clause Definition FDI State 1 1 If Group LaneO 10Bit 7 E 7 Group Radix Symbolic Symbol File Symbol File c progr lane_decode tsf Y ESTEE press F1 Event Name optional Tektronix istae 4 e y A oo Gysharet on snap180542 C E rLA rrigger rDr GyRemovable Disk E EEG sem e Remember to always use conditional storage This is because the preprocessor clock is free running and the Storage bit is used to qualify what is sent to the logic analyzer modules There is a separate storage bit for HPD HPD Valid e The Event Code field makes it easy to trigger on particular packet typ
16. able that provides detail on how to solder the flex pcb to your board Refer to this document 2 Polarity matters Makes sure you know how the and sides of the signal are connected Adjustment to polarity can be made in the Probe manager FS1036 Flying Lead flex tips only Pin Il Not the sideband signals pni Ground Pin Il Ground Pin The FS1036 flying lead cable has 8 pairs of channel connectors which are labeled A G for up to 4 channels of a link and B H which can be used for another link Make the appropriate cable and channel selections in the Probe Manager before taking any measurements FS1040 DP interposer The FS1040 DisplayPort interposer is designed to plug between the motherboard and the DisplayPort cable from the monitor The FS1040 then provides the high speed serial signals to the preprocessor as well as the Aux channel and HPD signal connections The cable provides a complete pass thru of all 20 signals specified for the DP cable in section 4 2 of the v1 1a specification There is no reordering of the lane bits The interposer has been qualified at 2 7GBps The FS1040 is connected to the FS443x probe in the same manner as the other probe cable It can be selected on the Probe Manager Config page Aux and HPD signals can be attached to the 3 pin headers on the FS1040 Polarity of the connection is important so match the pin 1 labels on the sideband cables to the labeled pins on the FS1
17. at comes up about Windows XP compatibility ignore this warning and continue with installation 8 Click Finish to complete the installation Once all the previous steps have completed all necessary software as well as USB drivers will be installed This procedure only needs to be done on initial install You may now go to the desktop and click on the Probe manager icon to start the probe manager If you are installing on a PC to only control the FS4435 then you can omit the installation of the FS1163 AUX exe but you must follow the rest of the steps For instructions on loading system files please refer to the section on loading system files later in this manual The FuturePlus Systems FS1055 cable is designed to attach to the 90 pin connectors Connecting the on the FS4435 and to the TLA7AA connector on the other end Each FS1055 connects Tektronix logic 2 FS4435 90 pin pods 17 channels each to 1 TLA module input 34 channels analyzer to the FS4435 The table below explains how to connect TLA7AA4 card to the FS4435 Logic Analyzer FS4435 Comment DP Master 1 A3 A2 A1 Clock D3 D2 A2 270 Mhz at 2 7Gbs Master 1 A1 AO A3 160 MHz at 1 62Gbs D1 DO A4 AUX Master 2 A3 A2 B1 Clock D3 D2 B2 A1 AO B3 D1 DO B4 10b Link A and B Master C3 C2 A1 Clock C1 CO A2 A1 AO A3 D1 DO A4 Master A3 A2 B1 D3 D2 B2 E3 E2 B3 E1 EO B4 Based on the probing needs install the appropriate modules into the Tektronix logic analyzer
18. ayed in the status bar are also logged in the Log Form if logging is enabled The menu bar contains the following options File e Open Config File Displays an open file dialog in which the user may navigate to and open the file contains a previous session s saved probed settings e Save As Displays a save file dialog in which the user may specify where a preprocessor settings system file may be saved e Exit Shut down the application Edit e Modify Title String Allows the user to specify the title string that appears in all sub dialog s title bar This is helpful when running multiple probes Run Stop e Run Probe Mgr Running the preprocessor with the current settings This is an alternative to clicking the tool bar Run button e Stop Probe Mgr Stop the probe This is an alternative to clicking the tool bar Stop button Upgrade e FPGA Upgrade one of 2 protocol specific FPAG configurations Help e About Display version numbers for the Probe Manager application and FPGA configuration Pr eprocessor The application displays up to five sub dialogs These are used to configure the Configuration FS4435 probe The four sub forms are e Probe Configuration Covers the type of cable used and basic aspects of the link being probed e Filters Allows the user to specify the types of packets to be filtered e Pixel Recognizers Allows the user to trigger on a particular pixel value e Log Entries
19. d Data Error 1 1 This state includes an error TRAIN 1 A Training or IDLE sequence has been detected Packet Recognizer 3 1 Packet recognized pulsed for one clock cycle during packet Event Code 8 Describes what type of packet signal event or error event Code is held for duration of packet Transfer unit except that signal and error events can over write any state except the start state When start and end coincide the event code for the starting packet is displayed Sideband signals 3 Spares when in DisplayPort mode Spare 2 Spare Data Present 4 1 Corresponding lane data byte is present O Data not valid 3 2 1 0 This might be used to indicate that this lane has been dropped LOS 4 1 Corresponding lane Loss of Signal O Signal detect 3 2 1 0 Logically named reflects lane reverse status Lane 0 Control Fla 1 1 K character control O D character data Lane 0 8b Data Decoded 8b value Lane 1 Symbol Invalid 1 0 Valid 8b decode 1 Incorrect disparity or code violation Lane 1 Control Flag 1 1 K character control 0 D character data Lane 1 8b Data 8 Decoded 8b value Lane 2 Symbol Invalid 1 07 Valid 8b decode 1 Incorrect disparity or code violation Lane 2 Control Flag 1 12K character control 0 2 D character data Lane 2 8b Data 8 Decoded 8b value Lane 3 Symbol Invalid 1 0 Valid 8b decode 1 Incorrect disparity or code violation Lane 3 Control Fla 1 1 K character control 0 D character data Lane 3 8b Data 8
20. e assembly eene 12 EST040 DP interposer nieto eie eto crie eq eee donata HERE tuse 13 Installing your Software for the First Time ccce cresce eee eee eee eee ee etnue 14 Connecting the Tektronix logic analyzer to the FS4435 15 Loading System files eese een tee eoe een eae erae onse eee eo ao ro VN a pa CERE ee eee P Se Va sU ka Fe ERE Ce nU 16 Offlin ANALYSIS s csesssscessscosecsesssseonasssscecesstssensscoudesssenssonssesuucs sdesseenanceodesenesesveseseaeseseses 17 Probe Manager Application scsssscssssscsssscsssscsssccsssssssssssssascsssesssssssssssssssessssss 18 Preprocessor Configuration icc etd depre E UPPER PUE REEL HERRERA ERR 20 Dynamic Lane width tracking sessi 21 Bite ring 2 rnt ERREUR ORI E ERR OU uU 22 Ib ONT unen TEE 23 Advanced Pixel Triggering 2 rne serrer edet a een EY EE Pear sape eR 24 How to Triggerona Bad Pixel iiie eb P aC RP IRE ea 28 Log File oreet RD pe mU etti ipie p EHE ON PRU S 29 State VINE TETTE 30 SYMDOL AMES sicssocsccdeascecsissoesdscenccsssacsnenssvoncsessconsscsinepessvsdsnccssisenseseeensevesesenasesvenssececsenecs 31 GUSTA i i T EAE A M 32 ACQUIPING DE T E E E E A E S AA E N 33 The Protocol Disassembler ccssssscssscssscsssscssscssscsccscecscsscsesssecssscsesssesssssessoees 34 DP Groups aseo trie torso seeks ette donceedectusecessanes coeeedscatedncde
21. eceecseusesoncseesteeseursdencesoese 35 WX MCInUM M NOs iaar seS 38 10 b dec d GROUPS siiscscesesiscessssvssssceccscvscsnvsesecscsiensesscecsuctedvenpevesesesecsiensesesuesscesessenees 39 FPGA Upsrade cec 40 General Infotinationia suede Basie AANA TNS 41 Characteristics o asses cunaoncecexsnsaesausteeesuauenasceusonevavia CERNERET ENS eacceneoevctasuentssoencadieaeeners 41 Standards Supported e orte t ERE RO EEES 4l Power Requirements 35 5 per cR REO Ea VIRA FEE CERT RO FUE E TH EE ER DE 4l Logic Analyzer Required uei eee ER P ERR re PNE TERRE EUH UT 4l Number of Probes Used visa 2 n ee rote obedece tq ente eme flete dei 41 Environmental Temperature eeeeeseseeseeeeeeeeeee nennen enne entente entente innen enne 4l Altitude 5 22 mec da shana dara dh etidm ida eh ite 41 ET rnidity 25 angetan e Gto Ne RC be ERE reed 41 Testing and Troubleshooting 4 eerte eee etr tete erre ee Peng 41 SEEVICIIG ure OUS Dd ep Cn Rios Due d d fact 41 How to reach us For Technical Support FuturePlus Systems Corporation 36 Olde English Road Bedford NH 03110 TEL 603 471 2734 FAX 603 471 2738 On the web http www futureplus com For Sales and Marketing Support FuturePlus Systems Corporation TEL 719 278 3540 FAX 719 278 9586 On the web http www futureplus com FuturePlus Systems has technical sales representatives in several major countries For an up to
22. er pods and the link status LEDs are toggled The FS4435 can maintain lock and processing on a DP link as it changes lane width under certain conditions FuturePlus Systems recommends that you stop the preprocessor reconfigure the lane width and then restart the preprocessor This will set up the serdes properly for that new lane width and all the LEDs and Error Log should operate properly at that new lane width Filtering The Filter dialogue page provides the user with a comprehensive suite of predefined filter functions to apply to either Link These filters are state based which means that the event has to occur on all active lanes for it to be filtered Control Symbols cannot be filtered as they are needed for Protocol Decode DP Filters mi E E a E a LI LI E E a DP Filters Dialog Filter types include all types of states Many of the filters will operate on several types of states e g Content Protection Control Symbols will filter all control symbols associated with any Content Protection sequence of states Filters can be enabled to filter out entire secondary data packets There are currently no capabilities to filter portions of any secondary data packets Filtering is done in real time by the FS4435 hardware It must be stopped to change Filter settings Filtering out unwanted traffic such as dummy data symbols can extend the storage capabilities of the logic analyzer Filtering out irrelevant bu
23. es To capture specific traffic use the channel signals that can assist in identifying the activity that you want to capture For example to capture training use the channel TRAIN which goes high during training activity Turning off descrambling when looking at training will properly display the K characters Acquiring Data First insure that the FS4435 is attached to its external power supply and powered on which would be indicated by a green Power On LED Open up the Probe Manager software and insure the appropriate selections are made and applied finally make sure that the preprocessor is connected via the appropriate cable s to the target system Once connected with the link active open up the Probe Config window and select cable type lane width and other options Verify that lane activity indicators show activity at the correct lanes Run the preprocessor and observe the LEDs If a link s Signal LED is green but its Data LED is orange then there may be a need to select different options for lane width lane reverse or lane inversion in the Probe Config window The FS4435 should show a green Signal LED of any Link being probed as well as a green or dark data LED Configure the analyzer trigger menu to acquire data Select RUN and as soon as the trigger condition is met the logic analyzer will begin to acquire data The analyzer will continue to acquire data and will display the data when the analyzer memory is full the t
24. ge bit will be pulsed as each byte is ready the Command and ADDR Fields will be unchanged 1 r 0 b decode G i A 10b decode mode is provided in the FS4435 This mode has to be loaded using the Probe Manger at start up It requires different connections from the Tek modules and provides the following labels for the user Pre defined Label Bits Definition Usage Logic Analyzer Probes Align Flag 1 1 Alignment of multi lane link detected A4 4 Any Invalid Error Flag 1 1 This state includes an 8b10b code error A4 3 either disparity error or decode error in any active lane LOS 3 2 1 0 4 1 Corresponding lane Loss of Signal A4 2 0 07 Signal detect on lane A3 16 x2 x4 mode only Any LOS 1 17 Loss of Signal detected in any active lane A3 15 07 Signal detected in all active lanes Lane 0 Disparity Error 1 1 Lane 0 data has incorrect 8b10b disparit A3 14 Lane 0 Invalid Decode Error 1 1 Lane 0 data is not a valid 8b10b code A3 13 LaneO 10 Physical Lane 0 Data 10 bit encoded A3 12 3 Lane 1 Disparity Error 1 12 Lane 1 data has incorrect 8b10b disparity A3 2 Lane 1 Invalid Decode Error 1 1 7 Lane 1 data is not a valid 8b10b code A3 1 Lane1 10 Physical Lane 1 Data 10 bit encoded A3 0 A2 16 8 Lane 2 Disparity Error 1 17 Lane 2 data has incorrect 8b10b disparity A2 7 Lane 2 Invalid Decode Error 1 1 Lane 2 data is not a valid 8b10b code A2 6 Lane2 10 Physical Lane 2 Data 10 bit encoded A2
25. h the system file If you are analyzing more than 1 link simply choose another analyzer module from the system window and select Load Support Package to load the second module A list of Support Packages are as follows FS1163 DisplayPort AuxPort DisplayPort Auxiliary Port The following is an example listing screen showing the protocol decode provided by the Disassembler for DisplayPort i g x E Fie Edit view Data System Tools Window Help 81 x amp lgllasle Fy Al A setu trigger waveform amp listing Status _ Ide GD ek rita e Rel eS x30 E activity ALA X Gn 0 search z i ai Cursor 1 Y tof Cursor 2 w 14 875ns DisplayPort DisplayPort DisplayPort DisplayPort DisplayPort DisplayPort DisplayPort fDisplayPort hd Sample EventCode peas Lane CtlFlag Lane 0 Lane 1 Lane 2 Lane 3 LOS Grane 65530 58 Dummy Data 0 oo oo 00 00 0 000 65531 58 Dummy Data 0 oo oo 00 oo 0 ooo 65532 58 Dummy Data 00 oo no 00 0 000 65533 58 Dummy Data 0 oo oo o0 oo 000 ummy Data 65535 5C 1 sc 5C 5C sc 15C 65537 5C 0 01 01 01 01 0 001 65538 5C eee fT EF ee Ep ER Ld Eee rT We ee OEF 65539 5C 0 3c 3c 3c 3c 0 03c 5C 0 3c 3c 3c 3c 0 5c 0 3c 3c 3c 3c 0 5C 0 3c 3c 3c 3c 0 65540 sc os o1 04 0g 0 005 65541 sc 40 28 oo 00 0 040 5C 0 40 28 00 00 0 5c 0 40 28 00 oo 0 65542 5C 0 03 oo 03 oo 0 003 65543 5C 0 26 23 00 21 0 026 5C 0 26 23 o0 21 0 5c
26. hannel has its own clock 67KHz so that it can be clocked into separate modules in the LA on a separate clock domain It also has its own dis assembler that has to be loaded separately Field Bits Definition Probe Channel Command 4 Command Field B1 3 0 ADDR 11 0 12 Address Field B1 15 4 ADDR 19 12 8 Address Field B2 7 0 Aux CLK 1 B1 16 DATA 7 0 8 Data field B2 15 8 SYNC 1 Sync Bit B3 0 First part of the transfer CMD ADDR and DATA are all updated if SYNC is 0 then only DATA is updated STOP 1 Stop last byte of the transfer B3 1 Spare 1 B3 2 Spare 1 B3 3 Request 1 High when transaction is request B3 4 Response 1 High when transaction is response B3 5 Timeout 1 Response Timer timeout period 300us B3 6 o Unplugged HPD Low level 1 HPD pulsed low 25ms to 1 25ms a Interrupt event event signaled on rising edge of HPD LE pulsed low 1 75ms unplug repluged event signaled on rising edge of HPD EB dee In HPD High level Storage 1 Indicates Valid states B3 15 Byte Count Number of valid bytes received inclusive of current B4 10 6 state The Storage bit should be used as a qualifier for storing AUX data The rate at which Storage is pulsed depends on the packet type AUX transfers begin with a four bit CMD a 20 bit address and 8 bits of data Some packet types contain additional data which will be presented 8 bits at a time For the additional bytes the Stora
27. ing Dummy 0 1 0 1 1 0 0 0 Vertical Blanking MSA 0 1 0 1 1 1 0 0 Vertical Blanking Audio 0 1 1 0 0 0 0 0 Stream Vertical Blanking Audio TS 0 1 1 0 0 1 0 0 Vertical Blanking Reserved 0 1 1 0 1 0 0 0 Vertical Blanking Extension 0 1 1 1 1 0 0 Vertical Blanking Info Frame 0 1 1 1 0 0 Event Code Errors These signals are asserted for 1 state and are defined as the following Mismatch The mismatch bit is set when there when the KChar or configuration fields of the active lanes don t match Checks are made on all KChars and the VBID MVID and MAUD fields V err MVID Check The V err bit is set when the no video bit is set in the VBID and the MVID field is not O A err MAUD Check The A err bit is set when the audio multe bit is set in the VBID and the MVAUD field is not O Missed SR There is a BE counter on each of the four lanes If 512 BEs are received without receiving an SR on any lane the Missed SR error is asserted AUX Group Aux Port is a half duplex bi directional channel between DisplayPort transmitter source and DisplayPort receiver sink It consists of 1 differential pair transporting self clocked data The AUX CH supports a bandwidth of 1Mbps The DisplayPort Source Device is the master also referred to as AUX CH requester that initiates an AUX CH transaction DisplayPort Sink Device is the slave also referred to as the replier is the device that responds to the transaction Aux c
28. lead There are also a variety of link implementations besides widths There are protocol attributes such as lane inversion data scrambling and lane reversal which need to be defined in the Probe Manager in order for the preprocessor to capture data properly It is strongly recommended that the user methodically proceed in the following manner when setting up the probe There is more detail on each step in this manual 1 Load the Probe Manager software and FS1163 on the PC and or logic analyzer Leave the CD in the system for access to the USB drivers 2 Configure merge the logic analyzer modules as required and run the Tektronix Logic analyzer s internal diagnostics If the analyzer passes then make the appropriate target probe connections to the FS4435 preprocessor and from the preprocessor to the TLA FS1055 cables 3 Connect the appropriate probing cable s to the target system power up the probe This may result in a Windows dialog searching for the FTDI FTD2XX USB drivers direct it to the Probe Manager CD Check the Windows Device Manager to make sure that it loaded properly 4 Open up the Probe Manager application and select the appropriate settings for the probe cable being used and the target link Check that the expected Pad assignments for the probed link show green after the Run button has been pressed For the first capture turn off all the filters 5 If the FS4435 preprocessor LEDs are all Green and the fir
29. load during the first connection of the FS4435 Windows MUST be directed to load the drivers from this CD in the system or the proper USB drivers will not load In some cases it may necessary to temporarily disconnect the Windows system from the local network to insure that Windows does not automatically default to getting the drivers from the Internet If the correct USB drivers are not loaded the user will see a Windows error Unable to load DLL as soon as the Run button is used NOTE The Microsoft NET Framework must be on the system for the Probe Manager application to load properly 2 FS4435 probe This preprocessor requires its own DC power supply which is provided Additionally this preprocessor is completely initialized set up and controlled by the Probe Manager software that resides on a Windows based system either stand alone PC or TLA logic analyzer All communication to the FS4435 preprocessor is by means of the USB port on the PC or logic analyzer Improper or incomplete installation of either the correct USB driver or the Probe Manager software will prevent operation of the FS4435 Tektronix Logic Analyzer The TLA Disassembler files for the TLA7xxx analyzer FS1163 are on a CD Install these files as required and follow the instructions for logic analyzer module card interconnections and logic analyzer connections to the FS4435 probe Target platform There are two probing options mid bus probe or flying
30. nnection to AUX and HPD e Loss of Lock LEDs under the cover of the preprocessor Link A lane 0 3 are on the top and Link B lane 0 3 are below them Red indicates Loss of Lock which will prevent preprocessor operation Dark indicates proper operation e LED indication of preprocessor power on and Link status For each link there is a pair of LEDs which have the following states Link A or B Meaning Link A or B Meaning Signal LED Data LED color color Green Link OK Green Data clocking Into Analyzer Dark Loss of Signal Dark No Data clocking into Analyzer Orange Data Invalid 8b10b error Orange Any Error 8b10b Align Framing Idle Red Receiver Fault or Int Red Preprocessor Clock Error FS4435 Probing Cables sideband cables The FS4435 can be configured with different probing cables dependent on what the user requires FS1032 2 size midbus footprint probe cable for x1 to x4 FS1036 Flying lead probing cable for x1 to x4 FS1040 DisplayPort Interposer The DisplayPort Probing application note provides specific information on the successful application of midbus probing and also details general requirements for the Reference Clock signal and other aspects of the link to be probed The FS4435 manual assumes that the user is familiar with this information and has applied it The cable should be attached to the FS4435 and carefully secured with the 2 captive fasteners on the cable The probing end sh
31. ould be attached to the target by screwing into the retention module midbus probe Use of the flying lead probe requires careful installation and mechanical support of special flex circuit tips The sideband signals for DP need to be connected to the FS4435 preprocessor separately from the data link probing cables There are uniquely identified and labeled cables for doing this These must be properly oriented for polarity The DP AUX channel requires a high speed differential connection using a Samtec 050 header where pins 1 and 3 are AUXp and AUXn The HP INT signal has its own cable that also connects to a 050 header pin 1 is the signal and pin 2 is the ground connection NOTE These signals cannot see voltages higher than 4 VDC or there is a risk of damaging the preprocessor Flying Lead Probing FS1036 cable assembly The FS1036 flying lead cable assembly allows the FS4435 preprocessor to connect to components on the target board by means of directly soldering a flex pcb to a component or feature on the target pcb then connecting the header on the flying lead cable to the other end of the flex pcb 100 2 54 REF MDC E 100 2 54 REF SUB SCF 134473 01 DA 4602 010 11 6820 25 012 0 20 REF TYP 039 0 99 REF 210 5 33 REF STIFFENER o22 0 55 REF A few general guidelines about the use of the flying lead cable 1 There is an instruction booklet with the FS1036 c
32. pixel value is on Line 1 ONLY look for the start of video frame must filter out stuff data m probe manager Group EventCode Vertical Blanking BE Reset Counter 2 And Go To 2 Else If Group EventCode l Vertical Blanking BE Then GoTo Qet Run State 2 State 2 check for dessed color at desired location ox d not found go to next video frame M Counter 2 376 And Group Storage 1 And Group Piel Recognizer 1 Then Trigger All Modules Else If Counter 2 lt 376 And Group Storage 1 Then Inc Counter 2And Go To 2 Else If Channel PktRecog_0 Low And Group Storage 1 Then GoTo1 How to Trigger on a Bad Pixel A simple way to find a bad pixel in a screen is to have the source drive the screen to all one color for example black RGB 0 0 0 Program the Logic Analyzer to look for not black on any of the active lanes Note When using the Pixel Recognizer as part of the triggers it is recommended that Active Video Stuffing Data Symbols be filtered out using the Filtering menu Below is an example trigger that shows how this can be accomplished d Trigger DisplayPort E 16 xl JE Fie Edi View System Tools Window Help xj iie ley 2 A mese on eel se je Qa Storage rains r Force Main Prefill T Trigger Pos Fr BE 50 Storage If Group Storage 1 Run Then Store Sample J State 1 Trigger on
33. rigger specification is TRUE or when you select STOP Main Link status is communicated by a pair of LEDs as follows Signal LED State Meaning Dark LOS no signal on an active lane Red RX Fault Lost Signal Lost Synch on Data FIFO over run or under run See Log for more information Orange Invalid Symbol or Disparity Error Green OK Data LED State Meaning Red FPGA Lost lock on clock s Preprocessor needs to stop and run again Orange Any Error Invalid Symbol or Disparity Error Align Framing ldle Green OK Data clocking into analyzer Dark No Data due to filtering or not running All transient events such as a single bit error or a packet clocked into the analyzer are stretched to short visible pulses on the LEDs There are no LED s to show the status of the AUXPORT The Protocol Disassembler Captured DP data is as shown in the following figure The figure below displays the Main Link protocol decode ATLA Listing 1 J File Edit view Data System Tools Window Help glali mee E 9 A isetup lifdTriager P waveform Zisting Status Ide gt gt Tek PETERE F activity AJA X aE E fSearch hd fh amp hf Cursor 1 v o f Cursor 27 14 875ns Di Uy up paca us Mon DisplayPort DisplayPort Da EE ayPort Duet i ayPort puer E ayPort piede ort m pem me 0 pese 65530 Dummy Data 65531 Dummy Data 65532 Dummy Data 65533 Dummy Data
34. s traffic can help users focus on specific packets of interest To filter out any particular traffic type click on the appropriate box so a Y appears and click apply You must restart the preprocessor by pressing the green run button so the new values will be written to the preprocessor hardware DP has only one link and thus there are no controls to specify filters for link A or B The status of the probe and the link under test can be seen in this tab page Pixel Recognition Display Port Pattern Recognizers g g NEN The Pixel Recognition function allows the user to trigger on any pixel value It s set up involves the following controls Pixel Format Either RGB YCbCr 4 4 4 format or YCbCr 4 2 2 format Pixel Width Select the correct total bits per pixel format from the choices listed The target system s pixel format can be found in the MSA packet of the DP listing Pixel Value Enter the decimal or Hex value of each color component of the pixel to be triggered on Leaving a field blank will define a don t care for that value Click on the Apply button after the values are set to set the Pixel Recognizer to flag the defined value The Group name Pixel Recognizer can then be used in the Trigger statement This signal will pulse high on the state that contains this pixel value Advanced Pixel Triggering The Pixel Recognizer function of the FS4435 can be combined with the triggering func
35. st trace file captured on the logic analyzer has no error messages then it is a good indication that all initial settings are correct 6 Alink showing Signal LED green and Data LED orange constantly needs settings for link width lane reverse or lane inversion adjusted in the Probe Config window 7 Alink showing Signal LED orange or red may have a problem with the reference clock settings or connection More information on link signal status can be seen in the Log File window Depending on the DP target system Reference Clock and data lane signal characteristics such as jitter tolerance jitter spectrum and or signal characteristics at the probing location the user may always see some level of orange DATA LED activity and see the corresponding errors recorded on the TLA and in the Probe Error Log Please remember that the FS4435 cannot operate with spread spectrum clocking on the link Front Panel The connections and features of the FS4435 preprocessor include e DC input for provided external AC to DC power supply please note that the use of any other power supply voids the warranty on the FS4435 On Off switch and USB connections to the Windows PC TLA7xxx where the Probe Manager software will be loaded e Link Probe cable connection for 1 of the probing cables mid bus or FL e Logic Analyzer 90 pin pod connections A1 A4 are connections for A Link Processor and B1 B4 are for B Link Processor e Cables for co
36. system installed on the PC if you need this software please contact Tektronix Offline analysis allows a user to be able to analyze a trace offline at a PC so it frees up the analyzer for another person to use the analyzer to capture data In order to view decoded data offline after installing the TLA7xxx environment on a PC you must install the FuturePlus software Please follow the installation instructions for Setting up TLA7xxx analyzer Once the FuturePlus software has been installed follow these steps to import the data and view it From the desktop double click on the Tektronix TLA icon When the application comes up there will be a series of questions answer the first question asking which startup option to use select Continue Offline On the analyzer type question select Cancel When the application comes all the way up you should have a blank screen with a menu bar and tool bar at the top Open the tla file using the File Load System menu selection and browse to the desired tla file Probe Manager Application The Probe Manager software can be found as the FS44xx Probe Mgr exe file on the CD provided in the Documentation package Insert the CD into the computer that will be used to control the FS4435 probe This computer must have a USB connection Using Windows File Manager select the FS44xx Probe Mgr exe file and double click it which initiates the installation software on the computer and places an icon
37. t to 9 counter 1 7 line number 1 Trigger Level 4 Once the desired line is found we use the index number of the pixel pixel index numbers start at 0 to find what state to test the pixel recognizer against The value of Counter 2 is as follows Counter 2 7 Pixel Index number Link Width Bits per pixel 8 1 If the desired pixel color at the specified location is not part of this frame the trigger will go back to State 1 and look for this location color combination in the next frame The logic analyzer triggering combined with the pixel recognizer will get the trigger to the exact pixel if it is a x1 configuration Based on the number of lanes and the format of the pixel it will at worst get it to the correct state where the user will visually have to determine which out of 4 pixels matches the recognizer There are several saved Triggers for this advanced Pixel triggering These can be loaded from the File menu Fie Edt View System Tools Window Help Go Online Local Go Offline Choose TLA Default System Ctrl D Load System Ctrl 0 Save System Chrl S Save System As Default Module Load Module Save Module Save Module As Load Support Package 1 Load Data Window CT i Reload Selected Program Look ine 3 stored triggers z e er EB Default Trigger Desktop ee el 3 Floppy A Save T gg Local Disk C Tm C Program Files Save Trigger As Gia TLA 700 Supports Page Setup C DisplayPor Print
38. teristics are not specifications but are typical operating characteristics for the FS4435 probe If the product is used in a manner not specified by manufacturer then the protection provided by the equipment may become impaired DisplayPort version 1 1a 100 240VAC 2 amps Tektronix TLA7AA4 modules installed in a TLA71x or TLA7Oxx frame The State Adapter Probe interface uses 4 FS1055 cables of 90 pin type Non operating 40 to 75 degrees C 40 to 167 degrees F Operating 20 to 30 degrees C 68 86 degrees F Operating 4 6000m 15 000 ft Non operating 15 3000m 50 000 ft Up to 80 relative humidity Avoid sudden extreme temperature changes which would cause condensation on the FS4435 module There are no automatic performance tests or adjustments for the FS4435 module If a failure is suspected in the FS4435 module contact the factory or your FuturePlus Systems authorized distributor The repair strategy for the FS4435 is module replacement However if parts of the FS4435 module are damaged or lost contact the factory for a list of replacement parts
39. tion on the operating characteristics and cable header pinout for the FS4435 probe The following terms are used to describe aspects of the DP bus e Channel One differential signal 2 wires e Link One direction of a DP link The FS4435 handles 1 DP and 1 Aux link Accessories Supplied Minimum Equipment Required Analyzing the DP Bus This chapter introduces you to the FuturePlus Systems FS4435 preprocessor and lists the minimum equipment required for analysis The FS4435 is a DP State Analysis preprocessor The preprocessor can connect to the target by either a half size midbus probe or flying leads The sideband signals such as AUX and HPD connect to the probe using separate cables The preprocessor itself is controlled by the Probe Manager software which runs under Windows and communicates with the preprocessor via a USB cable The FS4435 snoops a link without significantly degrading its signal integrity The high speed serial signal is deserialized and processed for packet identification by the FS4435 before being sent to the logic analyzer connections Additionally the preprocessor provides trigger and filtering functions The dis assembler software running on the logic analyzer provides information regarding the transactions within the captured traffic The FS4435 product consists of the following accessories e The FS4435 preprocessor power supply and cable Protocol Disassemblers FS1163 and Aux Port for DP
40. tionality of the logic analyzer to find a specific pixel value at a specific pixel location The user is required to know the following information in order to set up these triggers Number of lanes Format of the pixel RGB YCbCr bits per pixel Horizontal line that will contain the pixel Pixel color value This function uses multiple levels of triggering Note For this trigger to work filters must be set so Stuffed Data symbols during the active video segment are filtered out Conditional Storage using Group Storage 1 Level 1 locate the start of the active video frame Vertical Blanking BE Level 2 and 3 locate the start of the defined horizontal line Horizontal Blanking BE using counter 1 Level 4 Find the logic analyzer state within the desired video line that the desired pixel is located on If no trigger then go to Level 1 Trigger Level 1 The start of a video frame can be defined as the Vertical Blanking End and can be set in the trigger using the Event code Vertical Blanking BE However some systems can generate multiple Vertical BEs before any Horizontal video so a trigger function may need to include FO or F1 pixel information to determine the start of the desired video frame Trigger Level 2 and 3 The horizontal line number for the desired pixel has to be defined by the user This line can be counted up to by using the Event Code Horizontal Blanking BE Note that for a pixel at line 10 the counter would be se
41. y installed on that instrument FuturePlus Systems does not warrant that the operation of the hardware or software will be uninterrupted or error free The foregoing warranty shall not apply to defects resulting from improper or inadequate maintenance by the Buyer Buyer supplied software or interfacing unauthorized modification or misuse operation outside of the environmental specifications for the product or improper site preparation or maintenance NO OTHER WARRANTY IS EXPRESSED OR IMPLIED FUTUREPLUS SYSTEMS SPECIFICALLY DISCLAIMS THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE THE REMEDIES PROVIDED HEREIN ARE BUYER S SOLE AND EXCLUSIVE REMEDIES FUTUREPLUS SYSTEMS SHALL NOT BE LIABLE FOR ANY DIRECT INDIRECT SPECIAL INCIDENTAL OR CONSEQUENTIAL DAMAGES WHETHER BASED ON CONTRACT TORT OR ANY OTHER LEGAL THEORY Product maintenance agreements and other customer assistance agreements are available for FuturePlus Systems products For assistance contact Technical Support How to Use This Manual Definitions Introduction This manual is organized to help you quickly find the information you need e Analyzing the DP Bus chapter introduces you to the FS4435 and lists the minimum equipment required and accessories supplied for DP bus analysis e The State Analysis chapter explains how to configure the FS4435 to perform state analysis on your bus e The General Information chapter provides informa
Download Pdf Manuals
Related Search