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User`s Manual 06.96 8-Bit CMOS Microcontroller http://www.siemens

1. C504 AC Characteristics for C504 L24 C504 2R24 cont d External Data Memory Characteristics Parameter Symbol Limit Values Unit 24 MHz clock Variable Clock l fc c 3 5 MHz to 24 MHz min max min max RD pulse width TRLRH 180 6tac 70 ns WR pulse width wiwH 180 6toc 70 ns Address hold after ALE Laxe 56 2tac 27 ns RD to valid data in fai pv 118 5fteic 90 ns Data hold after RD RHDX 0 0 ns Data float after RD RHDZ 63 2foic 20 ns ALE to valid data in fiiov 200 8toc 133 ns Address to valid data in lavov 220 Moro 155 ns ALE to WR or RD fiw 75 175 3toacL 50 3tgg 50 ns Address valid to WR TAVWL 67 Atco 97 ns WR or RD high to ALE high twain 117 67 toa 25 tag 25 ns Data valid to WR transition Lovwx 5 fee 37 ns Data setup before WR foavwH 170 7torc 122 ns Data hold after WR fwHax 15 faic 27 ns Address float after RD TRLAz 0 0 ns External Clock Drive Parameter Symbol Limit Values Unit Variable Clock Freq 3 5 MHz to 24 MHz min max Oscillator period feet 41 7 294 ns High time LcHox 12 torot feicx ns Low time cicx 12 fecic feucx ns Rise time lech 12 ns Fall time cHcL 12 ns Semiconductor Group 10 9 Device Specifications C504 SIEMENS 10 6 AC Characteristics for C504 L40 C504 2R40
2. Figure 6 17 Timer 2 in Capture Mode The baud rate generator mode is selected by RCLK 1 and or TCLK 1 in SFR T2CON It will be described in conjunction with the serial port Semiconductor Group 6 29 SIEMENS On Chip Peripheral Components C504 6 3 Capture Compare Unit CCU The Capture Compare Unit CCU of the C504 is designed for applications which have a demand for digital signal generation and or event capturing e g pulse width modulation pulse width measuring It consists of a 16 bit 3 channel capture compare unit CAPCOM and a 10 bit 1 channel compare unit COMP In compare mode the CAPCOM unit provides two output signals per channel which can have inverted signal polarity and non overlapping pulse transitions The COMP unit can generate a single PWM output signal and is further used to modulate the CAPCOM output signals For motor control applications both units CAPCOM and COMP may generate versatile multichannel PWM signals which are basically either controlled by compare timer 1 or by a typical hall sensor pattern at the interrupt inputs block commutation 16 Bit Capture Compare Unit CAPCOM Period Register Mode Trap Initialization Select Registers Registers CTRAP CCPH CCPL CMSELO CMSEL1 COINI TREN Offset Register CC Channel 0 CCO CT10FH CT10FL CCHO CCLO COUTO CC Channel 1 CC1 Compare CCH1 CCL1 pd f COUT1 Timer 1 16 Bit CC Channel 2
3. o P1 5 COUT1 EXT gt P1 6 CC2 CTH P1 7 COUT2 1 P3 0 RxD ETS P3 1 TxD EE P3 2 AN4 INTO L L1 P3 3 AN5 INT1 C e P3 4 AN6 TO CN P3 5 AN7 T1 C MCP02532 Figure 1 3 Pin Configuration top view Semiconductor Group 1 4 SIEMENS Introduction C504 Table 1 1 Pin Definitions and Functions Symbol Pin Number l O Function P MQFP 44 P1 0 P1 7 40 44 O Port 1 1 3 is an 8 bit bidirectional port Port pins can be used for digital input output P1 0 P1 3 can also be used as analog inputs of the A D converter As secondary digital functions port 1 contains the timer 2 pins and the capture compare inputs outputs Port 1 pins are assigned to be used as analog inputs via the register P1ANA The functions are assigned to the pins of port 1 as follows 40 P1 0 ANO T2 Analog input channel 0 input to counter 2 41 P1 1 AN1 T2EX Analog input channel 1 capture reload trigger of timer 2 up down count 42 P1 2 AN2 CCO Analog input channel 2 input output of capture compare channel 0 43 P1 3 AN3 COUTO Analog input channel 3 output of capture compare channel 0 44 P1 4 CC1 Input output of capture compare channel 1 1 P1 5 COUT1 Output of capture compare channel 1 2 P1 6 CC2 Input output of capture compare channel 2 3 P1 7 COUT2 Output of capture compare channel 2 RESET 4 RESET A high level on this pin for one machine cycle while the osc
4. Figure 6 37a Serial Interface Mode 1 Functional Diagram Semiconductor Group 6 89 SIEMENS On Chip Peripheral Components C504 Transmit 3 N e o D o no gt co I amp o T 5 eo o or Lo 2o xo gt lt 0 I LL mo co aw wn ao gt x om o zo ES y a A x2 La E xo ze E amp 5 lt Receive Figure 6 37b Serial Interface Mode 1 Timing Diagram Semiconductor Group 6 90 SIEMENS On Chip Peripheral Components C504 6 4 6 Details about Modes 2 and 3 Eleven bits are transmitted through TXD or received through RXD a start bit 0 8 data bits LSB first a programmable 9th data bit and a stop bit 1 On transmit the 9th data bit TB8 can be assigned the value of 0 or 1 On receive the 9th data bit goes into RB8 in SCON The baud rate is programmable to either 1 32 or 1 64 the oscillator frequency in mode 2 When bit SMOD in SFR PCON 871 is set the baud rate is fosc 32 Mode 3 may have a variable baud rate generated from either timer 1 or 2 depending on the state of TCLK and RCLK SFR T2CON Figure 6 38a shows a functional diagram of the serial port in modes 2 and 3 The receive portion is exactly the same as in mode 1 The transmit portion differs from mode 1 only in the 9th bit of the transmit shift register The associated timings for transmit receive are illustrated in figure 6 38b Transmission is initiated by any instruction that uses SBU
5. lllllele n 65 1 A D Converter Operation ooooooocccocnnn mmm 6 5 2 A D Converter Registers 000 cee eee ee Semiconductor Group 1 2 SIEMENS C504 Table of Contents Page 6 5 3 A D Converter Clock Selection o oooooococoomomomomons 6 99 6 5 4 A D Conversion Timing zat sm RAD ERROR ERR MEX ca 6 100 6 5 5 A D Converter Calibration 224 23 wx educa Red rx roda 6 104 6 5 6 A D Converter Analog Input Selection ooo oooomooo 6 105 7 Interrupt SYSTEM cir E TE EE ER NES EE a nee 7 1 7 1 Interrupt SITUE B oves ES Deep RETE ayn trate arn SIM Sg EE E S eR 7 4 7 2 Interrupt Sources and Vectors at per rS ne ere EE REIS ESOS 7 4 7 3 Interrupt Registers Acco meet eee EIU RS IE hee ea e EE EAS QUSE 7 5 7 3 1 Interrupt Enable Registers sra ar AAA 7 5 7 3 2 Interrupt Prioritiy Registers rr A a 7 7 7 3 3 Interrupt Request Flags rca LA A PI 7 9 7 4 How Interrupts are Handled a na a nananana eee es 7 10 7 5 External Interrupts eue A A At RS 7 11 7 6 Interrupt Response Time 0 cc ee eens 7 14 8 Fail Safe Mechanisms eeeeeeeeeeee 8 1 8 1 Programmable Watchdog Timer 20000 cee eee ees 8 1 8 1 1 Refreshing the Watchdog Timer 220000 cee eee 8 4 8 1 2 Watchdog Reset and Watchdog Status Flag WDTS 8 4 8 2 Oscillator Watchdog Unit 3 2 9s dd Gtr ted ee hee OO 8 5 8 2 1 Detailed Description of the Oscillator Watchdog U
6. iode Active CC2 Phase COUTO COUT2 State No 1 2 3 4 5 1 2 3 4 5 1 b Timing in rotate right mode BCM1 07 0 1 with COINI XX000000p Start ined e e be Le be Lei b Timer 1 ile cco couT1 High Active CC2 Phase COUTO COUT2 State No 2 1 5 4 3 2 1 9 4 3 2 MCTO2614 Figure 6 33 Basic Compare Timer 1 Controlled 5 Pole PWM Timing Semiconductor Group 6 74 SIEMENS On Chip Peripheral Components C504 a Timing in rotate left mode BCM1 071 0 with COINI XX111111 B Start ee AA AA AA AAA Compare Timer 1 gt cco pEzsE xp a e e a A AAA oo ASS A es A o is 3 COUT2 State No 1 2 3 4 5 6 1 2 3 4 5 CC2 CC1 b Timing in rotate right mode BCM1 0 0 1 with COINI XX000000p Start AAA AAA Compare Timer 1 Low Active Phase gt CCO A lt wx com A PI PES BOUT eo e ae A le e A A le EA E E e ER COUT2 State No 2 1 6 5 4 3 2 1 6 5 4 CC2 CC1 High Active Phase MCTO2615 Figure 6 34 Basic Compare Timer 1 Controlled 6 Pole PWM Timing Semiconductor Group 6 75 SIEMENS On Chip Peripheral Components Table 6 10 to 6 12 show as a state table the basic signal pattern def
7. 0 0 eee eee 6 3 2 1 CAPCOM Unit Clocking Scheme 00055 6 3 2 2 CAPCOM Unit Operating Mode 0 Ls 6 3 2 3 CAPCOM Unit Operating Mode 1 Lis 6 3 2 4 CAPCOM Unit Timing Relationships 6 3 2 5 Burst Mode of CAPCOM COMP Unit 6 3 2 6 CAPCOM Unit in Capture Mode sss 6 3 2 7 Trap Function of the CAPCOM Unit in Compare Mode 6 3 2 8 CAPCOM Register aire 6 3 3 Compare COMP Unit Operation o o o oooooo 6 3 4 Combined Multi Channel PWM Modes 6 3 4 1 Special Function Register BCON 00 0 eee eee 6 3 4 2 Signal Generation in Multi Channel PWM Modes 6 3 4 3 Block Commutation PWM Mode sees 6 3 4 4 Compare Timer 1 Controlled Multi Channel PWM Modes 6 3 4 5 Trap Function in Multi Channel Block Commutation Mode 6 4 Serial Interface USART 0 000 ccc es 6 4 4 Multiprocessor Communications 000e eens 6 4 2 Serial Port Registers 0 0 cece eee 6 43 TBauUd ales 240 0019 et Dia ta wie oe ata wes 6 4 3 1 Using Timer 1 to Generate Baud Rates 6 4 3 2 Using Timer 2 to Generate Baud Rates 6 44 Details about Mode O 0 es 6 4 5 Details about Mode 1 2 sac icones wr ee yeu Rn 6 46 Details about Modes 2 and 3 ssssss 6 5 10 bit A D Converter
8. Single or continuous conversion mode Interrupt request generation after each conversion Using successive approximation conversion technique via a capacitor array Bullt in hidden calibration of offset and linearity errors The externally applied reference voltage range has to be held on a fixed value within the specifications The main functional blocks of the A D converter are shown in figure 6 39 6 5 1 A D Converter Operation An internal start of a single A D conversion is triggered by a write to ADDATL instruction The start procedure itself is independent of the value which is written to ADDATL When single conversion mode is selected bit ADM 0 only one A D conversion is performed In continuous mode bit ADM 1 after completion of an A D conversion a new A D conversion is triggered automatically until bit ADM is reset The busy flag BSY ADCONO 4 is automatically set when an A D conversion is in progress After completion of the conversion it is reset by hardware This flag can be read only a write has no effect The interrupt request flag IADC IRCONO 0 is set when an A D conversion is completed The bits MXO to MX2 in special function register ADCONO and ADCON are used for selection of the analog input channel The bits MXO to MX2 are represented in both registers ADCONO and ADCON 1 however these bits are present only once Therefore there are two methods of selecting an analog input channel If a new channel is
9. 10 16 Loading and interfacing wei tor hincene ty meto 6 14 REN 3 Beate eG eta bs See CRI da Co c ett d tal SOS V fuf fe N 3 6 6 80 Output drivers circuitry Minette PS 6 8 Reset Slay Bee ah eter ECEISUM eek er x XO C ON E AS 5 1 Mixed digital analog I O pins 6 10 Fast power on reset 5 2 Multifunctional digital O pins 6 8 Hardware reset timing 5 4 Push pull digital analog I O pins 6 11 Power on reset timing 5 3 Push pull digital I O pins 6 11 Alora 3 6 6 79 6 80 Output input sample timing 6 13 RMAP esses nn 3 3 3 7 Read modify write operation AS a 6 15 ROM protection NA Nd etm 4 8 Types and structures 6 1 Protected ROM mode 4 9 Port O circuitry 6 5 Protected ROM verification example 4 10 Port 1 3 circuitry 6 6 Unprotected ROM mode 4 8 Port 2 circuitry LA ai a ae E ial 6 7 RSO AS A e 2 3 3 7 Standard I O port circuitry A 6 3 to 6 4 RS1 iE a d ELA cd O Dir D RS De d 2 3 3 7 Power down mode e 9 5 RxD DAA A aaa a TER 3 7 Power saving modes 9 1 Semiconductor Group 11 4 SIEMENS Index C504 SBUF i S enin 3 4 3 6 6 79 6 80 SON citeer ds id 3 4 3 6 6 79 6 80 Serial interface USART 6 78 Baudrate generation 6 81 with timer d 6 82 with timer2 6 83 Multiprocessor communication 6 79 Operating
10. Vo 0 9 Voc V Toy 800 uA in push pull mode and COUT3 Output high voltage port 0 in Von 2 4 V Tou 800 uA 2 external bus mode ALE PSEN 0 9 Voc Tou 80 pA 2 Logic 0 input current ports 1 2 3 Ji 10 50 uA Vin 0 45 V Logical 1 to 0 transition current Iu 65 650 uA Vn 2V ports 1 2 3 Input leakage current port 0 EA J t1 uA 0 45 lt Vn lt Voc Pin capacitance Cio 10 pF f 1 MHz T 25 C Overload current loy t5 mA 78 Semiconductor Group 10 2 SIEMENS Device Specifications C504 Parameter Symbol Limit Values Unit Test Condition typ max Power supply current Active mode 12 MHz Igc 16 TBD mA Voc 25V Idle mode 12 MHz 9 Toc 8 TBD mA Voc 5 V Active mode 24 MHz Tec 25 TBD mA Voc 5 V Idle mode 24 MHz 9 Toc 13 TBD mA Voc 5 V Active mode 40 MHz Tec 38 TBD mA Voc 5V Idle mode 40 MHz 5 Toc 17 TBD mA Voc 5 V 5 Power down mode Ipp 1 50 WA Vec 2 5 5 V9 1 2 3 4 S z 8 9 Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the Vo of ALE and port 3 The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1 to 0 transitions during bus operation In the worst case capacitive loading gt 100 pF the noise pulse on ALE line may exceed 0 8 V In such cases it may be desirable t
11. and the program counter is not incremented In any case execution is completed at the end of S6P2 Figures 2 2 a and b show the timing of a 1 byte 1 cycle instruction and for a 2 byte 1 cycle instruction Most C504 instructions are executed in one cycle MUL multiply and DIV divide are the only instructions that take more than two cycles to complete they take four cycles Normally two code bytes are fetched from the program memory during every machine cycle The only exception to this is when a MOVX instruction is executed MOVX is a one byte 2 cycle instruction that accesses external data memory During a MOVX the two fetches in the second cycle are skipped while the external data memory is being addressed and strobed Figure 2 2 c and d show the timing for a normal 1 byte 2 cycle instruction and for a MOVX instruction Semiconductor Group 2 4 SIEM ENS Fundamental Structure C504 ua RAE dl Eli hal P1 P2 P1 P2 P1 P2IP1 P2 P1 P2IP1 P2IP1 P21P1 P21P1 P2IP1 P21P1 P2 P1 P2 osc XTAL2 ALE Read Read next Opcode Opcode Discard Read next Opcode Y Again SIsTSISISIs a 1 Byte 1 Cycle Instruction e g INC A Read Read 2nd E Opcode Byte p Read next Opcode Sas e b 2 Byte 1 Cycle Instruction e g ADD A Data Read next Opcode Again 4 Read Read next Opcode Discard Opcode Y Y Y ISISTSTSTS TS TS TS TS Te TS T c 1 Byte 2 Cycle Instruction e g INC DPTR Read next
12. 00 6 44 12 MHz timing 10 6 to 10 7 Register write on the fly o 6 44 24 MHz timing 10 8 to 10 9 A att 599 40 MHz timing 10 10 to 10 11 E ee Moto ah AC Testin so zc Float x 10 16 General operation cce 6 31 Input output waveforms 10 16 perece lees ae sa as 2 AG a tees ad TS 2 2 3 4 3 8 TEM Die dro ADCL 3 8 4 pole PWM timing 6 74 ADCLO PIACULA 6 98 5 pole PWM timing 6 75 ADCL4 5 LL LL LLL LLL 6 98 6 pole PWM timing 6 76 ADCONO dO b ULM 3 4 3 8 6 97 Block commutation mode 6 71 ADCON1 A A ote 3 4 3 8 6 97 Multi pole PWM state tables 6 77 6 78 ADDATH Van rat Niue Ye P 3 4 3 8 6 96 Output waveforms o 6 69 to 6 70 ADDATL 3 4 3 8 6 96 Register BCON 6 66 ADM 3 8 6 97 Signal generation 6 68 ALE signal A A i 4 4 Trap function eg mp Rx 6 78 Cibo E E A Ns Capture compare unit CCU 6 30 B o COOP ie o Ea EOS EP gs 3 8 MENS ES Se GOEN NER 3 8 Basic CPU timing mo o9 m m o om o m 5 9 5 3 c 3 3 2 4 CCOI 3 8 BOE Mes ra tad uu eR 3 8 85B aean AN 4 CCOR S nist ii 3 8 BCEN or Lxx uu ae 3 8 6 67 CCOREN 3 8 BCERB o a tna ties 3 8 6 67 AN 3 8 A 26 cratic aret DRE 3 8 6 67 CCAFEN LLL 3 8 BGM osse 3 8 6 67 DENCIA MN MEAR 3 8 BOMBE is 3 8 6 66 CCAR AA Ln sp QN E 3 8 BCON momo om om om om om omo nom o m m m nm sm n n n 3 5 3 8 6 66 CC1 REN S n PET ROSE SUE 3 8 Block diagram tot a
13. 2 Bit addressable special function registers 3 SFR is located in the mapped SFR area For accessing this SFR bit RMAP in SFR SYSCON must be set Semiconductor Group SIEMENS Memory Organization C504 Table 3 2 Contents of the SFRs SFRs in numeric order of their addresses cont d Addr Register Content Bit 7 Bit6 q Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 after Reset BOW P3 FFH RD WR T1 TO INT1 INTO TxD RxD BOW 99 PSANA XX11 EAN7 EAN6 EAN5 EAN4 11XXp Bly SYSCON XX10 EALE RMAP XMAP XXXO0p B8y IPO XX00 PT2 PS PT1 PX1 PTO PXO 0000p B9y IP1 XX00 PCT1 PCCM PCT2 PCEM PX2 PADC 0000p COW WDCON XXXX OWDS WDTS WDT SWDT 0000p City CT2CON 0001 CT2P ECT2O STE2 CT2 CT2R CLK2 CLK1 CLKO 0000p RES C24 CCLO 00H y 6 5 4 3 2 1 0 C34 CCHO 00H y 6 5 4 3 2 1 0 C4y CCL1 00H y 6 5 4 3 2 1 0 C5y CCH1 00H Y 6 5 4 3 2 1 0 C6y CCL2 00y y 6 5 4 3 2 1 0 C74 CCH2 00H y 6 5 4 3 2 1 0 C8y T2CON 00g TF2 EXF2 RCLK TCLK EXEN2 TR2 C T2 CP RL2 C94 T2MOD XXXX DCEN XXXO0p CAy RC2L 00H Y 6 5 4 3 2 1 0 CBy RC2H 00H y 6 5 4 3 2 1 0 CCH TL2 00H y 6 5 4 3 2 1 0 CDy TH2 00H y 6 5 4 3 2 1 0 CF4 TRCON 00y TRPEN TRF TREN5 TREN4 TREN3 TREN2 TREN1 TRENO DOW PSW 00H CY AC FO RS1 RSO
14. 6 1 2 Standard I O Port Circuitry Figure 6 1 shows a functional diagram of a typical bit latch and I O buffer which is the core of each of the four l O ports The bit latch one bit in the port s SFR is represented as a type D flip flop which will clock in a value from the internal bus in response to a write to latch signal from the CPU The Q output of the flip flop is placed on the internal bus in response to a read latch signal from the CPU The level of the port pin itself is placed on the internal bus in response to a read pin signal from the CPU Some instructions that read from a port i e from the corresponding port SFR PO P2 P3 activate the read latch signal while others activate the read pin signal Read Latch Int Bus Port Port Write Driver Pin to Circuit Latch MCS01822 Read Pin Figure 6 1 Basic Structure of a Port Circuitry Semiconductor Group 6 3 SIEMENS On Chip Peripheral Components C504 Port 1 2 and 3 output drivers have internal pullup FET s see figure 6 2 Each I O line can be used independently as an input or output To be used as an input the port bit must contain a one 1 that means for figure 6 2 Q 0 which turns off the output driver FET n1 Then for ports 1 2 and 3 the pin is pulled high by the internal pullups but can be pulled low by an external source When externally pulled low the port pins source current Z or J For this reason these ports are
15. COMP unit Semiconductor Group 6 65 SIEMENS On Chip Peripheral Components C504 For the monitoring of the sensor input signal timing in block commutation mode the signal transitions at INTO 2 can also generate an interrupt if enabled and a capture event at channel 0 of the CAPCOM unit compare timer 1 For emergency cases trap function of CTRAP input signal the six outputs CCx and COUTx can be put selectively to its inactive phase At the multi pole PWM modes of the C504 a change of the PWM output states active or inactive is triggered by compare timer 1 which is running either in operating mode 0 or 1 If its count value reaches 00004 the PWM output signal changes its state according a well defined state table The multi pole PWM modes are split up into three modes 4 pole multi channel PWM mode 4 PWM output signals 5 pole multi channel PWM mode 5 PWM output signals 6 pole multi channel PWM mode 6 PWM output signals 6 3 4 1 Special Function Register BCON The BCON register controls the selection of multi channel PWM modes It also contains the block commutation interrupt enable and status bit flag Special Function Register BCON Address D7 Reset Value 00H Bit No MSB LSB 7 6 5 4 3 2 1 0 D74 BEMh PWM1 PWMO EBCE BCERR BCEN BCM1 BCMO BCON Bit Function BCMP In multi channel PWM mode Machine polarity If BCMP is set and multi channel PWM mode is s
16. D CLK Zero Detector Stop Bit Shift gt Start Generation Data TX Control gt 16 TX Clock TI Send Baud Serial 21 Rate e Port Clock Interrupt 16 Sample RX Clock RI Load SBUF Start RX Control 1 to 0 Transition Detector 1FF Shift 1 l elector Input Shift Register 9Bits Shift Load T st SBUF gt DVA SBUF SZ RXD Read Internal Bus MCS02105 Figure 6 38a Serial Interface Mode 2 and 3 Functional Diagram Semiconductor Group 6 92 C504 On Chip Peripheral Components SIEMENS L8SZ0LON Po la seu ajduwes z gt 10 0819 4g 9 c 9019 XH E jeseg 9 u 9 ig dos Transmit ldiS 9pOW Ld9S Z epo ANAS 01 SUM x Figure 6 38b Serial Interface Mode 2 and 3 Timing Diagram 6 93 Semiconductor Group SIEMENS On Chip Peripheral Components C504 6 5 10 bit A D Converter The C504 includes a high performance high speed 10 bit A D Converter ADC with 8 analog input channels lt operates with a successive approximation technique and uses self calibration mechanisms for reduction and compensation of offset and linearity errors The A D converter provides the following features 8multiplexed input channels port 1 3 which can also be used as digital outputs inputs 10 bit resolution
17. Vcc 5 V 10 15 Vss 0 V T 0 to 70 C for the SAB C504 T 40 to 85 C for the SAF C504 C for port 0 ALE and PSEN outputs 100 pF C for all other outputs 80 pF Program Memory Characteristics Parameter Symbol Limit Values Unit 40 MHz clock Variable Clock 1 tere 3 5 MHz to 40 MHz min max min max ALE pulse width fu 35 2tac_ 15 ns Address setup to ALE tavLL 10 toro 15 ns Address hold after ALE fLLAX 10 toro 15 ns ALE low to valid instr in fiy 55 4torcL 45 ns ALE to PSEN fip 10 toro 15 ns PSEN pulse width Tope 60 Stac 15 ns PSEN to valid instr in foi 25 Store 50 ns Input instruction hold after PSEN fexix 0 0 ns Input instruction float after PSEN len 20 forie ns Address valid after PSEN ley 20 fee 5 ns Address to valid instr in favi 65 Stec 60 ns Address float to PSEN tazpL 5 5 ns Interfacing the C504 to devices with float times up to 25 ns is permissible This limited bus contention will not cause any damage to port O drivers Semiconductor Group 10 10 Device Specifications SIEMENS C504 AC Characteristics for C504 L40 C504 2R40 cont d External Data Memory Characteristics Parameter Symbol Limit Values Unit
18. WDCON CO e dowos wors wor swor Control Logic External HW Reset WDTREL MCS01771 Figure 8 1 Block Diagram of the Programmable Watchdog Timer Semiconductor Group 8 1 SIEMENS Fail Safe Mechanisms C504 Special Function Register WDTREL Address 86 Reset Value 00y Bit No MSB LSB 7 6 5 4 3 2 1 0 Bbg ADT Watchdog Timer Reload Register WDTREL H PSEL i CAM Bit Function WDTPSEL Watchdog timer prescaler select bit When set the watchdog timer is clocked through an additional divide by 16 prescaler WDTREL 6 0 Seven bit reload value for the high byte of the watchdog timer This value is loaded to WDTH when a refresh is triggered by a consecutive setting of bits WDT and SWDT Special Function Register WDCON Address C0y Reset Value XXXX 0000p Bit No MSB LSB 7 6 5 4 3 2 1 0 COH OWDS WDTS WDT SWDT WDCON Bit Function Not implemented Reserved for future use OWDS Oscillator Watchdog Timer Status Flag Set by hardware when an oscillator watchdog reset occured Can be set and cleared by software WDTS Watchdog Timer Status Flag Set by hardware when a Watchdog Timer reset occured Can be cleared and set by software WDT Watchdog Timer Refresh Flag Set to initiate a refresh of the watchdog timer Must be set directly before SWDT is set to prevent an unintentional refresh
19. if it is sorted You must bear the costs of transport For packing material that is returned to us unsorted or which we are not obliged to accept we shall have to invoice you for any costs in curred Components used in life support devices or systems must be expressly authorized for such purpose Critical components of the Semiconductor Group of Siemens AG may only be used in life support devices or systems with the express written approval of the Semiconductor Group of Siemens AG 1 Acritical component is a component used in a life support device or system whose failure can reasonably be expected to cause the failure of that life support device or system or to affect its safety or effectiveness of that device or system 2 Life support devices or systems are intended a to be implanted in the human body or b to support and or maintain and sustain hu man life If they fail it is reasonable to assume that the health of the user may be endangered SIEMENS rans Table of Contents Page 1 Introduction s sa netran tanaan Eaa e Maa Eaa a dE S Ea Ea H aa Eoi a 1 1 2 Fundamental Structure ooocooooooconcn 2 1 2 1 CRU NP AAA ES SAA ASAS A AE 2 2 2 2 AAN acr sca otc ior nhe Pear en gra SOR e E REV us teen Gy ache 2 4 3 Memory Organization eeeeeeeeeeeeeee eene 3 1 3 1 Program Memory Code Space ooococoococcoco eller 3 2 3 2 Data Memory Data Space 0 000 else 3 2 3 3 General Purpose Register
20. 1 and 3 lines are listed in table 6 2 Table 6 2 Alternate Functions of Port 1 and 3 Port Second third Port Function Function Type ANO T2 C Analog input channel 0 input to counter 2 AN1 T2EX C Analog input channel 1 capture reload trigger of timer 2 up down count P1 2 AN2 CCO E Analog input channel 2 CAPCOM channel 0 input output P1 3 ANS COUTO E Analog input channel 3 CAPCOM channel 0 output P1 4 CC1 D CAPCOM channel 1 input output P1 5 COUT1 D CAPCOM channel 1 output P1 6 CC2 D CAPCOM channel 2 input output P1 7 COUT2 D CAPCOM channel 2 output P3 0 RxD B Serial port s receiver data input asynchronous or data input output synchronous P3 1 TxD B Serial port s transmitter data output asynchronous or data clock output synchronous P3 2 AN4 INTO C Analog input channel 4 External interrupt O input timer O gate control P3 3 AN5 INTT C Analog input channel 5 External interrupt 1 input timer 1 gate control P3 4 AN6 TO C Analog input channel 6 Timer 0 external counter input P3 5 ANT7 Tl C Analog input channel 7 Timer 1 external counter input P3 6 WR INT2 B External data memory write strobe External interrupt 2 input P3 7 RD B External data momory read strobe Prior to the description of the port type specific port configurations the general port structure is described in the next section Semiconductor Group 6 2 SIEMENS On Chip Peripheral Components C504
21. A Port 0 tam g nx tavov Port 2 P2 0 P2 7 or A8 A15 from DPH A8 A15 from PCH MCT00097 Data Memory Read Cycle Semiconductor Group 10 12 SIEMENS Device Specifications C504 z Iwan ALE PSEN 3 uw S wi wn tawx t AVLL fwHax A0 A7 from PCL r c tawwe Port 2 P2 0 P2 7 or A8 A15 from DPH A8 A15 from PCH A0 A7 from Ri or DPL Port 0 Instr IN MCT00098 Data Memory Write Cycle MCT00033 External Clock Cycle Semiconductor Group 10 13 SIEMENS Device Specifications C504 10 7 ROM Verification Characteristics for C504 2R ROM Verification Mode 1 Parameter Symbol Limit Values Unit min max Address to valid data Lavov 10 foro ns P1 0 P1 7 P2 0 P2 4 Port 0 P2 7 ENABLE MCTO00049 Address P1 0 P1 7 2 AO A7 Inputs P2 5 P2 6 PSEN Vss P2 0 P2 4 A8 A12 ALE EA Vi Data P0 0 PO 7 DO D7 RESET Vss ROM Verification Mode 1 Semiconductor Group 10 14 SIEMENS Device Specifications C504 ROM Verification Mode 2 Parameter Symbol Limit Values Unit min typ max ALE pulse width Lawo 2 fcc ns ALE period Lacy 12 tac ns Data valid after ALE Lova 4 toe ns Data stable after ALE Losa 8 facic ns P3 5 setup to ALE low tas toLcL ns Oscillat
22. Low time teLcx 20 foo feucx ns Rise time lech 20 ns Fall time TcHcL 20 ns Semiconductor Group 10 7 Device Specifications C504 SIEMENS 10 5 AC Characteristics for C504 L24 C504 2R24 Voc 5 V 10 15 Vss 0 V T 0 to 70 C for the SAB C504 T 40 to 85 C for the SAF C504 C for port 0 ALE and PSEN outputs 100 pF C for all other outputs 80 pF Program Memory Characteristics Parameter Symbol Limit Values Unit 24 MHz clock Variable Clock l fg c 3 5 MHz to 24 MHz min max min max ALE pulse width la 43 E 2fac 40 ns Address setup to ALE AVLL 17 faci 25 ns Address hold after ALE f Lax 17 fec 25 ns ALE low to valid instr in fw 80 4toc 87 ns ALE to PSEN fuel 22 faic 20 ns PSEN pulse width Tu 95 3toc 30 ns PSEN to valid instr in foy 60 Stoic 65 ns Input instruction hold after PSEN tpxix 0 0 ns Input instruction float after PSEN tpxiz 32 faic 10 ns Address valid after PSEN texav 37 E tac 5 ns Address to valid instr in tayiy 148 Stec 60 ns Address float to PSEN tizi 0 0 ns Interfacing the C504 to devices with float times up to 37 ns is permissible This limited bus contention will not cause any damage to port O drivers Semiconductor Group 10 8 SIEMENS Device Specifications
23. OV F1 P D24 CP2L 00H 7 6 5 4 3 2 1 0 1 X means that the value is undefined and the location is reserved 2 Bit addressable special function registers 3 SFR is located in the mapped SFR area For accessing this SFR bit RMAP in SFR SYSCON must be set Semiconductor Group SIEMENS Memory Organization C504 Table 3 2 Contents of the SFRs SFRs in numeric order of their addresses cont d Addr Register Content Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit 0 after Reset D34 CP2H XXXX 1 0 XX00p D44 CMP2L 00H of 6 5 4 3 2 1 D5j CMP2H XXXX A XX00p D6y CCIE 00H ECTP ECTC CC2 CC2 CC1 CC1 CCO CCO FEN REN FEN REN FEN REN D74 BCON 00H BCMP PWM1 PWMO EBCE BCERR BCEN BCM1 BCMO BCEM D84 ADCONO XX00 ADC BSY ADM MX2 MX1 MXO 0000p D94 ADDATH 00y 9 7 6 5 4 29 2 DAy ADDATL 00XX 1 XXXXB DCH ADCON1 0O1XX j ADCL1 ADCLO MX2 MX1 MXO X000p DEW CCPL 00H 6 m 4 3 2 1 0 DFy CCPH 00H 6 5 4 3 2 1 0 E0y ACC 00H 6 15 4 3 2 1 0 Ely CT1ICON 0001 CTM ETRP STE1 CT1 CT1R CLK2 CLK1 CLKO 0000p RES E2y COINI FFH COUT COUT COUT CC2 COUT CC1l COUT CCOl 3l XI 2l 11 Ol ESH CMSELO 00y CMSEL CMSEL CMSEL CMSEL CMSEL CMSEL CMSEL CMSEL 13 12 11 10 03 02 01 00 E44 CMSEL1 00y 0 0 0 0 CMSEL CMSEL CMSEL CMSEL 23 22 21
24. Ol ol z o o e e Zz o p e e z Es gt lt e m z o o O o Zz as Ai ja E S o ITCON 2 one l IENO 2 ITCON 3 A D Converter IADC ADCON 5 FADC 3 Bit addressable IENT O 4 Request Flag is cleared by hardware C504 Low Priority Timer 0 Overflow TFO High Priority TCON 5 IENO 1 Timer 1 Overflow eo TCON 7 MCS02576 Figure 7 1a Interrupt Request Sources Part 1 Semiconductor Group 7 2 SIEMENS Interrupt System C504 P3 6 WR INT2 lt 7 Low Priority High Priorit t ITCON 7 ITCON 4 E 6 ITCON 5 ccor He 21 P1 2 AN2 CC0 CCIEO 0 EUR 1 RN CCIEO 1 P1 4 CC1 E CCIEO 2 UE CC1FEN CCIR 3 IEN1 4 CCIEO 3 CC2R e P1 6 CC2 CCIEO 4 EA 5 den CCIEO 5 CT1FP Compare Timer 1 GCIR ror gt 1 7 Interrupt CCIE 7 ECT CTIFC o IEN1 5 CCIR 6 TECTC Compare Timer 2 CCIE 6 Interrupt CT2P CT2CON 7 ECT TRF a IEN1 3 CCU Emergency TRONS ETRP 21 a Interrupt CTICON 6 ECEM EE Eu J Bit addressable IENT 2 BCON 3 Request Flag is EBCE cleared by hardware BCON 4 MCB02596 a o 5 2 pun mo D E lt o 2 o o pa o 2 E o o MX o Pun 2 Ez o o o Figure 7 1b Interrupt Request Sources Part 2 Semiconductor Group 7 3 Interrupt System C504 SIEMENS 7 1 Interrupt Structure A co
25. Request Flags Interrupt Sources Request SFR Byte Bit Flags Address Address External Interrupt 0 IEO TCON 88y 88H A D converter IADC IADC ADCONO D8g DDH Timer O Interrupt TFO TCON 88H 8Dy External Interrupt 1 IE1 TCON 88H 8By Timer 1 Interrupt TF1 TCON 88H 8Fy Serial Channel RI SCON 98H 98H TI SCON 98H 99h Timer 2 Interrupt TF2 T2CON C8H CFy EXF2 T2CON C8y CEH External Interrupt 2 IT2 ITCON 9AH 9Ay 7 Capture Compare Match Interrupt CCxR CCIR ESH E514 0 2 4 CCxF CCIR E5H E5H 1 3 5 Compare Timer 1 Interrupt CT1FP CCIR E5H ESH 7 CT1FC CCIR ESH E5y 6 Compare Timer 2 Interrupt CT2P CT2CON D2y D2y 7 CCU Emergency Interrupt TRF TRCON E7y E7H 6 BCERR BCON D7H D7y 3 Semiconductor Group 7 9 SIEMENS Interrupt System C504 7 4 How Interrupts are Handled The interrupt flags are sampled at S5P2 in each machine cycle The sampled flags are polled during the following machine cycle If one of the flags was in a set condition at S5P2 of the preceeding cycle the polling cycle will find it and the interrupt system will generate a LCALL to the appropriate service routine provided this hardware generated LCALL is not blocked by any of the following conditions 1 An interrupt of equal or higher priority is already in progress 2 The current polling cycle is not in the final cycle of the instruction in progress 3 The instruction in progress is RETI or any write access to registers IEO IE1 or IPO IP1 Any of these three conditions will bl
26. Sources and vector addresses 7 4 CREER e e in ted 2 3 3 7 POr tata tas dass ice 3 4 3 7 Else site did exeat 2 3 3 7 IP essen nnn 3 4 3 7 7 8 Fast power on reset 5 2 8 7 EO ae tree r E o PS 3 6 Featutes oo 1 2 A t tte ec tte ue s 3 6 Functional units 1 1 ITZ eee nn nn nn 3 6 Fundamental structure 2 1 ITCON pi sieaas as a 3 4 3 6 7 13 G L GATE oegi eee 3 6 6 19 Logic symbol 1 3 General purpose registers 32 M CIED nu ius ess ba d toad cass 3 6 9 1 MOS oye e RE e dE 3 6 6 19 cae Tr LR 3 6 9 1 IV rese treu ard evt dte 3 6 6 19 H Memory map xv X Res 3 1 Hardware reset o o o o 5 1 Memory organization 3 1 I Data memory oves pk XH ed Ox 3 2 AAA cies oo as 6 1 to 6 15 General purpose registers me liz MEER ers A EN ai 3 6 MeMO sius oci ade 91 IDE T I3 S s aiu i ara por hs e dpt 3 6 Programi MEMO so deseas 3 2 HEIP e RAE dU eed EP M E Sd ME oso Sees gg AE A SE EDS suu Er A O ME C pup IgE T anii OPPRERPPITS DE REESE 3 6 Semiconductor Group 11 3 SIEMENS Index C504 O Behaviour of external pins 9 3 Oscillator watchdog 8 5 General description 9 1 Behaviour at reset 5 2 Idle mode 9 3 Block diagram tes datis qu 8 6 Entering essen 9 4 Fast power on reset 8 7 Functionality 0 0 sees 9 3 Functionality ts desd 8 5
27. Structure C504 Special Function Register PSW Address DO Reset Value 00y Bit No MSB LSB D7y D6y D5y D4y D3y D2y Diy DOy DOy CY AC FO RS1 RSO OV F1 P PSW Bit Function CY Carry Flag Used by arithmetic instruction AC Auxiliary Carry Flag Used by instructions which execute BCD operations FO General Purpose Flag RS1 Register Bank select control bits RSO These bits are used to select one of the four register banks RS1 RSO Function 0 0 Bank 0 selected data address 00y4 07y 0 1 Bank 1 selected data address 08y 0F y 1 0 Bank 2 selected data address 104 17y 1 1 Bank 3 selected data address 18y 1Fy OV Overflow Flag Used by arithmetic instruction F1 General Purpose Flag P Parity Flag Set cleared by hardware after each instruction to indicate an odd even number of one bits in the accumulator i e even parity B Register The B register is used during multiply and divide and serves as both source and destination For other instructions it can be treated as another scratch pad register Stack Pointer The stack pointer SP register is 8 bits wide It is incremented before data is stored during PUSH and CALL executions and decremented after data is popped during a POP and RET RETI execution i e it always points to the last valid stack byte While the stack may reside anywhere in the on chip RAM the stack pointer is initialized to 074 after
28. TLO are used to specify the high byte and the low byte of timer 0 TH1 and TL1 for timer 1 respectively The operating modes are described and shown for timer O If not explicitly noted this applies also to timer 1 Semiconductor Group 6 17 SIEMENS On Chip Peripheral Components C504 Special Function Register TCON Address 88 Bit No 88H MSB LSB 7 6 5 4 3 2 1 0 8FH 8EH 8DH 8CH 8By 8AH 89H 88H TF1 TR1 TFO TRO IE1 IT1 IEO ITO The shaded bits are not used in controlling timer counter 0 and 1 Reset Value 00y TCON Bit Function TRO Timer O run control bit Set cleared by software to turn timer counter 0 ON OFF TFO Timer 0 overflow flag Set by hardware on timer counter overflow Cleared by hardware when processor vectors to interrupt routine TR1 Timer 1 run control bit Set cleared by software to turn timer counter 1 ON OFF TF1 Timer 1 overflow flag Set by hardware on timer counter overflow Cleared by hardware when processor vectors to interrupt routine Semiconductor Group 6 18 SIEMENS On Chip Peripheral Components C504 Special Function Register TMOD Address 89 Reset Value 00y Bit No MSB LSB 7 6 5 4 3 2 1 0 894 GATE C T M1 MO GATE C T M1 MO TMOD MAA JF Timer 1 Control Timer O Control Bit Function GATE Gating control When set timer counter x is enabled only while INT x pin is
29. Termination ooooooooo 9 4 Oca ia 2 3 3 7 Power down mode 9 5 OWDS 0 cece eee esee 3 7 8 2 Entering 6 scene 9 5 P External wake up timing 9 6 P 2 3 3 7 Functionality 00m iron 9 5 PO A A ee MON 3 4 3 6 Termination 20 1 9 us ao Dorn ts x ats 9 6 NR cd ena es 3 4 3 6 Registers PCON PCON1 9 1 9 2 P1ANA 3 4 3 6 6 1 6 105 Program memory bra duel bu gei AY 3 2 COMMERCIO EP VM 3 4 3 6 Protected ROM verifiy timimg 4 9 c NM TONO EUR 34 8972 FSs ee SET P3ANA ooo 3 4 3 7 6 1 6 105 i E E ps Package information 10 17 E MU IE TOUS Pu ate PADO eras ass e ios 3 7 7 8 Ed HERI Ur 37 a Parallel I O CAPO Ga De O od B2 eni exscr aid 3 7 7 7 POG ise due A Ok da 3 7 7 8 A IEEE 37 nj WO ia 9 5 6 07 PCON aa cel x di PN fa Ye d 3 4 3 5 3 6 6 81 9 1 PWM1 o 3 8 6 67 PARO dE frente fa 3 7 7 7 POONT1 z nsi mE 3 5 3 6 9 2 PKA esu echan 3 7 7 7 ARMS ERE TEE TE 3 7 7 8 PX2 37 7 8 n sp PNE Qum fade rote i ala um tut ss DEL Sos re MUS SER E ERE 36 91 A ur See EE 3 6 9 1 RBS eee eee eee 3 6 6 79 6 80 Pin configuration 1 4 RC2H AAA 3 5 3 7 6 28 Pin definitions to 1 4 1 5 to O AS 3 5 3 7 6 28 Porseni nit uere ane 6 1 to 6 15 ROEK aaae a o aa AEE S 3 7 6 25 Alternate functions 6 2 o 3 7 Basic structure 6 3 Recommended oscillator circuits
30. Watchdog Status Flag WDTS If the software fails to clear the watchdog in time an internally generated watchdog reset is entered at the counter state 7FFCy The duration of the reset signal then depends on the prescaler selection either 8 or 128 cycles This internal reset differs from an external one in so far as the Watchdog Timer is not disabled and bit WDTS is set The WDTS is a flip flop which is set by a Watchdog Timer reset and can be cleared by an external hardware reset Bit WDTS allows the software to examine from which source the reset was activated The bit WDTS can also be cleared by software Semiconductor Group 8 4 SIEMENS Fail Safe Mechanisms C504 8 2 Oscillator Watchdog Unit The oscillator watchdog unit serves for three functions Monitoring of the on chip oscillator s function The watchdog supervises the on chip oscillator s frequency if it is lower than the frequency of the auxiliary RC oscillator in the watchdog unit the internal clock is supplied by the RC oscillator and the device is brought into reset if the failure condition disappears i e the on chip oscillator has a higher frequency than the RC oscillator the part executes a final reset phase of typ 1 ms in order to allow the oscillator to stabilize then the oscillator watchdog reset is released and the part starts program execution again Fast internal reset after power on The oscillator watchdog unit provides a clock supply for the reset b
31. additional strong pullups p1 to emit 1 s for the entire external memory cycle instead of the weak ones p2 and p3 used during normal port activity Read Latch Addr Control Voc Internal Pull Up Arrangement Int Bus Port Pin Write to Latch Read Pin MCS02123 Figure 6 5 Port 2 Circuitry If no external bus cycles are generated using data or code memory accesses port 0 can be used for I O functions Note during MOVX accesses to the internal XRAM no external bus cycles are generated Semiconductor Group 6 7 SIEMENS On Chip Peripheral Components C504 6 1 3 Detailed Output Driver Circuitry In fact the pullups mentioned before and included in figure 6 2 6 4 and 6 5 are pullup arrangements The differences of the port types available in the C504 is described in the next sections 6 1 3 1 Type B Port Driver Circuitry Figure 6 6 shows the output driver circuit of the type B multifunctional digital I O port lines The basic circuitry of these ports is shown in figure 6 4 The pullup arrangement of type B port lines has one n channel pulldown FET and three pullup FETs Delay 2 Osc Periodes Mec l J L 21 pi cJ p24 p Port e e e o Pin 0 n1 v Vss Input Data 1 read pin s MCS01824 Figure 6 6 Driver Circuit of Type B Port Pins The pulldown FET n1 is of n channel type It i
32. and the switched CCx COUTx active phase signal can be identical or inverted Compare Timer 1 Mode 0 Compare Timer 2 Output Signal COINI Bit 1 FAT TUUUNUUUL i Active Phase Compare Timer 1 Mode 0 Compare Timer 2 Output Signal CCx COUTx CCx COUTx Bit CMSELx 3 1 Compare timer 2 transitions in active phase at COUTx COINI Bit 0 LAA MCTO2610 Figure 6 30 Compare Timer 2 Controlled Active Phase of the Multi Channel PWM Modes with CMSELx 3 1 Semiconductor Group 6 70 SIEMENS On Chip Peripheral Components C504 6 3 4 3 Block Commutation PWM Mode In block commutation mode the INTO 2 inputs are sampled once each processor cycle If the input signal combination at INTO 2 changes its state the outputs CCx and COUTx are set to their new state according table 6 9 Table 6 9 Block Commutation Control Table Mode INTO INT2 CCO CC2 COUTO COUT2 BCM1 BCMO Inputs Outputs Outputs INTO INT INT2 CCO CC1 CC2 COUTO COUT1 COUT2 Rotate left 1 0 0 0 inactive inactive inactive inactive inactive inactive Rotate right 1 4 1 1 inactive inactive inactive inactive inactive inactive Rotate left 1 0 1 inactive inactive active active inactive inactive 1 0 0 inactive active inactive active inactive inactive 1 1 0 inactiv
33. as input In this configuration only the weak pullup FET p2 is active which sources the current Ji If in addition the pullup FET p3 is activated a higher current can be sourced 1 Thus an additional power consumption can be avoided if port pins are used as inputs with a low level applied However the driving capability is stronger if a logic high level is output The described activating and deactivating of the four different transistors translates into four states the pins can be input low state IL p2 active only input high state IH steady output high state SOH p2 and p3 active forced output high state FOH p1 p2 and p3 active output low state OL n1 active If a pin is used as input and a low level is applied it will be in IL state if a high level is applied it will switch to IH state If the latch is loaded with O the pin will be in OL state If the latch holds a 0 and is loaded with 1 the pin will enter FOH state for two cycles and then switch to SOH state If the latch holds a 1 and is reloaded with a 1 no state change will occur At the beginning of power on reset the pins will be in IL state latch is set to 1 voltage level on pin is below of the trip point of p3 Depending on the voltage level and load applied to the pin it will remain in this state or will switch to IH SOH state If it is used as output the weak pull up p2 will pull the voltage level at the pin above
34. at the XTAL pins and pullup resistors on the port 0 lines Semiconductor Group 4 8 SIEMENS External Bus Interface C504 4 7 2 Protected ROM Mode If the ROM s protected the ROM verification mode 2 as shown in figure 4 4 is used to verify the content of the ROM The detailed timing characteristics of the ROM verification mode is shown in the AC specifications chapter 10 RESET AN 1 ALE Pulse after Reset Data for Data for Data for Data for Addr 0 Addr 2 _ Addr X 16 1 Addr X 16 Addr X 16 41 Low Verify Error Hihg Verify OK Inputs ALE Ks PSEN EA Ya RESET MCTO2594 Figure 4 4 ROM Verification Mode 2 ROM verification mode 2 is selected if the inputs PSEN EA and ALE are put to the specified logic levels With RESET going inactive the ROM verification mode 2 sequence is started The C504 2R outputs an ALE signal with a period of 12 to and expects data bytes at port 0 The data bytes at port O are assigned to the ROM addresses in the following way 1 Data Byte content of internal ROM address 0000y 2 Data Byte content of internal ROM address 0001 y 3 Data Byte content of internal ROM address 00024 16 Data Byte content of internal ROM address 000FH The C504 2R does not output any address information during the ROM verification mode 2 The first data byte to be verified is always the byte which is assigned to the internal ROM address 0000H and must be put onto the data bus with the fall
35. bit time in the other modes in any serial reception exception see SM2 RI must be cleared by software Semiconductor Group 6 80 SIEMENS On Chip Peripheral Components C504 6 4 3 Baud Rates There are several possibilities to generate the baud rate clock for the serial interface depending on the mode in which it is operated To clearify the terminology something should be said about the differences between baud rate clock and baud rate The serial interface requires a clock rate which is 16 times the baud rate for the internal synchronization Therefore the baud rate generators have to provide a baud rate clock to the serial interface which there divided by 16 results in the actual baud rate However all formulas given in the following section are already include the factor and calculate the final baud rate The baud rate generation is further controlled by bit SMOD which is located in SFR PCON Special Function Register PCON Address 875 Reset Value 000X0000g Bit No MSB LSB 7 6 5 4 3 2 1 0 874 SMOD PDS IDLS GF1 GFO PDE IDLE PCON The functions of the shaded bits are not described in this section Symbol Function SMOD Baud rate double bit When set the baud rate of the serial channel in mode 1 2 3 is doubled Mode 0 The baud rate in mode 0 is fixed Mode 0 baud rate oscillator frequency 12 fosc 12 Mode 2 The baud rate in mode 2 depends
36. by 16 counter not to the WRITE to SBUF signal The transmission begins with activation of SEND which puts the start bit at TXD One bit time later DATA is activated which enables the output bit of the transmit shift register to TXD The first shift pulse occurs one bit time after that As data bits shift out to the right zeroes are clocked in from the left When the MSB of the data byte is at the output position of the shift register then the 1 that was initially loaded into the 9th position is just to the left of the MSB and all positions to the left of that contain zeroes This condition flags the TX control unit to do one last shift and then deactivate SEND and set TI This occurs at the 10th divide by 16 rollover after WRITE to SBUF Reception is initiated by a detected 1 to 0 transition at RXD For this purpose RXD is sampled at a rate of 16 times whatever baud rate has been established When a transition is detected the divide by 16 counter is immediately reset and 1FFy is written into the input shift register and reception of the rest of the frame will proceed The 16 states of the counter divide each bit time into 16ths At the 7th 8th and 9th counter states of each bit time the bit detector samples the value of RXD The value accepted is the value that was seen in at latest 2 of the 3 samples This is done for the noise rejection If the value accepted during the first bit time is not 0 the receive circuits are reset and t
37. by hardware When the compare timer 2 period and compare registers are initialized after reset bit STE2 must also be set to enable the shadow latch transfer when compare timer 2 is started the first time Note Read operations with the compare timer 2 period and compare registers always access the shadow registers and not the real registers because of capture mode Semiconductor Group 6 60 SIEMENS On Chip Peripheral Components C504 Compare Timer 2 Control Register CT2CON The 10 bit compare timer 2 is controlled by the bits of the CT2CON register With this register the count mode the timer input clock rate and the compare timer reset function is controlled Special Function Register CT2CON Address C1 y Reset Value 00010000g Bit No MSB LSB 6 5 4 3 2 1 0 Ciy CT2P ECT2O STE2 CT2RES CT2R CLK2 CLK1 CLKO CT2CON Bit Function CT2P Compare timer 2 period flag When the compare timer 2 value matches with the compare timer 2 period register value bit CT2P is set If the compare timer 2 interrupt is enabled the setting of CT2P will generate an compare timer 2 interrupt Bit CT2P must be cleared by software ECT2O Enable compare timer 2 output When ECT20 is cleared and compare timer 2 is running output COUTS is put into the logic state as defined by bit COUTSI which is located in SFR COINI 6 When ECT20 is set and compare timer 2 is running the compare timer 2 output COUTS is e
38. case Semiconductor Group 6 84 SIEMENS On Chip Peripheral Components C504 6 4 4 Details about Mode 0 Serial data enters and exists through RXD TXD outputs the shift clock 8 data bits are transmitted received LSB first The baud rate is fixed at fosc 12 Figure 6 36a shows a simplyfied functional diagram of the serial port in mode 0 The associated timing is illustrated in figure 6 36b Transmission is initiated by any instruction that uses SBUF as a destination register The WRITE to SBUF signal at S6P2 also loads a 1 into the 9th position of the transmit shift register and tells the TX control block to commence a transmission The internal timing is such that one full machine cycle will elapse between WRITE to SBUF and activation of SEND SEND enables the output of the shift register to the alternate output function line of P3 0 and also enables SHIFT CLOCK to the alternate output function line of P3 1 SHIFT CLOCK is low during S3 S4 and S5 of every machine cycle and high during S6 S1 and S2 At S6P2 of every machine cycle in which SEND is active the contents of the transmit shift register are shifted to the right one position As data bits shift out to the right zeroes come in from the left When the MSB of the data byte is at the output position of the shift register then the 1 that was initialy loaded into the 9th position is just to the left of the MSB and all positions to the left of that contain zeroes This
39. characteristics The A D converter calibration is implemented in a way that a user program which executes A D conversions is not affected by its operation Further the user program has no control on the calibration mechanism The calibration itself executes two basic functions Offset calibration compensation of the offset error of the internal comparator Linearity calibration correction of the binary weighted capacitor network The A D converter calibration operates in two phases calibration after a reset operation and calibration at each A D conversion The calibration phases are controlled by a state machine in the A D converter This state machine executes the calibration phases and stores the calibration results dynamically in a small calibration RAM After a reset operation the A D calibration is automatically started This reset calibration phase which takes 3328 fapc clocks alternating offset and linearity calibration is executed Therefore at 12 MHz oscillator frequency and with the default after reset prescaler value of 8 a reset calibration time of approx 4 4 ms is reached For achieving a proper reset calibration the fApc prescaler value must satisfy the condition fapc max 2 MHz If this condition is not met at a specific oscillator frequency with the default prescaler value after reset the fApc prescaler must be adjusted immediately after reset by setting bits ADCL1 and ADCLO im SFR ADCON 1 to a suitable value
40. chip peripherals timer 0 timer 1 timer 2 serial interface A D converter and capture compare unit and four interrupts may be triggered externally P1 1 T2EX P3 2 INTO P3 3 INTT and P3 6 INT2 If the capture compare unit is not used in an application its capture features can be used to provide additional 3 external interrupt inputs An additional non maskable 13th interrupt is reserved for the external wake up from power down mode feature Compared with the C501 the functionality of the external interrupts is extended In the edge triggered mode of the external interrupts it is possible to select between a falling a rising or a falling and rising edge interrupt trigger condition The capture compare unit provides four new interrupt vectors an interrupt vector for the compare timer 1 reset count direction change event an interrupt vector for the compare timer 2 reset event an interrupt vector for a capture or compare match event and an interrupt vector for two emergency conditions of the CAPCOM unit trap and block commutation error Figure 7 1a and 1b give a general overview of the interrupt sources and illustrate the request and control flags which are described in the next sections Semiconductor Group 7 1 SIEMENS Interrupt System Timer 2 Overflow 12 IENO 3 T2CON 7 c u AHA EXF2 T2EX xev IENO 5 IE 6 T2CON 3 E p USART Sean aa IENO 4 AN a v B
41. condition flags the TX control block to do one last shift and then deactivate SEND and set TI Both of these actions occur at S1P1 of the 10th machine cycle after WRITE to SBUF Reception is initiated by the condition REN 1 and R1 0 At S6P2 of the next machine cycle the RX control unit writes the bits 1111 1110 to the receive shift register and in the next clock phase activates RECEIVE RECEIVE enables SHIFT CLOCK to the alternate output function line of P3 1 SHIFT CLOCK makes transitions at S3P1 and S6P1 of every machine cycle At S6P2 of every machine cycle in which RECEIVE is active the contents of the receive shift register are shifted to the left one position The value that comes in from the right is the value that was sampled at the P3 0 pin at S5P2 of the same machine cycle As data bit comes in from the right 1s shift out to the left When the 0 that was initially loaded into the rightmost position arrives at the leftmost position in the shift register it flags the RX control block to do one last shift and load SBUF At S1P1 of the 10th machine cycle after the write to SCON that cleared RI RECEIVE is cleared and RI is set Semiconductor Group 6 85 SIEMENS On Chip Peripheral Components C504 Internal Bus Write to SBUF RXD P3 0 Alt Output Function TXD P3 1 Alt Output Serial Function Port Interrupt REN Al x RI Receive RX Control RXD P3 0 Alt Input Function L
42. gt gt E e 3 2 gt CC 4 50 AE aa oS 333 cc 7 12 5 tos OF 0 CC content of the CCxH CCxL compare registers CCP content of the CCPH CCPL period register CT1OF content of the CT1OFH CTIOFL offset registers MCTO2601 Figure 6 21 Compare Timer 1 Mode 0 In the example above compare timer 1 counts from 0000y up to 00074 value stored in CCPH CCPL The offset registers CT1OFH CT1OFL have a value of 00004 If programmed in compare mode two output signals are assigned to the related CAPCOM channel x CCx and COUTx The mode select bits in the SFRs CMSELO and CMSEL1 define which of these two outputs will be Semiconductor Group 6 34 SIEMENS On Chip Peripheral Components C504 controlled by the CAPCOM channel In figure 6 21 only the CCx signal is referenced but the same or the inverted waveform can be generated at the COUTx outputs After reset all CCx COUTx pins are at high level driven by a weak pullup With the programming of the CMSEL1 or CMSELO registers all affected compare outputs are switched to push pull mode and start driving an initial level which is defined by the bits in SFR COINI In figure 6 21 the upper five waveforms are assigned to a CCx pin with the appropriate bit in COINI cleared while the lower five waveforms are assigned to a CCx pin with the appropriate bit in COINI set When the count value of the compare timer 1 is incremented and the new value matches with
43. high or low level Additionally in rotate right or rotate left mode a wrong follower condition according table 6 9 can cause the setting of BCERR see description of bit BCEM If the block commutation interrupt is enabled EBCE 1 the setting of BCERR will generate a CCU emergency interrupt BCERR must be reset by software BCEN Block commutation enable If BCEN is set the multi channel PWM modes of the CAPCOM unit as selected by the bits PWM1 PWMO are enabled for operation Before BCEN bit is set all required PWM compare outputs should be programmed to operate as compare outputs by writing the registers CMSEL1 CMSELO BCM1 Multi channel PWM mode output pattern selection BCMO Additionally to the bits PWM1 and PWMO these two control bits select the output signal pattern in all multi channel PWM modes The detailed signal pattern information is given in table 6 9 to table 6 12 BCM1 BCMO Function 0 0 Idle mode 0 1 1 Rotate right mode 1 0 Rotate left mode 1 Slow down mode Note When a multi channel PWM mode is initiated the first time after reset BCON must be written twice first write operation with bit BCEN cleared and all other bits set cleared as required BCM1 0 must be 0 0 for idle mode followed by a second write operation with the same BCON bit pattern of the first write operation but with BCEN set After this second BCON write operation compare timer 1 can be started setting CT1R
44. immediately the first instruction of the interrupt service routine will be executed in the third machine cycle which follows the write result cycle IADC must be reset by software Depending on the application typically there are three methods to handle the A D conversion in the C504 Software delay The machine cycles of the A D conversion are counted and the program executes a software delay e g NOPs before reading the A D conversion result in the write result cycle This is the fastest method to get the result of an A D conversion Polling BSY bit The BSY bit is polled and the program waits until BSY 0 Attention a polling JB instruction which is two machine cycles long possibly may not recognize the BSY 0 condition during the write result cycle in the continuous conversion mode A D conversion interrupt After the start of an A D conversion the A D converter interrupt is enabled The result of the A D conversion is read in the interrupt service routine If other C504 interrupts are enabled the interrupt latency must be regarded Therefore this software method is the slowest method to get the result of an A D conversion Depending on the oscillator frequency of the C504 and the selected divider ratio of the A D converter prescaler the total time of an A D conversion is calculated according figure 6 41 and table 6 14 Figure 6 43 on the next page shows the minimum A D conversion time in relation to the oscillator frequenc
45. in CAPCOM Operating Mode 1 riod CT1 CT10FF e alu ompare alue Offset ti lt O lt D o CT1 2 CTRAP MCTO2606 Figure 6 26 Trap Function of the CAPCOM Unit Semiconductor Group 6 43 SIEMENS On Chip Peripheral Components C504 6 3 2 8 CAPCOM Register The CAPCOM unit of the C504 contains several special function registers Table 6 6 gives an overview of the CAPCOM related registers Table 6 6 Special Function Registers of the CAPCOM Unit Unit Symbol Description Address CAPCOM CT1CON Compare timer 1 control register Ely Capture CCPL Compare timer 1 period register low byte DEy Compare CCPH Compare timer 1 period register high byte DFH Unit CT1OFL Compare timer 1 offset register low byte E6H CT1OFH Compare timer 1 offset register high byte E7y CMSELO Capture compare mode select register 0 ESH CMSEL1 Capture compare mode select register 1 E4y CCLO Capture compare register 0 low byte C2y CCHO Capture compare register 0 high byte C3H CCL1 Capture compare register 1 low byte C4y CCH1 Capture compare register 1 high byte C5H CCL2 Capture compare register 2 low byte C6H CCH2 Capture compare register 2 high byte C7y CCIR Capture compare interrupt request flag register E5y CCIE Capture compare interrupt enable register D6H COINI Compare output initialization register E2y TRCON Trap enable register CFy The following sections d
46. is generated when TRF is set TRF must be reset by software TREN5 TRENO Trap enable control bits Bits at even bit positions 0 2 4 are assigned to the CCx compare outputs Bits at odd bit positions 1 3 5 are assigned to the COUTx compare outputs TRENx 0 Compare channel output provides CAPCOM output signal in trap state TRENx 1 Compare channel output is enabled to set the logic level of the compare output CCx or COUTx in the trap state to a logic state as defined by the corresponding bits of the COINI register When writing TRENO 5 bit TRF should be set to 0 Otherwise setting TRENO 5 will generate a software trap interrupt Semiconductor Group 6 58 SIEMENS On Chip Peripheral Components C504 6 3 3 Compare COMP Unit Operation The Capture Compare Unit CCU of the C504 also provides an 10 bit Compare Unit COMP which operates as a single channel pulse generator with a pulse width modulated output signal This output signal is available at the output pin COUT3 of the C504 In the combined multi channel PWM modes and in burst mode of the CAPCOM unit the output signal of the COMP unit can also be switched to the output signals COUTx Figure 6 27 shows the block diagram and the pulse generation scheme of the COMP unit e g initial value of COUTS is set to 0 ATo CAPCOM Output Control Compare Registers COUTXI CMP2H CMP2L COINI 6 Y i Compare Timer 2 10 Bit Up Counter Control Registe
47. logic state 1 1 gt 0 Compare timer 1 is stopped and reset to 0000jj compare outputs are set to the logic state as defined in SFR COINI Note for capture mode Setting CT1R20 and CT1RES 1 after a capture event will destroy the value stored in the capture register CCx Therefore CT1RES should be set to 0 in capture mode Reason if CT1R20 and CT1RES 1 all shadow registers are transparent switched directly to the real registers Note When software power down mode is entered with CT1RES bit of SFR CT1CON set the compare timer 1 is reset after the execution of a wake up from power down mode procedure When CT1RES is cleared before software power down mode is entered and a wake up from power down mode procedure has been executed the compare timer 1 is not reset Depending on the state of bit CT1R at power down mode entry the compare timer 1 either stops CT1R20 or continues CT1R 1 counting after a wake up from power down mode procedure Further details of the power down mode are described in chapter 9 2 Semiconductor Group 6 46 SIEMENS On Chip Peripheral Components C504 Compare Timer 1 Period Register The compare timer 1 period registers CCPH and CCPL store the 16 bit value for the compare timer 1 count period CCPH holds the high byte of the 16 bit period value and CCPL holds the low byte If CCPH CCPL is written always shadow latches are loaded The content of these shadow latches is transferred to
48. low byte E6H 00H CT1OFH Compare timer 1 offset register high byte E7y 00H CMSELO Capture compare mode select register 0 E3y 00H CMSEL1 Capture compare mode select register 1 E44 00H COINI Compare output initialization register E2H FFH TRCON Trap enable control register CFy 00H CCLO Capture compare register 0 low byte C24 00H CCHO Capture compare register 0 high byte C3H 00H CCL1 Capture compare register 1 low byte C4y 00H CCH1 Capture compare register 1 high byte C5H 00H CCL2 Capture compare register 2 low byte C6H 00H CCH2 Capture compare register 2 high byte C7y 00H CCIR Capture compare interrupt request flag reg ESH 00H CCIE Capture compare interrupt enable register D6y 00H CT2CON Compare timer 2 control register Ciy 00010000 CP2L Compare timer 2 period register low byte D2y 00H CP2H Compare timer 2 period register high byte D3y XXXXXX00p CMP2L Compare timer 2 compare register low byte D4y 00H CMP2H Compare timer 2 compare register high byte D5y XXXXXX00p BCON _ Block commutation control register D7H 00H Watchdog WDCON Watchdog Timer Control Register COW XXXX0000p WDTREL Watchdog Timer Reload Register 86H 00H Power PCON Power Control Register 87H 000X0000p Save Mode PCON1 Power Control Register 1 88y OXXXXXXXg 9 1 Bit addressable special function registers 2 This special function register is listed repeatedly since some bits of it also belong to other functional blocks 3 X m
49. lwj Internal Clock MCB02578 Figure 8 2 Functional Block Diagram of the Oscillator Watchdog The frequency coming from the RC oscillator is divided by 5 and compared to the on chip oscillator s frequency If the frequency coming from the on chip oscillator is found lower than the frequency derived from the RC oscillator the watchdog detects a failure condition the oscillation at the on chip oscillator could stop because of crystal damage etc In this case it switches the input of the internal clock system to the output of the RC oscillator This means that the part is being clocked even if the on chip oscillator has stopped or has not yet started At the same time the watchdog activates the internal reset in order to bring the part in its defined reset state The reset is performed because clock is available from the RC oscillator This internal watchdog reset has the same effects as an externally applied reset signal with the following exceptions The Watchdog Timer Status flag Semiconductor Group 8 6 SIEMENS Fail Safe Mechanisms C504 WDTS is not reset the Watchdog Timer however is stopped and bit OWDS is set This allows the software to examine error conditions detected by the Watchdog Timer even if meanwhile an oscillator failure occured The oscillator watchdog is able to detect a recovery of the on chip oscillator after a failure If the frequency derived from the on chip oscillator is again higher than the reference th
50. mode 0 6 85 Operating mode 1 6 88 Operating mode 2and3 6 91 Reale S ics un Gnd os 6 79 SMOD Eo A ecu deren ois et asd ed 3 6 6 80 SMI uet erue riii i E 3 6 6 80 SM esa sida 3 6 6 80 SMOD cene ule eA 3 6 6 81 SPa a Ae A I A healing 2 3 3 4 3 6 Special Function Registers 3 3 Access with RMAP 3 3 Table address ordered 3 6 to 3 8 Table functional order 3 4 to 3 5 STET cse ie ida ea 3 8 6 44 6 45 STEZ Lao ae 3 7 6 61 SID Taste te eto netos ENS E 3 7 8 2 SYSCON 3 3 3 4 3 7 4 4 4 6 O 3 7 Td ae suec hee CNN OE WU 3 7 JB us eese ra in esha seeded 3 6 p ce EEUU EM 3 5 3 7 6 25 p dq A OR ee eee ee ee 3 6 6 28 TEMOD 1 ped a 3 5 3 7 6 26 A E 3 6 6 79 6 80 AAA v 3 7 6 25 TON sta ee 3 4 3 6 6 18 TUS A A A 3 6 A HEEL Ee 3 6 A eiue soU 3 7 6 25 6 27 THOSE 3 4 3 6 A A 3 4 3 6 AA O RH IDEE S 3 5 3 7 Mi bos dalt DE a IS 3 6 6 79 6 80 Timer counter o oooooo 6 16 Timer counter 0 and 1 6 17 to 6 23 Mode 0 13 bit timer counter 6 20 Mode 1 16 bit timer counter 6 21 Mode 2 8 bit rel timer counter 6 22 Semiconductor Group 11 5 Mode 3 two 8 bit timer counter 6 23 W Registers 6 18 to 6 19 Timer counter 2 6 24 to 6 29 16 bit auto reload mode 6 26 to 6 28 16 bit capture mode 6 29 Operating modes 6 24
51. mode the compare timer 2 output signal can be also switched to the CAPCOM output pins COUTO COUT1 and COUT3 In these modes the polarity of the modulated output signal at COUT2 0 can be inverted by setting bit COUTXI COINI 6 The COMP unit has five SFRs which are listed in table 6 7 Table 6 7 Special Function Registers of the COMP Unit Unit Symbol Description Address COMP CT2CON Compare timer 2 control register C1H Compare CP2L Compare timer 2 period register low byte D2H Unit CP2H Compare timer 2 period register high byte D3y CMP2L Compare timer 2 compare register low byte D4y CMP2H Compare timer 2 compare register high byte D5H The compare timer 2 period and compare registers store a 10 bit value organized in two bytes For proper synchronization purposes these registers are not written directly Each value of a write operation to these registers is stored in shadow latches The transfer of these shadow latches into the real registers is synchronized with the compare timer 2 value 000y and controlled by bit STE2 When the period or compare value is changed by writing the corresponding SFR the setting of bit STE2 CT2CON 5 enables the write transfer of the shadow registers into the real registers This shadow latch transfer happens when the compare timer 2 reaches the count value 000H the next time after STE2 has been set With the automatic transfer of the shadow latches to the real registers bit STE2 is reset
52. of a higher priority level goes active prior to S5P2 in the machine cycle labeled C3 in figure 7 2 then in accordance with the above rules it will be vectored to during C5 and C6 without any instruction for the lower priority routine to be executed Thus the processor acknowledges an interrupt request by executing a hardware generated LCALL to the appropriate servicing routine In some cases it also clears the flag that generated the interrupt while in other cases it does not then this has to be done by the user s software The hardware clears the external interrupt flags IENO and IEN1 only if they were transition activated The hardware generated LCALL pushes the contents of the program counter onto the stack but it does not save the PSW and reloads the program counter with an address that depends on the source of the interrupt being vectored too Execution proceeds from that location until the RETI instruction is encountered The RETI instruction informs the processor that the interrupt routine is no longer in progress then pops the two top bytes from the stack and reloads the program counter Execution of the interrupted program continues from the point where it was stopped Note that the RETI instruction is very important because it informs the processor that the program left the current interrupt priority level A simple RET instruction would also have returned execution to the interrupted program but it would have left the interrupt control
53. of the watchdog timer SWDT Watchdog Timer Start Flag Set to activate the Watchdog Timer When directly set after setting WDT a watchdog timer refresh is performed Semiconductor Group 8 2 SIEMENS Fail Safe Mechanisms C504 Immediately after start the Watchdog Timer is initialized to the reload value programmed to WDTREL 0 WDTREL 6 After an external HW reset an oscillator watchdog power on reset or a watchdog timer reset register WDTREL is cleared to 00y The lower seven bits of WDTREL can be loaded by software at any time Examples given for 12 and 24 MHz external oscillator frequency Table 8 1 Watchdog Timer Time Out Periods WDTREL Time Out Period Comments fosc 12 MHz fos 24 MHz 00H 65 535 ms 32 768 ms This is the default value 80H 14s 0 55 s Maximum time period 7Fy 512 us 256 us Minimum time period Starting the Watchdog Timer The Watchdog Timer can be started by software bit SWDT in SFR WDCON but it cannot be stopped during active mode of the device If the software fails to clear the watchdog timer an internal reset will be initiated The reset cause external reset or reset caused by the watchdog can be examined by software status flag WDTS in WDCON is set A refresh of the watchdog timer is done by setting bits WDT SFR WDCON and SWDT consecutively This double instruction sequence has been implemented to increase system security It must be noted howeve
54. on the value of bit SMOD in special function register PCON 871 If SMOD 0 which is the value on reset the baud rate is fos 64 If SMOD 1 the baud rate is foso 32 Mode 2 baud rate 25M0D 64x fos0c Modes 1 and 3 The baud rates in mode1 and 3 are determined by the timer overflow rate These baud rates can be determined by timer 1 or by timer 2 or by both one for transmit and the other for receive Semiconductor Group 6 81 SIEMENS On Chip Peripheral Components C504 6 4 3 1 Using Timer 1 to Generate Baud Rates When timer 1 is used as the baud rate generator the baud rates in modes 1 and 3 are determined by the timer 1 overflow rate and the value of SMOD as follows Modes 1 3 baud rate 28M0D 32x timer 1 overflow rate The timer 1 interrupt should be disabled in this application The timer itself can be configured for either timer or counter operation and in any of its 3 running modes In the most typical applications it is configured for timer operation in the auto reload mode high nibble of TMOD 0010B In that case the baud rate is given by the formula Modes 1 3 baud rate 29 9P 32xfos J 12x 256 TH1 One can achieve very low baud rates with timer 1 by leaving the timer 1 interrupt enabled and configuring the timer to run as a 16 bit timer high nibble of TMOD 0001B and using the timer 1 interrupt to do a 16 bit software reload Table 6 13 lists commonly used baud rates and how they can be obta
55. output signals with different initial logic states with burst mode disabled CMSELx3 0 and burst mode enabled CMSELx3 1 Generally the CCx outputs cannot operate in burst mode Optionally the signal at COUTx may have inverted polarity than the PWM signal which is available at pin COUTS Semiconductor Group 6 40 SIEMENS On Chip Peripheral Components C504 Depending on the corresponding initial compare output level bit in COINI either a low or high level for the non modulated state at the COUTx pins can be selected Burst mode can be enabled in both operating modes of the compare timer 1 The burst mode as shown in figure 6 25 is only valid if the block commutation mode of the CCU is disabled bit BCEN of SFR BCON cleared The modulation of the compare output signals at COUTx is switched on COUTS signal is switched to COUTx when the compare timer 1 content plus the value stored in the compare timer 1 offset register is equal or greater than the value stored in the compare register of CAPCOM channel x 6 3 2 6 CAPCOM Unit in Capture Mode The three channels of the CAPCOM unit can be individually programmed to operate in capture mode In capture mode each CAPCOM channel offers one capture input at the pins CCx Compare timer 1 runs either in operating mode 0 or 1 A rising or and falling edge at CCx will copy the actual value of the compare timer 1 into the compare capture registers Interrupts can be generated selectively at each transit
56. p3 s trip point after some time and p3 will turn on and provide a strong 1 Note however that if the load exceeds the drive capability of p2 Z the pin might remain in the IL state and provide a week 1 until the first O to 1 transition on the latch occurs Until this the output level might stay below the trip point of the external circuitry The same is true if a pin is used as bidirectional line and the external circuitry is switched from outpout to input when the pin is held at 0 and the load then exceeds the p2 drive capabilities If the load exceeds J the pin can be forced to 1 by writing a 0 followed by a 1 to the port pin Semiconductor Group 6 9 SIEMENS On Chip Peripheral Components C504 6 1 3 2 Type C Port Driver Circuitry Figure 6 7 shows the port driver circuit of the type C mixed digital analog l O port lines of the C504 The analog function is selected by the bits in the SFRs P1ANA and P3ANA Delay 2 Osc Periodes Vec A o Port i E l Pin Q e e n1 Enable Analog Input bits of SFR P1ANA or gt SFR P3ANA v Vss Input Data 1 read pin v To A D Converter MCS02580 Figure 6 7 Driver Circuit of Type C Port Pins Semiconductor Group 6 10 SIEMENS On Chip Peripheral Components C504 6 1 3 3 Type D Port Driver Circuitry The driver and control structure of the port pin
57. reset procedure after power on Figure 5 1 shows the power on sequence under control of the oscillator watchdog Normally the devices of the 8051 family enter their default reset state not before the on chip oscillator starts The reason is that the external reset signal must be internally synchronized and processed in order to bring the device into the correct reset state Especially if a crystal is used the start up time of the oscillator is relatively long typ 10 ms During this time period the pins have an undefined state which could have severe effects especially to actuators connected to port pins In the C504 the oscillator watchdog unit avoids this situation In this case after power on the oscillator watchdog s RC oscillator starts working within a very short start up time typ less than 2 microseconds In the following the watchdog circuitry detects a failure condition for the on chip oscillator because this has not yet started a failure is always recognized if the watchdog s RC oscillator runs faster than the on chip oscillator As long as this condition is detected the watchdog uses the RC oscillator output as clock source for the chip rather than the on chip oscillator s output This allows correct resetting of the part and brings also all ports to the defined state see figure 5 1 Under worst case conditions fast Voc rise time e g 1us measured from Vec 4 25 V up to stable port condition the delay between power on and the
58. sometimes called quasi bidirectional Read Latch cc Internal Pull Up Arrangement Int Bus Pin Write to a Latch MCS01823 Read Pin Figure 6 2 Basic Output Driver Circuit of Ports 1 2 and 3 Semiconductor Group 6 4 SIEMENS On Chip Peripheral Components C504 6 1 2 1 Port 0 Circuitry Port 0 in contrast to ports 1 2 and 3 is considered as true bidirectional because the port 0 pins float when configured as inputs Thus this port differs in not having internal pullups The pullup FET in the PO output driver see figure 6 3 is used only when the port is emitting 1 s during the external memory accesses Otherwise the pullup is always off Consequently PO lines that are used as output port lines are open drain lines Writing a 1 to the port latch leaves both output FETs off and the pin floats In that condition it can be used as high impedance input If port O is configured as general I O port and has to emit logic high level 1 external pullups are required Addr Data Ve Control Read Latch Port Pin Int Bus Write to Latch Read Pin MCS02434 Figure 6 3 Port 0 Circuitry Semiconductor Group 6 5 SIEMENS On Chip Peripheral Components C504 6 1 2 2 Port 1 and Port 3 Circuitry The pins of ports 1 and 3 are multifunctional They are port pins and also serve to implement special features as listed in table 6 2 Fi
59. system thinking an interrupt was still in progress In this case no interrupt of the same or lower priority level would be acknowledged 7 5 External Interrupts The external interrupts 0 1 and 2 can be programmed to be level activated or transition activated by setting or clearing bit ITO IT1 or IT2 respectively in register TCON or ITCON If ITx 0 x 2 0 or 1 external interrupt x is triggered by a detected low level at the INTx pin If ITx 1 external interrupt x is edge triggered Further in edge triggered mode two bits of the ITCON register define the type of signal transition for which the external interrupt inputs are sensitive Edge triggered interrupt can be activated for an interrupt input signal at the rising edge at the falling edge or at both signal transitions In edge triggered mode if successive samples of the INTx pin show a different logic level in two consequent machine cycles the corresponding interrupt request flag IEx in TCON ITCON is set Flag bit IEx 1 then requests the interrupt If the external interrupt O 1 or2 is level activated the external source has to hold the request active until the requested interrupt is actually generated Then it has to deactivate the request before the interrupt service routine is completed or else another interrupt will be generated The external timer 2 reload trigger interrupt request flag EXF2 will be activated by a negative transition at pin P1 1 T2bEX but only if bit EXEN2 i
60. the C504 basically consists of two phases an inactive phase and an active phase The inactive phase of a PWM output signal is defined by the bit in the register COINI A 1 in a bit location of COINI defines the high level of the corresponding PWM compare output signal as its inactive phase With a 0 in a bit location of COINI a low level is selected as inactive phase Output signals during the active phase An active phase of a compare output signal in multi channel PWM mode can be controlled either by the CAPCOM unit compare timer 1 or modulated by compare timer 2 The selection is done by bit CMSELx 3 see note below table 6 8 Figure 6 29 shows the different possibilities for controlling the active phase of a compare output signal using compare timer 1 Compare timer 1 may operate either in mode 0 or mode 1 When the multi channel PWM generation is in progress the duration of the active phase is always equal to two periods of compare timer 1 As shown in figure 6 29a a compare output signal CCx or COUTx of a CAPCOM channel is either at low or high level during the whole active phase when the value stored in the compare timer 1 offset registers CT1OFH CT1OFL and the value stored in the its compare registers CCHx CCLx is equal 0000H When the compare value is not equal 0000 y and less or equal the period value the active phase of the related compare output signal CCx or COUTx is controlled by the CAPCOM unit as shown in figure 6 29b S
61. the SAB 80C52 C501 the C504 incorporates a genuine 10 bit A D Converter a capture compare unit a XRAM data memory as well as some enhancements in the Timer 2 and Fail Save Mechanism Unit Figure 2 1 shows a block diagram of the C504 igital 1 0 igital 1 0 og Inputs igital 1 0 igital 1 0 og Inputs Capture Compare Unit A D Converter 10 Bit Emulation Support Logic MCB02591 Figure 2 1 Block Diagram of the C504 Semiconductor Group 2 1 SIEMENS Fundamental Structure C504 2 1 CPU The C504 is efficient both as a controller and as an arithmetic processor It has extensive facilities for binary and BCD arithmetic and excels in its bit handling capabilities Efficient use of program memory results from an instruction set consisting of 4496 one byte 4196 two byte and 1596 three byte instructions With a 12 MHz crystal 58 of the instructions execute in 1 0 us 40 MHz 300 ns The CPU Central Processing Unit of the C504 consists of the instruction decoder the arithmetic section and the program control section Each program instruction is decoded by the instruction decoder This unit generates the internal signals controlling the functions of the individual units within the CPU They have an effect on the source and destination of data transfers and control the ALU processing The arithmetic section of the processor performs extensive data manipulation and is co
62. tin 48 x tin Further timing conditions tapc min 500 ns tin 2 fosc 2 teLeL Semiconductor Group 10 4 SIEMENS Device Specifications C504 Notes 1 Vain may exceed Vagnp Or Varer up to the absolute maximum ratings However the conversion result in these cases will be X000y or X3FF y respectively M During the sample time the input capacitance Ca can be charged discharged by the external source The internal resistance of the analog source must allow the capacitance to reach their final voltage level within ts After the end of the sample time ts changes of the analog input voltage have no effect on the conversion result cS This parameter includes the sample time ts the time for determining the digital result and the time for the calibration Values for the conversion clock t4pc depend on programming and can be taken from the table on the previous page gt Tye is tested at Varer 5 0 V Vacuno 0 V Vcc 4 9 V It is guaranteed by design characterization for all other voltages within the defined voltage range If an overload condition occurs on maximum 2 not selected analog input pins and the absolute sum of input overload currents on all analog input pins does not exceed 10 mA an additional conversion error of 1 2 LSB is permissible 5 During the conversion the ADC s capacitance must be repeatedly charged or discharged The internal resistance of the reference source must allow the capacitan
63. 0 mA Not 100 96 tested guaranteed by design characterization The typical cc values are periodically measured at Ta 25 but not 100 tested Semiconductor Group 10 3 SIEMENS Device Specifications C504 10 3 A D Converter Characteristics Vec 5 V 10 15 96 Vas 0 V T 0 to 70 C for the SAB C504 Vss 0 1 V lt V heno lt Vas 0 2 V Ta gt 40 to 1 10 C for the SAH C504 T 40 to 125 C for the SAK C504 Parameter Symbol Limit Values Unit Test Condition min max Analog input voltage Van Vias Vasi V 1 Sample time ts 64 X fn ns Prescaler 32 32 X n Prescaler 16 16 X tn Prescaler 8 8 X ty Prescaler 4 Conversion cycle time tapec 384 X fin ns Prescaler 32 192 x tin Prescaler 16 96 X tn Prescaler 8 48 X fn Prescaler 4 9 Total unadjusted error Tue 2 LSB Vgg 0 5V lt Vin Voc 0 5V 4 4 LSB Vss lt Vin lt Vss 0 5V Voc 0 5V lt Vin lt Voc 4 Internal resistance of Race faoc 250 KO fapc in ns 99 reference voltage source 0 25 Internal resistance of Risse ts 500 kQ fsin ns 99 analog source 0 25 ADC input capacitance Cam 50 pF 9 Notes see next page Clock calculation table ClockPrescaler ADCL1 0 tapc ts tADCC Ratio 32 1 1 32Xtin 64XtiN 984X tin 16 1 0 1l6xtm 32Xxtiy 192 x tin 8 0 1 8 X tin 16 Xtin 96 X tiny 4 0 0 4 X tin 8 X
64. 13 P3 7 RD RD control output enables the external data memory CTRAP 6 CCU Trap Input With CTRAP low the compare outputs of the CAPCOM unit are switched to the logic level as defined in the COINI register if they are enabled by the bits in SFR TRCON CTRAP is an input pin with an internal pullup resistor For power saving reasons the signal source which drives the CTRAP input should be at high or floating level during power down mode Input O Output Semiconductor Group 1 6 SIEMEN Introduction 2 C504 Table 1 1 Pin Definitions and Functions cont d Symbol Pin Number l O Function P MQFP 44 XTAL2 14 XTAL2 Output of the inverting oscillator amplifier XTAL1 15 XTAL1 Input to the inverting oscillator amplifier and input to the internal clock generator circuits To drive the device from an external clock source XTAL1 should be driven while XTAL2 is left unconnected There are no requirements on the duty cycle of the external clock signal since the input to the internal clocking circuitry is divided down by a divide by two flip flop Minimum and maximum high and low times as well as rise fall times specified in the AC characteristics must be observed P2 0 P2 7 18 25 O Port 2 is a bidirectional I O port with internal pullup resistors Port 2 pins that have 1s written to them are pulled high by the internal pullup resistors and in that state can be used as inputs As i
65. 2 1 0 CMSEL CMSEL CMSEL CMSEL CMSEL CMSEL CMSEL CMSEL ESH 19 12 11 10 03 02 01 og i 2MBELO S AAA E Y AH CAPCOM CAPCOM Channel 1 Channel 0 7 6 5 4 3 2 1 0 CMSEL CMSEL CMSEL CMSEL E4y 0 0 0 0 23 22 21 20 CMSEL1 TT F y CAPCOM Channel 2 Bit Function Reserved bits should be written with 0 CMSELx3 Switching compare timer 2 output signal to COUTx x 0 2 If CMSELx3 is set and compare mode is selected for the outputs COUTx the output signal of the 10 bit compare unit typically a higher frequency signal is switched modulated to the COUTx pin The state of COINI at the start of compare timer 1 defines the logic level of the CAPCOM channel output signal at in which the COMP output signal is output at COUTx COINI is set The COMP output is switched to COUTx during the low phase of the CAPCOM channel X signal COINI is cleared The COMP output is switched to COUTx during the high phase of the CAPCOM channel X signal Semiconductor Group 6 49 SIEMENS On Chip Peripheral Components C504 Bit Function CMSELx2 0 CAPCOM capture compare mode enable bits x 0 2 The CMSEL registers are used to select enable the operating mode and the output input pin configuration of the capture compare channels Each CAPCOM channel can be programmed individually either for compare or capture operation CMSEL x2 CMSEL x1 CMSEL x0 Mode Compare outputs disabled No com
66. 20 ESH CCIR 00H CT1FP CT1FC CC2F CC2R CC1iF CC1R CCOF CCOR E64 CTIOFL 00y M 6 25 4 3 2 1 0 E7y CT1OFH 00H 7 6 5 4 3 2 1 0 Fou B 00H D 6 5 4 3 2 1 0 1 X means that the value is undefined and the location is reserved 2 Bit addressable special function registers Semiconductor Group SIEMENS External Bus Interface C504 4 External Bus Interface The C504 allows for external memory expansion To accomplish this the external bus interface common to most 8051 based controllers is employed 4 1 Accessing External Memory It is possible to distinguish between accesses to external program memory and external data memory or other peripheral components respectively This distinction is made by hardware accesses to external program memory use the signal PSEN program store enable as a read strobe Accesses to external data memory use RD and WR to strobe the memory alternate functions of P3 7 and P3 6 Port O and port 2 with exceptions are used to provide data and address signals In this section only the port O and port 2 functions relevant to external memory accesses are described Fetches from external program memory always use a 16 bit address Accesses to external data memory can use either a 16 bit address MOVX DPTR or an 8 bit address MOVX Ri Role of PO and P2 as Data Address Bus When used for accessing external memory port 0 provides the data byte time multiplexed with the low byte of the addr
67. 4 6 Accessing through RO R1 4 7 Enable disable control 4 4 HO5S8l can Ra AP VER AME CEA 4 6 Semiconductor Group 11 6
68. 40 MHz clock Variable Clock 1 teic 3 5 MHz to 40 MHz min max min max RD pulse width TRLRH 120 6tac 30 ns WR pulse width wiwH 120 6toac 30 ns Address hold after ALE Laxe 35 2tac 15 ns RD to valid data in fai pv 75 Stoc 50 ns Data hold after RD RHDX 0 0 ns Data float after RD RHDZ 38 2toc 12 ns ALE to valid data in fiiov 150 8tcc 50 ns Address to valid data in lavov 150 ec 75 ns ALE to WR or RD fiw 60 90 3toacL 15 3tgg 15 ns Address valid to WR CavwL 70 4tac 30 ns WR or RD high to ALE high twain 10 40 tua 15 fag 15 ns Data valid to WR transition Lovwx 5 faic 20 ns Data setup before WR foavwH 125 7toc 50 ns Data hold after WR fwHax 5 faic 20 ns Address float after RD Triaz 0 0 ns External Clock Drive Parameter Symbol Limit Values Unit Variable Clock Freq 3 5 MHz to 40 MHz min max Oscillator period eic 25 294 ns High time cucx 10 toro feicx ns Low time teLcx 10 foo feucx ns Rise time lech 10 ns Fall time Touch 10 ns Semiconductor Group 10 11 SIEMENS Device Specifications C504 IT i ALE PSEN Port 0 Port 2 A8 A15 A8 A15 Program Memory Read Cycle MCT00096 fw ALE PSEN me bw ja TT v gt Inv m lag 44 nupz lua gt RLAZ Tex AQ A7 from XX Data IN NW A0 A7 RiorDPL VV Hil from PCL V
69. 6 83 SIEMENS On Chip Peripheral Components C504 The timer can be configured for either timer or counter operation In the most typical applications itis configured for timer operation C T2 0 Timer operation is a little different for timer 2 when its being used as a baud rate generator Normally as a timer it would increment every machine cycle thus at fosc 12 As a baud rate generator however it increments every state time fosc 2 In that case the baud rate is given by the formula Modes 1 3 baud rate fos 32x 65536 RC2H RC2L where RC2H RC2L is the content of RC2H and RC2L taken as a 16 bit unsigned integer Note that the rollover in TH2 does not set TF2 and will not generate an interrupt Therefore the timer 2 interrupt does not have to be disabled when timer 2 is in the baud rate generator mode Note too that if EXEN2 is set a 1 to 0 transition in T2EX can be used as an extra external interrupt if desired It should be noted that when timer 2 is running TR2 1 in timer function in the baud rate generator mode one should not try to read or write TH2 or TL2 Under these conditions the timer is being incremented every state time and the results of a read or write may not be accurate The RC registers may be read but shouldn t be written to because a write might overlap a reload and cause write and or reload errors Turn the timer off clear TR2 before accessing the timer 2 or RC registers in this
70. AB 80C52 enter their default reset state not before the on chip oscillator starts The reason is that the external reset signal must be internally synchronized and processed in order to bring the device into the correct reset state Especially if a crystal is used the start up time of the oscillator is relatively long typ 10 ms During this time period the pins have an undefined state which could have severe effects e g to actuators connected to port pins In the C504 the oscillator watchdog unit avoids this situation After power on the oscillator watchdog s RC oscillator starts working within a very short start up time typ less than 2 microseconds In the following the watchdog circuitry detects a failure condition for the on chip oscillator because this has not yet started a failure is always recognized if the watchdog s RC oscillator runs faster than the on chip oscillator As long as this condition is valid the watchdog uses the RC oscillator output as clock source for the chip This allows correct resetting of the part and brings all ports to the defined state The delay time between power on and correct reset state is max 34 us more details see chapter 5 2 Semiconductor Group 8 7 SIEMENS Power Saving Modes C504 9 Power Saving Modes The C504 allows two power saving modes of the device Idle mode Power down mode The functions of the power saving modes are controlled by bits which are located in the special functi
71. After the reset calibration phase the A D converter is calibrated according to its DC characteristics Nevertheless during the reset calibration phase single or continuous A D can be executed In this case it must be regarded that the reset calibration is interrupted and continued after the end of the A D conversion Therefore interrupting the reset calibration phase by A D conversions extends the total reset calibration time If the specified total unadjusted error TUE has to be valid for an A D conversion it is recommended to start the first A D conversions after reset when the reset calibration phase is finished Depending on the oscillator frequency used the reset calibration phase can be possibly shortened by setting ADCL1 and ADCLO prescaler value to its final value immediately after reset After the reset calibration a second calibration mechanism is initiated This calibration is coupled to each A D conversion With this second calibration mechanism alternatively offset and linearity calibration values stored in the calibration RAM are always checked when an A D conversion is executed and corrected if required Semiconductor Group 6 104 SIEMENS On Chip Peripheral Components C504 6 5 6 A D Converter Analog Input Selection The analog inputs are located at port 1 and port 3 4 lines on each port The corresponding port 1 and port 3 pins have a port structure which allows to use it either as digital l Os or analog inputs see s
72. CC2 CCH2 CCL2 A COUT2 Cntrl Register CT1CON Prescaler 10 Bit Compare Unit COMP Period Register CP2H CP2L Compare fsc 2 Com R PA Timer 2 pare Reg e gt COUT3 a Block INTO Commutation M Cntrl Register Control I INTI CT2CON INT2 BCON MCB02598 Figure 6 18 Block Diagram of the Capture Compare Unit CCU Semiconductor Group 6 30 SIEMENS On Chip Peripheral Components C504 6 3 1 The compare timer 1 and 2 are free running processor clock coupled 16 bit 10 bit timers which have each a count rate with a maximum of fosc 2 up to fosc 256 The compare timer operations with General Capture Compare Unit Operation its possible compare output signal waveforms are shown in figure 6 19 Compare Timer 1 Operating Mode O a Standard PWM edge aligned 7 Period Value Compare _ Value 00004 Compare Timer 1 Operating Mode 1 a Symetrical PWM center aligned Period b Standard PWM single edge aligned with constant single edge delay 7 Y Period Value Compare _ Value Offset lt CCx Lu Lu COUTx b Symetrical PWM center aligned with constant edge delay E Period _ 7 Value Value Compare Compare _ Value Value j 0000 y Offset 7 forr forr 4 M pem CCx CC
73. E xen e tel n 3 6 9 1 EG PC dioit Petri Duet 3 8 6 54 AIG MOE se oes 9 3 Emulation concept 4 5 ID Stn ar E EE 3 6 9 1 A dao MAE ca E 3 6 7 5 Ei e es 3 6 ETO rash iile rie erbe 3 6 7 5 A E eae wees 3 6 A cO had ER RE RA nes 3 6 7 5 AN MC TE 3 6 EIS ibo veis mee to leds 3 6 7 5 IE NOS burn iot ER 3 4 3 6 7 5 EIRP ot cotes ec Edu 3 8 6 45 IEN T eoo rios 3 4 3 6 6 97 7 6 EWP D ass site Peor ne 3 6 9 2 NTO niece A ER ede arceat 3 7 EXA x a 3 6 7 5 A ren rd E 3 7 EX D dou Reo doa 3 6 7 5 Interrupts os ur ep Retro 7 1 o ME MM UE ER 3 6 7 6 Block diagram 7 2 to 7 3 Execution of instructions 2 4 2 5 Enable registers 7 5 EXEN2 3 7 6 25 6 26 6 27 6 29 Entry sequence timing 7 10 EXE2 cet te cese sus 3 7 6 25 6 27 External Interrupts 7 11 External bus interface 4 1 Edge level triggering 7 12 ALE signal a nn Rh 4 4 Interrupt detection 7 12 ALE switch off control 4 4 ITCON register 7 13 Overlapping of data program memory 4 2 Handling procedure 7 10 Program memory access 4 2 Priority registers 7 7 Program data memory timing 4 3 Priority within level structure 7 8 FSENSIQUISI S irt eh s REESE 4 2 Request flagS 7 9 Role or PO and P2 us os Re 4 1 Response tiMe 7 14 F
74. ECT2 ECEM EX2 EADC IEN1 Bit Function Reserved bits for future use ECT1 Compare Timer 1 Interrupt enable If ECT1 1 the compare timer 1 interrupt is enabled ECCM Capture compare match interrupt If ECCM 1 the capture compare interrupt is enabled ECT2 Compare timer 2 interrupt enable If ECT2 1 the compare timer 2 interrupt is enabled ECEM CCU emergency interrupt enable If ECEM 1 the emergency interrupt of the CCU is enabled EX2 Timer 2 Interrupt Enable If EX2 1 the external interrupt 2 is enabled EADC A D converter interrupt enable If EADC 1 the A D Converter interrupt is enabled Semiconductor Group 7 6 SIEMEN Interrupt System 2 C504 7 3 2 Interrupt Prioritiy Registers Each interrupt source can also be individually programmed to one of two priority levels by setting or clearing a bit in the SFRs IPO or IP1 interrupt priority O low priority 1 high priority Special Function Registers IPO Address B84 Reset Value XX000000p BitNo MSB LSB 7 6 5 4 3 2 1 0 B8y PT2 PS PT1 PX1 PTO PXO IPO Bit Function Reserved bits for future use PT2 Timer 2 interrupt priority level If PT2 0 the Timer 2 interrupt has a low priority PS Serial channel interrupt priority level If PS 0 the Serial Channel interrupt has a low priority PT1 Timer 1 overflow interrupt priority level If PT1 0 the Timer 1 inte
75. F Bit Function SMO Serial port 0 operating mode selection bits SM1 SMO SM1 Selected operating mode 0 0 Serial mode 0 Shift register fixed baud rate fosc 12 0 1 Serial mode 1 8 bit UART variable baud rate 1 0 Serial mode 2 9 bit UART fixed baud rate foso 32 or fosc 64 1 1 Serial mode 3 9 bit UART variable baud rate SM2 Enable serial port multiprocessor communication in modes 2 and 3 In mode 2 or 3 if SM2 is set to 1 then RIO will not be activated if the received 9th data bit RB8 is 0 In mode 1 if SM2 1 then RI will not be activated if a valid stop bit was not received In mode 0 SM2 should be 0 REN Enable receiver of serial port 0 Enables serial reception Set by software to enable serial reception Cleared by software to disable serial reception TB8 Serial port transmitter bit 9 TB8 Is the 9th data bit that will be transmitted in modes 2 and 3 Set or cleared by software as desired RB8 Serial port receiver bit 9 In modes 2 and 3 RB8 is the 9th data bit that was received In mode 1 if SM2 0 RB8 is the stop bit that was received In mode 0 RB8 is not used TI Serial port transmitter interrupt flag Tl is set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other modes in any serial transmission TI must be cleared by software RI Serial port receiver interrupt flag RIO is set by hardware at the end of the 8th bit time in mode 0 or halfway through the stop
76. F as a destination register The WRITE to SBUF signal also loads TB8 into the 9th bit position of the transmit shift register and flags the TX control unit that a transmission is requested Transmission starts at the next rollover in the divide by 16 counter Thus the bit times are synchronized to the divide by 16 counter not to the WRITE to SBUF signal The transmision begins with activation of SEND which puts the start bit at TXD One bit time later DATA is activated which enables the output bit of the transmit shift register to TXD The first shift pulse occurs one bit time after that The first shift clocks a 1 the stop bit into the 9th bit position of the shift register Thereafter only zeroes are clocked in Thus as data bits shift out to the right zeroes are clocked in from the left When TB8 is at the output position of the shift register then the stop bit is just to the left of TB8 and all positions to the left of that contain zeroes This conditon flags the TX control unit to do one last shift and then deactivate SEND and set TI This occurs at the 11th divide by 16 rollover after WRITE to SBUF Reception is initiated by a detected 1 to 0 transition at RXD For this purpose RXD is sampled at a rate of 16 times whatever baud rate has been established When a transition is detected the divide by 16 counter is immediately reset and 1FFy is written to the input shift register At the 7th 8th and 9th counter states of each bi
77. IE2 External interrupt 2 004By TRF BCERR CAPCOM emergency interrupt 0053H CT2P Compare timer 2 interrupt 005BH CCOF CC2F CCOR CC2R Capture compare match interrupt 0063H CT1FP CT1FC Compare timer 1 interrupt 006By E Power down interrupt 007BH A special interrupt source is the power down mode interrupt This interrupt is automatically enabled when the C504 is in power down mode and bit EWPD enable wake up from power down mode in SFR PCON1 is set If these two conditions are met and when the oscillator watchdog unit start up phase after a wake up condition INTO 0 is finished the C504 starts with an interrupt at address 007BH All other interrupts are now disabled until the RETI instruction of the power down interrupt routine has been executed Semiconductor Group 7 4 SIEMENS Interrupt System C504 7 3 Interrupt Registers 7 3 1 Interrupt Enable Registers Each interrupt vector can be individually enabled or disabled by setting or clearing the corresponding bit in the interrupt enable registers IENO IEN1 Register IENO also contains the global disable bit EA which can be cleared to disable all interrupts at once Some interrupts sources have further enable bits e g EXEN2 ECTR etc Such interrupt enable bits are controlled by specific bits in the SFRs of the corresponding peripheral units described in chapter 6 The IENO register contains the general enable disable flags of the external interrupts O and 1 the timer int
78. M pulse generation when compare timer 2 reaches the count value 000y instead of compare timer 1 in all other modes All other trap functions of the multi channel PWM modes are identical as described in chapter 6 3 2 7 Semiconductor Group 6 77 SIEMENS On Chip Peripheral Components C504 6 4 Serial Interface USART The serial port is full duplex meaning it can transmit and receive simultaneously It is also receive buffered meaning it can commence reception of a second byte before a previously received byte has been read from the receive register However if the first byte still hasn t been read by the time reception of the second byte is complete one of the bytes will be lost The serial port receive and transmit registers are both accessed at special function register SBUF Writing to SBUF loads the transmit register and reading SBUF accesses a physically separate receive register The serial port can operate in 4 modes one synchronous mode three asynchronous modes Mode 0 Shift Register Synchronous Mode Serial data enters and exits through RXD TXD outputs the shift clock 8 data bits are transmitted received LSB first The baud rate is fixed at of the oscillator frequency See section 6 3 3 for more detailed information Mode 1 8 Bit USART Variable Baud Rate 10 bits are transmitted through TXD or received through RXD a start bit 0 8 data bits LSB first and a stop bit 1 On receive the s
79. Metric Quad Flat Package z 4 2 5 3 Qa 2 E o Tal F o8 M i a ggg 0 3106 a 0 2 WA BID G 44x 0 0 2 A B D 44x 0 0 2 A B D H 4x L i A SIB Aa i e O E 440 dl E Index Marking 1 _ 06x45 1 Does not include plastic or metal protrusion of 0 25 max per side N N oO LO o gt a O Sorts of Packing Package outlines for tubes trays etc are contained in our Data Book Package Information SMD Surface Mounted Device Dimensions in mm Semiconductor Group 10 17 Index SIEMENS Semiconductor Group C504 11 Index C A Ce oi edt crues 3 6 3 7 6 19 6 25 A D converter 6 94 Capture compare unit CCU to 6 78 Analog input pin selection 6 105 Deere Unites sd qo epis ae Block diagram aso mers 6 95 d ELE LE Calculation of conversion time 6 103 des ub Danh QE UT oe Calibration mechanisms 6 104 2 A oa pee ODU es Clock selection 6 99 i e DIM EH i Conversion time calculation 6 102 ee cies au Conversion timing 621004 o he AE iuit e 6 94 Interrupt related registers 6 52 Registers o e teenaa 6 96 to 6 98 Mode select registers 6 49 System clock relationship s 6 103 eet hus una eee QA ODE jas A D converter characteristics 10 4 to 10 5 n Mul Os oe Absolute maximum ratings PO AD oie a eee eer AC 2 3 3 7 Register description 6 44 to 6 58 AC characteristics URL ae ye Register survey
80. NTO to INT2 block commutation mode or by the operation of compare timer 1 multi pole PWM mode In the active phase of a combined multi channel PWM mode output signal during its low or high state the compare timer 1 compare output signal or the compare timer 2 output signal or both can be switched selectively to the CCx or COUTx PWM output lines The combined multi channel PWM modes are controlled by the BCON block commutation control register Figure 6 28 shows the block diagram of the multi channel PWM mode logic which is integrated in the C504 CCU Emergency Interrupt Combined t Trap Control CTRAP INTO ei INTI Control CCO INT2 He CON Port 1 as Control Logic COUTO COUT1 COUT2 Capture Channel 0 in Interrupt Capture Mode Period 16 Bit 10 Bit Comp Match Compare Compare COUTZ Interrupt Timer 1 Timer 2 MCB02608 Figure 6 28 Block Commutation Control in the C504 In block commutation mode a well defined incoming digital signal pattern of e g hall sensor signals which are applied to the TNTO 2 inputs is sampled Each transition at the INTO 2 inputs results in a change of the state of the PWM outputs In block commutation mode all six PWM output signals CCx and COUTx x 0 2 are outputs According a block commutation table table 6 9 the outputs CCx are put either to a low or high state while the outputs COUTx are switched to the PWM signal which is generated by the 10 bit compare timer 2
81. Opcode Again Read Read next Opcode Opcode No Fetch No Fetch IN MOVX j sco No ALE sIsTSTeTSISIWSIsISISISIs d MOVX 1 Byte 2 Cycle MCB01816 NS Access External Memory Figure 2 2 Fetch Execute Sequence Semiconductor Group SIEMENS Memory Organization C504 3 Memory Organization The C504 CPU manipulates operands in the following four address spaces upto 64 Kbyte of external program memory up to 64 Kbyte of external data memory 256 bytes of internal data memory 256 bytes of internal XRAM data memory a 128 byte special function register area Figure 3 1 illustrates the memory address spaces of the C504 FFFF y FFFF y Internal XRAM FFOO y FEFF y External Indirect Direct Address Address FF y niema E ay External RAM Register H 804 3FFF y Internal External Internal EA 1 EA 0 RAM 00004 0000 y 00y Code Space Data Space Internal Data Space MCD02592 Figure 3 1 C504 Memory Map Semiconductor Group 3 1 SIEMENS Memory Organization C504 3 1 Program Memory Code Space The C504 2R has 16 Kbytes of read only program memory while the C504 L has no internal program memory The program memory can be externally expanded up to 64 Kbytes If the EA pin is held high the C504 executes out of internal ROM unless the program counter address exceeds 3FFFy Locations 40004 through FFFFy are then fetched from the external program mem
82. PWM outputs drive a logic state as defined by the related bits in register COINI Semiconductor Group 6 76 SIEMENS On Chip Peripheral Components C504 Table 6 12 6 Pole PWM Timing State Table Actual State and PWM Phase Follower State No No Output Signals BCM1 BCMO CCO COUT1 CC2 COUTO CC1 COUT2 10 1 1 0 0 0 1 1 0 inactive inactive inactive inactive inactive inactive 2 1 0 7 1 active active inactive inactive inactive inactive 5 2 0 7 2 inactive active active inactive inactive inactive 1 3 0 7 3 inactive inactive active active inactive inactive 2 4 0 7 4 inactive inactive inactive active active inactive 3 5 0 7 5 inactive inactive inactive inactive active active 4 6 0 7 6 active inactive inactive inactive inactive active 5 1 0 ra 7 inactive active inactive active inactive active 2 1 0 7 Note In the inactive phase the PWM outputs drive a logic state as defined by the related bits in register COINI 6 3 4 5 Trap Function in Multi Channel Block Commutation Mode The trap function in the block commutation mode operates similar to the trap function as described in chapter Table 6 3 2 7 Trap Function of the CAPCOM Unit in Compare Mode on page 42 But there is one difference when CTRAP becomes inactive high the CCx and COUTx outputs are again switched back to the PW
83. Registers cw te oc arouse 6 25 to 6 26 Timings Data memory read cycle 10 12 Data memory write cycle 10 13 External clock timing 10 13 Program memory read cycle 10 12 ROM verification mode 1 10 14 ROM verification mode 2 10 15 PO C 3 4 3 6 ACETUM pcr 3 4 3 6 AS scott derat viene 3 5 3 7 MOD es rw coria tala HE 3 4 3 6 6 19 PROA cte tenure ptr tac heh ea 3 6 lllo HT co 3 6 lc Pp 3 7 6 24 6 25 VRGON arpas dives 3 5 3 7 6 44 6 58 TRENO C edem FECERIS EE ERO ES 3 7 TRENT m5 Rosin temp pA REOS 3 7 TREN2 aud Persae EUR 3 7 TRENJ vosotras hx EE 3 7 TRENG casta tetas 3 7 MENS bisa t erc rore La Eon 3 7 TRENS 0 cidade eee 6 58 cap ERE MERIT TEE 3 7 6 58 TRPEN ciorum eed eres 3 7 6 58 XIV 4v s urba ae poi ma 3 7 Unprotected ROM verifiy timimg 4 8 Watchdog til Tier eee e RI 8 1 Block diagram sse 8 1 Functionality ib ERLI REGES 8 1 Refreshing of the WDT 8 4 Registers WDCON and WDTREL 8 2 Reset operation 8 4 Starting of the WDT 8 3 Time out periods 8 3 WDGOODN csi EUER amp 3 5 3 7 8 2 A etu xm uon OE TEES 3 7 8 2 WDTBSEL S Is pma ines 3 6 8 2 WDTREL ss ostia 3 5 3 6 8 2 SIEMENS Index C504 WDTS a ees cardia ideo 3 7 8 2 VV BE aee wreck weenie Pp C wes 3 7 X XMAP me ES 3 7 4 4 4 6 XRAM operati0N 4 6 Accessing through DPTR
84. S5P2 in every machine cycle The value is not polled by the circuitry until the next machine cycle If the request is active and conditions are right for it to be acknowledged a hardware subroutine call to the requested service routine will be next instruction to be executed The call itself takes two cycles Thus a minimum of three complete machine cycles will elapse between activation and external interrupt request and the beginning of execution of the first instruction of the service routine A longer response time would be obtained if the request was blocked by one of the three previously listed conditions If an interrupt of equal or higer priority is already in progress the additional wait time obviously depends on the nature of the other interrupt s service routine If the instruction in progress is not in its final cycle the additional wait time cannot be more than 3 cycles since the longest instructions MUL and DIV are only 4 cycles long and if the instruction in progress is RETI or a write access to the registers IEN or IP the additional wait time cannot be more than 5 cycles a maximum of one more cycle to complete the instruction in progress plus 4 cycles to complete the next instruction if the instruction is MUL or DIV Thus a single interrupt system the response time is always more than 3 cycles and less than 9 cycles Semiconductor Group 7 14 SIEMENS Fail Safe Mechanisms C504 8 Fail Safe Mechanisms The C504 offers e
85. SAB C501 compatible 1 O port lines which can be used for digital I O The type A ports port O and port 2 are also designed for accessing external data or program memory Type B port lines are located at port 3 and provide alternate functions for the serial interface or are used as control outputs during external data memory accesses The C504 provides eight analog input lines which are realized as mixed digital analog inputs The 8 analog inputs are split into two groups of four inputs each Four analog inputs ANO ANS are located at the port 1 pins P1 0 to P1 3 and the other four analog inputs AN4 AN7 are located at the port 3 pins P3 2 to P3 5 type C and type E port lines After reset all analog inputs are disabled and the related pins of port 1 and 3 are configured as digital inputs The analog function of the specific port 1 and port 3 pins is enabled by bits in the SFRs P1ANA and P3ANA Writing a O to a bit position of P1ANA or P3ANA assigns the corresponding pin to operate as analog input Semiconductor Group 6 1 SIEMENS On Chip Peripheral Components C504 Note P1ANA and P3ANA are mapped SFRs and can be only accessed if bit RMAP in SFR SYSCON is set description see chapter 6 5 4 Type D and E port lines can be switched to push pull drive capability when they are used as compare outputs of the CAPCOM unit As already mentioned port 1 and 3 are provided for multiple alternate functions These second and third functions of the port
86. SIEMENS C504 8 Bit CM OS M icrocontroller User s M anual 06 96 C504 Revision History Current Version 05 96 Previous Version Page Page Subjects major changes since last revision in previous in new Version Version Edition 05 96 This edition was realized using the software system FrameMaker Published by Siemens AG Bereich Halbleiter Marketing Kommunikation BalanstraBe 73 81541 M nchen O Siemens AG 1996 All Rights Reserved Attention please As far as patents or other rights of third parties are concerned liability is only assumed for components not for applications processes and circuits implemented within components or assemblies The information describes the type of component and shall not be considered as assured characteristics Terms of delivery and rights to change design reserved For questions on technology delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide see address list Due to technical requirements components may contain dangerous substances For information on the types in question please contact your nearest Siemens Office Semiconductor Group Siemens AG is an approved CECC manufacturer Packing Please use the recycling operators known to you We can also help you get in touch with your nearest sales office By agreement we will take packing material back
87. UT OUT OUT OUT OUT o Houi A 0 A N PCL OUT PCL OUT PCL OUT PCL OUT valid valid valid valid b e One Machine Cycle One Machine Cycle s1 s2 s3 s4 s5 s6 st s2 s3 s4 s5 s6 ALE PSEN inm EE EE a RD WI MOVX P2 PCH DPH OUT OR PCH OUT OUT P2 OUT OUT DATA po IN Hau e Qui i A A A PCL OUT DPL or Ri PCL OUT valid valid valid MCD02575 Figure 4 1 External Program Memory Execution Semiconductor Group 4 3 SIEMENS External Bus Interface C504 4 4 ALE Address Latch Enable The main function of ALE is to provide a properly timed signal to latch the low byte of an address from PO into an external latch during fetches from external memory The address byte is valid at the negative transition of ALE For that purpose ALE is activated twice every machine cycle This activation takes place even if the cycle involves no external fetch The only time no ALE pulse comes out is during an access to external data memory when RD WR signals are active The first ALE of the second cycle of a MOVX instruction is missing see figure 4 1 b Consequently in any system that does not use data memory ALE is activated at a constant rate of 1 6 of the oscillator frequency and can be used for external clocking or timing purposes The C504 allows to switch off the ALE output signal If the internal ROM is used EA 1 and ALE is switched off by EALE 0 ALE will only go active during e
88. XXp Bit No MSB LSB 7 6 0 Da ae a DA 4 98 a ADDATH ADDATL The registers ADDATH and ADDATL hold the 10 bit conversion result in left justified data format The most significant bit of the 10 bit conversion result is bit 7 of ADDATH The least significant bit of the 10 bit conversion result is bit 6 of ADDATL To get a 10 bit conversion result both ADDAT register must be read If an 8 bit conversion result is required only the reading of ADDATH is necessary The data remains in ADDAT until it is overwritten by the next converted data ADDAT can be read or written under software control If the A D converter of the C504 is not used register ADDATH can be used as an additional general purpose register Semiconductor Group 6 96 SIEMENS On Chip Peripheral Components C504 Special Function Registers ADCONO Address D814 Special Function Registers ADCON1 Address DC Special Function Registers IEN1 Address A9 Bit No D8y DCH A9H Reset Value XX000000p Reset Value 01XXX000p Reset Value XX000000p MSB LSB 7 6 5 4 3 2 1 0 ADC BSY ADM MX2 MX1 MXO ADCONO ADCL1 ADCLO MX2 MX1 MXO ADCON1 ECT1 ECCM ECT2 ECEM EX2 EADC IEN1 The shaded bits are not used for A D converter control Bit Function Reserved bits for future use ADC A D converter interrupt reques
89. a reset This causes the stack to begin a location 08y above register bank zero The SP can be read or written under software control Semiconductor Group 2 3 SIEMENS Fundamental Structure C504 2 2 CPU Timing A machine cycle consists of 6 states 12 oscillator periods Each state is divided into a phase 1 half during which the phase 1 clock is active and a phase 2 half during which the phase 2 clock is active Thus a machine cycle consists of 12 oscillator periods numbered S1P1 state 1 phase 1 through S6P2 state 6 phase 2 Each state lasts for two oscillator periods Typically arithmetic and logically operations take place during phase 1 and internal register to register transfers take place during phase 2 The diagrams in figure 2 2 show the fetch execute timing related to the internal states and phases Since these internal clock signals are not user accessible the XTAL2 oscillator signals and the ALE address latch enable signal are shown for external reference ALE is normally activated twice during each machine cycle once during S1P2 and S2P1 and again during S4P2 and S5P1 Executing of a one cycle instruction begins at S1P2 when the op code is latched into the instruction register If it is a two byte instruction the second reading takes place during S4 of the same machine cycle If itis a one byte instruction there is still a fetch at S4 but the byte read which would be the next op code is ignored discarded fetch
90. and 2 and the input buffers of port O are also used for accessing external memory In this application port O outputs the low byte of the external memory address time multiplexed with the byte being written or read Port 2 outputs the high byte of the external memory address when the address is 16 bits wide Otherwise the port 2 pins continue emitting the P2 SFR contents In this function port 0 is not an open drain port but uses a strong internal pullup FET 6 1 1 Port Structures The C504 generally allows digital I O on 32 lines grouped into 4 bidirectional 8 bit ports Each port bit consists of a latch an output driver and an input buffer Read and write accesses to the I O ports PO P3 are performed via their corresponding special function registers Depending on the specific ports multiple functions are assigned to the port pins Therefore the parallel I O ports of the C504 can be grouped into five different types which are listed in table 6 1 Table 6 1 C504 Port Structures Type Description A Standard digital I O ports which can be also used for external address data bus Standard multifunctional digital I O port lines C Mixed digital analog I O port lines with programmable analog input function D Standard digital I O port lines with push pull drive capability E Mixed digital analog I O port lines with push pull drive capability and programmable analog input function Type A and B port pins are standard
91. annel 16 bit capture compare unit 1 channel 10 bit compare unit e USART e 10 bit A D Converter with 8 multiplexed inputs Twelve interrupt sources with two priority levels e On chip emulation support logic Enhanced Hooks Technology Programmable 15 bit Watchdog Timer e Oscillator Watchdog Fast Power On Reset Power Saving Modes e M QFP 44 package e Temperature ranges SAB C504 7 0to 70 C SAF C504 T 40to 85 C SAH C504 T4 40to 110 C max operating frequency TBD SAK C504 T4 40to 125 C max operating frequency 12 MHz Semiconductor Group 1 2 SIEMENS Introduction C504 Kc Ves VAREF VAGND Port 0 lt gt 8 Bit Digital 1 0 XTAL1 Port 1 or XTAL2 gt 8 Bit Digital 1 0 4 Bit Analog Inputs RESET C504 EA Port 2 ALE K gt 8 Bit Digital 1 0 PSEN Port 3 o lt gt 8 Bit Digital 1 0 CTRAP 4 Bit Analog Inputs COUT3 MCLO2590 Figure 1 2 Logic Symbol Semiconductor Group 1 3 SIEMENS Introduction C504 P0 4 AD4 P0 5 AD5 P0 6 AD6 P0 7 AD7 30 29 28 27 26 25 24 23 P0 3 AD3 P2 4 A12 P0 2 AD2 P2 3 A11 P0 1 AD1 P2 2 M0 P0 0 ADO P2 1 A9 VAREF C504 LM P2 0 A8 VGND Voc P1 0 ANO T2 EL Vos P1 1 AN1 TEX XTAL1 P1 2 AN2 CCO XTAL2 P1 3 AN3 COUTO P3 7 RD P1 4 CC1 P3 6 WR INT2
92. are synchronously switched to the compare channel output signal generation when compare timer 1 has reached the count value 0000p The trap function is controlled by bits in the TRCON register The general enable function of the external CTRAP signal is controlled by one bit TRPEN Further each CAPCOM compare channel output can be enabled disabled selectively for trap function Figure 6 26 shows the trap function for the two outputs CCx and COUTx of one compare channel x The timing diagram implies that the trap function is enabled at the CCx and COUTx outputs At reference point 1 in figure 6 26 CTRAP becomes active and at reference point 2 the trap state is released again synchronously to the compare timer 1 count state 00004 If the trap function is enabled and CTRAP becomes active bit TRF trap flag in SFR TRCON is set and a CCU emergency interrupt will be generated if the related interrupt enable bits are set The flag TRF is level sensitive and must be cleared by software The trap function used in block commutation mode differs from the trap function described above Especially the synchronization scheme is different see section 6 3 4 5 Semiconductor Group 6 42 SIEMENS On Chip Peripheral Components C504 a Trap Function in CAPCOM Operating Mode 0 CT1 CTIOFF Period Value Compare Value Offset oe II rap State yy COUTx pee Trap State 1 CTRAP b Trap Function
93. as static and PWM modulated outputs CAPCOM channel 0 can be used in block commutation mode for a capture operation which is triggered by each transition at the external interrupt inputs Further the multi channel PWM mode signal generation can be also triggered by the period of compare timer 1 These operating modes are referenced as multi pole PWM modes Using the CTRAP input signal of the C504 the compare outputs can be put immediately into a high or low state and released again to its actually generated compare output signal The CCU unit has four main interrupt sources with their specific interrupt vectors Interrupts can be generated at the compare timer 1 period match or count change events at the compare timer 2 period match event ata CAPCOM compare match or capture event and at a CAPCOM emergency event An emergency event occurs if an active CTRAP signal is detected or if an error condition in block commutation mode is detected All interrupt sources can be enabled disabled individually Semiconductor Group 6 32 SIEMENS On Chip Peripheral Components C504 6 3 2 CAPCOM Unit Operation 6 3 2 1 CAPCOM Unit Clocking Scheme The CAPCOM unit is basically controlled by the 16 bit compare timer 1 Compare timer 1 is the timing base for all compare and capture capabilities of the CAPCOM unit The input clock for compare timer 1 is directly coupled to the clock rate of the C504 Its frequency can be selected via three bits of the CT1CON
94. ce to reach their final voltage level within the indicated time The maximum internal resistance results from the programmed conversion timing 6 Not 100 tested but guaranteed by design characterization Semiconductor Group 10 5 Device Specifications C504 SIEMENS 10 4 AC Characteristics for C504 L C504 2R Voc 5 V 10 15 Vss 0 V T 0 to 70 C T 40 to 85 C T 40 to 110 C for the SAH C504 T 40 to 125 C for the SAK C504 C for port 0 ALE and PSEN outputs 100 pF C for all other outputs 80 pF for the SAB C504 for the SAF C504 Program Memory Characteristics Parameter Symbol Limit Values Unit 12 MHz clock Variable Clock l fc c 3 5 MHz to 12 MHz min max min max ALE pulse width fuu 127 2f cg 40 ns Address setup to ALE fAVLL 43 fcc 40 ns Address hold after ALE tax 30 fec 23 ns ALE low to valid instr in fw 233 Ata c 100 ns ALE to PSEN Tum 58 foc 25 ns PSEN pulse width Tore 215 Stoc 35 ns PSEN to valid instr in fat 150 Sfc c 100 ns Input instruction hold after PSEN lokis 0 0 ns Input instruction float after PSEN laz 63 E foro 20 ns Address valid after PSEN texav 75 tac 8 ns Address to valid instr in tayiy 302 Stoic 115 ns Address float to PSEN izpi 0 0 ns Interfacing the C504 to d
95. compare registers are 16 bit register organized as two 8 bit byte wide registers Each of the three CAPCOM channels has one capture compare registers In compare mode they hold a compare value which typically defines the duty cycle of the output signals In capture mode the actual compare timer 1 value is transferred into the capture compare registers at a capture event If CCLx CCHx is written always shadow latches are loaded The content of these shadow latches is transferred to the real registers when STE1 is set and the compare timer 1 reaches its period value operating mode 0 or count value 0000y operating mode 1 When the capture compare registers are read always the real registers are accessed because of capture mode Special Function Registers CCLO CCHO Addresses C2y C3py Reset Value 00y Special Function Registers CCL1 CCH1 Addresses C4y C5py Reset Value 00H Special Function Registers CCL2 CCH2 Addresses C6y C7 py Reset Value 00H Bit No MSB LSB 7 6 5 4 3 2 1 0 C2y 7 6 5 4 3 2 1 LSB CCLO C3H MSB 6 5 4 3 2 1 0 CCHO C4y 7 6 5 4 3 2 E LSB CCL1 C5H MSB 6 5 4 m 2 A 0 CCH1 C6y a 6 5 4 3 2 1 LSB CCL2 C7H MSB 6 5 4 3 2 1 0 CCH2 Bit Function CCLx 7 0 Capture compare value low byte x 0 2 The 8 bit value in the CCLx register is the low part of the 16 bit capture compare value of channel x CCHx 7 0 Capture com
96. controlled PWM waveforms can be generated 4 pole multi channel PWM waveforms 5 pole multi channel PWM waveforms 6 pole multi channel PWM waveforms The basic waveforms of these three compare timer 1 controlled PWM modes are shown the following three figures 6 32 to 6 34 The figures show waveforms for different COINI values with the resulting active inactive phases and rotate right rotate left condition All three figures assume that compare timer 1 operates with 100 duty cycle compare and offset registers 00004 and without compare timer 2 modulation Compare timer 1 duty cycles less than 100 or compare timer 2 modulation in the multi channel PWM modes is shown in figures 6 29 and 6 30 a Timing in rotate left mode BCM1 0 1 0 with COINI XX111111p Start Timer 1 gt cco COUT1 Low Active a A ee ee COUT2 State No 1 2 3 4 1 2 3 4 1 2 b Timing in rotate right mode BCM1 0 0 1 with COINI XX000000g Start Timer 1 gt cco COUT1 High Active pos A ra E rr e e COUT2 State No 2 1 4 3 2 1 4 3 2 MCT02612 Figure 6 32 Basic Compare Timer 1 Controlled 4 Pole PWM Timing Semiconductor Group 6 73 SIEMENS On Chip Peripheral Components C504 a Timing in rotate left mode BCM1 0 1 0 with COINI XX111111 g Start Timer 1 gt CCO COUT1
97. correct port reset state is Typ 18us Max 34us The RC oscillator will already run at a Voc below 4 25V lower specification limit Therefore at slower Vcc rise times the delay time will be less than the two values given above After the on chip oscillator has finally started the oscillator watchdog detects the correct function then the watchdog still holds the reset active for a time period of max 768 cycles of the RC oscillator clock in order to allow the oscillation of the on chip oscillator to stabilize figure 5 1 Il Subsequently the clock is supplied by the on chip oscillator and the oscillator watchdog s reset request is released figure 5 1 IIl However an externally applied reset still remains active figure 5 1 IV and the device does not start program execution figure 5 1 V before the external reset is also released Although the oscillator watchdog provides a fast internal reset it is additionally necessary to apply the external reset signal when powering up The reasons are as follows Termination of Software Power Down Mode Reset of the status flag OWDS that is set by the oscillator watchdog during the power up sequence Using a crystal or ceramic resonator for clock generation the external reset signal must be hold active at least until the on chip oscillator has started and the internal watchdog reset phase is completed after phase III in figure 5 1 When an external clock generator is used pha
98. ctor Group 6 100 SIEMENS On Chip Peripheral Components C504 Conversion Time tco During the conversion time the analog voltage is converted into a 10 bit digital value using the successive approximation technique with a binary weighted capacitor network During an A D conversion also a calibration takes place During this calibration alternating offset and linearity calibration cycles are executed see also section 6 5 5 At the end of the conversion time the BSY bit is reset and the IADC bit in SFR ADCONO is set indicating an A D converter interrupt condition Write Result Time twp At the result phase the conversion result is written into the ADDAT registers Figure 6 42 shows how an A D conversion is embedded into the microcontroller cycle scheme using the relation 6 x t yn 1 instruction cycle It also shows the behaviour of the busy flag BSY and the interrupt flag IADC during an A D conversion Prescaler Selection Write Result Cycle ADCL1 ADCLO MOV ADDATL 0 1 Instruction Cycle MOV A ADDATL tN CaN x x tp2p sp a4 s5p epjz7p 6s89 j9 t t x xEti2 s 4l 5j X x 0112 3 4 5 xu xqpti2 s3 4 5 65 6 65 66 67 68 l Start of next Start of A D i Conversion in Conversion Cycle Na tanec US continuous mode A D Conversion Cycle write ADDAT leida BSY Bit P Cont Conv Single Conv A APP A IADC Bit First Instruction of an Inte
99. cycle following the one in which the transition was detected Since it takes two machine cycles 24 oscillator periods to recognize a 1 to 0 transition the maximum count rate is 1 24 of the oscillator frequency There are no restrictions on the duty cycle of the external input signal but to ensure that a given level is sampled at least once before it changes it must be held for at least one full machine cycle Semiconductor Group 6 16 SIEMENS On Chip Peripheral Components C504 6 2 1 Timer Counter 0 and 1 Timer counter O and 1 of the C504 are fully compatible with timer counter O and 1 of the C501 and can be used in the same four operating modes Mode 0 8 bit timer counter with a divide by 32 prescaler Mode 1 16 bit timer counter Mode 2 8 bit timer counter with 8 bit auto reload Mode 3 Timer counter 0 is configured as one 8 bit timer counter and one 8 bit timer Timer counter 1 in this mode holds its count The effect is the same as setting TR1 0 External inputs INTO and INT1 can be programmed to function as a gate for timer counters 0 and 1 to facilitate pulse width measurements Each timer consists of two 8 bit registers THO and TLO for timer counter 0 TH1 and TL1 for timer counter 1 which may be combined to one timer configuration depending on the mode that is established The functions of the timers are controlled by two special function registers TCON and TMOD In the following descriptions the symbols THO and
100. cycle of CCx outputs 100 Duty cycle of COUTx outputs uA z 100 96 Semiconductor Group 6 39 SIEMENS On Chip Peripheral Components C504 6 3 2 5 Burst Mode of CAPCOM COMP Unit In the burst mode both units of the CCU are combined in a way that the CAPCOM outputs COUTx are modulated by the output signal of the COMP unit Using the burst mode the CAPCOM unit operates in compare mode and the COMP unit provides a PWM signal which is switched to the COUTx outputs This PWM signal typically has a higher frequency than the compare output signal of the CAPCOM unit Figure 6 25 shows the waveform generation using the burst mode Count Value A Period Register Compare Timer 1 CT1OFF 2 0 Compare Register Start of LEN Time COUTx COINI 1 CMSELx3 0 Burst Mode COUTx Disabled COINI 0 J Compare AAAAAAAAAAAS AAAAAAAAAS AA Timer 2 AVV VV VV VVV VVV VV VVV VVV VV YV COUT3 COUT3I 0 s LULL LLL COUTXI 0 COINI 1 COUT3I 0 LULL UUU COUTXI 1 COUT3I 1 d MU UUUUUU COUTXI 1 COINI 0 COUTSI 1 LLL LULL COUTXI 0 Note If the Bits COUT3l and COUTXI in the COINI register are identical COUT3 and the burst signals at COUTx have the same polarity MCTO2605 Figure 6 25 Burst Mode Operation The burst mode of a COUTx output is enabled by the bit CMSELx3 which is located in the mode select registers CMSELO and CMSEL1 Figure 6 25 shows four CAPCOM
101. d 3m d read pin di To A D Converter MCS02582 Figure 6 9 Driver Circuit of Type E Port Pins Semiconductor Group 6 12 SIEMENS On Chip Peripheral Components C504 6 1 4 Port Timing When executing an instruction that changes the value of a port latch the new value arrives at the latch during S6P2 of the final cycle of the instruction However port latches are only sampled by their output buffers during phase 1 of any clock period during phase 2 the output buffer holds the value it noticed during the previous phase 1 Consequently the new value in the port latch will not appear at the output pin until the next phase 1 which will be at S1P1 of the next machine cycle When an instruction reads a value from a port pin e g MOV A P1 the port pin is actually sampled in state 5 phase 1 or phase 2 depending on port and alternate functions Figure 6 10 illustrates this port timing It must be noted that this mechanism of sampling once per machine cycle is also used if a port pin is to detect an edge e g when used as counter input In this case an edge is detected when the sampled value differs from the value that was sampled the cycle before Therefore there must be met certain requirements on the pulse length of signals in order to avoid signal edges not being detected The minimum time period of high and low level is one machine cycle which guarantees that this logic level is noticed by the port at least once S4 S5 S6 S1
102. divide by 16 1 1 divide by 32 EADC Enable A D converter interrupt If EADC 0 the A D converter interrupt is disabled Note Generally before entering the power down mode an A D conversion in progress must be stopped If a single A D conversion is running it must be terminated by polling the BSY bit or waiting for the A D conversion interrupt In continuous conversion mode bit ADM must be cleared and the last A D conversion must be terminated before entering the power down mode A single A D conversion is started by writing to SFR ADDATL with dummy data A continuous conversion is started under the following conditions By setting bit ADM during a running single A D conversion By setting bit ADM when at least one A D conversion has occured after the last reset operation Bywriting ADDATL with dummy data after bit ADM has been set before if no A D conversion has occured after the last reset operation When bit ADM is reset by software in continuous conversion mode the just running A D conversion is stopped after its end Semiconductor Group 6 98 SIEMENS On Chip Peripheral Components C504 6 5 3 A D Converter Clock Selection The ADC uses two clock signals for operation the conversion clock f apc 1 tapc and the input clock fiy 21 tjN Both clock signals are derived from the C504 system clock fosc which is applied at the XTAL pins The input clock fiy is always fosc 2 while the conversion clock must b
103. e active inactive inactive inactive active 0 1 0 active inactive inactive inactive inactive active 0 1 1 active inactive inactive inactive active inactive 0 0 1 inactive inactive active inactive active inactive Rotate right 1 1 0 active inactive inactive inactive active inactive 1 0 0 active inactive inactive inactive inactive active 1 0 1 inactive active inactive inactive inactive active 0 0 1 inactive active inactive active inactive inactive 0 1 1 inactive inactive active active inactive inactive 0 1 0 inactive inactive active inactive active inactive Slow down X X X inactive inactive inactive active active active Idle 2 X X X inactive inactive inactive inactive inactive inactive 1 If one of these two combinations of INTx signals is detected in rotate left or rotate right mode bit BCERR flag is set If enabled a CCU emergency interrupt can be generated When these states error states are reached immediately idle state is entered 2 Idle state is also entered when a wrong follower is detected if bit BCON 7 BCEM is set When idle state is entered the BCERR flag is always set Idle state can only be left when the BCERR flag is reset by software In block commutation mode CAPCOM channel 0 is automatically configured for capture mode In block commutation mode any signal transition at INTO 2 generates a capture pulse for CAPCOM cha
104. e 10 bit compare timer 2 unit COUT3 can be disabled and set to a high or low state EA 29 External Access Enable When held at high level instructions are fetched from the internal ROM C504 2R only when the PC is less than 4000y When held at low level the C504 fetches all instructions from external program memory For the C504 L this pin must be tied low P0 0 P0 7 30 37 O Porto is an 8 bit open drain bidirectional I O port Port O pins that have 1s written to them float and in that state can be used as high impendance inputs Port 0 is also the multiplexed low order address and data bus during accesses to external program or data memory In this application it uses strong internal pullup resistors when issuing 1 s Port O also outputs the code bytes during program verification in the C504 2R External pullup resistors are required during program ROM verification Vaner 38 Reference voltage for the A D converter VAGND 39 Reference ground for the A D converter Vas 16 Ground 0V Voc 17 Power Supply 45V Input O Output Semiconductor Group 1 8 SIEMENS Fundamental Structure C504 2 Fundamental Structure The C504 basically is fully compatible to the architecture of the standard 8051 microcontroller family Especially it is functionally upward compatible with the SAB 80C52 C501 microcontrollers While maintaining all architectural and operational characteristics of
105. e adapted to the input clock fosc The conversion clock is limited to a maximum frequency of 2 MHz Therefore the ADC clock prescaler must be programmed to a value which assures that the conversion clock does not exceed 2 MHz The prescaler ratio is selected by the bits ADCL1 and ADCLO of SFR ADCON1 The table in figure 6 40 shows the prescaler ratio which must be selected for typical system clock rates Up to 16 MHz system clock the prescaler ratio 4 is selected Up to 32 MHz a prescaler ratio of at least 8 must be selected and beyond 32 MHz the prescaler ratio 16 has to be selected The prescaler ratio 32 can be selected when the maximum performance of the A D converter is not necessarily required or the input impedance of the analog source is to high to reach the maximum accuracy Conversion Clock fanc A D Converter Clock Prescaler Input Clock fiy Conditions fapemax lt 2MHz N fosc __1 2 2fecl MCS02617 MCU System Clock Prescaler fApc Rate fosc Ratio MHz 3 5 MHz 4 438 12 MHz 4 1 5 16 MHz 4 2 24 MHz 8 1 5 32 MHz 8 2 40 MHz 16 Figure 6 40 A D Converter Clock Selection The duration of an A D conversion is a multiple of the period of the f y clock signal The calculation of the A D conversion time is shown in the next section Semiconductor Group 6 99 SIEMENS On Chip Peripheral Components C504 6 5 4 A D Conversion Timing An A D conversion is int
106. e eod Ur getto rte da 6 1 6 1 2 Standard I O Port Circuitry s o5 a De ci Rr eap TE WR Y eo es eae RUE 6 3 6 1 21 POM OCCU ida 6 5 6 1 2 2 Port 1 and Port 3 Circuitry a EUROS tona ces 6 6 6 1 2 3 Port 2 Circuitry n naana O 6 7 6 1 3 Detailed Output Driver Circuitry a nn anaa aaae 6 8 6 1 3 1 Type B Port Driver Circuitry a A RE Rove eh en 6 8 6 1 3 2 Type C Port Driver Circuitry 25 lt saved yu s or RO yan o eden are d 6 10 6 1 3 3 Type D Port Driver Circuitry o esr re m RR RE MUR EE RE RUP ER ER 6 11 6 1 3 4 Type E Port Driver Circuitry 20 0 0c cee 6 12 Semiconductor Group l 1 05 96 SIEMENS C504 Table of Contents Q L4 POM TIMINGS sus AA 6 1 5 Port Loading and Interfacing ooocoooooooooooo 6 1 6 Read Modify Write Feature of Ports 2and 3 6 2 TIMES COUNT Si Dace ba pes Wa a are hes aad 6 2 1 Timer CounterO and 1 0 ccc ee eee 6 21 Mode U pe Se a ee oa atin Wetec cd eds e ch atm ha as ae Ou o iu us idis aetna A he Eee plut 2 129 MOOG a ue idea xoa ein Wea aed ERU ace as Eee abut Sed ModE Sigs sath dea kata en eee nda ie Goa fae eae 6 22 men COIN Lo rs ay oo ee heeds ke cece Mele Soe 6 2 2 1 Auto Reload Up or Down Counter o o ooooooo 02 212 Capito q ane gust aa am da E AO OO SMS dore 6 3 Capture Compare Unit CCU 2 0000s 6 3 1 General Capture Compare Unit Operation 6 3 2 CAPCOM Unit Operation
107. e register In figure 6 22 the waveforms a and b show an example for a waveform of two signals with a constant delay of their rising edge A compare register value of 3 is assumed Using inverted signal polarity SFR COINI signal c can be generated at COUTx If the value in the offset register plus the value of the period register is less or equal to the value stored in the compare register a static 1 or a static 0 will be generated at COUTx see figure 6 22 d and e Therefore CCx will also stay at a static level if the compare register value is greater than the value stored in the period register Semiconductor Group 6 35 SIEMENS On Chip Peripheral Components C504 Count Value A CCPz7 Period Reg CT1 CT1OFF CT10F 2 Offset Reg CC COINI Pin 3 0 CCx a 3 0 COUTx b 3 1 COUTx c gt CT10F cop 0 COUTx 0 0 d CTOF 0 COUTx 100 e CC content of the CCxH CCxL compare registers CCP content of the CCPH CCPL period register CT10F content of the CT10FH CT1OFL offset registers MCTO2602 Figure 6 22 Compare Timer 1 with Offset not equal 0 Mode 0 Semiconductor Group 6 36 SIEMENS On Chip Peripheral Components C504 6 3 2 3 CAPCOM Unit Operating Mode 1 Using compare time
108. e watchdog starts a final reset sequence which takes typ 1 ms Within that time the clock is still supplied by the RC oscillator and the part is held in reset This allows a reliable stabilization of the on chip oscillator After that the watchdog toggles the clock supply back to the on chip oscillator and releases the reset request If no external reset is applied in this moment the part will start program execution If an external reset is active however the device will keep the reset state until also the external reset request disappears Furthermore the status flag OWDS is set if the oscillator watchdog was active The status flag can be evaluated by software to detect that a reset was caused by the oscillator watchdog The flag OWDS can be set or cleared by software An external reset request however also resets OWDS and WDTS If software power down mode is activated the RC oscillator and the on chip oscillator is stopped Both oscillators are again started in power down mode when a low level is detected at the INTO input pin and when bit EWPD in SFR PCON1 is set wake up from power down mode enabled After the start up phase of the watchdog circuitry in power down mode a power down mode wake up interrupt is generated instead of an internal reset 8 2 2 Fast Internal Reset after Power On The C504 can use the oscillator watchdog unit for a fast internal reset procedure after power on Normally the members of the 8051 family e g S
109. eans that the value is undefined and the location is reserved 4 SFR is located in the mapped SFR area For accessing this SFR bit RMAP in SFR SYSCON must be set Semiconductor Group SIEMENS Memory Organization C504 Table 3 2 Contents of the SFRs SFRs in numeric order of their addresses Addr Register Content Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit 1 Bit 0 after Reset 8042 PO FFy T 6 5 4 3 2 1 0 81H SP 07H 7 6 5 4 3 2 1 0 82H DPL 00H 7 6 5 4 3 2 1 0 83H DPH 00H T4 6 5 4 3 2 1 0 864 WDTREL 00y WDT 6 5 4 3 2 1 0 PSEL 87H PCON 000X SMOD IPDS IDLS GF1 GFO PDE IDLE 0000p 88 2 TCON 00H TF1 TR1 TFO TRO IE1 IT1 IEO ITO 88 29 PCON1 OXXX EWPD XXXXB 894 TMOD 00H GATE C T M1 MO GATE C T M1 MO 8Ay TLO 00H 7 6 5 4 3 2 1 8By ITLI 00H 7 6 5 4 d 2 1 8Cy THO 00H M 6 5 4 3 2 1 8Dy TH 00H T 6 5 4 3 2 1 90942 P1 FFy FA 6 i5 4 3 2 T2EX T2 90429 P1ANA XXXX EAN3 EAN2 EAN EANO 1111B 98H SCON 00H SMO SM1 SM2 REN TB8 RB8 TI RI 99h SBUF XXH 7 6 5 4 3 2 1 0 9A ITCON 0010 IT2 IE2 IZETF I2ETR HETF METR IOETF IOETR 1010p A0y P2 FFy M 6 ES 4 3 2 1 0 A8y IENO 0X00 EA ET2 ES ET1 EX1 ETO EX0 0000p A94 IEN1 XX00 ECT1 ECCM ECT2 ECEM EX2 EADC 0000p 1 X means that the value is undefined and the location is reserved
110. ection 6 1 3 2 and 6 1 3 4 The analog input function of these digital analog port lines is selected via the registers P1 ANA and P3ANA These two registers are mapped registers and can be accessed when bit RMAP in SFR SYSCON is set when writing to its address 904 or BO If the specific bit location of P1 ANA or P3ANA is set the corresponding port line is configured as an digital input With a O in the bit location the port line operates as analog port Special Function Registers P1ANA Address 90 Reset Value XXXX1111p Special Function Registers P3ANA Address B0y Reset Value XX1111XXp Bit No MSB LSB 7 6 5 4 3 2 1 0 90H EAN3 EAN2 EAN1 EANO P1ANA Bow EAN7 EAN6 EAN5 EAN4 P3ANA Bit Function EAN3 EANO Enable analog port 1 inputs If EANx x 3 0 is cleared port pin P1 x is enabled for operation as an analog input If EANx is set port pin P1 x is enabled for digital I O function default after reset EAN7 EAN4 Enable analog port 1 input If EANx x 7 4 is cleared port pin P3 x 2 is enabled for operation as an analog input If EANx is set port pin P3 x 2 is enabled for digital I O function default after reset Semiconductor Group 6 105 SIEMENS Interrupt System C504 7 Interrupt System The C504 provides 12 interrupt sources with two priority levels Eight interrupts can be generated by the on
111. ection is changed from down to up counting when the compare timer value has reached 0000j4 Generally the compare outputs CCx are always assigned to a match condition with the compare timer value directly while the compare outputs COUTx are assigned to a match condition with the compare timer value plus the offset value Therefore signal waveforms with non overlapping signal transitions as shown in figure 6 19 b and d can be generated Further the initial logic output level of the CAPCOM channel outputs when used in compare mode can be selected This allows to generate waveforms with inverting signal polarities In capture mode of the CAPCOM unit the value of the compare timer 1 is stored in the capture registers if a signal transition occurs at the pins CCx The compare unit COMP is a 10 bit compare unit which can be used to generate a pulse width modulated signal This PWM output signal drives the output pin COUTS In burst mode and in the PWM modes the output of the COMP unit can be switched to the COUTx outputs The block commutation control logic allows to generate versatile multi channel PWM output signals In one of theses modes the block commutation mode signal transitions at the three external interrupt inputs are used to trigger the PWM signal generation logic Depending on these signal transitions the six I O lines of the CAPCOM unit which are decoupled in block commutation mode from the three capture compare channels are driven
112. ed after wake up is 007B p After the RETI instruction of the power down wake up interrupt routine has been executed the instruction which follows the initiating power down mode double instruction sequence will be executed The peripheral units timer 0 1 2 CCU and WDT are frozen until end of phase 4 All interrupts of the C504 are disabled from phase 2 until the end of phase 4 Other Interrupts can be first handled after the RETI instruction of the wake up interrupt routine Semiconductor Group 9 7 SIEMENS Device Specifications C504 10 Device Specifications 10 1 Absolute Maximum Ratings Ambient temperature under bias Ta cccccconnnoccccnnnnnccnnnonananancnnnncnnnnnnnnnnnnnnos 0 C to 4 70 Storage temperature T3 oisi bte eb rtl IE enun nel P bx ia ud 65 to 150 C Voltage on Vec pins with respect to ground Vss coooococcccccnnccconanananaccnnnanonannos 0 5Vt06 5V Voltage on any pin with respect to ground Vias 0 5V to Voc 0 5 V Input current on any pin during overload condition ssseesssesss 10 mA to 10 mA Absolute sum of all input currents during overload condition 100 mA Power dissipation certe rt eR Eo RE Ee Ho ee TBD Note Stresses above those listed under Absolute Maximum Ratings may cause permanent damage of the device This is a stress rating only and functional operation of the device at these or any other conditi
113. ed in mode O by the condition RI 0 and REN 1 Reception is initiated in the other modes by the incoming start bit if REN 1 The serial interfaces also provide interrupt requests when a transmission or a reception of a frame has completed The corresponding interrupt request flags for serial interface O are TI or RI resp See chapter 7 of this user manual for more details about the interrupt structure The interrupt request flags TI and RI can also be used for polling the serial interface O if the serial interrupt is not to be used i e serial interrupt O not enabled Semiconductor Group 6 78 SIEMENS On Chip Peripheral Components C504 6 4 4 Multiprocessor Communications Modes 2 and 3 have a special provision for multiprocessor communications In these modes 9 data bits are received The 9th one goes into RB8 Then comes a stop bit The port can be programmed such that when the stop bit is received the serial port interrupt will be activated only if RB8 1 This feature is enabled by setting bit SM2 in SCON A way to use this feature in multiprocessor systems is as follows When the master processor wants to transmit a block of data to one of several slaves it first sends out an address byte which identifies the target slave An address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte With SM2 1 no slave will be interrupted by a data byte An address byte however will interrupt all
114. efore the on chip oscillator has started The oscillator watchdog unit also works identically to the monitoring function Control of external wake up from software power down mode When the power down mode is left by a low level at the INTO pin the oscillator watchdog unit assures that the microcontroller resumes operation execution of the power down wake up interrupt with the nominal clock rate In the power down mode the RC oscillator and the on chip oscillator are stopped Both oscillators are started again when power down mode is released When the on chip oscillator has a higher frequency than the RC oscillator the microcontroller starts operation after a final delay of typ 1 ms in order to allow the on chip oscillator to stabilize Note The oscillator watchdog unit is always enabled Semiconductor Group 8 5 SIEMENS Fail Safe Mechanisms C504 8 2 1 Detailed Description of the Oscillator Watchdog Unit Figure 8 2 shows the block diagram of the oscillator watchdog unit It consists of an internal RC oscillator which provides the reference frequency for the comparison with the frequency of the on chip oscillator Power Down Mode Activated x sl Power Down Mode P3 2 Control Control Wake Up Interrupt INTO Logic Logic e Internal Reset Start Stop e RC Oscillator fre Frequency Comparator XTAL1 On Chip XTALD O Oscillator WDCON CO y Ld
115. elected PWM1 0 0 0 all enabled compare outputs COUTx and CCx are switched to the compare timer 2 output signal during their active phase If BCMP is cleared only the COUTx outputs are switched to the compare timer 2 output signal during the active phase in multi channel PWM mode CMSELx3 must be set for that functionality BCEM In block commutation mode Error mode select bit If BCEM is set in block commutation mode in rotate right or rotate left mode additionally a wrong follower condition causes the setting of BCERR if EBCE is set Semiconductor Group 6 66 SIEMENS On Chip Peripheral Components C504 Bit Function PWM1 Multi channel PWM mode selection PWMO These bits select the operating mode of the multi channel PWM modes PWM1 PWMO Function 0 0 Block commutation mode 0 1 4 pole multi channel PWM mode 1 0 5 pole multi channel PWM mode 1 1 6 pole multi channel PWM mode EBCE Enable interrupt of block commutation mode error If EBCE is set the emergency interrupt for a block commutation mode error condition of the CCU is enabled In block commutation mode an emergency error condition occurs if a false signal state at INT2 INTO or a wrong follower state if selected by bit BCEM is detected see also table 6 9 BCERR Block commutation mode error flag In block commutation mode BCERR is set in rotate right or rotate left mode if after a transition at INTx all INTx inputs are at
116. emiconductor Group 6 68 SIEMENS On Chip Peripheral Components C504 Compare Timer 1 Mode 0 CCx COUTx Compare Timer 1 Mode 1 CCx COUTx Compare Timer 1 Mode 0 CCx COUTx Compare Timer 1 Mode 1 COINI Bit 1 MAA E p E p COINI Bit 1 ANAND Compare Timer 1 Mode 0 CCx COUTx Compare Timer 1 Mode 1 CCx COUTx Compare Timer 1 Mode 0 CCx COUTx Compare Timer 1 Mode 1 CCx COUTx a No transitions in active phase offset and compare value 0 COINI Bit 0 AAA V0 _ TW b CAPCOM transitions in active phase 0 lt compare value lt period value offset value 0 COINI Bit 0 VV MCT02609 Figure 6 29 Compare Timer 1 Controlled Active Phase of the Multi Channel PWM Modes with CMSELx 3 0 Semiconductor Group 6 69 SIEMENS On Chip Peripheral Components Figure 6 30 shows the different possibilities for controlling the active phase of a compare output signal using compare timer 2 In this operating mode which is selected when bit CMSELx 3 is set the compare timer 2 output signal is switched to the COUTx or CCx outputs during the active phase of a multi channel PWM signal Bit BCEN BCON 7 defines whether only COUTx or COUTx and CCx are provided by the compare timer 2 output signal Depending on the bits COUT3l and COUTXI of COINI the polarity of COUT3
117. ernally started by writing into the SFR ADDATL with dummy data A write to SFR ADDATL will start a new conversion even if a conversion is currently in progress The conversion begins with the next machine cycle and the BSY flag in SFR ADCONO will be set The A D conversion procedure is divided into three parts Sample phase ts used for sampling the analog input voltage Conversion phase tco used for the A D conversion includes calibration Write result phase twp used for writing the conversion result into the ADDAT registers The total A D conversion time is defined by tapcc which is the sum of the two phase times tg and tco The duration of the three phases of an A D conversion is specified by its specific timing parameter as shown in figure 6 41 Start of Result is written A D Conversion into ADDAT v BSY Bit Conversion Phase Write Result Phase too fance A D Conversion Cycle Time tance ts fco PS Prescaler Value MCT02619 Prescaler Ratio tg tco PS 2 x PS x tin 32 64 x tin 16 32 X tin 8 16 x tin 4 8 X tin Figure 6 41 A D Conversion Timing Sample Time ts During this time the internal capacitor array is connected to the selected analog input channel and is loaded with the analog voltage to be converted The analog voltage is internally fed to a voltage comparator With beginning of the sample phase the BSY bit in SFR ADCONO is set Semicondu
118. errupt is disabled Compare timer 1 operating mode 0 Bit has no effect on the interrupt generation Compare timer 1 operating mode 1 If ECTC 1 an interrupt is generated when compare timer 1 reaches count value 0000y and changes its count direction from down to up counting Semiconductor Group 6 54 SIEMENS On Chip Peripheral Components C504 Bit Function CCxREN x 0 2 Capture compare rising edge interrupt enable Capture Mode If CCxREN is set an interrupt is generated at a low to high transition rising edge of the corresponding CCx input signal Compare Mode If CCxREN is set an interrupt is generated if the compare timer 1 value matches the compare register CCx value during the up counting phase of the compare timer 1 This function is available in both compare timer 1 operating modes CCxFEN x 0 2 Capture compare falling edge interrupt enable Capture Mode If CCxFEN is set an interrupt is generated at a high to low transition falling edge of the corresponding CCx input signal Compare Mode If CCxFEN is set an interrupt is generated only in compare timer mode 1 if the compare timer 1 value matches the compare register CCx value during the down counting phase of the compare timer 1 This function is available only in compare timer 1 operating mode 1 Semiconductor Group 6 55 SIEMENS On Chip Peripheral Components C504 Compare Output Initialization Reg
119. errupts the USART interrupt and the AD converter interrupt The external interrupt 2 and the four interrupts of the CCU are enabled disabled by bits in the IEN1 register After reset the enable bits of IEO and IE1 are set to 0 That means that the corresponding interrupts are disabled Special Function Registers IENO Address A8j Reset Value 0X000000p Bit No MSB LSB AFH AEH ADy ACH ABH AAH A9H A8H A8H EA ET2 ES ET1 EX1 ETO EX0 IENO Bit Function EA Disables all Interrupts If EA 0 no interrupt will be acknowledged If EA 1 each interrupt source is individually enabled or disabled by setting or clearing its enable bit Reserved bits for future use ET2 Timer 2 interrupt enable If ET2 1 the Timer 2 interrupt is enabled ES Serial channel interrupt enable If ES 1 the Serial Channel interrupt is enabled ET1 Timer 1 overflow interrupt enable If ET1 1 the Timer 1 interrupt is enabled EX1 External interrupt 1 enable If EX1 1 the external interrupt 1 is enabled ETO Timer 0 overflow interrupt enable If ETO 1 the Timer 0 interrupt is enabled EXO External interrupt O enable If EXO 1 the external interrupt 0 is enabled Semiconductor Group 7 5 SIEMENS Interrupt System C504 Special Function Registers IEN1 Address A9y Reset Value XX000000g Bit No MSB LSB 7 6 5 4 3 2 1 0 A9H E ECT1 ECOM
120. escribe the CAPCOM registers in detail Writing the CAPCOM Period Offset Compare Registers on the Fly If the compare timer 1 is running period offset or compare register can be written with modified values for generating new periods or duty cycles of the compare output signals For proper synchronization purposes a special mechanism for updating of the 16 bit offset period and compare registers is implemented in the C504 This mechanism is based on shadow latches When new values for offset period or compare registers have been written into the shadow latches the real register update operation must be initiated by setting bit STE1 shadow transfer enable in SFR CT1CON When this bit is set the content of the shadow latches is transferred to the real registers under the following conditions Compare timer 1 operating mode O Compare timer 1 has reached the period value stored in the CCPH CCPL registers Compare timer 1 operating mode 1 Compare timer 1 has reached the count value 0000 y When the register transfer has been executed STE1 is reset by hardware So the software can recognize when the register transfer has occurred When the compare timer 1 is started by setting the run bit CT1R the first time after reset a shadow register transfer into the real registers is automatically executed In this case STE1 must not be set Semiconductor Group 6 44 SIEMENS On Chip Peripheral Components C504 Compare Timer 1 Control Re
121. ess In this state port O is disconnected from its own port latch and the address data signal drives both FETs in the port 0 output buffers Thus in this application the port 0 pins are not open drain outputs and do not require external pullup resistors During any access to external memory the CPU writes FF to the port 0 latch the special function register thus obliterating whatever information the port 0 SFR may have been holding Whenever a 16 bit address is used the high byte of the address comes out on port 2 where it is held for the duration of the read or write cycle During this time the port 2 lines are disconnected from the port 2 latch the special function register Thus the port 2 latch does not have to contain 1s and the contents of the port 2 SFR are not modified If an 8 bit address is used MOVX Ri the contents of the port 2 SFR remain at the port 2 pins throughout the external memory cycle This will facilitate paging It should be noted that if a port 2 pin outputs an address bit that is a 1 strong pullups will be used for the entire read write cycle and not only for two oscillator periods Semiconductor Group 4 1 SIEMENS External Bus Interface C504 Timing The timing of the external bus interface in particular the relationship between the control signals ALE PSEN RD WR and information on port 0 and port 2 is illustrated in figure 4 1 a and b Data memory in a write cycle the data byte to be
122. evices with float times up to 75 ns is permissible This limited bus contention will not cause any damage to port O drivers Semiconductor Group 10 6 SIEMENS Device Specifications C504 AC Characteristics for C504 L C504 2R cont d External Data Memory Characteristics Parameter Symbol Limit Values Unit 12 MHz clock Variable Clock l fc c 3 5 MHz to 12 MHz min max min max RD pulse width TRLRH 400 6tcoLc 100 ns WR pulse width wiwH 400 6t c 100 ns Address hold after ALE Laxe 114 2tac 53 ns RD to valid data in fai pv 252 5torc 165 ns Data hold after RD RHDX 0 0 ns Data float after RD RHDZ 97 2tec 70 ns ALE to valid data in fiiov 517 8tcoic 150 ns Address to valid data in favpv 585 9fo c 165 ns ALE to WR or RD fiw 200 300 Steric 50 3tgg 50 ns Address valid to WR or RD TAVWL 203 Afore 130 ns WR or RD high to ALE high twin 143 123 uM Ifac 40 Ins Data valid to WR transition Lovwx 33 faic 50 ns Data setup before WR TovwH 433 7torc 150 ns Data hold after WR fwHax 33 faic 50 ns Address float after RD TRLAz 0 0 ns External Clock Drive Parameter Symbol Limit Values Unit Variable Clock Freq 3 5 MHz to 12 MHz min max Oscillator period feet 83 3 294 ns High time cucx 20 toro feicx ns
123. g applications The C504 2R contains a non volatile 16Kx8 read only program memory a volatile on chip 512x8 read write data memory four 8 bit wide ports three 16 bit timers counters a 16 bit capture compare unit a 10 bit compare timer a twelve source two priority level interrupt structure a serial port versatile fail save mechanisms on chip emulation support logic and a genuine 10 bit A D converter The C504 L is identical to the C504 2R except that it lacks the on chip program memory Therefore the term C504 refers to all versions within this documentation unless otherwise noted Oscillator Watchdog XRAM RAM Porto PK gt 1 0 10 Bit ADC 256x8 256x8 Timer 2 it Digi Do mel O 5 8 Digitol 1 0 16 Bi gt 4 Bit Analog Inputs Capture Compare E T1 Port2 IK gt 1 0 10 Bit Compare Unit y 8 Bit Digital 1 0 Watchdog Timer gt 4 Bi Analog Inputs MCB02589 On Chip Emulation Support Module Figure 1 1 C504 Functional Units Semiconductor Group 1 1 SIEMEN Introduction 2 C504 Listed below is a summary of the main features of the C504 Fully compatible to standard 8051 microcontroller Upto 40 MHz external operating frequency 16 Kx8 ROM C504 2R only 256x8 RAM e 256x8 XRAM Four 8 bit ports 2 ports with mixed analog digital I O capability Three 16 bit timers counters timer 2 with up down counter feature Capture compare unit for PWM signal generation and signal capturing 3 ch
124. gister The 16 bit compare timer 1 is controlled by the bits of the CT1CON register With this register the count mode the trap interrupt enable the compare timer start stop and reset and the timer input clock rate is controlled Special Function Register CT1CON Address El y Reset Value 00010000g Bit No Ely MSB LSB 6 5 4 3 2 1 0 CTM ETRP STE1 CT1RES CT1R CLK2 CLK1 CLKO CT1CON Bit Function CTM Compare timer 1 operating mode selection CTM 0 selects operating mode 0 up count and CTM 1 selects operating mode 1 up down count for compare timer 1 ETRP CCU emergency trap interrupt enable If ETRP 1 the emergency interrupt for the CCU trap signal is enabled STE1 CAPCOM unit shadow latch transfer enable When STE1 is set the content of the compare timer 1 period compare and offset registers CCPH CCPL CCHx CCLx CT1OFH CT1OFL is transferred to its real registers when compare timer 1 reaches the next time the period value operating mode 0 or value 0000y operating mode 1 After the shadow transfer event STE1 is reset by hardware CLK2 Compare timer 1 input clock selection CLK1 The input clock for the compare timer 1 is derived from the clock rate fosc of CLKO the C504 via a programmable prescaler The following table shows the programmable prescaler ratios CLK2 CLK1 CLKO Function Compare timer 1 input clock is fog 2 Compare t
125. gure 6 4 shows a functional diagram of a port latch with alternate function To pass the alternate function to the output pin and vice versa however the gate between the latch and driver circuit must be open Thus to use the alternate input or output functions the corresponding bit latch in the port SFR has to contain a one 1 otherwise the pulldown FET is on and the port pin is stuck at 0 After reset all port latches contain ones 1 Alternate V Output e Read Function Latch Internal Pull Up Arrangement e o Pin Int Bus MCS01827 Read Alternate Pin Input Function Figure 6 4 Ports 1 and 3 Semiconductor Group 6 6 SIEMENS On Chip Peripheral Components C504 6 1 2 3 Port 2 Circuitry As shown in figure 6 3 and below in figure 6 5 the output drivers of ports O and 2 can be switched to an internal address or address data bus for use in external memory accesses In this application they cannot be used as general purpose l O even if not all address lines are used externally The switching is done by an internal control signal dependent on the input level at the EA pin and or the contents of the program counter If the ports are configured as an address data bus the port latches are disconnected from the driver circuit During this time the PO P2 SFR remains unchanged Being an address data bus port 0 uses a pullup FET as shown in figure 6 5 When a 16 bit address is used port 2 uses the
126. he XTAL1 and XTAL2 pins The RESET signal must be active for at least one machine cycle after this time the C504 remains in its reset state as long as the signal is active When the signal goes inactive this transition is recognized in the following state 5 phase 2 of the machine cycle Then the processor starts its address output when configured for external ROM in the following state 5 phase 1 One phase later state 5 phase 2 the first falling edge at pin ALE occurs Figure 5 2 shows this timing for a configuration with EA 0 external program memory Thus between the release of the RESET signal and the first falling edge at ALE there is a time period of at least one machine cycle but less than two machine cycles One Machine Cycle s4 s5 s6 St S2 aa Md Dod oe paa E P ite des ae d rr aer Whe Pe Dn Te ME ais ites SLIT s ith al UE AAA i Pa m ALE MCT02092 Figure 5 2 CPU Timing after Reset Semiconductor Group 5 4 SIEMENS On Chip Peripheral Components C504 6 On Chip Peripheral Components 6 1 Parallel I O The C504 has four 8 bit I O ports Port 0 is an open drain bidirectional I O port while ports 1 to 3 are quasi bidirectional I O ports with internal pullup resistors That means when configured as inputs ports 1 to 3 will be pulled high and will source current when externally pulled low Port O will float when configured as input The output drivers of port 0
127. he power down is enabled IDLE Idle mode enable bit When set starting of the idle mode is enabled Semiconductor Group 9 1 SIEMENS Power Saving Modes C504 Special Function Register PCON1 Mapped Address 88H Reset Value OXXXXXXXp Bit No MSB 7 6 5 4 3 2 1 0 884 EWPD PCON1 Symbol Function Reserved for future use EWPD External wake up from power down enable bit Setting EWPD before entering power down mode enables the external wake up from power down mode capability via the pin INTO more details see section 9 2 Semiconductor Group 9 2 SIEMENS Power Saving Modes C504 9 1 Idle Mode In the idle mode the oscillator of the C504 continues to run but the CPU is gated off from the clock signal However the interrupt system the serial port the A D converter and all timers with the exception of the watchdog timer are further provided with the clock The CPU status is preserved in its entirety the stack pointer program counter program status word accumulator and all other registers maintain their data during idle mode The reduction of power consumption which can be achieved by this feature depends on the number of peripherals running If all timers are stopped and the A D converter and the serial interface are not running the maximum power reduction can be achieved This state is also the test condition for the idle mode Tec So
128. he read strobe for external fetches is PSEN PSEN is not activated for internal fetches When the CPU is accessing external program memory PSEN is activated twice every cycle except during a MOVX instruction no matter whether or not the byte fetched is actually needed for the current instruction When PSEN is activated its timing is not the same as for RD A complete RD cycle including activation and deactivation of ALE and RD takes 12 oscillator periods A complete PSEN cycle including activation and deactivation of ALE and PSEN takes 6 oscillator periods The execution sequence for these two types of read cycles is shown in figure 4 1 a and b 4 3 Overlapping External Data and Program Memory Spaces In some applications it is desirable to execute a program from the same physical memory that is used for storing data In the C504 the external program and data memory spaces can be combined by AND ing PSEN and RD A positive logic AND of these two signals produces an active low read strobe that can be used for the combined physical memory Since the PSEN cycle is faster than the RD cycle the external memory needs to be fast enough to adapt to the PSEN cycle Semiconductor Group 4 2 SIEMENS External Bus Interface C504 a e One Machine Cycle One Machine Cycle s1 s2 s3 s4 s5 s6 s1 s2 s3 s4 s5 se ALE PSEN A RD without MOVX O
129. he unit goes back to looking for another 1 to 0 transition This is to provide rejection or false start bits If the start bit proves valid it is shifted into the input shift register and reception of the rest of the frame will proceed As data bits come in from the right 1s shift out to the left When the start bit arrives at the leftmost position in the shift register which in mode 1 is a 9 bit register it flags the RX control block to do one last shift load SBUF and RB8 and set RI The signal to load SBUF and RB8 and to set RI will be generated if and only if the following conditions are met at the time the final shift pulse is generated 1 RI 0 and 2 Either SM2 0 or the received stop bit 1 If either of these two condtions is not met the received frame is irretrievably lost If both conditions are met the stop bit goes into RB8 the 8 data bit goes into SBUF and RI is activated At this time whether the above conditions are met or not the unit goes back to looking for a 1 to 0 transition in RXD Semiconductor Group 6 88 SIEMENS On Chip Peripheral Components C504 S Internal Bus Write mA aul D D SBUF Shift TX Control Baud Rate Clock Interrupt 1 to 0 Load r Transition SBUF Detector RX Control 1FF y Shift Detector Input Shift Register 9Bits RXD Load SBUF SBUF Read sir V 6 Internal Bus 2 MCS02103
130. high and TRx control bit is set When cleared timer x is enabled whenever TRx control bit is set C T Counter or timer select bit Set for counter operation input from Tx input pin Cleared for timer operation input from internal system clock M1 Mode select bits MO s M1 MO Function 0 0 8 bit timer counter THx operates as 8 bit timer counter TLx serves as 5 bit prescaler 0 1 16 bit timer counter THx and TLx are cascaded there is no prescaler 1 0 8 bit auto reload timer counter THx holds a value which is to be reloaded into TLx each time it overflows 1 1 Timer O TLO is an 8 bit timer counter controlled by the standard timer 0 control bits THO is an 8 bit timer only controlled by timer 1 control bits Timer 1 Timer counter 1 stops Semiconductor Group 6 19 SIEMENS On Chip Peripheral Components C504 6 2 1 1 Mode 0 Putting either timer counter 0 1 into mode 0 configures it as an 8 bit timer counter with a divide by 32 prescaler Figure 6 11 shows the mode 0 operation In this mode the timer register is configured as a 13 bit register As the count rolls over from all 1 s to all 0 s it sets the timer overflow flag TFO The overflow flag TFO then can be used to request an interrupt The counted input is enabled to the timer when TRO 1 and either Gate 0 or INTO 1 setting Gate 1 allows the timer to be controlled by external input INTO to facili
131. ia the INTO wake up capability Execution of Qu Power Down Lt Watchdog Circuit _ Interrupt Mode Oscillator Start up Phase at 007B y 1 3 4 A 10 us rim Sms typ RETI Instruction Detailed Timing of Beginning of Phase 4 ALE Hj mala Address Data 7 ATA Ist ns MCT02597 Figure 9 1 Wake up from Power Down Mode Procedure Semiconductor Group 9 6 SIEMENS Power Saving Modes C504 When the power down mode wake up capability has been enabled bit EWPD in SFR PCON1 set prior to entering power down mode the power down mode can be exit via INTO while executing the following procedure 1 2 In power down mode pin INTO must be held at high level Power down mode is left when INTO goes low With INTO low the internal RC oscillator is started INTO is then latched by the RC oscillator clock signal Therefore INTO should be held at low level for at least 10 us latch phase After this delay INTO can be set again to high level if required Thereafter the oscillator watchdog unit controls the wake up procedure in its start up phase The oscillator watchdog unit starts operation as described in section 8 2 1 When the on chip oscillator clock is detected for stable nominal frequency the microcontroller further waits for a delay of typically 1ms and then starts again with its operation initiating the power down wake up interrupt The interrupt address of the first instruction to be execut
132. illator is running resets the device An internal diffused resistor to Vss permits power on reset using only an external capacitor to Vec 2 Input O Output Semiconductor Group 1 5 SIEMEN Introduction 2 C504 Table 1 1 Pin Definitions and Functions cont d Symbol Pin Number l O Function P MQFP 44 P3 0 P3 7 5 7 13 O Port3 is an 8 bit bidirectional port P3 0 RxD and P3 1 TxD operate as defined for the C501 P3 2 to P3 7 contain the external interrupt inputs timer inputs input and as an additional optinal function four of the analog inputs of the A D converter Port 3 pins are assigned to be used as analog inputs by the bits of SFR P3ANA P3 6 WR can be assigned as a third interrupt input The functions are assigned to the pins of port 3 as follows 5 P3 0 RxD Receiver data input asynch or data input output synch of serial interface 7 P3 1 TxD Transmitter data output asynch or clock output synch of serial interface 8 P3 2 AN4 INTO Analog input channel 4 external interrupt O input timer O gate control input 9 P3 3 AN5 INT1 Analog input channel 5 external interrupt 1 input timer 1 gate control input 10 P3 4 AN6 TO Analog input channel 6 timer 0 counter input 11 P3 5 AN7 T1 Analog input channel 7 timer 1 counter input 12 P3 6 WR INT2 WR control output latches the data byte from port 0 into the external data memory external interrupt 2 input
133. imer 1 input clock is fogc 4 Compare timer 1 input clock is fosc 8 Compare timer 1 input clock is fosc 16 Compare timer 1 input clock is fos 32 Compare timer 1 input clock is fosc 64 Compare timer 1 input clock is fos 128 0 o0 o o OIO oOo 0 1 0 1 0 1 0 1 Compare timer 1 input clock is fosc 256 Semiconductor Group 6 45 SIEMENS On Chip Peripheral Components C504 Bit Function CT1RES Compare timer 1 reset control CT1R Compare timer 1 run stop control These two bits controls the start stop and reset function of the compare timer 1 CT1RES is used to reset the compare timer and CT1R is used to start and stop the compare timer 1 The following table shows the functions of these two bits CT1RES CT1R Function 0 0 Compare timer 1 is stopped and holds its value the compare outputs stay in the logic state as they are 1 0 Compare timer 1 is stopped and reset compare outputs are set to the logic state as defined in SFR COINI default after reset 0 0 gt 1 Compare timer 1 starts Before CT1R is set the first time the CMSEL register should be programmed enable capture compare functions 1 0 gt 1 Compare timer 1 starts running from count value 0000y compare outputs are set to the logic state as defined in SFR COINI 0 1 0 Compare timer 1 is stopped and holds its value the compare outputs drive their actual
134. imer 1 is running interrupts can be generated at a period match or a count direction change event The lower 6 bits of CCIE are the CAPCOM channel specific interrupt enable disable control bits for the capture or compare match interrupt The functions of these bits depend on the selected mode capture or compare of a capture compare channel In compare mode compare channel specific interrupts can be generated at a match event between compare register content and compare timer 1 count value during the up or down counting phase of compare timer 1 In capture mode capture channel specific interrupts can be generated selectively at rising or falling or both edges of the capture input signals at CCx Special Function Registers CCIE Address D6jy Reset Value 00y Bit No MSB LSB 7 6 5 4 3 2 1 0 D6y ECTP ECTC CC2FEN CC2REN CC1FEN CCTREN CCOFEN CCOREN CCIE Bit Function ECTP Enable compare timer 1 period interrupt If ECTP 0 the compare timer 1 period interrupt is disabled Compare timer 1 operating mode O If ECTP 1 an interrupt is generated when compare timer 1 reaches the period value Compare timer 1 operating mode 1 If ECTP 1 an interrupt is generated when compare timer 1 reaches the period value and changes the count direction from up to down counting ECTC Enable compare timer 1 count direction change interrupt enable If ECTC 0 the compare timer 1 count change int
135. imulated externally An external stimulation at these lines during reset activates several test modes which are reserved for test purposes This in turn may cause unpredictable output operations at several port pins At the reset pin a pulldown resistor is internally connected to Vss to allow a power up reset with an external capacitor only An automatic reset can be obtained when Vec is applied by connecting the reset pin to Voc via a capacitor After Voc has been turned on the capacitor must hold the voltage level at the reset pin for a specific time to effect a complete reset A correct reset leaves the processor in a defined state The program execution starts at location 00004 After reset is internally accomplished the port latches of ports 0 2 and 3 default in FFy This leaves port 0 floating since it is an open drain port when not used as data address bus All other l O port lines ports 2 and 3 output a one 1 Port 1 which is a input only port has no internal latch and therefore the contents of the special function register P1 depends on the levels applied to port 1 The contents of the internal RAM and XRAM of the C504 is not affected by a reset After power up the contents are undefined while it remains unchanged during a reset if the power supply is not turned off Semiconductor Group 5 1 SIEMENS System Reset C504 5 2 Fast Internal Reset after Power On The C504 uses the oscillator watchdog unit for a fast internal
136. in CT1CON and therafter BCM1 0 can be put into another mode than the idle mode Semiconductor Group 6 67 SIEMENS On Chip Peripheral Components C504 6 3 4 2 Signal Generation in Multi Channel PWM Modes The multi channel PWM modes of the C504 use the pins CCx and COUTx for compare output signal generation Before signal generation of a multi channel PWM mode can be started the COINI register should be programmed with the logic value of the multi channel PWM inactive phase After this the output pins which are required for the multi channel PWM signal generation must be programmed to operate as compare outputs by writing the mode select registers CMSELO and CMSEL1 Table 6 8 shows the CMSELO CMSELt1 register bits which are required for the full operation of the multi channel PWM modes Table 6 8 Programming of Multi Channel PWM Compare Outputs Multi Channel PWM Mode CMSEL1 CMSELO Block commutation XXXX Y011p Y011 YO11p 6 pole multi channel PWM 5 pole multi channel PWM Y010 YO11p 4 pole multi channel PWM Y010 YO01p Note The abrevation X means don t care The abrevation Y bit CMSELx 3 represents the burst mode bit If Y 0 the signal generation at the COUTx pins is controlled by compare timer 1 If Y 1 the signal generation at the COUTx pins is also controlled by compare timer 1 but modulated by compare timer 2 Definition of the active and inactive phase of a PWM signal A PWM output signal of
137. ined from timer 1 Table 6 13 Timer 1 Generated Commonly Used Baud Rates Baud Rate fosc SMOD Timer 1 C T Mode Reload Value Mode 0 max 1 MHz 12 MHz X X X X Mode 2 max 375 K 12 MHz 1 X X X Modes 1 3 62 5 K 12 MHz 1 0 2 FFy 19 2 K 11 059 MHz 1 0 2 FDH 9 6 K 11 059 MHz 0 0 2 FDy 4 8K 11 059 MHz 0 0 2 FAH 2 4K 11 059 MHz 0 0 2 F4y 1 2K 11 059 MHz 0 0 2 ESy 110 6 MHz 0 0 2 72H 110 12 MHz 0 0 1 FEEBH Semiconductor Group 6 82 SIEMENS On Chip Peripheral Components C504 6 4 3 2 Using Timer 2 to Generate Baud Rates Timer 2 is selected as the baud rate generator by setting TCLK and or RCLK in T2CON Note then the baud rates for transmit and receive can be simultaneously different Setting RCLK and or TCLK puts timer 2 into its baud rate generator mode as shown in figure 6 35 Timer 1 Overflow OSC c T2 0 Control P1 0 T2 g Deo TX CLOCK 16 Control P1 1 T2EX gt PE eco gt EXF2 Timer 2 Interrupt EXEN2 MCS02586 Figure 6 35 Timer 2 in Baud Rate Generator Mode The baud rate generator mode is similar to the auto reload mode in that rollover in TH2 causes the timer 2 registers to be reloaded with the 16 bit value in registers RC2H and RC2L which are preset by software Now the baud rates in modes 1 and 3 are determined by timer 2 s overflow rate as follows Modes 1 3 baud rate timer 2 overflow rate 16 Semiconductor Group
138. ing edge of RESET With each following ALE pulse the ROM address pointer is internally incremented and the expected data byte for the next ROM address must be delivered externally Between two ALE pulses the data at port 0 is latched at 6 tz c after ALE rising edge and compared internally with the ROM content of the actual address If an verify error is detected the error Semiconductor Group 4 9 SIEMENS External Bus Interface C504 condition is stored internally After each 16th data byte the cumulated verify result pass or fail of the last 16 verify operations is output at P3 5 P3 5 is always set or cleared after each 16 byte block of the verify sequence In ROM verification mode 2 the C504 2R must be provided with a system clock at the XTAL pins Figure 4 5 shows an application example of a external circuitry which allows to verify a protected ROM inside the C504 in ROM verification mode 2 With RESET going inactive the C504 2R starts the ROM verify sequence Its ALE is clocking an 14 bit address counter This counter generates the addresses for an external EPROM which is programmed with the content of the internal protected ROM The verify detect logic typically displays the state of the verify error output P3 5 P3 5 can be latched with the falling edge of ALE When the last byte of the internal ROM has been handled the C504 starts generating a PSEN signal This signal or the CY signal of the address counter indicate to the ve
139. inition of the three multi pole PWM modes It also includes the information the slow down mode and idle mode casd bits BMC1 0 0 0 and 1 1 Table 6 10 4 Pole PWM Timing State Table Actual State and PWM Phase Follower State No No Output Signals BCM1 BCMO CCO COUT1 CC2 COUT2 0 1 1 0 0 0 1 1 0 inactive inactive inactive inactive 2 1 0 5 1 active inactive inactive active 4 2 0 5 2 active active inactive inactive 1 3 0 5 3 inactive active active inactive 2 4 0 5 4 inactive inactive active active 3 1 0 5 5 inactive active inactive active 2 1 0 5 Note In the inactive phase the PWM outputs drive a logic state as defined by the related bits in register COINI Table 6 11 5 Pole PWM Timing State Table Actual State and PWM Phase Follower State No No Output Signals BCM1 BCMO CCO COUT1 CC2 COUTO COUT2 0 1 0 0 0 1 1 0 inactive inactive inactive inactive inactive 2 1 0 6 1 active inactive inactive inactive active 5 2 0 6 2 active active inactive inactive inactive 1 3 0 6 3 inactive active active inactive inactive 2 4 0 6 4 inactive inactive active active inactive 3 5 0 6 5 inactive inactive inactive active active 4 1 0 6 6 inactive active inactive active active 2 1 0 6 Note In the inactive phase the
140. ion of the capture input signal at 0 The capture mode is selected by writing the mode select registers CMSEL1 and CMSELO with the appropriate values The bit combinations in CMSELO and CMSEL1 also define the signal transition type falling rising edge which generates a capture event If a CAPCOM channel is enabled for capture mode its CCx input is sampled with 2 tc cL fosc 2 half external CPU clock rate Consecutive capture events generated through signal transitions at a CCx capture input overwrite the corresponding 16 bit compare capture register contents This must be regarded when successive signal transitions are processed Semiconductor Group 6 41 SIEMENS On Chip Peripheral Components C504 6 3 2 7 Trap Function of the CAPCOM Unit in Compare Mode When a channel of the CAPCOM unit operates in compare mode its output lines can be decoupled in trap mode from the CAPCOM pulse generation The trap mode is controlled by the external signal CTRAP The CTRAP signal is sampled once each 2nd oscillator clock cycle If a low is detected the trap flag TRF of register TRCON is set and CCx or COUTx compare outputs are switched immediately to the logic inactive state as defined by the bits in COINI If CT1RES 0 compare timer 1 continues its operation but no compare output signal will be generated If CTRES 1 compare timer 1 is reset when CTRAP becomes active When CTRAP is sampled inactive high again the compare channel outputs
141. ister COINI The six lower bits of the COINI register define the initial values of the port 1 lines which are programmed to be used as a compare output If an output of the CAPCOM unit is enabled for compare mode operation by writing the corresponding bit combination into the CMSELO CMSEL1 registers the compare output is switched into push pull mode and starts driving an initial logic level as defined by the bits of the COINI register The value of the bits of COINI may be is further selectively switched to the compare outputs during the trap state Bit COUTXI controls an inverter for the COMP unit output signal when it is wired to the CCx and COUTx outputs in burst or multi channel PWM mode COUTSI defines the initial logic level at COUT3 before compare timer 2 is started as well as the logic state when COUTS is disabled by setting bit ECT2O in SFR CT2CON see figure 6 27 The COINI register should be written prior to the starting of the compare timers Any write operation to the COINI register when the compare timer is running will affect the compare output signals immediately and drive the logic value as defined by the bits of COINI Special Function Register COINI Address E24 Reset Value FFy Bit No MSB LSB 7 6 5 4 3 2 1 0 E2H COUT3I COUTXI COUT2I CC2l COUT1I CC1l COUTOI CCol COINI CAPCOM CAPCOM CAPCOM Channel 2 Channel 1 Channel 0 Bit Function COUTSI COUTS initial logic level This b
142. it changes it should be held for at least one full machine cycle Semiconductor Group 6 24 SIEMENS On Chip Peripheral Components C504 Special Function Register T2CON Address C8y Reset Value 00y Bit No MSB LSB 7 6 5 4 3 2 1 0 CFy CEH CDu CCH CBH CAH C9H C8H C8y TF2 EXF2 RCLK TCLK EXEN2 TR2 C T2 CP RL2 T2CON Bit Function TF2 Timer 2 Overflow Flag Set by a timer 2 overflow Must be cleared by software TF2 will not be set when either RCLK 1 or TCLK 1 EXF2 Timer 2 External Flag Set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 1 When timer 2 interrupt is enabled EXF2 1 will cause the CPU to vector to the timer 2 interrupt routine EXF2 must be cleared by software EXF2 does not cause an interrupt in up down counter mode DCEN 1 SFR T2MOD RCLK Receive Clock Enable When set causes the serial port to use timer 2 overflow pulses for its receive clock in serial port modes 1 and 3 RCLK 0 causes timer 1 overflows to be used for the receive clock TCLK Transmit Clock Enable When set causes the serial port to use timer 2 overflow pulses for its transmit clock in serial port modes 1 and 3 TCLK 0 causes timer 1 overflow to be used for the transmit clock EXEN2 Timer 2 External Enable When set allows a capture or reload to occur as a result of a negative transition on pin T2EX P1 1 if timer 2 is not being used to cloc
143. it defines the initial logic state of the output COUTS before compare timer 2 is started the first time Further COUTSI defines the logic state which is output to COUT3 when bit ECT2O CT2CON 6 is reset COUTS disabled COUTXI COUTx inversion in burst and block commutation When COUTXI is set the output signal of compare timer 2 which is wired to the compare outputs COUTx x 0 2 in burst or block commutation mode is inverted Semiconductor Group 6 56 SIEMENS On Chip Peripheral Components C504 Bit Function CCxl COUTxI Compare output initial value compare output level in trap condition x 0 2 Bits at even bit positions 0 2 4 are assigned to the CCx compare outputs Bits at odd bit positions 1 3 5 are assigned to the COUTx compare outputs CCxl COUTxI 20 If compare timer 1 is not running after reset an output CCx COUTx x 0 2 is switched into push pull mode and starts driving an initial value of 0 when this CCX COUTx output is programmed as compare output by writing the corresponding bit combination into the CMSELO CMSEL1 registers If the compare timer runs and a bit of register TREN is set a compare channel output will be switched to 0 level in trap state CCxl COUTxI 1 If compare timer 1 is not running after reset an output CCx COUTx x 0 2 is switched into push pull mode and starts driving an initial value of 1 when this CCX COUTx output is programmed as compare output by wri
144. k the serial port EXEN2 0 causes timer 2 to ignore events at T2EX TR2 Start Stop Control for Timer 2 TR2 1 starts timer 2 C T2 Timer or Counter Select for Timer 2 C T2 0 for timer function C T2 1 for external event counter falling edge triggered CP RL2 Capture Reload Select CP RL2 1 causes captures to occur an negative transitions at pin T2EX if EXEN2 1 CP RL2 0 causes automatic reloads to occur when timer 2 overflows or negative transitions occur at pin T2EX when EXEN2 1 When either RCLK 1 or TCLK 1 this bit is ignored and the timer is forced to auto reload on timer 2 overflow Semiconductor Group 6 25 SIEMENS On Chip Peripheral Components C504 6 2 2 1 Auto Reload Up or Down Counter Timer 2 can be programmed to count up or down when configured in its 16 bit auto reload mode This feature is invoked by a bit named DCEN Down Counter Enable SFR T2MOD 0C9H When DCEN is set timer 2 can count up or down depending on the value of pin T2EX P1 1 Special Function Register T2MOD Address C9j Reset Value XXXX XXX0p Bit No MSB LSB 7 6 5 4 3 2 1 0 Coy DCEN T2MOD Bit Function Not implemented reserved for future use DCEN When set this bit allows timer 2 to be configured as an up down counter Figure 6 15 shows timer 2 automatically counting up when DCEN 0 In this mode there are tw
145. l feature which makes it possible to freeze the processor s status either for a predefined time or until an external event reverts the controller to normal operation as discussed below The watchdog timer is the only peripheral which is automatically stopped during idle mode If it was not disabled on entering idle mode the watchdog timer would reset the controller thus abandoning the idle mode The idle mode is entered by two consecutive instructions The first instruction sets the flag bit IDLE PCON 0 and must not set bit IDLS PCON 5 the following instruction sets the start bit IDLS PCON 5 and must not set bit IDLE PCON 0 The hardware ensures that a concurrent setting of both bits IDLE and IDLS does not initiate the idle mode Bits IDLE and IDLS will automatically be cleared after being set If one of these register bits is read the value that appears is 0 This double instruction is implemented to minimize the chance of an unintentional entering of the idle mode which would leave the watchdog timer s task of system protection without effect Note PCON is not a bit addressable register so the above mentioned sequence for entering the idle mode is obtained by byte handling instructions as shown in the following example ORL PCON 00000001B Set bit IDLE bit IDLS must not be set ORL PCON 00100000B Set bit IDLS bit IDLE must not be set The instruction that sets bit IDLS is the last instruction executed before going into id
146. le mode There are two ways to terminate the idle mode The idle mode can be terminated by activating any enabled interrupt This interrupt will be serviced and normally the instruction to be executed following the RETI instruction will be the one following the instruction that sets the bit IDLS The other way to terminate the idle mode is a hardware reset Since the oscillator is still running the hardware reset must be held active only for two machine cycles for a complete reset Semiconductor Group 9 4 SIEMENS Power Saving Modes C504 9 2 Power Down Mode In the power down mode the RC osciillator and the on chip oscillator which operates with the XTAL pins is stopped Therefore all functions of the microcontroller are stopped and only the contents of the on chip RAM XRAM and the SFR s are maintained The port pins which are controlled by their port latches output the values that are held by their SFR s The port pins which serve the alternate output functions show the values they had at the end of the last cycle of the instruction which initiated the power down mode ALE and PSEN hold at logic low level see table 9 1 The power down mode can be left either by an active reset signal or by a low signal at the INTO pin Using reset to leave power down mode puts the microcontroller with its SFRs into the reset state Using the INTO pin for power down mode maintains the state of the SFRs which has been frozen when power down m
147. ly be set if compare timer 1 runs in operating mode 1 CTM 1 CT1FC is set when compare timer 1 reaches count value 00004 and changes the count direction from down to up counting If compare timer 1 interrupt is enabled the setting of CT1FC will generate a compare timer 1 interrupt Bit CT1FC must be cleared by software CCxR Capture compare match on up count flag x 0 2 Capture Mode CCxR is set at a low to high transition rising edge of the corresponding CCx capture input signal Compare Mode CCxR is set if the compare timer 1 value matches the compare register CCx value during the up count phase Semiconductor Group 6 52 SIEMENS On Chip Peripheral Components C504 Bit Function CCxF Capture compare match on down count flag x 0 2 Capture Mode CCxF is set at a high to low transition falling edge of the corresponding CCx capture input signal Compare Mode CCxF is set if the compare timer 1 value matches the compare register CCx value during the down count phase only in compare timer 1 operating mode 1 Semiconductor Group 6 53 SIEMENS On Chip Peripheral Components C504 Capture Compare Interrupt Enable Register The bits of the interrupt enable register CCIE control the specific interrupt enable disable functions of the CAPCOM part of the capture compare unit The bits ECTP and ECTC control the compare timer 1 period count change interrupt Depending on the mode in which compare t
148. m2 0 0 0 UU UU UU US Input sampled e g MOV A P1 or Output e g ANL P1 A Old Data X New Data MCT02475 Figure 6 10 Port Timing Semiconductor Group 6 13 SIEMENS On Chip Peripheral Components C504 6 1 5 Port Loading and Interfacing The output buffers of ports 2 and 3 can drive TTL inputs directly The maximum port load which still guarantees correct logic output levels can be looked up in the DC characteristics in the Data Sheet of the C504 The corresponding parameters are Vo and Vou The same applies to port 0 output buffers They do however require external pullups to drive floating inputs except when being used as the address data bus When used as inputs it must be noted that the ports 2 and 3 are not floating but have internal pullup transistors The driving devices must be capable of sinking a sufficient current if a logic low level shall be applied to the port pin the parameters 7 7 and in the DC characteristics specify these currents Port O as well as the input only port 1 however have floating inputs when used for digital input Semiconductor Group 6 14 SIEMENS On Chip Peripheral Components C504 6 1 6 Read Modify Write Feature of Ports 2 and 3 Some port reading instructions read the latch and others read the pin The instructions reading the latch rather than the pin read a value possibly change it and then rewrite it to the latch These are called read modif
149. mmon mechanism is used to generate the various interrupts Each interrupt source has its own request flag s located in a special function register e g TCON T2CON SCON ADCONO Provided the peripheral or external source meets the condition for an interrupt the dedicated request flag is set whether an interrupt is enabled or not For example each timer 0 overflow sets the corresponding request flag TFO If it is already set it retains a one 1 But the interrupt is not necessarily serviced Now each interrupt requested by the corresponding flag can individually be enabled or disabled by the enable bits in the SFRs IENO and IEN1 This determines whether the interrupt will actually be performed In addition there is a global enable bit for all interrupts which when cleared disables all interrupts independent of their individual enable bits 7 2 Interrupt Sources and Vectors Each interrupt source has an interrupt vector address associated This vector address is accessed first if the corresponding interrupt is serviced More details about the interrupt servicing are given in section 7 4 Table 7 1 lists these interrupts Table 7 1 Interrupt Vector Addresses Request Flags Interrupt Source Vector Address IEO External interrupt 0 0003H TFO Timer 0 interrupt 000By IE1 External interrupt 1 0013H TF1 Timer 1 interrupt 001BH RI TI Serial port interrupt 0023H TF2 EXF2 Timer 2 interrupt 002By IADC A D converter interrupt 0043H
150. mprised of the arithmetic logic unit ALU an A register B register and PSW register The ALU accepts 8 bit data words from one or two sources and generates an 8 bit result under the control of the instruction decoder The ALU performs the arithmetic operations add substract multiply divide increment decrement BDC decimal add adjust and compare and the logic operations AND OR Exclusive OR complement and rotate right left or swap nibble left four Also included is a Boolean processor performing the bit operations as set clear completement jump if not set jump if set and clear and move to from carry Between any addressable bit or its complement and the carry flag it can perform the bit operations of logical AND or logical OR with the result returned to the carry flag The program control section controls the sequence in which the instructions stored in program memory are executed The 16 bit program counter PC holds the address of the next instruction to be executed The conditional branch logic enables internal and external events to the processor to cause a change in the program execution sequence Accumulator ACC is the symbol for the accumulator register The mnemonics for accumulator specific instructions however refer to the accumulator simply as A Program Status Word The Program Status Word PSW contains several status bits that reflect the current state of the CPU Semiconductor Group 2 2 SIEMENS Fundamental
151. n above is used and when bit EWPD in SFR PCON1 is 0 the power down mode can only be left by a reset operation If the external wake up from power down capability should be used its function must be enabled using the following instruction sequence prior to executing the double instruction sequence shown above ORL SYSCON 00010000B set RMAP ORL PCON1 80H enable external wake up from power down by setting EWPD ANL SYSCON 11101111B reset RMAP for future SFR accesses Notes Before entering the power down mode an A D conversion in progress should be stopped Further the port latch of SFR P3 2 P3 2 INTO pin should contain a 1 pin operates as input Otherwise the wake up sequence discussed in the next chapter will be started immediately when power down mode is entered Semiconductor Group 9 5 SIEMENS Power Saving Modes C504 9 2 2 Exit from Power Down If power down mode is exit via a hardware reset the microcontroller with its SFRs is put into the hardware reset state and the content of RAM and XRAM are not changed The reset signal that terminates the power down mode also restarts the RC oscillator and the on chip oscillatror The reset operation should not be activated before Voc is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize similar to power on reset Figure 9 1 shows the procedure which must is executed when power down mode is left v
152. nabled and outputs the PWM signal of the COMP unit STE2 COMP unit shadow latch transfer enable When STE2 is set the content of the compare timer 2 period and compare latches CP2H CP2L CMP2H CMP2L is transferred to its real registers when compare timer 2 reaches the next time the period value After the shadow transfer event STE2 is reset by hardware Semiconductor Group 6 61 SIEMENS On Chip Peripheral Components C504 Bit Function CT2RES Compare timer 2 reset control CT2R Compare timer 2 run stop control These two bits controls the start stop and reset function of the compare timer 2 CT2RES is used to reset the compare timer and CT2R is used to start and stop the compare timer 1 The following table shows the functions of these two bits CT2RES CT2R Function 0 0 Compare timer 2 is stopped compare output COUT3 stay in the logic state as it is 0 1 Compare timer 2 is running If CT2R is set the first time after reset COUTS is set to the logic state as defined by bit COUTSI of SFR COINI 1 0 Compare timer 2 is stopped and reset The output COUTS is set to the logic state as defined by bit COUTSI of SFR COINI default after reset 1 1 Compare timer 2 is further running Note ECT2O must be set for COUTS signal output enable CLK2 Compare timer 2 input clock selection CLK1 The input clock for the compare timer 2 is derived from the clock rate fosc of CLKO the C504 via a pr
153. nctional blocks of the C504 Table 3 2 illustrates the contents of the SFRs in numeric order of their addresses Semiconductor Group 3 3 SIEMENS Memory Organization C504 Table 3 1 Special Function Registers Functional Blocks Block Symbol Name Address Contents after Reset CPU ACC Accumulator E0y 00H B B Register FOH 00H DPH Data Pointer High Byte 83H 00H DPL Data Pointer Low Byte 82H 00H PSW Program Status Word Register DOW 00H SP Stack Pointer 81H 07H SYSCON System Control Register Bly XX10XXX0p Interrupt IENO Interrupt Enable Register 0 A8y 0X000000p System IEN1 Interrupt Enable Register 1 A9H XX000000p CCIE Capture Compare Interrupt Enable Reg D6H 00H IPO Interrupt Priority Register 0 B8y XX000000p IP1 Interrupt Priority Register 1 BOY XX000000p ITCON Interrupt Trigger Condition Register 9AH 00101010 Ports PO Port 0 80y FFH P1 Port 1 90H FFH P1ANA Port 1 Analog Input Selection Register 90429 XXXX1111p2 P2 Port 2 A0H FFH P3 Port 3 Boy FFH P3ANA Port 3 Analog Input Selection Register BOQ 9 XX1111XXp A D ADCONO A D Converter Control Register 0 D8y XX000000p Converter ADCON1 A D Converter Control Register 1 DCH 01XXX000p ADDATH A D Converter Data Register High Byte D9H 00H ADDATL A D Converter Data Register Low Byte DAH 00XXXXXXp P1ANA Port 1 Analog Input Selection Register 90H XXXX1111g P3ANA Port 3 Analog In
154. nhanced fail safe mechanisms which allow an automatic recovery from software upset or hardware failure a programmable watchdog timer WDT with variable time out period from 512 us up to approx 1 1 s at 12 MHz an oscillator watchdog OWD which monitors the on chip oscillator and forces the microcontroller into reset state in case the on chip oscillator fails it also provides the clock for a fast internal reset after power on 8 1 Programmable Watchdog Timer To protect the system against software upset the user s program has to clear the watchdog within a previously programmed time period If the software fails to do this periodical refresh of the Watchdog Timer an internal hardware reset will be initiated The software can be designed such that the watchdog times out if the program does not work properly It also times out if a software error is based on hardware related problems The Watchdog Timer in the C504 is a 15 bit timer which is incremented by a count rate of either Sovere 2 Or fovcre 32 fevoig fosc 12 That is the machine clock is divided by a series of arrangement of two prescalers a divide by two and a divide by 16 prescaler The divide by 16 prescaler is enabled by setting bit WDTPSEL bit 7 of SFR WDTREL From the 15 bit Watchdog Timer count value only the upper 7 bits can be programmed Figure 8 1 shows the block diagram of the programmable Watchdog Timer SE WDT Reset Request 4 WDTH
155. nit 8 6 8 2 2 Fast Internal Reset after Power On 0 000000 cece eee 8 7 9 Power Saving Modes 000 e cece eee eee eee eee 9 1 9 1 Idle Mode apre tha eeu des pk O Sse Pen OSE ane and kee 9 3 9 2 Power Down Mode 0 ccc eect eee eees 9 5 9 2 1 Invoking Power Down Mode 000 0c cece e teen eens 9 5 9 2 2 Exit from POWerDOWN 2338 Ged bas Geek ide va eee eee oe id EC rca 9 6 10 Device Specifications 2 00 cece eee eee 10 1 10 1 Absolute Maximum Ratings occccccccccooooo 10 1 10 2 DC Characteristics ns eres dd tak ae ean aes 10 2 10 3 A D Converter Characteristics llle 10 4 10 4 A AC Characteristics for C504 L C504 2R 0 eee 10 6 10 5 AC Characteristics for C504 L24 C504 2R24 004 10 8 10 6 AC Characteristics for C504 L40 C504 2R40 10 10 10 7 ROM Verification Characteristics for CB04 2R ooooooooooooo 10 14 10 8 Package I formation snags ware Sau ire d eR ood sod EORR RN AA 10 17 11 Index A re ei Ee eae a a he awe ee i e 11 1 Semiconductor Group l 3 05 96 Introduction SIEMENS 204 1 Introduction The C504 is a modified and extended version of the C503 Microcontroller Its enhanced functionality especially the capture compare unit CCU allows to use the MCU in motor control applications Further the C504 is compatible with the SAB 80C52 C501 microcontrollers and can replace it in existin
156. nnel 0 CCHO CCLO independently on the selected INTO 2 signal transition type rising or falling edge as defined in the SFR ITCON SFR ITCON can be used to generate additional interrupts at an INTO 2 signal transition Semiconductor Group 6 71 SIEMENS On Chip Peripheral Components Figure 6 31 gives an example of a block commutation mode timing with bit BCMP of BCON cleared only COUTx outputs are modulated with compare timer 2 output signal It shows the rotate left case BCM1 BCMO 1 0 and rotate right case BCM1 BCMO 0 1 For the timing shown in figure 6 31 the COINI register is set to XX111111p This means that a high level is defined as inactive phase The CMSELx 3 bits in the CMSELO CMSEL1 registers must also be set compare timer 2 switched to COUTx during active phase The timing shown below is directly derived from table 6 9 INTO 1 INTO 1 1 1 1 1 0 0 0 0 0 b Block commutation mode timing in rotate right mode BCM1 0 0 0 a Block commutation mode timing in rotate left mode BCM1 0 1 0 1 Input Signals Output Signals Input Signals Output Signals MCT02611 Figure 6 31 Block Commutation Mode Timing Semiconductor Group 6 72 SIEMENS On Chip Peripheral Components C504 6 3 4 4 Compare Timer 1 Controlled Multi Channel PWM Modes Using the multi channel PWM modes of the C504 several compare timer 1
157. nputs port 2 pins being externally pulled low will source current in the DC characteristics because of the internal pullup resistors Port 2 emits the high order address byte during fetches from external program memory and during accesses to external data memory that use 16 bit addresses MOVX DPTR In this application it uses strong internal pullup resistors when issuing 1s During accesses to external data memory that use 8 bit addresses MOVX Ri port 2 issues the contents of the P2 special function register PSEN 26 O The Program Store Enable output is a control signal that enables the external program memory to the bus during external fetch operations It is activated every six oscillator periodes except during external data memory accesses Remains high during internal program execution ALE 27 O The Address Latch Enable output is used for latching the low byte of the address into external memory during normal operation It is activated every six oscillator periodes except during an external data memory access When instructions are executed from internal ROM EA 1 the ALE generation can be disabled by bit EALE in SFR SYSCON 2 Input O Output Semiconductor Group 1 7 SIEMEN Introduction 2 C504 Table 1 1 Pin Definitions and Functions cont d Symbol Pin Number l O Function P MQFP 44 COUT3 28 O 10 Bit compare channel output This pin is used for the output signal of th
158. nstructions are MOVX A QDPTR Read MOVX DPTR A Write Using these instructions with the XRAM disabled implies that port O is used as address low data bus port 2 for high address output and two lines of port 3 P3 6 WR INT2 P3 7 RD for control to access up to 64 KB of external memory If the XRAM is enabled and if the effective address stored in DPTR is in the range of 0000p to FEFFy these instruction will access external memory If XRAM is enabled and if the address is within FFO0y to FFFFy the physically internal XRAM of the C504 will be accessed External memory which is located in this address range cannot be accessed in this case because no external bus cycles will generated Therefore port 0 2 and 3 can be used as general purpose l O if only the XRAM memory space is addressed by the user program Semiconductor Group 4 6 SIEMENS External Bus Interface C504 4 6 3 Accesses to XRAM using the Registers RO R1 8 bit Addressing Mode The C504 architecture provides also instructions for accesses to external data memory and XRAM which use an 8 bit address indirect addressing with registers RO or R1 These instructions are MOVX A QhRi Read MOVX RIA Write Using these instructions with the XRAM disabled implies that port O is used as address data bus port 2 for high address output and two lines of port 3 P3 6 WR INT2 P3 7 RD for control Normally these instructions are used to access 256 byte pages of e
159. o options selectable by bit EXEN2 in SFR T2CON Semiconductor Group 6 26 SIEMENS On Chip Peripheral Components C504 TL2 l Overflow gt 21 RC2H RC2L TF2 Transition 21 Timer 2 Detection Control Interrupt P1 1 e MCS02584 EXEN2 Figure 6 15 Timer 2 Auto Reload Mode DCEN 0 If EXEN2 0 timer 2 counts up to FFFFy and then sets the TF2 bit upon overflow The overflow also causes the timer registers to be reloaded with the 16 bit value in RC2H and RC2L The values in RC2H and RC2L are preset by software If EXEN2 1 a 16 bit reload can be triggered either by an overflow or by a 1 to 0 transition at the external input T2EX P1 1 This transition also sets the EXF2 bit Both the TF2 and EXF2 bits can generate an timer 2 interrupt if enabled Setting the DCEN bit enables timer 2 to count up or down as shown in figure 6 16 In this mode the T2EX pin controls the direction of count Semiconductor Group 6 27 SIEMENS On Chip Peripheral Components C504 down counting reload value Toggle TF2 Timer 2 Interrupt 1 UP 0 DOWN RC2H RC2L up counting reload value MCS02585 Figure 6 16 Timer 2 Auto Reload Mode DCEN 1 A logic 1 at T2EX makes timer 2 count up The timer will overflow at FFFFy and set the TF2 bit This overflow also causes the 16 bit value in RC2H and RC2L to be reloaded into the time
160. o qualify ALE with a schmitt trigger or use an address latch with a schmitt trigger strobe input Capacitive loading on ports 0 and 2 may cause the Vo on ALE and PSEN to momentarily fall below the 0 9 Voc specification when the address lines are stabilizing Ipp power down mode is measured under following conditions EA Port0 Vec RESET Vss XTAL2 N C XTAL1 Vss Vacno Vss all other pins are disconnected Icc active mode is measured with XTAL1 driven with cLcH cucL 5ns Vi Vss 0 5 V Vin Voc 0 5 V XTAL2 N C EA Port0 Porti RESET Vgc all other pins are disconnected would be slightly higher if a crystal oscillator is used appr 1 mA Icc idle mode is measured with all output pins disconnected and with all peripherals disabled XTAL1 driven with CLCH cHeL 5 ns Vit Vss 0 5 V Vin Voc 0 5 V XTAL2 N C RESET EA Vss Port0 Voc all other pins are disconnected Icc max at other frequencies is given by active mode TBD idle mode TBD where fos is the oscillator frequency in MHz cc values are given in mA and measured at Voc 5 V Overload conditions occur if the standard operating conditions are exeeded ie the voltage on any pin exeeds the specified range i e Voy gt Voc 0 5 V or Voy lt Vss 0 5 V The supply voltage Vec and Vss must remain within the specified limits The absolute sum of input currents on all port pins may not exceed 5
161. oad T st Read LV M Internal Bus 2 MCS02101 Figure 6 36a Serial Interface Mode 0 Functional Diagram Semiconductor Group 6 86 SIEMENS On Chip Peripheral Components C504 Transmit Receive S 4 Write to SBUF E S6P2 Send Shift TXD Shift Clock bs S3P1 Write to SCON Clear RI Receive Shift S5P TXD Shift Clock MCT02102 Figure 6 36b Serial Interface Mode 0 Timing Diagram Semiconductor Group 6 87 SIEMENS On Chip Peripheral Components C504 6 4 5 Details about Mode 1 Ten bits are transmitted through TXD or received through RXD a start bit 0 8 data bits LSB first and a stop bit 1 On receive the stop bit goes into RB8 in SCON The baud rate is determined either by the timer 1 overflow rate or the timer 2 overflow rate or both one for transmit and the other for receive Figure 6 37a shows a simplified functional diagram of the serial port in mode 1 The assiociated timings for transmit receive are illustrated in figure 6 37b Transmission is initiated by an instruction that uses SBUF as a destination register The WRITE to SBUF signal also loads a 1 into the 9th bit position of the transmit shift register and flags the TX control unit that a transmission is requested Transmission starts at the next rollover in the divide by 16 counter Thus the bit times are synchronized to the divide
162. ock the generation of the LCALL to the interrupt service routine Condition 2 ensures that the instruction in progress is completed before vectoring to any service routine Condition 3 ensures that if the instruction in progress is RETI or any write access to registers IENO IEN1 or IPO IP1 then at least one more instruction will be executed before any interrupt is vectored too this delay guarantees that changes of the interrupt status can be observed by the CPU The polling cycle is repeated with each machine cycle and the values polled are the values that were present at S5P2 of the previous machine cycle Note that if any interrupt flag is active but not being responded to for one of the conditions already mentioned or if the flag is no longer active when the blocking condition is removed the denied interrupt will not be serviced In other words the fact that the interrupt flag was once active but not serviced is not remembered Every polling cycle interrogates only the pending interrupt requests The polling cycle LCALL sequence is illustrated in figure 7 2 C1 gt ja C2 gt lt C3 C4 gt lt C5 S5P2 1 EY SS ES Interrupts Long Call to Interrupt Interrupt Interrupt are polled Vector Address Routine is latched MCTO1859 Figure 7 2 Interrupt Response Timing Diagram Semiconductor Group 7 10 SIEMENS Interrupt System C504 Note that if an interrupt
163. ode is entered In the power down mode of operation V can be reduced to minimize power consumption It must be ensured however that is Vec not reduced before the power down mode is invoked and that Vec is restored to its normal operating level before the power down mode is terminated 9 2 1 Invoking Power Down Mode The power down mode is entered by two consecutive instructions The first instruction has to set the flag bit PDE PCON 1 and must not set bit PDS PCON 6 the following instruction has to set the start bit PDS PCON 6 and must not set bit PDE PCON 1 The hardware ensures that a concurrent setting of both bits PDE and PDS does not initiate the power down mode Bits PDE and PDS will automatically be cleared after having been set and the value shown by reading one of these bits is always 0 This double instruction is implemented to minimize the chance of unintentionally entering the power down mode which could possibly freeze the chip s activity in an undesired status PCON is not a bit addressable register so the above mentioned sequence for entering the power down mode is obtained by byte handling instructions as shown in the following example ORL PCON 00000010B set bit PDE bit PDS must not be set ORL PCON 01000000B set bit PDS bit PDE must not be set enter power down The instruction that sets bit PDS is the last instruction executed before going into power down mode When the double instruction sequence show
164. of THO which is preset by software The reload leaves THO unchanged OSC 12 y C T 0 Interrupt TFO rS Reload P3 4 T0 Gate P3 2 INTO MCB021 40 Figure 6 13 Timer Counter 0 1 Mode 2 8 Bit Timer Counter with Auto Reload Semiconductor Group 6 22 SIEMENS On Chip Peripheral Components C504 6 2 1 4 Mode 3 Mode 3 has different effects on timer 0 and timer 1 Timer 1 in mode 3 simply holds its count The effect is the same as setting TR1 0 Timer 0 in mode 3 establishes TLO and THO as two separate counters The logic for mode 3 on timer 0 is shown in figure 6 14 TLO uses the timer O control bits C T Gate TRO INTO and TFO THO is locked into a timer function counting machine cycles and takes over the use of TR1 and TF1 from timer 1 Thus THO now controls the timer 1 interrupt Mode 3 is provided for applications requiring an extra 8 bit timer or counter When timer 0 is in mode 3 timer 1 can be turned on and off by switching it out of and into its own mode 3 or can still be used by the serial channel as a baud rate generator or in fact in any application not requiring an interrupt from timer 1 itself OSC 12 fosc h 2 Y Ole TLo Interrupt e ero TFO A 8 Bits P3 4 T0 ost Control 1 TR1 Gate O 21 P3 2 INTO Interrupt THO fosc 112 ero TRI Control MCS02096 Figure 6 14 Timer Counter 0 Mode 3 Two 8 Bit Timers Counters Semiconductor Gr
165. ogrammable prescaler The following table shows the programmable prescaler ratios CLK2 CLK1 CLKO Function Compare timer 1 input clock is fog 2 Compare timer 1 input clock is fogc 4 Compare timer 1 input clock is fosc 8 Compare timer 1 input clock is fosc 16 Compare timer 1 input clock is fos 32 Compare timer 1 input clock is fos 64 Compare timer 1 input clock is fosc 128 O O O AO 1 oO OC O 0 1 0 1 0 1 0 1 Compare timer 1 input clock is fosc 256 Note With a reset operation external or internal compare timer 2 is reset 0001 and stopped When software power down mode is entered with CT2RES bit of SFR CT2CON set the compare timer 2 is reset after the execution of a wake up from power down mode procedure When CT2RES is cleared before software power down mode is entered and a wake up from power down mode procedure has been executed the compare timer 2 is not reset Depending on the state of bit CT2R at power down mode entry the compare timer 2 either stops CT2R 0 or continues CT2R 1 counting after a wake up from power down mode procedure Further details of the power down mode are described in chapter 9 2 Semiconductor Group 6 62 SIEMENS On Chip Peripheral Components C504 Compare Timer 2 Period Register The compare timer 2 period registers CP2L CP2H hold the 10 bit value for the compare time
166. on registers PCON und PCON1 Both registers have the same SFR address 884 PCON1 is located in the mapped SFR area and is accessed with RMAP 1 Bit RMAP is located in SFR SYSCON B1p bit 4 The bits PDE PDS and IDLE IDLS located in SFR PCON select the power down mode or the idle mode respectively If the power down mode and the idle mode are set at the same time power down takes precedence Furthermore register PCON contains two general purpose flags For example the flag bits GFO and GF1 can be used to give an indication if an interrupt occurred during normal operation or during an idle Then an instruction that activates idle can also set one or both flag bits When idle is terminated by an interrupt the interrupt service routine can examine the flag bits Special Function Register PCON Address 87g Reset Value 000X0000g Bit No MSB LSB 7 6 5 4 3 2 1 0 874 SMOD PDS IDLS GF1 GFO PDE IDLE PCON The function of the shaded bit is not described in this section Symbol Function PDS Power down start bit The instruction that sets the PDS flag bit is the last instruction before entering the power down mode IDLS Idle start bit The instruction that sets the IDLS flag bit is the last instruction before entering the idle mode Not implemented Reserved for future use GF1 General purpose flag GFO General purpose flag PDE Power down enable bit When set starting of t
167. ons above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for longer periods may affect device reliability During overload conditions Vin gt Vec or Vin lt Vss the Voltage on Vcc pins with respect to ground Vss must not exceed the values defined by the absolute maximum ratings Semiconductor Group 10 1 SIEMENS Device Specifications C504 10 2 DC Characteristics Voc 5 V 1096 15 Vas 0 V T 0 to 70 C T 40 to 85 C T 40 to 110 C T 2 40 to 125 C for the SAB C504 for the SAF C504 for the SAH C504 for the SAK C504 Parameter Symbol Limit Values Unit Test Condition min max Input low voltage except EA Vi 0 5 0 2Voc IV RESET CTRAP 0 1 Input low voltage EA Vi 0 5 0 2 Vo IV 0 3 Input low voltage RESET Vio 0 5 0 2 Voc V CTRAP 0 1 Input high voltage except XTAL1 V 0 2 Vee Vece 0 5 V RESET and CTRAP 0 9 Input high voltage to XTAL1 Vua 0 7 Voc Voo 0 5 V Input high voltage to RESET and Vio 0 6 Voc Vec 05 V Output low voltage ports 1 2 3 Vo 0 45 V Io 1 6 mA COUT3 Output low voltage port 0 ALE Vo 0 45 V Ig 3 2 mA PSEN Output high voltage ports 1 2 3 Voy 2 4 V Ton 80 uA 0 9 Voc Io 10 uA Output high voltage ports 1 3 pins
168. or frequency lao 4 6 MHz ALE roto RR bit vos MCT02613 ROM Verification Mode 2 Semiconductor Group 10 15 SIEMENS Device Specifications C504 Vec 0 9V 0 2Vec 0 9 Test Points 0 2 Vcc 0 1 0 45V MCT00039 AC Inputs during testing are driven at Voc 0 5 V for a logic 1 and 0 45 V for a logic 0 Timing measurements are made at Viymin for a logic 1 and Vi ma for a logic 0 AC Testing Input Output Waveforms Voy 0 1V Timing Reference oad Points V oaa 0 1 V VoL 0 1V MCT00038 For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded Vo Vo level occurs Iolo 2 20 mA AC Testing Float Waveforms Crystal Oscillator Mode Driving from External Source External Oscillator Signal XTALI XTAL Js 3 9 40 MHz T XTAL2 NS XTAL2 C 20 pF 10 pF incl stray capacitance MCS02579 Recommended Oscillator Circuits for Crystal Oscillator Semiconductor Group 10 16 SIEMENS Device Specifications C504 10 8 Package Information P MQFP 44 SMD Plastic
169. ory If the EA pin is held low the C504 fetches all instructions from the external program memory 3 2 Data Memory Data Space The data memory address space consists of an internal and an external memory space The internal data memory is divided into three physically separate and distinct blocks the lower 128 bytes of RAM the upper 128 bytes of RAM and the 128 byte special function register SFR area While the upper 128 bytes of data memory and the SFR area share the same address locations they are accessed through different addressing modes The lower 128 bytes of data memory can be accessed through direct or register indirect addressing the upper 128 bytes of RAM can be accessed through register indirect addressing the special function registers are accessible through direct addressing Four 8 register banks each bank consisting of eight 8 bit multi purpose registers occupy locations 0 through 1Fy in the lower RAM area The next 16 bytes locations 204 through 2Fy contain 128 directly addressable bit locations The stack can be located anywhere in the internal data memory address space and the stack depth can be expanded up to 256 bytes The external data memory can be expanded up to 64 Kbytes and can be accessed by instructions that use a 16 bit or an 8 bit address 3 3 General Purpose Registers The lower 32 locations of the internal RAM are assigned to four banks with eight general purpose registers GPRs each Only one of the
170. oup 6 23 SIEMENS On Chip Peripheral Components C504 6 2 2 Timer Counter 2 Timer 2 is a 16 bit timer counter which can operate as timer or counter It has three operating modes 16 bit auto reload mode up or down counting 16 bit capture mode Baudrate generator see 6 4 2 2 Serial Interface The modes are selected by bits in the SFR T2CON C8 as shown in table 6 4 Table 6 4 Timer Counter 2 Operating Modes RCLK TCLK CP RL2 TR2 Mode 0 0 16 bit auto reload 16 bit capture Baud rate generator OFF O A 0 1 1 X X X Timer 2 consists of two 8 bit registers TH2 and TL2 In the timer function the TL2 register is incremented every machine cycle Since a machine cycle consists of 12 oscillator periods the count rate is 1 12 of the oscillator frequency In the counter function the register is incremented in response to a 1 to 0 transition at its corresponding external input pin T2 P1 0 In this function the external input is sampled during S5P2 of every machine cycle When the samples show a high in one cycle and a low in the next cycle the count is incremented The new value appears in the register during S3P1 of the cycle following the one in which the transition was detected Since it takes two machine cycles to recognize a 1 to 0 transition the maximum count rate is 1 24 of the oscillator frequency To ensure that a given level is sampled at least once before
171. ow latches are loaded The content of these shadow latches is transferred to the real registers when STE1 is set and the compare timer 1 reaches its period value operating mode 0 or count value 0000y operating mode 1 When the compare timer 1 offset registers are read always shadow latches are accessed Special Function Register CT1OFL Address E6y Reset Value 00H Special Function Register CT1OFH Address E7jy Reset Value 00H Bit No MSB LSB 7 6 5 4 3 2 1 0 E6y 7 6 5 4 3 2 1 LSB CT1OFL E7H MSB 6 5 4 3 ie 1 0 CT1OFH Bit Function CT1OFL 7 0 8 bit compare timer 1 offset value low byte The 8 bit value in the CT1OFL register is the low part of the offset value for compare timer 1 CT10FH 7 0 8 bit compare timer 1 offset value high byte The 8 bit value in the CT1OFH register is the high part of the offset value for compare timer 1 Semiconductor Group 6 48 SIEMENS On Chip Peripheral Components C504 Capture Compare Channel Mode Select Register The capture compare channel of the CAPCOM unit can operate individually either in compare mode or in capture mode The CMSELO and CMSEL1 registers contain the mode select bits for the CAPCOM unit Special Function Register CMSELO Address E3y Reset Value 00y Special Function Register CMSEL1 Address E44 Reset Value 00y Bit No MSB LSB 7 6 5 4 3
172. pare output signal is generated CCx and COUTx are normal l O pins or analog input pins Compare output on pin CCx enabled COUTx is normal I O pin or analog input pin Compare output on pin COUTx enabled CCx is normal I O pin or analog input pin Compare outputs on pins CCx and COUTx enabled or analog input pin Capture mode enabled signal transitions at CCx do not generate a capture event COUTx is a normal I O pin Capture mode enabled CCx is configured as a capture input and a rising edge at CCx transfers compare timer 1 content into the capture register COUTx is a normal I O pin or analog input pin Capture mode enabled CCx is configured as a capture input and a falling edge at CCx transfers compare timer 1 content into the capture register COUTx is a normal I O pin or analog input pin Capture mode enabled CCx is configured as a capture input A rising and a falling edge at CCx transfer the compare timer 1 content into the capture register COUTx is a normal I O pin or analog input pin Note only CCO COUTO can be analog inputs if not selected as compare output In compare mode the two output signals of a CAPCOM channel can be enabled selectively In capture mode the type of signal transition which will generate a capture event can be chosen Semiconductor Group 6 50 SIEMENS On Chip Peripheral Components C504 Capture Compare Registers of CAPCOM Unit The capture
173. pare value high byte x 0 2 The 8 bit value in the CCHx register is the low part of the 16 bit capture compare value of channel x Semiconductor Group 6 51 SIEMENS On Chip Peripheral Components C504 Capture Compare Interrupt Request Flags Register The interrupt flags of the CAPCOM capture compare match and compare timer 1 interrupt are located in the register CCIR AII CAPCOM capture compare match interrupt flags are set by hardware and must be cleared by software A capture compare match interrupt is generated with the setting of a CCxR bit x 0 2 if the corresponding enable bits are set The compare timer 1 interrupt is triggered by the CT1FP or CT1FC bits of SFR CCIR Special Function Register CCIR Address E5p Reset Value 00y Bit No MSB LSB 7 6 5 4 3 2 1 0 E5y CT1FP CT1FC CC2F CC2R CC1F CC1R CCOF CCOR CCIR CAPCOM CAPCOM CAPCOM Channel 2 Channel 1 Channel 0 Bit Function CT1FP Compare timer 1 period flag Compare timer 1 operating mode 0 CT1FP is set if compare timer 1 reaches the period value Compare timer 1 operating mode 1 CT1FP is set if compare timer 1 reaches the period value and changes the count direction from up to down counting Bit CT1FP must be cleared by software If compare timer 1 interrupt is enabled the setting of CT1FP will generate a compare timer 1 interrupt CT1FC Compare timer 1 count direction change flag This flag can on
174. pt cannot be interrupted by any other interrupt source If two requests of different priority level are received simultaneously the request of higher priority is serviced If requests of the same priority are received simultaneously an internal polling sequence determines which request is serviced Thus within each priority level there is a second priority structure determined by the polling sequence vertical and horizontal as shown in table 7 2 below If e g the external interrupt 0 and the A D converter interrupt have the same priority and if they are active simultaneously the external interrupt O will be serviced first Table 7 2 Interrupt Source Structure Interrupt Source Priority High Priority Low Priority External Interrupt O A D Converter High Timer 0 Interrupt External Interrupt 2 External Interrupt 1 CCU Emergency Interrupt Timer 1 Interrupt Compare Timer 2 Interrupt Serial Channel Capture Compare Match Interrupt Timer 2 Interrupt Compare Timer 1 Interrupt Low Semiconductor Group SIEMENS Interrupt System C504 7 3 3 Interrupt Request Flags The interrupt request flags are located in different SFRs Table 7 3 shows the bit locations of the interrupt request flags More detailed information about the interrupt request flags is given in the sections of chapter 6 which describe the corresponding peripheral unit in detail Table 7 3 Locations of the Interrupt
175. put Selection Register BOH XX1111XXp Serial PCON Power Control Register 87H 000X0000p Channels SBUF Serial Channel Buffer Register 99H XXH SCON Serial Channel Control Register 98g 00H Timer 0 TCON Timer 0 1 Control Register 88y 00H Timer 1 THO Timer 0 High Byte 8CH 00y TH1 Timer 1 High Byte 8DH 00H TLO Timer 0 Low Byte 8AH 00H TL1 Timer 1 Low Byte 8By 00H TMOD _ Timer Mode Register 89H 00H 1 Bit addressable special function registers 2 This special function register is listed repeatedly since some bits of it also belong to other functional blocks 3 X means that the value is undefined and the location is reserved 4 SFR is located in the mapped SFR area For accessing this SFR bit RMAP in SFR SYSCON must be set Semiconductor Group SIEMENS Memory Organization C504 Table 3 1 Special Function Registers Functional Blocks cont d Block Symbol Name Address Contents after Reset Timer 2 T2CON Timer 2 Control Register C8y 00H T2MOD Timer 2 Mode Register C9H XXXXXXXOp RC2H Timer 2 Reload Capture Register High Byte CBy 00H RC2L Timer 2 Reload Capture Register Low Byte CAH 00H TH2 Timer 2 High Byte CDH 00H TL2 Timer 2 Low Byte CCH 00H Capture CT1CON Compare timer 1 control register Ely 00010000 Compare CCPL Compare timer 1 period register low byte DEH 00H Unit CCPH Compare timer 1 period register high byte DFH 00H CT1OFL Compare timer 1 offset register
176. r CT2CON Pulse Generation fosc 2 Programmable Prescaler Period Registers CP2H CP2L COUT3 COINI 7 ECT20 CT2 Value A eee of ae CP2H CP2L CMP2H CMP2L Stat of CT2 y COUT3 COUT3I 0 COUT3 COUT3I 1 MCT02607 Figure 6 27 COMP Unit Block Diagram and Pulse Generation Scheme The COMP unit has an 10 bit up counter compare timer 2 CT2 which starts counting from 000 up to the value stored in the period register and then is again reset This compare timer 2 operation is equal to the operating mode 0 of compare timer 1 When the count value of CT2 matches the Semiconductor Group 6 59 SIEMENS On Chip Peripheral Components C504 value stored in the compare registers CMP2H CMP2L COUTS toggles its logic state When compare timer 2 is reset to 000y COUTS toggles again its logic state COUTS is only an output pin After a reset operation COUTS drives a high level as defined by the reset value 21 of bit COUT3 of SFR COINI When compare timer 2 is running bit CT2R in SFR CT2CON is set bit ECT2O in SFR CT2CON allows to disconnect COUTS from compare timer 2 signal generation In this case the logic value of COUTSI bit COINI 7 is put to the COUTS output When ECT20 is set thereafter the compare timer 2 output signal is again switched to the COUT3 output In the combined multi channel PWM modes and in the burst
177. r registers TH2 and TL2 respectively A logic 0 at T2EX makes timer 2 count down Now the timer underflows when TH2 and TL2 equal the values stored in RC2H and RC2L The underflow sets the TF2 bit and causes FFFFy to be reloaded into the timer registers The EXF2 bit toggles whenever timer 2 overflows or underflows This bit can be used as a 17th bit of resolution if desired In this operating mode EXF2 does not flag an interrupt Note P1 1 T2EX is sampled during S5P2 of every machine cycle The next increment decrement of timer 2 will be done during S3P1 in the next cycle Semiconductor Group 6 28 SIEMENS On Chip Peripheral Components C504 6 2 2 2 Capture In the capture mode there are two options selected by bit EXEN2 in SFR T2CON If EXEN2 0 timer 2 is a 16 bit timer or counter which upon overflow sets bit TF2 in SFR T2CON This bit can be used to generate an interrupt If EXEN2 1 timer 2 still does the above but with added feature that a 1 to 0 transition at external input T2EX causes the current value in TH2 and TL2 to be captured into RC2H and RC2L respectively In addition the transition at T2EX causes bit EXF2 in SFR T2CON to be set The EXF2 bit like TF2 can generate an interrupt The capture mode is illustrated in figure 6 17 6712 0 Control P1 0 T2 C T2 TH2 TL2 aria yo RC2H RC2L TF2 s Timer 2 Transition gt 1 Interrupt Detection Control P1 1 gt EXF2 T2bX EXEN2 MCT02437
178. r that the watchdog timer is halted during the idle mode and power down mode of the processor see section Power Saving Modes Therefore it is possible to use the idle mode in combination with the watchdog timer function But even the watchdog timer cannot reset the device when one of the power saving modes has been entered accidentally Semiconductor Group 8 3 SIEMENS Fail Safe Mechanisms C504 8 1 1 Refreshing the Watchdog Timer At the same time the Watchdog Timer is started the 7 bit register WDTH is preset by the contents of WDTREL 0 to WDTREL 6 Once started the Watchdog Timer cannot be stopped by software but can be refreshed to the reload value only by first setting bit WDT WDCON and by the next instruction setting SWDT WDCON Bit WDT will automatically be cleared during the third machine cycle after having been set This double instruction refresh of the Watchdog Timer is implemented to minimize the chance of an unintentional reset of the watchdog unit When the Watchdog Timer is started or refreshed its non accessible lower 8 bits stored in WDTL see figure 8 1 are reset to 00y The reload register WDTREL can be written at any time as already mentioned Therefore a periodical refresh of WDTREL can be added to the above mentioned starting procedure of the Watchdog Timer Thus a wrong reload value caused by a possible distortion during the write operation to WDTREL can be corrected by software 8 1 2 Watchdog Reset and
179. r 1 in operating mode 1 two symmetrical output signals with constant edge delay at each signal transition can be generated per channel Figure 6 23 shows the operating mode 1 timing in detail Count Value CT1 CT10FF A CCP 27 Period Reg CTIOF 2 Offset Reg 0 0 i Start of cn Time CCx CC 5 COINI Bit 0 A Ep ee E A A 29 COUTx CC 5 COINI Bit 0 25 COUTx CC 5 COINI Bit 1 97 CC content of the CCxH CCxL compare registers CCP content of the CCPH CCPL period register CT10F content of the CT10FH CT1OFL offset registers MCTO2603 Figure 6 23 Compare Timer 1 with Offset 0 Dead Time Mode 1 In the example above compare timer 1 counts from 00004 up to 00074 value stored in period register CCPH CCPL and then counts down again to 00004 The maximum and minimum 0000H values of the compare timer 1 occur always once in the count value sequence In the example shown in figure 6 23 the offset registers have a value of 00024 With the programming of the CMSEL1 or CMSELO registers all affected compare outputs are switched to push pull mode and start driving an initial level which is defined by the bits in SFR COINI Equal to operating mode 0 two compare output signals are assigned to the related CAPCOM channel CCx and COUTx The compare outputs CCx change their sta
180. r 2 period When the compare timer 2 value is equal to the value stored in the period register the COUTS signal changes from inactive to active state If CP2H CP2L is written only shadow latches are written The content of these latches is transferred to the real registers at compare timer count value 000 using bit STE2 of SFR CT2CON When the compare timer 2 period registers CP2L CP2H are read always the shadow registers are accessed Special Function Register CP2L Address D24 Reset Value 00H Special Function Register CP2H Address D3 Reset Value XXXXXX00p Bit No MSB LSB 7 6 5 4 3 2 1 0 D24 T 6 5 4 3 2 1 0 CP2L D3H 1 0 CP2H Bit Function CP2L 7 0 Compare timer 2 period low byte The CMP2L register holds the lower 8 bits of the 10 bit compare value for compare timer 2 CP2H 1 0 Compare timer 2 period high bits The CMP2H register holds most significant two bits of the 10 bit compare value for compare timer 2 Reserved bits Semiconductor Group 6 63 SIEMENS On Chip Peripheral Components C504 Compare Timer 2 Compare Registers The compare registers CMP2H CMP2L of compare timer 2 hold the 10 bit compare value which defines the duty cycle of the output signal at COUTS When the compare timer 2 value is equal to the value stored in the CMP2H CMP2L register the COUTS signal changes from low to high state If CMP2H CMP2L is written only shadow la
181. re Timer 1 Unit Semiconductor Group 6 38 SIEMENS On Chip Peripheral Components C504 Table 6 5 shows the resolution and the period value range which depends from the selected compare timer 1 input clock prescaler ratio Table 6 5 Resolution and Period of the Compare Timer 1 at fosc 40 MHz Compare Operating Mode 0 Operating Mode 1 mer Resolution Period Resolution Period Input Clock fosc 2 50 ns 100ns 3 28 ms 50 ns 200 ns 6 55 ms fosc 4 100 ns 200 ns 6 55 ms 100 ns 400 ns 13 11 ms fosc 8 200 ns 400 ns 13 11 ms 200 ns 800 ns 26 21 ms fosc 16 400 ns 800 ns 26 21 ms 400 ns 1 6 us 52 43 ms fosc 32 800 ns 1 6 us 52 43 ms 800 ns 3 2 us 104 86 ms fosc 64 1 6 us 3 2 us 104 86 ms 1 6 us 6 4 us 209 71 ms fosc 128 3 2 us 6 4 us 209 72 ms 3 2 us 12 8 us 419 42 ms fosc 256 6 4 us 12 8 us 419 43 ms 6 4 us 25 6 us 838 85 ms Compare timer 1 period and duty cycle values can be calculated using the formulas below In these formulas the following abrevations are used pv period value stored in the period registers CCPH CCPL ov Offset value stored in the offset registers CTI OFH CT1OFL cv compare value stored in the capture compare registers CCHx CCLx Operating Mode 0 Period value pv 1 cv o Duty cycle of CCx outputs XE 100 Duty cycle of COUTx outputs m 100 pv 1 Operating Mode 1 Period value 2 pv cv Duty
182. register in a range of fosc 2 up to fosc 256 For the understanding of the following timing diagrams figure 6 20 shows the internal clocking scheme of the CAPCOM unit The internal input clock of the CAPCOM unit is a symmetrical clock with 5096 duty cycle The clock transitions edges of the CAPCOM internal input clock are used for different actions at clock edge 1 the compare timer 1 is clocked to the next count value and with clock edge 2 the compare outputs CCx and COUTx are toggled set to the new logic level if required uc D D min 50 ns 40 MHz clock rate NK fosc 2 D Q 4 ox amp I LE LI LILI LI LILI D a K fosc 8 D a E K fosc 16 D increment decrement of compare timer 1 2 change modify logic level at CCx COUTx MCDO2600 Figure 6 20 CAPCOM Unit Clocking Scheme Generally the CAPCOM clocking scheme shown above is also valid for the COMP compare timer 2 unit Semiconductor Group 6 33 SIEMENS On Chip Peripheral Components C504 6 3 2 2 CAPCOM Unit Operating Mode 0 Figure 6 21 shows the CAPCOM unit timing in operating mode 0 in detail CT1 Value A CCP 7 Period Reg Offset Reg CT10F 0 Start of CTI S CC 0 E CC 2 1 87 5 x o Y EP 225 CC 4 50 Owe t on oS die CC 7 12 5 oO Own CC gt 7 0 0 A a a S O CC 0 100 2 CC 1 87 5 x
183. rify detect logic the end of the internal ROM verification Verify Detect Logic CLK CY 14 Bit Address Counter C504 2R Compare Code ROM MCB02595 Figure 4 5 ROM Verification Mode 2 External Circuitry Example Semiconductor Group 4 10 SIEMEN System Reset x C504 5 System Reset 5 1 Hardware Reset Operation The hardware reset function incorporated in the C504 allows for an easy automatic start up at a minimum of additional hardware and forces the controller to a predefined default state The hardware reset function can also be used during normal operation in order to restart the device This is particularly done when the power down mode is to be terminated Additionally to the hardware reset which is applied externally to the C504 there are two internal reset sources the watchdog timer and the oscillator watchdog The chapter at hand only deals with the external hardware reset The reset input is an active high input An internal Schmitt trigger is used at the input for noise rejection Since the reset is synchronized internally the RESET pin must be held high for at least one machine cycle 12 oscillator periods while the oscillator is running With the oscillator running the internal reset is executed during the second machine cycle and is repeated every cycle until RESET goes low again During reset pins ALE and PSEN are configured as inputs and should not be st
184. rrupt Routine MCTO2620 Figure 6 42 A D Conversion Timing in Relation to Processor Cycles Depending on the selected prescaler ratio see figure 6 40 four different relationships between machine cycles and A D conversion are possible The A D conversion is started when SFR ADDATL is written with dummy data This write operation may take one or two machine cycles In figure 6 42 the instruction MOV ADDATL 0 starts the A D conversion machine cycle X 1 and X The total A D conversion sample conversion and calibration phase is finished with the end of the 8th 16th 32th or 64th machine cycle after the A D conversion start In the next machine cycle the conversion result is written into the ADDAT registers and can be read in the same cycle by an instruction e g MOV A ADDATL If continuous conversion is selected bit ADM set the next conversion is started with the beginning of the machine cycle which follows the writre result cycle Semiconductor Group 6 101 On Chip Peripheral Components C504 SIEMENS The BSY bit is set at the beginning of the first A D conversion machine cycle and reset at the beginning of the write result cycle If continuous conversion is selected BSY is again set with the beginning of the machine cycle which follows the write result cycle The interrupt flag IADC is set at the end of the A D conversion If the A D converter interrupt is enabled and the A D converter interrupt is priorized to be serviced
185. rrupt has a low priority PX1 External interrupt 1 priority level If PX1 0 the external interrupt 1 has a low priority PTO Timer O overflow interrupt priority level If PTO 0 the Timer 0 interrupt has a low priority PXO External interrupt O priority level If PXO O the external interrupt O has a low priority Semiconductor Group 7 7 SIEMENS Interrupt System C504 Special Function Registers IP1 Address B9 4 Reset Value XX000000g Bit No MSB LSB 7 6 5 4 3 2 1 0 BOY PCT1 PCCM PCT2 PCEM PX2 PADC IP1 Bit Function Reserved bits for future use PCT1 Compare timer 1 interrupt priority level If PCT1 0 the compare timer interrupt has a low priority PCCM Capture compare match interrupt priority level If PCCM 0 the capture compare match interrupt has a low priority PCT2 Compare timer 2 interrupt priority level If PCT2 0 the compare timer interrupt has a low priority PCEM CCU emergency interrupt priority level If PCEM 0 the CCU trap interrupt has a low priority PX2 External interrupt 2 priority level If PX2 0 the external interrupt 2 has a low priority PADC A D converter interrupt priority level If PADC 0 the A D Converter interrupt has a low priority A low priority interrupt can itself be interrupted by a high priority interrupt but not by another low priority interrupt A high priority interru
186. s 0 00 cece eee eee eee 3 2 3 4 Special Function Registers 000 cece eee eee 3 3 4 External Bus Interface 222200 see e eee eee eee 4 1 4 1 Accessing External Memoty cose E ERR pena ae PaaS RESTE NY X 4 1 4 2 PSEN Program tore Enable 5 22 xao NUR NR E Rr Kits 4 2 4 3 Overlapping External Data and Program Memory Spaces 4 2 4 4 ALE Address Latch Enable ois d kae cem it Ca OX RE d Ra P UR o xd 4 4 4 5 Enhanced Hooks Emulation Concept o oooocccccccc eee eae 4 5 4 6 XRAM Operation 452372 es EC ati OR e e al Doa sa 4 6 4 6 1 Reset Operation of the XRAM 0 cece sees 4 6 4 6 2 Accesses to XRAM using the DPTR 16 bit Addressing Mode 4 6 4 6 3 Accesses to XRAM using the Registers RO R1 8 bit Addressing Mode 4 7 4 6 4 XRAM ACCESS Enable oue cune epiac e cue Y S CO Hee Os 4 7 4 7 ROM Protection for C504 2R 2 1 ees 4 8 4 7 1 Unprotected ROM Mode 0 0 cee 4 8 4 7 2 Protected ROM Mode 0 0 cece ete eens 4 9 5 System Res t uc se Swen Cat EPpRRA SEE MUERE RE Rare ERU Ee dese 5 1 5 1 Hardware Reset Operation illii 5 1 5 2 Fast Internal Reset after Power On 0000 eee eee ees 5 2 5 3 Hardware Reset Timing id eer Ser Rr OUR CRX E RUN Rede A aA 5 4 6 On Chip Peripheral Components Lllleee 6 1 6 1 Parallel OX z e set Gols e orm prend oa RS Ve tox ire hes ee m Ee ec gl 6 1 61 1 Port Structures ion
187. s a very strong driver transistor which is capable of sinking high currents 7o it is only activated if a 0 is programmed to the port pin A short circuit to Vo must be avoided if the transistor is turned on since the high current might destroy the FET This also means that no 0 must be programmed into the latch of a pin that is used as inpu The pullup FET p1 is of p channel type It is activated for two oscillator periods S1P1 and S1P2 if a 0 to 1 transition is programmed to the port pin i e a 1 is programmed to the port latch which contained a 0 The extra pullup can drive a similar current as the pulldown FET n1 This provides a fast transition of the logic levels at the pin The pullup FET p2 is of p channel type It is always activated when a 1 is in the port latch thus providing the logic high output level This pullup FET sources a much lower current than p1 therefore the pin may also be tied to ground e g when used as input with logic low input level Semiconductor Group 6 8 SIEMENS On Chip Peripheral Components C504 The pullup FET p3 is of p channel type It is only activated if the voltage at the port pin is higher than approximately 1 0 to 1 5 V This provides an additional pullup current if a logic high level shall be output at the pin and the voltage is not forced lower than approximately 1 0 to 1 5 V However this transistor is turned off if the pin is driven to a logic low level e g when used
188. s gu mS 2 1 CORFO 3 8 A eee A SICOBEEN agonia iaa 3 8 Gale Ate BS ts 3 8 SIEMENS Index C504 A 5s bas cards fas far he sca um 3 8 CPU GE2REN uta Ses arto StS kA 3 8 Accumulator 0055 2 2 CCHO 3 5 3 7 6 44 6 51 adi e 1 PT PET c 2 3 AAA 3 5 3 7 6 44 6 51 Basic timiliQgo terror 2 4 COH2 res 3 5 3 7 6 44 6 51 Fetch execute diagram 2 5 CCIE 3 4 3 5 3 8 6 44 6 54 Functionality cueca a 2 2 COIR x a ca 3 5 3 8 6 44 6 52 Program status word 2 3 COLO i e beac fs 3 5 3 7 6 44 6 51 Stack pointer sr 2 3 GUN 2 ca 3 5 3 7 6 44 6 51 CPU TIMING i ss xm po ttle 2 5 O R EM 3 5 3 7 6 44 6 51 CT1CON 3 5 3 8 6 44 6 45 CCPH 3 5 3 8 6 44 6 47 GTTEG sca A e 3 8 6 52 CCPL sae ts hoe 3 5 3 8 6 44 6 47 G TH EP aaa tta 3 8 6 52 COXE 22ers 22 a e EN 6 53 CT1OFH 3 5 3 8 6 32 6 44 6 48 COXFEN X 0 2 nanana aaa aaa 6 55 CT1OFL 3 5 3 8 6 32 6 44 6 48 CONMOEO A etude iit acts settee 6 57 el A 3 8 6 46 GGXR ooo nas dua 6 52 GITRES aa tut ELLLESnfIOEe weu 3 8 6 46 CGxREN x 0 2 2 22 2222 21r 6 55 CT2CON 3 5 3 7 6 60 6 61 GEKO tisakuna Sh 3 7 3 8 6 45 6 62 lA A 3 7 6 61 GUA eite 3 7 3 8 6 45 6 62 A etr 3 7 6 62 CLK2 3 7 3 8 6 45 6 62 GI2RES bee 3 7 6 62 CMP2H 3 5 3 8 6 60 6 64 GI Mis i Ree T ENa 3 8 6 45 CMP2L 3 5 3 8 6 60 6 64 GY Tr h
189. s set Since the external interrupt pins are sampled once in each machine cycle an input low should be held for at least 12 oscillator periods to ensure sampling If the external interrupt is transition activated for negative transitions the external source has to hold the request pin high for at least one machine cycle and then hold it low for at least one machine cycle to ensure that a negative transition falling edge is recognized so that the corresponding interrupt request flag will be set see figure 7 3 In edge triggered mode the external interrupt request flags will automatically be cleared by the CPU when the service routine is called Semiconductor Group 7 11 SIEMENS Interrupt System C504 a Level Activated Interrupt Low Level Threshold gt 1 Machine Cycle lt gt b Transition Activated Interrupt High Level Threshold IxETF 1 4 gt 1 Machine cycle gt 1 Machine Cycle Low Level Threshold d 4 gt Transition to be detected bu High Level Threshold INTx IXETR 1 4 Low Level Threshold MCT02577 Figure 7 3 External Interrupt Detection The edge triggered interrupt mode selection for all three dedicated external interrupts and two INT2 control bits are selected in the SFR ITCON External Interrupt Trigger Condition Register The edge trigger mode selection is defined in a way default value of ITCON after reset that their function is up
190. s used for compare output functions have a port structure which allows a true push pull output driving capability Type D This output driver characteristic is only enabled used when the corresponding port lines are used as compare outputs The analog function is selected by the bits in the SFRs P1ANA and P3ANA The push pull port structure is illustrated in figure 6 8 Delay Enable Vec 2 Osc Periodes Push Pull p3 Port Pin Input Data read pin MCS02581 Figure 6 8 Driver Circuit of Type D Port Pins Semiconductor Group 6 11 SIEMENS On Chip Peripheral Components C504 6 1 3 4 Type E Port Driver Circuitry The type E ports are a combination of type C and type D port drivers They combine push pull driving characteristic with the capability to select the port pin for analog input function The push pull driver characteristic is only enabled used when the corresponding port lines are used as compare outputs The analog function is selected by the bits in the SFRs P1ANA and P3ANA The push pull mixed digital analog port structure is illustrated in figure 6 9 Delay Enable Vec 2 Osc Periodes Push Pull A e p p2 l p3 21 e g Port e e e O Pin Q p e n1 Enable Analog Input bits of SFR P1ANA or SFR P3ANA
191. se banks may be enabled at a time Two bits in the program status word RSO PSW 3 and RS1 PSW 4 select the active register bank see description of the PSW in chapter 2 This allows fast context switching which is useful when entering subroutines or interrupt service routines The 8 general purpose registers of the selected register bank may be accessed by register addressing With register addressing the instruction op code indicates which register is to be used For indirect addressing RO and R1 are used as pointer or index register to address internal or external memory e g MOV RO Reset initializes the stack pointer to location 074 and increments it once to start from location 08y which is also the first register RO of register bank 1 Thus if one is going to use more than one register bank the SP should be initialized to a different location of the RAM which is not used for data storage Semiconductor Group 3 2 SIEMENS Memory Organization C504 3 4 Special Function Registers The registers except the program counter and the four general purpose register banks reside in the special function register area The special function register area consists of two portions the standard special function register area and the mapped special function register area Three special function registers of the C504 PCON1 P1ANA P3ANA are located in the mapped special function register area For accessing the mapped special function regi
192. se ll is very short Therefore an external reset time of typically 1 ms is sufficient in most applications Generally for reset time generation at power on an external capacitor can be applied to the RESET pin Semiconductor Group 5 2 C504 System Reset SIEMENS 160ZO VIA uojjnoex3 WDJBOJ4 jo DIS sajo 89 M 280 Aq joublsjasoy xo gouanbas le jo esnoq plq jasay PU p jesay ul SDIS 9S0 suIDWad Od diy9 u0 spog D Jesey 40 b I950 2 wo 49019 gt srl yg XDW srg dh sjlog japun UQ J9MOJ Jesey Power On of the C504 Figure 5 1 5 3 Semiconductor Group SIEMEN System Reset x C504 5 3 Hardware Reset Timing This section describes the timing of the hardware reset signal The input pin RESET is sampled once during each machine cycle This happens in state 5 phase 2 Thus the external reset signal is synchronized to the internal CPU timing When the reset is found active high level the internal reset procedure is started It needs two complete machine cycles to put the complete device to its correct reset state i e all special function registers contain their default values the port latches contain 1 s etc Note that this reset procedure is also performed if there is no clock available at the device This is done by the oscillator watchdog which provides an auxiliary clock for performing a perfect reset without clock at t
193. sed to verify unprotected ROMs a ROM address is applied externally to the C504 2R and the ROM data byte is output at port 0 ROM verification mode 2 which is used to verify ROM protected devices operates different ROM addresses are generated internally and the expected data bytes must be applied externally to the device by the manufacturer or by the customer and are compared internally with the data bytes from the ROM After 16 byte verify operations the state of the P3 5 pin shows whether the last 16 bytes have been verified correctly This mechanism provides a very high security of ROM protection Only the owner of the ROM code and the manufacturer who know the content of the ROM can read out and verify it with less effort 4 7 1 Unprotected ROM Mode If the ROM is unprotected the ROM verification mode 1 as shown in figure 4 3 is used to read out the content of the ROM see also the AC specifications in chapter 10 A o Inputs PSEN P2 6 Ks ALE EA Vy RESET V MCD02593 Figure 4 3 ROM Verification Mode 1 ROM verification mode 1 is selected if the inputs PSEN ALE EA and RESET are put to the specified logic level P2 6 and P2 7 must be held at low level Whenever the 14 bit address of the internal ROM byte to be read is applied to the port 1 and port 2 after a delay time port O outputs the content of the addressed internal program memory cell In ROM verification mode 1 the C504 2R must be provided with a system clock
194. selected in ADCON1 the change is automatically done in the corresponding bits MXO to MX2 in ADCONO and vice versa Four lines of port 1 and 3 each are dual purpose input output ports These pins can be used either for digital I O functions or as the analog inputs If less than 8 analog inputs are required the unused analog inputs at port 1 or 3 are free for digital I O functions Semiconductor Group 6 94 SIEMENS On Chip Peripheral Components C504 Internal IEN1 A91 im P1ANA 901 EAN3 EAN2 EAN1 EANO P3ANA BO y EAN7 EAN6 EAN5 EAN4 E ADCON1 DCH ADCL1 ADCL MXO ADCONO D8y ADC ADM MX2 M A A ADDATH ADDATL D94 DAy gt Continuous v vv Port 1 3 T S amp H A D Converter v v Clock Conversion Clock f fosc 2 Prescaler ADO 32 16 8 4 Input Clock fy VAREF gt VAGND gt Start of Conversion Write to Internal Shaded bit locations are not used in ADC functions ADDATL Bus MCB02616 Figure 6 39 Block Diagram A D Converter Semiconductor Group 6 95 SIEMENS On Chip Peripheral Components C504 6 5 2 A D Converter Registers This section describes the bits functions of all registers which are used by the A D converter Special Function Registers ADDATH Address D914 Special Function Registers ADDATL Address DA Reset Value 00y Reset Value OOXXXX
195. slaves so that each slave can examine the received byte and see if it is beeing addressed The addressed slave will clear its SM2 bit and prepare to receive the data bytes that will be coming The slaves that weren t being addressed leave their SM2s set and go on about their business ignoring the incoming data bytes SM2 has no effect in mode 0 and in mode 1 can be used to check the validity of the stop bit In a mode 1 reception if SM2 1 the receive interrupt will not be activated unless a valid stop bit is received 6 4 2 Serial Port Registers The serial port control and status register is the special function register SCON This register contains not only the mode selection bits but also the 9th data bit for transmit and receive TB8 and RB8 and the serial port interrupt bits TI and RI SBUF is the receive and transmit buffer of serial interface 0 Writing to SBUF loads the transmit register and initiates transmission Reading out SBUF accesses a physically separate receive register Semiconductor Group 6 79 SIEMENS On Chip Peripheral Components C504 Special Function Register SCON Address 98 4 Reset Value 00H Special Function Register SBUF Address 994 Reset Value XXy Bit No MSB LSB 9Fy 9Ey 9DH 9CH 9By 9AH 99H 98H 98H SMO SM1 SM2 REN TB8 RB8 TI RI SCON 7 6 5 4 3 2 1 0 99H Serial Interface O Buffer Register SBU
196. ster area bit RMAP in special function register SYSCON must be set All other special function registers of the C504 are located in the standard special function register area Special Function Register SYSCON Address B1 y Reset Value XX10XXX0p Bit No MSB LSB 7 6 5 4 3 2 1 0 BiH EALE RMAP XMAP SYSCON The functions of the shaded bits are not described in this section Bit Function Not implemented Reserved for future use RMAP Special function register map bit RMAP 0 The access to the non mapped standard special function register area is enabled RMAP 1 The access to the mapped special function register area is enabled As long as bit RMAP is set mapped special function registers can be accessed This bit is not cleared by hardware automatically Thus when non mapped mapped registers are to be accessed the bit RMAP must be cleared set by software respectively each There are also 128 directly addressable bits available within each SFR area standard and mapped SFR area All SFRs with addresses where address bits 0 2 are O e g 80H 88y 90y 98 F8j FFH are bitaddressable The 63 special function register SFR include pointers and registers that provide an interface between the CPU and the other on chip peripherals The SFRs of the C504 are listed in table 3 1 and table 3 2 In table 3 1 they are organized in groups which refer to the fu
197. t be used to drive the base of a transistor When a 1 is written to the bit the transistor is turned on If the CPU then reads the same port bit at the pin rather than the latch it will read the base voltage of the transitor approx 0 7 V i e a logic low level and interpret it as 0 For example when modifying a port bit by a SETB or CLR instruction another bit in this port with the above mentioned configuration might be changed if the value read from the pin were written back to the latch However reading the latch rater than the pin will return the correct value of 1 Semiconductor Group 6 15 SIEMENS On Chip Peripheral Components C504 6 2 Timers Counters The C504 contains three 16 bit timers counters which are useful in many applications for timing and counting In timer function the register is incremented every machine cycle Thus one can think of it as counting machine cycles Since a machine cycle consists of 12 oscillator periods the counter rate is 1 12 of the oscillator frequency In counter function the register is incremented in response to a 1 to 0 transition falling edge at its corresponding external input pin TO or T1 alternate functions of P3 4 and P3 5 resp In this function the external input is sampled during S5P2 of every machine cycle When the samples show a high in one cycle and a low in the next cycle the count is incremented The new count value appears in the register during S3P1 of the
198. t flag Set by hardware at the end of a A D conversion Must be cleared by software BSY Busy flag This flag indicates whether a conversion is in progress BSY 1 The flag is cleared by hardware when the conversion is finished ADM A D conversion mode When set a continous A D conversion is selected If cleared during a running A D conversion the conversion is stopped at its end MX2 MXO A D converter input channel select bits Bits MX2 0 can be written or read either in ADCONO or ADCON1 The channel selection done by writing to ADCON 1 0 overwrites the selection in ADCON 0 1 when ADCON 1 0 is written after ADCON O 1 The analog inputs are selected according the following table MX2 MX1 MXO0 Selected Analog Input 0 0 0 P1 0 ANO 0 0 P1 1 AN1 0 1 0 P1 2 AN2 0 1 1 P1 3 AN3 1 0 0 P3 2 AN4 1 0 1 P3 3 AN5 1 1 0 P3 4 ANG 1 1 1 P3 5 AN7 Semiconductor Group 6 97 SIEMENS On Chip Peripheral Components C504 Bit Function ADCL1 A D converter clock prescaler selection ADCLO ADCL1 and ADCLO select the prescaler ratio for the A D conversion clock fapc Depending on the clock rate fosc of the C504 fapc must be adjusted in a way that the resulting conversion clock fApc is less or equal 2 MHz see section 6 5 3 The prescaler ratio is selected according the following table ADCL1 ADCLO Prescaler Ratio 0 0 divide by 4 0 1 divide by 8 default after reset 1 0
199. t time the bit detector samples the value of RXD The value accepted is the value that was seen in at least 2 of the 3 samples If the value accepted during the first bit time is not 0 the receive circuits are reset and the unit goes back to looking for another 1 to O transition If the start bit proves valid it is shifted into the input shift register and reception of the rest of the frame will proceed As data bit come from the right 1s shift out to the left When the start bit arrives at the leftmost position in the shift register which in modes 2 and 3 is a 9 bit register it flags the RX control block to do one last shift load SBUF and RB8 and to set RI The signal to load SBUF and RB8 and to set RI will be generated if and only if the following conditions are met at the time the final shift pulse is generated 1 RI 2 0 and 2 Either SM2 0 or the received 9th data bit 1 If either of these conditions is not met the received frame is irretrievably lost and RI is not set If both conditions are met the received 9th data bit goes into RB8 and the first 8 data bit goes into SBUF One bit time later whether the above conditions were met or not the unit goes back to looking for a 1 to 0 transition at the RXD input Note that the value of the received stop bit is irrelevant to SBUF RB8 or RI Semiconductor Group 6 91 SIEMENS On Chip Peripheral Components C504 Internal Bus d TB8 7 SBUF 3 SBUF E 21 TXD
200. tate pulse width measurements TRO is a control bit in the special function register TCON Gate is in TMOD The 13 bit register consists of all 8 bits of THO and the lower 5 bits of TLO The upper 3 bits of TLO are indeterminate and should be ignored Setting the run flag TRO does not clear the registers Mode 0 operation is the same for timer 0 as for timer 1 Substitute TRO TFO THO TLO and INTO for the corresponding timer 1 signals in figure 6 11 There are two different gate bits one for timer 1 TMOD 7 and one for timer 0 TMOD 3 P3 4 T0 1 TRO Gate O gt 1 P3 2 INTO MCS02583 Figure 6 11 Timer Counter 0 Mode 0 13 Bit Timer Counter C T 0 e ero n que TFO Interrupt A 5 Bits 8 Bits C T 1 Control Semiconductor Group 6 20 SIEMENS On Chip Peripheral Components C504 6 2 1 2 Mode 1 Mode 1 is the same as mode 0 except that the timer register is running with all 16 bits Mode 1 is shown in figure 6 12 OSC TLO THO Bis 8Bits P3 4 TO ZEN ore Control 1 Gate m P3 2 INTO Interrupt TFO MCS02095 Figure 6 12 Timer Counter 0 Mode 1 16 Bit Timer Counter Semiconductor Group 6 21 SIEMENS On Chip Peripheral Components C504 6 2 1 3 Mode2 Mode 2 configures the timer register as an 8 bit counter TLO with automatic reload as shown in figure 6 13 Overflow from TLO not only sets TFO but also reloads TLO with the contents
201. tches are written The content of these latches is transferred to the real registers when compare timer count value 000 is reached and bit STE2 of SFR CT2CON has been set When the compare CMP2H CMP2L registers are read always the shadow registers are accessed Special Function Registers CMP2L Address D414 Reset Value 00H Special Function Registers CMP2H Address D5 Reset Value XXXXXX00p Bit No MSB LSB 7 6 5 4 3 2 1 0 D4y 7 6 5 4 3 2 1 0 CMP2L D5H 1 0 CMP2H Bit Function CMP2L 7 0 Compare value low byte for compare timer 2 The CMP2L register holds the lower 8 bits of the 10 bit compare value for compare timer 2 CMP2H 1 0 Compare value high bits for compare timer 2 The CMP2H register holds most significant two bits of the 10 bit compare value for compare timer 2 Reserved bits Semiconductor Group 6 64 SIEMENS On Chip Peripheral Components C504 6 3 4 Combined Multi Channel PWM Modes The CCU unit of the C504 is designed to support also motor control or inverter applications which have a demand for specific multi channel PWM signal generation In these combined multi channel PWM modes the CAPCOM unit compare timer 1 and the COMP unit compare timer 2 of the C504 CCU are working together In the combined multi channel PWM modes the signal generation of the CCx and COUTx PWM outputs can basically be controlled either by the interrupt inputs I
202. te if a match of compare timer 1 content and the corresponding compare register occurs The compare outputs COUTx change their state when a match of compare timer 1 content plus the value stored in the offset registers and the corresponding compare register has occurred If the value in the offset register plus the value of the period register is less or equal to the value stored in the compare register a static 1 or a static 0 will be generated at COUTx In the same way CCx will also stay at a static level is the compare register value is greater than the value stored in the period register Semiconductor Group 6 37 SIEMENS On Chip Peripheral Components 6 3 2 4 CAPCOM Unit Timing Relationships Depending on the operating mode of the compare timer 1 compare output signals can be generated with a maximum period and resolution as shown in figure 6 24 This example also demonstrates the reloading of the compare and period registers which occurs when compare timer 1 reaches the count value 0000y Operating Mode 0 Value Start of CT1 CCxReg 1 CCP 1 a Load Reg with Load Reg with Count A CCxReg 2 CCx Reg 2 Operating Mode 1 Value Start of CT1 min 100 ns 40 MHz clock rate Load Reg with Count A CCx Reg 1 CCP 4 CCxReg 1 CCP 2 CCx COUTx _ min 200 ns 40 MHz clock rate MCTO2604 Figure 6 24 Maximum Period and Resolution of the Compa
203. the value stored in the corresponding compare register the related compare output changes its logic state When the compare timer is reset to 0000y the related compare output changes its logic state again With the scheme shown in figure 6 21 output waveforms with duty cycles between 096 and 100 can be generated For a compare register value of 00004 the output will remain at high level COINI bit 0 or low level COINI bit 2 1 representing a duty cycle of 100 If the value stored in the compare register is higher than the value of the period register a low level COINI bit 2 0 or high level COINI bit 1 corresponds to a duty cycle of 0 Figure 6 22 shows the waveform generation in operating mode 0 when the offset register has a value which is not equal 0000y example CT1OFH CT1OFL 00024 Using compare timer 1 with an offset value not equal 0 is used to generate single edge aligned signals with a constant delay between one of the two signal transitions Compare timer 1 always counts from 0000y up to the value stored in CCP also if the value in the offset register is not equal 0 With reset count value 0000p of the compare timer 1 the CCx and COUTx will always change their logic state During the up counting phase CCx will change the logic state when the compare timer value is equal to the compare register value and COUTx will change the logic state when the compare timer value plus the offset value matches the value stored in the compar
204. the real registers when STE1 is set and the compare timer 1 reaches its period value operating mode 0 or count value 00004 operating mode 1 When the compare timer 1 period registers are read always shadow latches are accessed Special Function Register CCPL Address DE Reset Value 00y Special Function Register CCPH Address DF Reset Value 00y Bit No MSB LSB 7 6 5 4 3 2 1 0 DEH 7 6 5 4 3 2 1 LSB CCPL DFy MSB 6 5 4 3 2 1 0 CCPH Bit Function CCPL 7 0 Compare timer 1 period value low byte The 8 bit value in the CCPL register is the low byte of the 16 bit period value of compare timer 1 CCPH 7 0 Compare timer 1 period value high byte The 8 bit value in the CCPH register is the high byte of the 16 bit period value of compare timer 1 Semiconductor Group 6 47 SIEMENS On Chip Peripheral Components C504 Compare Timer 1 Offset Register The CT1OFH and CT1OFL registers contain the value for the compare timer 1 CT1OFH holds the high byte of the 16 bit offset value and CT1OFL holds the low byte For the detection of a compare match event which results in changing polarity of a COUTx compare output signal the content of CT1OFH CT10OFL is always added to the actual value of the compare timer 1 The value stored in the offset registers has no effect on the signal generation at the CCx compare outputs If the compare timer 1 offset registers are written always shad
205. the user has to take care which peripheral should continue to run and which has to be stopped during idle mode Also the state of all port pins either the pins controlled by their latches or controlled by their secondary functions depends on the status of the controller when entering idle mode Normally the port pins hold the logical state they had at the time idle mode was activated If some pins are programmed to serve their alternate functions they still continue to output during idle mode if the assigned function is on This applies to the serial interface in case it cannot finish reception or transmission during normal operation The control signals ALE and PSEN hold at logic high levels Table 9 1 Status of External Pins During Idle and Power Down Mode Outputs Last Instruction Executed from Last Instruction Executed from Internal Code Memory External Code Memory Idle Power Down Idle Power Down ALE High Low High Low PSEN High Low High Low PORT 0 Data Data Float Float PORT2 Data Data Address Data PORT3 Data alternate Data last output Data alternate Data last output outputs outputs Semiconductor Group 9 3 SIEMENS Power Saving Modes C504 As in normal operation mode the ports can be used as inputs during idle mode Thus a capture or reload operation can be triggered the timers can be used to count external events and external interrupts will be detected The idle mode is a usefu
206. ting the corresponding bit combination into the CMSELO CMSEL1 registers If the compare timer runs and a bit of register TREN is set a compare channel output will be switched to 1 level in trap state The COINI values are only valid for capture compare outputs which are enabled for compare mode operation Semiconductor Group 6 57 SIEMENS On Chip Peripheral Components C504 Trap Enable Register The trap enable register TREN is used to enable selectively the compare outputs of the three CAPCOM channels for switching it into high or low level in the trap state as defined by the bits of the COINI register Additionally for a general enable of the trap function bit TRPEN must be set The TRF flag indicates when an low level is detected at the CTRAP input signal Special Function Register TRCON Address CF Reset Value 00H Bit No MSB LSB 7 6 5 4 3 2 1 0 CFy TRPEN TRF TRENS TREN4 TRENS TREN2 TREN1 TRENO TRCON Lc eS d CAPCOM CAPCOM CAPCOM Channel 2 Channel 1 Channel 0 Bit Function TRPEN External CTRAP trap function enable bit This bit is a general enable bit for the trap function of the CTRAP input signal TRPEN 20 External trap input C IRAP is disabled default after reset TRPEN 1 External trap input CTRAP is enabled TRF Trap flag TRF is set by hardware if the trap function is enabled TRPEN 1 and the CTRAP level becomes active low If enabled an interrupt
207. tion of the device during emulation and to transfer informations about the program execution and data transfer between the external emulation hardware ICE system and the C500 MCU Semiconductor Group 4 5 SIEMENS External Bus Interface C504 4 6 XRAM Operation The XRAM in the C504 is a memory area that is logically located at the upper end of the external memory space but is integrated on the chip Because the XRAM is used in the same way as external data memory the same instruction types must be used for accessing the XRAM The XRAM can be enabled and disabled by the XMAP bit in the SYSCON register 4 6 1 Reset Operation of the XRAM The content of the XRAM is not affected by a reset After power up the content is undefined while it remains unchanged during and after a reset as long as the power supply is not turned off If a reset occurs during a write operation to XRAM the content of a XRAM memory location depends on the cycle in which the active reset signal is detected MOVX is a 2 cycle instruction Reset during 1st cycle The new value will not be written to XRAM The old value is not affected Reset during 2nd cycle The old value in XRAM is overwritten by the new value After reset the access to the XRAM is disabled bit XMAP of SYSCON 0 4 6 2 Accesses to XRAM using the DPTR 16 bit Addressing Mode The XRAM can be accessed by two read write instructions which use the 16 bit DPTR for indirect addressing These i
208. top bit goes into RB8 in special function register SCON The baud rate is variable See section 6 3 4 for more detailed information Mode 2 9 Bit USART Fixed Baud Rate 11 bits are transmitted through TXD or received through RXD a start bit 0 8 data bits LSB first a programmable 9th data bit and a stop bit 1 On transmit the 9th data bit TB8 in SCON can be assigned to the value of 0 or 1 Or for example the parity bit P in the PSW could be moved into TB8 On receive the 9th data bit goes into RB8 in special function register SCON while the stop bit is ignored The baud rate is programmable to either 1 32 or of the oscillator frequency See section 6 3 5 for more detailed information Mode 3 9 Bit USART Variable Baud Rate 11 bits are transmitted through TXD or received through RXD a start bit 0 8 data bits LSB first a programmable 9th data bit and a stop bit 1 In fact mode 3 is the same as mode 2 in all respects except the baud rate The baud rate in mode 3 is variable See section 6 3 5 for more detailed information In all four modes transmission is initiated by any instruction that uses SBUF as a destination register Reception is initiated in mode 0 by the condition RI 0 and REN 1 Reception is initiated in the other modes by the incomming start bit if REN 1 In all four modes transmission is initiated by any instruction that uses SBUF as a destination register Reception is initiat
209. ulation Concept The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new innovative way to control the execution of C500 MCUs and to gain extensive information on the internal operation of the controllers Emulation of on chip ROM based programs is possible too Each production chip has built in logic for the support of the Enhanced Hooks Emulation Concept Therefore no costly bond out chips are necessary for emulation This also ensure that emulation and production chips are identical The Enhanced Hooks Technology which requires embedded logic in the C500 allows the C500 together with an EH IC to function similar to a bond out chip This simplifies the design and reduces costs of an ICE system ICE systems using an EH IC and a compatible C500 are able to emulate all operating modes of the different versions of the C500 This includes emulation of ROM ROM with code rollover and ROMless modes of operation It is also able to operate in single step mode and to read the SFRs after a break ICE System Interface to Emulation Hardware SYSCON RSYSCON TCON RTCON TCON RTCON Enhanced Hooks Interface Circuit Optional o 1 0 Ports Port3 Port 1 RPort2 RPortO TEA TALE TPSEN Target System Interface MCS02647 Figure 4 2 Basic C500 MCU Enhanced Hooks Concept Configuration Port 0 port 2 and some of the control lines of the C500 based MCU are used by Enhanced Hooks Emulation Concept to control the opera
210. ward compatible to the basic external interrupt functionality of the SAB C501 The INT2 enable bit EX2 is located in IEN1 and the INT2 priority bit is located in IP2 The level edge control bit and the IE2 flag for INT2 is located in ITCON Semiconductor Group 7 12 SIEMENS Interrupt System C504 Special Function Registers ITCON Address 9Ajy Reset Value 00101010g Bit No MSB LSB 7 6 5 4 3 2 1 0 9AH IT2 IE2 12ETF I2ETR HETF HETR IOETF IOETR ITCON INT2 INT1 INTO Bit Function IT2 External Interrupt 2 Trigger Mode Selection If IT2 is cleared INT2 is operates in level triggered mode If IT2 is set INT2 operates in edge triggered mode IE2 External Interrupt 2 Flag If an external interrupt is recognized bit IE2 is set In edge triggered mode this bit is reset by hardware when the interrupt is serviced IXETF External Interrupt Edge Trigger Mode Selection IXETR x 0 2 refers to INTO INT2 IxETF IxETR Function 0 0 INTx inputs are not sensitive for either rising or falling edge 0 1 INTx operates in rising edge triggered mode 1 0 INTx operates in falling edge triggered mode default after reset 1 1 INTx operates in falling and rising edge triggered mode Semiconductor Group 7 13 SIEMENS Interrupt System C504 7 6 Interrupt Response Time If an external interrupt is recognized its corresponding request flag is set at
211. written appears on port 0 just before WR is activated and remains there until after WR is deactivated In a read cycle the incoming byte is accepted at port O before the read strobe is deactivated Program memory Signal PSEN functions as a read strobe External Program Memory Access The external program memory is accessed under two conditions whenever signal EA is active or whenever the program counter PC contains a number that is larger than 3FFF H This requires the ROM less version C504 L to have EA wired low to allow the lower 16K program bytes to be fetched from external memory When the CPU is executing out of external program memory all 8 bits of port 2 are dedicated to an output function and may not be used for general purpose l O The contents of the port 2 SFR however is not affected During external program memory fetches port 2 lines output the high byte of the PC and during accesses to external data memory they output either DPH or the port 2 SFR depending on whether the external data memory access is a MOVX QDPTR or a MOVX Ri Since the C504 L has no internal program memory accesses to program memory are always external and port 2 is at all times dedicated to output the high order address byte This means that port 0 and port 2 of the C504 L can never be used as general purpose I O This also applies to the C504 2R when it is operated with only an external program memory 4 2 PSEN Program Store Enable T
212. x COUTx COUTx 7 Interrupts can be generated MCTO2599 Figure 6 19 Basic Operating Modes of the CAPCOM Unit Semiconductor Group 6 31 SIEMENS On Chip Peripheral Components C504 Both compare timers start counting upwards from 0000y up to a count value stored in the period registers If the value stored in the period register is reached they are reset operating mode 0 or the count direction is changed from up counting to down counting operating mode 1 Using operating mode 0 edge aligned PWM signals can be generated Using operating mode 1 center aligned PWM signals can be generated Compare timer 1 can be programmed for both operating modes while compare timer 2 always works in operating mode 0 with one output signal COUTS Figure 6 19 a and c shows the function of these basic operating modes Compare timer 1 has an additional 16 bit offset register which consists of the high byte stored in CT1OFH and the low byte stored in CT1OFL If the value stored in CT1OFF is 0 the compare timer operates as shown in figure 6 19 a and c If the value stored in CT1OFF is not zero the compare timer operates as shown in figure 6 19 b and d In operating mode 0 the compare timer 1 is always reset after its value was equal to the value stored in period register In operating mode 1 the count direction of the compare timer is changed from up to down counting when its value has reached the value stored in the period register The count dir
213. xternal data memory accesses MOVX instructions and code memory accesses with an address greater than 3FFFy external code memory fetches If EA 0 the ALE generation is always enabled and the bit EALE has no effect After a hardware reset the ALE generation is enabled Special Function Register SYSCON Address B1 y Reset Value XX10XXX0p Bit No MSB LSB 7 6 5 4 3 2 1 0 BiH EALE RMAP XMAP SYSCON The function of the shaded bit is not described in this section Bit Function Not implemented Reserved for future use EALE Enable ALE output EALE 0 ALE generation is disabled disables ALE signal generation during internal code memory accesses EA 1 With EA 1 ALE is automatically generated at MOVX instructions and code memory accesses with an address greater 3FFFy EALE 1 ALE generation is enabled If EA 0 the ALE generation is always enabled and the bit EALE has no effect on the ALE generation XMAP Enable XRAM XMAP 0 XRAM disabled XMAP 1 XRAM enabled If XRAM is enabled 8 bit MOVX instructions using Ri always access the internal XRAM and do not generate external bus cycles If XRAM is enabled 16 bit MOVX instructions using DPTR access the XRAM if the address is in the range of FFO0y to FFFFy and do not generate external bus cycles in this address range Semiconductor Group 4 4 SIEMENS External Bus Interface C504 4 5 Enhanced Hooks Em
214. xternal memory If the XRAM is enabled these instruction will only access the internal XRAM External memory cannot be accessed in this case because no external bus cycle will be generated Therefore port 0 2 and 3 can be used as standard I O if only the internal XRAM is used 4 6 4 XRAM Access Enable The C504 maps 256 bytes of the external data space into the on chip XRAM Especially when using the 8 bit addressing modes this could prevent access to the external memory extension and might induce problems when porting software Therefore it is possible to enable and disable the on chip XRAM using the bit XMAP in SFR SYSCON register description see section 4 4 When the XRAM is disabled default after reset all external data memory accesses will go to the external data memory area Semiconductor Group 4 7 SIEMENS External Bus Interface C504 4 7 ROM Protection for C504 2R The C504 2R ROM version allows to protect the content of the internal ROM against read out by non authorized people The type of ROM protection protected or unprotected is fixed with the ROM mask Therefore the customer of a C504 2R ROM version has to define whether ROM protection has to be selected or not The C504 2R devices which operate from internal ROM are always checked for correct ROM content during production test Therefore unprotected and also protected ROMs must provide a procedure to verify the ROM content In ROM verification mode 1 which is u
215. y fosc The minimum conversion time is 6 us which can be achieved at fosc of 16 or 32 MHz Table 6 14 A D Conversion Time for Dedicated System Clock Rates fosc MHz Prescaler fApc MHz Sample Time Total Conversion Ratio PS ts us Time tApcc us 3 5 4 438 4 57 27 43 12 4 1 5 1 33 8 16 4 2 1 6 24 8 1 5 1 33 8 32 8 2 1 6 40 16 1 25 1 6 9 6 Semiconductor Group 6 102 SIEMENS On Chip Peripheral Components C504 Note The prescaler ratios in table 6 14 are mimimum values At system clock rates fosc up to 16 MHz the divider ratio 8 16 or 32 can also be used At system clock rates between 16 and 32 MHz the divider ratios 16 and 32 can be used Using higher divider ratios than required increases the total conversion time but can be useful in applications which have voltage sources with higher input resistances for the analog inputs increased sample phase tance us A 50 ADCC min 6 us Prescaler 4 Prescaler 8 Prescaler 16 Et tit eE I L O O O A A O O focs 3 5 10 20 30 40 MHz MCT02621 Figure 6 43 Minimum A D Conversion Time in Relation to System Clock Semiconductor Group 6 103 SIEMENS On Chip Peripheral Components C504 6 5 5 A D Converter Calibration The C504 A D converter includes hidden internal calibration mechanisms which assure a save functionality of the A D converter according to the DC
216. y sate eh e fa ap ee a dete t Tf 2 3 3 7 CMSELO 3 5 3 8 6 44 6 49 D EMSELDO roto do es ale 3 8 Ac os ds doe ede iba ert 3 2 GMSELU arnes s bp ue E Ras 3 8 DC characteristics 10 2 to 10 3 CMSELO02 le dpi ss 3 8 DOEN vr eu 3 7 6 26 6 27 6 28 OMSELOS su iii biet eaten ba 3 8 Device Characteristics 10 1 to 10 17 CMSEL1 3 5 3 8 6 44 6 49 DP ee ias tuii 3 4 3 6 GMSELTO ride ad 3 8 pic Muertes lr 3 4 3 6 EMSELT La ARES 3 8 E GMSEL12 vi ata aa 3 8 io ia ace 3 6 7 5 GCGMSELIS 24 29 Avis oo E bah Aes 3 8 EAD Ple A turi E LLL LL 3 6 6 98 7 6 GMSEL20 s pes 3 8 E ER NEP CELLA RUM 3 7 4 4 CMSEL21 een nnne 3 8 aa daran 3 6 OM ato t usi 3 8 A O IA 3 6 O A e e 9 8 X MR PPM METRE 3 6 COINI occ 3 5 9 8 6 44 6 56 EANO a ano oo Gene nes 3 6 COUTOl csse n 3 8 A aes ae kare 3 7 O o Mita OS EANES ai hi let vente nats 3 7 COUTAI 0 eee eee n ne 3 8 A A does seb as 3 7 COUTSI 66 eee eee 3 8 6 56 EAN Paita 3 7 DU TA as 3 8 6 56 FANTO meae Sind dud AA 6 105 COUTXI x 0 2 eene 6 97 E e or eti e LI MAL els 3 8 6 67 ol cC PNE 6 25 ECCM A 3 6 7 6 GB BE2 uk a 3 7 6 24 ECEM cules ane LLL LLL LLL 3 6 7 6 CP2H coco 3 5 9 8 6 60 6 63 ECT bats E E E 3 6 7 6 CP2L ccoo 3 5 9 7 6 60 6 63 EG T2 ca ina ida data 3 6 7 6 Semiconductor Group SIEMENS index C504 ECT 20 gt eres cards ra 4 eres ep 3 7 6 61 ADG ones hp bv oe ODE SEXE vs 3 8 6 97 ECTO CU 3 8 6 54 IDE
217. y write instructions which are listed in table 6 3 If the destination is a port or a port pin these instructions read the latch rather than the pin Note that all other instructions which can be used to read a port exclusively read the port pin In any case reading from latch or pin resp is performed by reading the SFR PO P2 and P3 for example MOV A P3 reads the value from port 3 pins while ANL P3 40AAH reads from the latch modifies the value and writes it back to the latch It is not obvious that the last three instructions in table 6 3 are read modify write instructions but they are The reason is that they read the port byte all 8 bits modify the addressed bit then write the complete byte back to the latch Table 6 3 Read Modify Write Instructions Instruction Function ANL Logic AND e g ANLP1 A ORL Logic OR e g ORL P2 A XRL Logic exclusive OR e g XRL P3 A JBC Jump if bit is set and clear bit e g JBC P1 1 LABEL CPL Complement bit e g CPL P3 0 INC Increment byte e g INC P4 DEC Decrement byte e g DEC P5 DJNZ Decrement and jump if not zero e g DJNZ P3 EL MOV Px y C Move carry bit to bit y of port x CLR Px y Clear bit y of port x SETB Px y Set bit y of port x The reason why read modify write instructions are directed to the latch rather than the pin is to avoid a possible misinterpretation of the voltage level at the pin For example a port bit migh

User`s Manual 06.96 8-Bit CMOS Microcontroller http://www.siemens

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