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1. 9596 non condensing Altitude 300m to 3 000m Shock 15g 11ms Bump 10g 16ms Vibration sinusoidal 2g 10 150Hz Conformal coating on request mikro elektronik gmbh n rnberg EM1 Data Sheet 2008 07 31 Technical Data Safety PCB manufactured with a flammability rating of 94V 0 by UL recognized manufacturers EMC Tested according to EN 55022 radio disturbance IEC1000 4 2 ESD and IEC1000 4 4 burst BIOS MENMON Software Support VxWorks Linux ELinOS QNX PikeOS partitionable RTOS certified platform CANopen firmware Vector Informatik CAN support MEN Driver Interface System MDIS for Windows Linux VxWorks QNX OS 9 For more information on supported operating system versions and drivers see Software man mikro elektronik gmbh n rnberg EM1 Data Sheet 2008 07 31 Diagram e Front Panel 8 Jon Board Ethernet 10 100Base T RS232 q PowerPC MPC5200 USB 1 1 CAN bus CAN bus Multifunction external bus UO Connector J2 mm ll Carrier Board PCI 104 J1 man mikro elektronik gmbh n rnberg EM1 Data Sheet 2008 07 31 Configuration amp Options Standard Configurations Article No CPU Type FPGA System RAM NAND Flash Boot Flash Additional SRAM Misc SDRAM 15EM01 00 MPC5200 12 000 LE 128 MB 128 MB 2 MB 16 MB 2 MB Front UO 384MHz 15EMO1NOO MPC5200B 18 752 LE 256 MB 1 GB 2 MB 16 MB 2 M
2. Fast Ethernet COM USB 1 1 front Dual CAN controller MENMON BIOS for PowerPC cards COMs graphics IDE etc optional via FPGA Stackable with PCI 104 disk Flash or network for hardware testing or for debugging applications without running any operating system The EMI is designed to operate under harsh environmental conditions including 40 to 85 C operation temperature shock vibration humidity It focuses on applications in transportation railways automotive and avionics For a first evaluation of the functions of the EMT it is strongly recommended to use the EK6 ESM starter kit The kit consists of the standard CPU module an FPGA loaded with additional I O functions the carrier card with I O connectors an external PSU VGA and RJ45 to D Sub cables and an adapter for mounting a PCI 104 module ESM modules are complete computers which consist of the hardware CPU chip set memory I O which is not fixed to any application specific function and an FPGA programmed in VHDL code for user defined I O ESM modules are based on PCI They have two system connectors J1 has a fixed signal assignment while J2 is variable depending on the final application specific configuration of the ESM and the carrier The EM1 comes with MENMON support This firmware BIOS board J2 also feeds the I O signals of the functions can be used for bootstrapping operating systems from programmed in the FPGA to the carrie
3. names are trademarks or registered trademarks of their respective holders Information in this document has been carefully checked and is believed to be accurate as of the date of publication however no responsibility is assumed for inaccuracies MEN Mikro Elektronik accepts no liability for consequential or incidental damages arising from the use of its products and reserves the right to make changes on the products herein without notice to improve reliability function or design MEN Mikro Elektronik does not assume any liability arising out of the application or use of the products described in this document The products of MEN Mikro Elektronik are not suited for use in nuclear reactors or for application in medical appliances used for therapeutical purposes Application of MEN s products in such plants is only possible after the user has precisely specified the operation environment and after MEN Mikro Elektronik has consequently adapted and released the product Copyright 2008 MEN Mikro Elektronik GmbH All rights reserved un an Ee mikro elektronik gmbh n rnberg
4. B Front UO 384MHz 15EMO1A00 MPC5200B 18 752 LE 256 MB 128 MB 2 MB 16 MB 2 MB Rear I O 384MHz 15EMO1A01 MPC5200B 18 752 LE 256 MB 128 MB 2 MB 16 MB 2 MB Rear I O 5V 384MHz only Options CPU MPC5200 384 MHz Memory System RAM o 128 MB or 256 MB NAND Flash o OMB up to maximum available Boot Flash o 2 MB 4 MB or 8 MB Additional SDRAM o 0 MB or 16 MB m SRAM o 0 MB or 2 MB 128KB non volatile FRAM instead of SRAM 1 0 m Front connections o D Sub connectors for Ethernet and COM USB Second Ethernet channel at front through FPGA Mechanical PCI and I O connectors can also be placed for face to face assembly ESM Type N Please note that some of these options may only be available for large volumes Please ask our sales staff for more information man mikro elektronik gmbh n rnberg FPGA EM1 Data Sheet 2008 07 31 FPGA Capabilities FPGA Altera Cyclone EP1C12 o 12 060 logic elements o 239 616 total RAM bits Connection o Available pin count 77 pins o Functions available e g via I O connector Flexible Configuration This MEN board offers the possibility to add customized LO functionality in FPGA t depends on the board type pin counts and number of logic elements which IP cores make sense and or can be implemented Please contact MEN for information on feasibility Depending on the hardware platform SA Adapters can be used to realize the physical lines MEN I
5. EM1 Data Sheet 2008 07 31 EMT Embedded System Module with MPC5200 The EMI can be supplied as a stand alone module with an application specific carrier card and or with additionally plugged PCI 104 modules The EMI is controlled by the MPC5200 PowerPC processor which was specially developed for automotive applications and which operates at up to 400 MHz and 700 MIPS The complete ESM module in standard form has an operational temperature of 40 to 85 C The CPU consumes less than 1 W at 384 MHz The EM1 is equipped with up to 256 MB soldered SDRAM and up to 1 GB NAND Flash as well as with 16 MB additional SDRAM up to 8 MB boot Flash and 2 MB battery backed SRAM The EMI provides one Fast Ethernet interface second interface prepared through FPGA one serial line and USB 1 1 at its front panel As an alternative to RJ45 D Sub connectors guarantee reliable functions also in harsh environments Two CAN controllers with V2 0A B CAN protocol are included in the MPC5200 The physical CAN interfaces are accessible via SA Adapters M Further UARTs and other additional I O functions can be realized in the on board FPGA and accessed via a carrier board The functionality of the FPGA is dynamically loaded by the application software m Embedded System Module with MPC5200 384 MHz FPGA 12 000 LEs approx 144 000 gates Up to 256 MB on board DDR SDRAM Up to 8 MB boot Flash NAND Flash 2 MB SRAM 16 MB additional SDRAM
6. P MEN for EM1 EM1A EMIN EK6 EK6N F12N and F12 13Z025 40 QNX native driver MEN for 162025 UART and 162125 UART 13Z044 40 QNX native driver MEN for 162044 DISP frame buffer Software Firmware BIOS 14EM01 00 MENMON Firmware for EM1 EM1A EM1N F12 and F12N object code Documentation 20EMOO 00 ESM Specification 20EMO1 00 EMI User Manual 20EMOT ER EMI Errata 21APPNOO9 Application Note 162025 UART and 167125 UART under Linux 21MENM 00 MENMON 2nd Edition User Manual 22Z025 ER 16Z025_UART Errata For the most up to date ordering information and direct links to other data sheets and downloads see the EM1 online data sheet under www men de men mikro elektronik gmbh n rnberg EM1 Data Sheet 2008 07 31 Contact Information Germany France USA MEN Mikro Elektronik GmbH MEN Mikro Elektronik SA MEN Micro Inc Neuwieder Strake 5 7 18 rue Ren Cassin 24 North Main Street 90411 Nuremberg ZA de la Ch telaine Ambler PA 19002 Phone 49 911 99 33 5 0 74240 Gaillard Phone 215 542 9575 Fax 49 911 99 33 5 901 Phone 33 0 450 955 312 Fax 215 542 9577 E mail info men de Fax 33 0 450 955 211 E mail sales amp menmicro com www men de E mail info men france fr www menmicro com www men france fr The date of issue stated in this data sheet refers to the Technical Data only Changes in ordering information given herein do not affect the date of issue All brand or product
7. P Cores MEN has a large number of standard IP cores to choose from Examples IDE e g PIO mode 0 UDMA mode 5 UARTs CAN bus Display control Fast Ethernet 10 100Base T EI EG 00 SS For IP cores developed by MEN please refer to our IP core overview n IP Core compare chart PDF MEN also offers development of new customized IP cores Third Party IP Cores Third party IP cores can also be used in combination with MEN IP cores Examples o www altera com D www opencores org FPGA Design Environment m Altera offers free download of Quartus Il Web Edition o Complete environment for FPGA and CPLD design o Includes schematic and text based design entry o Integrated VHDL and Verilog HDL synthesis and support for third party synthesis software nu SOPC Builder system generation software o Place and route verification and programming m Altera Quartus Il Web Edition FPGA design tool man mikro elektronik gmbh n rnberg EM1 Data Sheet 2008 07 31 Ordering Information Related Hardware O8EK06 00 ESM evaluation kit for EM1 Mini ATX carrier board EM1 with PowerPC MPC5200 384MHz 128MB DDR SDRAM 128MB NAND Flash 2MB SRAM 16MB graphics memory 2 MB boot Flash 1 Fast Ethernet 1 UART 1 USB 1 1 graphics IDE RJ45 to D Sub cable VGA cable external PSU and adapter for mounting of one PCI 104 module 0 60 C discontinued as of June 28 2007 MPC5200B 384MHz FPGA 18 752
8. logic elements 256MB SDRAM 128MB NAND Flash 2MB SRAM 16MB graphics memory 2MB boot Flash 40 85 C with qualified components MPC5200B 384MHz FPGA 18 752 logic elements 256MB SDRAM 128MB NAND Flash 2MB SRAM 16MB graphics memory 2MB boot Flash single 5V supply 40 85 C with qualified components MPC5200B 384MHz FPGA 18 752 logic elements 256 MB SDRAM 1 GB NAND Flash 2 MB SRAM 16 MB graphics memory 2 MB boot Flash front 2 Fast Ethernet RJ45 1 UART RJA5 1 USB 40 85 C with qualified components also for ESM evaluation kit EK6N 15EM01A00 15EM01A01 15EM01NO00 Miscellaneous 05F006 00 RS232 interface cable RJ45 to 9 pin D Sub 1 COM to 1 COM 2m Software OS independent 13Z015 06 MDIS4 2004 driver MEN for 162029 CAN MSCAN Layer2 13Z016 06 MDIS4 2004 driver MEN for 162029 CAN CANopen master 13Z017 06 MDIS4 2004 low level driver sources MEN for 16Z034_GPIO and 16Z037_GPIO Software Linux 13Z025 90 Linux native driver MEN for 162025 UART 162057 UART and 162125 UART 13Z044 90 Linux native driver MEN for 16Z044_DISP frame buffer Software Windows 13Z044 70 Windows native driver MEN for 16Z044_DISP frame buffer Software VxWorks 10EM01 60 VxWorks amp BSP MEN for EM1 EM1A EM1N EK6 EK6N F12N and F12 13Z025 60 VxWorks native driver MEN for 16Z025_UART 16Z057_UART and 16Z125_UART Software QNX 10EMO1 40 QNX BS
9. ng on FPGA configuration Front Connections s One USB 1 1 Series A Two Ethernet RJ45 or D Sub s One RS232 UART COM1 RJ45 or D Sub FPGA Standard factory FPGA configuration o Main bus interface n 167070 IDEDISK IDE controller for NAND Flash o 162043 SDRAM Additional SDRAM controller 16MB 1MB used for graphics n 162023 IDENHS IDE controller PIO mode 0 non hot swap n 162044 DISP Display controller 800 x 600 60Hz 70Hz 6 bit RGB o 162031 SPI SPI touch panel controller n 162025 UART UART controller controls COMT10 COM 3 n 162034 GPIO GPIO controller 6 lines The FPGA offers the possibility to add customized I O functionality See FPGA PCI Interface m 32 bit 32 MHz PCI interface at PCI 104 connector J1 Compliant with PCI Specification 2 2 Support of 4 external masters Miscellaneous Real time clock Power supervision and watchdog Electrical Specifications Supply voltage power consumption o 5V 2 5 10mA max only for USB o 3 3V 2 5 1A typ MTBF 232 000h 40 C derived from MIL HDBK 217F Mechanical Specifications Dimensions conforming to ESM specification PCB 149mm x 71mm Type I S Weight 90g w o heat sink Environmental Specifications Temperature range operation n 40 485 C o Airspeed min 2 m s Temperature range storage 40 85 C Relative humidity operation max 9596 non condensing Relative humidity storage max
10. r card man mikro elektronik gmbh n rnberg Technical Data EM1 Data Sheet 2008 07 31 CPU m PowerPC o MPC5200 o Up to 400MHz Memory 2x16KB L1 data and instruction cache integrated in MPC5200 Up to 256MB SDRAM system memory n Soldered o DDR o 64MHz memory bus frequency Up to 1GB soldered NAND Flash and more FPGA controlled 16MB additional SDRAM FPGA controlled e g for video data and NAND Flash firmware Up to 8MB boot Flash 2MB battery backed SRAM or 128KB non volatile FRAM Serial EEPROM 8kbits for factory settings Mass Storage Parallel IDE PATA o One port for hard disk drives o Available via UO connector o FPGA controlled Up to 1GB soldered ATA NAND Flash and more FPGA controlled Graphics Available via I O connector FPGA controlled 1 0 USB o One USB 1 1 port o Series A connector at front panel o OHCI implementation n Data rates up to 12Mbits s Ethernet o One 10 100Base T Ethernet channel o Second Ethernet channel can be implemented through update of FPGA o Two RJ45 or one D Sub connector at front panel m One RS232 UART COM1 o RJA5 or D Sub connector at front panel o Data rates up to 115 2kbits s o 512 byte transmit receive buffer o Handshake lines CTS RTS CAN bus o Two CAN bus channels o 2 0 A B CAN protocol o Data rates up to 1 Mbit s o Connection via on board connectors o External transceivers using SA Adapters Further UO dependi

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