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71M6515H Demo Board User`s Manual - Part Number Search

1. 26 2 APPLICATION INFORMATION s kreovania ra 27 24 Calbr tiori sauna passed 27 2 1 1 27 2 1 2 BD T ETT 27 2 1 3 Error Sources in a Meter ERR 28 2 1 4 Calibration with Three 01000110110 29 2 1 5 Calibration with Five Measurements nn nn nn rr 30 2 1 6 Calibration for Meters with Rogowski Coil 31 2 1 7 Calibration SDreadsliBels 32 21 8 Compensating for 33 2 2 Schematic iie dirlo NR Rm Um 35 2 2 1 Components for the VFLT PPI 35 2 2 2 FC e 35 22 WO PRME 35 425 Demo BOSTA tc 37 2 3 1 Testing the Demo Board Using the 37 2 3 2 FCN IVINS TOS ee Sen oa to o 30 3 HARDWARE DESCRIPTION a 41 3 1 Board Description Jumpers Sw
2. 33 Figure 2 5 Non Linearity Caused by Quantification 33 Figure 2 6 Voltage Divider Tor kon iol nn no 35 Figure 2 7 External Components for 5 2 9 35 Figure erede 36 Figure 2 9 Typical GUI VVC OW EEE 37 Figure 2 10 Meter with Calibration rn 38 Figure 2 11 Calibration System 5 39 Figure 3 1 71M6515H Demo Board Connectors Headers LEDs Switches 43 Figure 4 1 TERIDIAN 71M6515H Demo Board Electrical Schematic 1 3 48 Figure 4 2 TERIDIAN 71M6515H Demo Board Electrical Schematic 2 3 49 Figure 4 3 TERIDIAN 71M6515H Demo Board Electrical Schematic 3 3 50 Figure 4 4 TERIDIAN 71M6515H Demo Board Top 52 Figure 4 5 TERIDIAN 71M6515H Demo Board Bottom 53 Figure 4 6 TERIDIAN 71M6515H Demo Board Top Signal 54 Figure 4 7 TERIDIAN 7 1M6515H Demo Board Middle Layer 1 Ground Plane 55 Figure 4 8 TERIDIAN 71M6515H Demo Board Middle Layer 2 Supply Plane 56 Figure 4 9 TERIDIAN 71M6515H De
3. A summary of all of the GUI window areas follows on the next pages Copyright 2005 TERIDIAN Semiconductor Corporation d SEMICONDUCTOR CORP 1 8 5 GUI WINDOW CONTROL AND DISPLAY FIELDS DETAILED DESCRIPTION Energy Voltage Current and Phase Area 1 This area is in the upper left corner of the GUI window and contains a number of display fields arranged in columns Phase A is the left column phase B is the center column and phase C is the right column Next to the display fields in this area there are a list field and a rectangular button controlling basic functions of the Energy Voltage Current and Phase Area GUI Element Label Element Type Accumulated energy List field This control toggles the display of the Wh and fields Instantaneous energy from total accumulated energy to instantaneous energy i e energy per accumulation interval CLR ACCUM Rectangular Resets the accumulators for Wh VARh and to zero It also button resets the Main Edge counters in the Status Mask area and the pulse counters The function of the display fields depends on the selected mode accumulated or instantaneous energy GUI Element Label Function Accumulated Energy Function Instantaneous Energy Selected Selected Wh energy real power x time for each power x time collected during the last phase accumulation interval for each phase reactive energy reactive power x reactive p
4. an san Dela a 44 JP 18 Pin Description pins 5 7 9 and 17 are 44 S ED TT 45 71M6515H Demo Board Bill 9 51 Debug Board Bill 58 71M6515H Pin Description Table 12 63 Description Table 2 2 3 eie totu tton Edna qoe a rn 64 Copyright 2005 TERIDIAN Semiconductor Corporation 1 2 1 3 1 4 d J TERIDIAN GETTING STARTED GENERAL The TERIDIAN Semiconductor Corporation TSC 71M6515H Demo Board is a demonstration board for evaluating the 71M6515H IC for 3 phase electronic power metering applications It incorporates a 71M6515H integrated circuit peripheral circuitry such an on board power supply as well as a companion Debug Board that allows a connection to a PC running Windows 2000 XP through a RS232 port The demo board allows the evaluation of the 71M6515H power meter controller chip for measurement accuracy and overall system use A control program running on a Windows 2000 XP compatible PC allows control and monitoring of the 71M6515H IC on an abstract level via a graphical user interface GUI SAFETY AND ESD NOTES Connecting live voltages to the demo board system will result in potentially hazardous voltages on the demo board EXTREME CAUTIO
5. In this section requirements for calibration systems will be discussed and calibration procedures will be suggested Sample calibration procedures for CT shunt meters are provided requiring three or five measurements A sample calibration procedure is provided for Rogowski meters CALIBRATION SYSTEMS Performing a proper calibration requires that a calibration system is used i e equipment that applies accurate voltage load current and load angle to the unit being calibrated while measuring the response from the unit being calibrated in a repeatable way By repeatable we mean that the calibration system is synchronized to the meter being calibrated Best results are achieved when the first pulse from the meter opens the measurement window of the calibration system This mode of operation is opposed to a calibrator that opens the measurement window at random time and that therefore may or may not catch certain pulses emitted by the meter It is also very important that the calibration system just like the hookup of a real meter applies voltage constantly while varying the current For the calibration of the 71M6515H it is essential that voltage is applied at least a few seconds before the measurement is started i e before current is applied This is necessary because e Incase the internal power supply is used the 71M6515H needs a few seconds to power up e Evenif the 71M6515H has DC power V3P3 filters and other functions inside the CE
6. R61 220K R68 220K R19 220K R29 220K R42 220K R49 220K R62 220K R69 220K R20 220K R30 120K R43 220K R50 120K R63 220K R70 120K R21 220K R31 4 7K R44 220K R51 4 7K R64 220K R71 4 7K TP2 VA L5 VA R32 750 C9 0 001uF V3P3 C33 0 001uF GND TP4 VB N 18 VB R52 750 V3P3 C43 0 001uF GND TP6 QUO 11 R72 750 V3P3 C44 0 001uF GND TERIDIAN SEMICONDUCTOR CORP JP26 L3 R1 R14 1 19 TEST POINT GND C8 0 001uF C31 C32 0 001uF 0 001uF JP27 L6 R13 R34 TP3 TP20 TEST POINT C10 0 001uF C34 C35 0 001uF 0 001uUF JP28 L9 R23 R53 TP5 TE TEST POINT C36 C37 0 001uF 0 001uF C12 0 001uF CURRENT SHUNT CONNECTIONS 1206 PACKAGE Figure 4 2 TERIDIAN 71M6515H Demo Board Electrical Schematic 2 3 49 of 66 Copyright 2005 TERIDIAN Semiconductor Corporation TERIDIAN SEMICONDUCTOR CORP 71 6515 Demo Board User s Manual WPULSE R74 3 V2P5 x R75 and C38 EU SYNCHRONOUS V3P3 CLOSE TO IC SERIAL PORT E GND VARS R76 DIO CONNECTOR CONNECTOR aM eue AU mue sw2 R77 C38 V3P3 GND 0 00107 RESETZ 1 0 d RESET 10 PULSE4 RPULSE C19 JP8 TP31 CMP VREF C18 0 1u TMUXOUT l sb GND NC ED ep at PULSE OUTP
7. 10pF d Figure 2 8 Oscillator Circuit Note It is not necessary to place an external resistor across the crystal i e R91 on the 4 Layer Demo Board must not be populated Note Capacitor values for the crystal must be 15pF Revision 2 0 36 of 66 Copyright 2005 TERIDIAN Semiconductor Corporation d jTERIDIAN 2 3 TESTING THE DEMO BOARD This section will explain how the 71M6515H IC can be tested Hints given in this section will help evaluating the features of the Demo Board and understanding the IC and its peripherals 2 3 1 TESTING THE DEMO BOARD USING THE GUI It is a good idea to get familiar with the features of the 71M6515H chip and the Demo Board using the GUI program Some features can be explored by just feeding the 5VDC to the Demo Board without any high voltage involved When applying voltage and current signals to the Demo Board the GUI should look similar to the screen print shown in Figure 2 9 EN TSC 71M6515 Power Meter IC Test Program v1 10 14 OCT 2005 Pulse1 5 Pulse S S Pulse4 S Config Status Mask CH ulsel Source Pulse2 Source Pulse3 Source Pulse4 Source VA Calc y 1 BOOTUP W 10 266 10282 10274 ENABLE O saca VARh 016 0101 0 _1 ENABLE 0 sace 10 084 10087 sacc Vims 220040 220 040 E imm O T VPEAK Ims 0 436 0 436 A IPhase 0 sei 9 357 ZB
8. Positive p direction 60 1 Current Na 790 Current leads voltage Y capacitive p A ae 2 S PD Voltage Generating Energy Using Energy Figure 2 1 Phase Angle Definitions 2 1 3 ERROR SOURCES IN A METER CT SHUNT RESISTOR A typical meter has phase and gain errors as shown by s and Axy in Figure 2 2 Following the typical meter convention of current phase being in the lag direction the small amount of phase lead in a typical current sensor is represented as s The errors shown in Figure 2 2 represent the sum of all gain and phase errors They include errors in voltage attenuators current sensors and in ADC gains n other words no errors are made in the input or meter boxes INPUT ERRORS METER mec RM 16 gt gt IDEAL I ACTUAL I Ay 0 is phase lag ds is phase lead w IDEAL IV ACTUAL IV ds Vnus V gt gt IDEAL ACTUAL V ACTUAL IDEAL _ ACTUAL _ IDEAL IDEAL ERROR Figure 2 2 Watt Meter with Gain and Phase Errors During the calibration phase we measure errors and then introduce correction factors to nullify their effect With three unknowns to determine we must make at least three measurements If we make more measurements we can average the results C
9. 8 13 in the CONFIG register default 60 The length of an accumulation cycle is t SUM CYCLES 16 66ms WRATE The value in the pulse rate control register RATE default 683 X The pulse rate acceleration factor determined by bits 25 PULSE FAST and 26 PULSE SLOW in the CONFIG register default 2 1 5 Almost any desired Kh factor can be selected for the Demo Board by resolving the formula for WRATE Revision 2 0 24 of 66 Copyright 2005 TERIDIAN Semiconductor Corporation 1 8 7 d J TERIDIAN ADJUSTING THE DEMO BOARDS TO DIFFERENT CURRENT TRANSFORMERS AND VOLTAGE DIVIDERS The Demo Board is prepared for use with 2000 1 current transformers CTs This means that for the unmodified Demo Board 208A on the primary side at 2000 1 ratio result in 104mA on the secondary side causing 177mV at the 1 7Q resistor pairs R24 R25 R36 R37 R56 R57 2 x 3 4Q in parallel In general when IMAX is applied to the primary side of the CT the voltage Vin at the IA or IB input of the 71M6515H IC is determined by the following formula R IMAX Vn where N transformer winding ratio R resistor on the secondary side If for example IMAX 208A are applied to a CT with a 2500 1 ratio only 83 2mA will be generated on the secondary side causing only 141mV The steps required to adapt a 71M6515H Demo Board to a trans former with a winding ratio of 2500 1 are outlined below 177mV _ 1 The formula N is applied to calc
10. Ay Ay cos ds Ay tan 60 sin 9 lt 1 Subtract 8 from 7 9 Eg 2Ayy Ay tan 60 sin 9 use equation 5 7 B d ccu 60 300 tan 60 sin cos 11 E E Eiso 2 tan 60 tan Es m Eoo tan 60 E Eig 2 10 E 123 090 2 an O Copyright 2005 TERIDIAN Semiconductor Corporation d J TERIDIAN Now that we know the Axi and s errors we calculate the new calibration voltage gain coefficient from the previous ones DUE uu as Ay We calculate PHADJ from the desired phase lag tan I 1 2 220 2 cos 2af T 1 2 sin zf T tan l 1 2 cos 2zf T And we calculate the new calibration current gain coefficient including compensation for a slight gain increase in the phase calibration circuit NEW 2 2 PHADJ 2 2 29 PHADJ 2 1 29 co 2 7 1 2 1 29 co 27 1 27 PHADJ 22 XI CALIBRATION FOR METERS WITH ROGOWSKI SENSORS Rogowski coils generate a signal that is the derivative of the current The 6515H Rogowski module implemented in the Rogowski CE image digitally compensates for this effect and has the usual gain and phase calibration adjustments Additionally calibration adjustments are provided to eliminate voltage coupling from the sensor input Current sensors built from Rogowski coils have a relatively high output impedance that is susceptible to capacitive coupling
11. HEADERS SXIPIN _S1017 36ND PZC36SAAN L2 3 ERI BGEYOROOV Panasonic 730 3 Re 10 Ax 10042 50 20008 008 Yageo 681 1 2861206 3118 0FCT ND 9C12069AG8ROFKHFT Yageo La o RR O ERJ 6GEYOROOV Panasonic 35 6 RIZRIZRARSZRSSRIZ 750 05 860805 RRIZPTSODCT ND RRI220P 781 D SUSUMU DP maemaeRseRe4ROe ROS 1 12 12 737 R2iR25R36R3756R57 34 80106 311 340FCT ND SCTZ06SAGRAOFGHFT Yageo 6 RERGRIBRISRNO 10K 8609603 PIOKGCTND ERISCEVIOM Panasonic Pao filo esw 60619 EVQ PUXOSM Panasonic MES SH TO TERIDIAN 55 1 16149964 169 55 YAMAICHI Table 4 1 71M6515H Demo Board Bill of Material Copyright 2005 TERIDIAN Semiconductor Corporation d J TERIDIAN RUI TRAL unc Te VA IN h a Ui quo 4 cet TIME313 BOARD REV 2 yC 2 SBI EM E END AVE CR Hb RDT FR M END SEDATA BLLK A Figure 4 4 TERIDIAN 71 6515 Demo Board View Copyright 2005 TERIDIAN Semiconductor Corporation d J TERIDIAN tk He Figure 4 5 TERIDIAN 71M6515H Demo Board Bottom View O C
12. R2 5 ND R6 0 59 of 66 V5 DBG C1 C3 0 1UF GND DBG V5 DBG 5 TERIDIAN SEMICONDUCTOR CORP VDD2 GND2 DOUT GND2 0 1UF STATUS LEDs DIO00 DIO01 51002 p V3P3 ND ND 2 VUXOU ND D UAR 57 ND D DART ER ND DB ND DB V5 DB A P VS DE UART T HEADER 8X2 DEBUG CONNECTOR jT ERIDIAN EXT SUPPLY BYTE BLASTER Wr NULL AA EE i TOP NORMAL BOT CELLE O Figure 4 12 Debug Board Bottom View Copyright 2005 TERIDIAN Semiconductor Corporation 71M6515H Demo Board Users Manual Figure 4 14 Debug Board Middle Layer 1 Ground Plane Revision 2 0 61 of 66 Copyright 2005 TERIDIAN Semiconductor Corporation 71 6515 Demo Board Users Manual Figure 4 16 Debug Board Bottom Trace Layer Revision 2 0 Copyright 2005 TERIDIAN Semiconductor Corporation TERIDIAN SEMICONDUCTOR CORP 62 of 66 d J TERIDIAN Power Ground Pin Description Nome Fin No Type Description Ne 49 60 EN Analog ground This pin should be connected directly to the ground plane 1 EN Digital ground These pins must be connected directly to the ground plane 50 V3P3A EN Analog power A 3 3V analog power supply should be connected to this pin V3P3D M m 7 Digital power supply 3 3V digital power supply should
13. The parameters entered here are closely related to the calibration parameters Watt 0 Noise compensation factor for the Watt calculation VAR 0 Noise compensation factor for the VAR calculation Noise compensation factor for the current calculation Multi Purpose Area 13 This area consists of two list fields and three rectangular buttons SCALED RAW List field This list field toggles the display of display and entry fields between scaled displayed values scaled using VMAX and raw data raw counts from 6515H mode In scaled mode values for voltage current and energy will be displayed as V A Wh VARh etc In raw mode the values will appear in the internal format of the 71M6515H chip STANDARD List field This list field toggles the values shown in display and entry fields HEX between standard decimal and hexadecimal mode Refresh Rectangular Pressing this button forces the GUI to transmit any changes made in button entry or list fields to the 71M6515H chip Apply Rectangular Placing the cursor into another entry field will have the same effect as button the Refresh button Pressing this button will apply a change made in an entry field CLEAR Rectangular Pressing this button will clear the contents of the Status Window button Revision 2 0 19 of 66 Copyright 2005 TERIDIAN Semiconductor Corporation d JL EPIDIAN SEMICONDUCTOR CORP Digital I O Area 14 This area consists of three
14. directly in Volts The GUI will round the entered value to the next possible value that can be represented with the resolution used for this parameter Determines the sag alarm setting Sag must persist 54 CNT 397us before the sag alarm is generated Allowed range is 1 to 2734 Default is 80 31 7ms Starting V 39 974 Determines the voltage below which the calculation of frequency zero crossings and voltage phase is suppressed Starting 0 048 Determines the current below which the calculation of current related values is suppressed Revision 2 0 18 of 66 Copyright 2005 TERIDIAN Semiconductor Corporation 71 6515 Demo Board Users Manual SEMICONDUCTOR CORP Real Time Monitor Area 11 This area consists of four entry fields to the right of the System Constants area The entries determine any four CE data memory locations to be monitored The RTM ENABLE square button in the Configuration area has to be in the 1 position for the RTM to be active First CE data memory location to be monitored RTM1 Second CE data memory location to be monitored RTM2 Third CE data memory location to be monitored RTM3 Fourth CE data memory location to be monitored Note Using the RTM interface requires special external hardware Contact TERIDIAN for details QUANT Area 12 This area consists of three entry fields that can be used to eliminate non linearity at low currents caused by truncation noise
15. entry fields below the Real Time Monitor area The entries determine the configuration and settings of the eight DIO pins DO to D7 GUI Element Function Label M 0x00 The hexadecimal number entered here defines the pattern that is applied to the I O pins mE 0x00 The hexadecimal pattern entered in this field determines whether a DEDGE interrupt is generated upon a bit changing its status A 1 means that the corresponding DIO pin generates an interrupt DEDGE interrupts are only generated for DIO pins that are configured as inputs Direction OxFF The hexadecimal number entered here defines whether I O pins are inputs 0 or outputs 1 A signal transition on an input pin will generate a DEDGE interrupt only once This interrupt will not be syn chronized with the accumulation interval or the 1 sec interrupt Several transitions per accumulation interval are possible With every signal transition on a DIO pin the message Some Dn pin values have changed will be displayed in the Status Window Status Window Area 15 This is the white rectangular window at the bottom center of the GUI display Activities of the PMtest exe GUI Control program error messages etc are listed here If more events occur than can be displayed in the lines of this window the display will scroll Events and messages that occurred in the past will then be displayed by scrolling the window using the scroll arrows to the right of it When the r
16. for PHADJ after the phase error os has been calculated use the PHADJ equation shown below Note that the default value of PHADJ is not zero but rather 3973 PHADJ PHADJ previous 9x 1786 0 If voltage coupling at low currents is introducing unacceptable errors perform step 2 below to select non zero values for VFEED A VFEED B and VFEED C Copyright 2005 TERIDIAN Semiconductor Corporation jT ERIDIAN Step 2 Voltage Cancellation Select a small current lays where voltage coupling introduces at least 1 5 energy error At this current measure the errors Eo and Ergo to determine the coefficient VFEED E E V VFEED o 2 AMS MAX VFEED pius MAX V aus 2 1 7 CALIBRATION SPREADSHEETS Calibration spreadsheets are available from TERIDIAN Semiconductor Figure 2 3 shows the spreadsheet used for three measurements Figure 2 3 shows the calibration spreadsheet used for five measurements TERIDIAN SEMICONDUCTOR CORP 71M6511 71M6513 71M6515 Calibration Worksheet Three Measurements Enter values in yellow fields REV 4 0 Results will show in green fields Date 9 28 2005 frequency E 50 Author WJH click on yellow field to select from pull down list PHASE A fraction c Energy reading at 0 0 CAL IA 16384 p POM Voltage Energy reading at 60 0 CAL VA 16384 N q Voltage reading at 0 PHADJ A 0 P4 N Current lags N Expected voltage v
17. from the large voltages present in the meter The most dominant coupling is usually capacitance between the primary of the coil and the coil s output This coupling adds a component proportional to the derivative of voltage to the sensor output This effect is compensated by the voltage coupling calibration coefficients As with the CT procedure the calibration procedure for Rogowski sensors uses the meter s display to calibrate the voltage path and the pulse outputs to perform the remaining energy calibrations The calibration procedure must be done to each phase separately making sure that the pulse generator is driven by the accumulated real energy for just that phase In other words the pulse generator input should be set to WhA WhB or WhC depending on the phase being calibrated The IC has to be configured for Rogowski mode IMAGE 01 In preparation of the calibration all calibration parameters are set to their default values VMAX and MAX are set to reflect the system design parameters WRATE and PUSE SLOW PULSE FAST are adjusted to obtain the desired Kh Step 1 Basic Calibration After making sure VFEED A VFEED B and VFEED C are zero perform either the three measurement procedure 2 1 4 or the five measurement calibration procedure 2 1 5 described in the CT section Perform the procedure at a current large enough that energy readings are immune from voltage coupling effects The one exception to the CT procedure is the equation
18. require time to get synchronized in order to obtain accurate measurements For a typical energy calibration a meter calibration system is used to apply a calibrated load e g 240V at 30A while interfacing the voltage and current sensors to the 71M6515H This load should result in an observable pulse rate at the WPULSE output depending on the selected energy per pulse For example 7 2kW will result in a pulse rate corresponding to 7200Wh 3600s 2Wh s Most calibration systems provide ways to evaluate the observed pulse rate by comparing it to the ideal pulse rate DEFINITIONS Each meter phase must be calibrated individually The PHADJ equations apply only when a current transformer is used for the phase in question If a Rogowski coil is used the phase compensation should be correct by default and adjustments are required only to CAL Ix and CAL Note that positive load angles correspond to lagging current see Figure 2 1 The calibration procedures described below should be followed after interfacing the voltage and current sensors to the 71M6515H chip When properly interfaced the V3P3 power supply is connected to the meter neutral and is the DC reference for each input Each voltage and current waveform as seen by the 71M6515H is scaled to be less than 250mV peak Copyright 2005 TERIDIAN Semiconductor Corporation d J TERIDIAN POE UR S Voltage N 2 5 A Current lags N voltage N
19. supply When using an external battery the battery is connected between pins 2 and 3 GND Table 3 1 71M6515H Demo Board Description 1 3 Copyright 2005 TERIDIAN Semiconductor Corporation d J TERIDIAN 5 Volt external Plug for connecting the external 5 VDC power supply supply wall transformer Chip reset switch The RESETZ pin has an internal pull up RESET that allows normal chip operation When the switch is pressed the RESETZ pin is pulled low which resets the IC into a known state VA IN VB IN Spade terminals mounted on the bottom of the board for VC IN the connection of the phase A B and C wires Each point JP22 JP23 an has a resistor divider that leads to the VA VB or VC pin 4 JP24 on the chip Caution High Voltage Do not touch these pins TP 13 TP 14 GND test points Three pin header for selecting the pulse output initial power up In the default setting a jumper is ve plugged between pins 2 and 3 causing pulse outputs to be at the low 0V state Three pin header for enabling the UART of the 71M6515H UARTCSZ In the default setting a jumper is plugged between pins 2 and 3 causing the UART to be enabled When the IC is configured to generate interrupts on the INTERRUPT IRQZ pin this LED will blink IRQZ active low will cause the LED to be on This LED is activated by the RPUSE output if RPULSE is 19 VARS selected with JP30 pins 2 and 3 Alternativ
20. 3 Copyright 2005 TERIDIAN Semiconductor Corporation d J TERIDIAN This 3 pin header allows selection of the baud rate for the UART of the 71M6515H In the default position pin 1 to BAUDRATE 2 the chip operates at 19 2kbps When the jumper is plugged between pins 2 and 3 the chip operates at 38 4kbps 29 Serial number field The serial number of the Demo Board is entered in this field by TERIDIAN 30 64 pin socket containing the 71M6515H chip Table 3 3 71M6515H Demo Board Description 3 3 S m 4 1 2 1 Figure 3 1 71M6515H Demo Board Connectors Headers LEDs Switches Copyright 2005 TERIDIAN Semiconductor Corporation d J TERIDIAN 3 2 CONNECTOR DESCRIPTIONS 3 2 1 JP6 SSI INTERFACE JP6 provides access to the SSl related pins of the 71M6515H chip via decoupling resistors of 620 for each signal The pin layout for JP6 is shown in Table 3 4 sn 6 sem _ Table 3 4 JP6 Pin Description 3 2 2 18 EXTERNAL INTERFACE JP18 provides access to the digital I O pins and to other signals of the 71M6515H chip The pin layout for JP18 is shown in Table 3 5 Signal sPi Pin suma iem Siona Dr we o Pusen 7 2 w wuse forame n rz mum 2 reuse ew s Runn u nos DO DIO reuse 5 oo jm 5300 Table 3 5 JP18 Pin Descrip
21. 4 Y Cal deg 0 Calibrate IC 16384 v Cal deg Calibrate VC 16384 1 Ims Peak DAP TAFT Phaze Adjust rag BN oe 7 Count 18 Phase 0 4 7 To 3841 Starting V Phase Adjust DEG SCALE 7 1 PULSE SLOV 19 005 Hours 9 e e e 9 e 8 o e 9 9 Mr e a PULSE FAST EL 4 vEesdA watt VFeed Jen a o l Regal Time Clock VFeedB IB 8x Cet ATC _ Set ATC 2005 10417 VFeedE watt VFeed 0 IC 8x DEFAULT PPM 0 Est 15 27 21 Chip Version Figure 1 4 Host GUI Window w Functional Groups Areas Marked and Numbered 1 8 4 GUI WINDOW DISPLAY AND CONTROL FIELDS The PMTEST GUI window as shown in Figure 1 4 contains a number of major blocks or areas Pulse Source Select Config Status Mask Calibration Constants Temperature Compensation Real Time Monitor Digital I O Thresholds and Operating Time These major blocks labeled 1 through 12 in Figure 1 4 group the functionally related buttons and fields together The elements of the GUI are as follows e Rectangular buttons Buttons that can be clicked by the user to initiate an action ACCUM e Square buttons Buttons that can be clicked by the user to initiate an action The square buttons have a single digit showing the current state of
22. 5 Transformers WPULSE O a External Interface O IA O k V3P3 Connector JP26 NJ E RPULSE M O JP18 JP29 IB E bugs WPULSE O IC ees 7 o RPULSE IC oj 28 H O USUS DIO 0 8 Ra VC 0224 VB o JP23 4 BO TX 0922 e RX VA VB SSI Connector m JP1 Io s VC SSI Signals O t1 JP6 NEUTRAL sos LA GND qs ETIN ICM MEE GND DEBUG BOARD OPTIONAL e 51 5V e 2 TX RS 232 PO DB9 DC INTERFACE 2 o COM Port RX lt Y o O t 2 DA DIES E UARTCSZ OPTO SUPPLY OPTIONAL RTM INTERFACE TMUXOUT porto 2 1 BAUDRATE EROR ao CKTEST O OBI V5 DBG E O OPTO O 5V DC i JP31 PULSE INIT 1 V5 NI GND DBG O JP21 EE Figure 1 2 Block diagram for the TERIDIAN 71M6515H Demonstration Meter with Debug Board Note All input signals are referenced to the V3P3 3 3V power supply to the chip 1 6 1 POWER SUPPLY SETUP There are several choices for meter power supply e Internal using phase A of the AC line voltage The internal power supply is only suitable when phase A exceeds 220V RMS e External 5VDC connector J1 on the Demo Board and external 5VDC connector J1 on the Debug Board The power supply jumper JP1 must be consistent with the power supply choice JP1 disconnects phase A from the power supply This jumper sh
23. 6 Copyright 2005 TERIDIAN Semiconductor Corporation d J TERIDIAN Table of Contents 1 GETTING STARTED M 7 WA Generala a E E X 7 1 2 Safety and INOS 7 1 9 D mo 7 JU MEE S 11 Ei 7 1 5 Suggested Equipment not included 8 16 Demo Board Test Setup ias pass iai cect cee ete 8 1 6 1 Power Supply 1 9 1 6 2 Serial Se DD snis edite oa 10 ler the ga so S UU n A zac a nato 10 1 5 WISI the Demo Zo sie i kid A Za ni o aaa 11 1 8 1 Starting up the Demo Board and the GUI Program e nn nn 11 1 8 2 Controlling the Demo taion ka rola n ako nn vina 11 Ip MEC Rise OVER EN mm 12 1 8 4 Window Display and Control 12 1 8 5 GUI Window Control and Display Fields Detailed Description 14 1 8 6 Adjusting the Kh Factor for the Demo mnn nnne nnn 24 1 8 7 Adjusting the Demo Boards to Different Current Transformers and Voltage Dividers 25 1 9 Calibrating the Demo
24. 6GEYOROOV Panasonic PB switch P8051SCT ND EVQ PJX05M Panasonic 4 X P A 6 V M 3M N D U1 U2 U3 U5 U6 ISOLATOR SOIC8 ADUM1100AR ND ADUM1100AR A TP5 TP6 Test Point Ea 1 5011K ND 5011 Keystone Electronics RS232 DRIVER 28SSOP MAX3237CAI ND MAX3237CAI MAXIM Table 4 2 Debug Board Bill of Material J1 J2 J3 R W _6 4 7 2 8 8 po 1 20 1 NO 0 Copyright 2005 TERIDIAN Semiconductor Corporation 71M6515H Demo Board User s Manual 089 RS232 NIN Woo 0 Revision 2 0 RXPC 5Vdc EXT SUPPLY J1 RAPC712 GND_DBG JP1 HDR2X1 _ HDR2X1 V5 DBG GND DBG C14 V5 DBG C11 TP5 TP6 TP TP a a 2 2 10uF 16 Case V5 13 0 1 U4 MAX3237CAI 232VP1 27 232VN1 4 2 1 232 T2IN T3IN T4IN RX232 R1OUTBF R1OUT R20UT R3OUT R5 10K GND DBG 28 25 24 23 22 19 17 16 21 20 18 GND DBG RS232 TRANSCEIVER 232C1P1 C15 0 1uF v5 DBG 232C1M1 C19 232C2P1 C18 0 1uF 0 1uF 232C2M1 GND DBG GND DB TXISO ND DB RXISO V5 DBG 22 0 1uF GND DBG V5 DB ND DB C23 0 1 GND DBG OI DN Co ADUM 1100 ADUM 1100 Figure 4 10 Debug Board Schematics Copyright 2005 TERIDIAN Semiconductor Corporation O sw2 DISPLAY SEL GND DBG GND 0 1uF C21 GND 0 1uF 8 V3P3 7 ND 6
25. 71 6515 Demo Board Users Manual Revision 2 0 Uae SEMICONDUCTOR CORP ial ul ab a Ah A 71M6515H Demo Board USER S MANUAL T T r x E Hi 177 pz BAUDRATE PT 78 um GND pur XL v um ENE SADY _ R 5 0 6519 4 1 ENDA BSDATA END SSCLK R L DEBUG EEE Ek Els t BEE 12 5 2005 2 06 PM Revision 2 0 TERIDIAN Semiconductor Corporation 6440 Oak Canyon Rd Irvine CA 92618 5201 Phone 714 508 8800 Fax 714 508 8878 http www teridian com meter support teridian com 1 of 66 Copyright 2005 TERIDIAN Semiconductor Corporation d jTERIDIAN TERIDIAN Semiconductor Corporation makes no warranty for the use of its products other than expressly contained in the Company s warranty detailed in the TERIDIAN Semiconductor Corporation standard Terms and Conditions The company assumes no responsibility for any errors which may appear in this document reserves the right to change devices or specifications detailed herein at any time without notice and does not make any commitment to update the information contained herein Copyright 2005 TERIDIAN Semiconductor Corporation 71 6515 Demo Board Users Manual 71M6515H 3 Phase Power Meter AFE IC DEMO BOARD USER S MANUAL Revision 2 0 3 of 6
26. ADC in the 6515H can be disabled by selecting 1 with button this button This setting can be used for saving power on the target chip 3 Square The value for TMUX determines the source selected for the buttons and TMUX output pin on the 71M6515H The value can be List field selected with the three buttons Freq Source 2 Square The phase to be used for measuring the signal frequency can buttons and be selected with the two buttons as a binary word Entry field m field The measured frequency of the phase determined by the Freq Source field is displayed here EE ONLY Square The CE only operation mode can be selected by setting this button square button to 1 Omits internal calculation of IPHASE IRMS VAH and VRMS This feature permits smaller accumulation intervals SUM CYCLES 15 6 Square The CE mode to be used standard or Rogowski can be buttons and selected with the two buttons as a binary word IMAGE cannot Entry field be selected while the CE is running To change the setting follow this sequence 1 Disable the CE 2 Reset the 6515H 3 Select the new image 4 Enable the CE Square The 6515H chip can be reset by selecting 1 with this button button and Rectangular button Copyright 2005 TERIDIAN Semiconductor Corporation d J TERIDIAN GUI Element Element Default Function Label Type PULSE SLOW Square This button in conjunction with PULSE FAST WRATE button the Pulse S
27. B Silk screen layer Bottom side Debug Board PCB Metal Layer Top side signal layer Debug Board PCB Metal Layer Middle 1 ground plane Debug Board PCB Metal Layer Middle 2 supply plane Debug Board PCB Metal Layer Bottom side signal layer 71M6515H Description 71M6515H Pin Description and Pin out Diagram Copyright 2005 TERIDIAN Semiconductor Corporation 71 6515 Demo Board User s Manual Neutral JP22 L2 Revision 2 0 RAPC712 5VDC EXT SUPPLY L1 R2 8 06K C29 zi 5 0 030UF 1000V MS 6 8V 1W R4 25 5K C6 R6 04 100 2W 1N4148 130 0 47UF 1000 2 JPA Enw ii PS SEL 0 68 1206 PACKAGE 3P3 G1 G2 G3 G6 GND O gt FT R10 ND TMUXOUT T ND UARI TX 62 ND 2 UART RX Top Mount Holes DEBUG MOUNT 5 R11 HEADER 8X2 62 DEBUG CONNECTOR R12 62 Figure 4 1 TERIDIAN 71M6515H Demo Board Electrical Schematic 1 3 Copyright 2005 TERIDIAN Semiconductor Corporation TERIDIAN lt SEMICONDUCTOR CORP V3P3 D7 UCLAMP3301D CKTEST TMUXOUT UART_TX 48 of 66 71 6515 Demo Board User s Manual R15 R16 R17 VA IN VA IN 220K 220K 220K R26 R27 220K 220K JP23 R38 R39 R40 VB IN VB IN VB 220K 220K 220K R46 R47 220 220 JP24 R58 R59 R60 VC IN IN 220 220 220 R66 R67 220 220 JP25 NEUTRA NEUTRAL C14 i 001uF VOLTAGE GND CONNECTIONS Revision 2 0 R18 220K R28 220K R41 220K R48 220K
28. EE o 358 CLR ACCUM eo o PED EEE fo Gain Adjust Accumulated energy 2 o READY 1 Calibration Constants Temperature Compensation Pulse width 6 68 msec 683 Quant 9 0 1 DSB 9 0 x Raw 8451 76 Watt 0 Calibrate 16384 VMAX ms 600 0 Real Time Monitor 0 ADC DIS 2 CREEPC da Calibrate V 16375 maxims meg RITMO 0x00 vafo IGNORED Calibrate 16384 i RTM1 0 o FULSE1 0 0 PULSE2 Calibrate VB 16377 A RTM2 0x00 FULSE3 Calibrate IC 16384 RTM3 000 Source A FULSE4 Calibrate VC 16372 1 SCALED STAN DARD i ONLY 60 0 Main Edge 1 Digital 1 0 Phase Adjust 0 p por Refresh o 120 alues p Adiust 0 IMAGE CT Shunt 46215 PPM C2 555 Starting 39974 0500 QUEM B Phase Adjust 0 TE 3 ma Ti DEG SCALE 22721 Stating 0 048 Directions Ux CLEAR o RESET Operating Time Rogowski Constants PULSE SLOW Hours 1 PULSE FAST Es VFeeda Watt VFeed T IA B 5 VFeedB Watt VFeedB E IB 9 me pe ud _ 2005 1071 VFeedC Watt VFeedC _8 2005 10 13 second tic 0 DEFAULT PPM Chip Version 651 5803 v Exit 10 57 11 Figure 2 9 Typical GUI Window A few observations can be deri
29. N SHOULD BE TAKEN WHEN HANDLING THE DEMO BOARD ONCE IT IS CONNECTED TO LIVE VOLTAGES THE DEMO SYSTEM 15 ESD SENSITIVE ESD PRECAUTIONS SHOULD BE TAKEN WHEN HANDLING THE DEMO BOARD DEMO KIT CONTENTS e 71M6515H Demo board containing 71M6515H AFE IC e Debug Board e Two 5VDC 1 000mA universal wall transformer with 2 5mm plug Switchcraft 712A compatible Serial cable 089 Male Female 2m Digi Key AE1020 ND e CD ROM containing documentation data sheet board schematics BOM layout PC executable program GUI and calibration spreadsheet Note The media CD ROM contains a file named readme txt that specifies all files found on the media and their purpose COMPATIBILITY STATEMENT This manual is compatible with REV1 1 October 14 2005 of the Control Program GUI and with 71M6515H code revision 1 1 October 14 2005 Copyright 2005 TERIDIAN Semiconductor Corporation d jTERIDIAN 71M6515H Demo Board User s Manual 1 5 SUGGESTED EQUIPMENT NOT INCLUDED PC w MS Windows versions XT or 2000 equipped with RS232 port COM port 9 connector 1 6 DEMO BOARD TEST SETUP Figure 1 1 shows the basic connections of the Demo Board plus Debug Board with the external eguipment Figure 1 1 TERIDIAN 71M6515H Demo and Debug Boards Basic Connections The 71M6515H demo board system is shown in Figure 1 2 It consists of a stand alone rectangular meter Demo Board and an optional Debug Board most Debug Boar
30. Rogowski Sensor Calibration constant for phase current default m Calibration constant for phase C current default TT Calibration constant for phase C voltage default 16384 Phase Adjust A Calibration constant for phase A current Calibration constant for phase A current angle default 0 angle default 397 3 Phase Adjust B Calibration constant for phase B current Calibration constant for phase B current angle default 0 angle default 3973 Phase Adjust C Calibration constant for phase C current Calibration constant for phase C current angle default 0 angle default 3973 During calibration see section 2 1 the values of the calibration coefficients obtained with the calibration formulae should be entered in these fields Temperature Compensation Area 3 This area consists of a vertical column of entry and display fields to the right of the Calibration Constants area The Gain Adjust field from area 1 functionally belongs in the Temperature Compensation area GUI Element Element em Type Display Display field Display field Raw temperature chip substrate temperature Delta T Display field Difference between raw and nominal calibration temperature Nominal Entry field The raw temperature should be entered here during calibration The constant correction coefficient for the RTC can be Toa cego Enty teig o entered here if RTC compensation is requ
31. UT 3 TP UARTCSZ UARTCSZ sl V3P3 u JPT9 GND io f d 1 2 C40 Nele m a IN 2 gt gt al GND 0 1uF g NE p Z LI o Deo I B JP9 V3P3 Ol ama GND CLAMP3B01DC23 we 51 small green SMT LED 10uF GND R78 C42 IRQZ 6515 64TQFP UX_SYNC MUX_SYNC RDY 10K D 0 001uF D C24 INTERRUPT 10pF Y1 32 768Khz R55 C25 GND R45 10K S R33 10pF 5 R110 x 10K GND 10k IE GNO 25 GND GND DIDO Io oo TP 13 TP14 TP15 TP16 3 WAY RESISTOR PAD TP TP TP TP POPULATE 10K BETWEEN 142 R111 5 R112 GND S V3P3 gt S Z gt C28 pm X 1k 1k 0 1uF m GND TMUXOUT CKTEST TMUXOUT CKTEST 10 ND ND 1 TINO 38 4K 1 9 2k P RATE 4 2 JP32 TP17 18 TES Figure 4 3 TERIDIAN 71M6515H Demo Board Electrical Schematic 3 3 Revision 2 0 50 of 66 Copyright 2005 TERIDIAN Semiconductor Corporation d J TERIDIAN item T Part P8 Footprint PIN Manufacturer PIN Manufacturer La I o SE co Block capacitor 9 222383 30474 ne Toe o a cecco TK Die 575 ucena 50033 UciAMPSSOIDICT SEMTECH LEDSM Green RGOB05 160 414 tND LTST Ci70KGKT 2 6 3P83P5JP299e32
32. age scaling factor as described in section 1 8 IMAX current scaling factor as described in section 1 8 LSB QUANT LSB value 7 4162 10 W VI QUANT W Example Assuming an observed error as in Figure 2 5 we determine the error at 1A to be 1 If VMAX is 600V and IMAX 208A and if the measurement was taken at 240V we determine QUANT as follows 340 1 QUANT_W 100 11339 600 208 7 4162 10 QUANT W is to be written to the CE location Ox2F It does not matter which current value is chosen as long as the corresponding error value is significant 5 error at 0 2 used in the above eguation will produce the same result for W Input noise and truncation can cause similar errors in the VAR calculation that can be eliminated using the QUANT VAR variable QUANT VAR is determined using the same formula as QUANT Copyright 2005 TERIDIAN Semiconductor Corporation 2 2 2 2 1 2 2 2 2 2 3 SCHEMATIC INFORMATION In this section hints on proper schematic design are provided that will help designing circuits that are functional and sufficiently immune to EMI electromagnetic interference COMPONENTS FOR THE VFLT PIN The VFLT pin pin 59 of the 7 M6515H must never be left unconnected A voltage divider should be used to establish that the voltage at VFLT is in a safe range when the meter is in mission mode see Figure 2 6 VFLT must be lower than 2 9V in all cas
33. alibration voltage gain coefficient from the previous ones CAL V We calculate PHADJ from os the desired phase lag tan l 12 2 220 2 eos277 T 1 2 sin 2zf T tan l 1 2 cos 2zf T And we calculate the new calibration current gain coefficient including compensation for a slight gain increase in the phase calibration circuit 3 CAL PHADJ 22 Copyright 2005 TERIDIAN Semiconductor Corporation d J TERIDIAN CAL I 1 TM 2 PHADJ 2 2 PHADJ 201 2 cos 2f T 1 2 1 2 cosQzf T 1 27 CAL Ly XI CALIBRATION WITH FIVE MEASUREMENTS The five measurement method provides more orthogonality between the gain and phase error derivations This method involves measuring Ev Eo E180 Eso and E300 Again set all calibration factors to nominal i e CAL IA 16384 CAL VA 16384 PHADJ A 0 First calculate Axy from Ey 1 gt Ay 1 Calculate from Eo and E40 IV A v A 0 2 UE P Ay 1 0 IV cos 0 IV A s A cos 180 0 3 E 8 4 A COS 1 180 IV cos 1 80 XV XI 4 24 4 cos 0 2 P 2608 95 gt E 2 1 A yy 5 0 Use above results along with Ego and Eoo to calculate ds _ IV Ay Ay cos 60 4 IV cos 60 Ay Ay 00 0 Ay Ay tan 60 sin 1 IV Ayy Ay cos 60 9 4 IV cos 60
34. as in the range of 0 025 to 0 459 a range that can easily be compensated by calibration Copyright 2005 TERIDIAN Semiconductor Corporation MATERIDIAN 71M6515H Demo Board Users Manual du SEMICONDUCTOR CORP WinBoard Meter Testing Serial No 3625 _ JD x Testing Functions Options FilefGraph Turbo Test E E cn 9 E A Exit Cancel REunF3 AdjOpticFa Creep F5 Mode Skip FT View F3 Save F10 Station 1 Total Saved Model 2300 CONTINUE MODE Task Hyper Sequence Test Az Az Phase Rev Std service Step Type Found Left Revs Ele Amp Angle Power Freg Limit AEP Lookup dr mms rem RE emas a 7 0 200 00 o w kh 3 32005 oltage Per one EEIRECELBENEREL TL BET AF Limits 1 Limit AL Limits 2 Al Limit Service Single Phase mi Reverse Power Start Delay 2 Optics Middle IR Test Complete Figure 2 11 Calibration System Screen Revision 2 0 Copyright 2005 TERIDIAN Semiconductor Corporation 39 of 66 71 6515 Demo Board Users Manual Revision 2 0 40 of 66 Copyright 2005 TERIDIAN Semiconductor Corporation d J TERIDIAN 3 HARDWARE DESCRIPTION 3 1 BOARD DESCRIPTION JUMPERS SWITCHES AND TEST POINTS The items described in t
35. be connected to this pin VBAT 45 Battery backup power supply A battery or super capacitor Is to be connected between VBAT and GNDD If no battery is used connect VBAT to V2P5 46 O Output of the 2 5V regulator A 0 11F capacitor should be connected to this pin Analog Pin Description CACO EX Line Current Sense Inputs Voltage inputs to the internal A D converter IA IB IC 56 55 54 Typically they are connected to the output of a current transformer The input is referenced to V3P3A Line Voltage Sense Inputs Voltage inputs to the internal A D converter A VB VC 53 52 51 Typically they are connected to the output of a resistor divider The input is referenced to V3P3A V VFLT Power Fault Input V Auxiliary input VREF Voltage Reference for the ADC Crystal Inputs A 32768Hz crystal should be connected across these pins XIN XOUT Typically a 10pF capacitor is also connected from each pin to GNDA See the datasheet of the crystal manufacturer for details Table 4 3 71M6515H Pin Description Table 1 2 Copyright 2005 TERIDIAN Semiconductor Corporation d J TERIDIAN Digital Pin Description Pins labeled RESERVED are not to be connected Unless otherwise indicated all inputs and outputs are standard CMOS Inputs do NOT have internal pull ups or pull downs Clock PLL output be enabled and disabled by CKOUT DSB see Status Mask 42 21 23 I
36. d can be made to generate interrupts When the square button right next to the status bit is pressed 1 the corresponding bit when active will generate an interrupt on the IRQZ output pin Activity on the IRQZ output pin is indicated with the green LED D8 on the Demo Board Copyright 2005 TERIDIAN Semiconductor Corporation TETADIAN FO fundamental of the input signal bit Vpeak bit Ipeak bit 1 second bit VXEDGE bit change in the state of the VX comparator DEDGE bit change in the state of any selected DIO XOVF bit host has failed to read at least one energy output value READY bit fresh output values are available O CREEPC O OmepbitrpaeC 00000 IGNORED O Commandignored by he TiMGSISH _ PULSE 0 PULSEW_ERR bit missing host data when in extemal mode PULSE 0 PULSER ERR bi missing host data when in external mode PULSES 0 PULSES ERRbi mssnghostdatawheninexemalmode PULSES 0 PULSEA ERR bit missing host data when in extemal mode Main Edge Area 18 This area consists of two display fields below the Status Word area Label Main Edge This field displays the number of zero crossings encountered in the last COUNT accumulation interval Main Edge TOTAL This field displays the total number of zero crossings counted since the last reset The value is reset to zero when the CLR ACCUM button in the Energy Volta
37. ds are partially assembled and have less components than shown in Figure 1 2 The Demo Board contains all circuits necessary for operation as a meter front end calibration LEDs and power supply The Debug Board is optically isolated from the meter and interfaces to a PC through a 9 pin serial port For serial communication between the PC and the TERIDIAN 71M6515H the Debug Board needs to be plugged with its connector J3 into connector JP21 of the Demo Board Connections to the external signals to be measured i e scaled AC voltages and current signals derived from shunt resistors or current transformers are provided on the rear side of the demo board Note It is recommended to set up the demo board with no live AC voltage connected and to connect live AC voltages only after the user is familiar with the demo system Revision 2 0 8 of 66 Copyright 2005 TERIDIAN Semiconductor Corporation d J TERIDIAN DEMONSTRATION METER 71M6515H JP30 D6 Single Chip Meter V3P3 AFE External Current D
38. ectangular CLEAR button above the Status Window is pressed the messages displayed in the Status Window are deleted Copyright 2005 TERIDIAN Semiconductor Corporation d SEMICONDUCTOR CORP Configuration Area 16 This area labeled Config consists of several square buttons entry fields and list fields located in a column to the left of the Status Mask area Combinations of square buttons are mirrored as list fields This means the same function can be controlled by either pressing the square buttons or by selecting a setting from the corresponding list field GUI Element Element E Type Square Selects the method for calculating VAh If O is selected the button and VAh is computed from Vnus Inus if A IS selected VAh is List field computed as the square root of Wh VARh RTM ENABLE Sguare Enables disables the Real Time Monitor CE ENABLE must button be 1 CE ENABLE Square Enables disables the CE button 3 Square 101 The equation to be used by the CE can be selected with the buttons and 5 three buttons as a binary word Entry field SUM CYCLES 6 Square 111100 The value for SUM CYCLES can be selected with the six buttons and 60 buttons as a binary word The length of an accumulation cycle Entry field 15 t SUM CYCLES 16 66ms SUM CYCLES should be gt 15 unless VA 0 or CE ONLY CKOUT DSB Square Disables the CKOUT pin of the target chip when set to 1 button ADC DIS Square The
39. ely the LED can be used to display the PULSEA output if the jumper on JP30 is between pins 1 and 2 Multi purpose test point consisting of a 12X2 header The 20 JP18 pulse outputs UART signals DIO pins interrupt control signals for baud rate and pulse polarity can be accessed Test point for D6 VARS When an optical pickup is not 22 TP31 used for the VARS or PULSE4 signal the pulses may be picked up with an electrical connection to TP31 This 3 pin header allows selection of the source signal for 23 JP30 PULSEA RPULSE to 3 the RPULSE pin drives the LED When the jumper is plugged between pins 1 and 2 the PULSE4 pin drives the LED This 3 pin header allows selection of the source signal for D5 WATTS with a jumper In the default position pin 2 25 29 PULSE3 WPULSE to 3 the WPULSE pin drives the LED When the jumper is plugged between pins 1 and 2 the PULSES pin drives the LED This LED is activated by the WPULSE output if WPULSE is selected with JP29 pins 2 and 3 Alternatively the LED Ro ES can be used to display the PULSE3 output if the jumper JP29 is between pins 1 and 2 JP21 DEBUG Connector for the Debug Board 2x8 pin male header D6 VARS with a jumper In the default position pin 2 Test point for D5 WATTS When an optical pickup is not 24 TP30 used for the WATTS or PULSES signal the pulses may be picked up with an electrical connection to TP30 Table 3 2 71M6515H Demo Board Description 2
40. emented VFeed BI 00 Not implemented VFeed C I Not implemented Pulse Source Selection Area 3 This area consists of four list fields to the right of the Energy Voltage Current and Phase area The entries determine the configuration and settings of the two pulse outputs used for four quadrant metering Pulse1 Source Wh This list field allows selection of internal external or one of 35 post processed parameters as the source for the PULSEW output Pulse2 Source VARh This list field allows selection of internal external or one of 35 post processed parameters as the source for the PULSER output Pulse3 Source Wh This list field allows selection of either an external host input or one of 35 post processed parameters as the source for the PULSE3 output The selection none is also available When none is selected the pulse output is disabled Pulse4 Source VARh This list field allows selection of either an external host input or one of 35 post processed parameters as the source for the PULSE4 output The selection none is also available When none is selected the pulse output is disabled When external source is selected for any pulse generator the missing pulse flags PULSE1 PULSE2 PULSE3 PULSE4 will be active for each accumulation interval for which the host does not provide an input Pulse Count Area 6 This area consists of a vertical column of display
41. es in order to keep the hardware watchdog timer enabled R83 V3P3 FERRITE C41 0 1UF C42 Figure 2 6 Voltage Divider for VFLT RESET CIRCUIT Even though a functional meter will not necessarily need a reset switch the 71M6515H Demo Boards provide a reset pushbutton SW2 that can be used when prototyping and debugging software When a circuit is used in an EMI environment the RESETZ pin should be supported by the external components shown in Figure 2 7 R75 should be in the range of 2000 R77 should be around 100 The capacitor Cas should be 1000pF and should be mounted as close as possible to the IC In cases where the trace from the pushbutton switch to the RESETZ pin poses an EMI problem Rz can be removed V3P3 SW2 R77 RESETZ C38 1000pF GND Figure 2 7 External Components for RESETZ OSCILLATOR The oscillator of the 71M6515H drives a standard 32 768kHz watch crystal see Figure 2 8 Crystals of this type are accurate and do not require a high current oscillator circuit The oscillator in the 71M6515H has been designed specifically to handle watch crystals and is compatible with their high impedance and limited power handling capability The oscillator power dissipation is very low to maximize the lifetime of any battery backup device attached to the VBAT pin Copyright 2005 TERIDIAN Semiconductor Corporation GATERIDIAN n 71M6515H 10pF XIN crystal L
42. fields underneath the Pulse Source area PULSE1 Cnt This field displays the count of pulses generated on the PULSEW output PULSE2 Cnt 8 3 This field displays the count of pulses generated on the PULSER output PULSE3 Cnt 00 This field displays the count of pulses generated on the PULSE3 output PULSE4 Cnt This field displays the pulse count of pulses generated on the PULSEA Pressing the CLR ACCUM button in area 1 will reset the pulse counts to zero Revision 2 0 16 of 66 Copyright 2005 TERIDIAN Semiconductor Corporation 71M6515H Demo Board User s Manual n a External Pulse Control Area 7 This area consists of a vertical column of combined display entry fields to the right of the Pulse Count area A field can be made and entry field by selecting External for the corresponding pulse source in the Pulse Source Selection area In all other selections the fields are display fields When the corresponding Pulse Source selection in the Pulse Source Selection area is Externa values can be entered in the External Pulse Control fields to simulate pulse control by the host A new value must be entered in each new accumulation interval The displayed values return to zero as soon as the next accumulation interval starts and no new values are supplied by the host If no values are supplied by the host the associated flags in the STATUS register see STATUS MASK area will be set If very large nu
43. ge Current and Phase Area is pressed Revision 2 0 23 of 66 Copyright 2005 TERIDIAN Semiconductor Corporation HL EPICUREI Operating Time RTC Area 19 This area consists of three display fields and two rectangular buttons all located towards the lower right edge of the GUI window Operating time Display field Displays the total operating time of the 6515H chip measured in 0 01 hours Display field Displays the date of year according to the RTC in the 6515H chip Clock Real Time Display field Displays the time of day according to the RTC in the 6515H chip Clock Set RTC Rectangular Pressing this button synchronizes the RTC of the 6515H chip with the button clock of the host PC EXIT Rectangular Pressing this button will terminate the GUI control program button Chip Version Area 20 This area consists of only one display field Chip Version This field displays the type and version of the 6515H chip e g 6515HB03 1 8 ADJUSTING THE KH FACTOR FOR THE DEMO BOARD The Kh factor i e energy per pulse is determined by the following equation VMAX IMAX Ins 15757 Wh Pulse SUM _CYCLES WRATE X Where VMAX The RMS voltage value that corresponds to the 250mV maximum input signal to the IC default 600V IMAX The RMS current value that corresponds to the 250mV maximum input signal to the IC default 208A SUM_CYCLES The value controlling the length of the accumulation cycle as determined by bits
44. he following tables refer to the flags in Figure 3 1 Schematic amp Item PCB Silk Figure 2 1 Screen Reference Header for high speed serial interface SSI One pin row is connected to GND TP17 TMUXOUT Testpoint for TMUXOUT signal TP18 CKTEST Test point for CKTEST signal JP19 o pin header A jumper should be installed between V3P3 and VFLT to disable the hardware watchdog timer VREF Test point for VREF signal Two pin headers that provide access to the current input 1 5 IA IB IC pins of the IC One terminal is ground the other is the respective line current sense input to the IC 7 JP26 JP27 IA IN IB IN CT connections The two pin headers are mounted on the JP28 IC IN bottom of the PCB One terminal is the 3 3V reference Two pin header When the jumper is installed the on board power supply AC signal is used to power the demo m board When not installed the board must be powered an external supply connected to S1 Normally installed Two pin header test points One end is either the VA VB TP2 TP4 TP6 VB and VC or VC line voltage input to the IC and the other end is V3P3 A spade terminal mounted on the bottom of the board for wee the connection of the NEUTRAL wire JP8 VBAT Selection Three pin header that allows selection of power to the VBAT pin In the default setting a jumper is placed 11 between pins 1 and 2 causing VBAT to be tied to the IC
45. ime an energy sum of 3 2 Wh is collected Similarly the red LED D6 will flash each time a reactive energy sum of 3 2 VARh is collected CONTROLLING THE DEMO BOARD Upon starting the PMTEST exe application the graphical user interface GUI of the demo application shown in Figure 1 4 will be displayed on the screen The gray boxes are the meter outputs and the white boxes contain host i e user inputs It is important to enable the computation engine CE in order to see activity in the GUI window You can check the computation engine CE status by verifying the status of the button on the left of in the Config block of the GUI It should display a 1 as shown in Figure 1 4 If not the CE can be enabled by clicking the 0 button to the left of the CE ENABLE text using the left mouse button Upon clicking the 0 will toggle to a 1 and the green and red indicator lights underneath the Status Mask text will start blinking Copyright 2005 TERIDIAN Semiconductor Corporation SEMICONDUCTOR CORP 1 8 3 GUI WINDOW OVERVIEW EJ TSC 71M6515 Power Meter IC Test Program 1 10 14 2005 are IE Pulse Cnt Pulse Cnt Pulse3 Cnt VPhase Angle Pulse4 Cnt IGNORED PULSE PULSE PULSES PULSE4 tel 1634 Calibrate 16384 Dear Calibrate IB 16384 Nominal Calibrate VB 1638
46. in these fields determine the system parameters of the Demo Board IMAX is tne RMS meter current that results in 220mV peak signal at the ADC input This variable reflects the scaling implemented by the voltage sensing resistors of the Demo Board Note When using shunt resistors as current sensors IMAX must be calculated as Vppmax 250mV y IMAX 7 2 VMAX is the RMS meter voltage that results in 250mV peak signal at the ADC input This variable reflects the design of the current sensing circuitry of the Demo Board assuming a 2000 1 current transformer Warning Thresholds Area 10 This area consists of seven entry fields to the right of the Temperature Compensation area ement Default Function gt gt gt 27000 Determines the creep threshold For each phase if WSUM X and VARSUM X of that phase are less than the value in the CREEP field the contents of Wh and VARh for that phase will be set to zero for the whole accumulation interval If all phases are below the creep threshold the CREEP bit in the status word is set The default value is 6000 Vrms Peak 733 2 Threshold for alarms measured Vrms Irms Peak 254 2 Threshold for over current alarms measured in Arms Sag Vpk 79 9 Determines the voltage sag threshold The peak voltage must exceed the voltage entered in this field at least once each 540 CNT samples in order to prevent a sag warning Values can be entered
47. ired The linear correction coefficient for the RTC can be entered Y Cal deg 1 Entry field here if RTC compensation is reguired Y Cal dea 2 Entrv field The quadratic correction coefficient for the RTC can be 9 y entered here if RTC compensation is required The linear compensation coefficient of gain over temperature is entered here automatically as soon as a temperature value is entered in Nominal field M E fiel Values determined by host may be entered here if the DEFAULT PPM bit in the Configuration area is set to 0 The quadratic compensation coefficient of gain over m temperature is entered here See the PPM C field for details Scaling factor for the calculation of temperature The default DEG SCALE Entry field 22721 value for DEG SCALE 22121 should not be changed TEMP X DEGSCALE 2e TEMP RAW TEMP NOM Copyright 2005 TERIDIAN Semiconductor Corporation HL EPICURI Rogowski Calibration Area 4 This area consists of two vertical columns of entry fields in the lower left side of the window The coefficients are only active when the Rogowski image is selected for the CE VFeedA Watt 00 Calibration coefficient for phase A voltage feed through default 0 VFeedB Watt 8 3 Calibration coefficient for phase B voltage feed through default 0 VFeedC 0 Calibration coefficient for phase C voltage feed through default 0 VFeed A 8 Not impl
48. itches and Test Points 41 3 2 Connector DeSCrIDUOTIS o DG e PauU Ua i usu a di pai ovca lovn ia aa 44 Copyright 2005 TERIDIAN Semiconductor Corporation d J TERIDIAN 3 2 1 JP6 SSI 44 S22 JP18 External Interface RR EE Zrod ni nou kora 44 9 2 21 Debug mena o r Ye pe ab ve a Pi 45 3 3 Board Hardware Specifications uui aiii caasa o il lcd GR DU doi Dp EE cR iii ln a 46 4 APRENDI c 47 List of Figures Figure 1 1 TERIDIAN 71M6515H Demo and Debug Boards Basic 8 Figure 1 2 Block diagram for the TERIDIAN 71M6515H Demonstration Meter with Debug Board 9 Figure 1 3 Control Program 222 vu na oc an a aurae Pavla kn tes ky essa nd s kni 10 Figure 1 4 Host GUI Window w Functional Groups Areas Marked and Numbered 12 Figure 2 1 Phase Angle 28 Figure 2 2 Watt Meter with Gain and Phase 28 Figure 2 3 Calibration Spreadsheet for Three 32 Figure 2 4 Calibration Spreadsheet for Five
49. l Interface Connector JP18 Functional Specification e Program Memory e Time Base Frequency e Time Base Temperature Coefficient Controls and Displays e Reset Watts PULSE3 VARS PULSEA e INTERRUPT Measurement Range e Voltage e Current 40 95 180V 700V RMS 0 5V 25mA typical 0 240V RMS 0 250mV p p Concentric connector 2 5mm Spade Terminals and headers on PCB bottom 8x2 Header 0 1 pitch 64 Socket 12 2 Header 0 1 pitch 128kByte serial FLASH 32 768kHz 20PPM at 25 C 0 04 max Button SW2 red LED D5 red LED D6 green LED 120 700 V rms resistor division ratio 1 3 398 1 7Q termination for 2 000 1 CT input 200A Copyright 2005 TERIDIAN Semiconductor Corporation d J TERIDIAN APPENDIX 71M6515H Demo Board Description 71M6515H Demo Board Specifications 71M6515H Demo Board Electrical Schematic 71M6515H Demo Board Bill of Materials 71M6515H Demo Board PCB Silk screen layer Top side 71M6515H Demo Board PCB Silk screen layer Bottom side 71M6515H Demo Board PCB Metal Layer Top side 71M6515H Demo Board PCB Metal Layer Middle 1 ground plane 71M6515H Demo Board PCB Metal Layer Middle 2 supply plane 71M6515H Demo Board PCB Metal Layer Bottom Debug Board Description Debug Board Electrical Schematic Debug Board Bill of Materials Debug Board PCB Silk screen layer Top side Debug Board PC
50. mbers are entered the pulses may be generated over several accumulation intervals When the corresponding Pulse Source selection in the Pulse Source Selection area is Internal or post processed values the display fields of the External Pulse Control area contain input values N that correspond to the pulse rate f per the equation f WRATE 35 82 10 In other words the ADC count corresponding to the applied voltages at the Vn and In pins VA IA VB IB VC IC will be displayed Pulset 0 Host provided pulse count for the PULSEW output Puse O Host provided pulse count for the PULSER output Pulse3 o Host provided pulse count for the PULSE3 output Pulses O Host provided pulse count for the PULS4W output Pulse Width and Pulse Rate Control Area 8 This area consists of two entry fields to the right of the Temperature Compensation area WRATE 683 This field together with SUM CYCLES and In8 determines the Kh factor of the chip as follows VMAX IMAX Ins Kho OA 5757 Wh Pulse SUM CYCLES WRATE X X is determined by the two fields PULSE SLOW and PULSE FAST in the Configuration area Pulse Width This field determines the pulse width in ms Revision 2 0 17 of 66 Copyright 2005 TERIDIAN Semiconductor Corporation 71 6515 Demo Board User s Manual System Constants Area 9 This area consists of two entry fields to the right of the Temperature Compensation area Entries
51. meter connected to a typical calibration system The calibrator supplies calibrated voltage and current signals to the meter It should be noted that the current flows through the CT or CTs that are not part of the Demo Board The Demo Board rather receives the voltage output signals fro the CT An optical pickup senses the pulses emitted by the meter and reports them to the calibrator Some calibration systems have electrical pickups The calibrator measures the time between the pulses and compares it to the expected time based on the meter Kh and the applied power Optical Pickup for Pulses Calibrator Figure 2 10 Meter with Calibration System TERIDIAN Demo Boards are not calibrated prior to shipping However the Demo Board pulse outputs are tested and compared to the expected pulse output Figure 2 11 shows the screen on the controlling PC for a typical Demo Board The numbers in the red fields under As Found represents the measured errors The rows represent measurements under various conditions such as Row 1 Phase A at 30A Row 2 Phase B at 30A Row 3 Phase C at 30A Row 4 All elements combined at 30A each and 60 phase angle Row 5 All elements combined at 0 3A each and 0 phase angle Row 6 All elements combined at 200A each and 0 phase angle Both numbers are given in percent This means that for the measured Demo Board the sum of all errors resulting from tolerances of PCB components CTs and 71M6515H tolerances w
52. mo Board Bottom Signal 57 Figure 4 10 Debug Board 5 59 Figure 4 11 Debug Board TOP VIEW h NARRE ask akne 60 Figure 4 12 Debug Board Bottom 60 Figure 4 13 Debug Board Top Signal 61 Figure 4 14 Debug Board Middle Layer 1 Ground 61 Figure 4 15 Debug Board Middle Layer 2 Supply 62 Figure 4 16 Debug Board Bottom Trace Layer sun sun 62 Figure 4 17 TERIDIAN 71M6515H LQFP64 Pinout top 65 Copyright 2005 TERIDIAN Semiconductor Corporation d jTERIDIAN List of Tables Table 1 1 Table 1 2 Table 1 3 Table 3 1 Table 3 2 Table 3 3 Table 3 4 Table 3 5 Table 3 6 Table 4 1 Table 4 2 Table 4 3 Table 4 4 Jumper settings on Debug t na nosia 10 Straight Cable ConnecionS kot 10 Null modem cable connections non noo 10 71M6515H Demo Board Description 1 3 ca cassa on 41 71M6515H Demo Board Description 2 3 42 71M6515H Demo Board Description 3 3 43
53. nput output pins 0 through 7 These pins should not be floated if configured as input PULSE4 15 O Thefourthpulsegeneratoroutput PULSES 4 O JThefhidpusegeneratorouput PULSE INT 40 The pulse output initial power up voltage BAUD 16 TheUARTbaudrate 1 38 4kbd 0 192kbd Interrupt output low active A falling edge indicates the end of a measurement frame IRQZ 41 as well as alarms Rises when status word is read MUXSYNC 25 O Falls at beginning of conversion cycle for IA Chip reset Input pin with internal pull up resistor used to reset the RESETZ 47 chip into a known state For normal operation this pin is set to 1 reset the chip this pin is driven to 0 for 5 microseconds Enables the UART when 0 The UART is disabled when this pin is set UARTCSZ 34 to 1 A positive pulse on this pin will reset the UART No external reset circuitry is necessary for power up reset High Speed Synchronous Interface 551 If SRDY is not used it should be tied low 24 SSI optional handshake input 9 SSI frame pulse output one SSCLK wide 5 SSI clock output 5MHz or 10MHz selectable 8 SSI data output changes on the rising edge of SSCLK 44 4 A m TX UART serial Interface transmitter output 2 10 11 12 13 17 18 19 RESERVED 20 26 28 29 These pins must not be connected 30 31 32 43 64 TMUXOUT Digital output test multiplexer Controlled TMUX 2 0 RPULSE 36 Selectable
54. ol Program Icon PMTest exe can work in two baud rates and on any COM port To configure PMTest exe for the desired operation mode the original PMTest exe file is copied to or to a file with a name of the form PMTestxxxCy exe If xxx 192 the program will operate at 19 2kb s if xxx 384 the program will operate at 38 4kb s UART speed when communicating with the 71M6515H The number substituted for y states the COM port number that the program is using for communicating with the host Example When named PMTest192C2 exe the program will operate with 19 2kb s via COM port 2 Copyright 2005 TERIDIAN Semiconductor Corporation 1 8 1 8 1 1 8 2 d J TERIDIAN Note For smooth operation of the PMTest program it is important to observe the following rules e 115 important to exit all programs that access COM port 1 before PMTEST exe is started e Make sure all applicable updates to the Windows operating system are installed before running the application e PMTest exe will not run on Windows 98 or older operating systems Real time performance can be affected by processor intense operations of the PC such as starting new applications loading files into applications or ending applications Such operations have to be avoided to ensure uninterrupted communication between PC and the 6515H Demo Board Do not press the ALT key on the keyboard USING THE DEMO BOARD The 71M6515H Demo Board is a ready to
55. oltage N Measured voltage inductive AM JOSE men Energy reading at 0 CAL_IB 16384 ON MM EM ET POPSET Energy reading at 60 1 14895 Energy reading at 0 PHADJ B 0 X der d Expected voltage N capacitive Measured voltage Se D Energy reading at 0 CAL IC 16357 2 Voltage gy feeding _ Energy reading at 60 CAL VC 17031 Generating Energy Using Energy Energy reading at 0 PHADJ C 12434 Readings Enter 0 if the error is 090 Expected voltage 240 Measured voltage 230 88 enter 3 if meter runs 390 slow Figure 2 3 Calibration Spreadsheet for Three Measurements Copyright 2005 TERIDIAN Semiconductor Corporation d J TERIDIAN T E RI D A N 71M6511 71M6513 71M6515 Calibration Worksheet i Five Measurements Results will show in green fields SEMICONDUCTOR CORP Enter values in yellow fields 4 0 Date 9 28 2005 AC freguency 60 Author WJH click on yellow field to select from pull down list PHASE A fraction Po ccu IC Energy reading at 0 gt CAL IA 16219 520 A Energy reading at 60 25 CAL_VA 16222 E Energy reading at 60 LES PHADJ A 445 2 Energy reading 180 2 poda E Voltage error at 0 ia inductive Expected voltage 240 Measured voltage direction 60 ha A Current PHASE ps Energy reading a
56. opyright 2005 TERIDIAN Semiconductor Corporation d J TERIDIAN Figure 4 6 TERIDIAN 71M6515H Demo Board Top Signal Layer Copyright 2005 TERIDIAN Semiconductor Corporation d JTERIDIAN Figure 4 7 TERIDIAN 71M6515H Demo Board Middle Layer 1 Ground Plane Copyright 2005 TERIDIAN Semiconductor Corporation d JTERIDIAN Figure 4 8 TERIDIAN 71M6515H Demo Board Middle Layer 2 Supply Plane Copyright 2005 TERIDIAN Semiconductor Corporation d J TERIDIAN NE Figure 4 9 TERIDIAN 71M6515H Demo Board Bottom Signal Layer O Copyright 2005 TER DIAN Semiconductor Corporation SEMICONDUCTOR CORP 1 21 1 610 12 023 RCOB0b 4458491ND C2012X7RIH104K 47816731ND TAJBIOGKOT6R A LITEON oo G1 G2 G3 G4 MTHOLE 2202K ND 2202K ND Keystone Electronics 4 40 1 4 screw H342 ND PMS 4400 0025 PH Building Fasteners 7 4 40 5 16 screw H343 ND PMS 4400 0031 PH Building Fasteners 4 40 nut H216 ND HNZ440 Building Fasteners 9 right angle DSUB9 SKT A2100 ND 745781 4 2 ED 42 DC Connector RAPC712 SC1152 ND RAPC712 Switchcraft 33 HEADER F 8X2 8X2PIN 929852 01 36 ND 929852 01 36 10 JP1 JP2 JP3 JP4 HEADER 2 2X1PIN 51011 36 PZC36SAAN Sullins R1 R5 R7 R8 RCO805 P10KACT ND ERJ 6GEYJ103V Panasonic R2 R3 RCO805 P1 0KACT ND ERJ 6GEYJ102V Panasonic RC0805 86 RCOBOS ERJ
57. opyright 2005 TERIDIAN Semiconductor Corporation d J TERIDIAN CALIBRATION WITH THREE MEASUREMENTS The simplest calibration method is to make three measurements Typically a voltage measurement and two Watt hour Wh measurements are made We assume the voltage measurement has the error Ey and the two Wh measurements have errors Eo and where Eo is measured with O and is measured with 60 These values should be simple ratios not percentage values They should be zero when the meter is accurate and negative when the meter runs slow The fundamental frequency is fo T is equal to 1 fs where fs is the sample frequency 2560 62Hz Set all calibration factors to nominal CAL A 16384 CAL VA 16384 PHADJ A 0 From the voltage measurement we determine that 1 gt We use the other two measurements to determine and Axi IV Ay cos 0 0 2 cos 1 IV cos 0 Ps E 1 2 Ay Ay 0 2 IV Ay Ay cos 60 ds A cos 60 j IV cos 60 eos 60 _ Ay Ay cos 60 cos sin 60 sin _ 1 cos 60 Ay Ay 05 0 A vy Ay tan 60 sin 9 1 Combining Za and 3a 4 E 1 tan 60 tan 0 udis 5 n Dtan 60 Ea cu 63 4 0 E 1 tan 60 and from 2a El 8 0 Now that we know the and s errors we calculate the new c
58. ould usually be left in place The internal supply is not strong enough to power the Debug Board Thus the external power supply should always be used for the Debug Board regardless whether the meter is powered by its internal supply or through an external supply Copyright 2005 TERIDIAN Semiconductor Corporation d J TERIDIAN 1 6 2 SERIAL CONNECTION SETUP For connection of the DB9 serial port to a PC either a straight or a so called null modem cable may be used JP1 and JP2 are plugged in for the straight cable and JP3 JP4 are empty The jumper configuration is reversed for the null modem cable as shown in Table 1 1 Configuration JP1 JP2 JP3 JP4 Straight Cable installed installed Null Modem Cable s installed installed Table 1 1 Jumper settings on Debug Board JP1 through JP4 can also be used to alter the connection when the PC is not configured as a DCE device Table 1 2 shows the connections necessary for the straight DB9 cable and the pin definitions 2 Table 1 2 Straight cable connections Table 1 3 shows the connections necessary for the null modem 9 cable and the pin definitions 3 Table 1 3 Null modem cable connections 1 7 PREPARING THE The Control Program PMtest exe must be copied from the CD ROM to a directory on the host PC The program can then be started directly by double clicking on the PMTest exe icon see Figure 1 3 PMTest exe Figure 1 3 Contr
59. ource area selects the X factor for the pulse generation rate PULSE FAST Square This button in conjunction with PULSE SLOW selects the X button factor for the pulse generation rate see WRATE field 1892 6 o o sto 0 1 19277 00375 1 0 IA 8x Square Additional ADC gain of 8x can be selected for phase A by button selecting 1 IB 8x Square Additional ADC gain of 8x can be selected for phase B by button selecting 1 IC 8x Square Additional ADC gain of 8x can be selected for phase C by button selecting 1 DEFAULT Square This button enables temperature compensation by the host If PPM button the bit associated with DEFAULT PPM is 0 the 71 6515 internally controls the temperature compensation based on the stored VREF characterization values When DEFAULT PPM is 0 the host may write values into the and PPMC2 fields to influence temperature compensation When DEFAULT PPM is toggled back to 0 after the host had written values to the PPMC and PPMC2 fields these fields will go back to displaying the original internal values Status Word and Status Mask Area 17 This area consists of 18 square buttons and indicator lights towards the right edge of the GUI window The bits of the STATUS word are displayed in the indicator lights right next to the square buttons A green light indicates no activity a red light indicates that the corresponding bit is set Individual bits of the STATUS wor
60. ower x time for each phase time for each phase VAh These fields display the accumulated These fields display the energy real VARh These fields display the accumulated These fields display the reactive energy These fields display the accumulated These fields display the accumulated apparent energy apparent power x apparent energy apparent power x time for each phase time collected during the last accumulation interval for each phase Vrms These fields display the momentary voltages RMS for each phase These fields display the momentary currents RMS for each phase These fields display the momentary phase angles of the currents for each phase VPhase angle These fields display the momentary phase angles between the phases A and B underneath AB and B and C underneath Gain Adjust This field displays the current value of the gain adjusted by the temperature compensation mechanism It is functionally associated with the fields in area 10 When no compensation is active or the temperature deviation is minimal the default value of 16384 will be displayed Copyright 2005 TERIDIAN Semiconductor Corporation d SEMICONDUCTOR CORP Calibration Constants Area 2 This area is on the left side of the GUI window and contains three entry fields for each phase The function depends on the selected CE image CT Shunt or Rogowski sensor GUI Element Function CT Shunt Function
61. pulse output default VARh pulse WPULSE 30 Selectable pulse output default Wh pulse Table 4 4 71M6515H Pin Description Table 2 2 Copyright 2005 TERIDIAN Semiconductor Corporation d J TERIDIAN 64 RESERVEE 63 XOUT 62 GNDD 61 XIN 60 GNDA 59 VFLT 58 VX 57 VREF 56 IA 51 VC 50 49 GNDA 55 54 IC 53 52 VB GNDD GNDD RESERVED 2 47 RESETZ 46 2 5 TX 4 45 VBAT SSCLK 5 44 RX e T RI D IAN 43 RESERVED V3P3D 7 42 DO SSDATA 8 IRQZ SFR o 71M651 5H IGT 40 PULSE INIT RESERVED 10 39 D6 RESERVED 1 38 D5 RESERVED 12 37 D4 RESERVED 13 36 RPULSE PULSE3 14 35 WPULSE PULSE4 15 34 UARTCSZ BAUD RATE a3 D7 2 D1 121 D2 22 D3 23 SRDY 24 RESERVED 17 RESERVED 18 RESERVED 19 RESERVED 20 MUX SYNCL 125 RESERVED 26 GNDD 27 RESERVED 28 RESERVED 29 RESERVED 30 RESERVED 31 RESERVED Figure 4 17 TERIDIAN 71M6515H LQFP64 Pinout top view Note Pins labeled as RESERVED must not be connected Copyright 2005 TERIDIAN Semiconductor Corporation jTERIDIAN User s Manual This User s Manual contains proprietary product definition information of TERIDIAN Semiconductor Corporation TSC and is made available for informational purposes only TERIDIAN assume
62. s no obligation regarding future manufacture unless agreed to in writing If and when manufactured and sold this product is sold subject to the terms and conditions of sale supplied at the time of order acknowledgment including those pertaining to warranty patent infringement and limitation of liability TERIDIAN Semiconductor Corporation TSC reserves the right to make changes in specifications at any time without notice Accordingly the reader is cautioned to verify that a data sheet is current before placing orders TSC assumes no liability for applications assistance TERIDIAN Semiconductor Corp 6440 Oak Canyon Rd Irvine CA 92618 5201 TEL 714 508 8800 FAX 714 508 8877 http www teridian com Copyright 2005 TERIDIAN Semiconductor Corporation
63. t 0 2 CAL IB 16223 Energy reading at 60 2 CAL VB 16222 N Energy reading at 60 2 PHADJ B 0 capacitive Energy reading at 180 2 E J Voltage error at 0 N gs M Expected voltage 240 Measured voltage Voltage NE E PHASE C Generating Energy Using Energy Energy reading at 0 CAL IC 16384 Energy reading at 60 0 CAL VC 16384 Energy reading at 60 0 PHADJ 0 Readings Enter 0 if the error is 0 Energy reading at 180 enter 5 if meter runs 5 fast Voltage error at 0 enter 3 if meter runs 3 slow Expected voltage 240 240 Measured voltage Figure 2 4 Calibration Spreadsheet for Five Measurements 2 1 8 COMPENSATING FOR NON LINEARITIES Nonlinearity is most noticeable at low currents as shown in Figure 2 5 and can result from input noise and truncation Nonlinearities can be eliminated using the QUANT_W variable error Figure 2 5 Non Linearity Caused by Quantification Noise The error can be seen as the presence of a virtual constant noise current While 10mA hardly contribute any error at currents of 10A and above the noise becomes dominant at small currents Copyright 2005 TERIDIAN Semiconductor Corporation d J TERIDIAN The value to be used for QUANT can be determined by the following formula error 100 VMAX LSB Where error observed error at a given voltage V and current 1 VMAX volt
64. the signal A 1 is on and a 0 is off 111 CKOUT_DSB ADC DIS Entry fields White rectangular fields that can be edited by the user The delete key plus the number and cursor keys work in this type of field Calibration Constants Calibrate IA 16384 Calibrate VA 16384 Calibrate IB 16384 Calibrate 16384 Calibrate IC 16384 Copyright 2005 TERIDIAN Semiconductor Corporation e Display fields Gray rectangular fields that indicate settings measurements etc of the 6515H chip These fields cannot be edited by the user Wh 0 000 0 000 fields Entry fields that allow selection from the pre determined list of choices once down pointing arrow is pressed pull down menus e Indicator lights Red and green activity indicators underneath the Status Mask label E Som Green lights mean no activity Red lights mean that the corresponding bit in 1 BooTUP the STATUS mask is set i e the condition is true p 51 With an input signal phase voltage present the FO light will be on sanc indicating that the square wave following the input signal is being e o Fo generated The light at 1SEC will blink red every second Other lights will E stay green until the corresponding condition is true e g when input O o 15 signal meets a sag or over voltage threshold O 0 DEDGE a
65. tion pins 3 5 7 9 and 17 are non functional O Copyright 2005 TERIDIAN Semiconductor Corporation 71 6515 Demo Board Users Manual 3 2 3 21 DEBUG INTERFACE JP21 provides the connection to the Debug Board It carries the UART TX and RX signals needed for the communication with the host A few other signals are useful for diagnosis and test are provided also The pin layout for JP21 is shown in Table 3 6 Revision 2 0 24 Pin In line 1221 oigna 4 Jr LIT gt Y INCSISLOT CI low CKTEST TX UART RX UART Table 3 6 JP21 Pin Description 2 ER GN 8 Go _ 0 2 9 1 10 12 14 16 Copyright 2005 TERIDIAN Semiconductor Corporation 45 of 66 d J TERIDIAN 3 3 BOARD HARDWARE SPECIFICATIONS PCB Dimensions e Width e Length e Thickness e Height w components and 3 8 spacers Environmental e Operating Temperature 5 125 130 2mm 4 7 119 4mm 0 062 1 6mm 1 5 38 1mm 40 85 function of crystal oscillator affected outside 10 to 60 e Storage Temperature Power Supply e When using AC Input Signal DC Input Voltage powered from DC supply e Supply Current Input Signal Range e AC Voltage Signals VA VB VC AC Current Signals IB IC from Transducer Interface Connectors DC Supply Jack 51 to Wall Transformer e Input Signals e Debug Board JP21 e Target Chip U5 e Externa
66. to those applied for the current transformer should be used In the following example we assume that the line voltage is not applied to the resistor divider for VA formed by R15 R21 R26 R31 and R32 but to a voltage transformer with a ratio N of 20 1 followed by a simple resistor divider We also assume that we want to maintain the value for VMAX at 600V to provide headroom for large voltage excursions When applying VMAX at the primary side of the transformer the secondary voltage Vi is Vs VMAX Vs is scaled by the resistor divider ratio When the input voltage to the voltage channel of the 71M6515H is the desired 177mV Vs is then given by Vs 177mV Resolving for Rr we get Rr VMAX N 177mV 600V 30 177mV 170 45 This divider ratio can be implemented for example with a combination of one 16 95kQ and one 1009 resistor Copyright 2005 TERIDIAN Semiconductor Corporation 1 9 CALIBRATING THE DEMO METER The general calibration procedure is as follows 1 Obtain the deviation from ideal accuracy using a meter calibration system see section 2 1 2 Calculate the calibration values using the error terms obtained in step 1 see section 2 1 3 Enter the calibration values generated in step 2 using the GUI 4 meter with the new calibration constants Copyright 2005 TERIDIAN Semiconductor Corporation d J TERIDIAN APPLICATION INFORMATION CALIBRATION PROCEDURE
67. ulate the new resistor Rx We calculate Rx to 2 1150 2 Changing the resistors R24 R25 R106 R107 to a combined resistance of 2 1159 for each pair will cause the desired voltage drop of 177mV appearing at the IA or IB inputs of the 71M6515H IC 3 WRATE should be adjusted to achieve the desired Kh factor as described in section 1 8 6 Simply scaling MAX is not recommended since peak voltages at the 71M6515H inputs should always be in the range of O through x250mV equivalent to 177mV rms If a CT with a much lower winding ratio than 1 2 000 is used higher secondary currents will result causing excessive voltages at the 71M6515H inputs Conversely CTs with much higher ratio will tend to decrease the useable signal voltage range at the 71 6515 inputs and may thus decrease resolution The 71M6515H Demo Board comes equipped with its own network of resistor dividers for voltage measurement mounted on the PCB The resistor values for the 4 layer Demo Board are 2 5477MQ R15 R21 R26 R31 combined and 7500 R32 resulting in a ratio of 1 3 393 933 This means that equals 176 78 3 393 933 600 A large value for VMAX has been selected in order to have headroom for over voltages This choice need not be of concern since the ADC in the 71M6515H has enough resolution even when operating at 120Vrms or 240Vrms If a different set of voltage dividers or an external voltage transformer is to be used scaling techniques similar
68. use meter with a preprogrammed scaling factor Kh of 3 2 Wh pulse In order to be used with a calibrated load or a meter calibration system the board should be connected to the AC power source using the spade terminals on the bottom of the board The current transformers should be connected to the dual pin headers on the bottom of the board For the Kh to be adjusted properly current transformers with 2 000 1 winding ratio must be used STARTING UP THE DEMO BOARD AND THE GUI PROGRAM In order to control and monitor the Demo Board the connections specified in section 1 6 have to be established The sequence of actions when powering up the Demo Board is as follows 1 Power up the Demo Board 2 Start the GUI Control Program PMTest exe 3 Check for communication between the GUI Control Program and the 71M6515H Communication is established when the green LED indicator labeled 1SEC on the GUI screen flashes red every second 4 Initialize the 71M6515H to match the desired application and measurement parameters Establish the CE image calibration factors pulse parameters nominal temperature IMAX VMAX using the commands and fields described in 1 8 2 5 Establish the desired configuration using the bits of the CONFIG register field 16 in the GUI window but do not enable the CE 6 Enable the CE by clicking the square button next to CE ENABLE Once voltage is applied and load current is flowing the red LED 05 will flash each t
69. ved from the sample GUI window in Figure 2 9 1 The 1 second interrupt is enabled 2 Pulse source 4 are selected to be external but host data is missing causing the PULSES and PULSE4 interrupts to occur 3 Araw temperature value of 856 000 has been stored in the nominal temperature field The chip is now 3 6 above the nominal temperature 4 Wh have been selected for pulse source 1 and 10 Wh pulses have been generated 5 The temperature compensation factors PPM C and have been calculated by the chip and together with the temperature deviation from nominal the gain is adjusted to 16382 6 10 2Wh 0 1VARh and 10 08VAh have been collected in each channel the RMS voltages are close to 220V the RMS currents are at 0 435A and the phase angles are at O degrees 7T Phase A is selected for frequency detection The measured frequency is at 60Hz and 120 zero crossings were detected in the previous accumulation interval Copyright 2005 TERIDIAN Semiconductor Corporation 2 3 2 d jTERIDIAN SEMICONDUCTOR CORP FUNCTIONAL METER TEST This is the test that every Demo Board has to pass before being integrated into a Demo Kit Before going into the functional meter test the Demo Board has already passed a series of bench top tests but the functional meter test is the first test that applies realistic high voltages and current signals from current transformers to the Demo Board Figure 2 10 shows a

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